From e04bfdacb368da1f52135926e5c18dfa126e7cb1 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 25 Mar 2014 11:39:33 -0600 Subject: ARM: tegra: add Jetson TK1 board Jetson TK1 is an NVIDIA Tegra124 reference board, which shares much of its design with Venice2. Signed-off-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/jetson-tk1.h | 79 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) create mode 100644 include/configs/jetson-tk1.h (limited to 'include') diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h new file mode 100644 index 00000000000..6255750c3b2 --- /dev/null +++ b/include/configs/jetson-tk1.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2013-2014 + * NVIDIA Corporation + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#include "tegra124-common.h" + +/* Enable fdt support for Jetson TK1. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra124-jetson-tk1 +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + +/* High-level configuration options */ +#define V_PROMPT "Tegra124 (Jetson TK1) # " +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" + +/* Board-specific serial config */ +#define CONFIG_SERIAL_MULTI +#define CONFIG_TEGRA_ENABLE_UARTD +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE + +#define CONFIG_BOARD_EARLY_INIT_F + +/* I2C */ +#define CONFIG_SYS_I2C_TEGRA +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS TEGRA_I2C_NUM_CONTROLLERS +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C + +/* SD/MMC */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_TEGRA_MMC +#define CONFIG_CMD_MMC + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 + +/* SPI */ +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ +#define CONFIG_TEGRA114_SPI_CTRLS 6 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#define CONFIG_SF_DEFAULT_SPEED 24000000 +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_SIZE (4 << 20) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + +/* USB networking support */ +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* General networking support */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP + +#include "tegra-common-post.h" + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 6dd3b566893a99629771e076dca1ce8db7b77dc1 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 28 Mar 2014 12:03:36 -0400 Subject: mtd: Add a CONFIG_SPL_MTD_SUPPORT for a more full NAND subsystem in SPL This mainly converts the am335x_spl_bch driver to the "normal" format which means a slight change to nand_info within the driver. Acked-by: Scott Wood Signed-off-by: Tom Rini --- README | 4 +++ drivers/mtd/nand/am335x_spl_bch.c | 54 +++++++++++++++++++-------------------- include/configs/ti_armv7_common.h | 1 + spl/Makefile | 1 + 4 files changed, 33 insertions(+), 27 deletions(-) (limited to 'include') diff --git a/README b/README index 39e05d333c6..7b5d01ba6b3 100644 --- a/README +++ b/README @@ -3326,6 +3326,10 @@ FIT uImage format: Support for NAND boot using simple NAND drivers that expose the cmd_ctrl() interface. + CONFIG_SPL_MTD_SUPPORT + Support for the MTD subsystem within SPL. Useful for + environment on NAND support within SPL. + CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT Set for the SPL on PPC mpc8xxx targets, support for drivers/ddr/fsl/libddr.o in SPL binary. diff --git a/drivers/mtd/nand/am335x_spl_bch.c b/drivers/mtd/nand/am335x_spl_bch.c index c84851bab58..bd89b067d5b 100644 --- a/drivers/mtd/nand/am335x_spl_bch.c +++ b/drivers/mtd/nand/am335x_spl_bch.c @@ -16,7 +16,7 @@ #include static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS; -static nand_info_t mtd; +nand_info_t nand_info[1]; static struct nand_chip nand_chip; #define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ @@ -30,12 +30,12 @@ static struct nand_chip nand_chip; static int nand_command(int block, int page, uint32_t offs, u8 cmd) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = nand_info[0].priv; int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; - while (!this->dev_ready(&mtd)) + while (!this->dev_ready(&nand_info[0])) ; /* Emulate NAND_CMD_READOOB */ @@ -45,11 +45,11 @@ static int nand_command(int block, int page, uint32_t offs, } /* Begin command latch cycle */ - hwctrl(&mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); + hwctrl(&nand_info[0], cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE); if (cmd == NAND_CMD_RESET) { - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); - while (!this->dev_ready(&mtd)) + hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + while (!this->dev_ready(&nand_info[0])) ; return 0; } @@ -60,35 +60,35 @@ static int nand_command(int block, int page, uint32_t offs, /* Set ALE and clear CLE to start address cycle */ /* Column address */ - hwctrl(&mtd, offs & 0xff, + hwctrl(&nand_info[0], offs & 0xff, NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */ - hwctrl(&mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ + hwctrl(&nand_info[0], (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */ /* Row address */ - hwctrl(&mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ - hwctrl(&mtd, ((page_addr >> 8) & 0xff), + hwctrl(&nand_info[0], (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */ + hwctrl(&nand_info[0], ((page_addr >> 8) & 0xff), NAND_CTRL_ALE); /* A[27:20] */ #ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE /* One more address cycle for devices > 128MiB */ - hwctrl(&mtd, (page_addr >> 16) & 0x0f, + hwctrl(&nand_info[0], (page_addr >> 16) & 0x0f, NAND_CTRL_ALE); /* A[31:28] */ #endif - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); if (cmd == NAND_CMD_READ0) { /* Latch in address */ - hwctrl(&mtd, NAND_CMD_READSTART, + hwctrl(&nand_info[0], NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); /* * Wait a while for the data to be ready */ - while (!this->dev_ready(&mtd)) + while (!this->dev_ready(&nand_info[0])) ; } else if (cmd == NAND_CMD_RNDOUT) { - hwctrl(&mtd, NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE | + hwctrl(&nand_info[0], NAND_CMD_RNDOUTSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE); - hwctrl(&mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); + hwctrl(&nand_info[0], NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE); } return 0; @@ -96,7 +96,7 @@ static int nand_command(int block, int page, uint32_t offs, static int nand_is_bad_block(int block) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = nand_info[0].priv; nand_command(block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB); @@ -117,7 +117,7 @@ static int nand_is_bad_block(int block) static int nand_read_page(int block, int page, void *dst) { - struct nand_chip *this = mtd.priv; + struct nand_chip *this = nand_info[0].priv; u_char ecc_calc[ECCTOTAL]; u_char ecc_code[ECCTOTAL]; u_char oob_data[CONFIG_SYS_NAND_OOBSIZE]; @@ -133,15 +133,15 @@ static int nand_read_page(int block, int page, void *dst) nand_command(block, page, 0, NAND_CMD_READ0); for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - this->ecc.hwctl(&mtd, NAND_ECC_READ); + this->ecc.hwctl(&nand_info[0], NAND_ECC_READ); nand_command(block, page, data_pos, NAND_CMD_RNDOUT); - this->read_buf(&mtd, p, eccsize); + this->read_buf(&nand_info[0], p, eccsize); nand_command(block, page, oob_pos, NAND_CMD_RNDOUT); - this->read_buf(&mtd, oob, eccbytes); - this->ecc.calculate(&mtd, p, &ecc_calc[i]); + this->read_buf(&nand_info[0], oob, eccbytes); + this->ecc.calculate(&nand_info[0], p, &ecc_calc[i]); data_pos += eccsize; oob_pos += eccbytes; @@ -160,7 +160,7 @@ static int nand_read_page(int block, int page, void *dst) * from correct_data(). We just hope that all possible errors * are corrected by this routine. */ - this->ecc.correct(&mtd, p, &ecc_code[i], &ecc_calc[i]); + this->ecc.correct(&nand_info[0], p, &ecc_code[i], &ecc_calc[i]); } return 0; @@ -206,13 +206,13 @@ void nand_init(void) /* * Init board specific nand support */ - mtd.priv = &nand_chip; + nand_info[0].priv = &nand_chip; nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE; board_nand_init(&nand_chip); if (nand_chip.select_chip) - nand_chip.select_chip(&mtd, 0); + nand_chip.select_chip(&nand_info[0], 0); /* NAND chip may require reset after power-on */ nand_command(0, 0, 0, NAND_CMD_RESET); @@ -222,5 +222,5 @@ void nand_init(void) void nand_deselect(void) { if (nand_chip.select_chip) - nand_chip.select_chip(&mtd, -1); + nand_chip.select_chip(&nand_info[0], -1); } diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 69d69a54212..1127b5b6fb1 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -245,6 +245,7 @@ #define CONFIG_SPL_NAND_BASE #define CONFIG_SPL_NAND_DRIVERS #define CONFIG_SPL_NAND_ECC +#define CONFIG_SPL_MTD_SUPPORT #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #endif diff --git a/spl/Makefile b/spl/Makefile index 6fec2522a8c..a4d973744b3 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -104,6 +104,7 @@ libs-$(CONFIG_SPL_SPI_SUPPORT) += drivers/spi/ libs-y += fs/ libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/ libs-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ drivers/power/pmic/ +libs-$(CONFIG_SPL_MTD_SUPPORT) += drivers/mtd/ libs-$(if $(CONFIG_CMD_NAND),$(CONFIG_SPL_NAND_SUPPORT)) += drivers/mtd/nand/ libs-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/ libs-$(CONFIG_SPL_ONENAND_SUPPORT) += drivers/mtd/onenand/ -- cgit v1.3.1 From fb3ad9bd923daafed9818c579d841f05c8ecbeb0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 28 Mar 2014 15:03:29 -0400 Subject: TI: Add, use a DEFAULT_LINUX_BOOT_ENV environment string To deal with a reoccurring problem properly we need to specify addresses for the Linux kernel, Flatted Device Tree and ramdisk that obey the constraints within the kernel's Documentation/arm/Booting file but also make sure that we relocate things within a valid address range. It is possible with these addresses to also set fdt_high and initrd_high to the value of 0xffffffff. We don't do this by default to allow for the most likely success of people using custom addresses however. Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 5 +---- include/configs/am43xx_evm.h | 5 +---- include/configs/ti_armv7_common.h | 22 +++++++++++++++++++++- include/configs/ti_omap4_common.h | 4 +--- include/configs/ti_omap5_common.h | 5 +---- 5 files changed, 25 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ea9e758a696..41485179e4f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -61,11 +61,8 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "fdtaddr=0x80F80000\0" \ - "fdt_high=0xffffffff\0" \ + DEFAULT_LINUX_BOOT_ENV \ "boot_fdt=try\0" \ - "rdaddr=0x81000000\0" \ "bootpart=0:2\0" \ "bootdir=/boot\0" \ "bootfile=zImage\0" \ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 614857dd25c..27777c51baa 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -112,10 +112,7 @@ #ifndef CONFIG_SPL_BUILD #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "fdtaddr=0x80F80000\0" \ - "fdt_high=0xffffffff\0" \ - "rdaddr=0x81000000\0" \ + DEFAULT_LINUX_BOOT_ENV \ "fdtfile=undefined\0" \ "bootpart=0:2\0" \ "bootdir=/boot\0" \ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 1127b5b6fb1..ec8eec60a96 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -36,8 +36,28 @@ /* * Our DDR memory always starts at 0x80000000 and U-Boot shall have * relocated itself to higher in memory by the time this value is used. + * However, set this to a 32MB offset to allow for easier Linux kernel + * booting as the default is often used as the kernel load address. */ -#define CONFIG_SYS_LOAD_ADDR 0x80000000 +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +/* + * We setup defaults based on constraints from the Linux kernel, which should + * also be safe elsewhere. We have the default load at 32MB into DDR (for + * the kernel), FDT above 128MB (the maximum location for the end of the + * kernel), and the ramdisk 512KB above that (allowing for hopefully never + * seen large trees). We say all of this must be within the first 256MB + * as that will normally be within the kernel lowmem and thus visible via + * bootm_size and we only run on platforms with 256MB or more of memory. + */ +#define DEFAULT_LINUX_BOOT_ENV \ + "loadaddr=0x82000000\0" \ + "kernel_addr_r=0x82000000\0" \ + "fdtaddr=0x88000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "rdaddr=0x88080000\0" \ + "ramdisk_addr_r=0x88080000\0" \ + "bootm_size=0x10000000\0" /* * Default to a quick boot delay. diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index bcb5eabd756..387f570da02 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -87,10 +87,8 @@ * Environment setup */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ + DEFAULT_LINUX_BOOT_ENV \ "console=ttyO2,115200n8\0" \ - "fdt_high=0xffffffff\0" \ - "fdtaddr=0x80f80000\0" \ "fdtfile=undefined\0" \ "bootpart=0:2\0" \ "bootdir=/boot\0" \ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 7b10fbd28ac..2443d559346 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -70,10 +70,7 @@ #endif #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "fdtaddr=0x80F80000\0" \ - "fdt_high=0xffffffff\0" \ - "rdaddr=0x81000000\0" \ + DEFAULT_LINUX_BOOT_ENV \ "console=" CONSOLEDEV ",115200n8\0" \ "fdtfile=undefined\0" \ "bootpart=0:2\0" \ -- cgit v1.3.1 From 18e44ce3f8edbb87519ffdf34d96c1ccc33626c9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 28 Mar 2014 15:03:30 -0400 Subject: am335x_evm: Update the ramdisk args, we pass things in just fine via DT Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 41485179e4f..ebe2ab35de3 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -79,7 +79,7 @@ "nfsopts=nolock\0" \ "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ "::off\0" \ - "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ + "ramroot=/dev/ram0 rw\0" \ "ramrootfstype=ext2\0" \ "mmcargs=setenv bootargs console=${console} " \ "${optargs} " \ -- cgit v1.3.1 From bea0fd5e6aa73367eb14840cd4f5cecd422e3374 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 28 Mar 2014 15:03:31 -0400 Subject: am43xx_evm: Update the ramdisk args, we pass things in just fine via DT Signed-off-by: Tom Rini --- include/configs/am43xx_evm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 27777c51baa..2d9825beeb3 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -128,7 +128,7 @@ "usbroot=/dev/sda2 rw\0" \ "usbrootfstype=ext4 rootwait\0" \ "usbdev=0\0" \ - "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ + "ramroot=/dev/ram0 rw\0" \ "ramrootfstype=ext2\0" \ "mmcargs=setenv bootargs console=${console} " \ "${optargs} " \ -- cgit v1.3.1 From 2737f0112b83172df433a034ce68c43a170db25c Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 3 Apr 2014 07:52:52 -0400 Subject: TI:omap5: Move CONFIG_ENV_SIZE to board config files The size of the environment depends on the backing store, move this to the board config files. Signed-off-by: Tom Rini --- include/configs/dra7xx_evm.h | 1 + include/configs/omap5_uevm.h | 1 + include/configs/ti_omap5_common.h | 2 -- 3 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 291c538a346..99be52b2872 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -17,6 +17,7 @@ /* MMC ENV related defines */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ +#define CONFIG_ENV_SIZE (128 << 10) #define CONFIG_ENV_OFFSET 0xE0000 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_SYS_REDUNDAND_ENVIRONMENT diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index 783b7c3e329..7e2ecd53f52 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -26,6 +26,7 @@ /* MMC ENV related defines */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ +#define CONFIG_ENV_SIZE (128 << 10) #define CONFIG_ENV_OFFSET 0xE0000 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_SYS_REDUNDAND_ENVIRONMENT diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 2443d559346..642ca0a7354 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -46,8 +46,6 @@ #include #include -#define CONFIG_ENV_SIZE (128 << 10) - #include /* -- cgit v1.3.1 From d3289aac64c5785d782b8a6e1ab2112e1e463b33 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 3 Apr 2014 07:52:53 -0400 Subject: TI:armv7: Change Falcon Mode DT load address In general, we want to load the DT at base+128MB, so that we ahve sufficient room for the kernel and a larger device tree. In the case of OMAP3, use 64MB instead as we have a number of boards with 128MB DDR. Signed-off-by: Tom Rini --- include/configs/am43xx_evm.h | 2 ++ include/configs/ti_am335x_common.h | 2 ++ include/configs/ti_armv7_common.h | 2 -- include/configs/ti_omap3_common.h | 3 +++ include/configs/ti_omap4_common.h | 2 ++ include/configs/ti_omap5_common.h | 2 ++ 6 files changed, 11 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 2d9825beeb3..4e56ffce7aa 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -35,6 +35,8 @@ /* SPL defines. */ #define CONFIG_SPL_TEXT_BASE 0x40300350 #define CONFIG_SPL_MAX_SIZE (220 << 10) /* 220KB */ +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) #define CONFIG_SPL_YMODEM_SUPPORT /* Enabling L2 Cache */ diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 50c32037ffb..128b66edef5 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -61,6 +61,8 @@ */ #define CONFIG_SPL_TEXT_BASE 0x402F0400 #define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) /* Enable the watchdog inside of SPL */ #define CONFIG_SPL_WATCHDOG_SUPPORT diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index ec8eec60a96..1efc9886610 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -224,8 +224,6 @@ #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" #ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 - /* FAT */ #define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage" #define CONFIG_SPL_FAT_LOAD_ARGS_NAME "args" diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 854cb78882d..1c6ee4c653f 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -61,6 +61,9 @@ #define CONFIG_SPL_MAX_SIZE (54 * 1024) #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (64 << 20)) + #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_SUPPORT diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 387f570da02..77fbfb64100 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -156,6 +156,8 @@ #define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_DISPLAY_PRINT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index 642ca0a7354..a582fa40412 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -140,6 +140,8 @@ #define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_DISPLAY_PRINT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ + (128 << 20)) #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_AM33XX_BCH /* ELM support */ -- cgit v1.3.1 From 585d8bc11656e6e43eb4efeecc22505377fe099e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 17 Apr 2014 17:23:25 -0400 Subject: am335x_evm: Drop SPI SPL support from the default build This is only useful with the _spiboot build target anyhow, so only include it then. Drop CONFIG_SPL_OS_BOOT support then as the flash is small and didn't include a spot for the device tree already. Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index ebe2ab35de3..036c609582a 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -213,14 +213,6 @@ #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" -/* SPI flash. */ -#define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SPL_SPI_FLASH_SUPPORT -#define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 - #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" #ifdef CONFIG_NAND @@ -362,6 +354,15 @@ * 0x442000 - 0x800000 : Userland */ #if defined(CONFIG_SPI_BOOT) +/* SPL related */ +#undef CONFIG_SPL_OS_BOOT /* Not supported by existing map */ +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED @@ -437,7 +438,6 @@ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Reduce SPL size by removing unlikey targets */ -#undef CONFIG_SPL_SPI_SUPPORT #ifdef CONFIG_NOR_BOOT #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -- cgit v1.3.1 From 79b079f35c31bab26e45a526bd128891ab6c5c1d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 3 Apr 2014 07:52:56 -0400 Subject: dra7xx_evm: Add QSPI_4 support, qspiboot build target We previously only supported QSPI_1 (single) support. Add QSPI_4 (quad) read support as well. This means we can be given one of two boot device values, but don't care which it is, so perform a fixup on the QSPI_4 value. We add a qspiboot build target to better show how you would use QSPI as a boot device in deployment. When we boot from QSPI, we can check the environment for 'boot_os' to control Falcon Mode. Signed-off-by: Sourav Poddar Signed-off-by: Tom Rini --- arch/arm/cpu/armv7/omap-common/boot-common.c | 11 +++++++++ board/ti/dra7xx/evm.c | 19 ++++++++++++++ boards.cfg | 1 + include/configs/dra7xx_evm.h | 37 +++++++++++++++++++++++++++- 4 files changed, 67 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 52e0f4a6cf5..30335647605 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -56,6 +56,17 @@ void save_omap_boot_params(void) *((u32 *)(dev_data + BOOT_MODE_OFFSET)); } } + +#ifdef CONFIG_DRA7XX + /* + * We get different values for QSPI_1 and QSPI_4 being used, but + * don't actually care about this difference. Rather than + * mangle the later code, if we're coming in as QSPI_4 just + * change to the QSPI_1 value. + */ + if (gd->arch.omap_boot_params.omap_bootdevice == 11) + gd->arch.omap_boot_params.omap_bootdevice = BOOT_DEVICE_SPI; +#endif } #ifdef CONFIG_SPL_BUILD diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index c6c4fd1743b..073d15127cf 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "mux_data.h" @@ -124,6 +125,24 @@ int board_mmc_init(bd_t *bis) } #endif +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + +#ifdef CONFIG_SPL_ENV_SUPPORT + env_init(); + env_relocate_spec(); + if (getenv_yesno("boot_os") != 1) + return 1; +#endif + + return 0; +} +#endif + #ifdef CONFIG_DRIVER_TI_CPSW /* Delay value to add to calibrated value */ diff --git a/boards.cfg b/boards.cfg index b4203f1b576..23687c8bece 100644 --- a/boards.cfg +++ b/boards.cfg @@ -361,6 +361,7 @@ Active arm armv7 omap4 ti panda Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla +Active arm armv7 omap5 ti dra7xx dra7xx_evm_qspiboot dra7xx_evm:CONS_INDEX=1,QSPI_BOOT Lokesh Vutla Active arm armv7 omap5 ti omap5_uevm omap5_uevm - - Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu :Tetsuyuki Kobayashi diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 99be52b2872..8d0a0eb8bc6 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -14,6 +14,7 @@ #define CONFIG_DRA7XX +#ifndef CONFIG_QSPI_BOOT /* MMC ENV related defines */ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ @@ -21,6 +22,7 @@ #define CONFIG_ENV_OFFSET 0xE0000 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) #define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#endif #define CONFIG_CMD_SAVEENV #if (CONFIG_CONS_INDEX == 1) @@ -76,13 +78,46 @@ #define CONFIG_SF_DEFAULT_SPEED 48000000 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 +/* + * Default to using SPI for environment, etc. + * 0x000000 - 0x010000 : QSPI.SPL (64KiB) + * 0x010000 - 0x020000 : QSPI.SPL.backup1 (64KiB) + * 0x020000 - 0x030000 : QSPI.SPL.backup2 (64KiB) + * 0x030000 - 0x040000 : QSPI.SPL.backup3 (64KiB) + * 0x040000 - 0x140000 : QSPI.u-boot (1MiB) + * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB) + * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB) + * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB) + * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) + * 0x9E0000 - 0x2000000 : USERLAND + */ +#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 +#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 +#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 +#if defined(CONFIG_QSPI_BOOT) +/* In SPL, use the environment and discard MMC support for space. */ +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_SPL_MMC_SUPPORT +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE (64 << 10) /* 64 KiB */ +#endif +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +#define CONFIG_ENV_SIZE (64 << 10) +#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */ +#define CONFIG_ENV_OFFSET 0x1C0000 +#define CONFIG_ENV_OFFSET_REDUND 0x1D0000 +#endif + /* SPI SPL */ #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_BUS 0 #define CONFIG_SPL_SPI_CS 0 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 #define CONFIG_SUPPORT_EMMC_BOOT -- cgit v1.3.1 From 0dd54619ca6316d75c26c09e3c86e2b8e2697d23 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 3 Apr 2014 15:17:14 -0400 Subject: TI:armv7: Switch to CONFIG_SYS_BOARD_GENERIC Tested on AM335x GP EVM, AM335x EVM SK, Beaglebone White, Beaglebone Black, AM437xx GP EVM, OMAP5 uEVM, OMAP4 Pandaboard Signed-off-by: Tom Rini --- include/configs/ti_armv7_common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 1efc9886610..2aa35407fd3 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -20,6 +20,7 @@ /* Common define for many platforms. */ #define CONFIG_OMAP #define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD /* * We typically do not contain NOR flash. In the cases where we do, we -- cgit v1.3.1 From df4dbb5df6ab1c1d27b3fd4acbaad69b47095daf Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 3 Apr 2014 15:17:15 -0400 Subject: TI:omap3: Convert omap3_beagle to ti_omap3_common.h Convert to using the common config files. This requires a little more flexibility in the common files than we had been using before. Signed-off-by: Tom Rini --- boards.cfg | 2 +- include/configs/omap3_beagle.h | 184 ++++---------------------------------- include/configs/ti_armv7_common.h | 8 ++ include/configs/ti_omap3_common.h | 1 + 4 files changed, 25 insertions(+), 170 deletions(-) (limited to 'include') diff --git a/boards.cfg b/boards.cfg index 23687c8bece..96a69670069 100644 --- a/boards.cfg +++ b/boards.cfg @@ -351,7 +351,7 @@ Active arm armv7 omap3 technexion tao3530 Active arm armv7 omap3 technexion twister twister - Stefano Babic Active arm armv7 omap3 teejet mt_ventoux mt_ventoux - Stefano Babic Active arm armv7 omap3 ti am3517crane am3517_crane - Nagendra T S -Active arm armv7 omap3 ti beagle omap3_beagle - Tom Rini +Active arm armv7 omap3 ti beagle omap3_beagle omap3_beagle:NAND Tom Rini Active arm armv7 omap3 ti evm omap3_evm - Tom Rini Active arm armv7 omap3 ti evm omap3_evm_quick_mmc - - Active arm armv7 omap3 ti evm omap3_evm_quick_nand - - diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 0b574215375..fae0e6ffcb4 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -12,19 +12,22 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ + /* - * High Level Configuration Options + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. We use this rather than the inherited defines from + * ti_armv7_common.h for backwards compatibility. */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON - -#define CONFIG_SDRC /* The chip has SDRC controller */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#include /* get chip and board defs */ -#include +#include /* * Display CPU and Board information @@ -32,57 +35,10 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - #define CONFIG_MISC_INIT_R -#define CONFIG_OF_LIBFDT -#define CONFIG_CMD_BOOTZ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */ - -/* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 /* Status LED */ #define CONFIG_STATUS_LED 1 @@ -134,44 +90,23 @@ #define CONFIG_CMD_ASKENV #define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_FS_GENERIC /* Generic FS support */ -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ + #define MTDIDS_DEFAULT "nand0=nand" #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ "1920k(u-boot),128k(u-boot-env),"\ "4m(kernel),-(fs)" -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ #define CONFIG_USB_STORAGE /* USB storage support */ #define CONFIG_CMD_NAND /* NAND support */ #define CONFIG_CMD_LED /* LED support */ -#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#define CONFIG_CMD_NFS /* NFS support */ -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP #define CONFIG_CMD_SETEXPR /* Evaluate expressions */ #define CONFIG_CMD_GPIO /* Enable gpio command */ -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_IMI /* iminfo */ -#undef CONFIG_CMD_IMLS /* List all found images */ - -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_OMAP34XX #define CONFIG_VIDEO_OMAP3 /* DSS Support */ /* * TWL4030 */ -#define CONFIG_TWL4030_POWER 1 #define CONFIG_TWL4030_LED 1 /* @@ -179,17 +114,9 @@ */ #define CONFIG_SYS_NAND_QUIET_TEST 1 #define CONFIG_NAND_OMAP_GPMC -#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ - /* to access nand */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -/* Environment information */ -#define CONFIG_BOOTDELAY 3 - #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "rdaddr=0x81000000\0" \ @@ -310,45 +237,13 @@ "run mmcbootz; " \ "fi; " \ -#define CONFIG_AUTO_COMPLETE 1 -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # " -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_ALT_MEMTEST 1 -#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ - /* defaults */ -#define CONFIG_SYS_MEMTEST_END (0x87FFFFFF) /* 128MB */ -#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ - /* * OMAP3 has 12 GP timers, they can be driven by the system clock * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). * This rate is divided by a local divisor. */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - /*----------------------------------------------------------------------- * FLASH and environment organization */ @@ -359,8 +254,6 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M #define PISMO1_ONEN_SIZE GPMC_SIZE_128M -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - #if defined(CONFIG_CMD_NAND) #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE #endif @@ -370,6 +263,7 @@ #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP #define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ @@ -377,49 +271,12 @@ #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - #define CONFIG_OMAP3_SPI #define CONFIG_SYS_CACHELINE_SIZE 64 /* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_TEXT_BASE 0x40200800 -#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_POWER_SUPPORT #define CONFIG_SPL_OMAP3_ID_NAND -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" /* NAND boot config */ #define CONFIG_SYS_NAND_5_ADDR_CYCLE @@ -433,17 +290,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 3 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_TEXT_BASE 0x80100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - #endif /* __CONFIG_H */ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 2aa35407fd3..485427276aa 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -111,7 +111,9 @@ */ #ifdef CONFIG_NAND #define CONFIG_NAND_OMAP_GPMC +#ifndef CONFIG_SYS_NAND_BASE #define CONFIG_SYS_NAND_BASE 0x8000000 +#endif #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND #endif @@ -209,12 +211,18 @@ * We have the SPL malloc pool at the end of the BSS area. */ #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x80800000 +#endif +#ifndef CONFIG_SPL_BSS_START_ADDR #define CONFIG_SPL_BSS_START_ADDR 0x80a00000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ +#endif +#ifndef CONFIG_SYS_SPL_MALLOC_START #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ CONFIG_SPL_BSS_MAX_SIZE) #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN +#endif /* RAW SD card / eMMC locations. */ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 1c6ee4c653f..ade35d295a2 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -68,6 +68,7 @@ #ifdef CONFIG_NAND #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SYS_NAND_BASE 0x30000000 #endif /* Now bring in the rest of the common code. */ -- cgit v1.3.1 From 00c200f137b60a04b137e0c7f9097f87ea2ee755 Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Fri, 4 Apr 2014 13:16:47 -0400 Subject: fdt: call ft_board_setup_ex() at the end of image_setup_libfdt() The keystone2 SOC requires to fix all 32 bit aliased addresses to their 36 physical format. This has to happen after all fdt nodes are added or modified. Signed-off-by: Vitaly Andrianov Signed-off-by: Murali Karicheri Acked-by: Tom Rini --- common/image-fdt.c | 5 +++++ include/fdt_support.h | 7 +++++++ 2 files changed, 12 insertions(+) (limited to 'include') diff --git a/common/image-fdt.c b/common/image-fdt.c index a54a919a5b3..5d64009df7d 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -487,5 +487,10 @@ int image_setup_libfdt(bootm_headers_t *images, void *blob, if (!ft_verify_fdt(blob)) return -1; +#ifdef CONFIG_SOC_K2HK + if (IMAGE_OF_BOARD_SETUP) + ft_board_setup_ex(blob, gd->bd); +#endif + return 0; } diff --git a/include/fdt_support.h b/include/fdt_support.h index 9871e2f81a0..15eba01662b 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -63,6 +63,13 @@ int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose); #endif void ft_board_setup(void *blob, bd_t *bd); +/* + * The keystone2 SOC requires all 32 bit aliased addresses to be converted + * to their 36 physical format. This has to happen after all fdt nodes + * are added or modified by the image_setup_libfdt(). The ft_board_setup_ex() + * called at the end of the image_setup_libfdt() is to do that convertion. + */ +void ft_board_setup_ex(void *blob, bd_t *bd); void ft_cpu_setup(void *blob, bd_t *bd); void ft_pci_setup(void *blob, bd_t *bd); -- cgit v1.3.1 From bf411ea9f11a757cb3916f3a2e9753f4e0208672 Mon Sep 17 00:00:00 2001 From: "Karicheri, Muralidharan" Date: Fri, 4 Apr 2014 13:16:48 -0400 Subject: tools: mkimage: add support for gpimage format This patch add support for gpimage format as a preparatory patch for porting u-boot for keystone2 devices and is based on omapimage format. It re-uses gph header to store the size and loadaddr as done in omapimage.c Signed-off-by: Vitaly Andrianov Signed-off-by: Murali Karicheri Acked-by: Tom Rini --- common/image.c | 1 + include/image.h | 1 + tools/Makefile | 2 + tools/gpheader.h | 40 +++++++++++++++++++ tools/gpimage-common.c | 80 +++++++++++++++++++++++++++++++++++++ tools/gpimage.c | 77 ++++++++++++++++++++++++++++++++++++ tools/imagetool.c | 2 + tools/imagetool.h | 1 + tools/omapimage.c | 104 ++++++++----------------------------------------- tools/omapimage.h | 5 --- 10 files changed, 220 insertions(+), 93 deletions(-) create mode 100644 tools/gpheader.h create mode 100644 tools/gpimage-common.c create mode 100644 tools/gpimage.c (limited to 'include') diff --git a/common/image.c b/common/image.c index 9c6bec5b769..fcc5a9c3e12 100644 --- a/common/image.c +++ b/common/image.c @@ -125,6 +125,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_FILESYSTEM, "filesystem", "Filesystem Image", }, { IH_TYPE_FIRMWARE, "firmware", "Firmware", }, { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, + { IH_TYPE_GPIMAGE, "gpimage", "TI Keystone SPL Image",}, { IH_TYPE_KERNEL, "kernel", "Kernel Image", }, { IH_TYPE_KERNEL_NOLOAD, "kernel_noload", "Kernel Image (no loading done)", }, { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, diff --git a/include/image.h b/include/image.h index 6afd57bafdd..8095bc89143 100644 --- a/include/image.h +++ b/include/image.h @@ -215,6 +215,7 @@ struct lmb; #define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */ #define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */ #define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */ +#define IH_TYPE_GPIMAGE 17 /* TI Keystone GPHeader Image */ /* * Compression Types diff --git a/tools/Makefile b/tools/Makefile index 097cc1df178..911ad435900 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -73,6 +73,8 @@ dumpimage-mkimage-objs := aisimage.o \ crc32.o \ default_image.o \ fit_image.o \ + gpimage.o \ + gpimage-common.o \ image-fit.o \ image-host.o \ image.o \ diff --git a/tools/gpheader.h b/tools/gpheader.h new file mode 100644 index 00000000000..63a28a264d5 --- /dev/null +++ b/tools/gpheader.h @@ -0,0 +1,40 @@ +/* + * (C) Copyright 2014 + * Texas Instruments Incorporated + * Refactored common functions in to gpimage-common.c. Include this common + * header file + * + * (C) Copyright 2010 + * Linaro LTD, www.linaro.org + * Author: John Rigby + * Based on TI's signGP.c + * + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2008 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _GPIMAGE_H_ +#define _GPIMAGE_H_ + +/* common headers for gpimage and omapimage formats */ +struct gp_header { + uint32_t size; + uint32_t load_addr; +}; +#define GPIMAGE_HDR_SIZE (sizeof(struct gp_header)) + +/* common functions across gpimage and omapimage handlers */ +int valid_gph_size(uint32_t size); +int valid_gph_load_addr(uint32_t load_addr); +int gph_verify_header(struct gp_header *gph, int be); +void gph_print_header(const struct gp_header *gph, int be); +void gph_set_header(struct gp_header *gph, uint32_t size, uint32_t load_addr, + int be); +int gpimage_check_params(struct image_tool_params *params); +#endif diff --git a/tools/gpimage-common.c b/tools/gpimage-common.c new file mode 100644 index 00000000000..b343a3aa8b7 --- /dev/null +++ b/tools/gpimage-common.c @@ -0,0 +1,80 @@ +/* + * (C) Copyright 2014 + * Texas Instruments Incorporated + * Refactored common functions in to gpimage-common.c. + * + * (C) Copyright 2010 + * Linaro LTD, www.linaro.org + * Author: John Rigby + * Based on TI's signGP.c + * + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2008 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "imagetool.h" +#include +#include +#include "gpheader.h" + +/* Helper to convert size and load_addr to big endian */ +void to_be32(uint32_t *gph_size, uint32_t *gph_load_addr) +{ + *gph_size = cpu_to_be32(*gph_size); + *gph_load_addr = cpu_to_be32(*gph_load_addr); +} + +int gph_verify_header(struct gp_header *gph, int be) +{ + uint32_t gph_size = gph->size, gph_load_addr = gph->load_addr; + + if (be) + to_be32(&gph_size, &gph_load_addr); + + if (!gph_size || !gph_load_addr) + return -1; + + return 0; +} + +void gph_print_header(const struct gp_header *gph, int be) +{ + uint32_t gph_size = gph->size, gph_load_addr = gph->load_addr; + + if (be) + to_be32(&gph_size, &gph_load_addr); + + if (!gph_size) { + fprintf(stderr, "Error: invalid image size %x\n", gph_size); + exit(EXIT_FAILURE); + } + + if (!gph_load_addr) { + fprintf(stderr, "Error: invalid image load address %x\n", + gph_load_addr); + exit(EXIT_FAILURE); + } + printf("GP Header: Size %x LoadAddr %x\n", gph_size, gph_load_addr); +} + +void gph_set_header(struct gp_header *gph, uint32_t size, uint32_t load_addr, + int be) +{ + gph->size = size; + gph->load_addr = load_addr; + if (be) + to_be32(&gph->size, &gph->load_addr); +} + +int gpimage_check_params(struct image_tool_params *params) +{ + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)); +} diff --git a/tools/gpimage.c b/tools/gpimage.c new file mode 100644 index 00000000000..1cabb5b612e --- /dev/null +++ b/tools/gpimage.c @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2014 + * Texas Instruments Incorporated + * Add gpimage format for keystone devices to format spl image. This is + * Based on omapimage.c + * + * (C) Copyright 2010 + * Linaro LTD, www.linaro.org + * Author: John Rigby + * Based on TI's signGP.c + * + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * (C) Copyright 2008 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "imagetool.h" +#include +#include +#include "gpheader.h" + +static uint8_t gpimage_header[GPIMAGE_HDR_SIZE]; + +/* to be in keystone gpimage */ +static int gpimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_GPIMAGE) + return EXIT_SUCCESS; + return EXIT_FAILURE; +} + +static int gpimage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + struct gp_header *gph = (struct gp_header *)ptr; + + return gph_verify_header(gph, 1); +} + +static void gpimage_print_header(const void *ptr) +{ + const struct gp_header *gph = (struct gp_header *)ptr; + + gph_print_header(gph, 1); +} + +static void gpimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + struct gp_header *gph = (struct gp_header *)ptr; + + gph_set_header(gph, sbuf->st_size - GPIMAGE_HDR_SIZE, params->addr, 1); +} + +/* + * gpimage parameters + */ +static struct image_type_params gpimage_params = { + .name = "TI KeyStone GP Image support", + .header_size = GPIMAGE_HDR_SIZE, + .hdr = (void *)&gpimage_header, + .check_image_type = gpimage_check_image_types, + .verify_header = gpimage_verify_header, + .print_header = gpimage_print_header, + .set_header = gpimage_set_header, + .check_params = gpimage_check_params, +}; + +void init_gpimage_type(void) +{ + register_image_type(&gpimage_params); +} diff --git a/tools/imagetool.c b/tools/imagetool.c index 29d21890978..da72115e532 100644 --- a/tools/imagetool.c +++ b/tools/imagetool.c @@ -45,6 +45,8 @@ void register_image_tool(imagetool_register_t image_register) init_ubl_image_type(); /* Init Davinci AIS support */ init_ais_image_type(); + /* Init TI Keystone boot image generation/list support */ + init_gpimage_type(); } /* diff --git a/tools/imagetool.h b/tools/imagetool.h index c2c9aea60eb..a3e9d302eb3 100644 --- a/tools/imagetool.h +++ b/tools/imagetool.h @@ -167,6 +167,7 @@ void init_mxs_image_type(void); void init_fit_image_type(void); void init_ubl_image_type(void); void init_omap_image_type(void); +void init_gpimage_type(void); void pbl_load_uboot(int fd, struct image_tool_params *mparams); diff --git a/tools/omapimage.c b/tools/omapimage.c index d59bc4d40de..1e0c1647968 100644 --- a/tools/omapimage.c +++ b/tools/omapimage.c @@ -15,57 +15,24 @@ */ #include "imagetool.h" +#include #include +#include "gpheader.h" #include "omapimage.h" /* Header size is CH header rounded up to 512 bytes plus GP header */ #define OMAP_CH_HDR_SIZE 512 -#define OMAP_GP_HDR_SIZE (sizeof(struct gp_header)) -#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE+OMAP_GP_HDR_SIZE) +#define OMAP_FILE_HDR_SIZE (OMAP_CH_HDR_SIZE + GPIMAGE_HDR_SIZE) static int do_swap32 = 0; -static uint32_t omapimage_swap32(uint32_t data) -{ - uint32_t result = 0; - result = (data & 0xFF000000) >> 24; - result |= (data & 0x00FF0000) >> 8; - result |= (data & 0x0000FF00) << 8; - result |= (data & 0x000000FF) << 24; - return result; -} - static uint8_t omapimage_header[OMAP_FILE_HDR_SIZE]; static int omapimage_check_image_types(uint8_t type) { if (type == IH_TYPE_OMAPIMAGE) return EXIT_SUCCESS; - else { - return EXIT_FAILURE; - } -} - -/* - * Only the simplest image type is currently supported: - * TOC pointing to CHSETTINGS - * TOC terminator - * CHSETTINGS - * - * padding to OMAP_CH_HDR_SIZE bytes - * - * gp header - * size - * load_addr - */ -static int valid_gph_size(uint32_t size) -{ - return size; -} - -static int valid_gph_load_addr(uint32_t load_addr) -{ - return load_addr; + return EXIT_FAILURE; } static int omapimage_verify_header(unsigned char *ptr, int image_size, @@ -73,13 +40,13 @@ static int omapimage_verify_header(unsigned char *ptr, int image_size, { struct ch_toc *toc = (struct ch_toc *)ptr; struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE); - uint32_t offset, size, gph_size, gph_load_addr; + uint32_t offset, size; while (toc->section_offset != 0xffffffff && toc->section_size != 0xffffffff) { if (do_swap32) { - offset = omapimage_swap32(toc->section_offset); - size = omapimage_swap32(toc->section_size); + offset = cpu_to_be32(toc->section_offset); + size = cpu_to_be32(toc->section_size); } else { offset = toc->section_offset; size = toc->section_size; @@ -92,20 +59,7 @@ static int omapimage_verify_header(unsigned char *ptr, int image_size, toc++; } - if (do_swap32) { - gph_size = omapimage_swap32(gph->size); - gph_load_addr = omapimage_swap32(gph->load_addr); - } else { - gph_size = gph->size; - gph_load_addr = gph->load_addr; - } - - if (!valid_gph_size(gph_size)) - return -1; - if (!valid_gph_load_addr(gph_load_addr)) - return -1; - - return 0; + return gph_verify_header(gph, do_swap32); } static void omapimage_print_section(struct ch_settings *chs) @@ -135,13 +89,13 @@ static void omapimage_print_header(const void *ptr) const struct ch_toc *toc = (struct ch_toc *)ptr; const struct gp_header *gph = (struct gp_header *)(ptr+OMAP_CH_HDR_SIZE); - uint32_t offset, size, gph_size, gph_load_addr; + uint32_t offset, size; while (toc->section_offset != 0xffffffff && toc->section_size != 0xffffffff) { if (do_swap32) { - offset = omapimage_swap32(toc->section_offset); - size = omapimage_swap32(toc->section_size); + offset = cpu_to_be32(toc->section_offset); + size = cpu_to_be32(toc->section_size); } else { offset = toc->section_offset; size = toc->section_size; @@ -160,26 +114,7 @@ static void omapimage_print_header(const void *ptr) toc++; } - if (do_swap32) { - gph_size = omapimage_swap32(gph->size); - gph_load_addr = omapimage_swap32(gph->load_addr); - } else { - gph_size = gph->size; - gph_load_addr = gph->load_addr; - } - - if (!valid_gph_size(gph_size)) { - fprintf(stderr, "Error: invalid image size %x\n", gph_size); - exit(EXIT_FAILURE); - } - - if (!valid_gph_load_addr(gph_load_addr)) { - fprintf(stderr, "Error: invalid image load address %x\n", - gph_load_addr); - exit(EXIT_FAILURE); - } - - printf("GP Header: Size %x LoadAddr %x\n", gph_size, gph_load_addr); + gph_print_header(gph, do_swap32); } static int toc_offset(void *hdr, void *member) @@ -208,8 +143,8 @@ static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd, toc++; memset(toc, 0xff, sizeof(*toc)); - gph->size = sbuf->st_size - OMAP_FILE_HDR_SIZE; - gph->load_addr = params->addr; + gph_set_header(gph, sbuf->st_size - OMAP_FILE_HDR_SIZE, + params->addr, 0); if (strncmp(params->imagename, "byteswap", 8) == 0) { do_swap32 = 1; @@ -217,20 +152,13 @@ static void omapimage_set_header(void *ptr, struct stat *sbuf, int ifd, uint32_t *data = (uint32_t *)ptr; while (swapped <= (sbuf->st_size / sizeof(uint32_t))) { - *data = omapimage_swap32(*data); + *data = cpu_to_be32(*data); swapped++; data++; } } } -int omapimage_check_params(struct image_tool_params *params) -{ - return (params->dflag && (params->fflag || params->lflag)) || - (params->fflag && (params->dflag || params->lflag)) || - (params->lflag && (params->dflag || params->fflag)); -} - /* * omapimage parameters */ @@ -242,7 +170,7 @@ static struct image_type_params omapimage_params = { .verify_header = omapimage_verify_header, .print_header = omapimage_print_header, .set_header = omapimage_set_header, - .check_params = omapimage_check_params, + .check_params = gpimage_check_params, }; void init_omap_image_type(void) diff --git a/tools/omapimage.h b/tools/omapimage.h index 45d14eaf9cc..8744ae7a2de 100644 --- a/tools/omapimage.h +++ b/tools/omapimage.h @@ -25,10 +25,5 @@ struct ch_settings { uint32_t flags; }; -struct gp_header { - uint32_t size; - uint32_t load_addr; -}; - #define KEY_CHSETTINGS 0xC0C0C0C1 #endif /* _OMAPIMAGE_H_ */ -- cgit v1.3.1 From e8459dcc33c3f3fc5a98b7b69bb3ddd7ad77f632 Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Fri, 4 Apr 2014 13:16:52 -0400 Subject: i2c, davinci: convert driver to new mutlibus/mutliadapter framework - add davinci driver to new multibus/multiadpater support - adapted all config files, which uses this driver Signed-off-by: Vitaly Andrianov Signed-off-by: Murali Karicheri Acked-by: Heiko Schocher --- arch/arm/cpu/arm926ejs/davinci/dm355.c | 2 +- arch/arm/cpu/arm926ejs/davinci/dm365.c | 2 +- arch/arm/cpu/arm926ejs/davinci/dm644x.c | 2 +- arch/arm/cpu/arm926ejs/davinci/dm646x.c | 2 +- drivers/i2c/Makefile | 2 +- drivers/i2c/davinci_i2c.c | 401 +++++++++++++++++++------------- drivers/i2c/davinci_i2c.h | 27 ++- include/configs/cam_enc_4xx.h | 8 +- include/configs/da830evm.h | 8 +- include/configs/da850evm.h | 8 +- include/configs/davinci_dm355evm.h | 8 +- include/configs/davinci_dm355leopard.h | 8 +- include/configs/davinci_dm365evm.h | 8 +- include/configs/davinci_dm6467evm.h | 8 +- include/configs/davinci_dvevm.h | 8 +- include/configs/davinci_schmoogie.h | 8 +- include/configs/davinci_sffsdr.h | 8 +- include/configs/davinci_sonata.h | 8 +- include/configs/ea20.h | 7 +- include/configs/enbw_cmc.h | 8 +- 20 files changed, 306 insertions(+), 235 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/arm926ejs/davinci/dm355.c b/arch/arm/cpu/arm926ejs/davinci/dm355.c index 5f85162b8e0..f9550a16d34 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm355.c +++ b/arch/arm/cpu/arm926ejs/davinci/dm355.c @@ -19,7 +19,7 @@ void davinci_enable_uart0(void) } -#ifdef CONFIG_DRIVER_DAVINCI_I2C +#ifdef CONFIG_SYS_I2C_DAVINCI void davinci_enable_i2c(void) { lpsc_on(DAVINCI_LPSC_I2C); diff --git a/arch/arm/cpu/arm926ejs/davinci/dm365.c b/arch/arm/cpu/arm926ejs/davinci/dm365.c index 0af2d0236d8..f6ca527e74c 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm365.c +++ b/arch/arm/cpu/arm926ejs/davinci/dm365.c @@ -12,7 +12,7 @@ void davinci_enable_uart0(void) lpsc_on(DAVINCI_LPSC_UART0); } -#ifdef CONFIG_DRIVER_DAVINCI_I2C +#ifdef CONFIG_SYS_I2C_DAVINCI void davinci_enable_i2c(void) { lpsc_on(DAVINCI_LPSC_I2C); diff --git a/arch/arm/cpu/arm926ejs/davinci/dm644x.c b/arch/arm/cpu/arm926ejs/davinci/dm644x.c index 788e57840f8..c58e271e281 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm644x.c +++ b/arch/arm/cpu/arm926ejs/davinci/dm644x.c @@ -47,7 +47,7 @@ void davinci_enable_emac(void) } #endif -#ifdef CONFIG_DRIVER_DAVINCI_I2C +#ifdef CONFIG_SYS_I2C_DAVINCI void davinci_enable_i2c(void) { lpsc_on(DAVINCI_LPSC_I2C); diff --git a/arch/arm/cpu/arm926ejs/davinci/dm646x.c b/arch/arm/cpu/arm926ejs/davinci/dm646x.c index 86a508f6a12..cfea8300def 100644 --- a/arch/arm/cpu/arm926ejs/davinci/dm646x.c +++ b/arch/arm/cpu/arm926ejs/davinci/dm646x.c @@ -18,7 +18,7 @@ void davinci_enable_emac(void) } #endif -#ifdef CONFIG_DRIVER_DAVINCI_I2C +#ifdef CONFIG_SYS_I2C_DAVINCI void davinci_enable_i2c(void) { lpsc_on(DAVINCI_DM646X_LPSC_I2C); diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 36d5e5f1a2e..e33586d8a6b 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -6,7 +6,6 @@ # obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o -obj-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o obj-$(CONFIG_DW_I2C) += designware_i2c.o obj-$(CONFIG_I2C_MVTWSI) += mvtwsi.o obj-$(CONFIG_I2C_MV) += mv_i2c.o @@ -16,6 +15,7 @@ obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_U8500_I2C) += u8500_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o diff --git a/drivers/i2c/davinci_i2c.c b/drivers/i2c/davinci_i2c.c index 6e5260c4825..9ca99c4abd0 100644 --- a/drivers/i2c/davinci_i2c.c +++ b/drivers/i2c/davinci_i2c.c @@ -1,8 +1,9 @@ /* * TI DaVinci (TMS320DM644x) I2C driver. * - * Copyright (C) 2007 Sergey Kubushyn - * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * (C) Copyright 2007 Sergey Kubushyn * -------------------------------------------------------- * * SPDX-License-Identifier: GPL-2.0+ @@ -12,306 +13,372 @@ #include #include #include +#include #include "davinci_i2c.h" #define CHECK_NACK() \ do {\ if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\ - REG(I2C_CON) = 0;\ - return(1);\ - }\ + REG(&(i2c_base->i2c_con)) = 0;\ + return 1;\ + } \ } while (0) +static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap); -static int wait_for_bus(void) +static int wait_for_bus(struct i2c_adapter *adap) { + struct i2c_regs *i2c_base = davinci_get_base(adap); int stat, timeout; - REG(I2C_STAT) = 0xffff; + REG(&(i2c_base->i2c_stat)) = 0xffff; for (timeout = 0; timeout < 10; timeout++) { - if (!((stat = REG(I2C_STAT)) & I2C_STAT_BB)) { - REG(I2C_STAT) = 0xffff; - return(0); + stat = REG(&(i2c_base->i2c_stat)); + if (!((stat) & I2C_STAT_BB)) { + REG(&(i2c_base->i2c_stat)) = 0xffff; + return 0; } - REG(I2C_STAT) = stat; + REG(&(i2c_base->i2c_stat)) = stat; udelay(50000); } - REG(I2C_STAT) = 0xffff; - return(1); + REG(&(i2c_base->i2c_stat)) = 0xffff; + return 1; } -static int poll_i2c_irq(int mask) +static int poll_i2c_irq(struct i2c_adapter *adap, int mask) { + struct i2c_regs *i2c_base = davinci_get_base(adap); int stat, timeout; for (timeout = 0; timeout < 10; timeout++) { udelay(1000); - stat = REG(I2C_STAT); - if (stat & mask) { - return(stat); - } + stat = REG(&(i2c_base->i2c_stat)); + if (stat & mask) + return stat; } - REG(I2C_STAT) = 0xffff; - return(stat | I2C_TIMEOUT); + REG(&(i2c_base->i2c_stat)) = 0xffff; + return stat | I2C_TIMEOUT; } - -void flush_rx(void) +static void flush_rx(struct i2c_adapter *adap) { + struct i2c_regs *i2c_base = davinci_get_base(adap); + while (1) { - if (!(REG(I2C_STAT) & I2C_STAT_RRDY)) + if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY)) break; - REG(I2C_DRR); - REG(I2C_STAT) = I2C_STAT_RRDY; + REG(&(i2c_base->i2c_drr)); + REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY; udelay(1000); } } +static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed) +{ + struct i2c_regs *i2c_base = davinci_get_base(adap); + uint32_t div, psc; + + psc = 2; + /* SCLL + SCLH */ + div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; + REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */ + REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */ + REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll)); + + adap->speed = speed; + return 0; +} -void i2c_init(int speed, int slaveadd) +static void davinci_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) { - u_int32_t div, psc; + struct i2c_regs *i2c_base = davinci_get_base(adap); - if (REG(I2C_CON) & I2C_CON_EN) { - REG(I2C_CON) = 0; - udelay (50000); + if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) { + REG(&(i2c_base->i2c_con)) = 0; + udelay(50000); } - psc = 2; - div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */ - REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */ - REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */ - REG(I2C_SCLH) = div - REG(I2C_SCLL); + davinci_i2c_setspeed(adap, speed); - REG(I2C_OA) = slaveadd; - REG(I2C_CNT) = 0; + REG(&(i2c_base->i2c_oa)) = slaveadd; + REG(&(i2c_base->i2c_cnt)) = 0; /* Interrupts must be enabled or I2C module won't work */ - REG(I2C_IE) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | + REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE; /* Now enable I2C controller (get it out of reset) */ - REG(I2C_CON) = I2C_CON_EN; + REG(&(i2c_base->i2c_con)) = I2C_CON_EN; udelay(1000); } -int i2c_set_bus_speed(unsigned int speed) -{ - i2c_init(speed, CONFIG_SYS_I2C_SLAVE); - return 0; -} - -int i2c_probe(u_int8_t chip) +static int davinci_i2c_probe(struct i2c_adapter *adap, uint8_t chip) { + struct i2c_regs *i2c_base = davinci_get_base(adap); int rc = 1; - if (chip == REG(I2C_OA)) { - return(rc); - } + if (chip == REG(&(i2c_base->i2c_oa))) + return rc; - REG(I2C_CON) = 0; - if (wait_for_bus()) {return(1);} + REG(&(i2c_base->i2c_con)) = 0; + if (wait_for_bus(adap)) + return 1; /* try to read one byte from current (or only) address */ - REG(I2C_CNT) = 1; - REG(I2C_SA) = chip; - REG(I2C_CON) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP); - udelay (50000); + REG(&(i2c_base->i2c_cnt)) = 1; + REG(&(i2c_base->i2c_sa)) = chip; + REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | + I2C_CON_STP); + udelay(50000); - if (!(REG(I2C_STAT) & I2C_STAT_NACK)) { + if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) { rc = 0; - flush_rx(); - REG(I2C_STAT) = 0xffff; + flush_rx(adap); + REG(&(i2c_base->i2c_stat)) = 0xffff; } else { - REG(I2C_STAT) = 0xffff; - REG(I2C_CON) |= I2C_CON_STP; + REG(&(i2c_base->i2c_stat)) = 0xffff; + REG(&(i2c_base->i2c_con)) |= I2C_CON_STP; udelay(20000); - if (wait_for_bus()) {return(1);} + if (wait_for_bus(adap)) + return 1; } - flush_rx(); - REG(I2C_STAT) = 0xffff; - REG(I2C_CNT) = 0; - return(rc); + flush_rx(adap); + REG(&(i2c_base->i2c_stat)) = 0xffff; + REG(&(i2c_base->i2c_cnt)) = 0; + return rc; } - -int i2c_read(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip, + uint32_t addr, int alen, uint8_t *buf, int len) { - u_int32_t tmp; + struct i2c_regs *i2c_base = davinci_get_base(adap); + uint32_t tmp; int i; if ((alen < 0) || (alen > 2)) { - printf("%s(): bogus address length %x\n", __FUNCTION__, alen); - return(1); + printf("%s(): bogus address length %x\n", __func__, alen); + return 1; } - if (wait_for_bus()) {return(1);} + if (wait_for_bus(adap)) + return 1; if (alen != 0) { /* Start address phase */ tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX; - REG(I2C_CNT) = alen; - REG(I2C_SA) = chip; - REG(I2C_CON) = tmp; + REG(&(i2c_base->i2c_cnt)) = alen; + REG(&(i2c_base->i2c_sa)) = chip; + REG(&(i2c_base->i2c_con)) = tmp; - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); CHECK_NACK(); switch (alen) { - case 2: - /* Send address MSByte */ - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = (addr >> 8) & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } - - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); - - CHECK_NACK(); - /* No break, fall through */ - case 1: - /* Send address LSByte */ - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = addr & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } - - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK | I2C_STAT_ARDY); - - CHECK_NACK(); - - if (!(tmp & I2C_STAT_ARDY)) { - REG(I2C_CON) = 0; - return(1); - } + case 2: + /* Send address MSByte */ + if (tmp & I2C_STAT_XRDY) { + REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff; + } else { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } + + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); + + CHECK_NACK(); + /* No break, fall through */ + case 1: + /* Send address LSByte */ + if (tmp & I2C_STAT_XRDY) { + REG(&(i2c_base->i2c_dxr)) = addr & 0xff; + } else { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } + + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | + I2C_STAT_NACK | I2C_STAT_ARDY); + + CHECK_NACK(); + + if (!(tmp & I2C_STAT_ARDY)) { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } } } /* Address phase is over, now read 'len' bytes and stop */ tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP; - REG(I2C_CNT) = len & 0xffff; - REG(I2C_SA) = chip; - REG(I2C_CON) = tmp; + REG(&(i2c_base->i2c_cnt)) = len & 0xffff; + REG(&(i2c_base->i2c_sa)) = chip; + REG(&(i2c_base->i2c_con)) = tmp; for (i = 0; i < len; i++) { - tmp = poll_i2c_irq(I2C_STAT_RRDY | I2C_STAT_NACK | I2C_STAT_ROVR); + tmp = poll_i2c_irq(adap, I2C_STAT_RRDY | I2C_STAT_NACK | + I2C_STAT_ROVR); CHECK_NACK(); if (tmp & I2C_STAT_RRDY) { - buf[i] = REG(I2C_DRR); + buf[i] = REG(&(i2c_base->i2c_drr)); } else { - REG(I2C_CON) = 0; - return(1); + REG(&(i2c_base->i2c_con)) = 0; + return 1; } } - tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); + tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK); CHECK_NACK(); if (!(tmp & I2C_STAT_SCD)) { - REG(I2C_CON) = 0; - return(1); + REG(&(i2c_base->i2c_con)) = 0; + return 1; } - flush_rx(); - REG(I2C_STAT) = 0xffff; - REG(I2C_CNT) = 0; - REG(I2C_CON) = 0; + flush_rx(adap); + REG(&(i2c_base->i2c_stat)) = 0xffff; + REG(&(i2c_base->i2c_cnt)) = 0; + REG(&(i2c_base->i2c_con)) = 0; - return(0); + return 0; } - -int i2c_write(u_int8_t chip, u_int32_t addr, int alen, u_int8_t *buf, int len) +static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip, + uint32_t addr, int alen, uint8_t *buf, int len) { - u_int32_t tmp; + struct i2c_regs *i2c_base = davinci_get_base(adap); + uint32_t tmp; int i; if ((alen < 0) || (alen > 2)) { - printf("%s(): bogus address length %x\n", __FUNCTION__, alen); - return(1); + printf("%s(): bogus address length %x\n", __func__, alen); + return 1; } if (len < 0) { - printf("%s(): bogus length %x\n", __FUNCTION__, len); - return(1); + printf("%s(): bogus length %x\n", __func__, len); + return 1; } - if (wait_for_bus()) {return(1);} + if (wait_for_bus(adap)) + return 1; /* Start address phase */ - tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP; - REG(I2C_CNT) = (alen == 0) ? len & 0xffff : (len & 0xffff) + alen; - REG(I2C_SA) = chip; - REG(I2C_CON) = tmp; + tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | + I2C_CON_TRX | I2C_CON_STP; + REG(&(i2c_base->i2c_cnt)) = (alen == 0) ? + len & 0xffff : (len & 0xffff) + alen; + REG(&(i2c_base->i2c_sa)) = chip; + REG(&(i2c_base->i2c_con)) = tmp; switch (alen) { - case 2: - /* Send address MSByte */ - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + case 2: + /* Send address MSByte */ + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); - CHECK_NACK(); + CHECK_NACK(); - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = (addr >> 8) & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } - /* No break, fall through */ - case 1: - /* Send address LSByte */ - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + if (tmp & I2C_STAT_XRDY) { + REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff; + } else { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } + /* No break, fall through */ + case 1: + /* Send address LSByte */ + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); - CHECK_NACK(); + CHECK_NACK(); - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = addr & 0xff; - } else { - REG(I2C_CON) = 0; - return(1); - } + if (tmp & I2C_STAT_XRDY) { + REG(&(i2c_base->i2c_dxr)) = addr & 0xff; + } else { + REG(&(i2c_base->i2c_con)) = 0; + return 1; + } } for (i = 0; i < len; i++) { - tmp = poll_i2c_irq(I2C_STAT_XRDY | I2C_STAT_NACK); + tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK); CHECK_NACK(); - if (tmp & I2C_STAT_XRDY) { - REG(I2C_DXR) = buf[i]; - } else { - return(1); - } + if (tmp & I2C_STAT_XRDY) + REG(&(i2c_base->i2c_dxr)) = buf[i]; + else + return 1; } - tmp = poll_i2c_irq(I2C_STAT_SCD | I2C_STAT_NACK); + tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK); CHECK_NACK(); if (!(tmp & I2C_STAT_SCD)) { - REG(I2C_CON) = 0; - return(1); + REG(&(i2c_base->i2c_con)) = 0; + return 1; } - flush_rx(); - REG(I2C_STAT) = 0xffff; - REG(I2C_CNT) = 0; - REG(I2C_CON) = 0; + flush_rx(adap); + REG(&(i2c_base->i2c_stat)) = 0xffff; + REG(&(i2c_base->i2c_cnt)) = 0; + REG(&(i2c_base->i2c_con)) = 0; + + return 0; +} + +static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap) +{ + switch (adap->hwadapnr) { +#if I2C_BUS_MAX >= 3 + case 2: + return (struct i2c_regs *)I2C2_BASE; +#endif +#if I2C_BUS_MAX >= 2 + case 1: + return (struct i2c_regs *)I2C1_BASE; +#endif + case 0: + return (struct i2c_regs *)I2C_BASE; + + default: + printf("wrong hwadapnr: %d\n", adap->hwadapnr); + } - return(0); + return NULL; } + +U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe, + davinci_i2c_read, davinci_i2c_write, + davinci_i2c_setspeed, + CONFIG_SYS_DAVINCI_I2C_SPEED, + CONFIG_SYS_DAVINCI_I2C_SLAVE, + 0) + +#if I2C_BUS_MAX >= 2 +U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe, + davinci_i2c_read, davinci_i2c_write, + davinci_i2c_setspeed, + CONFIG_SYS_DAVINCI_I2C_SPEED1, + CONFIG_SYS_DAVINCI_I2C_SLAVE1, + 1) +#endif + +#if I2C_BUS_MAX >= 3 +U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe, + davinci_i2c_read, davinci_i2c_write, + davinci_i2c_setspeed, + CONFIG_SYS_DAVINCI_I2C_SPEED2, + CONFIG_SYS_DAVINCI_I2C_SLAVE2, + 2) +#endif diff --git a/drivers/i2c/davinci_i2c.h b/drivers/i2c/davinci_i2c.h index 79ff7a3d678..20d43424b9f 100644 --- a/drivers/i2c/davinci_i2c.h +++ b/drivers/i2c/davinci_i2c.h @@ -12,18 +12,21 @@ #define I2C_WRITE 0 #define I2C_READ 1 -#define I2C_OA (I2C_BASE + 0x00) -#define I2C_IE (I2C_BASE + 0x04) -#define I2C_STAT (I2C_BASE + 0x08) -#define I2C_SCLL (I2C_BASE + 0x0c) -#define I2C_SCLH (I2C_BASE + 0x10) -#define I2C_CNT (I2C_BASE + 0x14) -#define I2C_DRR (I2C_BASE + 0x18) -#define I2C_SA (I2C_BASE + 0x1c) -#define I2C_DXR (I2C_BASE + 0x20) -#define I2C_CON (I2C_BASE + 0x24) -#define I2C_IV (I2C_BASE + 0x28) -#define I2C_PSC (I2C_BASE + 0x30) +struct i2c_regs { + u32 i2c_oa; + u32 i2c_ie; + u32 i2c_stat; + u32 i2c_scll; + u32 i2c_sclh; + u32 i2c_cnt; + u32 i2c_drr; + u32 i2c_sa; + u32 i2c_dxr; + u32 i2c_con; + u32 i2c_iv; + u32 res_2c; + u32 i2c_psc; +}; /* I2C masks */ diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index 8182a7577bc..d1a8ff2a82f 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -57,10 +57,10 @@ #define CONFIG_RESET_PHY_R /* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ /* NAND: socketed, two chipselects, normally 2 GBytes */ #define CONFIG_NAND_DAVINCI diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index c4cc62ecb41..27171950a6c 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -55,10 +55,10 @@ /* * I2C Configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */ -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 /* 100Kbps won't work, H/W bug */ +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /* * I2C EEPROM definitions for catalyst 24W256 EEPROM chip diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 509fe20d2c2..860a11dd2b3 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -166,10 +166,10 @@ /* * I2C Configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 25000 -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 /* diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h index 6382e75b95e..c2e187e3de2 100644 --- a/include/configs/davinci_dm355evm.h +++ b/include/configs/davinci_dm355evm.h @@ -41,10 +41,10 @@ #define DM9000_DATA (CONFIG_DM9000_BASE + 2) /* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ /* NAND: socketed, two chipselects, normally 2 GBytes */ #define CONFIG_NAND_DAVINCI diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h index 234bbc09965..5188fdf8785 100644 --- a/include/configs/davinci_dm355leopard.h +++ b/include/configs/davinci_dm355leopard.h @@ -40,10 +40,10 @@ #define DM9000_DATA (CONFIG_DM9000_BASE + 16) /* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x10 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* NAND */ #define CONFIG_NAND_DAVINCI diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index b547289d2d0..c4fccfd39a4 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -49,10 +49,10 @@ #define CONFIG_NET_RETRY_COUNT 10 /* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x10 /* SMBus host address */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ /* NAND: socketed, two chipselects, normally 2 GBytes */ #define CONFIG_NAND_DAVINCI diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h index 2132342eb7e..8a3c4533473 100644 --- a/include/configs/davinci_dm6467evm.h +++ b/include/configs/davinci_dm6467evm.h @@ -60,10 +60,10 @@ extern unsigned int davinci_arm_clk_get(void); #define CONFIG_BAUDRATE 115200 /* I2C Configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 80000 -#define CONFIG_SYS_I2C_SLAVE 10 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Network & Ethernet Configuration */ #define CONFIG_DRIVER_TI_EMAC diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index d8fa64600ae..9b3d0febc01 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -77,10 +77,10 @@ /*===================*/ /* I2C Configuration */ /*===================*/ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /*==================================*/ /* Network & Ethernet Configuration */ /*==================================*/ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index f9a0a76d367..96c8fe2a4d4 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -46,10 +46,10 @@ /*===================*/ /* I2C Configuration */ /*===================*/ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /*==================================*/ /* Network & Ethernet Configuration */ /*==================================*/ diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h index 44449df9cd8..6e07cce766e 100644 --- a/include/configs/davinci_sffsdr.h +++ b/include/configs/davinci_sffsdr.h @@ -42,10 +42,10 @@ #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */ /* I2C Configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /* Network & Ethernet Configuration */ #define CONFIG_DRIVER_TI_EMAC #define CONFIG_MII diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index ac543f8d942..cd23aaca209 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -78,10 +78,10 @@ /*===================*/ /* I2C Configuration */ /*===================*/ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /*==================================*/ /* Network & Ethernet Configuration */ /*==================================*/ diff --git a/include/configs/ea20.h b/include/configs/ea20.h index 58e40ed888d..1d50a37d2fc 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -78,9 +78,10 @@ /* * I2C Configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ /* * Network & Ethernet Configuration diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h index 03b74a2dabe..30ca95f02d5 100644 --- a/include/configs/enbw_cmc.h +++ b/include/configs/enbw_cmc.h @@ -73,10 +73,10 @@ /* * I2C Configuration */ -#define CONFIG_HARD_I2C -#define CONFIG_DRIVER_DAVINCI_I2C -#define CONFIG_SYS_I2C_SPEED 80000 -#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 #define CONFIG_CMD_I2C -- cgit v1.3.1 From ef509b9063fb702ce69d1a64ff293698a04075d6 Mon Sep 17 00:00:00 2001 From: Vitaly Andrianov Date: Fri, 4 Apr 2014 13:16:53 -0400 Subject: k2hk: add support for k2hk SOC and EVM k2hk EVM is based on Texas Instruments Keystone2 Hawking/Kepler SoC. Keystone2 SoC has ARM v7 Cortex-A15 MPCore processor. Please refer the ti/k2hk_evm/README for details on the board, build and other information. This patch add support for keystone architecture and k2hk evm. Signed-off-by: Vitaly Andrianov Signed-off-by: Murali Karicheri Signed-off-by: WingMan Kwok Signed-off-by: Sandeep Nair --- Makefile | 10 + arch/arm/cpu/armv7/keystone/Makefile | 16 ++ arch/arm/cpu/armv7/keystone/aemif.c | 71 +++++ arch/arm/cpu/armv7/keystone/clock.c | 318 +++++++++++++++++++++ arch/arm/cpu/armv7/keystone/cmd_clock.c | 124 ++++++++ arch/arm/cpu/armv7/keystone/cmd_mon.c | 131 +++++++++ arch/arm/cpu/armv7/keystone/ddr3.c | 69 +++++ arch/arm/cpu/armv7/keystone/init.c | 56 ++++ arch/arm/cpu/armv7/keystone/msmc.c | 68 +++++ arch/arm/cpu/armv7/keystone/psc.c | 237 +++++++++++++++ arch/arm/cpu/armv7/keystone/spl.c | 45 +++ arch/arm/include/asm/arch-keystone/clock-k2hk.h | 109 +++++++ arch/arm/include/asm/arch-keystone/clock.h | 17 ++ arch/arm/include/asm/arch-keystone/clock_defs.h | 111 +++++++ arch/arm/include/asm/arch-keystone/emif_defs.h | 73 +++++ arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 150 ++++++++++ arch/arm/include/asm/arch-keystone/hardware.h | 175 ++++++++++++ arch/arm/include/asm/arch-keystone/i2c_defs.h | 17 ++ arch/arm/include/asm/arch-keystone/nand_defs.h | 23 ++ arch/arm/include/asm/arch-keystone/psc_defs.h | 90 ++++++ arch/arm/include/asm/arch-keystone/spl.h | 12 + board/ti/k2hk_evm/Makefile | 9 + board/ti/k2hk_evm/README | 122 ++++++++ board/ti/k2hk_evm/board.c | 236 +++++++++++++++ board/ti/k2hk_evm/ddr3.c | 268 +++++++++++++++++ boards.cfg | 1 + drivers/serial/ns16550.c | 8 + include/configs/k2hk_evm.h | 212 ++++++++++++++ 28 files changed, 2778 insertions(+) create mode 100644 arch/arm/cpu/armv7/keystone/Makefile create mode 100644 arch/arm/cpu/armv7/keystone/aemif.c create mode 100644 arch/arm/cpu/armv7/keystone/clock.c create mode 100644 arch/arm/cpu/armv7/keystone/cmd_clock.c create mode 100644 arch/arm/cpu/armv7/keystone/cmd_mon.c create mode 100644 arch/arm/cpu/armv7/keystone/ddr3.c create mode 100644 arch/arm/cpu/armv7/keystone/init.c create mode 100644 arch/arm/cpu/armv7/keystone/msmc.c create mode 100644 arch/arm/cpu/armv7/keystone/psc.c create mode 100644 arch/arm/cpu/armv7/keystone/spl.c create mode 100644 arch/arm/include/asm/arch-keystone/clock-k2hk.h create mode 100644 arch/arm/include/asm/arch-keystone/clock.h create mode 100644 arch/arm/include/asm/arch-keystone/clock_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/emif_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/hardware-k2hk.h create mode 100644 arch/arm/include/asm/arch-keystone/hardware.h create mode 100644 arch/arm/include/asm/arch-keystone/i2c_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/nand_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/psc_defs.h create mode 100644 arch/arm/include/asm/arch-keystone/spl.h create mode 100644 board/ti/k2hk_evm/Makefile create mode 100644 board/ti/k2hk_evm/README create mode 100644 board/ti/k2hk_evm/board.c create mode 100644 board/ti/k2hk_evm/ddr3.c create mode 100644 include/configs/k2hk_evm.h (limited to 'include') diff --git a/Makefile b/Makefile index b2937e95e1b..464d731c2e2 100644 --- a/Makefile +++ b/Makefile @@ -870,6 +870,16 @@ OBJCOPYFLAGS_u-boot.spr = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE $(call if_changed,pad_cat) +MKIMAGEFLAGS_u-boot-spl.gph = -A $(ARCH) -T gpimage -C none \ + -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE) -n SPL +spl/u-boot-spl.gph: spl/u-boot-spl.bin FORCE + $(call if_changed,mkimage) + +OBJCOPYFLAGS_u-boot-spi.gph = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ + --gap-fill=0 +u-boot-spi.gph: spl/u-boot-spl.gph u-boot.img FORCE + $(call if_changed,pad_cat) + ifneq ($(CONFIG_TEGRA),) OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE) u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile new file mode 100644 index 00000000000..05b385204de --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/Makefile @@ -0,0 +1,16 @@ +# +# (C) Copyright 2012-2014 +# Texas Instruments Incorporated, +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += aemif.o +obj-y += init.o +obj-y += psc.o +obj-y += clock.o +obj-y += cmd_clock.o +obj-y += cmd_mon.o +obj-y += msmc.o +obj-$(CONFIG_SPL_BUILD) += spl.o +obj-y += ddr3.o diff --git a/arch/arm/cpu/armv7/keystone/aemif.c b/arch/arm/cpu/armv7/keystone/aemif.c new file mode 100644 index 00000000000..9b26886dba6 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/aemif.c @@ -0,0 +1,71 @@ +/* + * Keystone2: Asynchronous EMIF Configuration + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define AEMIF_CFG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) +#define AEMIF_CFG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) +#define AEMIF_CFG_WR_SETUP(v) (((v) & 0x0f) << 26) +#define AEMIF_CFG_WR_STROBE(v) (((v) & 0x3f) << 20) +#define AEMIF_CFG_WR_HOLD(v) (((v) & 0x07) << 17) +#define AEMIF_CFG_RD_SETUP(v) (((v) & 0x0f) << 13) +#define AEMIF_CFG_RD_STROBE(v) (((v) & 0x3f) << 7) +#define AEMIF_CFG_RD_HOLD(v) (((v) & 0x07) << 4) +#define AEMIF_CFG_TURN_AROUND(v) (((v) & 0x03) << 2) +#define AEMIF_CFG_WIDTH(v) (((v) & 0x03) << 0) + +#define set_config_field(reg, field, val) \ + do { \ + if (val != -1) { \ + reg &= ~AEMIF_CFG_##field(0xffffffff); \ + reg |= AEMIF_CFG_##field(val); \ + } \ + } while (0) + +void configure_async_emif(int cs, struct async_emif_config *cfg) +{ + unsigned long tmp; + + if (cfg->mode == ASYNC_EMIF_MODE_NAND) { + tmp = __raw_readl(&davinci_emif_regs->nandfcr); + tmp |= (1 << cs); + __raw_writel(tmp, &davinci_emif_regs->nandfcr); + + } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) { + tmp = __raw_readl(&davinci_emif_regs->one_nand_cr); + tmp |= (1 << cs); + __raw_writel(tmp, &davinci_emif_regs->one_nand_cr); + } + + tmp = __raw_readl(&davinci_emif_regs->abncr[cs]); + + set_config_field(tmp, SELECT_STROBE, cfg->select_strobe); + set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait); + set_config_field(tmp, WR_SETUP, cfg->wr_setup); + set_config_field(tmp, WR_STROBE, cfg->wr_strobe); + set_config_field(tmp, WR_HOLD, cfg->wr_hold); + set_config_field(tmp, RD_SETUP, cfg->rd_setup); + set_config_field(tmp, RD_STROBE, cfg->rd_strobe); + set_config_field(tmp, RD_HOLD, cfg->rd_hold); + set_config_field(tmp, TURN_AROUND, cfg->turn_around); + set_config_field(tmp, WIDTH, cfg->width); + + __raw_writel(tmp, &davinci_emif_regs->abncr[cs]); +} + +void init_async_emif(int num_cs, struct async_emif_config *config) +{ + int cs; + + for (cs = 0; cs < num_cs; cs++) + configure_async_emif(cs, config + cs); +} diff --git a/arch/arm/cpu/armv7/keystone/clock.c b/arch/arm/cpu/armv7/keystone/clock.c new file mode 100644 index 00000000000..bfa4c9d8f6a --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/clock.c @@ -0,0 +1,318 @@ +/* + * Keystone2: pll initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static void wait_for_completion(const struct pll_init_data *data) +{ + int i; + for (i = 0; i < 100; i++) { + sdelay(450); + if ((pllctl_reg_read(data->pll, stat) & PLLSTAT_GO) == 0) + break; + } +} + +struct pll_regs { + u32 reg0, reg1; +}; + +static const struct pll_regs pll_regs[] = { + [CORE_PLL] = { K2HK_MAINPLLCTL0, K2HK_MAINPLLCTL1}, + [PASS_PLL] = { K2HK_PASSPLLCTL0, K2HK_PASSPLLCTL1}, + [TETRIS_PLL] = { K2HK_ARMPLLCTL0, K2HK_ARMPLLCTL1}, + [DDR3A_PLL] = { K2HK_DDR3APLLCTL0, K2HK_DDR3APLLCTL1}, + [DDR3B_PLL] = { K2HK_DDR3BPLLCTL0, K2HK_DDR3BPLLCTL1}, +}; + +/* Fout = Fref * NF(mult) / NR(prediv) / OD */ +static unsigned long pll_freq_get(int pll) +{ + unsigned long mult = 1, prediv = 1, output_div = 2; + unsigned long ret; + u32 tmp, reg; + + if (pll == CORE_PLL) { + ret = external_clk[sys_clk]; + if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN) { + /* PLL mode */ + tmp = __raw_readl(K2HK_MAINPLLCTL0); + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = (((tmp & PLLM_MULT_HI_SMASK) >> 6) | + (pllctl_reg_read(pll, mult) & + PLLM_MULT_LO_MASK)) + 1; + output_div = ((pllctl_reg_read(pll, secctl) >> + PLL_CLKOD_SHIFT) & PLL_CLKOD_MASK) + 1; + + ret = ret / prediv / output_div * mult; + } + } else { + switch (pll) { + case PASS_PLL: + ret = external_clk[pa_clk]; + reg = K2HK_PASSPLLCTL0; + break; + case TETRIS_PLL: + ret = external_clk[tetris_clk]; + reg = K2HK_ARMPLLCTL0; + break; + case DDR3A_PLL: + ret = external_clk[ddr3a_clk]; + reg = K2HK_DDR3APLLCTL0; + break; + case DDR3B_PLL: + ret = external_clk[ddr3b_clk]; + reg = K2HK_DDR3BPLLCTL0; + break; + default: + return 0; + } + + tmp = __raw_readl(reg); + + if (!(tmp & PLLCTL_BYPASS)) { + /* Bypass disabled */ + prediv = (tmp & PLL_DIV_MASK) + 1; + mult = ((tmp >> PLL_MULT_SHIFT) & PLL_MULT_MASK) + 1; + output_div = ((tmp >> PLL_CLKOD_SHIFT) & + PLL_CLKOD_MASK) + 1; + ret = ((ret / prediv) * mult) / output_div; + } + } + + return ret; +} + +unsigned long clk_get_rate(unsigned int clk) +{ + switch (clk) { + case core_pll_clk: return pll_freq_get(CORE_PLL); + case pass_pll_clk: return pll_freq_get(PASS_PLL); + case tetris_pll_clk: return pll_freq_get(TETRIS_PLL); + case ddr3a_pll_clk: return pll_freq_get(DDR3A_PLL); + case ddr3b_pll_clk: return pll_freq_get(DDR3B_PLL); + case sys_clk0_1_clk: + case sys_clk0_clk: return pll_freq_get(CORE_PLL) / pll0div_read(1); + case sys_clk1_clk: return pll_freq_get(CORE_PLL) / pll0div_read(2); + case sys_clk2_clk: return pll_freq_get(CORE_PLL) / pll0div_read(3); + case sys_clk3_clk: return pll_freq_get(CORE_PLL) / pll0div_read(4); + case sys_clk0_2_clk: return clk_get_rate(sys_clk0_clk) / 2; + case sys_clk0_3_clk: return clk_get_rate(sys_clk0_clk) / 3; + case sys_clk0_4_clk: return clk_get_rate(sys_clk0_clk) / 4; + case sys_clk0_6_clk: return clk_get_rate(sys_clk0_clk) / 6; + case sys_clk0_8_clk: return clk_get_rate(sys_clk0_clk) / 8; + case sys_clk0_12_clk: return clk_get_rate(sys_clk0_clk) / 12; + case sys_clk0_24_clk: return clk_get_rate(sys_clk0_clk) / 24; + case sys_clk1_3_clk: return clk_get_rate(sys_clk1_clk) / 3; + case sys_clk1_4_clk: return clk_get_rate(sys_clk1_clk) / 4; + case sys_clk1_6_clk: return clk_get_rate(sys_clk1_clk) / 6; + case sys_clk1_12_clk: return clk_get_rate(sys_clk1_clk) / 12; + default: + break; + } + return 0; +} + +void init_pll(const struct pll_init_data *data) +{ + u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj; + + pllm = data->pll_m - 1; + plld = (data->pll_d - 1) & PLL_DIV_MASK; + pllod = (data->pll_od - 1) & PLL_CLKOD_MASK; + + if (data->pll == MAIN_PLL) { + /* The requered delay before main PLL configuration */ + sdelay(210000); + + tmp = pllctl_reg_read(data->pll, secctl); + + if (tmp & (PLLCTL_BYPASS)) { + setbits_le32(pll_regs[data->pll].reg1, + BIT(MAIN_ENSAT_OFFSET)); + + pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN | + PLLCTL_PLLENSRC); + sdelay(340); + + pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS); + pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN); + sdelay(21000); + + pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN); + } else { + pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN | + PLLCTL_PLLENSRC); + sdelay(340); + } + + pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); + + clrsetbits_le32(pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK, + (pllm << 6)); + + /* Set the BWADJ (12 bit field) */ + tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */ + clrsetbits_le32(pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK, + (tmp_ctl << PLL_BWADJ_LO_SHIFT)); + clrsetbits_le32(pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK, + (tmp_ctl >> 8)); + + /* + * Set the pll divider (6 bit field) * + * PLLD[5:0] is located in MAINPLLCTL0 + */ + clrsetbits_le32(pll_regs[data->pll].reg0, PLL_DIV_MASK, plld); + + /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */ + pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK, + (pllod << PLL_CLKOD_SHIFT)); + wait_for_completion(data); + + pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1); + pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2); + pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3); + pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4); + pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5); + + pllctl_reg_setbits(data->pll, alnctl, 0x1f); + + /* + * Set GOSET bit in PLLCMD to initiate the GO operation + * to change the divide + */ + pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO); + sdelay(1500); /* wait for the phase adj */ + wait_for_completion(data); + + /* Reset PLL */ + pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST); + sdelay(21000); /* Wait for a minimum of 7 us*/ + pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST); + sdelay(105000); /* Wait for PLL Lock time (min 50 us) */ + + pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS); + + tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN); + + } else if (data->pll == TETRIS_PLL) { + bwadj = pllm >> 1; + /* 1.5 Set PLLCTL0[BYPASS] =1 (enable bypass), */ + setbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS); + /* + * Set CHIPMISCCTL1[13] = 0 (enable glitchfree bypass) + * only applicable for Kepler + */ + clrbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN); + /* 2 In PLLCTL1, write PLLRST = 1 (PLL is reset) */ + setbits_le32(pll_regs[data->pll].reg1 , + PLL_PLLRST | PLLCTL_ENSAT); + + /* + * 3 Program PLLM and PLLD in PLLCTL0 register + * 4 Program BWADJ[7:0] in PLLCTL0 and BWADJ[11:8] in + * PLLCTL1 register. BWADJ value must be set + * to ((PLLM + 1) >> 1) – 1) + */ + tmp = ((bwadj & PLL_BWADJ_LO_MASK) << PLL_BWADJ_LO_SHIFT) | + (pllm << 6) | + (plld & PLL_DIV_MASK) | + (pllod << PLL_CLKOD_SHIFT) | PLLCTL_BYPASS; + __raw_writel(tmp, pll_regs[data->pll].reg0); + + /* Set BWADJ[11:8] bits */ + tmp = __raw_readl(pll_regs[data->pll].reg1); + tmp &= ~(PLL_BWADJ_HI_MASK); + tmp |= ((bwadj>>8) & PLL_BWADJ_HI_MASK); + __raw_writel(tmp, pll_regs[data->pll].reg1); + /* + * 5 Wait for at least 5 us based on the reference + * clock (PLL reset time) + */ + sdelay(21000); /* Wait for a minimum of 7 us*/ + + /* 6 In PLLCTL1, write PLLRST = 0 (PLL reset is released) */ + clrbits_le32(pll_regs[data->pll].reg1, PLL_PLLRST); + /* + * 7 Wait for at least 500 * REFCLK cycles * (PLLD + 1) + * (PLL lock time) + */ + sdelay(105000); + /* 8 disable bypass */ + clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS); + /* + * 9 Set CHIPMISCCTL1[13] = 1 (disable glitchfree bypass) + * only applicable for Kepler + */ + setbits_le32(K2HK_MISC_CTRL, ARM_PLL_EN); + } else { + setbits_le32(pll_regs[data->pll].reg1, PLLCTL_ENSAT); + /* + * process keeps state of Bypass bit while programming + * all other DDR PLL settings + */ + tmp = __raw_readl(pll_regs[data->pll].reg0); + tmp &= PLLCTL_BYPASS; /* clear everything except Bypass */ + + /* + * Set the BWADJ[7:0], PLLD[5:0] and PLLM to PLLCTL0, + * bypass disabled + */ + bwadj = pllm >> 1; + tmp |= ((bwadj & PLL_BWADJ_LO_SHIFT) << PLL_BWADJ_LO_SHIFT) | + (pllm << PLL_MULT_SHIFT) | + (plld & PLL_DIV_MASK) | + (pllod << PLL_CLKOD_SHIFT); + __raw_writel(tmp, pll_regs[data->pll].reg0); + + /* Set BWADJ[11:8] bits */ + tmp = __raw_readl(pll_regs[data->pll].reg1); + tmp &= ~(PLL_BWADJ_HI_MASK); + tmp |= ((bwadj >> 8) & PLL_BWADJ_HI_MASK); + + /* set PLL Select (bit 13) for PASS PLL */ + if (data->pll == PASS_PLL) + tmp |= PLLCTL_PAPLL; + + __raw_writel(tmp, pll_regs[data->pll].reg1); + + /* Reset bit: bit 14 for both DDR3 & PASS PLL */ + tmp = PLL_PLLRST; + /* Set RESET bit = 1 */ + setbits_le32(pll_regs[data->pll].reg1, tmp); + /* Wait for a minimum of 7 us*/ + sdelay(21000); + /* Clear RESET bit */ + clrbits_le32(pll_regs[data->pll].reg1, tmp); + sdelay(105000); + + /* clear BYPASS (Enable PLL Mode) */ + clrbits_le32(pll_regs[data->pll].reg0, PLLCTL_BYPASS); + sdelay(21000); /* Wait for a minimum of 7 us*/ + } + + /* + * This is required to provide a delay between multiple + * consequent PPL configurations + */ + sdelay(210000); +} + +void init_plls(int num_pll, struct pll_init_data *config) +{ + int i; + + for (i = 0; i < num_pll; i++) + init_pll(&config[i]); +} diff --git a/arch/arm/cpu/armv7/keystone/cmd_clock.c b/arch/arm/cpu/armv7/keystone/cmd_clock.c new file mode 100644 index 00000000000..afd30f38534 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/cmd_clock.c @@ -0,0 +1,124 @@ +/* + * keystone2: commands for clocks + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +struct pll_init_data cmd_pll_data = { + .pll = MAIN_PLL, + .pll_m = 16, + .pll_d = 1, + .pll_od = 2, +}; + +int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + if (argc != 5) + goto pll_cmd_usage; + + if (strncmp(argv[1], "pa", 2) == 0) + cmd_pll_data.pll = PASS_PLL; + else if (strncmp(argv[1], "arm", 3) == 0) + cmd_pll_data.pll = TETRIS_PLL; + else if (strncmp(argv[1], "ddr3a", 5) == 0) + cmd_pll_data.pll = DDR3A_PLL; + else if (strncmp(argv[1], "ddr3b", 5) == 0) + cmd_pll_data.pll = DDR3B_PLL; + else + goto pll_cmd_usage; + + cmd_pll_data.pll_m = simple_strtoul(argv[2], NULL, 10); + cmd_pll_data.pll_d = simple_strtoul(argv[3], NULL, 10); + cmd_pll_data.pll_od = simple_strtoul(argv[4], NULL, 10); + + printf("Trying to set pll %d; mult %d; div %d; OD %d\n", + cmd_pll_data.pll, cmd_pll_data.pll_m, + cmd_pll_data.pll_d, cmd_pll_data.pll_od); + init_pll(&cmd_pll_data); + + return 0; + +pll_cmd_usage: + return cmd_usage(cmdtp); +} + +U_BOOT_CMD( + pllset, 5, 0, do_pll_cmd, + "set pll multiplier and pre divider", + "
\n" +); + +int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + unsigned int clk; + unsigned int freq; + + if (argc != 2) + goto getclk_cmd_usage; + + clk = simple_strtoul(argv[1], NULL, 10); + + freq = clk_get_rate(clk); + printf("clock index [%d] - frequency %u\n", clk, freq); + return 0; + +getclk_cmd_usage: + return cmd_usage(cmdtp); +} + +U_BOOT_CMD( + getclk, 2, 0, do_getclk_cmd, + "get clock rate", + "\n" + "See the 'enum clk_e' in the k2hk clock.h for clk indexes\n" +); + +int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int psc_module; + int res; + + if (argc != 3) + goto psc_cmd_usage; + + psc_module = simple_strtoul(argv[1], NULL, 10); + if (strcmp(argv[2], "en") == 0) { + res = psc_enable_module(psc_module); + printf("psc_enable_module(%d) - %s\n", psc_module, + (res) ? "ERROR" : "OK"); + return 0; + } + + if (strcmp(argv[2], "di") == 0) { + res = psc_disable_module(psc_module); + printf("psc_disable_module(%d) - %s\n", psc_module, + (res) ? "ERROR" : "OK"); + return 0; + } + + if (strcmp(argv[2], "domain") == 0) { + res = psc_disable_domain(psc_module); + printf("psc_disable_domain(%d) - %s\n", psc_module, + (res) ? "ERROR" : "OK"); + return 0; + } + +psc_cmd_usage: + return cmd_usage(cmdtp); +} + +U_BOOT_CMD( + psc, 3, 0, do_psc_cmd, + "", + " \n" + "See the hardware.h for Power and Sleep Controller (PSC) Domains\n" +); diff --git a/arch/arm/cpu/armv7/keystone/cmd_mon.c b/arch/arm/cpu/armv7/keystone/cmd_mon.c new file mode 100644 index 00000000000..f9f58a37dfc --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/cmd_mon.c @@ -0,0 +1,131 @@ +/* + * K2HK: secure kernel command file + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +asm(".arch_extension sec\n\t"); + +static int mon_install(u32 addr, u32 dpsc, u32 freq) +{ + int result; + + __asm__ __volatile__ ( + "stmfd r13!, {lr}\n" + "mov r0, %1\n" + "mov r1, %2\n" + "mov r2, %3\n" + "blx r0\n" + "ldmfd r13!, {lr}\n" + : "=&r" (result) + : "r" (addr), "r" (dpsc), "r" (freq) + : "cc", "r0", "r1", "r2", "memory"); + return result; +} + +static int do_mon_install(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 addr, dpsc_base = 0x1E80000, freq; + int rcode = 0; + + if (argc < 2) + return CMD_RET_USAGE; + + freq = clk_get_rate(sys_clk0_6_clk); + + addr = simple_strtoul(argv[1], NULL, 16); + + rcode = mon_install(addr, dpsc_base, freq); + printf("## installed monitor, freq [%d], status %d\n", + freq, rcode); + + return 0; +} + +U_BOOT_CMD(mon_install, 2, 0, do_mon_install, + "Install boot kernel at 'addr'", + "" +); + +static void core_spin(void) +{ + while (1) + ; /* forever */; +} + +int mon_power_on(int core_id, void *ep) +{ + int result; + + asm volatile ( + "stmfd r13!, {lr}\n" + "mov r1, %1\n" + "mov r2, %2\n" + "mov r0, #0\n" + "smc #0\n" + "ldmfd r13!, {lr}\n" + : "=&r" (result) + : "r" (core_id), "r" (ep) + : "cc", "r0", "r1", "r2", "memory"); + return result; +} + +int mon_power_off(int core_id) +{ + int result; + + asm volatile ( + "stmfd r13!, {lr}\n" + "mov r1, %1\n" + "mov r0, #1\n" + "smc #1\n" + "ldmfd r13!, {lr}\n" + : "=&r" (result) + : "r" (core_id) + : "cc", "r0", "r1", "memory"); + return result; +} + +int do_mon_power(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + int rcode = 0, core_id, on; + void (*fn)(void); + + fn = core_spin; + + if (argc < 3) + return CMD_RET_USAGE; + + core_id = simple_strtoul(argv[1], NULL, 16); + on = simple_strtoul(argv[2], NULL, 16); + + if (on) + rcode = mon_power_on(core_id, fn); + else + rcode = mon_power_off(core_id); + + if (on) { + if (!rcode) + printf("core %d powered on successfully\n", core_id); + else + printf("core %d power on failure\n", core_id); + } else { + printf("core %d powered off successfully\n", core_id); + } + + return 0; +} + +U_BOOT_CMD(mon_power, 3, 0, do_mon_power, + "Power On/Off secondary core", + "mon_power \n" + "- coreid (1-3) and oper (1 - ON, 0 - OFF)\n" + "" +); diff --git a/arch/arm/cpu/armv7/keystone/ddr3.c b/arch/arm/cpu/armv7/keystone/ddr3.c new file mode 100644 index 00000000000..4875db76a35 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/ddr3.c @@ -0,0 +1,69 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg) +{ + unsigned int tmp; + + while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) + & 0x00000001) != 0x00000001) + ; + + __raw_writel(phy_cfg->pllcr, base + KS2_DDRPHY_PLLCR_OFFSET); + + tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); + tmp &= ~(phy_cfg->pgcr1_mask); + tmp |= phy_cfg->pgcr1_val; + __raw_writel(tmp, base + KS2_DDRPHY_PGCR1_OFFSET); + + __raw_writel(phy_cfg->ptr0, base + KS2_DDRPHY_PTR0_OFFSET); + __raw_writel(phy_cfg->ptr1, base + KS2_DDRPHY_PTR1_OFFSET); + __raw_writel(phy_cfg->ptr3, base + KS2_DDRPHY_PTR3_OFFSET); + __raw_writel(phy_cfg->ptr4, base + KS2_DDRPHY_PTR4_OFFSET); + + tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); + tmp &= ~(phy_cfg->dcr_mask); + tmp |= phy_cfg->dcr_val; + __raw_writel(tmp, base + KS2_DDRPHY_DCR_OFFSET); + + __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET); + __raw_writel(phy_cfg->dtpr1, base + KS2_DDRPHY_DTPR1_OFFSET); + __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); + __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET); + __raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET); + __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); + __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET); + __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET); + + __raw_writel(phy_cfg->zq0cr1, base + KS2_DDRPHY_ZQ0CR1_OFFSET); + __raw_writel(phy_cfg->zq1cr1, base + KS2_DDRPHY_ZQ1CR1_OFFSET); + __raw_writel(phy_cfg->zq2cr1, base + KS2_DDRPHY_ZQ2CR1_OFFSET); + + __raw_writel(phy_cfg->pir_v1, base + KS2_DDRPHY_PIR_OFFSET); + while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) + ; + + __raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET); + while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) + ; +} + +void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg) +{ + __raw_writel(emif_cfg->sdcfg, base + KS2_DDR3_SDCFG_OFFSET); + __raw_writel(emif_cfg->sdtim1, base + KS2_DDR3_SDTIM1_OFFSET); + __raw_writel(emif_cfg->sdtim2, base + KS2_DDR3_SDTIM2_OFFSET); + __raw_writel(emif_cfg->sdtim3, base + KS2_DDR3_SDTIM3_OFFSET); + __raw_writel(emif_cfg->sdtim4, base + KS2_DDR3_SDTIM4_OFFSET); + __raw_writel(emif_cfg->zqcfg, base + KS2_DDR3_ZQCFG_OFFSET); + __raw_writel(emif_cfg->sdrfc, base + KS2_DDR3_SDRFC_OFFSET); +} diff --git a/arch/arm/cpu/armv7/keystone/init.c b/arch/arm/cpu/armv7/keystone/init.c new file mode 100644 index 00000000000..044015aed64 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/init.c @@ -0,0 +1,56 @@ +/* + * Keystone2: Architecture initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void chip_configuration_unlock(void) +{ + __raw_writel(KEYSTONE_KICK0_MAGIC, KEYSTONE_KICK0); + __raw_writel(KEYSTONE_KICK1_MAGIC, KEYSTONE_KICK1); +} + +int arch_cpu_init(void) +{ + chip_configuration_unlock(); + icache_enable(); + +#ifdef CONFIG_SOC_K2HK + share_all_segments(8); + share_all_segments(9); + share_all_segments(10); /* QM PDSP */ + share_all_segments(11); /* PCIE */ +#endif + + return 0; +} + +void reset_cpu(ulong addr) +{ + volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL); + u32 tmp; + + tmp = *rstctrl & KS2_RSTCTRL_MASK; + *rstctrl = tmp | KS2_RSTCTRL_KEY; + + *rstctrl &= KS2_RSTCTRL_SWRST; + + for (;;) + ; +} + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +#endif +} diff --git a/arch/arm/cpu/armv7/keystone/msmc.c b/arch/arm/cpu/armv7/keystone/msmc.c new file mode 100644 index 00000000000..f3f1621d205 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/msmc.c @@ -0,0 +1,68 @@ +/* + * MSMC controller utilities + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct mpax { + u32 mpaxl; + u32 mpaxh; +}; + +struct msms_regs { + u32 pid; + u32 _res_04; + u32 smcerrar; + u32 smcerrxr; + u32 smedcc; + u32 smcea; + u32 smsecc; + u32 smpfar; + u32 smpfxr; + u32 smpfr; + u32 smpfcr; + u32 _res_2c; + u32 sbndc[8]; + u32 sbndm; + u32 sbnde; + u32 _res_58; + u32 cfglck; + u32 cfgulck; + u32 cfglckstat; + u32 sms_mpax_lck; + u32 sms_mpax_ulck; + u32 sms_mpax_lckstat; + u32 ses_mpax_lck; + u32 ses_mpax_ulck; + u32 ses_mpax_lckstat; + u32 smestat; + u32 smirstat; + u32 smirc; + u32 smiestat; + u32 smiec; + u32 _res_94_c0[12]; + u32 smncerrar; + u32 smncerrxr; + u32 smncea; + u32 _res_d0_1fc[76]; + struct mpax sms[16][8]; + struct mpax ses[16][8]; +}; + + +void share_all_segments(int priv_id) +{ + struct msms_regs *msmc = (struct msms_regs *)K2HK_MSMC_CTRL_BASE; + int j; + + for (j = 0; j < 8; j++) { + msmc->sms[priv_id][j].mpaxh &= 0xffffff7ful; + msmc->ses[priv_id][j].mpaxh &= 0xffffff7ful; + } +} diff --git a/arch/arm/cpu/armv7/keystone/psc.c b/arch/arm/cpu/armv7/keystone/psc.c new file mode 100644 index 00000000000..c844dc84d50 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/psc.c @@ -0,0 +1,237 @@ +/* + * Keystone: PSC configuration module + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define DEVICE_REG32_R(addr) __raw_readl((u32 *)(addr)) +#define DEVICE_REG32_W(addr, val) __raw_writel(val, (u32 *)(addr)) + +#ifdef CONFIG_SOC_K2HK +#define DEVICE_PSC_BASE K2HK_PSC_BASE +#endif + +int psc_delay(void) +{ + udelay(10); + return 10; +} + +/* + * FUNCTION PURPOSE: Wait for end of transitional state + * + * DESCRIPTION: Polls pstat for the selected domain and waits for transitions + * to be complete. + * + * Since this is boot loader code it is *ASSUMED* that interrupts + * are disabled and no other core is mucking around with the psc + * at the same time. + * + * Returns 0 when the domain is free. Returns -1 if a timeout + * occurred waiting for the completion. + */ +int psc_wait(u32 domain_num) +{ + u32 retry; + u32 ptstat; + + /* + * Do nothing if the power domain is in transition. This should never + * happen since the boot code is the only software accesses psc. + * It's still remotely possible that the hardware state machines + * initiate transitions. + * Don't trap if the domain (or a module in this domain) is + * stuck in transition. + */ + retry = 0; + + do { + ptstat = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PSTAT); + ptstat = ptstat & (1 << domain_num); + } while ((ptstat != 0) && ((retry += psc_delay()) < + PSC_PTSTAT_TIMEOUT_LIMIT)); + + if (retry >= PSC_PTSTAT_TIMEOUT_LIMIT) + return -1; + + return 0; +} + +u32 psc_get_domain_num(u32 mod_num) +{ + u32 domain_num; + + /* Get the power domain associated with the module number */ + domain_num = DEVICE_REG32_R(DEVICE_PSC_BASE + + PSC_REG_MDCFG(mod_num)); + domain_num = PSC_REG_MDCFG_GET_PD(domain_num); + + return domain_num; +} + +/* + * FUNCTION PURPOSE: Power up/down a module + * + * DESCRIPTION: Powers up/down the requested module and the associated power + * domain if required. No action is taken it the module is + * already powered up/down. + * + * This only controls modules. The domain in which the module + * resides will be left in the power on state. Multiple modules + * can exist in a power domain, so powering down the domain based + * on a single module is not done. + * + * Returns 0 on success, -1 if the module can't be powered up, or + * if there is a timeout waiting for the transition. + */ +int psc_set_state(u32 mod_num, u32 state) +{ + u32 domain_num; + u32 pdctl; + u32 mdctl; + u32 ptcmd; + u32 reset_iso; + u32 v; + + /* + * Get the power domain associated with the module number, and reset + * isolation functionality + */ + v = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCFG(mod_num)); + domain_num = PSC_REG_MDCFG_GET_PD(v); + reset_iso = PSC_REG_MDCFG_GET_RESET_ISO(v); + + /* Wait for the status of the domain/module to be non-transitional */ + if (psc_wait(domain_num) != 0) + return -1; + + /* + * Perform configuration even if the current status matches the + * existing state + * + * Set the next state of the power domain to on. It's OK if the domain + * is always on. This code will not ever power down a domain, so no + * change is made if the new state is power down. + */ + if (state == PSC_REG_VAL_MDCTL_NEXT_ON) { + pdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + + PSC_REG_PDCTL(domain_num)); + pdctl = PSC_REG_PDCTL_SET_NEXT(pdctl, + PSC_REG_VAL_PDCTL_NEXT_ON); + DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_PDCTL(domain_num), + pdctl); + } + + /* Set the next state for the module to enabled/disabled */ + mdctl = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num)); + mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state); + mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, reset_iso); + DEVICE_REG32_W(DEVICE_PSC_BASE + PSC_REG_MDCTL(mod_num), mdctl); + + /* Trigger the enable */ + ptcmd = DEVICE_REG32_R(DEVICE_PSC_BASE + PSC_REG_PTCMD); + ptcmd |= (u32)(1< + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include +#include + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static struct pll_init_data spl_pll_config[] = { + CORE_PLL_799, + TETRIS_PLL_500, +}; + +void spl_init_keystone_plls(void) +{ + init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config); +} + +void spl_board_init(void) +{ + spl_init_keystone_plls(); + preloader_console_init(); +} + +u32 spl_boot_device(void) +{ +#if defined(CONFIG_SPL_SPI_LOAD) + return BOOT_DEVICE_SPI; +#else + puts("Unknown boot device\n"); + hang(); +#endif +} diff --git a/arch/arm/include/asm/arch-keystone/clock-k2hk.h b/arch/arm/include/asm/arch-keystone/clock-k2hk.h new file mode 100644 index 00000000000..6a69a8d2bed --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/clock-k2hk.h @@ -0,0 +1,109 @@ +/* + * K2HK: Clock management APIs + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_K2HK_H +#define __ASM_ARCH_CLOCK_K2HK_H + +#include + +#ifndef __ASSEMBLY__ + +enum ext_clk_e { + sys_clk, + alt_core_clk, + pa_clk, + tetris_clk, + ddr3a_clk, + ddr3b_clk, + mcm_clk, + pcie_clk, + sgmii_srio_clk, + xgmii_clk, + usb_clk, + rp1_clk, + ext_clk_count /* number of external clocks */ +}; + +extern unsigned int external_clk[ext_clk_count]; + +enum clk_e { + core_pll_clk, + pass_pll_clk, + tetris_pll_clk, + ddr3a_pll_clk, + ddr3b_pll_clk, + sys_clk0_clk, + sys_clk0_1_clk, + sys_clk0_2_clk, + sys_clk0_3_clk, + sys_clk0_4_clk, + sys_clk0_6_clk, + sys_clk0_8_clk, + sys_clk0_12_clk, + sys_clk0_24_clk, + sys_clk1_clk, + sys_clk1_3_clk, + sys_clk1_4_clk, + sys_clk1_6_clk, + sys_clk1_12_clk, + sys_clk2_clk, + sys_clk3_clk +}; + +#define K2HK_CLK1_6 sys_clk0_6_clk + +/* PLL identifiers */ +enum pll_type_e { + CORE_PLL, + PASS_PLL, + TETRIS_PLL, + DDR3A_PLL, + DDR3B_PLL, +}; +#define MAIN_PLL CORE_PLL + +/* PLL configuration data */ +struct pll_init_data { + int pll; + int pll_m; /* PLL Multiplier */ + int pll_d; /* PLL divider */ + int pll_od; /* PLL output divider */ +}; + +#define CORE_PLL_799 {CORE_PLL, 13, 1, 2} +#define CORE_PLL_983 {CORE_PLL, 16, 1, 2} +#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2} +#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2} +#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2} +#define PASS_PLL_983 {PASS_PLL, 16, 1, 2} +#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2} +#define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2} +#define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2} +#define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2} +#define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2} +#define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2} +#define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2} +#define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1} +#define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1} +#define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1} +#define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1} +#define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2} +#define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4} +#define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2} +#define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6} + +void init_plls(int num_pll, struct pll_init_data *config); +void init_pll(const struct pll_init_data *data); +unsigned long clk_get_rate(unsigned int clk); +unsigned long clk_round_rate(unsigned int clk, unsigned long hz); +int clk_set_rate(unsigned int clk, unsigned long hz); + +#endif + +#endif diff --git a/arch/arm/include/asm/arch-keystone/clock.h b/arch/arm/include/asm/arch-keystone/clock.h new file mode 100644 index 00000000000..324501b75ae --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/clock.h @@ -0,0 +1,17 @@ +/* + * keystone2: common clock header file + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +#ifdef CONFIG_SOC_K2HK +#include +#endif + +#endif diff --git a/arch/arm/include/asm/arch-keystone/clock_defs.h b/arch/arm/include/asm/arch-keystone/clock_defs.h new file mode 100644 index 00000000000..b251aff3832 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/clock_defs.h @@ -0,0 +1,111 @@ +/* + * keystone2: common pll clock definitions + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CLOCK_DEFS_H_ +#define _CLOCK_DEFS_H_ + +#include + +#define BIT(x) (1 << (x)) + +/* PLL Control Registers */ +struct pllctl_regs { + u32 ctl; /* 00 */ + u32 ocsel; /* 04 */ + u32 secctl; /* 08 */ + u32 resv0; + u32 mult; /* 10 */ + u32 prediv; /* 14 */ + u32 div1; /* 18 */ + u32 div2; /* 1c */ + u32 div3; /* 20 */ + u32 oscdiv1; /* 24 */ + u32 resv1; /* 28 */ + u32 bpdiv; /* 2c */ + u32 wakeup; /* 30 */ + u32 resv2; + u32 cmd; /* 38 */ + u32 stat; /* 3c */ + u32 alnctl; /* 40 */ + u32 dchange; /* 44 */ + u32 cken; /* 48 */ + u32 ckstat; /* 4c */ + u32 systat; /* 50 */ + u32 ckctl; /* 54 */ + u32 resv3[2]; + u32 div4; /* 60 */ + u32 div5; /* 64 */ + u32 div6; /* 68 */ + u32 div7; /* 6c */ + u32 div8; /* 70 */ + u32 div9; /* 74 */ + u32 div10; /* 78 */ + u32 div11; /* 7c */ + u32 div12; /* 80 */ +}; + +static struct pllctl_regs *pllctl_regs[] = { + (struct pllctl_regs *)(CLOCK_BASE + 0x100) +}; + +#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) +#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) +#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) + +#define pllctl_reg_rmw(pll, reg, mask, val) \ + pllctl_reg_write(pll, reg, \ + (pllctl_reg_read(pll, reg) & ~(mask)) | val) + +#define pllctl_reg_setbits(pll, reg, mask) \ + pllctl_reg_rmw(pll, reg, 0, mask) + +#define pllctl_reg_clrbits(pll, reg, mask) \ + pllctl_reg_rmw(pll, reg, mask, 0) + +#define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1) + +/* PLLCTL Bits */ +#define PLLCTL_BYPASS BIT(23) +#define PLL_PLLRST BIT(14) +#define PLLCTL_PAPLL BIT(13) +#define PLLCTL_CLKMODE BIT(8) +#define PLLCTL_PLLSELB BIT(7) +#define PLLCTL_ENSAT BIT(6) +#define PLLCTL_PLLENSRC BIT(5) +#define PLLCTL_PLLDIS BIT(4) +#define PLLCTL_PLLRST BIT(3) +#define PLLCTL_PLLPWRDN BIT(1) +#define PLLCTL_PLLEN BIT(0) +#define PLLSTAT_GO BIT(0) + +#define MAIN_ENSAT_OFFSET 6 + +#define PLLDIV_ENABLE BIT(15) + +#define PLL_DIV_MASK 0x3f +#define PLL_MULT_MASK 0x1fff +#define PLL_MULT_SHIFT 6 +#define PLLM_MULT_HI_MASK 0x7f +#define PLLM_MULT_HI_SHIFT 12 +#define PLLM_MULT_HI_SMASK (PLLM_MULT_HI_MASK << PLLM_MULT_HI_SHIFT) +#define PLLM_MULT_LO_MASK 0x3f +#define PLL_CLKOD_MASK 0xf +#define PLL_CLKOD_SHIFT 19 +#define PLL_CLKOD_SMASK (PLL_CLKOD_MASK << PLL_CLKOD_SHIFT) +#define PLL_BWADJ_LO_MASK 0xff +#define PLL_BWADJ_LO_SHIFT 24 +#define PLL_BWADJ_LO_SMASK (PLL_BWADJ_LO_MASK << PLL_BWADJ_LO_SHIFT) +#define PLL_BWADJ_HI_MASK 0xf + +#define PLLM_RATIO_DIV1 (PLLDIV_ENABLE | 0) +#define PLLM_RATIO_DIV2 (PLLDIV_ENABLE | 0) +#define PLLM_RATIO_DIV3 (PLLDIV_ENABLE | 1) +#define PLLM_RATIO_DIV4 (PLLDIV_ENABLE | 4) +#define PLLM_RATIO_DIV5 (PLLDIV_ENABLE | 17) + +#endif /* _CLOCK_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-keystone/emif_defs.h b/arch/arm/include/asm/arch-keystone/emif_defs.h new file mode 100644 index 00000000000..a3378aa30e8 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/emif_defs.h @@ -0,0 +1,73 @@ +/* + * emif definitions to re-use davinci emif driver on Keystone2 + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * (C) Copyright 2007 Sergey Kubushyn + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _EMIF_DEFS_H_ +#define _EMIF_DEFS_H_ + +#include + +struct davinci_emif_regs { + uint32_t ercsr; + uint32_t awccr; + uint32_t sdbcr; + uint32_t sdrcr; + uint32_t abncr[4]; + uint32_t sdtimr; + uint32_t ddrsr; + uint32_t ddrphycr; + uint32_t ddrphysr; + uint32_t totar; + uint32_t totactr; + uint32_t ddrphyid_rev; + uint32_t sdsretr; + uint32_t eirr; + uint32_t eimr; + uint32_t eimsr; + uint32_t eimcr; + uint32_t ioctrlr; + uint32_t iostatr; + uint32_t rsvd0; + uint32_t one_nand_cr; + uint32_t nandfcr; + uint32_t nandfsr; + uint32_t rsvd1[2]; + uint32_t nandfecc[4]; + uint32_t rsvd2[15]; + uint32_t nand4biteccload; + uint32_t nand4bitecc[4]; + uint32_t nanderradd1; + uint32_t nanderradd2; + uint32_t nanderrval1; + uint32_t nanderrval2; +}; + +#define davinci_emif_regs \ + ((struct davinci_emif_regs *)DAVINCI_ASYNC_EMIF_CNTRL_BASE) + +#define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2)) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK (3 << 4) +#define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) +#define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) +#define DAVINCI_NANDFCR_4BIT_ECC_START (1 << 12) +#define DAVINCI_NANDFCR_4BIT_CALC_START (1 << 13) + +/* Chip Select setup */ +#define DAVINCI_ABCR_STROBE_SELECT (1 << 31) +#define DAVINCI_ABCR_EXT_WAIT (1 << 30) +#define DAVINCI_ABCR_WSETUP(n) ((n) << 26) +#define DAVINCI_ABCR_WSTROBE(n) ((n) << 20) +#define DAVINCI_ABCR_WHOLD(n) ((n) << 17) +#define DAVINCI_ABCR_RSETUP(n) ((n) << 13) +#define DAVINCI_ABCR_RSTROBE(n) ((n) << 7) +#define DAVINCI_ABCR_RHOLD(n) ((n) << 4) +#define DAVINCI_ABCR_TA(n) ((n) << 2) +#define DAVINCI_ABCR_ASIZE_16BIT 1 +#define DAVINCI_ABCR_ASIZE_8BIT 0 + +#endif diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h new file mode 100644 index 00000000000..50ff13a3b20 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -0,0 +1,150 @@ +/* + * K2HK: SoC definitions + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_ARCH_HARDWARE_K2HK_H +#define __ASM_ARCH_HARDWARE_K2HK_H + +#define K2HK_ASYNC_EMIF_CNTRL_BASE 0x21000a00 +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE K2HK_ASYNC_EMIF_CNTRL_BASE +#define K2HK_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 +#define K2HK_ASYNC_EMIF_DATA_CE1_BASE 0x34000000 +#define K2HK_ASYNC_EMIF_DATA_CE2_BASE 0x38000000 +#define K2HK_ASYNC_EMIF_DATA_CE3_BASE 0x3c000000 + +#define K2HK_PLL_CNTRL_BASE 0x02310000 +#define CLOCK_BASE K2HK_PLL_CNTRL_BASE +#define KS2_RSTCTRL (K2HK_PLL_CNTRL_BASE + 0xe8) +#define KS2_RSTCTRL_KEY 0x5a69 +#define KS2_RSTCTRL_MASK 0xffff0000 +#define KS2_RSTCTRL_SWRST 0xfffe0000 + +#define K2HK_PSC_BASE 0x02350000 +#define KS2_DEVICE_STATE_CTRL_BASE 0x02620000 +#define JTAG_ID_REG (KS2_DEVICE_STATE_CTRL_BASE + 0x18) +#define K2HK_DEVSTAT (KS2_DEVICE_STATE_CTRL_BASE + 0x20) + +#define K2HK_MISC_CTRL (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c) + +#define ARM_PLL_EN BIT(13) + +#define K2HK_SPI0_BASE 0x21000400 +#define K2HK_SPI1_BASE 0x21000600 +#define K2HK_SPI2_BASE 0x21000800 +#define K2HK_SPI_BASE K2HK_SPI0_BASE + +/* Chip configuration unlock codes and registers */ +#define KEYSTONE_KICK0 (KS2_DEVICE_STATE_CTRL_BASE + 0x38) +#define KEYSTONE_KICK1 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c) +#define KEYSTONE_KICK0_MAGIC 0x83e70b13 +#define KEYSTONE_KICK1_MAGIC 0x95a4f1e0 + +/* PA SS Registers */ +#define KS2_PASS_BASE 0x02000000 + +/* PLL control registers */ +#define K2HK_MAINPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x350) +#define K2HK_MAINPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x354) +#define K2HK_PASSPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x358) +#define K2HK_PASSPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C) +#define K2HK_DDR3APLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x360) +#define K2HK_DDR3APLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x364) +#define K2HK_DDR3BPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x368) +#define K2HK_DDR3BPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x36C) +#define K2HK_ARMPLLCTL0 (KS2_DEVICE_STATE_CTRL_BASE + 0x370) +#define K2HK_ARMPLLCTL1 (KS2_DEVICE_STATE_CTRL_BASE + 0x374) + +/* Power and Sleep Controller (PSC) Domains */ +#define K2HK_LPSC_MOD 0 +#define K2HK_LPSC_DUMMY1 1 +#define K2HK_LPSC_USB 2 +#define K2HK_LPSC_EMIF25_SPI 3 +#define K2HK_LPSC_TSIP 4 +#define K2HK_LPSC_DEBUGSS_TRC 5 +#define K2HK_LPSC_TETB_TRC 6 +#define K2HK_LPSC_PKTPROC 7 +#define KS2_LPSC_PA K2HK_LPSC_PKTPROC +#define K2HK_LPSC_SGMII 8 +#define KS2_LPSC_CPGMAC K2HK_LPSC_SGMII +#define K2HK_LPSC_CRYPTO 9 +#define K2HK_LPSC_PCIE 10 +#define K2HK_LPSC_SRIO 11 +#define K2HK_LPSC_VUSR0 12 +#define K2HK_LPSC_CHIP_SRSS 13 +#define K2HK_LPSC_MSMC 14 +#define K2HK_LPSC_GEM_0 15 +#define K2HK_LPSC_GEM_1 16 +#define K2HK_LPSC_GEM_2 17 +#define K2HK_LPSC_GEM_3 18 +#define K2HK_LPSC_GEM_4 19 +#define K2HK_LPSC_GEM_5 20 +#define K2HK_LPSC_GEM_6 21 +#define K2HK_LPSC_GEM_7 22 +#define K2HK_LPSC_EMIF4F_DDR3A 23 +#define K2HK_LPSC_EMIF4F_DDR3B 24 +#define K2HK_LPSC_TAC 25 +#define K2HK_LPSC_RAC 26 +#define K2HK_LPSC_RAC_1 27 +#define K2HK_LPSC_FFTC_A 28 +#define K2HK_LPSC_FFTC_B 29 +#define K2HK_LPSC_FFTC_C 30 +#define K2HK_LPSC_FFTC_D 31 +#define K2HK_LPSC_FFTC_E 32 +#define K2HK_LPSC_FFTC_F 33 +#define K2HK_LPSC_AI2 34 +#define K2HK_LPSC_TCP3D_0 35 +#define K2HK_LPSC_TCP3D_1 36 +#define K2HK_LPSC_TCP3D_2 37 +#define K2HK_LPSC_TCP3D_3 38 +#define K2HK_LPSC_VCP2X4_A 39 +#define K2HK_LPSC_CP2X4_B 40 +#define K2HK_LPSC_VCP2X4_C 41 +#define K2HK_LPSC_VCP2X4_D 42 +#define K2HK_LPSC_VCP2X4_E 43 +#define K2HK_LPSC_VCP2X4_F 44 +#define K2HK_LPSC_VCP2X4_G 45 +#define K2HK_LPSC_VCP2X4_H 46 +#define K2HK_LPSC_BCP 47 +#define K2HK_LPSC_DXB 48 +#define K2HK_LPSC_VUSR1 49 +#define K2HK_LPSC_XGE 50 +#define K2HK_LPSC_ARM_SREFLEX 51 +#define K2HK_LPSC_TETRIS 52 + +#define K2HK_UART0_BASE 0x02530c00 + +/* DDR3A definitions */ +#define K2HK_DDR3A_EMIF_CTRL_BASE 0x21010000 +#define K2HK_DDR3A_EMIF_DATA_BASE 0x80000000 +#define K2HK_DDR3A_DDRPHYC 0x02329000 +/* DDR3B definitions */ +#define K2HK_DDR3B_EMIF_CTRL_BASE 0x21020000 +#define K2HK_DDR3B_EMIF_DATA_BASE 0x60000000 +#define K2HK_DDR3B_DDRPHYC 0x02328000 + +/* Queue manager */ +#define DEVICE_QM_MANAGER_BASE 0x02a02000 +#define DEVICE_QM_DESC_SETUP_BASE 0x02a03000 +#define DEVICE_QM_MANAGER_QUEUES_BASE 0x02a80000 +#define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000 +#define DEVICE_QM_QUEUE_STATUS_BASE 0x02a40000 +#define DEVICE_QM_NUM_LINKRAMS 2 +#define DEVICE_QM_NUM_MEMREGIONS 20 + +#define DEVICE_PA_CDMA_GLOBAL_CFG_BASE 0x02004000 +#define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400 +#define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800 +#define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000 + +#define DEVICE_PA_CDMA_RX_NUM_CHANNELS 24 +#define DEVICE_PA_CDMA_RX_NUM_FLOWS 32 +#define DEVICE_PA_CDMA_TX_NUM_CHANNELS 9 + +/* MSMC control */ +#define K2HK_MSMC_CTRL_BASE 0x0bc00000 + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h new file mode 100644 index 00000000000..a305a0cc098 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -0,0 +1,175 @@ +/* + * Keystone2: Common SoC definitions, structures etc. + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +#include + +#ifndef __ASSEMBLY__ + +#include +#include + +#define REG(addr) (*(volatile unsigned int *)(addr)) +#define REG_P(addr) ((volatile unsigned int *)(addr)) + +typedef volatile unsigned int dv_reg; +typedef volatile unsigned int *dv_reg_p; + +#define ASYNC_EMIF_NUM_CS 4 +#define ASYNC_EMIF_MODE_NOR 0 +#define ASYNC_EMIF_MODE_NAND 1 +#define ASYNC_EMIF_MODE_ONENAND 2 +#define ASYNC_EMIF_PRESERVE -1 + +struct async_emif_config { + unsigned mode; + unsigned select_strobe; + unsigned extend_wait; + unsigned wr_setup; + unsigned wr_strobe; + unsigned wr_hold; + unsigned rd_setup; + unsigned rd_strobe; + unsigned rd_hold; + unsigned turn_around; + enum { + ASYNC_EMIF_8 = 0, + ASYNC_EMIF_16 = 1, + ASYNC_EMIF_32 = 2, + } width; +}; + +void init_async_emif(int num_cs, struct async_emif_config *config); + +struct ddr3_phy_config { + unsigned int pllcr; + unsigned int pgcr1_mask; + unsigned int pgcr1_val; + unsigned int ptr0; + unsigned int ptr1; + unsigned int ptr2; + unsigned int ptr3; + unsigned int ptr4; + unsigned int dcr_mask; + unsigned int dcr_val; + unsigned int dtpr0; + unsigned int dtpr1; + unsigned int dtpr2; + unsigned int mr0; + unsigned int mr1; + unsigned int mr2; + unsigned int dtcr; + unsigned int pgcr2; + unsigned int zq0cr1; + unsigned int zq1cr1; + unsigned int zq2cr1; + unsigned int pir_v1; + unsigned int pir_v2; +}; + +struct ddr3_emif_config { + unsigned int sdcfg; + unsigned int sdtim1; + unsigned int sdtim2; + unsigned int sdtim3; + unsigned int sdtim4; + unsigned int zqcfg; + unsigned int sdrfc; +}; + +#endif + +#define BIT(x) (1 << (x)) + +#define KS2_DDRPHY_PIR_OFFSET 0x04 +#define KS2_DDRPHY_PGCR0_OFFSET 0x08 +#define KS2_DDRPHY_PGCR1_OFFSET 0x0C +#define KS2_DDRPHY_PGSR0_OFFSET 0x10 +#define KS2_DDRPHY_PGSR1_OFFSET 0x14 +#define KS2_DDRPHY_PLLCR_OFFSET 0x18 +#define KS2_DDRPHY_PTR0_OFFSET 0x1C +#define KS2_DDRPHY_PTR1_OFFSET 0x20 +#define KS2_DDRPHY_PTR2_OFFSET 0x24 +#define KS2_DDRPHY_PTR3_OFFSET 0x28 +#define KS2_DDRPHY_PTR4_OFFSET 0x2C +#define KS2_DDRPHY_DCR_OFFSET 0x44 + +#define KS2_DDRPHY_DTPR0_OFFSET 0x48 +#define KS2_DDRPHY_DTPR1_OFFSET 0x4C +#define KS2_DDRPHY_DTPR2_OFFSET 0x50 + +#define KS2_DDRPHY_MR0_OFFSET 0x54 +#define KS2_DDRPHY_MR1_OFFSET 0x58 +#define KS2_DDRPHY_MR2_OFFSET 0x5C +#define KS2_DDRPHY_DTCR_OFFSET 0x68 +#define KS2_DDRPHY_PGCR2_OFFSET 0x8C + +#define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184 +#define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194 +#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4 +#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4 + +#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0 + +#define IODDRM_MASK 0x00000180 +#define ZCKSEL_MASK 0x01800000 +#define CL_MASK 0x00000072 +#define WR_MASK 0x00000E00 +#define BL_MASK 0x00000003 +#define RRMODE_MASK 0x00040000 +#define UDIMM_MASK 0x20000000 +#define BYTEMASK_MASK 0x0003FC00 +#define MPRDQ_MASK 0x00000080 +#define PDQ_MASK 0x00000070 +#define NOSRA_MASK 0x08000000 +#define ECC_MASK 0x00000001 + +#define KS2_DDR3_MIDR_OFFSET 0x00 +#define KS2_DDR3_STATUS_OFFSET 0x04 +#define KS2_DDR3_SDCFG_OFFSET 0x08 +#define KS2_DDR3_SDRFC_OFFSET 0x10 +#define KS2_DDR3_SDTIM1_OFFSET 0x18 +#define KS2_DDR3_SDTIM2_OFFSET 0x1C +#define KS2_DDR3_SDTIM3_OFFSET 0x20 +#define KS2_DDR3_SDTIM4_OFFSET 0x28 +#define KS2_DDR3_PMCTL_OFFSET 0x38 +#define KS2_DDR3_ZQCFG_OFFSET 0xC8 + +#ifdef CONFIG_SOC_K2HK +#include +#endif + +#ifndef __ASSEMBLY__ +static inline int cpu_is_k2hk(void) +{ + unsigned int jtag_id = __raw_readl(JTAG_ID_REG); + unsigned int part_no = (jtag_id >> 12) & 0xffff; + + return (part_no == 0xb981) ? 1 : 0; +} + +static inline int cpu_revision(void) +{ + unsigned int jtag_id = __raw_readl(JTAG_ID_REG); + unsigned int rev = (jtag_id >> 28) & 0xf; + + return rev; +} + +void share_all_segments(int priv_id); +int cpu_to_bus(u32 *ptr, u32 length); +void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); +void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); +void init_ddr3(void); +void sdelay(unsigned long); + +#endif + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-keystone/i2c_defs.h b/arch/arm/include/asm/arch-keystone/i2c_defs.h new file mode 100644 index 00000000000..d4256526cc7 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/i2c_defs.h @@ -0,0 +1,17 @@ +/* + * keystone: i2c driver definitions + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _I2C_DEFS_H_ +#define _I2C_DEFS_H_ + +#define I2C0_BASE 0x02530000 +#define I2C1_BASE 0x02530400 +#define I2C2_BASE 0x02530800 +#define I2C_BASE I2C0_BASE + +#endif diff --git a/arch/arm/include/asm/arch-keystone/nand_defs.h b/arch/arm/include/asm/arch-keystone/nand_defs.h new file mode 100644 index 00000000000..58417dbc0b5 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/nand_defs.h @@ -0,0 +1,23 @@ +/* + * nand driver definitions to re-use davinci nand driver on Keystone2 + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * (C) Copyright 2007 Sergey Kubushyn + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _NAND_DEFS_H_ +#define _NAND_DEFS_H_ + +#include +#include + +#define MASK_CLE 0x4000 +#define MASK_ALE 0x2000 + +#define NAND_READ_START 0x00 +#define NAND_READ_END 0x30 +#define NAND_STATUS 0x70 + +#endif diff --git a/arch/arm/include/asm/arch-keystone/psc_defs.h b/arch/arm/include/asm/arch-keystone/psc_defs.h new file mode 100644 index 00000000000..70d22cf2178 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/psc_defs.h @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _PSC_DEFS_H_ +#define _PSC_DEFS_H_ + +#include + +/* + * FILE PURPOSE: Local Power Sleep Controller definitions + * + * FILE NAME: psc_defs.h + * + * DESCRIPTION: Provides local definitions for the power saver controller + * + */ + +/* Register offsets */ +#define PSC_REG_PTCMD 0x120 +#define PSC_REG_PSTAT 0x128 +#define PSC_REG_PDSTAT(x) (0x200 + (4 * (x))) +#define PSC_REG_PDCTL(x) (0x300 + (4 * (x))) +#define PSC_REG_MDCFG(x) (0x600 + (4 * (x))) +#define PSC_REG_MDSTAT(x) (0x800 + (4 * (x))) +#define PSC_REG_MDCTL(x) (0xa00 + (4 * (x))) + +#define BOOTBITMASK(x, y) ((((((u32)1 << (((u32)x) - ((u32)y) + (u32)1)) - \ + (u32)1)) << ((u32)y))) + +#define BOOT_READ_BITFIELD(z, x, y) (((u32)z) & BOOTBITMASK(x, y)) >> (y) +#define BOOT_SET_BITFIELD(z, f, x, y) (((u32)z) & ~BOOTBITMASK(x, y)) | \ + ((((u32)f) << (y)) & BOOTBITMASK(x, y)) + +/* PDCTL */ +#define PSC_REG_PDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 0, 0) +#define PSC_REG_PDCTL_SET_PDMODE(x, y) BOOT_SET_BITFIELD((x), (y), 15, 12) + +/* PDSTAT */ +#define PSC_REG_PDSTAT_GET_STATE(x) BOOT_READ_BITFIELD((x), 4, 0) + +/* MDCFG */ +#define PSC_REG_MDCFG_GET_PD(x) BOOT_READ_BITFIELD((x), 20, 16) +#define PSC_REG_MDCFG_GET_RESET_ISO(x) BOOT_READ_BITFIELD((x), 14, 14) + +/* MDCTL */ +#define PSC_REG_MDCTL_SET_NEXT(x, y) BOOT_SET_BITFIELD((x), (y), 4, 0) +#define PSC_REG_MDCTL_SET_LRSTZ(x, y) BOOT_SET_BITFIELD((x), (y), 8, 8) +#define PSC_REG_MDCTL_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8) +#define PSC_REG_MDCTL_SET_RESET_ISO(x, y) BOOT_SET_BITFIELD((x), (y), \ + 12, 12) + +/* MDSTAT */ +#define PSC_REG_MDSTAT_GET_STATUS(x) BOOT_READ_BITFIELD((x), 5, 0) +#define PSC_REG_MDSTAT_GET_LRSTZ(x) BOOT_READ_BITFIELD((x), 8, 8) +#define PSC_REG_MDSTAT_GET_LRSTDONE(x) BOOT_READ_BITFIELD((x), 9, 9) + +/* PDCTL states */ +#define PSC_REG_VAL_PDCTL_NEXT_ON 1 +#define PSC_REG_VAL_PDCTL_NEXT_OFF 0 + +#define PSC_REG_VAL_PDCTL_PDMODE_SLEEP 0 + +/* MDCTL states */ +#define PSC_REG_VAL_MDCTL_NEXT_SWRSTDISABLE 0 +#define PSC_REG_VAL_MDCTL_NEXT_OFF 2 +#define PSC_REG_VAL_MDCTL_NEXT_ON 3 + +/* MDSTAT states */ +#define PSC_REG_VAL_MDSTAT_STATE_ON 3 +#define PSC_REG_VAL_MDSTAT_STATE_ENABLE_IN_PROG 0x24 +#define PSC_REG_VAL_MDSTAT_STATE_OFF 2 +#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG1 0x20 +#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG2 0x21 +#define PSC_REG_VAL_MDSTAT_STATE_DISABLE_IN_PROG3 0x22 + +/* + * Timeout limit on checking PTSTAT. This is the number of times the + * wait function will be called before giving up. + */ +#define PSC_PTSTAT_TIMEOUT_LIMIT 100 + +u32 psc_get_domain_num(u32 mod_num); +int psc_enable_module(u32 mod_num); +int psc_disable_module(u32 mod_num); +int psc_disable_domain(u32 domain_num); + +#endif /* _PSC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-keystone/spl.h b/arch/arm/include/asm/arch-keystone/spl.h new file mode 100644 index 00000000000..7012ea7ff0e --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/spl.h @@ -0,0 +1,12 @@ +/* + * (C) Copyright 2012-2014 + * Texas Instruments, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_SPL_H_ + +#define BOOT_DEVICE_SPI 2 + +#endif diff --git a/board/ti/k2hk_evm/Makefile b/board/ti/k2hk_evm/Makefile new file mode 100644 index 00000000000..3645f2feb01 --- /dev/null +++ b/board/ti/k2hk_evm/Makefile @@ -0,0 +1,9 @@ +# +# K2HK-EVM: board Makefile +# (C) Copyright 2012-2014 +# Texas Instruments Incorporated, +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += board.o +obj-y += ddr3.o diff --git a/board/ti/k2hk_evm/README b/board/ti/k2hk_evm/README new file mode 100644 index 00000000000..bfeb05b4a4e --- /dev/null +++ b/board/ti/k2hk_evm/README @@ -0,0 +1,122 @@ +U-Boot port for Texas Instruments XTCIEVMK2X +============================================ + +Author: Murali Karicheri + +This README has information on the u-boot port for XTCIEVMK2X EVM board. +Documentation for this board can be found at + http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx + +The board is based on Texas Instruments Keystone2 family of SoCs : K2H, K2K. +More details on these SoCs are available at company websites + K2K: http://www.ti.com/product/tci6638k2k + K2H: http://www.ti.com/product/tci6638k2h + +Board configuration: +==================== + +Some of the peripherals that are configured by u-boot are:- + +1. 2GB DDR3 (can support 8GB SO DIMM as well) +2. 512M NAND (over ti emif16 bus) +3. 6MB MSM SRAM (part of the SoC) +4. two 1GBit Ethernet ports (SoC supports upto 4) +5. two UART ports +6. three i2c interfaces +7. three spi interfaces (only 1 interface supported in driver) + +There are seperate PLLs to drive clocks to Tetris ARM and Peripherals. +To bring up SMP Linux on this board, there is a boot monitor +code that will be installed in MSMC SRAM. There is command available +to install this image from u-boot. + +The port related files can be found at following folders + keystone2 SoC related files: arch/arm/cpu/armv7/keystone/ + K2HK evm board files: board/ti/k2hk_evm/ + +board configuration file: include/configs/k2hk_evm.h + +Supported boot modes: + - SPI NOR boot + +Supported image formats:- + - u-boot.bin: for loading and running u-boot.bin through Texas instruments + code composure studio (CCS) + - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot + +Build instructions: +=================== + +To build u-boot.bin + >make k2hk_evm_config + >make u-boot-spi.gph + +To build u-boot-spi.gph + >make k2hk_evm_config + >make u-boot-spi.gph + +Load and Run U-Boot on K2HK EVM using CCS +========================================= + +Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin +on EVM. See instructions at below link for installing CCS on a Windows PC. +http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started# +Installing_Code_Composer_Studio +Use u-boot.bin from the build folder for loading annd running u-boot binary +on EVM. Follow instructions at +http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup +to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode" +and Power ON the EVM. Follow instructions to connect serial port of EVM to +PC and start TeraTerm or Hyper Terminal. + +Start CCS on a Windows machine and Launch Target +configuration as instructed at http://processors.wiki.ti.com/index.php/ +MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS. +The instructions provided in the above link uses a script for +loading the u-boot binary on the target EVM. Instead do the following:- + +1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D + isconnected: Unknown)" at the debug window (This is created once Target + configuration is launched) and select "Connect Target". +2. Once target connect is successful, choose Tools->Load Memory option from the + top level menu. At the Load Memory window, choose the file u-boot.bin + through "Browse" button and click "next >" button. In the next window, enter + Start address as 0xc001000, choose Type-size "32 bits" and click "Finish" + button. +3. Click View -> Registers from the top level menu to view registers window. +4. From Registers, window expand "Core Registers" to view PC. Edit PC value + to be 0xc001000. From the "Run" top level menu, select "Free Run" +5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as + below and type any key to stop autoboot as instructed := + +U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59) + +I2C: ready +Detected SO-DIMM [SQR-SD3T-2G1333SED] +DRAM: 1.1 GiB +NAND: 512 MiB +Net: K2HK_EMAC +Warning: K2HK_EMAC using MAC address from net device +, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3 +Hit any key to stop autoboot: 0 + +SPI NOR Flash programming instructions +====================================== +U-Boot image can be flashed to first 512KB of the NOR flash using following +instructions:- + +1. Start CCS and run U-boot as described above. +2. Suspend Target. Select Run -> Suspend from top level menu + CortexA15_1 (Free Running)" +3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM + using CCS", but using address 0x87000000. +4. Free Run the target as desribed earlier (step 4) to get u-boot prompt +5. At the U-Boot console type following to setup u-boot environment variables. + setenv addr_uboot 0x87000000 + setenv filesize + run burn_uboot + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + to "SPI Little Endian Boot mode" as per instruction at + http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. +6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash. diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c new file mode 100644 index 00000000000..aef67f4b48f --- /dev/null +++ b/board/ti/k2hk_evm/board.c @@ -0,0 +1,236 @@ +/* + * K2HK EVM : Board initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +u32 device_big_endian; + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = 122880000, + [alt_core_clk] = 125000000, + [pa_clk] = 122880000, + [tetris_clk] = 125000000, + [ddr3a_clk] = 100000000, + [ddr3b_clk] = 100000000, + [mcm_clk] = 312500000, + [pcie_clk] = 100000000, + [sgmii_srio_clk] = 156250000, + [xgmii_clk] = 156250000, + [usb_clk] = 100000000, + [rp1_clk] = 123456789 /* TODO: cannot find + what is that */ +}; + +static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = { + { /* CS0 */ + .mode = ASYNC_EMIF_MODE_NAND, + .wr_setup = 0xf, + .wr_strobe = 0x3f, + .wr_hold = 7, + .rd_setup = 0xf, + .rd_strobe = 0x3f, + .rd_hold = 7, + .turn_around = 3, + .width = ASYNC_EMIF_8, + }, + +}; + +static struct pll_init_data pll_config[] = { + CORE_PLL_1228, + PASS_PLL_983, + TETRIS_PLL_1200, +}; + +int dram_init(void) +{ + init_ddr3(); + + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_RAM_BANK_SIZE); + init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config); + return 0; +} + +/* Byte swap the 32-bit data if the device is BE */ +int cpu_to_bus(u32 *ptr, u32 length) +{ + u32 i; + + if (device_big_endian) + for (i = 0; i < length; i++, ptr++) + *ptr = __swab32(*ptr); + + return 0; +} + +#if defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void) +{ + init_plls(ARRAY_SIZE(pll_config), pll_config); + return 0; +} +#endif + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +#define K2_DDR3_START_ADDR 0x80000000 +void ft_board_setup(void *blob, bd_t *bd) +{ + u64 start[2]; + u64 size[2]; + char name[32], *env, *endp; + int lpae, nodeoffset; + u32 ddr3a_size; + int nbanks; + + env = getenv("mem_lpae"); + lpae = env && simple_strtol(env, NULL, 0); + + ddr3a_size = 0; + if (lpae) { + env = getenv("ddr3a_size"); + if (env) + ddr3a_size = simple_strtol(env, NULL, 10); + if ((ddr3a_size != 8) && (ddr3a_size != 4)) + ddr3a_size = 0; + } + + nbanks = 1; + start[0] = bd->bi_dram[0].start; + size[0] = bd->bi_dram[0].size; + + /* adjust memory start address for LPAE */ + if (lpae) { + start[0] -= K2_DDR3_START_ADDR; + start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; + } + + if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { + size[1] = ((u64)ddr3a_size - 2) << 30; + start[1] = 0x880000000; + nbanks++; + } + + /* reserve memory at start of bank */ + sprintf(name, "mem_reserve_head"); + env = getenv(name); + if (env) { + start[0] += ustrtoul(env, &endp, 0); + size[0] -= ustrtoul(env, &endp, 0); + } + + sprintf(name, "mem_reserve"); + env = getenv(name); + if (env) + size[0] -= ustrtoul(env, &endp, 0); + + fdt_fixup_memory_banks(blob, start, size, nbanks); + + /* Fix up the initrd */ + if (lpae) { + u64 initrd_start, initrd_end; + u32 *prop1, *prop2; + int err; + nodeoffset = fdt_path_offset(blob, "/chosen"); + if (nodeoffset >= 0) { + prop1 = (u32 *)fdt_getprop(blob, nodeoffset, + "linux,initrd-start", NULL); + prop2 = (u32 *)fdt_getprop(blob, nodeoffset, + "linux,initrd-end", NULL); + if (prop1 && prop2) { + initrd_start = __be32_to_cpu(*prop1); + initrd_start -= K2_DDR3_START_ADDR; + initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_start = __cpu_to_be64(initrd_start); + initrd_end = __be32_to_cpu(*prop2); + initrd_end -= K2_DDR3_START_ADDR; + initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_end = __cpu_to_be64(initrd_end); + + err = fdt_delprop(blob, nodeoffset, + "linux,initrd-start"); + if (err < 0) + puts("error deleting initrd-start\n"); + + err = fdt_delprop(blob, nodeoffset, + "linux,initrd-end"); + if (err < 0) + puts("error deleting initrd-end\n"); + + err = fdt_setprop(blob, nodeoffset, + "linux,initrd-start", + &initrd_start, + sizeof(initrd_start)); + if (err < 0) + puts("error adding initrd-start\n"); + + err = fdt_setprop(blob, nodeoffset, + "linux,initrd-end", + &initrd_end, + sizeof(initrd_end)); + if (err < 0) + puts("error adding linux,initrd-end\n"); + } + } + } +} + +void ft_board_setup_ex(void *blob, bd_t *bd) +{ + int lpae; + char *env; + u64 *reserve_start, size; + + env = getenv("mem_lpae"); + lpae = env && simple_strtol(env, NULL, 0); + + if (lpae) { + /* + * the initrd and other reserved memory areas are + * embedded in in the DTB itslef. fix up these addresses + * to 36 bit format + */ + reserve_start = (u64 *)((char *)blob + + fdt_off_mem_rsvmap(blob)); + while (1) { + *reserve_start = __cpu_to_be64(*reserve_start); + size = __cpu_to_be64(*(reserve_start + 1)); + if (size) { + *reserve_start -= K2_DDR3_START_ADDR; + *reserve_start += + CONFIG_SYS_LPAE_SDRAM_BASE; + *reserve_start = + __cpu_to_be64(*reserve_start); + } else { + break; + } + reserve_start += 2; + } + } +} +#endif diff --git a/board/ti/k2hk_evm/ddr3.c b/board/ti/k2hk_evm/ddr3.c new file mode 100644 index 00000000000..6092eb8fe33 --- /dev/null +++ b/board/ti/k2hk_evm/ddr3.c @@ -0,0 +1,268 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/************************* *****************************/ +static struct ddr3_phy_config ddr3phy_1600_64A = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), + .dcr_val = ((1 << 10) | (1 << 27)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x12868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_emif_config ddr3_1600_64 = { + .sdcfg = 0x6200CE6aul, + .sdtim1 = 0x16709C55ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x435DFF54ul, + .sdtim4 = 0x553F0CFFul, + .zqcfg = 0xF0073200ul, + .sdrfc = 0x00001869ul, +}; + +static struct ddr3_phy_config ddr3phy_1600_32 = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), + .dcr_val = ((1 << 10) | (1 << 27)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x12868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_emif_config ddr3_1600_32 = { + .sdcfg = 0x6200DE6aul, + .sdtim1 = 0x16709C55ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x435DFF54ul, + .sdtim4 = 0x553F0CFFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001869ul, +}; + +/************************* *****************************/ +static struct ddr3_phy_config ddr3phy_1333_64A = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | + NOSRA_MASK | UDIMM_MASK), + .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x12857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_emif_config ddr3_1333_64 = { + .sdcfg = 0x62008C62ul, + .sdtim1 = 0x125C8044ul, + .sdtim2 = 0x00001D29ul, + .sdtim3 = 0x32CDFF43ul, + .sdtim4 = 0x543F0ADFul, + .zqcfg = 0xF0073200ul, + .sdrfc = 0x00001457ul, +}; + +static struct ddr3_phy_config ddr3phy_1333_32 = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | + NOSRA_MASK | UDIMM_MASK), + .dcr_val = ((1 << 10) | (1 << 27) | (1 << 29)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x12857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +static struct ddr3_emif_config ddr3_1333_32 = { + .sdcfg = 0x62009C62ul, + .sdtim1 = 0x125C8044ul, + .sdtim2 = 0x00001D29ul, + .sdtim3 = 0x32CDFF43ul, + .sdtim4 = 0x543F0ADFul, + .zqcfg = 0xf0073200ul, + .sdrfc = 0x00001457ul, +}; + +/************************* *****************************/ +static struct ddr3_phy_config ddr3phy_1333_64 = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK | NOSRA_MASK), + .dcr_val = ((1 << 10) | (1 << 27)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x12857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; +/******************************************************/ +int get_dimm_params(char *dimm_name) +{ + u8 spd_params[256]; + int ret; + int old_bus; + + i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); + + old_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + ret = i2c_read(0x53, 0, 1, spd_params, 256); + + i2c_set_bus_num(old_bus); + + dimm_name[0] = '\0'; + + if (ret) { + puts("Cannot read DIMM params\n"); + return 1; + } + + /* + * We need to convert spd data to dimm parameters + * and to DDR3 EMIF and PHY regirsters values. + * For now we just return DIMM type string value. + * Caller may use this value to choose appropriate + * a pre-set DDR3 configuration + */ + + strncpy(dimm_name, (char *)&spd_params[0x80], 18); + dimm_name[18] = '\0'; + + return 0; +} + +struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); +struct pll_init_data ddr3b_333 = DDR3_PLL_333(B); +struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); +struct pll_init_data ddr3b_400 = DDR3_PLL_400(B); + +void init_ddr3(void) +{ + char dimm_name[32]; + + get_dimm_params(dimm_name); + + printf("Detected SO-DIMM [%s]\n", dimm_name); + + if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { + init_pll(&ddr3a_400); + if (cpu_revision() > 0) { + init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_64A); + init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_64); + printf("DRAM: Capacity 8 GiB (includes reported below)\n"); + } else { + init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1600_32); + init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_32); + printf("DRAM: Capacity 4 GiB (includes reported below)\n"); + } + } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { + init_pll(&ddr3a_333); + if (cpu_revision() > 0) { + init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_64A); + init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_64); + } else { + init_ddrphy(K2HK_DDR3A_DDRPHYC, &ddr3phy_1333_32); + init_ddremif(K2HK_DDR3A_EMIF_CTRL_BASE, &ddr3_1333_32); + } + } else { + printf("Unknown SO-DIMM. Cannot configure DDR3\n"); + while (1) + ; + } + + init_pll(&ddr3b_333); + init_ddrphy(K2HK_DDR3B_DDRPHYC, &ddr3phy_1333_64); + init_ddremif(K2HK_DDR3B_EMIF_CTRL_BASE, &ddr3_1333_64); +} diff --git a/boards.cfg b/boards.cfg index 96a69670069..c44ef0b10c8 100644 --- a/boards.cfg +++ b/boards.cfg @@ -294,6 +294,7 @@ Active arm armv7 exynos samsung trats Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak Active arm armv7 highbank - highbank highbank - Rob Herring +Active arm armv7 keystone ti k2hk_evm k2hk_evm - Vitaly Andrianov Active arm armv7 mx5 denx m53evk m53evk m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg Marek Vasut Active arm armv7 mx5 esg ima3-mx53 ima3-mx53 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg - Active arm armv7 mx5 freescale mx51evk mx51evk mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg Stefano Babic diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index fbc37b27e8e..8a134549433 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -30,6 +30,11 @@ #define serial_in(y) readb(y) #endif +#if defined(CONFIG_K2HK_EVM) +#define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 +#define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) +#endif + #ifndef CONFIG_SYS_NS16550_IER #define CONFIG_SYS_NS16550_IER 0x00 #endif /* CONFIG_SYS_NS16550_IER */ @@ -77,6 +82,9 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) /* /16 is proper to hit 115200 with 48MHz */ serial_out(0, &com_port->mdr1); #endif /* CONFIG_OMAP */ +#if defined(CONFIG_K2HK_EVM) + serial_out(UART_REG_VAL_PWREMU_MGMT_UART_ENABLE, &com_port->regC); +#endif } #ifndef CONFIG_NS16550_MIN_FUNCTIONS diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h new file mode 100644 index 00000000000..9d0ba248cf8 --- /dev/null +++ b/include/configs/k2hk_evm.h @@ -0,0 +1,212 @@ +/* + * Configuration header file for TI's k2hk-evm + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_K2HK_EVM_H +#define __CONFIG_K2HK_EVM_H + +/* Platform type */ +#define CONFIG_SOC_K2HK +#define CONFIG_K2HK_EVM + +/* U-Boot Build Configuration */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ +#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SYS_THUMB_BUILD + +/* SoC Configuration */ +#define CONFIG_ARMV7 +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_ARCH_TIMER +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_TEXT_BASE 0x0c001000 +#define CONFIG_SPL_TARGET "u-boot-spi.gph" +#define CONFIG_SYS_DCACHE_OFF + +/* Memory Configuration */ +#define CONFIG_NR_DRAM_BANKS 2 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 +#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ +#define CONFIG_STACKSIZE (512 << 10) /* 512 KiB */ +#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4 MiB */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ + GENERATED_GBL_DATA_SIZE) + +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE 0x0c200000 +#define CONFIG_SPL_PAD_TO 65536 +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) +#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SPL_TEXT_BASE + \ + CONFIG_SPL_MAX_SIZE) +#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ + CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) +#define CONFIG_SPL_STACK_SIZE (8 * 1024) +#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ + CONFIG_SYS_SPL_MALLOC_SIZE + \ + CONFIG_SPL_STACK_SIZE - 4) +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SPL_FRAMEWORK + +/* UART Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 K2HK_UART0_BASE +#define CONFIG_SYS_NS16550_CLK clk_get_rate(K2HK_CLK1_6) +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* SPI Configuration */ +#define CONFIG_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_DAVINCI_SPI +#define CONFIG_SYS_SPI_BASE K2HK_SPI_BASE +#define CONFIG_SYS_SPI_CLK clk_get_rate(K2HK_LPSC_EMIF25_SPI) +#define CONFIG_SF_DEFAULT_SPEED 30000000 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED + +/* I2C Configuration */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_DAVINCI +#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ +#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ +#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 +#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ +#define I2C_BUS_MAX 3 + +/* EEPROM definitions */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 +#define CONFIG_ENV_EEPROM_IS_ON_I2C + +/* NAND Configuration */ +#define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_CS 2 +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST +#define CONFIG_SYS_NAND_PAGE_2K + +#define CONFIG_SYS_NAND_LARGEPAGE +#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE +#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x100000 +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ + "1024k(bootloader)ro,512k(params)ro," \ + "-(ubifs)" +/* U-Boot command configuration */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_SF +#define CONFIG_CMD_EEPROM + +/* U-Boot general configuration */ +#define CONFIG_SYS_PROMPT "K2HK EVM # " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE 2048 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE +#define CONFIG_TIMESTAMP + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "boot=ramfs\0" \ + "tftp_root=/\0" \ + "nfs_root=/export\0" \ + "mem_lpae=1\0" \ + "mem_reserve=512M\0" \ + "addr_fdt=0x87000000\0" \ + "addr_kern=0x88000000\0" \ + "addr_mon=0x0c5f0000\0" \ + "addr_uboot=0x87000000\0" \ + "addr_fs=0x82000000\0" \ + "addr_ubi=0x82000000\0" \ + "fdt_high=0xffffffff\0" \ + "run_mon=mon_install ${addr_mon}\0" \ + "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \ + "init_ubi=run args_all args_ubi; " \ + "ubi part ubifs; ubifsmount boot\0" \ + "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \ + "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \ + "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ + "burn_uboot=sf probe; sf erase 0 0x100000; " \ + "sf write ${addr_uboot} 0 ${filesize}\0" \ + "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ + "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \ + "burn_ubi=nand erase.part ubifs; " \ + "nand write ${addr_ubi} ubifs ${filesize}\0" \ + "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ + "args_ramfs=setenv bootargs ${bootargs} earlyprintk " \ + "rdinit=/sbin/init rw root=/dev/ram0 " \ + "initrd=0x802000000,9M\0" \ + "mtdparts=mtdparts=davinci_nand.0:" \ + "1024k(bootloader)ro,512k(params)ro,522752k(ubifs)\0" +#define CONFIG_BOOTCOMMAND \ + "run init_${boot} get_fdt_${boot} get_mon_${boot} " \ + "get_kern_${boot} run_mon run_kern" +#define CONFIG_BOOTARGS \ + +/* Linux interfacing */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_SYS_BARGSIZE 1024 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) + +#define CONFIG_SUPPORT_RAW_INITRD + +/* we may include files below only after all above definitions */ +#include +#include +#define CONFIG_SYS_HZ_CLOCK clk_get_rate(K2HK_CLK1_6) + +#endif /* __CONFIG_K2HK_EVM_H */ -- cgit v1.3.1 From 56f624d06a1bea4e592e32be66821e3d9a43539e Mon Sep 17 00:00:00 2001 From: "Karicheri, Muralidharan" Date: Fri, 4 Apr 2014 13:16:55 -0400 Subject: k2hk-evm: add configuration for spi1 and spi2 support currently only spi0 is enabled on k2hk evm. This configuration update is needed to enable spi1 and spi2. Signed-off-by: Murali Karicheri Acked-by: Tom Rini --- include/configs/k2hk_evm.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 9d0ba248cf8..28a6d722fbb 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -81,7 +81,16 @@ #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_DAVINCI_SPI +#define CONFIG_SYS_SPI0 #define CONFIG_SYS_SPI_BASE K2HK_SPI_BASE +#define CONFIG_SYS_SPI0_NUM_CS 4 +#define CONFIG_SYS_SPI1 +#define CONFIG_SYS_SPI1_BASE K2HK_SPI1_BASE +#define CONFIG_SYS_SPI1_NUM_CS 4 +#define CONFIG_SYS_SPI2 +#define CONFIG_SYS_SPI2_NUM_CS 4 +#define CONFIG_SYS_SPI2_BASE K2HK_SPI2_BASE +#define CONFIG_CMD_SPI #define CONFIG_SYS_SPI_CLK clk_get_rate(K2HK_LPSC_EMIF25_SPI) #define CONFIG_SF_DEFAULT_SPEED 30000000 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED -- cgit v1.3.1 From fc9a8e8d40e770b00383c2433c843fe68e38dad3 Mon Sep 17 00:00:00 2001 From: "Karicheri, Muralidharan" Date: Tue, 1 Apr 2014 15:01:13 -0400 Subject: keystone2: net: add keystone ethernet driver Ethernet driver configures the CPSW, SGMI and Phy and uses the the Navigator APIs. The driver supports 4 Ethernet ports and can work with only one port at a time. Port configurations are defined in board.c. Signed-off-by: Vitaly Andrianov Signed-off-by: Murali Karicheri Signed-off-by: WingMan Kwok --- arch/arm/include/asm/arch-keystone/emac_defs.h | 240 +++++++++ board/ti/k2hk_evm/board.c | 65 +++ drivers/net/Makefile | 1 + drivers/net/keystone_net.c | 716 +++++++++++++++++++++++++ include/configs/k2hk_evm.h | 35 ++ 5 files changed, 1057 insertions(+) create mode 100644 arch/arm/include/asm/arch-keystone/emac_defs.h create mode 100644 drivers/net/keystone_net.c (limited to 'include') diff --git a/arch/arm/include/asm/arch-keystone/emac_defs.h b/arch/arm/include/asm/arch-keystone/emac_defs.h new file mode 100644 index 00000000000..0aa2f89d780 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/emac_defs.h @@ -0,0 +1,240 @@ +/* + * emac definitions for keystone2 devices + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _EMAC_DEFS_H_ +#define _EMAC_DEFS_H_ + +#include +#include + +#define DEVICE_REG32_R(a) readl(a) +#define DEVICE_REG32_W(a, v) writel(v, a) + +#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900) +#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300) +#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100) + +#define KEYSTONE2_EMAC_GIG_ENABLE + +#define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110) + +#ifdef CONFIG_SOC_K2HK +/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk)) +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */ +#endif + +/* MII Status Register */ +#define MII_STATUS_REG 1 +#define MII_STATUS_LINK_MASK (0x4) + +/* Marvell 88E1111 PHY ID */ +#define PHY_MARVELL_88E1111 (0x01410cc0) + +#define MDIO_CONTROL_IDLE (0x80000000) +#define MDIO_CONTROL_ENABLE (0x40000000) +#define MDIO_CONTROL_FAULT_ENABLE (0x40000) +#define MDIO_CONTROL_FAULT (0x80000) +#define MDIO_USERACCESS0_GO (0x80000000) +#define MDIO_USERACCESS0_WRITE_READ (0x0) +#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) +#define MDIO_USERACCESS0_ACK (0x20000000) + +#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) +#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) +#define EMAC_MACCONTROL_GIGFORCE (1 << 17) +#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) + +#define EMAC_MIN_ETHERNET_PKT_SIZE 60 + +struct mac_sl_cfg { + u_int32_t max_rx_len; /* Maximum receive packet length. */ + u_int32_t ctl; /* Control bitfield */ +}; + +/* + * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t + */ +#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24) +#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23) +#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22) +#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18) +#define GMACSL_RX_ENABLE_GIG_FORCE (1 << 17) +#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16) +#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15) +#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11) +#define GMACSL_TX_ENABLE_SHORT_GAP (1 << 10) +#define GMACSL_ENABLE_GIG_MODE (1 << 7) +#define GMACSL_TX_ENABLE_PACE (1 << 6) +#define GMACSL_ENABLE (1 << 5) +#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4) +#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3) +#define GMACSL_ENABLE_LOOPBACK (1 << 1) +#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0) + +/* + * DEFINTITION: function return values + */ +#define GMACSL_RET_OK 0 +#define GMACSL_RET_INVALID_PORT -1 +#define GMACSL_RET_WARN_RESET_INCOMPLETE -2 +#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3 +#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4 + +/* Register offsets */ +#define CPGMACSL_REG_ID 0x00 +#define CPGMACSL_REG_CTL 0x04 +#define CPGMACSL_REG_STATUS 0x08 +#define CPGMACSL_REG_RESET 0x0c +#define CPGMACSL_REG_MAXLEN 0x10 +#define CPGMACSL_REG_BOFF 0x14 +#define CPGMACSL_REG_RX_PAUSE 0x18 +#define CPGMACSL_REG_TX_PAURSE 0x1c +#define CPGMACSL_REG_EM_CTL 0x20 +#define CPGMACSL_REG_PRI 0x24 + +/* Soft reset register values */ +#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0) +#define CPGMAC_REG_RESET_VAL_RESET (1 << 0) + +/* Maxlen register values */ +#define CPGMAC_REG_MAXLEN_LEN 0x3fff + +/* Control bitfields */ +#define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5) +#define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4) +#define CPSW_CTL_P0_PASS_PRI_TAGGED (1 << 3) +#define CPSW_CTL_P0_ENABLE (1 << 2) +#define CPSW_CTL_VLAN_AWARE (1 << 1) +#define CPSW_CTL_FIFO_LOOPBACK (1 << 0) + +#define DEVICE_CPSW_NUM_PORTS 5 /* 5 switch ports */ +#define DEVICE_CPSW_BASE (0x02090800) +#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */ +#define SWITCH_MAX_PKT_SIZE 9000 + +/* Register offsets */ +#define CPSW_REG_CTL 0x004 +#define CPSW_REG_STAT_PORT_EN 0x00c +#define CPSW_REG_MAXLEN 0x040 +#define CPSW_REG_ALE_CONTROL 0x608 +#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4) + +/* Register values */ +#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf +#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000) +#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010) +#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3 + +#define SGMII_REG_STATUS_LOCK BIT(4) +#define SGMII_REG_STATUS_LINK BIT(0) +#define SGMII_REG_STATUS_AUTONEG BIT(2) +#define SGMII_REG_CONTROL_AUTONEG BIT(0) +#define SGMII_REG_CONTROL_MASTER BIT(5) +#define SGMII_REG_MR_ADV_ENABLE BIT(0) +#define SGMII_REG_MR_ADV_LINK BIT(15) +#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12) +#define SGMII_REG_MR_ADV_GIG_MODE BIT(11) + +#define SGMII_LINK_MAC_MAC_AUTONEG 0 +#define SGMII_LINK_MAC_PHY 1 +#define SGMII_LINK_MAC_MAC_FORCED 2 +#define SGMII_LINK_MAC_FIBER 3 +#define SGMII_LINK_MAC_PHY_FORCED 4 + +#define TARGET_SGMII_BASE KS2_PASS_BASE + 0x00090100 +#define TARGET_SGMII_BASE_ADDRESSES {KS2_PASS_BASE + 0x00090100, \ + KS2_PASS_BASE + 0x00090200, \ + KS2_PASS_BASE + 0x00090400, \ + KS2_PASS_BASE + 0x00090500} + +#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100)) + +/* + * SGMII registers + */ +#define SGMII_IDVER_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000) +#define SGMII_SRESET_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004) +#define SGMII_CTL_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010) +#define SGMII_STATUS_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014) +#define SGMII_MRADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018) +#define SGMII_LPADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020) +#define SGMII_TXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030) +#define SGMII_RXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034) +#define SGMII_AUXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038) + +#define DEVICE_EMACSL_BASE(x) (KS2_PASS_BASE + 0x00090900 + (x) * 0x040) +#define DEVICE_N_GMACSL_PORTS 4 +#define DEVICE_EMACSL_RESET_POLL_COUNT 100 + +#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604) + +#ifdef CONFIG_SOC_K2HK +#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI 0x06060606 +#endif + +#define hw_config_streaming_switch() \ + DEVICE_REG32_W(DEVICE_PSTREAM_CFG_REG_ADDR, \ + DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI); + +/* EMAC MDIO Registers Structure */ +struct mdio_regs { + dv_reg version; + dv_reg control; + dv_reg alive; + dv_reg link; + dv_reg linkintraw; + dv_reg linkintmasked; + u_int8_t rsvd0[8]; + dv_reg userintraw; + dv_reg userintmasked; + dv_reg userintmaskset; + dv_reg userintmaskclear; + u_int8_t rsvd1[80]; + dv_reg useraccess0; + dv_reg userphysel0; + dv_reg useraccess1; + dv_reg userphysel1; +}; + +/* Ethernet MAC Registers Structure */ +struct emac_regs { + dv_reg idver; + dv_reg maccontrol; + dv_reg macstatus; + dv_reg soft_reset; + dv_reg rx_maxlen; + u32 rsvd0; + dv_reg rx_pause; + dv_reg tx_pause; + dv_reg emcontrol; + dv_reg pri_map; + u32 rsvd1[6]; +}; + +#define SGMII_ACCESS(port, reg) \ + *((volatile unsigned int *)(sgmiis[port] + reg)) + +struct eth_priv_t { + char int_name[32]; + int rx_flow; + int phy_addr; + int slave_port; + int sgmii_link_type; +}; + +extern struct eth_priv_t eth_priv_cfg[]; + +int keystone2_emac_initialize(struct eth_priv_t *eth_priv); +void sgmii_serdes_setup_156p25mhz(void); +void sgmii_serdes_shutdown(void); + +#endif /* _EMAC_DEFS_H_ */ diff --git a/board/ti/k2hk_evm/board.c b/board/ti/k2hk_evm/board.c index aef67f4b48f..dc39139565f 100644 --- a/board/ti/k2hk_evm/board.c +++ b/board/ti/k2hk_evm/board.c @@ -17,6 +17,7 @@ #include #include #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -70,6 +71,70 @@ int dram_init(void) return 0; } +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +struct eth_priv_t eth_priv_cfg[] = { + { + .int_name = "K2HK_EMAC", + .rx_flow = 22, + .phy_addr = 0, + .slave_port = 1, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2HK_EMAC1", + .rx_flow = 23, + .phy_addr = 1, + .slave_port = 2, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2HK_EMAC2", + .rx_flow = 24, + .phy_addr = 2, + .slave_port = 3, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2HK_EMAC3", + .rx_flow = 25, + .phy_addr = 3, + .slave_port = 4, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, +}; + +int get_eth_env_param(char *env_name) +{ + char *env; + int res = -1; + + env = getenv(env_name); + if (env) + res = simple_strtol(env, NULL, 0); + + return res; +} + +int board_eth_init(bd_t *bis) +{ + int j; + int res; + char link_type_name[32]; + + for (j = 0; j < (sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t)); + j++) { + sprintf(link_type_name, "sgmii%d_link_type", j); + res = get_eth_env_param(link_type_name); + if (res >= 0) + eth_priv_cfg[j].sgmii_link_type = res; + + keystone2_emac_initialize(ð_priv_cfg[j]); + } + + return 0; +} +#endif + /* Byte swap the 32-bit data if the device is BE */ int cpu_to_bus(u32 *ptr, u32 length) { diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 7f9ce90a6d5..6005f7e4137 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_FTMAC110) += ftmac110.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GRETH) += greth.o obj-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o +obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_LAN91C96) += lan91c96.o diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c new file mode 100644 index 00000000000..f95c9280765 --- /dev/null +++ b/drivers/net/keystone_net.c @@ -0,0 +1,716 @@ +/* + * Ethernet driver for TI K2HK EVM. + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include + +#include +#include +#include +#include +#include +#include + +unsigned int emac_dbg; + +unsigned int emac_open; +static unsigned int sys_has_mdio = 1; + +#ifdef KEYSTONE2_EMAC_GIG_ENABLE +#define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) +#else +#define emac_gigabit_enable(x) /* no gigabit to enable */ +#endif + +#define RX_BUFF_NUMS 24 +#define RX_BUFF_LEN 1520 +#define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN + +static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16); + +struct rx_buff_desc net_rx_buffs = { + .buff_ptr = rx_buffs, + .num_buffs = RX_BUFF_NUMS, + .buff_len = RX_BUFF_LEN, + .rx_flow = 22, +}; + +static void keystone2_eth_mdio_enable(void); + +static int gen_get_link_speed(int phy_addr); + +/* EMAC Addresses */ +static volatile struct emac_regs *adap_emac = + (struct emac_regs *)EMAC_EMACSL_BASE_ADDR; +static volatile struct mdio_regs *adap_mdio = + (struct mdio_regs *)EMAC_MDIO_BASE_ADDR; + +int keystone2_eth_read_mac_addr(struct eth_device *dev) +{ + struct eth_priv_t *eth_priv; + u32 maca = 0; + u32 macb = 0; + + eth_priv = (struct eth_priv_t *)dev->priv; + + /* Read the e-fuse mac address */ + if (eth_priv->slave_port == 1) { + maca = __raw_readl(MAC_ID_BASE_ADDR); + macb = __raw_readl(MAC_ID_BASE_ADDR + 4); + } + + dev->enetaddr[0] = (macb >> 8) & 0xff; + dev->enetaddr[1] = (macb >> 0) & 0xff; + dev->enetaddr[2] = (maca >> 24) & 0xff; + dev->enetaddr[3] = (maca >> 16) & 0xff; + dev->enetaddr[4] = (maca >> 8) & 0xff; + dev->enetaddr[5] = (maca >> 0) & 0xff; + + return 0; +} + +static void keystone2_eth_mdio_enable(void) +{ + u_int32_t clkdiv; + + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + + writel((clkdiv & 0xffff) | + MDIO_CONTROL_ENABLE | + MDIO_CONTROL_FAULT | + MDIO_CONTROL_FAULT_ENABLE, + &adap_mdio->control); + + while (readl(&adap_mdio->control) & MDIO_CONTROL_IDLE) + ; +} + +/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */ +int keystone2_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) +{ + int tmp; + + while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) + ; + + writel(MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_READ | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16), + &adap_mdio->useraccess0); + + /* Wait for command to complete */ + while ((tmp = readl(&adap_mdio->useraccess0)) & MDIO_USERACCESS0_GO) + ; + + if (tmp & MDIO_USERACCESS0_ACK) { + *data = tmp & 0xffff; + return 0; + } + + *data = -1; + return -1; +} + +/* + * Write to a PHY register via MDIO inteface. + * Blocks until operation is complete. + */ +int keystone2_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) +{ + while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) + ; + + writel(MDIO_USERACCESS0_GO | + MDIO_USERACCESS0_WRITE_WRITE | + ((reg_num & 0x1f) << 21) | + ((phy_addr & 0x1f) << 16) | + (data & 0xffff), + &adap_mdio->useraccess0); + + /* Wait for command to complete */ + while (readl(&adap_mdio->useraccess0) & MDIO_USERACCESS0_GO) + ; + + return 0; +} + +/* PHY functions for a generic PHY */ +static int gen_get_link_speed(int phy_addr) +{ + u_int16_t tmp; + + if ((!keystone2_eth_phy_read(phy_addr, MII_STATUS_REG, &tmp)) && + (tmp & 0x04)) { + return 0; + } + + return -1; +} + +static void __attribute__((unused)) + keystone2_eth_gigabit_enable(struct eth_device *dev) +{ + u_int16_t data; + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + + if (sys_has_mdio) { + if (keystone2_eth_phy_read(eth_priv->phy_addr, 0, &data) || + !(data & (1 << 6))) /* speed selection MSB */ + return; + } + + /* + * Check if link detected is giga-bit + * If Gigabit mode detected, enable gigbit in MAC + */ + writel(readl(&(adap_emac[eth_priv->slave_port - 1].maccontrol)) | + EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE, + &(adap_emac[eth_priv->slave_port - 1].maccontrol)) + ; +} + +int keystone_sgmii_link_status(int port) +{ + u32 status = 0; + + status = __raw_readl(SGMII_STATUS_REG(port)); + + return status & SGMII_REG_STATUS_LINK; +} + + +int keystone_get_link_status(struct eth_device *dev) +{ + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + int sgmii_link; + int link_state = 0; +#if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1 + int j; + + for (j = 0; (j < CONFIG_GET_LINK_STATUS_ATTEMPTS) && (link_state == 0); + j++) { +#endif + sgmii_link = + keystone_sgmii_link_status(eth_priv->slave_port - 1); + + if (sgmii_link) { + link_state = 1; + + if (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) + if (gen_get_link_speed(eth_priv->phy_addr)) + link_state = 0; + } +#if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1 + } +#endif + return link_state; +} + +int keystone_sgmii_config(int port, int interface) +{ + unsigned int i, status, mask; + unsigned int mr_adv_ability, control; + + switch (interface) { + case SGMII_LINK_MAC_MAC_AUTONEG: + mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | + SGMII_REG_MR_ADV_LINK | + SGMII_REG_MR_ADV_FULL_DUPLEX | + SGMII_REG_MR_ADV_GIG_MODE); + control = (SGMII_REG_CONTROL_MASTER | + SGMII_REG_CONTROL_AUTONEG); + + break; + case SGMII_LINK_MAC_PHY: + case SGMII_LINK_MAC_PHY_FORCED: + mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; + control = SGMII_REG_CONTROL_AUTONEG; + + break; + case SGMII_LINK_MAC_MAC_FORCED: + mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE | + SGMII_REG_MR_ADV_LINK | + SGMII_REG_MR_ADV_FULL_DUPLEX | + SGMII_REG_MR_ADV_GIG_MODE); + control = SGMII_REG_CONTROL_MASTER; + + break; + case SGMII_LINK_MAC_FIBER: + mr_adv_ability = 0x20; + control = SGMII_REG_CONTROL_AUTONEG; + + break; + default: + mr_adv_ability = SGMII_REG_MR_ADV_ENABLE; + control = SGMII_REG_CONTROL_AUTONEG; + } + + __raw_writel(0, SGMII_CTL_REG(port)); + + /* + * Wait for the SerDes pll to lock, + * but don't trap if lock is never read + */ + for (i = 0; i < 1000; i++) { + udelay(2000); + status = __raw_readl(SGMII_STATUS_REG(port)); + if ((status & SGMII_REG_STATUS_LOCK) != 0) + break; + } + + __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port)); + __raw_writel(control, SGMII_CTL_REG(port)); + + + mask = SGMII_REG_STATUS_LINK; + + if (control & SGMII_REG_CONTROL_AUTONEG) + mask |= SGMII_REG_STATUS_AUTONEG; + + for (i = 0; i < 1000; i++) { + status = __raw_readl(SGMII_STATUS_REG(port)); + if ((status & mask) == mask) + break; + } + + return 0; +} + +int mac_sl_reset(u32 port) +{ + u32 i, v; + + if (port >= DEVICE_N_GMACSL_PORTS) + return GMACSL_RET_INVALID_PORT; + + /* Set the soft reset bit */ + DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + + CPGMACSL_REG_RESET, CPGMAC_REG_RESET_VAL_RESET); + + /* Wait for the bit to clear */ + for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { + v = DEVICE_REG32_R(DEVICE_EMACSL_BASE(port) + + CPGMACSL_REG_RESET); + if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != + CPGMAC_REG_RESET_VAL_RESET) + return GMACSL_RET_OK; + } + + /* Timeout on the reset */ + return GMACSL_RET_WARN_RESET_INCOMPLETE; +} + +int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg) +{ + u32 v, i; + int ret = GMACSL_RET_OK; + + if (port >= DEVICE_N_GMACSL_PORTS) + return GMACSL_RET_INVALID_PORT; + + if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) { + cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN; + ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG; + } + + /* Must wait if the device is undergoing reset */ + for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) { + v = DEVICE_REG32_R(DEVICE_EMACSL_BASE(port) + + CPGMACSL_REG_RESET); + if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) != + CPGMAC_REG_RESET_VAL_RESET) + break; + } + + if (i == DEVICE_EMACSL_RESET_POLL_COUNT) + return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE; + + DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN, + cfg->max_rx_len); + + DEVICE_REG32_W(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL, + cfg->ctl); + + return ret; +} + +int ethss_config(u32 ctl, u32 max_pkt_size) +{ + u32 i; + + /* Max length register */ + DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_MAXLEN, max_pkt_size); + + /* Control register */ + DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_CTL, ctl); + + /* All statistics enabled by default */ + DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN, + CPSW_REG_VAL_STAT_ENABLE_ALL); + + /* Reset and enable the ALE */ + DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL, + CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE | + CPSW_REG_VAL_ALE_CTL_BYPASS); + + /* All ports put into forward mode */ + for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++) + DEVICE_REG32_W(DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i), + CPSW_REG_VAL_PORTCTL_FORWARD_MODE); + + return 0; +} + +int ethss_start(void) +{ + int i; + struct mac_sl_cfg cfg; + + cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER; + cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL; + + for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) { + mac_sl_reset(i); + mac_sl_config(i, &cfg); + } + + return 0; +} + +int ethss_stop(void) +{ + int i; + + for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) + mac_sl_reset(i); + + return 0; +} + +int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num) +{ + if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE) + num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE; + + return netcp_send(buffer, num_bytes, (slave_port_num) << 16); +} + +/* Eth device open */ +static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) +{ + u_int32_t clkdiv; + int link; + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + + debug("+ emac_open\n"); + + net_rx_buffs.rx_flow = eth_priv->rx_flow; + + sys_has_mdio = + (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0; + + psc_enable_module(KS2_LPSC_PA); + psc_enable_module(KS2_LPSC_CPGMAC); + + sgmii_serdes_setup_156p25mhz(); + + if (sys_has_mdio) + keystone2_eth_mdio_enable(); + + keystone_sgmii_config(eth_priv->slave_port - 1, + eth_priv->sgmii_link_type); + + udelay(10000); + + /* On chip switch configuration */ + ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE); + + /* TODO: add error handling code */ + if (qm_init()) { + printf("ERROR: qm_init()\n"); + return -1; + } + if (netcp_init(&net_rx_buffs)) { + qm_close(); + printf("ERROR: netcp_init()\n"); + return -1; + } + + /* + * Streaming switch configuration. If not present this + * statement is defined to void in target.h. + * If present this is usually defined to a series of register writes + */ + hw_config_streaming_switch(); + + if (sys_has_mdio) { + /* Init MDIO & get link state */ + clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; + writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | + MDIO_CONTROL_FAULT, &adap_mdio->control) + ; + + /* We need to wait for MDIO to start */ + udelay(1000); + + link = keystone_get_link_status(dev); + if (link == 0) { + netcp_close(); + qm_close(); + return -1; + } + } + + emac_gigabit_enable(dev); + + ethss_start(); + + debug("- emac_open\n"); + + emac_open = 1; + + return 0; +} + +/* Eth device close */ +void keystone2_eth_close(struct eth_device *dev) +{ + debug("+ emac_close\n"); + + if (!emac_open) + return; + + ethss_stop(); + + netcp_close(); + qm_close(); + + emac_open = 0; + + debug("- emac_close\n"); +} + +static int tx_send_loop; + +/* + * This function sends a single packet on the network and returns + * positive number (number of bytes transmitted) or negative for error + */ +static int keystone2_eth_send_packet(struct eth_device *dev, + void *packet, int length) +{ + int ret_status = -1; + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + + tx_send_loop = 0; + + if (keystone_get_link_status(dev) == 0) + return -1; + + emac_gigabit_enable(dev); + + if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0) + return ret_status; + + if (keystone_get_link_status(dev) == 0) + return -1; + + emac_gigabit_enable(dev); + + return length; +} + +/* + * This function handles receipt of a packet from the network + */ +static int keystone2_eth_rcv_packet(struct eth_device *dev) +{ + void *hd; + int pkt_size; + u32 *pkt; + + hd = netcp_recv(&pkt, &pkt_size); + if (hd == NULL) + return 0; + + NetReceive((uchar *)pkt, pkt_size); + + netcp_release_rxhd(hd); + + return pkt_size; +} + +/* + * This function initializes the EMAC hardware. + */ +int keystone2_emac_initialize(struct eth_priv_t *eth_priv) +{ + struct eth_device *dev; + + dev = malloc(sizeof(struct eth_device)); + if (dev == NULL) + return -1; + + memset(dev, 0, sizeof(struct eth_device)); + + strcpy(dev->name, eth_priv->int_name); + dev->priv = eth_priv; + + keystone2_eth_read_mac_addr(dev); + + dev->iobase = 0; + dev->init = keystone2_eth_open; + dev->halt = keystone2_eth_close; + dev->send = keystone2_eth_send_packet; + dev->recv = keystone2_eth_rcv_packet; + + eth_register(dev); + + return 0; +} + +void sgmii_serdes_setup_156p25mhz(void) +{ + unsigned int cnt; + + /* + * configure Serializer/Deserializer (SerDes) hardware. SerDes IP + * hardware vendor published only register addresses and their values + * to be used for configuring SerDes. So had to use hardcoded values + * below. + */ + clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000); + clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282); + clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438); + clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700); + clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000); + + clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080); + clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000); + clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000); + clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000); + clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8); + clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4); + clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400); + clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800); + clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082); + clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385); + + clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080); + clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000); + clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000); + clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000); + clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8); + clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4); + clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400); + clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800); + clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082); + clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385); + + clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080); + clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000); + clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000); + clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000); + clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8); + clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4); + clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400); + clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800); + clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082); + clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385); + + clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080); + clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000); + clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000); + clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000); + clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8); + clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4); + clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400); + clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800); + clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082); + clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385); + + clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800); + clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000); + clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00); + clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600); + clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000); + clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000); + clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000); + clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b); + clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000); + clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e); + clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003); + clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f); + + clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00); + clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72); + clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100); + clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060); + clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000); + clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220); + clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602); + clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1); + clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989); + clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001); + clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000); + clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000); + clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d); + + /*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/ + clrbits_le32(0x0232a010, 1 << 28); + + /* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */ + clrbits_le32(0x0232a228, 1 << 29); + writel(0xF800F8C0, 0x0232bfe0); + clrbits_le32(0x0232a428, 1 << 29); + writel(0xF800F8C0, 0x0232bfe4); + clrbits_le32(0x0232a628, 1 << 29); + writel(0xF800F8C0, 0x0232bfe8); + clrbits_le32(0x0232a828, 1 << 29); + writel(0xF800F8C0, 0x0232bfec); + + /*Enable pll via the pll_ctrl 0x0014*/ + writel(0xe0000000, 0x0232bff4) + ; + + /*Waiting for SGMII Serdes PLL lock.*/ + for (cnt = 10000; cnt > 0 && ((readl(0x02090114) & 0x10) == 0); cnt--) + ; + + for (cnt = 10000; cnt > 0 && ((readl(0x02090214) & 0x10) == 0); cnt--) + ; + + for (cnt = 10000; cnt > 0 && ((readl(0x02090414) & 0x10) == 0); cnt--) + ; + + for (cnt = 10000; cnt > 0 && ((readl(0x02090514) & 0x10) == 0); cnt--) + ; + + udelay(45000); +} + +void sgmii_serdes_shutdown(void) +{ + /* + * shutdown SerDes hardware. SerDes hardware vendor published only + * register addresses and their values. So had to use hardcoded + * values below. + */ + clrbits_le32(0x0232bfe0, 3 << 29 | 3 << 13); + setbits_le32(0x02320228, 1 << 29); + clrbits_le32(0x0232bfe4, 3 << 29 | 3 << 13); + setbits_le32(0x02320428, 1 << 29); + clrbits_le32(0x0232bfe8, 3 << 29 | 3 << 13); + setbits_le32(0x02320628, 1 << 29); + clrbits_le32(0x0232bfec, 3 << 29 | 3 << 13); + setbits_le32(0x02320828, 1 << 29); + + clrbits_le32(0x02320034, 3 << 29); + setbits_le32(0x02320010, 1 << 28); +} diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 28a6d722fbb..9bb8f342b60 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -114,6 +114,20 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 #define CONFIG_ENV_EEPROM_IS_ON_I2C +/* Network Configuration */ +#define CONFIG_DRIVER_TI_KEYSTONE_NET +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 32 +#define CONFIG_NET_MULTI +#define CONFIG_GET_LINK_STATUS_ATTEMPTS 5 +#define CONFIG_SYS_SGMII_REFCLK_MHZ 312 +#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 +#define CONFIG_SYS_SGMII_RATESCALE 2 + /* NAND Configuration */ #define CONFIG_NAND_DAVINCI #define CONFIG_SYS_NAND_CS 2 @@ -178,24 +192,45 @@ "addr_fs=0x82000000\0" \ "addr_ubi=0x82000000\0" \ "fdt_high=0xffffffff\0" \ + "name_fdt=uImage-k2hk-evm.dtb\0" \ + "name_fs=arago-console-image.cpio.gz\0" \ + "name_kern=uImage-keystone-evm.bin\0" \ + "name_mon=skern-keystone-evm.bin\0" \ + "name_uboot=u-boot-spi-keystone-evm.gph\0" \ + "name_ubi=keystone-evm-ubifs.ubi\0" \ "run_mon=mon_install ${addr_mon}\0" \ "run_kern=bootm ${addr_kern} - ${addr_fdt}\0" \ + "init_net=run args_all args_net\0" \ "init_ubi=run args_all args_ubi; " \ "ubi part ubifs; ubifsmount boot\0" \ + "get_fdt_net=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ "get_fdt_ubi=ubifsload ${addr_fdt} ${name_fdt}\0" \ + "get_kern_net=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ "get_kern_ubi=ubifsload ${addr_kern} ${name_kern}\0" \ + "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ "get_mon_ubi=ubifsload ${addr_mon} ${name_mon}\0" \ + "get_uboot_net=dhcp ${addr_uboot} ${tftp_root}/${name_uboot}\0" \ "burn_uboot=sf probe; sf erase 0 0x100000; " \ "sf write ${addr_uboot} 0 ${filesize}\0" \ "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1\0" \ "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,2048\0" \ + "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ + "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ + "${nfs_options} ip=dhcp\0" \ + "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ + "get_fdt_ramfs=dhcp ${addr_fdt} ${tftp_root}/${name_fdt}\0" \ + "get_kern_ramfs=dhcp ${addr_kern} ${tftp_root}/${name_kern}\0" \ + "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ + "get_fs_ramfs=dhcp ${addr_fs} ${tftp_root}/${name_fs}\0" \ + "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ "burn_ubi=nand erase.part ubifs; " \ "nand write ${addr_ubi} ubifs ${filesize}\0" \ "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ "args_ramfs=setenv bootargs ${bootargs} earlyprintk " \ "rdinit=/sbin/init rw root=/dev/ram0 " \ "initrd=0x802000000,9M\0" \ + "no_post=1\0" \ "mtdparts=mtdparts=davinci_nand.0:" \ "1024k(bootloader)ro,512k(params)ro,522752k(ubifs)\0" #define CONFIG_BOOTCOMMAND \ -- cgit v1.3.1 From ae3248a3fdb262b6e1d62d0602a008c46089b842 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 8 Apr 2014 09:50:51 -0500 Subject: omap3: zoom1: enable CONFIG_SYS_GENERIC_BOARD CONFIG_SYS_GENERIC_BOARD should now be enabled for generic functionality Further information in doc/README.generic-board Signed-off-by: Nishanth Menon --- include/configs/omap3_zoom1.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index f0fa96efcb8..c4178d8c156 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -20,6 +20,7 @@ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */ #define CONFIG_OMAP_COMMON +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SDRC /* The chip has SDRC controller */ -- cgit v1.3.1 From 9d70e7728582836c7f09bc28a08f296566d17a53 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 8 Apr 2014 09:50:53 -0500 Subject: OMAP3: zoom1: enable LAN9211 Zoom1 was wrongly setup for LAN91C96. Fix it by enabling LAN9211. Signed-off-by: Nishanth Menon --- board/logicpd/zoom1/zoom1.c | 20 ++++++++++++++++++-- include/configs/omap3_zoom1.h | 10 +++++++++- 2 files changed, 27 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 56e512fe059..461a852724e 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -102,9 +102,25 @@ int board_mmc_init(bd_t *bis) int board_eth_init(bd_t *bis) { int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); + +#ifdef CONFIG_SMC911X +#define STR_ENV_ETHADDR "ethaddr" + + struct eth_device *dev; + uchar eth_addr[6]; + + rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); + if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) { + dev = eth_get_dev_by_index(0); + if (dev) { + eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr); + } else { + printf("zoom1: Couldn't get eth device\n"); + rc = -1; + } + } #endif + return rc; } #endif diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index c4178d8c156..4a4dfd96954 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -115,7 +115,7 @@ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ #undef CONFIG_CMD_IMI /* iminfo */ #undef CONFIG_CMD_IMLS /* List all found images */ -#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #undef CONFIG_CMD_NFS /* NFS support */ #define CONFIG_SYS_NO_FLASH @@ -265,4 +265,12 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 +#ifdef CONFIG_CMD_NET +/* Ethernet (LAN9211 from SMSC9118 family) */ +#define CONFIG_SMC911X +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE DEBUG_BASE + +#endif + #endif /* __CONFIG_H */ -- cgit v1.3.1 From d71dd0428c3b58be8de93b37f54fbf9c26b92eca Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 8 Apr 2014 09:50:54 -0500 Subject: omap3: zoom1: enable common network commands Basic networking commands for usability. Signed-off-by: Nishanth Menon --- include/configs/omap3_zoom1.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 4a4dfd96954..4fb36287086 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -116,7 +116,9 @@ #undef CONFIG_CMD_IMI /* iminfo */ #undef CONFIG_CMD_IMLS /* List all found images */ #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ -#undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_I2C -- cgit v1.3.1 From 4e8183b7d4afc4795712fc54a8aee07ab5108b26 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 8 Apr 2014 09:50:55 -0500 Subject: omap3: zoom1: disable JFFS2 and enable FS_GENERIC This is more in line with commits 664979a2a9f764b63b8094458b87247d254b0cc1(omap3_beagle: remove JFFS2 support.) and 102ce9ea7afdda80fe25aa786975e1722196bdb9 (omap3_beagle: enable CMD_FS_GENERIC and simplify load of image/ramdisk) CMD_FS_GENERIC allows us to simplify where we load up our image from either from ext2/fat etc. So, lets use that instead of cumbersome options we'd have to use. Sticking with existing conventions, defaults will be: bootfile=uImage bootpart=0:1 (first partition) bootdir=/ (/ in first partition) Signed-off-by: Nishanth Menon --- include/configs/omap3_zoom1.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 4fb36287086..110e3db9ddb 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -104,7 +104,13 @@ #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ +#define CONFIG_CMD_FS_GENERIC /* Generic FS support */ +#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ + "1920k(u-boot),128k(u-boot-env),"\ + "4m(kernel),-(fs)" #define CONFIG_CMD_I2C /* I2C serial bus support */ #define CONFIG_CMD_MMC /* MMC support */ @@ -143,19 +149,15 @@ /* CS0 */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ - /* partition */ /* Environment information */ #define CONFIG_BOOTDELAY 10 #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ + "bootfile=uImage\0" \ + "bootdir=/\0" \ + "bootpart=0:1\0" \ "usbtty=cdc_acm\0" \ "console=ttyS2,115200n8\0" \ "mmcdev=0\0" \ @@ -172,7 +174,7 @@ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ + "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ @@ -186,7 +188,7 @@ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ - "if run loaduimage; then " \ + "if run loadimage; then " \ "run mmcboot; " \ "else run nandboot; " \ "fi; " \ -- cgit v1.3.1 From c2e7c7b2d9c2ca9e087ab79d7da15f115ed7ed7f Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 8 Apr 2014 09:50:56 -0500 Subject: omap3: zoom1: enable bootz Boot from zImage and fdt_file if uImage is not available to maintain the legacy behavior. Signed-off-by: Nishanth Menon --- include/configs/omap3_zoom1.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 110e3db9ddb..477fb102d01 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -45,6 +45,7 @@ #define CONFIG_REVISION_TAG 1 #define CONFIG_OF_LIBFDT 1 +#define CONFIG_CMD_BOOTZ 1 /* * Size of malloc() pool @@ -155,7 +156,9 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ + "fdtaddr=0x80f80000\0" \ "bootfile=uImage\0" \ + "fdtfile=omap3-ldp.dtb\0" \ "bootdir=/\0" \ "bootpart=0:1\0" \ "usbtty=cdc_acm\0" \ @@ -175,9 +178,14 @@ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ + "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ + "loadzimage=setenv bootfile zImage; if run loadimage; then run loadfdt;fi\0"\ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ + "mmczboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootz ${loadaddr} - ${fdtaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ "nand read ${loadaddr} 280000 400000; " \ @@ -190,8 +198,10 @@ "else " \ "if run loadimage; then " \ "run mmcboot; " \ + "else if run loadzimage; then " \ + "run mmczboot; " \ "else run nandboot; " \ - "fi; " \ + "fi; fi;" \ "fi; " \ "else run nandboot; fi" -- cgit v1.3.1 From ea467c73ed7c0ecc663546cba6d3993c90558e29 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 8 Apr 2014 09:50:57 -0500 Subject: omap3: zoom1: fix default console We do not use ttyS2 anymore in Linux, it changed to ttyO2 a few years back. never too late to update. Signed-off-by: Nishanth Menon --- include/configs/omap3_zoom1.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 477fb102d01..4f933d9d7e4 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -162,7 +162,7 @@ "bootdir=/\0" \ "bootpart=0:1\0" \ "usbtty=cdc_acm\0" \ - "console=ttyS2,115200n8\0" \ + "console=ttyO2,115200n8\0" \ "mmcdev=0\0" \ "videomode=1024x768@60,vxres=1024,vyres=768\0" \ "videospec=omapfb:vram:2M,vram:4M\0" \ -- cgit v1.3.1 From 161d2d5ea8262e97cac77eec3ed7d32069cb7444 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 8 Apr 2014 09:50:58 -0500 Subject: omap3: zoom1: switch to generic ti_omap3_common config header ti_omap3_common contains a lot of common header definitions that help reduce the size of the zoom1 config file. So, use the generic header and customize as needed for the platform (example: no spl). Signed-off-by: Nishanth Menon --- board/logicpd/zoom1/config.mk | 1 - include/configs/omap3_zoom1.h | 124 ++++++------------------------------------ 2 files changed, 16 insertions(+), 109 deletions(-) (limited to 'include') diff --git a/board/logicpd/zoom1/config.mk b/board/logicpd/zoom1/config.mk index f5a19edd8f9..c7ebfd9e698 100644 --- a/board/logicpd/zoom1/config.mk +++ b/board/logicpd/zoom1/config.mk @@ -14,4 +14,3 @@ # (mem base + reserved) # For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index 4f933d9d7e4..7c5540ff660 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -16,16 +16,22 @@ /* * High Level Configuration Options */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */ -#define CONFIG_OMAP_COMMON #define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_SDRC /* The chip has SDRC controller */ - +#define CONFIG_NAND +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #include /* get chip and board defs */ #include +#include + +/* Remove SPL boot option - we do not support that on LDP yet */ +#undef CONFIG_SPL +#undef CONFIG_SPL_FRAMEWORK +#undef CONFIG_SPL_OS_BOOT + +/* Generic NAND definition conflicts with debug_base */ +#undef CONFIG_SYS_NAND_BASE /* * Display CPU and Board information @@ -33,58 +39,16 @@ #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - #define CONFIG_MISC_INIT_R -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_CMD_BOOTZ 1 - -/* - * Size of malloc() pool - */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) /* * Hardware drivers */ -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 /* UART3 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 @@ -100,23 +64,14 @@ #define CONFIG_USBD_MANUFACTURER "Texas Instruments" #define CONFIG_USBD_PRODUCT_NAME "Zoom1" -/* commands to include */ -#include - -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_FS_GENERIC /* Generic FS support */ -#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define MTDIDS_DEFAULT "nand0=nand" #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ "1920k(u-boot),128k(u-boot-env),"\ "4m(kernel),-(fs)" -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ -#define CONFIG_CMD_NAND /* NAND support */ +#if defined(CONFIG_CMD_NAND) #define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ +#endif #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ @@ -127,32 +82,24 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP -#define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_I2C -#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 -#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#undef CONFIG_SYS_I2C_OMAP24XX #define CONFIG_SYS_I2C_OMAP34XX /* * TWL4030 */ -#define CONFIG_TWL4030_POWER 1 #define CONFIG_TWL4030_LED 1 /* * Board NAND Info. */ -#define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand at */ /* CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ /* Environment information */ -#define CONFIG_BOOTDELAY 10 #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ @@ -205,50 +152,13 @@ "fi; " \ "else run nandboot; fi" -#define CONFIG_AUTO_COMPLETE 1 /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "OMAP3 Zoom1 # " -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ - /* works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1) /* memtest */ +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_2 + \ 0x01F00000) /* 31MB */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - /*----------------------------------------------------------------------- * FLASH and environment organization */ @@ -259,8 +169,6 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M #define PISMO1_ONEN_SIZE GPMC_SIZE_128M -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - #if defined(CONFIG_CMD_NAND) #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE #endif -- cgit v1.3.1 From 2e8f5dc16ad360cc15ea402a1dc4d421a04adbbd Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 17 Apr 2014 17:40:15 -0400 Subject: am43xx_evm: Drop SPI SPL QSPI booting on this board does not use SPL, so drop SPI-SPL related options. Signed-off-by: Tom Rini --- include/configs/am43xx_evm.h | 8 -------- 1 file changed, 8 deletions(-) (limited to 'include') diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 4e56ffce7aa..d5e6c4b0dc7 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -98,14 +98,6 @@ #define CONFIG_SF_DEFAULT_SPEED 48000000 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 -/* SPI SPL */ -#define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_FLASH_SUPPORT -#define CONFIG_SPL_SPI_BUS 0 -#define CONFIG_SPL_SPI_CS 0 -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 - /* Enhance our eMMC support / experience. */ #define CONFIG_CMD_GPT #define CONFIG_EFI_PARTITION -- cgit v1.3.1 From ac9ae1333ec09b279617395b7f6ac0c02001b464 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 10 Apr 2014 16:17:30 -0500 Subject: ARM: highbank: use config_distro_defaults.h Adapt highbank to use config_distro_defaults.h and remove the redundant defines. Signed-off-by: Rob Herring --- include/configs/highbank.h | 25 ++----------------------- 1 file changed, 2 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 7dbee3cdb99..f8794dce819 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -7,15 +7,15 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include + #define CONFIG_SYS_DCACHE_OFF #define CONFIG_SYS_THUMB_BUILD #define CONFIG_SYS_NO_FLASH -#define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP #define CONFIG_FIT -#define CONFIG_SUPPORT_RAW_INITRD #define CONFIG_SYS_BOOTMAPSZ (16 << 20) #define CONFIG_SYS_TIMER_RATE (150000000/256) @@ -48,35 +48,18 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION - #define CONFIG_CALXEDA_XGMAC -/* PXE support */ -#define CONFIG_BOOTP_PXE -#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 -#define CONFIG_BOOTP_VCI_STRING "U-boot.armv7.highbank" - /* * Command line configuration. */ #include #define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF #define CONFIG_CMD_MEMORY #define CONFIG_CMD_LOADS #define CONFIG_CMD_SCSI -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_EXT4 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#define CONFIG_BOOTDELAY 2 #define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_RESET_TO_RETRY #define CONFIG_AUTOBOOT_KEYED @@ -85,14 +68,10 @@ /* * Miscellaneous configurable options */ -#define CONFIG_CMDLINE_EDITING -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_PROMPT "Highbank #" -#define CONFIG_SYS_HUSH_PARSER /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT)+16) -- cgit v1.3.1 From 7904b70885f3c589c239f6ac978f299a6744557f Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 10 Apr 2014 16:17:31 -0500 Subject: ARM: highbank: use default prompt Since highbank is actually shared between Highbank and Midway platforms, remove the Highbank name from the prompt and use the default. Signed-off-by: Rob Herring --- include/configs/highbank.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/highbank.h b/include/configs/highbank.h index f8794dce819..a6202cfab44 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -71,7 +71,6 @@ #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PROMPT "Highbank #" /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT)+16) -- cgit v1.3.1 From 264e0e591bbd1c66d6bd5fb8f2438f17c3ba17ea Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Fri, 18 Apr 2014 11:15:55 -0600 Subject: config: enable CMD_BMP when API+LCD is enabled When both CONFIG_API and CONFIG_LCD are enabled, the API code calls lcd_display_bitmap(). That isn't compiled unless either CONFIG_CMD_BMP or CONFIG_SPLASH_SCREEN is enabled. In order to prevent build problems, have config_fallbacks.h enable CONFIG_CMD_BMP when both API and LCD are enabled. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass --- include/config_fallbacks.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/config_fallbacks.h b/include/config_fallbacks.h index e6fb47be0bd..b304a4103de 100644 --- a/include/config_fallbacks.h +++ b/include/config_fallbacks.h @@ -71,6 +71,10 @@ #define CONFIG_LIB_RAND #endif +#if defined(CONFIG_API) && defined(CONFIG_LCD) +#define CONFIG_CMD_BMP +#endif + #ifndef CONFIG_SYS_PROMPT #define CONFIG_SYS_PROMPT "=> " #endif -- cgit v1.3.1 From ad0e4639545b0928a3673114962ee1f3e56402d7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 22 Mar 2014 17:12:58 -0600 Subject: sandbox: Provide a build option to avoid using SDL Some machines do not have SDL libraries installed, and it is still useful to build sandbox without LCD/keyboard support. Add an option for this, used as follows: make sandbox_config all NO_SDL=1 Signed-off-by: Simon Glass --- arch/sandbox/config.mk | 6 ++++++ include/configs/sandbox.h | 16 ++++++++++++++-- 2 files changed, 20 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index e094ae2d053..c3f889fb1cb 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -18,3 +18,9 @@ cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map CONFIG_ARCH_DEVICE_TREE := sandbox + +# Define this to avoid linking with SDL, which requires SDL libraries +# This can solve 'sdl-config: Command not found' errors +ifneq ($(NO_SDL),) +PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL +endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index fa62cb6cd5b..6bb2546eda5 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -140,8 +140,6 @@ #define CONFIG_CROS_EC #define CONFIG_CMD_CROS_EC #define CONFIG_CROS_EC_SANDBOX -#define CONFIG_KEYBOARD -#define CONFIG_CROS_EC_KEYB #define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_BOARD_LATE_INIT @@ -149,7 +147,12 @@ #define CONFIG_SOUND_SANDBOX #define CONFIG_CMD_SOUND +#ifndef SANDBOX_NO_SDL #define CONFIG_SANDBOX_SDL +#endif + +/* LCD and keyboard require SDL support */ +#ifdef CONFIG_SANDBOX_SDL #define CONFIG_LCD #define CONFIG_VIDEO_SANDBOX_SDL #define CONFIG_CMD_BMP @@ -158,9 +161,18 @@ #define CONFIG_SYS_CONSOLE_IS_IN_ENV #define LCD_BPP LCD_COLOR16 +#define CONFIG_CROS_EC_KEYB +#define CONFIG_KEYBOARD + #define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial,cros-ec-keyb\0" \ "stdout=serial,lcd\0" \ "stderr=serial,lcd\0" +#else + +#define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" +#endif #define CONFIG_GZIP_COMPRESSED #define CONFIG_BZIP2 -- cgit v1.3.1 From 8e2615752ee6d5daf8ce2e1e599a0512750f24b9 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 4 Apr 2014 20:09:58 +0900 Subject: bd_info: remove bi_barudrate member from struct bd_info gd->bd->bi_baudrate is a copy of gd->baudrate. Since baudrate is a common feature for all architectures, keep gd->baudrate only. It is true that bi_baudrate was passed to the kernel in that structure but it was a long time ago. Signed-off-by: Masahiro Yamada Cc: Tom Rini Cc: Simon Glass Cc: Wolfgang Denk Cc: Heiko Schocher Acked-by: Michal Simek (For microblaze) --- arch/arm/include/asm/u-boot.h | 1 - arch/arm/lib/board.c | 1 - arch/avr32/include/asm/u-boot.h | 1 - arch/avr32/lib/board.c | 1 - arch/blackfin/include/asm/u-boot.h | 1 - arch/blackfin/lib/board.c | 2 -- arch/m68k/include/asm/u-boot.h | 1 - arch/m68k/lib/board.c | 1 - arch/microblaze/include/asm/u-boot.h | 1 - arch/microblaze/lib/board.c | 1 - arch/mips/include/asm/u-boot.h | 1 - arch/mips/lib/board.c | 1 - arch/nds32/include/asm/u-boot.h | 1 - arch/nds32/lib/board.c | 1 - arch/nios2/include/asm/u-boot.h | 1 - arch/nios2/lib/board.c | 1 - arch/openrisc/include/asm/u-boot.h | 1 - arch/openrisc/lib/board.c | 1 - arch/powerpc/cpu/mpc85xx/fdt.c | 2 +- arch/powerpc/include/asm/u-boot.h | 1 - arch/powerpc/lib/board.c | 1 - arch/sh/include/asm/u-boot.h | 1 - arch/sh/lib/board.c | 1 - arch/sparc/include/asm/u-boot.h | 1 - arch/sparc/lib/board.c | 1 - board/muas3001/muas3001.c | 4 +++- board/mvblue/mvblue.c | 5 ++--- common/board_f.c | 9 --------- common/cmd_bdinfo.c | 28 ++++++++++++++-------------- drivers/serial/serial.c | 10 +++------- include/asm-generic/u-boot.h | 1 - 31 files changed, 23 insertions(+), 61 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h index cb81232b832..43cc4946838 100644 --- a/arch/arm/include/asm/u-boot.h +++ b/arch/arm/include/asm/u-boot.h @@ -27,7 +27,6 @@ #ifndef __ASSEMBLY__ typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ ulong bi_arch_number; /* unique id for this board */ ulong bi_boot_params; /* where this board expects params */ unsigned long bi_arm_freq; /* arm frequency */ diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 92e85c4db51..9b473b5eaba 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -445,7 +445,6 @@ void board_init_f(ulong bootflag) post_run(NULL, POST_ROM | post_bootmode_get(0)); #endif - gd->bd->bi_baudrate = gd->baudrate; /* Ram ist board specific, so move it to board code ... */ dram_init_banksize(); display_dram_config(); /* and display it */ diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h index bff17d5ed26..6aef8087490 100644 --- a/arch/avr32/include/asm/u-boot.h +++ b/arch/avr32/include/asm/u-boot.h @@ -7,7 +7,6 @@ #define __ASM_U_BOOT_H__ 1 typedef struct bd_info { - unsigned int bi_baudrate; unsigned char bi_phy_id[4]; unsigned long bi_board_number; void *bi_boot_params; diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index 28c2ec09efd..7680102f523 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -220,7 +220,6 @@ void board_init_f(ulong board_type) */ bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; bd->bi_dram[0].size = sdram_size; - bd->bi_baudrate = gd->baudrate; memcpy(new_gd, gd, sizeof(gd_t)); diff --git a/arch/blackfin/include/asm/u-boot.h b/arch/blackfin/include/asm/u-boot.h index fc36ced519e..acaeee9053e 100644 --- a/arch/blackfin/include/asm/u-boot.h +++ b/arch/blackfin/include/asm/u-boot.h @@ -13,7 +13,6 @@ #define _U_BOOT_H_ 1 typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ phys_size_t bi_memsize; /* size of DRAM memory in bytes */ diff --git a/arch/blackfin/lib/board.c b/arch/blackfin/lib/board.c index 62342014a47..87842557dfd 100644 --- a/arch/blackfin/lib/board.c +++ b/arch/blackfin/lib/board.c @@ -69,7 +69,6 @@ static int display_banner(void) static int init_baudrate(void) { gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); - gd->bd->bi_baudrate = gd->baudrate; return 0; } @@ -92,7 +91,6 @@ static void display_global_data(void) printf(" |-env_valid: %lx\n", gd->env_valid); printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt)); printf(" \\-bd: %p\n", gd->bd); - printf(" |-bi_baudrate: %x\n", bd->bi_baudrate); printf(" |-bi_boot_params: %lx\n", bd->bi_boot_params); printf(" |-bi_memstart: %lx\n", bd->bi_memstart); printf(" |-bi_memsize: %lx\n", bd->bi_memsize); diff --git a/arch/m68k/include/asm/u-boot.h b/arch/m68k/include/asm/u-boot.h index 99de31aff5f..983cb2d9671 100644 --- a/arch/m68k/include/asm/u-boot.h +++ b/arch/m68k/include/asm/u-boot.h @@ -44,7 +44,6 @@ typedef struct bd_info { unsigned long bi_vcofreq; /* vco Freq in MHz */ unsigned long bi_flbfreq; /* Flexbus Freq in MHz */ #endif - unsigned int bi_baudrate; /* Console Baudrate */ } bd_t; #endif /* __ASSEMBLY__ */ diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index e75b6a98dd5..318ca01ea7f 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -342,7 +342,6 @@ board_init_f (ulong bootflag) bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */ bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */ #endif - bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ #ifdef CONFIG_SYS_EXTBDINFO strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version)); diff --git a/arch/microblaze/include/asm/u-boot.h b/arch/microblaze/include/asm/u-boot.h index ab3f23202d6..54d415ebb5b 100644 --- a/arch/microblaze/include/asm/u-boot.h +++ b/arch/microblaze/include/asm/u-boot.h @@ -24,7 +24,6 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned int bi_baudrate; /* Console Baudrate */ ulong bi_boot_params; /* where this board expects params */ } bd_t; diff --git a/arch/microblaze/lib/board.c b/arch/microblaze/lib/board.c index fafeeaebd63..600c80ab766 100644 --- a/arch/microblaze/lib/board.c +++ b/arch/microblaze/lib/board.c @@ -78,7 +78,6 @@ void board_init_f(ulong not_used) memset((void *)bd, 0, GENERATED_BD_INFO_SIZE); gd->bd = bd; gd->baudrate = CONFIG_BAUDRATE; - bd->bi_baudrate = CONFIG_BAUDRATE; bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h index 0eb170ded8e..4909a2a5c4b 100644 --- a/arch/mips/include/asm/u-boot.h +++ b/arch/mips/include/asm/u-boot.h @@ -23,7 +23,6 @@ #else /* !CONFIG_SYS_GENERIC_BOARD */ typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index 3200d87e30a..3feb0207120 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -204,7 +204,6 @@ void board_init_f(ulong bootflag) */ bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM */ bd->bi_memsize = gd->ram_size; /* size of DRAM in bytes */ - bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ memcpy(id, (void *)gd, sizeof(gd_t)); diff --git a/arch/nds32/include/asm/u-boot.h b/arch/nds32/include/asm/u-boot.h index 8170d28f7c2..44e72d414b9 100644 --- a/arch/nds32/include/asm/u-boot.h +++ b/arch/nds32/include/asm/u-boot.h @@ -23,7 +23,6 @@ #include typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c index 2d4c6231a37..4c06a4866b1 100644 --- a/arch/nds32/lib/board.c +++ b/arch/nds32/lib/board.c @@ -255,7 +255,6 @@ void board_init_f(ulong bootflag) addr_sp &= ~0x07; debug("New Stack Pointer is: %08lx\n", addr_sp); - gd->bd->bi_baudrate = gd->baudrate; /* Ram isn't board specific, so move it to board code ... */ dram_init_banksize(); display_dram_config(); /* and display it */ diff --git a/arch/nios2/include/asm/u-boot.h b/arch/nios2/include/asm/u-boot.h index 6849b4ae9f2..51f6c30ef76 100644 --- a/arch/nios2/include/asm/u-boot.h +++ b/arch/nios2/include/asm/u-boot.h @@ -23,7 +23,6 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned int bi_baudrate; /* Console Baudrate */ } bd_t; /* For image.h:image_check_target_arch() */ diff --git a/arch/nios2/lib/board.c b/arch/nios2/lib/board.c index bb1a8a73407..f24218ff1c1 100644 --- a/arch/nios2/lib/board.c +++ b/arch/nios2/lib/board.c @@ -92,7 +92,6 @@ void board_init(void) bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; #endif - bd->bi_baudrate = CONFIG_BAUDRATE; for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { WATCHDOG_RESET(); diff --git a/arch/openrisc/include/asm/u-boot.h b/arch/openrisc/include/asm/u-boot.h index 5c288a85ffc..cdb8ff996ed 100644 --- a/arch/openrisc/include/asm/u-boot.h +++ b/arch/openrisc/include/asm/u-boot.h @@ -16,7 +16,6 @@ #define _U_BOOT_H_ typedef struct bd_info { - unsigned int bi_baudrate; /* serial console baudrate */ unsigned long bi_arch_number; /* unique id for this board */ unsigned long bi_boot_params; /* where this board expects params */ unsigned long bi_memstart; /* start of DRAM memory */ diff --git a/arch/openrisc/lib/board.c b/arch/openrisc/lib/board.c index 391d1e19c51..234668538ca 100644 --- a/arch/openrisc/lib/board.c +++ b/arch/openrisc/lib/board.c @@ -84,7 +84,6 @@ void board_init(void) bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; #endif - bd->bi_baudrate = CONFIG_BAUDRATE; for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { WATCHDOG_RESET(); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 0cc21c7f680..ed80a841804 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -674,7 +674,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_CPM2 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart", - "current-speed", bd->bi_baudrate, 1); + "current-speed", gd->baudrate, 1); do_fixup_by_compat_u32(blob, "fsl,cpm2-brg", "clock-frequency", bd->bi_brgfreq, 1); diff --git a/arch/powerpc/include/asm/u-boot.h b/arch/powerpc/include/asm/u-boot.h index f4d4a6b3003..e1b566fa568 100644 --- a/arch/powerpc/include/asm/u-boot.h +++ b/arch/powerpc/include/asm/u-boot.h @@ -64,7 +64,6 @@ typedef struct bd_info { unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ #endif - unsigned int bi_baudrate; /* Console Baudrate */ #if defined(CONFIG_405) || \ defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || \ diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 8b03d3aa07b..57b4a09b04e 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -547,7 +547,6 @@ void board_init_f(ulong bootflag) bd->bi_ipbfreq = gd->arch.ipb_clk; bd->bi_pcifreq = gd->pci_clk; #endif /* CONFIG_MPC5xxx */ - bd->bi_baudrate = gd->baudrate; /* Console Baudrate */ #ifdef CONFIG_SYS_EXTBDINFO strncpy((char *) bd->bi_s_version, "1.2", sizeof(bd->bi_s_version)); diff --git a/arch/sh/include/asm/u-boot.h b/arch/sh/include/asm/u-boot.h index 81d51612824..ea37c244970 100644 --- a/arch/sh/include/asm/u-boot.h +++ b/arch/sh/include/asm/u-boot.h @@ -20,7 +20,6 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned int bi_baudrate; /* Console Baudrate */ unsigned long bi_boot_params; /* where this board expects params */ } bd_t; diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 8498153d4ea..1eb7afb89e5 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -155,7 +155,6 @@ void sh_generic_init(void) bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; #endif - bd->bi_baudrate = CONFIG_BAUDRATE; for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { WATCHDOG_RESET(); diff --git a/arch/sparc/include/asm/u-boot.h b/arch/sparc/include/asm/u-boot.h index 66cf4b023d6..5f12e581316 100644 --- a/arch/sparc/include/asm/u-boot.h +++ b/arch/sparc/include/asm/u-boot.h @@ -40,7 +40,6 @@ typedef struct bd_info { unsigned short bi_ethspeed; /* Ethernet speed in Mbps */ unsigned long bi_intfreq; /* Internal Freq, in MHz */ unsigned long bi_busfreq; /* Bus Freq, in MHz */ - unsigned int bi_baudrate; /* Console Baudrate */ } bd_t; #endif /* __ASSEMBLY__ */ diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c index c778ba26e73..b311a946c05 100644 --- a/arch/sparc/lib/board.c +++ b/arch/sparc/lib/board.c @@ -173,7 +173,6 @@ void board_init_f(ulong bootflag) bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; #endif - bd->bi_baudrate = CONFIG_BAUDRATE; bd->bi_bootflags = bootflag; /* boot / reboot flag (for LynxOS) */ gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c index 42b0a035c7d..08eb5e82903 100644 --- a/board/muas3001/muas3001.c +++ b/board/muas3001/muas3001.c @@ -286,6 +286,8 @@ int board_early_init_r (void) } #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +DECLARE_GLOBAL_DATA_PTR; + /* * update "memory" property in the blob */ @@ -314,7 +316,7 @@ void ft_blob_update (void *blob, bd_t *bd) /* baudrate */ nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial"); if (nodeoffset >= 0) { - speed = cpu_to_be32 (bd->bi_baudrate); + speed = cpu_to_be32 (gd->baudrate); ret = fdt_setprop (blob, nodeoffset, "current-speed", &speed, sizeof (unsigned long)); if (ret < 0) diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c index 69abb06251e..63503e89da1 100644 --- a/board/mvblue/mvblue.c +++ b/board/mvblue/mvblue.c @@ -58,7 +58,6 @@ int checkboard (void) u32 BoardType = get_BoardType (); char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" }; char *p; - bd_t *bd = gd->bd; hw_watchdog_reset (); @@ -71,8 +70,8 @@ int checkboard (void) if ((p = getenv ("console_nr")) != NULL) { unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3; - bd->bi_baudrate &= ~3; - bd->bi_baudrate |= con_nr & 3; + gd->baudrate &= ~3; + gd->baudrate |= con_nr & 3; } return 0; } diff --git a/common/board_f.c b/common/board_f.c index cbdf06f812e..aea6bff5551 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -708,14 +708,6 @@ static int init_post(void) } #endif -static int setup_baud_rate(void) -{ - /* Ick, can we get rid of this line? */ - gd->bd->bi_baudrate = gd->baudrate; - - return 0; -} - static int setup_dram_config(void) { /* Ram is board specific, so move it to board code ... */ @@ -954,7 +946,6 @@ static init_fnc_t init_sequence_f[] = { INIT_FUNC_WATCHDOG_RESET setup_board_part2, #endif - setup_baud_rate, display_new_sp, #ifdef CONFIG_SYS_EXTBDINFO setup_board_extra, diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 238cadb1e1f..f283a1616e9 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -148,7 +148,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_mhz("ethspeed", bd->bi_ethspeed); #endif printf("IP addr = %s\n", getenv("ipaddr")); - printf("baudrate = %6u bps\n", bd->bi_baudrate); + printf("baudrate = %6u bps\n", gd->baudrate); print_num("relocaddr", gd->relocaddr); board_detail(); return 0; @@ -176,7 +176,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -198,7 +198,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_CMD_NET) print_eths(); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -231,7 +231,7 @@ int do_bdinfo(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %6u bps\n", bd->bi_baudrate); + printf("baudrate = %6u bps\n", gd->baudrate); return 0; } @@ -277,7 +277,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -304,7 +304,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -324,7 +324,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -344,7 +344,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -368,7 +368,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_CMD_NET) print_eths(); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) print_num("TLB addr", gd->arch.tlb_addr); #endif @@ -406,7 +406,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -440,7 +440,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); print_mhz("ethspeed", bd->bi_ethspeed); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -490,7 +490,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -512,7 +512,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %u bps\n", bd->bi_baudrate); + printf("baudrate = %u bps\n", gd->baudrate); return 0; } @@ -530,7 +530,7 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) print_eth(0); printf("ip_addr = %s\n", getenv("ipaddr")); #endif - printf("baudrate = %d bps\n", bd->bi_baudrate); + printf("baudrate = %d bps\n", gd->baudrate); return 0; } diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index c4fb59cfb31..fd61a5e5458 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -74,9 +74,6 @@ static int on_baudrate(const char *name, const char *value, enum env_op op, } gd->baudrate = baudrate; -#if defined(CONFIG_PPC) || defined(CONFIG_MCF52x2) - gd->bd->bi_baudrate = baudrate; -#endif serial_setbrg(); @@ -502,12 +499,11 @@ int uart_post_test(int flags) unsigned char c; int ret, saved_baud, b; struct serial_device *saved_dev, *s; - bd_t *bd = gd->bd; /* Save current serial state */ ret = 0; saved_dev = serial_current; - saved_baud = bd->bi_baudrate; + saved_baud = gd->baudrate; for (s = serial_devices; s; s = s->next) { /* If this driver doesn't support loop back, skip it */ @@ -530,7 +526,7 @@ int uart_post_test(int flags) /* Test every available baud rate */ for (b = 0; b < ARRAY_SIZE(bauds); ++b) { - bd->bi_baudrate = bauds[b]; + gd->baudrate = bauds[b]; serial_setbrg(); /* @@ -572,7 +568,7 @@ int uart_post_test(int flags) done: /* Restore previous serial state */ serial_current = saved_dev; - bd->bi_baudrate = saved_baud; + gd->baudrate = saved_baud; serial_reinit_all(); serial_setbrg(); diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index c18e4ca27a3..62cb1eabc1f 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -66,7 +66,6 @@ typedef struct bd_info { unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */ unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */ #endif - unsigned int bi_baudrate; /* Console Baudrate */ #if defined(CONFIG_405) || \ defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || \ -- cgit v1.3.1 From d57dee5787ad96d2c80bf36f443276592d39ee21 Mon Sep 17 00:00:00 2001 From: "Karicheri, Muralidharan" Date: Wed, 9 Apr 2014 15:38:46 -0400 Subject: serial: nsl16550: add hw flow control support keystone serial hw support hw flow control. This patch enables hw flow control for keystone EVMs as an optional feature based on CONFIG_SERIAL_HW_FLOW_CONTROL. Signed-off-by: Murali Karicheri --- README | 4 ++++ drivers/serial/ns16550.c | 6 ++++++ include/ns16550.h | 1 + 3 files changed, 11 insertions(+) (limited to 'include') diff --git a/README b/README index 80a1bfaad2a..61c2caca316 100644 --- a/README +++ b/README @@ -751,6 +751,10 @@ The following options need to be configured: boot loader that has already initialized the UART. Define this variable to flush the UART at init time. + CONFIG_SERIAL_HW_FLOW_CONTROL + + Define this variable to enable hw flow control in serial driver. + Current user of this option is drivers/serial/nsl16550.c driver - Console Interface: Depending on board, define exactly one serial port diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 8a134549433..f26979dbe15 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -33,6 +33,12 @@ #if defined(CONFIG_K2HK_EVM) #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 #define UART_REG_VAL_PWREMU_MGMT_UART_ENABLE ((1 << 14) | (1 << 13) | (1 << 0)) +#undef UART_MCRVAL +#ifdef CONFIG_SERIAL_HW_FLOW_CONTROL +#define UART_MCRVAL (UART_MCR_RTS | UART_MCR_AFE) +#else +#define UART_MCRVAL (UART_MCR_RTS) +#endif #endif #ifndef CONFIG_SYS_NS16550_IER diff --git a/include/ns16550.h b/include/ns16550.h index 51cb5b4a66d..17f829f6f9b 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -100,6 +100,7 @@ typedef struct NS16550 *NS16550_t; #define UART_MCR_OUT1 0x04 /* Out 1 */ #define UART_MCR_OUT2 0x08 /* Out 2 */ #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ #define UART_MCR_DMA_EN 0x04 #define UART_MCR_TX_DFR 0x08 -- cgit v1.3.1 From c85bb5a01a5a87c4937665816b17e281f9552413 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 18 Apr 2014 19:09:47 +0900 Subject: rand: do not surround function declarations by #ifdef Signed-off-by: Masahiro Yamada --- include/common.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index 5fb0bb2d3d4..2adf5f90b8c 100644 --- a/include/common.h +++ b/include/common.h @@ -820,12 +820,10 @@ char * strmhz(char *buf, unsigned long hz); #include /* lib/rand.c */ -#if defined(CONFIG_LIB_RAND) || defined(CONFIG_LIB_HW_RAND) #define RAND_MAX -1U void srand(unsigned int seed); unsigned int rand(void); unsigned int rand_r(unsigned int *seedp); -#endif /* common/console.c */ int console_init_f(void); /* Before relocation; uses the serial stuff */ -- cgit v1.3.1 From da384a9d7628c77140023e7c095f79ecfe5a4e2d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 18 Apr 2014 19:09:48 +0900 Subject: net: rename and refactor eth_rand_ethaddr() function Some functions in include/net.h are ported from include/linux/etherdevice.h of Linux Kernel. For ex. is_zero_ether_addr() is_multicast_ether_addr() is_broadcast_ether_addr() is_valid_ether_addr(); So, we should use the same function name as that of Linux Kernel, eth_rand_addr(), for consistency. Besides, eth_rand_addr() has been implemented as an inline function. So it should not be surrounded by #ifdef CONFIG_RANDOM_MACADDR. Signed-off-by: Masahiro Yamada Acked-by: Joe Hershberger --- board/buffalo/lsxl/lsxl.c | 2 +- drivers/net/dm9000x.c | 2 +- drivers/net/ftmac110.c | 2 +- include/net.h | 36 +++++++++++++++++++----------------- net/eth.c | 22 ---------------------- 5 files changed, 22 insertions(+), 42 deletions(-) (limited to 'include') diff --git a/board/buffalo/lsxl/lsxl.c b/board/buffalo/lsxl/lsxl.c index eca1683a6fe..659a124b227 100644 --- a/board/buffalo/lsxl/lsxl.c +++ b/board/buffalo/lsxl/lsxl.c @@ -231,7 +231,7 @@ static void rescue_mode(void) printf("Entering rescue mode..\n"); #ifdef CONFIG_RANDOM_MACADDR if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { - eth_random_enetaddr(enetaddr); + eth_random_addr(enetaddr); if (eth_setenv_enetaddr("ethaddr", enetaddr)) { printf("Failed to set ethernet address\n"); set_led(LED_ALARM_BLINKING); diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index b68d808c742..4de9d41642e 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -345,7 +345,7 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd) if (!is_valid_ether_addr(dev->enetaddr)) { #ifdef CONFIG_RANDOM_MACADDR printf("Bad MAC address (uninitialized EEPROM?), randomizing\n"); - eth_random_enetaddr(dev->enetaddr); + eth_random_addr(dev->enetaddr); printf("MAC: %pM\n", dev->enetaddr); #else printf("WARNING: Bad MAC address (uninitialized EEPROM?)\n"); diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c index 8eee272cf14..98c4f09629b 100644 --- a/drivers/net/ftmac110.c +++ b/drivers/net/ftmac110.c @@ -425,7 +425,7 @@ int ftmac110_initialize(bd_t *bis) dev->recv = ftmac110_recv; if (!eth_getenv_enetaddr_by_index("eth", card_nr, dev->enetaddr)) - eth_random_enetaddr(dev->enetaddr); + eth_random_addr(dev->enetaddr); /* allocate tx descriptors (it must be 16 bytes aligned) */ chip->txd = dma_alloc_coherent( diff --git a/include/net.h b/include/net.h index 0802fad8761..735b0b9d26f 100644 --- a/include/net.h +++ b/include/net.h @@ -130,23 +130,6 @@ extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr); extern int eth_getenv_enetaddr_by_index(const char *base_name, int index, uchar *enetaddr); -#ifdef CONFIG_RANDOM_MACADDR -/* - * The u-boot policy does not allow hardcoded ethernet addresses. Under the - * following circumstances a random generated address is allowed: - * - in emergency cases, where you need a working network connection to set - * the ethernet address. - * Eg. you want a rescue boot and don't have a serial port to access the - * CLI to set environment variables. - * - * In these cases, we generate a random locally administered ethernet address. - * - * Args: - * enetaddr - returns 6 byte hardware address - */ -extern void eth_random_enetaddr(uchar *enetaddr); -#endif - extern int usb_eth_initialize(bd_t *bi); extern int eth_init(bd_t *bis); /* Initialize the device */ extern int eth_send(void *packet, int length); /* Send a packet */ @@ -674,6 +657,25 @@ static inline int is_valid_ether_addr(const u8 *addr) return !is_multicast_ether_addr(addr) && !is_zero_ether_addr(addr); } +/** + * eth_random_addr - Generate software assigned random Ethernet address + * @addr: Pointer to a six-byte array containing the Ethernet address + * + * Generate a random Ethernet address (MAC) that is not multicast + * and has the local assigned bit set. + */ +static inline void eth_random_addr(uchar *addr) +{ + int i; + unsigned int seed = get_timer(0); + + for (i = 0; i < 6; i++) + addr[i] = rand_r(&seed); + + addr[0] &= 0xfe; /* clear multicast bit */ + addr[0] |= 0x02; /* set local assignment bit (IEEE802) */ +} + /* Convert an IP address to a string */ extern void ip_to_string(IPaddr_t x, char *s); diff --git a/net/eth.c b/net/eth.c index 32bd10c8290..99386e3e631 100644 --- a/net/eth.c +++ b/net/eth.c @@ -63,28 +63,6 @@ static int eth_mac_skip(int index) return ((skip_state = getenv(enetvar)) != NULL); } -#ifdef CONFIG_RANDOM_MACADDR -void eth_random_enetaddr(uchar *enetaddr) -{ - uint32_t rval; - - srand(get_timer(0)); - - rval = rand(); - enetaddr[0] = rval & 0xff; - enetaddr[1] = (rval >> 8) & 0xff; - enetaddr[2] = (rval >> 16) & 0xff; - - rval = rand(); - enetaddr[3] = rval & 0xff; - enetaddr[4] = (rval >> 8) & 0xff; - enetaddr[5] = (rval >> 16) & 0xff; - - /* make sure it's local and unicast */ - enetaddr[0] = (enetaddr[0] | 0x02) & ~0x01; -} -#endif - /* * CPU and board-specific Ethernet initializations. Aliased function * signals caller to move on -- cgit v1.3.1 From c42f56d96d1ec642496ee0fdf741dc13fbbec2e2 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 18 Apr 2014 19:09:49 +0900 Subject: blackfin: replace bfin_gen_rand_mac() with eth_random_addr() bfin_gen_rand_mac() uses __DATE__ as the seed for random ethernet address. This makes the build non-deterministic. In the first place, it should not be implemented as a Bfin-specific function. Use eth_random_addr() instead. Signed-off-by: Masahiro Yamada Cc: Sonic Zhang --- arch/blackfin/include/asm/net.h | 28 ---------------------------- board/bct-brettl2/bct-brettl2.c | 3 +-- board/bf518f-ezbrd/bf518f-ezbrd.c | 3 +-- board/bf526-ezbrd/bf526-ezbrd.c | 3 +-- board/bf527-ezkit/bf527-ezkit.c | 3 +-- board/bf537-minotaur/bf537-minotaur.c | 3 +-- board/bf537-pnav/bf537-pnav.c | 3 +-- board/bf537-srv1/bf537-srv1.c | 3 +-- board/bf537-stamp/bf537-stamp.c | 3 +-- board/cm-bf527/cm-bf527.c | 3 +-- board/cm-bf537e/cm-bf537e.c | 3 +-- board/cm-bf537u/cm-bf537u.c | 3 +-- board/dnp5370/dnp5370.c | 3 +-- board/ip04/ip04.c | 3 +-- board/tcm-bf518/tcm-bf518.c | 3 +-- board/tcm-bf537/tcm-bf537.c | 3 +-- include/configs/bct-brettl2.h | 1 + include/configs/bf518f-ezbrd.h | 2 +- include/configs/bf526-ezbrd.h | 2 +- include/configs/bf527-ezkit.h | 2 +- include/configs/bf537-minotaur.h | 1 + include/configs/bf537-pnav.h | 2 +- include/configs/bf537-srv1.h | 2 +- include/configs/bf537-stamp.h | 2 +- include/configs/cm-bf527.h | 2 +- include/configs/cm-bf537e.h | 2 +- include/configs/cm-bf537u.h | 2 +- include/configs/dnp5370.h | 2 ++ include/configs/ip04.h | 1 + include/configs/tcm-bf518.h | 2 +- include/configs/tcm-bf537.h | 2 +- 31 files changed, 31 insertions(+), 69 deletions(-) delete mode 100644 arch/blackfin/include/asm/net.h (limited to 'include') diff --git a/arch/blackfin/include/asm/net.h b/arch/blackfin/include/asm/net.h deleted file mode 100644 index 97cb46691e4..00000000000 --- a/arch/blackfin/include/asm/net.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * net.h - misc Blackfin network helpers - * - * Copyright (c) 2008-2009 Analog Devices Inc. - * - * Licensed under the GPL-2 or later. - */ - -#ifndef __ASM_BFIN_RAND_MAC__ -#define __ASM_BFIN_RAND_MAC__ - -/* If the board does not have a real MAC assigned to it, then generate a - * locally administrated pseudo-random one based on CYCLES and compile date. - */ -static inline void bfin_gen_rand_mac(uchar *mac_addr) -{ - /* make something up */ - const char s[] = __DATE__; - size_t i; - u32 cycles; - for (i = 0; i < 6; ++i) { - asm("%0 = CYCLES;" : "=r" (cycles)); - mac_addr[i] = cycles ^ s[i]; - } - mac_addr[0] = (mac_addr[0] | 0x02) & ~0x01; /* make it local unicast */ -} - -#endif diff --git a/board/bct-brettl2/bct-brettl2.c b/board/bct-brettl2/bct-brettl2.c index de5b9ff0e75..6be9b180159 100644 --- a/board/bct-brettl2/bct-brettl2.c +++ b/board/bct-brettl2/bct-brettl2.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -33,7 +32,7 @@ int checkboard(void) static void board_init_enetaddr(uchar *mac_addr) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); eth_setenv_enetaddr("ethaddr", mac_addr); } diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c index 09a2353e7d9..3a94a572eb2 100644 --- a/board/bf518f-ezbrd/bf518f-ezbrd.c +++ b/board/bf518f-ezbrd/bf518f-ezbrd.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -48,7 +47,7 @@ static void board_init_enetaddr(uchar *mac_addr) if (!valid_mac) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); } eth_setenv_enetaddr("ethaddr", mac_addr); diff --git a/board/bf526-ezbrd/bf526-ezbrd.c b/board/bf526-ezbrd/bf526-ezbrd.c index 4695b1161a0..368d6be25fb 100644 --- a/board/bf526-ezbrd/bf526-ezbrd.c +++ b/board/bf526-ezbrd/bf526-ezbrd.c @@ -12,7 +12,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -45,7 +44,7 @@ static void board_init_enetaddr(uchar *mac_addr) if (!valid_mac) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); } eth_setenv_enetaddr("ethaddr", mac_addr); diff --git a/board/bf527-ezkit/bf527-ezkit.c b/board/bf527-ezkit/bf527-ezkit.c index 211cf24ac30..88e18690e03 100644 --- a/board/bf527-ezkit/bf527-ezkit.c +++ b/board/bf527-ezkit/bf527-ezkit.c @@ -13,7 +13,6 @@ #include #include #include -#include #include DECLARE_GLOBAL_DATA_PTR; @@ -47,7 +46,7 @@ static void board_init_enetaddr(uchar *mac_addr) if (!valid_mac) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); } eth_setenv_enetaddr("ethaddr", mac_addr); diff --git a/board/bf537-minotaur/bf537-minotaur.c b/board/bf537-minotaur/bf537-minotaur.c index 920429c12e6..ca61ef97b86 100644 --- a/board/bf537-minotaur/bf537-minotaur.c +++ b/board/bf537-minotaur/bf537-minotaur.c @@ -12,7 +12,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -27,7 +26,7 @@ int checkboard(void) static void board_init_enetaddr(uchar *mac_addr) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); eth_setenv_enetaddr("ethaddr", mac_addr); } diff --git a/board/bf537-pnav/bf537-pnav.c b/board/bf537-pnav/bf537-pnav.c index c5125288cbd..df0011026a6 100644 --- a/board/bf537-pnav/bf537-pnav.c +++ b/board/bf537-pnav/bf537-pnav.c @@ -12,7 +12,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -27,7 +26,7 @@ int checkboard(void) static void board_init_enetaddr(uchar *mac_addr) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); eth_setenv_enetaddr("ethaddr", mac_addr); } diff --git a/board/bf537-srv1/bf537-srv1.c b/board/bf537-srv1/bf537-srv1.c index 04d38910b3f..725296a4163 100644 --- a/board/bf537-srv1/bf537-srv1.c +++ b/board/bf537-srv1/bf537-srv1.c @@ -12,7 +12,6 @@ #include #include #include -#include DECLARE_GLOBAL_DATA_PTR; @@ -27,7 +26,7 @@ int checkboard(void) static void board_init_enetaddr(uchar *mac_addr) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); eth_setenv_enetaddr("ethaddr", mac_addr); } diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c index 5fdf8379c08..32045a9e47c 100644 --- a/board/bf537-stamp/bf537-stamp.c +++ b/board/bf537-stamp/bf537-stamp.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -48,7 +47,7 @@ static void board_init_enetaddr(uchar *mac_addr) if (!valid_mac) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); } eth_setenv_enetaddr("ethaddr", mac_addr); diff --git a/board/cm-bf527/cm-bf527.c b/board/cm-bf527/cm-bf527.c index a5f70a4f839..1533eb9c7a8 100644 --- a/board/cm-bf527/cm-bf527.c +++ b/board/cm-bf527/cm-bf527.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include "../cm-bf537e/gpio_cfi_flash.h" @@ -46,7 +45,7 @@ static void board_init_enetaddr(uchar *mac_addr) if (!valid_mac) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); } eth_setenv_enetaddr("ethaddr", mac_addr); diff --git a/board/cm-bf537e/cm-bf537e.c b/board/cm-bf537e/cm-bf537e.c index 8daf3ad06e8..e79f90f95bc 100644 --- a/board/cm-bf537e/cm-bf537e.c +++ b/board/cm-bf537e/cm-bf537e.c @@ -12,7 +12,6 @@ #include #include #include -#include #include "gpio_cfi_flash.h" DECLARE_GLOBAL_DATA_PTR; @@ -32,7 +31,7 @@ static void board_init_enetaddr(char *var) return; printf("Warning: %s: generating 'random' MAC address\n", var); - bfin_gen_rand_mac(enetaddr); + eth_random_addr(enetaddr); eth_setenv_enetaddr(var, enetaddr); } diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c index 5941b5fcbe0..632cbda5c06 100644 --- a/board/cm-bf537u/cm-bf537u.c +++ b/board/cm-bf537u/cm-bf537u.c @@ -12,7 +12,6 @@ #include #include #include -#include #include "../cm-bf537e/gpio_cfi_flash.h" DECLARE_GLOBAL_DATA_PTR; @@ -32,7 +31,7 @@ static void board_init_enetaddr(char *var) return; printf("Warning: %s: generating 'random' MAC address\n", var); - bfin_gen_rand_mac(enetaddr); + eth_random_addr(enetaddr); eth_setenv_enetaddr(var, enetaddr); } diff --git a/board/dnp5370/dnp5370.c b/board/dnp5370/dnp5370.c index 4b3873bd4f3..df721c9944a 100644 --- a/board/dnp5370/dnp5370.c +++ b/board/dnp5370/dnp5370.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -55,7 +54,7 @@ static void board_init_enetaddr(uchar *mac_addr) if (!valid_mac) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); } eth_setenv_enetaddr("ethaddr", mac_addr); diff --git a/board/ip04/ip04.c b/board/ip04/ip04.c index c8ae5128b0e..ae526334267 100644 --- a/board/ip04/ip04.c +++ b/board/ip04/ip04.c @@ -13,7 +13,6 @@ #include #include #include -#include int checkboard(void) { @@ -33,7 +32,7 @@ int misc_init_r(void) uchar enetaddr[6]; if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(enetaddr); + eth_random_addr(enetaddr); eth_setenv_enetaddr("ethaddr", enetaddr); } diff --git a/board/tcm-bf518/tcm-bf518.c b/board/tcm-bf518/tcm-bf518.c index 5964059dd1d..5d25fcd0a91 100644 --- a/board/tcm-bf518/tcm-bf518.c +++ b/board/tcm-bf518/tcm-bf518.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include @@ -47,7 +46,7 @@ static void board_init_enetaddr(uchar *mac_addr) if (!valid_mac) { puts("Warning: Generating 'random' MAC address\n"); - bfin_gen_rand_mac(mac_addr); + eth_random_addr(mac_addr); } eth_setenv_enetaddr("ethaddr", mac_addr); diff --git a/board/tcm-bf537/tcm-bf537.c b/board/tcm-bf537/tcm-bf537.c index 38aaae6870b..a4f0f7121b1 100644 --- a/board/tcm-bf537/tcm-bf537.c +++ b/board/tcm-bf537/tcm-bf537.c @@ -12,7 +12,6 @@ #include #include #include -#include #include "../cm-bf537e/gpio_cfi_flash.h" DECLARE_GLOBAL_DATA_PTR; @@ -32,7 +31,7 @@ static void board_init_enetaddr(char *var) return; printf("Warning: %s: generating 'random' MAC address\n", var); - bfin_gen_rand_mac(enetaddr); + eth_random_addr(enetaddr); eth_setenv_enetaddr(var, enetaddr); } diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h index 06f095cc41b..c1eda963851 100644 --- a/include/configs/bct-brettl2.h +++ b/include/configs/bct-brettl2.h @@ -75,6 +75,7 @@ #define CONFIG_ROOTPATH "/romfs/brettl2" /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ +#define CONFIG_LIB_RAND #endif diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h index 9eb85ebf3df..9e374c40244 100644 --- a/include/configs/bf518f-ezbrd.h +++ b/include/configs/bf518f-ezbrd.h @@ -89,7 +89,7 @@ #define CONFIG_PHY_ADDR 3 /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h index 3065d22f0bd..972eca9c174 100644 --- a/include/configs/bf526-ezbrd.h +++ b/include/configs/bf526-ezbrd.h @@ -87,7 +87,7 @@ #define CONFIG_HOSTNAME bf526-ezbrd /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h index 748ddb3b157..92c183e27c2 100644 --- a/include/configs/bf527-ezkit.h +++ b/include/configs/bf527-ezkit.h @@ -85,7 +85,7 @@ #define CONFIG_HOSTNAME bf527-ezkit /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings diff --git a/include/configs/bf537-minotaur.h b/include/configs/bf537-minotaur.h index 156eeabb06d..3bc364ccfdf 100644 --- a/include/configs/bf537-minotaur.h +++ b/include/configs/bf537-minotaur.h @@ -89,6 +89,7 @@ /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */ +#define CONFIG_LIB_RAND /* * Flash Settings diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h index 3aa3d50a89b..ba74a695f88 100644 --- a/include/configs/bf537-pnav.h +++ b/include/configs/bf537-pnav.h @@ -67,7 +67,7 @@ #define CONFIG_HOSTNAME bf537-pnav /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:24:21:18 */ - +#define CONFIG_LIB_RAND /* * Flash Settings diff --git a/include/configs/bf537-srv1.h b/include/configs/bf537-srv1.h index e12d761a245..0b723cf934e 100644 --- a/include/configs/bf537-srv1.h +++ b/include/configs/bf537-srv1.h @@ -88,7 +88,7 @@ #define CONFIG_ROOTPATH "/romfs" /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:42 */ - +#define CONFIG_LIB_RAND /* * Flash Settings diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index e1705cadaee..a302f839a1e 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -67,7 +67,7 @@ #define CONFIG_HOSTNAME bf537-stamp /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h index 384d8715adc..8d3ae49913e 100644 --- a/include/configs/cm-bf527.h +++ b/include/configs/cm-bf527.h @@ -85,7 +85,7 @@ #define CONFIG_HOSTNAME cm-bf527 /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h index 67cf801a3fe..47967d71203 100644 --- a/include/configs/cm-bf537e.h +++ b/include/configs/cm-bf537e.h @@ -73,7 +73,7 @@ #define CONFIG_HOSTNAME cm-bf537e /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h index 34ce75baebd..88c99821b1e 100644 --- a/include/configs/cm-bf537u.h +++ b/include/configs/cm-bf537u.h @@ -71,7 +71,7 @@ #define CONFIG_HOSTNAME cm-bf537u /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings diff --git a/include/configs/dnp5370.h b/include/configs/dnp5370.h index 4f2c742a5d1..3f1f9f38462 100644 --- a/include/configs/dnp5370.h +++ b/include/configs/dnp5370.h @@ -55,6 +55,8 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_PING + +#define CONFIG_LIB_RAND #endif /* diff --git a/include/configs/ip04.h b/include/configs/ip04.h index 0efa2b7b9f2..3767502faa5 100644 --- a/include/configs/ip04.h +++ b/include/configs/ip04.h @@ -77,6 +77,7 @@ #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE + 2) +#define CONFIG_LIB_RAND /* * Flash Settings diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h index 1ff34d517d8..a77ba697d0f 100644 --- a/include/configs/tcm-bf518.h +++ b/include/configs/tcm-bf518.h @@ -68,7 +68,7 @@ #define CONFIG_HOSTNAME tcm-bf518 /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h index 370d97ffe03..c4c1c579bc1 100644 --- a/include/configs/tcm-bf537.h +++ b/include/configs/tcm-bf537.h @@ -73,7 +73,7 @@ #define CONFIG_HOSTNAME tcm-bf537 /* Uncomment next line to use fixed MAC address */ /* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ - +#define CONFIG_LIB_RAND /* * Flash Settings -- cgit v1.3.1 From 488c47a141179fc3fa10779be6268e56f88ec18d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 28 Apr 2014 10:18:34 +0900 Subject: config: remove platform CONFIG_SYS_HZ definition part 4 Some new boards define CONFIG_SYS_HZ again! Remove. Signed-off-by: Masahiro Yamada Acked-by: Bo Shen --- include/configs/T208xRDB.h | 1 - include/configs/ids8313.h | 1 - include/configs/sama5d3_xplained.h | 1 - 3 files changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 73d82edb80f..0be0a0feb0b 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -750,7 +750,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ /* * For booting Linux, the board info and command line data diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h index 613f7e1a2ef..c1b3b633e96 100644 --- a/include/configs/ids8313.h +++ b/include/configs/ids8313.h @@ -474,7 +474,6 @@ #define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_HZ 1000 /* Initial Memory map for Linux*/ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 91cc7d8e583..41c946d1ec8 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -17,7 +17,6 @@ /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_AT91FAMILY #define CONFIG_ARCH_CPU_INIT -- cgit v1.3.1 From 8b454eeeea0ba021ee27f3e103daf1f8fa87bd16 Mon Sep 17 00:00:00 2001 From: Łukasz Majewski Date: Tue, 6 May 2014 09:36:05 +0200 Subject: fs:ext4:write:fix: Reinitialize global variables after updating a file This bug shows up when file stored on the ext4 file system is updated. The ext4fs_delete_file() is responsible for deleting file's (e.g. uImage) data. However some global data (especially ext4fs_indir2_block), which is used during file deletion are left unchanged. The ext4fs_indir2_block pointer stores reference to old ext4 double indirect allocated blocks. When it is unchanged, after file deletion, ext4fs_write_file() uses the same pointer (since it is already initialized - i.e. not NULL) to return number of blocks to write. This trunks larger file when previous one was smaller. Lets consider following scenario: 1. Flash target with ext4 formatted boot.img (which has uImage [*] on itself) 2. Developer wants to upload their custom uImage [**] - When new uImage [**] is smaller than the [*] - everything works correctly - we are able to store the whole smaller file with corrupted ext4fs_indir2_block pointer - When new uImage [**] is larger than the [*] - theCRC is corrupted, since truncation on data stored at eMMC was done. 3. When uImage CRC error appears, then reboot and LTHOR/DFU reflashing causes proper setting of ext4fs_indir2_block() and after that uImage[**] is successfully stored (correct uImage [*] metadata is stored at an eMMC on the first flashing). Due to above the bug was very difficult to reproduce. This patch sets default values for all ext4fs_indir* pointers/variables. Signed-off-by: Lukasz Majewski --- fs/ext4/ext4_common.c | 35 ++++++++++++++++++++++++++--------- fs/ext4/ext4_write.c | 1 + include/ext4fs.h | 1 + 3 files changed, 28 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index 62e2e804928..1c1172163c0 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -1841,16 +1841,20 @@ long int read_allocated_block(struct ext2_inode *inode, int fileblock) return blknr; } -void ext4fs_close(void) +/** + * ext4fs_reinit_global() - Reinitialize values of ext4 write implementation's + * global pointers + * + * This function assures that for a file with the same name but different size + * the sequential store on the ext4 filesystem will be correct. + * + * In this function the global data, responsible for internal representation + * of the ext4 data are initialized to the reset state. Without this, during + * replacement of the smaller file with the bigger truncation of new file was + * performed. + */ +void ext4fs_reinit_global(void) { - if ((ext4fs_file != NULL) && (ext4fs_root != NULL)) { - ext4fs_free_node(ext4fs_file, &ext4fs_root->diropen); - ext4fs_file = NULL; - } - if (ext4fs_root != NULL) { - free(ext4fs_root); - ext4fs_root = NULL; - } if (ext4fs_indir1_block != NULL) { free(ext4fs_indir1_block); ext4fs_indir1_block = NULL; @@ -1870,6 +1874,19 @@ void ext4fs_close(void) ext4fs_indir3_blkno = -1; } } +void ext4fs_close(void) +{ + if ((ext4fs_file != NULL) && (ext4fs_root != NULL)) { + ext4fs_free_node(ext4fs_file, &ext4fs_root->diropen); + ext4fs_file = NULL; + } + if (ext4fs_root != NULL) { + free(ext4fs_root); + ext4fs_root = NULL; + } + + ext4fs_reinit_global(); +} int ext4fs_iterate_dir(struct ext2fs_node *dir, char *name, struct ext2fs_node **fnode, int *ftype) diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c index 3db22f8f93d..c42add9a7ea 100644 --- a/fs/ext4/ext4_write.c +++ b/fs/ext4/ext4_write.c @@ -562,6 +562,7 @@ static int ext4fs_delete_file(int inodeno) ext4fs_update(); ext4fs_deinit(); + ext4fs_reinit_global(); if (ext4fs_init() != 0) { printf("error in File System init\n"); diff --git a/include/ext4fs.h b/include/ext4fs.h index aacb147de24..fbbb002b167 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -133,6 +133,7 @@ int ext4fs_open(const char *filename); int ext4fs_read(char *buf, unsigned len); int ext4fs_mount(unsigned part_length); void ext4fs_close(void); +void ext4fs_reinit_global(void); int ext4fs_ls(const char *dirname); int ext4fs_exists(const char *filename); void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot); -- cgit v1.3.1 From 06118973ede291df8617c4089972cbf888bdc96b Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Thu, 8 May 2014 16:14:05 +0800 Subject: fs/fat: add fat12 cluster check Signed-off-by: Josh Wu --- include/fat.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/fat.h b/include/fat.h index c8eb7ccd290..65da733aef3 100644 --- a/include/fat.h +++ b/include/fat.h @@ -85,7 +85,9 @@ + (mydata->fatsize != 32 ? 0 : \ (FAT2CPU16((dent)->starthi) << 16))) #define CHECK_CLUST(x, fatsize) ((x) <= 1 || \ - (x) >= ((fatsize) != 32 ? 0xfff0 : 0xffffff0)) + (x) >= ((fatsize) != 32 ? \ + ((fatsize) != 16 ? 0xff0 : 0xfff0) : \ + 0xffffff0)) typedef struct boot_sector { __u8 ignored[3]; /* Bootstrap code */ -- cgit v1.3.1 From 2e98f70882f8c1a09b662137884c1435a97c9a1c Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Thu, 8 May 2014 16:14:06 +0800 Subject: fs: fat_write: fix the incorrect last cluster checking In fat_write.c, the last clust condition check is incorrect: if ((curclust >= 0xffffff8) || (curclust >= 0xfff8)) { ... ... } For example, in FAT32 if curclust is 0x11000. It is a valid clust. But on above condition check, it will be think as a last clust. So the correct last clust check should be: in fat32, curclust >= 0xffffff8 in fat16, curclust >= 0xfff8 in fat12, curclust >= 0xff8 This patch correct the last clust check. Signed-off-by: Josh Wu --- fs/fat/fat_write.c | 2 +- include/fat.h | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index cef138ec965..90d6ab63bf7 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -882,7 +882,7 @@ static dir_entry *find_directory_entry(fsdata *mydata, int startsect, } curclust = get_fatent_value(mydata, dir_curclust); - if ((curclust >= 0xffffff8) || (curclust >= 0xfff8)) { + if (IS_LAST_CLUST(curclust, mydata->fatsize)) { empty_dentptr = dentptr; return NULL; } diff --git a/include/fat.h b/include/fat.h index 65da733aef3..81d9790420d 100644 --- a/include/fat.h +++ b/include/fat.h @@ -84,6 +84,9 @@ #define START(dent) (FAT2CPU16((dent)->start) \ + (mydata->fatsize != 32 ? 0 : \ (FAT2CPU16((dent)->starthi) << 16))) +#define IS_LAST_CLUST(x, fatsize) ((x) >= ((fatsize) != 32 ? \ + ((fatsize) != 16 ? 0xff8 : 0xfff8) : \ + 0xffffff8)) #define CHECK_CLUST(x, fatsize) ((x) <= 1 || \ (x) >= ((fatsize) != 32 ? \ ((fatsize) != 16 ? 0xff0 : 0xfff0) : \ -- cgit v1.3.1 From b625b9aef383be4366670e8d22b13d48ef8aa870 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 11:23:43 +0100 Subject: fpga: spartan2: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek --- board/esd/pmc440/fpga.c | 2 +- board/matrix_vision/mvsmr/fpga.c | 2 +- drivers/fpga/spartan2.c | 40 ++++++++++++++++++++-------------------- drivers/fpga/xilinx.c | 14 +++++++------- include/spartan2.h | 32 ++++++++++++++++---------------- include/xilinx.h | 2 +- 6 files changed, 46 insertions(+), 46 deletions(-) (limited to 'include') diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c index b7b62dd94db..cef20508827 100644 --- a/board/esd/pmc440/fpga.c +++ b/board/esd/pmc440/fpga.c @@ -47,7 +47,7 @@ Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = { }; #endif -Xilinx_Spartan2_Slave_Serial_fns ngcc_fpga_fns = { +xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = { ngcc_fpga_pre_config_fn, ngcc_fpga_pgm_fn, ngcc_fpga_clk_fn, diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c index 88035a9e9e3..639bc7c75b9 100644 --- a/board/matrix_vision/mvsmr/fpga.c +++ b/board/matrix_vision/mvsmr/fpga.c @@ -27,7 +27,7 @@ Xilinx_Spartan3_Slave_Serial_fns fpga_fns = { }; Xilinx_desc spartan3 = { - Xilinx_Spartan2, + xilinx_spartan2, slave_serial, XILINX_XC3S200_SIZE, (void *) &fpga_fns, diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 6eab1b51e55..bd317095c65 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -31,29 +31,29 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan2_sp_info(Xilinx_desc *desc ); */ +static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_sp_info(Xilinx_desc *desc ); */ -static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan2_ss_info(Xilinx_desc *desc ); */ +static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_ss_info(Xilinx_desc *desc ); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Spartan2_ss_load (desc, buf, bsize); + ret_val = spartan2_ss_load(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Spartan2_sp_load (desc, buf, bsize); + ret_val = spartan2_sp_load(desc, buf, bsize); break; default: @@ -64,19 +64,19 @@ int Spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Spartan2_ss_dump (desc, buf, bsize); + ret_val = spartan2_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Spartan2_sp_dump (desc, buf, bsize); + ret_val = spartan2_sp_dump(desc, buf, bsize); break; default: @@ -87,7 +87,7 @@ int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan2_info( Xilinx_desc *desc ) +int spartan2_info(Xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -96,10 +96,10 @@ int Spartan2_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -248,10 +248,10 @@ static int Spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -296,10 +296,10 @@ static int Spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Serial_fns *fn = desc->iface_fns; + xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns; int i; unsigned char val; @@ -439,7 +439,7 @@ static int Spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 2e0db535d47..47bbf395140 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -149,11 +149,11 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) printf ("%s: Invalid device descriptor\n", __FUNCTION__); } else switch (desc->family) { - case Xilinx_Spartan2: + case xilinx_spartan2: #if defined(CONFIG_FPGA_SPARTAN2) PRINTF ("%s: Launching the Spartan-II Loader...\n", __FUNCTION__); - ret_val = Spartan2_load (desc, buf, bsize); + ret_val = spartan2_load(desc, buf, bsize); #else printf ("%s: No support for Spartan-II devices.\n", __FUNCTION__); @@ -206,11 +206,11 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) printf ("%s: Invalid device descriptor\n", __FUNCTION__); } else switch (desc->family) { - case Xilinx_Spartan2: + case xilinx_spartan2: #if defined(CONFIG_FPGA_SPARTAN2) PRINTF ("%s: Launching the Spartan-II Reader...\n", __FUNCTION__); - ret_val = Spartan2_dump (desc, buf, bsize); + ret_val = spartan2_dump(desc, buf, bsize); #else printf ("%s: No support for Spartan-II devices.\n", __FUNCTION__); @@ -262,7 +262,7 @@ int xilinx_info (Xilinx_desc * desc) if (xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("Family: \t"); switch (desc->family) { - case Xilinx_Spartan2: + case xilinx_spartan2: printf ("Spartan-II\n"); break; case Xilinx_Spartan3: @@ -316,9 +316,9 @@ int xilinx_info (Xilinx_desc * desc) if (desc->iface_fns) { printf ("Device Function Table @ 0x%p\n", desc->iface_fns); switch (desc->family) { - case Xilinx_Spartan2: + case xilinx_spartan2: #if defined(CONFIG_FPGA_SPARTAN2) - Spartan2_info (desc); + spartan2_info(desc); #else /* just in case */ printf ("%s: No support for Spartan-II devices.\n", diff --git a/include/spartan2.h b/include/spartan2.h index 087a27d3cc0..a9fc68acc89 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -10,9 +10,9 @@ #include -extern int Spartan2_load(Xilinx_desc *desc, const void *image, size_t size); -extern int Spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int Spartan2_info(Xilinx_desc *desc); +int spartan2_load(Xilinx_desc *desc, const void *image, size_t size); +int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +int spartan2_info(Xilinx_desc *desc); /* Slave Parallel Implementation function table */ typedef struct { @@ -29,7 +29,7 @@ typedef struct { Xilinx_busy_fn busy; Xilinx_abort_fn abort; Xilinx_post_fn post; -} Xilinx_Spartan2_Slave_Parallel_fns; +} xilinx_spartan2_slave_parallel_fns; /* Slave Serial Implementation function table */ typedef struct { @@ -40,7 +40,7 @@ typedef struct { Xilinx_done_fn done; Xilinx_wr_fn wr; Xilinx_post_fn post; -} Xilinx_Spartan2_Slave_Serial_fns; +} xilinx_spartan2_slave_serial_fns; /* Device Image Sizes *********************************************************************/ @@ -63,36 +63,36 @@ typedef struct { *********************************************************************/ /* Spartan-II devices */ #define XILINX_XC2S15_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie } #define XILINX_XC2S30_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie } #define XILINX_XC2S50_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie } #define XILINX_XC2S100_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie } #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie } #define XILINX_XC2S200_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie } #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie } #define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie } #define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie } #define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie } #define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie } #endif /* _SPARTAN2_H_ */ diff --git a/include/xilinx.h b/include/xilinx.h index 00a585e5fc3..9d870b2d848 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -26,7 +26,7 @@ typedef enum { /* typedef Xilinx_iface */ typedef enum { /* typedef Xilinx_Family */ min_xilinx_type, /* low range check value */ - Xilinx_Spartan2, /* Spartan-II Family */ + xilinx_spartan2, /* Spartan-II Family */ Xilinx_VirtexE, /* Virtex-E Family */ Xilinx_Virtex2, /* Virtex2 Family */ Xilinx_Spartan3, /* Spartan-III Family */ -- cgit v1.3.1 From 2a6e3869f25093cd4032a3cd64ee455afbd668bf Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 11:28:42 +0100 Subject: fpga: spartan3: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek --- board/armadeus/apf27/fpga.c | 4 ++-- board/astro/mcf5373l/fpga.c | 4 ++-- board/balloon3/balloon3.c | 2 +- board/esd/pmc440/fpga.c | 4 ++-- board/matrix_vision/mvsmr/fpga.c | 2 +- board/spear/x600/fpga.c | 2 +- board/teejet/mt_ventoux/mt_ventoux.c | 2 +- drivers/fpga/spartan3.c | 40 ++++++++++++++++++------------------ drivers/fpga/xilinx.c | 14 ++++++------- include/spartan3.h | 38 +++++++++++++++++----------------- include/xilinx.h | 2 +- 11 files changed, 57 insertions(+), 57 deletions(-) (limited to 'include') diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c index 0c08c0640ef..56fde200e79 100644 --- a/board/armadeus/apf27/fpga.c +++ b/board/armadeus/apf27/fpga.c @@ -26,7 +26,7 @@ * Spartan2 code is used to download our Spartan 3 :) code is compatible. * Just take care about the file size */ -Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = { +xilinx_spartan3_slave_parallel_fns fpga_fns = { fpga_pre_fn, fpga_pgm_fn, fpga_init_fn, @@ -43,7 +43,7 @@ Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = { }; Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { - {Xilinx_Spartan3, + {xilinx_spartan3, slave_parallel, 1196128l/8, (void *)&fpga_fns, diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index c679ad7f65c..152ff1f58c9 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -363,7 +363,7 @@ int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie) * relocated at runtime. * FIXME: relocation not yet working for coldfire, see below! */ -Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = { +xilinx_spartan3_slave_serial_fns xilinx_fns = { xilinx_pre_config_fn, xilinx_pgm_fn, xilinx_clk_fn, @@ -375,7 +375,7 @@ Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = { }; Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { - {Xilinx_Spartan3, + {xilinx_spartan3, slave_serial, XILINX_XC3S4000_SIZE, (void *)&xilinx_fns, diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c index 04e0574658a..4aa66052da9 100644 --- a/board/balloon3/balloon3.c +++ b/board/balloon3/balloon3.c @@ -191,7 +191,7 @@ int fpga_cs_fn(int assert_clk, int flush, int cookie) return assert_clk; } -Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = { +xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_init_fn, diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c index cef20508827..18a1b63088d 100644 --- a/board/esd/pmc440/fpga.c +++ b/board/esd/pmc440/fpga.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #define USE_SP_CODE #ifdef USE_SP_CODE -Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = { +xilinx_spartan3_slave_parallel_fns pmc440_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_init_fn, @@ -36,7 +36,7 @@ Xilinx_Spartan3_Slave_Parallel_fns pmc440_fpga_fns = { fpga_post_config_fn, }; #else -Xilinx_Spartan3_Slave_Serial_fns pmc440_fpga_fns = { +xilinx_spartan3_slave_serial_fns pmc440_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_clk_fn, diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c index 639bc7c75b9..b2074552439 100644 --- a/board/matrix_vision/mvsmr/fpga.c +++ b/board/matrix_vision/mvsmr/fpga.c @@ -16,7 +16,7 @@ #include "fpga.h" #include "mvsmr.h" -Xilinx_Spartan3_Slave_Serial_fns fpga_fns = { +xilinx_spartan3_slave_serial_fns fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_clk_fn, diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c index c06c9947777..c26eba42845 100644 --- a/board/spear/x600/fpga.c +++ b/board/spear/x600/fpga.c @@ -163,7 +163,7 @@ static int fpga_wr_fn(int assert_write, int flush, int cookie) return assert_write; } -static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = { +static xilinx_spartan3_slave_serial_fns x600_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_clk_fn, diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index c32d554ea42..a36176494e4 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -190,7 +190,7 @@ int fpga_clk_fn(int assert_clk, int flush, int cookie) return assert_clk; } -Xilinx_Spartan3_Slave_Serial_fns mt_ventoux_fpga_fns = { +xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_clk_fn, diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 3edc5c2c66a..e40abbfb946 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -35,29 +35,29 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan3_sp_info(Xilinx_desc *desc ); */ +static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_sp_info(Xilinx_desc *desc ); */ -static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int Spartan3_ss_info(Xilinx_desc *desc); */ +static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_ss_info(Xilinx_desc *desc); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Spartan3_ss_load (desc, buf, bsize); + ret_val = spartan3_ss_load(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Spartan3_sp_load (desc, buf, bsize); + ret_val = spartan3_sp_load(desc, buf, bsize); break; default: @@ -68,19 +68,19 @@ int Spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Spartan3_ss_dump (desc, buf, bsize); + ret_val = spartan3_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Spartan3_sp_dump (desc, buf, bsize); + ret_val = spartan3_sp_dump(desc, buf, bsize); break; default: @@ -91,7 +91,7 @@ int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Spartan3_info( Xilinx_desc *desc ) +int spartan3_info(Xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -100,10 +100,10 @@ int Spartan3_info( Xilinx_desc *desc ) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; PRINTF ("%s: start with interface functions @ 0x%p\n", __FUNCTION__, fn); @@ -254,10 +254,10 @@ static int Spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -302,10 +302,10 @@ static int Spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns; + xilinx_spartan3_slave_serial_fns *fn = desc->iface_fns; int i; unsigned char val; @@ -457,7 +457,7 @@ static int Spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 47bbf395140..7d93d641f6a 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -159,11 +159,11 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); #endif break; - case Xilinx_Spartan3: + case xilinx_spartan3: #if defined(CONFIG_FPGA_SPARTAN3) PRINTF ("%s: Launching the Spartan-III Loader...\n", __FUNCTION__); - ret_val = Spartan3_load (desc, buf, bsize); + ret_val = spartan3_load(desc, buf, bsize); #else printf ("%s: No support for Spartan-III devices.\n", __FUNCTION__); @@ -216,11 +216,11 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); #endif break; - case Xilinx_Spartan3: + case xilinx_spartan3: #if defined(CONFIG_FPGA_SPARTAN3) PRINTF ("%s: Launching the Spartan-III Reader...\n", __FUNCTION__); - ret_val = Spartan3_dump (desc, buf, bsize); + ret_val = spartan3_dump(desc, buf, bsize); #else printf ("%s: No support for Spartan-III devices.\n", __FUNCTION__); @@ -265,7 +265,7 @@ int xilinx_info (Xilinx_desc * desc) case xilinx_spartan2: printf ("Spartan-II\n"); break; - case Xilinx_Spartan3: + case xilinx_spartan3: printf ("Spartan-III\n"); break; case Xilinx_Virtex2: @@ -325,9 +325,9 @@ int xilinx_info (Xilinx_desc * desc) __FUNCTION__); #endif break; - case Xilinx_Spartan3: + case xilinx_spartan3: #if defined(CONFIG_FPGA_SPARTAN3) - Spartan3_info (desc); + spartan3_info(desc); #else /* just in case */ printf ("%s: No support for Spartan-III devices.\n", diff --git a/include/spartan3.h b/include/spartan3.h index 72e7c0ddd00..93ca8a40bc3 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -10,9 +10,9 @@ #include -extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size); -extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int Spartan3_info(Xilinx_desc *desc); +int spartan3_load(Xilinx_desc *desc, const void *image, size_t size); +int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +int spartan3_info(Xilinx_desc *desc); /* Slave Parallel Implementation function table */ typedef struct { @@ -29,7 +29,7 @@ typedef struct { Xilinx_busy_fn busy; Xilinx_abort_fn abort; Xilinx_post_fn post; -} Xilinx_Spartan3_Slave_Parallel_fns; +} xilinx_spartan3_slave_parallel_fns; /* Slave Serial Implementation function table */ typedef struct { @@ -42,7 +42,7 @@ typedef struct { Xilinx_post_fn post; Xilinx_bwr_fn bwr; /* block write function */ Xilinx_abort_fn abort; -} Xilinx_Spartan3_Slave_Serial_fns; +} xilinx_spartan3_slave_serial_fns; /* Device Image Sizes *********************************************************************/ @@ -73,46 +73,46 @@ typedef struct { *********************************************************************/ /* Spartan-III devices */ #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie } #define XILINX_XC3S200_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie } #define XILINX_XC3S400_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie } #define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie } #define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie } #define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie } #define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie } #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie } /* Spartan-3E devices */ #define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie } #define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie } #define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie } #define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie } #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie } #define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \ -{ Xilinx_Spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie } #endif /* _SPARTAN3_H_ */ diff --git a/include/xilinx.h b/include/xilinx.h index 9d870b2d848..365c0c358eb 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -29,7 +29,7 @@ typedef enum { /* typedef Xilinx_Family */ xilinx_spartan2, /* Spartan-II Family */ Xilinx_VirtexE, /* Virtex-E Family */ Xilinx_Virtex2, /* Virtex2 Family */ - Xilinx_Spartan3, /* Spartan-III Family */ + xilinx_spartan3, /* Spartan-III Family */ xilinx_zynq, /* Zynq Family */ max_xilinx_type /* insert all new types before this */ } Xilinx_Family; /* end, typedef Xilinx_Family */ -- cgit v1.3.1 From d9071ce0a8cd684589c9c35e4d7c604a9cbd7d62 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 11:33:36 +0100 Subject: fpga: virtex2: Avoid CamelCase No functional changes. Signed-off-by: Michal Simek --- board/gen860t/fpga.c | 4 ++-- drivers/fpga/virtex2.c | 34 +++++++++++++++++----------------- drivers/fpga/xilinx.c | 14 +++++++------- include/virtex2.h | 34 +++++++++++++++++----------------- include/xilinx.h | 2 +- 5 files changed, 44 insertions(+), 44 deletions(-) (limited to 'include') diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c index b7984dd0fec..48a4222ac41 100644 --- a/board/gen860t/fpga.c +++ b/board/gen860t/fpga.c @@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Note that these are pointers to code that is in Flash. They will be * relocated at runtime. */ -Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = { +xilinx_virtex2_slave_selectmap_fns fpga_fns = { fpga_pre_config_fn, fpga_pgm_fn, fpga_init_fn, @@ -57,7 +57,7 @@ Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = { }; Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { - {Xilinx_Virtex2, + {xilinx_virtex2, slave_selectmap, XILINX_XC2V3000_SIZE, (void *) &fpga_fns, diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index b5a895d41a7..1cd9046a248 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -84,25 +84,25 @@ #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ #endif -static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__); - ret_val = Virtex2_ss_load (desc, buf, bsize); + ret_val = virtex2_ss_load(desc, buf, bsize); break; case slave_selectmap: PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__); - ret_val = Virtex2_ssm_load (desc, buf, bsize); + ret_val = virtex2_ssm_load(desc, buf, bsize); break; default: @@ -112,19 +112,19 @@ int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; switch (desc->iface) { case slave_serial: PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__); - ret_val = Virtex2_ss_dump (desc, buf, bsize); + ret_val = virtex2_ss_dump(desc, buf, bsize); break; case slave_parallel: PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__); - ret_val = Virtex2_ssm_dump (desc, buf, bsize); + ret_val = virtex2_ssm_dump(desc, buf, bsize); break; default: @@ -134,7 +134,7 @@ int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int Virtex2_info (Xilinx_desc * desc) +int virtex2_info(Xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -153,10 +153,10 @@ int Virtex2_info (Xilinx_desc * desc) * INIT_B and DONE lines. If both are high, configuration has * succeeded. Congratulations! */ -static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; - Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; + xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; PRINTF ("%s:%d: Start with interface functions @ 0x%p\n", __FUNCTION__, __LINE__, fn); @@ -352,10 +352,10 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* * Read the FPGA configuration data */ -static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; - Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns; + xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; if (fn) { unsigned char *data = (unsigned char *) buf; @@ -404,13 +404,13 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); return FPGA_FAIL; } -static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); return FPGA_FAIL; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 7d93d641f6a..6953535f082 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -169,11 +169,11 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); #endif break; - case Xilinx_Virtex2: + case xilinx_virtex2: #if defined(CONFIG_FPGA_VIRTEX2) PRINTF ("%s: Launching the Virtex-II Loader...\n", __FUNCTION__); - ret_val = Virtex2_load (desc, buf, bsize); + ret_val = virtex2_load(desc, buf, bsize); #else printf ("%s: No support for Virtex-II devices.\n", __FUNCTION__); @@ -226,11 +226,11 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); #endif break; - case Xilinx_Virtex2: + case xilinx_virtex2: #if defined( CONFIG_FPGA_VIRTEX2) PRINTF ("%s: Launching the Virtex-II Reader...\n", __FUNCTION__); - ret_val = Virtex2_dump (desc, buf, bsize); + ret_val = virtex2_dump(desc, buf, bsize); #else printf ("%s: No support for Virtex-II devices.\n", __FUNCTION__); @@ -268,7 +268,7 @@ int xilinx_info (Xilinx_desc * desc) case xilinx_spartan3: printf ("Spartan-III\n"); break; - case Xilinx_Virtex2: + case xilinx_virtex2: printf ("Virtex-II\n"); break; case xilinx_zynq: @@ -334,9 +334,9 @@ int xilinx_info (Xilinx_desc * desc) __FUNCTION__); #endif break; - case Xilinx_Virtex2: + case xilinx_virtex2: #if defined(CONFIG_FPGA_VIRTEX2) - Virtex2_info (desc); + virtex2_info(desc); #else /* just in case */ printf ("%s: No support for Virtex-II devices.\n", diff --git a/include/virtex2.h b/include/virtex2.h index 2e9a4f52da3..1e6624ca962 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -11,9 +11,9 @@ #include -extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size); -extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int Virtex2_info(Xilinx_desc *desc); +int virtex2_load(Xilinx_desc *desc, const void *image, size_t size); +int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +int virtex2_info(Xilinx_desc *desc); /* * Slave SelectMap Implementation function table. @@ -32,7 +32,7 @@ typedef struct { Xilinx_busy_fn busy; Xilinx_abort_fn abort; Xilinx_post_fn post; -} Xilinx_Virtex2_Slave_SelectMap_fns; +} xilinx_virtex2_slave_selectmap_fns; /* Slave Serial Implementation function table */ typedef struct { @@ -40,7 +40,7 @@ typedef struct { Xilinx_clk_fn clk; Xilinx_rdata_fn rdata; Xilinx_wdata_fn wdata; -} Xilinx_Virtex2_Slave_Serial_fns; +} xilinx_virtex2_slave_serial_fns; /* Device Image Sizes (in bytes) *********************************************************************/ @@ -60,39 +60,39 @@ typedef struct { /* Descriptor Macros *********************************************************************/ #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie } #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie } #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie } #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie } #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie } #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie } #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie } #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie } #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie } #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie } #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie } #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \ -{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie } #endif /* _VIRTEX2_H_ */ diff --git a/include/xilinx.h b/include/xilinx.h index 365c0c358eb..fa89fb68351 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -28,7 +28,7 @@ typedef enum { /* typedef Xilinx_Family */ min_xilinx_type, /* low range check value */ xilinx_spartan2, /* Spartan-II Family */ Xilinx_VirtexE, /* Virtex-E Family */ - Xilinx_Virtex2, /* Virtex2 Family */ + xilinx_virtex2, /* Virtex2 Family */ xilinx_spartan3, /* Spartan-III Family */ xilinx_zynq, /* Zynq Family */ max_xilinx_type /* insert all new types before this */ -- cgit v1.3.1 From f8c1be9816a60d1f627954fe202b502917c69863 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 12:49:21 +0100 Subject: fpga: xilinx: Avoid CamelCase for in Xilinx_desc No functional changes. Signed-off-by: Michal Simek --- board/armadeus/apf27/fpga.c | 2 +- board/astro/mcf5373l/fpga.c | 2 +- board/balloon3/balloon3.c | 2 +- board/esd/pmc440/fpga.c | 2 +- board/gen860t/fpga.c | 2 +- board/matrix_vision/mvsmr/fpga.c | 2 +- board/spear/x600/fpga.c | 2 +- board/teejet/mt_ventoux/mt_ventoux.c | 2 +- board/xilinx/zynq/board.c | 14 +++++++------- drivers/fpga/spartan2.c | 26 +++++++++++++------------- drivers/fpga/spartan3.c | 26 +++++++++++++------------- drivers/fpga/virtex2.c | 22 +++++++++++----------- drivers/fpga/xilinx.c | 14 +++++++------- drivers/fpga/zynqpl.c | 6 +++--- include/spartan2.h | 6 +++--- include/spartan3.h | 6 +++--- include/virtex2.h | 6 +++--- include/xilinx.h | 10 +++++----- include/zynqpl.h | 6 +++--- 19 files changed, 79 insertions(+), 79 deletions(-) (limited to 'include') diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c index 56fde200e79..7d6e1e462c9 100644 --- a/board/armadeus/apf27/fpga.c +++ b/board/armadeus/apf27/fpga.c @@ -42,7 +42,7 @@ xilinx_spartan3_slave_parallel_fns fpga_fns = { fpga_post_fn, }; -Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { +xilinx_desc fpga[CONFIG_FPGA_COUNT] = { {xilinx_spartan3, slave_parallel, 1196128l/8, diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index 152ff1f58c9..9dc82c5737c 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -374,7 +374,7 @@ xilinx_spartan3_slave_serial_fns xilinx_fns = { xilinx_fastwr_fn }; -Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { +xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { {xilinx_spartan3, slave_serial, XILINX_XC3S4000_SIZE, diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c index 4aa66052da9..aa108ca1539 100644 --- a/board/balloon3/balloon3.c +++ b/board/balloon3/balloon3.c @@ -207,7 +207,7 @@ xilinx_spartan3_slave_parallel_fns balloon3_fpga_fns = { fpga_post_config_fn, }; -Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel, +xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel, (void *)&balloon3_fpga_fns, 0); /* Initialize the FPGA */ diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c index 18a1b63088d..f876da855b1 100644 --- a/board/esd/pmc440/fpga.c +++ b/board/esd/pmc440/fpga.c @@ -57,7 +57,7 @@ xilinx_spartan2_slave_serial_fns ngcc_fpga_fns = { ngcc_fpga_post_config_fn }; -Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { +xilinx_desc fpga[CONFIG_FPGA_COUNT] = { XILINX_XC3S1200E_DESC( #ifdef USE_SP_CODE slave_parallel, diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c index 48a4222ac41..dd0ef707d6d 100644 --- a/board/gen860t/fpga.c +++ b/board/gen860t/fpga.c @@ -56,7 +56,7 @@ xilinx_virtex2_slave_selectmap_fns fpga_fns = { fpga_post_config_fn }; -Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { +xilinx_desc fpga[CONFIG_FPGA_COUNT] = { {xilinx_virtex2, slave_selectmap, XILINX_XC2V3000_SIZE, diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c index b2074552439..518992578c1 100644 --- a/board/matrix_vision/mvsmr/fpga.c +++ b/board/matrix_vision/mvsmr/fpga.c @@ -26,7 +26,7 @@ xilinx_spartan3_slave_serial_fns fpga_fns = { 0 }; -Xilinx_desc spartan3 = { +xilinx_desc spartan3 = { xilinx_spartan2, slave_serial, XILINX_XC3S200_SIZE, diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c index c26eba42845..b256222e186 100644 --- a/board/spear/x600/fpga.c +++ b/board/spear/x600/fpga.c @@ -173,7 +173,7 @@ static xilinx_spartan3_slave_serial_fns x600_fpga_fns = { fpga_post_config_fn, }; -static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { +static xilinx_desc fpga[CONFIG_FPGA_COUNT] = { XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0) }; diff --git a/board/teejet/mt_ventoux/mt_ventoux.c b/board/teejet/mt_ventoux/mt_ventoux.c index a36176494e4..b4a0a72bd0f 100644 --- a/board/teejet/mt_ventoux/mt_ventoux.c +++ b/board/teejet/mt_ventoux/mt_ventoux.c @@ -200,7 +200,7 @@ xilinx_spartan3_slave_serial_fns mt_ventoux_fpga_fns = { fpga_post_config_fn, }; -Xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial, +xilinx_desc fpga = XILINX_XC6SLX4_DESC(slave_serial, (void *)&mt_ventoux_fpga_fns, 0); /* Initialize the FPGA */ diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 485a5e4a249..c8cc2bc9344 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -14,15 +14,15 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_FPGA -Xilinx_desc fpga; +xilinx_desc fpga; /* It can be done differently */ -Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); -Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); -Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); -Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); -Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); -Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); +xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10); +xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15); +xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20); +xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30); +xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45); +xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100); #endif int board_init(void) diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index bd317095c65..0796729436c 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -31,17 +31,17 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int spartan2_sp_info(Xilinx_desc *desc ); */ +static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_sp_info(xilinx_desc *desc ); */ -static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int spartan2_ss_info(Xilinx_desc *desc ); */ +static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan2_ss_info(xilinx_desc *desc ); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -64,7 +64,7 @@ int spartan2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -87,7 +87,7 @@ int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan2_info(Xilinx_desc *desc) +int spartan2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -96,7 +96,7 @@ int spartan2_info(Xilinx_desc *desc) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; @@ -248,7 +248,7 @@ static int spartan2_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan2_slave_parallel_fns *fn = desc->iface_fns; @@ -296,7 +296,7 @@ static int spartan2_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan2_slave_serial_fns *fn = desc->iface_fns; @@ -439,7 +439,7 @@ static int spartan2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int spartan2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index e40abbfb946..1304b4c646e 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -35,17 +35,17 @@ #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */ #endif -static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int spartan3_sp_info(Xilinx_desc *desc ); */ +static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_sp_info(xilinx_desc *desc ); */ -static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -/* static int spartan3_ss_info(Xilinx_desc *desc); */ +static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); +/* static int spartan3_ss_info(xilinx_desc *desc); */ /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -68,7 +68,7 @@ int spartan3_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -91,7 +91,7 @@ int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan3_info(Xilinx_desc *desc) +int spartan3_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -100,7 +100,7 @@ int spartan3_info(Xilinx_desc *desc) /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ -static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; @@ -254,7 +254,7 @@ static int spartan3_sp_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_sp_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan3_slave_parallel_fns *fn = desc->iface_fns; @@ -302,7 +302,7 @@ static int spartan3_sp_dump(Xilinx_desc *desc, const void *buf, size_t bsize) /* ------------------------------------------------------------------------- */ -static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume the worst */ xilinx_spartan3_slave_serial_fns *fn = desc->iface_fns; @@ -457,7 +457,7 @@ static int spartan3_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int spartan3_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { /* Readback is only available through the Slave Parallel and */ /* boundary-scan interfaces. */ diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 1cd9046a248..a582bf2d798 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -84,13 +84,13 @@ #define CONFIG_SYS_FPGA_WAIT_CONFIG CONFIG_SYS_HZ/5 /* 200 ms */ #endif -static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize); -static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize); -static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); +static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -112,7 +112,7 @@ int virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -134,7 +134,7 @@ int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int virtex2_info(Xilinx_desc *desc) +int virtex2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -153,7 +153,7 @@ int virtex2_info(Xilinx_desc *desc) * INIT_B and DONE lines. If both are high, configuration has * succeeded. Congratulations! */ -static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; @@ -352,7 +352,7 @@ static int virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize) /* * Read the FPGA configuration data */ -static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns; @@ -404,13 +404,13 @@ static int virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -static int virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); return FPGA_FAIL; } -static int virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) { printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__); return FPGA_FAIL; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 6953535f082..b0e9cb35a31 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -31,7 +31,7 @@ #endif /* Local Static Functions */ -static int xilinx_validate (Xilinx_desc * desc, char *fn); +static int xilinx_validate(xilinx_desc *desc, char *fn); /* ------------------------------------------------------------------------- */ @@ -43,7 +43,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) unsigned char *dataptr; unsigned int i; const fpga_desc *desc; - Xilinx_desc *xdesc; + xilinx_desc *xdesc; dataptr = (unsigned char *)fpgadata; /* Find out fpga_description */ @@ -94,7 +94,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) return FPGA_FAIL; } } else { - printf("%s: Please fill correct device ID to Xilinx_desc\n", + printf("%s: Please fill correct device ID to xilinx_desc\n", __func__); } printf(" part number = \"%s\"\n", buffer); @@ -141,7 +141,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) return fpga_load(devnum, dataptr, swapsize); } -int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ @@ -198,7 +198,7 @@ int xilinx_load(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; /* assume a failure */ @@ -255,7 +255,7 @@ int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int xilinx_info (Xilinx_desc * desc) +int xilinx_info(xilinx_desc *desc) { int ret_val = FPGA_FAIL; @@ -369,7 +369,7 @@ int xilinx_info (Xilinx_desc * desc) /* ------------------------------------------------------------------------- */ -static int xilinx_validate (Xilinx_desc * desc, char *fn) +static int xilinx_validate(xilinx_desc *desc, char *fn) { int ret_val = false; diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index 923a1586d8b..b4d0e2278c9 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -36,7 +36,7 @@ #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ #endif -int zynq_info(Xilinx_desc *desc) +int zynq_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -153,7 +153,7 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) } -int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) +int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) { unsigned long ts; /* Timestamp */ u32 partialbit = 0; @@ -358,7 +358,7 @@ int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_SUCCESS; } -int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize) +int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) { return FPGA_FAIL; } diff --git a/include/spartan2.h b/include/spartan2.h index a9fc68acc89..33b25e6b8b9 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -10,9 +10,9 @@ #include -int spartan2_load(Xilinx_desc *desc, const void *image, size_t size); -int spartan2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -int spartan2_info(Xilinx_desc *desc); +int spartan2_load(xilinx_desc *desc, const void *image, size_t size); +int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize); +int spartan2_info(xilinx_desc *desc); /* Slave Parallel Implementation function table */ typedef struct { diff --git a/include/spartan3.h b/include/spartan3.h index 93ca8a40bc3..e06b99bff55 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -10,9 +10,9 @@ #include -int spartan3_load(Xilinx_desc *desc, const void *image, size_t size); -int spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -int spartan3_info(Xilinx_desc *desc); +int spartan3_load(xilinx_desc *desc, const void *image, size_t size); +int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize); +int spartan3_info(xilinx_desc *desc); /* Slave Parallel Implementation function table */ typedef struct { diff --git a/include/virtex2.h b/include/virtex2.h index 1e6624ca962..dd47965aad3 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -11,9 +11,9 @@ #include -int virtex2_load(Xilinx_desc *desc, const void *image, size_t size); -int virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -int virtex2_info(Xilinx_desc *desc); +int virtex2_load(xilinx_desc *desc, const void *image, size_t size); +int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize); +int virtex2_info(xilinx_desc *desc); /* * Slave SelectMap Implementation function table. diff --git a/include/xilinx.h b/include/xilinx.h index fa89fb68351..5900c837440 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -34,20 +34,20 @@ typedef enum { /* typedef Xilinx_Family */ max_xilinx_type /* insert all new types before this */ } Xilinx_Family; /* end, typedef Xilinx_Family */ -typedef struct { /* typedef Xilinx_desc */ +typedef struct { /* typedef xilinx_desc */ Xilinx_Family family; /* part type */ Xilinx_iface iface; /* interface type */ size_t size; /* bytes of data part can accept */ void *iface_fns; /* interface function table */ int cookie; /* implementation specific cookie */ char *name; /* device name in bitstream */ -} Xilinx_desc; /* end, typedef Xilinx_desc */ +} xilinx_desc; /* end, typedef xilinx_desc */ /* Generic Xilinx Functions *********************************************************************/ -extern int xilinx_load(Xilinx_desc *desc, const void *image, size_t size); -extern int xilinx_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int xilinx_info(Xilinx_desc *desc); +int xilinx_load(xilinx_desc *desc, const void *image, size_t size); +int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize); +int xilinx_info(xilinx_desc *desc); /* Board specific implementation specific function types *********************************************************************/ diff --git a/include/zynqpl.h b/include/zynqpl.h index c81446e9860..fdee69110ce 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -12,9 +12,9 @@ #include -extern int zynq_load(Xilinx_desc *desc, const void *image, size_t size); -extern int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize); -extern int zynq_info(Xilinx_desc *desc); +int zynq_load(xilinx_desc *desc, const void *image, size_t size); +int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize); +int zynq_info(xilinx_desc *desc); #define XILINX_ZYNQ_7010 0x2 #define XILINX_ZYNQ_7015 0x1b -- cgit v1.3.1 From 2df9d5c431fca07c9868a36b48ee771bde6b19e8 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 12:58:20 +0100 Subject: fpga: xilinx: Fix the rest of CamelCases No functional changes. Signed-off-by: Michal Simek --- board/astro/mcf5373l/fpga.c | 38 +++++++++++++++++++------------------- include/spartan2.h | 40 ++++++++++++++++++++-------------------- include/spartan3.h | 44 ++++++++++++++++++++++---------------------- include/virtex2.h | 34 +++++++++++++++++----------------- include/xilinx.h | 42 +++++++++++++++++++++--------------------- 5 files changed, 99 insertions(+), 99 deletions(-) (limited to 'include') diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index 9dc82c5737c..81ec1920657 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -203,7 +203,7 @@ int astro5373l_altera_load(void) } /* Set the FPGA's PROG_B line to the specified level */ -int xilinx_pgm_fn(int assert, int flush, int cookie) +int xilinx_pgm_config_fn(int assert, int flush, int cookie) { gpio_t *gpiop = (gpio_t *)MMAP_GPIO; @@ -218,7 +218,7 @@ int xilinx_pgm_fn(int assert, int flush, int cookie) * Test the state of the active-low FPGA INIT line. Return 1 on INIT * asserted (low). */ -int xilinx_init_fn(int cookie) +int xilinx_init_config_fn(int cookie) { gpio_t *gpiop = (gpio_t *)MMAP_GPIO; @@ -226,7 +226,7 @@ int xilinx_init_fn(int cookie) } /* Test the state of the active-high FPGA DONE pin */ -int xilinx_done_fn(int cookie) +int xilinx_done_config_fn(int cookie) { gpio_t *gpiop = (gpio_t *)MMAP_GPIO; @@ -234,7 +234,7 @@ int xilinx_done_fn(int cookie) } /* Abort an FPGA operation */ -int xilinx_abort_fn(int cookie) +int xilinx_abort_config_fn(int cookie) { gpio_t *gpiop = (gpio_t *)MMAP_GPIO; /* ensure all SPI peripherals and FPGAs are deselected */ @@ -300,7 +300,7 @@ int xilinx_post_config_fn(int cookie) return rc; } -int xilinx_clk_fn(int assert_clk, int flush, int cookie) +int xilinx_clk_config_fn(int assert_clk, int flush, int cookie) { gpio_t *gpiop = (gpio_t *)MMAP_GPIO; @@ -311,7 +311,7 @@ int xilinx_clk_fn(int assert_clk, int flush, int cookie) return assert_clk; } -int xilinx_wr_fn(int assert_write, int flush, int cookie) +int xilinx_wr_config_fn(int assert_write, int flush, int cookie) { gpio_t *gpiop = (gpio_t *)MMAP_GPIO; @@ -322,7 +322,7 @@ int xilinx_wr_fn(int assert_write, int flush, int cookie) return assert_write; } -int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie) +int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie) { size_t bytecount = 0; gpio_t *gpiop = (gpio_t *)MMAP_GPIO; @@ -365,13 +365,13 @@ int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie) */ xilinx_spartan3_slave_serial_fns xilinx_fns = { xilinx_pre_config_fn, - xilinx_pgm_fn, - xilinx_clk_fn, - xilinx_init_fn, - xilinx_done_fn, - xilinx_wr_fn, + xilinx_pgm_config_fn, + xilinx_clk_config_fn, + xilinx_init_config_fn, + xilinx_done_config_fn, + xilinx_wr_config_fn, 0, - xilinx_fastwr_fn + xilinx_fastwr_config_fn }; xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { @@ -395,12 +395,12 @@ int astro5373l_xilinx_load(void) * so set stuff here instead of static initialisation: */ xilinx_fns.pre = xilinx_pre_config_fn; - xilinx_fns.pgm = xilinx_pgm_fn; - xilinx_fns.clk = xilinx_clk_fn; - xilinx_fns.init = xilinx_init_fn; - xilinx_fns.done = xilinx_done_fn; - xilinx_fns.wr = xilinx_wr_fn; - xilinx_fns.bwr = xilinx_fastwr_fn; + xilinx_fns.pgm = xilinx_pgm_config_fn; + xilinx_fns.clk = xilinx_clk_config_fn; + xilinx_fns.init = xilinx_init_config_fn; + xilinx_fns.done = xilinx_done_config_fn; + xilinx_fns.wr = xilinx_wr_config_fn; + xilinx_fns.bwr = xilinx_fastwr_config_fn; xilinx_fpga[i].iface_fns = (void *)&xilinx_fns; fpga_add(fpga_xilinx, &xilinx_fpga[i]); } diff --git a/include/spartan2.h b/include/spartan2.h index 33b25e6b8b9..25db6e7a60d 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -16,30 +16,30 @@ int spartan2_info(xilinx_desc *desc); /* Slave Parallel Implementation function table */ typedef struct { - Xilinx_pre_fn pre; - Xilinx_pgm_fn pgm; - Xilinx_init_fn init; - Xilinx_err_fn err; - Xilinx_done_fn done; - Xilinx_clk_fn clk; - Xilinx_cs_fn cs; - Xilinx_wr_fn wr; - Xilinx_rdata_fn rdata; - Xilinx_wdata_fn wdata; - Xilinx_busy_fn busy; - Xilinx_abort_fn abort; - Xilinx_post_fn post; + xilinx_pre_fn pre; + xilinx_pgm_fn pgm; + xilinx_init_fn init; + xilinx_err_fn err; + xilinx_done_fn done; + xilinx_clk_fn clk; + xilinx_cs_fn cs; + xilinx_wr_fn wr; + xilinx_rdata_fn rdata; + xilinx_wdata_fn wdata; + xilinx_busy_fn busy; + xilinx_abort_fn abort; + xilinx_post_fn post; } xilinx_spartan2_slave_parallel_fns; /* Slave Serial Implementation function table */ typedef struct { - Xilinx_pre_fn pre; - Xilinx_pgm_fn pgm; - Xilinx_clk_fn clk; - Xilinx_init_fn init; - Xilinx_done_fn done; - Xilinx_wr_fn wr; - Xilinx_post_fn post; + xilinx_pre_fn pre; + xilinx_pgm_fn pgm; + xilinx_clk_fn clk; + xilinx_init_fn init; + xilinx_done_fn done; + xilinx_wr_fn wr; + xilinx_post_fn post; } xilinx_spartan2_slave_serial_fns; /* Device Image Sizes diff --git a/include/spartan3.h b/include/spartan3.h index e06b99bff55..56698ac9c72 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -16,32 +16,32 @@ int spartan3_info(xilinx_desc *desc); /* Slave Parallel Implementation function table */ typedef struct { - Xilinx_pre_fn pre; - Xilinx_pgm_fn pgm; - Xilinx_init_fn init; - Xilinx_err_fn err; - Xilinx_done_fn done; - Xilinx_clk_fn clk; - Xilinx_cs_fn cs; - Xilinx_wr_fn wr; - Xilinx_rdata_fn rdata; - Xilinx_wdata_fn wdata; - Xilinx_busy_fn busy; - Xilinx_abort_fn abort; - Xilinx_post_fn post; + xilinx_pre_fn pre; + xilinx_pgm_fn pgm; + xilinx_init_fn init; + xilinx_err_fn err; + xilinx_done_fn done; + xilinx_clk_fn clk; + xilinx_cs_fn cs; + xilinx_wr_fn wr; + xilinx_rdata_fn rdata; + xilinx_wdata_fn wdata; + xilinx_busy_fn busy; + xilinx_abort_fn abort; + xilinx_post_fn post; } xilinx_spartan3_slave_parallel_fns; /* Slave Serial Implementation function table */ typedef struct { - Xilinx_pre_fn pre; - Xilinx_pgm_fn pgm; - Xilinx_clk_fn clk; - Xilinx_init_fn init; - Xilinx_done_fn done; - Xilinx_wr_fn wr; - Xilinx_post_fn post; - Xilinx_bwr_fn bwr; /* block write function */ - Xilinx_abort_fn abort; + xilinx_pre_fn pre; + xilinx_pgm_fn pgm; + xilinx_clk_fn clk; + xilinx_init_fn init; + xilinx_done_fn done; + xilinx_wr_fn wr; + xilinx_post_fn post; + xilinx_bwr_fn bwr; /* block write function */ + xilinx_abort_fn abort; } xilinx_spartan3_slave_serial_fns; /* Device Image Sizes diff --git a/include/virtex2.h b/include/virtex2.h index dd47965aad3..d39286c7ab9 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -19,27 +19,27 @@ int virtex2_info(xilinx_desc *desc); * Slave SelectMap Implementation function table. */ typedef struct { - Xilinx_pre_fn pre; - Xilinx_pgm_fn pgm; - Xilinx_init_fn init; - Xilinx_err_fn err; - Xilinx_done_fn done; - Xilinx_clk_fn clk; - Xilinx_cs_fn cs; - Xilinx_wr_fn wr; - Xilinx_rdata_fn rdata; - Xilinx_wdata_fn wdata; - Xilinx_busy_fn busy; - Xilinx_abort_fn abort; - Xilinx_post_fn post; + xilinx_pre_fn pre; + xilinx_pgm_fn pgm; + xilinx_init_fn init; + xilinx_err_fn err; + xilinx_done_fn done; + xilinx_clk_fn clk; + xilinx_cs_fn cs; + xilinx_wr_fn wr; + xilinx_rdata_fn rdata; + xilinx_wdata_fn wdata; + xilinx_busy_fn busy; + xilinx_abort_fn abort; + xilinx_post_fn post; } xilinx_virtex2_slave_selectmap_fns; /* Slave Serial Implementation function table */ typedef struct { - Xilinx_pgm_fn pgm; - Xilinx_clk_fn clk; - Xilinx_rdata_fn rdata; - Xilinx_wdata_fn wdata; + xilinx_pgm_fn pgm; + xilinx_clk_fn clk; + xilinx_rdata_fn rdata; + xilinx_wdata_fn wdata; } xilinx_virtex2_slave_serial_fns; /* Device Image Sizes (in bytes) diff --git a/include/xilinx.h b/include/xilinx.h index 5900c837440..b72aece7c90 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -12,7 +12,7 @@ /* Xilinx types *********************************************************************/ -typedef enum { /* typedef Xilinx_iface */ +typedef enum { /* typedef xilinx_iface */ min_xilinx_iface_type, /* low range check value */ slave_serial, /* serial data and external clock */ master_serial, /* serial data w/ internal clock (not used) */ @@ -22,21 +22,21 @@ typedef enum { /* typedef Xilinx_iface */ slave_selectmap, /* slave SelectMap (virtex2) */ devcfg, /* devcfg interface (zynq) */ max_xilinx_iface_type /* insert all new types before this */ -} Xilinx_iface; /* end, typedef Xilinx_iface */ +} xilinx_iface; /* end, typedef xilinx_iface */ -typedef enum { /* typedef Xilinx_Family */ +typedef enum { /* typedef xilinx_family */ min_xilinx_type, /* low range check value */ xilinx_spartan2, /* Spartan-II Family */ - Xilinx_VirtexE, /* Virtex-E Family */ + xilinx_virtexE, /* Virtex-E Family */ xilinx_virtex2, /* Virtex2 Family */ xilinx_spartan3, /* Spartan-III Family */ xilinx_zynq, /* Zynq Family */ max_xilinx_type /* insert all new types before this */ -} Xilinx_Family; /* end, typedef Xilinx_Family */ +} xilinx_family; /* end, typedef xilinx_family */ typedef struct { /* typedef xilinx_desc */ - Xilinx_Family family; /* part type */ - Xilinx_iface iface; /* interface type */ + xilinx_family family; /* part type */ + xilinx_iface iface; /* interface type */ size_t size; /* bytes of data part can accept */ void *iface_fns; /* interface function table */ int cookie; /* implementation specific cookie */ @@ -51,19 +51,19 @@ int xilinx_info(xilinx_desc *desc); /* Board specific implementation specific function types *********************************************************************/ -typedef int (*Xilinx_pgm_fn)( int assert_pgm, int flush, int cookie ); -typedef int (*Xilinx_init_fn)( int cookie ); -typedef int (*Xilinx_err_fn)( int cookie ); -typedef int (*Xilinx_done_fn)( int cookie ); -typedef int (*Xilinx_clk_fn)( int assert_clk, int flush, int cookie ); -typedef int (*Xilinx_cs_fn)( int assert_cs, int flush, int cookie ); -typedef int (*Xilinx_wr_fn)( int assert_write, int flush, int cookie ); -typedef int (*Xilinx_rdata_fn)( unsigned char *data, int cookie ); -typedef int (*Xilinx_wdata_fn)( unsigned char data, int flush, int cookie ); -typedef int (*Xilinx_busy_fn)( int cookie ); -typedef int (*Xilinx_abort_fn)( int cookie ); -typedef int (*Xilinx_pre_fn)( int cookie ); -typedef int (*Xilinx_post_fn)( int cookie ); -typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie ); +typedef int (*xilinx_pgm_fn)(int assert_pgm, int flush, int cookie); +typedef int (*xilinx_init_fn)(int cookie); +typedef int (*xilinx_err_fn)(int cookie); +typedef int (*xilinx_done_fn)(int cookie); +typedef int (*xilinx_clk_fn)(int assert_clk, int flush, int cookie); +typedef int (*xilinx_cs_fn)(int assert_cs, int flush, int cookie); +typedef int (*xilinx_wr_fn)(int assert_write, int flush, int cookie); +typedef int (*xilinx_rdata_fn)(unsigned char *data, int cookie); +typedef int (*xilinx_wdata_fn)(unsigned char data, int flush, int cookie); +typedef int (*xilinx_busy_fn)(int cookie); +typedef int (*xilinx_abort_fn)(int cookie); +typedef int (*xilinx_pre_fn)(int cookie); +typedef int (*xilinx_post_fn)(int cookie); +typedef int (*xilinx_bwr_fn)(void *buf, size_t len, int flush, int cookie); #endif /* _XILINX_H_ */ -- cgit v1.3.1 From 14cfc4f3735d9704cb6a630ef302be596d380684 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 13 Mar 2014 13:07:57 +0100 Subject: fpga: xilinx: Simplify load/dump/info function handling Connect FPGA version with appropriate operations to remove huge switch-cases for every FPGA family. Tested on Zynq. Spartan2/Spartan3/Virtex2 just compile test. Signed-off-by: Michal Simek --- board/armadeus/apf27/fpga.c | 1 + board/astro/mcf5373l/fpga.c | 3 +- drivers/fpga/spartan2.c | 12 +++- drivers/fpga/spartan3.c | 12 +++- drivers/fpga/virtex2.c | 12 +++- drivers/fpga/xilinx.c | 159 ++------------------------------------------ drivers/fpga/zynqpl.c | 13 ++-- include/spartan2.h | 28 ++++---- include/spartan3.h | 36 +++++----- include/virtex2.h | 28 ++++---- include/xilinx.h | 7 ++ include/zynqpl.h | 16 ++--- 12 files changed, 104 insertions(+), 223 deletions(-) (limited to 'include') diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c index 7d6e1e462c9..65a4812c35b 100644 --- a/board/armadeus/apf27/fpga.c +++ b/board/armadeus/apf27/fpga.c @@ -48,6 +48,7 @@ xilinx_desc fpga[CONFIG_FPGA_COUNT] = { 1196128l/8, (void *)&fpga_fns, 0, + &spartan3_op, "3s200aft256"} }; diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index 81ec1920657..1d044d96a56 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -379,7 +379,8 @@ xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = { slave_serial, XILINX_XC3S4000_SIZE, (void *)&xilinx_fns, - 0} + 0, + &spartan3_op} }; /* Initialize the fpga. Return 1 on success, 0 on failure. */ diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index 0796729436c..70540561403 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -41,7 +41,7 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -64,7 +64,7 @@ int spartan2_load(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -87,7 +87,7 @@ int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan2_info(xilinx_desc *desc) +static int spartan2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -447,3 +447,9 @@ static int spartan2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } + +struct xilinx_fpga_op spartan2_op = { + .load = spartan2_load, + .dump = spartan2_dump, + .info = spartan2_info, +}; diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 1304b4c646e..5c9412c2f63 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -45,7 +45,7 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ -int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -68,7 +68,7 @@ int spartan3_load(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) +static int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -91,7 +91,7 @@ int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int spartan3_info(xilinx_desc *desc) +static int spartan3_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -465,3 +465,9 @@ static int spartan3_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } + +struct xilinx_fpga_op spartan3_op = { + .load = spartan3_load, + .dump = spartan3_dump, + .info = spartan3_info, +}; diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index a582bf2d798..e092147edd1 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -90,7 +90,7 @@ static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize); static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize); static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -112,7 +112,7 @@ int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) +static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) { int ret_val = FPGA_FAIL; @@ -134,7 +134,7 @@ int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize) return ret_val; } -int virtex2_info(xilinx_desc *desc) +static int virtex2_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -417,3 +417,9 @@ static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize) } /* vim: set ts=4 tw=78: */ + +struct xilinx_fpga_op virtex2_op = { + .load = virtex2_load, + .dump = virtex2_dump, + .info = virtex2_info, +}; diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index b0e9cb35a31..8837f5c122e 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -19,17 +19,6 @@ #include #include -#if 0 -#define FPGA_DEBUG -#endif - -/* Define FPGA_DEBUG to get debug printf's */ -#ifdef FPGA_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - /* Local Static Functions */ static int xilinx_validate(xilinx_desc *desc, char *fn); @@ -143,116 +132,22 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size) int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize) { - int ret_val = FPGA_FAIL; /* assume a failure */ - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else - switch (desc->family) { - case xilinx_spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - PRINTF ("%s: Launching the Spartan-II Loader...\n", - __FUNCTION__); - ret_val = spartan2_load(desc, buf, bsize); -#else - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - PRINTF ("%s: Launching the Spartan-III Loader...\n", - __FUNCTION__); - ret_val = spartan3_load(desc, buf, bsize); -#else - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) - PRINTF ("%s: Launching the Virtex-II Loader...\n", - __FUNCTION__); - ret_val = virtex2_load(desc, buf, bsize); -#else - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - PRINTF("%s: Launching the Zynq PL Loader...\n", - __func__); - ret_val = zynq_load(desc, buf, bsize); -#else - printf("%s: No support for Zynq devices.\n", - __func__); -#endif - break; - - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } + return FPGA_FAIL; + } - return ret_val; + return desc->operations->load(desc, buf, bsize); } int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize) { - int ret_val = FPGA_FAIL; /* assume a failure */ - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else - switch (desc->family) { - case xilinx_spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - PRINTF ("%s: Launching the Spartan-II Reader...\n", - __FUNCTION__); - ret_val = spartan2_dump(desc, buf, bsize); -#else - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - PRINTF ("%s: Launching the Spartan-III Reader...\n", - __FUNCTION__); - ret_val = spartan3_dump(desc, buf, bsize); -#else - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_virtex2: -#if defined( CONFIG_FPGA_VIRTEX2) - PRINTF ("%s: Launching the Virtex-II Reader...\n", - __FUNCTION__); - ret_val = virtex2_dump(desc, buf, bsize); -#else - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - PRINTF("%s: Launching the Zynq PL Reader...\n", - __func__); - ret_val = zynq_dump(desc, buf, bsize); -#else - printf("%s: No support for Zynq devices.\n", - __func__); -#endif - break; - - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } + return FPGA_FAIL; + } - return ret_val; + return desc->operations->dump(desc, buf, bsize); } int xilinx_info(xilinx_desc *desc) @@ -315,47 +210,7 @@ int xilinx_info(xilinx_desc *desc) if (desc->iface_fns) { printf ("Device Function Table @ 0x%p\n", desc->iface_fns); - switch (desc->family) { - case xilinx_spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - spartan2_info(desc); -#else - /* just in case */ - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - spartan3_info(desc); -#else - /* just in case */ - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) - virtex2_info(desc); -#else - /* just in case */ - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - case xilinx_zynq: -#if defined(CONFIG_FPGA_ZYNQPL) - zynq_info(desc); -#else - /* just in case */ - printf("%s: No support for Zynq devices.\n", - __func__); -#endif - /* Add new family types here */ - default: - /* we don't need a message here - we give one up above */ - ; - } + desc->operations->info(desc); } else printf ("No Device Function Table.\n"); diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c index b4d0e2278c9..dcd34951ad6 100644 --- a/drivers/fpga/zynqpl.c +++ b/drivers/fpga/zynqpl.c @@ -36,7 +36,7 @@ #define CONFIG_SYS_FPGA_PROG_TIME (CONFIG_SYS_HZ * 4) /* 4 s */ #endif -int zynq_info(xilinx_desc *desc) +static int zynq_info(xilinx_desc *desc) { return FPGA_SUCCESS; } @@ -152,8 +152,7 @@ static void *check_data(u8 *buf, size_t bsize, u32 *swap) return 0; } - -int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) { unsigned long ts; /* Timestamp */ u32 partialbit = 0; @@ -358,7 +357,13 @@ int zynq_load(xilinx_desc *desc, const void *buf, size_t bsize) return FPGA_SUCCESS; } -int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) +static int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize) { return FPGA_FAIL; } + +struct xilinx_fpga_op zynq_op = { + .load = zynq_load, + .dump = zynq_dump, + .info = zynq_info, +}; diff --git a/include/spartan2.h b/include/spartan2.h index 25db6e7a60d..2aca954e73a 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -10,10 +10,6 @@ #include -int spartan2_load(xilinx_desc *desc, const void *image, size_t size); -int spartan2_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int spartan2_info(xilinx_desc *desc); - /* Slave Parallel Implementation function table */ typedef struct { xilinx_pre_fn pre; @@ -42,6 +38,8 @@ typedef struct { xilinx_post_fn post; } xilinx_spartan2_slave_serial_fns; +extern struct xilinx_fpga_op spartan2_op; + /* Device Image Sizes *********************************************************************/ /* Spartan-II (2.5V) */ @@ -63,36 +61,36 @@ typedef struct { *********************************************************************/ /* Spartan-II devices */ #define XILINX_XC2S15_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S15_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S30_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S30_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S50_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S50_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S100_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S100_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S150_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S150_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S200_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S200_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S50E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S50E_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S100E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S100E_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S150E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S150E_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S200E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S200E_SIZE, fn_table, cookie, &spartan2_op } #define XILINX_XC2S300E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie } +{ xilinx_spartan2, iface, XILINX_XC2S300E_SIZE, fn_table, cookie, &spartan2_op } #endif /* _SPARTAN2_H_ */ diff --git a/include/spartan3.h b/include/spartan3.h index 56698ac9c72..d6d67a6e560 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -10,10 +10,6 @@ #include -int spartan3_load(xilinx_desc *desc, const void *image, size_t size); -int spartan3_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int spartan3_info(xilinx_desc *desc); - /* Slave Parallel Implementation function table */ typedef struct { xilinx_pre_fn pre; @@ -44,6 +40,8 @@ typedef struct { xilinx_abort_fn abort; } xilinx_spartan3_slave_serial_fns; +extern struct xilinx_fpga_op spartan3_op; + /* Device Image Sizes *********************************************************************/ /* Spartan-III (1.2V) */ @@ -73,46 +71,48 @@ typedef struct { *********************************************************************/ /* Spartan-III devices */ #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S200_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S400_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie, &spartan3_op } /* Spartan-3E devices */ #define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie, &spartan3_op } #define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie, \ + &spartan3_op } #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie, \ + &spartan3_op } #define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \ -{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie } +{ xilinx_spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie, &spartan3_op } #endif /* _SPARTAN3_H_ */ diff --git a/include/virtex2.h b/include/virtex2.h index d39286c7ab9..7b7825f513e 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -11,9 +11,7 @@ #include -int virtex2_load(xilinx_desc *desc, const void *image, size_t size); -int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int virtex2_info(xilinx_desc *desc); +extern struct xilinx_fpga_op virtex2_op; /* * Slave SelectMap Implementation function table. @@ -60,39 +58,39 @@ typedef struct { /* Descriptor Macros *********************************************************************/ #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, &virtex2_op } #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \ -{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie } +{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, &virtex2_op } #endif /* _VIRTEX2_H_ */ diff --git a/include/xilinx.h b/include/xilinx.h index b72aece7c90..9801267c593 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -40,9 +40,16 @@ typedef struct { /* typedef xilinx_desc */ size_t size; /* bytes of data part can accept */ void *iface_fns; /* interface function table */ int cookie; /* implementation specific cookie */ + struct xilinx_fpga_op *operations; /* operations */ char *name; /* device name in bitstream */ } xilinx_desc; /* end, typedef xilinx_desc */ +struct xilinx_fpga_op { + int (*load)(xilinx_desc *, const void *, size_t); + int (*dump)(xilinx_desc *, const void *, size_t); + int (*info)(xilinx_desc *); +}; + /* Generic Xilinx Functions *********************************************************************/ int xilinx_load(xilinx_desc *desc, const void *image, size_t size); diff --git a/include/zynqpl.h b/include/zynqpl.h index fdee69110ce..8a9ec3297fb 100644 --- a/include/zynqpl.h +++ b/include/zynqpl.h @@ -12,9 +12,7 @@ #include -int zynq_load(xilinx_desc *desc, const void *image, size_t size); -int zynq_dump(xilinx_desc *desc, const void *buf, size_t bsize); -int zynq_info(xilinx_desc *desc); +extern struct xilinx_fpga_op zynq_op; #define XILINX_ZYNQ_7010 0x2 #define XILINX_ZYNQ_7015 0x1b @@ -33,21 +31,21 @@ int zynq_info(xilinx_desc *desc); /* Descriptor Macros */ #define XILINX_XC7Z010_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, "7z010" } +{ xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, &zynq_op, "7z010" } #define XILINX_XC7Z015_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, "7z015" } +{ xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, &zynq_op, "7z015" } #define XILINX_XC7Z020_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, "7z020" } +{ xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, &zynq_op, "7z020" } #define XILINX_XC7Z030_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, "7z030" } +{ xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, &zynq_op, "7z030" } #define XILINX_XC7Z045_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" } +{ xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, &zynq_op, "7z045" } #define XILINX_XC7Z100_DESC(cookie) \ -{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" } +{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, &zynq_op, "7z100" } #endif /* _ZYNQPL_H_ */ -- cgit v1.3.1 From 652e29b4a0d5ff418a4f1a633912976cd7331758 Mon Sep 17 00:00:00 2001 From: Shaveta Leekha Date: Fri, 11 Apr 2014 14:12:40 +0530 Subject: board/b4qds: VID support The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. B4860QDS has a PowerOne ZM7300 programmable digital Power Manager which is programmed as per the value read from the fuses. Reference for this code is taken from t4qds VID implementation. Signed-off-by: Shaveta Leekha Signed-off-by: Poonam Aggrwal --- board/freescale/b4860qds/b4860qds.c | 240 ++++++++++++++++++++++++++++++++++++ include/configs/B4860QDS.h | 11 ++ 2 files changed, 251 insertions(+) (limited to 'include') diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c index d9c88a074f8..b2d53781438 100644 --- a/board/freescale/b4860qds/b4860qds.c +++ b/board/freescale/b4860qds/b4860qds.c @@ -23,6 +23,7 @@ #include "../common/qixis.h" #include "../common/vsc3316_3308.h" #include "../common/idt8t49n222a_serdes_clk.h" +#include "../common/zm7300.h" #include "b4860qds.h" #include "b4860qds_qixis.h" #include "b4860qds_crossbar_con.h" @@ -94,6 +95,238 @@ int select_i2c_ch_pca(u8 ch) return 0; } +/* + * read_voltage from sensor on I2C bus + * We use average of 4 readings, waiting for 532us befor another reading + */ +#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */ +#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */ + +static inline int read_voltage(void) +{ + int i, ret, voltage_read = 0; + u16 vol_mon; + + for (i = 0; i < NUM_READINGS; i++) { + ret = i2c_read(I2C_VOL_MONITOR_ADDR, + I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2); + if (ret) { + printf("VID: failed to read core voltage\n"); + return ret; + } + if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) { + printf("VID: Core voltage sensor error\n"); + return -1; + } + debug("VID: bus voltage reads 0x%04x\n", vol_mon); + /* LSB = 4mv */ + voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4; + udelay(WAIT_FOR_ADC); + } + /* calculate the average */ + voltage_read /= NUM_READINGS; + + return voltage_read; +} + +static int adjust_vdd(ulong vdd_override) +{ + int re_enable = disable_interrupts(); + ccsr_gur_t __iomem *gur = + (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 fusesr; + u8 vid; + int vdd_target, vdd_last; + int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */ + int ret; + unsigned int orig_i2c_speed; + unsigned long vdd_string_override; + char *vdd_string; + static const uint16_t vdd[32] = { + 0, /* unused */ + 9875, /* 0.9875V */ + 9750, + 9625, + 9500, + 9375, + 9250, + 9125, + 9000, + 8875, + 8750, + 8625, + 8500, + 8375, + 8250, + 8125, + 10000, /* 1.0000V */ + 10125, + 10250, + 10375, + 10500, + 10625, + 10750, + 10875, + 11000, + 0, /* reserved */ + }; + struct vdd_drive { + u8 vid; + unsigned voltage; + }; + + ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + printf("VID: I2c failed to switch channel\n"); + ret = -1; + goto exit; + } + + /* get the voltage ID from fuse status register */ + fusesr = in_be32(&gur->dcfg_fusesr); + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_VID_MASK; + if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) { + vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CORENET_DCFG_FUSESR_ALTVID_MASK; + } + vdd_target = vdd[vid]; + debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n", + vid, vdd_target/10); + + /* check override variable for overriding VDD */ + vdd_string = getenv("b4qds_vdd_mv"); + if (vdd_override == 0 && vdd_string && + !strict_strtoul(vdd_string, 10, &vdd_string_override)) + vdd_override = vdd_string_override; + if (vdd_override >= 819 && vdd_override <= 1212) { + vdd_target = vdd_override * 10; /* convert to 1/10 mV */ + debug("VDD override is %lu\n", vdd_override); + } else if (vdd_override != 0) { + printf("Invalid value.\n"); + } + + if (vdd_target == 0) { + printf("VID: VID not used\n"); + ret = 0; + goto exit; + } + + /* + * Read voltage monitor to check real voltage. + * Voltage monitor LSB is 4mv. + */ + vdd_last = read_voltage(); + if (vdd_last < 0) { + printf("VID: abort VID adjustment\n"); + ret = -1; + goto exit; + } + + debug("VID: Core voltage is at %d mV\n", vdd_last); + ret = select_i2c_ch_pca(I2C_MUX_CH_DPM); + if (ret) { + printf("VID: I2c failed to switch channel to DPM\n"); + ret = -1; + goto exit; + } + + /* Round up to the value of step of Voltage regulator */ + voltage = roundup(vdd_target, ZM_STEP); + debug("VID: rounded up voltage = %d\n", voltage); + + /* lower the speed to 100kHz to access ZM7300 device */ + debug("VID: Setting bus speed to 100KHz if not already set\n"); + orig_i2c_speed = i2c_get_bus_speed(); + if (orig_i2c_speed != 100000) + i2c_set_bus_speed(100000); + + /* Read the existing level on board, if equal to requsted one, + no need to re-set */ + existing_voltage = zm_read_voltage(); + + /* allowing the voltage difference of one step 0.0125V acceptable */ + if ((existing_voltage >= voltage) && + (existing_voltage < (voltage + ZM_STEP))) { + debug("VID: voltage already set as requested,returning\n"); + ret = existing_voltage; + goto out; + } + debug("VID: Changing voltage for board from %dmV to %dmV\n", + existing_voltage/10, voltage/10); + + if (zm_disable_wp() < 0) { + ret = -1; + goto out; + } + /* Change Voltage: the change is done through all the steps in the + way, to avoid reset to the board due to power good signal fail + in big voltage change gap jump. + */ + if (existing_voltage > voltage) { + temp_voltage = existing_voltage - ZM_STEP; + while (temp_voltage >= voltage) { + ret = zm_write_voltage(temp_voltage); + if (ret == temp_voltage) { + temp_voltage -= ZM_STEP; + } else { + /* ZM7300 device failed to set + * the voltage */ + printf + ("VID:Stepping down vol failed:%dmV\n", + temp_voltage/10); + ret = -1; + goto out; + } + } + } else { + temp_voltage = existing_voltage + ZM_STEP; + while (temp_voltage < (voltage + ZM_STEP)) { + ret = zm_write_voltage(temp_voltage); + if (ret == temp_voltage) { + temp_voltage += ZM_STEP; + } else { + /* ZM7300 device failed to set + * the voltage */ + printf + ("VID:Stepping up vol failed:%dmV\n", + temp_voltage/10); + ret = -1; + goto out; + } + } + } + + if (zm_enable_wp() < 0) + ret = -1; + + /* restore the speed to 400kHz */ +out: debug("VID: Restore the I2C bus speed to %dKHz\n", + orig_i2c_speed/1000); + i2c_set_bus_speed(orig_i2c_speed); + if (ret < 0) + goto exit; + + ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR); + if (ret) { + printf("VID: I2c failed to switch channel\n"); + ret = -1; + goto exit; + } + vdd_last = read_voltage(); + select_i2c_ch_pca(I2C_CH_DEFAULT); + + if (vdd_last > 0) + printf("VID: Core voltage %d mV\n", vdd_last); + else + ret = -1; + +exit: + if (re_enable) + enable_interrupts(); + return ret; +} + int configure_vsc3316_3308(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -697,6 +930,13 @@ int board_early_init_r(void) #ifdef CONFIG_SYS_DPAA_QBMAN setup_portals(); #endif + /* + * Adjust core voltage according to voltage ID + * This function changes I2C mux to channel 2. + */ + if (adjust_vdd(0) < 0) + printf("Warning: Adjusting core voltage failed\n"); + /* SerDes1 refclks need to be set again, as default clks * are not suitable for CPRI and onboard SGMIIs to work * simultaneously. diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index df371b771d5..a6125568a2c 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -115,6 +115,17 @@ #define IDT_SERDES1_ADDRESS 0x6E #define IDT_SERDES2_ADDRESS 0x6C +/* Voltage monitor on channel 2*/ +#define I2C_MUX_CH_VOL_MONITOR 0xa +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +#define CONFIG_ZM7300 +#define I2C_MUX_CH_DPM 0xa +#define I2C_DPM_ADDR 0x28 + #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_SYS_NO_FLASH -- cgit v1.3.1 From 0b2e13d9ccbe56e32dc674cf896b2fb55684368c Mon Sep 17 00:00:00 2001 From: Chunhe Lan Date: Mon, 14 Apr 2014 18:42:06 +0800 Subject: powerpc/85xx: Add T4240RDB board support T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: Chunhe Lan [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h] --- arch/powerpc/cpu/mpc85xx/t4240_ids.c | 2 + board/freescale/t4rdb/Makefile | 12 + board/freescale/t4rdb/ddr.c | 118 ++++++ board/freescale/t4rdb/ddr.h | 78 ++++ board/freescale/t4rdb/eth.c | 146 +++++++ board/freescale/t4rdb/law.c | 28 ++ board/freescale/t4rdb/pci.c | 23 ++ board/freescale/t4rdb/t4240rdb.c | 125 ++++++ board/freescale/t4rdb/t4_pbi.cfg | 31 ++ board/freescale/t4rdb/t4_rcw.cfg | 7 + board/freescale/t4rdb/t4rdb.h | 18 + board/freescale/t4rdb/tlb.c | 111 ++++++ boards.cfg | 1 + drivers/mmc/fsl_esdhc.c | 2 +- include/configs/T4240RDB.h | 752 +++++++++++++++++++++++++++++++++++ 15 files changed, 1453 insertions(+), 1 deletion(-) create mode 100644 board/freescale/t4rdb/Makefile create mode 100644 board/freescale/t4rdb/ddr.c create mode 100644 board/freescale/t4rdb/ddr.h create mode 100644 board/freescale/t4rdb/eth.c create mode 100644 board/freescale/t4rdb/law.c create mode 100644 board/freescale/t4rdb/pci.c create mode 100644 board/freescale/t4rdb/t4240rdb.c create mode 100644 board/freescale/t4rdb/t4_pbi.cfg create mode 100644 board/freescale/t4rdb/t4_rcw.cfg create mode 100644 board/freescale/t4rdb/t4rdb.h create mode 100644 board/freescale/t4rdb/tlb.c create mode 100644 include/configs/T4240RDB.h (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c index f1813151346..1a3cb339874 100644 --- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c +++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c @@ -64,11 +64,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { }; #endif +#ifdef CONFIG_SYS_SRIO struct srio_liodn_id_table srio_liodn_tbl[] = { SET_SRIO_LIODN_BASE(1, 307), SET_SRIO_LIODN_BASE(2, 387), }; int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); +#endif struct liodn_id_table liodn_tbl[] = { #ifdef CONFIG_SYS_DPAA_QBMAN diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile new file mode 100644 index 00000000000..f7f7fc01774 --- /dev/null +++ b/board/freescale/t4rdb/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_T4240RDB) += t4240rdb.o +obj-y += ddr.o +obj-y += eth.o +obj-$(CONFIG_PCI) += pci.o +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c new file mode 100644 index 00000000000..5a43c1bc78f --- /dev/null +++ b/board/freescale/t4rdb/ddr.c @@ -0,0 +1,118 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + /* + * we use identical timing for all slots. If needed, change the code + * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num]; + */ + if (popts->registered_dimm_en) + pbsp = rdimms[0]; + else + pbsp = udimms[0]; + + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks && + (pdimm->rank_density >> 30) >= pbsp->rank_gb) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for data\n" + "rate %lu MT/s\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n" + "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x,\n" + "wrlvl_ctrl_3 0x%x\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb, + pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2, + pbsp->wrlvl_ctl_3); + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h new file mode 100644 index 00000000000..7b854767e7a --- /dev/null +++ b/board/freescale/t4rdb/ddr.h @@ -0,0 +1,78 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a}, + {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09}, + {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b}, + {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a}, + {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c}, + {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c}, + {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a}, + {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a}, + {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b}, + {} +}; + +static const struct board_specific_parameters rdimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 + */ + {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, + {} +}; + +/* + * The three slots have slightly different timing. The center values are good + * for all slots. We use identical speed tables for them. In future use, if + * DIMMs require separated tables, make more entries as needed. + */ +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +/* + * The three slots have slightly different timing. See comments above. + */ +static const struct board_specific_parameters *rdimms[] = { + rdimm0, +}; + + +#endif diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c new file mode 100644 index 00000000000..d220475b5a8 --- /dev/null +++ b/board/freescale/t4rdb/eth.c @@ -0,0 +1,146 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * Chunhe Lan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/fman.h" +#include "t4rdb.h" + +void fdt_fixup_board_enet(void *fdt) +{ + return; +} + +int board_eth_init(bd_t *bis) +{ +#if defined(CONFIG_FMAN_ENET) + int i, interface; + struct memac_mdio_info dtsec_mdio_info; + struct memac_mdio_info tgec_mdio_info; + struct mii_dev *dev; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 srds_prtcl_s1, srds_prtcl_s2; + + srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + + dtsec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR; + + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the 1G MDIO bus */ + fm_memac_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the 10G MDIO bus */ + fm_memac_mdio_init(bis, &tgec_mdio_info); + + if (srds_prtcl_s1 == 28) { + /* SGMII */ + fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1); + fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2); + fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3); + fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4); + } else { + puts("Invalid SerDes1 protocol for T4240RDB\n"); + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + +#if (CONFIG_SYS_NUM_FMAN == 2) + if (srds_prtcl_s2 == 56) { + /* SGMII && XFI */ + fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); + fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); + fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); + fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8); + fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR); + } else { + puts("Invalid SerDes2 protocol for T4240RDB\n"); + } + + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + interface = fm_info_get_enet_if(i); + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } + + for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_XGMII: + dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); + fm_info_set_mdio(i, dev); + break; + default: + break; + } + } +#endif /* CONFIG_SYS_NUM_FMAN */ + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ + + return pci_eth_init(bis); +} diff --git a/board/freescale/t4rdb/law.c b/board/freescale/t4rdb/law.c new file mode 100644 index 00000000000..1f5876885c0 --- /dev/null +++ b/board/freescale/t4rdb/law.c @@ -0,0 +1,28 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + /* Limit DCSR to 32M to access NPC Trace Buffer */ + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c new file mode 100644 index 00000000000..6387a20caec --- /dev/null +++ b/board/freescale/t4rdb/pci.c @@ -0,0 +1,23 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/t4rdb/t4240rdb.c b/board/freescale/t4rdb/t4240rdb.c new file mode 100644 index 00000000000..5448c86c482 --- /dev/null +++ b/board/freescale/t4rdb/t4240rdb.c @@ -0,0 +1,125 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "t4rdb.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + + printf("Board: %sRDB, ", cpu->name); + + puts("SERDES Reference Clocks:\n"); + printf(" SERDES1=100MHz SERDES2=156.25MHz\n" + " SERDES3=100MHz SERDES4=100MHz\n"); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + return 0; +} + +int misc_init_r(void) +{ + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + fdt_fixup_dr_usb(blob, bd); + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif +} + +/* + * This function is called by bdinfo to print detail board information. + * As an exmaple for future board, we organize the messages into + * several sections. If applicable, the message is in the format of + * = + * It should aligned with normal output of bdinfo command. + * + * Voltage: Core, DDR and another configurable voltages + * Clock : Critical clocks which are not printed already + * RCW : RCW source if not printed already + * Misc : Other important information not in above catagories + */ +void board_detail(void) +{ + int rcwsrc; + + /* RCW section SW3[4] */ + rcwsrc = 0x0; + puts("RCW source = "); + switch (rcwsrc & 0x1) { + case 0x1: + puts("SDHC/eMMC\n"); + break; + default: + puts("I2C normal addressing\n"); + break; + } +} diff --git a/board/freescale/t4rdb/t4_pbi.cfg b/board/freescale/t4rdb/t4_pbi.cfg new file mode 100644 index 00000000000..c9f8ced2a3b --- /dev/null +++ b/board/freescale/t4rdb/t4_pbi.cfg @@ -0,0 +1,31 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#512KB SRAM +09010100 00000000 +09010104 fff80009 +09010f00 08000000 +#enable CPC1 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff80000 +09000d08 81000012 +#slow mdio clock +095fc030 00008148 +095fd030 00808148 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/board/freescale/t4rdb/t4_rcw.cfg b/board/freescale/t4rdb/t4_rcw.cfg new file mode 100644 index 00000000000..13408bd01fb --- /dev/null +++ b/board/freescale/t4rdb/t4_rcw.cfg @@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +#serdes protocol 28_56_2_10 +16070019 18101916 00000000 00000000 +70701050 00448c00 6c020000 f5000000 +00000000 ee0000ee 00000000 000287fc +00000000 50000000 00000000 00000028 diff --git a/board/freescale/t4rdb/t4rdb.h b/board/freescale/t4rdb/t4rdb.h new file mode 100644 index 00000000000..fb25d43291e --- /dev/null +++ b/board/freescale/t4rdb/t4rdb.h @@ -0,0 +1,18 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __T4RDB_H__ +#define __T4RDB_H__ + +#undef CONFIG_SYS_NUM_FM1_DTSEC +#undef CONFIG_SYS_NUM_FM2_DTSEC +#define CONFIG_SYS_NUM_FM1_DTSEC 4 +#define CONFIG_SYS_NUM_FM2_DTSEC 4 + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/t4rdb/tlb.c b/board/freescale/t4rdb/tlb.c new file mode 100644 index 00000000000..4b50bcd09b0 --- /dev/null +++ b/board/freescale/t4rdb/tlb.c @@ -0,0 +1,111 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 512K SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_512K, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_32M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_64K, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 9d90550794c..b7c6da95a29 100644 --- a/boards.cfg +++ b/boards.cfg @@ -983,6 +983,7 @@ Active powerpc mpc85xx - freescale t4qds Active powerpc mpc85xx - freescale t4qds T4240QDS_SECURE_BOOT T4240QDS:PPC_T4240,SECURE_BOOT Aneesh Bansal Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - +Active powerpc mpc85xx - freescale t4rdb T4240RDB T4240RDB:PPC_T4240 Chunhe Lan Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD controlcenterd:36BIT,SDCARD Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_36BIT_SDCARD_DEVELOP controlcenterd:36BIT,SDCARD,DEVELOP Dirk Eibach Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 4c3b93d413d..50cba64d99a 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -96,7 +96,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) else if (cmd->resp_type & MMC_RSP_PRESENT) xfertyp |= XFERTYP_RSPTYP_48; -#if defined(CONFIG_MX53) || defined(CONFIG_T4240QDS) +#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) xfertyp |= XFERTYP_CMDTYP_ABORT; #endif diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h new file mode 100644 index 00000000000..b1a8053a539 --- /dev/null +++ b/include/configs/T4240RDB.h @@ -0,0 +1,752 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * T4240 RDB board configuration file + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_T4240RDB +#define CONFIG_PHYS_64BIT + +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE4 + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg +#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg +#endif + +#define CONFIG_DDR_ECC + +#define CONFIG_CMD_REGINFO + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MP /* support multiple processors */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff40000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ + +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE + +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 +#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + +#define CONFIG_DDR_SPD +#define CONFIG_SYS_FSL_DDR3 + + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* controller 4, Base address 203000 */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#ifdef CONFIG_SYS_NO_FLASH +#ifndef CONFIG_RAMBOOT_PBL +#define CONFIG_ENV_IS_NOWHERE +#endif +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 1658) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_SYS_CLK_FREQ 66666666 +#define CONFIG_DDR_CLK_FREQ 133333333 + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +/* + * DDR Setup + */ +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x52 +#define SPD_EEPROM_ADDRESS2 0x54 +#define SPD_EEPROM_ADDRESS3 0x56 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_MAX_ECCPOS 256 +#define CONFIG_SYS_NAND_MAX_OOBFREE 2 +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ + | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ + | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + + +/* I2C */ +#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ +#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ +#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ + +#define I2C_MUX_CH_DEFAULT 0x8 +#define I2C_MUX_CH_VOL_MONITOR 0xa +#define I2C_MUX_CH_VSC3316_FS 0xc +#define I2C_MUX_CH_VSC3316_BS 0xd + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_ADDR 0x40 +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 50 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 50 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +#define CONFIG_SYS_PMAN +#define CONFIG_SYS_DPAA_DCE +#define CONFIG_SYS_DPAA_RMAN +#define CONFIG_SYS_INTERLAKEN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 825KB (1650 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_CORTINA +#define CONFIG_CORTINA_FW_ADDR 0xefe00000 +#define CONFIG_CORTINA_FW_LENGTH 0x40000 +#define CONFIG_PHY_TERANETICS +#define SGMII_PHY_ADDR1 0x0 +#define SGMII_PHY_ADDR2 0x1 +#define SGMII_PHY_ADDR3 0x2 +#define SGMII_PHY_ADDR4 0x3 +#define SGMII_PHY_ADDR5 0x4 +#define SGMII_PHY_ADDR6 0x5 +#define SGMII_PHY_ADDR7 0x6 +#define SGMII_PHY_ADDR8 0x7 +#define FM1_10GEC1_PHY_ADDR 0x10 +#define FM1_10GEC2_PHY_ADDR 0x11 +#define FM2_10GEC1_PHY_ADDR 0x12 +#define FM2_10GEC2_PHY_ADDR 0x13 +#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR +#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR +#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR +#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR +#endif + + +/* SATA */ +#ifdef CONFIG_FSL_SATA_V2 +#define CONFIG_LIBATA +#define CONFIG_FSL_SATA + +#define CONFIG_SYS_SATA_MAX_DEVICE 2 +#define CONFIG_SATA1 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA +#define CONFIG_SATA2 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA + +#define CONFIG_LBA48 +#define CONFIG_CMD_SATA +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* +* USB +*/ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#define CONFIG_HAS_FSL_DR_USB + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define __USB_PHY_TYPE utmi + +/* + * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be + * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way + * interleaving. It can be cacheline, page, bank, superbank. + * See doc/README.fsl-ddr for details. + */ +#define CTRL_INTLV_PREFERED 3way_4KB + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:" \ + "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ + "bank_intlv=auto;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=t4240rdb/t4240rdb.dtb\0" \ + "bdev=sda3\0" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#include + +#ifdef CONFIG_SECURE_BOOT +/* Secure Boot target was not getting build for T4240 because of + * increased binary size. So the size is being reduced by removing USB + * which is anyways not used in Secure Environment. + */ +#undef CONFIG_CMD_USB +#endif + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From c665c473b605349b1c58890493255dd70e0b60fe Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 24 Apr 2014 11:10:09 +0800 Subject: powerpc/t208x: enable errata A006261, A006593, A006379 Enable errata A006261, A006593, A006379 for T208x. Additionally enable CONFIG_CMD_ERRATA for T2080RDB. Signed-off-by: Shengzhou Liu --- arch/powerpc/include/asm/config_mpc85xx.h | 3 +++ arch/powerpc/include/asm/fsl_errata.h | 3 +++ include/configs/T208xRDB.h | 1 + 3 files changed, 7 insertions(+) (limited to 'include') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 864e74c0c76..0d6eb491f1a 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -798,6 +798,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022) #define CONFIG_SYS_FSL_SFP_VER_3_0 #define CONFIG_SYS_FSL_ISBC_VER 2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_SYS_FSL_ERRATUM_A006261 +#define CONFIG_SYS_FSL_ERRATUM_A006593 +#define CONFIG_SYS_FSL_ERRATUM_A006379 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index 4eba85cc347..d820121ee3a 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -52,6 +52,9 @@ static inline bool has_erratum_a006261(void) return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0); case SVR_T1040: return IS_SVR_REV(svr, 1, 0); + case SVR_T2080: + case SVR_T2081: + return IS_SVR_REV(svr, 1, 0); case SVR_P5040: return IS_SVR_REV(svr, 1, 0); } diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 0be0a0feb0b..5b261788c9a 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -721,6 +721,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA #define CONFIG_CMD_MII #define CONFIG_CMD_I2C #define CONFIG_CMD_PING -- cgit v1.3.1 From 18794944c6f60b912db8509012d10793f35586ae Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Wed, 30 Apr 2014 15:01:44 +0200 Subject: kmp204x: selftest/factory test pin support This patch defines the post_hotkeys_pressed() function that is used for: - triggering POST memory regions test - starting the test application through the checktestboot command in a script by setting the active bank to testbank The post_hotkeys_pressed return the state of the SELFTEST pin. The patch moves from the complete POST-memory test that is too long in its SLOW version for our production HW test procedure to the much shorter POST-memory-regions test. Finally, the unused #defines for the not so relevant mtest command are removed. Signed-off-by: Stefan Bigler Signed-off-by: Valentin Longchamp --- board/keymile/kmp204x/kmp204x.c | 13 +++++++++++++ include/configs/km/kmp204x-common.h | 6 +----- 2 files changed, 14 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index fba1bdd4381..1ce8429075f 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -250,3 +250,16 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_mac_addresses(blob); #endif } + +#if defined(CONFIG_POST) + +/* DIC26_SELFTEST GPIO used to start factory test sw */ +#define SELFTEST_PORT GPIO_A +#define SELFTEST_PIN 31 + +int post_hotkeys_pressed(void) +{ + qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN); + return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN); +} +#endif diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 418e3d12981..f9bcef3ff1d 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -85,11 +85,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00800000 -#define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_PANIC_HANG /* do not reset board on panic */ +#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ /* * Config the L3 Cache as L3 SRAM -- cgit v1.3.1 From 848b31ab0f56d828b1d986c48b495d15abb73a65 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Wed, 30 Apr 2014 15:01:45 +0200 Subject: kmp204x: update the CONFIG_PRAM and CONFIG_KM_RESERVED_PRAM defines This prevents u-boot from accessing into the reserved memory areas that we have for /var and the logbooks. Signed-off-by: Valentin Longchamp --- include/configs/km/kmp204x-common.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index f9bcef3ff1d..e4c5e7bd99d 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -139,10 +139,12 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_KM_PNVRAM 0x80000 /* physical RAM MTD size [hex] */ #define CONFIG_KM_PHRAM 0x100000 -/* resereved pram area at the end of memroy [hex] */ -#define CONFIG_KM_RESERVED_PRAM 0x0 -/* enable protected RAM */ -#define CONFIG_PRAM 0 +/* reserved pram area at the end of memory [hex] + * u-boot reserves some memory for the MP boot page */ +#define CONFIG_KM_RESERVED_PRAM 0x1000 +/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable + * is not valid yet, which is the case for when u-boot copies itself to RAM */ +#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) #define CONFIG_KM_CRAMFS_ADDR 0x2000000 #define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ -- cgit v1.3.1 From 522641a78862d2ecf9b89cc29dfb4429ee1b4103 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Wed, 30 Apr 2014 15:01:49 +0200 Subject: kmp204x: enable the errata command Signed-off-by: Valentin Longchamp --- include/configs/km/kmp204x-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index e4c5e7bd99d..efd96352eca 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -381,6 +381,7 @@ int get_scl(void); */ #define CONFIG_CMD_PCI #define CONFIG_CMD_NET +#define CONFIG_CMD_ERRATA /* we don't need flash support */ #define CONFIG_SYS_NO_FLASH -- cgit v1.3.1 From eab3bfbcd18daa8c29c8b6eda00527c01d6f8f27 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Wed, 30 Apr 2014 19:21:14 +0200 Subject: PPC 85xx QEMU: Make a generic board file This patch enables the E500 QEMU board to use the generic cross-arch board infrastructure. Signed-off-by: Alexander Graf --- include/configs/qemu-ppce500.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 10e014d33c4..763a47ac3dc 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -19,6 +19,7 @@ #undef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xf01000 /* 15 MB */ +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_SYS_MPC85XX_NO_RESETVEC -- cgit v1.3.1 From 18025756b5e79ae96f67e1b5ac87d5ff6467d1cc Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 25 Apr 2014 12:06:17 -0700 Subject: powerpc/mpc8572ds: Increase u-boot size to 768KB U-boot image has grown and exceeded the predefined 512KB. Increasing to 768KB to align with other powerpc boards. Tested on MPC8572DS for 32- and 36-bit targets with NOR flash boot. NAND boot is not covered by this patch. Also update board maintainer for these boards. Signed-off-by: York Sun Acked-by: Heiko Schocher --- boards.cfg | 4 ++-- include/configs/MPC8572DS.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/boards.cfg b/boards.cfg index ba54e2fd362..9fa01a2c35f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -812,8 +812,8 @@ Active powerpc mpc85xx - freescale mpc8568mds Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS - - Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM - Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND - -Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - - -Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT - +Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - York Sun +Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT York Sun Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND - Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND - Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT - diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 7b63945888b..3a30febcba2 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -30,7 +30,7 @@ #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#define CONFIG_SYS_TEXT_BASE 0xeff40000 #endif #ifndef CONFIG_RESET_VECTOR_ADDRESS -- cgit v1.3.1 From 701e640145474131161de53a407d95d0d2f77082 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 30 Apr 2014 14:43:47 -0700 Subject: powerpc/mpc85xx: Fix boot_flag for calling board_init_f() baord_init_f takes one argument, boot_flag. It has not been used for powerpc, until recently changing to use generic board architecture. The boot flag is added as a return value from cpu_init_f(). Signed-off-by: York Sun CC: Alexander Graf --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 7 ++++--- arch/powerpc/cpu/mpc85xx/spl_minimal.c | 4 +++- arch/powerpc/cpu/mpc85xx/start.S | 2 +- include/common.h | 5 ++++- 4 files changed, 12 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 2656b794be7..d6cf88555a1 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -368,12 +368,12 @@ void fsl_erratum_a007212_workaround(void) } #endif -void cpu_init_f (void) +ulong cpu_init_f(void) { + ulong flag = 0; extern void m8560_cpm_reset (void); #ifdef CONFIG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); #endif #if defined(CONFIG_SECURE_BOOT) struct law_entry law; @@ -442,13 +442,14 @@ void cpu_init_f (void) #ifdef CONFIG_DEEP_SLEEP /* disable the console if boot from deep sleep */ if (in_be32(&gur->scrtsr[0]) & (1 << 3)) - gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; + flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; #endif #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 fsl_erratum_a007212_workaround(); #endif + return flag; } /* Implement a dummy function for those platforms w/o SERDES */ diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index 9e4c6c90788..cc45f715e84 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -12,7 +12,7 @@ DECLARE_GLOBAL_DATA_PTR; -void cpu_init_f(void) +ulong cpu_init_f(void) { #ifdef CONFIG_SYS_INIT_L2_ADDR ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; @@ -27,6 +27,8 @@ void cpu_init_f(void) out_be32(&l2cache->l2ctl, (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE)); #endif + + return 0; } #ifndef CONFIG_SYS_FSL_TBCLK_DIV diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 01491464587..d8c9fb6b287 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1158,7 +1158,7 @@ _start_cont: mtmsr r3 isync - bl cpu_init_f + bl cpu_init_f /* return boot_flag for calling board_init_f */ bl board_init_f isync diff --git a/include/common.h b/include/common.h index 2adf5f90b8c..13e5dc74e63 100644 --- a/include/common.h +++ b/include/common.h @@ -729,9 +729,12 @@ void get_sys_info ( sys_info_t * ); #if defined(CONFIG_8xx) || defined(CONFIG_MPC8260) void cpu_init_f (volatile immap_t *immr); #endif -#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx) +#if defined(CONFIG_4xx) || defined(CONFIG_MCF52x2) || defined(CONFIG_MPC86xx) void cpu_init_f (void); #endif +#ifdef CONFIG_MPC85xx +ulong cpu_init_f(void); +#endif int cpu_init_r (void); #if defined(CONFIG_MPC8260) -- cgit v1.3.1 From 15672c6dbd7e5a110773480ccfe47b98ba1dc6f8 Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 30 Apr 2014 14:43:49 -0700 Subject: powerpc/freescale: Convert selected boards to generic board architecture This patch converts the following boards to use generic board: MPC8536DS, MPC8572DS, MPC8641HPCN, p1_p2_rdb_pc, corenet_ds, t4qds, B4860QDS. It has been tested on NOR boot on MPC8536DS, MPC8572DS, P1021RDB, P4080DS, P5020DS, P5040DS, P3041DS, T4240QDS, B4860QDS. Signed-off-by: York Sun CC: Ying Zhang CC: Prabhakar Kushwaha CC: Haijun.Zhang CC: Scott Wood CC: Shaohui Xie --- include/configs/B4860QDS.h | 3 +++ include/configs/MPC8536DS.h | 2 ++ include/configs/MPC8572DS.h | 3 +++ include/configs/MPC8641HPCN.h | 3 +++ include/configs/corenet_ds.h | 3 +++ include/configs/p1_p2_rdb_pc.h | 3 +++ include/configs/t4qds.h | 2 ++ 7 files changed, 19 insertions(+) (limited to 'include') diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index a6125568a2c..47aca9c00f2 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -7,6 +7,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* * B4860 QDS board configuration file */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index f15e1626f0b..72f5fde16a7 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -11,6 +11,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_36BIT diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 3a30febcba2..48ae9d4cae6 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -11,6 +11,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_36BIT diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 7443acec80b..a0d7d52627d 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -16,6 +16,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + /* High Level Configuration Options */ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index db6b9be73c6..c8b7c2dff78 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -10,6 +10,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #include "../board/freescale/common/ics307_clk.h" #ifdef CONFIG_RAMBOOT_PBL diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index e745945ba73..56b638e23b6 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -10,6 +10,9 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO + #ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT #endif diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index 36bc5294ef4..75609b9f617 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -10,6 +10,8 @@ #ifndef __T4QDS_H #define __T4QDS_H +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_CMD_REGINFO /* High Level Configuration Options */ -- cgit v1.3.1