From 93f26f130eede8db0cb47afcaf66016987b91731 Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Fri, 5 Sep 2014 13:52:36 +0800 Subject: net: Merge asm/fsl_enet.h into fsl_mdio.h fsl_enet.h defines the mapping of the usual MII management registers, which are included in the MDIO register block common to Freescale ethernet controllers. So it shouldn't depend on the CPU architecture but it should be actually part of the arch independent fsl_mdio.h. To remove the arch dependency, merge the content of asm/fsl_enet.h into fsl_mdio.h. Some files (like fm_eth.h) were simply including fsl_enet.h only for phy.h. These were updated to include phy.h instead. Signed-off-by: Claudiu Manoil --- include/fm_eth.h | 2 +- include/fsl_mdio.h | 13 ++++++++++++- include/tsec.h | 2 +- 3 files changed, 14 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/fm_eth.h b/include/fm_eth.h index 98edfcf4add..e46a684129d 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -8,8 +8,8 @@ #define __FM_ETH_H__ #include +#include #include -#include enum fm_port { FM1_DTSEC1, diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h index b58713d896f..2137282df3f 100644 --- a/include/fsl_mdio.h +++ b/include/fsl_mdio.h @@ -10,7 +10,18 @@ #include #include -#include + +struct tsec_mii_mng { + u32 miimcfg; /* MII management configuration reg */ + u32 miimcom; /* MII management command reg */ + u32 miimadd; /* MII management address reg */ + u32 miimcon; /* MII management control reg */ + u32 miimstat; /* MII management status reg */ + u32 miimind; /* MII management indication reg */ + u32 ifstat; /* Interface Status Register */ +}; + +int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc); /* PHY register offsets */ #define PHY_EXT_PAGE_ACCESS 0x1f diff --git a/include/tsec.h b/include/tsec.h index 1046426c5c1..20547153a19 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -20,7 +20,7 @@ #include #include #include -#include +#include #define TSEC_SIZE 0x01000 #define TSEC_MDIO_OFFSET 0x01000 -- cgit v1.3.1 From 52d00a812a29974e660f64a8839ddb550dca5290 Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Fri, 5 Sep 2014 13:52:38 +0800 Subject: ls102xa: etsec: Add etsec support for LS102xA This patch is to add etsec support for LS102xA. First, Little-endian descriptor mode should be enabled. So RxBDs and TxBDs are interpreted with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET are different from PowerPC, redefine them for LS1021xA. Signed-off-by: Alison Wang --- drivers/net/tsec.c | 7 +++++++ include/tsec.h | 7 ++++++- 2 files changed, 13 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index e9138f03381..79d656133ad 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -20,6 +20,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -270,6 +271,9 @@ void redundant_init(struct eth_device *dev) out_be32(®s->tstat, TSTAT_CLEAR_THALT); out_be32(®s->rstat, RSTAT_CLEAR_RHALT); clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); +#ifdef CONFIG_LS102XA + setbits_be32(®s->dmactrl, DMACTRL_LE); +#endif do { uint16_t status; @@ -366,6 +370,9 @@ static void startup_tsec(struct eth_device *dev) out_be32(®s->tstat, TSTAT_CLEAR_THALT); out_be32(®s->rstat, RSTAT_CLEAR_RHALT); clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); +#ifdef CONFIG_LS102XA + setbits_be32(®s->dmactrl, DMACTRL_LE); +#endif } /* This returns the status bits of the device. The return value diff --git a/include/tsec.h b/include/tsec.h index 20547153a19..1119d2cb60b 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -20,10 +20,14 @@ #include #include #include -#include +#ifdef CONFIG_LS102XA +#define TSEC_SIZE 0x40000 +#define TSEC_MDIO_OFFSET 0x40000 +#else #define TSEC_SIZE 0x01000 #define TSEC_MDIO_OFFSET 0x01000 +#endif #define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520) @@ -128,6 +132,7 @@ #define DMACTRL_INIT_SETTINGS 0x000000c3 #define DMACTRL_GRS 0x00000010 #define DMACTRL_GTS 0x00000008 +#define DMACTRL_LE 0x00008000 #define TSTAT_CLEAR_THALT 0x80000000 #define RSTAT_CLEAR_RHALT 0x00800000 -- cgit v1.3.1 From c82e9de400ee36038c76be67c5a6fb39c165ac1c Mon Sep 17 00:00:00 2001 From: Wang Huan Date: Fri, 5 Sep 2014 13:52:39 +0800 Subject: esdhc: Add CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE macros For LS102xA, the processor is in little-endian mode, while esdhc IP is in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE are added. So accessing ESDHC registers can be determined by ESDHC IP's endian mode. Signed-off-by: Alison Wang --- doc/README.fsl-esdhc | 5 +++++ include/fsl_esdhc.h | 14 +++++++++++++- 2 files changed, 18 insertions(+), 1 deletion(-) create mode 100644 doc/README.fsl-esdhc (limited to 'include') diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc new file mode 100644 index 00000000000..b70f271d1a4 --- /dev/null +++ b/doc/README.fsl-esdhc @@ -0,0 +1,5 @@ +CONFIG_SYS_FSL_ESDHC_LE means ESDHC IP is in little-endian mode. +CONFIG_SYS_FSL_ESDHC_BE means ESDHC IP is in big-endian mode. + +Accessing ESDHC registers can be determined by ESDHC IP's endian +mode or processor's endian mode. diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 9814964937d..c1b6648591e 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -162,7 +162,19 @@ struct fsl_esdhc_cfg { }; /* Select the correct accessors depending on endianess */ -#if __BYTE_ORDER == __LITTLE_ENDIAN +#if defined CONFIG_SYS_FSL_ESDHC_LE +#define esdhc_read32 in_le32 +#define esdhc_write32 out_le32 +#define esdhc_clrsetbits32 clrsetbits_le32 +#define esdhc_clrbits32 clrbits_le32 +#define esdhc_setbits32 setbits_le32 +#elif defined(CONFIG_SYS_FSL_ESDHC_BE) +#define esdhc_read32 in_be32 +#define esdhc_write32 out_be32 +#define esdhc_clrsetbits32 clrsetbits_be32 +#define esdhc_clrbits32 clrbits_be32 +#define esdhc_setbits32 setbits_be32 +#elif __BYTE_ORDER == __LITTLE_ENDIAN #define esdhc_read32 in_le32 #define esdhc_write32 out_le32 #define esdhc_clrsetbits32 clrsetbits_le32 -- cgit v1.3.1 From ef87cab66492fe530bb6ec2e499b030c5ae60286 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 5 Sep 2014 13:52:43 +0800 Subject: driver/ddr/fsl: Add support of overriding chip select write leveling JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: York Sun --- drivers/ddr/fsl/ctrl_regs.c | 3 +++ drivers/ddr/fsl/interactive.c | 2 ++ include/fsl_ddr_sdram.h | 2 ++ 3 files changed, 7 insertions(+) (limited to 'include') diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 5e0ee77e46c..d9cac2296a2 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -2276,6 +2276,9 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, if (ip_rev > 0x40400) unq_mrs_en = 1; + if (ip_rev > 0x40700) + ddr->debug[18] = popts->cswl_override; + set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en); set_ddr_sdram_mode(ddr, popts, common_dimm, cas_latency, additive_latency, unq_mrs_en); diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index 7fb418744e0..6aa16b23ddc 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -511,6 +511,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, CTRL_OPTIONS(wrlvl_override), CTRL_OPTIONS(wrlvl_sample), CTRL_OPTIONS(wrlvl_start), + CTRL_OPTIONS(cswl_override), CTRL_OPTIONS(rcw_override), CTRL_OPTIONS(rcw_1), CTRL_OPTIONS(rcw_2), @@ -801,6 +802,7 @@ static void print_memctl_options(const memctl_options_t *popts) CTRL_OPTIONS(wrlvl_override), CTRL_OPTIONS(wrlvl_sample), CTRL_OPTIONS(wrlvl_start), + CTRL_OPTIONS_HEX(cswl_override), CTRL_OPTIONS(rcw_override), CTRL_OPTIONS(rcw_1), CTRL_OPTIONS(rcw_2), diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index e8a2db91cb7..987119b014e 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -281,6 +281,7 @@ typedef struct memctl_options_partial_s { #define DDR_DATA_BUS_WIDTH_64 0 #define DDR_DATA_BUS_WIDTH_32 1 #define DDR_DATA_BUS_WIDTH_16 2 +#define DDR_CSWL_CS0 0x04000001 /* * Generalized parameters for memory controller configuration, * might be a little specific to the FSL memory controller @@ -340,6 +341,7 @@ typedef struct memctl_options_s { unsigned int cpo_override; unsigned int write_data_delay; /* DQS adjust */ + unsigned int cswl_override; unsigned int wrlvl_override; unsigned int wrlvl_sample; /* Write leveling */ unsigned int wrlvl_start; -- cgit v1.3.1 From 550e3dc090888fbc9c0fc4066541a2b4eb88c47b Mon Sep 17 00:00:00 2001 From: Wang Huan Date: Fri, 5 Sep 2014 13:52:44 +0800 Subject: arm: ls102xa: Add basic support for LS1021AQDS board LS102xA is an ARMv7 implementation. This patch is to add basic support for LS1021AQDS board. One DDR controller DUART1 is used as the console For the detail board information, please refer to README. Signed-off-by: Alison Wang Signed-off-by: Jason Jin Signed-off-by: York Sun Signed-off-by: Yuan Yao Signed-off-by: Prabhakar Kushwaha --- arch/arm/Kconfig | 4 + board/freescale/ls1021aqds/Kconfig | 23 ++ board/freescale/ls1021aqds/MAINTAINERS | 6 + board/freescale/ls1021aqds/Makefile | 9 + board/freescale/ls1021aqds/README | 112 ++++++++ board/freescale/ls1021aqds/ddr.c | 159 +++++++++++ board/freescale/ls1021aqds/ddr.h | 49 ++++ board/freescale/ls1021aqds/eth.c | 186 ++++++++++++ board/freescale/ls1021aqds/ls1021aqds.c | 255 +++++++++++++++++ board/freescale/ls1021aqds/ls1021aqds_qixis.h | 35 +++ configs/ls1021aqds_nor_defconfig | 2 + include/configs/ls1021aqds.h | 389 ++++++++++++++++++++++++++ 12 files changed, 1229 insertions(+) create mode 100644 board/freescale/ls1021aqds/Kconfig create mode 100644 board/freescale/ls1021aqds/MAINTAINERS create mode 100644 board/freescale/ls1021aqds/Makefile create mode 100644 board/freescale/ls1021aqds/README create mode 100644 board/freescale/ls1021aqds/ddr.c create mode 100644 board/freescale/ls1021aqds/ddr.h create mode 100644 board/freescale/ls1021aqds/eth.c create mode 100644 board/freescale/ls1021aqds/ls1021aqds.c create mode 100644 board/freescale/ls1021aqds/ls1021aqds_qixis.h create mode 100644 configs/ls1021aqds_nor_defconfig create mode 100644 include/configs/ls1021aqds.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 22f0f09af6e..d7ed3e207d2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -470,6 +470,9 @@ config TARGET_LS2085A_EMU config TARGET_LS2085A_SIMU bool "Support ls2085a_simu" +config TARGET_LS1021AQDS + bool "Support ls1021aqds_nor" + config TARGET_BALLOON3 bool "Support balloon3" @@ -594,6 +597,7 @@ source "board/eukrea/cpu9260/Kconfig" source "board/eukrea/cpuat91/Kconfig" source "board/faraday/a320evb/Kconfig" source "board/freescale/ls2085a/Kconfig" +source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/mx23evk/Kconfig" source "board/freescale/mx25pdk/Kconfig" source "board/freescale/mx28evk/Kconfig" diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig new file mode 100644 index 00000000000..c28bd2b8358 --- /dev/null +++ b/board/freescale/ls1021aqds/Kconfig @@ -0,0 +1,23 @@ +if TARGET_LS1021AQDS + +config SYS_CPU + string + default "armv7" + +config SYS_BOARD + string + default "ls1021aqds" + +config SYS_VENDOR + string + default "freescale" + +config SYS_SOC + string + default "ls102xa" + +config SYS_CONFIG_NAME + string + default "ls1021aqds" + +endif diff --git a/board/freescale/ls1021aqds/MAINTAINERS b/board/freescale/ls1021aqds/MAINTAINERS new file mode 100644 index 00000000000..021d82b74d3 --- /dev/null +++ b/board/freescale/ls1021aqds/MAINTAINERS @@ -0,0 +1,6 @@ +LS1021AQDS BOARD +M: Alison Wang +S: Maintained +F: board/freescale/ls1021aqds/ +F: include/configs/ls1021aqds.h +F: configs/ls1021aqds_nor_defconfig diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile new file mode 100644 index 00000000000..3b6903c83bc --- /dev/null +++ b/board/freescale/ls1021aqds/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021aqds.o +obj-y += ddr.o +obj-y += eth.o diff --git a/board/freescale/ls1021aqds/README b/board/freescale/ls1021aqds/README new file mode 100644 index 00000000000..c561776621a --- /dev/null +++ b/board/freescale/ls1021aqds/README @@ -0,0 +1,112 @@ +Overview +-------- +The LS1021AQDS is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +------------------ +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000, as well as virtualization support, advanced +security features and the broadest array of high-speed interconnects and +optimized peripheral features ever offered in a sub-3 W processor. + +The QorIQ LS1021A processor features an integrated LCD controller, +CAN controller for implementing industrial protocols, DDR3L/4 running +up to 1600 MHz, integrated security engine and QUICC Engine, and ECC +protection on both L1 and L2 caches. The LS1021A processor is pin- and +software-compatible with the QorIQ LS1020A and LS1022A processors. + +The LS1021A SoC includes the following function and features: + + - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture + - Dual high-preformance ARM Cortex-A7 cores, each core includes: + - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) + - 512 Kbyte shared coherent L2 Cache (with ECC protection) + - NEON Co-processor (per core) + - 40-bit physical addressing + - Vector floating-point support + - ARM Core-Link CCI-400 Cache Coherent Interconnect + - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration + supporting speeds up to 1600Mtps + - ECC and interleaving support + - VeTSEC Ethernet complex + - Up to 3x virtualized 10/100/1000 Ethernet controllers + - MII, RMII, RGMII, and SGMII support + - QoS, lossless flow control, and IEEE 1588 support + - 4-lane 6GHz SerDes + - High speed interconnect (4 SerDes lanes with are muxed for these protocol) + - Two PCI Express Gen2 controllers running at up to 5 GHz + - One Serial ATA 3.0 supporting 6 GT/s operation + - Two SGMII interfaces supporting 1000 Mbps + - Additional peripheral interfaces + - One high-speed USB 3.0 controller with integrated PHY and one high-speed + USB 2.00 controller with ULPI + - Integrated flash controller (IFC) with 16-bit interface + - Quad SPI NOR Flash + - One enhanced Secure digital host controller + - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) + - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power + UARTs + - Three I2C controllers + - Eight FlexTimers four supporting PWM and four FlexCAN ports + - Four GPIO controllers supporting up to 109 general purpose I/O signals + - Integrated advanced audio block: + - Four synchronous audio interfaces (SAI) + - Sony/Philips Digital Interconnect Format (SPDIF) + - Asynchronous Sample Rate Converter (ASRC) + - Hardware based crypto offload engine + - IPSec forwarding at up to 1Gbps + - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported + - Public key hardware accelerator + - True Random Number Generator (NIST Certified) + - Advanced Encryption Standard Accelerators (AESA) + - Data Encryption Standard Accelerators + - QUICC Engine ULite block + - Two universal communication controllers (TDM and HDLC) supporting 64 + multichannels, each running at 64 Kbps + - Support for 256 channels of HDLC + - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported + +LS1021AQDS board Overview +------------------------- + - DDR Controller + - Supports rates of up to 1600 MHz data-rate + - Supports one DDR3LP UDIMM, of single-, dual- types. + - IFC/Local Bus + - NAND flash: 512M 8-bit NAND flash + - NOR: 128MB 16-bit NOR Flash + - Ethernet + - Three on-board RGMII 10/100/1G ethernet ports. + - FPGA + - Clocks + - System and DDR clock (SYSCLK, DDRCLK) + - SERDES clocks + - Power Supplies + - SDHC + - SDHC/SDXC connector + - Other IO + - Two Serial ports + - Three I2C ports + +Memory map +----------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB +0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB +0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB diff --git a/board/freescale/ls1021aqds/ddr.c b/board/freescale/ls1021aqds/ddr.c new file mode 100644 index 00000000000..679c654fb57 --- /dev/null +++ b/board/freescale/ls1021aqds/ddr.c @@ -0,0 +1,159 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include "ddr.h" + +DECLARE_GLOBAL_DATA_PTR; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 3) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->cpo_override = pbsp->cpo_override; + popts->write_data_delay = + pbsp->write_data_delay; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found for %lu MT/s\n", + ddr_freq); + printf("Trying to use the highest speed (%u) parameters\n", + pbsp_highest->datarate_mhz_high); + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + } else { + panic("DIMM is not supported by this board"); + } +found: + debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n", + pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb); + + /* force DDR bus width to 32 bits */ + popts->data_bus_width = 1; + popts->otf_burst_chop_en = 0; + popts->burst_length = DDR_BL8; + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 1; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->cswl_override = DDR_CSWL_CS0; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +#ifdef CONFIG_SYS_DDR_RAW_TIMING +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tckmin_x_ps = 1071, + .caslat_x = 0xfe << 4, /* 5,6,7,8 */ + .taa_ps = 13125, + .twr_ps = 15000, + .trcd_ps = 13125, + .trrd_ps = 7500, + .trp_ps = 13125, + .tras_ps = 37500, + .trc_ps = 50625, + .trfc_ps = 160000, + .twtr_ps = 7500, + .trtp_ps = 7500, + .refresh_rate_ps = 7800000, + .tfaw_ps = 37500, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + static const char dimm_model[] = "Fixed DDR on board"; + + if (((controller_number == 0) && (dimm_number == 0)) || + ((controller_number == 1) && (dimm_number == 0))) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} +#endif + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing DDR....using SPD\n"); + dram_size = fsl_ddr_sdram(); + + return dram_size; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h new file mode 100644 index 00000000000..16d87cbe82f --- /dev/null +++ b/board/freescale/ls1021aqds/ddr.h @@ -0,0 +1,49 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR_H__ +#define __DDR_H__ +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 rank_gb; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo_override; + u32 write_data_delay; + u32 force_2t; +}; + +/* + * These tables contain all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | + */ + {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +#endif diff --git a/board/freescale/ls1021aqds/eth.c b/board/freescale/ls1021aqds/eth.c new file mode 100644 index 00000000000..be351befec0 --- /dev/null +++ b/board/freescale/ls1021aqds/eth.c @@ -0,0 +1,186 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file handles the board muxing between the RGMII/SGMII PHYs on + * Freescale LS1021AQDS board. The RGMII PHYs are the three on-board 1Gb + * ports. The SGMII PHYs are provided by the standard Freescale four-port + * SGMII riser card. + * + * Muxing is handled via the PIXIS BRDCFG4 register. The EMI1 bits control + * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII depends + * on which port is used. The value for SGMII depends on which slot the riser + * is inserted in. + */ + +#include +#include +#include +#include +#include +#include + +#include "../common/sgmii_riser.h" +#include "../common/qixis.h" + +#define EMI1_MASK 0x1f +#define EMI1_RGMII0 1 +#define EMI1_RGMII1 2 +#define EMI1_RGMII2 3 +#define EMI1_SGMII1 0x1c +#define EMI1_SGMII2 0x1d + +struct ls1021a_mdio { + struct mii_dev *realbus; +}; + +static void ls1021a_mux_mdio(int addr) +{ + u8 brdcfg4; + + brdcfg4 = QIXIS_READ(brdcfg[4]); + brdcfg4 &= EMI1_MASK; + + switch (addr) { + case EMI1_RGMII0: + brdcfg4 |= 0; + break; + case EMI1_RGMII1: + brdcfg4 |= 0x20; + break; + case EMI1_RGMII2: + brdcfg4 |= 0x40; + break; + case EMI1_SGMII1: + brdcfg4 |= 0x60; + break; + case EMI1_SGMII2: + brdcfg4 |= 0x80; + break; + default: + brdcfg4 |= 0xa0; + break; + } + + QIXIS_WRITE(brdcfg[4], brdcfg4); +} + +static int ls1021a_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct ls1021a_mdio *priv = bus->priv; + + ls1021a_mux_mdio(addr); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int ls1021a_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct ls1021a_mdio *priv = bus->priv; + + ls1021a_mux_mdio(addr); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int ls1021a_mdio_reset(struct mii_dev *bus) +{ + struct ls1021a_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static int ls1021a_mdio_init(char *realbusname, char *fakebusname) +{ + struct ls1021a_mdio *lsmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate LS102xA MDIO bus\n"); + return -1; + } + + lsmdio = malloc(sizeof(*lsmdio)); + if (!lsmdio) { + printf("Failed to allocate LS102xA private data\n"); + free(bus); + return -1; + } + + bus->read = ls1021a_mdio_read; + bus->write = ls1021a_mdio_write; + bus->reset = ls1021a_mdio_reset; + sprintf(bus->name, fakebusname); + + lsmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!lsmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(lsmdio); + return -1; + } + + bus->priv = lsmdio; + + return mdio_register(bus); +} + +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[3]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + if (is_serdes_configured(SGMII_TSEC1)) { + puts("eTSEC1 is in sgmii mode\n"); + tsec_info[num].flags |= TSEC_SGMII; + tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; + } else { + tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; + } + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (is_serdes_configured(SGMII_TSEC2)) { + puts("eTSEC2 is in sgmii mode\n"); + tsec_info[num].flags |= TSEC_SGMII; + tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; + } else { + tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; + } + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + +#ifdef CONFIG_FSL_SGMII_RISER + fsl_sgmii_riser_init(tsec_info, num); +#endif + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + + /* Register the virtual MDIO front-ends */ + ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_RGMII_MDIO"); + ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_SGMII_MDIO"); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c new file mode 100644 index 00000000000..12e83f76454 --- /dev/null +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -0,0 +1,255 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "ls1021aqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +enum { + MUX_TYPE_SD_PCI4, + MUX_TYPE_SD_PC_SA_SG_SG, + MUX_TYPE_SD_PC_SA_PC_SG, + MUX_TYPE_SD_PC_SG_SG, +}; + +int checkboard(void) +{ + char buf[64]; + u8 sw; + + puts("Board: LS1021AQDS\n"); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw == 0x8) + puts("PromJet\n"); + else if (sw == 0x9) + puts("NAND\n"); + else if (sw == 0x15) + printf("IFCCard\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + + printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n", + QIXIS_READ(id), QIXIS_READ(arch)); + + printf("FPGA: v%d (%s), build %d\n", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch (sysclk_conf & 0x0f) { + case QIXIS_SYSCLK_64: + return 64000000; + case QIXIS_SYSCLK_83: + return 83333333; + case QIXIS_SYSCLK_100: + return 100000000; + case QIXIS_SYSCLK_125: + return 125000000; + case QIXIS_SYSCLK_133: + return 133333333; + case QIXIS_SYSCLK_150: + return 150000000; + case QIXIS_SYSCLK_160: + return 160000000; + case QIXIS_SYSCLK_166: + return 166666666; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((ddrclk_conf & 0x30) >> 4) { + case QIXIS_DDRCLK_100: + return 100000000; + case QIXIS_DDRCLK_125: + return 125000000; + case QIXIS_DDRCLK_133: + return 133333333; + } + return 66666666; +} + +int dram_init(void) +{ + gd->ram_size = initdram(0); + + return 0; +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {CONFIG_SYS_FSL_ESDHC_ADDR}, +}; + +int board_mmc_init(bd_t *bis) +{ + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} +#endif + +int select_i2c_ch_pca9547(u8 ch) +{ + int ret; + + ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1); + if (ret) { + puts("PCA: failed to select proper channel\n"); + return ret; + } + + return 0; +} + +int board_early_init_f(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + +#ifdef CONFIG_TSEC_ENET + out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV); + out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV); +#endif + +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + + /* Workaround for the issue that DDR could not respond to + * barrier transaction which is generated by executing DSB/ISB + * instruction. Set CCI-400 control override register to + * terminate the barrier transaction. After DDR is initialized, + * allow barrier transaction to DDR again */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); + + return 0; +} + +int config_board_mux(int ctrl_type) +{ + u8 reg12; + + reg12 = QIXIS_READ(brdcfg[12]); + + switch (ctrl_type) { + case MUX_TYPE_SD_PCI4: + reg12 = 0x38; + break; + case MUX_TYPE_SD_PC_SA_SG_SG: + reg12 = 0x01; + break; + case MUX_TYPE_SD_PC_SA_PC_SG: + reg12 = 0x01; + break; + case MUX_TYPE_SD_PC_SG_SG: + reg12 = 0x21; + break; + default: + printf("Wrong mux interface type\n"); + return -1; + } + + QIXIS_WRITE(brdcfg[12], reg12); + + return 0; +} + +int config_serdes_mux(void) +{ + struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 cfg; + + cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; + cfg >>= RCWSR4_SRDS1_PRTCL_SHIFT; + + switch (cfg) { + case 0x0: + config_board_mux(MUX_TYPE_SD_PCI4); + break; + case 0x30: + config_board_mux(MUX_TYPE_SD_PC_SA_SG_SG); + break; + case 0x60: + config_board_mux(MUX_TYPE_SD_PC_SG_SG); + break; + case 0x70: + config_board_mux(MUX_TYPE_SD_PC_SA_PC_SG); + break; + default: + printf("SRDS1 prtcl:0x%x\n", cfg); + break; + } + + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + + /* Set CCI-400 control override register to + * enable barrier transaction */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); + +#ifndef CONFIG_SYS_FSL_NO_SERDES + fsl_serdes_init(); + config_serdes_mux(); +#endif + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} diff --git a/board/freescale/ls1021aqds/ls1021aqds_qixis.h b/board/freescale/ls1021aqds/ls1021aqds_qixis.h new file mode 100644 index 00000000000..09b3be2f9c2 --- /dev/null +++ b/board/freescale/ls1021aqds/ls1021aqds_qixis.h @@ -0,0 +1,35 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1021AQDS_QIXIS_H__ +#define __LS1021AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1021AQDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 +#define QIXIS_SYSCLK_150 0x5 +#define QIXIS_SYSCLK_160 0x6 +#define QIXIS_SYSCLK_166 0x7 +#define QIXIS_SYSCLK_64 0x8 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +#define QIXIS_SRDS1CLK_100 0x0 + +#endif diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig new file mode 100644 index 00000000000..9e42d61095b --- /dev/null +++ b/configs/ls1021aqds_nor_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1021AQDS=y diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h new file mode 100644 index 00000000000..657e3b6d48d --- /dev/null +++ b/include/configs/ls1021aqds.h @@ -0,0 +1,389 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_LS102XA + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +/* + * Generic Timer Definitions + */ +#define GENERIC_TIMER_CLK 12500000 + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif + +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x67f80000 +#endif + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CONFIG_DDR_SPD +#define SPD_EEPROM_ADDRESS 0x51 +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define CONFIG_SYS_DDR_RAW_TIMING + +#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ +#define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_SYS_HAS_SERDES + +/* + * IFC Definitions + */ +#define CONFIG_FSL_IFC +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) + +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1a) | \ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWPH(0xe) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ + CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} + +/* + * NAND Flash Definitions + */ +#define CONFIG_NAND_FSL_IFC + +#define CONFIG_SYS_NAND_BASE 0x7e800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x7) | \ + FTIM0_NAND_TWH(0xa)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0xe) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ + FTIM2_NAND_TREH(0xa) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* + * QIXIS Definitions + */ +#define CONFIG_FSL_QIXIS + +#ifdef CONFIG_FSL_QIXIS +#define QIXIS_BASE 0x7fb00000 +#define QIXIS_BASE_PHYS QIXIS_BASE +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_LBMAP_SWITCH 6 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x44 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* + * QIXIS Timing parameters for IFC GPCM + */ +#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ + FTIM0_GPCM_TEADC(0xe) | \ + FTIM0_GPCM_TEAHC(0xe)) +#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ + FTIM2_GPCM_TCH(0xe) | \ + FTIM2_GPCM_TWP(0xf0)) +#define CONFIG_SYS_FPGA_FTIM3 0x0 +#endif + +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + +#define CONFIG_BAUDRATE 115200 + +/* + * I2C + */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC + +/* + * I2C bus multiplexer + */ +#define I2C_MUX_PCA_ADDR_PRI 0x77 +#define I2C_MUX_CH_DEFAULT 0x8 + +/* + * MMC + */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC + +/* + * eTSEC + */ +#define CONFIG_TSEC_ENET + +#ifdef CONFIG_TSEC_ENET +#define CONFIG_MII +#define CONFIG_MII_DEFAULT_TSEC 3 +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 1 +#define TSEC2_PHY_ADDR 2 +#define TSEC3_PHY_ADDR 3 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_REALTEK + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 + +#define CONFIG_FSL_SGMII_RISER 1 +#define SGMII_RISER_PHY_OFFSET 0x1b + +#ifdef CONFIG_FSL_SGMII_RISER +#define CONFIG_SYS_TBIPA_VALUE 8 +#endif + +#endif +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +#define CONFIG_CMDLINE_TAG +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CMD_IMLS + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ + "fdt_high=0xcfffffff\0" \ + "initrd_high=0xcfffffff\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_ENV_EXISTS +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (30 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_CMD_BOOTZ + +#endif -- cgit v1.3.1 From c8a7d9dab01c00c9efb5431284e9f16f8f2e92bb Mon Sep 17 00:00:00 2001 From: Wang Huan Date: Fri, 5 Sep 2014 13:52:45 +0800 Subject: arm: ls102xa: Add basic support for LS1021ATWR board LS102xA is an ARMv7 implementation. This patch is to add basic support for LS1021ATWR board. One DDR controller DUART1 is used as the console For the detail board information, please refer to README. Signed-off-by: Chen Lu Signed-off-by: Yuan Yao Signed-off-by: Alison Wang --- arch/arm/Kconfig | 4 + board/freescale/ls1021atwr/Kconfig | 23 ++ board/freescale/ls1021atwr/MAINTAINERS | 6 + board/freescale/ls1021atwr/Makefile | 7 + board/freescale/ls1021atwr/README | 109 ++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 482 ++++++++++++++++++++++++++++++++ configs/ls1021atwr_nor_defconfig | 2 + include/configs/ls1021atwr.h | 273 ++++++++++++++++++ 8 files changed, 906 insertions(+) create mode 100644 board/freescale/ls1021atwr/Kconfig create mode 100644 board/freescale/ls1021atwr/MAINTAINERS create mode 100644 board/freescale/ls1021atwr/Makefile create mode 100644 board/freescale/ls1021atwr/README create mode 100644 board/freescale/ls1021atwr/ls1021atwr.c create mode 100644 configs/ls1021atwr_nor_defconfig create mode 100644 include/configs/ls1021atwr.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d7ed3e207d2..11143a8c380 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -473,6 +473,9 @@ config TARGET_LS2085A_SIMU config TARGET_LS1021AQDS bool "Support ls1021aqds_nor" +config TARGET_LS1021ATWR + bool "Support ls1021atwr_nor" + config TARGET_BALLOON3 bool "Support balloon3" @@ -598,6 +601,7 @@ source "board/eukrea/cpuat91/Kconfig" source "board/faraday/a320evb/Kconfig" source "board/freescale/ls2085a/Kconfig" source "board/freescale/ls1021aqds/Kconfig" +source "board/freescale/ls1021atwr/Kconfig" source "board/freescale/mx23evk/Kconfig" source "board/freescale/mx25pdk/Kconfig" source "board/freescale/mx28evk/Kconfig" diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig new file mode 100644 index 00000000000..057808df998 --- /dev/null +++ b/board/freescale/ls1021atwr/Kconfig @@ -0,0 +1,23 @@ +if TARGET_LS1021ATWR + +config SYS_CPU + string + default "armv7" + +config SYS_BOARD + string + default "ls1021atwr" + +config SYS_VENDOR + string + default "freescale" + +config SYS_SOC + string + default "ls102xa" + +config SYS_CONFIG_NAME + string + default "ls1021atwr" + +endif diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS new file mode 100644 index 00000000000..4e5bc15a0d6 --- /dev/null +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -0,0 +1,6 @@ +LS1021ATWR BOARD +M: Alison Wang +S: Maintained +F: board/freescale/ls1021atwr/ +F: include/configs/ls1021atwr.h +F: configs/ls1021atwr_nor_defconfig diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile new file mode 100644 index 00000000000..b5df668713f --- /dev/null +++ b/board/freescale/ls1021atwr/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021atwr.o diff --git a/board/freescale/ls1021atwr/README b/board/freescale/ls1021atwr/README new file mode 100644 index 00000000000..d2821cbb6ba --- /dev/null +++ b/board/freescale/ls1021atwr/README @@ -0,0 +1,109 @@ +Overview +-------- +The LS1021ATWR is a Freescale reference board that hosts the LS1021A SoC. + +LS1021A SoC Overview +------------------ +The QorIQ LS1 family, which includes the LS1021A communications processor, +is built on Layerscape architecture, the industry's first software-aware, +core-agnostic networking architecture to offer unprecedented efficiency +and scale. + +A member of the value-performance tier, the QorIQ LS1021A processor provides +extensive integration and power efficiency for fanless, small form factor +enterprise networking applications. Incorporating dual ARM Cortex-A7 cores +running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark +performance of over 6,000, as well as virtualization support, advanced +security features and the broadest array of high-speed interconnects and +optimized peripheral features ever offered in a sub-3 W processor. + +The QorIQ LS1021A processor features an integrated LCD controller, +CAN controller for implementing industrial protocols, DDR3L/4 running +up to 1600 MHz, integrated security engine and QUICC Engine, and ECC +protection on both L1 and L2 caches. The LS1021A processor is pin- and +software-compatible with the QorIQ LS1020A and LS1022A processors. + +The LS1021A SoC includes the following function and features: + + - ARM Cortex-A7 MPCore compliant with ARMv7-A architecture + - Dual high-preformance ARM Cortex-A7 cores, each core includes: + - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection) + - 512 Kbyte shared coherent L2 Cache (with ECC protection) + - NEON Co-processor (per core) + - 40-bit physical addressing + - Vector floating-point support + - ARM Core-Link CCI-400 Cache Coherent Interconnect + - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration + supporting speeds up to 1600Mtps + - ECC and interleaving support + - VeTSEC Ethernet complex + - Up to 3x virtualized 10/100/1000 Ethernet controllers + - MII, RMII, RGMII, and SGMII support + - QoS, lossless flow control, and IEEE 1588 support + - 4-lane 6GHz SerDes + - High speed interconnect (4 SerDes lanes with are muxed for these protocol) + - Two PCI Express Gen2 controllers running at up to 5 GHz + - One Serial ATA 3.0 supporting 6 GT/s operation + - Two SGMII interfaces supporting 1000 Mbps + - Additional peripheral interfaces + - One high-speed USB 3.0 controller with integrated PHY and one high-speed + USB 2.00 controller with ULPI + - Integrated flash controller (IFC) with 16-bit interface + - Quad SPI NOR Flash + - One enhanced Secure digital host controller + - Display controller unit (DCU) 24-bit RGB (12-bit DDR pin interface) + - Ten UARTs comprised of two 16550 compliant DUARTs, and six low power + UARTs + - Three I2C controllers + - Eight FlexTimers four supporting PWM and four FlexCAN ports + - Four GPIO controllers supporting up to 109 general purpose I/O signals + - Integrated advanced audio block: + - Four synchronous audio interfaces (SAI) + - Sony/Philips Digital Interconnect Format (SPDIF) + - Asynchronous Sample Rate Converter (ASRC) + - Hardware based crypto offload engine + - IPSec forwarding at up to 1Gbps + - QorIQ Trust Architecture, Secure Boot, and ARM TrustZone supported + - Public key hardware accelerator + - True Random Number Generator (NIST Certified) + - Advanced Encryption Standard Accelerators (AESA) + - Data Encryption Standard Accelerators + - QUICC Engine ULite block + - Two universal communication controllers (TDM and HDLC) supporting 64 + multichannels, each running at 64 Kbps + - Support for 256 channels of HDLC + - QorIQ TrustArchitecture with Secure Boot, as well as ARM TrustZone supported + +LS1021ATWR board Overview +------------------------- + - DDR Controller + - Supports rates of up to 1600 MHz data-rate + - Supports one DDR3LP SDRAM. + - IFC/Local Bus + - NOR: 128MB 16-bit NOR Flash + - Ethernet + - Three on-board RGMII 10/100/1G ethernet ports. + - CPLD + - Clocks + - System and DDR clock (SYSCLK, DDRCLK) + - SERDES clocks + - Power Supplies + - SDHC + - SDHC/SDXC connector + - Other IO + - One Serial port + - Three I2C ports + +Memory map +----------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB +0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c new file mode 100644 index 00000000000..92ad8cd9bd3 --- /dev/null +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -0,0 +1,482 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define VERSION_MASK 0x00FF +#define BANK_MASK 0x0001 +#define CONFIG_RESET 0x1 +#define INIT_RESET 0x1 + +#define CPLD_SET_MUX_SERDES 0x20 +#define CPLD_SET_BOOT_BANK 0x40 + +#define BOOT_FROM_UPPER_BANK 0x0 +#define BOOT_FROM_LOWER_BANK 0x1 + +#define LANEB_SATA (0x01) +#define LANEB_SGMII1 (0x02) +#define LANEC_SGMII1 (0x04) +#define LANEC_PCIEX1 (0x08) +#define LANED_PCIEX2 (0x10) +#define LANED_SGMII2 (0x20) + +#define MASK_LANE_B 0x1 +#define MASK_LANE_C 0x2 +#define MASK_LANE_D 0x4 +#define MASK_SGMII 0x8 + +#define KEEP_STATUS 0x0 +#define NEED_RESET 0x1 + +struct cpld_data { + u8 cpld_ver; /* cpld revision */ + u8 cpld_ver_sub; /* cpld sub revision */ + u8 pcba_ver; /* pcb revision number */ + u8 system_rst; /* reset system by cpld */ + u8 soft_mux_on; /* CPLD override physical switches Enable */ + u8 cfg_rcw_src1; /* Reset config word 1 */ + u8 cfg_rcw_src2; /* Reset config word 2 */ + u8 vbank; /* Flash bank selection Control */ + u8 gpio; /* GPIO for TWR-ELEV */ + u8 i2c3_ifc_mux; + u8 mux_spi2; + u8 can3_usb2_mux; /* CAN3 and USB2 Selection */ + u8 qe_lcd_mux; /* QE and LCD Selection */ + u8 serdes_mux; /* Multiplexed pins for SerDes Lanes */ + u8 global_rst; /* reset with init CPLD reg to default */ + u8 rev1; /* Reserved */ + u8 rev2; /* Reserved */ +}; + +static void convert_serdes_mux(int type, int need_reset); + +void cpld_show(void) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + printf("CPLD: V%x.%x\nPCBA: V%x.0\nVBank: %d\n", + in_8(&cpld_data->cpld_ver) & VERSION_MASK, + in_8(&cpld_data->cpld_ver_sub) & VERSION_MASK, + in_8(&cpld_data->pcba_ver) & VERSION_MASK, + in_8(&cpld_data->vbank) & BANK_MASK); + +#ifdef CONFIG_DEBUG + printf("soft_mux_on =%x\n", + in_8(&cpld_data->soft_mux_on)); + printf("cfg_rcw_src1 =%x\n", + in_8(&cpld_data->cfg_rcw_src1)); + printf("cfg_rcw_src2 =%x\n", + in_8(&cpld_data->cfg_rcw_src2)); + printf("vbank =%x\n", + in_8(&cpld_data->vbank)); + printf("gpio =%x\n", + in_8(&cpld_data->gpio)); + printf("i2c3_ifc_mux =%x\n", + in_8(&cpld_data->i2c3_ifc_mux)); + printf("mux_spi2 =%x\n", + in_8(&cpld_data->mux_spi2)); + printf("can3_usb2_mux =%x\n", + in_8(&cpld_data->can3_usb2_mux)); + printf("qe_lcd_mux =%x\n", + in_8(&cpld_data->qe_lcd_mux)); + printf("serdes_mux =%x\n", + in_8(&cpld_data->serdes_mux)); +#endif +} + +int checkboard(void) +{ + puts("Board: LS1021ATWR\n"); + cpld_show(); + + return 0; +} + +void ddrmc_init(void) +{ + struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); + + out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); + + out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); + out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); + out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); + out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); + out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); + out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); + + out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); + + out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); + out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); + + out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); + + out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); + + out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); + out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); + + out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); + out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); + + out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); + out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); + + out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); + udelay(1); + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | DDR_SDRAM_CFG_MEM_EN); +} + +int dram_init(void) +{ +#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) + ddrmc_init(); +#endif + + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {CONFIG_SYS_FSL_ESDHC_ADDR}, +}; + +int board_mmc_init(bd_t *bis) +{ + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} +#endif + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + if (is_serdes_configured(SGMII_TSEC1)) { + puts("eTSEC1 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (is_serdes_configured(SGMII_TSEC2)) { + puts("eTSEC2 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif +#ifdef CONFIG_TSEC3 + SET_STD_TSEC_INFO(tsec_info[num], 3); + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +int config_serdes_mux(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; + + protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT; + switch (protocol) { + case 0x10: + convert_serdes_mux(LANEB_SATA, KEEP_STATUS); + convert_serdes_mux(LANED_PCIEX2 | + LANEC_PCIEX1, KEEP_STATUS); + break; + case 0x20: + convert_serdes_mux(LANEB_SGMII1, KEEP_STATUS); + convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); + convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); + break; + case 0x30: + convert_serdes_mux(LANEB_SATA, KEEP_STATUS); + convert_serdes_mux(LANEC_SGMII1, KEEP_STATUS); + convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); + break; + case 0x70: + convert_serdes_mux(LANEB_SATA, KEEP_STATUS); + convert_serdes_mux(LANEC_PCIEX1, KEEP_STATUS); + convert_serdes_mux(LANED_SGMII2, KEEP_STATUS); + break; + } + + return 0; +} + +int board_early_init_f(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + +#ifdef CONFIG_TSEC_ENET + out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV); + out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); + udelay(10); + out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV); +#endif + +#ifdef CONFIG_FSL_IFC + init_early_memctl_regs(); +#endif + + return 0; +} + +int board_init(void) +{ +#ifndef CONFIG_SYS_FSL_NO_SERDES + fsl_serdes_init(); + config_serdes_mux(); +#endif + + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} + +u8 flash_read8(void *addr) +{ + return __raw_readb(addr + 1); +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} + +static void convert_flash_bank(char bank) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + printf("Now switch to boot from flash bank %d.\n", bank); + cpld_data->soft_mux_on = CPLD_SET_BOOT_BANK; + cpld_data->vbank = bank; + + printf("Reset board to enable configuration.\n"); + cpld_data->system_rst = CONFIG_RESET; +} + +static int flash_bank_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "0") == 0) + convert_flash_bank(BOOT_FROM_UPPER_BANK); + else if (strcmp(argv[1], "1") == 0) + convert_flash_bank(BOOT_FROM_LOWER_BANK); + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + boot_bank, 2, 0, flash_bank_cmd, + "Flash bank Selection Control", + "bank[0-upper bank/1-lower bank] (e.g. boot_bank 0)" +); + +static int cpld_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + if (argc > 2) + return CMD_RET_USAGE; + if ((argc == 1) || (strcmp(argv[1], "conf") == 0)) + cpld_data->system_rst = CONFIG_RESET; + else if (strcmp(argv[1], "init") == 0) + cpld_data->global_rst = INIT_RESET; + else + return CMD_RET_USAGE; + + return 0; +} + +U_BOOT_CMD( + cpld_reset, 2, 0, cpld_reset_cmd, + "Reset via CPLD", + "conf\n" + " -reset with current CPLD configuration\n" + "init\n" + " -reset and initial CPLD configuration with default value" + +); + +static void convert_serdes_mux(int type, int need_reset) +{ + char current_serdes; + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + current_serdes = cpld_data->serdes_mux; + + switch (type) { + case LANEB_SATA: + current_serdes &= ~MASK_LANE_B; + break; + case LANEB_SGMII1: + current_serdes |= (MASK_LANE_B | MASK_SGMII | MASK_LANE_C); + break; + case LANEC_SGMII1: + current_serdes &= ~(MASK_LANE_B | MASK_SGMII | MASK_LANE_C); + break; + case LANED_SGMII2: + current_serdes |= MASK_LANE_D; + break; + case LANEC_PCIEX1: + current_serdes |= MASK_LANE_C; + break; + case (LANED_PCIEX2 | LANEC_PCIEX1): + current_serdes |= MASK_LANE_C; + current_serdes &= ~MASK_LANE_D; + break; + default: + printf("CPLD serdes MUX: unsupported MUX type 0x%x\n", type); + return; + } + + cpld_data->soft_mux_on |= CPLD_SET_MUX_SERDES; + cpld_data->serdes_mux = current_serdes; + + if (need_reset == 1) { + printf("Reset board to enable configuration\n"); + cpld_data->system_rst = CONFIG_RESET; + } +} + +void print_serdes_mux(void) +{ + char current_serdes; + struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); + + current_serdes = cpld_data->serdes_mux; + + printf("Serdes Lane B: "); + if ((current_serdes & MASK_LANE_B) == 0) + printf("SATA,\n"); + else + printf("SGMII 1,\n"); + + printf("Serdes Lane C: "); + if ((current_serdes & MASK_LANE_C) == 0) + printf("SGMII 1,\n"); + else + printf("PCIe,\n"); + + printf("Serdes Lane D: "); + if ((current_serdes & MASK_LANE_D) == 0) + printf("PCIe,\n"); + else + printf("SGMII 2,\n"); + + printf("SGMII 1 is on lane "); + if ((current_serdes & MASK_SGMII) == 0) + printf("C.\n"); + else + printf("B.\n"); +} + +static int serdes_mux_cmd(cmd_tbl_t *cmdtp, int flag, int argc, + char * const argv[]) +{ + if (argc != 2) + return CMD_RET_USAGE; + if (strcmp(argv[1], "sata") == 0) { + printf("Set serdes lane B to SATA.\n"); + convert_serdes_mux(LANEB_SATA, NEED_RESET); + } else if (strcmp(argv[1], "sgmii1b") == 0) { + printf("Set serdes lane B to SGMII 1.\n"); + convert_serdes_mux(LANEB_SGMII1, NEED_RESET); + } else if (strcmp(argv[1], "sgmii1c") == 0) { + printf("Set serdes lane C to SGMII 1.\n"); + convert_serdes_mux(LANEC_SGMII1, NEED_RESET); + } else if (strcmp(argv[1], "sgmii2") == 0) { + printf("Set serdes lane D to SGMII 2.\n"); + convert_serdes_mux(LANED_SGMII2, NEED_RESET); + } else if (strcmp(argv[1], "pciex1") == 0) { + printf("Set serdes lane C to PCIe X1.\n"); + convert_serdes_mux(LANEC_PCIEX1, NEED_RESET); + } else if (strcmp(argv[1], "pciex2") == 0) { + printf("Set serdes lane C & lane D to PCIe X2.\n"); + convert_serdes_mux((LANED_PCIEX2 | LANEC_PCIEX1), NEED_RESET); + } else if (strcmp(argv[1], "show") == 0) { + print_serdes_mux(); + } else { + return CMD_RET_USAGE; + } + + return 0; +} + +U_BOOT_CMD( + lane_bank, 2, 0, serdes_mux_cmd, + "Multiplexed function setting for SerDes Lanes", + "sata\n" + " -change lane B to sata\n" + "lane_bank sgmii1b\n" + " -change lane B to SGMII1\n" + "lane_bank sgmii1c\n" + " -change lane C to SGMII1\n" + "lane_bank sgmii2\n" + " -change lane D to SGMII2\n" + "lane_bank pciex1\n" + " -change lane C to PCIeX1\n" + "lane_bank pciex2\n" + " -change lane C & lane D to PCIeX2\n" + "\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n" +); diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig new file mode 100644 index 00000000000..5f465d31003 --- /dev/null +++ b/configs/ls1021atwr_nor_defconfig @@ -0,0 +1,2 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1021ATWR=y diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h new file mode 100644 index 00000000000..cb6b4004250 --- /dev/null +++ b/include/configs/ls1021atwr.h @@ -0,0 +1,273 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_LS102XA + +#define CONFIG_SYS_GENERIC_BOARD + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +/* + * Generic Timer Definitions + */ +#define GENERIC_TIMER_CLK 12500000 + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x67f80000 +#endif + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_SYS_HAS_SERDES + +/* + * IFC Definitions + */ +#define CONFIG_FSL_IFC +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) + +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_TRHZ_80) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TAVDS(0x0) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) | \ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWP(0x1c) | \ + FTIM2_NOR_TWPH(0x0e)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS + +/* CPLD */ + +#define CONFIG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE + +#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) +#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* CPLD Timing parameters for IFC GPCM */ +#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ + FTIM0_GPCM_TEADC(0xf) | \ + FTIM0_GPCM_TEAHC(0xf)) +#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0xff)) +#define CONFIG_SYS_FPGA_FTIM3 0x0 +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + +#define CONFIG_BAUDRATE 115200 + +/* + * I2C + */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC + +/* + * MMC + */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC + +/* + * eTSEC + */ +#define CONFIG_TSEC_ENET + +#ifdef CONFIG_TSEC_ENET +#define CONFIG_MII +#define CONFIG_MII_DEFAULT_TSEC 1 +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" + +#define TSEC1_PHY_ADDR 2 +#define TSEC2_PHY_ADDR 0 +#define TSEC3_PHY_ADDR 1 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#endif + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + +#define CONFIG_CMDLINE_TAG +#define CONFIG_CMDLINE_EDITING +#define CONFIG_CMD_IMLS + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 128 + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ + "initrd_high=0xcfffffff\0" \ + "fdt_high=0xcfffffff\0" + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_CMD_ENV_EXISTS +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_MEMINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x9fffffff + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (30 * 1024) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +/* + * Environment + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_CMD_BOOTZ + +#endif -- cgit v1.3.1 From 5ea060a9f96740969d1d1c392e446da823bb01d3 Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Fri, 5 Sep 2014 13:52:46 +0800 Subject: net: tsec: Remove tx snooping support from LS1 Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a workaround for LS1. It has been observed that currently the Tx stops functioning after a fair amount of Tx traffic with these settings on. These bits are sticky and once set they cannot be reset from Linux, for instance. Signed-off-by: Claudiu Manoil --- include/tsec.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/tsec.h b/include/tsec.h index 1119d2cb60b..58cdc19df3a 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -129,7 +129,11 @@ #define MINFLR_INIT_SETTINGS 0x00000040 +#ifdef CONFIG_LS102XA +#define DMACTRL_INIT_SETTINGS 0x00000003 +#else #define DMACTRL_INIT_SETTINGS 0x000000c3 +#endif #define DMACTRL_GRS 0x00000010 #define DMACTRL_GTS 0x00000008 #define DMACTRL_LE 0x00008000 -- cgit v1.3.1 From 327def5060d03648801b8c92b3235b0c9426af47 Mon Sep 17 00:00:00 2001 From: Wang Huan Date: Fri, 5 Sep 2014 13:52:48 +0800 Subject: video: dcu: Add DCU driver support This patch is to add DCU driver support. DCU also named 2D-ACE(Two Dimensional Animation and Compositing Engine) is a system master that fetches graphics stored in internal or external memory and displays them on a TFT LCD panel. Signed-off-by: Alison Wang --- arch/arm/include/asm/arch-ls102xa/config.h | 4 + drivers/video/Makefile | 1 + drivers/video/fsl_dcu_fb.c | 365 +++++++++++++++++++++++++++++ include/fsl_dcu_fb.h | 16 ++ 4 files changed, 386 insertions(+) create mode 100644 drivers/video/fsl_dcu_fb.c create mode 100644 include/fsl_dcu_fb.h (limited to 'include') diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 08c21afd1ee..ed78c33e0a3 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -24,6 +24,7 @@ #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) +#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 @@ -60,6 +61,9 @@ #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE +#define CONFIG_SYS_FSL_DCU_BE + +#define DCU_LAYER_MAX_NUM 16 #define CONFIG_SYS_FSL_SRDS_1 diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 93a91c3fa61..0914ea173d8 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_EXYNOS_MIPI_DSIM) += exynos_mipi_dsi.o exynos_mipi_dsi_common.o \ exynos_mipi_dsi_lowlevel.o obj-$(CONFIG_EXYNOS_PWM_BL) += exynos_pwm_bl.o obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o +obj-$(CONFIG_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o obj-$(CONFIG_L5F31188) += l5f31188.o obj-$(CONFIG_MPC8XX_LCD) += mpc8xx_lcd.o obj-$(CONFIG_PXA_LCD) += pxa_lcd.o diff --git a/drivers/video/fsl_dcu_fb.c b/drivers/video/fsl_dcu_fb.c new file mode 100644 index 00000000000..d4cd3827766 --- /dev/null +++ b/drivers/video/fsl_dcu_fb.c @@ -0,0 +1,365 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "videomodes.h" + +/* Convert the X,Y resolution pair into a single number */ +#define RESOLUTION(x, y) (((u32)(x) << 16) | (y)) + +#ifdef CONFIG_SYS_FSL_DCU_LE +#define dcu_read32 in_le32 +#define dcu_write32 out_le32 +#elif defined(CONFIG_SYS_FSL_DCU_BE) +#define dcu_read32 in_be32 +#define dcu_write32 out_be32 +#endif + +#define DCU_MODE_BLEND_ITER(x) ((x) << 20) +#define DCU_MODE_RASTER_EN (1 << 14) +#define DCU_MODE_NORMAL 1 +#define DCU_MODE_COLORBAR 3 +#define DCU_BGND_R(x) ((x) << 16) +#define DCU_BGND_G(x) ((x) << 8) +#define DCU_BGND_B(x) (x) +#define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16) +#define DCU_DISP_SIZE_DELTA_X(x) (x) +#define DCU_HSYN_PARA_BP(x) ((x) << 22) +#define DCU_HSYN_PARA_PW(x) ((x) << 11) +#define DCU_HSYN_PARA_FP(x) (x) +#define DCU_VSYN_PARA_BP(x) ((x) << 22) +#define DCU_VSYN_PARA_PW(x) ((x) << 11) +#define DCU_VSYN_PARA_FP(x) (x) +#define DCU_SYN_POL_INV_PXCK_FALL (0 << 6) +#define DCU_SYN_POL_NEG_REMAIN (0 << 5) +#define DCU_SYN_POL_INV_VS_LOW (1 << 1) +#define DCU_SYN_POL_INV_HS_LOW (1) +#define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16) +#define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8) +#define DCU_THRESHOLD_OUT_BUF_LOW(x) (x) +#define DCU_UPDATE_MODE_MODE (1 << 31) +#define DCU_UPDATE_MODE_READREG (1 << 30) + +#define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16) +#define DCU_CTRLDESCLN_1_WIDTH(x) (x) +#define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16) +#define DCU_CTRLDESCLN_2_POSX(x) (x) +#define DCU_CTRLDESCLN_4_EN (1 << 31) +#define DCU_CTRLDESCLN_4_TILE_EN (1 << 30) +#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29) +#define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28) +#define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20) +#define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16) +#define DCU_CTRLDESCLN_4_RLE_EN (1 << 15) +#define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4) +#define DCU_CTRLDESCLN_4_BB_ON (1 << 2) +#define DCU_CTRLDESCLN_4_AB(x) (x) +#define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16) +#define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8) +#define DCU_CTRLDESCLN_5_CKMAX_B(x) (x) +#define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16) +#define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8) +#define DCU_CTRLDESCLN_6_CKMIN_B(x) (x) +#define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16) +#define DCU_CTRLDESCLN_7_TILE_HOR(x) (x) +#define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x) +#define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x) + +#define BPP_16_RGB565 4 +#define BPP_24_RGB888 5 +#define BPP_32_ARGB8888 6 + +/* + * This setting is used for the TWR_LCD_RGB card + */ +static struct fb_videomode fsl_dcu_mode_480_272 = { + .name = "480x272-60", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = 91996, + .left_margin = 2, + .right_margin = 2, + .upper_margin = 1, + .lower_margin = 1, + .hsync_len = 41, + .vsync_len = 2, + .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, + .vmode = FB_VMODE_NONINTERLACED +}; + +/* + * This setting is used for Siliconimage SiI9022A HDMI + */ +static struct fb_videomode fsl_dcu_mode_640_480 = { + .name = "640x480-60", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = 39722, + .left_margin = 48, + .right_margin = 16, + .upper_margin = 33, + .lower_margin = 10, + .hsync_len = 96, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, +}; + +/* + * DCU register map + */ +struct dcu_reg { + u32 desc_cursor[4]; + u32 mode; + u32 bgnd; + u32 disp_size; + u32 hsyn_para; + u32 vsyn_para; + u32 synpol; + u32 threshold; + u32 int_status; + u32 int_mask; + u32 colbar[8]; + u32 div_ratio; + u32 sign_calc[2]; + u32 crc_val; + u8 res_064[0x6c-0x64]; + u32 parr_err_status1; + u8 res_070[0x7c-0x70]; + u32 parr_err_status3; + u32 mparr_err_status1; + u8 res_084[0x90-0x84]; + u32 mparr_err_status3; + u32 threshold_inp_buf[2]; + u8 res_09c[0xa0-0x9c]; + u32 luma_comp; + u32 chroma_red; + u32 chroma_green; + u32 chroma_blue; + u32 crc_pos; + u32 lyr_intpol_en; + u32 lyr_luma_comp; + u32 lyr_chrm_red; + u32 lyr_chrm_grn; + u32 lyr_chrm_blue; + u8 res_0c4[0xcc-0xc8]; + u32 update_mode; + u32 underrun; + u8 res_0d4[0x100-0xd4]; + u32 gpr; + u32 slr_l[2]; + u32 slr_disp_size; + u32 slr_hvsync_para; + u32 slr_pol; + u32 slr_l_transp[2]; + u8 res_120[0x200-0x120]; + u32 ctrldescl[DCU_LAYER_MAX_NUM][16]; +}; + +static struct fb_info info; + +static void reset_total_layers(void) +{ + struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; + int i; + + for (i = 0; i < DCU_LAYER_MAX_NUM; i++) { + dcu_write32(®s->ctrldescl[i][0], 0); + dcu_write32(®s->ctrldescl[i][1], 0); + dcu_write32(®s->ctrldescl[i][2], 0); + dcu_write32(®s->ctrldescl[i][3], 0); + dcu_write32(®s->ctrldescl[i][4], 0); + dcu_write32(®s->ctrldescl[i][5], 0); + dcu_write32(®s->ctrldescl[i][6], 0); + dcu_write32(®s->ctrldescl[i][7], 0); + dcu_write32(®s->ctrldescl[i][8], 0); + dcu_write32(®s->ctrldescl[i][9], 0); + dcu_write32(®s->ctrldescl[i][10], 0); + } + + dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); +} + +static int layer_ctrldesc_init(int index, u32 pixel_format) +{ + struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; + unsigned int bpp = BPP_24_RGB888; + + dcu_write32(®s->ctrldescl[index][0], + DCU_CTRLDESCLN_1_HEIGHT(info.var.yres) | + DCU_CTRLDESCLN_1_WIDTH(info.var.xres)); + + dcu_write32(®s->ctrldescl[index][1], + DCU_CTRLDESCLN_2_POSY(0) | + DCU_CTRLDESCLN_2_POSX(0)); + + dcu_write32(®s->ctrldescl[index][2], (unsigned int)info.screen_base); + + switch (pixel_format) { + case 16: + bpp = BPP_16_RGB565; + break; + case 24: + bpp = BPP_24_RGB888; + break; + case 32: + bpp = BPP_32_ARGB8888; + break; + default: + printf("unsupported color depth: %u\n", pixel_format); + } + + dcu_write32(®s->ctrldescl[index][3], + DCU_CTRLDESCLN_4_EN | + DCU_CTRLDESCLN_4_TRANS(0xff) | + DCU_CTRLDESCLN_4_BPP(bpp) | + DCU_CTRLDESCLN_4_AB(0)); + + dcu_write32(®s->ctrldescl[index][4], + DCU_CTRLDESCLN_5_CKMAX_R(0xff) | + DCU_CTRLDESCLN_5_CKMAX_G(0xff) | + DCU_CTRLDESCLN_5_CKMAX_B(0xff)); + dcu_write32(®s->ctrldescl[index][5], + DCU_CTRLDESCLN_6_CKMIN_R(0) | + DCU_CTRLDESCLN_6_CKMIN_G(0) | + DCU_CTRLDESCLN_6_CKMIN_B(0)); + + dcu_write32(®s->ctrldescl[index][6], + DCU_CTRLDESCLN_7_TILE_VER(0) | + DCU_CTRLDESCLN_7_TILE_HOR(0)); + + dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0)); + dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0)); + + dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); + + return 0; +} + +int fsl_dcu_init(unsigned int xres, unsigned int yres, + unsigned int pixel_format) +{ + struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; + unsigned int div, mode; + + /* Memory allocation for framebuffer */ + info.screen_size = + info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8); + info.screen_base = (char *)memalign(ARCH_DMA_MINALIGN, + roundup(info.screen_size, ARCH_DMA_MINALIGN)); + memset(info.screen_base, 0, info.screen_size); + + reset_total_layers(); + div = dcu_set_pixel_clock(info.var.pixclock); + dcu_write32(®s->div_ratio, (div - 1)); + + dcu_write32(®s->disp_size, + DCU_DISP_SIZE_DELTA_Y(info.var.yres) | + DCU_DISP_SIZE_DELTA_X(info.var.xres / 16)); + + dcu_write32(®s->hsyn_para, + DCU_HSYN_PARA_BP(info.var.left_margin) | + DCU_HSYN_PARA_PW(info.var.hsync_len) | + DCU_HSYN_PARA_FP(info.var.right_margin)); + + dcu_write32(®s->vsyn_para, + DCU_VSYN_PARA_BP(info.var.upper_margin) | + DCU_VSYN_PARA_PW(info.var.vsync_len) | + DCU_VSYN_PARA_FP(info.var.lower_margin)); + + dcu_write32(®s->synpol, + DCU_SYN_POL_INV_PXCK_FALL | + DCU_SYN_POL_NEG_REMAIN | + DCU_SYN_POL_INV_VS_LOW | + DCU_SYN_POL_INV_HS_LOW); + + dcu_write32(®s->bgnd, + DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0)); + + dcu_write32(®s->mode, + DCU_MODE_BLEND_ITER(DCU_LAYER_MAX_NUM) | + DCU_MODE_RASTER_EN); + + dcu_write32(®s->threshold, + DCU_THRESHOLD_LS_BF_VS(0x3) | + DCU_THRESHOLD_OUT_BUF_HIGH(0x78) | + DCU_THRESHOLD_OUT_BUF_LOW(0)); + + mode = dcu_read32(®s->mode); + dcu_write32(®s->mode, mode | DCU_MODE_NORMAL); + + layer_ctrldesc_init(0, pixel_format); + + return 0; +} + +void *video_hw_init(void) +{ + static GraphicDevice ctfb; + const char *options; + unsigned int depth = 0, freq = 0; + struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272; + + if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq, + &options)) + return NULL; + + /* Find the monitor port, which is a required option */ + if (!options) + return NULL; + if (strncmp(options, "monitor=", 8) != 0) + return NULL; + + switch (RESOLUTION(ctfb.winSizeX, ctfb.winSizeY)) { + case RESOLUTION(480, 272): + fsl_dcu_mode_db = &fsl_dcu_mode_480_272; + break; + case RESOLUTION(640, 480): + fsl_dcu_mode_db = &fsl_dcu_mode_640_480; + break; + default: + printf("unsupported resolution %ux%u\n", + ctfb.winSizeX, ctfb.winSizeY); + } + + info.var.xres = fsl_dcu_mode_db->xres; + info.var.yres = fsl_dcu_mode_db->yres; + info.var.bits_per_pixel = 32; + info.var.pixclock = fsl_dcu_mode_db->pixclock; + info.var.left_margin = fsl_dcu_mode_db->left_margin; + info.var.right_margin = fsl_dcu_mode_db->right_margin; + info.var.upper_margin = fsl_dcu_mode_db->upper_margin; + info.var.lower_margin = fsl_dcu_mode_db->lower_margin; + info.var.hsync_len = fsl_dcu_mode_db->hsync_len; + info.var.vsync_len = fsl_dcu_mode_db->vsync_len; + info.var.sync = fsl_dcu_mode_db->sync; + info.var.vmode = fsl_dcu_mode_db->vmode; + info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8; + + if (platform_dcu_init(ctfb.winSizeX, ctfb.winSizeY, + options + 8, fsl_dcu_mode_db) < 0) + return NULL; + + ctfb.frameAdrs = (unsigned int)info.screen_base; + ctfb.plnSizeX = ctfb.winSizeX; + ctfb.plnSizeY = ctfb.winSizeY; + + ctfb.gdfBytesPP = 4; + ctfb.gdfIndex = GDF_32BIT_X888RGB; + + ctfb.memSize = info.screen_size; + + return &ctfb; +} diff --git a/include/fsl_dcu_fb.h b/include/fsl_dcu_fb.h new file mode 100644 index 00000000000..42632984d35 --- /dev/null +++ b/include/fsl_dcu_fb.h @@ -0,0 +1,16 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include + +int fsl_dcu_init(unsigned int xres, unsigned int yres, + unsigned int pixel_format); + +/* Prototypes for external board-specific functions */ +int platform_dcu_init(unsigned int xres, unsigned int yres, + const char *port, struct fb_videomode *dcu_fb_videomode); +unsigned int dcu_set_pixel_clock(unsigned int pixclock); -- cgit v1.3.1 From b4ecc8c6f8c85d25f72933af23531728069a5b0f Mon Sep 17 00:00:00 2001 From: Wang Huan Date: Fri, 5 Sep 2014 13:52:50 +0800 Subject: ls102xa: dcu: Add platform support for DCU on LS1021ATWR board This patch adds the TWR_LCD_RGB card/HDMI options and the common configuration for DCU on LS1021ATWR board. Signed-off-by: Alison Wang --- board/freescale/ls1021atwr/Makefile | 1 + board/freescale/ls1021atwr/dcu.c | 47 +++++++++++++++++++++++++++++++++ board/freescale/ls1021atwr/ls1021atwr.c | 6 +++++ include/configs/ls1021atwr.h | 18 +++++++++++++ 4 files changed, 72 insertions(+) create mode 100644 board/freescale/ls1021atwr/dcu.c (limited to 'include') diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile index b5df668713f..01296c04b29 100644 --- a/board/freescale/ls1021atwr/Makefile +++ b/board/freescale/ls1021atwr/Makefile @@ -5,3 +5,4 @@ # obj-y += ls1021atwr.o +obj-$(CONFIG_FSL_DCU_FB) += dcu.o diff --git a/board/freescale/ls1021atwr/dcu.c b/board/freescale/ls1021atwr/dcu.c new file mode 100644 index 00000000000..8fe4ccbeb40 --- /dev/null +++ b/board/freescale/ls1021atwr/dcu.c @@ -0,0 +1,47 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include "div64.h" +#include "../common/dcu_sii9022a.h" + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int dcu_set_pixel_clock(unsigned int pixclock) +{ + unsigned long long div; + + div = (unsigned long long)(gd->bus_clk / 1000); + div *= (unsigned long long)pixclock; + do_div(div, 1000000000); + + return div; +} + +int platform_dcu_init(unsigned int xres, unsigned int yres, + const char *port, + struct fb_videomode *dcu_fb_videomode) +{ + const char *name; + unsigned int pixel_format; + + if (strncmp(port, "twr_lcd", 4) == 0) { + name = "TWR_LCD_RGB card"; + } else { + name = "HDMI"; + dcu_set_dvi_encoder(dcu_fb_videomode); + } + + printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); + + pixel_format = 32; + fsl_dcu_init(xres, yres, pixel_format); + + return 0; +} diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 92ad8cd9bd3..b522ff28e5e 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -261,6 +261,12 @@ int board_early_init_f(void) init_early_memctl_regs(); #endif +#ifdef CONFIG_FSL_DCU_FB + out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV); + out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN); + out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV); +#endif + return 0; } diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index cb6b4004250..45b2272ff5b 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -162,6 +162,24 @@ #define CONFIG_FSL_ESDHC #define CONFIG_GENERIC_MMC +/* + * Video + */ +#define CONFIG_FSL_DCU_FB + +#ifdef CONFIG_FSL_DCU_FB +#define CONFIG_VIDEO +#define CONFIG_CMD_BMP +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO + +#define CONFIG_FSL_DCU_SII9022A +#define CONFIG_SYS_I2C_DVI_BUS_NUM 1 +#define CONFIG_SYS_I2C_DVI_ADDR 0x39 +#endif + /* * eTSEC */ -- cgit v1.3.1 From 1a7ae2585410cdd6d88713bcd941463370aacd2e Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 8 Sep 2014 18:05:26 +0900 Subject: microblaze: remove #ident directive to fix build error The microblaze-generic board fails to build at least with the kernel.org crosstool: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/ x86_64-gcc-4.9.0-nolibc_microblaze-linux.tar.xz $ make CROSS_COMPILE=microblaze-linux- microblaze-generic_defconfig all [ snip ] CC disk/part.o CC disk/part_dos.o LD disk/built-in.o CC drivers/block/systemace.o {standard input}: Assembler messages: {standard input}:2495: Error: operation combines symbols in different segments {standard input}:2496: Error: operation combines symbols in different segments {standard input}:2499: Error: operation combines symbols in different segments {standard input}:2500: Error: operation combines symbols in different segments {standard input}:2505: Error: operation combines symbols in different segments {standard input}:2506: Error: operation combines symbols in different segments {standard input}:2515: Error: operation combines symbols in different segments {standard input}:2516: Error: operation combines symbols in different segments {standard input}:2519: Error: operation combines symbols in different segments {standard input}:2520: Error: operation combines symbols in different segments {standard input}:2529: Error: operation combines symbols in different segments {standard input}:2530: Error: operation combines symbols in different segments {standard input}:2533: Error: operation combines symbols in different segments {standard input}:2534: Error: operation combines symbols in different segments {standard input}:2539: Error: operation combines symbols in different segments {standard input}:2540: Error: operation combines symbols in different segments {standard input}:2549: Error: operation combines symbols in different segments {standard input}:2550: Error: operation combines symbols in different segments make[3]: *** [drivers/block/systemace.o] Error 1 make[2]: *** [drivers/block] Error 2 make[1]: *** [drivers] Error 2 make: *** [__build_one_by_one] Error 2 It looks like the cause of this error message is the "#ident" directive. Signed-off-by: Masahiro Yamada Cc: Michal Simek Signed-off-by: Michal Simek --- include/systemace.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/systemace.h b/include/systemace.h index 73affc42bed..3f342d565c5 100644 --- a/include/systemace.h +++ b/include/systemace.h @@ -6,7 +6,6 @@ * * SPDX-License-Identifier: GPL-2.0+ */ -#ident "$Id:$" #ifdef CONFIG_SYSTEMACE -- cgit v1.3.1 From 9fb02491fe96991cbedc49c7ebe5cdd271d1b6a7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 3 Sep 2014 17:37:01 -0600 Subject: dm: Make driver model available before board_init() For some boards board_init() will change GPIOs, so we need to have driver model available before then. Adjust the board init to arrange this, but enable it for driver model only, just to be safe. This does create additional #ifdef logic, but it is safer than trying to make a pervasive change which may cause some boards to break. Signed-off-by: Simon Glass --- common/board_r.c | 24 +++++++++++------------- common/stdio.c | 18 ++++++++++++++++-- include/stdio_dev.h | 24 +++++++++++++++++++++++- 3 files changed, 50 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/common/board_r.c b/common/board_r.c index 64beae5f348..6ac2b7e1601 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -715,6 +715,15 @@ init_fnc_t init_sequence_r[] = { /* TODO: could x86/PPC have this also perhaps? */ #ifdef CONFIG_ARM initr_caches, +#endif + initr_reloc_global_data, + initr_barrier, + initr_malloc, + bootstage_relocate, +#ifdef CONFIG_DM + initr_dm, +#endif +#ifdef CONFIG_ARM board_init, /* Setup chipselects */ #endif /* @@ -726,16 +735,7 @@ init_fnc_t init_sequence_r[] = { #ifdef CONFIG_CLOCKS set_cpu_clk_info, /* Setup clock information */ #endif - initr_reloc_global_data, - initr_barrier, - initr_malloc, - bootstage_relocate, -#ifdef CONFIG_DM_SERIAL - stdio_init, -#endif -#ifdef CONFIG_DM - initr_dm, -#endif + stdio_init_tables, initr_serial, initr_announce, INIT_FUNC_WATCHDOG_RESET @@ -821,9 +821,7 @@ init_fnc_t init_sequence_r[] = { */ initr_pci, #endif -#ifndef CONFIG_DM_SERIAL - stdio_init, -#endif + stdio_add_devices, initr_jumptable, #ifdef CONFIG_API initr_api, diff --git a/common/stdio.c b/common/stdio.c index 692ca7f1cdf..c878103a482 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -215,7 +215,7 @@ int stdio_deregister(const char *devname) } #endif /* CONFIG_SYS_STDIO_DEREGISTER */ -int stdio_init (void) +int stdio_init_tables(void) { #if defined(CONFIG_NEEDS_MANUAL_RELOC) /* already relocated for current ARM implementation */ @@ -232,6 +232,11 @@ int stdio_init (void) /* Initialize the list */ INIT_LIST_HEAD(&(devs.list)); + return 0; +} + +int stdio_add_devices(void) +{ #ifdef CONFIG_SYS_I2C i2c_init_all(); #else @@ -265,5 +270,14 @@ int stdio_init (void) #ifdef CONFIG_CBMEM_CONSOLE cbmemc_init(); #endif - return (0); + + return 0; +} + +int stdio_init(void) +{ + stdio_init_tables(); + stdio_add_devices(); + + return 0; } diff --git a/include/stdio_dev.h b/include/stdio_dev.h index a7d0825c7e5..268de8ea700 100644 --- a/include/stdio_dev.h +++ b/include/stdio_dev.h @@ -78,7 +78,29 @@ extern char *stdio_names[MAX_FILES]; */ int stdio_register (struct stdio_dev * dev); int stdio_register_dev(struct stdio_dev *dev, struct stdio_dev **devp); -int stdio_init (void); + +/** + * stdio_init_tables() - set up stdio tables ready for devices + * + * This does not add any devices, but just prepares stdio for use. + */ +int stdio_init_tables(void); + +/** + * stdio_add_devices() - Add stdio devices to the table + * + * This makes calls to all the various subsystems that use stdio, to make + * them register with stdio. + */ +int stdio_add_devices(void); + +/** + * stdio_init() - Sets up stdio ready for use + * + * This calls stdio_init_tables() and stdio_add_devices() + */ +int stdio_init(void); + void stdio_print_current_devices(void); #ifdef CONFIG_SYS_STDIO_DEREGISTER int stdio_deregister(const char *devname); -- cgit v1.3.1 From a47411110ce982a9c66ef039622f2e32cf9fab5f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 3 Sep 2014 17:37:02 -0600 Subject: dm: tegra: Set up a pre-reloc malloc() Allocate 1KB so that driver model can operate before relocation. Signed-off-by: Simon Glass --- include/configs/tegra-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index d27fcebd7c4..7852f9ad847 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -40,6 +40,7 @@ * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) /* * NS16550 Configuration -- cgit v1.3.1 From 2fccd2d96badcdf6165658a99771a4c475586279 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 3 Sep 2014 17:37:03 -0600 Subject: tegra: Convert tegra GPIO driver to use driver model This is an implementation of GPIOs for Tegra that uses driver model. It has been tested on trimslice and also using the new iotrace feature. The implementation uses a top-level GPIO device (which has no actual GPIOS). Under this all the banks are created as separate GPIO devices. The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7, ..., Z0..Z7, AA0..AA7, etc. Since driver model is not yet available before relocation, or in SPL, a special function is provided for seaboard's SPL code. Signed-off-by: Simon Glass --- arch/arm/include/asm/arch-tegra/gpio.h | 15 +- board/nvidia/seaboard/seaboard.c | 2 +- drivers/gpio/tegra_gpio.c | 327 +++++++++++++++++++++++++++------ include/configs/tegra-common.h | 1 + 4 files changed, 283 insertions(+), 62 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-tegra/gpio.h b/arch/arm/include/asm/arch-tegra/gpio.h index 44cd455699e..7334e0ccd50 100644 --- a/arch/arm/include/asm/arch-tegra/gpio.h +++ b/arch/arm/include/asm/arch-tegra/gpio.h @@ -6,6 +6,8 @@ #ifndef _TEGRA_GPIO_H_ #define _TEGRA_GPIO_H_ +#define TEGRA_GPIOS_PER_PORT 8 +#define TEGRA_PORTS_PER_BANK 4 #define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8) #define GPIO_NAME_SIZE 20 /* gpio_request max label len */ @@ -25,9 +27,14 @@ struct tegra_gpio_config { u32 init:2; }; -/* - * Tegra-specific GPIO API +/** + * tegra_spl_gpio_direction_output() - set the output value of a GPIO + * + * This function is only used from SPL on seaboard, which needs to enable a + * GPIO to get the UART running. It could be done in U-Boot rather than SPL, + * but for now, this gets it working */ +int tegra_spl_gpio_direction_output(int gpio, int value); /** * Configure a list of GPIOs @@ -37,8 +44,4 @@ struct tegra_gpio_config { */ void gpio_config_table(const struct tegra_gpio_config *config, int len); -void gpio_info(void); - -#define gpio_status() gpio_info() - #endif /* TEGRA_GPIO_H_ */ diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index ce2db40f9eb..6a243f0aea9 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -22,7 +22,7 @@ void gpio_early_init_uart(void) #ifndef CONFIG_SPL_BUILD gpio_request(GPIO_PI3, NULL); #endif - gpio_direction_output(GPIO_PI3, 0); + tegra_spl_gpio_direction_output(GPIO_PI3, 0); } #endif diff --git a/drivers/gpio/tegra_gpio.c b/drivers/gpio/tegra_gpio.c index fea9d17f8e6..1cc4abb8a93 100644 --- a/drivers/gpio/tegra_gpio.c +++ b/drivers/gpio/tegra_gpio.c @@ -12,10 +12,17 @@ */ #include +#include +#include +#include +#include #include #include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; enum { TEGRA_CMD_INFO, @@ -24,14 +31,18 @@ enum { TEGRA_CMD_INPUT, }; -static struct gpio_names { - char name[GPIO_NAME_SIZE]; -} gpio_names[MAX_NUM_GPIOS]; +struct tegra_gpio_platdata { + struct gpio_ctlr_bank *bank; + const char *port_name; /* Name of port, e.g. "B" */ + int base_gpio; /* Port number for this port (0, 1,.., n-1) */ +}; -static char *get_name(int i) -{ - return *gpio_names[i].name ? gpio_names[i].name : "UNKNOWN"; -} +/* Information about each port at run-time */ +struct tegra_port_info { + char label[TEGRA_GPIOS_PER_PORT][GPIO_NAME_SIZE]; + struct gpio_ctlr_bank *bank; + int base_gpio; /* Port number for this port (0, 1,.., n-1) */ +}; /* Return config of pin 'gpio' as GPIO (1) or SFPIO (0) */ static int get_config(unsigned gpio) @@ -121,38 +132,72 @@ static void set_level(unsigned gpio, int high) writel(u, &bank->gpio_out[GPIO_PORT(gpio)]); } +static int check_reserved(struct udevice *dev, unsigned offset, + const char *func) +{ + struct tegra_port_info *state = dev_get_priv(dev); + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + + if (!*state->label[offset]) { + printf("tegra_gpio: %s: error: gpio %s%d not reserved\n", + func, uc_priv->bank_name, offset); + return -EBUSY; + } + + return 0; +} + +/* set GPIO pin 'gpio' as an output, with polarity 'value' */ +int tegra_spl_gpio_direction_output(int gpio, int value) +{ + /* Configure as a GPIO */ + set_config(gpio, 1); + + /* Configure GPIO output value. */ + set_level(gpio, value); + + /* Configure GPIO direction as output. */ + set_direction(gpio, 1); + + return 0; +} + /* * Generic_GPIO primitives. */ -int gpio_request(unsigned gpio, const char *label) +static int tegra_gpio_request(struct udevice *dev, unsigned offset, + const char *label) { - if (gpio >= MAX_NUM_GPIOS) - return -1; + struct tegra_port_info *state = dev_get_priv(dev); - if (label != NULL) { - strncpy(gpio_names[gpio].name, label, GPIO_NAME_SIZE); - gpio_names[gpio].name[GPIO_NAME_SIZE - 1] = '\0'; - } + if (*state->label[offset]) + return -EBUSY; + + strncpy(state->label[offset], label, GPIO_NAME_SIZE); + state->label[offset][GPIO_NAME_SIZE - 1] = '\0'; /* Configure as a GPIO */ - set_config(gpio, 1); + set_config(state->base_gpio + offset, 1); return 0; } -int gpio_free(unsigned gpio) +static int tegra_gpio_free(struct udevice *dev, unsigned offset) { - if (gpio >= MAX_NUM_GPIOS) - return -1; + struct tegra_port_info *state = dev_get_priv(dev); + int ret; + + ret = check_reserved(dev, offset, __func__); + if (ret) + return ret; + state->label[offset][0] = '\0'; - gpio_names[gpio].name[0] = '\0'; - /* Do not configure as input or change pin mux here */ return 0; } /* read GPIO OUT value of pin 'gpio' */ -static int gpio_get_output_value(unsigned gpio) +static int tegra_gpio_get_output_value(unsigned gpio) { struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; @@ -166,24 +211,34 @@ static int gpio_get_output_value(unsigned gpio) return (val >> GPIO_BIT(gpio)) & 1; } + /* set GPIO pin 'gpio' as an input */ -int gpio_direction_input(unsigned gpio) +static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset) { - debug("gpio_direction_input: pin = %d (port %d:bit %d)\n", - gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); + struct tegra_port_info *state = dev_get_priv(dev); + int ret; + + ret = check_reserved(dev, offset, __func__); + if (ret) + return ret; /* Configure GPIO direction as input. */ - set_direction(gpio, 0); + set_direction(state->base_gpio + offset, 0); return 0; } /* set GPIO pin 'gpio' as an output, with polarity 'value' */ -int gpio_direction_output(unsigned gpio, int value) +static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset, + int value) { - debug("gpio_direction_output: pin = %d (port %d:bit %d) = %s\n", - gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), - value ? "HIGH" : "LOW"); + struct tegra_port_info *state = dev_get_priv(dev); + int gpio = state->base_gpio + offset; + int ret; + + ret = check_reserved(dev, offset, __func__); + if (ret) + return ret; /* Configure GPIO output value. */ set_level(gpio, value); @@ -195,25 +250,38 @@ int gpio_direction_output(unsigned gpio, int value) } /* read GPIO IN value of pin 'gpio' */ -int gpio_get_value(unsigned gpio) +static int tegra_gpio_get_value(struct udevice *dev, unsigned offset) { - struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE; - struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)]; + struct tegra_port_info *state = dev_get_priv(dev); + int gpio = state->base_gpio + offset; + int ret; int val; - debug("gpio_get_value: pin = %d (port %d:bit %d)\n", - gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); + ret = check_reserved(dev, offset, __func__); + if (ret) + return ret; + + debug("%s: pin = %d (port %d:bit %d)\n", __func__, + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio)); - val = readl(&bank->gpio_in[GPIO_PORT(gpio)]); + val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]); return (val >> GPIO_BIT(gpio)) & 1; } /* write GPIO OUT value to pin 'gpio' */ -int gpio_set_value(unsigned gpio, int value) +static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value) { + struct tegra_port_info *state = dev_get_priv(dev); + int gpio = state->base_gpio + offset; + int ret; + + ret = check_reserved(dev, offset, __func__); + if (ret) + return ret; + debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n", - gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value); + gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value); /* Configure GPIO output value. */ set_level(gpio, value); @@ -241,26 +309,175 @@ void gpio_config_table(const struct tegra_gpio_config *config, int len) } } -/* - * Display Tegra GPIO information +static int tegra_gpio_get_function(struct udevice *dev, unsigned offset) +{ + struct tegra_port_info *state = dev_get_priv(dev); + int gpio = state->base_gpio + offset; + + if (!*state->label[offset]) + return GPIOF_UNUSED; + if (!get_config(gpio)) + return GPIOF_FUNC; + else if (get_direction(gpio)) + return GPIOF_OUTPUT; + else + return GPIOF_INPUT; +} + +static int tegra_gpio_get_state(struct udevice *dev, unsigned int offset, + char *buf, int bufsize) +{ + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + struct tegra_port_info *state = dev_get_priv(dev); + int gpio = state->base_gpio + offset; + const char *label; + int is_output; + int is_gpio; + int size; + + label = state->label[offset]; + is_gpio = get_config(gpio); /* GPIO, not SFPIO */ + size = snprintf(buf, bufsize, "%s%d: ", + uc_priv->bank_name ? uc_priv->bank_name : "", offset); + buf += size; + bufsize -= size; + if (is_gpio) { + is_output = get_direction(gpio); + + snprintf(buf, bufsize, "%s: %d [%c]%s%s", + is_output ? "out" : " in", + is_output ? + tegra_gpio_get_output_value(gpio) : + tegra_gpio_get_value(dev, offset), + *label ? 'x' : ' ', + *label ? " " : "", + label); + } else { + snprintf(buf, bufsize, "sfpio"); + } + + return 0; +} + +static const struct dm_gpio_ops gpio_tegra_ops = { + .request = tegra_gpio_request, + .free = tegra_gpio_free, + .direction_input = tegra_gpio_direction_input, + .direction_output = tegra_gpio_direction_output, + .get_value = tegra_gpio_get_value, + .set_value = tegra_gpio_set_value, + .get_function = tegra_gpio_get_function, + .get_state = tegra_gpio_get_state, +}; + +/** + * Returns the name of a GPIO port + * + * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ... + * + * @base_port: Base port number (0, 1..n-1) + * @return allocated string containing the name */ -void gpio_info(void) +static char *gpio_port_name(int base_port) { - unsigned c; - int type; + char *name, *s; + + name = malloc(3); + if (name) { + s = name; + *s++ = 'A' + (base_port % 26); + if (base_port >= 26) + *s++ = *name; + *s = '\0'; + } - for (c = 0; c < MAX_NUM_GPIOS; c++) { - type = get_config(c); /* GPIO, not SFPIO */ - if (type) { - printf("GPIO_%d:\t%s is an %s, ", c, - get_name(c), - get_direction(c) ? "OUTPUT" : "INPUT"); - if (get_direction(c)) - printf("value = %d", gpio_get_output_value(c)); - else - printf("value = %d", gpio_get_value(c)); - printf("\n"); - } else - continue; + return name; +} + +static const struct udevice_id tegra_gpio_ids[] = { + { .compatible = "nvidia,tegra30-gpio" }, + { .compatible = "nvidia,tegra20-gpio" }, + { } +}; + +static int gpio_tegra_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev->uclass_priv; + struct tegra_port_info *priv = dev->priv; + struct tegra_gpio_platdata *plat = dev->platdata; + + /* Only child devices have ports */ + if (!plat) + return 0; + + priv->bank = plat->bank; + priv->base_gpio = plat->base_gpio; + + uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT; + uc_priv->bank_name = plat->port_name; + + return 0; +} + +/** + * We have a top-level GPIO device with no actual GPIOs. It has a child + * device for each Tegra port. + */ +static int gpio_tegra_bind(struct udevice *parent) +{ + struct tegra_gpio_platdata *plat = parent->platdata; + struct gpio_ctlr *ctlr; + int bank_count; + int bank; + int ret; + int len; + + /* If this is a child device, there is nothing to do here */ + if (plat) + return 0; + + /* + * This driver does not make use of interrupts, other than to figure + * out the number of GPIO banks + */ + if (!fdt_getprop(gd->fdt_blob, parent->of_offset, "interrupts", &len)) + return -EINVAL; + bank_count = len / 3 / sizeof(u32); + ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob, + parent->of_offset, "reg"); + for (bank = 0; bank < bank_count; bank++) { + int port; + + for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) { + struct tegra_gpio_platdata *plat; + struct udevice *dev; + int base_port; + + plat = calloc(1, sizeof(*plat)); + if (!plat) + return -ENOMEM; + plat->bank = &ctlr->gpio_bank[bank]; + base_port = bank * TEGRA_PORTS_PER_BANK + port; + plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port; + plat->port_name = gpio_port_name(base_port); + + ret = device_bind(parent, parent->driver, + plat->port_name, plat, -1, &dev); + if (ret) + return ret; + dev->of_offset = parent->of_offset; + } } + + return 0; } + +U_BOOT_DRIVER(gpio_tegra) = { + .name = "gpio_tegra", + .id = UCLASS_GPIO, + .of_match = tegra_gpio_ids, + .bind = gpio_tegra_bind, + .probe = gpio_tegra_probe, + .priv_auto_alloc_size = sizeof(struct tegra_port_info), + .ops = &gpio_tegra_ops, +}; diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 7852f9ad847..f1187f165ee 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -20,6 +20,7 @@ #define CONFIG_DM #define CONFIG_CMD_DM +#define CONFIG_DM_GPIO #define CONFIG_SYS_TIMER_RATE 1000000 #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE -- cgit v1.3.1 From aac07d49d00b4bc8ca3f4aca0f3ad26385fb1d37 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 4 Sep 2014 16:27:24 -0600 Subject: dm: fdt: Add a function to look up a chosen node Within /chosen we may have a node which points to another node, similar to how /aliases works. Add a helper function to do this lookup. Signed-off-by: Simon Glass --- include/fdtdec.h | 12 ++++++++++++ lib/fdtdec.c | 15 +++++++++++++++ 2 files changed, 27 insertions(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 856e6cf766d..4f5aafb516d 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -374,6 +374,18 @@ int fdtdec_get_alias_seq(const void *blob, const char *base, int node, */ int fdtdec_get_alias_node(const void *blob, const char *name); +/** + * Get the offset of the given chosen node + * + * This looks up a property in /chosen containing the path to another node, + * then finds the offset of that node. + * + * @param blob Device tree blob (if NULL, then error is returned) + * @param name Property name, e.g. "stdout-path" + * @return Node offset referred to by that chosen node, or -ve FDT_ERR_... + */ +int fdtdec_get_chosen_node(const void *blob, const char *name); + /* * Get the name for a compatible ID * diff --git a/lib/fdtdec.c b/lib/fdtdec.c index eb5aa20526f..2b08be24050 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -380,6 +380,21 @@ int fdtdec_get_alias_node(const void *blob, const char *name) return fdt_path_offset(blob, prop); } +int fdtdec_get_chosen_node(const void *blob, const char *name) +{ + const char *prop; + int chosen_node; + int len; + + if (!blob) + return -FDT_ERR_NOTFOUND; + chosen_node = fdt_path_offset(blob, "/chosen"); + prop = fdt_getprop(blob, chosen_node, name, &len); + if (!prop) + return -FDT_ERR_NOTFOUND; + return fdt_path_offset(blob, prop); +} + int fdtdec_check_fdt(void) { /* -- cgit v1.3.1 From 1f359e3611c55d9cfae88dafce04db1833033bd0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 4 Sep 2014 16:27:25 -0600 Subject: dm: Adjust lists_bind_fdt() to return the bound device Allow the caller to find out the device that was bound in response to this call. Signed-off-by: Simon Glass --- drivers/core/lists.c | 10 +++++++--- drivers/core/root.c | 2 +- include/dm/lists.h | 6 +++++- 3 files changed, 13 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/drivers/core/lists.c b/drivers/core/lists.c index 0f08bfd6ff2..699f94b435f 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -118,7 +118,8 @@ static int driver_check_compatible(const void *blob, int offset, return -ENOENT; } -int lists_bind_fdt(struct udevice *parent, const void *blob, int offset) +int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, + struct udevice **devp) { struct driver *driver = ll_entry_start(struct driver, driver); const int n_ents = ll_entry_count(struct driver, driver); @@ -130,6 +131,8 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset) int ret = 0; dm_dbg("bind node %s\n", fdt_get_name(blob, offset, NULL)); + if (devp) + *devp = NULL; for (entry = driver; entry != driver + n_ents; entry++) { ret = driver_check_compatible(blob, offset, entry->of_match); name = fdt_get_name(blob, offset, NULL); @@ -149,10 +152,11 @@ int lists_bind_fdt(struct udevice *parent, const void *blob, int offset) ret = device_bind(parent, entry, name, NULL, offset, &dev); if (ret) { dm_warn("Error binding driver '%s'\n", entry->name); - if (!result || ret != -ENOENT) - result = ret; + return ret; } else { found = true; + if (devp) + *devp = dev; } break; } diff --git a/drivers/core/root.c b/drivers/core/root.c index 393dd98b9db..a328a4876f1 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -91,7 +91,7 @@ int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset, if (pre_reloc_only && !fdt_getprop(blob, offset, "u-boot,dm-pre-reloc", NULL)) continue; - err = lists_bind_fdt(parent, blob, offset); + err = lists_bind_fdt(parent, blob, offset, NULL); if (err && !ret) ret = err; } diff --git a/include/dm/lists.h b/include/dm/lists.h index 87a3af59c2e..23568952467 100644 --- a/include/dm/lists.h +++ b/include/dm/lists.h @@ -53,7 +53,11 @@ int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only); * @parent: parent driver (root) * @blob: device tree blob * @offset: offset of this device tree node + * @devp: if non-NULL, returns a pointer to the bound device + * @return 0 if device was bound, -EINVAL if the device tree is invalid, + * other -ve value on error */ -int lists_bind_fdt(struct udevice *parent, const void *blob, int offset); +int lists_bind_fdt(struct udevice *parent, const void *blob, int offset, + struct udevice **devp); #endif -- cgit v1.3.1 From 57d92753d4cada5c314a7d6bcfe7ad79b00c2eb8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 4 Sep 2014 16:27:26 -0600 Subject: dm: Add a uclass for serial devices Serial devices support simple byte input/output and a few operations to find out whether data is available. Add a basic uclass for serial devices to be used by drivers that are converted to driver model. Signed-off-by: Simon Glass --- drivers/serial/Makefile | 4 + drivers/serial/serial-uclass.c | 213 +++++++++++++++++++++++++++++++++++++++++ include/dm/uclass-id.h | 1 + include/serial.h | 92 ++++++++++++++++++ 4 files changed, 310 insertions(+) create mode 100644 drivers/serial/serial-uclass.c (limited to 'include') diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 571c18fa932..4720e1d1448 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -5,7 +5,11 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_DM_SERIAL +obj-y += serial-uclass.o +else obj-y += serial.o +endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c new file mode 100644 index 00000000000..d04104e7470 --- /dev/null +++ b/drivers/serial/serial-uclass.c @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* The currently-selected console serial device */ +struct udevice *cur_dev __attribute__ ((section(".data"))); + +#ifndef CONFIG_SYS_MALLOC_F_LEN +#error "Serial is required before relocation - define CONFIG_SYS_MALLOC_F_LEN to make this work" +#endif + +static void serial_find_console_or_panic(void) +{ + int node; + + /* Check for a chosen console */ + node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path"); + if (node < 0) + node = fdtdec_get_alias_node(gd->fdt_blob, "console"); + if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &cur_dev)) + return; + + /* + * If the console is not marked to be bound before relocation, bind + * it anyway. + */ + if (node > 0 && + !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &cur_dev)) { + if (!device_probe(cur_dev)) + return; + cur_dev = NULL; + } + + /* + * Failing that, get the device with sequence number 0, or in extremis + * just the first serial device we can find. But we insist on having + * a console (even if it is silent). + */ + if (uclass_get_device_by_seq(UCLASS_SERIAL, 0, &cur_dev) && + (uclass_first_device(UCLASS_SERIAL, &cur_dev) || !cur_dev)) + panic("No serial driver found"); +} + +/* Called prior to relocation */ +int serial_init(void) +{ + serial_find_console_or_panic(); + gd->flags |= GD_FLG_SERIAL_READY; + + return 0; +} + +/* Called after relocation */ +void serial_initialize(void) +{ + serial_find_console_or_panic(); +} + +void serial_putc(char ch) +{ + struct dm_serial_ops *ops = serial_get_ops(cur_dev); + int err; + + do { + err = ops->putc(cur_dev, ch); + } while (err == -EAGAIN); + if (ch == '\n') + serial_putc('\r'); +} + +void serial_setbrg(void) +{ + struct dm_serial_ops *ops = serial_get_ops(cur_dev); + + if (ops->setbrg) + ops->setbrg(cur_dev, gd->baudrate); +} + +void serial_puts(const char *str) +{ + while (*str) + serial_putc(*str++); +} + +int serial_tstc(void) +{ + struct dm_serial_ops *ops = serial_get_ops(cur_dev); + + if (ops->pending) + return ops->pending(cur_dev, true); + + return 1; +} + +int serial_getc(void) +{ + struct dm_serial_ops *ops = serial_get_ops(cur_dev); + int err; + + do { + err = ops->getc(cur_dev); + } while (err == -EAGAIN); + + return err >= 0 ? err : 0; +} + +void serial_stdio_init(void) +{ +} + +void serial_stub_putc(struct stdio_dev *sdev, const char ch) +{ + struct udevice *dev = sdev->priv; + struct dm_serial_ops *ops = serial_get_ops(dev); + + ops->putc(dev, ch); +} + +void serial_stub_puts(struct stdio_dev *sdev, const char *str) +{ + while (*str) + serial_stub_putc(sdev, *str++); +} + +int serial_stub_getc(struct stdio_dev *sdev) +{ + struct udevice *dev = sdev->priv; + struct dm_serial_ops *ops = serial_get_ops(dev); + + int err; + + do { + err = ops->getc(dev); + } while (err == -EAGAIN); + + return err >= 0 ? err : 0; +} + +int serial_stub_tstc(struct stdio_dev *sdev) +{ + struct udevice *dev = sdev->priv; + struct dm_serial_ops *ops = serial_get_ops(dev); + + if (ops->pending) + return ops->pending(dev, true); + + return 1; +} + +static int serial_post_probe(struct udevice *dev) +{ + struct stdio_dev sdev; + struct dm_serial_ops *ops = serial_get_ops(dev); + struct serial_dev_priv *upriv = dev->uclass_priv; + int ret; + + /* Set the baud rate */ + if (ops->setbrg) { + ret = ops->setbrg(dev, gd->baudrate); + if (ret) + return ret; + } + + if (!(gd->flags & GD_FLG_RELOC)) + return 0; + + memset(&sdev, '\0', sizeof(sdev)); + + strncpy(sdev.name, dev->name, sizeof(sdev.name)); + sdev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT; + sdev.priv = dev; + sdev.putc = serial_stub_putc; + sdev.puts = serial_stub_puts; + sdev.getc = serial_stub_getc; + sdev.tstc = serial_stub_tstc; + stdio_register_dev(&sdev, &upriv->sdev); + + return 0; +} + +static int serial_pre_remove(struct udevice *dev) +{ +#ifdef CONFIG_SYS_STDIO_DEREGISTER + struct serial_dev_priv *upriv = dev->uclass_priv; + + if (stdio_deregister_dev(upriv->sdev)) + return -EPERM; +#endif + + return 0; +} + +UCLASS_DRIVER(serial) = { + .id = UCLASS_SERIAL, + .name = "serial", + .post_probe = serial_post_probe, + .pre_remove = serial_pre_remove, + .per_device_auto_alloc_size = sizeof(struct serial_dev_priv), +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index dd95fca428d..7f0e37b7b78 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -21,6 +21,7 @@ enum uclass_id { /* U-Boot uclasses start here */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ + UCLASS_SERIAL, /* Serial UART */ UCLASS_COUNT, UCLASS_INVALID = -1, diff --git a/include/serial.h b/include/serial.h index d232d470a33..8f574e4ef89 100644 --- a/include/serial.h +++ b/include/serial.h @@ -72,4 +72,96 @@ extern int write_port(struct stdio_dev *port, char *buf); extern int read_port(struct stdio_dev *port, char *buf, int size); #endif +struct udevice; + +/** + * struct struct dm_serial_ops - Driver model serial operations + * + * The uclass interface is implemented by all serial devices which use + * driver model. + */ +struct dm_serial_ops { + /** + * setbrg() - Set up the baud rate generator + * + * Adjust baud rate divisors to set up a new baud rate for this + * device. Not all devices will support all rates. If the rate + * cannot be supported, the driver is free to select the nearest + * available rate. or return -EINVAL if this is not possible. + * + * @dev: Device pointer + * @baudrate: New baud rate to use + * @return 0 if OK, -ve on error + */ + int (*setbrg)(struct udevice *dev, int baudrate); + /** + * getc() - Read a character and return it + * + * If no character is available, this should return -EAGAIN without + * waiting. + * + * @dev: Device pointer + * @return character (0..255), -ve on error + */ + int (*getc)(struct udevice *dev); + /** + * putc() - Write a character + * + * @dev: Device pointer + * @ch: character to write + * @return 0 if OK, -ve on error + */ + int (*putc)(struct udevice *dev, const char ch); + /** + * pending() - Check if input/output characters are waiting + * + * This can be used to return an indication of the number of waiting + * characters if the driver knows this (e.g. by looking at the FIFO + * level). It is acceptable to return 1 if an indeterminant number + * of characters is waiting. + * + * This method is optional. + * + * @dev: Device pointer + * @input: true to check input characters, false for output + * @return number of waiting characters, 0 for none, -ve on error + */ + int (*pending)(struct udevice *dev, bool input); + /** + * clear() - Clear the serial FIFOs/holding registers + * + * This method is optional. + * + * This quickly clears any input/output characters from the UART. + * If this is not possible, but characters still exist, then it + * is acceptable to return -EAGAIN (try again) or -EINVAL (not + * supported). + * + * @dev: Device pointer + * @return 0 if OK, -ve on error + */ + int (*clear)(struct udevice *dev); +#if CONFIG_POST & CONFIG_SYS_POST_UART + /** + * loop() - Control serial device loopback mode + * + * @dev: Device pointer + * @on: 1 to turn loopback on, 0 to turn if off + */ + int (*loop)(struct udevice *dev, int on); +#endif +}; + +/** + * struct serial_dev_priv - information about a device used by the uclass + * + * @sdev: stdio device attached to this uart + */ +struct serial_dev_priv { + struct stdio_dev *sdev; +}; + +/* Access the serial operations for a device */ +#define serial_get_ops(dev) ((struct dm_serial_ops *)(dev)->driver->ops) + #endif -- cgit v1.3.1 From 890fcefe2e20b30a3d98f667c2dcfb382b1de2e6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 4 Sep 2014 16:27:27 -0600 Subject: sandbox: Convert serial driver to use driver model Adjust the sandbox serial driver to use the new driver model uclass. The driver works much as before, but within the new framework. Signed-off-by: Simon Glass --- drivers/serial/sandbox.c | 67 +++++++++++++++++++++++++---------------------- include/configs/sandbox.h | 3 +++ 2 files changed, 39 insertions(+), 31 deletions(-) (limited to 'include') diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index 51fd871dff9..ac54e0167eb 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -11,12 +11,16 @@ */ #include +#include +#include #include #include #include #include #include +DECLARE_GLOBAL_DATA_PTR; + /* * * serial_buf: A buffer that holds keyboard characters for the @@ -30,27 +34,21 @@ static char serial_buf[16]; static unsigned int serial_buf_write; static unsigned int serial_buf_read; -static int sandbox_serial_init(void) +static int sandbox_serial_probe(struct udevice *dev) { struct sandbox_state *state = state_get_current(); if (state->term_raw != STATE_TERM_COOKED) os_tty_raw(0, state->term_raw == STATE_TERM_RAW_WITH_SIGS); - return 0; -} -static void sandbox_serial_setbrg(void) -{ + return 0; } -static void sandbox_serial_putc(const char ch) +static int sandbox_serial_putc(struct udevice *dev, const char ch) { os_write(1, &ch, 1); -} -static void sandbox_serial_puts(const char *str) -{ - os_write(1, str, strlen(str)); + return 0; } static unsigned int increment_buffer_index(unsigned int index) @@ -58,12 +56,15 @@ static unsigned int increment_buffer_index(unsigned int index) return (index + 1) % ARRAY_SIZE(serial_buf); } -static int sandbox_serial_tstc(void) +static int sandbox_serial_pending(struct udevice *dev, bool input) { const unsigned int next_index = increment_buffer_index(serial_buf_write); ssize_t count; + if (!input) + return 0; + os_usleep(100); #ifdef CONFIG_LCD lcd_sync(); @@ -74,38 +75,42 @@ static int sandbox_serial_tstc(void) count = os_read_no_block(0, &serial_buf[serial_buf_write], 1); if (count == 1) serial_buf_write = next_index; + return serial_buf_write != serial_buf_read; } -static int sandbox_serial_getc(void) +static int sandbox_serial_getc(struct udevice *dev) { int result; - while (!sandbox_serial_tstc()) - ; /* buffer empty */ + if (!sandbox_serial_pending(dev, true)) + return -EAGAIN; /* buffer empty */ result = serial_buf[serial_buf_read]; serial_buf_read = increment_buffer_index(serial_buf_read); return result; } -static struct serial_device sandbox_serial_drv = { - .name = "sandbox_serial", - .start = sandbox_serial_init, - .stop = NULL, - .setbrg = sandbox_serial_setbrg, - .putc = sandbox_serial_putc, - .puts = sandbox_serial_puts, - .getc = sandbox_serial_getc, - .tstc = sandbox_serial_tstc, +static const struct dm_serial_ops sandbox_serial_ops = { + .putc = sandbox_serial_putc, + .pending = sandbox_serial_pending, + .getc = sandbox_serial_getc, }; -void sandbox_serial_initialize(void) -{ - serial_register(&sandbox_serial_drv); -} +static const struct udevice_id sandbox_serial_ids[] = { + { .compatible = "sandbox,serial" }, + { } +}; -__weak struct serial_device *default_serial_console(void) -{ - return &sandbox_serial_drv; -} +U_BOOT_DRIVER(serial_sandbox) = { + .name = "serial_sandbox", + .id = UCLASS_SERIAL, + .of_match = sandbox_serial_ids, + .probe = sandbox_serial_probe, + .ops = &sandbox_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +U_BOOT_DEVICE(serial_sandbox_non_fdt) = { + .name = "serial_sandbox", +}; diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index bf2d25c8712..f5fa4b3ddc3 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -31,6 +31,9 @@ #define CONFIG_DM_DEMO_SHAPE #define CONFIG_DM_GPIO #define CONFIG_DM_TEST +#define CONFIG_DM_SERIAL + +#define CONFIG_SYS_STDIO_DEREGISTER /* Number of bits in a C 'long' on this architecture */ #define CONFIG_SANDBOX_BITS_PER_LONG 64 -- cgit v1.3.1 From fa54eb12431efa845bc5692347ee3a7f39d897bc Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 4 Sep 2014 16:27:32 -0600 Subject: dm: serial: Move baud rate calculation to ns16550.c Move the function that calculates the baud rate divisor into ns16550.c so it can be used by that file. Signed-off-by: Simon Glass --- drivers/serial/ns16550.c | 18 +++++++++++++++++- drivers/serial/serial_ns16550.c | 14 ++++---------- include/ns16550.h | 13 +++++++++++++ 3 files changed, 34 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 079f67d3801..3f5f4efe077 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -4,7 +4,7 @@ * modified to use CONFIG_SYS_ISA_MEM and new defines */ -#include +#include #include #include #include @@ -45,6 +45,22 @@ #define CONFIG_SYS_NS16550_IER 0x00 #endif /* CONFIG_SYS_NS16550_IER */ +int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) +{ + const unsigned int mode_x_div = 16; + +#ifdef CONFIG_OMAP1510 + /* If can't cleanly clock 115200 set div to 1 */ + if ((clock == 12000000) && (baudrate == 115200)) { + port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */ + return 1; /* return 1 for base divisor */ + } + port->osc_12m_sel = 0; /* clear if previsouly set */ +#endif + + return DIV_ROUND_CLOSEST(clock, mode_x_div * baudrate); +} + void NS16550_init(NS16550_t com_port, int baud_divisor) { #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_OMAP34XX)) diff --git a/drivers/serial/serial_ns16550.c b/drivers/serial/serial_ns16550.c index dafeed742df..632da4cf70b 100644 --- a/drivers/serial/serial_ns16550.c +++ b/drivers/serial/serial_ns16550.c @@ -81,7 +81,8 @@ static NS16550_t serial_ports[6] = { static int eserial##port##_init(void) \ { \ int clock_divisor; \ - clock_divisor = calc_divisor(serial_ports[port-1]); \ + clock_divisor = ns16550_calc_divisor(serial_ports[port-1], \ + CONFIG_SYS_NS16550_CLK, gd->baudrate); \ NS16550_init(serial_ports[port-1], clock_divisor); \ return 0 ; \ } \ @@ -118,14 +119,6 @@ static NS16550_t serial_ports[6] = { .puts = eserial##port##_puts, \ } -static int calc_divisor (NS16550_t port) -{ - const unsigned int mode_x_div = 16; - - return DIV_ROUND_CLOSEST(CONFIG_SYS_NS16550_CLK, - mode_x_div * gd->baudrate); -} - void _serial_putc(const char c,const int port) { @@ -167,7 +160,8 @@ _serial_setbrg (const int port) { int clock_divisor; - clock_divisor = calc_divisor(PORT); + clock_divisor = ns16550_calc_divisor(PORT, CONFIG_SYS_NS16550_CLK, + gd->baudrate); NS16550_reinit(PORT, clock_divisor); } diff --git a/include/ns16550.h b/include/ns16550.h index d1f3a906c09..d93e28e3eca 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -170,3 +170,16 @@ void NS16550_putc(NS16550_t com_port, char c); char NS16550_getc(NS16550_t com_port); int NS16550_tstc(NS16550_t com_port); void NS16550_reinit(NS16550_t com_port, int baud_divisor); + +/** + * ns16550_calc_divisor() - calculate the divisor given clock and baud rate + * + * Given the UART input clock and required baudrate, calculate the divisor + * that should be used. + * + * @port: UART port + * @clock: UART input clock speed in Hz + * @baudrate: Required baud rate + * @return baud rate divisor that should be used + */ +int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate); -- cgit v1.3.1 From 12e431b2777ce3b6940d7b7f1e32e28f58277560 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 4 Sep 2014 16:27:34 -0600 Subject: dm: serial: Add driver model support for ns16550 Add driver model support so that ns16550 can support operation both with and without driver model. The driver needs a clock frequency so cannot stand alone unfortunately. The clock frequency must be provided by a separate driver. Signed-off-by: Simon Glass --- doc/device-tree-bindings/serial/ns16550.txt | 10 ++ drivers/serial/Makefile | 2 +- drivers/serial/ns16550.c | 156 +++++++++++++++++++++++++++- include/ns16550.h | 53 ++++++++++ 4 files changed, 218 insertions(+), 3 deletions(-) create mode 100644 doc/device-tree-bindings/serial/ns16550.txt (limited to 'include') diff --git a/doc/device-tree-bindings/serial/ns16550.txt b/doc/device-tree-bindings/serial/ns16550.txt new file mode 100644 index 00000000000..ef0b9aee6d0 --- /dev/null +++ b/doc/device-tree-bindings/serial/ns16550.txt @@ -0,0 +1,10 @@ +NS16550 UART + +This UART driver supports many chip variants and is used in mamy SoCs. + +Required properties: +- compatible: "ns16550" or "nvidia,tegra20-uart" +- reg: start address and size of registers +- reg-shift: shift value indicating register size: 0=byte, 1=16bit,2=32bit etc. +- clock-frequency: input clock frequency for the UART (used to calculate the + baud rate divisor) diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 4720e1d1448..5ae6416a4f9 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -9,6 +9,7 @@ ifdef CONFIG_DM_SERIAL obj-y += serial-uclass.o else obj-y += serial.o +obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o endif obj-$(CONFIG_ALTERA_UART) += altera_uart.o @@ -20,7 +21,6 @@ obj-$(CONFIG_MCFUART) += mcfuart.o obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P) += serial_s5p.o -obj-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o obj-$(CONFIG_IMX_SERIAL) += serial_imx.o obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index d54eba63372..63a9ef68444 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -5,17 +5,25 @@ */ #include +#include +#include +#include #include +#include #include #include #include +DECLARE_GLOBAL_DATA_PTR; + #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ UART_MCR_RTS) /* RTS/DTR */ #define UART_FCRVAL (UART_FCR_FIFO_EN | \ UART_FCR_RXSR | \ UART_FCR_TXSR) /* Clear & enable FIFOs */ + +#ifndef CONFIG_DM_SERIAL #ifdef CONFIG_SYS_NS16550_PORT_MAPPED #define serial_out(x, y) outb(x, (ulong)y) #define serial_in(y) inb((ulong)y) @@ -29,6 +37,7 @@ #define serial_out(x, y) writeb(x, y) #define serial_in(y) readb(y) #endif +#endif /* !CONFIG_DM_SERIAL */ #if defined(CONFIG_SOC_KEYSTONE) #define UART_REG_VAL_PWREMU_MGMT_UART_DISABLE 0 @@ -45,6 +54,58 @@ #define CONFIG_SYS_NS16550_IER 0x00 #endif /* CONFIG_SYS_NS16550_IER */ +#ifdef CONFIG_DM_SERIAL +static void ns16550_writeb(NS16550_t port, int offset, int value) +{ + struct ns16550_platdata *plat = port->plat; + unsigned char *addr; + + offset *= 1 << plat->reg_shift; + addr = plat->base + offset; + /* + * As far as we know it doesn't make sense to support selection of + * these options at run-time, so use the existing CONFIG options. + */ +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED + outb(value, addr); +#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN) + out_le32(addr, value); +#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) + out_be32(addr, value); +#elif defined(CONFIG_SYS_BIG_ENDIAN) + writeb(value, addr + (1 << plat->reg_shift) - 1); +#else + writeb(value, addr); +#endif +} + +static int ns16550_readb(NS16550_t port, int offset) +{ + struct ns16550_platdata *plat = port->plat; + unsigned char *addr; + + offset *= 1 << plat->reg_shift; + addr = plat->base + offset; +#ifdef CONFIG_SYS_NS16550_PORT_MAPPED + return inb(addr); +#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_SYS_BIG_ENDIAN) + return in_le32(addr); +#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN) + return in_be32(addr); +#elif defined(CONFIG_SYS_BIG_ENDIAN) + return readb(addr + (1 << plat->reg_shift) - 1); +#else + return readb(addr); +#endif +} + +/* We can clean these up once everything is moved to driver model */ +#define serial_out(value, addr) \ + ns16550_writeb(com_port, addr - (unsigned char *)com_port, value) +#define serial_in(addr) \ + ns16550_readb(com_port, addr - (unsigned char *)com_port) +#endif + int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate) { const unsigned int mode_x_div = 16; @@ -79,7 +140,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) */ if ((serial_in(&com_port->lsr) & (UART_LSR_TEMT | UART_LSR_THRE)) == UART_LSR_THRE) { - NS16550_setbrg(com_port, baud_divisor); + if (baud_divisor != -1) + NS16550_setbrg(com_port, baud_divisor); serial_out(0, &com_port->mdr1); } #endif @@ -95,7 +157,8 @@ void NS16550_init(NS16550_t com_port, int baud_divisor) NS16550_setbrg(com_port, 0); serial_out(UART_MCRVAL, &com_port->mcr); serial_out(UART_FCRVAL, &com_port->fcr); - NS16550_setbrg(com_port, baud_divisor); + if (baud_divisor != -1) + NS16550_setbrg(com_port, baud_divisor); #if defined(CONFIG_OMAP) || \ defined(CONFIG_AM33XX) || defined(CONFIG_SOC_DA8XX) || \ defined(CONFIG_TI81XX) || defined(CONFIG_AM43XX) @@ -154,3 +217,92 @@ int NS16550_tstc(NS16550_t com_port) } #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ + +#ifdef CONFIG_DM_SERIAL +static int ns16550_serial_putc(struct udevice *dev, const char ch) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + + if (!(serial_in(&com_port->lsr) & UART_LSR_THRE)) + return -EAGAIN; + serial_out(ch, &com_port->thr); + + /* + * Call watchdog_reset() upon newline. This is done here in putc + * since the environment code uses a single puts() to print the complete + * environment upon "printenv". So we can't put this watchdog call + * in puts(). + */ + if (ch == '\n') + WATCHDOG_RESET(); + + return 0; +} + +static int ns16550_serial_pending(struct udevice *dev, bool input) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + + if (input) + return serial_in(&com_port->lsr) & UART_LSR_DR ? 1 : 0; + else + return serial_in(&com_port->lsr) & UART_LSR_THRE ? 0 : 1; +} + +static int ns16550_serial_getc(struct udevice *dev) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + + if (!serial_in(&com_port->lsr) & UART_LSR_DR) + return -EAGAIN; + + return serial_in(&com_port->rbr); +} + +static int ns16550_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + struct ns16550_platdata *plat = com_port->plat; + int clock_divisor; + + clock_divisor = ns16550_calc_divisor(com_port, plat->clock, baudrate); + + NS16550_setbrg(com_port, clock_divisor); + + return 0; +} + +int ns16550_serial_probe(struct udevice *dev) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + + NS16550_init(com_port, -1); + + return 0; +} + +int ns16550_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct NS16550 *const com_port = dev_get_priv(dev); + struct ns16550_platdata *plat = dev->platdata; + fdt_addr_t addr; + + addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->base = (unsigned char *)addr; + plat->reg_shift = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "reg-shift", 1); + com_port->plat = plat; + + return 0; +} + +const struct dm_serial_ops ns16550_serial_ops = { + .putc = ns16550_serial_putc, + .pending = ns16550_serial_pending, + .getc = ns16550_serial_getc, + .setbrg = ns16550_serial_setbrg, +}; +#endif /* CONFIG_DM_SERIAL */ diff --git a/include/ns16550.h b/include/ns16550.h index d93e28e3eca..5784cfd97b8 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -23,6 +23,14 @@ #include +#ifdef CONFIG_DM_SERIAL +/* + * For driver model we always use one byte per register, and sort out the + * differences in the driver + */ +#define CONFIG_SYS_NS16550_REG_SIZE (-1) +#endif + #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) #error "Please define NS16550 registers size." #elif defined(CONFIG_SYS_NS16550_MEM32) @@ -37,6 +45,21 @@ unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; #endif +/** + * struct ns16550_platdata - information about a NS16550 port + * + * @base: Base register address + * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) + * @clock: UART base clock speed in Hz + */ +struct ns16550_platdata { + unsigned char *base; + int reg_shift; + int clock; +}; + +struct udevice; + struct NS16550 { UART_REG(rbr); /* 0 */ UART_REG(ier); /* 1 */ @@ -65,6 +88,9 @@ struct NS16550 { UART_REG(scr); /* 10*/ UART_REG(ssr); /* 11*/ #endif +#ifdef CONFIG_DM_SERIAL + struct ns16550_platdata *plat; +#endif }; #define thr rbr @@ -183,3 +209,30 @@ void NS16550_reinit(NS16550_t com_port, int baud_divisor); * @return baud rate divisor that should be used */ int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate); + +/** + * ns16550_serial_ofdata_to_platdata() - convert DT to platform data + * + * Decode a device tree node for an ns16550 device. This includes the + * register base address and register shift properties. The caller must set + * up the clock frequency. + * + * @dev: dev to decode platform data for + * @return: 0 if OK, -EINVAL on error + */ +int ns16550_serial_ofdata_to_platdata(struct udevice *dev); + +/** + * ns16550_serial_probe() - probe a serial port + * + * This sets up the serial port ready for use, except for the baud rate + * @return 0, or -ve on error + */ +int ns16550_serial_probe(struct udevice *dev); + +/** + * struct ns16550_serial_ops - ns16550 serial operations + * + * These should be used by the client driver for the driver's 'ops' member + */ +extern const struct dm_serial_ops ns16550_serial_ops; -- cgit v1.3.1 From c369139234c03b1494394d12cd27009f47aa6606 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 4 Sep 2014 16:27:35 -0600 Subject: tegra: dts: Add serial port details Some Tegra device tree files do not include information about the serial ports. Add this and also add information about the input clock speed. The console alias needs to be set up to indicate which port is used for the console. Also add a binding file since this is missing. Series-changes; 5 - Add full serial port nodes from Linux tree (commit fc9d4dbe) - Use /chosen/stdout-path instead of /aliases/console to specify the console Signed-off-by: Simon Glass --- arch/arm/dts/tegra114-dalmore.dts | 4 + arch/arm/dts/tegra114.dtsi | 53 +++++ arch/arm/dts/tegra124-jetson-tk1.dts | 4 + arch/arm/dts/tegra124-venice2.dts | 4 + arch/arm/dts/tegra124.dtsi | 66 ++++++ arch/arm/dts/tegra20-colibri_t20_iris.dts | 4 + arch/arm/dts/tegra20-harmony.dts | 4 + arch/arm/dts/tegra20-medcom-wide.dts | 4 + arch/arm/dts/tegra20-paz00.dts | 4 + arch/arm/dts/tegra20-plutux.dts | 4 + arch/arm/dts/tegra20-seaboard.dts | 4 + arch/arm/dts/tegra20-tec.dts | 4 + arch/arm/dts/tegra20-trimslice.dts | 4 + arch/arm/dts/tegra20-ventana.dts | 4 + arch/arm/dts/tegra20-whistler.dts | 4 + arch/arm/dts/tegra20.dtsi | 51 ++++- arch/arm/dts/tegra30-beaver.dts | 4 + arch/arm/dts/tegra30-cardhu.dts | 4 + arch/arm/dts/tegra30-tamonten.dtsi | 4 + arch/arm/dts/tegra30.dtsi | 66 ++++++ include/dt-bindings/clock/tegra114-car.h | 342 ++++++++++++++++++++++++++++++ include/dt-bindings/clock/tegra124-car.h | 342 ++++++++++++++++++++++++++++++ include/dt-bindings/clock/tegra20-car.h | 158 ++++++++++++++ include/dt-bindings/clock/tegra30-car.h | 273 ++++++++++++++++++++++++ 24 files changed, 1405 insertions(+), 10 deletions(-) create mode 100644 include/dt-bindings/clock/tegra114-car.h create mode 100644 include/dt-bindings/clock/tegra124-car.h create mode 100644 include/dt-bindings/clock/tegra20-car.h create mode 100644 include/dt-bindings/clock/tegra30-car.h (limited to 'include') diff --git a/arch/arm/dts/tegra114-dalmore.dts b/arch/arm/dts/tegra114-dalmore.dts index 435c01e9f66..81ad212e712 100644 --- a/arch/arm/dts/tegra114-dalmore.dts +++ b/arch/arm/dts/tegra114-dalmore.dts @@ -6,6 +6,10 @@ model = "NVIDIA Dalmore"; compatible = "nvidia,dalmore", "nvidia,tegra114"; + chosen { + stdout-path = &uartd; + }; + aliases { i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi index 59434e0a8f7..88bdc490450 100644 --- a/arch/arm/dts/tegra114.dtsi +++ b/arch/arm/dts/tegra114.dtsi @@ -1,3 +1,4 @@ +#include #include #include @@ -116,6 +117,58 @@ status = "disabled"; }; + uarta: serial@70006000 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartd: serial@70006300 { + compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi@7000d400 { compatible = "nvidia,tegra114-spi"; reg = <0x7000d400 0x200>; diff --git a/arch/arm/dts/tegra124-jetson-tk1.dts b/arch/arm/dts/tegra124-jetson-tk1.dts index 464287e03ec..ffad1160cd9 100644 --- a/arch/arm/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/dts/tegra124-jetson-tk1.dts @@ -6,6 +6,10 @@ model = "NVIDIA Jetson TK1"; compatible = "nvidia,jetson-tk1", "nvidia,tegra124"; + chosen { + stdout-path = &uartd; + }; + aliases { i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; diff --git a/arch/arm/dts/tegra124-venice2.dts b/arch/arm/dts/tegra124-venice2.dts index f003413bd79..f7ccfc5ddd4 100644 --- a/arch/arm/dts/tegra124-venice2.dts +++ b/arch/arm/dts/tegra124-venice2.dts @@ -6,6 +6,10 @@ model = "NVIDIA Venice2"; compatible = "nvidia,venice2", "nvidia,tegra124"; + chosen { + stdout-path = &uarta; + }; + aliases { i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; diff --git a/arch/arm/dts/tegra124.dtsi b/arch/arm/dts/tegra124.dtsi index 4561c5f8394..3288f28daeb 100644 --- a/arch/arm/dts/tegra124.dtsi +++ b/arch/arm/dts/tegra124.dtsi @@ -1,3 +1,4 @@ +#include #include #include @@ -126,6 +127,71 @@ status = "disabled"; }; + uarta: serial@70006000 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartd: serial@70006300 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uarte: serial@70006400 { + compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; + reg = <0x70006400 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_UARTE>; + resets = <&tegra_car 66>; + reset-names = "serial"; + dmas = <&apbdma 20>, <&apbdma 20>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi@7000d400 { compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; reg = <0x7000d400 0x200>; diff --git a/arch/arm/dts/tegra20-colibri_t20_iris.dts b/arch/arm/dts/tegra20-colibri_t20_iris.dts index c0e54af8868..7cf08f4101f 100644 --- a/arch/arm/dts/tegra20-colibri_t20_iris.dts +++ b/arch/arm/dts/tegra20-colibri_t20_iris.dts @@ -6,6 +6,10 @@ model = "Toradex Colibri T20"; compatible = "toradex,t20", "nvidia,tegra20"; + chosen { + stdout-path = &uarta; + }; + aliases { usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; diff --git a/arch/arm/dts/tegra20-harmony.dts b/arch/arm/dts/tegra20-harmony.dts index b115f87821d..982a14c61c4 100644 --- a/arch/arm/dts/tegra20-harmony.dts +++ b/arch/arm/dts/tegra20-harmony.dts @@ -6,6 +6,10 @@ model = "NVIDIA Tegra20 Harmony evaluation board"; compatible = "nvidia,harmony", "nvidia,tegra20"; + chosen { + stdout-path = &uartd; + }; + aliases { usb0 = "/usb@c5008000"; usb1 = "/usb@c5004000"; diff --git a/arch/arm/dts/tegra20-medcom-wide.dts b/arch/arm/dts/tegra20-medcom-wide.dts index a9a07f9bcd7..be2ed42dbd7 100644 --- a/arch/arm/dts/tegra20-medcom-wide.dts +++ b/arch/arm/dts/tegra20-medcom-wide.dts @@ -6,6 +6,10 @@ model = "Avionic Design Medcom-Wide"; compatible = "ad,medcom-wide", "nvidia,tegra20"; + chosen { + stdout-path = &uartd; + }; + aliases { usb0 = "/usb@c5008000"; sdhci0 = "/sdhci@c8000600"; diff --git a/arch/arm/dts/tegra20-paz00.dts b/arch/arm/dts/tegra20-paz00.dts index 780203cfb3a..9d735b5e6bf 100644 --- a/arch/arm/dts/tegra20-paz00.dts +++ b/arch/arm/dts/tegra20-paz00.dts @@ -6,6 +6,10 @@ model = "Toshiba AC100 / Dynabook AZ"; compatible = "compal,paz00", "nvidia,tegra20"; + chosen { + stdout-path = &uarta; + }; + aliases { usb0 = "/usb@c5008000"; sdhci0 = "/sdhci@c8000600"; diff --git a/arch/arm/dts/tegra20-plutux.dts b/arch/arm/dts/tegra20-plutux.dts index 20016f29bb3..e5562a9ca52 100644 --- a/arch/arm/dts/tegra20-plutux.dts +++ b/arch/arm/dts/tegra20-plutux.dts @@ -6,6 +6,10 @@ model = "Avionic Design Plutux"; compatible = "ad,plutux", "nvidia,tegra20"; + chosen { + stdout-path = &uartd; + }; + aliases { usb0 = "/usb@c5008000"; sdhci0 = "/sdhci@c8000600"; diff --git a/arch/arm/dts/tegra20-seaboard.dts b/arch/arm/dts/tegra20-seaboard.dts index c0e2e1e5fdb..43b9911c896 100644 --- a/arch/arm/dts/tegra20-seaboard.dts +++ b/arch/arm/dts/tegra20-seaboard.dts @@ -10,6 +10,10 @@ bootargs = "vmalloc=192M video=tegrafb console=ttyS0,115200n8 root=/dev/mmcblk1p3 rw rootwait"; }; + chosen { + stdout-path = &uartd; + }; + aliases { /* This defines the order of our ports */ usb0 = "/usb@c5008000"; diff --git a/arch/arm/dts/tegra20-tec.dts b/arch/arm/dts/tegra20-tec.dts index 4c1b08d7684..e99bd447c1b 100644 --- a/arch/arm/dts/tegra20-tec.dts +++ b/arch/arm/dts/tegra20-tec.dts @@ -6,6 +6,10 @@ model = "Avionic Design Tamonten Evaluation Carrier"; compatible = "ad,tec", "nvidia,tegra20"; + chosen { + stdout-path = &uartd; + }; + aliases { usb0 = "/usb@c5008000"; sdhci0 = "/sdhci@c8000600"; diff --git a/arch/arm/dts/tegra20-trimslice.dts b/arch/arm/dts/tegra20-trimslice.dts index ee31476c1eb..cee5cfe0d2d 100644 --- a/arch/arm/dts/tegra20-trimslice.dts +++ b/arch/arm/dts/tegra20-trimslice.dts @@ -6,6 +6,10 @@ model = "Compulab TrimSlice board"; compatible = "compulab,trimslice", "nvidia,tegra20"; + chosen { + stdout-path = &uarta; + }; + aliases { usb0 = "/usb@c5008000"; usb1 = "/usb@c5000000"; diff --git a/arch/arm/dts/tegra20-ventana.dts b/arch/arm/dts/tegra20-ventana.dts index 1a526bab641..68122039180 100644 --- a/arch/arm/dts/tegra20-ventana.dts +++ b/arch/arm/dts/tegra20-ventana.dts @@ -6,6 +6,10 @@ model = "NVIDIA Tegra20 Ventana evaluation board"; compatible = "nvidia,ventana", "nvidia,tegra20"; + chosen { + stdout-path = &uartd; + }; + aliases { usb0 = "/usb@c5008000"; sdhci0 = "/sdhci@c8000600"; diff --git a/arch/arm/dts/tegra20-whistler.dts b/arch/arm/dts/tegra20-whistler.dts index eb92264f9d6..4fd2496dbc5 100644 --- a/arch/arm/dts/tegra20-whistler.dts +++ b/arch/arm/dts/tegra20-whistler.dts @@ -6,6 +6,10 @@ model = "NVIDIA Tegra20 Whistler evaluation board"; compatible = "nvidia,whistler", "nvidia,tegra20"; + chosen { + stdout-path = &uarta; + }; + aliases { i2c0 = "/i2c@7000d000"; usb0 = "/usb@c5008000"; diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index a524f6eed41..5f927f7e0d4 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -1,3 +1,4 @@ +#include #include #include @@ -189,39 +190,69 @@ dma-channel = < 1 >; }; - serial@70006000 { + uarta: serial@70006000 { compatible = "nvidia,tegra20-uart"; reg = <0x70006000 0x40>; reg-shift = <2>; - interrupts = < 68 >; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + status = "disabled"; }; - serial@70006040 { + uartb: serial@70006040 { compatible = "nvidia,tegra20-uart"; reg = <0x70006040 0x40>; reg-shift = <2>; - interrupts = < 69 >; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; + status = "disabled"; }; - serial@70006200 { + uartc: serial@70006200 { compatible = "nvidia,tegra20-uart"; reg = <0x70006200 0x100>; reg-shift = <2>; - interrupts = < 78 >; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; + status = "disabled"; }; - serial@70006300 { + uartd: serial@70006300 { compatible = "nvidia,tegra20-uart"; reg = <0x70006300 0x100>; reg-shift = <2>; - interrupts = < 122 >; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; }; - serial@70006400 { + uarte: serial@70006400 { compatible = "nvidia,tegra20-uart"; reg = <0x70006400 0x100>; reg-shift = <2>; - interrupts = < 123 >; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_UARTE>; + resets = <&tegra_car 66>; + reset-names = "serial"; + dmas = <&apbdma 20>, <&apbdma 20>; + dma-names = "rx", "tx"; + status = "disabled"; }; nand: nand-controller@70008000 { diff --git a/arch/arm/dts/tegra30-beaver.dts b/arch/arm/dts/tegra30-beaver.dts index 85e62e9db32..ad140def95f 100644 --- a/arch/arm/dts/tegra30-beaver.dts +++ b/arch/arm/dts/tegra30-beaver.dts @@ -6,6 +6,10 @@ model = "NVIDIA Beaver"; compatible = "nvidia,beaver", "nvidia,tegra30"; + chosen { + stdout-path = &uarta; + }; + aliases { i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; diff --git a/arch/arm/dts/tegra30-cardhu.dts b/arch/arm/dts/tegra30-cardhu.dts index ea2cf76ff3a..b4fbe71aa53 100644 --- a/arch/arm/dts/tegra30-cardhu.dts +++ b/arch/arm/dts/tegra30-cardhu.dts @@ -6,6 +6,10 @@ model = "NVIDIA Cardhu"; compatible = "nvidia,cardhu", "nvidia,tegra30"; + chosen { + stdout-path = &uarta; + }; + aliases { i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; diff --git a/arch/arm/dts/tegra30-tamonten.dtsi b/arch/arm/dts/tegra30-tamonten.dtsi index 50d5762311e..c73afef34ad 100644 --- a/arch/arm/dts/tegra30-tamonten.dtsi +++ b/arch/arm/dts/tegra30-tamonten.dtsi @@ -8,6 +8,10 @@ reg = <0x80000000 0x40000000>; }; + chosen { + stdout-path = &uartd; + }; + aliases { i2c0 = "/i2c@7000c000"; i2c1 = "/i2c@7000c700"; diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi index 7be3791fc9a..fb92a0fef96 100644 --- a/arch/arm/dts/tegra30.dtsi +++ b/arch/arm/dts/tegra30.dtsi @@ -1,3 +1,4 @@ +#include #include #include @@ -122,6 +123,71 @@ status = "disabled"; }; + uarta: serial@70006000 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartb: serial@70006040 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006040 0x40>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartc: serial@70006200 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006200 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uartd: serial@70006300 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006300 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + uarte: serial@70006400 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006400 0x100>; + reg-shift = <2>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_UARTE>; + resets = <&tegra_car 66>; + reset-names = "serial"; + dmas = <&apbdma 20>, <&apbdma 20>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi@7000d400 { compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000d400 0x200>; diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h new file mode 100644 index 00000000000..6d0d8d8ef31 --- /dev/null +++ b/include/dt-bindings/clock/tegra114-car.h @@ -0,0 +1,342 @@ +/* + * This header provides constants for binding nvidia,tegra114-car. + * + * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 160 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 160 and + * above. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H + +/* 0 */ +/* 1 */ +/* 2 */ +/* 3 */ +#define TEGRA114_CLK_RTC 4 +#define TEGRA114_CLK_TIMER 5 +#define TEGRA114_CLK_UARTA 6 +/* 7 (register bit affects uartb and vfir) */ +/* 8 */ +#define TEGRA114_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA114_CLK_I2S1 11 +#define TEGRA114_CLK_I2C1 12 +#define TEGRA114_CLK_NDFLASH 13 +#define TEGRA114_CLK_SDMMC1 14 +#define TEGRA114_CLK_SDMMC4 15 +/* 16 */ +#define TEGRA114_CLK_PWM 17 +#define TEGRA114_CLK_I2S2 18 +#define TEGRA114_CLK_EPP 19 +/* 20 (register bit affects vi and vi_sensor) */ +#define TEGRA114_CLK_GR2D 21 +#define TEGRA114_CLK_USBD 22 +#define TEGRA114_CLK_ISP 23 +#define TEGRA114_CLK_GR3D 24 +/* 25 */ +#define TEGRA114_CLK_DISP2 26 +#define TEGRA114_CLK_DISP1 27 +#define TEGRA114_CLK_HOST1X 28 +#define TEGRA114_CLK_VCP 29 +#define TEGRA114_CLK_I2S0 30 +/* 31 */ + +/* 32 */ +/* 33 */ +#define TEGRA114_CLK_APBDMA 34 +/* 35 */ +#define TEGRA114_CLK_KBC 36 +/* 37 */ +/* 38 */ +/* 39 (register bit affects fuse and fuse_burn) */ +#define TEGRA114_CLK_KFUSE 40 +#define TEGRA114_CLK_SBC1 41 +#define TEGRA114_CLK_NOR 42 +/* 43 */ +#define TEGRA114_CLK_SBC2 44 +/* 45 */ +#define TEGRA114_CLK_SBC3 46 +#define TEGRA114_CLK_I2C5 47 +#define TEGRA114_CLK_DSIA 48 +/* 49 */ +#define TEGRA114_CLK_MIPI 50 +#define TEGRA114_CLK_HDMI 51 +#define TEGRA114_CLK_CSI 52 +/* 53 */ +#define TEGRA114_CLK_I2C2 54 +#define TEGRA114_CLK_UARTC 55 +#define TEGRA114_CLK_MIPI_CAL 56 +#define TEGRA114_CLK_EMC 57 +#define TEGRA114_CLK_USB2 58 +#define TEGRA114_CLK_USB3 59 +/* 60 */ +#define TEGRA114_CLK_VDE 61 +#define TEGRA114_CLK_BSEA 62 +#define TEGRA114_CLK_BSEV 63 + +/* 64 */ +#define TEGRA114_CLK_UARTD 65 +/* 66 */ +#define TEGRA114_CLK_I2C3 67 +#define TEGRA114_CLK_SBC4 68 +#define TEGRA114_CLK_SDMMC3 69 +/* 70 */ +#define TEGRA114_CLK_OWR 71 +/* 72 */ +#define TEGRA114_CLK_CSITE 73 +/* 74 */ +/* 75 */ +#define TEGRA114_CLK_LA 76 +#define TEGRA114_CLK_TRACE 77 +#define TEGRA114_CLK_SOC_THERM 78 +#define TEGRA114_CLK_DTV 79 +#define TEGRA114_CLK_NDSPEED 80 +#define TEGRA114_CLK_I2CSLOW 81 +#define TEGRA114_CLK_DSIB 82 +#define TEGRA114_CLK_TSEC 83 +/* 84 */ +/* 85 */ +/* 86 */ +/* 87 */ +/* 88 */ +#define TEGRA114_CLK_XUSB_HOST 89 +/* 90 */ +#define TEGRA114_CLK_MSENC 91 +#define TEGRA114_CLK_CSUS 92 +/* 93 */ +/* 94 */ +/* 95 (bit affects xusb_dev and xusb_dev_src) */ + +/* 96 */ +/* 97 */ +/* 98 */ +#define TEGRA114_CLK_MSELECT 99 +#define TEGRA114_CLK_TSENSOR 100 +#define TEGRA114_CLK_I2S3 101 +#define TEGRA114_CLK_I2S4 102 +#define TEGRA114_CLK_I2C4 103 +#define TEGRA114_CLK_SBC5 104 +#define TEGRA114_CLK_SBC6 105 +#define TEGRA114_CLK_D_AUDIO 106 +#define TEGRA114_CLK_APBIF 107 +#define TEGRA114_CLK_DAM0 108 +#define TEGRA114_CLK_DAM1 109 +#define TEGRA114_CLK_DAM2 110 +#define TEGRA114_CLK_HDA2CODEC_2X 111 +/* 112 */ +#define TEGRA114_CLK_AUDIO0_2X 113 +#define TEGRA114_CLK_AUDIO1_2X 114 +#define TEGRA114_CLK_AUDIO2_2X 115 +#define TEGRA114_CLK_AUDIO3_2X 116 +#define TEGRA114_CLK_AUDIO4_2X 117 +#define TEGRA114_CLK_SPDIF_2X 118 +#define TEGRA114_CLK_ACTMON 119 +#define TEGRA114_CLK_EXTERN1 120 +#define TEGRA114_CLK_EXTERN2 121 +#define TEGRA114_CLK_EXTERN3 122 +/* 123 */ +/* 124 */ +#define TEGRA114_CLK_HDA 125 +/* 126 */ +#define TEGRA114_CLK_SE 127 + +#define TEGRA114_CLK_HDA2HDMI 128 +/* 129 */ +/* 130 */ +/* 131 */ +/* 132 */ +/* 133 */ +/* 134 */ +/* 135 */ +/* 136 */ +/* 137 */ +/* 138 */ +/* 139 */ +/* 140 */ +/* 141 */ +/* 142 */ +/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ +/* xusb_host_src and xusb_ss_src) */ +#define TEGRA114_CLK_CILAB 144 +#define TEGRA114_CLK_CILCD 145 +#define TEGRA114_CLK_CILE 146 +#define TEGRA114_CLK_DSIALP 147 +#define TEGRA114_CLK_DSIBLP 148 +/* 149 */ +#define TEGRA114_CLK_DDS 150 +/* 151 */ +#define TEGRA114_CLK_DP2 152 +#define TEGRA114_CLK_AMX 153 +#define TEGRA114_CLK_ADX 154 +/* 155 (bit affects dfll_ref and dfll_soc) */ +#define TEGRA114_CLK_XUSB_SS 156 +/* 157 */ +/* 158 */ +/* 159 */ + +/* 160 */ +/* 161 */ +/* 162 */ +/* 163 */ +/* 164 */ +/* 165 */ +/* 166 */ +/* 167 */ +/* 168 */ +/* 169 */ +/* 170 */ +/* 171 */ +/* 172 */ +/* 173 */ +/* 174 */ +/* 175 */ +/* 176 */ +/* 177 */ +/* 178 */ +/* 179 */ +/* 180 */ +/* 181 */ +/* 182 */ +/* 183 */ +/* 184 */ +/* 185 */ +/* 186 */ +/* 187 */ +/* 188 */ +/* 189 */ +/* 190 */ +/* 191 */ + +#define TEGRA114_CLK_UARTB 192 +#define TEGRA114_CLK_VFIR 193 +#define TEGRA114_CLK_SPDIF_IN 194 +#define TEGRA114_CLK_SPDIF_OUT 195 +#define TEGRA114_CLK_VI 196 +#define TEGRA114_CLK_VI_SENSOR 197 +#define TEGRA114_CLK_FUSE 198 +#define TEGRA114_CLK_FUSE_BURN 199 +#define TEGRA114_CLK_CLK_32K 200 +#define TEGRA114_CLK_CLK_M 201 +#define TEGRA114_CLK_CLK_M_DIV2 202 +#define TEGRA114_CLK_CLK_M_DIV4 203 +#define TEGRA114_CLK_PLL_REF 204 +#define TEGRA114_CLK_PLL_C 205 +#define TEGRA114_CLK_PLL_C_OUT1 206 +#define TEGRA114_CLK_PLL_C2 207 +#define TEGRA114_CLK_PLL_C3 208 +#define TEGRA114_CLK_PLL_M 209 +#define TEGRA114_CLK_PLL_M_OUT1 210 +#define TEGRA114_CLK_PLL_P 211 +#define TEGRA114_CLK_PLL_P_OUT1 212 +#define TEGRA114_CLK_PLL_P_OUT2 213 +#define TEGRA114_CLK_PLL_P_OUT3 214 +#define TEGRA114_CLK_PLL_P_OUT4 215 +#define TEGRA114_CLK_PLL_A 216 +#define TEGRA114_CLK_PLL_A_OUT0 217 +#define TEGRA114_CLK_PLL_D 218 +#define TEGRA114_CLK_PLL_D_OUT0 219 +#define TEGRA114_CLK_PLL_D2 220 +#define TEGRA114_CLK_PLL_D2_OUT0 221 +#define TEGRA114_CLK_PLL_U 222 +#define TEGRA114_CLK_PLL_U_480M 223 + +#define TEGRA114_CLK_PLL_U_60M 224 +#define TEGRA114_CLK_PLL_U_48M 225 +#define TEGRA114_CLK_PLL_U_12M 226 +#define TEGRA114_CLK_PLL_X 227 +#define TEGRA114_CLK_PLL_X_OUT0 228 +#define TEGRA114_CLK_PLL_RE_VCO 229 +#define TEGRA114_CLK_PLL_RE_OUT 230 +#define TEGRA114_CLK_PLL_E_OUT0 231 +#define TEGRA114_CLK_SPDIF_IN_SYNC 232 +#define TEGRA114_CLK_I2S0_SYNC 233 +#define TEGRA114_CLK_I2S1_SYNC 234 +#define TEGRA114_CLK_I2S2_SYNC 235 +#define TEGRA114_CLK_I2S3_SYNC 236 +#define TEGRA114_CLK_I2S4_SYNC 237 +#define TEGRA114_CLK_VIMCLK_SYNC 238 +#define TEGRA114_CLK_AUDIO0 239 +#define TEGRA114_CLK_AUDIO1 240 +#define TEGRA114_CLK_AUDIO2 241 +#define TEGRA114_CLK_AUDIO3 242 +#define TEGRA114_CLK_AUDIO4 243 +#define TEGRA114_CLK_SPDIF 244 +#define TEGRA114_CLK_CLK_OUT_1 245 +#define TEGRA114_CLK_CLK_OUT_2 246 +#define TEGRA114_CLK_CLK_OUT_3 247 +#define TEGRA114_CLK_BLINK 248 +/* 249 */ +/* 250 */ +/* 251 */ +#define TEGRA114_CLK_XUSB_HOST_SRC 252 +#define TEGRA114_CLK_XUSB_FALCON_SRC 253 +#define TEGRA114_CLK_XUSB_FS_SRC 254 +#define TEGRA114_CLK_XUSB_SS_SRC 255 + +#define TEGRA114_CLK_XUSB_DEV_SRC 256 +#define TEGRA114_CLK_XUSB_DEV 257 +#define TEGRA114_CLK_XUSB_HS_SRC 258 +#define TEGRA114_CLK_SCLK 259 +#define TEGRA114_CLK_HCLK 260 +#define TEGRA114_CLK_PCLK 261 +#define TEGRA114_CLK_CCLK_G 262 +#define TEGRA114_CLK_CCLK_LP 263 +#define TEGRA114_CLK_DFLL_REF 264 +#define TEGRA114_CLK_DFLL_SOC 265 +/* 266 */ +/* 267 */ +/* 268 */ +/* 269 */ +/* 270 */ +/* 271 */ +/* 272 */ +/* 273 */ +/* 274 */ +/* 275 */ +/* 276 */ +/* 277 */ +/* 278 */ +/* 279 */ +/* 280 */ +/* 281 */ +/* 282 */ +/* 283 */ +/* 284 */ +/* 285 */ +/* 286 */ +/* 287 */ + +/* 288 */ +/* 289 */ +/* 290 */ +/* 291 */ +/* 292 */ +/* 293 */ +/* 294 */ +/* 295 */ +/* 296 */ +/* 297 */ +/* 298 */ +/* 299 */ +#define TEGRA114_CLK_AUDIO0_MUX 300 +#define TEGRA114_CLK_AUDIO1_MUX 301 +#define TEGRA114_CLK_AUDIO2_MUX 302 +#define TEGRA114_CLK_AUDIO3_MUX 303 +#define TEGRA114_CLK_AUDIO4_MUX 304 +#define TEGRA114_CLK_SPDIF_MUX 305 +#define TEGRA114_CLK_CLK_OUT_1_MUX 306 +#define TEGRA114_CLK_CLK_OUT_2_MUX 307 +#define TEGRA114_CLK_CLK_OUT_3_MUX 308 +#define TEGRA114_CLK_DSIA_MUX 309 +#define TEGRA114_CLK_DSIB_MUX 310 +#define TEGRA114_CLK_CLK_MAX 311 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h new file mode 100644 index 00000000000..fd8d62ac7f6 --- /dev/null +++ b/include/dt-bindings/clock/tegra124-car.h @@ -0,0 +1,342 @@ +/* + * This header provides constants for binding nvidia,tegra124-car. + * + * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 185 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 185 and + * above. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H + +/* 0 */ +/* 1 */ +/* 2 */ +#define TEGRA124_CLK_ISPB 3 +#define TEGRA124_CLK_RTC 4 +#define TEGRA124_CLK_TIMER 5 +#define TEGRA124_CLK_UARTA 6 +/* 7 (register bit affects uartb and vfir) */ +/* 8 */ +#define TEGRA124_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA124_CLK_I2S1 11 +#define TEGRA124_CLK_I2C1 12 +#define TEGRA124_CLK_NDFLASH 13 +#define TEGRA124_CLK_SDMMC1 14 +#define TEGRA124_CLK_SDMMC4 15 +/* 16 */ +#define TEGRA124_CLK_PWM 17 +#define TEGRA124_CLK_I2S2 18 +/* 20 (register bit affects vi and vi_sensor) */ +/* 21 */ +#define TEGRA124_CLK_USBD 22 +#define TEGRA124_CLK_ISP 23 +/* 26 */ +/* 25 */ +#define TEGRA124_CLK_DISP2 26 +#define TEGRA124_CLK_DISP1 27 +#define TEGRA124_CLK_HOST1X 28 +#define TEGRA124_CLK_VCP 29 +#define TEGRA124_CLK_I2S0 30 +/* 31 */ + +/* 32 */ +/* 33 */ +#define TEGRA124_CLK_APBDMA 34 +/* 35 */ +#define TEGRA124_CLK_KBC 36 +/* 37 */ +/* 38 */ +/* 39 (register bit affects fuse and fuse_burn) */ +#define TEGRA124_CLK_KFUSE 40 +#define TEGRA124_CLK_SBC1 41 +#define TEGRA124_CLK_NOR 42 +/* 43 */ +#define TEGRA124_CLK_SBC2 44 +/* 45 */ +#define TEGRA124_CLK_SBC3 46 +#define TEGRA124_CLK_I2C5 47 +#define TEGRA124_CLK_DSIA 48 +/* 49 */ +#define TEGRA124_CLK_MIPI 50 +#define TEGRA124_CLK_HDMI 51 +#define TEGRA124_CLK_CSI 52 +/* 53 */ +#define TEGRA124_CLK_I2C2 54 +#define TEGRA124_CLK_UARTC 55 +#define TEGRA124_CLK_MIPI_CAL 56 +#define TEGRA124_CLK_EMC 57 +#define TEGRA124_CLK_USB2 58 +#define TEGRA124_CLK_USB3 59 +/* 60 */ +#define TEGRA124_CLK_VDE 61 +#define TEGRA124_CLK_BSEA 62 +#define TEGRA124_CLK_BSEV 63 + +/* 64 */ +#define TEGRA124_CLK_UARTD 65 +#define TEGRA124_CLK_UARTE 66 +#define TEGRA124_CLK_I2C3 67 +#define TEGRA124_CLK_SBC4 68 +#define TEGRA124_CLK_SDMMC3 69 +#define TEGRA124_CLK_PCIE 70 +#define TEGRA124_CLK_OWR 71 +#define TEGRA124_CLK_AFI 72 +#define TEGRA124_CLK_CSITE 73 +/* 74 */ +/* 75 */ +#define TEGRA124_CLK_LA 76 +#define TEGRA124_CLK_TRACE 77 +#define TEGRA124_CLK_SOC_THERM 78 +#define TEGRA124_CLK_DTV 79 +#define TEGRA124_CLK_NDSPEED 80 +#define TEGRA124_CLK_I2CSLOW 81 +#define TEGRA124_CLK_DSIB 82 +#define TEGRA124_CLK_TSEC 83 +/* 84 */ +/* 85 */ +/* 86 */ +/* 87 */ +/* 88 */ +#define TEGRA124_CLK_XUSB_HOST 89 +/* 90 */ +#define TEGRA124_CLK_MSENC 91 +#define TEGRA124_CLK_CSUS 92 +/* 93 */ +/* 94 */ +/* 95 (bit affects xusb_dev and xusb_dev_src) */ + +/* 96 */ +/* 97 */ +/* 98 */ +#define TEGRA124_CLK_MSELECT 99 +#define TEGRA124_CLK_TSENSOR 100 +#define TEGRA124_CLK_I2S3 101 +#define TEGRA124_CLK_I2S4 102 +#define TEGRA124_CLK_I2C4 103 +#define TEGRA124_CLK_SBC5 104 +#define TEGRA124_CLK_SBC6 105 +#define TEGRA124_CLK_D_AUDIO 106 +#define TEGRA124_CLK_APBIF 107 +#define TEGRA124_CLK_DAM0 108 +#define TEGRA124_CLK_DAM1 109 +#define TEGRA124_CLK_DAM2 110 +#define TEGRA124_CLK_HDA2CODEC_2X 111 +/* 112 */ +#define TEGRA124_CLK_AUDIO0_2X 113 +#define TEGRA124_CLK_AUDIO1_2X 114 +#define TEGRA124_CLK_AUDIO2_2X 115 +#define TEGRA124_CLK_AUDIO3_2X 116 +#define TEGRA124_CLK_AUDIO4_2X 117 +#define TEGRA124_CLK_SPDIF_2X 118 +#define TEGRA124_CLK_ACTMON 119 +#define TEGRA124_CLK_EXTERN1 120 +#define TEGRA124_CLK_EXTERN2 121 +#define TEGRA124_CLK_EXTERN3 122 +#define TEGRA124_CLK_SATA_OOB 123 +#define TEGRA124_CLK_SATA 124 +#define TEGRA124_CLK_HDA 125 +/* 126 */ +#define TEGRA124_CLK_SE 127 + +#define TEGRA124_CLK_HDA2HDMI 128 +#define TEGRA124_CLK_SATA_COLD 129 +/* 130 */ +/* 131 */ +/* 132 */ +/* 133 */ +/* 134 */ +/* 135 */ +/* 136 */ +/* 137 */ +/* 138 */ +/* 139 */ +/* 140 */ +/* 141 */ +/* 142 */ +/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ +/* xusb_host_src and xusb_ss_src) */ +#define TEGRA124_CLK_CILAB 144 +#define TEGRA124_CLK_CILCD 145 +#define TEGRA124_CLK_CILE 146 +#define TEGRA124_CLK_DSIALP 147 +#define TEGRA124_CLK_DSIBLP 148 +#define TEGRA124_CLK_ENTROPY 149 +#define TEGRA124_CLK_DDS 150 +/* 151 */ +#define TEGRA124_CLK_DP2 152 +#define TEGRA124_CLK_AMX 153 +#define TEGRA124_CLK_ADX 154 +/* 155 (bit affects dfll_ref and dfll_soc) */ +#define TEGRA124_CLK_XUSB_SS 156 +/* 157 */ +/* 158 */ +/* 159 */ + +/* 160 */ +/* 161 */ +/* 162 */ +/* 163 */ +/* 164 */ +/* 165 */ +#define TEGRA124_CLK_I2C6 166 +/* 167 */ +/* 168 */ +/* 169 */ +/* 170 */ +#define TEGRA124_CLK_VIM2_CLK 171 +/* 172 */ +/* 173 */ +/* 174 */ +/* 175 */ +#define TEGRA124_CLK_HDMI_AUDIO 176 +#define TEGRA124_CLK_CLK72MHZ 177 +#define TEGRA124_CLK_VIC03 178 +/* 179 */ +#define TEGRA124_CLK_ADX1 180 +#define TEGRA124_CLK_DPAUX 181 +#define TEGRA124_CLK_SOR0 182 +/* 183 */ +#define TEGRA124_CLK_GPU 184 +#define TEGRA124_CLK_AMX1 185 +#define TEGRA124_CLK_AFC0 186 +#define TEGRA124_CLK_AFC1 187 +#define TEGRA124_CLK_AFC2 188 +#define TEGRA124_CLK_AFC3 189 +#define TEGRA124_CLK_AFC4 190 +#define TEGRA124_CLK_AFC5 191 +#define TEGRA124_CLK_UARTB 192 +#define TEGRA124_CLK_VFIR 193 +#define TEGRA124_CLK_SPDIF_IN 194 +#define TEGRA124_CLK_SPDIF_OUT 195 +#define TEGRA124_CLK_VI 196 +#define TEGRA124_CLK_VI_SENSOR 197 +#define TEGRA124_CLK_FUSE 198 +#define TEGRA124_CLK_FUSE_BURN 199 +#define TEGRA124_CLK_CLK_32K 200 +#define TEGRA124_CLK_CLK_M 201 +#define TEGRA124_CLK_CLK_M_DIV2 202 +#define TEGRA124_CLK_CLK_M_DIV4 203 +#define TEGRA124_CLK_PLL_REF 204 +#define TEGRA124_CLK_PLL_C 205 +#define TEGRA124_CLK_PLL_C_OUT1 206 +#define TEGRA124_CLK_PLL_C2 207 +#define TEGRA124_CLK_PLL_C3 208 +#define TEGRA124_CLK_PLL_M 209 +#define TEGRA124_CLK_PLL_M_OUT1 210 +#define TEGRA124_CLK_PLL_P 211 +#define TEGRA124_CLK_PLL_P_OUT1 212 +#define TEGRA124_CLK_PLL_P_OUT2 213 +#define TEGRA124_CLK_PLL_P_OUT3 214 +#define TEGRA124_CLK_PLL_P_OUT4 215 +#define TEGRA124_CLK_PLL_A 216 +#define TEGRA124_CLK_PLL_A_OUT0 217 +#define TEGRA124_CLK_PLL_D 218 +#define TEGRA124_CLK_PLL_D_OUT0 219 +#define TEGRA124_CLK_PLL_D2 220 +#define TEGRA124_CLK_PLL_D2_OUT0 221 +#define TEGRA124_CLK_PLL_U 222 +#define TEGRA124_CLK_PLL_U_480M 223 + +#define TEGRA124_CLK_PLL_U_60M 224 +#define TEGRA124_CLK_PLL_U_48M 225 +#define TEGRA124_CLK_PLL_U_12M 226 +#define TEGRA124_CLK_PLL_X 227 +#define TEGRA124_CLK_PLL_X_OUT0 228 +#define TEGRA124_CLK_PLL_RE_VCO 229 +#define TEGRA124_CLK_PLL_RE_OUT 230 +#define TEGRA124_CLK_PLL_E 231 +#define TEGRA124_CLK_SPDIF_IN_SYNC 232 +#define TEGRA124_CLK_I2S0_SYNC 233 +#define TEGRA124_CLK_I2S1_SYNC 234 +#define TEGRA124_CLK_I2S2_SYNC 235 +#define TEGRA124_CLK_I2S3_SYNC 236 +#define TEGRA124_CLK_I2S4_SYNC 237 +#define TEGRA124_CLK_VIMCLK_SYNC 238 +#define TEGRA124_CLK_AUDIO0 239 +#define TEGRA124_CLK_AUDIO1 240 +#define TEGRA124_CLK_AUDIO2 241 +#define TEGRA124_CLK_AUDIO3 242 +#define TEGRA124_CLK_AUDIO4 243 +#define TEGRA124_CLK_SPDIF 244 +#define TEGRA124_CLK_CLK_OUT_1 245 +#define TEGRA124_CLK_CLK_OUT_2 246 +#define TEGRA124_CLK_CLK_OUT_3 247 +#define TEGRA124_CLK_BLINK 248 +/* 249 */ +/* 250 */ +/* 251 */ +#define TEGRA124_CLK_XUSB_HOST_SRC 252 +#define TEGRA124_CLK_XUSB_FALCON_SRC 253 +#define TEGRA124_CLK_XUSB_FS_SRC 254 +#define TEGRA124_CLK_XUSB_SS_SRC 255 + +#define TEGRA124_CLK_XUSB_DEV_SRC 256 +#define TEGRA124_CLK_XUSB_DEV 257 +#define TEGRA124_CLK_XUSB_HS_SRC 258 +#define TEGRA124_CLK_SCLK 259 +#define TEGRA124_CLK_HCLK 260 +#define TEGRA124_CLK_PCLK 261 +#define TEGRA124_CLK_CCLK_G 262 +#define TEGRA124_CLK_CCLK_LP 263 +#define TEGRA124_CLK_DFLL_REF 264 +#define TEGRA124_CLK_DFLL_SOC 265 +#define TEGRA124_CLK_VI_SENSOR2 266 +#define TEGRA124_CLK_PLL_P_OUT5 267 +#define TEGRA124_CLK_CML0 268 +#define TEGRA124_CLK_CML1 269 +#define TEGRA124_CLK_PLL_C4 270 +#define TEGRA124_CLK_PLL_DP 271 +#define TEGRA124_CLK_PLL_E_MUX 272 +/* 273 */ +/* 274 */ +/* 275 */ +/* 276 */ +/* 277 */ +/* 278 */ +/* 279 */ +/* 280 */ +/* 281 */ +/* 282 */ +/* 283 */ +/* 284 */ +/* 285 */ +/* 286 */ +/* 287 */ + +/* 288 */ +/* 289 */ +/* 290 */ +/* 291 */ +/* 292 */ +/* 293 */ +/* 294 */ +/* 295 */ +/* 296 */ +/* 297 */ +/* 298 */ +/* 299 */ +#define TEGRA124_CLK_AUDIO0_MUX 300 +#define TEGRA124_CLK_AUDIO1_MUX 301 +#define TEGRA124_CLK_AUDIO2_MUX 302 +#define TEGRA124_CLK_AUDIO3_MUX 303 +#define TEGRA124_CLK_AUDIO4_MUX 304 +#define TEGRA124_CLK_SPDIF_MUX 305 +#define TEGRA124_CLK_CLK_OUT_1_MUX 306 +#define TEGRA124_CLK_CLK_OUT_2_MUX 307 +#define TEGRA124_CLK_CLK_OUT_3_MUX 308 +#define TEGRA124_CLK_DSIA_MUX 309 +#define TEGRA124_CLK_DSIB_MUX 310 +#define TEGRA124_CLK_SOR0_LVDS 311 +#define TEGRA124_CLK_PLL_M_UD 311 +#define TEGRA124_CLK_CLK_MAX 312 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h new file mode 100644 index 00000000000..9406207cfac --- /dev/null +++ b/include/dt-bindings/clock/tegra20-car.h @@ -0,0 +1,158 @@ +/* + * This header provides constants for binding nvidia,tegra20-car. + * + * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 95 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 96 and + * above. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H + +#define TEGRA20_CLK_CPU 0 +/* 1 */ +/* 2 */ +#define TEGRA20_CLK_AC97 3 +#define TEGRA20_CLK_RTC 4 +#define TEGRA20_CLK_TIMER 5 +#define TEGRA20_CLK_UARTA 6 +/* 7 (register bit affects uart2 and vfir) */ +#define TEGRA20_CLK_GPIO 8 +#define TEGRA20_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA20_CLK_I2S1 11 +#define TEGRA20_CLK_I2C1 12 +#define TEGRA20_CLK_NDFLASH 13 +#define TEGRA20_CLK_SDMMC1 14 +#define TEGRA20_CLK_SDMMC4 15 +#define TEGRA20_CLK_TWC 16 +#define TEGRA20_CLK_PWM 17 +#define TEGRA20_CLK_I2S2 18 +#define TEGRA20_CLK_EPP 19 +/* 20 (register bit affects vi and vi_sensor) */ +#define TEGRA20_CLK_GR2D 21 +#define TEGRA20_CLK_USBD 22 +#define TEGRA20_CLK_ISP 23 +#define TEGRA20_CLK_GR3D 24 +#define TEGRA20_CLK_IDE 25 +#define TEGRA20_CLK_DISP2 26 +#define TEGRA20_CLK_DISP1 27 +#define TEGRA20_CLK_HOST1X 28 +#define TEGRA20_CLK_VCP 29 +/* 30 */ +#define TEGRA20_CLK_CACHE2 31 + +#define TEGRA20_CLK_MEM 32 +#define TEGRA20_CLK_AHBDMA 33 +#define TEGRA20_CLK_APBDMA 34 +/* 35 */ +#define TEGRA20_CLK_KBC 36 +#define TEGRA20_CLK_STAT_MON 37 +#define TEGRA20_CLK_PMC 38 +#define TEGRA20_CLK_FUSE 39 +#define TEGRA20_CLK_KFUSE 40 +#define TEGRA20_CLK_SBC1 41 +#define TEGRA20_CLK_NOR 42 +#define TEGRA20_CLK_SPI 43 +#define TEGRA20_CLK_SBC2 44 +#define TEGRA20_CLK_XIO 45 +#define TEGRA20_CLK_SBC3 46 +#define TEGRA20_CLK_DVC 47 +#define TEGRA20_CLK_DSI 48 +/* 49 (register bit affects tvo and cve) */ +#define TEGRA20_CLK_MIPI 50 +#define TEGRA20_CLK_HDMI 51 +#define TEGRA20_CLK_CSI 52 +#define TEGRA20_CLK_TVDAC 53 +#define TEGRA20_CLK_I2C2 54 +#define TEGRA20_CLK_UARTC 55 +/* 56 */ +#define TEGRA20_CLK_EMC 57 +#define TEGRA20_CLK_USB2 58 +#define TEGRA20_CLK_USB3 59 +#define TEGRA20_CLK_MPE 60 +#define TEGRA20_CLK_VDE 61 +#define TEGRA20_CLK_BSEA 62 +#define TEGRA20_CLK_BSEV 63 + +#define TEGRA20_CLK_SPEEDO 64 +#define TEGRA20_CLK_UARTD 65 +#define TEGRA20_CLK_UARTE 66 +#define TEGRA20_CLK_I2C3 67 +#define TEGRA20_CLK_SBC4 68 +#define TEGRA20_CLK_SDMMC3 69 +#define TEGRA20_CLK_PEX 70 +#define TEGRA20_CLK_OWR 71 +#define TEGRA20_CLK_AFI 72 +#define TEGRA20_CLK_CSITE 73 +/* 74 */ +#define TEGRA20_CLK_AVPUCQ 75 +#define TEGRA20_CLK_LA 76 +/* 77 */ +/* 78 */ +/* 79 */ +/* 80 */ +/* 81 */ +/* 82 */ +/* 83 */ +#define TEGRA20_CLK_IRAMA 84 +#define TEGRA20_CLK_IRAMB 85 +#define TEGRA20_CLK_IRAMC 86 +#define TEGRA20_CLK_IRAMD 87 +#define TEGRA20_CLK_CRAM2 88 +#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */ +#define TEGRA20_CLK_CLK_D 90 +/* 91 */ +#define TEGRA20_CLK_CSUS 92 +#define TEGRA20_CLK_CDEV2 93 +#define TEGRA20_CLK_CDEV1 94 +/* 95 */ + +#define TEGRA20_CLK_UARTB 96 +#define TEGRA20_CLK_VFIR 97 +#define TEGRA20_CLK_SPDIF_IN 98 +#define TEGRA20_CLK_SPDIF_OUT 99 +#define TEGRA20_CLK_VI 100 +#define TEGRA20_CLK_VI_SENSOR 101 +#define TEGRA20_CLK_TVO 102 +#define TEGRA20_CLK_CVE 103 +#define TEGRA20_CLK_OSC 104 +#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */ +#define TEGRA20_CLK_CLK_M 106 +#define TEGRA20_CLK_SCLK 107 +#define TEGRA20_CLK_CCLK 108 +#define TEGRA20_CLK_HCLK 109 +#define TEGRA20_CLK_PCLK 110 +#define TEGRA20_CLK_BLINK 111 +#define TEGRA20_CLK_PLL_A 112 +#define TEGRA20_CLK_PLL_A_OUT0 113 +#define TEGRA20_CLK_PLL_C 114 +#define TEGRA20_CLK_PLL_C_OUT1 115 +#define TEGRA20_CLK_PLL_D 116 +#define TEGRA20_CLK_PLL_D_OUT0 117 +#define TEGRA20_CLK_PLL_E 118 +#define TEGRA20_CLK_PLL_M 119 +#define TEGRA20_CLK_PLL_M_OUT1 120 +#define TEGRA20_CLK_PLL_P 121 +#define TEGRA20_CLK_PLL_P_OUT1 122 +#define TEGRA20_CLK_PLL_P_OUT2 123 +#define TEGRA20_CLK_PLL_P_OUT3 124 +#define TEGRA20_CLK_PLL_P_OUT4 125 +#define TEGRA20_CLK_PLL_S 126 +#define TEGRA20_CLK_PLL_U 127 + +#define TEGRA20_CLK_PLL_X 128 +#define TEGRA20_CLK_COP 129 /* a/k/a avp */ +#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */ +#define TEGRA20_CLK_PLL_REF 131 +#define TEGRA20_CLK_TWD 132 +#define TEGRA20_CLK_CLK_MAX 133 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */ diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h new file mode 100644 index 00000000000..889e49ba0aa --- /dev/null +++ b/include/dt-bindings/clock/tegra30-car.h @@ -0,0 +1,273 @@ +/* + * This header provides constants for binding nvidia,tegra30-car. + * + * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB + * registers. These IDs often match those in the CAR's RST_DEVICES registers, + * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In + * this case, those clocks are assigned IDs above 160 in order to highlight + * this issue. Implementations that interpret these clock IDs as bit values + * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to + * explicitly handle these special cases. + * + * The balance of the clocks controlled by the CAR are assigned IDs of 160 and + * above. + */ + +#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H +#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H + +#define TEGRA30_CLK_CPU 0 +/* 1 */ +/* 2 */ +/* 3 */ +#define TEGRA30_CLK_RTC 4 +#define TEGRA30_CLK_TIMER 5 +#define TEGRA30_CLK_UARTA 6 +/* 7 (register bit affects uartb and vfir) */ +#define TEGRA30_CLK_GPIO 8 +#define TEGRA30_CLK_SDMMC2 9 +/* 10 (register bit affects spdif_in and spdif_out) */ +#define TEGRA30_CLK_I2S1 11 +#define TEGRA30_CLK_I2C1 12 +#define TEGRA30_CLK_NDFLASH 13 +#define TEGRA30_CLK_SDMMC1 14 +#define TEGRA30_CLK_SDMMC4 15 +/* 16 */ +#define TEGRA30_CLK_PWM 17 +#define TEGRA30_CLK_I2S2 18 +#define TEGRA30_CLK_EPP 19 +/* 20 (register bit affects vi and vi_sensor) */ +#define TEGRA30_CLK_GR2D 21 +#define TEGRA30_CLK_USBD 22 +#define TEGRA30_CLK_ISP 23 +#define TEGRA30_CLK_GR3D 24 +/* 25 */ +#define TEGRA30_CLK_DISP2 26 +#define TEGRA30_CLK_DISP1 27 +#define TEGRA30_CLK_HOST1X 28 +#define TEGRA30_CLK_VCP 29 +#define TEGRA30_CLK_I2S0 30 +#define TEGRA30_CLK_COP_CACHE 31 + +#define TEGRA30_CLK_MC 32 +#define TEGRA30_CLK_AHBDMA 33 +#define TEGRA30_CLK_APBDMA 34 +/* 35 */ +#define TEGRA30_CLK_KBC 36 +#define TEGRA30_CLK_STATMON 37 +#define TEGRA30_CLK_PMC 38 +/* 39 (register bit affects fuse and fuse_burn) */ +#define TEGRA30_CLK_KFUSE 40 +#define TEGRA30_CLK_SBC1 41 +#define TEGRA30_CLK_NOR 42 +/* 43 */ +#define TEGRA30_CLK_SBC2 44 +/* 45 */ +#define TEGRA30_CLK_SBC3 46 +#define TEGRA30_CLK_I2C5 47 +#define TEGRA30_CLK_DSIA 48 +/* 49 (register bit affects cve and tvo) */ +#define TEGRA30_CLK_MIPI 50 +#define TEGRA30_CLK_HDMI 51 +#define TEGRA30_CLK_CSI 52 +#define TEGRA30_CLK_TVDAC 53 +#define TEGRA30_CLK_I2C2 54 +#define TEGRA30_CLK_UARTC 55 +/* 56 */ +#define TEGRA30_CLK_EMC 57 +#define TEGRA30_CLK_USB2 58 +#define TEGRA30_CLK_USB3 59 +#define TEGRA30_CLK_MPE 60 +#define TEGRA30_CLK_VDE 61 +#define TEGRA30_CLK_BSEA 62 +#define TEGRA30_CLK_BSEV 63 + +#define TEGRA30_CLK_SPEEDO 64 +#define TEGRA30_CLK_UARTD 65 +#define TEGRA30_CLK_UARTE 66 +#define TEGRA30_CLK_I2C3 67 +#define TEGRA30_CLK_SBC4 68 +#define TEGRA30_CLK_SDMMC3 69 +#define TEGRA30_CLK_PCIE 70 +#define TEGRA30_CLK_OWR 71 +#define TEGRA30_CLK_AFI 72 +#define TEGRA30_CLK_CSITE 73 +/* 74 */ +#define TEGRA30_CLK_AVPUCQ 75 +#define TEGRA30_CLK_LA 76 +/* 77 */ +/* 78 */ +#define TEGRA30_CLK_DTV 79 +#define TEGRA30_CLK_NDSPEED 80 +#define TEGRA30_CLK_I2CSLOW 81 +#define TEGRA30_CLK_DSIB 82 +/* 83 */ +#define TEGRA30_CLK_IRAMA 84 +#define TEGRA30_CLK_IRAMB 85 +#define TEGRA30_CLK_IRAMC 86 +#define TEGRA30_CLK_IRAMD 87 +#define TEGRA30_CLK_CRAM2 88 +/* 89 */ +#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ +/* 91 */ +#define TEGRA30_CLK_CSUS 92 +#define TEGRA30_CLK_CDEV2 93 +#define TEGRA30_CLK_CDEV1 94 +/* 95 */ + +#define TEGRA30_CLK_CPU_G 96 +#define TEGRA30_CLK_CPU_LP 97 +#define TEGRA30_CLK_GR3D2 98 +#define TEGRA30_CLK_MSELECT 99 +#define TEGRA30_CLK_TSENSOR 100 +#define TEGRA30_CLK_I2S3 101 +#define TEGRA30_CLK_I2S4 102 +#define TEGRA30_CLK_I2C4 103 +#define TEGRA30_CLK_SBC5 104 +#define TEGRA30_CLK_SBC6 105 +#define TEGRA30_CLK_D_AUDIO 106 +#define TEGRA30_CLK_APBIF 107 +#define TEGRA30_CLK_DAM0 108 +#define TEGRA30_CLK_DAM1 109 +#define TEGRA30_CLK_DAM2 110 +#define TEGRA30_CLK_HDA2CODEC_2X 111 +#define TEGRA30_CLK_ATOMICS 112 +#define TEGRA30_CLK_AUDIO0_2X 113 +#define TEGRA30_CLK_AUDIO1_2X 114 +#define TEGRA30_CLK_AUDIO2_2X 115 +#define TEGRA30_CLK_AUDIO3_2X 116 +#define TEGRA30_CLK_AUDIO4_2X 117 +#define TEGRA30_CLK_SPDIF_2X 118 +#define TEGRA30_CLK_ACTMON 119 +#define TEGRA30_CLK_EXTERN1 120 +#define TEGRA30_CLK_EXTERN2 121 +#define TEGRA30_CLK_EXTERN3 122 +#define TEGRA30_CLK_SATA_OOB 123 +#define TEGRA30_CLK_SATA 124 +#define TEGRA30_CLK_HDA 125 +/* 126 */ +#define TEGRA30_CLK_SE 127 + +#define TEGRA30_CLK_HDA2HDMI 128 +#define TEGRA30_CLK_SATA_COLD 129 +/* 130 */ +/* 131 */ +/* 132 */ +/* 133 */ +/* 134 */ +/* 135 */ +/* 136 */ +/* 137 */ +/* 138 */ +/* 139 */ +/* 140 */ +/* 141 */ +/* 142 */ +/* 143 */ +/* 144 */ +/* 145 */ +/* 146 */ +/* 147 */ +/* 148 */ +/* 149 */ +/* 150 */ +/* 151 */ +/* 152 */ +/* 153 */ +/* 154 */ +/* 155 */ +/* 156 */ +/* 157 */ +/* 158 */ +/* 159 */ + +#define TEGRA30_CLK_UARTB 160 +#define TEGRA30_CLK_VFIR 161 +#define TEGRA30_CLK_SPDIF_IN 162 +#define TEGRA30_CLK_SPDIF_OUT 163 +#define TEGRA30_CLK_VI 164 +#define TEGRA30_CLK_VI_SENSOR 165 +#define TEGRA30_CLK_FUSE 166 +#define TEGRA30_CLK_FUSE_BURN 167 +#define TEGRA30_CLK_CVE 168 +#define TEGRA30_CLK_TVO 169 +#define TEGRA30_CLK_CLK_32K 170 +#define TEGRA30_CLK_CLK_M 171 +#define TEGRA30_CLK_CLK_M_DIV2 172 +#define TEGRA30_CLK_CLK_M_DIV4 173 +#define TEGRA30_CLK_PLL_REF 174 +#define TEGRA30_CLK_PLL_C 175 +#define TEGRA30_CLK_PLL_C_OUT1 176 +#define TEGRA30_CLK_PLL_M 177 +#define TEGRA30_CLK_PLL_M_OUT1 178 +#define TEGRA30_CLK_PLL_P 179 +#define TEGRA30_CLK_PLL_P_OUT1 180 +#define TEGRA30_CLK_PLL_P_OUT2 181 +#define TEGRA30_CLK_PLL_P_OUT3 182 +#define TEGRA30_CLK_PLL_P_OUT4 183 +#define TEGRA30_CLK_PLL_A 184 +#define TEGRA30_CLK_PLL_A_OUT0 185 +#define TEGRA30_CLK_PLL_D 186 +#define TEGRA30_CLK_PLL_D_OUT0 187 +#define TEGRA30_CLK_PLL_D2 188 +#define TEGRA30_CLK_PLL_D2_OUT0 189 +#define TEGRA30_CLK_PLL_U 190 +#define TEGRA30_CLK_PLL_X 191 + +#define TEGRA30_CLK_PLL_X_OUT0 192 +#define TEGRA30_CLK_PLL_E 193 +#define TEGRA30_CLK_SPDIF_IN_SYNC 194 +#define TEGRA30_CLK_I2S0_SYNC 195 +#define TEGRA30_CLK_I2S1_SYNC 196 +#define TEGRA30_CLK_I2S2_SYNC 197 +#define TEGRA30_CLK_I2S3_SYNC 198 +#define TEGRA30_CLK_I2S4_SYNC 199 +#define TEGRA30_CLK_VIMCLK_SYNC 200 +#define TEGRA30_CLK_AUDIO0 201 +#define TEGRA30_CLK_AUDIO1 202 +#define TEGRA30_CLK_AUDIO2 203 +#define TEGRA30_CLK_AUDIO3 204 +#define TEGRA30_CLK_AUDIO4 205 +#define TEGRA30_CLK_SPDIF 206 +#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ +#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ +#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ +#define TEGRA30_CLK_SCLK 210 +#define TEGRA30_CLK_BLINK 211 +#define TEGRA30_CLK_CCLK_G 212 +#define TEGRA30_CLK_CCLK_LP 213 +#define TEGRA30_CLK_TWD 214 +#define TEGRA30_CLK_CML0 215 +#define TEGRA30_CLK_CML1 216 +#define TEGRA30_CLK_HCLK 217 +#define TEGRA30_CLK_PCLK 218 +/* 219 */ +/* 220 */ +/* 221 */ +/* 222 */ +/* 223 */ + +/* 288 */ +/* 289 */ +/* 290 */ +/* 291 */ +/* 292 */ +/* 293 */ +/* 294 */ +/* 295 */ +/* 296 */ +/* 297 */ +/* 298 */ +/* 299 */ +#define TEGRA30_CLK_CLK_OUT_1_MUX 300 +#define TEGRA30_CLK_CLK_OUT_2_MUX 301 +#define TEGRA30_CLK_CLK_OUT_3_MUX 302 +#define TEGRA30_CLK_AUDIO0_MUX 303 +#define TEGRA30_CLK_AUDIO1_MUX 304 +#define TEGRA30_CLK_AUDIO2_MUX 305 +#define TEGRA30_CLK_AUDIO3_MUX 306 +#define TEGRA30_CLK_AUDIO4_MUX 307 +#define TEGRA30_CLK_SPDIF_MUX 308 +#define TEGRA30_CLK_CLK_MAX 309 + +#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ -- cgit v1.3.1 From 858530a8c0a7ce7e573e513934804a00d6676813 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 4 Sep 2014 16:27:36 -0600 Subject: dm: tegra: Enable driver model for serial Use driver model for serial ports. Since Tegra now uses driver model for serial, adjust the definition of V_NS16550_CLK so that it is clear that this is only used for SPL. Signed-off-by: Simon Glass --- drivers/serial/Makefile | 1 + drivers/serial/serial_tegra.c | 38 ++++++++++++++++++++++++++++++++++++++ include/configs/tegra-common.h | 9 ++++++++- 3 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 drivers/serial/serial_tegra.c (limited to 'include') diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 5ae6416a4f9..853a8c69197 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o obj-$(CONFIG_MXS_AUART) += mxs_auart.o obj-$(CONFIG_ARC_SERIAL) += serial_arc.o +obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_tegra.c b/drivers/serial/serial_tegra.c new file mode 100644 index 00000000000..7eb70e1de13 --- /dev/null +++ b/drivers/serial/serial_tegra.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +static const struct udevice_id tegra_serial_ids[] = { + { .compatible = "nvidia,tegra20-uart" }, + { } +}; + +static int tegra_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct ns16550_platdata *plat = dev_get_platdata(dev); + int ret; + + ret = ns16550_serial_ofdata_to_platdata(dev); + if (ret) + return ret; + plat->clock = V_NS16550_CLK; + + return 0; +} +U_BOOT_DRIVER(serial_ns16550) = { + .name = "serial_tegra20", + .id = UCLASS_SERIAL, + .of_match = tegra_serial_ids, + .ofdata_to_platdata = tegra_serial_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata), + .priv_auto_alloc_size = sizeof(struct NS16550), + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, +}; diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index f1187f165ee..834b3d5686c 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -21,6 +21,9 @@ #define CONFIG_DM #define CONFIG_CMD_DM #define CONFIG_DM_GPIO +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM_SERIAL +#endif #define CONFIG_SYS_TIMER_RATE 1000000 #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE @@ -46,10 +49,14 @@ /* * NS16550 Configuration */ -#define CONFIG_SYS_NS16550 +#ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#else +#define CONFIG_TEGRA_SERIAL +#endif +#define CONFIG_SYS_NS16550 /* * Common HW configuration. -- cgit v1.3.1 From 3b6129702489ef4e327adeeef79ad73da8f6b59d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Sun, 31 Aug 2014 15:16:53 +0900 Subject: kbuild: force to define __UBOOT__ in all the C sources U-Boot has imported various source files from other projects, mostly Linux. Something like #ifdef __UBOOT__ [ modification for U-Boot ] #else [ original code ] #endif is an often used strategy for clarification of adjusted parts, that is, easier re-sync in future. Instead of defining __UBOOT__ in each source file, passing it from the top Makefile would be easier. Signed-off-by: Masahiro Yamada Acked-by: Marek Vasut Acked-by: Heiko Schocher --- Makefile | 2 +- drivers/mtd/mtdconcat.c | 1 - drivers/mtd/mtdcore.c | 1 - drivers/mtd/mtdpart.c | 1 - drivers/mtd/nand/nand_base.c | 1 - drivers/mtd/nand/nand_bbt.c | 1 - drivers/mtd/nand/nand_ids.c | 1 - drivers/mtd/ubi/attach.c | 1 - drivers/mtd/ubi/build.c | 1 - drivers/mtd/ubi/crc32.c | 1 - drivers/mtd/ubi/debug.c | 1 - drivers/mtd/ubi/debug.h | 1 - drivers/mtd/ubi/eba.c | 1 - drivers/mtd/ubi/fastmap.c | 1 - drivers/mtd/ubi/io.c | 1 - drivers/mtd/ubi/kapi.c | 1 - drivers/mtd/ubi/ubi.h | 1 - drivers/mtd/ubi/upd.c | 1 - drivers/mtd/ubi/vmt.c | 1 - drivers/mtd/ubi/vtbl.c | 1 - drivers/mtd/ubi/wl.c | 1 - drivers/usb/musb-new/am35x.c | 1 - drivers/usb/musb-new/musb_core.c | 1 - drivers/usb/musb-new/musb_dsps.c | 1 - drivers/usb/musb-new/musb_gadget.c | 1 - drivers/usb/musb-new/musb_gadget_ep0.c | 1 - drivers/usb/musb-new/musb_host.c | 1 - drivers/usb/musb-new/musb_uboot.c | 1 - drivers/usb/musb-new/omap2430.c | 1 - fs/ubifs/budget.c | 1 - fs/ubifs/debug.c | 1 - fs/ubifs/debug.h | 1 - fs/ubifs/io.c | 1 - fs/ubifs/log.c | 1 - fs/ubifs/lprops.c | 1 - fs/ubifs/lpt.c | 1 - fs/ubifs/lpt_commit.c | 1 - fs/ubifs/master.c | 1 - fs/ubifs/misc.h | 1 - fs/ubifs/recovery.c | 1 - fs/ubifs/replay.c | 1 - fs/ubifs/sb.c | 1 - fs/ubifs/scan.c | 1 - fs/ubifs/super.c | 1 - fs/ubifs/tnc.c | 1 - fs/ubifs/tnc_misc.c | 1 - fs/ubifs/ubifs.c | 1 - fs/ubifs/ubifs.h | 1 - include/linux/mtd/flashchip.h | 1 - include/linux/mtd/mtd.h | 1 - include/linux/mtd/nand.h | 1 - include/linux/mtd/ubi.h | 1 - include/linux/rbtree.h | 1 - include/mtd/mtd-abi.h | 1 - lib/list_sort.c | 1 - lib/rbtree.c | 1 - 56 files changed, 1 insertion(+), 56 deletions(-) (limited to 'include') diff --git a/Makefile b/Makefile index 42263e4de28..62b202fb11e 100644 --- a/Makefile +++ b/Makefile @@ -341,7 +341,7 @@ CHECK = sparse CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF) -KBUILD_CPPFLAGS := -D__KERNEL__ +KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__ KBUILD_CFLAGS := -Wall -Wstrict-prototypes \ -Wno-format-security \ diff --git a/drivers/mtd/mtdconcat.c b/drivers/mtd/mtdconcat.c index 39daeabd9f1..3e36918f1cd 100644 --- a/drivers/mtd/mtdconcat.c +++ b/drivers/mtd/mtdconcat.c @@ -10,7 +10,6 @@ * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index 6ad03575f64..e0b7e3af72f 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -9,7 +9,6 @@ * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c index 2f20b92a882..cfbaa3d9a0c 100644 --- a/drivers/mtd/mtdpart.c +++ b/drivers/mtd/mtdpart.c @@ -9,7 +9,6 @@ * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 085b1541cda..7153e3ca363 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -29,7 +29,6 @@ * */ -#define __UBOOT__ #ifndef __UBOOT__ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index c8f28c792b2..cf4a82d93a9 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -59,7 +59,6 @@ * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 54f9f138967..9ed05778d37 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -8,7 +8,6 @@ * published by the Free Software Foundation. * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/ubi/attach.c b/drivers/mtd/ubi/attach.c index 9fce02ef267..1bdbfa71d91 100644 --- a/drivers/mtd/ubi/attach.c +++ b/drivers/mtd/ubi/attach.c @@ -70,7 +70,6 @@ * o Otherwise this is corruption type 2. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/ubi/build.c b/drivers/mtd/ubi/build.c index ff8bf0cedfc..584cf5f22b3 100644 --- a/drivers/mtd/ubi/build.c +++ b/drivers/mtd/ubi/build.c @@ -17,7 +17,6 @@ * later using the "UBI control device". */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/ubi/crc32.c b/drivers/mtd/ubi/crc32.c index 0d65bf4b8a5..9c54ea4db0c 100644 --- a/drivers/mtd/ubi/crc32.c +++ b/drivers/mtd/ubi/crc32.c @@ -20,7 +20,6 @@ * Version 2. See the file COPYING for more details. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/ubi/debug.c b/drivers/mtd/ubi/debug.c index af254da4883..6dcc4e4844b 100644 --- a/drivers/mtd/ubi/debug.c +++ b/drivers/mtd/ubi/debug.c @@ -8,7 +8,6 @@ #include #include "ubi.h" -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/ubi/debug.h b/drivers/mtd/ubi/debug.h index 980eb11ed23..bfa9dfb42bd 100644 --- a/drivers/mtd/ubi/debug.h +++ b/drivers/mtd/ubi/debug.h @@ -13,7 +13,6 @@ void ubi_dump_flash(struct ubi_device *ubi, int pnum, int offset, int len); void ubi_dump_ec_hdr(const struct ubi_ec_hdr *ec_hdr); void ubi_dump_vid_hdr(const struct ubi_vid_hdr *vid_hdr); -#define __UBOOT__ #ifndef __UBOOT__ #include #endif diff --git a/drivers/mtd/ubi/eba.c b/drivers/mtd/ubi/eba.c index 3c2a7e69e18..fce0ff8bdf0 100644 --- a/drivers/mtd/ubi/eba.c +++ b/drivers/mtd/ubi/eba.c @@ -29,7 +29,6 @@ * 64 bits is enough to never overflow. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/ubi/fastmap.c b/drivers/mtd/ubi/fastmap.c index 787522fa2eb..a2166e431c2 100644 --- a/drivers/mtd/ubi/fastmap.c +++ b/drivers/mtd/ubi/fastmap.c @@ -6,7 +6,6 @@ * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #else diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c index 41d7eb76388..0e2e9335fe5 100644 --- a/drivers/mtd/ubi/io.c +++ b/drivers/mtd/ubi/io.c @@ -73,7 +73,6 @@ * back and writes the whole sub-page. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/ubi/kapi.c b/drivers/mtd/ubi/kapi.c index 0183c93b0b0..fd2bbd64f13 100644 --- a/drivers/mtd/ubi/kapi.c +++ b/drivers/mtd/ubi/kapi.c @@ -8,7 +8,6 @@ /* This file mostly implements UBI kernel API functions */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h index 20fd704ecaf..754b3371d25 100644 --- a/drivers/mtd/ubi/ubi.h +++ b/drivers/mtd/ubi/ubi.h @@ -10,7 +10,6 @@ #ifndef __UBI_UBI_H__ #define __UBI_UBI_H__ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/ubi/upd.c b/drivers/mtd/ubi/upd.c index 220c120515a..c52c9ce776a 100644 --- a/drivers/mtd/ubi/upd.c +++ b/drivers/mtd/ubi/upd.c @@ -26,7 +26,6 @@ * transaction with a roll-back capability. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #else diff --git a/drivers/mtd/ubi/vmt.c b/drivers/mtd/ubi/vmt.c index d9665a446a3..f4392f59692 100644 --- a/drivers/mtd/ubi/vmt.c +++ b/drivers/mtd/ubi/vmt.c @@ -11,7 +11,6 @@ * resizing. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/ubi/vtbl.c b/drivers/mtd/ubi/vtbl.c index e6c8f5bbe0e..ae8ea38c625 100644 --- a/drivers/mtd/ubi/vtbl.c +++ b/drivers/mtd/ubi/vtbl.c @@ -43,7 +43,6 @@ * damaged. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c index 102309016ac..6886f89df25 100644 --- a/drivers/mtd/ubi/wl.c +++ b/drivers/mtd/ubi/wl.c @@ -86,7 +86,6 @@ * room for future re-works of the WL sub-system. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/usb/musb-new/am35x.c b/drivers/usb/musb-new/am35x.c index 57c9bd393b8..857d7eb0cce 100644 --- a/drivers/usb/musb-new/am35x.c +++ b/drivers/usb/musb-new/am35x.c @@ -26,7 +26,6 @@ * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/usb/musb-new/musb_core.c b/drivers/usb/musb-new/musb_core.c index 36681b6fc87..4edd6d729d1 100644 --- a/drivers/usb/musb-new/musb_core.c +++ b/drivers/usb/musb-new/musb_core.c @@ -89,7 +89,6 @@ * Most of the conditional compilation will (someday) vanish. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/usb/musb-new/musb_dsps.c b/drivers/usb/musb-new/musb_dsps.c index 9a03917e87d..17ed224488f 100644 --- a/drivers/usb/musb-new/musb_dsps.c +++ b/drivers/usb/musb-new/musb_dsps.c @@ -29,7 +29,6 @@ * da8xx.c would be merged to this file after testing. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/usb/musb-new/musb_gadget.c b/drivers/usb/musb-new/musb_gadget.c index d2cb91a898f..97acf93d316 100644 --- a/drivers/usb/musb-new/musb_gadget.c +++ b/drivers/usb/musb-new/musb_gadget.c @@ -33,7 +33,6 @@ * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/usb/musb-new/musb_gadget_ep0.c b/drivers/usb/musb-new/musb_gadget_ep0.c index 8c3b0a145a4..5a715013a23 100644 --- a/drivers/usb/musb-new/musb_gadget_ep0.c +++ b/drivers/usb/musb-new/musb_gadget_ep0.c @@ -33,7 +33,6 @@ * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/usb/musb-new/musb_host.c b/drivers/usb/musb-new/musb_host.c index 9a2cf59d924..bbcee88241b 100644 --- a/drivers/usb/musb-new/musb_host.c +++ b/drivers/usb/musb-new/musb_host.c @@ -33,7 +33,6 @@ * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/drivers/usb/musb-new/musb_uboot.c b/drivers/usb/musb-new/musb_uboot.c index 0d7b89fcf6e..2676f09c384 100644 --- a/drivers/usb/musb-new/musb_uboot.c +++ b/drivers/usb/musb-new/musb_uboot.c @@ -4,7 +4,6 @@ #include #include -#define __UBOOT__ #include #include "linux-compat.h" #include "usb-compat.h" diff --git a/drivers/usb/musb-new/omap2430.c b/drivers/usb/musb-new/omap2430.c index b1c4dc78285..98f4830912b 100644 --- a/drivers/usb/musb-new/omap2430.c +++ b/drivers/usb/musb-new/omap2430.c @@ -24,7 +24,6 @@ * Suite 330, Boston, MA 02111-1307 USA * */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/fs/ubifs/budget.c b/fs/ubifs/budget.c index 9ed40177cb9..c626cbf4843 100644 --- a/fs/ubifs/budget.c +++ b/fs/ubifs/budget.c @@ -20,7 +20,6 @@ */ #include "ubifs.h" -#define __UBOOT__ #ifndef __UBOOT__ #include #else diff --git a/fs/ubifs/debug.c b/fs/ubifs/debug.c index 2f50a554bbe..6e6f018b2f5 100644 --- a/fs/ubifs/debug.c +++ b/fs/ubifs/debug.c @@ -16,7 +16,6 @@ * various local functions of those subsystems. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/fs/ubifs/debug.h b/fs/ubifs/debug.h index 6d325af8bcc..807ce1b7338 100644 --- a/fs/ubifs/debug.h +++ b/fs/ubifs/debug.h @@ -12,7 +12,6 @@ #ifndef __UBIFS_DEBUG_H__ #define __UBIFS_DEBUG_H__ -#define __UBOOT__ /* Checking helper functions */ typedef int (*dbg_leaf_callback)(struct ubifs_info *c, struct ubifs_zbranch *zbr, void *priv); diff --git a/fs/ubifs/io.c b/fs/ubifs/io.c index f87341e1087..bdccdc45e11 100644 --- a/fs/ubifs/io.c +++ b/fs/ubifs/io.c @@ -59,7 +59,6 @@ * they are read from the flash media. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/fs/ubifs/log.c b/fs/ubifs/log.c index ced04240c54..0355fe2b048 100644 --- a/fs/ubifs/log.c +++ b/fs/ubifs/log.c @@ -16,7 +16,6 @@ * journal. */ -#define __UBOOT__ #ifdef __UBOOT__ #include #endif diff --git a/fs/ubifs/lprops.c b/fs/ubifs/lprops.c index fc6686bb08b..a1a814f7797 100644 --- a/fs/ubifs/lprops.c +++ b/fs/ubifs/lprops.c @@ -17,7 +17,6 @@ * an empty LEB for the journal, or a very dirty LEB for garbage collection. */ -#define __UBOOT__ #ifdef __UBOOT__ #include #endif diff --git a/fs/ubifs/lpt.c b/fs/ubifs/lpt.c index c49d3b0687f..8489e90e4a3 100644 --- a/fs/ubifs/lpt.c +++ b/fs/ubifs/lpt.c @@ -33,7 +33,6 @@ */ #include "ubifs.h" -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/fs/ubifs/lpt_commit.c b/fs/ubifs/lpt_commit.c index cad422e0662..c818d4ca5af 100644 --- a/fs/ubifs/lpt_commit.c +++ b/fs/ubifs/lpt_commit.c @@ -14,7 +14,6 @@ * subsystem. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/fs/ubifs/master.c b/fs/ubifs/master.c index 00ca855e818..761e0704e4a 100644 --- a/fs/ubifs/master.c +++ b/fs/ubifs/master.c @@ -11,7 +11,6 @@ /* This file implements reading and writing the master node */ -#define __UBOOT__ #include "ubifs.h" #ifdef __UBOOT__ #include diff --git a/fs/ubifs/misc.h b/fs/ubifs/misc.h index 4316d3c8ae2..7cad2bed1b2 100644 --- a/fs/ubifs/misc.h +++ b/fs/ubifs/misc.h @@ -16,7 +16,6 @@ #ifndef __UBIFS_MISC_H__ #define __UBIFS_MISC_H__ -#define __UBOOT__ /** * ubifs_zn_dirty - check if znode is dirty. * @znode: znode to check diff --git a/fs/ubifs/recovery.c b/fs/ubifs/recovery.c index f54a440cd51..763770738b7 100644 --- a/fs/ubifs/recovery.c +++ b/fs/ubifs/recovery.c @@ -36,7 +36,6 @@ * refuses to mount. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/fs/ubifs/replay.c b/fs/ubifs/replay.c index 6393b15b185..7268b37a49c 100644 --- a/fs/ubifs/replay.c +++ b/fs/ubifs/replay.c @@ -21,7 +21,6 @@ * larger is the journal, the more memory its index may consume. */ -#define __UBOOT__ #ifdef __UBOOT__ #include #include diff --git a/fs/ubifs/sb.c b/fs/ubifs/sb.c index fc0194aa267..4983bf62897 100644 --- a/fs/ubifs/sb.c +++ b/fs/ubifs/sb.c @@ -16,7 +16,6 @@ */ #include "ubifs.h" -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/fs/ubifs/scan.c b/fs/ubifs/scan.c index 5523d4e6608..6fc464bb485 100644 --- a/fs/ubifs/scan.c +++ b/fs/ubifs/scan.c @@ -16,7 +16,6 @@ * debugging functions. */ -#define __UBOOT__ #ifdef __UBOOT__ #include #endif diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index dd9b668ee76..01d449a7afa 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -15,7 +15,6 @@ * corresponding subsystems, but most of it is here. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/fs/ubifs/tnc.c b/fs/ubifs/tnc.c index eda50705574..95cae548bf2 100644 --- a/fs/ubifs/tnc.c +++ b/fs/ubifs/tnc.c @@ -19,7 +19,6 @@ * the mutex locked. */ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/fs/ubifs/tnc_misc.c b/fs/ubifs/tnc_misc.c index 81bdad92034..f808e0bc2fd 100644 --- a/fs/ubifs/tnc_misc.c +++ b/fs/ubifs/tnc_misc.c @@ -16,7 +16,6 @@ * putting it all in one file would make that file too big and unreadable. */ -#define __UBOOT__ #ifdef __UBOOT__ #include #endif diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index b91a6fd26f2..49e6f469ca6 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -26,7 +26,6 @@ #include "ubifs.h" #include -#define __UBOOT__ #include #include diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h index acc6a404dde..0ce2475e0b8 100644 --- a/fs/ubifs/ubifs.h +++ b/fs/ubifs/ubifs.h @@ -15,7 +15,6 @@ #ifndef __UBIFS_H__ #define __UBIFS_H__ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/include/linux/mtd/flashchip.h b/include/linux/mtd/flashchip.h index 7028ee1e77a..e5c7d1cf0d3 100644 --- a/include/linux/mtd/flashchip.h +++ b/include/linux/mtd/flashchip.h @@ -9,7 +9,6 @@ #ifndef __MTD_FLASHCHIP_H__ #define __MTD_FLASHCHIP_H__ -#define __UBOOT__ #ifndef __UBOOT__ /* For spinlocks. sched.h includes spinlock.h from whichever directory it * happens to be in - so we don't have to care whether we're on 2.2, which diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 1526d075c78..86664132759 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -8,7 +8,6 @@ #ifndef __MTD_MTD_H__ #define __MTD_MTD_H__ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 67d2651481b..8438490fe42 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -16,7 +16,6 @@ #ifndef __LINUX_MTD_NAND_H #define __LINUX_MTD_NAND_H -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/include/linux/mtd/ubi.h b/include/linux/mtd/ubi.h index d9e58aedf63..05d0ab54c01 100644 --- a/include/linux/mtd/ubi.h +++ b/include/linux/mtd/ubi.h @@ -10,7 +10,6 @@ #define __LINUX_UBI_H__ #include -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/include/linux/rbtree.h b/include/linux/rbtree.h index b5994e3799d..2cc16a3e7de 100644 --- a/include/linux/rbtree.h +++ b/include/linux/rbtree.h @@ -17,7 +17,6 @@ #ifndef _LINUX_RBTREE_H #define _LINUX_RBTREE_H -#define __UBOOT__ #ifndef __UBOOT__ #include #endif diff --git a/include/mtd/mtd-abi.h b/include/mtd/mtd-abi.h index b9f4bcb154b..0ef582aeec2 100644 --- a/include/mtd/mtd-abi.h +++ b/include/mtd/mtd-abi.h @@ -8,7 +8,6 @@ #ifndef __MTD_ABI_H__ #define __MTD_ABI_H__ -#define __UBOOT__ #ifdef __UBOOT__ #include #endif diff --git a/lib/list_sort.c b/lib/list_sort.c index 81de0a17de8..e841da53ee6 100644 --- a/lib/list_sort.c +++ b/lib/list_sort.c @@ -1,4 +1,3 @@ -#define __UBOOT__ #ifndef __UBOOT__ #include #include diff --git a/lib/rbtree.c b/lib/rbtree.c index 9e52f70d173..5de3bf40263 100644 --- a/lib/rbtree.c +++ b/lib/rbtree.c @@ -9,7 +9,6 @@ linux/lib/rbtree.c */ -#define __UBOOT__ #include #ifndef __UBOOT__ #include -- cgit v1.3.1 From e6ca1ad604419619e2e6ba16a6e43cf15ff07fb1 Mon Sep 17 00:00:00 2001 From: Steve Rae Date: Wed, 3 Sep 2014 10:05:54 -0700 Subject: implement the Android sparse image format update to provide usable implementation to U-Boot Signed-off-by: Steve Rae --- common/aboot.c | 129 +++++++++++++++++++++++++++++--------------------- include/aboot.h | 28 +++++++++++ include/sparse_defs.h | 7 +++ 3 files changed, 111 insertions(+), 53 deletions(-) create mode 100644 include/aboot.h create mode 100644 include/sparse_defs.h (limited to 'include') diff --git a/common/aboot.c b/common/aboot.c index 3611feb1c39..d5c464bd7da 100644 --- a/common/aboot.c +++ b/common/aboot.c @@ -3,6 +3,7 @@ * All rights reserved. * * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved. + * Portions Copyright 2014 Broadcom Corporation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -33,44 +34,32 @@ * to the "BSD-3-Clause", therefore, DO NOT MODIFY THIS LICENSE TEXT! */ -void cmd_flash_mmc_sparse_img(const char *arg, void *data, unsigned sz) +#include +#include +#include +#include +#include +#include + +void write_sparse_image(block_dev_desc_t *dev_desc, + disk_partition_t *info, const char *part_name, + void *data, unsigned sz) { + lbaint_t blk; + lbaint_t blkcnt; + lbaint_t blks; + uint32_t bytes_written = 0; unsigned int chunk; unsigned int chunk_data_sz; uint32_t *fill_buf = NULL; uint32_t fill_val; - uint32_t chunk_blk_cnt = 0; sparse_header_t *sparse_header; chunk_header_t *chunk_header; uint32_t total_blocks = 0; - unsigned long long ptn = 0; - unsigned long long size = 0; - int index = INVALID_PTN; int i; - uint8_t lun = 0; - - index = partition_get_index(arg); - ptn = partition_get_offset(index); - if(ptn == 0) { - fastboot_fail("partition table doesn't exist"); - return; - } - - size = partition_get_size(index); - if (ROUND_TO_PAGE(sz,511) > size) { - fastboot_fail("size too large"); - return; - } - - lun = partition_get_lun(index); - mmc_set_lun(lun); /* Read and skip over sparse image header */ sparse_header = (sparse_header_t *) data; - if ((sparse_header->total_blks * sparse_header->blk_sz) > size) { - fastboot_fail("size too large"); - return; - } data += sparse_header->file_hdr_sz; if (sparse_header->file_hdr_sz > sizeof(sparse_header_t)) @@ -92,17 +81,31 @@ void cmd_flash_mmc_sparse_img(const char *arg, void *data, unsigned sz) debug("total_blks: %d\n", sparse_header->total_blks); debug("total_chunks: %d\n", sparse_header->total_chunks); + /* verify sparse_header->blk_sz is an exact multiple of info->blksz */ + if (sparse_header->blk_sz != + (sparse_header->blk_sz & ~(info->blksz - 1))) { + printf("%s: Sparse image block size issue [%u]\n", + __func__, sparse_header->blk_sz); + fastboot_fail("sparse image block size issue"); + return; + } + + puts("Flashing Sparse Image\n"); + /* Start processing chunks */ + blk = info->start; for (chunk=0; chunktotal_chunks; chunk++) { /* Read and skip over chunk header */ chunk_header = (chunk_header_t *) data; data += sizeof(chunk_header_t); - debug("=== Chunk Header ===\n"); - debug("chunk_type: 0x%x\n", chunk_header->chunk_type); - debug("chunk_data_sz: 0x%x\n", chunk_header->chunk_sz); - debug("total_size: 0x%x\n", chunk_header->total_sz); + if (chunk_header->chunk_type != CHUNK_TYPE_RAW) { + debug("=== Chunk Header ===\n"); + debug("chunk_type: 0x%x\n", chunk_header->chunk_type); + debug("chunk_data_sz: 0x%x\n", chunk_header->chunk_sz); + debug("total_size: 0x%x\n", chunk_header->total_sz); + } if (sparse_header->chunk_hdr_sz > sizeof(chunk_header_t)) { @@ -115,6 +118,7 @@ void cmd_flash_mmc_sparse_img(const char *arg, void *data, unsigned sz) } chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz; + blkcnt = chunk_data_sz / info->blksz; switch (chunk_header->chunk_type) { case CHUNK_TYPE_RAW: @@ -126,14 +130,25 @@ void cmd_flash_mmc_sparse_img(const char *arg, void *data, unsigned sz) return; } - if (mmc_write(ptn + - ((uint64_t)total_blocks * - sparse_header->blk_sz), - chunk_data_sz, (unsigned int *)data)) - { + if (blk + blkcnt > info->start + info->size) { + printf( + "%s: Request would exceed partition size!\n", + __func__); + fastboot_fail( + "Request would exceed partition size!"); + return; + } + + blks = dev_desc->block_write(dev_desc->dev, blk, blkcnt, + data); + if (blks != blkcnt) { + printf("%s: Write failed " LBAFU "\n", + __func__, blks); fastboot_fail("flash write failure"); return; } + blk += blkcnt; + bytes_written += blkcnt * info->blksz; total_blocks += chunk_header->chunk_sz; data += chunk_data_sz; break; @@ -148,9 +163,9 @@ void cmd_flash_mmc_sparse_img(const char *arg, void *data, unsigned sz) } fill_buf = (uint32_t *) - memalign(CACHE_LINE, - ROUNDUP(sparse_header->blk_sz, - CACHE_LINE)); + memalign(ARCH_DMA_MINALIGN, + ROUNDUP(info->blksz, + ARCH_DMA_MINALIGN)); if (!fill_buf) { fastboot_fail( @@ -160,27 +175,34 @@ void cmd_flash_mmc_sparse_img(const char *arg, void *data, unsigned sz) fill_val = *(uint32_t *)data; data = (char *) data + sizeof(uint32_t); - chunk_blk_cnt = chunk_data_sz / sparse_header->blk_sz; - for (i = 0; i < (sparse_header->blk_sz / sizeof(fill_val)); i++) - { + for (i = 0; i < (info->blksz / sizeof(fill_val)); i++) fill_buf[i] = fill_val; + + if (blk + blkcnt > info->start + info->size) { + printf( + "%s: Request would exceed partition size!\n", + __func__); + fastboot_fail( + "Request would exceed partition size!"); + return; } - for (i = 0; i < chunk_blk_cnt; i++) - { - if (mmc_write(ptn + - ((uint64_t)total_blocks * - sparse_header->blk_sz), - sparse_header->blk_sz, fill_buf)) - { + for (i = 0; i < blkcnt; i++) { + blks = dev_desc->block_write(dev_desc->dev, + blk, 1, fill_buf); + if (blks != 1) { + printf( + "%s: Write failed, block # " LBAFU "\n", + __func__, blkcnt); fastboot_fail("flash write failure"); free(fill_buf); return; } - - total_blocks++; + blk++; } + bytes_written += blkcnt * info->blksz; + total_blocks += chunk_data_sz / sparse_header->blk_sz; free(fill_buf); break; @@ -189,7 +211,7 @@ void cmd_flash_mmc_sparse_img(const char *arg, void *data, unsigned sz) total_blocks += chunk_header->chunk_sz; break; - case CHUNK_TYPE_CRC: + case CHUNK_TYPE_CRC32: if (chunk_header->total_sz != sparse_header->chunk_hdr_sz) { @@ -202,8 +224,8 @@ void cmd_flash_mmc_sparse_img(const char *arg, void *data, unsigned sz) break; default: - debug("Unkown chunk type: %x\n", - chunk_header->chunk_type); + printf("%s: Unknown chunk type: %x\n", __func__, + chunk_header->chunk_type); fastboot_fail("Unknown chunk type"); return; } @@ -211,6 +233,7 @@ void cmd_flash_mmc_sparse_img(const char *arg, void *data, unsigned sz) debug("Wrote %d blocks, expected to write %d blocks\n", total_blocks, sparse_header->total_blks); + printf("........ wrote %u bytes to '%s'\n", bytes_written, part_name); if (total_blocks != sparse_header->total_blks) fastboot_fail("sparse image write failure"); diff --git a/include/aboot.h b/include/aboot.h new file mode 100644 index 00000000000..30e4d36df8b --- /dev/null +++ b/include/aboot.h @@ -0,0 +1,28 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#define ROUNDUP(x, y) (((x) + ((y) - 1)) & ~((y) - 1)) + +void fastboot_fail(const char *s); +void fastboot_okay(const char *s); + +static inline int is_sparse_image(void *buf) +{ + sparse_header_t *s_header = (sparse_header_t *)buf; + + if ((le32_to_cpu(s_header->magic) == SPARSE_HEADER_MAGIC) && + (le16_to_cpu(s_header->major_version) == 1)) + return 1; + + return 0; +} + +void write_sparse_image(block_dev_desc_t *dev_desc, + disk_partition_t *info, const char *part_name, + void *data, unsigned sz); diff --git a/include/sparse_defs.h b/include/sparse_defs.h new file mode 100644 index 00000000000..d0612c94e5d --- /dev/null +++ b/include/sparse_defs.h @@ -0,0 +1,7 @@ +/* + * Copyright 2014 Broadcom Corporation. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include -- cgit v1.3.1 From fb8ffd7cfc68b3dc44e182356a207d784cb30b34 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Thu, 4 Sep 2014 02:40:58 +0900 Subject: compiler*.h: sync include/linux/compiler*.h with Linux 3.16 Copy them from Linux v3.16 tag. My main motivation of this commit is to add compiler-clang.h. Signed-off-by: Masahiro Yamada Cc: Jeroen Hofstee --- include/linux/compiler-clang.h | 12 ++++++ include/linux/compiler-gcc.h | 57 ++++++++++++++++++-------- include/linux/compiler-gcc3.h | 20 ++++----- include/linux/compiler-gcc4.h | 59 +++++++++++++++++++-------- include/linux/compiler-intel.h | 40 ++++++++++++++++++ include/linux/compiler.h | 92 +++++++++++++++++++++++++++++++++++++++++- 6 files changed, 236 insertions(+), 44 deletions(-) create mode 100644 include/linux/compiler-clang.h create mode 100644 include/linux/compiler-intel.h (limited to 'include') diff --git a/include/linux/compiler-clang.h b/include/linux/compiler-clang.h new file mode 100644 index 00000000000..d1e49d52b64 --- /dev/null +++ b/include/linux/compiler-clang.h @@ -0,0 +1,12 @@ +#ifndef __LINUX_COMPILER_H +#error "Please don't include directly, include instead." +#endif + +/* Some compiler specific definitions are overwritten here + * for Clang compiler + */ + +#ifdef uninitialized_var +#undef uninitialized_var +#define uninitialized_var(x) x = *(&(x)) +#endif diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h index 9896e547b94..02ae99e8e6d 100644 --- a/include/linux/compiler-gcc.h +++ b/include/linux/compiler-gcc.h @@ -5,6 +5,9 @@ /* * Common definitions for all gcc versions go here. */ +#define GCC_VERSION (__GNUC__ * 10000 \ + + __GNUC_MINOR__ * 100 \ + + __GNUC_PATCHLEVEL__) /* Optimization barrier */ @@ -34,9 +37,15 @@ __asm__ ("" : "=r"(__ptr) : "0"(ptr)); \ (typeof(ptr)) (__ptr + (off)); }) +/* Make the optimizer believe the variable can be manipulated arbitrarily. */ +#define OPTIMIZER_HIDE_VAR(var) __asm__ ("" : "=r" (var) : "0" (var)) + +#ifdef __CHECKER__ +#define __must_be_array(arr) 0 +#else /* &a[0] degrades to a pointer: a different type from an array */ -#define __must_be_array(a) \ - BUILD_BUG_ON_ZERO(__builtin_types_compatible_p(typeof(a), typeof(&a[0]))) +#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0])) +#endif /* * Force always-inline if the user requests it so via the .config, @@ -44,15 +53,18 @@ */ #if !defined(CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING) || \ !defined(CONFIG_OPTIMIZE_INLINING) || (__GNUC__ < 4) -# define inline inline __attribute__((always_inline)) -# define __inline__ __inline__ __attribute__((always_inline)) -# define __inline __inline __attribute__((always_inline)) +# define inline inline __attribute__((always_inline)) notrace +# define __inline__ __inline__ __attribute__((always_inline)) notrace +# define __inline __inline __attribute__((always_inline)) notrace +#else +/* A lot of inline functions can cause havoc with function tracing */ +# define inline inline notrace +# define __inline__ __inline__ notrace +# define __inline __inline notrace #endif #define __deprecated __attribute__((deprecated)) -#ifndef __packed -# define __packed __attribute__((packed)) -#endif +#define __packed __attribute__((packed)) #define __weak __attribute__((weak)) /* @@ -60,8 +72,12 @@ * naked functions because then mcount is called without stack and frame pointer * being set up and there is no chance to restore the lr register to the value * before mcount was called. + * + * The asm() bodies of naked functions often depend on standard calling conventions, + * therefore they must be noinline and noclone. GCC 4.[56] currently fail to enforce + * this, so we must do so ourselves. See GCC PR44290. */ -#define __naked __attribute__((naked)) notrace +#define __naked __attribute__((naked)) noinline __noclone notrace #define __noreturn __attribute__((noreturn)) @@ -75,13 +91,10 @@ * would be. * [...] */ -#ifndef __pure -# define __pure __attribute__((pure)) -#endif -#ifndef __aligned -# define __aligned(x) __attribute__((aligned(x))) -#endif -#define __printf(a,b) __attribute__((format(printf,a,b))) +#define __pure __attribute__((pure)) +#define __aligned(x) __attribute__((aligned(x))) +#define __printf(a, b) __attribute__((format(printf, a, b))) +#define __scanf(a, b) __attribute__((format(scanf, a, b))) #define noinline __attribute__((noinline)) #define __attribute_const__ __attribute__((__const__)) #define __maybe_unused __attribute__((unused)) @@ -91,3 +104,15 @@ #define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h) #define gcc_header(x) _gcc_header(x) #include gcc_header(__GNUC__) + +#if !defined(__noclone) +#define __noclone /* not needed */ +#endif + +/* + * A trick to suppress uninitialized variable warning without generating any + * code + */ +#define uninitialized_var(x) x = x + +#define __always_inline inline __attribute__((always_inline)) diff --git a/include/linux/compiler-gcc3.h b/include/linux/compiler-gcc3.h index 2befe6513ce..7d89febe4d7 100644 --- a/include/linux/compiler-gcc3.h +++ b/include/linux/compiler-gcc3.h @@ -2,20 +2,22 @@ #error "Please don't include directly, include instead." #endif -#if __GNUC_MINOR__ >= 3 +#if GCC_VERSION < 30200 +# error Sorry, your compiler is too old - please upgrade it. +#endif + +#if GCC_VERSION >= 30300 # define __used __attribute__((__used__)) #else # define __used __attribute__((__unused__)) #endif -#if __GNUC_MINOR__ >= 4 +#if GCC_VERSION >= 30400 #define __must_check __attribute__((warn_unused_result)) #endif -/* - * A trick to suppress uninitialized variable warning without generating any - * code - */ -#define uninitialized_var(x) x = x - -#define __always_inline inline __attribute__((always_inline)) +#ifdef CONFIG_GCOV_KERNEL +# if GCC_VERSION < 30400 +# error "GCOV profiling support for gcc versions below 3.4 not included" +# endif /* __GNUC_MINOR__ */ +#endif /* CONFIG_GCOV_KERNEL */ diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h index 27d11ca7b08..2507fd2a1eb 100644 --- a/include/linux/compiler-gcc4.h +++ b/include/linux/compiler-gcc4.h @@ -4,7 +4,7 @@ /* GCC 4.1.[01] miscompiles __weak */ #ifdef __KERNEL__ -# if __GNUC_MINOR__ == 1 && __GNUC_PATCHLEVEL__ <= 1 +# if GCC_VERSION >= 40100 && GCC_VERSION <= 40101 # error Your version of gcc miscompiles the __weak directive # endif #endif @@ -12,17 +12,12 @@ #define __used __attribute__((__used__)) #define __must_check __attribute__((warn_unused_result)) #define __compiler_offsetof(a,b) __builtin_offsetof(a,b) -#ifndef __always_inline -# define __always_inline inline __attribute__((always_inline)) -#endif -/* - * A trick to suppress uninitialized variable warning without generating any - * code - */ -#define uninitialized_var(x) x = x +#if GCC_VERSION >= 40100 && GCC_VERSION < 40600 +# define __compiletime_object_size(obj) __builtin_object_size(obj, 0) +#endif -#if __GNUC_MINOR__ >= 3 +#if GCC_VERSION >= 40300 /* Mark functions as cold. gcc will assume any path leading to a call to them will be unlikely. This means a lot of manual unlikely()s are unnecessary now for any paths leading to the usual suspects @@ -38,8 +33,15 @@ the kernel context */ #define __cold __attribute__((__cold__)) +#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) -#if __GNUC_MINOR__ >= 5 +#ifndef __CHECKER__ +# define __compiletime_warning(message) __attribute__((warning(message))) +# define __compiletime_error(message) __attribute__((error(message))) +#endif /* __CHECKER__ */ +#endif /* GCC_VERSION >= 40300 */ + +#if GCC_VERSION >= 40500 /* * Mark a position in code as unreachable. This can be used to * suppress control flow warnings after asm blocks that transfer @@ -50,14 +52,37 @@ * unreleased. Really, we need to have autoconf for the kernel. */ #define unreachable() __builtin_unreachable() -#endif +/* Mark a function definition as prohibited from being cloned. */ +#define __noclone __attribute__((__noclone__)) + +#endif /* GCC_VERSION >= 40500 */ + +#if GCC_VERSION >= 40600 +/* + * Tell the optimizer that something else uses this function or variable. + */ +#define __visible __attribute__((externally_visible)) #endif -#if __GNUC_MINOR__ > 0 -#define __compiletime_object_size(obj) __builtin_object_size(obj, 0) +/* + * GCC 'asm goto' miscompiles certain code sequences: + * + * http://gcc.gnu.org/bugzilla/show_bug.cgi?id=58670 + * + * Work it around via a compiler barrier quirk suggested by Jakub Jelinek. + * Fixed in GCC 4.8.2 and later versions. + * + * (asm goto is automatically volatile - the naming reflects this.) + */ +#define asm_volatile_goto(x...) do { asm goto(x); asm (""); } while (0) + +#ifdef CONFIG_ARCH_USE_BUILTIN_BSWAP +#if GCC_VERSION >= 40400 +#define __HAVE_BUILTIN_BSWAP32__ +#define __HAVE_BUILTIN_BSWAP64__ #endif -#if __GNUC_MINOR__ >= 4 -#define __compiletime_warning(message) __attribute__((warning(message))) -#define __compiletime_error(message) __attribute__((error(message))) +#if GCC_VERSION >= 40800 || (defined(__powerpc__) && GCC_VERSION >= 40600) +#define __HAVE_BUILTIN_BSWAP16__ #endif +#endif /* CONFIG_ARCH_USE_BUILTIN_BSWAP */ diff --git a/include/linux/compiler-intel.h b/include/linux/compiler-intel.h new file mode 100644 index 00000000000..ba147a1727e --- /dev/null +++ b/include/linux/compiler-intel.h @@ -0,0 +1,40 @@ +#ifndef __LINUX_COMPILER_H +#error "Please don't include directly, include instead." +#endif + +#ifdef __ECC + +/* Some compiler specific definitions are overwritten here + * for Intel ECC compiler + */ + +#include + +/* Intel ECC compiler doesn't support gcc specific asm stmts. + * It uses intrinsics to do the equivalent things. + */ +#undef RELOC_HIDE +#undef OPTIMIZER_HIDE_VAR + +#define RELOC_HIDE(ptr, off) \ + ({ unsigned long __ptr; \ + __ptr = (unsigned long) (ptr); \ + (typeof(ptr)) (__ptr + (off)); }) + +/* This should act as an optimization barrier on var. + * Given that this compiler does not have inline assembly, a compiler barrier + * is the best we can do. + */ +#define OPTIMIZER_HIDE_VAR(var) barrier() + +/* Intel ECC compiler doesn't support __builtin_types_compatible_p() */ +#define __must_be_array(a) 0 + +#endif + +#ifndef __HAVE_BUILTIN_BSWAP16__ +/* icc has this, but it's called _bswap16 */ +#define __HAVE_BUILTIN_BSWAP16__ +#define __builtin_bswap16 _bswap16 +#endif + diff --git a/include/linux/compiler.h b/include/linux/compiler.h index 5be3dab4a69..d5ad7b1118f 100644 --- a/include/linux/compiler.h +++ b/include/linux/compiler.h @@ -5,16 +5,23 @@ #ifdef __CHECKER__ # define __user __attribute__((noderef, address_space(1))) -# define __kernel /* default address space */ +# define __kernel __attribute__((address_space(0))) # define __safe __attribute__((safe)) # define __force __attribute__((force)) # define __nocast __attribute__((nocast)) # define __iomem __attribute__((noderef, address_space(2))) +# define __must_hold(x) __attribute__((context(x,1,1))) # define __acquires(x) __attribute__((context(x,0,1))) # define __releases(x) __attribute__((context(x,1,0))) # define __acquire(x) __context__(x,1) # define __release(x) __context__(x,-1) # define __cond_lock(x,c) ((c) ? ({ __acquire(x); 1; }) : 0) +# define __percpu __attribute__((noderef, address_space(3))) +#ifdef CONFIG_SPARSE_RCU_POINTER +# define __rcu __attribute__((noderef, address_space(4))) +#else +# define __rcu +#endif extern void __chk_user_ptr(const volatile void __user *); extern void __chk_io_ptr(const volatile void __iomem *); #else @@ -27,13 +34,20 @@ extern void __chk_io_ptr(const volatile void __iomem *); # define __chk_user_ptr(x) (void)0 # define __chk_io_ptr(x) (void)0 # define __builtin_warning(x, y...) (1) +# define __must_hold(x) # define __acquires(x) # define __releases(x) # define __acquire(x) (void)0 # define __release(x) (void)0 # define __cond_lock(x,c) (c) +# define __percpu +# define __rcu #endif +/* Indirect macros required for expanded argument pasting, eg. __LINE__. */ +#define ___PASTE(a,b) a##b +#define __PASTE(a,b) ___PASTE(a,b) + #ifdef __KERNEL__ #ifdef __GNUC__ @@ -49,6 +63,13 @@ extern void __chk_io_ptr(const volatile void __iomem *); # include #endif +/* Clang compiler defines __GNUC__. So we will overwrite implementations + * coming from above header files here + */ +#ifdef __clang__ +#include +#endif + /* * Generic compiler-dependent macros required for kernel * build go below this comment. Actual compiler/compiler version @@ -156,6 +177,15 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); (typeof(ptr)) (__ptr + (off)); }) #endif +#ifndef OPTIMIZER_HIDE_VAR +#define OPTIMIZER_HIDE_VAR(var) barrier() +#endif + +/* Not-quite-unique ID. */ +#ifndef __UNIQUE_ID +# define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __LINE__) +#endif + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ @@ -228,7 +258,7 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); /* * Rather then using noinline to prevent stack consumption, use - * noinline_for_stack instead. For documentaiton reasons. + * noinline_for_stack instead. For documentation reasons. */ #define noinline_for_stack noinline @@ -270,11 +300,20 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); # define __section(S) __attribute__ ((__section__(#S))) #endif +#ifndef __visible +#define __visible +#endif + /* Are two types/vars the same type (ignoring qualifiers)? */ #ifndef __same_type # define __same_type(a, b) __builtin_types_compatible_p(typeof(a), typeof(b)) #endif +/* Is this type a native word size -- useful for atomic operations */ +#ifndef __native_word +# define __native_word(t) (sizeof(t) == sizeof(int) || sizeof(t) == sizeof(long)) +#endif + /* Compile time object size, -1 for unknown */ #ifndef __compiletime_object_size # define __compiletime_object_size(obj) -1 @@ -284,8 +323,49 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); #endif #ifndef __compiletime_error # define __compiletime_error(message) +/* + * Sparse complains of variable sized arrays due to the temporary variable in + * __compiletime_assert. Unfortunately we can't just expand it out to make + * sparse see a constant array size without breaking compiletime_assert on old + * versions of GCC (e.g. 4.2.4), so hide the array from sparse altogether. + */ +# ifndef __CHECKER__ +# define __compiletime_error_fallback(condition) \ + do { ((void)sizeof(char[1 - 2 * condition])); } while (0) +# endif +#endif +#ifndef __compiletime_error_fallback +# define __compiletime_error_fallback(condition) do { } while (0) #endif +#define __compiletime_assert(condition, msg, prefix, suffix) \ + do { \ + bool __cond = !(condition); \ + extern void prefix ## suffix(void) __compiletime_error(msg); \ + if (__cond) \ + prefix ## suffix(); \ + __compiletime_error_fallback(__cond); \ + } while (0) + +#define _compiletime_assert(condition, msg, prefix, suffix) \ + __compiletime_assert(condition, msg, prefix, suffix) + +/** + * compiletime_assert - break build and emit msg if condition is false + * @condition: a compile-time constant condition to check + * @msg: a message to emit if condition is false + * + * In tradition of POSIX assert, this macro will break the build if the + * supplied condition is *false*, emitting the supplied error message if the + * compiler has support to do so. + */ +#define compiletime_assert(condition, msg) \ + _compiletime_assert(condition, msg, __compiletime_assert_, __LINE__) + +#define compiletime_assert_atomic_type(t) \ + compiletime_assert(__native_word(t), \ + "Need native word sized stores/loads for atomicity.") + /* * Prevent the compiler from merging or refetching accesses. The compiler * is also forbidden from reordering successive instances of ACCESS_ONCE(), @@ -300,4 +380,12 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect); */ #define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x)) +/* Ignore/forbid kprobes attach on very low level functions marked by this attribute: */ +#ifdef CONFIG_KPROBES +# define __kprobes __attribute__((__section__(".kprobes.text"))) +# define nokprobe_inline __always_inline +#else +# define __kprobes +# define nokprobe_inline inline +#endif #endif /* __LINUX_COMPILER_H */ -- cgit v1.3.1 From 10226f2992da55b8427fa9b293bc16676327f34a Mon Sep 17 00:00:00 2001 From: Guillaume GARDET Date: Fri, 5 Sep 2014 15:32:46 +0200 Subject: OMAP4: Use generic 'load' command instead of 'fatload' for 'loadbootscript' and 'loadbootenv' as already done for 'loadimage' and 'loaduimage'. This patch uses generic 'load' command instead of 'fatload' for 'loadbootscript' and 'loadbootenv' as already done for 'loadimage' and 'loaduimage' for OMAP4 boards. This allows to use EXT partition instead of FAT, while keeping FAT compatibility. Signed-off-by: Guillaume GARDET Cc: Tom Rini --- include/configs/ti_omap4_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h index 8c7310c9a1d..b0f199e3f4a 100644 --- a/include/configs/ti_omap4_common.h +++ b/include/configs/ti_omap4_common.h @@ -101,10 +101,10 @@ "vram=${vram} " \ "root=${mmcroot} " \ "rootfstype=${mmcrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ "source ${loadaddr}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ + "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ "env import -t ${loadaddr} ${filesize}\0" \ "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ -- cgit v1.3.1 From 3aae66e2a74ac89724d16b6e8908dcd0d2825eeb Mon Sep 17 00:00:00 2001 From: Guillaume GARDET Date: Thu, 11 Sep 2014 09:23:08 +0200 Subject: am335x_evm: Add boot script support to am335x_evm This patch adds boot script support to am335x_evm Signed-off-by: Guillaume GARDET Cc: Tom Rini --- include/configs/am335x_evm.h | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index df1a6fc5288..aef0ad3fbe9 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -115,6 +115,9 @@ "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ "ip=dhcp\0" \ "bootenv=uEnv.txt\0" \ + "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ + "source ${loadaddr}\0" \ "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ "importbootenv=echo Importing environment from mmc ...; " \ "env import -t -r $loadaddr $filesize\0" \ @@ -142,17 +145,21 @@ "mmcboot=mmc dev ${mmcdev}; " \ "if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loadimage; then " \ - "run mmcloados;" \ - "fi;" \ + "if run loadbootscript; then " \ + "run bootscript;" \ + "else " \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadimage; then " \ + "run mmcloados;" \ + "fi;" \ + "fi ;" \ "fi;\0" \ "spiboot=echo Booting from spi ...; " \ "run spiargs; " \ -- cgit v1.3.1 From d6b79434644f67d04d089061f449535675a640eb Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Fri, 18 Jul 2014 16:43:08 +0800 Subject: ARM: atmel: sama5d3xek: enable NOR flash support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- include/configs/sama5d3xek.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 56c2454dff2..0104d5f90a9 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -79,8 +79,19 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME -/* No NOR flash */ +/* NOR flash */ +#define CONFIG_CMD_FLASH + +#ifdef CONFIG_CMD_FLASH +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CONFIG_SYS_MAX_FLASH_SECT 131 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#else #define CONFIG_SYS_NO_FLASH +#endif /* * Command line configuration. -- cgit v1.3.1 From 09e03e0592c91dc0b7588ebc2d208bed08502c35 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Tue, 2 Sep 2014 18:13:23 +0800 Subject: ARM: at91sam9n12ek: convert to generic board support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Josh Wu Signed-off-by: Andreas Bießmann --- include/configs/at91sam9n12ek.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 9b0e588c6b8..f02fce95b39 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -31,6 +31,7 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD /* general purpose I/O */ #define CONFIG_AT91_GPIO -- cgit v1.3.1 From 015b18c642d9b0f92d1b35f6d6ed73a6a0b29675 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Tue, 2 Sep 2014 18:14:11 +0800 Subject: ARM: at91sam9rlek: convert to generic board support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Josh Wu Signed-off-by: Andreas Bießmann --- include/configs/at91sam9rlek.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index 3747098d2ad..b8d5dd156f9 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -34,6 +34,8 @@ #define CONFIG_CMD_BOOTZ #define CONFIG_OF_LIBFDT +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_ATMEL_LEGACY #define CONFIG_AT91_GPIO 1 #define CONFIG_AT91_GPIO_PULLUP 1 -- cgit v1.3.1