From 91ee54741e1687844c2e8a94304d8306d6db12ba Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Mon, 22 Feb 2021 18:18:11 +0000 Subject: board/km: add support for seli8 design based on nxp ls102x The SELI8 design is a new tdm service unit card for Hitachi-Powergrids XMC and FOX product lines. It is based on NXP LS1021 SoC and it provides following interfaces: - IFC interface for NOR, NAND and external FPGA's - 1 x RGMII ETH for debug purposes - 2 x SGMII ETH for management communication via back-plane - 1 x uQE HDLC for management communication via back-plane - 1 x I2C for peripheral devices - 1 x SPI for peripheral devices - 1 x UART for debug logging It is foreseen that the design will be later re-used for another XMC and FOX service cards with similar SoC requirements. Signed-off-by: Rainer Boschung Signed-off-by: Matteo Ghidoni Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- include/configs/km/pg-wcom-ls102xa.h | 292 +++++++++++++++++++++++++++++++++++ include/configs/pg-wcom-seli8.h | 45 ++++++ 2 files changed, 337 insertions(+) create mode 100644 include/configs/km/pg-wcom-ls102xa.h create mode 100644 include/configs/pg-wcom-seli8.h (limited to 'include') diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h new file mode 100644 index 00000000000..3d7519c9354 --- /dev/null +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -0,0 +1,292 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Hitachi Power Grids. All rights reserved. + */ + +#ifndef __CONFIG_PG_WCOM_LS102XA_H +#define __CONFIG_PG_WCOM_LS102XA_H + +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* include common defines/options for all Keymile boards */ +#include "keymile-common.h" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +#define CONFIG_SYS_CLK_FREQ 66666666 +/* + * Take into account default implementation where DDR_FDBK_MULTI is consider as + * configured for DDR_PLL = 2*MEM_PLL_RAT. + * In our case DDR_FDBK_MULTI is 2, means DDR_PLL = MEM_PLL_RAT. + */ +#define CONFIG_DDR_CLK_FREQ (100000000 >> 1) + +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +#define CONFIG_DDR_SPD + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x54 + +/* + * IFC Definitions + */ +/* NOR Flash Definitions */ +#define CONFIG_FSL_IFC +#define CONFIG_SYS_FLASH_BASE 0x60000000 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_TE | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64 * 1024 * 1024) + +#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_AVD_TGL_PGM_EN | \ + CSOR_NOR_ADM_SHIFT(0x4) | \ + CSOR_NOR_NOR_MODE_ASYNC_NOR | \ + CSOR_NOR_TRHZ_20 | \ + CSOR_NOR_BCTLD) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ + FTIM0_NOR_TEADC(0x7) | \ + FTIM0_NOR_TAVDS(0x0) | \ + FTIM0_NOR_TEAHC(0x1)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ + FTIM1_NOR_TRAD_NOR(0x21) | \ + FTIM1_NOR_TSEQRAD_NOR(0x21)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ + FTIM2_NOR_TCH(0x1) | \ + FTIM2_NOR_TWPH(0x6) | \ + FTIM2_NOR_TWP(0xb)) +#define CONFIG_SYS_NOR_FTIM3 0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } + +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_WRITE_SWAPPED_DATA + +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 + +/* NAND Flash Definitions */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0x68000000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR_EXT (0x0) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_TE | \ + CSPR_MSEL_NAND | \ + CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN \ + | CSOR_NAND_ECC_DEC_EN \ + | CSOR_NAND_ECC_MODE_4 \ + | CSOR_NAND_RAL_3 \ + | CSOR_NAND_PGS_2K \ + | CSOR_NAND_SPRZ_64 \ + | CSOR_NAND_PB(64) \ + | CSOR_NAND_TRHZ_40 \ + | CSOR_NAND_BCTLD) + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x3) | \ + FTIM0_NAND_TWP(0x8) | \ + FTIM0_NAND_TWCHT(0x3) | \ + FTIM0_NAND_TWH(0x5)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1e) | \ + FTIM1_NAND_TWBE(0x1e) | \ + FTIM1_NAND_TRR(0x6) | \ + FTIM1_NAND_TRP(0x8)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x9) | \ + FTIM2_NAND_TREH(0x5) | \ + FTIM2_NAND_TWHRE(0x3c)) +#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x1e)) + +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* QRIO FPGA Definitions */ +#define CONFIG_SYS_QRIO_BASE 0x70000000 +#define CONFIG_SYS_QRIO_BASE_PHYS CONFIG_SYS_QRIO_BASE + +#define CONFIG_SYS_CSPR2_EXT (0x00) +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_TE | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CSOR2 (CSOR_GPCM_ADM_SHIFT(0x4) | \ + CSOR_GPCM_TRHZ_20 | \ + CSOR_GPCM_BCTLD) +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x2) | \ + FTIM0_GPCM_TEADC(0x8) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x6)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x1) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x7)) +#define CONFIG_SYS_CS2_FTIM3 0x04000000 + +/* + * Serial Port + */ +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + +/* + * I2C + */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_MAX_HOPS 1 +#define CONFIG_SYS_NUM_I2C_BUSES 3 +#define I2C_MUX_PCA_ADDR 0x70 +#define I2C_MUX_CH_DEFAULT 0x0 +#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ + {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ + {1, {I2C_NULL_HOP} }, \ + } + +/* + * eTSEC + */ +#ifdef CONFIG_TSEC_ENET +#define CONFIG_ETHPRIME "ethernet@2d90000" +#endif + +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define CONFIG_SMP_PEN_ADDR 0x01ee0200 +#define COUNTER_FREQUENCY 12500000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 256 +#define CONFIG_FSL_DEVICE_DISABLE + +/* + * Miscellaneous configurable options + */ + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_LS102XA_STREAM_ID + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */ +#define CONFIG_SYS_QE_FW_ADDR 0x60020000 + +#define CONFIG_SYS_BOOTCOUNT_BE + +/* + * Environment + */ + +#define CONFIG_ENV_TOTAL_SIZE 0x40000 +#define ENV_DEL_ADDR CONFIG_ENV_ADDR_REDUND /* direct for newenv */ + +#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ +#define CONFIG_KM_DEF_ENV +#endif + +#ifndef CONFIG_KM_DEF_BOOT_ARGS_CPU +#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" +#endif + +#define CONFIG_KM_DEF_ENV_CPU \ + "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ + "cramfsloadfdt=" \ + "cramfsload ${fdt_addr_r} " \ + "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ + "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ + "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize} && " \ + "erase " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize} && " \ + "cp.b ${load_addr_r} " \ + __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize} && " \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize}\0" \ + "update-nor=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ + " +${filesize} && " \ + "erase " __stringify(CONFIG_SYS_FLASH_BASE) \ + " +${filesize} && " \ + "cp.b ${load_addr_r} " \ + __stringify(CONFIG_SYS_FLASH_BASE) " ${filesize} && " \ + "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ + " +" __stringify(CONFIG_SYS_MONITOR_LEN)"\0" \ + "set_fdthigh=true\0" \ + "checkfdt=true\0" \ + "" + +#define CONFIG_KM_NEW_ENV \ + "newenv=protect off " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ + "erase " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) " && " \ + "protect on " __stringify(ENV_DEL_ADDR) \ + " +" __stringify(CONFIG_ENV_TOTAL_SIZE) "\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_KM_NEW_ENV \ + CONFIG_KM_DEF_ENV \ + "EEprom_ivm=pca9547:70:9\0" \ + "" + +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Increase map for Linux */ + +#endif diff --git a/include/configs/pg-wcom-seli8.h b/include/configs/pg-wcom-seli8.h new file mode 100644 index 00000000000..9a7669c940b --- /dev/null +++ b/include/configs/pg-wcom-seli8.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Hitachi Power Grids. All rights reserved. + */ + +#ifndef __CONFIG_PG_WCOM_SELI8_H +#define __CONFIG_PG_WCOM_SELI8_H + +#define CONFIG_HOSTNAME "SELI8" + +#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" +#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" + +/* PAXK FPGA Definitions */ +#define CONFIG_SYS_CSPR3_EXT (0x00) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_PAX_BASE) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) +#define CONFIG_SYS_CSOR3 (CSOR_GPCM_ADM_SHIFT(0x4) | \ + CSOR_GPCM_TRHZ_40) +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x6) | \ + FTIM0_GPCM_TEADC(0x7) | \ + FTIM0_GPCM_TEAHC(0x2)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x2) | \ + FTIM1_GPCM_TRAD(0x12)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x3) | \ + FTIM2_GPCM_TCH(0x1) | \ + FTIM2_GPCM_TWP(0x12)) +#define CONFIG_SYS_CS3_FTIM3 0x04000000 + +/* PRST */ +#define KM_LIU_RST 0 +#define KM_PAXK_RST 1 +#define KM_DBG_ETH_RST 15 + +/* QRIO GPIOs used for deblocking */ +#define KM_I2C_DEBLOCK_PORT QRIO_GPIO_A +#define KM_I2C_DEBLOCK_SCL 20 +#define KM_I2C_DEBLOCK_SDA 21 + +#include "km/pg-wcom-ls102xa.h" + +#endif /* __CONFIG_PG_WCOM_SELI8_H */ -- cgit v1.3.1 From 173c66bf9c0cfefd0ff69f0939c95900340d0988 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 14 Mar 2021 20:14:46 +0800 Subject: of: extra: Introduce ofnode_phy_is_fixed_link() API Introduce a helper API ofnode_phy_is_fixed_link() to detect whether the ethernet controller connects to a fixed-link pseudo-PHY device. Note there are two ways to describe a fixed PHY attached to an Ethernet device: - the new DT binding, where 'fixed-link' is a sub-node of the Ethernet device - the old DT binding, where 'fixed-link' is a property with 5 cells encoding various information about the fixed PHY Signed-off-by: Bin Meng Reviewed-by: Simon Glass Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- drivers/core/of_extra.c | 23 +++++++++++++++++++++++ include/dm/of_extra.h | 20 ++++++++++++++++++++ 2 files changed, 43 insertions(+) (limited to 'include') diff --git a/drivers/core/of_extra.c b/drivers/core/of_extra.c index 653344529e6..7702beff97b 100644 --- a/drivers/core/of_extra.c +++ b/drivers/core/of_extra.c @@ -130,3 +130,26 @@ int ofnode_decode_memory_region(ofnode config_node, const char *mem_type, return 0; } + +bool ofnode_phy_is_fixed_link(ofnode eth_node, ofnode *phy_node) +{ + ofnode node, subnode; + int len; + + subnode = ofnode_find_subnode(eth_node, "fixed-link"); + if (ofnode_valid(subnode)) { + /* new binding */ + node = subnode; + } else if (ofnode_get_property(eth_node, "fixed-link", &len) && + len == (5 * sizeof(__be32))) { + /* old binding */ + node = eth_node; + } else { + return false; + } + + if (phy_node) + *phy_node = node; + + return true; +} diff --git a/include/dm/of_extra.h b/include/dm/of_extra.h index fc4f9743196..f0d205491c1 100644 --- a/include/dm/of_extra.h +++ b/include/dm/of_extra.h @@ -94,4 +94,24 @@ int ofnode_decode_memory_region(ofnode config_node, const char *mem_type, const char *suffix, fdt_addr_t *basep, fdt_size_t *sizep); +/** + * ofnode_phy_is_fixed_link() - Detect fixed-link pseudo-PHY device + * + * This function detects whether the ethernet controller connects to a + * fixed-link pseudo-PHY device. + * + * This function supports the following two DT bindings: + * - the new DT binding, where 'fixed-link' is a sub-node of the + * Ethernet device + * - the old DT binding, where 'fixed-link' is a property with 5 + * cells encoding various information about the fixed PHY + * + * If both new and old bindings exist, the new one is preferred. + * + * @param eth_node ofnode containing the fixed-link subnode/property + * @param phy_node if fixed-link PHY detected, containing the PHY ofnode + * @return true if a fixed-link pseudo-PHY device exists, false otherwise + */ +bool ofnode_phy_is_fixed_link(ofnode eth_node, ofnode *phy_node); + #endif -- cgit v1.3.1 From ff98da06674d47ff995edd068bcbd4ae6da69f00 Mon Sep 17 00:00:00 2001 From: Claudiu Manoil Date: Sun, 14 Mar 2021 20:14:57 +0800 Subject: sandbox: Add a DSA sandbox driver and unit test The DSA sandbox driver is used for unit testing the DSA class code. It implements a simple 2 port switch plus 1 CPU port, and uses a very simple tag to identify the ports. The DSA sandbox device is connected via CPU port to a regular Ethernet sandbox device, called 'dsa-test-eth, managed by the existing eth sandbox driver. The 'dsa-test-eth' is not intended for testing the eth class code however, but it is used to emulate traffic through the 'lan0' and 'lan1' front pannel switch ports. To achieve this the dsa sandbox driver registers a tx handler for the 'dsa-test-eth' device. The switch ports, labeled as 'lan0' and 'lan1', are also registered as eth devices by the dsa class code this time. So pinging through these switch ports is as easy as: => setenv ethact lan0 => ping 1.2.3.5 Unit tests for the dsa class code were also added. The 'dsa_probe' test exercises most API functions from dsa.h. The 'dsa' unit test simply exercises ARP/ICMP traffic through the two switch ports, including tag injection and extraction, with the help of the dsa sandbox driver. I took care to minimize the impact on the existing eth unit tests, though some adjustments needed to be made with the addition of extra eth interfaces used by the dsa unit tests. The additional eth interfaces also require MAC addresses, these have been added to the sandbox default environment. Signed-off-by: Alex Marginean Signed-off-by: Claudiu Manoil Reviewed-by: Simon Glass Signed-off-by: Vladimir Oltean Message-Id: <20210216224804.3355044-5-olteanv@gmail.com> Signed-off-by: Bin Meng Reviewed-by: Priyanka Jain --- arch/Kconfig | 2 + arch/sandbox/dts/test.dts | 48 +++++++++++++ drivers/net/Kconfig | 9 +++ drivers/net/Makefile | 1 + drivers/net/dsa_sandbox.c | 179 ++++++++++++++++++++++++++++++++++++++++++++++ include/configs/sandbox.h | 2 + test/dm/Makefile | 1 + test/dm/dsa.c | 82 +++++++++++++++++++++ test/dm/eth.c | 10 +-- 9 files changed, 329 insertions(+), 5 deletions(-) create mode 100644 drivers/net/dsa_sandbox.c create mode 100644 test/dm/dsa.c (limited to 'include') diff --git a/arch/Kconfig b/arch/Kconfig index 70232239278..dd1ff9d963f 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -162,6 +162,8 @@ config SANDBOX imply CMD_CLONE imply SILENT_CONSOLE imply BOOTARGS_SUBST + imply PHY_FIXED + imply DM_DSA config SH bool "SuperH architecture" diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 8c4c2bfddd9..57f4dc1e578 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -15,7 +15,9 @@ aliases { console = &uart0; eth0 = "/eth@10002000"; + eth2 = &swp_0; eth3 = ð_3; + eth4 = &dsa_eth0; eth5 = ð_5; gpio1 = &gpio_a; gpio2 = &gpio_b; @@ -478,6 +480,52 @@ fake-host-hwaddr = [00 00 66 44 22 22]; }; + dsa_eth0: dsa-test-eth { + compatible = "sandbox,eth"; + reg = <0x10006000 0x1000>; + fake-host-hwaddr = [00 00 66 44 22 66]; + }; + + dsa-test { + compatible = "sandbox,dsa"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + swp_0: port@0 { + reg = <0>; + label = "lan0"; + phy-mode = "rgmii-rxid"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + swp_1: port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "rgmii-txid"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@2 { + reg = <2>; + ethernet = <&dsa_eth0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + firmware { sandbox_firmware: sandbox-firmware { compatible = "sandbox,firmware"; diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 54f7b81624e..72822eaec4b 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -78,6 +78,15 @@ config DM_ETH_PHY help Enable driver model for Ethernet Generic PHY . +config DSA_SANDBOX + depends on DM_DSA && SANDBOX + default y + bool "Sandbox: Mocked DSA driver" + help + This driver implements a dummy DSA switch connected to a dummy sandbox + Ethernet device used as DSA master, to test DSA class code, including + exported DSA API and datapath processing of Ethernet traffic. + menuconfig NETDEVICES bool "Network device support" depends on NET diff --git a/drivers/net/Makefile b/drivers/net/Makefile index ce7b9e3478b..2ce89f7e3c6 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_ETH_DESIGNWARE_SOCFPGA) += dwmac_socfpga.o obj-$(CONFIG_ETH_DESIGNWARE_S700) += dwmac_s700.o obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o obj-$(CONFIG_DNET) += dnet.o +obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o obj-$(CONFIG_DM_ETH_PHY) += eth-phy-uclass.o obj-$(CONFIG_E1000) += e1000.o obj-$(CONFIG_E1000_SPI) += e1000_spi.o diff --git a/drivers/net/dsa_sandbox.c b/drivers/net/dsa_sandbox.c new file mode 100644 index 00000000000..4b62670e5d1 --- /dev/null +++ b/drivers/net/dsa_sandbox.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019-2021 NXP Semiconductors + */ + +#include +#include +#include + +#define DSA_SANDBOX_MAGIC 0x00415344 +#define DSA_SANDBOX_TAG_LEN sizeof(struct dsa_sandbox_tag) + +struct dsa_sandbox_priv { + struct eth_sandbox_priv *master_priv; + int port_en_mask; +}; + +struct dsa_sandbox_tag { + u32 magic; + u32 port; +}; + +static bool sb_dsa_port_enabled(struct udevice *dev, int port) +{ + struct dsa_sandbox_priv *priv = dev_get_priv(dev); + + return priv->port_en_mask & BIT(port); +} + +static bool sb_dsa_master_enabled(struct udevice *dev) +{ + struct dsa_sandbox_priv *priv = dev_get_priv(dev); + + return !priv->master_priv->disabled; +} + +static int dsa_sandbox_port_enable(struct udevice *dev, int port, + struct phy_device *phy) +{ + struct dsa_sandbox_priv *priv = dev_get_priv(dev); + + if (!sb_dsa_master_enabled(dev)) + return -EFAULT; + + priv->port_en_mask |= BIT(port); + + return 0; +} + +static void dsa_sandbox_port_disable(struct udevice *dev, int port, + struct phy_device *phy) +{ + struct dsa_sandbox_priv *priv = dev_get_priv(dev); + + priv->port_en_mask &= ~BIT(port); +} + +static int dsa_sandbox_xmit(struct udevice *dev, int port, void *packet, + int length) +{ + struct dsa_sandbox_tag *tag = packet; + + if (!sb_dsa_master_enabled(dev)) + return -EFAULT; + + if (!sb_dsa_port_enabled(dev, port)) + return -EFAULT; + + tag->magic = DSA_SANDBOX_MAGIC; + tag->port = port; + + return 0; +} + +static int dsa_sandbox_rcv(struct udevice *dev, int *port, void *packet, + int length) +{ + struct dsa_sandbox_tag *tag = packet; + + if (!sb_dsa_master_enabled(dev)) + return -EFAULT; + + if (tag->magic != DSA_SANDBOX_MAGIC) + return -EFAULT; + + *port = tag->port; + if (!sb_dsa_port_enabled(dev, tag->port)) + return -EFAULT; + + return 0; +} + +static const struct dsa_ops dsa_sandbox_ops = { + .port_enable = dsa_sandbox_port_enable, + .port_disable = dsa_sandbox_port_disable, + .xmit = dsa_sandbox_xmit, + .rcv = dsa_sandbox_rcv, +}; + +static int sb_dsa_handler(struct udevice *dev, void *packet, + unsigned int len) +{ + struct eth_sandbox_priv *master_priv; + struct dsa_sandbox_tag *tag = packet; + struct udevice *dsa_dev; + u32 port_index; + void *rx_buf; + int i; + + /* this emulates the switch hw and the network side */ + if (tag->magic != DSA_SANDBOX_MAGIC) + return -EFAULT; + + port_index = tag->port; + master_priv = dev_get_priv(dev); + dsa_dev = master_priv->priv; + if (!sb_dsa_port_enabled(dsa_dev, port_index)) + return -EFAULT; + + packet += DSA_SANDBOX_TAG_LEN; + len -= DSA_SANDBOX_TAG_LEN; + + if (!sandbox_eth_arp_req_to_reply(dev, packet, len)) + goto dsa_tagging; + if (!sandbox_eth_ping_req_to_reply(dev, packet, len)) + goto dsa_tagging; + + return 0; + +dsa_tagging: + master_priv->recv_packets--; + i = master_priv->recv_packets; + rx_buf = master_priv->recv_packet_buffer[i]; + len = master_priv->recv_packet_length[i]; + memmove(rx_buf + DSA_SANDBOX_TAG_LEN, rx_buf, len); + + tag = rx_buf; + tag->magic = DSA_SANDBOX_MAGIC; + tag->port = port_index; + len += DSA_SANDBOX_TAG_LEN; + master_priv->recv_packet_length[i] = len; + master_priv->recv_packets++; + + return 0; +} + +static int dsa_sandbox_probe(struct udevice *dev) +{ + struct dsa_sandbox_priv *priv = dev_get_priv(dev); + struct udevice *master = dsa_get_master(dev); + struct eth_sandbox_priv *master_priv; + + if (!master) + return -ENODEV; + + dsa_set_tagging(dev, DSA_SANDBOX_TAG_LEN, 0); + + master_priv = dev_get_priv(master); + master_priv->priv = dev; + master_priv->tx_handler = sb_dsa_handler; + + priv->master_priv = master_priv; + + return 0; +} + +static const struct udevice_id dsa_sandbox_ids[] = { + { .compatible = "sandbox,dsa" }, + { } +}; + +U_BOOT_DRIVER(dsa_sandbox) = { + .name = "dsa_sandbox", + .id = UCLASS_DSA, + .of_match = dsa_sandbox_ids, + .probe = dsa_sandbox_probe, + .ops = &dsa_sandbox_ops, + .priv_auto = sizeof(struct dsa_sandbox_priv), +}; diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index bbb7d12ad14..6e79d3f56ee 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -93,7 +93,9 @@ #endif #define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \ + "eth2addr=00:00:11:22:33:48\0" \ "eth3addr=00:00:11:22:33:45\0" \ + "eth4addr=00:00:11:22:33:48\0" \ "eth5addr=00:00:11:22:33:46\0" \ "eth6addr=00:00:11:22:33:47\0" \ "ipaddr=1.2.3.4\0" diff --git a/test/dm/Makefile b/test/dm/Makefile index d54abb73413..5de6fbfb5d5 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_CLK) += clk.o clk_ccf.o obj-$(CONFIG_CROS_EC) += cros_ec.o obj-$(CONFIG_DEVRES) += devres.o obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi_host.o +obj-$(CONFIG_DM_DSA) += dsa.o obj-$(CONFIG_DM_ETH) += eth.o obj-$(CONFIG_FIRMWARE) += firmware.o obj-$(CONFIG_DM_GPIO) += gpio.o diff --git a/test/dm/dsa.c b/test/dm/dsa.c new file mode 100644 index 00000000000..18c1776460d --- /dev/null +++ b/test/dm/dsa.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2020-2021 NXP Semiconductors + */ + +#include +#include +#include +#include +#include +#include + +/* This test exercises the major dsa.h API functions, after making sure + * that the DSA ports and the master Eth are correctly probed. + */ +static int dm_test_dsa_probe(struct unit_test_state *uts) +{ + struct udevice *dev_dsa, *dev_port, *dev_master; + struct dsa_pdata *dsa_pdata; + enum uclass_id id; + + id = uclass_get_by_name("dsa"); + ut_assert(id == UCLASS_DSA); + + ut_assertok(uclass_find_device_by_name(UCLASS_DSA, "dsa-test", + &dev_dsa)); + ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "dsa-test-eth", + &dev_master)); + ut_assertok(device_probe(dev_master)); + + ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "dsa-test@0", + &dev_port)); + ut_assertok(device_probe(dev_port)); + + ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "dsa-test@1", + &dev_port)); + ut_assertok(device_probe(dev_port)); + + /* exercise DSA API */ + dsa_pdata = dev_get_uclass_plat(dev_dsa); + ut_assertnonnull(dsa_pdata); + /* includes CPU port */ + ut_assert(dsa_pdata->num_ports == 3); + + ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "lan0", + &dev_port)); + ut_assertok(device_probe(dev_port)); + + ut_assertok(uclass_find_device_by_name(UCLASS_ETH, "lan1", + &dev_port)); + ut_assertok(device_probe(dev_port)); + + dev_master = dsa_get_master(dev_dsa); + ut_assertnonnull(dev_master); + ut_asserteq_str("dsa-test-eth", dev_master->name); + + return 0; +} + +DM_TEST(dm_test_dsa_probe, UT_TESTF_SCAN_FDT); + +/* This test sends ping requests with the local address through each DSA port + * via the sandbox DSA master Eth. + */ +static int dm_test_dsa(struct unit_test_state *uts) +{ + net_ping_ip = string_to_ip("1.2.3.5"); + + env_set("ethact", "eth2"); + ut_assertok(net_loop(PING)); + + env_set("ethact", "lan0"); + ut_assertok(net_loop(PING)); + env_set("ethact", "lan1"); + ut_assertok(net_loop(PING)); + + env_set("ethact", ""); + + return 0; +} + +DM_TEST(dm_test_dsa, UT_TESTF_SCAN_FDT); diff --git a/test/dm/eth.c b/test/dm/eth.c index fa8a69da701..e4ee6956106 100644 --- a/test/dm/eth.c +++ b/test/dm/eth.c @@ -53,8 +53,8 @@ static int dm_test_eth_alias(struct unit_test_state *uts) ut_assertok(net_loop(PING)); ut_asserteq_str("eth@10004000", env_get("ethact")); - /* Expected to fail since eth2 is not defined in the device tree */ - env_set("ethact", "eth2"); + /* Expected to fail since eth1 is not defined in the device tree */ + env_set("ethact", "eth1"); ut_assertok(net_loop(PING)); ut_asserteq_str("eth@10002000", env_get("ethact")); @@ -227,7 +227,7 @@ static int _dm_test_net_retry(struct unit_test_state *uts) * the active device should be eth0 */ sandbox_eth_disable_response(1, true); - env_set("ethact", "eth@10004000"); + env_set("ethact", "lan1"); env_set("netretry", "yes"); sandbox_eth_skip_timeout(); ut_assertok(net_loop(PING)); @@ -237,11 +237,11 @@ static int _dm_test_net_retry(struct unit_test_state *uts) * eth1 is disabled and netretry is no, so the ping should fail and the * active device should be eth1 */ - env_set("ethact", "eth@10004000"); + env_set("ethact", "lan1"); env_set("netretry", "no"); sandbox_eth_skip_timeout(); ut_asserteq(-ENONET, net_loop(PING)); - ut_asserteq_str("eth@10004000", env_get("ethact")); + ut_asserteq_str("lan1", env_get("ethact")); return 0; } -- cgit v1.3.1 From 80279fa1295af73beba8689450ba408130053ff1 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Sun, 14 Mar 2021 20:15:02 +0800 Subject: dm: core: Correctly read of simple-bus At present we decode simple bus using the following assumption: - parent #address-cells 1 - child #address-cells 1 - child #size-cells 1 However this might not always be the case. Update to use fdt_addr_t and fdt_size_t in 'struct simple_bus_plat', and use fdt_read_ranges() to correctly decode it according to the actual parent and child #address-cells / #size-cells under a Kconfig option CONFIG_SIMPLE_BUS_CORRECT_RANGE which can be turned on for any board that needs it. Signed-off-by: Bin Meng Reviewed-by: Simon Glass Reviewed-by: Priyanka Jain --- drivers/core/Kconfig | 13 +++++++++++++ drivers/core/simple-bus.c | 32 +++++++++++++++++++++++++------- include/dm/simple_bus.h | 6 +++--- 3 files changed, 41 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index 1eccac28c62..c7504edaf85 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -235,6 +235,19 @@ config SPL_SIMPLE_BUS Supports the 'simple-bus' driver, which is used on some systems in SPL. +config SIMPLE_BUS_CORRECT_RANGE + bool "Decode the 'simple-bus' by honoring the #address-cells and #size-cells" + depends on SIMPLE_BUS + help + Decoding the 'simple-bus' by honoring the #address-cells + and #size-cells of parent/child bus. If unset, #address-cells of + parent bus is assumed to be 1, #address-cells and #size-cells of + child bus is also assumed to be 1, to save some spaces of using + an advanced API to decode the , which benefits SPL image + builds that have size limits. + + If you are unsure about this, Say N here. + config SIMPLE_PM_BUS bool "Support simple-pm-bus driver" depends on DM && OF_CONTROL && CLK && POWER_DOMAIN diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c index b0c2c209587..18f52d26df2 100644 --- a/drivers/core/simple-bus.c +++ b/drivers/core/simple-bus.c @@ -4,8 +4,12 @@ */ #include +#include #include #include +#include + +DECLARE_GLOBAL_DATA_PTR; fdt_addr_t simple_bus_translate(struct udevice *dev, fdt_addr_t addr) { @@ -22,16 +26,30 @@ static int simple_bus_post_bind(struct udevice *dev) #if CONFIG_IS_ENABLED(OF_PLATDATA) return 0; #else - u32 cell[3]; + struct simple_bus_plat *plat = dev_get_uclass_plat(dev); int ret; - ret = dev_read_u32_array(dev, "ranges", cell, ARRAY_SIZE(cell)); - if (!ret) { - struct simple_bus_plat *plat = dev_get_uclass_plat(dev); + if (CONFIG_IS_ENABLED(SIMPLE_BUS_CORRECT_RANGE)) { + uint64_t caddr, paddr, len; + + /* only read range index 0 */ + ret = fdt_read_range((void *)gd->fdt_blob, dev_of_offset(dev), + 0, &caddr, &paddr, &len); + if (!ret) { + plat->base = caddr; + plat->target = paddr; + plat->size = len; + } + } else { + u32 cell[3]; - plat->base = cell[0]; - plat->target = cell[1]; - plat->size = cell[2]; + ret = dev_read_u32_array(dev, "ranges", cell, + ARRAY_SIZE(cell)); + if (!ret) { + plat->base = cell[0]; + plat->target = cell[1]; + plat->size = cell[2]; + } } return dm_scan_fdt_dev(dev); diff --git a/include/dm/simple_bus.h b/include/dm/simple_bus.h index 4ad4cc4051d..b7104013c05 100644 --- a/include/dm/simple_bus.h +++ b/include/dm/simple_bus.h @@ -7,9 +7,9 @@ #define __DM_SIMPLE_BUS_H struct simple_bus_plat { - u32 base; - u32 size; - u32 target; + fdt_addr_t base; + fdt_size_t size; + fdt_addr_t target; }; #endif -- cgit v1.3.1 From 6d1ab4a10e3051def7c5d7b522042b84a122f0a1 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Fri, 26 Mar 2021 19:40:58 +0100 Subject: board: sl28: enable DM_SERIAL With all preparations in place, switch over to DM_SERIAL. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/Kconfig | 1 + include/configs/kontron_sl28.h | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fa98c1a6d11..b39b043efe3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1616,6 +1616,7 @@ config TARGET_SL28 select DM_RNG select DM_RTC select DM_SCSI + select DM_SERIAL select DM_SPI select DM_USB select SPL_DM if SPL diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index 5d818a708d0..5f11205802e 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -49,8 +49,6 @@ #define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE /* serial port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -- cgit v1.3.1 From a98550236f803c5a4fb6fe489bc9aff315b388eb Mon Sep 17 00:00:00 2001 From: Mian Yousaf Kaukab Date: Tue, 30 Mar 2021 16:04:14 +0200 Subject: ls1012a: use default scan_dev_for_boot MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit scan_dev_for_efi is supposed to be called from scan_dev_for_boot. However, this call is missing for ls1012a boards. As a result EFI boot doesn’t work. Fix this issue by removing custom definition of scan_dev_for_boot and use the default definition instead. Signed-off-by: Mian Yousaf Kaukab Reviewed-by: Priyanka Jain --- include/configs/ls1012a2g5rdb.h | 7 ------- include/configs/ls1012afrdm.h | 7 ------- include/configs/ls1012afrwy.h | 7 ------- include/configs/ls1012aqds.h | 7 ------- include/configs/ls1012ardb.h | 7 ------- 5 files changed, 35 deletions(-) (limited to 'include') diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index bbc3ffd7f0d..9962b9872af 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -61,13 +61,6 @@ "run scan_dev_for_boot; " \ "fi; " \ "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ "boot_a_script=" \ "load ${devtype} ${devnum}:${distro_bootpart} " \ "${scriptaddr} ${prefix}${script}; " \ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 8de20e3ff45..02dd59892bc 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -47,13 +47,6 @@ "run scan_dev_for_boot; " \ "fi; " \ "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ "installer=load usb 0:2 $load_addr " \ "/flex_installer_arm64.itb; " \ "bootm $load_addr#$board\0" \ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 29c344c63a9..ba152834d5a 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -80,13 +80,6 @@ "run scan_dev_for_boot; " \ "fi; " \ "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ "boot_a_script=" \ "load ${devtype} ${devnum}:${distro_bootpart} " \ "${scriptaddr} ${prefix}${script}; " \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index c4c9b7f5019..36be8f42c97 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -131,13 +131,6 @@ "run scan_dev_for_boot; " \ "fi; " \ "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ "boot_a_script=" \ "load ${devtype} ${devnum}:${distro_bootpart} " \ "${scriptaddr} ${prefix}${script}; " \ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 94e742ee844..582945b2ab1 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -79,13 +79,6 @@ "run scan_dev_for_boot; " \ "fi; " \ "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ "boot_a_script=" \ "load ${devtype} ${devnum}:${distro_bootpart} " \ "${scriptaddr} ${prefix}${script}; " \ -- cgit v1.3.1