From 0d79f4f490352f6e1500cdd12a3b0e8b17265bde Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 18 Jul 2013 12:13:40 -0700 Subject: ARM: tegra: Make cache line size SoC specific Currently all Tegra SoCs are assumed to have 32 byte cache lines. This isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and therefore uses a cache line size of 64 bytes. Move the cache line size setting to the per-SoC common configuration file. Signed-off-by: Thierry Reding Tested-by: Stephen Warren Reviewed-by: Stephen Warren Signed-off-by: Tom Warren --- include/configs/tegra-common.h | 2 -- include/configs/tegra114-common.h | 3 +++ include/configs/tegra20-common.h | 3 +++ include/configs/tegra30-common.h | 3 +++ 4 files changed, 9 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index ccd68a19fd4..0aac14e1c36 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -17,8 +17,6 @@ #define CONFIG_TEGRA /* which is a Tegra generic machine */ #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - #include /* get chip and board defs */ /* diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 44e98e50195..c3de9a999e9 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -18,6 +18,9 @@ #define _TEGRA114_COMMON_H_ #include "tegra-common.h" +/* Cortex-A15 uses a cache line size of 64 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 64 + /* * NS16550 Configuration */ diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index d5e9ee4062e..b009a316b14 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -9,6 +9,9 @@ #define _TEGRA20_COMMON_H_ #include "tegra-common.h" +/* Cortex-A9 uses a cache line size of 32 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Errata configuration */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 5ac88165041..99acbfd28b2 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -9,6 +9,9 @@ #define _TEGRA30_COMMON_H_ #include "tegra-common.h" +/* Cortex-A9 uses a cache line size of 32 bytes */ +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* * Errata configuration */ -- cgit v1.3.1 From e94f0af969f8832fe9acd1af91fa08b88facbd58 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 18 Jul 2013 12:13:41 -0700 Subject: ARM: tegra: Enable data cache on Dalmore Disabling the data cache is no longer required to boot Dalmore, so enable it. This results in notably better performance when loading and booting the Linux kernel. Signed-off-by: Thierry Reding Signed-off-by: Tom Warren --- include/configs/dalmore.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h index 145e7ac926d..bdf012b2b8e 100644 --- a/include/configs/dalmore.h +++ b/include/configs/dalmore.h @@ -21,9 +21,6 @@ #include "tegra114-common.h" -/* Must be off for Dalmore to boot !?!? FIXME */ -#define CONFIG_SYS_DCACHE_OFF - /* Enable fdt support for Dalmore. Flash the image in u-boot-dtb.bin */ #define CONFIG_DEFAULT_DEVICE_TREE tegra114-dalmore #define CONFIG_OF_CONTROL -- cgit v1.3.1 From 8258c126143034bef2e35e01b2e14f2d90a7e0b5 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 14 Aug 2013 10:05:33 -0600 Subject: ARM: tegra: support raw ramdisks This way, we don't have to run mkimage on them. Signed-off-by: Stephen Warren Acked-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 0aac14e1c36..ba6c6bb9f5f 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -133,6 +133,7 @@ #define CONFIG_CMD_GPIO #define CONFIG_CMD_ENTERRCM #define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD /* Defines for SPL */ #define CONFIG_SPL -- cgit v1.3.1 From 0cfb8afed3939e2db4e028a86ea4803f7475941f Mon Sep 17 00:00:00 2001 From: Andreas Wass Date: Fri, 16 Aug 2013 18:24:37 +0200 Subject: ARM: mxs: Add mx28evk_auart_console target The target uses AUART 3 instead of the DUART for console output. Signed-off-by: Andreas Wass Cc: Fabio Estevam Cc: Marek Vasut --- boards.cfg | 1 + include/configs/mxs.h | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/boards.cfg b/boards.cfg index 454da7f974d..79d6cd88cd7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -203,6 +203,7 @@ mx23evk arm arm926ejs mx23evk freesca m28evk arm arm926ejs m28evk denx mxs m28evk mx28evk arm arm926ejs mx28evk freescale mxs mx28evk:ENV_IS_IN_MMC mx28evk_nand arm arm926ejs mx28evk freescale mxs mx28evk:ENV_IS_IN_NAND +mx28evk_auart_console arm arm926ejs mx28evk freescale mxs mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC sc_sps_1 arm arm926ejs sc_sps_1 schulercontrol mxs nhk8815 arm arm926ejs nhk8815 st nomadik nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND diff --git a/include/configs/mxs.h b/include/configs/mxs.h index a684166502f..124dc1e6cbd 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -119,11 +119,16 @@ /* GPIO */ #define CONFIG_MXS_GPIO -/* DUART Serial Driver */ +/* + * DUART Serial Driver. + * Conflicts with AUART driver which can be set by board. + */ +#ifndef CONFIG_MXS_AUART #define CONFIG_PL011_SERIAL #define CONFIG_PL011_CLOCK 24000000 #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } #define CONFIG_CONS_INDEX 0 +#endif /* Default baudrate can be overriden by board! */ #ifndef CONFIG_BAUDRATE #define CONFIG_BAUDRATE 115200 -- cgit v1.3.1 From e08d6f3aaf11e4138de1ed04acccbcf38d04f1b6 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 26 Jun 2013 10:11:06 +0800 Subject: arm: atmel: add gmac support for sama5d3xek board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add gmac support for sama5d3xek board, the gmac embedded in: - sama5d33, sama5d34, sama5d35 Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- arch/arm/cpu/armv7/at91/sama5d3_devices.c | 24 ++++++++++++++++++++++++ arch/arm/include/asm/arch-at91/at91_common.h | 1 + board/atmel/sama5d3xek/sama5d3xek.c | 20 ++++++++++++++++++++ include/configs/sama5d3xek.h | 5 +++++ 4 files changed, 50 insertions(+) (limited to 'include') diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c index 4a3fca56a1a..e55e1c66025 100644 --- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c +++ b/arch/arm/cpu/armv7/at91/sama5d3_devices.c @@ -144,6 +144,30 @@ void at91_macb_hw_init(void) /* Enable clock */ at91_periph_clk_enable(ATMEL_ID_EMAC); } + +void at91_gmac_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */ + + at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */ + + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_GMAC); +} #endif #ifdef CONFIG_LCD diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h index d6597023c6e..9f54fddce51 100644 --- a/arch/arm/include/asm/arch-at91/at91_common.h +++ b/arch/arm/include/asm/arch-at91/at91_common.h @@ -10,6 +10,7 @@ #define AT91_COMMON_H void at91_can_hw_init(void); +void at91_gmac_hw_init(void); void at91_macb_hw_init(void); void at91_mci_hw_init(void); void at91_serial0_hw_init(void); diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index 4a309ad17f5..97caf64d404 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -178,6 +179,8 @@ int board_init(void) #ifdef CONFIG_MACB if (has_emac()) at91_macb_hw_init(); + if (has_gmac()) + at91_gmac_hw_init(); #endif #ifdef CONFIG_LCD if (has_lcdc()) @@ -193,6 +196,21 @@ int dram_init(void) return 0; } +int board_phy_config(struct phy_device *phydev) +{ + /* rx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x2222); + /* tx data delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x2222); + /* rx/tx clock delay */ + ksz9021_phy_extended_write(phydev, + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf2f4); + + return 0; +} + int board_eth_init(bd_t *bis) { int rc = 0; @@ -200,6 +218,8 @@ int board_eth_init(bd_t *bis) #ifdef CONFIG_MACB if (has_emac()) rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); + if (has_gmac()) + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC, 0x00); #endif return rc; diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 10697d627af..3dcf012dd87 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -136,6 +136,11 @@ #define CONFIG_NET_MULTI #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_MACB_SEARCH_PHY +#define CONFIG_RGMII +#define CONFIG_CMD_MII +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_MICREL_KSZ9021 /* MMC */ #define CONFIG_CMD_MMC -- cgit v1.3.1 From ce76f0aac6b340582f9f08cf6c3d063df97e419f Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 26 Jun 2013 10:48:53 +0800 Subject: arm: atmel: add nand trimffs subcommand for at91sam9n12 and at91sam9x5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit as the at91sam9n12 and at91sam9x5 soc support PMECC, when use u-boot to flash the rootfs, in order to avoid flash one sector with all 0xff into NAND, so use nand trimffs subcommand to avoid it Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- include/configs/at91sam9n12ek.h | 3 +++ include/configs/at91sam9x5ek.h | 2 ++ 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index be8a28c3271..28a79258df4 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -122,6 +122,9 @@ #define CONFIG_PMECC_CAP 2 #define CONFIG_PMECC_SECTOR_SIZE 512 #define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000 + +#define CONFIG_CMD_NAND_TRIMFFS + #endif #define CONFIG_MTD_PARTITIONS diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 2b1533c85ac..b866a4b0c38 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -123,6 +123,8 @@ #define CONFIG_PMECC_SECTOR_SIZE 512 #define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000 +#define CONFIG_CMD_NAND_TRIMFFS + #define CONFIG_MTD_DEVICE #define CONFIG_CMD_MTDPARTS #define CONFIG_MTD_PARTITIONS -- cgit v1.3.1 From b2d96dc28ffb2acad250ffb551a442396db83f38 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Wed, 3 Jul 2013 11:11:45 +0800 Subject: ARM: at91: atmel_nand: pmecc driver will select the galois table by sector size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the galois index table offset in chip head file. So user do not need to set by himself. Driver will set it correctly according to sector_size. Signed-off-by: Josh Wu Acked-by: Scott Wood [rebased on master] Signed-off-by: Andreas Bießmann --- arch/arm/include/asm/arch-at91/at91sam9x5.h | 6 ++++++ doc/README.atmel_pmecc | 14 -------------- drivers/mtd/nand/atmel_nand.c | 5 ++++- include/configs/at91sam9x5ek.h | 1 - include/configs/sama5d3xek.h | 1 - 5 files changed, 10 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-at91/at91sam9x5.h b/arch/arm/include/asm/arch-at91/at91sam9x5.h index fcc6fdc2193..a47103851e4 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9x5.h +++ b/arch/arm/include/asm/arch-at91/at91sam9x5.h @@ -161,6 +161,12 @@ #define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP #define ATMEL_ID_UHP ATMEL_ID_UHPHS +/* + * PMECC table in ROM + */ +#define ATMEL_PMECC_INDEX_OFFSET_512 0x8000 +#define ATMEL_PMECC_INDEX_OFFSET_1024 0x10000 + /* * at91sam9x5 specific prototypes */ diff --git a/doc/README.atmel_pmecc b/doc/README.atmel_pmecc index b483744ea59..41f3bd78608 100644 --- a/doc/README.atmel_pmecc +++ b/doc/README.atmel_pmecc @@ -19,17 +19,6 @@ To use PMECC in this driver, the user needs to set: It can be 2, 4, 8, 12 or 24. 2. The PMECC sector size: CONFIG_PMECC_SECTOR_SIZE. It only can be 512 or 1024. - 3. The PMECC index lookup table's offsets in ROM code: CONFIG_PMECC_INDEX_TABLE_OFFSET. - In the chip datasheet section "Boot Stragegies", you can find - two Galois Field Table in the ROM code. One table is for 512-bytes - sector. Another is for 1024-byte sector. Each Galois Field includes - two sub-table: indext table & alpha table. - In the beginning of each Galois Field Table is the index table, - Alpha table is in the following. - So the index table's offset is same as the Galois Field Table. - - Please set CONFIG_PMECC_INDEX_TABLE_OFFSET correctly according the - Galois Field Table's offset base on the sector size you used. Take AT91SAM9X5EK as an example, the board definition file likes: @@ -38,7 +27,4 @@ Take AT91SAM9X5EK as an example, the board definition file likes: #define CONFIG_ATMEL_NAND_HW_PMECC 1 #define CONFIG_PMECC_CAP 2 #define CONFIG_PMECC_SECTOR_SIZE 512 -#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000 -NOTE: If you use 1024 as the sector size, then need set 0x10000 as the - CONFIG_PMECC_INDEX_TABLE_OFFSET diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index f844990e381..304491bcb41 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -637,7 +637,10 @@ static int atmel_pmecc_nand_init_params(struct nand_chip *nand, cap = host->pmecc_corr_cap = CONFIG_PMECC_CAP; sector_size = host->pmecc_sector_size = CONFIG_PMECC_SECTOR_SIZE; - host->pmecc_index_table_offset = CONFIG_PMECC_INDEX_TABLE_OFFSET; + if (host->pmecc_sector_size == 512) + host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_512; + else + host->pmecc_index_table_offset = ATMEL_PMECC_INDEX_OFFSET_1024; MTDDEBUG(MTD_DEBUG_LEVEL1, "Initialize PMECC params, cap: %d, sector: %d\n", diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index b866a4b0c38..c799955ba60 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -121,7 +121,6 @@ #define CONFIG_ATMEL_NAND_HW_PMECC 1 #define CONFIG_PMECC_CAP 2 #define CONFIG_PMECC_SECTOR_SIZE 512 -#define CONFIG_PMECC_INDEX_TABLE_OFFSET 0x8000 #define CONFIG_CMD_NAND_TRIMFFS diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 3dcf012dd87..ab9617eae92 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -126,7 +126,6 @@ #define CONFIG_ATMEL_NAND_HW_PMECC #define CONFIG_PMECC_CAP 4 #define CONFIG_PMECC_SECTOR_SIZE 512 -#define CONFIG_PMECC_INDEX_TABLE_OFFSET ATMEL_PMECC_INDEX_OFFSET_512 #define CONFIG_CMD_NAND_TRIMFFS #endif -- cgit v1.3.1 From 2f96b06be5838bcb5e2ee7cbeba4fe59edfd29b0 Mon Sep 17 00:00:00 2001 From: "Wu, Josh" Date: Wed, 3 Jul 2013 11:11:47 +0800 Subject: linux/compat.h: move dev_err, dev_info and dev_dbg from usb driver to compat.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since kernel code current use many dev_xxx() instead of using printk. To compatible, move those dev_xxx from usb driver to linux/compat.h. Then all driver code can use dev_err, dev_info and dev_vdbg. This patch also removed duplicated macro definitions in usb driver. Signed-off-by: Josh Wu Acked-by: Scott Wood Signed-off-by: Andreas Bießmann --- drivers/usb/musb-new/linux-compat.h | 16 ---------------- include/linux/compat.h | 8 ++++++++ 2 files changed, 8 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/drivers/usb/musb-new/linux-compat.h b/drivers/usb/musb-new/linux-compat.h index 72c8c2bad19..d7a5663deb3 100644 --- a/drivers/usb/musb-new/linux-compat.h +++ b/drivers/usb/musb-new/linux-compat.h @@ -39,15 +39,6 @@ typedef unsigned long dmaaddr_t; #define cpu_relax() do {} while (0) #define pr_debug(fmt, args...) debug(fmt, ##args) -#define dev_dbg(dev, fmt, args...) \ - debug(fmt, ##args) -#define dev_vdbg(dev, fmt, args...) \ - debug(fmt, ##args) -#define dev_info(dev, fmt, args...) \ - printf(fmt, ##args) -#define dev_err(dev, fmt, args...) \ - printf(fmt, ##args) -#define printk printf #define WARN(condition, fmt, args...) ({ \ int ret_warn = !!condition; \ @@ -55,13 +46,6 @@ typedef unsigned long dmaaddr_t; printf(fmt, ##args); \ ret_warn; }) -#define KERN_DEBUG -#define KERN_NOTICE -#define KERN_WARNING -#define KERN_ERR - -#define kfree(ptr) free(ptr) - #define pm_runtime_get_sync(dev) do {} while (0) #define pm_runtime_put(dev) do {} while (0) #define pm_runtime_put_sync(dev) do {} while (0) diff --git a/include/linux/compat.h b/include/linux/compat.h index e1338bf489f..3fdfb399b50 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -3,6 +3,14 @@ #define ndelay(x) udelay(1) +#define dev_dbg(dev, fmt, args...) \ + debug(fmt, ##args) +#define dev_vdbg(dev, fmt, args...) \ + debug(fmt, ##args) +#define dev_info(dev, fmt, args...) \ + printf(fmt, ##args) +#define dev_err(dev, fmt, args...) \ + printf(fmt, ##args) #define printk printf #define KERN_EMERG -- cgit v1.3.1 From 5471c4a862ce8c9e3340501d0f1968cbf1abf56a Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Fri, 9 Aug 2013 15:45:39 +0800 Subject: arm: sama5d3: remove unused define MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The CONFIG_MAX_NAND_CHIPS never used, remove it No where define LCD_TEST_PATTERN, so no need undefine Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- include/configs/sama5d3xek.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index ab9617eae92..43bb16a37b2 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -56,7 +56,6 @@ #define LCD_BPP LCD_COLOR16 #define LCD_OUTPUT_BPP 24 #define CONFIG_LCD_LOGO -#undef LCD_TEST_PATTERN #define CONFIG_LCD_INFO #define CONFIG_LCD_INFO_BELOW_LOGO #define CONFIG_SYS_WHITE_ON_BLACK @@ -112,7 +111,6 @@ #define CONFIG_CMD_NAND #ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_MAX_CHIPS 1 #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -- cgit v1.3.1 From a4c79b3a53c5619ee2ca66f555f6a66ad84d9b0d Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Sun, 11 Aug 2013 14:26:20 +0000 Subject: arm: atmel: sama5d3: fix typo error for CONFIG_ENV_IS_NOWHERE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix typo error for CONFIG_ENV_IS_NOWHERE from CONIG_ENV_IS_NOWHERE Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- include/configs/sama5d3xek.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 43bb16a37b2..409919898eb 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -197,7 +197,7 @@ "bootm 0x22000000 - 0x21000000" #define CONFIG_SYS_MMC_ENV_DEV 0 #else -#define CONIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_NOWHERE #endif #ifdef CONFIG_SYS_USE_MMC -- cgit v1.3.1 From 77461a65380381b322784d03cdae22f916a2e3b4 Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Tue, 13 Aug 2013 14:50:49 +0800 Subject: arm: atmel: remove the config.mk file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit remove the config.mk file move text base define to board config file for following boards - at91sam9m10g45ek - at91sam9x5ek Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- board/atmel/at91sam9m10g45ek/config.mk | 1 - board/atmel/at91sam9x5ek/config.mk | 1 - include/configs/at91sam9m10g45ek.h | 2 ++ include/configs/at91sam9x5ek.h | 2 ++ 4 files changed, 4 insertions(+), 2 deletions(-) delete mode 100644 board/atmel/at91sam9m10g45ek/config.mk delete mode 100644 board/atmel/at91sam9x5ek/config.mk (limited to 'include') diff --git a/board/atmel/at91sam9m10g45ek/config.mk b/board/atmel/at91sam9m10g45ek/config.mk deleted file mode 100644 index 9d3c5ae2777..00000000000 --- a/board/atmel/at91sam9m10g45ek/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x73f00000 diff --git a/board/atmel/at91sam9x5ek/config.mk b/board/atmel/at91sam9x5ek/config.mk deleted file mode 100644 index 6589a12a93c..00000000000 --- a/board/atmel/at91sam9x5ek/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x26f00000 diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 2aea55567da..fc4ecec7ad4 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -13,6 +13,8 @@ #include +#define CONFIG_SYS_TEXT_BASE 0x73f00000 + #define CONFIG_AT91_LEGACY #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index c799955ba60..4a2ac9aabde 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -11,6 +11,8 @@ #include +#define CONFIG_SYS_TEXT_BASE 0x26f00000 + /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -- cgit v1.3.1 From bc6958988726977b4089da1b13f6467e8e28efd2 Mon Sep 17 00:00:00 2001 From: "Jens Scharsig (BuS Elektronik)" Date: Thu, 22 Aug 2013 08:11:23 +0200 Subject: arm: atmel: cpux9k2: board update and enhancement MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - fix adresses in env settings in config header - add missing CONFIG_STANDALONE_LOAD_ADDR to eb_cpux9k2 config header - remove jffs2 support, board doesn't use this anymore - add ubifs support - change sizes and start for partitions Signed-off-by: Jens Scharsig (BuS Elektronik) Signed-off-by: Andreas Bießmann --- include/configs/eb_cpux9k2.h | 62 +++++++++++++++++++++++--------------------- 1 file changed, 32 insertions(+), 30 deletions(-) (limited to 'include') diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h index 247e37b6ddd..ccc7bd0a8aa 100644 --- a/include/configs/eb_cpux9k2.h +++ b/include/configs/eb_cpux9k2.h @@ -39,6 +39,7 @@ #define CONFIG_SYS_TEXT_BASE 0x21f00000 #endif #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ +#define CONFIG_STANDALONE_LOAD_ADDR 0x21000000 #define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */ #define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1 @@ -123,41 +124,40 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP #define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 #define CONFIG_CMD_MII #define CONFIG_CMD_NAND #define CONFIG_CMD_PING -#define CONFIG_I2C_CMD_NO_FLAT #define CONFIG_I2C_CMD_TREE #define CONFIG_CMD_USB #define CONFIG_CMD_FAT - +#define CONFIG_CMD_UBI +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_UBIFS #define CONFIG_SYS_LONGHELP /* - * Filesystems + * MTD defines */ -#define CONFIG_JFFS2_NAND 1 +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE +#define CONFIG_LZO -#ifndef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_OFFSET 0 -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#else -#define MTDIDS_DEFAULT "nor0=0,nand0=1" +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=atmel_nand" #define MTDPARTS_DEFAULT "mtdparts=" \ - "0:" \ - "384k(U-Boot)," \ - "128k(Env)," \ - "128k(Splash)," \ - "4M(Kernel)," \ - "-(FS)" \ + "physmap-flash.0:" \ + "512k(U-Boot)," \ + "128k(Env)," \ + "128k(Splash)," \ + "4M(Kernel)," \ + "384k(MiniFS)," \ + "-(FS)" \ ";" \ - "1:" \ - "-(jffs2)" -#endif /* CONFIG_JFFS2_CMDLINE */ - + "atmel_nand:" \ + "1M(emergency)," \ + "-(data)" /* * Hardware drivers */ @@ -328,7 +328,7 @@ #define CONFIG_BOOTDELAY 5 #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x80000) #define CONFIG_ENV_SIZE 0x20000 /* sectors are 128K here */ #define CONFIG_BAUDRATE 115200 @@ -347,12 +347,14 @@ "displayheight=512\0" \ "displaybsteps=1023\0" \ "ubootaddr=10000000\0" \ - "splashimage=10080000\0" \ - "kerneladdr=100A0000\0" \ + "splashimage=100A0000\0" \ + "kerneladdr=100C0000\0" \ "kernelsize=00400000\0" \ - "rootfsaddr=104A0000\0" \ + "rootfsaddr=10520000\0" \ "copy_addr=21200000\0" \ - "rootfssize=00B60000\0" \ + "rootfssize=00AE0000\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ "bootargsdefaults=set bootargs " \ "console=ttyS0,115200 " \ "video=vcxk_fb:xres:${displaywidth}," \ @@ -373,15 +375,15 @@ "erase $(rootfsaddr) +$(rootfssize);" \ "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \ "\0" \ - "update_uboot=protect off 10000000 1005FFFF;" \ + "update_uboot=protect off 10000000 1007FFFF;" \ "dhcp $(copy_addr) u-boot_eb_cpux9k2;" \ - "erase 10000000 1005FFFF;" \ + "erase 10000000 1007FFFF;" \ "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \ - "protect on 10000000 1005FFFF;reset\0" \ + "protect on 10000000 1007FFFF;reset\0" \ "update_splash=protect off $(splashimage) +20000;" \ "dhcp $(copy_addr) splash_eb_cpux9k2.bmp;" \ "erase $(splashimage) +20000;" \ - "cp.b $(fileaddr) 10080000 $(filesize);" \ + "cp.b $(fileaddr) $(splashimage) $(filesize);" \ "protect on $(splashimage) +20000;reset\0" \ "emergency=run bootargsdefaults;" \ "set bootargs $(bootargs) root=initramfs boot=emergency " \ -- cgit v1.3.1 From 5b47f2d92ba02a5dc2b31a677fd8150ad3c68b6a Mon Sep 17 00:00:00 2001 From: Oleksandr Tyshchenko Date: Tue, 6 Aug 2013 14:03:27 +0300 Subject: sdp4430: Initialize board id using CONFIG_MACH_TYPE Use CONFIG_MACH_TYPE generic macro to set the machine type number in the common arm code instead of setting it in the board code. Signed-off-by: Oleksandr Tyshchenko --- board/ti/sdp4430/sdp.c | 1 - include/configs/omap4_sdp4430.h | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c index 25daaa9ffb1..b20ca9ebfd5 100644 --- a/board/ti/sdp4430/sdp.c +++ b/board/ti/sdp4430/sdp.c @@ -28,7 +28,6 @@ int board_init(void) { gpmc_init(); - gd->bd->bi_arch_number = MACH_TYPE_OMAP_4430SDP; gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */ return 0; diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index 3da78b65750..f40e0b718fc 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -17,6 +17,7 @@ * High Level Configuration Options */ #define CONFIG_4430SDP 1 /* working with SDP */ +#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_4430SDP #include -- cgit v1.3.1 From 372d7fa1bf23a33066a8a88b6fb01ea931ae1b91 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Sun, 11 Aug 2013 18:20:00 +0200 Subject: ARM: igep00x0.h: Enable raw initrd support Now that IGEP base boards default environment use the bootz command to boot a zImage instead of a uImage, it makes sense to add support to supply a raw initrd image to the kernel if needed. Signed-off-by: Javier Martinez Canillas --- include/configs/igep00x0.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/igep00x0.h b/include/configs/igep00x0.h index 722c56652f1..9982cf6e900 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/igep00x0.h @@ -45,6 +45,7 @@ #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ +#define CONFIG_SUPPORT_RAW_INITRD /* * NS16550 Configuration -- cgit v1.3.1 From c27efde68dfd7fd2da364d556d586495e78d3396 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:43 -0400 Subject: am33xx: Correct and expand comments on CONFIG_SPL_MAX_SIZE We had been allowing the max size to be larger than actually allowed by the ROM. Expand the commentary here to explain why we set these locations. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-am33xx/omap.h | 2 +- include/configs/ti_am335x_common.h | 10 ++++++++-- 2 files changed, 9 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 1f8431196f2..225072186db 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -18,7 +18,7 @@ #ifdef CONFIG_AM33XX #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 -#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000 +#define SRAM_SCRATCH_SPACE_ADDR 0x4030B800 #elif defined(CONFIG_TI81XX) #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index fd3ffab015b..0eae9c8105a 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -41,9 +41,15 @@ #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_NET_RETRY_COUNT 10 -/* SPL defines. */ +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x402F0400 and 0x4030B800 as a download area and + * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also + * supports X-MODEM loading via UART, and we leverage this and then use + * Y-MODEM to load u-boot.img, when booted over UART. + */ #define CONFIG_SPL_TEXT_BASE 0x402F0400 -#define CONFIG_SPL_MAX_SIZE (0x4030C000 - CONFIG_SPL_TEXT_BASE) +#define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_YMODEM_SUPPORT /* -- cgit v1.3.1 From a7142dd0963d44d446cf4be5ba710a04c2223e86 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:44 -0400 Subject: TI:armv7: Move CONFIG_SPL_LIBDISK_SUPPORT to MMC section We only need this library when we're doing "disk" access to MMC/SD. Update comment around the rest of CONFIG_SPL_LIB* to note that the others are always required. Signed-off-by: Tom Rini --- include/configs/ti_armv7_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index e0ab6912baf..1e4bca55a46 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -223,14 +223,14 @@ #endif #ifdef CONFIG_MMC +#define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SPL_FAT_SUPPORT #endif -/* General parts of the framework. */ +/* General parts of the framework, required. */ #define CONFIG_SPL_I2C_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT -- cgit v1.3.1 From c3799fceda6c37ad04bd62b6dd0db6225c11626b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:45 -0400 Subject: omap5: Expand CONFIG_SPL_MAX_SIZE and comment upon SRAM_SCRATCH_SPACE_ADDR After examining both TRMs and doing some experimentation, we can rely on using the start of the download area for CONFIG_SPL_TEXT_BASE and then move SRAM_SCRATCH_SPACE_ADDR up, just like am335x. This is required for peripheral boot modes such as UART. Signed-off-by: Tom Rini --- arch/arm/include/asm/arch-omap5/omap.h | 11 ++++++++++- include/configs/omap5_common.h | 4 ++-- 2 files changed, 12 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 597c692b97c..e9a51d34038 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -153,6 +153,15 @@ struct s32ktimer { #define EFUSE_4 0x45145100 #endif /* __ASSEMBLY__ */ +/* + * In all cases, the TRM defines the RAM Memory Map for the processor + * and indicates the area for the downloaded image. We use all of that + * space for download and once up and running may use other parts of the + * map for our needs. We set a scratch space that is at the end of the + * OMAP5 download area, but within the DRA7xx download area (as it is + * much larger) and do not, at this time, make use of the additional + * space. + */ #ifdef CONFIG_DRA7XX #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */ @@ -160,7 +169,7 @@ struct s32ktimer { #define NON_SECURE_SRAM_START 0x40300000 #define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */ #endif -#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START +#define SRAM_SCRATCH_SPACE_ADDR 0x4031E000 /* base address for indirect vectors (internal boot mode) */ #define SRAM_ROM_VECT_BASE 0x4031F000 diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 8e82fed2347..0345c577dc7 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -128,8 +128,8 @@ /* Defines for SPL */ -#define CONFIG_SPL_TEXT_BASE 0x40300350 -#define CONFIG_SPL_MAX_SIZE 0x19000 /* 100K */ +#define CONFIG_SPL_TEXT_BASE 0x40300000 +#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_DISPLAY_PRINT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" -- cgit v1.3.1 From a7a0640085ac7a47091471034553f9b619053654 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:46 -0400 Subject: TI:am335x: Better comment and organize the networking related options While in here, drop CONFIG_BOOTP_DEFAULT as it is unused in the code. Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 11 +++++++++-- include/configs/ti_am335x_common.h | 11 +++++------ 2 files changed, 14 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index e0a87f8bc4d..5ed1dca2a85 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -228,17 +228,24 @@ /* SPL */ #ifndef CONFIG_NOR_BOOT #define CONFIG_SPL_YMODEM_SUPPORT + +/* CPSW support */ +#define CONFIG_SPL_ETH_SUPPORT + +/* USB gadget RNDIS */ +#define CONFIG_SPL_MUSB_NEW_SUPPORT + +/* General network SPL, both CPSW and USB gadget RNDIS */ #define CONFIG_SPL_NET_SUPPORT #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" -#define CONFIG_SPL_ETH_SUPPORT + #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_BUS 0 #define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 -#define CONFIG_SPL_MUSB_NEW_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" #ifdef CONFIG_NAND diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 0eae9c8105a..837c02cc29f 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -28,18 +28,17 @@ #define CONFIG_SYS_NS16550_CLK 48000000 /* Network defines. */ -#define CONFIG_CMD_NET +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_DRIVER_TI_CPSW -#define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ /* * SPL related defines. The Public RAM memory map the ROM defines the -- cgit v1.3.1 From 610af383f13934f039e401e6adbee527ae645b06 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:47 -0400 Subject: am335x_evm: Add comment by SPL SPI support Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 5ed1dca2a85..4e6429c7c8a 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -240,12 +240,14 @@ #define CONFIG_SPL_ENV_SUPPORT #define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" +/* SPI flash. */ #define CONFIG_SPL_SPI_SUPPORT #define CONFIG_SPL_SPI_FLASH_SUPPORT #define CONFIG_SPL_SPI_LOAD #define CONFIG_SPL_SPI_BUS 0 #define CONFIG_SPL_SPI_CS 0 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" #ifdef CONFIG_NAND -- cgit v1.3.1 From 85a02aa9ccf3757c09e56e06926024cec6d9cfa0 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:48 -0400 Subject: am335x_evm: Regroup USB options Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 80 +++++++++++++++++++++++--------------------- 1 file changed, 41 insertions(+), 39 deletions(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 4e6429c7c8a..eae5a19f2ab 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -171,44 +171,6 @@ "run mmcboot;" \ "run nandboot;" -/* USB Composite download gadget - g_dnl */ -#define CONFIG_USB_GADGET -#define CONFIG_USBDOWNLOAD_GADGET - -/* USB TI's IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x0403 -#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 -#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" - -/* USB Device Firmware Update support */ -#define CONFIG_DFU_FUNCTION -#define CONFIG_DFU_MMC -#define CONFIG_CMD_DFU -#define DFU_ALT_INFO_MMC \ - "boot part 0 1;" \ - "rootfs part 0 2;" \ - "MLO fat 0 1;" \ - "MLO.raw mmc 100 100;" \ - "u-boot.img.raw mmc 300 400;" \ - "spl-os-args.raw mmc 80 80;" \ - "spl-os-image.raw mmc 900 2000;" \ - "spl-os-args fat 0 1;" \ - "spl-os-image fat 0 1;" \ - "u-boot.img fat 0 1;" \ - "uEnv.txt fat 0 1" -#ifdef CONFIG_NAND -#define CONFIG_DFU_NAND -#define DFU_ALT_INFO_NAND \ - "SPL part 0 1;" \ - "SPL.backup1 part 0 2;" \ - "SPL.backup2 part 0 3;" \ - "SPL.backup3 part 0 4;" \ - "u-boot part 0 5;" \ - "u-boot-spl-os part 0 6;" \ - "kernel part 0 8;" \ - "rootfs part 0 9" -#endif - /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ @@ -283,13 +245,19 @@ #endif /* - * USB configuration + * USB configuration. We enable MUSB support, both for host and for + * gadget. We set USB0 as peripheral and USB1 as host, based on the + * board schematic and physical port wired to each. Then for host we + * add mass storage support and for gadget we add both RNDIS ethernet + * and DFU. */ #define CONFIG_USB_MUSB_DSPS #define CONFIG_ARCH_MISC_INIT #define CONFIG_MUSB_GADGET #define CONFIG_MUSB_PIO_ONLY #define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_USB_GADGET +#define CONFIG_USBDOWNLOAD_GADGET #define CONFIG_USB_GADGET_DUALSPEED #define CONFIG_USB_GADGET_VBUS_DRAW 2 #define CONFIG_MUSB_HOST @@ -307,6 +275,11 @@ #define CONFIG_USB_ETHER #define CONFIG_USB_ETH_RNDIS #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" + +/* USB TI's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x0403 +#define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 +#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" #endif /* CONFIG_MUSB_GADGET */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) @@ -318,6 +291,35 @@ #undef CONFIG_SPL_ETH_SUPPORT #endif +/* USB Device Firmware Update support */ +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_CMD_DFU +#define DFU_ALT_INFO_MMC \ + "boot part 0 1;" \ + "rootfs part 0 2;" \ + "MLO fat 0 1;" \ + "MLO.raw mmc 100 100;" \ + "u-boot.img.raw mmc 300 400;" \ + "spl-os-args.raw mmc 80 80;" \ + "spl-os-image.raw mmc 900 2000;" \ + "spl-os-args fat 0 1;" \ + "spl-os-image fat 0 1;" \ + "u-boot.img fat 0 1;" \ + "uEnv.txt fat 0 1" +#ifdef CONFIG_NAND +#define CONFIG_DFU_NAND +#define DFU_ALT_INFO_NAND \ + "SPL part 0 1;" \ + "SPL.backup1 part 0 2;" \ + "SPL.backup2 part 0 3;" \ + "SPL.backup3 part 0 4;" \ + "u-boot part 0 5;" \ + "u-boot-spl-os part 0 6;" \ + "kernel part 0 8;" \ + "rootfs part 0 9" +#endif + /* * Default to using SPI for environment, etc. * 0x000000 - 0x020000 : SPL (128KiB) -- cgit v1.3.1 From 1dd44e5a4a7ed4b723f2907eb832e65047107255 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:49 -0400 Subject: TI:armv7: Re-order slightly the generic CONFIG options, expand related comments Re-group the general options to note things that can be removed safely to reduce binary size when not required, and expand the comment about what commands we do include to note it could be replaced with a specific list of required one. While at it, move the CMD parts of various blocks IP to the end of the list for consistency. Signed-off-by: Tom Rini --- include/configs/ti_armv7_common.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index 1e4bca55a46..e89e8744df4 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -60,12 +60,12 @@ /* I2C IP block */ #define CONFIG_I2C -#define CONFIG_CMD_I2C #define CONFIG_HARD_I2C #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_I2C_MULTI_BUS #define CONFIG_DRIVER_OMAP24XX_I2C +#define CONFIG_CMD_I2C /* MMC/SD IP block */ #define CONFIG_MMC @@ -87,10 +87,10 @@ * access CS0 at is 0x8000000. */ #ifdef CONFIG_NAND -#define CONFIG_CMD_NAND #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_BASE 0x8000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_CMD_NAND #endif /* @@ -103,14 +103,18 @@ * console baudrate of 115200 and use the default baud rate table. */ #define CONFIG_SYS_MALLOC_LEN (1024 << 10) -#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_BAUDRATE 115200 +#define CONFIG_ENV_VARS_UBOOT_CONFIG /* Strongly encouraged */ +#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ + +/* As stated above, the following choices are optional. */ +#define CONFIG_SYS_LONGHELP #define CONFIG_AUTO_COMPLETE #define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_PROMPT "U-Boot# " #define CONFIG_VERSION_VARIABLE -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_BAUDRATE 115200 /* We set the max number of command args high to avoid HUSH bugs. */ #define CONFIG_SYS_MAXARGS 64 @@ -123,9 +127,6 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_CONSOLE_INFO_QUIET - /* * When we have SPI, NOR or NAND flash we expect to be making use of * mtdparts, both for ease of use in U-Boot and for passing information @@ -141,7 +142,8 @@ * useful commands. Note that we must have set CONFIG_SYS_NO_FLASH * prior to this include, in order to skip a few commands. When we do * have flash, if we expect these commands they must be enabled in that - * config. + * config. If desired, a specific list of desired commands can be used + * instead. */ #include #define CONFIG_CMD_ASKENV -- cgit v1.3.1 From 78c392f143260a5ea2a4cb1051eae13611858036 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:51 -0400 Subject: TI:am33xx: Move SPL YMODEM support to the per-board config Signed-off-by: Tom Rini --- include/configs/ti_am335x_common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 837c02cc29f..d2e34aeed48 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -49,7 +49,6 @@ */ #define CONFIG_SPL_TEXT_BASE 0x402F0400 #define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_YMODEM_SUPPORT /* * Since SPL did pll and ddr initialization for us, -- cgit v1.3.1 From 078aa4f1310f88aaf9727fc5eb0b493d4fe232a9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:52 -0400 Subject: TI:omap5: Clarify comments about SPL and DDR timings in common config Signed-off-by: Tom Rini --- include/configs/omap5_common.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 0345c577dc7..98ba559c86d 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -28,9 +28,12 @@ /* Use General purpose timer 1 */ #define CONFIG_SYS_TIMERBASE GPT2_BASE +/* + * For the DDR timing information we can either dynamically determine + * the timings to use or use pre-determined timings (based on using the + * dynamic method. Default to the static timing infomation. + */ #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - -/* Defines for SDRAM init */ #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS @@ -127,7 +130,13 @@ "fi" -/* Defines for SPL */ +/* + * SPL related defines. The Public RAM memory map the ROM defines the + * area between 0x40300000 and 0x4031E000 as a download area for OMAP5 + * (dra7xx is larger, but we do not need to be larger at this time). We + * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and + * print some information. + */ #define CONFIG_SPL_TEXT_BASE 0x40300000 #define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_DISPLAY_PRINT -- cgit v1.3.1 From 318aeb46493bb7f8b139aba6e084cb4bc2f70533 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:53 -0400 Subject: omap5_uevm: Better comment why we have TCA642X and the reset time Signed-off-by: Tom Rini --- include/configs/omap5_uevm.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h index d10c2b56f94..39487097981 100644 --- a/include/configs/omap5_uevm.h +++ b/include/configs/omap5_uevm.h @@ -35,12 +35,15 @@ #define CONFIG_PARTITION_UUIDS #define CONFIG_CMD_PART +/* Required support for the TCA642X GPIO we have on the uEVM */ #define CONFIG_TCA642X #define CONFIG_CMD_TCA642X #define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 #define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 #define CONSOLEDEV "ttyO2" + +/* Max time to hold reset on this board, see doc/README.omap-reset-time */ #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 16296 #include -- cgit v1.3.1 From 457bb50560c983fc69090dad1fb16b128e88a520 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 20 Aug 2013 08:53:54 -0400 Subject: dra7xx_evm: Re-order and comment the networking related config options Signed-off-by: Tom Rini --- include/configs/dra7xx_evm.h | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index 58786ffa912..4fbe768cbc7 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -26,21 +26,19 @@ #include /* CPSW Ethernet */ -#define CONFIG_CMD_NET +#define CONFIG_CMD_NET /* 'bootp' and 'tftp' */ #define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII -#define CONFIG_DRIVER_TI_CPSW -#define CONFIG_MII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ #define CONFIG_BOOTP_DNS2 #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_NET_MULTI -#define CONFIG_PHY_GIGE +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ +#define CONFIG_MII /* Required in net/eth.c */ +#define CONFIG_PHY_GIGE /* per-board part of CPSW */ #define CONFIG_PHYLIB #define CONFIG_PHY_ADDR 2 -- cgit v1.3.1 From b26354cfd5371759f93224b8b69335e160bcc686 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 19 Aug 2013 16:39:00 +0200 Subject: video: add formike lcd panel init Signed-off-by: Heiko Schocher Cc: Anatolij Gustschin Cc: Tom Rini Acked-by: Anatolij Gustschin --- drivers/video/Makefile | 1 + drivers/video/formike.c | 511 ++++++++++++++++++++++++++++++++++++++++++++++++ include/video.h | 4 + 3 files changed, 516 insertions(+) create mode 100644 drivers/video/formike.c (limited to 'include') diff --git a/drivers/video/Makefile b/drivers/video/Makefile index f1fb26c1804..ede1d1a5311 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_VIDEO_SM501) += sm501.o COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o COBJS-$(CONFIG_VIDEO_TEGRA) += tegra.o COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o +COBJS-$(CONFIG_FORMIKE) += formike.o COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) diff --git a/drivers/video/formike.c b/drivers/video/formike.c new file mode 100644 index 00000000000..b9b68221387 --- /dev/null +++ b/drivers/video/formike.c @@ -0,0 +1,511 @@ +/* + * LCD: Formike, TFT 4.3", 480x800, RGB24, KWH043ST20-F01, DriverIC NT35510-16 + * LCD initialization via SPI + * + * SPDX-License-Identifier: GPL-2.0 + * Based on: + * + */ +#include +#include +#include + +#define TAG_READ 0x80 +#define TAG_WRITE 0x00 + +#define TAG_DATA 0x40 +#define TAG_COMMAND 0x00 + +#define TAG_ADDR_H 0x20 +#define TAG_ADDR_L 0x00 + +static int spi_write_tag_val(struct spi_slave *spi, unsigned char tag, + unsigned char val) +{ + unsigned long flags = SPI_XFER_BEGIN; + u8 buf[2]; + int ret; + + buf[0] = tag; + buf[1] = val; + flags |= SPI_XFER_END; + + ret = spi_xfer(spi, 16, buf, NULL, flags); +#ifdef KWH043ST20_F01_SPI_DEBUG + printf("spi_write_tag_val: tag=%02X, val=%02X ret: %d\n", + tag, val, ret); +#endif /* KWH043ST20_F01_SPI_DEBUG */ + if (ret) + debug("%s: Failed to send: %d\n", __func__, ret); + + return ret; +} + +static void spi_write_dat(struct spi_slave *spi, unsigned int val) +{ + spi_write_tag_val(spi, TAG_WRITE|TAG_DATA, val); +} + +static void spi_write_com(struct spi_slave *spi, unsigned int addr) +{ + spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_H, + (addr & 0xff00) >> 8); + spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_L, + (addr & 0x00ff) >> 0); +} + +int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) +{ + struct spi_slave *spi; + int ret; + + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + debug("%s: Failed to set up slave\n", __func__); + return -1; + } + + ret = spi_claim_bus(spi); + if (ret) { + debug("%s: Failed to claim SPI bus: %d\n", __func__, ret); + goto err_claim_bus; + } + + + /* LV2 Page 1 enable */ + spi_write_com(spi, 0xF000); spi_write_dat(spi, 0x55); + spi_write_com(spi, 0xF001); spi_write_dat(spi, 0xAA); + spi_write_com(spi, 0xF002); spi_write_dat(spi, 0x52); + spi_write_com(spi, 0xF003); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xF004); spi_write_dat(spi, 0x01); + + /* AVDD Set AVDD 5.2V */ + spi_write_com(spi, 0xB000); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB001); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB002); spi_write_dat(spi, 0x0D); + + /* AVDD ratio */ + spi_write_com(spi, 0xB600); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB601); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB602); spi_write_dat(spi, 0x34); + + /* AVEE -5.2V */ + spi_write_com(spi, 0xB100); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB101); spi_write_dat(spi, 0x0D); + spi_write_com(spi, 0xB102); spi_write_dat(spi, 0x0D); + + /* AVEE ratio */ + spi_write_com(spi, 0xB700); spi_write_dat(spi, 0x35); + spi_write_com(spi, 0xB701); spi_write_dat(spi, 0x35); + spi_write_com(spi, 0xB702); spi_write_dat(spi, 0x35); + + /* VCL -2.5V */ + spi_write_com(spi, 0xB200); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xB201); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xB202); spi_write_dat(spi, 0x00); + + /* VCL ratio */ + spi_write_com(spi, 0xB800); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xB801); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xB802); spi_write_dat(spi, 0x24); + + /* VGH 15V */ + spi_write_com(spi, 0xBF00); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xB300); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xB301); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xB302); spi_write_dat(spi, 0x08); + + /* VGH ratio */ + spi_write_com(spi, 0xB900); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB901); spi_write_dat(spi, 0x34); + spi_write_com(spi, 0xB902); spi_write_dat(spi, 0x34); + + /* VGLX ratio */ + spi_write_com(spi, 0xBA00); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xBA01); spi_write_dat(spi, 0x24); + spi_write_com(spi, 0xBA02); spi_write_dat(spi, 0x24); + + /* VGMP/VGSP 4.7V/0V */ + spi_write_com(spi, 0xBC00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBC01); spi_write_dat(spi, 0x88); + spi_write_com(spi, 0xBC02); spi_write_dat(spi, 0x00); + + /* VGMN/VGSN -4.7V/0V */ + spi_write_com(spi, 0xBD00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBD01); spi_write_dat(spi, 0x88); + spi_write_com(spi, 0xBD02); spi_write_dat(spi, 0x00); + + /* VCOM 1.525V */ + spi_write_com(spi, 0xBE00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBE01); spi_write_dat(spi, 0x7A); + + /* Gamma Setting */ + spi_write_com(spi, 0xD100); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD101); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD102); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD103); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD104); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD105); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD106); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD107); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD108); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD109); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD10A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD10B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD10C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD10D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD10E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD10F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD110); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD111); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD112); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD113); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD114); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD115); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD116); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD117); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD118); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD119); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD11A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD11B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD11C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD11D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD11E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD11F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD120); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD121); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD122); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD123); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD124); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD125); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD126); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD127); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD128); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD129); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD12A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD12B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD12C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD12D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD12E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD12F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD130); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD131); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD132); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD133); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD200); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD201); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD202); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD203); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD204); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD205); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD206); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD207); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD208); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD209); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD20A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD20B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD20C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD20D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD20E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD20F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD210); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD211); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD212); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD213); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD214); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD215); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD216); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD217); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD218); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD219); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD21A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD21B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD21C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD21D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD21E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD21F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD220); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD221); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD222); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD223); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD224); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD225); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD226); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD227); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD228); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD229); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD22A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD22B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD22C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD22D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD22E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD22F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD230); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD231); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD232); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD233); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD300); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD301); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD302); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD303); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD304); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD305); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD306); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD307); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD308); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD309); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD30A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD30B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD30C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD30D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD30E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD30F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD310); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD311); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD312); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD313); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD314); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD315); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD316); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD317); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD318); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD319); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD31A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD31B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD31C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD31D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD31E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD31F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD320); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD321); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD322); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD323); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD324); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD325); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD326); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD327); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD328); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD329); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD32A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD32B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD32C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD32D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD32E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD32F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD330); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD331); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD332); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD333); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD400); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD401); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD402); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD403); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD404); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD405); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD406); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD407); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD408); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD409); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD40A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD40B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD40C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD40D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD40E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD40F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD410); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD411); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD412); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD413); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD414); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD415); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD416); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD417); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD418); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD419); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD41A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD41B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD41C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD41D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD41E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD41F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD420); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD421); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD422); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD423); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD424); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD425); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD426); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD427); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD428); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD429); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD42A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD42B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD42C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD42D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD42E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD42F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD430); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD431); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD432); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD433); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD500); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD501); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD502); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD503); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD504); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD505); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD506); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD507); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD508); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD509); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD50A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD50B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD50C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD50D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD50E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD50F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD510); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD511); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD512); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD513); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD514); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD515); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD516); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD517); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD518); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD519); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD51A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD51B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD51C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD51D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD51E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD51F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD520); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD521); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD522); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD523); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD524); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD525); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD526); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD527); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD528); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD529); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD52A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD52B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD52C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD52D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD52E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD52F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD530); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD531); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD532); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD533); spi_write_dat(spi, 0xFF); + + spi_write_com(spi, 0xD600); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD601); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xD602); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD603); spi_write_dat(spi, 0x15); + spi_write_com(spi, 0xD604); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD605); spi_write_dat(spi, 0x30); + spi_write_com(spi, 0xD606); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD607); spi_write_dat(spi, 0x47); + spi_write_com(spi, 0xD608); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD609); spi_write_dat(spi, 0x5B); + spi_write_com(spi, 0xD60A); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD60B); spi_write_dat(spi, 0x7D); + spi_write_com(spi, 0xD60C); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD60D); spi_write_dat(spi, 0x9D); + spi_write_com(spi, 0xD60E); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD60F); spi_write_dat(spi, 0xCC); + spi_write_com(spi, 0xD610); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xD611); spi_write_dat(spi, 0xF3); + spi_write_com(spi, 0xD612); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD613); spi_write_dat(spi, 0x32); + spi_write_com(spi, 0xD614); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD615); spi_write_dat(spi, 0x63); + spi_write_com(spi, 0xD616); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD617); spi_write_dat(spi, 0xB1); + spi_write_com(spi, 0xD618); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD619); spi_write_dat(spi, 0xF0); + spi_write_com(spi, 0xD61A); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xD61B); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD61C); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD61D); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD61E); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD61F); spi_write_dat(spi, 0x67); + spi_write_com(spi, 0xD620); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD621); spi_write_dat(spi, 0x90); + spi_write_com(spi, 0xD622); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD623); spi_write_dat(spi, 0xCB); + spi_write_com(spi, 0xD624); spi_write_dat(spi, 0x02); + spi_write_com(spi, 0xD625); spi_write_dat(spi, 0xF2); + spi_write_com(spi, 0xD626); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD627); spi_write_dat(spi, 0x2A); + spi_write_com(spi, 0xD628); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD629); spi_write_dat(spi, 0x51); + spi_write_com(spi, 0xD62A); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD62B); spi_write_dat(spi, 0x80); + spi_write_com(spi, 0xD62C); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD62D); spi_write_dat(spi, 0x9F); + spi_write_com(spi, 0xD62E); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD62F); spi_write_dat(spi, 0xBE); + spi_write_com(spi, 0xD630); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD631); spi_write_dat(spi, 0xF9); + spi_write_com(spi, 0xD632); spi_write_dat(spi, 0x03); + spi_write_com(spi, 0xD633); spi_write_dat(spi, 0xFF); + + /* LV2 Page 0 enable */ + spi_write_com(spi, 0xF000); spi_write_dat(spi, 0x55); + spi_write_com(spi, 0xF001); spi_write_dat(spi, 0xAA); + spi_write_com(spi, 0xF002); spi_write_dat(spi, 0x52); + spi_write_com(spi, 0xF003); spi_write_dat(spi, 0x08); + spi_write_com(spi, 0xF004); spi_write_dat(spi, 0x00); + + /* Display control */ + spi_write_com(spi, 0xB100); spi_write_dat(spi, 0xFC); + spi_write_com(spi, 0xB101); spi_write_dat(spi, 0x00); + + /* Source hold time */ + spi_write_com(spi, 0xB600); spi_write_dat(spi, 0x05); + + /* Gate EQ control */ + spi_write_com(spi, 0xB700); spi_write_dat(spi, 0x70); + spi_write_com(spi, 0xB701); spi_write_dat(spi, 0x70); + + /* Source EQ control (Mode 2) */ + spi_write_com(spi, 0xB800); spi_write_dat(spi, 0x01); + spi_write_com(spi, 0xB801); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xB802); spi_write_dat(spi, 0x05); + spi_write_com(spi, 0xB803); spi_write_dat(spi, 0x05); + + /* Inversion mode (Column) */ + spi_write_com(spi, 0xBC00); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBC01); spi_write_dat(spi, 0x00); + spi_write_com(spi, 0xBC02); spi_write_dat(spi, 0x00); + + /* Timing control 8phase dual side/4H/4delay/RST_EN */ + spi_write_com(spi, 0xC900); spi_write_dat(spi, 0xD0); + spi_write_com(spi, 0xC901); spi_write_dat(spi, 0x82); + spi_write_com(spi, 0xC902); spi_write_dat(spi, 0x50); + spi_write_com(spi, 0xC903); spi_write_dat(spi, 0x50); + spi_write_com(spi, 0xC904); spi_write_dat(spi, 0x50); + + spi_write_com(spi, 0x3A00); spi_write_dat(spi, 0x55); + mdelay(120); + spi_write_com(spi, 0x1100); + mdelay(120); + spi_write_com(spi, 0x2900); + mdelay(120); + /* spi_write_com(spi, 0x2100); spi_write_dat(spi, 0x00); */ + spi_write_com(spi, 0x2C00); + + return 0; +err_claim_bus: + spi_free_slave(spi); + return -1; +} diff --git a/include/video.h b/include/video.h index f7e27f8477b..0ff857bc9f5 100644 --- a/include/video.h +++ b/include/video.h @@ -63,4 +63,8 @@ void video_position_cursor(unsigned col, unsigned row); /* Clear the display */ void video_clear(void); +#if defined(CONFIG_FORMIKE) +int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode); +#endif #endif -- cgit v1.3.1 From c0dcece7d9925506a950e45028cbd25614aad791 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 19 Aug 2013 16:39:01 +0200 Subject: arm, am335x: add support for 3 siemens boards add support for the am335x based boards from siemens: dxr2: - DDR3 128MiB - NAND 256MiB - Ethernet with external Switch SMSC LAN9303 - no PMIC - internal Watchdog - DFU support pxm2: - DDR2 512 MiB - NAND 1024 MiB - PMIC - PHY atheros ar803x - USB Host - internal Watchdog - DFU support rut: - DDR3 256 MiB - NAND 256 MiB - PMIC - PHY natsemi dp83630 - external Watchdog - DFU support Signed-off-by: Heiko Schocher Signed-off-by: Roger Meier Signed-off-by: Samuel Egli Cc: Pascal Bach Cc: Tom Rini --- MAINTAINERS | 5 + board/siemens/common/board.c | 171 ++++++++++++ board/siemens/common/factoryset.c | 284 ++++++++++++++++++++ board/siemens/common/factoryset.h | 27 ++ board/siemens/dxr2/Makefile | 49 ++++ board/siemens/dxr2/board.c | 241 +++++++++++++++++ board/siemens/dxr2/board.h | 69 +++++ board/siemens/dxr2/mux.c | 112 ++++++++ board/siemens/pxm2/Makefile | 49 ++++ board/siemens/pxm2/board.c | 429 ++++++++++++++++++++++++++++++ board/siemens/pxm2/board.h | 22 ++ board/siemens/pxm2/mux.c | 186 +++++++++++++ board/siemens/pxm2/pmic.h | 71 +++++ board/siemens/rut/Makefile | 49 ++++ board/siemens/rut/board.c | 432 ++++++++++++++++++++++++++++++ board/siemens/rut/board.h | 22 ++ board/siemens/rut/mux.c | 347 ++++++++++++++++++++++++ boards.cfg | 3 + include/configs/dxr2.h | 94 +++++++ include/configs/pxm2.h | 153 +++++++++++ include/configs/rut.h | 156 +++++++++++ include/configs/siemens-am33x-common.h | 463 +++++++++++++++++++++++++++++++++ tools/logos/siemens.bmp | Bin 0 -> 25766 bytes 23 files changed, 3434 insertions(+) create mode 100644 board/siemens/common/board.c create mode 100644 board/siemens/common/factoryset.c create mode 100644 board/siemens/common/factoryset.h create mode 100644 board/siemens/dxr2/Makefile create mode 100644 board/siemens/dxr2/board.c create mode 100644 board/siemens/dxr2/board.h create mode 100644 board/siemens/dxr2/mux.c create mode 100644 board/siemens/pxm2/Makefile create mode 100644 board/siemens/pxm2/board.c create mode 100644 board/siemens/pxm2/board.h create mode 100644 board/siemens/pxm2/mux.c create mode 100644 board/siemens/pxm2/pmic.h create mode 100644 board/siemens/rut/Makefile create mode 100644 board/siemens/rut/board.c create mode 100644 board/siemens/rut/board.h create mode 100644 board/siemens/rut/mux.c create mode 100644 include/configs/dxr2.h create mode 100644 include/configs/pxm2.h create mode 100644 include/configs/rut.h create mode 100644 include/configs/siemens-am33x-common.h create mode 100644 tools/logos/siemens.bmp (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 23965a8d335..d4af7bc87e2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1087,6 +1087,11 @@ Sergey Yanovich lp8x4x xscale/pxa +Roger Meier + dxr2 ARM ARMV7 (AM335x SoC) + pxm2 ARM ARMV7 (AM335x SoC) + rut ARM ARMV7 (AM335x SoC) + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c new file mode 100644 index 00000000000..6279c3281ce --- /dev/null +++ b/board/siemens/common/board.c @@ -0,0 +1,171 @@ +/* + * Common board functions for siemens AM335X based boards + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/board/ti/am335x/board.c + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../common/factoryset.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +void set_uart_mux_conf(void) +{ + enable_uart0_pin_mux(); +} + +void set_mux_conf_regs(void) +{ + /* Initalize the board header */ + enable_i2c0_pin_mux(); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + enable_board_pin_mux(); +} + +void sdram_init(void) +{ + spl_siemens_board_init(); + board_init_ddr(); + + return; +} +#endif /* #ifdef CONFIG_SPL_BUILD */ + +#ifndef CONFIG_SPL_BUILD +/* + * Basic board specific setup. Pinmux has been handled already. + */ +int board_init(void) +{ +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif /* defined(CONFIG_HW_WATCHDOG) */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + if (read_eeprom() < 0) + puts("Could not get board ID.\n"); + + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_FACTORYSET + factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR); +#endif + gpmc_init(); + +#ifdef CONFIG_VIDEO + board_video_init(); +#endif + + return 0; +} +#endif /* #ifndef CONFIG_SPL_BUILD */ + +#define OSC (V_OSCK/1000000) +const struct dpll_params dpll_ddr = { + DDR_PLL_FREQ, OSC-1, 1, -1, -1, -1, -1}; + +const struct dpll_params *get_dpll_ddr_params(void) +{ + return &dpll_ddr; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + omap_nand_switch_ecc(1, 8); + + return 0; +} +#endif + +#ifndef CONFIG_SPL_BUILD +#if defined(BOARD_DFU_BUTTON_GPIO) +/* + * This command returns the status of the user button on + * Input - none + * Returns - 1 if button is held down + * 0 if button is not held down + */ +static int +do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int button = 0; + int gpio; + + gpio = BOARD_DFU_BUTTON_GPIO; + gpio_request(gpio, "DFU"); + gpio_direction_input(gpio); + if (gpio_get_value(gpio)) + button = 1; + else + button = 0; + + gpio_free(gpio); + if (!button) { + /* LED0 - RED=1: GPIO2_0 2*32 = 64 */ + gpio_request(BOARD_DFU_BUTTON_LED, ""); + gpio_direction_output(BOARD_DFU_BUTTON_LED, 1); + gpio_set_value(BOARD_DFU_BUTTON_LED, 1); + } + + return button; +} + +U_BOOT_CMD( + dfubutton, CONFIG_SYS_MAXARGS, 1, do_userbutton, + "Return the status of the DFU button", + "" +); +#endif + +static int +do_usertestwdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + printf("\n\n\n Go into infinite loop\n\n\n"); + while (1) + ; + return 0; +}; + +U_BOOT_CMD( + testwdt, CONFIG_SYS_MAXARGS, 1, do_usertestwdt, + "Sends U-Boot into infinite loop", + "" +); + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + printf("Enable d-cache\n"); + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif /* CONFIG_SYS_DCACHE_OFF */ +#endif /* !CONFIG_SPL_BUILD */ diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c new file mode 100644 index 00000000000..eda9141c546 --- /dev/null +++ b/board/siemens/common/factoryset.c @@ -0,0 +1,284 @@ +/* + * + * Read FactorySet information from EEPROM into global structure. + * (C) Copyright 2013 Siemens Schweiz AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#if !defined(CONFIG_SPL_BUILD) + +#include +#include +#include +#include +#include +#include +#include +#include +#include "factoryset.h" + +#define EEPR_PG_SZ 0x80 +#define EEPROM_FATORYSET_OFFSET 0x400 +#define OFF_PG EEPROM_FATORYSET_OFFSET/EEPR_PG_SZ + +/* Global variable that contains necessary information from FactorySet */ +struct factorysetcontainer factory_dat; + +#define fact_get_char(i) *((char *)&eeprom_buf[i]) + +static int fact_match(unsigned char *eeprom_buf, uchar *s1, int i2) +{ + if (s1 == NULL) + return -1; + + while (*s1 == fact_get_char(i2++)) + if (*s1++ == '=') + return i2; + + if (*s1 == '\0' && fact_get_char(i2-1) == '=') + return i2; + + return -1; +} + +static int get_factory_val(unsigned char *eeprom_buf, int size, uchar *name, + uchar *buf, int len) +{ + int i, nxt = 0; + + for (i = 0; fact_get_char(i) != '\0'; i = nxt + 1) { + int val, n; + + for (nxt = i; fact_get_char(nxt) != '\0'; ++nxt) { + if (nxt >= size) + return -1; + } + + val = fact_match(eeprom_buf, (uchar *)name, i); + if (val < 0) + continue; + + /* found; copy out */ + for (n = 0; n < len; ++n, ++buf) { + *buf = fact_get_char(val++); + if (*buf == '\0') + return n; + } + + if (n) + *--buf = '\0'; + + printf("env_buf [%d bytes] too small for value of \"%s\"\n", + len, name); + + return n; + } + return -1; +} + +static +int get_factory_record_val(unsigned char *eeprom_buf, int size, uchar *record, + uchar *name, uchar *buf, int len) +{ + int ret = -1; + int i, nxt = 0; + int c; + unsigned char end = 0xff; + + for (i = 0; fact_get_char(i) != end; i = nxt) { + nxt = i + 1; + if (fact_get_char(i) == '>') { + int pos; + int endpos; + int z; + + c = strncmp((char *)&eeprom_buf[i + 1], (char *)record, + strlen((char *)record)); + if (c == 0) { + /* record found */ + pos = i + strlen((char *)record) + 2; + nxt = pos; + /* search for "<" */ + c = -1; + for (z = pos; fact_get_char(z) != end; z++) { + if ((fact_get_char(z) == '<') || + (fact_get_char(z) == '>')) { + endpos = z; + nxt = endpos; + c = 0; + break; + } + } + } + if (c == 0) { + /* end found -> call get_factory_val */ + eeprom_buf[endpos] = end; + ret = get_factory_val(&eeprom_buf[pos], + size - pos, name, buf, len); + /* fix buffer */ + eeprom_buf[endpos] = '<'; + debug("%s: %s.%s = %s\n", + __func__, record, name, buf); + return ret; + } + } + } + return ret; +} + +int factoryset_read_eeprom(int i2c_addr) +{ + int i, pages = 0, size = 0; + unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH]; + unsigned char *cp, *cp1; + +#if defined(CONFIG_DFU_FUNCTION) + factory_dat.usb_vendor_id = CONFIG_G_DNL_VENDOR_NUM; + factory_dat.usb_product_id = CONFIG_G_DNL_PRODUCT_NUM; +#endif + if (i2c_probe(i2c_addr)) + goto err; + + if (i2c_read(i2c_addr, EEPROM_FATORYSET_OFFSET, 2, hdr, sizeof(hdr))) + goto err; + + if ((hdr[0] != 0x99) || (hdr[1] != 0x80)) { + printf("FactorySet is not right in eeprom.\n"); + return 1; + } + + /* get FactorySet size */ + size = (hdr[2] << 8) + hdr[3] + sizeof(hdr); + if (size > 0x3bfa) + size = 0x3bfa; + + pages = size / EEPR_PG_SZ; + + /* + * read the eeprom using i2c + * I can not read entire eeprom in once, so separate into several + * times. Furthermore, fetch eeprom take longer time, so we fetch + * data after every time we got a record from eeprom + */ + debug("Read eeprom page :\n"); + for (i = 0; i < pages; i++) + if (i2c_read(i2c_addr, (OFF_PG + i) * EEPR_PG_SZ, 2, + eeprom_buf + (i * EEPR_PG_SZ), EEPR_PG_SZ)) + goto err; + + if (size % EEPR_PG_SZ) + if (i2c_read(i2c_addr, (OFF_PG + pages) * EEPR_PG_SZ, 2, + eeprom_buf + (pages * EEPR_PG_SZ), + (size % EEPR_PG_SZ))) + goto err; + + /* we do below just for eeprom align */ + for (i = 0; i < size; i++) + if (eeprom_buf[i] == '\n') + eeprom_buf[i] = 0; + + /* skip header */ + size -= sizeof(hdr); + cp = (uchar *)eeprom_buf + sizeof(hdr); + + /* get mac address */ + get_factory_record_val(cp, size, (uchar *)"ETH1", (uchar *)"mac", + buf, MAX_STRING_LENGTH); + cp1 = buf; + for (i = 0; i < 6; i++) { + factory_dat.mac[i] = simple_strtoul((char *)cp1, NULL, 16); + cp1 += 3; + } + +#if defined(CONFIG_DFU_FUNCTION) + /* read vid and pid for dfu mode */ + if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1", + (uchar *)"vid", buf, + MAX_STRING_LENGTH)) { + factory_dat.usb_vendor_id = simple_strtoul((char *)buf, + NULL, 16); + } + + if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1", + (uchar *)"pid", buf, + MAX_STRING_LENGTH)) { + factory_dat.usb_product_id = simple_strtoul((char *)buf, + NULL, 16); + } + printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id, + factory_dat.usb_product_id); +#endif + if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV", + (uchar *)"id", buf, + MAX_STRING_LENGTH)) { + if (strncmp((const char *)buf, "PXM50", 5) == 0) + factory_dat.pxm50 = 1; + else + factory_dat.pxm50 = 0; + } + debug("PXM50: %d\n", factory_dat.pxm50); +#if defined(CONFIG_VIDEO) + if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1", + (uchar *)"name", factory_dat.disp_name, + MAX_STRING_LENGTH)) { + debug("display name: %s\n", factory_dat.disp_name); + } + +#endif + return 0; + +err: + printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return 1; +} + +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + +static int factoryset_mac_setenv(void) +{ + uint8_t mac_addr[6]; + + debug("FactorySet: Set mac address\n"); + if (is_valid_ether_addr(factory_dat.mac)) { + memcpy(mac_addr, factory_dat.mac, 6); + } else { + uint32_t mac_hi, mac_lo; + + debug("Warning: FactorySet: not set. Fallback to E-fuse\n"); + mac_lo = readl(&cdev->macid0l); + mac_hi = readl(&cdev->macid0h); + + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + if (!is_valid_ether_addr(mac_addr)) { + printf("Warning: ethaddr not set by FactorySet or E-fuse. Set variable to overcome this.\n"); + return -1; + } + } + + eth_setenv_enetaddr("ethaddr", mac_addr); + return 0; +} + +int factoryset_setenv(void) +{ + int ret = 0; + + if (factoryset_mac_setenv() < 0) + ret = -1; + + return ret; +} + +int g_dnl_bind_fixup(struct usb_device_descriptor *dev) +{ + put_unaligned(factory_dat.usb_vendor_id, &dev->idVendor); + put_unaligned(factory_dat.usb_product_id, &dev->idProduct); + return 0; +} +#endif /* defined(CONFIG_SPL_BUILD) */ diff --git a/board/siemens/common/factoryset.h b/board/siemens/common/factoryset.h new file mode 100644 index 00000000000..445f3842da1 --- /dev/null +++ b/board/siemens/common/factoryset.h @@ -0,0 +1,27 @@ +/* + * Common board functions for siemens AM335X based boards + * (C) Copyright 2013 Siemens Schweiz AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FACTORYSET_H +#define __FACTORYSET_H + +#define MAX_STRING_LENGTH 32 + +struct factorysetcontainer { + uchar mac[6]; + int usb_vendor_id; + int usb_product_id; + int pxm50; +#if defined(CONFIG_VIDEO) + unsigned char disp_name[MAX_STRING_LENGTH]; +#endif +}; + +int factoryset_read_eeprom(int i2c_addr); +int factoryset_setenv(void); +extern struct factorysetcontainer factory_dat; + +#endif /* __FACTORYSET_H */ diff --git a/board/siemens/dxr2/Makefile b/board/siemens/dxr2/Makefile new file mode 100644 index 00000000000..a09b467d5a0 --- /dev/null +++ b/board/siemens/dxr2/Makefile @@ -0,0 +1,49 @@ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +ifdef CONFIG_SPL_BUILD +COBJS := mux.o +endif + +COBJS += board.o +ifndef CONFIG_SPL_BUILD +COBJS += ../common/factoryset.o +endif +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c new file mode 100644 index 00000000000..af9d84f1282 --- /dev/null +++ b/board/siemens/dxr2/board.c @@ -0,0 +1,241 @@ +/* + * Board functions for TI AM335X based dxr2 board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * + * Board functions for TI AM335X based boards + * u-boot:/board/ti/am335x/board.c + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" +#include "../common/factoryset.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +static struct dxr2_baseboard_id __attribute__((section(".data"))) settings; + +const struct ddr3_data ddr3_default = { + 0x33524444, 0x56312e33, 0x0100, 0x0001, 0x003A, 0x008A, 0x010B, + 0x00C4, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x0006, 0x61C04AB2, + 0x00000618, +}; + +static void set_default_ddr3_timings(void) +{ + printf("Set default DDR3 settings\n"); + settings.ddr3 = ddr3_default; +} + +static void print_ddr3_timings(void) +{ + printf("\n\nDDR3 Timing parameters:\n"); + printf("Diff Eeprom Default\n"); + PRINTARGS(magic); + PRINTARGS(version); + PRINTARGS(ddr3_sratio); + PRINTARGS(iclkout); + + PRINTARGS(dt0rdsratio0); + PRINTARGS(dt0wdsratio0); + PRINTARGS(dt0fwsratio0); + PRINTARGS(dt0wrsratio0); + + PRINTARGS(sdram_tim1); + PRINTARGS(sdram_tim2); + PRINTARGS(sdram_tim3); + + PRINTARGS(emif_ddr_phy_ctlr_1); + + PRINTARGS(sdram_config); + PRINTARGS(ref_ctrl); +} + +static void print_chip_data(void) +{ + printf("\n"); + printf("Device: '%s'\n", settings.chip.sdevname); + printf("HW version: '%s'\n", settings.chip.shwver); +} +#endif /* CONFIG_SPL_BUILD */ + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + /* Check if baseboard eeprom is available */ + if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + printf("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n"); + return 1; + } + +#ifdef CONFIG_SPL_BUILD + /* Read Siemens eeprom data (DDR3) */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_DDR3, 2, + (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) { + printf("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n"); + set_default_ddr3_timings(); + } + /* Read Siemens eeprom data (CHIP) */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_ADDR_CHIP, 2, + (uchar *)&settings.chip, sizeof(settings.chip))) + printf("Could not read chip settings\n"); + + if (ddr3_default.magic == settings.ddr3.magic && + ddr3_default.version == settings.ddr3.version) { + printf("Using DDR3 settings from EEPROM\n"); + } else { + if (ddr3_default.magic != settings.ddr3.magic) + printf("Error: No valid DDR3 data in eeprom.\n"); + if (ddr3_default.version != settings.ddr3.version) + printf("Error: DDR3 data version does not match.\n"); + + printf("Using default settings\n"); + set_default_ddr3_timings(); + } + + if (MAGIC_CHIP == settings.chip.magic) { + printf("Valid chip data in eeprom\n"); + print_chip_data(); + } else { + printf("Error: No chip data in eeprom\n"); + } + + print_ddr3_timings(); +#endif + return 0; +} + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs dxr2_ddr3_emif_reg_data = { + .zq_config = 0x50074BE4, +}; + +struct ddr_data dxr2_ddr3_data = { + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +struct cmd_control dxr2_ddr3_cmd_ctrl_data = { + .cmd0dldiff = 0, + .cmd1dldiff = 0, + .cmd2dldiff = 0, +}; + /* pass values from eeprom */ + dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1; + dxr2_ddr3_emif_reg_data.sdram_tim2 = settings.ddr3.sdram_tim2; + dxr2_ddr3_emif_reg_data.sdram_tim3 = settings.ddr3.sdram_tim3; + dxr2_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 = + settings.ddr3.emif_ddr_phy_ctlr_1; + dxr2_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config; + dxr2_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl; + + dxr2_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0; + dxr2_ddr3_data.datawdsratio0 = settings.ddr3.dt0wdsratio0; + dxr2_ddr3_data.datafwsratio0 = settings.ddr3.dt0fwsratio0; + dxr2_ddr3_data.datawrsratio0 = settings.ddr3.dt0wrsratio0; + + dxr2_ddr3_cmd_ctrl_data.cmd0csratio = settings.ddr3.ddr3_sratio; + dxr2_ddr3_cmd_ctrl_data.cmd0iclkout = settings.ddr3.iclkout; + dxr2_ddr3_cmd_ctrl_data.cmd1csratio = settings.ddr3.ddr3_sratio; + dxr2_ddr3_cmd_ctrl_data.cmd1iclkout = settings.ddr3.iclkout; + dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio; + dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout; + + config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &dxr2_ddr3_data, + &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0); +} + +static void spl_siemens_board_init(void) +{ + return; +} +#endif /* if def CONFIG_SPL_BUILD */ + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_MII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 4, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +int board_eth_init(bd_t *bis) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + int n = 0; + int rv; + + factoryset_setenv(); + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + return n; +} +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#include "../common/board.c" diff --git a/board/siemens/dxr2/board.h b/board/siemens/dxr2/board.h new file mode 100644 index 00000000000..2be78fbab24 --- /dev/null +++ b/board/siemens/dxr2/board.h @@ -0,0 +1,69 @@ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#define PARGS3(x) settings.ddr3.x-ddr3_default.x, \ + settings.ddr3.x, ddr3_default.x +#define PRINTARGS(y) printf("%x, %8x, %8x : "#y"\n", PARGS3(y)) +#define MAGIC_CHIP 0x50494843 + +/* Automatic generated definition */ +/* Wed, 19 Jun 2013 10:57:48 +0200 */ +/* From file: draco/ddr3-data-micron.txt */ +struct ddr3_data { + unsigned int magic; /* 0x33524444 */ + unsigned int version; /* 0x56312e33 */ + unsigned short int ddr3_sratio; /* 0x0100 */ + unsigned short int iclkout; /* 0x0001 */ + unsigned short int dt0rdsratio0; /* 0x003A */ + unsigned short int dt0wdsratio0; /* 0x008A */ + unsigned short int dt0fwsratio0; /* 0x010B */ + unsigned short int dt0wrsratio0; /* 0x00C4 */ + unsigned int sdram_tim1; /* 0x0888A39B */ + unsigned int sdram_tim2; /* 0x26247FDA */ + unsigned int sdram_tim3; /* 0x501F821F */ + unsigned short int emif_ddr_phy_ctlr_1; /* 0x0006 */ + unsigned int sdram_config; /* 0x61C04AB2 */ + unsigned int ref_ctrl; /* 0x00000618 */ +}; + +struct chip_data { + unsigned int magic; + char sdevname[16]; + char shwver[7]; +}; + +struct dxr2_baseboard_id { + struct ddr3_data ddr3; + struct chip_data chip; +}; + +/* + * We have three pin mux functions that must exist. We must be able to enable + * uart0, for initial output and i2c0 to read the main EEPROM. We then have a + * main pinmux function that can be overridden to enable all other pinmux that + * is required on the board. + */ +void enable_uart0_pin_mux(void); +void enable_uart1_pin_mux(void); +void enable_uart2_pin_mux(void); +void enable_uart3_pin_mux(void); +void enable_uart4_pin_mux(void); +void enable_uart5_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/siemens/dxr2/mux.c b/board/siemens/dxr2/mux.c new file mode 100644 index 00000000000..bc80b79d7e9 --- /dev/null +++ b/board/siemens/dxr2/mux.c @@ -0,0 +1,112 @@ +/* + * pinmux setup for siemens dxr2 board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux uart3_pin_mux[] = { + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {-1}, +}; + +static struct module_pin_mux gpios_pin_mux[] = { + /* DFU button GPIO0_27*/ + {OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)}, + {OFFSET(gpmc_csn3), MODE(7) }, /* LED0 GPIO2_0 */ + {OFFSET(emu0), MODE(7)}, /* LED1 GPIO3_7 */ + {-1}, +}; + +static struct module_pin_mux ethernet_pin_mux[] = { + {OFFSET(mii1_col), (MODE(3) | RXACTIVE)}, + {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_txen), (MODE(1))}, + {OFFSET(mii1_rxdv), (MODE(3) | RXACTIVE)}, + {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd1), (MODE(1))}, + {OFFSET(mii1_txd0), (MODE(1))}, + {OFFSET(mii1_txclk), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxclk), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd3), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd2), (MODE(1))}, + {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)}, + {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)}, + {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_uart3_pin_mux(void) +{ + configure_module_pin_mux(uart3_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + enable_uart3_pin_mux(); + configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(ethernet_pin_mux); + configure_module_pin_mux(gpios_pin_mux); +} diff --git a/board/siemens/pxm2/Makefile b/board/siemens/pxm2/Makefile new file mode 100644 index 00000000000..a09b467d5a0 --- /dev/null +++ b/board/siemens/pxm2/Makefile @@ -0,0 +1,49 @@ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +ifdef CONFIG_SPL_BUILD +COBJS := mux.o +endif + +COBJS += board.o +ifndef CONFIG_SPL_BUILD +COBJS += ../common/factoryset.o +endif +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c new file mode 100644 index 00000000000..2c1841f8aed --- /dev/null +++ b/board/siemens/pxm2/board.c @@ -0,0 +1,429 @@ +/* + * Board functions for TI AM335X based pxm2 board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/board.c + * + * Board functions for TI AM335X based boards + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "../../../drivers/video/da8xx-fb.h" +#include +#include +#include +#include +#include +#include +#include +#include "board.h" +#include "../common/factoryset.h" +#include "pmic.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs pxm2_ddr3_emif_reg_data = { + .sdram_config = 0x41805332, + .sdram_tim1 = 0x666b3c9, + .sdram_tim2 = 0x243631ca, + .sdram_tim3 = 0x33f, + .emif_ddr_phy_ctlr_1 = 0x100005, + .zq_config = 0, + .ref_ctrl = 0x81a, +}; + +struct ddr_data pxm2_ddr3_data = { + .datardsratio0 = 0x81204812, + .datawdsratio0 = 0, + .datafwsratio0 = 0x8020080, + .datawrsratio0 = 0x4010040, + .datauserank0delay = 1, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +struct cmd_control pxm2_ddr3_cmd_ctrl_data = { + .cmd0csratio = 0x80, + .cmd0dldiff = 0, + .cmd0iclkout = 0, + .cmd1csratio = 0x80, + .cmd1dldiff = 0, + .cmd1iclkout = 0, + .cmd2csratio = 0x80, + .cmd2dldiff = 0, + .cmd2iclkout = 0, +}; + + config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &pxm2_ddr3_data, + &pxm2_ddr3_cmd_ctrl_data, &pxm2_ddr3_emif_reg_data, 0); +} + +/* + * voltage switching for MPU frequency switching. + * @module = mpu - 0, core - 1 + * @vddx_op_vol_sel = vdd voltage to set + */ + +#define MPU 0 +#define CORE 1 + +int voltage_update(unsigned int module, unsigned char vddx_op_vol_sel) +{ + uchar buf[4]; + unsigned int reg_offset; + + if (module == MPU) + reg_offset = PMIC_VDD1_OP_REG; + else + reg_offset = PMIC_VDD2_OP_REG; + + /* Select VDDx OP */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + buf[0] &= ~PMIC_OP_REG_CMD_MASK; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + /* Configure VDDx OP Voltage */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + buf[0] &= ~PMIC_OP_REG_SEL_MASK; + buf[0] |= vddx_op_vol_sel; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + if (i2c_read(PMIC_CTRL_I2C_ADDR, reg_offset, 1, buf, 1)) + return 1; + + if ((buf[0] & PMIC_OP_REG_SEL_MASK) != vddx_op_vol_sel) + return 1; + + return 0; +} + +#define OSC (V_OSCK/1000000) + +const struct dpll_params dpll_mpu_pxm2 = { + 720, OSC-1, 1, -1, -1, -1, -1}; + +void spl_siemens_board_init(void) +{ + uchar buf[4]; + /* + * pxm2 PMIC code. All boards currently want an MPU voltage + * of 1.2625V and CORE voltage of 1.1375V to operate at + * 720MHz. + */ + if (i2c_probe(PMIC_CTRL_I2C_ADDR)) + return; + + /* VDD1/2 voltage selection register access by control i/f */ + if (i2c_read(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1)) + return; + + buf[0] |= PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C; + + if (i2c_write(PMIC_CTRL_I2C_ADDR, PMIC_DEVCTRL_REG, 1, buf, 1)) + return; + + /* Frequency switching for OPP 120 */ + if (voltage_update(MPU, PMIC_OP_REG_SEL_1_2_6) || + voltage_update(CORE, PMIC_OP_REG_SEL_1_1_3)) { + printf("voltage update failed\n"); + } +} +#endif /* if def CONFIG_SPL_BUILD */ + +int read_eeprom(void) +{ + /* nothing ToDo here for this board */ + + return 0; +} + +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 1, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 4, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +int board_eth_init(bd_t *bis) +{ + int n = 0; +#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ + (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; +#ifdef CONFIG_FACTORYSET + int rv; + if (!is_valid_ether_addr(factory_dat.mac)) + printf("Error: no valid mac address\n"); + else + eth_setenv_enetaddr("ethaddr", factory_dat.mac); +#endif /* #ifdef CONFIG_FACTORYSET */ + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel(RGMII_MODE_ENABLE , &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif + return n; +} +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +static struct da8xx_panel lcd_panels[] = { + /* AUO G156XW01 V1 */ + [0] = { + .name = "AUO_G156XW01_V1", + .width = 1376, + .height = 768, + .hfp = 14, + .hbp = 64, + .hsw = 56, + .vfp = 1, + .vbp = 28, + .vsw = 3, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, + /* AUO B101EVN06 V0 */ + [1] = { + .name = "AUO_B101EVN06_V0", + .width = 1280, + .height = 800, + .hfp = 52, + .hbp = 84, + .hsw = 36, + .vfp = 3, + .vbp = 14, + .vsw = 6, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, + /* + * Settings from factoryset + * stored in EEPROM + */ + [2] = { + .name = "factoryset", + .width = 0, + .height = 0, + .hfp = 0, + .hbp = 0, + .hsw = 0, + .vfp = 0, + .vbp = 0, + .vsw = 0, + .pxl_clk = 60000000, + .invert_pxl_clk = 0, + }, +}; + +static const struct display_panel disp_panel = { + WVGA, + 32, + 16, + COLOR_ACTIVE, +}; + +static const struct lcd_ctrl_config lcd_cfg = { + &disp_panel, + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 32, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, +}; + +static int set_gpio(int gpio, int state) +{ + gpio_request(gpio, "temp"); + gpio_direction_output(gpio, state); + gpio_set_value(gpio, state); + gpio_free(gpio); + return 0; +} + +static int enable_backlight(void) +{ + set_gpio(BOARD_LCD_POWER, 1); + set_gpio(BOARD_BACK_LIGHT, 1); + set_gpio(BOARD_TOUCH_POWER, 1); + return 0; +} + +static int enable_pwm(void) +{ + struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE; + struct pwmss_ecap_regs *ecap; + int ticks = PWM_TICKS; + int duty = PWM_DUTY; + + ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE; + /* enable clock */ + setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN); + /* TimeStam Counter register */ + writel(0xdb9, &ecap->tsctr); + /* config period */ + writel(ticks - 1, &ecap->cap3); + writel(ticks - 1, &ecap->cap1); + setbits_le16(&ecap->ecctl2, + (ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0)); + /* config duty */ + writel(duty, &ecap->cap2); + writel(duty, &ecap->cap4); + /* start */ + setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN); + return 0; +} + +static struct dpll_regs dpll_lcd_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x98, + .cm_idlest_dpll = CM_WKUP + 0x48, + .cm_clksel_dpll = CM_WKUP + 0x54, +}; + +/* no console on this board */ +int board_cfb_skip(void) +{ + return 1; +} + +#define PLL_GET_M(v) ((v >> 8) & 0x7ff) +#define PLL_GET_N(v) (v & 0x7f) + +static int get_clk(struct dpll_regs *dpll_regs) +{ + unsigned int val; + unsigned int m, n; + int f = 0; + + val = readl(dpll_regs->cm_clksel_dpll); + m = PLL_GET_M(val); + n = PLL_GET_N(val); + f = (m * V_OSCK) / n; + + return f; +}; + +int clk_get(int clk) +{ + return get_clk(&dpll_lcd_regs); +}; + +static int conf_disp_pll(int m, int n) +{ + struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; + struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; + struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1}; + + u32 *const clk_domains[] = { + &cmper->lcdclkctrl, + 0 + }; + u32 *const clk_modules_explicit_en[] = { + &cmper->lcdclkctrl, + &cmper->lcdcclkstctrl, + &cmper->epwmss0clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + writel(0x0, &cmdpll->clklcdcpixelclk); + + do_setup_dpll(&dpll_lcd_regs, &dpll_lcd); + + return 0; +} + +static int board_video_init(void) +{ + /* set 300 MHz */ + conf_disp_pll(25, 2); + if (factory_dat.pxm50) + da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp); + else + da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp); + + enable_pwm(); + enable_backlight(); + + return 0; +} +#endif +#include "../common/board.c" diff --git a/board/siemens/pxm2/board.h b/board/siemens/pxm2/board.h new file mode 100644 index 00000000000..03626129dec --- /dev/null +++ b/board/siemens/pxm2/board.h @@ -0,0 +1,22 @@ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/siemens/pxm2/mux.c b/board/siemens/pxm2/mux.c new file mode 100644 index 00000000000..c64b0d23d52 --- /dev/null +++ b/board/siemens/pxm2/mux.c @@ -0,0 +1,186 @@ +/* + * pinmux setup for siemens pxm2 board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include "board.h" + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ + {OFFSET(nnmi), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_TXD */ + {-1}, +}; + +#ifdef CONFIG_NAND +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ + {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ + {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ + {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ + {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ + {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ + {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ + {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ + {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ + {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ + {OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUP_EN}, /* RGMII2_RD0 */ + {OFFSET(mcasp0_ahclkx), MODE(7) | PULLUDEN}, /* MCASP0_AHCLKX */ + {-1}, +}; +#endif + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL)}, + {-1}, +}; + +#ifndef CONFIG_NO_ETH +static struct module_pin_mux rgmii1_pin_mux[] = { + {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ + {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ + {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ + {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ + {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ + {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ + {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ + {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ + {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ + {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ + {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ + {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; + +static struct module_pin_mux rgmii2_pin_mux[] = { + {OFFSET(gpmc_a0), MODE(2)}, /* RGMII2_TCTL */ + {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII2_RCTL */ + {OFFSET(gpmc_a2), MODE(2)}, /* RGMII2_TD3 */ + {OFFSET(gpmc_a3), MODE(2)}, /* RGMII2_TD2 */ + {OFFSET(gpmc_a4), MODE(2)}, /* RGMII2_TD1 */ + {OFFSET(gpmc_a5), MODE(2)}, /* RGMII2_TD0 */ + {OFFSET(gpmc_a6), MODE(7)}, /* RGMII2_TCLK */ + {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII2_RCLK */ + {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII2_RD3 */ + {OFFSET(gpmc_a9), MODE(7)}, /* RGMII2_RD2 */ + {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII2_RD1 */ + {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ + {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ + {-1}, +}; +#endif + +#ifdef CONFIG_MMC +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ + {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ + {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUDEN)}, /* MMC0_CD */ + {-1}, +}; +#endif + +static struct module_pin_mux lcdc_pin_mux[] = { + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD_DAT0 */ + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD_DAT1 */ + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD_DAT2 */ + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD_DAT3 */ + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD_DAT4 */ + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD_DAT5 */ + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD_DAT6 */ + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD_DAT7 */ + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD_DAT8 */ + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD_DAT9 */ + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD_DAT10 */ + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD_DAT11 */ + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD_DAT12 */ + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD_DAT13 */ + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD_DAT14 */ + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD_DAT15 */ + {OFFSET(gpmc_ad8), (MODE(1))}, /* LCD_DAT16 */ + {OFFSET(gpmc_ad9), (MODE(1))}, /* LCD_DAT17 */ + {OFFSET(gpmc_ad10), (MODE(1))}, /* LCD_DAT18 */ + {OFFSET(gpmc_ad11), (MODE(1))}, /* LCD_DAT19 */ + {OFFSET(gpmc_ad12), (MODE(1))}, /* LCD_DAT20 */ + {OFFSET(gpmc_ad13), (MODE(1))}, /* LCD_DAT21 */ + {OFFSET(gpmc_ad14), (MODE(1))}, /* LCD_DAT22 */ + {OFFSET(gpmc_ad15), (MODE(1))}, /* LCD_DAT23 */ + {OFFSET(lcd_vsync), (MODE(0))}, /* LCD_VSYNC */ + {OFFSET(lcd_hsync), (MODE(0))}, /* LCD_HSYNC */ + {OFFSET(lcd_pclk), (MODE(0))}, /* LCD_PCLK */ + {OFFSET(lcd_ac_bias_en), (MODE(0))}, /* LCD_AC_BIAS_EN */ + {-1}, +}; + +static struct module_pin_mux ecap0_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux gpio_pin_mux[] = { + {OFFSET(mcasp0_fsx), MODE(7)}, /* GPIO3_15 LCD power*/ + {OFFSET(mcasp0_axr0), MODE(7)}, /* GPIO3_16 Backlight */ + {OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25 Touch power */ + {-1}, +}; +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); + configure_module_pin_mux(i2c1_pin_mux); +#ifdef CONFIG_NAND + configure_module_pin_mux(nand_pin_mux); +#endif +#ifndef CONFIG_NO_ETH + configure_module_pin_mux(rgmii1_pin_mux); + configure_module_pin_mux(rgmii2_pin_mux); +#endif +#ifdef CONFIG_MMC + configure_module_pin_mux(mmc0_pin_mux); +#endif + configure_module_pin_mux(lcdc_pin_mux); + configure_module_pin_mux(gpio_pin_mux); + configure_module_pin_mux(ecap0_pin_mux); +} diff --git a/board/siemens/pxm2/pmic.h b/board/siemens/pxm2/pmic.h new file mode 100644 index 00000000000..c6347e51293 --- /dev/null +++ b/board/siemens/pxm2/pmic.h @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef PMIC_H +#define PMIC_H + +/* + * The PMIC on this board is a TPS65910. + */ + +#define PMIC_SR_I2C_ADDR 0x12 +#define PMIC_CTRL_I2C_ADDR 0x2D +/* PMIC Register offsets */ +#define PMIC_VDD1_REG 0x21 +#define PMIC_VDD1_OP_REG 0x22 +#define PMIC_VDD2_REG 0x24 +#define PMIC_VDD2_OP_REG 0x25 +#define PMIC_DEVCTRL_REG 0x3f + +/* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */ +#define PMIC_VGAIN_SEL_MASK (0x3 << 6) +#define PMIC_ILMAX_MASK (0x1 << 5) +#define PMIC_TSTEP_MASK (0x7 << 2) +#define PMIC_ST_MASK (0x3) + +#define PMIC_REG_VGAIN_SEL_X1 (0x0 << 6) +#define PMIC_REG_VGAIN_SEL_X1_0 (0x1 << 6) +#define PMIC_REG_VGAIN_SEL_X3 (0x2 << 6) +#define PMIC_REG_VGAIN_SEL_X4 (0x3 << 6) + +#define PMIC_REG_ILMAX_1_0_A (0x0 << 5) +#define PMIC_REG_ILMAX_1_5_A (0x1 << 5) + +#define PMIC_REG_TSTEP_ (0x0 << 2) +#define PMIC_REG_TSTEP_12_5 (0x1 << 2) +#define PMIC_REG_TSTEP_9_4 (0x2 << 2) +#define PMIC_REG_TSTEP_7_5 (0x3 << 2) +#define PMIC_REG_TSTEP_6_25 (0x4 << 2) +#define PMIC_REG_TSTEP_4_7 (0x5 << 2) +#define PMIC_REG_TSTEP_3_12 (0x6 << 2) +#define PMIC_REG_TSTEP_2_5 (0x7 << 2) + +#define PMIC_REG_ST_OFF (0x0) +#define PMIC_REG_ST_ON_HI_POW (0x1) +#define PMIC_REG_ST_OFF_1 (0x2) +#define PMIC_REG_ST_ON_LOW_POW (0x3) + + +/* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */ +#define PMIC_OP_REG_SEL (0x7F) + +#define PMIC_OP_REG_CMD_MASK (0x1 << 7) +#define PMIC_OP_REG_CMD_OP (0x0 << 7) +#define PMIC_OP_REG_CMD_SR (0x1 << 7) + +#define PMIC_OP_REG_SEL_MASK (0x7F) +#define PMIC_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */ +#define PMIC_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */ + +/* Device control register . (DEVCTRL_REG) */ +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4) +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4) +#define PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4) + +#endif diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile new file mode 100644 index 00000000000..a09b467d5a0 --- /dev/null +++ b/board/siemens/rut/Makefile @@ -0,0 +1,49 @@ +# +# Makefile +# +# (C) Copyright 2013 Siemens Schweiz AG +# (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. +# +# Based on: +# u-boot:/board/ti/am335x/Makefile +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../common) +endif + +LIB = $(obj)lib$(BOARD).o + +ifdef CONFIG_SPL_BUILD +COBJS := mux.o +endif + +COBJS += board.o +ifndef CONFIG_SPL_BUILD +COBJS += ../common/factoryset.o +endif +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c new file mode 100644 index 00000000000..f2b04768179 --- /dev/null +++ b/board/siemens/rut/board.c @@ -0,0 +1,432 @@ +/* + * Board functions for TI AM335X based rut board + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/board.c + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "board.h" +#include "../common/factoryset.h" +#include "../../../drivers/video/da8xx-fb.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Read header information from EEPROM into global structure. + */ +static int read_eeprom(void) +{ + return 0; +} + +#ifdef CONFIG_SPL_BUILD +static void board_init_ddr(void) +{ +struct emif_regs rut_ddr3_emif_reg_data = { + .sdram_config = 0x61C04AB2, + .sdram_tim1 = 0x0888A39B, + .sdram_tim2 = 0x26337FDA, + .sdram_tim3 = 0x501F830F, + .emif_ddr_phy_ctlr_1 = 0x6, + .zq_config = 0x50074BE4, + .ref_ctrl = 0x93B, +}; + +struct ddr_data rut_ddr3_data = { + .datardsratio0 = 0x3b, + .datawdsratio0 = 0x85, + .datafwsratio0 = 0x100, + .datawrsratio0 = 0xc1, + .datauserank0delay = 1, + .datadldiff0 = PHY_DLL_LOCK_DIFF, +}; + +struct cmd_control rut_ddr3_cmd_ctrl_data = { + .cmd0csratio = 0x40, + .cmd0dldiff = 0, + .cmd0iclkout = 1, + .cmd1csratio = 0x40, + .cmd1dldiff = 0, + .cmd1iclkout = 1, + .cmd2csratio = 0x40, + .cmd2dldiff = 0, + .cmd2iclkout = 1, +}; + + config_ddr(DDR_PLL_FREQ, RUT_IOCTRL_VAL, &rut_ddr3_data, + &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0); +} + +static void spl_siemens_board_init(void) +{ + return; +} +#endif /* if def CONFIG_SPL_BUILD */ + +#if defined(CONFIG_DRIVER_TI_CPSW) +static void cpsw_control(int enabled) +{ + /* VTP can be added here */ + + return; +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 1, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, + { + .slave_reg_ofs = 0x308, + .sliver_reg_ofs = 0xdc0, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, +}; + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = 1, + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .bd_ram_ofs = 0x2000, + .mac_control = (1 << 5), + .control = cpsw_control, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) +int board_eth_init(bd_t *bis) +{ + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; + int n = 0; + int rv; + +#ifndef CONFIG_SPL_BUILD + factoryset_setenv(); +#endif + + /* Set rgmii mode and enable rmii clock to be sourced from chip */ + writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); + + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; + return n; +} +#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */ +#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */ + +#if defined(CONFIG_HW_WATCHDOG) +static bool hw_watchdog_init_done; +static int hw_watchdog_trigger_level; + +void hw_watchdog_reset(void) +{ + if (!hw_watchdog_init_done) + return; + + hw_watchdog_trigger_level = hw_watchdog_trigger_level ? 0 : 1; + gpio_set_value(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); +} + +void hw_watchdog_init(void) +{ + gpio_request(WATCHDOG_TRIGGER_GPIO, "watchdog_trigger"); + gpio_direction_output(WATCHDOG_TRIGGER_GPIO, hw_watchdog_trigger_level); + + hw_watchdog_reset(); + + hw_watchdog_init_done = 1; +} +#endif /* defined(CONFIG_HW_WATCHDOG) */ + +#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD) +static struct da8xx_panel lcd_panels[] = { + /* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */ + [0] = { + .name = "KWH043MC17-F01", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, + /* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */ + [1] = { + .name = "KWH043ST20-F01", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, + /* Multi-Inno, 4.3", 480x800, MI0430VT-1 */ + [2] = { + .name = "MI0430VT-1", + .width = 480, + .height = 800, + .hfp = 50, /* no spec, "don't care" values */ + .hbp = 50, + .hsw = 50, + .vfp = 50, + .vbp = 50, + .vsw = 50, + .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */ + .invert_pxl_clk = 1, + }, +}; + +static const struct display_panel disp_panels[] = { + [0] = { + WVGA, + 16, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, + [1] = { + WVGA, + 16, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, + [2] = { + WVGA, + 24, /* RGB 888 */ + 16, + COLOR_ACTIVE, + }, +}; + +static const struct lcd_ctrl_config lcd_cfgs[] = { + [0] = { + &disp_panels[0], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + [1] = { + &disp_panels[1], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 16, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + [2] = { + &disp_panels[2], + .ac_bias = 255, + .ac_bias_intrpt = 0, + .dma_burst_sz = 16, + .bpp = 24, + .fdd = 0x80, + .tft_alt_mode = 0, + .stn_565_mode = 0, + .mono_8bit_mode = 0, + .invert_line_clock = 1, + .invert_frm_clock = 1, + .sync_edge = 0, + .sync_ctrl = 1, + .raster_order = 0, + }, + +}; + +/* no console on this board */ +int board_cfb_skip(void) +{ + return 1; +} + +#define PLL_GET_M(v) ((v >> 8) & 0x7ff) +#define PLL_GET_N(v) (v & 0x7f) + +static struct dpll_regs dpll_lcd_regs = { + .cm_clkmode_dpll = CM_WKUP + 0x98, + .cm_idlest_dpll = CM_WKUP + 0x48, + .cm_clksel_dpll = CM_WKUP + 0x54, +}; + +static int get_clk(struct dpll_regs *dpll_regs) +{ + unsigned int val; + unsigned int m, n; + int f = 0; + + val = readl(dpll_regs->cm_clksel_dpll); + m = PLL_GET_M(val); + n = PLL_GET_N(val); + f = (m * V_OSCK) / n; + + return f; +}; + + + +int clk_get(int clk) +{ + return get_clk(&dpll_lcd_regs); +}; + +static int conf_disp_pll(int m, int n) +{ + struct cm_perpll *cmper = (struct cm_perpll *)CM_PER; + struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; + struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1}; +#if defined(DISPL_PLL_SPREAD_SPECTRUM) + struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; +#endif + + u32 *const clk_domains[] = { + &cmper->lcdclkctrl, + 0 + }; + u32 *const clk_modules_explicit_en[] = { + &cmper->lcdclkctrl, + &cmper->lcdcclkstctrl, + &cmper->spi1clkctrl, + 0 + }; + do_enable_clocks(clk_domains, clk_modules_explicit_en, 1); + /* 0x44e0_0500 write lcdc pixel clock mux Linux hat hier 0 */ + writel(0x0, &cmdpll->clklcdcpixelclk); + + do_setup_dpll(&dpll_lcd_regs, &dpll_lcd); + +#if defined(DISPL_PLL_SPREAD_SPECTRUM) + writel(0x64, &cmwkup->resv6[3]); /* 0x50 */ + writel(0x800, &cmwkup->resv6[2]); /* 0x4c */ + writel(readl(&cmwkup->clkmoddplldisp) | (1 << 12), + &cmwkup->clkmoddplldisp); /* 0x98 */ +#endif + return 0; +} + +static int set_gpio(int gpio, int state) +{ + gpio_request(gpio, "temp"); + gpio_direction_output(gpio, state); + gpio_set_value(gpio, state); + gpio_free(gpio); + return 0; +} + +static int enable_lcd(void) +{ + unsigned char buf[1]; + + set_gpio(BOARD_LCD_RESET, 1); + + /* spi lcd init */ + kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_3); + + /* backlight on */ + buf[0] = 0xf; + i2c_write(0x24, 0x7, 1, buf, 1); + buf[0] = 0x3f; + i2c_write(0x24, 0x8, 1, buf, 1); + return 0; +} + +int arch_early_init_r(void) +{ + enable_lcd(); + return 0; +} + +static int board_video_init(void) +{ + int i; + int anzdisp = ARRAY_SIZE(lcd_panels); + int display = 1; + + for (i = 0; i < anzdisp; i++) { + if (strncmp((const char *)factory_dat.disp_name, + lcd_panels[i].name, + strlen((const char *)factory_dat.disp_name)) == 0) { + printf("DISPLAY: %s\n", factory_dat.disp_name); + break; + } + } + if (i == anzdisp) { + i = 1; + printf("%s: %s not found, using default %s\n", __func__, + factory_dat.disp_name, lcd_panels[i].name); + } + conf_disp_pll(25, 2); + da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display], + lcd_cfgs[display].bpp); + + return 0; +} + + +#endif /* ifdef CONFIG_VIDEO */ +#include "../common/board.c" diff --git a/board/siemens/rut/board.h b/board/siemens/rut/board.h new file mode 100644 index 00000000000..03626129dec --- /dev/null +++ b/board/siemens/rut/board.h @@ -0,0 +1,22 @@ +/* + * board.h + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * TI AM335x boards information header + * u-boot:/board/ti/am335x/board.h + * + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +void enable_uart0_pin_mux(void); +void enable_i2c0_pin_mux(void); +void enable_board_pin_mux(void); +#endif diff --git a/board/siemens/rut/mux.c b/board/siemens/rut/mux.c new file mode 100644 index 00000000000..1eced013c79 --- /dev/null +++ b/board/siemens/rut/mux.c @@ -0,0 +1,347 @@ +/* + * pinmux setup for siemens rut board + * + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * u-boot:/board/ti/am335x/mux.c + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct module_pin_mux uart0_pin_mux[] = { + {OFFSET(uart0_rxd), (MODE(0) | PULLUDDIS | RXACTIVE)}, /* UART0_RXD */ + {OFFSET(uart0_txd), (MODE(0) | PULLUDDIS)}, /* UART0_TXD */ + {-1}, +}; + +static struct module_pin_mux ddr_pin_mux[] = { + {OFFSET(ddr_resetn), (MODE(0))}, + {OFFSET(ddr_csn0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ck), (MODE(0))}, + {OFFSET(ddr_nck), (MODE(0))}, + {OFFSET(ddr_casn), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_rasn), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_wen), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_ba2), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a2), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a3), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a4), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a5), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a6), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a7), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a8), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a9), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a10), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a11), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a12), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a13), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a14), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_a15), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_odt), (MODE(0))}, + {OFFSET(ddr_d0), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d1), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d2), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d3), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d4), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d5), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d6), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d7), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d8), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d9), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d10), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d11), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d12), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d13), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d14), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_d15), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqm0), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_dqm1), (MODE(0) | PULLUP_EN)}, + {OFFSET(ddr_dqs0), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqsn0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ddr_dqs1), (MODE(0) | RXACTIVE)}, + {OFFSET(ddr_dqsn1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ddr_vref), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ddr_vtp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux lcd_pin_mux[] = { + {OFFSET(gpmc_ad8), (MODE(1))}, + {OFFSET(gpmc_ad9), (MODE(1))}, + {OFFSET(gpmc_ad10), (MODE(1))}, + {OFFSET(gpmc_ad11), (MODE(1))}, + {OFFSET(gpmc_ad12), (MODE(1))}, + {OFFSET(gpmc_ad13), (MODE(1))}, + {OFFSET(gpmc_ad14), (MODE(1))}, + {OFFSET(gpmc_ad15), (MODE(1))}, + {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, + {OFFSET(lcd_vsync), (MODE(0))}, + {OFFSET(lcd_hsync), (MODE(0))}, + {OFFSET(lcd_pclk), (MODE(0))}, + {OFFSET(lcd_ac_bias_en), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux mmc0_pin_mux[] = { + {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux mii_pin_mux[] = { + {OFFSET(mii1_crs), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxerr), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_txen), (MODE(1))}, + {OFFSET(mii1_txd1), (MODE(1))}, + {OFFSET(mii1_txd0), (MODE(1))}, + {OFFSET(mii1_rxd1), (MODE(1) | RXACTIVE)}, + {OFFSET(mii1_rxd0), (MODE(1) | RXACTIVE)}, + {OFFSET(rmii1_refclk), (MODE(0) | RXACTIVE)}, + {OFFSET(mdio_data), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mdio_clk), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux gpio_pin_mux[] = { + {OFFSET(mii1_col), (MODE(7) | RXACTIVE)}, + {OFFSET(uart1_ctsn), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_rtsn), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_rxd), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart1_txd), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(mii1_rxdv), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txd2), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_txclk), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxclk), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxd3), (MODE(7) | RXACTIVE)}, + {OFFSET(mii1_rxd2), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a0), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a1), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a4), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a5), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a6), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a7), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a8), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a9), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a10), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_a11), (MODE(7) | RXACTIVE)}, + {OFFSET(gpmc_wpn), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_be1n), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn1), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn2), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_csn3), (MODE(7) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_aclkr), (MODE(7) | RXACTIVE)}, + {OFFSET(mcasp0_fsr), (MODE(7))}, + {OFFSET(mcasp0_axr1), (MODE(7) | RXACTIVE)}, + {OFFSET(mcasp0_ahclkx), (MODE(7) | RXACTIVE)}, + {OFFSET(xdma_event_intr0), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {OFFSET(xdma_event_intr1), (MODE(7) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux i2c0_pin_mux[] = { + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux i2c1_pin_mux[] = { + {OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS)}, + {OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux usb0_pin_mux[] = { + {OFFSET(usb0_dm), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_dp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_ce), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_id), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb0_drvvbus), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux usb1_pin_mux[] = { + {OFFSET(usb1_dm), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_dp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_ce), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_id), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_vbus), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(usb1_drvvbus), (MODE(0))}, + {-1}, +}; + +static struct module_pin_mux spi0_pin_mux[] = { + {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(spi0_cs1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux spi1_pin_mux[] = { + {OFFSET(mcasp0_aclkx), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_fsx), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_axr0), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {OFFSET(mcasp0_ahclkr), (MODE(3) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux jtag_pin_mux[] = { + {OFFSET(tms), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(tdi), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(tdo), (MODE(0) | PULLUP_EN)}, + {OFFSET(tck), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(ntrst), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux nand_pin_mux[] = { + {OFFSET(gpmc_ad0), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad1), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad2), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad3), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad4), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad5), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad6), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_ad7), (MODE(0) | RXACTIVE)}, + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUP_EN)}, + {OFFSET(gpmc_wen), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux ainx_pin_mux[] = { + {OFFSET(ain7), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain6), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain5), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain4), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain3), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain2), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain1), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ain0), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux rtc_pin_mux[] = { + {OFFSET(osc1_in), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(osc1_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(rtc_porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(enz_kaldo_1p8v), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux gpmc_pin_mux[] = { + {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(gpmc_clk), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +static struct module_pin_mux pmic_pin_mux[] = { + {OFFSET(pmic_power_en), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux osc_pin_mux[] = { + {OFFSET(osc0_in), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(osc0_out), (MODE(0) | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux pwm_pin_mux[] = { + {OFFSET(ecap0_in_pwm0_out), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(gpmc_a2), (MODE(6))}, + {OFFSET(gpmc_a3), (MODE(6))}, + {-1}, +}; + +static struct module_pin_mux emu_pin_mux[] = { + {OFFSET(emu0), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {OFFSET(emu1), (MODE(0) | RXACTIVE | PULLUP_EN)}, + {-1}, +}; + +static struct module_pin_mux vref_pin_mux[] = { + {OFFSET(vrefp), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(vrefn), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {-1}, +}; + +static struct module_pin_mux misc_pin_mux[] = { + {OFFSET(porz), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(nnmi), (MODE(0) | RXACTIVE | PULLUDDIS)}, + {OFFSET(ext_wakeup), (MODE(0) | RXACTIVE)}, + {-1}, +}; + +void enable_uart0_pin_mux(void) +{ + configure_module_pin_mux(uart0_pin_mux); +} + +void enable_i2c0_pin_mux(void) +{ + configure_module_pin_mux(i2c0_pin_mux); +} + +void enable_board_pin_mux(void) +{ + configure_module_pin_mux(ddr_pin_mux); + configure_module_pin_mux(lcd_pin_mux); + configure_module_pin_mux(mmc0_pin_mux); + configure_module_pin_mux(mii_pin_mux); + configure_module_pin_mux(gpio_pin_mux); + configure_module_pin_mux(i2c1_pin_mux); + configure_module_pin_mux(usb0_pin_mux); + configure_module_pin_mux(usb1_pin_mux); + configure_module_pin_mux(spi0_pin_mux); + configure_module_pin_mux(spi1_pin_mux); + configure_module_pin_mux(jtag_pin_mux); + configure_module_pin_mux(nand_pin_mux); + configure_module_pin_mux(ainx_pin_mux); + configure_module_pin_mux(rtc_pin_mux); + configure_module_pin_mux(gpmc_pin_mux); + configure_module_pin_mux(pmic_pin_mux); + configure_module_pin_mux(osc_pin_mux); + configure_module_pin_mux(pwm_pin_mux); + configure_module_pin_mux(emu_pin_mux); + configure_module_pin_mux(vref_pin_mux); + configure_module_pin_mux(misc_pin_mux); +} diff --git a/boards.cfg b/boards.cfg index d7c8d341b84..7ccc7ce8120 100644 --- a/boards.cfg +++ b/boards.cfg @@ -254,6 +254,9 @@ am335x_evm_uart5 arm armv7 am335x ti am335x_evm_usbspl arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT am335x_boneblack arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT am43xx_evm arm armv7 am43xx ti am33xx am43xx_evm:SERIAL1,CONS_INDEX=1 +dxr2 arm armv7 dxr2 siemens am33xx +pxm2 arm armv7 pxm2 siemens am33xx +rut arm armv7 rut siemens am33xx ti814x_evm arm armv7 ti814x ti am33xx ti816x_evm arm armv7 ti816x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 diff --git a/include/configs/dxr2.h b/include/configs/dxr2.h new file mode 100644 index 00000000000..cd553ec55b1 --- /dev/null +++ b/include/configs/dxr2.h @@ -0,0 +1,94 @@ +/* + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_DXR2_H +#define __CONFIG_DXR2_H + +#define CONFIG_SIEMENS_DXR2 +#define MACH_TYPE_DXR2 4315 +#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DXR2 + +#include "siemens-am33x-common.h" + +#define CONFIG_SYS_MPUCLK 275 +#define DXR2_IOCTRL_VAL 0x18b +#define DDR_PLL_FREQ 266 +#define CONFIG_SPL_AM33XX_DO_NOT_ENABLE_RTC32K + +#define BOARD_DFU_BUTTON_GPIO 27 +#define BOARD_DFU_BUTTON_LED 64 + +#undef CONFIG_DOS_PARTITION +#undef CONFIG_CMD_FAT + + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define EEPROM_ADDR_DDR3 0x90 +#define EEPROM_ADDR_CHIP 0x120 + +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 + +#undef CONFIG_SPL_NET_SUPPORT +#undef CONFIG_SPL_NET_VCI_STRING +#undef CONFIG_SPL_ETH_SUPPORT + +#undef CONFIG_MII +#undef CONFIG_PHY_GIGE +#define CONFIG_PHY_ADDR 0 +#define CONFIG_PHY_SMSC + +#define CONFIG_FACTORYSET + +/* Watchdog */ +#define CONFIG_OMAP_WATCHDOG + +#ifndef CONFIG_SPL_BUILD + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=dxr2\0" \ + "nand_img_size=0x300000\0" \ + "optargs=\0" \ + CONFIG_COMMON_ENV_SETTINGS + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTCOMMAND \ +"if dfubutton; then " \ + "run dfu_start; " \ + "reset; " \ +"fi;" \ +"if ping ${serverip}; then " \ + "run net_nfs; " \ +"fi;" \ +"run nand_boot;" + +#else +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif +#endif /* CONFIG_SPL_BUILD */ +#endif /* ! __CONFIG_DXR2_H */ diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h new file mode 100644 index 00000000000..20b0f9ab4d7 --- /dev/null +++ b/include/configs/pxm2.h @@ -0,0 +1,153 @@ +/* + * siemens pxm2 + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_PXM2_H +#define __CONFIG_PXM2_H + +#define CONFIG_SIEMENS_PXM2 +#define MACH_TYPE_PXM2 4309 +#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_PXM2 + +#include "siemens-am33x-common.h" + +#define CONFIG_SYS_MPUCLK 720 +#define DXR2_IOCTRL_VAL 0x18b +#define DDR_PLL_FREQ 266 + +#define BOARD_DFU_BUTTON_GPIO 59 +#define BOARD_DFU_BUTTON_LED 117 +#define BOARD_LCD_POWER 111 +#define BOARD_BACK_LIGHT 112 +#define BOARD_TOUCH_POWER 57 + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + + +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x300 + +#undef CONFIG_SPL_NET_SUPPORT +#undef CONFIG_SPL_NET_VCI_STRING +#undef CONFIG_SPL_ETH_SUPPORT + +#define CONFIG_PHY_ADDR 0 +#define CONFIG_PHY_ATHEROS + +#define CONFIG_FACTORYSET + +/* UBI Support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#endif + +/* Watchdog */ +#define CONFIG_OMAP_WATCHDOG + +#ifndef CONFIG_SPL_BUILD + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=pxm2\0" \ + "nand_img_size=0x500000\0" \ + "optargs=\0" \ + CONFIG_COMMON_ENV_SETTINGS \ + "mmc_dev=0\0" \ + "mmc_root=/dev/mmcblk0p2 rw\0" \ + "mmc_root_fs_type=ext4 rootwait\0" \ + "mmc_load_uimage=" \ + "mmc rescan; " \ + "setenv bootfile uImage;" \ + "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \ + "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "mmc_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv bootargs ${bootargs} " \ + "root=${mmc_root} ${mtdparts}" \ + "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \ + "eth=${ethaddr} " \ + "\0" \ + "mmc_boot=run mmc_args; " \ + "run mmc_load_uimage; " \ + "bootm ${kloadaddr}\0" \ + "" + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTCOMMAND \ + "if dfubutton; then " \ + "run dfu_start; " \ + "reset; " \ + "fi; " \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmc_dev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run mmc_load_uimage; then " \ + "run mmc_args;" \ + "bootm ${kloadaddr};" \ + "fi;" \ + "fi;" \ + "run nand_boot;" \ + "if ping ${serverip}; then " \ + "run net_nfs; " \ + "fi; " + +#else +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_VIDEO +#if defined(CONFIG_VIDEO) +#define CONFIG_VIDEO_DA8XX +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CMD_BMP +#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE +#define PWM_TICKS 0x1388 +#define PWM_DUTY 0x200 +#endif + +#endif /* ! __CONFIG_PXM2_H */ diff --git a/include/configs/rut.h b/include/configs/rut.h new file mode 100644 index 00000000000..7c94644de85 --- /dev/null +++ b/include/configs/rut.h @@ -0,0 +1,156 @@ +/* + * siemens rut + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RUT_H +#define __CONFIG_RUT_H + +#define CONFIG_SIEMENS_RUT +#define MACH_TYPE_RUT 4316 +#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT + +#include "siemens-am33x-common.h" + +#define CONFIG_SYS_MPUCLK 600 +#define RUT_IOCTRL_VAL 0x18b +#define DDR_PLL_FREQ 303 + + /* Physical Memory Map */ +#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ + +/* I2C Configuration */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ + +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 + +#undef CONFIG_SPL_NET_SUPPORT +#undef CONFIG_SPL_NET_VCI_STRING +#undef CONFIG_SPL_ETH_SUPPORT + +#define CONFIG_PHY_ADDR 1 +#define CONFIG_PHY_NATSEMI + +#define CONFIG_FACTORYSET + +/* UBI Support */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#endif + +/* Watchdog */ +#define WATCHDOG_TRIGGER_GPIO 14 + +#ifndef CONFIG_SPL_BUILD + +/* Default env settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=rut\0" \ + "splashpos=488,352\0" \ + "optargs=fixrtc --no-log consoleblank=0 \0" \ + CONFIG_COMMON_ENV_SETTINGS \ + "mmc_dev=0\0" \ + "mmc_root=/dev/mmcblk0p2 rw\0" \ + "mmc_root_fs_type=ext4 rootwait\0" \ + "mmc_load_uimage=" \ + "mmc rescan; " \ + "setenv bootfile uImage;" \ + "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \ + "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from mmc ...; " \ + "env import -t $loadaddr $filesize\0" \ + "mmc_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv bootargs ${bootargs} " \ + "root=${mmc_root} ${mtdparts}" \ + "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \ + "eth=${ethaddr} " \ + "\0" \ + "mmc_boot=run mmc_args; " \ + "run mmc_load_uimage; " \ + "bootm ${kloadaddr}\0" \ + "" + +#ifndef CONFIG_RESTORE_FLASH +/* set to negative value for no autoboot */ +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTCOMMAND \ + "if mmc rescan; then " \ + "echo SD/MMC found on device ${mmc_dev};" \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "run importbootenv;" \ + "fi;" \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run mmc_load_uimage; then " \ + "run mmc_args;" \ + "bootm ${kloadaddr};" \ + "fi;" \ + "fi;" \ + "run nand_boot;" \ + "if ping ${serverip}; then " \ + "run net_nfs; " \ + "fi; " + +#else +#define CONFIG_BOOTDELAY 0 + +#define CONFIG_BOOTCOMMAND \ + "setenv autoload no; " \ + "dhcp; " \ + "if tftp 80000000 debrick.scr; then " \ + "source 80000000; " \ + "fi" +#endif + +#endif /* CONFIG_SPL_BUILD */ + +#ifdef CONFIG_SPL_BUILD +#undef CONFIG_HW_WATCHDOG +#endif + +#define CONFIG_VIDEO +#if defined(CONFIG_VIDEO) +#define CONFIG_VIDEO_DA8XX +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CMD_BMP +#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE + +#define CONFIG_SPI +#define CONFIG_OMAP3_SPI + +#define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */ +#define CONFIG_ARCH_EARLY_INIT_R +#define CONFIG_FORMIKE +#endif + +#endif /* ! __CONFIG_RUT_H */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h new file mode 100644 index 00000000000..f0bac972fe0 --- /dev/null +++ b/include/configs/siemens-am33x-common.h @@ -0,0 +1,463 @@ +/* + * siemens am33x common board options + * (C) Copyright 2013 Siemens Schweiz AG + * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * U-Boot file:/include/configs/am335x_evm.h + * + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_SIEMENS_AM33X_COMMON_H +#define __CONFIG_SIEMENS_AM33X_COMMON_H + +#define CONFIG_AM33XX +#define CONFIG_OMAP +#define CONFIG_OMAP_COMMON + +#include + +#define CONFIG_DMA_COHERENT +#define CONFIG_DMA_COHERENT_SIZE (1 << 20) + +#define CONFIG_ENV_SIZE (0x2000) +#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "U-Boot# " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_SYS_NO_FLASH +#define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* commands to include */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_CACHE + +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#ifndef CONFIG_SPL_BUILD +#define CONFIG_ROOTPATH "/opt/eldk" +#endif + +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ENV_IS_NOWHERE + +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_AUTOLOAD "yes" + +/* Clock Defines */ +#define V_OSCK 24000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK) + +/* We set the max number of command args high to avoid HUSH bugs. */ +#define CONFIG_SYS_MAXARGS 32 + +/* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* + * memtest works on 8 MB in DRAM after skipping 32MB from + * start addr of ram disk + */ +#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024)) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ + + (8 * 1024 * 1024)) + +#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ +#define CONFIG_SYS_HZ 1000 /* 1ms clock */ + +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 + +#define CONFIG_SPI +#define CONFIG_OMAP3_SPI +#define CONFIG_MTD_DEVICE +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_WINBOND +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED (75000000) + + /* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ + GENERATED_GBL_DATA_SIZE) + /* Platform/Board specific defs */ +#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (48000000) +#define CONFIG_SYS_NS16550_COM1 0x44e09000 +#define CONFIG_SYS_NS16550_COM4 0x481a6000 + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SERIAL1 1 +#define CONFIG_CONS_INDEX 1 + +/* I2C Configuration */ +#define CONFIG_I2C +#define CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_DRIVER_OMAP24XX_I2C + + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_TEXT_BASE 0x402F0400 +#define CONFIG_SPL_MAX_SIZE (101 * 1024) +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_FS_FAT +#define CONFIG_SPL_I2C_SUPPORT + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT + +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_WATCHDOG_SUPPORT + +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 0 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 + +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_NAND_AM33XX_BCH +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_NAND_BASE +#define CONFIG_SPL_NAND_DRIVERS +#define CONFIG_SPL_NAND_ECC +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ + CONFIG_SYS_NAND_PAGE_SIZE) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + 34, 35, 36, 37, 38, 39, 40, 41, \ + 42, 43, 44, 45, 46, 47, 48, 49, \ + 50, 51, 52, 53, 54, 55, 56, 57, } + +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 14 + +#define CONFIG_SYS_NAND_ECCSTEPS 4 +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* + * Since SPL did pll and ddr initialization for us, + * we don't need to do it twice. + */ +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +#ifndef CONFIG_SPL_BUILD +/* + * USB configuration + */ +#define CONFIG_USB_MUSB_DSPS +#define CONFIG_ARCH_MISC_INIT +#define CONFIG_MUSB_GADGET +#define CONFIG_MUSB_PIO_ONLY +#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 +#define CONFIG_MUSB_HOST + +#define CONFIG_AM335X_USB0 +#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL +#define CONFIG_AM335X_USB1 +#define CONFIG_AM335X_USB1_MODE MUSB_HOST +#ifdef CONFIG_MUSB_HOST +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#endif + +#ifdef CONFIG_MUSB_GADGET +#define CONFIG_USB_ETHER +#define CONFIG_USB_ETH_RNDIS +#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" +#endif /* CONFIG_MUSB_GADGET */ + +#define CONFIG_USB_GADGET +#define CONFIG_USBDOWNLOAD_GADGET + +/* USB TI's IDs */ +#define CONFIG_USBD_HS +#define CONFIG_G_DNL_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_PRODUCT_NUM 0x4a47 +#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" + +/* USB Device Firmware Update support */ +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_NAND +#define CONFIG_CMD_DFU +#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20) + +#endif /* CONFIG_SPL_BUILD */ + +/* + * Default to using SPI for environment, etc. We have multiple copies + * of SPL as the ROM will check these locations. + * 0x0 - 0x20000 : First copy of SPL + * 0x20000 - 0x40000 : Second copy of SPL + * 0x40000 - 0x60000 : Third copy of SPL + * 0x60000 - 0x80000 : Fourth copy of SPL + * 0x80000 - 0xDF000 : U-Boot + * 0xDF000 - 0xE0000 : U-Boot Environment + * 0xE0000 - 0x442000 : Linux Kernel + * 0x442000 - 0x800000 : Userland + */ +#if defined(CONFIG_SPI_BOOT) +# undef CONFIG_ENV_IS_NOWHERE +# define CONFIG_ENV_IS_IN_SPI_FLASH +# define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED +# define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */ +# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ +#endif /* SPI support */ + +/* Unsupported features */ +#undef CONFIG_USE_IRQ + +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_DRIVER_TI_CPSW +#define CONFIG_MII +#define CONFIG_PHY_GIGE +#define CONFIG_PHYLIB +#define CONFIG_CMD_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_NET_MULTI + +#define CONFIG_NAND +/* NAND support */ +#ifdef CONFIG_NAND +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MTDPARTS + +#define MTDIDS_NAME_STR "omap2-nand.0" +#define MTDIDS_DEFAULT "nand0=" MTDIDS_NAME_STR +#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \ + "128k(spl)," \ + "128k(spl.backup1)," \ + "128k(spl.backup2)," \ + "128k(spl.backup3)," \ + "1920k(u-boot)," \ + "128k(uboot.env)," \ + "5120k(kernel_a)," \ + "5120k(kernel_b)," \ + "8192k(mtdoops)," \ + "-(rootfs)" +/* + * chip-size = 256MiB + *| name | size | address area | + *------------------------------------------------------- + *| spl | 128.000 KiB | 0x 0..0x 1ffff | + *| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff | + *| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff | + *| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff | + *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff | + *| uboot.env | 128.000 KiB | 0x 260000..0x 27ffff | + *| kernel_a | 5.000 MiB | 0x 280000..0x 77ffff | + *| kernel_b | 5.000 MiB | 0x 780000..0x c7ffff | + *| mtdoops | 8.000 MiB | 0x c80000..0x 147ffff | + *| rootfs | 235.500 MiB | 0x 1480000..0x fffffff | + *------------------------------------------------------- + */ + +#define DFU_ALT_INFO_NAND \ + "spl part 0 1;" \ + "spl.backup1 part 0 2;" \ + "spl.backup2 part 0 3;" \ + "spl.backup3 part 0 4;" \ + "u-boot part 0 5;" \ + "u-boot.env part 0 6;" \ + "kernel_a part 0 7;" \ + "kernel_b part 0 8;" \ + "rootfs partubi 0 10" + +#define CONFIG_COMMON_ENV_SETTINGS \ + "verify=no \0" \ + "project_dir=systemone\0" \ + "loadaddr=0x82000000\0" \ + "kloadaddr=0x81000000\0" \ + "script_addr=0x81900000\0" \ + "console=console=ttyMTD,mtdoops console=ttyO0,115200n8\0" \ + "active_set=a\0" \ + "nand_active_ubi_vol=rootfs_a\0" \ + "nand_root_fs_type=ubifs rootwait=1\0" \ + "nand_src_addr=0x280000\0" \ + "nand_src_addr_a=0x280000\0" \ + "nand_src_addr_b=0x780000\0" \ + "nfsopts=nolock rw mem=128M\0" \ + "ip_method=none\0" \ + "bootenv=uEnv.txt\0" \ + "bootargs_defaults=setenv bootargs " \ + "console=${console} " \ + "${optargs}\0" \ + "nand_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv nand_active_ubi_vol rootfs_${active_set};" \ + "setenv ${active_set} true;" \ + "if test -n ${a}; then " \ + "setenv nand_src_addr ${nand_src_addr_a};" \ + "fi;" \ + "if test -n ${b}; then " \ + "setenv nand_src_addr ${nand_src_addr_b};" \ + "fi;" \ + "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ + "ubi.mtd=9,2048;" \ + "setenv bootargs ${bootargs} " \ + "root=${nand_root} noinitrd ${mtdparts} " \ + "rootfstype=${nand_root_fs_type} ip=${ip_method} " \ + "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \ + "=mtdoops\0" \ + "dfu_args=run bootargs_defaults;" \ + "setenv bootargs ${bootargs} ;" \ + "mtdparts default; " \ + "dfu nand 0; \0" \ + "dfu_alt_info=" DFU_ALT_INFO_NAND "\0" \ + "net_args=run bootargs_defaults;" \ + "mtdparts default;" \ + "setenv bootfile ${project_dir}/kernel/uImage;" \ + "setenv rootpath /home/projects/${project_dir}/rootfs;" \ + "setenv bootargs ${bootargs} " \ + "root=/dev/nfs ${mtdparts} " \ + "nfsroot=${serverip}:${rootpath},${nfsopts} " \ + "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ + "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ + "nand_boot=echo Booting from nand, active set ${active_set} ...; " \ + "run nand_args; " \ + "nand read.i ${kloadaddr} ${nand_src_addr} " \ + "${nand_img_size}; bootm ${kloadaddr}\0" \ + "net_nfs=echo Booting from network ...; " \ + "run net_args; " \ + "tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \ + "bootm ${kloadaddr}\0" \ + "flash_self=run nand_boot\0" \ + "flash_self_test=setenv bootargs_defaults ${bootargs_defaults} test; " \ + "run nand_boot\0" \ + "dfu_start=echo Preparing for dfu mode ...; " \ + "run dfu_args; \0" \ + "preboot=echo; "\ + "echo Type 'run flash_self' to use kernel and root " \ + "filesystem on memory; echo Type 'run flash_self_test' to " \ + "use kernel and root filesystem on memory, boot in test " \ + "mode; echo Not ready yet: 'run flash_nfs' to use kernel " \ + "from memory and root filesystem over NFS; echo Type " \ + "'run net_nfs' to get Kernel over TFTP and mount root " \ + "filesystem over NFS; echo Set active_set variable to 'a' " \ + "or 'b' to select kernel and rootfs partition; " \ + "echo" \ + "\0" + +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ + /* to access nand at */ + /* CS0 */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND + devices */ +#if !defined(CONFIG_SPI_BOOT) +#undef CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#endif +#endif + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_OMAP_GPIO +#endif + +/* Watchdog */ +#define CONFIG_HW_WATCHDOG + +/* Stop autoboot with ESC ESC key detected */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR "\x1b\x1b" +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \ + "press \"\" to stop\n", bootdelay + +#endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */ diff --git a/tools/logos/siemens.bmp b/tools/logos/siemens.bmp new file mode 100644 index 00000000000..bff2b190e0c Binary files /dev/null and b/tools/logos/siemens.bmp differ -- cgit v1.3.1 From 901ce27c6f018992b7dd6c08d3c98cf217cc4c96 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 28 Aug 2013 12:00:18 -0400 Subject: siemens-am33x-common.h: Always build CONFIG_OMAP_GPIO support The MMC driver relies on this block now. Signed-off-by: Tom Rini --- include/configs/siemens-am33x-common.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index f0bac972fe0..5426ee8720c 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -447,9 +447,7 @@ #endif #endif -#ifndef CONFIG_SPL_BUILD #define CONFIG_OMAP_GPIO -#endif /* Watchdog */ #define CONFIG_HW_WATCHDOG -- cgit v1.3.1 From bce8837071617a13f8e28f60400ee826b3f8a308 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 26 Aug 2013 20:43:33 +0200 Subject: ARM: mxs: tools: Add mkimage support for MXS bootstream Add mkimage support for generating and verifying MXS bootstream. The implementation here is mostly a glue code between MXSSB v0.4 and mkimage, but the long-term goal is to rectify this and merge MXSSB with mkimage more tightly. Once this code is properly in U-Boot, MXSSB shall be deprecated in favor of mkimage-mxsimage support. Note that the mxsimage generator needs libcrypto from OpenSSL, I therefore enabled the libcrypto/libssl unconditionally. MXSSB: http://git.denx.de/?p=mxssb.git;a=summary The code is based on research presented at: http://www.rockbox.org/wiki/SbFileFormat Signed-off-by: Marek Vasut Cc: Tom Rini Cc: Fabio Estevam Cc: Stefano Babic Cc: Otavio Salvador --- arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg | 6 + arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg | 8 + common/image.c | 1 + config.mk | 9 + doc/README.mxsimage | 165 ++ include/image.h | 1 + tools/Makefile | 2 + tools/mkimage.c | 2 + tools/mkimage.h | 1 + tools/mxsimage.c | 2347 ++++++++++++++++++++++++++ tools/mxsimage.h | 230 +++ 11 files changed, 2772 insertions(+) create mode 100644 arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg create mode 100644 arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg create mode 100644 doc/README.mxsimage create mode 100644 tools/mxsimage.c create mode 100644 tools/mxsimage.h (limited to 'include') diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg new file mode 100644 index 00000000000..811876736c2 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -0,0 +1,6 @@ +SECTION 0x0 BOOTABLE + TAG LAST + LOAD 0x0 spl/u-boot-spl.bin + CALL 0x14 0x0 + LOAD 0x40000100 u-boot.bin + CALL 0x40000100 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg new file mode 100644 index 00000000000..ea772f0c869 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -0,0 +1,8 @@ +SECTION 0x0 BOOTABLE + TAG LAST + LOAD 0x0 spl/u-boot-spl.bin + LOAD IVT 0x8000 0x14 + CALL HAB 0x8000 0x0 + LOAD 0x40000100 u-boot.bin + LOAD IVT 0x8000 0x40000100 + CALL HAB 0x8000 0x0 diff --git a/common/image.c b/common/image.c index 56a5a626e6a..2c88091e6de 100644 --- a/common/image.c +++ b/common/image.c @@ -135,6 +135,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_SCRIPT, "script", "Script", }, { IH_TYPE_STANDALONE, "standalone", "Standalone Program", }, { IH_TYPE_UBLIMAGE, "ublimage", "Davinci UBL image",}, + { IH_TYPE_MXSIMAGE, "mxsimage", "Freescale MXS Boot Image",}, { -1, "", "", }, }; diff --git a/config.mk b/config.mk index 499eed13486..3b92f568eeb 100644 --- a/config.mk +++ b/config.mk @@ -194,6 +194,15 @@ LDFLAGS_FINAL += --gc-sections endif # TODO(sjg@chromium.org): Is this correct on Mac OS? + +# MXSImage needs LibSSL +ifneq ($(CONFIG_MX23)$(CONFIG_MX28),) +HOSTLIBS += -lssl -lcrypto +# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register +# the mxsimage support within tools/mxsimage.c . +HOSTCFLAGS += -DCONFIG_MXS +endif + ifdef CONFIG_FIT_SIGNATURE HOSTLIBS += -lssl -lcrypto diff --git a/doc/README.mxsimage b/doc/README.mxsimage new file mode 100644 index 00000000000..88a2caf3e62 --- /dev/null +++ b/doc/README.mxsimage @@ -0,0 +1,165 @@ +Freescale i.MX233/i.MX28 SB image generator via mkimage +======================================================= + +This tool allows user to produce SB BootStream encrypted with a zero key. +Such a BootStream is then bootable on i.MX23/i.MX28. + +Usage -- producing image: +========================= +The mxsimage tool is targeted to be a simple replacement for the elftosb2 . +To generate an image, write an image configuration file and run: + + mkimage -A arm -O u-boot -T mxsimage -n \ + + +The output bootstream file is usually using the .sb file extension. Note +that the example configuration files for producing bootable BootStream with +the U-Boot bootloader can be found under arch/arm/boot/cpu/arm926ejs/mxs/ +directory. See the following files: + + mxsimage.mx23.cfg -- This is an example configuration for i.MX23 + mxsimage.mx28.cfg -- This is an example configuration for i.MX28 + +Each configuration file uses very simple instruction semantics and a few +additional rules have to be followed so that a useful image can be produced. +These semantics and rules will be outlined now. + +- Each line of the configuration file contains exactly one instruction. +- Every numeric value must be encoded in hexadecimal and in format 0xabcdef12 . +- The configuration file is a concatenation of blocks called "sections" and + optionally "DCD blocks" (see below). + - Each "section" is started by the "SECTION" instruction. + - The "SECTION" instruction has the following semantics: + + SECTION u32_section_number [BOOTABLE] + - u32_section_number :: User-selected ID of the section + - BOOTABLE :: Sets the section as bootable + + - A bootable section is one from which the BootROM starts executing + subsequent instructions or code. Exactly one section must be selected + as bootable, usually the one containing the instructions and data to + load the bootloader. + + - A "SECTION" must be immediatelly followed by a "TAG" instruction. + - The "TAG" instruction has the following semantics: + + TAG [LAST] + - LAST :: Flag denoting the last section in the file + + - After a "TAG" unstruction, any of the following instructions may follow + in any order and any quantity: + + NOOP + - This instruction does nothing + + LOAD u32_address string_filename + - Instructs the BootROM to load file pointed by "string_filename" onto + address "u32_address". + + LOAD IVT u32_address u32_IVT_entry_point + - Crafts and loads IVT onto address "u32_address" with the entry point + of u32_IVT_entry_point. + - i.MX28-specific instruction! + + LOAD DCD u32_address u32_DCD_block_ID + - Loads the DCD block with ID "u32_DCD_block_ID" onto address + "u32_address" and executes the contents of this DCD block + - i.MX28-specific instruction! + + FILL u32_address u32_pattern u32_length + - Starts to write memory from addres "u32_address" with a pattern + specified by "u32_pattern". Writes exactly "u32_length" bytes of the + pattern. + + JUMP [HAB] u32_address [u32_r0_arg] + - Jumps onto memory address specified by "u32_address" by setting this + address in PT. The BootROM will pass the "u32_r0_arg" value in ARM + register "r0" to the executed code if this option is specified. + Otherwise, ARM register "r0" will default to value 0x00000000. The + optional "HAB" flag is i.MX28-specific flag turning on the HAB boot. + + CALL [HAB] u32_address [u32_r0_arg] + - See JUMP instruction above, as the operation is exactly the same with + one difference. The CALL instruction does allow returning into the + BootROM from the executed code. U-Boot makes use of this in it's SPL + code. + + MODE string_mode + - Restart the CPU and start booting from device specified by the + "string_mode" argument. The "string_mode" differs for each CPU + and can be: + i.MX23, string_mode = USB/I2C/SPI1_FLASH/SPI2_FLASH/NAND_BCH + JTAG/SPI3_EEPROM/SD_SSP0/SD_SSP1 + i.MX28, string_mode = USB/I2C/SPI2_FLASH/SPI3_FLASH/NAND_BCH + JTAG/SPI2_EEPROM/SD_SSP0/SD_SSP1 + + - An optional "DCD" blocks can be added at the begining of the configuration + file. Note that the DCD is only supported on i.MX28. + - The DCD blocks must be inserted before the first "section" in the + configuration file. + - The DCD block has the following semantics: + + DCD u32_DCD_block_ID + - u32_DCD_block_ID :: The ID number of the DCD block, must match + the ID number used by "LOAD DCD" instruction. + + - The DCD block must be followed by one of the following instructions. All + of the instructions operate either on 1, 2 or 4 bytes. This is selected by + the 'n' suffix of the instruction: + + WRITE.n u32_address u32_value + - Write the "u32_value" to the "u32_address" address. + + ORR.n u32_address u32_value + - Read the "u32_address", perform a bitwise-OR with the "u32_value" and + write the result back to "u32_address". + + ANDC.n u32_address u32_value + - Read the "u32_address", perform a bitwise-AND with the complement of + "u32_value" and write the result back to "u32_address". + + EQZ.n u32_address u32_count + - Read the "u32_address" at most "u32_count" times and test if the value + read is zero. If it is, break the loop earlier. + + NEZ.n u32_address u32_count + - Read the "u32_address" at most "u32_count" times and test if the value + read is non-zero. If it is, break the loop earlier. + + EQ.n u32_address u32_mask + - Read the "u32_address" in a loop and test if the result masked with + "u32_mask" equals the "u32_mask". If the values are equal, break the + reading loop. + + NEQ.n u32_address u32_mask + - Read the "u32_address" in a loop and test if the result masked with + "u32_mask" does not equal the "u32_mask". If the values are not equal, + break the reading loop. + + NOOP + - This instruction does nothing. + +- If the verbose output from the BootROM is enabled, the BootROM will produce a + letter on the Debug UART for each instruction it started processing. Here is a + mapping between the above instructions and the BootROM verbose output: + + H -- SB Image header loaded + T -- TAG instruction + N -- NOOP instruction + L -- LOAD instruction + F -- FILL instruction + J -- JUMP instruction + C -- CALL instruction + M -- MODE instruction + +Usage -- verifying image: +========================= + +The mxsimage can also verify and dump contents of an image. Use the following +syntax to verify and dump contents of an image: + + mkimage -l + +This will output all the information from the SB image header and all the +instructions contained in the SB image. It will also check if the various +checksums in the SB image are correct. diff --git a/include/image.h b/include/image.h index f93a39389a4..ee6eb8d2464 100644 --- a/include/image.h +++ b/include/image.h @@ -212,6 +212,7 @@ struct lmb; #define IH_TYPE_AISIMAGE 13 /* TI Davinci AIS Image */ #define IH_TYPE_KERNEL_NOLOAD 14 /* OS Kernel Image, can run from any load address */ #define IH_TYPE_PBLIMAGE 15 /* Freescale PBL Boot Image */ +#define IH_TYPE_MXSIMAGE 16 /* Freescale MXSBoot Image */ /* * Compression Types diff --git a/tools/Makefile b/tools/Makefile index 33fad6badba..bbae5a2266d 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -83,6 +83,7 @@ NOPED_OBJ_FILES-y += aisimage.o NOPED_OBJ_FILES-y += kwbimage.o NOPED_OBJ_FILES-y += pblimage.o NOPED_OBJ_FILES-y += imximage.o +NOPED_OBJ_FILES-y += mxsimage.o NOPED_OBJ_FILES-y += image-host.o NOPED_OBJ_FILES-y += omapimage.o NOPED_OBJ_FILES-y += mkenvimage.o @@ -209,6 +210,7 @@ $(obj)mkimage$(SFX): $(obj)aisimage.o \ $(obj)image-host.o \ $(FIT_SIG_OBJS) \ $(obj)imximage.o \ + $(obj)mxsimage.o \ $(obj)kwbimage.o \ $(obj)pblimage.o \ $(obj)md5.o \ diff --git a/tools/mkimage.c b/tools/mkimage.c index 58d25faed4b..7f221013e38 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -145,6 +145,8 @@ main (int argc, char **argv) init_kwb_image_type (); /* Init Freescale imx Boot image generation/list support */ init_imx_image_type (); + /* Init Freescale mxs Boot image generation/list support */ + init_mxs_image_type(); /* Init FIT image generation/list support */ init_fit_image_type (); /* Init TI OMAP Boot image generation/list support */ diff --git a/tools/mkimage.h b/tools/mkimage.h index ecb30322824..af491544e42 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -161,6 +161,7 @@ void init_pbl_image_type(void); void init_ais_image_type(void); void init_kwb_image_type (void); void init_imx_image_type (void); +void init_mxs_image_type(void); void init_default_image_type (void); void init_fit_image_type (void); void init_ubl_image_type(void); diff --git a/tools/mxsimage.c b/tools/mxsimage.c new file mode 100644 index 00000000000..5db19b216fa --- /dev/null +++ b/tools/mxsimage.c @@ -0,0 +1,2347 @@ +/* + * Freescale i.MX23/i.MX28 SB image generator + * + * Copyright (C) 2012-2013 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifdef CONFIG_MXS + +#include +#include +#include +#include +#include +#include + +#include + +#include "mkimage.h" +#include "mxsimage.h" +#include + + +/* + * DCD block + * |-Write to address command block + * | 0xf00 == 0xf33d + * | 0xba2 == 0xb33f + * |-ORR address with mask command block + * | 0xf00 |= 0x1337 + * |-Write to address command block + * | 0xba2 == 0xd00d + * : + */ +#define SB_HAB_DCD_WRITE 0xccUL +#define SB_HAB_DCD_CHECK 0xcfUL +#define SB_HAB_DCD_NOOP 0xc0UL +#define SB_HAB_DCD_MASK_BIT (1 << 3) +#define SB_HAB_DCD_SET_BIT (1 << 4) + +/* Addr.n = Value.n */ +#define SB_DCD_WRITE \ + (SB_HAB_DCD_WRITE << 24) +/* Addr.n &= ~Value.n */ +#define SB_DCD_ANDC \ + ((SB_HAB_DCD_WRITE << 24) | SB_HAB_DCD_SET_BIT) +/* Addr.n |= Value.n */ +#define SB_DCD_ORR \ + ((SB_HAB_DCD_WRITE << 24) | SB_HAB_DCD_SET_BIT | SB_HAB_DCD_MASK_BIT) +/* (Addr.n & Value.n) == 0 */ +#define SB_DCD_CHK_EQZ \ + (SB_HAB_DCD_CHECK << 24) +/* (Addr.n & Value.n) == Value.n */ +#define SB_DCD_CHK_EQ \ + ((SB_HAB_DCD_CHECK << 24) | SB_HAB_DCD_SET_BIT) +/* (Addr.n & Value.n) != Value.n */ +#define SB_DCD_CHK_NEQ \ + ((SB_HAB_DCD_CHECK << 24) | SB_HAB_DCD_MASK_BIT) +/* (Addr.n & Value.n) != 0 */ +#define SB_DCD_CHK_NEZ \ + ((SB_HAB_DCD_CHECK << 24) | SB_HAB_DCD_SET_BIT | SB_HAB_DCD_MASK_BIT) +/* NOP */ +#define SB_DCD_NOOP \ + (SB_HAB_DCD_NOOP << 24) + +struct sb_dcd_ctx { + struct sb_dcd_ctx *dcd; + + uint32_t id; + + /* The DCD block. */ + uint32_t *payload; + /* Size of the whole DCD block. */ + uint32_t size; + + /* Pointer to previous DCD command block. */ + uint32_t *prev_dcd_head; +}; + +/* + * IMAGE + * |-SECTION + * | |-CMD + * | |-CMD + * | `-CMD + * |-SECTION + * | |-CMD + * : : + */ +struct sb_cmd_list { + char *cmd; + size_t len; + unsigned int lineno; +}; + +struct sb_cmd_ctx { + uint32_t size; + + struct sb_cmd_ctx *cmd; + + uint8_t *data; + uint32_t length; + + struct sb_command payload; + struct sb_command c_payload; +}; + +struct sb_section_ctx { + uint32_t size; + + /* Section flags */ + unsigned int boot:1; + + struct sb_section_ctx *sect; + + struct sb_cmd_ctx *cmd_head; + struct sb_cmd_ctx *cmd_tail; + + struct sb_sections_header payload; +}; + +struct sb_image_ctx { + unsigned int in_section:1; + unsigned int in_dcd:1; + /* Image configuration */ + unsigned int verbose_boot:1; + unsigned int silent_dump:1; + char *input_filename; + char *output_filename; + char *cfg_filename; + uint8_t image_key[16]; + + /* Number of section in the image */ + unsigned int sect_count; + /* Bootable section */ + unsigned int sect_boot; + unsigned int sect_boot_found:1; + + struct sb_section_ctx *sect_head; + struct sb_section_ctx *sect_tail; + + struct sb_dcd_ctx *dcd_head; + struct sb_dcd_ctx *dcd_tail; + + EVP_CIPHER_CTX cipher_ctx; + EVP_MD_CTX md_ctx; + uint8_t digest[32]; + struct sb_key_dictionary_key sb_dict_key; + + struct sb_boot_image_header payload; +}; + +/* + * Instruction semantics: + * NOOP + * TAG [LAST] + * LOAD address file + * LOAD IVT address IVT_entry_point + * FILL address pattern length + * JUMP [HAB] address [r0_arg] + * CALL [HAB] address [r0_arg] + * MODE mode + * For i.MX23, mode = USB/I2C/SPI1_FLASH/SPI2_FLASH/NAND_BCH + * JTAG/SPI3_EEPROM/SD_SSP0/SD_SSP1 + * For i.MX28, mode = USB/I2C/SPI2_FLASH/SPI3_FLASH/NAND_BCH + * JTAG/SPI2_EEPROM/SD_SSP0/SD_SSP1 + */ + +/* + * AES libcrypto + */ +static int sb_aes_init(struct sb_image_ctx *ictx, uint8_t *iv, int enc) +{ + EVP_CIPHER_CTX *ctx = &ictx->cipher_ctx; + int ret; + + /* If there is no init vector, init vector is all zeroes. */ + if (!iv) + iv = ictx->image_key; + + EVP_CIPHER_CTX_init(ctx); + ret = EVP_CipherInit(ctx, EVP_aes_128_cbc(), ictx->image_key, iv, enc); + if (ret == 1) + EVP_CIPHER_CTX_set_padding(ctx, 0); + return ret; +} + +static int sb_aes_crypt(struct sb_image_ctx *ictx, uint8_t *in_data, + uint8_t *out_data, int in_len) +{ + EVP_CIPHER_CTX *ctx = &ictx->cipher_ctx; + int ret, outlen; + uint8_t *outbuf; + + outbuf = malloc(in_len); + if (!outbuf) + return -ENOMEM; + memset(outbuf, 0, sizeof(in_len)); + + ret = EVP_CipherUpdate(ctx, outbuf, &outlen, in_data, in_len); + if (!ret) { + ret = -EINVAL; + goto err; + } + + if (out_data) + memcpy(out_data, outbuf, outlen); + +err: + free(outbuf); + return ret; +} + +static int sb_aes_deinit(EVP_CIPHER_CTX *ctx) +{ + return EVP_CIPHER_CTX_cleanup(ctx); +} + +static int sb_aes_reinit(struct sb_image_ctx *ictx, int enc) +{ + int ret; + EVP_CIPHER_CTX *ctx = &ictx->cipher_ctx; + struct sb_boot_image_header *sb_header = &ictx->payload; + uint8_t *iv = sb_header->iv; + + ret = sb_aes_deinit(ctx); + if (!ret) + return ret; + return sb_aes_init(ictx, iv, enc); +} + +/* + * CRC32 + */ +static uint32_t crc32(uint8_t *data, uint32_t len) +{ + const uint32_t poly = 0x04c11db7; + uint32_t crc32 = 0xffffffff; + unsigned int byte, bit; + + for (byte = 0; byte < len; byte++) { + crc32 ^= data[byte] << 24; + + for (bit = 8; bit > 0; bit--) { + if (crc32 & (1UL << 31)) + crc32 = (crc32 << 1) ^ poly; + else + crc32 = (crc32 << 1); + } + } + + return crc32; +} + +/* + * Debug + */ +static void soprintf(struct sb_image_ctx *ictx, const char *fmt, ...) +{ + va_list ap; + + if (ictx->silent_dump) + return; + + va_start(ap, fmt); + vfprintf(stdout, fmt, ap); + va_end(ap); +} + +/* + * Code + */ +static time_t sb_get_timestamp(void) +{ + struct tm time_2000 = { + .tm_yday = 1, /* Jan. 1st */ + .tm_year = 100, /* 2000 */ + }; + time_t seconds_to_2000 = mktime(&time_2000); + time_t seconds_to_now = time(NULL); + + return seconds_to_now - seconds_to_2000; +} + +static int sb_get_time(time_t time, struct tm *tm) +{ + struct tm time_2000 = { + .tm_yday = 1, /* Jan. 1st */ + .tm_year = 0, /* 1900 */ + }; + const time_t seconds_to_2000 = mktime(&time_2000); + const time_t seconds_to_now = seconds_to_2000 + time; + struct tm *ret; + ret = gmtime_r(&seconds_to_now, tm); + return ret ? 0 : -EINVAL; +} + +static void sb_encrypt_sb_header(struct sb_image_ctx *ictx) +{ + EVP_MD_CTX *md_ctx = &ictx->md_ctx; + struct sb_boot_image_header *sb_header = &ictx->payload; + uint8_t *sb_header_ptr = (uint8_t *)sb_header; + + /* Encrypt the header, compute the digest. */ + sb_aes_crypt(ictx, sb_header_ptr, NULL, sizeof(*sb_header)); + EVP_DigestUpdate(md_ctx, sb_header_ptr, sizeof(*sb_header)); +} + +static void sb_encrypt_sb_sections_header(struct sb_image_ctx *ictx) +{ + EVP_MD_CTX *md_ctx = &ictx->md_ctx; + struct sb_section_ctx *sctx = ictx->sect_head; + struct sb_sections_header *shdr; + uint8_t *sb_sections_header_ptr; + const int size = sizeof(*shdr); + + while (sctx) { + shdr = &sctx->payload; + sb_sections_header_ptr = (uint8_t *)shdr; + + sb_aes_crypt(ictx, sb_sections_header_ptr, + ictx->sb_dict_key.cbc_mac, size); + EVP_DigestUpdate(md_ctx, sb_sections_header_ptr, size); + + sctx = sctx->sect; + }; +} + +static void sb_encrypt_key_dictionary_key(struct sb_image_ctx *ictx) +{ + EVP_MD_CTX *md_ctx = &ictx->md_ctx; + + sb_aes_crypt(ictx, ictx->image_key, ictx->sb_dict_key.key, + sizeof(ictx->sb_dict_key.key)); + EVP_DigestUpdate(md_ctx, &ictx->sb_dict_key, sizeof(ictx->sb_dict_key)); +} + +static void sb_decrypt_key_dictionary_key(struct sb_image_ctx *ictx) +{ + EVP_MD_CTX *md_ctx = &ictx->md_ctx; + + EVP_DigestUpdate(md_ctx, &ictx->sb_dict_key, sizeof(ictx->sb_dict_key)); + sb_aes_crypt(ictx, ictx->sb_dict_key.key, ictx->image_key, + sizeof(ictx->sb_dict_key.key)); +} + +static void sb_encrypt_tag(struct sb_image_ctx *ictx, + struct sb_cmd_ctx *cctx) +{ + EVP_MD_CTX *md_ctx = &ictx->md_ctx; + struct sb_command *cmd = &cctx->payload; + + sb_aes_crypt(ictx, (uint8_t *)cmd, + (uint8_t *)&cctx->c_payload, sizeof(*cmd)); + EVP_DigestUpdate(md_ctx, &cctx->c_payload, sizeof(*cmd)); +} + +static int sb_encrypt_image(struct sb_image_ctx *ictx) +{ + /* Start image-wide crypto. */ + EVP_MD_CTX_init(&ictx->md_ctx); + EVP_DigestInit(&ictx->md_ctx, EVP_sha1()); + + /* + * SB image header. + */ + sb_aes_init(ictx, NULL, 1); + sb_encrypt_sb_header(ictx); + + /* + * SB sections header. + */ + sb_encrypt_sb_sections_header(ictx); + + /* + * Key dictionary. + */ + sb_aes_reinit(ictx, 1); + sb_encrypt_key_dictionary_key(ictx); + + /* + * Section tags. + */ + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + struct sb_section_ctx *sctx = ictx->sect_head; + + while (sctx) { + cctx = sctx->cmd_head; + + sb_aes_reinit(ictx, 1); + + while (cctx) { + ccmd = &cctx->payload; + + sb_encrypt_tag(ictx, cctx); + + if (ccmd->header.tag == ROM_TAG_CMD) { + sb_aes_reinit(ictx, 1); + } else if (ccmd->header.tag == ROM_LOAD_CMD) { + sb_aes_crypt(ictx, cctx->data, cctx->data, + cctx->length); + EVP_DigestUpdate(&ictx->md_ctx, cctx->data, + cctx->length); + } + + cctx = cctx->cmd; + } + + sctx = sctx->sect; + }; + + /* + * Dump the SHA1 of the whole image. + */ + sb_aes_reinit(ictx, 1); + + EVP_DigestFinal(&ictx->md_ctx, ictx->digest, NULL); + sb_aes_crypt(ictx, ictx->digest, ictx->digest, sizeof(ictx->digest)); + + /* Stop the encryption session. */ + sb_aes_deinit(&ictx->cipher_ctx); + + return 0; +} + +static int sb_load_file(struct sb_cmd_ctx *cctx, char *filename) +{ + long real_size, roundup_size; + uint8_t *data; + long ret; + unsigned long size; + FILE *fp; + + if (!filename) { + fprintf(stderr, "ERR: Missing filename!\n"); + return -EINVAL; + } + + fp = fopen(filename, "r"); + if (!fp) + goto err_open; + + ret = fseek(fp, 0, SEEK_END); + if (ret < 0) + goto err_file; + + real_size = ftell(fp); + if (real_size < 0) + goto err_file; + + ret = fseek(fp, 0, SEEK_SET); + if (ret < 0) + goto err_file; + + roundup_size = roundup(real_size, SB_BLOCK_SIZE); + data = calloc(1, roundup_size); + if (!data) + goto err_file; + + size = fread(data, 1, real_size, fp); + if (size != (unsigned long)real_size) + goto err_alloc; + + cctx->data = data; + cctx->length = roundup_size; + + fclose(fp); + return 0; + +err_alloc: + free(data); +err_file: + fclose(fp); +err_open: + fprintf(stderr, "ERR: Failed to load file \"%s\"\n", filename); + return -EINVAL; +} + +static uint8_t sb_command_checksum(struct sb_command *inst) +{ + uint8_t *inst_ptr = (uint8_t *)inst; + uint8_t csum = 0; + unsigned int i; + + for (i = 0; i < sizeof(struct sb_command); i++) + csum += inst_ptr[i]; + + return csum; +} + +static int sb_token_to_long(char *tok, uint32_t *rid) +{ + char *endptr; + unsigned long id; + + if (tok[0] != '0' || tok[1] != 'x') { + fprintf(stderr, "ERR: Invalid hexadecimal number!\n"); + return -EINVAL; + } + + tok += 2; + + id = strtoul(tok, &endptr, 16); + if ((errno == ERANGE && id == ULONG_MAX) || (errno != 0 && id == 0)) { + fprintf(stderr, "ERR: Value can't be decoded!\n"); + return -EINVAL; + } + + /* Check for 32-bit overflow. */ + if (id > 0xffffffff) { + fprintf(stderr, "ERR: Value too big!\n"); + return -EINVAL; + } + + if (endptr == tok) { + fprintf(stderr, "ERR: Deformed value!\n"); + return -EINVAL; + } + + *rid = (uint32_t)id; + return 0; +} + +static int sb_grow_dcd(struct sb_dcd_ctx *dctx, unsigned int inc_size) +{ + uint32_t *tmp; + + if (!inc_size) + return 0; + + dctx->size += inc_size; + tmp = realloc(dctx->payload, dctx->size); + if (!tmp) + return -ENOMEM; + + dctx->payload = tmp; + + /* Assemble and update the HAB DCD header. */ + dctx->payload[0] = htonl((SB_HAB_DCD_TAG << 24) | + (dctx->size << 8) | + SB_HAB_VERSION); + + return 0; +} + +static int sb_build_dcd(struct sb_image_ctx *ictx, struct sb_cmd_list *cmd) +{ + struct sb_dcd_ctx *dctx; + + char *tok; + uint32_t id; + int ret; + + dctx = calloc(1, sizeof(*dctx)); + if (!dctx) + return -ENOMEM; + + ret = sb_grow_dcd(dctx, 4); + if (ret) + goto err_dcd; + + /* Read DCD block number. */ + tok = strtok(cmd->cmd, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: DCD block without number!\n", + cmd->lineno); + ret = -EINVAL; + goto err_dcd; + } + + /* Parse the DCD block number. */ + ret = sb_token_to_long(tok, &id); + if (ret) { + fprintf(stderr, "#%i ERR: Malformed DCD block number!\n", + cmd->lineno); + goto err_dcd; + } + + dctx->id = id; + + /* + * The DCD block is now constructed. Append it to the list. + * WARNING: The DCD size is still not computed and will be + * updated while parsing it's commands. + */ + if (!ictx->dcd_head) { + ictx->dcd_head = dctx; + ictx->dcd_tail = dctx; + } else { + ictx->dcd_tail->dcd = dctx; + ictx->dcd_tail = dctx; + } + + return 0; + +err_dcd: + free(dctx->payload); + free(dctx); + return ret; +} + +static int sb_build_dcd_block(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd, + uint32_t type) +{ + char *tok; + uint32_t address, value, length; + int ret; + + struct sb_dcd_ctx *dctx = ictx->dcd_tail; + uint32_t *dcd; + + if (dctx->prev_dcd_head && (type != SB_DCD_NOOP) && + ((dctx->prev_dcd_head[0] & 0xff0000ff) == type)) { + /* Same instruction as before, just append it. */ + ret = sb_grow_dcd(dctx, 8); + if (ret) + return ret; + } else if (type == SB_DCD_NOOP) { + ret = sb_grow_dcd(dctx, 4); + if (ret) + return ret; + + /* Update DCD command block pointer. */ + dctx->prev_dcd_head = dctx->payload + + dctx->size / sizeof(*dctx->payload) - 1; + + /* NOOP has only 4 bytes and no payload. */ + goto noop; + } else { + /* + * Either a different instruction block started now + * or this is the first instruction block. + */ + ret = sb_grow_dcd(dctx, 12); + if (ret) + return ret; + + /* Update DCD command block pointer. */ + dctx->prev_dcd_head = dctx->payload + + dctx->size / sizeof(*dctx->payload) - 3; + } + + dcd = dctx->payload + dctx->size / sizeof(*dctx->payload) - 2; + + /* + * Prepare the command. + */ + tok = strtok(cmd->cmd, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing DCD address!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + /* Read DCD destination address. */ + ret = sb_token_to_long(tok, &address); + if (ret) { + fprintf(stderr, "#%i ERR: Incorrect DCD address!\n", + cmd->lineno); + goto err; + } + + tok = strtok(NULL, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing DCD value!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + /* Read DCD operation value. */ + ret = sb_token_to_long(tok, &value); + if (ret) { + fprintf(stderr, "#%i ERR: Incorrect DCD value!\n", + cmd->lineno); + goto err; + } + + /* Fill in the new DCD entry. */ + dcd[0] = htonl(address); + dcd[1] = htonl(value); + +noop: + /* Update the DCD command block. */ + length = dctx->size - + ((dctx->prev_dcd_head - dctx->payload) * + sizeof(*dctx->payload)); + dctx->prev_dcd_head[0] = htonl(type | (length << 8)); + +err: + return ret; +} + +static int sb_build_section(struct sb_image_ctx *ictx, struct sb_cmd_list *cmd) +{ + struct sb_section_ctx *sctx; + struct sb_sections_header *shdr; + char *tok; + uint32_t bootable = 0; + uint32_t id; + int ret; + + sctx = calloc(1, sizeof(*sctx)); + if (!sctx) + return -ENOMEM; + + /* Read section number. */ + tok = strtok(cmd->cmd, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Section without number!\n", + cmd->lineno); + ret = -EINVAL; + goto err_sect; + } + + /* Parse the section number. */ + ret = sb_token_to_long(tok, &id); + if (ret) { + fprintf(stderr, "#%i ERR: Malformed section number!\n", + cmd->lineno); + goto err_sect; + } + + /* Read section's BOOTABLE flag. */ + tok = strtok(NULL, " "); + if (tok && (strlen(tok) == 8) && !strncmp(tok, "BOOTABLE", 8)) + bootable = SB_SECTION_FLAG_BOOTABLE; + + sctx->boot = bootable; + + shdr = &sctx->payload; + shdr->section_number = id; + shdr->section_flags = bootable; + + /* + * The section is now constructed. Append it to the list. + * WARNING: The section size is still not computed and will + * be updated while parsing it's commands. + */ + ictx->sect_count++; + + /* Mark that this section is bootable one. */ + if (bootable) { + if (ictx->sect_boot_found) { + fprintf(stderr, + "#%i WARN: Multiple bootable section!\n", + cmd->lineno); + } else { + ictx->sect_boot = id; + ictx->sect_boot_found = 1; + } + } + + if (!ictx->sect_head) { + ictx->sect_head = sctx; + ictx->sect_tail = sctx; + } else { + ictx->sect_tail->sect = sctx; + ictx->sect_tail = sctx; + } + + return 0; + +err_sect: + free(sctx); + return ret; +} + +static int sb_build_command_nop(struct sb_image_ctx *ictx) +{ + struct sb_section_ctx *sctx = ictx->sect_tail; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + + cctx = calloc(1, sizeof(*cctx)); + if (!cctx) + return -ENOMEM; + + ccmd = &cctx->payload; + + /* + * Construct the command. + */ + ccmd->header.checksum = 0x5a; + ccmd->header.tag = ROM_NOP_CMD; + + cctx->size = sizeof(*ccmd); + + /* + * Append the command to the last section. + */ + if (!sctx->cmd_head) { + sctx->cmd_head = cctx; + sctx->cmd_tail = cctx; + } else { + sctx->cmd_tail->cmd = cctx; + sctx->cmd_tail = cctx; + } + + return 0; +} + +static int sb_build_command_tag(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd) +{ + struct sb_section_ctx *sctx = ictx->sect_tail; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + char *tok; + + cctx = calloc(1, sizeof(*cctx)); + if (!cctx) + return -ENOMEM; + + ccmd = &cctx->payload; + + /* + * Prepare the command. + */ + /* Check for the LAST keyword. */ + tok = strtok(cmd->cmd, " "); + if (tok && !strcmp(tok, "LAST")) + ccmd->header.flags = ROM_TAG_CMD_FLAG_ROM_LAST_TAG; + + /* + * Construct the command. + */ + ccmd->header.checksum = 0x5a; + ccmd->header.tag = ROM_TAG_CMD; + + cctx->size = sizeof(*ccmd); + + /* + * Append the command to the last section. + */ + if (!sctx->cmd_head) { + sctx->cmd_head = cctx; + sctx->cmd_tail = cctx; + } else { + sctx->cmd_tail->cmd = cctx; + sctx->cmd_tail = cctx; + } + + return 0; +} + +static int sb_build_command_load(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd) +{ + struct sb_section_ctx *sctx = ictx->sect_tail; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + char *tok; + int ret, is_ivt = 0, is_dcd = 0; + uint32_t dest, dcd = 0; + + cctx = calloc(1, sizeof(*cctx)); + if (!cctx) + return -ENOMEM; + + ccmd = &cctx->payload; + + /* + * Prepare the command. + */ + tok = strtok(cmd->cmd, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing LOAD address or 'IVT'!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + /* Check for "IVT" flag. */ + if (!strcmp(tok, "IVT")) + is_ivt = 1; + if (!strcmp(tok, "DCD")) + is_dcd = 1; + if (is_ivt || is_dcd) { + tok = strtok(NULL, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing LOAD address!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + } + + /* Read load destination address. */ + ret = sb_token_to_long(tok, &dest); + if (ret) { + fprintf(stderr, "#%i ERR: Incorrect LOAD address!\n", + cmd->lineno); + goto err; + } + + /* Read filename or IVT entrypoint or DCD block ID. */ + tok = strtok(NULL, " "); + if (!tok) { + fprintf(stderr, + "#%i ERR: Missing LOAD filename or IVT ep or DCD block ID!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + if (is_ivt) { + /* Handle IVT. */ + struct sb_ivt_header *ivt; + uint32_t ivtep; + ret = sb_token_to_long(tok, &ivtep); + + if (ret) { + fprintf(stderr, + "#%i ERR: Incorrect IVT entry point!\n", + cmd->lineno); + goto err; + } + + ivt = calloc(1, sizeof(*ivt)); + if (!ivt) { + ret = -ENOMEM; + goto err; + } + + ivt->header = sb_hab_ivt_header(); + ivt->entry = ivtep; + ivt->self = dest; + + cctx->data = (uint8_t *)ivt; + cctx->length = sizeof(*ivt); + } else if (is_dcd) { + struct sb_dcd_ctx *dctx = ictx->dcd_head; + uint32_t dcdid; + uint8_t *payload; + uint32_t asize; + ret = sb_token_to_long(tok, &dcdid); + + if (ret) { + fprintf(stderr, + "#%i ERR: Incorrect DCD block ID!\n", + cmd->lineno); + goto err; + } + + while (dctx) { + if (dctx->id == dcdid) + break; + dctx = dctx->dcd; + } + + if (!dctx) { + fprintf(stderr, "#%i ERR: DCD block %08x not found!\n", + cmd->lineno, dcdid); + goto err; + } + + asize = roundup(dctx->size, SB_BLOCK_SIZE); + payload = calloc(1, asize); + if (!payload) { + ret = -ENOMEM; + goto err; + } + + memcpy(payload, dctx->payload, dctx->size); + + cctx->data = payload; + cctx->length = asize; + + /* Set the Load DCD flag. */ + dcd = ROM_LOAD_CMD_FLAG_DCD_LOAD; + } else { + /* Regular LOAD of a file. */ + ret = sb_load_file(cctx, tok); + if (ret) { + fprintf(stderr, "#%i ERR: Cannot load '%s'!\n", + cmd->lineno, tok); + goto err; + } + } + + if (cctx->length & (SB_BLOCK_SIZE - 1)) { + fprintf(stderr, "#%i ERR: Unaligned payload!\n", + cmd->lineno); + } + + /* + * Construct the command. + */ + ccmd->header.checksum = 0x5a; + ccmd->header.tag = ROM_LOAD_CMD; + ccmd->header.flags = dcd; + + ccmd->load.address = dest; + ccmd->load.count = cctx->length; + ccmd->load.crc32 = crc32(cctx->data, cctx->length); + + cctx->size = sizeof(*ccmd) + cctx->length; + + /* + * Append the command to the last section. + */ + if (!sctx->cmd_head) { + sctx->cmd_head = cctx; + sctx->cmd_tail = cctx; + } else { + sctx->cmd_tail->cmd = cctx; + sctx->cmd_tail = cctx; + } + + return 0; + +err: + free(cctx); + return ret; +} + +static int sb_build_command_fill(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd) +{ + struct sb_section_ctx *sctx = ictx->sect_tail; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + char *tok; + uint32_t address, pattern, length; + int ret; + + cctx = calloc(1, sizeof(*cctx)); + if (!cctx) + return -ENOMEM; + + ccmd = &cctx->payload; + + /* + * Prepare the command. + */ + tok = strtok(cmd->cmd, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing FILL address!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + /* Read fill destination address. */ + ret = sb_token_to_long(tok, &address); + if (ret) { + fprintf(stderr, "#%i ERR: Incorrect FILL address!\n", + cmd->lineno); + goto err; + } + + tok = strtok(NULL, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing FILL pattern!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + /* Read fill pattern address. */ + ret = sb_token_to_long(tok, &pattern); + if (ret) { + fprintf(stderr, "#%i ERR: Incorrect FILL pattern!\n", + cmd->lineno); + goto err; + } + + tok = strtok(NULL, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing FILL length!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + /* Read fill pattern address. */ + ret = sb_token_to_long(tok, &length); + if (ret) { + fprintf(stderr, "#%i ERR: Incorrect FILL length!\n", + cmd->lineno); + goto err; + } + + /* + * Construct the command. + */ + ccmd->header.checksum = 0x5a; + ccmd->header.tag = ROM_FILL_CMD; + + ccmd->fill.address = address; + ccmd->fill.count = length; + ccmd->fill.pattern = pattern; + + cctx->size = sizeof(*ccmd); + + /* + * Append the command to the last section. + */ + if (!sctx->cmd_head) { + sctx->cmd_head = cctx; + sctx->cmd_tail = cctx; + } else { + sctx->cmd_tail->cmd = cctx; + sctx->cmd_tail = cctx; + } + + return 0; + +err: + free(cctx); + return ret; +} + +static int sb_build_command_jump_call(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd, + unsigned int is_call) +{ + struct sb_section_ctx *sctx = ictx->sect_tail; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + char *tok; + uint32_t dest, arg = 0x0; + uint32_t hab = 0; + int ret; + const char *cmdname = is_call ? "CALL" : "JUMP"; + + cctx = calloc(1, sizeof(*cctx)); + if (!cctx) + return -ENOMEM; + + ccmd = &cctx->payload; + + /* + * Prepare the command. + */ + tok = strtok(cmd->cmd, " "); + if (!tok) { + fprintf(stderr, + "#%i ERR: Missing %s address or 'HAB'!\n", + cmd->lineno, cmdname); + ret = -EINVAL; + goto err; + } + + /* Check for "HAB" flag. */ + if (!strcmp(tok, "HAB")) { + hab = is_call ? ROM_CALL_CMD_FLAG_HAB : ROM_JUMP_CMD_FLAG_HAB; + tok = strtok(NULL, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing %s address!\n", + cmd->lineno, cmdname); + ret = -EINVAL; + goto err; + } + } + /* Read load destination address. */ + ret = sb_token_to_long(tok, &dest); + if (ret) { + fprintf(stderr, "#%i ERR: Incorrect %s address!\n", + cmd->lineno, cmdname); + goto err; + } + + tok = strtok(NULL, " "); + if (tok) { + ret = sb_token_to_long(tok, &arg); + if (ret) { + fprintf(stderr, + "#%i ERR: Incorrect %s argument!\n", + cmd->lineno, cmdname); + goto err; + } + } + + /* + * Construct the command. + */ + ccmd->header.checksum = 0x5a; + ccmd->header.tag = is_call ? ROM_CALL_CMD : ROM_JUMP_CMD; + ccmd->header.flags = hab; + + ccmd->call.address = dest; + ccmd->call.argument = arg; + + cctx->size = sizeof(*ccmd); + + /* + * Append the command to the last section. + */ + if (!sctx->cmd_head) { + sctx->cmd_head = cctx; + sctx->cmd_tail = cctx; + } else { + sctx->cmd_tail->cmd = cctx; + sctx->cmd_tail = cctx; + } + + return 0; + +err: + free(cctx); + return ret; +} + +static int sb_build_command_jump(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd) +{ + return sb_build_command_jump_call(ictx, cmd, 0); +} + +static int sb_build_command_call(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd) +{ + return sb_build_command_jump_call(ictx, cmd, 1); +} + +static int sb_build_command_mode(struct sb_image_ctx *ictx, + struct sb_cmd_list *cmd) +{ + struct sb_section_ctx *sctx = ictx->sect_tail; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + char *tok; + int ret; + unsigned int i; + uint32_t mode = 0xffffffff; + + cctx = calloc(1, sizeof(*cctx)); + if (!cctx) + return -ENOMEM; + + ccmd = &cctx->payload; + + /* + * Prepare the command. + */ + tok = strtok(cmd->cmd, " "); + if (!tok) { + fprintf(stderr, "#%i ERR: Missing MODE boot mode argument!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + for (i = 0; i < ARRAY_SIZE(modetable); i++) { + if (!strcmp(tok, modetable[i].name)) { + mode = modetable[i].mode; + break; + } + + if (!modetable[i].altname) + continue; + + if (!strcmp(tok, modetable[i].altname)) { + mode = modetable[i].mode; + break; + } + } + + if (mode == 0xffffffff) { + fprintf(stderr, "#%i ERR: Invalid MODE boot mode argument!\n", + cmd->lineno); + ret = -EINVAL; + goto err; + } + + /* + * Construct the command. + */ + ccmd->header.checksum = 0x5a; + ccmd->header.tag = ROM_MODE_CMD; + + ccmd->mode.mode = mode; + + cctx->size = sizeof(*ccmd); + + /* + * Append the command to the last section. + */ + if (!sctx->cmd_head) { + sctx->cmd_head = cctx; + sctx->cmd_tail = cctx; + } else { + sctx->cmd_tail->cmd = cctx; + sctx->cmd_tail = cctx; + } + + return 0; + +err: + free(cctx); + return ret; +} + +static int sb_prefill_image_header(struct sb_image_ctx *ictx) +{ + struct sb_boot_image_header *hdr = &ictx->payload; + + /* Fill signatures */ + memcpy(hdr->signature1, "STMP", 4); + memcpy(hdr->signature2, "sgtl", 4); + + /* SB Image version 1.1 */ + hdr->major_version = SB_VERSION_MAJOR; + hdr->minor_version = SB_VERSION_MINOR; + + /* Boot image major version */ + hdr->product_version.major = htons(0x999); + hdr->product_version.minor = htons(0x999); + hdr->product_version.revision = htons(0x999); + /* Boot image major version */ + hdr->component_version.major = htons(0x999); + hdr->component_version.minor = htons(0x999); + hdr->component_version.revision = htons(0x999); + + /* Drive tag must be 0x0 for i.MX23 */ + hdr->drive_tag = 0; + + hdr->header_blocks = + sizeof(struct sb_boot_image_header) / SB_BLOCK_SIZE; + hdr->section_header_size = + sizeof(struct sb_sections_header) / SB_BLOCK_SIZE; + hdr->timestamp_us = sb_get_timestamp() * 1000000; + + /* FIXME -- add proper config option */ + hdr->flags = ictx->verbose_boot ? SB_IMAGE_FLAG_VERBOSE : 0, + + /* FIXME -- We support only default key */ + hdr->key_count = 1; + + return 0; +} + +static int sb_postfill_image_header(struct sb_image_ctx *ictx) +{ + struct sb_boot_image_header *hdr = &ictx->payload; + struct sb_section_ctx *sctx = ictx->sect_head; + uint32_t kd_size, sections_blocks; + EVP_MD_CTX md_ctx; + + /* The main SB header size in blocks. */ + hdr->image_blocks = hdr->header_blocks; + + /* Size of the key dictionary, which has single zero entry. */ + kd_size = hdr->key_count * sizeof(struct sb_key_dictionary_key); + hdr->image_blocks += kd_size / SB_BLOCK_SIZE; + + /* Now count the payloads. */ + hdr->section_count = ictx->sect_count; + while (sctx) { + hdr->image_blocks += sctx->size / SB_BLOCK_SIZE; + sctx = sctx->sect; + } + + if (!ictx->sect_boot_found) { + fprintf(stderr, "ERR: No bootable section selected!\n"); + return -EINVAL; + } + hdr->first_boot_section_id = ictx->sect_boot; + + /* The n * SB section size in blocks. */ + sections_blocks = hdr->section_count * hdr->section_header_size; + hdr->image_blocks += sections_blocks; + + /* Key dictionary offset. */ + hdr->key_dictionary_block = hdr->header_blocks + sections_blocks; + + /* Digest of the whole image. */ + hdr->image_blocks += 2; + + /* Pointer past the dictionary. */ + hdr->first_boot_tag_block = + hdr->key_dictionary_block + kd_size / SB_BLOCK_SIZE; + + /* Compute header digest. */ + EVP_MD_CTX_init(&md_ctx); + + EVP_DigestInit(&md_ctx, EVP_sha1()); + EVP_DigestUpdate(&md_ctx, hdr->signature1, + sizeof(struct sb_boot_image_header) - + sizeof(hdr->digest)); + EVP_DigestFinal(&md_ctx, hdr->digest, NULL); + + return 0; +} + +static int sb_fixup_sections_and_tags(struct sb_image_ctx *ictx) +{ + /* Fixup the placement of sections. */ + struct sb_boot_image_header *ihdr = &ictx->payload; + struct sb_section_ctx *sctx = ictx->sect_head; + struct sb_sections_header *shdr; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + uint32_t offset = ihdr->first_boot_tag_block; + + while (sctx) { + shdr = &sctx->payload; + + /* Fill in the section TAG offset. */ + shdr->section_offset = offset + 1; + offset += shdr->section_size; + + /* Section length is measured from the TAG block. */ + shdr->section_size--; + + /* Fixup the TAG command. */ + cctx = sctx->cmd_head; + while (cctx) { + ccmd = &cctx->payload; + if (ccmd->header.tag == ROM_TAG_CMD) { + ccmd->tag.section_number = shdr->section_number; + ccmd->tag.section_length = shdr->section_size; + ccmd->tag.section_flags = shdr->section_flags; + } + + /* Update the command checksum. */ + ccmd->header.checksum = sb_command_checksum(ccmd); + + cctx = cctx->cmd; + } + + sctx = sctx->sect; + } + + return 0; +} + +static int sb_parse_line(struct sb_image_ctx *ictx, struct sb_cmd_list *cmd) +{ + char *tok; + char *line = cmd->cmd; + char *rptr; + int ret; + + /* Analyze the identifier on this line first. */ + tok = strtok_r(line, " ", &rptr); + if (!tok || (strlen(tok) == 0)) { + fprintf(stderr, "#%i ERR: Invalid line!\n", cmd->lineno); + return -EINVAL; + } + + cmd->cmd = rptr; + + /* DCD */ + if (!strcmp(tok, "DCD")) { + ictx->in_section = 0; + ictx->in_dcd = 1; + sb_build_dcd(ictx, cmd); + return 0; + } + + /* Section */ + if (!strcmp(tok, "SECTION")) { + ictx->in_section = 1; + ictx->in_dcd = 0; + sb_build_section(ictx, cmd); + return 0; + } + + if (!ictx->in_section && !ictx->in_dcd) { + fprintf(stderr, "#%i ERR: Data outside of a section!\n", + cmd->lineno); + return -EINVAL; + } + + if (ictx->in_section) { + /* Section commands */ + if (!strcmp(tok, "NOP")) { + ret = sb_build_command_nop(ictx); + } else if (!strcmp(tok, "TAG")) { + ret = sb_build_command_tag(ictx, cmd); + } else if (!strcmp(tok, "LOAD")) { + ret = sb_build_command_load(ictx, cmd); + } else if (!strcmp(tok, "FILL")) { + ret = sb_build_command_fill(ictx, cmd); + } else if (!strcmp(tok, "JUMP")) { + ret = sb_build_command_jump(ictx, cmd); + } else if (!strcmp(tok, "CALL")) { + ret = sb_build_command_call(ictx, cmd); + } else if (!strcmp(tok, "MODE")) { + ret = sb_build_command_mode(ictx, cmd); + } else { + fprintf(stderr, + "#%i ERR: Unsupported instruction '%s'!\n", + cmd->lineno, tok); + return -ENOTSUP; + } + } else if (ictx->in_dcd) { + char *lptr; + uint32_t ilen = '1'; + + tok = strtok_r(tok, ".", &lptr); + if (!tok || (strlen(tok) == 0) || (lptr && strlen(lptr) != 1)) { + fprintf(stderr, "#%i ERR: Invalid line!\n", + cmd->lineno); + return -EINVAL; + } + + if (lptr && + (lptr[0] != '1' && lptr[0] != '2' && lptr[0] != '4')) { + fprintf(stderr, "#%i ERR: Invalid instruction width!\n", + cmd->lineno); + return -EINVAL; + } + + if (lptr) + ilen = lptr[0] - '1'; + + /* DCD commands */ + if (!strcmp(tok, "WRITE")) { + ret = sb_build_dcd_block(ictx, cmd, + SB_DCD_WRITE | ilen); + } else if (!strcmp(tok, "ANDC")) { + ret = sb_build_dcd_block(ictx, cmd, + SB_DCD_ANDC | ilen); + } else if (!strcmp(tok, "ORR")) { + ret = sb_build_dcd_block(ictx, cmd, + SB_DCD_ORR | ilen); + } else if (!strcmp(tok, "EQZ")) { + ret = sb_build_dcd_block(ictx, cmd, + SB_DCD_CHK_EQZ | ilen); + } else if (!strcmp(tok, "EQ")) { + ret = sb_build_dcd_block(ictx, cmd, + SB_DCD_CHK_EQ | ilen); + } else if (!strcmp(tok, "NEQ")) { + ret = sb_build_dcd_block(ictx, cmd, + SB_DCD_CHK_NEQ | ilen); + } else if (!strcmp(tok, "NEZ")) { + ret = sb_build_dcd_block(ictx, cmd, + SB_DCD_CHK_NEZ | ilen); + } else if (!strcmp(tok, "NOOP")) { + ret = sb_build_dcd_block(ictx, cmd, SB_DCD_NOOP); + } else { + fprintf(stderr, + "#%i ERR: Unsupported instruction '%s'!\n", + cmd->lineno, tok); + return -ENOTSUP; + } + } else { + fprintf(stderr, "#%i ERR: Unsupported instruction '%s'!\n", + cmd->lineno, tok); + return -ENOTSUP; + } + + /* + * Here we have at least one section with one command, otherwise we + * would have failed already higher above. + * + * FIXME -- should the updating happen here ? + */ + if (ictx->in_section && !ret) { + ictx->sect_tail->size += ictx->sect_tail->cmd_tail->size; + ictx->sect_tail->payload.section_size = + ictx->sect_tail->size / SB_BLOCK_SIZE; + } + + return ret; +} + +static int sb_load_cmdfile(struct sb_image_ctx *ictx) +{ + struct sb_cmd_list cmd; + int lineno = 1; + FILE *fp; + char *line = NULL; + ssize_t rlen; + size_t len; + + fp = fopen(ictx->cfg_filename, "r"); + if (!fp) + goto err_file; + + while ((rlen = getline(&line, &len, fp)) > 0) { + memset(&cmd, 0, sizeof(cmd)); + + /* Strip the trailing newline. */ + line[rlen - 1] = '\0'; + + cmd.cmd = line; + cmd.len = rlen; + cmd.lineno = lineno++; + + sb_parse_line(ictx, &cmd); + } + + free(line); + + fclose(fp); + + return 0; + +err_file: + fclose(fp); + fprintf(stderr, "ERR: Failed to load file \"%s\"\n", + ictx->cfg_filename); + return -EINVAL; +} + +static int sb_build_tree_from_cfg(struct sb_image_ctx *ictx) +{ + int ret; + + ret = sb_load_cmdfile(ictx); + if (ret) + return ret; + + ret = sb_prefill_image_header(ictx); + if (ret) + return ret; + + ret = sb_postfill_image_header(ictx); + if (ret) + return ret; + + ret = sb_fixup_sections_and_tags(ictx); + if (ret) + return ret; + + return 0; +} + +static int sb_verify_image_header(struct sb_image_ctx *ictx, + FILE *fp, long fsize) +{ + /* Verify static fields in the image header. */ + struct sb_boot_image_header *hdr = &ictx->payload; + const char *stat[2] = { "[PASS]", "[FAIL]" }; + struct tm tm; + int sz, ret = 0; + unsigned char digest[20]; + EVP_MD_CTX md_ctx; + unsigned long size; + + /* Start image-wide crypto. */ + EVP_MD_CTX_init(&ictx->md_ctx); + EVP_DigestInit(&ictx->md_ctx, EVP_sha1()); + + soprintf(ictx, "---------- Verifying SB Image Header ----------\n"); + + size = fread(&ictx->payload, 1, sizeof(ictx->payload), fp); + if (size != sizeof(ictx->payload)) { + fprintf(stderr, "ERR: SB image header too short!\n"); + return -EINVAL; + } + + /* Compute header digest. */ + EVP_MD_CTX_init(&md_ctx); + EVP_DigestInit(&md_ctx, EVP_sha1()); + EVP_DigestUpdate(&md_ctx, hdr->signature1, + sizeof(struct sb_boot_image_header) - + sizeof(hdr->digest)); + EVP_DigestFinal(&md_ctx, digest, NULL); + + sb_aes_init(ictx, NULL, 1); + sb_encrypt_sb_header(ictx); + + if (memcmp(digest, hdr->digest, 20)) + ret = -EINVAL; + soprintf(ictx, "%s Image header checksum: %s\n", stat[!!ret], + ret ? "BAD" : "OK"); + if (ret) + return ret; + + if (memcmp(hdr->signature1, "STMP", 4) || + memcmp(hdr->signature2, "sgtl", 4)) + ret = -EINVAL; + soprintf(ictx, "%s Signatures: '%.4s' '%.4s'\n", + stat[!!ret], hdr->signature1, hdr->signature2); + if (ret) + return ret; + + if ((hdr->major_version != SB_VERSION_MAJOR) || + ((hdr->minor_version != 1) && (hdr->minor_version != 2))) + ret = -EINVAL; + soprintf(ictx, "%s Image version: v%i.%i\n", stat[!!ret], + hdr->major_version, hdr->minor_version); + if (ret) + return ret; + + ret = sb_get_time(hdr->timestamp_us / 1000000, &tm); + soprintf(ictx, + "%s Creation time: %02i:%02i:%02i %02i/%02i/%04i\n", + stat[!!ret], tm.tm_hour, tm.tm_min, tm.tm_sec, + tm.tm_mday, tm.tm_mon, tm.tm_year + 2000); + if (ret) + return ret; + + soprintf(ictx, "%s Product version: %x.%x.%x\n", stat[0], + ntohs(hdr->product_version.major), + ntohs(hdr->product_version.minor), + ntohs(hdr->product_version.revision)); + soprintf(ictx, "%s Component version: %x.%x.%x\n", stat[0], + ntohs(hdr->component_version.major), + ntohs(hdr->component_version.minor), + ntohs(hdr->component_version.revision)); + + if (hdr->flags & ~SB_IMAGE_FLAG_VERBOSE) + ret = -EINVAL; + soprintf(ictx, "%s Image flags: %s\n", stat[!!ret], + hdr->flags & SB_IMAGE_FLAG_VERBOSE ? "Verbose_boot" : ""); + if (ret) + return ret; + + if (hdr->drive_tag != 0) + ret = -EINVAL; + soprintf(ictx, "%s Drive tag: %i\n", stat[!!ret], + hdr->drive_tag); + if (ret) + return ret; + + sz = sizeof(struct sb_boot_image_header) / SB_BLOCK_SIZE; + if (hdr->header_blocks != sz) + ret = -EINVAL; + soprintf(ictx, "%s Image header size (blocks): %i\n", stat[!!ret], + hdr->header_blocks); + if (ret) + return ret; + + sz = sizeof(struct sb_sections_header) / SB_BLOCK_SIZE; + if (hdr->section_header_size != sz) + ret = -EINVAL; + soprintf(ictx, "%s Section header size (blocks): %i\n", stat[!!ret], + hdr->section_header_size); + if (ret) + return ret; + + soprintf(ictx, "%s Sections count: %i\n", stat[!!ret], + hdr->section_count); + soprintf(ictx, "%s First bootable section %i\n", stat[!!ret], + hdr->first_boot_section_id); + + if (hdr->image_blocks != fsize / SB_BLOCK_SIZE) + ret = -EINVAL; + soprintf(ictx, "%s Image size (blocks): %i\n", stat[!!ret], + hdr->image_blocks); + if (ret) + return ret; + + sz = hdr->header_blocks + hdr->section_header_size * hdr->section_count; + if (hdr->key_dictionary_block != sz) + ret = -EINVAL; + soprintf(ictx, "%s Key dict offset (blocks): %i\n", stat[!!ret], + hdr->key_dictionary_block); + if (ret) + return ret; + + if (hdr->key_count != 1) + ret = -EINVAL; + soprintf(ictx, "%s Number of encryption keys: %i\n", stat[!!ret], + hdr->key_count); + if (ret) + return ret; + + sz = hdr->header_blocks + hdr->section_header_size * hdr->section_count; + sz += hdr->key_count * + sizeof(struct sb_key_dictionary_key) / SB_BLOCK_SIZE; + if (hdr->first_boot_tag_block != (unsigned)sz) + ret = -EINVAL; + soprintf(ictx, "%s First TAG block (blocks): %i\n", stat[!!ret], + hdr->first_boot_tag_block); + if (ret) + return ret; + + return 0; +} + +static void sb_decrypt_tag(struct sb_image_ctx *ictx, + struct sb_cmd_ctx *cctx) +{ + EVP_MD_CTX *md_ctx = &ictx->md_ctx; + struct sb_command *cmd = &cctx->payload; + + sb_aes_crypt(ictx, (uint8_t *)&cctx->c_payload, + (uint8_t *)&cctx->payload, sizeof(*cmd)); + EVP_DigestUpdate(md_ctx, &cctx->c_payload, sizeof(*cmd)); +} + +static int sb_verify_command(struct sb_image_ctx *ictx, + struct sb_cmd_ctx *cctx, FILE *fp, + unsigned long *tsize) +{ + struct sb_command *ccmd = &cctx->payload; + unsigned long size, asize; + char *csum, *flag = ""; + int ret; + unsigned int i; + uint8_t csn, csc = ccmd->header.checksum; + ccmd->header.checksum = 0x5a; + csn = sb_command_checksum(ccmd); + ccmd->header.checksum = csc; + + if (csc == csn) + ret = 0; + else + ret = -EINVAL; + csum = ret ? "checksum BAD" : "checksum OK"; + + switch (ccmd->header.tag) { + case ROM_NOP_CMD: + soprintf(ictx, " NOOP # %s\n", csum); + return ret; + case ROM_TAG_CMD: + if (ccmd->header.flags & ROM_TAG_CMD_FLAG_ROM_LAST_TAG) + flag = "LAST"; + soprintf(ictx, " TAG %s # %s\n", flag, csum); + sb_aes_reinit(ictx, 0); + return ret; + case ROM_LOAD_CMD: + soprintf(ictx, " LOAD addr=0x%08x length=0x%08x # %s\n", + ccmd->load.address, ccmd->load.count, csum); + + cctx->length = ccmd->load.count; + asize = roundup(cctx->length, SB_BLOCK_SIZE); + cctx->data = malloc(asize); + if (!cctx->data) + return -ENOMEM; + + size = fread(cctx->data, 1, asize, fp); + if (size != asize) { + fprintf(stderr, + "ERR: SB LOAD command payload too short!\n"); + return -EINVAL; + } + + *tsize += size; + + EVP_DigestUpdate(&ictx->md_ctx, cctx->data, asize); + sb_aes_crypt(ictx, cctx->data, cctx->data, asize); + + if (ccmd->load.crc32 != crc32(cctx->data, asize)) { + fprintf(stderr, + "ERR: SB LOAD command payload CRC32 invalid!\n"); + return -EINVAL; + } + return 0; + case ROM_FILL_CMD: + soprintf(ictx, + " FILL addr=0x%08x length=0x%08x pattern=0x%08x # %s\n", + ccmd->fill.address, ccmd->fill.count, + ccmd->fill.pattern, csum); + return 0; + case ROM_JUMP_CMD: + if (ccmd->header.flags & ROM_JUMP_CMD_FLAG_HAB) + flag = " HAB"; + soprintf(ictx, + " JUMP%s addr=0x%08x r0_arg=0x%08x # %s\n", + flag, ccmd->fill.address, ccmd->jump.argument, csum); + return 0; + case ROM_CALL_CMD: + if (ccmd->header.flags & ROM_CALL_CMD_FLAG_HAB) + flag = " HAB"; + soprintf(ictx, + " CALL%s addr=0x%08x r0_arg=0x%08x # %s\n", + flag, ccmd->fill.address, ccmd->jump.argument, csum); + return 0; + case ROM_MODE_CMD: + for (i = 0; i < ARRAY_SIZE(modetable); i++) { + if (ccmd->mode.mode == modetable[i].mode) { + soprintf(ictx, " MODE %s # %s\n", + modetable[i].name, csum); + break; + } + } + fprintf(stderr, " MODE !INVALID! # %s\n", csum); + return 0; + } + + return ret; +} + +static int sb_verify_commands(struct sb_image_ctx *ictx, + struct sb_section_ctx *sctx, FILE *fp) +{ + unsigned long size, tsize = 0; + struct sb_cmd_ctx *cctx; + int ret; + + sb_aes_reinit(ictx, 0); + + while (tsize < sctx->size) { + cctx = calloc(1, sizeof(*cctx)); + if (!cctx) + return -ENOMEM; + if (!sctx->cmd_head) { + sctx->cmd_head = cctx; + sctx->cmd_tail = cctx; + } else { + sctx->cmd_tail->cmd = cctx; + sctx->cmd_tail = cctx; + } + + size = fread(&cctx->c_payload, 1, sizeof(cctx->c_payload), fp); + if (size != sizeof(cctx->c_payload)) { + fprintf(stderr, "ERR: SB command header too short!\n"); + return -EINVAL; + } + + tsize += size; + + sb_decrypt_tag(ictx, cctx); + + ret = sb_verify_command(ictx, cctx, fp, &tsize); + if (ret) + return -EINVAL; + } + + return 0; +} + +static int sb_verify_sections_cmds(struct sb_image_ctx *ictx, FILE *fp) +{ + struct sb_boot_image_header *hdr = &ictx->payload; + struct sb_sections_header *shdr; + unsigned int i; + int ret; + struct sb_section_ctx *sctx; + unsigned long size; + char *bootable = ""; + + soprintf(ictx, "----- Verifying SB Sections and Commands -----\n"); + + for (i = 0; i < hdr->section_count; i++) { + sctx = calloc(1, sizeof(*sctx)); + if (!sctx) + return -ENOMEM; + if (!ictx->sect_head) { + ictx->sect_head = sctx; + ictx->sect_tail = sctx; + } else { + ictx->sect_tail->sect = sctx; + ictx->sect_tail = sctx; + } + + size = fread(&sctx->payload, 1, sizeof(sctx->payload), fp); + if (size != sizeof(sctx->payload)) { + fprintf(stderr, "ERR: SB section header too short!\n"); + return -EINVAL; + } + } + + size = fread(&ictx->sb_dict_key, 1, sizeof(ictx->sb_dict_key), fp); + if (size != sizeof(ictx->sb_dict_key)) { + fprintf(stderr, "ERR: SB key dictionary too short!\n"); + return -EINVAL; + } + + sb_encrypt_sb_sections_header(ictx); + sb_aes_reinit(ictx, 0); + sb_decrypt_key_dictionary_key(ictx); + + sb_aes_reinit(ictx, 0); + + sctx = ictx->sect_head; + while (sctx) { + shdr = &sctx->payload; + + if (shdr->section_flags & SB_SECTION_FLAG_BOOTABLE) { + sctx->boot = 1; + bootable = " BOOTABLE"; + } + + sctx->size = (shdr->section_size * SB_BLOCK_SIZE) + + sizeof(struct sb_command); + soprintf(ictx, "SECTION 0x%x%s # size = %i bytes\n", + shdr->section_number, bootable, sctx->size); + + if (shdr->section_flags & ~SB_SECTION_FLAG_BOOTABLE) + fprintf(stderr, " WARN: Unknown section flag(s) %08x\n", + shdr->section_flags); + + if ((shdr->section_flags & SB_SECTION_FLAG_BOOTABLE) && + (hdr->first_boot_section_id != shdr->section_number)) { + fprintf(stderr, + " WARN: Bootable section does ID not match image header ID!\n"); + } + + ret = sb_verify_commands(ictx, sctx, fp); + if (ret) + return ret; + + sctx = sctx->sect; + } + + /* + * FIXME IDEA: + * check if the first TAG command is at sctx->section_offset + */ + return 0; +} + +static int sb_verify_image_end(struct sb_image_ctx *ictx, + FILE *fp, off_t filesz) +{ + uint8_t digest[32]; + unsigned long size; + off_t pos; + int ret; + + soprintf(ictx, "------------- Verifying image end -------------\n"); + + size = fread(digest, 1, sizeof(digest), fp); + if (size != sizeof(digest)) { + fprintf(stderr, "ERR: SB key dictionary too short!\n"); + return -EINVAL; + } + + pos = ftell(fp); + if (pos != filesz) { + fprintf(stderr, "ERR: Trailing data past the image!\n"); + return -EINVAL; + } + + /* Check the image digest. */ + EVP_DigestFinal(&ictx->md_ctx, ictx->digest, NULL); + + /* Decrypt the image digest from the input image. */ + sb_aes_reinit(ictx, 0); + sb_aes_crypt(ictx, digest, digest, sizeof(digest)); + + /* Check all of 20 bytes of the SHA1 hash. */ + ret = memcmp(digest, ictx->digest, 20) ? -EINVAL : 0; + + if (ret) + soprintf(ictx, "[FAIL] Full-image checksum: BAD\n"); + else + soprintf(ictx, "[PASS] Full-image checksum: OK\n"); + + return ret; +} + + +static int sb_build_tree_from_img(struct sb_image_ctx *ictx) +{ + long filesize; + int ret; + FILE *fp; + + if (!ictx->input_filename) { + fprintf(stderr, "ERR: Missing filename!\n"); + return -EINVAL; + } + + fp = fopen(ictx->input_filename, "r"); + if (!fp) + goto err_open; + + ret = fseek(fp, 0, SEEK_END); + if (ret < 0) + goto err_file; + + filesize = ftell(fp); + if (filesize < 0) + goto err_file; + + ret = fseek(fp, 0, SEEK_SET); + if (ret < 0) + goto err_file; + + if (filesize < (signed)sizeof(ictx->payload)) { + fprintf(stderr, "ERR: File too short!\n"); + goto err_file; + } + + if (filesize & (SB_BLOCK_SIZE - 1)) { + fprintf(stderr, "ERR: The file is not aligned!\n"); + goto err_file; + } + + /* Load and verify image header */ + ret = sb_verify_image_header(ictx, fp, filesize); + if (ret) + goto err_verify; + + /* Load and verify sections and commands */ + ret = sb_verify_sections_cmds(ictx, fp); + if (ret) + goto err_verify; + + ret = sb_verify_image_end(ictx, fp, filesize); + if (ret) + goto err_verify; + + ret = 0; + +err_verify: + soprintf(ictx, "-------------------- Result -------------------\n"); + soprintf(ictx, "Verification %s\n", ret ? "FAILED" : "PASSED"); + + /* Stop the encryption session. */ + sb_aes_deinit(&ictx->cipher_ctx); + + fclose(fp); + return ret; + +err_file: + fclose(fp); +err_open: + fprintf(stderr, "ERR: Failed to load file \"%s\"\n", + ictx->input_filename); + return -EINVAL; +} + +static void sb_free_image(struct sb_image_ctx *ictx) +{ + struct sb_section_ctx *sctx = ictx->sect_head, *s_head; + struct sb_dcd_ctx *dctx = ictx->dcd_head, *d_head; + struct sb_cmd_ctx *cctx, *c_head; + + while (sctx) { + s_head = sctx; + c_head = sctx->cmd_head; + + while (c_head) { + cctx = c_head; + c_head = c_head->cmd; + if (cctx->data) + free(cctx->data); + free(cctx); + } + + sctx = sctx->sect; + free(s_head); + } + + while (dctx) { + d_head = dctx; + dctx = dctx->dcd; + free(d_head->payload); + free(d_head); + } +} + +/* + * MXSSB-MKIMAGE glue code. + */ +static int mxsimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_MXSIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +static void mxsimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ +} + +int mxsimage_check_params(struct mkimage_params *params) +{ + if (!params) + return -1; + if (!strlen(params->imagename)) { + fprintf(stderr, + "Error: %s - Configuration file not specified, it is needed for mxsimage generation\n", + params->cmdname); + return -1; + } + + /* + * Check parameters: + * XIP is not allowed and verify that incompatible + * parameters are not sent at the same time + * For example, if list is required a data image must not be provided + */ + return (params->dflag && (params->fflag || params->lflag)) || + (params->fflag && (params->dflag || params->lflag)) || + (params->lflag && (params->dflag || params->fflag)) || + (params->xflag) || !(strlen(params->imagename)); +} + +static int mxsimage_verify_print_header(char *file, int silent) +{ + int ret; + struct sb_image_ctx ctx; + + memset(&ctx, 0, sizeof(ctx)); + + ctx.input_filename = file; + ctx.silent_dump = silent; + + ret = sb_build_tree_from_img(&ctx); + sb_free_image(&ctx); + + return ret; +} + +char *imagefile; +static int mxsimage_verify_header(unsigned char *ptr, int image_size, + struct mkimage_params *params) +{ + struct sb_boot_image_header *hdr; + + if (!ptr) + return -EINVAL; + + hdr = (struct sb_boot_image_header *)ptr; + + /* + * Check if the header contains the MXS image signatures, + * if so, do a full-image verification. + */ + if (memcmp(hdr->signature1, "STMP", 4) || + memcmp(hdr->signature2, "sgtl", 4)) + return -EINVAL; + + imagefile = params->imagefile; + + return mxsimage_verify_print_header(params->imagefile, 1); +} + +static void mxsimage_print_header(const void *hdr) +{ + if (imagefile) + mxsimage_verify_print_header(imagefile, 0); +} + +static int sb_build_image(struct sb_image_ctx *ictx, + struct image_type_params *tparams) +{ + struct sb_boot_image_header *sb_header = &ictx->payload; + struct sb_section_ctx *sctx; + struct sb_cmd_ctx *cctx; + struct sb_command *ccmd; + struct sb_key_dictionary_key *sb_dict_key = &ictx->sb_dict_key; + + uint8_t *image, *iptr; + + /* Calculate image size. */ + uint32_t size = sizeof(*sb_header) + + ictx->sect_count * sizeof(struct sb_sections_header) + + sizeof(*sb_dict_key) + sizeof(ictx->digest); + + sctx = ictx->sect_head; + while (sctx) { + size += sctx->size; + sctx = sctx->sect; + }; + + image = malloc(size); + if (!image) + return -ENOMEM; + iptr = image; + + memcpy(iptr, sb_header, sizeof(*sb_header)); + iptr += sizeof(*sb_header); + + sctx = ictx->sect_head; + while (sctx) { + memcpy(iptr, &sctx->payload, sizeof(struct sb_sections_header)); + iptr += sizeof(struct sb_sections_header); + sctx = sctx->sect; + }; + + memcpy(iptr, sb_dict_key, sizeof(*sb_dict_key)); + iptr += sizeof(*sb_dict_key); + + sctx = ictx->sect_head; + while (sctx) { + cctx = sctx->cmd_head; + while (cctx) { + ccmd = &cctx->payload; + + memcpy(iptr, &cctx->c_payload, sizeof(cctx->payload)); + iptr += sizeof(cctx->payload); + + if (ccmd->header.tag == ROM_LOAD_CMD) { + memcpy(iptr, cctx->data, cctx->length); + iptr += cctx->length; + } + + cctx = cctx->cmd; + } + + sctx = sctx->sect; + }; + + memcpy(iptr, ictx->digest, sizeof(ictx->digest)); + iptr += sizeof(ictx->digest); + + /* Configure the mkimage */ + tparams->hdr = image; + tparams->header_size = size; + + return 0; +} + +static int mxsimage_generate(struct mkimage_params *params, + struct image_type_params *tparams) +{ + int ret; + struct sb_image_ctx ctx; + + /* Do not copy the U-Boot image! */ + params->skipcpy = 1; + + memset(&ctx, 0, sizeof(ctx)); + + ctx.cfg_filename = params->imagename; + ctx.output_filename = params->imagefile; + ctx.verbose_boot = 1; + + ret = sb_build_tree_from_cfg(&ctx); + if (ret) + goto fail; + + ret = sb_encrypt_image(&ctx); + if (!ret) + ret = sb_build_image(&ctx, tparams); + +fail: + sb_free_image(&ctx); + + return ret; +} + +/* + * mxsimage parameters + */ +static struct image_type_params mxsimage_params = { + .name = "Freescale MXS Boot Image support", + .header_size = 0, + .hdr = NULL, + .check_image_type = mxsimage_check_image_types, + .verify_header = mxsimage_verify_header, + .print_header = mxsimage_print_header, + .set_header = mxsimage_set_header, + .check_params = mxsimage_check_params, + .vrec_header = mxsimage_generate, +}; + +void init_mxs_image_type(void) +{ + mkimage_register(&mxsimage_params); +} + +#else +void init_mxs_image_type(void) +{ +} +#endif diff --git a/tools/mxsimage.h b/tools/mxsimage.h new file mode 100644 index 00000000000..6cd59d2dbbe --- /dev/null +++ b/tools/mxsimage.h @@ -0,0 +1,230 @@ +/* + * Freescale i.MX28 SB image generator + * + * Copyright (C) 2012 Marek Vasut + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MXSSB_H__ +#define __MXSSB_H__ + +#include +#include + +#define SB_BLOCK_SIZE 16 + +#define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +struct sb_boot_image_version { + uint16_t major; + uint16_t pad0; + uint16_t minor; + uint16_t pad1; + uint16_t revision; + uint16_t pad2; +}; + +struct sb_boot_image_header { + union { + /* SHA1 of the header. */ + uint8_t digest[20]; + struct { + /* CBC-MAC initialization vector. */ + uint8_t iv[16]; + uint8_t extra[4]; + }; + }; + /* 'STMP' */ + uint8_t signature1[4]; + /* Major version of the image format. */ + uint8_t major_version; + /* Minor version of the image format. */ + uint8_t minor_version; + /* Flags associated with the image. */ + uint16_t flags; + /* Size of the image in 16b blocks. */ + uint32_t image_blocks; + /* Offset of the first tag in 16b blocks. */ + uint32_t first_boot_tag_block; + /* ID of the section to boot from. */ + uint32_t first_boot_section_id; + /* Amount of crypto keys. */ + uint16_t key_count; + /* Offset to the key dictionary in 16b blocks. */ + uint16_t key_dictionary_block; + /* Size of this header in 16b blocks. */ + uint16_t header_blocks; + /* Amount of section headers. */ + uint16_t section_count; + /* Section header size in 16b blocks. */ + uint16_t section_header_size; + /* Padding to align timestamp to uint64_t. */ + uint8_t padding0[2]; + /* 'sgtl' (since v1.1) */ + uint8_t signature2[4]; + /* Image generation date, in microseconds since 1.1.2000 . */ + uint64_t timestamp_us; + /* Product version. */ + struct sb_boot_image_version + product_version; + /* Component version. */ + struct sb_boot_image_version + component_version; + /* Drive tag for the system drive. (since v1.1) */ + uint16_t drive_tag; + /* Padding. */ + uint8_t padding1[6]; +}; + +#define SB_VERSION_MAJOR 1 +#define SB_VERSION_MINOR 1 + +/* Enable to HTLLC verbose boot report. */ +#define SB_IMAGE_FLAG_VERBOSE (1 << 0) + +struct sb_key_dictionary_key { + /* The CBC-MAC of image and sections header. */ + uint8_t cbc_mac[SB_BLOCK_SIZE]; + /* The AES key encrypted by image key (zero). */ + uint8_t key[SB_BLOCK_SIZE]; +}; + +struct sb_ivt_header { + uint32_t header; + uint32_t entry; + uint32_t reserved1; + uint32_t dcd; + uint32_t boot_data; + uint32_t self; + uint32_t csf; + uint32_t reserved2; +}; + +#define SB_HAB_IVT_TAG 0xd1UL +#define SB_HAB_DCD_TAG 0xd2UL + +#define SB_HAB_VERSION 0x40UL + +/* + * The "size" field in the IVT header is not naturally aligned, + * use this macro to fill first 4 bytes of the IVT header without + * causing issues on some systems (esp. M68k, PPC, MIPS-BE, ARM-BE). + */ +static inline uint32_t sb_hab_ivt_header(void) +{ + uint32_t ret = 0; + ret |= SB_HAB_IVT_TAG << 24; + ret |= sizeof(struct sb_ivt_header) << 16; + ret |= SB_HAB_VERSION; + return htonl(ret); +} + +struct sb_sections_header { + /* Section number. */ + uint32_t section_number; + /* Offset of this sections first instruction after "TAG". */ + uint32_t section_offset; + /* Size of the section in 16b blocks. */ + uint32_t section_size; + /* Section flags. */ + uint32_t section_flags; +}; + +#define SB_SECTION_FLAG_BOOTABLE (1 << 0) + +struct sb_command { + struct { + uint8_t checksum; + uint8_t tag; + uint16_t flags; +#define ROM_TAG_CMD_FLAG_ROM_LAST_TAG 0x1 +#define ROM_LOAD_CMD_FLAG_DCD_LOAD 0x1 /* MX28 only */ +#define ROM_JUMP_CMD_FLAG_HAB 0x1 /* MX28 only */ +#define ROM_CALL_CMD_FLAG_HAB 0x1 /* MX28 only */ + } header; + + union { + struct { + uint32_t reserved[3]; + } nop; + struct { + uint32_t section_number; + uint32_t section_length; + uint32_t section_flags; + } tag; + struct { + uint32_t address; + uint32_t count; + uint32_t crc32; + } load; + struct { + uint32_t address; + uint32_t count; + uint32_t pattern; + } fill; + struct { + uint32_t address; + uint32_t reserved; + /* Passed in register r0 before JUMP */ + uint32_t argument; + } jump; + struct { + uint32_t address; + uint32_t reserved; + /* Passed in register r0 before CALL */ + uint32_t argument; + } call; + struct { + uint32_t reserved1; + uint32_t reserved2; + uint32_t mode; + } mode; + + }; +}; + +/* + * Most of the mode names are same or at least similar + * on i.MX23 and i.MX28, but some of the mode names + * differ. The "name" field represents the mode name + * on i.MX28 as seen in Table 12-2 of the datasheet. + * The "altname" field represents the differently named + * fields on i.MX23 as seen in Table 35-3 of the + * datasheet. + */ +static const struct { + const char *name; + const char *altname; + const uint8_t mode; +} modetable[] = { + { "USB", NULL, 0x00 }, + { "I2C", NULL, 0x01 }, + { "SPI2_FLASH", "SPI1_FLASH", 0x02 }, + { "SPI3_FLASH", "SPI2_FLASH", 0x03 }, + { "NAND_BCH", NULL, 0x04 }, + { "JTAG", NULL, 0x06 }, + { "SPI3_EEPROM", "SPI2_EEPROM", 0x08 }, + { "SD_SSP0", NULL, 0x09 }, + { "SD_SSP1", NULL, 0x0A } +}; + +enum sb_tag { + ROM_NOP_CMD = 0x00, + ROM_TAG_CMD = 0x01, + ROM_LOAD_CMD = 0x02, + ROM_FILL_CMD = 0x03, + ROM_JUMP_CMD = 0x04, + ROM_CALL_CMD = 0x05, + ROM_MODE_CMD = 0x06 +}; + +struct sb_source_entry { + uint8_t tag; + uint32_t address; + uint32_t flags; + char *filename; +}; + +#endif /* __MXSSB_H__ */ -- cgit v1.3.1 From 27871e6b519ccd933bd91c879241995c272fef3b Mon Sep 17 00:00:00 2001 From: Bo Shen Date: Wed, 28 Aug 2013 14:36:56 +0000 Subject: ARM: atmel: sama5d3: drop unused CONFIG_NET_MULTI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop unused CONFIG_NET_MULTI Signed-off-by: Bo Shen Signed-off-by: Andreas Bießmann --- include/configs/sama5d3xek.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index 409919898eb..76fa500eddb 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -130,7 +130,6 @@ /* Ethernet Hardware */ #define CONFIG_MACB #define CONFIG_RMII -#define CONFIG_NET_MULTI #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_MACB_SEARCH_PHY #define CONFIG_RGMII -- cgit v1.3.1 From 31ad864e47f03288bf1d4232913b38ddb624345c Mon Sep 17 00:00:00 2001 From: Chin Liang See Date: Wed, 7 Aug 2013 10:06:56 -0500 Subject: socfpga: Adding configuration for development kit Separating the configuration file for Virtual Target and real hardware Cyclone V development kit Signed-off-by: Chin Liang See Reviewed-by: Pavel Machek Cc: Wolfgang Denk Cc: Pavel Machek Cc: Dinh Nguyen Cc: Tom Rini Cc: Albert Aribaud --- include/configs/socfpga_cyclone5.h | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h index b5a7a9addcf..06aeba61dd2 100644 --- a/include/configs/socfpga_cyclone5.h +++ b/include/configs/socfpga_cyclone5.h @@ -11,6 +11,8 @@ /* * High level configuration */ +/* Virtual target or real hardware */ +#define CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_ARMV7 #define CONFIG_L2_OFF @@ -21,11 +23,12 @@ #define CONFIG_SINGLE_BOOTLOADER #define CONFIG_SOCFPGA +/* base address for .text section */ +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TEXT_BASE 0x08000040 -#define V_NS16550_CLK 1000000 -#define CONFIG_BAUDRATE 57600 -#define CONFIG_SYS_HZ 1000 -#define CONFIG_TIMER_CLOCK_KHZ 2400 +#else +#define CONFIG_SYS_TEXT_BASE 0x01000040 +#endif #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* Console I/O Buffer Size */ @@ -154,7 +157,7 @@ /* SDRAM Bank #1 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* SDRAM memory size */ -#define PHYS_SDRAM_1_SIZE 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x40000000 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_START 0x00000000 @@ -170,8 +173,13 @@ #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_COM1 UART0_BASE - #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define V_NS16550_CLK 1000000 +#else +#define V_NS16550_CLK 100000000 +#endif +#define CONFIG_BAUDRATE 115200 /* * FLASH @@ -184,9 +192,15 @@ /* This timer use eosc1 where the clock frequency is fixed * throughout any condition */ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS - /* reload value when timer count to zero */ #define TIMER_LOAD_VAL 0xFFFFFFFF +/* Timer info */ +#define CONFIG_SYS_HZ 1000 +#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET +#define CONFIG_TIMER_CLOCK_KHZ 2400 +#else +#define CONFIG_TIMER_CLOCK_KHZ 25000 +#endif #define CONFIG_ENV_IS_NOWHERE -- cgit v1.3.1