From 34287efdaf6ed186a64445f65227b5407a1dcd63 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Mon, 29 Nov 2021 13:09:44 +0530 Subject: efi_loader: Add check for event log passed from firmware Platforms may have support to measure their initial firmware components and pass the event log to u-boot. The event log address can be passed in property tpm_event_log_addr and tpm_event_log_size of the tpm node. Platforms may choose their own specific mechanism to do so. A weak function is added to check if even log has been passed to u-boot from earlier firmware components. If available, the eventlog is parsed to check for its correctness and further event logs are appended to the passed log. Signed-off-by: Ruchika Gupta Reviewed-by: Ilias Apalodimas Tested-by: Ilias Apalodimas --- include/efi_loader.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index d52e399841b..67c40ca57a7 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -988,4 +988,6 @@ efi_status_t efi_esrt_register(void); */ efi_status_t efi_esrt_populate(void); efi_status_t efi_load_capsule_drivers(void); + +efi_status_t platform_get_eventlog(struct udevice *dev, u64 *addr, u32 *sz); #endif /* _EFI_LOADER_H */ -- cgit v1.3.1 From 2957a1e22407a84a2cc7c4ea5a8136af1d0278d9 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Mon, 29 Nov 2021 13:09:45 +0530 Subject: tpm: use more algorithms than sha256 on pcr_read The current tpm2_pcr_read is hardcoded using SHA256. Make the actual command to TPM configurable to use wider range of algorithms. The current command line is kept as is i.e limited to SHA-256 only. Signed-off-by: Ruchika Gupta Reviewed-by: Ilias Apalodimas --- cmd/tpm-v2.c | 3 ++- include/tpm-v2.h | 5 ++++- lib/tpm-v2.c | 12 ++++++++---- 3 files changed, 14 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c index daae91100a2..4ea5f9f094f 100644 --- a/cmd/tpm-v2.c +++ b/cmd/tpm-v2.c @@ -151,7 +151,8 @@ static int do_tpm_pcr_read(struct cmd_tbl *cmdtp, int flag, int argc, data = map_sysmem(simple_strtoul(argv[2], NULL, 0), 0); - rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, data, &updates); + rc = tpm2_pcr_read(dev, index, priv->pcr_select_min, TPM2_ALG_SHA256, + data, TPM2_DIGEST_LEN, &updates); if (!rc) { printf("PCR #%u content (%u known updates):\n", index, updates); print_byte_string(data, TPM2_DIGEST_LEN); diff --git a/include/tpm-v2.h b/include/tpm-v2.h index ceff7d245ed..4e9dd52cb6c 100644 --- a/include/tpm-v2.h +++ b/include/tpm-v2.h @@ -512,13 +512,16 @@ u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data, * @dev TPM device * @idx Index of the PCR * @idx_min_sz Minimum size in bytes of the pcrSelect array + * @algorithm Algorithm used, defined in 'enum tpm2_algorithms' * @data Output buffer for contents of the named PCR + * @digest_len len of the data * @updates Optional out parameter: number of updates for this PCR * * @return code of the operation */ u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz, - void *data, unsigned int *updates); + u16 algorithm, void *data, u32 digest_len, + unsigned int *updates); /** * Issue a TPM2_GetCapability command. This implementation is limited diff --git a/lib/tpm-v2.c b/lib/tpm-v2.c index 2e7b27bd6bb..1bf627853af 100644 --- a/lib/tpm-v2.c +++ b/lib/tpm-v2.c @@ -254,7 +254,8 @@ u32 tpm2_nv_write_value(struct udevice *dev, u32 index, const void *data, } u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz, - void *data, unsigned int *updates) + u16 algorithm, void *data, u32 digest_len, + unsigned int *updates) { u8 idx_array_sz = max(idx_min_sz, DIV_ROUND_UP(idx, 8)); u8 command_v2[COMMAND_BUFFER_SIZE] = { @@ -264,7 +265,7 @@ u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz, /* TPML_PCR_SELECTION */ tpm_u32(1), /* Number of selections */ - tpm_u16(TPM2_ALG_SHA256), /* Algorithm of the hash */ + tpm_u16(algorithm), /* Algorithm of the hash */ idx_array_sz, /* Array size for selection */ /* bitmap(idx) Selected PCR bitmap */ }; @@ -283,10 +284,13 @@ u32 tpm2_pcr_read(struct udevice *dev, u32 idx, unsigned int idx_min_sz, if (ret) return ret; + if (digest_len > response_len) + return TPM_LIB_ERROR; + if (unpack_byte_string(response, response_len, "ds", 10, &counter, - response_len - TPM2_DIGEST_LEN, data, - TPM2_DIGEST_LEN)) + response_len - digest_len, data, + digest_len)) return TPM_LIB_ERROR; if (updates) -- cgit v1.3.1 From 874e544e89a7f9f42796b23f8d43c56e203b6e69 Mon Sep 17 00:00:00 2001 From: Mike Karels Date: Wed, 27 Oct 2021 22:26:15 +0000 Subject: Fix MMC numbering issue for Raspberry Pi 3 Using mmc.dtbo from rpi-firmware to switch the controller for the SD card slot from sdhci to sdhost causes the numbering to change; the SD card is then not recognized at boot. Add to the range checked. Signed-off-by: Matthias Brugger --- include/configs/rpi.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 55768a46da2..4c5c1ac31f9 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -137,7 +137,8 @@ #if CONFIG_IS_ENABLED(CMD_MMC) #define BOOT_TARGET_MMC(func) \ func(MMC, mmc, 0) \ - func(MMC, mmc, 1) + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) #else #define BOOT_TARGET_MMC(func) #endif -- cgit v1.3.1 From 666da85dc98931b82efa68b0c1a96fc654b7a40b Mon Sep 17 00:00:00 2001 From: Leo Yu-Chi Liang Date: Thu, 4 Nov 2021 09:53:26 +0800 Subject: board: ae350: Support autoboot from RAM Add boot command "bootcmd_ram" to support autoboot from RAM. This feature could be useful at the very initial state of chip design when there is only a minimal set of peripheral. (e.g. without mmc and mac ..etc) The kernel image is default to be loaded at 0x2000000 via debug port, and the following script serves as an example: spl() { cmd="riscv64-linux-gdb -q \ -ex \"target remote $host:$port\" \ -ex \"load\" \ -ex \"thread apply all set \\\$pc=&_start\" \ -ex \"thread apply all set \\\$a0=\\\$mhartid\" \ -ex \"thread apply all set \\\$a1=\" \ -ex \"restore u-boot.itb binary 0x200000\" \ -ex \"restore Image binary 0x2000000\" \ -ex \"c\" \ spl/u-boot-spl " echo $cmd eval $cmd } The address where the kernel is loaded can be altered by changing the value of KERNEL_IMAGE_ADDR. Signed-off-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen --- include/configs/ax25-ae350.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h index bf3f34e428f..1c3f957d324 100644 --- a/include/configs/ax25-ae350.h +++ b/include/configs/ax25-ae350.h @@ -119,12 +119,23 @@ /* Increase max gunzip size */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) +/* Support autoboot from RAM (kernel image is loaded via debug port) */ +#define KERNEL_IMAGE_ADDR "0x2000000 " +#define BOOTENV_DEV_NAME_RAM(devtypeu, devtypel, instance) \ + "ram " +#define BOOTENV_DEV_RAM(devtypeu, devtypel, instance) \ + "bootcmd_ram=" \ + "booti " \ + KERNEL_IMAGE_ADDR \ + "- $fdtcontroladdr\0" + /* When we use RAM as ENV */ /* Enable distro boot */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) + func(DHCP, dhcp, na) \ + func(RAM, ram, na) #include #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v1.3.1 From 06142d6874ca58b420c3a77633317daa31c1b88e Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Wed, 17 Nov 2021 18:21:17 +0530 Subject: riscv: dts: Split Microchip device tree The device tree split into .dtsi and .dts files, common device node for eMMC/SD, enable I2C1, UART1 for console instead of UART0, enable the DDR 2GB memory and in that 288MB memory is reserved for fabric buffer. Signed-off-by: Padmarao Begari Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 518 +++++-------------- arch/riscv/dts/microchip-mpfs.dtsi | 571 +++++++++++++++++++++ .../interrupt-controller/microchip-mpfs-plic.h | 196 +++++++ .../dt-bindings/interrupt-controller/riscv-hart.h | 17 + 4 files changed, 913 insertions(+), 389 deletions(-) create mode 100644 arch/riscv/dts/microchip-mpfs.dtsi create mode 100644 include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h (limited to 'include') diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts index 89c4cf5fb2b..287ef3d23b7 100644 --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts @@ -1,417 +1,157 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 Microchip Technology Inc */ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021 Microchip Technology Inc. + * Padmarao Begari + */ /dts-v1/; -#include "dt-bindings/clock/microchip-mpfs-clock.h" + +#include "microchip-mpfs.dtsi" /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 / { - #address-cells = <2>; - #size-cells = <2>; - model = "Microchip MPFS Icicle Kit"; - compatible = "microchip,mpfs-icicle-kit"; + model = "Microchip PolarFire-SoC Icicle Kit"; + compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; aliases { - serial0 = &uart0; - ethernet0 = &emac1; + serial1 = &uart1; + ethernet0 = &mac1; }; chosen { - stdout-path = "serial0"; + stdout-path = "serial1"; }; - cpucomplex: cpus { - #address-cells = <1>; - #size-cells = <0>; + cpus { timebase-frequency = ; - cpu0: cpu@0 { - clocks = <&clkcfg CLK_CPU>; - compatible = "sifive,e51", "sifive,rocket0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - reg = <0>; - riscv,isa = "rv64imac"; - status = "disabled"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; - cpu0intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu1: cpu@1 { - clocks = <&clkcfg CLK_CPU>; - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <1>; - riscv,isa = "rv64imafdc"; - tlb-split; - status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; - cpu1intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu2: cpu@2 { - clocks = <&clkcfg CLK_CPU>; - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <2>; - riscv,isa = "rv64imafdc"; - tlb-split; - status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; - cpu2intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; + }; + + reserved-memory { + ranges; + #size-cells = <2>; + #address-cells = <2>; + + fabricbuf0: fabricbuf@0 { + compatible = "shared-dma-pool"; + reg = <0x0 0xae000000 0x0 0x2000000>; + label = "fabricbuf0-ddr-c"; }; - cpu3: cpu@3 { - clocks = <&clkcfg CLK_CPU>; - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <3>; - riscv,isa = "rv64imafdc"; - tlb-split; - status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; - cpu3intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; + + fabricbuf1: fabricbuf@1 { + compatible = "shared-dma-pool"; + reg = <0x0 0xc0000000 0x0 0x8000000>; + label = "fabricbuf1-ddr-nc"; }; - cpu4: cpu@4 { - clocks = <&clkcfg CLK_CPU>; - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <4>; - riscv,isa = "rv64imafdc"; - tlb-split; - status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; - cpu4intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; + + fabricbuf2: fabricbuf@2 { + compatible = "shared-dma-pool"; + reg = <0x0 0xd8000000 0x0 0x8000000>; + label = "fabricbuf2-ddr-nc-wcb"; }; }; - refclk: refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <600000000>; - clock-output-names = "msspllclk"; + + udmabuf0 { + compatible = "ikwzm,u-dma-buf"; + device-name = "udmabuf-ddr-c0"; + minor-number = <0>; + size = <0x0 0x2000000>; + memory-region = <&fabricbuf0>; + sync-mode = <3>; + }; + + udmabuf1 { + compatible = "ikwzm,u-dma-buf"; + device-name = "udmabuf-ddr-nc0"; + minor-number = <1>; + size = <0x0 0x8000000>; + memory-region = <&fabricbuf1>; + sync-mode = <3>; + }; + + udmabuf2 { + compatible = "ikwzm,u-dma-buf"; + device-name = "udmabuf-ddr-nc-wcb0"; + minor-number = <2>; + size = <0x0 0x8000000>; + memory-region = <&fabricbuf2>; + sync-mode = <3>; }; - ddr: memory@80000000 { + + ddrc_cache_lo: memory@80000000 { device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; + reg = <0x0 0x80000000 0x0 0x2e000000>; clocks = <&clkcfg CLK_DDRC>; + status = "okay"; }; - soc: soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "microchip,mpfs-icicle-kit", "simple-bus"; - ranges; - clint0: clint@2000000 { - compatible = "riscv,clint0"; - interrupts-extended = <&cpu0intc 3 &cpu0intc 7 - &cpu1intc 3 &cpu1intc 7 - &cpu2intc 3 &cpu2intc 7 - &cpu3intc 3 &cpu3intc 7 - &cpu4intc 3 &cpu4intc 7>; - reg = <0x0 0x2000000 0x0 0x10000>; - reg-names = "control"; - clock-frequency = ; - }; - cachecontroller: cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <1024>; - cache-size = <2097152>; - cache-unified; - interrupt-parent = <&plic>; - interrupts = <1 2 3>; - reg = <0x0 0x2010000 0x0 0x1000>; - }; - plic: interrupt-controller@c000000 { - #interrupt-cells = <1>; - compatible = "sifive,plic-1.0.0"; - reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,max-priority = <7>; - riscv,ndev = <186>; - interrupt-controller; - interrupts-extended = < - &cpu0intc 11 - &cpu1intc 11 &cpu1intc 9 - &cpu2intc 11 &cpu2intc 9 - &cpu3intc 11 &cpu3intc 9 - &cpu4intc 11 &cpu4intc 9>; - }; - uart0: serial@20000000 { - compatible = "ns16550a"; - reg = <0x0 0x20000000 0x0 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupt-parent = <&plic>; - interrupts = <90>; - clocks = <&clkcfg CLK_MMUART0>; - status = "okay"; - }; - clkcfg: clkcfg@20002000 { - compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>; - reg-names = "mss_sysreg"; - clocks = <&refclk>; - #clock-cells = <1>; - clock-output-names = "cpu", "axi", "ahb", "envm", - "mac0", "mac1", "mmc", "timer", - "mmuart0", "mmuart1", "mmuart2", - "mmuart3", "mmuart4", "spi0", "spi1", - "i2c0", "i2c1", "can0", "can1", "usb", - "reserved", "rtc", "qspi", "gpio0", - "gpio1", "gpio2", "ddrc", "fic0", - "fic1", "fic2", "fic3", "athena", - "cfm"; - }; - emmc: mmc@20008000 { - compatible = "cdns,sd4hc"; - reg = <0x0 0x20008000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupts = <88 89>; - pinctrl-names = "default"; - clocks = <&clkcfg CLK_MMC>; - bus-width = <4>; - cap-mmc-highspeed; - mmc-ddr-3_3v; - max-frequency = <200000000>; - non-removable; - no-sd; - no-sdio; - voltage-ranges = <3300 3300>; - status = "okay"; - }; - sdcard: sd@20008000 { - compatible = "cdns,sd4hc"; - reg = <0x0 0x20008000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupts = <88>; - pinctrl-names = "default"; - clocks = <&clkcfg CLK_MMC>; - bus-width = <4>; - disable-wp; - cap-sd-highspeed; - card-detect-delay = <200>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - max-frequency = <200000000>; - status = "disabled"; - }; - uart1: serial@20100000 { - compatible = "ns16550a"; - reg = <0x0 0x20100000 0x0 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupt-parent = <&plic>; - interrupts = <91>; - clocks = <&clkcfg CLK_MMUART1>; - status = "okay"; - }; - uart2: serial@20102000 { - compatible = "ns16550a"; - reg = <0x0 0x20102000 0x0 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupt-parent = <&plic>; - interrupts = <92>; - clocks = <&clkcfg CLK_MMUART2>; - status = "okay"; - }; - uart3: serial@20104000 { - compatible = "ns16550a"; - reg = <0x0 0x20104000 0x0 0x400>; - reg-io-width = <4>; - reg-shift = <2>; - interrupt-parent = <&plic>; - interrupts = <93>; - clocks = <&clkcfg CLK_MMUART3>; - status = "okay"; - }; - i2c0: i2c@2010a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "microchip,mpfs-mss-i2c"; - reg = <0x0 0x2010a000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupts = <58>; - clocks = <&clkcfg CLK_I2C0>; - status = "disabled"; - }; - i2c1: i2c@2010b000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "microchip,mpfs-mss-i2c"; - reg = <0x0 0x2010b000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupts = <61>; - clocks = <&clkcfg CLK_I2C1>; - status = "disabled"; - pac193x@10 { - compatible = "microchip,pac1934"; - reg = <0x10>; - samp-rate = <64>; - status = "disabled"; - ch1: channel0 { - uohms-shunt-res = <10000>; - rail-name = "VDD"; - channel_enabled; - }; - ch2: channel1 { - uohms-shunt-res = <10000>; - rail-name = "VDDA25"; - channel_enabled; - }; - ch3: channel2 { - uohms-shunt-res = <10000>; - rail-name = "VDD25"; - channel_enabled; - }; - ch4: channel3 { - uohms-shunt-res = <10000>; - rail-name = "VDDA"; - channel_enabled; - }; - }; - }; - emac0: ethernet@20110000 { - compatible = "microchip,mpfs-mss-gem"; - reg = <0x0 0x20110000 0x0 0x2000>; - interrupt-parent = <&plic>; - interrupts = <64 65 66 67>; - local-mac-address = [56 34 00 FC 00 02]; - phy-mode = "sgmii"; - clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AXI>; - clock-names = "pclk", "hclk"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - phy-handle = <&phy0>; - phy0: ethernet-phy@8 { - reg = <8>; - ti,fifo-depth = <0x01>; - }; - }; - emac1: ethernet@20112000 { - compatible = "microchip,mpfs-mss-gem"; - reg = <0x0 0x20112000 0x0 0x2000>; - interrupt-parent = <&plic>; - interrupts = <70 71 72 73>; - local-mac-address = [00 00 00 00 00 00]; - phy-mode = "sgmii"; - clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; - status = "okay"; + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x0 0x0 0x40000000>; + clocks = <&clkcfg CLK_DDRC>; + status = "okay"; + }; +}; - #address-cells = <1>; - #size-cells = <0>; - phy-handle = <&phy1>; - phy1: ethernet-phy@9 { - reg = <9>; - ti,fifo-depth = <0x01>; - }; - }; - gpio: gpio@20122000 { - compatible = "microchip,mpfs-mss-gpio"; - interrupt-parent = <&plic>; - interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26 - 27 28 29 30 31 32 33 34 35 36 37 38 39 - 40 41 42 43 44>; - gpio-controller; - clocks = <&clkcfg CLK_GPIO2>; - reg = <0x00 0x20122000 0x0 0x1000>; - reg-names = "control"; - #gpio-cells = <2>; - status = "disabled"; +&uart1 { + status = "okay"; +}; + +&mmc { + status = "okay"; + + bus-width = <4>; + disable-wp; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; + + pac193x: pac193x@10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + samp-rate = <64>; + status = "okay"; + ch1: channel0 { + uohms-shunt-res = <10000>; + rail-name = "VDDREG"; + channel_enabled; + }; + ch2: channel1 { + uohms-shunt-res = <10000>; + rail-name = "VDDA25"; + channel_enabled; + }; + ch3: channel2 { + uohms-shunt-res = <10000>; + rail-name = "VDD25"; + channel_enabled; + }; + ch4: channel3 { + uohms-shunt-res = <10000>; + rail-name = "VDDA_REG"; + channel_enabled; }; }; }; + +&mac1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@9 { + reg = <9>; + ti,fifo-depth = <0x1>; + }; +}; diff --git a/arch/riscv/dts/microchip-mpfs.dtsi b/arch/riscv/dts/microchip-mpfs.dtsi new file mode 100644 index 00000000000..4f449a3a934 --- /dev/null +++ b/arch/riscv/dts/microchip-mpfs.dtsi @@ -0,0 +1,571 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +#include "dt-bindings/clock/microchip-mpfs-clock.h" +#include "dt-bindings/interrupt-controller/microchip-mpfs-plic.h" +#include "dt-bindings/interrupt-controller/riscv-hart.h" + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Microchip PolarFire SoC"; + compatible = "microchip,mpfs"; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + clocks = <&clkcfg CLK_CPU>; + status = "disabled"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu1: cpu@1 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu2: cpu@2 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu3: cpu@3 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu4: cpu@4 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + clocks = <&clkcfg CLK_CPU>; + tlb-split; + status = "okay"; + operating-points = < + /* kHz uV */ + 600000 1100000 + 300000 950000 + 150000 750000 + >; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "microchip,mpfs-soc", "simple-bus"; + ranges; + + clint: clint@2000000 { + compatible = "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0xC000>; + interrupts-extended = + <&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER + &cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER + &cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER + &cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER + &cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>; + }; + + cachecontroller: cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + reg = <0x0 0x2010000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = ; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + }; + + pdma: pdma@3000000 { + compatible = "microchip,mpfs-pdma-uio","sifive,fu540-c000-pdma"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic>; + interrupts = ; + #dma-cells = <1>; + }; + + plic: interrupt-controller@c000000 { + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + #interrupt-cells = <1>; + riscv,ndev = <186>; + interrupt-controller; + interrupts-extended = <&cpu0_intc HART_INT_M_EXT + &cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT + &cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT + &cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT + &cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>; + }; + + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + clock-output-names = "msspllclk"; + }; + + clkcfg: clkcfg@20002000 { + compatible = "microchip,mpfs-clkcfg"; + reg = <0x0 0x20002000 0x0 0x1000>; + reg-names = "mss_sysreg"; + clocks = <&refclk>; + #clock-cells = <1>; + clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ + "mac0", "mac1", "mmc", "timer", /* 4-7 */ + "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ + "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ + "i2c1", "can0", "can1", "usb", /* 16-19 */ + "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ + "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ + "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ + }; + + /* Common node entry for eMMC/SD */ + mmc: mmc@20008000 { + compatible = "microchip,mpfs-sd4hc","cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + clocks = <&clkcfg CLK_MMC>; + interrupt-parent = <&plic>; + interrupts = ; + max-frequency = <200000000>; + status = "disabled"; + }; + + uart0: serial@20000000 { + compatible = "ns16550a"; + reg = <0x0 0x20000000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = ; + clocks = <&clkcfg CLK_MMUART0>; + status = "disabled"; /* Reserved for the HSS */ + }; + + uart1: serial@20100000 { + compatible = "ns16550a"; + reg = <0x0 0x20100000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = ; + clocks = <&clkcfg CLK_MMUART1>; + status = "disabled"; + }; + + uart2: serial@20102000 { + compatible = "ns16550a"; + reg = <0x0 0x20102000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = ; + clocks = <&clkcfg CLK_MMUART2>; + status = "disabled"; + }; + + uart3: serial@20104000 { + compatible = "ns16550a"; + reg = <0x0 0x20104000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = ; + clocks = <&clkcfg CLK_MMUART3>; + status = "disabled"; + }; + + uart4: serial@20106000 { + compatible = "ns16550a"; + reg = <0x0 0x20106000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = ; + clocks = <&clkcfg CLK_MMUART4>; + status = "disabled"; + }; + + spi0: spi@20108000 { + compatible = "microchip,mpfs-spi"; + reg = <0x0 0x20108000 0x0 0x1000>; + clocks = <&clkcfg CLK_SPI0>; + interrupt-parent = <&plic>; + interrupts = ; + num-cs = <8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@20109000 { + compatible = "microchip,mpfs-spi"; + reg = <0x0 0x20109000 0x0 0x1000>; + clocks = <&clkcfg CLK_SPI1>; + interrupt-parent = <&plic>; + interrupts = ; + num-cs = <8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@2010a000 { + compatible = "microchip,mpfs-i2c"; + reg = <0x0 0x2010a000 0x0 0x1000>; + clocks = <&clkcfg CLK_I2C0>; + interrupt-parent = <&plic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@2010b000 { + compatible = "microchip,mpfs-i2c"; + reg = <0x0 0x2010b000 0x0 0x1000>; + clocks = <&clkcfg CLK_I2C1>; + interrupt-parent = <&plic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@2010c000 { + compatible = "microchip,mpfs-can-uio"; + reg = <0x0 0x2010c000 0x0 0x1000>; + clocks = <&clkcfg CLK_CAN0>; + interrupt-parent = <&plic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can1: can@2010d000 { + compatible = "microchip,mpfs-can-uio"; + reg = <0x0 0x2010d000 0x0 0x1000>; + clocks = <&clkcfg CLK_CAN1>; + interrupt-parent = <&plic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mac0: ethernet@20110000 { + compatible = "cdns,macb"; + reg = <0x0 0x20110000 0x0 0x2000>; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; + interrupt-parent = <&plic>; + interrupts = ; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mac1: ethernet@20112000 { + compatible = "cdns,macb"; + reg = <0x0 0x20112000 0x0 0x2000>; + clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; + interrupt-parent = <&plic>; + interrupts = ; + local-mac-address = [00 00 00 00 00 00]; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + gpio0: gpio@20120000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20120000 0x0 0x1000>; + reg-names = "control"; + clocks = <&clkcfg CLK_GPIO0>; + interrupt-parent = <&plic>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@20121000 { + compatible = "microchip,mpfs-gpio"; + reg = <000 0x20121000 0x0 0x1000>; + reg-names = "control"; + clocks = <&clkcfg CLK_GPIO1>; + interrupt-parent = <&plic>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + gpio2: gpio@20122000 { + compatible = "microchip,mpfs-gpio"; + reg = <0x0 0x20122000 0x0 0x1000>; + reg-names = "control"; + clocks = <&clkcfg CLK_GPIO2>; + interrupt-parent = <&plic>; + gpio-controller; + #gpio-cells = <2>; + status = "disabled"; + }; + + rtc: rtc@20124000 { + compatible = "microchip,mpfs-rtc"; + reg = <0x0 0x20124000 0x0 0x1000>; + clocks = <&clkcfg CLK_RTC>; + clock-names = "rtc"; + interrupt-parent = <&plic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usb: usb@20201000 { + compatible = "microchip,mpfs-usb-host"; + reg = <0x0 0x20201000 0x0 0x1000>; + reg-names = "mc","control"; + clocks = <&clkcfg CLK_USB>; + interrupt-parent = <&plic>; + interrupts = ; + interrupt-names = "dma","mc"; + dr_mode = "host"; + status = "disabled"; + }; + + qspi: qspi@21000000 { + compatible = "microchip,mpfs-qspi"; + reg = <0x0 0x21000000 0x0 0x1000>; + clocks = <&clkcfg CLK_QSPI>; + interrupt-parent = <&plic>; + interrupts = ; + num-cs = <8>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mbox: mailbox@37020000 { + compatible = "microchip,mpfs-mailbox"; + reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + interrupt-parent = <&plic>; + interrupts = ; + #mbox-cells = <1>; + status = "disabled"; + }; + + pcie: pcie@2000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>; + clock-names = "fic0", "fic1", "fic3"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = ; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent = <&pcie>; + msi-controller; + mchp,axi-m-atr0 = <0x10 0x0>; + status = "disabled"; + pcie_intc: legacy-interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + syscontroller: syscontroller { + compatible = "microchip,mpfs-sys-controller"; + #address-cells = <1>; + #size-cells = <1>; + mboxes = <&mbox 0>; + }; + + hwrandom: hwrandom { + compatible = "microchip,mpfs-rng"; + #address-cells = <1>; + #size-cells = <1>; + syscontroller = <&syscontroller>; + }; + + serialnum: serialnum { + compatible = "microchip,mpfs-serial-number"; + #address-cells = <1>; + #size-cells = <1>; + syscontroller = <&syscontroller>; + }; + + fpgadigest: fpgadigest { + compatible = "microchip,mpfs-digest"; + #address-cells = <1>; + #size-cells = <1>; + syscontroller = <&syscontroller>; + }; + + devicecert: cert { + compatible = "microchip,mpfs-device-cert"; + #address-cells = <1>; + #size-cells = <1>; + syscontroller = <&syscontroller>; + }; + + signature: signature { + compatible = "microchip,mpfs-signature"; + #address-cells = <1>; + #size-cells = <1>; + syscontroller = <&syscontroller>; + }; + }; +}; diff --git a/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h b/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h new file mode 100644 index 00000000000..eba1bac7dfb --- /dev/null +++ b/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H + +#define PLIC_INT_INVALID 0 +#define PLIC_INT_L2_METADATA_CORR 1 +#define PLIC_INT_L2_METADATA_UNCORR 2 +#define PLIC_INT_L2_DATA_CORR 3 +#define PLIC_INT_L2_DATA_UNCORR 4 +#define PLIC_INT_DMA_CH0_DONE 5 +#define PLIC_INT_DMA_CH0_ERR 6 +#define PLIC_INT_DMA_CH1_DONE 7 +#define PLIC_INT_DMA_CH1_ERR 8 +#define PLIC_INT_DMA_CH2_DONE 9 +#define PLIC_INT_DMA_CH2_ERR 10 +#define PLIC_INT_DMA_CH3_DONE 11 +#define PLIC_INT_DMA_CH3_ERR 12 + +#define PLIC_INT_GPIO0_BIT0_OR_GPIO2_BIT0 13 +#define PLIC_INT_GPIO0_BIT1_OR_GPIO2_BIT1 14 +#define PLIC_INT_GPIO0_BIT2_OR_GPIO2_BIT2 15 +#define PLIC_INT_GPIO0_BIT3_OR_GPIO2_BIT3 16 +#define PLIC_INT_GPIO0_BIT4_OR_GPIO2_BIT4 17 +#define PLIC_INT_GPIO0_BIT5_OR_GPIO2_BIT5 18 +#define PLIC_INT_GPIO0_BIT6_OR_GPIO2_BIT6 19 +#define PLIC_INT_GPIO0_BIT7_OR_GPIO2_BIT7 20 +#define PLIC_INT_GPIO0_BIT8_OR_GPIO2_BIT8 21 +#define PLIC_INT_GPIO0_BIT9_OR_GPIO2_BIT9 22 +#define PLIC_INT_GPIO0_BIT10_OR_GPIO2_BIT10 23 +#define PLIC_INT_GPIO0_BIT11_OR_GPIO2_BIT11 24 +#define PLIC_INT_GPIO0_BIT12_OR_GPIO2_BIT12 25 +#define PLIC_INT_GPIO0_BIT13_OR_GPIO2_BIT13 26 +#define PLIC_INT_GPIO1_BIT0_OR_GPIO2_BIT14 27 +#define PLIC_INT_GPIO1_BIT1_OR_GPIO2_BIT15 28 +#define PLIC_INT_GPIO1_BIT2_OR_GPIO2_BIT16 29 +#define PLIC_INT_GPIO1_BIT3_OR_GPIO2_BIT17 30 +#define PLIC_INT_GPIO1_BIT4_OR_GPIO2_BIT18 31 +#define PLIC_INT_GPIO1_BIT5_OR_GPIO2_BIT19 32 +#define PLIC_INT_GPIO1_BIT6_OR_GPIO2_BIT20 33 +#define PLIC_INT_GPIO1_BIT7_OR_GPIO2_BIT21 34 +#define PLIC_INT_GPIO1_BIT8_OR_GPIO2_BIT22 35 +#define PLIC_INT_GPIO1_BIT9_OR_GPIO2_BIT23 36 +#define PLIC_INT_GPIO1_BIT10_OR_GPIO2_BIT24 37 +#define PLIC_INT_GPIO1_BIT11_OR_GPIO2_BIT25 38 +#define PLIC_INT_GPIO1_BIT12_OR_GPIO2_BIT26 39 +#define PLIC_INT_GPIO1_BIT13_OR_GPIO2_BIT27 40 +#define PLIC_INT_GPIO1_BIT14_OR_GPIO2_BIT28 41 +#define PLIC_INT_GPIO1_BIT15_OR_GPIO2_BIT29 42 +#define PLIC_INT_GPIO1_BIT16_OR_GPIO2_BIT30 43 +#define PLIC_INT_GPIO1_BIT17_OR_GPIO2_BIT31 44 +#define PLIC_INT_GPIO1_BIT18 45 +#define PLIC_INT_GPIO1_BIT19 46 +#define PLIC_INT_GPIO1_BIT20 47 +#define PLIC_INT_GPIO1_BIT21 48 +#define PLIC_INT_GPIO1_BIT22 49 +#define PLIC_INT_GPIO1_BIT23 50 +#define PLIC_INT_GPIO0_NON_DIRECT 51 +#define PLIC_INT_GPIO1_NON_DIRECT 52 +#define PLIC_INT_GPIO2_NON_DIRECT 53 +#define PLIC_INT_SPI0 54 +#define PLIC_INT_SPI1 55 +#define PLIC_INT_CAN0 56 +#define PLIC_INT_CAN1 57 +#define PLIC_INT_I2C0_MAIN 58 +#define PLIC_INT_I2C0_ALERT 59 +#define PLIC_INT_I2C0_SUS 60 +#define PLIC_INT_I2C1_MAIN 61 +#define PLIC_INT_I2C1_ALERT 62 +#define PLIC_INT_I2C1_SUS 63 +#define PLIC_INT_MAC0_INT 64 +#define PLIC_INT_MAC0_QUEUE1 65 +#define PLIC_INT_MAC0_QUEUE2 66 +#define PLIC_INT_MAC0_QUEUE3 67 +#define PLIC_INT_MAC0_EMAC 68 +#define PLIC_INT_MAC0_MMSL 69 +#define PLIC_INT_MAC1_INT 70 +#define PLIC_INT_MAC1_QUEUE1 71 +#define PLIC_INT_MAC1_QUEUE2 72 +#define PLIC_INT_MAC1_QUEUE3 73 +#define PLIC_INT_MAC1_EMAC 74 +#define PLIC_INT_MAC1_MMSL 75 +#define PLIC_INT_DDRC_TRAIN 76 +#define PLIC_INT_SCB_INTERRUPT 77 +#define PLIC_INT_ECC_ERROR 78 +#define PLIC_INT_ECC_CORRECT 79 +#define PLIC_INT_RTC_WAKEUP 80 +#define PLIC_INT_RTC_MATCH 81 +#define PLIC_INT_TIMER1 82 +#define PLIC_INT_TIMER2 83 +#define PLIC_INT_ENVM 84 +#define PLIC_INT_QSPI 85 +#define PLIC_INT_USB_DMA 86 +#define PLIC_INT_USB_MC 87 +#define PLIC_INT_MMC_MAIN 88 +#define PLIC_INT_MMC_WAKEUP 89 +#define PLIC_INT_MMUART0 90 +#define PLIC_INT_MMUART1 91 +#define PLIC_INT_MMUART2 92 +#define PLIC_INT_MMUART3 93 +#define PLIC_INT_MMUART4 94 +#define PLIC_INT_G5C_DEVRST 95 +#define PLIC_INT_G5C_MESSAGE 96 +#define PLIC_INT_USOC_VC_INTERRUPT 97 +#define PLIC_INT_USOC_SMB_INTERRUPT 98 +#define PLIC_INT_E51_0_MAINTENACE 99 +#define PLIC_INT_WDOG0_MRVP 100 +#define PLIC_INT_WDOG1_MRVP 101 +#define PLIC_INT_WDOG2_MRVP 102 +#define PLIC_INT_WDOG3_MRVP 103 +#define PLIC_INT_WDOG4_MRVP 104 +#define PLIC_INT_WDOG0_TOUT 105 +#define PLIC_INT_WDOG1_TOUT 106 +#define PLIC_INT_WDOG2_TOUT 107 +#define PLIC_INT_WDOG3_TOUT 108 +#define PLIC_INT_WDOG4_TOUT 109 +#define PLIC_INT_G5C_MSS_SPI 110 +#define PLIC_INT_VOLT_TEMP_ALARM 111 +#define PLIC_INT_ATHENA_COMPLETE 112 +#define PLIC_INT_ATHENA_ALARM 113 +#define PLIC_INT_ATHENA_BUS_ERROR 114 +#define PLIC_INT_USOC_AXIC_US 115 +#define PLIC_INT_USOC_AXIC_DS 116 +#define PLIC_INT_SPARE 117 +#define PLIC_INT_FABRIC_F2H_0 118 +#define PLIC_INT_FABRIC_F2H_1 119 +#define PLIC_INT_FABRIC_F2H_2 120 +#define PLIC_INT_FABRIC_F2H_3 121 +#define PLIC_INT_FABRIC_F2H_4 122 +#define PLIC_INT_FABRIC_F2H_5 123 +#define PLIC_INT_FABRIC_F2H_6 124 +#define PLIC_INT_FABRIC_F2H_7 125 +#define PLIC_INT_FABRIC_F2H_8 126 +#define PLIC_INT_FABRIC_F2H_9 127 +#define PLIC_INT_FABRIC_F2H_10 128 +#define PLIC_INT_FABRIC_F2H_11 129 +#define PLIC_INT_FABRIC_F2H_12 130 +#define PLIC_INT_FABRIC_F2H_13 131 +#define PLIC_INT_FABRIC_F2H_14 132 +#define PLIC_INT_FABRIC_F2H_15 133 +#define PLIC_INT_FABRIC_F2H_16 134 +#define PLIC_INT_FABRIC_F2H_17 135 +#define PLIC_INT_FABRIC_F2H_18 136 +#define PLIC_INT_FABRIC_F2H_19 137 +#define PLIC_INT_FABRIC_F2H_20 138 +#define PLIC_INT_FABRIC_F2H_21 139 +#define PLIC_INT_FABRIC_F2H_22 140 +#define PLIC_INT_FABRIC_F2H_23 141 +#define PLIC_INT_FABRIC_F2H_24 142 +#define PLIC_INT_FABRIC_F2H_25 143 +#define PLIC_INT_FABRIC_F2H_26 144 +#define PLIC_INT_FABRIC_F2H_27 145 +#define PLIC_INT_FABRIC_F2H_28 146 +#define PLIC_INT_FABRIC_F2H_29 147 +#define PLIC_INT_FABRIC_F2H_30 148 +#define PLIC_INT_FABRIC_F2H_31 149 +#define PLIC_INT_FABRIC_F2H_32 150 +#define PLIC_INT_FABRIC_F2H_33 151 +#define PLIC_INT_FABRIC_F2H_34 152 +#define PLIC_INT_FABRIC_F2H_35 153 +#define PLIC_INT_FABRIC_F2H_36 154 +#define PLIC_INT_FABRIC_F2H_37 155 +#define PLIC_INT_FABRIC_F2H_38 156 +#define PLIC_INT_FABRIC_F2H_39 157 +#define PLIC_INT_FABRIC_F2H_40 158 +#define PLIC_INT_FABRIC_F2H_41 159 +#define PLIC_INT_FABRIC_F2H_42 160 +#define PLIC_INT_FABRIC_F2H_43 161 +#define PLIC_INT_FABRIC_F2H_44 162 +#define PLIC_INT_FABRIC_F2H_45 163 +#define PLIC_INT_FABRIC_F2H_46 164 +#define PLIC_INT_FABRIC_F2H_47 165 +#define PLIC_INT_FABRIC_F2H_48 166 +#define PLIC_INT_FABRIC_F2H_49 167 +#define PLIC_INT_FABRIC_F2H_50 168 +#define PLIC_INT_FABRIC_F2H_51 169 +#define PLIC_INT_FABRIC_F2H_52 170 +#define PLIC_INT_FABRIC_F2H_53 171 +#define PLIC_INT_FABRIC_F2H_54 172 +#define PLIC_INT_FABRIC_F2H_55 173 +#define PLIC_INT_FABRIC_F2H_56 174 +#define PLIC_INT_FABRIC_F2H_57 175 +#define PLIC_INT_FABRIC_F2H_58 176 +#define PLIC_INT_FABRIC_F2H_59 177 +#define PLIC_INT_FABRIC_F2H_60 178 +#define PLIC_INT_FABRIC_F2H_61 179 +#define PLIC_INT_FABRIC_F2H_62 180 +#define PLIC_INT_FABRIC_F2H_63 181 +#define PLIC_INT_BUS_ERROR_UNIT_HART_0 182 +#define PLIC_INT_BUS_ERROR_UNIT_HART_1 183 +#define PLIC_INT_BUS_ERROR_UNIT_HART_2 184 +#define PLIC_INT_BUS_ERROR_UNIT_HART_3 185 +#define PLIC_INT_BUS_ERROR_UNIT_HART_4 186 + +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H */ diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h new file mode 100644 index 00000000000..c4331b8521b --- /dev/null +++ b/include/dt-bindings/interrupt-controller/riscv-hart.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H + +#define HART_INT_U_SOFT 0 +#define HART_INT_S_SOFT 1 +#define HART_INT_M_SOFT 3 +#define HART_INT_U_TIMER 4 +#define HART_INT_S_TIMER 5 +#define HART_INT_M_TIMER 7 +#define HART_INT_U_EXT 8 +#define HART_INT_S_EXT 9 +#define HART_INT_M_EXT 11 + +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */ -- cgit v1.3.1 From 54bec17f6b0326bbc22f993d28170d4c4df4ceed Mon Sep 17 00:00:00 2001 From: Masahisa Kojima Date: Tue, 7 Dec 2021 14:15:31 +0900 Subject: efi_loader: efi_tcg2_register returns appropriate error This commit modify efi_tcg2_register() to return the appropriate error. With this fix, sandbox will not boot because efi_tcg2_register() fails due to some missing feature in GetCapabilities. So disable sandbox if EFI_TCG2_PROTOCOL is enabled. UEFI secure boot variable measurement is not directly related to TCG2 protocol installation, tcg2_measure_secure_boot_variable() is moved to the separate function. Signed-off-by: Masahisa Kojima Reviewed-by: Ilias Apalodimas --- include/efi_loader.h | 2 ++ lib/efi_loader/Kconfig | 2 ++ lib/efi_loader/efi_setup.c | 4 +++ lib/efi_loader/efi_tcg2.c | 65 +++++++++++++++++++++++++++++++++------------- 4 files changed, 55 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index 67c40ca57a7..f4860e87fc1 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -525,6 +525,8 @@ efi_status_t efi_disk_register(void); efi_status_t efi_rng_register(void); /* Called by efi_init_obj_list() to install EFI_TCG2_PROTOCOL */ efi_status_t efi_tcg2_register(void); +/* Called by efi_init_obj_list() to do initial measurement */ +efi_status_t efi_tcg2_do_initial_measurement(void); /* measure the pe-coff image, extend PCR and add Event Log */ efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size, struct efi_loaded_image_obj *handle, diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 700dc838ddb..24f9a2bb757 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -308,6 +308,8 @@ config EFI_TCG2_PROTOCOL bool "EFI_TCG2_PROTOCOL support" default y depends on TPM_V2 + # Sandbox TPM currently fails on GetCapabilities needed for TCG2 + depends on !SANDBOX select SHA1 select SHA256 select SHA384 diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index 1aba71cd962..49172e35798 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -241,6 +241,10 @@ efi_status_t efi_init_obj_list(void) ret = efi_tcg2_register(); if (ret != EFI_SUCCESS) goto out; + + ret = efi_tcg2_do_initial_measurement(); + if (ret == EFI_SECURITY_VIOLATION) + goto out; } /* Secure boot */ diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index 5f71b188a03..bdfd9a37b54 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -153,6 +153,15 @@ static u16 alg_to_len(u16 hash_alg) return 0; } +static bool is_tcg2_protocol_installed(void) +{ + struct efi_handler *handler; + efi_status_t ret; + + ret = efi_search_protocol(efi_root, &efi_guid_tcg2_protocol, &handler); + return ret == EFI_SUCCESS; +} + static u32 tcg_event_final_size(struct tpml_digest_values *digest_list) { u32 len; @@ -1664,6 +1673,14 @@ void tcg2_uninit(void) event_log.buffer = NULL; efi_free_pool(event_log.final_buffer); event_log.final_buffer = NULL; + + if (!is_tcg2_protocol_installed()) + return; + + ret = efi_remove_protocol(efi_root, &efi_guid_tcg2_protocol, + (void *)&efi_tcg2_protocol); + if (ret != EFI_SUCCESS) + log_err("Failed to remove EFI TCG2 protocol\n"); } /** @@ -2345,12 +2362,37 @@ error: return ret; } +/** + * efi_tcg2_do_initial_measurement() - do initial measurement + * + * Return: status code + */ +efi_status_t efi_tcg2_do_initial_measurement(void) +{ + efi_status_t ret; + struct udevice *dev; + + if (!is_tcg2_protocol_installed()) + return EFI_SUCCESS; + + ret = platform_get_tpm2_device(&dev); + if (ret != EFI_SUCCESS) + return EFI_SECURITY_VIOLATION; + + ret = tcg2_measure_secure_boot_variable(dev); + if (ret != EFI_SUCCESS) + goto out; + +out: + return ret; +} + /** * efi_tcg2_register() - register EFI_TCG2_PROTOCOL * * If a TPM2 device is available, the TPM TCG2 Protocol is registered * - * Return: An error status is only returned if adding the protocol fails. + * Return: status code */ efi_status_t efi_tcg2_register(void) { @@ -2373,8 +2415,10 @@ efi_status_t efi_tcg2_register(void) } ret = efi_init_event_log(); - if (ret != EFI_SUCCESS) + if (ret != EFI_SUCCESS) { + tcg2_uninit(); goto fail; + } ret = efi_add_protocol(efi_root, &efi_guid_tcg2_protocol, (void *)&efi_tcg2_protocol); @@ -2391,24 +2435,9 @@ efi_status_t efi_tcg2_register(void) goto fail; } - ret = tcg2_measure_secure_boot_variable(dev); - if (ret != EFI_SUCCESS) { - tcg2_uninit(); - goto fail; - } - return ret; fail: log_err("Cannot install EFI_TCG2_PROTOCOL\n"); - /* - * Return EFI_SUCCESS and don't stop the EFI subsystem. - * That's done for 2 reasons - * - If the protocol is not installed the PCRs won't be extended. So - * someone later in the boot flow will notice that and take the - * necessary actions. - * - The TPM sandbox is limited and we won't be able to run any efi - * related tests with TCG2 enabled - */ - return EFI_SUCCESS; + return ret; } -- cgit v1.3.1 From 2abd8d1c9920cbc02ecef284c86ffe14be743c2b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 4 Dec 2021 08:56:30 -0700 Subject: efi: Rename UCLASS_EFI and IF_TYPE_EFI These names are better used for access to devices provided by an EFI layer. Use EFI_LOADER instead here, since these are only available in U-Boot's EFI_LOADER layer. Signed-off-by: Simon Glass Reviewed-by: Heinrich Schuchardt --- doc/develop/uefi/uefi.rst | 8 ++++---- drivers/block/blk-uclass.c | 4 ++-- include/blk.h | 2 +- include/dm/uclass-id.h | 2 +- lib/efi_driver/efi_block_device.c | 8 ++++---- lib/efi_driver/efi_uclass.c | 8 ++++---- 6 files changed, 16 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index f17138f5c76..a3e2656ab81 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -620,12 +620,12 @@ EFI_DRIVER_BINDING_PROTOCOL implementation for the UEFI drivers. A linker created list is used to keep track of the UEFI drivers. To create an entry in the list the UEFI driver uses the U_BOOT_DRIVER macro specifying -UCLASS_EFI as the ID of its uclass, e.g:: +UCLASS_EFI_LOADER as the ID of its uclass, e.g:: /* Identify as UEFI driver */ U_BOOT_DRIVER(efi_block) = { .name = "EFI block driver", - .id = UCLASS_EFI, + .id = UCLASS_EFI_LOADER, .ops = &driver_ops, }; @@ -651,8 +651,8 @@ UEFI block IO driver The UEFI block IO driver supports devices exposing the EFI_BLOCK_IO_PROTOCOL. When connected it creates a new U-Boot block IO device with interface type -IF_TYPE_EFI, adds child controllers mapping the partitions, and installs the -EFI_SIMPLE_FILE_SYSTEM_PROTOCOL on these. This can be used together with the +IF_TYPE_EFI_LOADER, adds child controllers mapping the partitions, and installs +the EFI_SIMPLE_FILE_SYSTEM_PROTOCOL on these. This can be used together with the software iPXE to boot from iSCSI network drives [4]. This driver is only available if U-Boot is configured with:: diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index 83682dcc181..a7470ae28d5 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -28,7 +28,7 @@ static const char *if_typename_str[IF_TYPE_COUNT] = { [IF_TYPE_SATA] = "sata", [IF_TYPE_HOST] = "host", [IF_TYPE_NVME] = "nvme", - [IF_TYPE_EFI] = "efi", + [IF_TYPE_EFI_LOADER] = "efiloader", [IF_TYPE_VIRTIO] = "virtio", [IF_TYPE_PVBLOCK] = "pvblock", }; @@ -44,7 +44,7 @@ static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = { [IF_TYPE_SATA] = UCLASS_AHCI, [IF_TYPE_HOST] = UCLASS_ROOT, [IF_TYPE_NVME] = UCLASS_NVME, - [IF_TYPE_EFI] = UCLASS_EFI, + [IF_TYPE_EFI_LOADER] = UCLASS_EFI_LOADER, [IF_TYPE_VIRTIO] = UCLASS_VIRTIO, [IF_TYPE_PVBLOCK] = UCLASS_PVBLOCK, }; diff --git a/include/blk.h b/include/blk.h index f0cc7ca1a28..f0835c3fed5 100644 --- a/include/blk.h +++ b/include/blk.h @@ -34,7 +34,7 @@ enum if_type { IF_TYPE_SATA, IF_TYPE_HOST, IF_TYPE_NVME, - IF_TYPE_EFI, + IF_TYPE_EFI_LOADER, IF_TYPE_PVBLOCK, IF_TYPE_VIRTIO, diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index fd139b9b2a0..b68088d0eed 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -48,7 +48,7 @@ enum uclass_id { UCLASS_DMA, /* Direct Memory Access */ UCLASS_DSA, /* Distributed (Ethernet) Switch Architecture */ UCLASS_ECDSA, /* Elliptic curve cryptographic device */ - UCLASS_EFI, /* EFI managed devices */ + UCLASS_EFI_LOADER, /* Devices created by UEFI applications */ UCLASS_ETH, /* Ethernet device */ UCLASS_ETH_PHY, /* Ethernet PHY device */ UCLASS_FIRMWARE, /* Firmware */ diff --git a/lib/efi_driver/efi_block_device.c b/lib/efi_driver/efi_block_device.c index 0937e3595a4..04cb3ef0d4e 100644 --- a/lib/efi_driver/efi_block_device.c +++ b/lib/efi_driver/efi_block_device.c @@ -147,7 +147,7 @@ static int efi_bl_bind(efi_handle_t handle, void *interface) if (!obj) return -ENOENT; - devnum = blk_find_max_devnum(IF_TYPE_EFI); + devnum = blk_find_max_devnum(IF_TYPE_EFI_LOADER); if (devnum == -ENODEV) devnum = 0; else if (devnum < 0) @@ -159,8 +159,8 @@ static int efi_bl_bind(efi_handle_t handle, void *interface) sprintf(name, "efiblk#%d", devnum); /* Create driver model udevice for the EFI block io device */ - ret = blk_create_device(parent, "efi_blk", name, IF_TYPE_EFI, devnum, - io->media->block_size, + ret = blk_create_device(parent, "efi_blk", name, IF_TYPE_EFI_LOADER, + devnum, io->media->block_size, (lbaint_t)io->media->last_block, &bdev); if (ret) return ret; @@ -209,6 +209,6 @@ static const struct efi_driver_ops driver_ops = { /* Identify as EFI driver */ U_BOOT_DRIVER(efi_block) = { .name = "EFI block driver", - .id = UCLASS_EFI, + .id = UCLASS_EFI_LOADER, .ops = &driver_ops, }; diff --git a/lib/efi_driver/efi_uclass.c b/lib/efi_driver/efi_uclass.c index 382c2b477f4..b01ce89c84e 100644 --- a/lib/efi_driver/efi_uclass.c +++ b/lib/efi_driver/efi_uclass.c @@ -308,7 +308,7 @@ efi_status_t efi_driver_init(void) log_debug("Initializing EFI driver framework\n"); for (drv = ll_entry_start(struct driver, driver); drv < ll_entry_end(struct driver, driver); ++drv) { - if (drv->id == UCLASS_EFI) { + if (drv->id == UCLASS_EFI_LOADER) { ret = efi_add_driver(drv); if (ret != EFI_SUCCESS) { log_err("Failed to add EFI driver %s\n", @@ -328,7 +328,7 @@ efi_status_t efi_driver_init(void) */ static int efi_uc_init(struct uclass *class) { - log_debug("Initializing UCLASS_EFI\n"); + log_debug("Initializing UCLASS_EFI_LOADER\n"); return 0; } @@ -340,13 +340,13 @@ static int efi_uc_init(struct uclass *class) */ static int efi_uc_destroy(struct uclass *class) { - log_debug("Destroying UCLASS_EFI\n"); + log_debug("Destroying UCLASS_EFI_LOADER\n"); return 0; } UCLASS_DRIVER(efi) = { .name = "efi", - .id = UCLASS_EFI, + .id = UCLASS_EFI_LOADER, .init = efi_uc_init, .destroy = efi_uc_destroy, }; -- cgit v1.3.1 From 42b7f4212a1cb9aa6a5ca959d1f40b6f8465fd8c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 4 Dec 2021 08:56:31 -0700 Subject: efi: Add uclass for devices provided by UEFI firmware UCLASS_EFI_LOADER is used for devices created by applications and drivers loaded by U-Boots UEFI implementation. This patch provides a new uclass (UCLASS_EFI_MEDIA) to be used for devices that provided by a UEFI firmware calling U-Boot as an EFI application. If the two uclasses can be unified, is left to future redesign. Signed-off-by: Simon Glass Reviewed-by: Heinrich Schuchardt --- MAINTAINERS | 3 +++ arch/sandbox/dts/test.dts | 4 ++++ disk/part.c | 5 ++++- drivers/block/Kconfig | 23 +++++++++++++++++++++++ drivers/block/Makefile | 3 +++ drivers/block/blk-uclass.c | 2 ++ drivers/block/efi-media-uclass.c | 15 +++++++++++++++ drivers/block/sb_efi_media.c | 20 ++++++++++++++++++++ include/blk.h | 1 + include/dm/uclass-id.h | 1 + test/dm/Makefile | 1 + test/dm/efi_media.c | 24 ++++++++++++++++++++++++ 12 files changed, 101 insertions(+), 1 deletion(-) create mode 100644 drivers/block/efi-media-uclass.c create mode 100644 drivers/block/sb_efi_media.c create mode 100644 test/dm/efi_media.c (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index e718ad21355..90666ce376c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -713,8 +713,11 @@ W: https://u-boot.readthedocs.io/en/latest/develop/uefi/u-boot_on_efi.html F: board/efi/efi-x86_app F: configs/efi-x86_app* F: doc/develop/uefi/u-boot_on_efi.rst +F: drivers/block/efi-media-uclass.c +F: drivers/block/sb_efi_media.c F: lib/efi/efi_app.c F: scripts/build-efi.sh +F: test/dm/efi_media.c EFI PAYLOAD M: Heinrich Schuchardt diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 8cd688e8d26..2cea4a43c87 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -498,6 +498,10 @@ compatible = "sandbox,clk-ccf"; }; + efi-media { + compatible = "sandbox,efi-media"; + }; + eth@10002000 { compatible = "sandbox,eth"; reg = <0x10002000 0x1000>; diff --git a/disk/part.c b/disk/part.c index fe1ebd4adf7..e857a9f9585 100644 --- a/disk/part.c +++ b/disk/part.c @@ -296,8 +296,11 @@ static void print_part_header(const char *type, struct blk_desc *dev_desc) case IF_TYPE_VIRTIO: puts("VirtIO"); break; + case IF_TYPE_EFI_MEDIA: + puts("EFI"); + break; default: - puts ("UNKNOWN"); + puts("UNKNOWN"); break; } printf (" device %d -- Partition Type: %s\n\n", diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 56a4eec05ac..755fdccb574 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -61,6 +61,29 @@ config TPL_BLOCK_CACHE help This option enables the disk-block cache in TPL +config EFI_MEDIA + bool "Support EFI media drivers" + default y if EFI || SANDBOX + help + Enable this to support media devices on top of UEFI. This enables + just the uclass so you also need a specific driver to make this do + anything. + + For sandbox there is a test driver. + +if EFI_MEDIA + +config EFI_MEDIA_SANDBOX + bool "Sandbox EFI media driver" + depends on SANDBOX + default y + help + Enables a simple sandbox media driver, used for testing just the + EFI_MEDIA uclass. It does not do anything useful, since sandbox does + not actually support running on top of UEFI. + +endif # EFI_MEDIA + config IDE bool "Support IDE controllers" select HAVE_BLOCK_DEVICE diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 94ab5c6f906..3778633da1d 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -14,3 +14,6 @@ obj-$(CONFIG_IDE) += ide.o endif obj-$(CONFIG_SANDBOX) += sandbox.o obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o + +obj-$(CONFIG_EFI_MEDIA) += efi-media-uclass.o +obj-$(CONFIG_EFI_MEDIA_SANDBOX) += sb_efi_media.o diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index a7470ae28d5..4ae8af6d609 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -28,6 +28,7 @@ static const char *if_typename_str[IF_TYPE_COUNT] = { [IF_TYPE_SATA] = "sata", [IF_TYPE_HOST] = "host", [IF_TYPE_NVME] = "nvme", + [IF_TYPE_EFI_MEDIA] = "efi", [IF_TYPE_EFI_LOADER] = "efiloader", [IF_TYPE_VIRTIO] = "virtio", [IF_TYPE_PVBLOCK] = "pvblock", @@ -44,6 +45,7 @@ static enum uclass_id if_type_uclass_id[IF_TYPE_COUNT] = { [IF_TYPE_SATA] = UCLASS_AHCI, [IF_TYPE_HOST] = UCLASS_ROOT, [IF_TYPE_NVME] = UCLASS_NVME, + [IF_TYPE_EFI_MEDIA] = UCLASS_EFI_MEDIA, [IF_TYPE_EFI_LOADER] = UCLASS_EFI_LOADER, [IF_TYPE_VIRTIO] = UCLASS_VIRTIO, [IF_TYPE_PVBLOCK] = UCLASS_PVBLOCK, diff --git a/drivers/block/efi-media-uclass.c b/drivers/block/efi-media-uclass.c new file mode 100644 index 00000000000..e012f6f2f4c --- /dev/null +++ b/drivers/block/efi-media-uclass.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Uclass for EFI media devices + * + * Copyright 2021 Google LLC + */ + +#include +#include + +UCLASS_DRIVER(efi_media) = { + .id = UCLASS_EFI_MEDIA, + .name = "efi_media", + .flags = DM_UC_FLAG_SEQ_ALIAS, +}; diff --git a/drivers/block/sb_efi_media.c b/drivers/block/sb_efi_media.c new file mode 100644 index 00000000000..52af155a600 --- /dev/null +++ b/drivers/block/sb_efi_media.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * EFI_MEDIA driver for sandbox + * + * Copyright 2021 Google LLC + */ + +#include +#include + +static const struct udevice_id sandbox_efi_media_ids[] = { + { .compatible = "sandbox,efi-media" }, + { } +}; + +U_BOOT_DRIVER(sandbox_efi_media) = { + .name = "sandbox_efi_media", + .id = UCLASS_EFI_MEDIA, + .of_match = sandbox_efi_media_ids, +}; diff --git a/include/blk.h b/include/blk.h index f0835c3fed5..dde21732572 100644 --- a/include/blk.h +++ b/include/blk.h @@ -37,6 +37,7 @@ enum if_type { IF_TYPE_EFI_LOADER, IF_TYPE_PVBLOCK, IF_TYPE_VIRTIO, + IF_TYPE_EFI_MEDIA, IF_TYPE_COUNT, /* Number of interface types */ }; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index b68088d0eed..0e26e1d1382 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -49,6 +49,7 @@ enum uclass_id { UCLASS_DSA, /* Distributed (Ethernet) Switch Architecture */ UCLASS_ECDSA, /* Elliptic curve cryptographic device */ UCLASS_EFI_LOADER, /* Devices created by UEFI applications */ + UCLASS_EFI_MEDIA, /* Devices provided by UEFI firmware */ UCLASS_ETH, /* Ethernet device */ UCLASS_ETH_PHY, /* Ethernet PHY device */ UCLASS_FIRMWARE, /* Firmware */ diff --git a/test/dm/Makefile b/test/dm/Makefile index 548649f8e82..d46552fbf32 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_DMA) += dma.o obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi_host.o obj-$(CONFIG_DM_DSA) += dsa.o obj-$(CONFIG_ECDSA_VERIFY) += ecdsa.o +obj-$(CONFIG_EFI_MEDIA_SANDBOX) += efi_media.o obj-$(CONFIG_DM_ETH) += eth.o ifneq ($(CONFIG_EFI_PARTITION),) obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o diff --git a/test/dm/efi_media.c b/test/dm/efi_media.c new file mode 100644 index 00000000000..e343a0e9c85 --- /dev/null +++ b/test/dm/efi_media.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Test for EFI_MEDIA uclass + * + * Copyright 2021 Google LLC + */ + +#include +#include +#include +#include +#include +#include + +/* Test that we can use the EFI_MEDIA uclass */ +static int dm_test_efi_media(struct unit_test_state *uts) +{ + struct udevice *dev; + + ut_assertok(uclass_first_device_err(UCLASS_EFI_MEDIA, &dev)); + + return 0; +} +DM_TEST(dm_test_efi_media, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT); -- cgit v1.3.1 From d8063dc373eb5ed5b4a31fdd3eecd32cba592696 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 4 Dec 2021 08:56:32 -0700 Subject: efi: Add a media/block driver for EFI block devices Add a block driver which handles read/write for EFI block devices. This driver actually already exists ('efi_block') but is not really suitable for use as a real U-Boot driver: - The operations do not provide a udevice - The code is designed for running as part of EFI loader, so uses EFI_PRINT() and EFI_CALL(). - The bind method probes the device, which is not permitted - It uses 'EFI' as its parent device The new driver is more 'normal', just requiring its platform data be set up in advance. Signed-off-by: Simon Glass Reviewed-by: Heinrich Schuchardt --- drivers/block/Kconfig | 10 +++++ drivers/block/Makefile | 1 + drivers/block/efi_blk.c | 115 ++++++++++++++++++++++++++++++++++++++++++++++++ include/efi.h | 11 +++++ 4 files changed, 137 insertions(+) create mode 100644 drivers/block/efi_blk.c (limited to 'include') diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 755fdccb574..8235430497d 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -82,6 +82,16 @@ config EFI_MEDIA_SANDBOX EFI_MEDIA uclass. It does not do anything useful, since sandbox does not actually support running on top of UEFI. +config EFI_MEDIA_BLK + bool "EFI media block driver" + depends on EFI_APP + default y + help + Enables a block driver for providing access to UEFI devices. This + allows use of block devices detected by the underlying UEFI + implementation. With this it is possible to use filesystems on these + devices, for example. + endif # EFI_MEDIA config IDE diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 3778633da1d..b221a7c6eea 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o obj-$(CONFIG_EFI_MEDIA) += efi-media-uclass.o obj-$(CONFIG_EFI_MEDIA_SANDBOX) += sb_efi_media.o +obj-$(CONFIG_EFI_MEDIA_BLK) += efi_blk.o diff --git a/drivers/block/efi_blk.c b/drivers/block/efi_blk.c new file mode 100644 index 00000000000..9d25ecbf37f --- /dev/null +++ b/drivers/block/efi_blk.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Block driver for EFI devices + * This supports a media driver of UCLASS_EFI with a child UCLASS_BLK + * It allows block-level access to EFI devices made available via EFI boot + * services + * + * Copyright 2021 Google LLC + */ + +#include +#include +#include +#include +#include + +struct efi_block_plat { + struct efi_block_io *blkio; +}; + +/** + * Read from block device + * + * @dev: device + * @blknr: first block to be read + * @blkcnt: number of blocks to read + * @buffer: output buffer + * Return: number of blocks transferred + */ +static ulong efi_bl_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, + void *buffer) +{ + struct efi_block_plat *plat = dev_get_plat(dev); + struct efi_block_io *io = plat->blkio; + efi_status_t ret; + + log_debug("read buf=%p, block=%lx, count=%lx: ", buffer, (ulong)blknr, + (ulong)blkcnt); + ret = io->read_blocks(io, io->media->media_id, blknr, + blkcnt * io->media->block_size, buffer); + log_debug("ret=%lx (dec %ld)\n", ret & ~EFI_ERROR_MASK, + ret & ~EFI_ERROR_MASK); + if (ret) + return 0; + + return blkcnt; +} + +/** + * Write to block device + * + * @dev: device + * @blknr: first block to be write + * @blkcnt: number of blocks to write + * @buffer: input buffer + * Return: number of blocks transferred + */ +static ulong efi_bl_write(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, + const void *buffer) +{ + struct efi_block_plat *plat = dev_get_plat(dev); + struct efi_block_io *io = plat->blkio; + efi_status_t ret; + + log_debug("write buf=%p, block=%lx, count=%lx: ", buffer, (ulong)blknr, + (ulong)blkcnt); + ret = io->write_blocks(io, io->media->media_id, blknr, + blkcnt * io->media->block_size, (void *)buffer); + log_debug("ret=%lx (dec %ld)\n", ret & ~EFI_ERROR_MASK, + ret & ~EFI_ERROR_MASK); + if (ret) + return 0; + + return blkcnt; +} + +/* Block device driver operators */ +static const struct blk_ops efi_blk_ops = { + .read = efi_bl_read, + .write = efi_bl_write, +}; + +U_BOOT_DRIVER(efi_block) = { + .name = "efi_block", + .id = UCLASS_BLK, + .ops = &efi_blk_ops, + .plat_auto = sizeof(struct efi_block_plat), +}; + +static int efi_media_bind(struct udevice *dev) +{ + struct efi_media_plat *plat = dev_get_plat(dev); + struct efi_block_plat *blk_plat; + struct udevice *blk; + int ret; + + ret = blk_create_devicef(dev, "efi_block", "blk", IF_TYPE_EFI_MEDIA, + dev_seq(dev), plat->blkio->media->block_size, + plat->blkio->media->last_block, &blk); + if (ret) { + debug("Cannot create block device\n"); + return ret; + } + blk_plat = dev_get_plat(blk); + blk_plat->blkio = plat->blkio; + + return 0; +} + +U_BOOT_DRIVER(efi_media) = { + .name = "efi_media", + .id = UCLASS_EFI_MEDIA, + .bind = efi_media_bind, + .plat_auto = sizeof(struct efi_media_plat), +}; diff --git a/include/efi.h b/include/efi.h index b5835422b95..0ec5913ddd1 100644 --- a/include/efi.h +++ b/include/efi.h @@ -414,6 +414,17 @@ struct efi_priv { void *next_hdr; }; +/* + * EFI attributes of the udevice handled by efi_media driver + * + * @handle: handle of the controller on which this driver is installed + * @blkio: block io protocol proxied by this driver + */ +struct efi_media_plat { + efi_handle_t handle; + struct efi_block_io *blkio; +}; + /* Base address of the EFI image */ extern char image_base[]; -- cgit v1.3.1 From d5f1beb058a48fb057d3a62dc751a19c1a3db279 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Mon, 6 Dec 2021 10:29:30 -0600 Subject: configs: beacon-rzg2m: Config to address new aliases The resync of the device trees from Linux 5.16-rc3 caused aliases to appear on the MMC devices which changed the numbering. This changed the default boot device and caused boot failure. Update the mmcdev variable to reflect the new aliases. Signed-off-by: Adam Ford --- include/configs/beacon-rzg2m.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/beacon-rzg2m.h b/include/configs/beacon-rzg2m.h index 18d442e06a6..14d6df328a7 100644 --- a/include/configs/beacon-rzg2m.h +++ b/include/configs/beacon-rzg2m.h @@ -23,7 +23,7 @@ "boot_fdt=try\0" \ "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ "initrd_addr=0x43800000\0" \ - "mmcdev=0\0" \ + "mmcdev=1\0" \ "mmcpart=1\0" \ "mmcrootpart=2\0" \ "finduuid=part uuid mmc ${mmcdev}:${mmcrootpart} uuid\0" \ -- cgit v1.3.1 From e8e66801bd512eb1e4c14efca34b7b254ad26110 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Nov 2021 03:24:44 +0100 Subject: ARM: stm32: Increase USB power-good delay on DHSOM The USB hub on STM32MP1 DHCOM boards needs to wait a bit longer until the USB Vbus is stable. Increase the USB power-good delay to 1 s. This adds default-undefined STM32MP_BOARD_EXTRA_ENV variable into stm32mp15_common.h to reduce duplication in board-specific config files adding custom environment. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard --- include/configs/stm32mp15_common.h | 7 ++++++- include/configs/stm32mp15_dh_dhsom.h | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 4e2cabff2e7..dab679f71e3 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -142,6 +142,10 @@ "env_check=if env info -p -d -q; then env save; fi\0" \ "boot_net_usb_start=true\0" +#ifndef STM32MP_BOARD_EXTRA_ENV +#define STM32MP_BOARD_EXTRA_ENV +#endif + #include /* @@ -169,7 +173,8 @@ STM32MP_BOOTCMD \ STM32MP_PARTS_DEFAULT \ BOOTENV \ - STM32MP_EXTRA + STM32MP_EXTRA \ + STM32MP_BOARD_EXTRA_ENV #endif /* ifndef CONFIG_SPL_BUILD */ #endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index c559cd72da7..bac9e8388a7 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -8,6 +8,9 @@ #ifndef __CONFIG_STM32MP15_DH_DHSOM_H__ #define __CONFIG_STM32MP15_DH_DHSOM_H__ +#define STM32MP_BOARD_EXTRA_ENV \ + "usb_pgood_delay=1000\0" + #include #define CONFIG_SPL_TARGET "u-boot.itb" -- cgit v1.3.1 From 44beea28456fc17b6b5137f0104b625d8741a5c6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Nov 2021 03:25:13 +0100 Subject: ARM: stm32: Add update_sf script to install U-Boot into SF on DHSOM Add script to read U-Boot from SD card and write it to matching locations in the SPI NOR, thus making the SPI NOR bootable. The script erases the entire SPI NOR, including U-Boot environment, to make sure the installation is clean. To retain environment from current running U-Boot, run 'saveenv' after running the 'update_sf' script. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- include/configs/stm32mp15_dh_dhsom.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index bac9e8388a7..b68e153f10b 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -9,7 +9,17 @@ #define __CONFIG_STM32MP15_DH_DHSOM_H__ #define STM32MP_BOARD_EXTRA_ENV \ - "usb_pgood_delay=1000\0" + "usb_pgood_delay=1000\0" \ + "update_sf=" /* Erase SPI NOR and install U-Boot from SD */ \ + "setexpr loadaddr1 ${loadaddr} + 0x1000000 && " \ + "load mmc 0:4 ${loadaddr1} /boot/u-boot-spl.stm32 && " \ + "env set filesize1 ${filesize} && " \ + "load mmc 0:4 ${loadaddr} /boot/u-boot.itb && " \ + "sf probe && sf erase 0 0x200000 && " \ + "sf update ${loadaddr1} 0 ${filesize1} && " \ + "sf update ${loadaddr1} 0x40000 ${filesize1} && " \ + "sf update ${loadaddr} 0x80000 ${filesize} && " \ + "env set filesize1 && env set loadaddr1\0" #include -- cgit v1.3.1 From e1d7b0b9c55a105ec8b9d8bcb24d68fc7b74789a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 13 Nov 2021 03:26:05 +0100 Subject: ARM: stm32: Increase PHY auto-negotiation timeout to 20s on DHSOM The Micrel PHYs on known DHSOM based boards take a while to come out of reset, increase the auto-negotiation timeout to prevent it from timing out in case the ethernet is used right after the board was reset. Signed-off-by: Marek Vasut Cc: Patrice Chotard Cc: Patrick Delaunay Reviewed-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- include/configs/stm32mp15_dh_dhsom.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/stm32mp15_dh_dhsom.h b/include/configs/stm32mp15_dh_dhsom.h index b68e153f10b..c79f0272cbe 100644 --- a/include/configs/stm32mp15_dh_dhsom.h +++ b/include/configs/stm32mp15_dh_dhsom.h @@ -8,6 +8,9 @@ #ifndef __CONFIG_STM32MP15_DH_DHSOM_H__ #define __CONFIG_STM32MP15_DH_DHSOM_H__ +/* PHY needs a longer autoneg timeout */ +#define PHY_ANEG_TIMEOUT 20000 + #define STM32MP_BOARD_EXTRA_ENV \ "usb_pgood_delay=1000\0" \ "update_sf=" /* Erase SPI NOR and install U-Boot from SD */ \ -- cgit v1.3.1 From 9e578f6340ba3f4324cd823872afe6eda39857d2 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Sun, 14 Feb 2021 03:17:18 +0100 Subject: clk: fix clk_get_rate() documentation Improve clk_get_rate() @return documentation that otherwise is a bit ambiguous. At the moment I expect to return 0 as error since the return type is 'ulong', instead the function really returns negative value in case the corresponding function pointer is null and returns 0 if the clock is invalid. Signed-off-by: Giulio Benetti Reviewed-by: Sean Anderson --- include/clk.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/clk.h b/include/clk.h index a928879b122..df5255e510e 100644 --- a/include/clk.h +++ b/include/clk.h @@ -389,7 +389,8 @@ int clk_free(struct clk *clk); * * @clk: A clock struct that was previously successfully requested by * clk_request/get_by_*(). - * @return clock rate in Hz, or -ve error code. + * @return clock rate in Hz on success, 0 for invalid clock, or -ve error code + * for other errors. */ ulong clk_get_rate(struct clk *clk); -- cgit v1.3.1 From 19b241c61faaa18c777e684ca5c43ad461af0afd Mon Sep 17 00:00:00 2001 From: AKASHI Takahiro Date: Fri, 10 Dec 2021 15:49:29 +0900 Subject: blk: add a helper function, blk_probe_or_unbind() This function will be commonly used in block device drivers in the succeeding patches. Signed-off-by: AKASHI Takahiro Reviewed-by: Simon Glass Reviewed-by: Heinrich Schuchardt --- drivers/block/blk-uclass.c | 13 +++++++++++++ include/blk.h | 12 ++++++++++++ 2 files changed, 25 insertions(+) (limited to 'include') diff --git a/drivers/block/blk-uclass.c b/drivers/block/blk-uclass.c index 4ae8af6d609..a055387570a 100644 --- a/drivers/block/blk-uclass.c +++ b/drivers/block/blk-uclass.c @@ -672,6 +672,19 @@ int blk_create_devicef(struct udevice *parent, const char *drv_name, return 0; } +int blk_probe_or_unbind(struct udevice *dev) +{ + int ret; + + ret = device_probe(dev); + if (ret) { + log_debug("probing %s failed\n", dev->name); + device_unbind(dev); + } + + return ret; +} + int blk_unbind_all(int if_type) { struct uclass *uc; diff --git a/include/blk.h b/include/blk.h index dde21732572..133204a82e1 100644 --- a/include/blk.h +++ b/include/blk.h @@ -370,6 +370,18 @@ int blk_create_devicef(struct udevice *parent, const char *drv_name, const char *name, int if_type, int devnum, int blksz, lbaint_t lba, struct udevice **devp); +/** + * blk_probe_or_unbind() - Try to probe + * + * Try to probe the device, primarily for enumerating partitions. + * If it fails, the device itself is unbound since it means that it won't + * work any more. + * + * @dev: The device to probe + * Return: 0 if OK, -ve on error + */ +int blk_probe_or_unbind(struct udevice *dev); + /** * blk_unbind_all() - Unbind all device of the given interface type * -- cgit v1.3.1 From 3cfc042d43f5c5cec4bcf0133202bdd8516df66c Mon Sep 17 00:00:00 2001 From: AKASHI Takahiro Date: Fri, 10 Dec 2021 15:49:36 +0900 Subject: dm: fix an 'undefined' error in some macros Due to a non-existing parameter name in macro's, use of those macro's will cause a compiler error of "undefined reference". Unfortunately, dm test doesn't fail because a wrong name ("&dev", hence it is accidentally a valid name in the context of a caller site) is passed on. Signed-off-by: AKASHI Takahiro Fixes: f262d4ca4b2b ("dm: core: Add a way to read platdata for all child devices") Fixes: 903e83ee8464 ("dm: core: Add a way to iterate through children, probing each") Reviewed-by: Simon Glass --- include/dm/device.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/dm/device.h b/include/dm/device.h index 3028d002ab0..f7900417066 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -959,8 +959,8 @@ static inline bool device_is_on_pci_bus(const struct udevice *dev) * @parent: parent device to scan */ #define device_foreach_child_of_to_plat(pos, parent) \ - for (int _ret = device_first_child_ofdata_err(parent, &dev); !_ret; \ - _ret = device_next_child_ofdata_err(&dev)) + for (int _ret = device_first_child_ofdata_err(parent, &pos); !_ret; \ + _ret = device_next_child_ofdata_err(&pos)) /** * device_foreach_child_probe() - iterate through children, probing them @@ -976,8 +976,8 @@ static inline bool device_is_on_pci_bus(const struct udevice *dev) * @parent: parent device to scan */ #define device_foreach_child_probe(pos, parent) \ - for (int _ret = device_first_child_err(parent, &dev); !_ret; \ - _ret = device_next_child_err(&dev)) + for (int _ret = device_first_child_err(parent, &pos); !_ret; \ + _ret = device_next_child_err(&pos)) /** * dm_scan_fdt_dev() - Bind child device in the device tree -- cgit v1.3.1