From 45a3ad81fafe3090f7f89b458f6bd9f547a453df Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 17 Oct 2016 15:51:35 +0200 Subject: mx35: adjust default environment for flea3 board Signed-off-by: Stefano Babic Signed-off-by: Heiko Schocher --- include/configs/flea3.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/flea3.h b/include/configs/flea3.h index 11d9391139f..0f7b3c82dbe 100644 --- a/include/configs/flea3.h +++ b/include/configs/flea3.h @@ -101,10 +101,9 @@ #define CONFIG_CMDLINE_EDITING #define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ @@ -227,8 +226,8 @@ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \ "load=tftp ${loadaddr} ${u-boot}\0" \ "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ - "update=protect off ${uboot_addr} +40000;" \ - "erase ${uboot_addr} +40000;" \ + "update=protect off ${uboot_addr} +80000;" \ + "erase ${uboot_addr} +80000;" \ "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ "upd=if run load;then echo Updating u-boot;if run update;" \ "then echo U-Boot updated;" \ -- cgit v1.3.1 From 36c0627ba5efd602d9ca8ebaae06f30d1890a41a Mon Sep 17 00:00:00 2001 From: Sven Ebenfeld Date: Fri, 25 Nov 2016 21:42:53 +0100 Subject: arm: imx: wandboard: fix compile error if CONFIG_VIDEO is deactivated When I tried to deactivate VIDEO support for the Wandboard, it still tried to initialize the Framebuffer and so on. That is the reason for the added ifdefs. CONFIG_VIDEO is enabled in the configuration as default and therefore nothing changes for the default user. The structs mx6dl_i2c2_pad_info and mx6q_i2c2_pad_info are only available when CONFIG_IPUV3 are set and should not be tried to access, when that define is not defined. Signed-off-by: Sven Ebenfeld --- board/wandboard/wandboard.c | 2 ++ include/configs/wandboard.h | 2 ++ 2 files changed, 4 insertions(+) (limited to 'include') diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index b3f3b34f440..2c9dc8b7c55 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -442,11 +442,13 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; +#if defined(CONFIG_VIDEO_IPUV3) setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); if (is_mx6dq()) setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info); else setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); +#endif return 0; } diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 8c5cf332fa9..406591ce2d5 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -74,6 +74,7 @@ #define CONFIG_PHY_ATHEROS /* Framebuffer */ +#ifdef CONFIG_VIDEO #define CONFIG_VIDEO_IPUV3 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN @@ -85,6 +86,7 @@ #define CONFIG_CMD_HDMIDETECT #define CONFIG_IMX_HDMI #define CONFIG_IMX_VIDEO_SKIP +#endif #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v1.3.1 From d9e268ed766b03c7d2fc36debcd62b6696395aad Mon Sep 17 00:00:00 2001 From: Sebastien Bourdelin Date: Tue, 8 Nov 2016 12:18:07 -0500 Subject: ARM: ts4600: add basic board support This commit adds basic support including: MMC, Serial console Signed-off-by: Sebastien Bourdelin Reviewed-by: Fabio Estevam --- arch/arm/Kconfig | 6 ++ board/technologic/ts4600/Kconfig | 15 ++++ board/technologic/ts4600/MAINTAINERS | 6 ++ board/technologic/ts4600/Makefile | 11 +++ board/technologic/ts4600/iomux.c | 149 +++++++++++++++++++++++++++++++++++ board/technologic/ts4600/ts4600.c | 89 +++++++++++++++++++++ configs/ts4600_defconfig | 18 +++++ include/configs/ts4600.h | 70 ++++++++++++++++ 8 files changed, 364 insertions(+) create mode 100644 board/technologic/ts4600/Kconfig create mode 100644 board/technologic/ts4600/MAINTAINERS create mode 100644 board/technologic/ts4600/Makefile create mode 100644 board/technologic/ts4600/iomux.c create mode 100644 board/technologic/ts4600/ts4600.c create mode 100644 configs/ts4600_defconfig create mode 100644 include/configs/ts4600.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 220022bcd9b..ed25e359766 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -574,6 +574,11 @@ config ARCH_SUNXI select USB_KEYBOARD if DISTRO_DEFAULTS select USE_TINY_PRINTF +config TARGET_TS4600 + bool "Support TS4600" + select CPU_ARM926EJS + select SUPPORT_SPL + config TARGET_TS4800 bool "Support TS4800" select CPU_V7 @@ -1025,6 +1030,7 @@ source "board/ti/ti816x/Kconfig" source "board/timll/devkit3250/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/toradex/colibri_vf/Kconfig" +source "board/technologic/ts4600/Kconfig" source "board/technologic/ts4800/Kconfig" source "board/vscom/baltos/Kconfig" source "board/woodburn/Kconfig" diff --git a/board/technologic/ts4600/Kconfig b/board/technologic/ts4600/Kconfig new file mode 100644 index 00000000000..d0dc2e1b734 --- /dev/null +++ b/board/technologic/ts4600/Kconfig @@ -0,0 +1,15 @@ +if TARGET_TS4600 + +config SYS_BOARD + default "ts4600" + +config SYS_VENDOR + default "technologic" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "ts4600" + +endif diff --git a/board/technologic/ts4600/MAINTAINERS b/board/technologic/ts4600/MAINTAINERS new file mode 100644 index 00000000000..6f683b5995e --- /dev/null +++ b/board/technologic/ts4600/MAINTAINERS @@ -0,0 +1,6 @@ +TS4600 BOARD +M: Sebastien Bourdelin +S: Maintained +F: board/technologic/ts4600/ +F: include/configs/ts4600.h +F: configs/ts4600_defconfig diff --git a/board/technologic/ts4600/Makefile b/board/technologic/ts4600/Makefile new file mode 100644 index 00000000000..faa29705829 --- /dev/null +++ b/board/technologic/ts4600/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2016 Savoir-faire Linux +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_SPL_BUILD +obj-y := ts4600.o +else +obj-y := iomux.o +endif diff --git a/board/technologic/ts4600/iomux.c b/board/technologic/ts4600/iomux.c new file mode 100644 index 00000000000..1398bbe0ccc --- /dev/null +++ b/board/technologic/ts4600/iomux.c @@ -0,0 +1,149 @@ +/* + * (C) Copyright 2016 Savoir-faire Linux Inc. + * + * Author: Sebastien Bourdelin + * + * Based on work from TS7680 code by: + * Kris Bahnsen + * Mark Featherston + * https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680 + * + * Derived from MX28EVK code by + * Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) + +const iomux_cfg_t iomux_setup[] = { + /* DUART */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + + /* MMC0 */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_SCK__SSP0_SCK | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL), + + /* MMC0 slot power enable */ + MX28_PAD_PWM3__GPIO_3_28 | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* I2C */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + +}; + +#define HW_DRAM_CTL29 (0x74 >> 2) +#define CS_MAP 0xf +#define COLUMN_SIZE 0x2 +#define ADDR_PINS 0x1 +#define APREBIT 0xa + +#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \ + ADDR_PINS << 8 | APREBIT) + +#define HW_DRAM_CTL39 (0x9c >> 2) +#define TFAW 0xb +#define TDLL 0xc8 + +#define HW_DRAM_CTL39_CONFIG (TFAW << 24 | TDLL) + +#define HW_DRAM_CTL41 (0xa4 >> 2) +#define TPDEX 0x2 +#define TRCD_INT 0x4 +#define TRC 0xd + +#define HW_DRAM_CTL41_CONFIG (TPDEX << 24 | TRCD_INT << 8 | TRC) + +#define HW_DRAM_CTL42 (0xa8 >> 2) +#define TRAS_MAX 0x36a6 +#define TRAS_MIN 0xa + +#define HW_DRAM_CTL42_CONFIG (TRAS_MAX << 8 | TRAS_MIN) + +#define HW_DRAM_CTL43 (0xac >> 2) +#define TRP 0x4 +#define TRFC 0x27 +#define TREF 0x2a0 + +#define HW_DRAM_CTL43_CONFIG (TRP << 24 | TRFC << 16 | TREF) + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + dram_vals[HW_DRAM_CTL29] = HW_DRAM_CTL29_CONFIG; + dram_vals[HW_DRAM_CTL39] = HW_DRAM_CTL39_CONFIG; + dram_vals[HW_DRAM_CTL41] = HW_DRAM_CTL41_CONFIG; + dram_vals[HW_DRAM_CTL42] = HW_DRAM_CTL42_CONFIG; + dram_vals[HW_DRAM_CTL43] = HW_DRAM_CTL43_CONFIG; +} + +void board_init_ll(const uint32_t arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} diff --git a/board/technologic/ts4600/ts4600.c b/board/technologic/ts4600/ts4600.c new file mode 100644 index 00000000000..70dfeadbccd --- /dev/null +++ b/board/technologic/ts4600/ts4600.c @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2016 Savoir-faire Linux Inc. + * + * Author: Sebastien Bourdelin + * + * Based on work from TS7680 code by: + * Kris Bahnsen + * Mark Featherston + * https://github.com/embeddedarm/u-boot/tree/master/board/technologic/ts7680 + * + * Derived from MX28EVK code by + * Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clocks at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_MMC +static int ts4600_mmc_cd(int id) +{ + return 1; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + mxs_iomux_setup_pad(MX28_PAD_PWM3__GPIO_3_28); + + /* Power-on SD */ + gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 1); + udelay(1000); + gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0); + + /* SD card */ + ret = mxsmmc_initialize(bis, 0, NULL, ts4600_mmc_cd); + if(ret != 0) { + printf("SD controller initialized with %d\n", ret); + } + + return ret; +} +#endif + +int checkboard(void) +{ + puts("Board: TS4600\n"); + + return 0; +} diff --git a/configs/ts4600_defconfig b/configs/ts4600_defconfig new file mode 100644 index 00000000000..c052dedf136 --- /dev/null +++ b/configs/ts4600_defconfig @@ -0,0 +1,18 @@ +CONFIG_ARM=y +CONFIG_TARGET_TS4600=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="ENV_IS_IN_MMC" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/ts4600.h b/include/configs/ts4600.h new file mode 100644 index 00000000000..9b7bd1b91dd --- /dev/null +++ b/include/configs/ts4600.h @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2016 Savoir-faire Linux Inc. + * + * Author: Sebastien Bourdelin + * + * Derived from MX28EVK code by + * Fabio Estevam + * Freescale Semiconductor, Inc. + * + * Configuration settings for the TS4600 Board + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIGS_TS4600_H__ +#define __CONFIGS_TS4600_H__ + +/* System configurations */ +#define CONFIG_MX28 /* i.MX28 SoC */ + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH /* No NOR Flash */ +#define CONFIG_DOS_PARTITION + +/* Memory configuration */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Environment */ +#define CONFIG_ENV_SIZE (8 * 1024) + +/* Environment is in MMC */ +#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (256 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +/* Boot Linux */ +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Extra Environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_addr=0x41000000\0" \ + "loadkernel=load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage\0" \ + "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} imx28-ts4600.dtb\0" \ + "loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot.ub\0" \ + "bootscript=echo Running bootscript from mmc...; " \ + "setenv mmcdev 0; " \ + "setenv mmcpart 2; " \ + "run loadbootscript && source ${loadaddr}; \0" \ + "sdboot=echo Booting from SD card ...; " \ + "setenv mmcdev 0; " \ + "setenv mmcpart 2; " \ + "setenv root /dev/mmcblk0p3; " \ + "run loadkernel && run loadfdt; \0" \ + "startbootsequence=run bootscript || run sdboot \0" \ + +#define CONFIG_BOOTCOMMAND \ + "mmc rescan; " \ + "run startbootsequence; " \ + "setenv cmdline_append console=ttyAMA0,115200; " \ + "setenv bootargs root=${root} rootwait rw ${cmdline_append}; " \ + "bootz ${loadaddr} - ${fdt_addr}; " + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_TS4600_H__ */ -- cgit v1.3.1 From 3ed82d6f9bcb3dd2403d432af28787ba1d83fe1b Mon Sep 17 00:00:00 2001 From: Sanchayan Maity Date: Fri, 25 Nov 2016 16:19:17 +0530 Subject: colibri_vf: Read kernel and device tree from static UBI volumes Our update scripts write the kernel and device tree in seperate UBI volumes. This allows to use a lot less UBI/UBIFS support in U-Boot, which should lower the risk of hitting bugs in this area. Signed-off-by: Sanchayan Maity --- include/configs/colibri_vf.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 0cd77fff51a..d58145e59d5 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -116,9 +116,9 @@ "ubiboot=run setup; " \ "setenv bootargs ${defargs} ${ubiargs} ${mtdparts} " \ "${setupargs} ${vidargs}; echo Booting from NAND...; " \ - "ubi part ubi && ubifsmount ubi0:rootfs && " \ - "ubifsload ${kernel_addr_r} /boot/${kernel_file} && " \ - "ubifsload ${fdt_addr_r} /boot/${soc}-colibri-${fdt_board}.dtb && " \ + "ubi part ubi && " \ + "ubi read ${kernel_addr_r} kernel && " \ + "ubi read ${fdt_addr_r} dtb && " \ "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ #define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot" -- cgit v1.3.1 From 792f186846672140deca7dfbf2f20aece26b5348 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Fri, 25 Nov 2016 16:56:57 -0200 Subject: mx6sx: Add initial support for UDOO Neo Board UDOO Neo Board is a development board from Seco that has three models: - UDOO Neo Basic - UDOO Neo Basic Kick Starter - UDOO Neo Extended - UDOO Neo Full All versions are based on the i.MX6 SoloX processor. For more details about the UDOO Neo board, please refer to: http://www.udoo.org/udoo-neo/ This work is based on a previous commit of Francesco Montefoschi : https://github.com/fmntf/u-boot/commit/877b71184a5105e708024f232d36aed574961844 Only tested on the UDOO Neo Full board. Signed-off-by: Breno Lima Reviewed-by: Fabio Estevam --- arch/arm/cpu/armv7/mx6/Kconfig | 5 + board/udoo/neo/Kconfig | 12 ++ board/udoo/neo/MAINTAINERS | 7 + board/udoo/neo/Makefile | 6 + board/udoo/neo/neo.c | 441 +++++++++++++++++++++++++++++++++++++++++ configs/udoo_neo_defconfig | 30 +++ include/configs/udoo_neo.h | 94 +++++++++ 7 files changed, 595 insertions(+) create mode 100644 board/udoo/neo/Kconfig create mode 100644 board/udoo/neo/MAINTAINERS create mode 100644 board/udoo/neo/Makefile create mode 100644 board/udoo/neo/neo.c create mode 100644 configs/udoo_neo_defconfig create mode 100644 include/configs/udoo_neo.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 8b2217edbda..a81d9440289 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -200,6 +200,10 @@ config TARGET_UDOO bool "udoo" select SUPPORT_SPL +config TARGET_UDOO_NEO + bool "UDOO Neo" + select SUPPORT_SPL + config TARGET_WANDBOARD bool "wandboard" select SUPPORT_SPL @@ -261,6 +265,7 @@ source "board/technexion/pico-imx6ul/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/tqc/tqma6/Kconfig" source "board/udoo/Kconfig" +source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" source "board/warp/Kconfig" diff --git a/board/udoo/neo/Kconfig b/board/udoo/neo/Kconfig new file mode 100644 index 00000000000..8f474df2487 --- /dev/null +++ b/board/udoo/neo/Kconfig @@ -0,0 +1,12 @@ +if TARGET_UDOO_NEO + +config SYS_VENDOR + default "udoo" + +config SYS_BOARD + default "neo" + +config SYS_CONFIG_NAME + default "udoo_neo" + +endif diff --git a/board/udoo/neo/MAINTAINERS b/board/udoo/neo/MAINTAINERS new file mode 100644 index 00000000000..743fe33d059 --- /dev/null +++ b/board/udoo/neo/MAINTAINERS @@ -0,0 +1,7 @@ +UDOO NEO BOARD +M: Breno Lima +M: Francesco Montefoschi +S: Maintained +F: board/udoo/neo/ +F: include/configs/udoo_neo.h +F: configs/udoo_neo_defconfig diff --git a/board/udoo/neo/Makefile b/board/udoo/neo/Makefile new file mode 100644 index 00000000000..150cbc1a971 --- /dev/null +++ b/board/udoo/neo/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2015 UDOO Team +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := neo.o diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c new file mode 100644 index 00000000000..7f17469d9af --- /dev/null +++ b/board/udoo/neo/neo.c @@ -0,0 +1,441 @@ +/* + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. + * Copyright (C) Jasbir Matharu + * Copyright (C) UDOO Team + * + * Author: Breno Lima + * Author: Francesco Montefoschi + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +enum { + UDOO_NEO_TYPE_BASIC, + UDOO_NEO_TYPE_BASIC_KS, + UDOO_NEO_TYPE_FULL, + UDOO_NEO_TYPE_EXTENDED, +}; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm) + +#define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) +#define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \ + MUX_MODE_SION) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + /* CD pin */ + MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Power */ + MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const board_recognition_pads[] = { + /*Connected to R184*/ + MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG, + /*Connected to R185*/ + MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG, +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + /* Configured for WLAN */ + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_b_pad = { + MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +static iomux_v3_cfg_t const peri_3v3_pads[] = { + MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + /* + * Because kernel set WDOG_B mux before pad with the commone pinctrl + * framwork now and wdog reset will be triggered once set WDOG_B mux + * with default pad setting, we set pad setting here to workaround this. + * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set + * as GPIO mux firstly here to workaround it. + */ + imx_iomux_v3_setup_pad(wdog_b_pad); + + /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ + imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, + ARRAY_SIZE(peri_3v3_pads)); + + /* Active high for ncp692 */ + gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); + + return 0; +} + +static int get_board_value(void) +{ + int r184, r185; + + imx_iomux_v3_setup_multiple_pads(board_recognition_pads, + ARRAY_SIZE(board_recognition_pads)); + + gpio_direction_input(IMX_GPIO_NR(4, 13)); + gpio_direction_input(IMX_GPIO_NR(4, 0)); + + r184 = gpio_get_value(IMX_GPIO_NR(4, 13)); + r185 = gpio_get_value(IMX_GPIO_NR(4, 0)); + + /* + * Machine selection - + * Machine r184, r185 + * --------------------------------- + * Basic 0 0 + * Basic Ks 0 1 + * Full 1 0 + * Extended 1 1 + */ + + return (r184 << 1) + r185; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR, 0, 4}, + {USDHC3_BASE_ADDR, 0, 4}, +}; + +#define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1) +#define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ +#ifndef CONFIG_SPL_BUILD + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers\ + (%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning:\ + failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +#else + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + u32 port; + + val = readl(&src_regs->sbmr1); + + if ((val & 0xc0) != 0x40) { + printf("Not boot from USDHC!\n"); + return -EINVAL; + } + + port = (val >> 11) & 0x3; + printf("port %d\n", port); + switch (port) { + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + gpio_direction_input(USDHC2_CD_GPIO); + gpio_direction_output(USDHC2_PWR_GPIO, 1); + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; + break; + } + + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif +} + +char *board_string(void) +{ + switch (get_board_value()) { + case UDOO_NEO_TYPE_BASIC: + return "BASIC"; + case UDOO_NEO_TYPE_BASIC_KS: + return "BASICKS"; + case UDOO_NEO_TYPE_FULL: + return "FULL"; + case UDOO_NEO_TYPE_EXTENDED: + return "EXTENDED"; + } + return "UNDEFINED"; +} + +int checkboard(void) +{ + printf("Board: UDOO Neo %s\n", board_string()); + return 0; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + setenv("board_name", board_string()); +#endif + + return 0; +} + +#ifdef CONFIG_SPL_BUILD + +#include +#include + +static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_ras = 0x00000020, + .dram_cas = 0x00000020, + .dram_odt0 = 0x00000020, + .dram_odt1 = 0x00000020, + .dram_sdba2 = 0x00000000, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_reset = 0x00000020, +}; + +static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000020, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_ctlds = 0x00000020, + .grp_ddr_type = 0x000c0000, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, +}; + +static const struct mx6_mmdc_calibration neo_mmcd_calib = { + .p0_mpwldectrl0 = 0x000E000B, + .p0_mpwldectrl1 = 0x000E0010, + .p0_mpdgctrl0 = 0x41600158, + .p0_mpdgctrl1 = 0x01500140, + .p0_mprddlctl = 0x3A383E3E, + .p0_mpwrdlctl = 0x3A383C38, +}; + +static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = { + .p0_mpwldectrl0 = 0x001E0022, + .p0_mpwldectrl1 = 0x001C0019, + .p0_mpdgctrl0 = 0x41540150, + .p0_mpdgctrl1 = 0x01440138, + .p0_mprddlctl = 0x403E4644, + .p0_mpwrdlctl = 0x3C3A4038, +}; + +/* MT41K256M16 */ +static struct mx6_ddr3_cfg neo_mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* MT41K128M16 */ +static struct mx6_ddr3_cfg neo_basic_mem_ddr = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} + +static void spl_dram_init(void) +{ + int board = get_board_value(); + + struct mx6_ddr_sysinfo sysinfo = { + .dsize = 1, /* width of data bus: 1 = 32 bits */ + .cs_density = 24, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); + if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS) + mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib, + &neo_basic_mem_ddr); + else + mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +#endif diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig new file mode 100644 index 00000000000..3304afb33c2 --- /dev/null +++ b/configs/udoo_neo_defconfig @@ -0,0 +1,30 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_TARGET_UDOO_NEO=y +CONFIG_SPL_EXT_SUPPORT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX" +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +# CONFIG_CMD_DHCP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIBFDT=y diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h new file mode 100644 index 00000000000..81e04810eb5 --- /dev/null +++ b/include/configs/udoo_neo.h @@ -0,0 +1,94 @@ +/* + * Copyright 2014-2015 Freescale Semiconductor, Inc. + * Copyright Jasbir Matharu + * Copyright 2015 UDOO Team + * + * Configuration settings for the UDOO NEO board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include "mx6_common.h" + +#include "imx6_spl.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_MXC_UART + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR + +/* Command definition */ +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC2*/ + +/* Linux only */ +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttymxc0,115200\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=undefined\0" \ + "fdt_addr=0x83000000\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcrootfstype=ext4\0" \ + "mmcautodetect=no\0" \ + "findfdt="\ + "if test $board_name = BASIC; then " \ + "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \ + "if test $board_name = BASICKS; then " \ + "setenv fdt_file imx6sx-udoo-neo-basic.dtb; fi; " \ + "if test $board_name = FULL; then " \ + "setenv fdt_file imx6sx-udoo-neo-full.dtb; fi; " \ + "if test $board_name = EXTENDED; then " \ + "setenv fdt_file imx6sx-udoo-neo-extended.dtb; fi; " \ + "if test $fdt_file = UNDEFINED; then " \ + "echo WARNING: Could not determine dtb to use; fi; \0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "ramdisk_addr_r=0x83000000\0" \ + "ramdiskaddr=0x83000000\0" \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + BOOTENV + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#define CONFIG_BOOTCOMMAND \ + "run findfdt; " \ + "run distro_bootcmd" + +#include + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* Environment organization */ +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_IS_IN_MMC + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 0405092bd21a44f5af22f17aeb0b82a0a11e1252 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 15 Nov 2016 10:38:23 -0800 Subject: arm: mx6: specify SPL padding Specify standard padding for payload to 68KB. This is derived from the maximum header size plus maximum SPL size. It matches the already defined offset for SD/eMMC devices (69KB) too. This allows to use the u-boot-with-spl.imx build target to generate a directly flashable image which can be flashed using: dd if=u-boot-with-spl.imx of=/dev/mmcblk0 bs=512 skip=2 While the patch has been created with SD/eMMC in mind, this also works with other boot media. The board file needs to configure the media specific (absolute) payload offset accordingly. Especially the IVT offset is boot media specific and can be retrieved from the reference manual (Table 8-25. Image Vector Table Offset and Initial Load Region Size). For NAND boot a define like this should do the job: #define CONFIG_SYS_NAND_U_BOOT_OFFS (SPL_PAD_TO + 0x400) Signed-off-by: Stefan Agner --- include/configs/imx6_spl.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index dce44387979..c5a035fccfa 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -29,6 +29,12 @@ #define CONFIG_SPL_TEXT_BASE 0x00908000 #define CONFIG_SPL_MAX_SIZE 0x10000 #define CONFIG_SPL_STACK 0x0091FFB8 +/* + * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the + * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a + * boot media (given that boot media specific offset is configured properly). + */ +#define CONFIG_SPL_PAD_TO 0x11000 /* NAND support */ #if defined(CONFIG_SPL_NAND_SUPPORT) -- cgit v1.3.1 From 9cd37b02a010addfbe6b2ed5b2eacd5bd7e36fb8 Mon Sep 17 00:00:00 2001 From: Angus Ainslie Date: Fri, 11 Nov 2016 11:31:39 -0700 Subject: imx7: SPI: add suport for SPI flash in mikroBUS slot Enable the escpi3 nets attached to the mikroBUS slot on the i.MX7 Sabre evalution board. Also enble the SPI flash commands to work with the "flash click" board. This is V2 of this patch with changes recommended by the maintainer CC: Jagan Teki --- board/freescale/mx7dsabresd/mx7dsabresd.c | 24 ++++++++++++++++++++++++ configs/mx7dsabresd_secure_defconfig | 3 +++ include/configs/mx7dsabresd.h | 3 +++ 3 files changed, 30 insertions(+) (limited to 'include') diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c index b9365445e85..6ccdd4b33b2 100644 --- a/board/freescale/mx7dsabresd/mx7dsabresd.c +++ b/board/freescale/mx7dsabresd/mx7dsabresd.c @@ -50,6 +50,9 @@ DECLARE_GLOBAL_DATA_PTR; #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) +#define SPI_PAD_CTRL \ + (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST) + #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) #ifdef CONFIG_SYS_I2C_MXC #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) @@ -68,6 +71,23 @@ static struct i2c_pads_info i2c_pad_info1 = { }; #endif +static iomux_v3_cfg_t const ecspi3_pads[] = { + MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1; +} + +static void setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); +} + int dram_init(void) { gd->ram_size = PHYS_SDRAM_SIZE; @@ -553,6 +573,10 @@ int board_init(void) board_qspi_init(); #endif +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + return 0; } diff --git a/configs/mx7dsabresd_secure_defconfig b/configs/mx7dsabresd_secure_defconfig index 126ce31ff73..ef935221c48 100644 --- a/configs/mx7dsabresd_secure_defconfig +++ b/configs/mx7dsabresd_secure_defconfig @@ -45,3 +45,6 @@ CONFIG_G_DNL_MANUFACTURER="FSL" CONFIG_G_DNL_VENDOR_NUM=0x0525 CONFIG_G_DNL_PRODUCT_NUM=0xa4a5 CONFIG_OF_LIBFDT=y +CONFIG_SPI_FLASH=y +CONFIG_CMD_SF=y +CONFIG_SPI_FLASH_EON=y diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 360a5e0d9c5..ca5f9db568b 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -201,6 +201,9 @@ #define CONFIG_ENV_SIZE SZ_8K #define CONFIG_ENV_IS_IN_MMC +/* MXC SPI driver support */ +#define CONFIG_MXC_SPI + /* * If want to use nand, define CONFIG_NAND_MXS and rework board * to support nand, since emmc has pin conflicts with nand -- cgit v1.3.1 From 730d25443aa894a32b9f66ebde3bfbf64b73ac7a Mon Sep 17 00:00:00 2001 From: Christoph Fritz Date: Tue, 29 Nov 2016 16:13:40 +0100 Subject: mx6sx: Add initial support for Samtec VIN|ING 2000 board This patch adds initial support for Samtec VIN|ING 2000 board. Signed-off-by: Christoph Fritz Reviewed-by: Stefano Babic Acked-by: Marek Vasut --- arch/arm/cpu/armv7/mx6/Kconfig | 7 + board/samtec/vining_2000/Kconfig | 12 + board/samtec/vining_2000/MAINTAINERS | 6 + board/samtec/vining_2000/Makefile | 6 + board/samtec/vining_2000/imximage.cfg | 132 +++++++++ board/samtec/vining_2000/vining_2000.c | 517 +++++++++++++++++++++++++++++++++ configs/vining_2000_defconfig | 31 ++ include/configs/vining_2000.h | 123 ++++++++ 8 files changed, 834 insertions(+) create mode 100644 board/samtec/vining_2000/Kconfig create mode 100644 board/samtec/vining_2000/MAINTAINERS create mode 100644 board/samtec/vining_2000/Makefile create mode 100644 board/samtec/vining_2000/imximage.cfg create mode 100644 board/samtec/vining_2000/vining_2000.c create mode 100644 configs/vining_2000_defconfig create mode 100644 include/configs/vining_2000.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index a81d9440289..8c96ba37c39 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -204,6 +204,12 @@ config TARGET_UDOO_NEO bool "UDOO Neo" select SUPPORT_SPL +config TARGET_SAMTEC_VINING_2000 + bool "samtec VIN|ING 2000" + select MX6SX + select DM + select DM_THERMAL + config TARGET_WANDBOARD bool "wandboard" select SUPPORT_SPL @@ -259,6 +265,7 @@ source "board/freescale/mx6ullevk/Kconfig" source "board/phytec/pcm058/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" +source "board/samtec/vining_2000/Kconfig" source "board/seco/Kconfig" source "board/solidrun/mx6cuboxi/Kconfig" source "board/technexion/pico-imx6ul/Kconfig" diff --git a/board/samtec/vining_2000/Kconfig b/board/samtec/vining_2000/Kconfig new file mode 100644 index 00000000000..3447c27fa4f --- /dev/null +++ b/board/samtec/vining_2000/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SAMTEC_VINING_2000 + +config SYS_BOARD + default "vining_2000" + +config SYS_VENDOR + default "samtec" + +config SYS_CONFIG_NAME + default "vining_2000" + +endif diff --git a/board/samtec/vining_2000/MAINTAINERS b/board/samtec/vining_2000/MAINTAINERS new file mode 100644 index 00000000000..027e52736fa --- /dev/null +++ b/board/samtec/vining_2000/MAINTAINERS @@ -0,0 +1,6 @@ +VINING_2000 BOARD +M: Ingo Schroeck +S: Maintained +F: board/samtec/vining_2000/ +F: include/configs/vining_2000.h +F: configs/vining_2000_defconfig diff --git a/board/samtec/vining_2000/Makefile b/board/samtec/vining_2000/Makefile new file mode 100644 index 00000000000..1b32f66aaaf --- /dev/null +++ b/board/samtec/vining_2000/Makefile @@ -0,0 +1,6 @@ +# (C) Copyright 2016 samtec automotive software & electronics gmbh +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := vining_2000.o diff --git a/board/samtec/vining_2000/imximage.cfg b/board/samtec/vining_2000/imximage.cfg new file mode 100644 index 00000000000..4133ddad2e1 --- /dev/null +++ b/board/samtec/vining_2000/imximage.cfg @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2016 samtec automotive software & electronics gmbh + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define __ASSEMBLY__ +#include + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi/sd/nand/onenand, qspi/nor + */ + +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* Enable all clocks */ +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +/* IOMUX - DDR IO Type */ +DATA 4 0x020e0618 0x000c0000 +DATA 4 0x020e05fc 0x00000000 + +/* Clock */ +DATA 4 0x020e032c 0x00000030 + +/* Address */ +DATA 4 0x020e0300 0x00000028 +DATA 4 0x020e02fc 0x00000028 +DATA 4 0x020e05f4 0x00000028 + +/* Control */ +DATA 4 0x020e0340 0x00000028 + +DATA 4 0x020e0320 0x00000000 +DATA 4 0x020e0310 0x00000028 +DATA 4 0x020e0314 0x00000028 +DATA 4 0x020e0614 0x00000028 + +/* Data Strobe */ +DATA 4 0x020e05f8 0x00020000 +DATA 4 0x020e0330 0x00000028 +DATA 4 0x020e0334 0x00000028 +DATA 4 0x020e0338 0x00000028 +DATA 4 0x020e033c 0x00000028 + +/* Data */ +DATA 4 0x020e0608 0x00020000 +DATA 4 0x020e060c 0x00000028 +DATA 4 0x020e0610 0x00000028 +DATA 4 0x020e061c 0x00000028 +DATA 4 0x020e0620 0x00000028 +DATA 4 0x020e02ec 0x00000028 +DATA 4 0x020e02f0 0x00000028 +DATA 4 0x020e02f4 0x00000028 +DATA 4 0x020e02f8 0x00000028 + +/* Calibrations - ZQ */ +DATA 4 0x021b0800 0xa1390003 + +/* Write leveling */ +DATA 4 0x021b080c 0x00290025 +DATA 4 0x021b0810 0x00210022 + +/* DQS Read Gate */ +DATA 4 0x021b083c 0x4142013a +DATA 4 0x021b0840 0x012e0123 + +/* Read/Write Delay */ +DATA 4 0x021b0848 0x43474949 +DATA 4 0x021b0850 0x38383c38 + +/* Read data bit delay */ +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 + +/* Complete calibration by forced measurement */ +DATA 4 0x021b08b8 0x00000800 + +/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */ +DATA 4 0x021b0004 0x0002002d +DATA 4 0x021b0008 0x00333040 +DATA 4 0x021b000c 0x676b52f2 +DATA 4 0x021b0010 0x926e8b63 +DATA 4 0x021b0014 0x01ff00db +DATA 4 0x021b0018 0x00011740 +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x000026d2 +DATA 4 0x021b0030 0x006b1023 +DATA 4 0x021b0040 0x0000005f +DATA 4 0x021b0000 0x84190000 + +/* Initialize MT41K256M16HA-125 - MR2 */ +DATA 4 0x021b001c 0x02008032 +/* MR3 */ +DATA 4 0x021b001c 0x00008033 +/* MR1 */ +DATA 4 0x021b001c 0x00048031 +/* MR0 */ +DATA 4 0x021b001c 0x15108030 +/* DDR device ZQ calibration */ +DATA 4 0x021b001c 0x04008040 + +/* Final DDR setup, before operation start */ +DATA 4 0x021b0020 0x00007800 +DATA 4 0x021b0818 0x00022227 +DATA 4 0x021b001c 0x00000000 diff --git a/board/samtec/vining_2000/vining_2000.c b/board/samtec/vining_2000/vining_2000.c new file mode 100644 index 00000000000..c92f37c9bb5 --- /dev/null +++ b/board/samtec/vining_2000/vining_2000.c @@ -0,0 +1,517 @@ +/* + * Copyright (C) 2016 samtec automotive software & electronics gmbh + * + * Author: Christoph Fritz + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \ + PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \ + PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL PAD_CTL_DSE_34ohm + +#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \ + PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm) + +#define USDHC_CLK_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST) + +#define USDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ + PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST) + +#define GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_PKE) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL), + MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_LCD1_VSYNC__GPIO3_IO_28 | MUX_PAD_CTRL(GPIO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_CLK_PAD_CTRL), + MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA4__USDHC4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA5__USDHC4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA6__USDHC4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const fec1_pads[] = { + MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL) | + MUX_MODE_SION, + /* LAN8720 PHY Reset */ + MX6_PAD_RGMII1_TD3__GPIO5_IO_9 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const pwm_led_pads[] = { + MX6_PAD_RGMII2_RD2__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* green */ + MX6_PAD_RGMII2_TD2__PWM6_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* red */ + MX6_PAD_RGMII2_RD3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), /* blue */ +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#define PHY_RESET IMX_GPIO_NR(5, 9) + +int board_eth_init(bd_t *bis) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + unsigned char eth1addr[6]; + + /* just to get secound mac address */ + imx_get_mac_from_fuse(1, eth1addr); + if (!getenv("eth1addr") && is_valid_ethaddr(eth1addr)) + eth_setenv_enetaddr("eth1addr", eth1addr); + + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); + + /* + * Generate phy reference clock via pin IOMUX ENET_REF_CLK1/2 by erasing + * ENET1/2_TX_CLK_DIR gpr1[14:13], so that reference clock is driven by + * ref_enetpll0/1 and enable ENET1/2_TX_CLK output driver. + */ + clrsetbits_le32(&iomuxc_regs->gpr[1], + IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK | + IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK, + IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK | + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(0, ENET_50MHZ); + if (ret) + goto eth_fail; + + /* reset phy */ + gpio_direction_output(PHY_RESET, 0); + mdelay(16); + gpio_set_value(PHY_RESET, 1); + mdelay(1); + + ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR, + IMX_FEC_BASE); + if (ret) + goto eth_fail; + + return ret; + +eth_fail: + printf("FEC MXC: %s:failed (%i)\n", __func__, ret); + gpio_set_value(PHY_RESET, 0); + return ret; +} + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO00__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO00__GPIO1_IO_0 | PC, + .gp = IMX_GPIO_NR(1, 0), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO01__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO01__GPIO1_IO_1 | PC, + .gp = IMX_GPIO_NR(1, 1), + }, +}; + +static struct pmic *pfuze_init(unsigned char i2cbus) +{ + struct pmic *p; + int ret; + u32 reg; + + ret = power_pfuze100_init(i2cbus); + if (ret) + return NULL; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return NULL; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Set SW1AB stanby volage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); + + /* Set SW1C standby voltage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); + + /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE100_SW1CCONF, ®); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(p, PFUZE100_SW1CCONF, reg); + + return p; +} + +static int pfuze_mode_init(struct pmic *p, u32 mode) +{ + unsigned char offset, i, switch_num; + u32 id; + int ret; + + pmic_reg_read(p, PFUZE100_DEVICEID, &id); + id = id & 0xf; + + if (id == 0) { + switch_num = 6; + offset = PFUZE100_SW1CMODE; + } else if (id == 1) { + switch_num = 4; + offset = PFUZE100_SW2MODE; + } else { + printf("Not supported, id=%d\n", id); + return -EINVAL; + } + + ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode); + if (ret < 0) { + printf("Set SW1AB mode error!\n"); + return ret; + } + + for (i = 0; i < switch_num - 1; i++) { + ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode); + if (ret < 0) { + printf("Set switch 0x%x mode error!\n", + offset + i * SWITCH_SIZE); + return ret; + } + } + + return ret; +} + +int power_init_board(void) +{ + struct pmic *p; + int ret; + + p = pfuze_init(I2C_PMIC); + if (!p) + return -ENODEV; + + ret = pfuze_mode_init(p, APS_PFM); + if (ret < 0) + return ret; + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX6 +static iomux_v3_cfg_t const usb_otg_pads[] = { + /* OGT1 */ + MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + /* OTG2 */ + MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL) +}; + +static void setup_iomux_usb(void) +{ + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); +} + +int board_usb_phy_mode(int port) +{ + if (port == 1) + return USB_INIT_HOST; + else + return usb_phy_mode(port); +} +#endif + +#ifdef CONFIG_PWM_IMX +static int set_pwm_leds(void) +{ + int ret; + + imx_iomux_v3_setup_multiple_pads(pwm_led_pads, + ARRAY_SIZE(pwm_led_pads)); + /* enable backlight PWM 2, green LED */ + ret = pwm_init(1, 0, 0); + if (ret) + goto error; + /* duty cycle 200ns, period: 8000ns */ + ret = pwm_config(1, 200, 8000); + if (ret) + goto error; + ret = pwm_enable(1); + if (ret) + goto error; + + /* enable backlight PWM 1, blue LED */ + ret = pwm_init(0, 0, 0); + if (ret) + goto error; + /* duty cycle 200ns, period: 8000ns */ + ret = pwm_config(0, 200, 8000); + if (ret) + goto error; + ret = pwm_enable(0); + if (ret) + goto error; + + /* enable backlight PWM 6, red LED */ + ret = pwm_init(5, 0, 0); + if (ret) + goto error; + /* duty cycle 200ns, period: 8000ns */ + ret = pwm_config(5, 200, 8000); + if (ret) + goto error; + ret = pwm_enable(5); + +error: + return ret; +} +#else +static int set_pwm_leds(void) +{ + return 0; +} +#endif + +#define ADCx_HC0 0x00 +#define ADCx_HS 0x08 +#define ADCx_HS_C0 BIT(0) +#define ADCx_R0 0x0c +#define ADCx_CFG 0x14 +#define ADCx_CFG_SWMODE 0x308 +#define ADCx_GC 0x18 +#define ADCx_GC_CAL BIT(7) + +static int read_adc(u32 *val) +{ + int ret; + void __iomem *b = map_physmem(ADC1_BASE_ADDR, 0x100, MAP_NOCACHE); + + /* use software mode */ + writel(ADCx_CFG_SWMODE, b + ADCx_CFG); + + /* start auto calibration */ + setbits_le32(b + ADCx_GC, ADCx_GC_CAL); + ret = wait_for_bit("ADC", b + ADCx_GC, ADCx_GC_CAL, ADCx_GC_CAL, 10, 0); + if (ret) + goto adc_exit; + + /* start conversion */ + writel(0, b + ADCx_HC0); + + /* wait for conversion */ + ret = wait_for_bit("ADC", b + ADCx_HS, ADCx_HS_C0, ADCx_HS_C0, 10, 0); + if (ret) + goto adc_exit; + + /* read result */ + *val = readl(b + ADCx_R0); + +adc_exit: + if (ret) + printf("ADC failure (ret=%i)\n", ret); + unmap_physmem(b, MAP_NOCACHE); + return ret; +} + +#define VAL_UPPER 2498 +#define VAL_LOWER 1550 + +static int set_pin_state(void) +{ + u32 val; + int ret; + + ret = read_adc(&val); + if (ret) + return ret; + + if (val >= VAL_UPPER) + setenv("pin_state", "connected"); + else if (val < VAL_UPPER && val > VAL_LOWER) + setenv("pin_state", "open"); + else + setenv("pin_state", "button"); + + return ret; +} + +int board_late_init(void) +{ + int ret; + + ret = set_pwm_leds(); + if (ret) + return ret; + + ret = set_pin_state(); + + return ret; +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + setup_iomux_usb(); + + return 0; +} + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC4_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(3, 28) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == USDHC4_BASE_ADDR) + return 1; + if (cfg->esdhc_base == USDHC2_BASE_ADDR) + return !gpio_get_value(USDHC2_CD_GPIO); + + return -EINVAL; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC4 + * mmc1 USDHC2 + */ + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); + if (ret) { + printf("Warning: failed to initialize USDHC4\n"); + return ret; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[1]); + if (ret) { + printf("Warning: failed to initialize USDHC2\n"); + return ret; + } + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); +#endif + + return 0; +} + +int checkboard(void) +{ + puts("Board: VIN|ING 2000\n"); + + return 0; +} diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig new file mode 100644 index 00000000000..b1f64f1c0f4 --- /dev/null +++ b/configs/vining_2000_defconfig @@ -0,0 +1,31 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_SAMTEC_VINING_2000=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/samtec/vining_2000/imximage.cfg" +CONFIG_BOOTDELAY=0 +CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_PCI=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y +CONFIG_OF_LIBFDT=y +CONFIG_MXC_USB_OTG_HACTIVE=y diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h new file mode 100644 index 00000000000..235574d55dc --- /dev/null +++ b/include/configs/vining_2000.h @@ -0,0 +1,123 @@ +/* + * Copyright (C) 2016 samtec automotive software & electronics gmbh + * + * Configuration settings for the Samtec VIN|ING 2000 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "mx6_common.h" + +#ifdef CONFIG_SPL +#include "imx6_spl.h" +#endif + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) +#include + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) + +#define CONFIG_STACKSIZE SZ_128K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* MMC Configuration */ +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR + +/* I2C Configs */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + +/* Network */ +#define CONFIG_FEC_MXC +#define CONFIG_MII + +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_MXC_PHYADDR 0x0 + +#define CONFIG_FEC_XCV_TYPE RMII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#endif + +#define CONFIG_CMD_PCI +#ifdef CONFIG_CMD_PCI +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_PCIE_IMX +#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) +#endif + +#define CONFIG_IMX_THERMAL + +#define CONFIG_PWM_IMX +#define CONFIG_IMX6_PWM_PER_CLK 66000000 +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_ENV_OFFSET (8 * SZ_64K) +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_OFFSET_REDUND (9 * SZ_64K) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE +#define CONFIG_ENV_IS_IN_MMC + +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_EFI_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC4 eMMC */ +/* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */ +#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */ +#endif + +#endif /* __CONFIG_H */ -- cgit v1.3.1