From 69c6d268a29cf6d61e096d815abf5abf24136f45 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Fri, 10 Jul 2009 18:37:15 +0000 Subject: Blackfin: use +(filesize) to make sure we are only doing what is necessary Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- include/configs/bfin_adi_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 1ca2e514205..ceb130c813d 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -160,8 +160,8 @@ "nand write $(loadaddr) 0 0x40000" # else # define UBOOT_ENV_UPDATE \ - "protect off 0x20000000 0x2003FFFF;" \ - "erase 0x20000000 0x2003FFFF;" \ + "protect off 0x20000000 +$(filesize);" \ + "erase 0x20000000 +$(filesize);" \ "cp.b $(loadaddr) 0x20000000 $(filesize)" # endif # define NETWORK_ENV_SETTINGS \ -- cgit v1.2.3 From aa7b248a05323d4720969227603e39a22777ed95 Mon Sep 17 00:00:00 2001 From: Michael Hennerich Date: Thu, 18 Jun 2009 09:12:50 +0000 Subject: Blackfin: bf537-stamp: comment CF-Flash Card Support better Signed-off-by: Michael Hennerich Signed-off-by: Mike Frysinger --- include/configs/bf537-stamp.h | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 98300db7b52..74b9ecd0b0a 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -178,9 +178,28 @@ /* * CF-CARD IDE-HDD Support */ -/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */ -/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */ -/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */ + +/* + * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card) + * Strange address mapping Blackfin A13 connects to CF_A0 + */ + +/* #define CONFIG_BFIN_TRUE_IDE */ + +/* + * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card) + * This should be the preferred mode + */ + +/* #define CONFIG_BFIN_CF_IDE */ + +/* + * Add IDE Disk Drive (HDD) support + * See example interface here: + * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin + */ + +/* #define CONFIG_BFIN_HDD_IDE */ #if defined(CONFIG_BFIN_CF_IDE) || \ defined(CONFIG_BFIN_HDD_IDE) || \ @@ -218,7 +237,7 @@ #define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ #define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */ +#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */ #elif defined(CONFIG_BFIN_CF_IDE) #define CONFIG_SYS_ATA_BASE_ADDR 0x20211800 @@ -226,7 +245,7 @@ #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */ #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */ #define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */ +#define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */ #elif defined(CONFIG_BFIN_HDD_IDE) #define CONFIG_SYS_ATA_BASE_ADDR 0x20314000 -- cgit v1.2.3 From 574b70df03fba0ea635e2fe71fbd7b97d19b706a Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Tue, 11 Aug 2009 14:20:13 +0000 Subject: Blackfin: enable more network commands for ADI dev boards Add dns and ntp to default networking commands, and ask for more dhcp options to better configure the network environment. Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- include/configs/bfin_adi_common.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index ceb130c813d..b615c79c846 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -12,6 +12,13 @@ # include # if ADI_CMDS_NETWORK # define CONFIG_CMD_DHCP +# define CONFIG_BOOTP_SUBNETMASK +# define CONFIG_BOOTP_GATEWAY +# define CONFIG_BOOTP_DNS +# define CONFIG_BOOTP_NTPSERVER +# define CONFIG_BOOTP_RANDOM_DELAY +# define CONFIG_KEEP_SERVERADDR +# define CONFIG_CMD_DNS # define CONFIG_CMD_PING # ifdef CONFIG_BFIN_MAC # define CONFIG_CMD_MII @@ -46,6 +53,9 @@ # endif # ifdef CONFIG_RTC_BFIN # define CONFIG_CMD_DATE +# if ADI_CMDS_NETWORK +# define CONFIG_CMD_SNTP +# endif # endif # ifdef CONFIG_SPI # define CONFIG_CMD_EEPROM -- cgit v1.2.3 From c4db335c2e0805e1ce4c33d278b77492c0812353 Mon Sep 17 00:00:00 2001 From: Robin Getz Date: Mon, 17 Aug 2009 15:23:02 +0000 Subject: Blackfin: change global data register from P5 to P3 Since the Blackfin ABI favors higher scratch registers by default, use the last scratch register (P3) for global data rather than the first (P5). This allows the compiler's register allocator to use higher number scratch P registers, which in turn better matches the Blackfin instruction set, which reduces the size of U-Boot by more than 1024 bytes... Signed-off-by: Robin Getz Signed-off-by: Mike Frysinger --- include/asm-blackfin/global_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h index 5c9903bb150..3194b72a537 100644 --- a/include/asm-blackfin/global_data.h +++ b/include/asm-blackfin/global_data.h @@ -66,6 +66,6 @@ typedef struct global_data { #define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */ #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ -#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P5") +#define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P3") #endif -- cgit v1.2.3 From 4640c2b8699bcdd2346a2c633486f07f061a2939 Mon Sep 17 00:00:00 2001 From: Harald Krapfenbauer Date: Thu, 20 Aug 2009 19:20:41 -0400 Subject: Blackfin: cm-bf537u: new board port The CM-BF537U is similar to the CM-BF537E module, but enough to need its own board port. Signed-off-by: Harald Krapfenbauer Signed-off-by: Mike Frysinger --- include/configs/cm-bf537u.h | 150 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 150 insertions(+) create mode 100644 include/configs/cm-bf537u.h (limited to 'include') diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h new file mode 100644 index 00000000000..d1870a8963f --- /dev/null +++ b/include/configs/cm-bf537u.h @@ -0,0 +1,150 @@ +/* + * U-boot - Configuration file for CM-BF537U board + */ + +#ifndef __CONFIG_CM_BF537U_H__ +#define __CONFIG_CM_BF537U_H__ + +#include + + +/* + * Processor Settings + */ +#define CONFIG_BFIN_CPU bf537-0.2 +#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS + + +/* + * Clock Settings + * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV + * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV + */ +/* CONFIG_CLKIN_HZ is any value in Hz */ +#define CONFIG_CLKIN_HZ 30000000 +/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ +/* 1 = CLKIN / 2 */ +#define CONFIG_CLKIN_HALF 0 +/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ +/* 1 = bypass PLL */ +#define CONFIG_PLL_BYPASS 0 +/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ +/* Values can range from 0-63 (where 0 means 64) */ +#define CONFIG_VCO_MULT 18 +/* CCLK_DIV controls the core clock divider */ +/* Values can be 1, 2, 4, or 8 ONLY */ +#define CONFIG_CCLK_DIV 1 +/* SCLK_DIV controls the system clock divider */ +/* Values can range from 1-15 */ +#define CONFIG_SCLK_DIV 5 +/* Core voltage */ +#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000) + + +/* + * Memory Settings + */ +#define CONFIG_MEM_ADD_WDTH 9 +#define CONFIG_MEM_SIZE 32 + +#define CONFIG_EBIU_SDRRC_VAL 0x3f8 +#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd + +#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL) +#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3) +#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3) + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024) + + +/* + * Network Settings + */ +#ifndef __ADSPBF534__ +#define ADI_CMDS_NETWORK 1 +#define CONFIG_NET_MULTI +/* The next 3 lines are for use with SMSC on EXT-BF5xx-USB-ETH2 */ +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_BASE 0x24000000 +#define CONFIG_SMC911X_16_BIT +#endif +#define CONFIG_HOSTNAME cm-bf537u +/* Uncomment next line to use fixed MAC address */ +/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */ + + +/* + * Flash Settings + */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_SYS_FLASH_BASE 0x20000000 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 35 + + +/* + * Env Storage Settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) +#define ENV_IS_EMBEDDED +#else +#define ENV_IS_EMBEDDED_CUSTOM +#endif +#ifdef ENV_IS_EMBEDDED +/* WARNING - the following is hand-optimized to fit within + * the sector before the environment sector. If it throws + * an error during compilation remove an object here to get + * it linked after the configuration sector. + */ +# define LDS_BOARD_TEXT \ + cpu/blackfin/traps.o (.text .text.*); \ + cpu/blackfin/interrupt.o (.text .text.*); \ + cpu/blackfin/serial.o (.text .text.*); \ + common/dlmalloc.o (.text .text.*); \ + lib_generic/crc32.o (.text .text.*); \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text .text.*); +#endif + + +/* + * I2C Settings + */ +#define CONFIG_BFIN_TWI_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 + + +/* + * Misc Settings + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_MISC_INIT_R +#define CONFIG_RTC_BFIN +#define CONFIG_UART_CONSOLE 0 + + +/* + * Pull in common ADI header for remaining command/environment setup + */ +#include + +#undef CONFIG_BOOTCOMMAND +#define CONFIG_BOOTCOMMAND "run flashboot" + +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + NAND_ENV_SETTINGS \ + NETWORK_ENV_SETTINGS \ + "flashboot=flread 20040000 1000000 280000; bootm 0x1000000\0" + +#endif -- cgit v1.2.3 From 69a25ce3578f34c8accb476f70089f3a44b78ed9 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 24 Aug 2009 20:36:25 -0400 Subject: Blackfin: increase default console size The default console size indirectly applies to length of env vars, so a smaller length makes it hard to pass longer command lines to kernels. Signed-off-by: Mike Frysinger --- include/asm-blackfin/config.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'include') diff --git a/include/asm-blackfin/config.h b/include/asm-blackfin/config.h index 6623fb7ae10..5739b1377c0 100644 --- a/include/asm-blackfin/config.h +++ b/include/asm-blackfin/config.h @@ -120,11 +120,7 @@ # define CONFIG_SYS_PROMPT "bfin> " #endif #ifndef CONFIG_SYS_CBSIZE -# ifdef CONFIG_CMD_KGDB -# define CONFIG_SYS_CBSIZE 1024 -# else -# define CONFIG_SYS_CBSIZE 256 -# endif +# define CONFIG_SYS_CBSIZE 1024 #endif #ifndef CONFIG_SYS_BARGSIZE # define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -- cgit v1.2.3 From 9c46e71af2b03ccd721c56b1dc906ead702d6fb5 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Mon, 24 Aug 2009 20:48:04 -0400 Subject: Blackfin: use scratch pad for exception stack If the memory layout pushes the stack out of the default DCPLB coverage, the exception handler may trigger a double fault by trying to push onto the uncovered stack. So handle the exception stack similar to the kernel by using the top of the scratch pad SRAM. Signed-off-by: Mike Frysinger --- include/asm-blackfin/config.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/asm-blackfin/config.h b/include/asm-blackfin/config.h index 5739b1377c0..25794dd4bf0 100644 --- a/include/asm-blackfin/config.h +++ b/include/asm-blackfin/config.h @@ -14,6 +14,10 @@ # error CONFIG_BFIN_CPU: your board config needs to define this #endif +#ifndef CONFIG_BFIN_SCRATCH_REG +# define CONFIG_BFIN_SCRATCH_REG retn +#endif + /* Make sure the structure is properly aligned */ #if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR) # error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned -- cgit v1.2.3 From c7bcdde46a7ef78628f0f09fdc6cb61bb1bd7e79 Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Wed, 2 Sep 2009 04:21:16 -0400 Subject: Blackfin: enable 64bit printf for nand Since the NAND code now uses 64bit code, make sure we enable support for ADI Blackfin boards in printf to avoid the warning: nand_util.c:45:2: warning: #warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output! Signed-off-by: Mike Frysinger --- include/configs/bfin_adi_common.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index b615c79c846..00bfc6e90bc 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -87,6 +87,9 @@ # define CONFIG_CMD_SPIBOOTLDR # endif #endif +#ifdef CONFIG_CMD_NAND +# define CONFIG_SYS_64BIT_VSPRINTF +#endif /* * Console Settings -- cgit v1.2.3 From 5e93bd1c9aaea886c5e5c7c1b6114ab36c30668f Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 21 Aug 2009 23:05:19 -0500 Subject: Consolidate arch-specific sbrk() implementations Signed-off-by: Peter Tyser --- include/malloc.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/malloc.h b/include/malloc.h index a38464e6291..0382169b6a0 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -937,6 +937,12 @@ int mALLOPt(); struct mallinfo mALLINFo(); #endif +/* + * Begin and End of memory area for malloc(), and current "brk" + */ +extern ulong mem_malloc_start; +extern ulong mem_malloc_end; +extern ulong mem_malloc_brk; #ifdef __cplusplus }; /* end of extern "C" */ -- cgit v1.2.3 From d4e8ada0f6d51e0e3b80790fb9375ac8910f5352 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 21 Aug 2009 23:05:21 -0500 Subject: Consolidate arch-specific mem_malloc_init() implementations Signed-off-by: Peter Tyser --- include/malloc.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/malloc.h b/include/malloc.h index 0382169b6a0..3e145ad11c3 100644 --- a/include/malloc.h +++ b/include/malloc.h @@ -944,6 +944,8 @@ extern ulong mem_malloc_start; extern ulong mem_malloc_end; extern ulong mem_malloc_brk; +void mem_malloc_init(ulong start, ulong size); + #ifdef __cplusplus }; /* end of extern "C" */ #endif -- cgit v1.2.3 From a3ab8caee696a1d53fc82fa321e2b2f179970168 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:45 +1000 Subject: i386: Add errno.h Signed-off-by: Graeme Russ --- include/asm-i386/errno.h | 1 + 1 file changed, 1 insertion(+) create mode 100644 include/asm-i386/errno.h (limited to 'include') diff --git a/include/asm-i386/errno.h b/include/asm-i386/errno.h new file mode 100644 index 00000000000..4c82b503d92 --- /dev/null +++ b/include/asm-i386/errno.h @@ -0,0 +1 @@ +#include -- cgit v1.2.3 From f3a8d6b29b1cd01fdd940e8ff7a62b1df0ebbf82 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:48 +1000 Subject: Fix environment configuration for eNET board The current configuration of the Environment has the redundant copy of the environment in the Boot Flash - This was never the intent. The Environment should instead be in the first two sectors of the first Strata Flash Signed-off-by: Graeme Russ --- include/configs/eNET.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/configs/eNET.h b/include/configs/eNET.h index dde4c832130..43567142323 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -188,14 +188,13 @@ * Environment configuration */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x20000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */ #define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE_1 + \ - CONFIG_ENV_OFFSET) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1 +/* Redundant Copy */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \ CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE /*----------------------------------------------------------------------- -- cgit v1.2.3 From d7549024098af093785151261266a02be19af633 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:50 +1000 Subject: i386: Misc PCI fixups Change PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY (Originally done in commit ff4e66e93c1a, regressed by commit 6d7f610b09f8) Cast PCI_ROM_ADDRESS_MASK to u32 Wrap probe_pci_video() call inside #ifdef CONFIG_VIDEO Change call to pci_find_class() to pci_find_devices(). This is based on a patch submitted on 1st March 2007 (Patch that fixes the compilation errors for sc520_cdp board) by mushtaq_k This patch requires that PCI_VIDEO_VENDOR_ID and PCI_VIDEO_DEVICE_ID be specified in the board config file. Dummy values have been added for the SC520 CDP board to enable compilation, but since I do not have one of these, I do know what the values should be Signed-off-by: Graeme Russ --- include/configs/sc520_cdp.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index 3e2bb02a462..36e1224e57a 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -206,6 +206,8 @@ ************************************************************/ #ifndef GRUSS_TESTING #define CONFIG_VIDEO /* To enable video controller support */ +#define PCI_VIDEO_VENDOR_ID 0 /*Use the appropriate vendor ID*/ +#define PCI_VIDEO_DEVICE_ID 0 /*Use the appropriate Device ID*/ #else #undef CONFIG_VIDEO #endif -- cgit v1.2.3 From 8907b8dbc5805094f1316d64737d3428b3863693 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:53 +1000 Subject: Misc ds1722 fixups This patch is based on a patch submitted by Jean-Christophe PLAGNIOL-VILLARD on 18th May 2008 as part of a general i386 / sc520 fixup which was never applied Signed-off-by: Graeme Russ --- include/ds1722.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 include/ds1722.h (limited to 'include') diff --git a/include/ds1722.h b/include/ds1722.h new file mode 100644 index 00000000000..44f0830c0b7 --- /dev/null +++ b/include/ds1722.h @@ -0,0 +1,32 @@ +/* + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _DS1722_H_ +#define _DS1722_H_ + +#define DS1722_RESOLUTION_8BIT 0x0 +#define DS1722_RESOLUTION_9BIT 0x1 +#define DS1722_RESOLUTION_10BIT 0x2 +#define DS1722_RESOLUTION_11BIT 0x3 +#define DS1722_RESOLUTION_12BIT 0x4 + +int ds1722_probe(int dev); + +#endif /* _DS1722_H_ */ -- cgit v1.2.3 From 91ee4e183cb7ac5f86e7673ead51400f19906635 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:54 +1000 Subject: Fixup sc520_spunk board Primary intent is to resolve build errors for this board which has been neglected for a very long time. I do not have one of these boards, so I cannot test functionality Signed-off-by: Graeme Russ --- include/configs/sc520_spunk.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h index d42ef842167..f3fc9602ada 100644 --- a/include/configs/sc520_spunk.h +++ b/include/configs/sc520_spunk.h @@ -37,6 +37,7 @@ #define CONFIG_X86 1 /* This is a X86 CPU */ #define CONFIG_SYS_SC520 1 /* Include support for AMD SC520 */ +#define CONFIG_SYS_SC520_SSI #define CONFIG_SYS_SDRAM_PRECHARGE_DELAY 6 /* 6T */ #define CONFIG_SYS_SDRAM_REFRESH_RATE 78 /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */ @@ -218,6 +219,7 @@ #define CONFIG_SYS_PCMCIA_CIS_WIN_SIZE 0x00100000 #define CONFIG_SYS_PCMCIA_IO_WIN 0xe000 #define CONFIG_SYS_PCMCIA_IO_WIN_SIZE 16 +#define CONFIG_PCMCIA_SLOT_A /* TODO: Check this */ /************************************************************ * DISK Partition support -- cgit v1.2.3 From 9b32f96b5b92ba13fdb4b5eb637734752235f260 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:55 +1000 Subject: Misc sc520 cdp fixups Now that the PCI, SATA et al compile problems have been resolved, the cludge that was applied to avoid them can be removed Signed-off-by: Graeme Russ --- include/configs/sc520_cdp.h | 22 ---------------------- 1 file changed, 22 deletions(-) (limited to 'include') diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index 36e1224e57a..214a9af356e 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -30,7 +30,6 @@ #define CONFIG_SKIP_RELOCATE_UBOOT -#define GRUSS_TESTING /* * High Level Configuration Options * (easy to change) @@ -85,11 +84,7 @@ #include #define CONFIG_CMD_PCI -#ifndef GRUSS_TESTING #define CONFIG_CMD_SATA -#else -#undef CONFIG_CMD_SATA -#endif #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NET #define CONFIG_CMD_EEPROM @@ -181,17 +176,10 @@ /************************************************************ *SATA/Native Stuff ************************************************************/ -#ifndef GRUSS_TESTING #define CONFIG_SYS_SATA_MAXBUS 2 /*Max Sata buses supported */ #define CONFIG_SYS_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */ #define CONFIG_SYS_SATA_MAX_DEVICE (CONFIG_SYS_SATA_MAXBUS* CONFIG_SYS_SATA_DEVS_PER_BUS) #define CONFIG_ATA_PIIX 1 /*Supports ata_piix driver */ -#else -#undef CONFIG_SYS_SATA_MAXBUS -#undef CONFIG_SYS_SATA_DEVS_PER_BUS -#undef CONFIG_SYS_SATA_MAX_DEVICE -#undef CONFIG_ATA_PIIX -#endif /************************************************************ @@ -204,13 +192,9 @@ /************************************************************ * Video/Keyboard support ************************************************************/ -#ifndef GRUSS_TESTING #define CONFIG_VIDEO /* To enable video controller support */ #define PCI_VIDEO_VENDOR_ID 0 /*Use the appropriate vendor ID*/ #define PCI_VIDEO_DEVICE_ID 0 /*Use the appropriate Device ID*/ -#else -#undef CONFIG_VIDEO -#endif #define CONFIG_I8042_KBD #define CONFIG_SYS_ISA_IO 0 @@ -223,7 +207,6 @@ /* * PCI stuff */ -#ifndef GRUSS_TESTING #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_PNP /* pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW @@ -232,11 +215,6 @@ #define CONFIG_SYS_SECOND_PCI_IRQ 9 #define CONFIG_SYS_THIRD_PCI_IRQ 11 #define CONFIG_SYS_FORTH_PCI_IRQ 15 -#else -#undef CONFIG_PCI -#undef CONFIG_PCI_PNP -#undef CONFIG_PCI_SCAN_SHOW -#endif #endif /* __CONFIG_H */ -- cgit v1.2.3 From ed7a1b681de1e31d18d5b92e2767ae8df3241687 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:56 +1000 Subject: i386: Replace [read, write]_mmcr_[byte, word, long] with memory mapped structure Signed-off-by: Graeme Russ --- include/asm-i386/ic/sc520.h | 417 +++++++++++++++++++++++++------------------- 1 file changed, 234 insertions(+), 183 deletions(-) (limited to 'include') diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h index bf395166512..57c99044224 100644 --- a/include/asm-i386/ic/sc520.h +++ b/include/asm-i386/ic/sc520.h @@ -24,179 +24,243 @@ #ifndef _ASM_IC_SC520_H_ #define _ASM_IC_SC520_H_ 1 -/* Memory mapped configuration registers, MMCR */ -#define SC520_REVID 0x0000 /* ElanSC520 Microcontroller Revision ID Register */ -#define SC520_CPUCTL 0x0002 /* Am5x86 CPU Control Register */ -#define SC520_DRCCTL 0x0010 /* SDRAM Control Register */ -#define SC520_DRCTMCTL 0x0012 /* SDRAM Timing Control Register */ -#define SC520_DRCCFG 0x0014 /* SDRAM Bank Configuration Register*/ -#define SC520_DRCBENDADR 0x0018 /* SDRAM Bank 0-3 Ending Address Register*/ -#define SC520_ECCCTL 0x0020 /* ECC Control Register */ -#define SC520_ECCSTA 0x0021 /* ECC Status Register */ -#define SC520_ECCCKBPOS 0x0022 /* ECC Check Bit Position Register */ -#define SC520_ECCSBADD 0x0024 /* ECC Single-Bit Error Address Register */ +#ifndef __ASSEMBLY__ + +void init_sc520(void); +unsigned long init_sc520_dram(void); + +/* Memory mapped configuration registers */ +typedef struct sc520_mmcr { + u16 revid; /* ElanSC520 microcontroller revision id */ + u8 cpuctl; /* am5x86 CPU control */ + + u8 pad_0x003[0x0d]; + + u8 drcctl; /* SDRAM control */ + u8 pad_0x011[0x01]; + u8 drctmctl; /* SDRAM timing control */ + u8 pad_0x013[0x01]; + u16 drccfg; /* SDRAM bank configuration*/ + u8 pad_0x016[0x02]; + u32 drcbendadr; /* SDRAM bank 0-3 ending address*/ + u8 pad_0x01c[0x04]; + u8 eccctl; /* ECC control */ + u8 eccsta; /* ECC status */ + u8 eccckbpos; /* ECC check bit position */ + u8 ecccktest; /* ECC Check Code Test */ + u32 eccsbadd; /* ECC single-bit error address */ + u32 eccmbadd; /* ECC multi-bit error address */ + + u8 pad_0x02c[0x14]; + + u8 dbctl; /* SDRAM buffer control */ + + u8 pad_0x041[0x0f]; + + u16 bootcsctl; /* /BOOTCS control */ + u8 pad_0x052[0x02]; + u16 romcs1ctl; /* /ROMCS1 control */ + u16 romcs2ctl; /* /ROMCS2 control */ + + u8 pad_0x058[0x08]; + + u16 hbctl; /* host bridge control */ + u16 hbtgtirqctl; /* host bridge target interrupt control */ + u16 hbtgtirqsta; /* host bridge target interrupt status */ + u16 hbmstirqctl; /* host bridge target interrupt control */ + u16 hbmstirqsta; /* host bridge master interrupt status */ + u8 pad_0x06a[0x02]; + u32 mstintadd; /* host bridge master interrupt address */ + + u8 sysarbctl; /* system arbiter control */ + u8 pciarbsta; /* PCI bus arbiter status */ + u16 sysarbmenb; /* system arbiter master enable */ + u32 arbprictl; /* arbiter priority control */ + + u8 pad_0x078[0x08]; + + u8 adddecctl; /* address decode control */ + u8 pad_0x081[0x01]; + u16 wpvsta; /* write-protect violation status */ + u8 pad_0x084[0x04]; + u32 par[16]; /* programmable address regions */ + + u8 pad_0x0c8[0x0b38]; + + u8 gpecho; /* GP echo mode */ + u8 gpcsdw; /* GP chip select data width */ + u16 gpcsqual; /* GP chip select qualification */ + u8 pad_0xc04[0x4]; + u8 gpcsrt; /* GP chip select recovery time */ + u8 gpcspw; /* GP chip select pulse width */ + u8 gpcsoff; /* GP chip select offset */ + u8 gprdw; /* GP read pulse width */ + u8 gprdoff; /* GP read offset */ + u8 gpwrw; /* GP write pulse width */ + u8 gpwroff; /* GP write offset */ + u8 gpalew; /* GP ale pulse width */ + u8 gpaleoff; /* GP ale offset */ + + u8 pad_0xc11[0x0f]; + + u16 piopfs15_0; /* PIO15-PIO0 pin function select */ + u16 piopfs31_16; /* PIO31-PIO16 pin function select */ + u8 cspfs; /* chip select pin function select */ + u8 pad_0xc25[0x01]; + u8 clksel; /* clock select */ + u8 pad_0xc27[0x01]; + u16 dsctl; /* drive strength control */ + u16 piodir15_0; /* PIO15-PIO0 direction */ + u16 piodir31_16; /* PIO31-PIO16 direction */ + u8 pad_0xc2e[0x02]; + u16 piodata15_0 ; /* PIO15-PIO0 data */ + u16 piodata31_16; /* PIO31-PIO16 data */ + u16 pioset15_0; /* PIO15-PIO0 set */ + u16 pioset31_16; /* PIO31-PIO16 set */ + u16 pioclr15_0; /* PIO15-PIO0 clear */ + u16 pioclr31_16; /* PIO31-PIO16 clear */ + + u8 pad_0xc3c[0x24]; + + u16 swtmrmilli; /* software timer millisecond count */ + u16 swtmrmicro; /* software timer microsecond count */ + u8 swtmrcfg; /* software timer configuration */ + + u8 pad_0xc65[0x0b]; + + u8 gptmrsta; /* GP timers status register */ + u8 pad_0xc71; + u16 gptmr0ctl; /* GP timer 0 mode/control */ + u16 gptmr0cnt; /* GP timer 0 count */ + u16 gptmr0maxcmpa; /* GP timer 0 maxcount compare A */ + u16 gptmr0maxcmpb; /* GP timer 0 maxcount compare B */ + u16 gptmr1ctl; /* GP timer 1 mode/control */ + u16 gptmr1cnt; /* GP timer 1 count */ + u16 gptmr1maxcmpa; /* GP timer 1 maxcount compare A */ + u16 gptmr1maxcmpb; /* GP timer 1 maxcount compare B*/ + u16 gptmr2ctl; /* GP timer 2 mode/control */ + u16 gptmr2cnt; /* GP timer 2 count */ + u8 pad_0xc86[0x08]; + u16 gptmr2maxcmpa; /* GP timer 2 maxcount compare A */ + + u8 pad_0xc90[0x20]; + + u16 wdtmrctl; /* watchdog timer control */ + u16 wdtmrcntl; /* watchdog timer count low */ + u16 wdtmrcnth; /* watchdog timer count high */ + + u8 pad_0xcb6[0x0a]; + + u8 uart1ctl; /* UART 1 general control */ + u8 uart1sta; /* UART 1 general status */ + u8 uart1fcrshad; /* UART 1 FIFO control shadow */ + u8 pad_0xcc3[0x01]; + u8 uart2ctl; /* UART 2 general control */ + u8 uart2sta; /* UART 2 general status */ + u8 uart2fcrshad; /* UART 2 FIFO control shadow */ + + u8 pad_0xcc7[0x09]; + + u8 ssictl; /* SSI control */ + u8 ssixmit; /* SSI transmit */ + u8 ssicmd; /* SSI command */ + u8 ssista; /* SSI status */ + u8 ssircv; /* SSI receive */ + + u8 pad_0xcd5[0x2b]; + + u8 picicr; /* interrupt control */ + u8 pad_0xd01[0x01]; + u8 pic_mode[3]; /* PIC interrupt mode */ + u8 pad_0xd05[0x03]; + u16 swint16_1; /* software interrupt 16-1 control */ + u8 swint22_17; /* software interrupt 22-17/NMI control */ + u8 pad_0xd0b[0x05]; + u16 intpinpol; /* interrupt pin polarity */ + u8 pad_0xd12[0x02]; + u16 pcihostmap; /* PCI host bridge interrupt mapping */ + u8 pad_0xd16[0x02]; + u16 eccmap; /* ECC interrupt mapping */ + u8 gp_tmr_int_map[3]; /* GP timer interrupt mapping */ + u8 pad_0xd1d[0x03]; + u8 pit_int_map[3]; /* PIT interrupt mapping */ + u8 pad_0xd23[0x05]; + u8 uart_int_map[2]; /* UART interrupt mapping */ + u8 pad_0xd2a[0x06]; + u8 pci_int_map[4]; /* PCI interrupt mapping (A through D)*/ + u8 pad_0xd34[0x0c]; + u8 dmabcintmap; /* DMA buffer chaining interrupt mapping */ + u8 ssimap; /* SSI interrupt mapping register */ + u8 wdtmap; /* watchdog timer interrupt mapping */ + u8 rtcmap; /* RTC interrupt mapping register */ + u8 wpvmap; /* write-protect interrupt mapping */ + u8 icemap; /* AMDebug JTAG Rx/Tx interrupt mapping */ + u8 ferrmap; /* floating point error interrupt mapping */ + u8 pad_0xd47[0x09]; + u8 gp_int_map[11]; /* GP IRQ interrupt mapping */ + + u8 pad_0xd5b[0x15]; + + u8 sysinfo; /* system board information */ + u8 pad_0xd71[0x01]; + u8 rescfg; /* reset configuration */ + u8 pad_0xd73[0x01]; + u8 ressta; /* reset status */ + + u8 pad_0xd75[0x0b]; + + u8 gpdmactl; /* GP-DMA Control */ + u8 gpdmammio; /* GP-DMA memory-mapped I/O */ + u16 gpdmaextchmapa; /* GP-DMA resource channel map a */ + u16 gpdmaextchmapb; /* GP-DMA resource channel map b */ + u8 gp_dma_ext_pg_0; /* GP-DMA channel extended page 0 */ + u8 gp_dma_ext_pg_1; /* GP-DMA channel extended page 0 */ + u8 gp_dma_ext_pg_2; /* GP-DMA channel extended page 0 */ + u8 gp_dma_ext_pg_3; /* GP-DMA channel extended page 0 */ + u8 gp_dma_ext_pg_5; /* GP-DMA channel extended page 0 */ + u8 gp_dma_ext_pg_6; /* GP-DMA channel extended page 0 */ + u8 gp_dma_ext_pg_7; /* GP-DMA channel extended page 0 */ + u8 pad_0xd8d[0x03]; + u8 gpdmaexttc3; /* GP-DMA channel 3 extender transfer count */ + u8 gpdmaexttc5; /* GP-DMA channel 5 extender transfer count */ + u8 gpdmaexttc6; /* GP-DMA channel 6 extender transfer count */ + u8 gpdmaexttc7; /* GP-DMA channel 7 extender transfer count */ + u8 pad_0xd94[0x4]; + u8 gpdmabcctl; /* buffer chaining control */ + u8 gpdmabcsta; /* buffer chaining status */ + u8 gpdmabsintenb; /* buffer chaining interrupt enable */ + u8 gpdmabcval; /* buffer chaining valid */ + u8 pad_0xd9c[0x04]; + u16 gpdmanxtaddl3; /* GP-DMA channel 3 next address low */ + u16 gpdmanxtaddh3; /* GP-DMA channel 3 next address high */ + u16 gpdmanxtaddl5; /* GP-DMA channel 5 next address low */ + u16 gpdmanxtaddh5; /* GP-DMA channel 5 next address high */ + u16 gpdmanxtaddl6; /* GP-DMA channel 6 next address low */ + u16 gpdmanxtaddh6; /* GP-DMA channel 6 next address high */ + u16 gpdmanxtaddl7; /* GP-DMA channel 7 next address low */ + u16 gpdmanxtaddh7; /* GP-DMA channel 7 next address high */ + u16 gpdmanxttcl3; /* GP-DMA channel 3 next transfer count low */ + u16 gpdmanxttch3; /* GP-DMA channel 3 next transfer count high */ + u16 gpdmanxttcl5; /* GP-DMA channel 5 next transfer count low */ + u16 gpdmanxttch5; /* GP-DMA channel 5 next transfer count high */ + u16 gpdmanxttcl6; /* GP-DMA channel 6 next transfer count low */ + u16 gpdmanxttch6; /* GP-DMA channel 6 next transfer count high */ + u16 gpdmanxttcl7; /* GP-DMA channel 7 next transfer count low */ + u16 gpdmanxttch7; /* GP-DMA channel 7 next transfer count high */ + + u8 pad_0xdc0[0x0240]; +} sc520_mmcr_t; + +extern volatile sc520_mmcr_t *sc520_mmcr; + +#endif + +/* MMCR Offsets (required for assembler code */ #define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */ -#define SC520_BOOTCSCTL 0x0050 /* /BOOTCS Control Register */ -#define SC520_ROMCS1CTL 0x0054 /* /ROMCS1 Control Register */ -#define SC520_ROMCS2CTL 0x0056 /* /ROMCS2 Control Register */ -#define SC520_HBCTL 0x0060 /* Host Bridge Control Register */ -#define SC520_HBTGTIRQCTL 0x0062 /* Host Bridge Target Interrupt Control Register */ -#define SC520_HBTGTIRQSTA 0x0064 /* Host Bridge Target Interrupt Status Register */ -#define SC520_HBMSTIRQCTL 0x0066 /* Host Bridge Target Interrupt Control Register */ -#define SC520_HBMSTIRQSTA 0x0068 /* Host Bridge Master Interrupt Status Register */ -#define SC520_MSTINTADD 0x006c /* Host Bridge Master Interrupt Address Register */ -#define SC520_SYSARBCTL 0x0070 /* System Arbiter Control Register */ -#define SC520_PCIARBSTA 0x0071 /* PCI Bus Arbiter Status Register */ -#define SC520_SYSARBMENB 0x0072 /* System Arbiter Master Enable Register */ -#define SC520_ARBPRICTL 0x0074 /* Arbiter Priority Control Register */ -#define SC520_ADDDECCTL 0x0080 /* Address Decode Control Register */ -#define SC520_WPVSTA 0x0082 /* Write-Protect Violation Status Register */ -#define SC520_PAR0 0x0088 /* Programmable Address Region 0 Register */ -#define SC520_PAR1 0x008c /* Programmable Address Region 1 Register */ -#define SC520_PAR2 0x0090 /* Programmable Address Region 2 Register */ -#define SC520_PAR3 0x0094 /* Programmable Address Region 3 Register */ -#define SC520_PAR4 0x0098 /* Programmable Address Region 4 Register */ -#define SC520_PAR5 0x009c /* Programmable Address Region 5 Register */ -#define SC520_PAR6 0x00a0 /* Programmable Address Region 6 Register */ -#define SC520_PAR7 0x00a4 /* Programmable Address Region 7 Register */ -#define SC520_PAR8 0x00a8 /* Programmable Address Region 8 Register */ -#define SC520_PAR9 0x00ac /* Programmable Address Region 9 Register */ -#define SC520_PAR10 0x00b0 /* Programmable Address Region 10 Register */ -#define SC520_PAR11 0x00b4 /* Programmable Address Region 11 Register */ -#define SC520_PAR12 0x00b8 /* Programmable Address Region 12 Register */ -#define SC520_PAR13 0x00bc /* Programmable Address Region 13 Register */ #define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */ #define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */ -#define SC520_GPECHO 0x0c00 /* GP Echo Mode Register */ -#define SC520_GPCSDW 0x0c01 /* GP Chip Select Data Width Register */ -#define SC520_GPCSQUAL 0x0c02 /* GP Chip Select Qualification Register */ -#define SC520_GPCSRT 0x0c08 /* GP Chip Select Recovery Time Register */ -#define SC520_GPCSPW 0x0c09 /* GP Chip Select Pulse Width Register */ -#define SC520_GPCSOFF 0x0c0a /* GP Chip Select Offset Register */ -#define SC520_GPRDW 0x0c0b /* GP Read Pulse Width Register */ -#define SC520_GPRDOFF 0x0c0c /* GP Read Offset Register */ -#define SC520_GPWRW 0x0c0d /* GP Write Pulse Width Register */ -#define SC520_GPWROFF 0x0c0e /* GP Write Offset Register */ -#define SC520_GPALEW 0x0c0f /* GP ALE Pulse Width Register */ -#define SC520_GPALEOFF 0x0c10 /* GP ALE Offset Register */ -#define SC520_PIOPFS15_0 0x0c20 /* PIO15-PIO0 Pin Function Select */ -#define SC520_PIOPFS31_16 0x0c22 /* PIO31-PIO16 Pin Function Select */ -#define SC520_CSPFS 0x0c24 /* Chip Select Pin Function Select */ -#define SC520_CLKSEL 0x0c26 /* Clock Select */ -#define SC520_DSCTL 0x0c28 /* Drive Strength Control */ -#define SC520_PIODIR15_0 0x0c2a /* PIO15-PIO0 Direction */ -#define SC520_PIODIR31_16 0x0c2c /* PIO31-PIO16 Direction */ -#define SC520_PIODATA15_0 0x0c30 /* PIO15-PIO0 Data */ -#define SC520_PIODATA31_16 0x0c32 /* PIO31-PIO16 Data */ -#define SC520_PIOSET15_0 0x0c34 /* PIO15-PIO0 Set */ -#define SC520_PIOSET31_16 0x0c36 /* PIO31-PIO16 Set */ -#define SC520_PIOCLR15_0 0x0c38 /* PIO15-PIO0 Clear */ -#define SC520_PIOCLR31_16 0x0c3a /* PIO31-PIO16 Clear */ -#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */ -#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */ -#define SC520_SWTMRCFG 0x0c64 /* Software Timer Configuration */ -#define SC520_GPTMRSTA 0x0c70 /* GP Timers Status Register */ -#define SC520_GPTMR0CTL 0x0c72 /* GP Timer 0 Mode/Control Register */ -#define SC520_GPTMR0CNT 0x0c74 /* GP Timer 0 Count Register */ -#define SC520_GPTMR0MAXCMPA 0x0c76 /* GP Timer 0 Maxcount Compare A Register */ -#define SC520_GPTMR0MAXCMPB 0x0c78 /* GP Timer 0 Maxcount Compare B Register */ -#define SC520_GPTMR1CTL 0x0c7a /* GP Timer 1 Mode/Control Register */ -#define SC520_GPTMR1CNT 0x0c7c /* GP Timer 1 Count Register */ -#define SC520_GPTMR1MAXCMPA 0x0c7e /* GP Timer 1 Maxcount Compare Register A */ -#define SC520_GPTMR1MAXCMPB 0x0c80 /* GP Timer 1 Maxcount Compare B Register */ -#define SC520_GPTMR2CTL 0x0c82 /* GP Timer 2 Mode/Control Register */ -#define SC520_GPTMR2CNT 0x0c84 /* GP Timer 2 Count Register */ -#define SC520_GPTMR2MAXCMPA 0x0c8e /* GP Timer 2 Maxcount Compare A Register */ -#define SC520_WDTMRCTL 0x0cb0 /* Watchdog Timer Control Register */ -#define SC520_WDTMRCNTL 0x0cb2 /* Watchdog Timer Count Low Register */ -#define SC520_WDTMRCNTH 0x0cb4 /* Watchdog Timer Count High Register */ -#define SC520_UART1CTL 0x0cc0 /* UART 1 General Control Register */ -#define SC520_UART1STA 0x0cc1 /* UART 1 General Status Register */ -#define SC520_UART1FCRSHAD 0x0cc2 /* UART 1 FIFO Control Shadow Register */ -#define SC520_UART2CTL 0x0cc4 /* UART 2 General Control Register */ -#define SC520_UART2STA 0x0cc5 /* UART 2 General Status Register */ -#define SC520_UART2FCRSHAD 0x0cc6 /* UART 2 FIFO Control Shadow Register */ -#define SC520_SSICTL 0x0cd0 /* SSI Control */ -#define SC520_SSIXMIT 0x0cd1 /* SSI Transmit */ -#define SC520_SSICMD 0x0cd2 /* SSI Command */ -#define SC520_SSISTA 0x0cd3 /* SSI Status */ -#define SC520_SSIRCV 0x0cd4 /* SSI Receive */ -#define SC520_PICICR 0x0d00 /* Interrupt Control Register */ -#define SC520_MPICMODE 0x0d02 /* Master PIC Interrupt Mode Register */ -#define SC520_SL1PICMODE 0x0d03 /* Slave 1 PIC Interrupt Mode Register */ -#define SC520_SL2PICMODE 0x0d04 /* Slave 2 PIC Interrupt Mode Register */ -#define SC520_SWINT16_1 0x0d08 /* Software Interrupt 16-1 Control Register */ -#define SC520_SWINT22_17 0x0d0a /* Software Interrupt 22-17/NMI Control Register */ -#define SC520_INTPINPOL 0x0d10 /* Interrupt Pin Polarity Register */ -#define SC520_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mappin Register */ -#define SC520_ECCMAP 0x0d18 /* ECC Interrupt Mapping Register */ -#define SC520_GPTMR0MAP 0x0d1a /* GP Timer 0 Interrupt Mapping Register */ -#define SC520_GPTMR1MAP 0x0d1b /* GP Timer 1 Interrupt Mapping Register */ -#define SC520_GPTMR2MAP 0x0d1c /* GP Timer 2 Interrupt Mapping Register */ -#define SC520_PIT0MAP 0x0d20 /* PIT0 Interrupt Mapping Register */ -#define SC520_PIT1MAP 0x0d21 /* PIT1 Interrupt Mapping Register */ -#define SC520_PIT2MAP 0x0d22 /* PIT2 Interrupt Mapping Register */ -#define SC520_UART1MAP 0x0d28 /* UART 1 Interrupt Mapping Register */ -#define SC520_UART2MAP 0x0d29 /* UART 2 Interrupt Mapping Register */ -#define SC520_PCIINTAMAP 0x0d30 /* PCI Interrupt A Mapping Register */ -#define SC520_PCIINTBMAP 0x0d31 /* PCI Interrupt B Mapping Register */ -#define SC520_PCIINTCMAP 0x0d32 /* PCI Interrupt C Mapping Register */ -#define SC520_PCIINTDMAP 0x0d33 /* PCI Interrupt D Mapping Register */ -#define SC520_DMABCINTMAP 0x0d40 /* DMA Buffer Chaining Interrupt Mapping Register */ -#define SC520_SSIMAP 0x0d41 /* SSI Interrupt Mapping Register */ -#define SC520_WDTMAP 0x0d42 /* Watchdog Timer Interrupt Mapping Register */ -#define SC520_RTCMAP 0x0d43 /* RTC Interrupt Mapping Register */ -#define SC520_WPVMAP 0x0d44 /* Write-Protect Interrupt Mapping Register */ -#define SC520_ICEMAP 0x0d45 /* AMDebug JTAG RX/TX Interrupt Mapping Register */ -#define SC520_FERRMAP 0x0d46 /* Floating Point Error Interrupt Mapping Register */ -#define SC520_GP0IMAP 0x0d50 /* GPIRQ0 Interrupt Mapping Register */ -#define SC520_GP1IMAP 0x0d51 /* GPIRQ1 Interrupt Mapping Register */ -#define SC520_GP2IMAP 0x0d52 /* GPIRQ2 Interrupt Mapping Register */ -#define SC520_GP3IMAP 0x0d53 /* GPIRQ3 Interrupt Mapping Register */ -#define SC520_GP4IMAP 0x0d54 /* GPIRQ4 Interrupt Mapping Register */ -#define SC520_GP5IMAP 0x0d55 /* GPIRQ5 Interrupt Mapping Register */ -#define SC520_GP6IMAP 0x0d56 /* GPIRQ6 Interrupt Mapping Register */ -#define SC520_GP7IMAP 0x0d57 /* GPIRQ7 Interrupt Mapping Register */ -#define SC520_GP8IMAP 0x0d58 /* GPIRQ8 Interrupt Mapping Register */ -#define SC520_GP9IMAP 0x0d59 /* GPIRQ9 Interrupt Mapping Register */ -#define SC520_GP10IMAP 0x0d5a /* GPIRQ10 Interrupt Mapping Register */ -#define SC520_SYSINFO 0x0d70 /* System Board Information Register */ -#define SC520_RESCFG 0x0d72 /* Reset Configuration Register */ -#define SC520_RESSTA 0x0d74 /* Reset Status Register */ -#define SC520_GPDMAMMIO 0x0d81 /* GP-DMA Memory-Mapped I/O Register */ -#define SC520_GPDMAEXTCHMAPA 0x0d82 /* GP-DMA Resource Channel Map A */ -#define SC520_GPDMAEXTCHMAPB 0x0d84 /* GP-DMA Resource Channel Map B */ -#define SC520_GPDMAEXTPG0 0x0d86 /* GP-DMA Channel 0 Extended Page */ -#define SC520_GPDMAEXTPG1 0x0d87 /* GP-DMA Channel 1 Extended Page */ -#define SC520_GPDMAEXTPG2 0x0d88 /* GP-DMA Channel 2 Extended Page */ -#define SC520_GPDMAEXTPG3 0x0d89 /* GP-DMA Channel 3 Extended Page */ -#define SC520_GPDMAEXTPG5 0x0d8a /* GP-DMA Channel 5 Extended Page */ -#define SC520_GPDMAEXTPG6 0x0d8b /* GP-DMA Channel 6 Extended Page */ -#define SC520_GPDMAEXTPG7 0x0d8c /* GP-DMA Channel 7 Extended Page */ -#define SC520_GPDMAEXTTC3 0x0d90 /* GP-DMA Channel 3 Extender Transfer count */ -#define SC520_GPDMAEXTTC5 0x0d91 /* GP-DMA Channel 5 Extender Transfer count */ -#define SC520_GPDMAEXTTC6 0x0d92 /* GP-DMA Channel 6 Extender Transfer count */ -#define SC520_GPDMAEXTTC7 0x0d93 /* GP-DMA Channel 7 Extender Transfer count */ -#define SC520_GPDMABCCTL 0x0d98 /* Buffer Chaining Control */ -#define SC520_GPDMABCSTA 0x0d99 /* Buffer Chaining Status */ -#define SC520_GPDMABSINTENB 0x0d9a /* Buffer Chaining Interrupt Enable */ -#define SC520_GPDMABCVAL 0x0d9b /* Buffer Chaining Valid */ -#define SC520_GPDMANXTADDL3 0x0da0 /* GP-DMA Channel 3 Next Address Low */ -#define SC520_GPDMANXTADDH3 0x0da2 /* GP-DMA Channel 3 Next Address High */ -#define SC520_GPDMANXTADDL5 0x0da4 /* GP-DMA Channel 5 Next Address Low */ -#define SC520_GPDMANXTADDH5 0x0da6 /* GP-DMA Channel 5 Next Address High */ -#define SC520_GPDMANXTADDL6 0x0da8 /* GP-DMA Channel 6 Next Address Low */ -#define SC520_GPDMANXTADDH6 0x0daa /* GP-DMA Channel 6 Next Address High */ -#define SC520_GPDMANXTADDL7 0x0dac /* GP-DMA Channel 7 Next Address Low */ -#define SC520_GPDMANXTADDH7 0x0dae /* GP-DMA Channel 7 Next Address High */ -#define SC520_GPDMANXTTCL3 0x0db0 /* GP-DMA Channel 3 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH3 0x0db2 /* GP-DMA Channel 3 Next Transfer Count High */ -#define SC520_GPDMANXTTCL5 0x0db4 /* GP-DMA Channel 5 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH5 0x0db6 /* GP-DMA Channel 5 Next Transfer Count High */ -#define SC520_GPDMANXTTCL6 0x0db8 /* GP-DMA Channel 6 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH6 0x0dba /* GP-DMA Channel 6 Next Transfer Count High */ -#define SC520_GPDMANXTTCL7 0x0dbc /* GP-DMA Channel 7 Next Transfer Count Low */ -#define SC520_GPDMANXTTCH7 0x0dbe /* GP-DMA Channel 7 Next Transfer Count High */ +#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */ +#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */ /* MMCR Register bits (not all of them :) ) */ @@ -221,7 +285,6 @@ #define SSISTA_BSY 0x02 /* SSI Busy */ #define SSISTA_TC_INT 0x01 /* SSI Transaction Complete Interrupt */ - /* BITS for SC520_ADDDECCTL: */ #define WPV_INT_ENB 0x80 /* Write-Protect Violation Interrupt Enable */ #define IO_HOLE_DEST_PCI 0x10 /* I/O Hole Access Destination */ @@ -233,7 +296,6 @@ #define SC520_REG_ADDR 0x00000cf8 #define SC520_REG_DATA 0x00000cfc - #define SC520_ISA_MEM_PHYS 0x00000000 #define SC520_ISA_MEM_BUS 0x00000000 #define SC520_ISA_MEM_SIZE 0x01000000 @@ -282,15 +344,4 @@ #define SC520_IRQ14 9 #define SC520_IRQ15 10 -/* utility functions */ -void write_mmcr_byte(u16 mmcr, u8 data); -void write_mmcr_word(u16 mmcr, u16 data); -void write_mmcr_long(u16 mmcr, u32 data); -u8 read_mmcr_byte(u16 mmcr); -u16 read_mmcr_word(u16 mmcr); -u32 read_mmcr_long(u16 mmcr); - -void init_sc520(void); -unsigned long init_sc520_dram(void); - #endif -- cgit v1.2.3 From 5b34a296d47b236dafbcaf1c91ae11b5aeb1ef51 Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 23 Aug 2009 12:59:58 +1000 Subject: Add PCI support to eNET board Signed-off-by: Graeme Russ --- include/configs/eNET.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 43567142323..243a5541785 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -86,6 +86,7 @@ #define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_PCI /* PCI support */ #define CONFIG_CMD_RUN /* run command in env variable */ #define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ @@ -200,13 +201,12 @@ /*----------------------------------------------------------------------- * PCI configuration */ -#undef CONFIG_PCI /* include pci support */ -#undef CONFIG_PCI_PNP /* pci plug-and-play */ -#undef CONFIG_PCI_SCAN_SHOW -#undef CONFIG_SYS_FIRST_PCI_IRQ -#undef CONFIG_SYS_SECOND_PCI_IRQ -#undef CONFIG_SYS_THIRD_PCI_IRQ -#undef CONFIG_SYS_FORTH_PCI_IRQ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* pci plug-and-play */ +#define CONFIG_SYS_FIRST_PCI_IRQ 10 +#define CONFIG_SYS_SECOND_PCI_IRQ 9 +#define CONFIG_SYS_THIRD_PCI_IRQ 11 +#define CONFIG_SYS_FORTH_PCI_IRQ 15 /*----------------------------------------------------------------------- * Hardware watchdog configuration -- cgit v1.2.3 From 795d246c278e70b4ba9868cc9f2c8fbada49d388 Mon Sep 17 00:00:00 2001 From: Eric Millbrandt Date: Fri, 28 Aug 2009 07:14:04 -0500 Subject: galaxy5200: Add chip select region for an Epson S1D15313 Signed-off-by: Eric Millbrandt --- include/configs/galaxy5200.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index 8d530d86aa1..a5b5a03a9a2 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -211,6 +211,11 @@ #define CONFIG_SYS_CS1_SIZE 0x90000 #define CONFIG_SYS_CS1_CFG 0x0002d900 +/* Chip Select configuration for Epson S1D13513 */ +#define CONFIG_SYS_CS3_START 0x10000000 +#define CONFIG_SYS_CS3_SIZE 0x400000 +#define CONFIG_SYS_CS3_CFG 0xffff3d10 + /* * Ethernet configuration */ -- cgit v1.2.3 From d8bc55a6fb28876abcbf4a3fc3b6c3ce429c1bb3 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Tue, 1 Sep 2009 20:58:03 +0400 Subject: Move uninitialized_var() macro from ubi_uboot.h to compiler.h This is needed so that we could use this macro for non-UBI code. Signed-off-by: Anton Vorontsov --- include/compiler.h | 3 +++ include/ubi_uboot.h | 4 +--- 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/compiler.h b/include/compiler.h index 272fd3cf628..e602cce2e9b 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -122,4 +122,7 @@ typedef unsigned int uintptr_t; #endif +/* compiler options */ +#define uninitialized_var(x) x = x + #endif diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index 74312abf039..60f6a5fb4f5 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -15,6 +15,7 @@ #define __UBOOT_UBI_H #include +#include #include #include #include @@ -51,9 +52,6 @@ do { \ #undef CONFIG_MTD_UBI_DEBUG_MSG_BLD #define CONFIG_MTD_UBI_DEBUG_DISABLE_BGT -/* compiler options */ -#define uninitialized_var(x) x = x - /* build.c */ #define get_device(...) #define put_device(...) -- cgit v1.2.3 From 9f23ca42b3ba19b24e66fade572f2b86d929b6e8 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 4 Sep 2009 23:20:29 +0200 Subject: ARM: Update mach-types Signed-off-by: Wolfgang Denk --- include/asm-arm/mach-types.h | 2068 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 2056 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index 5293d679eb0..6c1f5ac4e6c 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -1,6 +1,9 @@ /* - * This was automagically generated from arch/arm/tools/mach-types! + * This was automagically generated from mach-types! * Do NOT edit + * + * Last update: Fri Sep 4 22:16:22 2009 + * */ #ifndef __ASM_ARM_MACH_TYPE_H @@ -1451,7 +1454,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_H6044 1458 #define MACH_TYPE_APP 1459 #define MACH_TYPE_TCT_HAMMER 1460 -#define MACH_TYPE_HERMES 1461 +#define MACH_TYPE_HERALD 1461 #define MACH_TYPE_ARTEMIS 1462 #define MACH_TYPE_HTCTITAN 1463 #define MACH_TYPE_QRANIUM 1464 @@ -1765,7 +1768,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_MI424WR 1778 #define MACH_TYPE_AXS_ULTRAX 1779 #define MACH_TYPE_AT572D940DEB 1780 -#define MACH_TYPE_DAVINCI_DA8XX_EVM 1781 +#define MACH_TYPE_DAVINCI_DA830_EVM 1781 #define MACH_TYPE_EP9302 1782 #define MACH_TYPE_AT572D940HFEB 1783 #define MACH_TYPE_CYBOOK3 1784 @@ -2241,6 +2244,163 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_OMAP3_WL_FF 2258 #define MACH_TYPE_SIMCOM 2259 #define MACH_TYPE_MCWEBIO 2260 +#define MACH_TYPE_OMAP3_PHRAZER 2261 +#define MACH_TYPE_DARWIN 2262 +#define MACH_TYPE_ORATISCOMU 2263 +#define MACH_TYPE_RTSBC20 2264 +#define MACH_TYPE_I780 2265 +#define MACH_TYPE_GEMINI324 2266 +#define MACH_TYPE_ORATISLAN 2267 +#define MACH_TYPE_ORATISALOG 2268 +#define MACH_TYPE_ORATISMADI 2269 +#define MACH_TYPE_ORATISOT16 2270 +#define MACH_TYPE_ORATISDESK 2271 +#define MACH_TYPE_V2P_CA9 2272 +#define MACH_TYPE_SINTEXO 2273 +#define MACH_TYPE_CM3389 2274 +#define MACH_TYPE_OMAP3_CIO 2275 +#define MACH_TYPE_SGH_I900 2276 +#define MACH_TYPE_BST100 2277 +#define MACH_TYPE_PASSION 2278 +#define MACH_TYPE_INDESIGN_AT91SAM 2279 +#define MACH_TYPE_C4_BADGER 2280 +#define MACH_TYPE_C4_VIPER 2281 +#define MACH_TYPE_D2NET 2282 +#define MACH_TYPE_BIGDISK 2283 +#define MACH_TYPE_NOTALVISION 2284 +#define MACH_TYPE_OMAP3_KBOC 2285 +#define MACH_TYPE_CYCLONE 2286 +#define MACH_TYPE_NINJA 2287 +#define MACH_TYPE_AT91SAM9G20EK_2MMC 2288 +#define MACH_TYPE_BCMRING 2289 +#define MACH_TYPE_RESOL_DL2 2290 +#define MACH_TYPE_IFOSW 2291 +#define MACH_TYPE_HTCRHODIUM 2292 +#define MACH_TYPE_HTCTOPAZ 2293 +#define MACH_TYPE_MATRIX504 2294 +#define MACH_TYPE_MRFSA 2295 +#define MACH_TYPE_SC_P270 2296 +#define MACH_TYPE_ATLAS5_EVB 2297 +#define MACH_TYPE_PELCO_LOBOX 2298 +#define MACH_TYPE_DILAX_PCU200 2299 +#define MACH_TYPE_LEONARDO 2300 +#define MACH_TYPE_ZORAN_APPROACH7 2301 +#define MACH_TYPE_DP6XX 2302 +#define MACH_TYPE_BCM2153_VESPER 2303 +#define MACH_TYPE_MAHIMAHI 2304 +#define MACH_TYPE_CLICKC 2305 +#define MACH_TYPE_ZB_GATEWAY 2306 +#define MACH_TYPE_TAZCARD 2307 +#define MACH_TYPE_TAZDEV 2308 +#define MACH_TYPE_ANNAX_CB_ARM 2309 +#define MACH_TYPE_ANNAX_DM3 2310 +#define MACH_TYPE_CEREBRIC 2311 +#define MACH_TYPE_ORCA 2312 +#define MACH_TYPE_PC9260 2313 +#define MACH_TYPE_EMS285A 2314 +#define MACH_TYPE_GEC2410 2315 +#define MACH_TYPE_GEC2440 2316 +#define MACH_TYPE_ARCH_MW903 2317 +#define MACH_TYPE_MW2440 2318 +#define MACH_TYPE_ECAC2378 2319 +#define MACH_TYPE_TAZKIOSK 2320 +#define MACH_TYPE_WHITERABBIT_MCH 2321 +#define MACH_TYPE_SBOX9263 2322 +#define MACH_TYPE_OREO 2323 +#define MACH_TYPE_SMDK6442 2324 +#define MACH_TYPE_OPENRD_BASE 2325 +#define MACH_TYPE_INCREDIBLE 2326 +#define MACH_TYPE_INCREDIBLEC 2327 +#define MACH_TYPE_HEROCT 2328 +#define MACH_TYPE_MMNET1000 2329 +#define MACH_TYPE_DEVKIT8000 2330 +#define MACH_TYPE_DEVKIT9000 2331 +#define MACH_TYPE_MX31TXTR 2332 +#define MACH_TYPE_U380 2333 +#define MACH_TYPE_HUALU_BOARD 2334 +#define MACH_TYPE_NPCMX50 2335 +#define MACH_TYPE_MX51_LANGE51 2336 +#define MACH_TYPE_MX51_LANGE52 2337 +#define MACH_TYPE_RIOM 2338 +#define MACH_TYPE_COMCAS 2339 +#define MACH_TYPE_WSI_MX27 2340 +#define MACH_TYPE_CM_T35 2341 +#define MACH_TYPE_NET2BIG 2342 +#define MACH_TYPE_MOTOROLA_A1600 2343 +#define MACH_TYPE_IGEP0020 2344 +#define MACH_TYPE_IGEP0010 2345 +#define MACH_TYPE_MV6281GTWGE2 2346 +#define MACH_TYPE_SCAT100 2347 +#define MACH_TYPE_SANMINA 2348 +#define MACH_TYPE_MOMENTO 2349 +#define MACH_TYPE_NUC9XX 2350 +#define MACH_TYPE_NUC910EVB 2351 +#define MACH_TYPE_NUC920EVB 2352 +#define MACH_TYPE_NUC950EVB 2353 +#define MACH_TYPE_NUC945EVB 2354 +#define MACH_TYPE_NUC960EVB 2355 +#define MACH_TYPE_NUC932EVB 2356 +#define MACH_TYPE_NUC900 2357 +#define MACH_TYPE_SD1SOC 2358 +#define MACH_TYPE_LN2440BC 2359 +#define MACH_TYPE_RSBC 2360 +#define MACH_TYPE_OPENRD_CLIENT 2361 +#define MACH_TYPE_HPIPAQ11X 2362 +#define MACH_TYPE_WAYLAND 2363 +#define MACH_TYPE_ACNBSX102 2364 +#define MACH_TYPE_HWAT91 2365 +#define MACH_TYPE_AT91SAM9263CS 2366 +#define MACH_TYPE_CSB732 2367 +#define MACH_TYPE_U8500 2368 +#define MACH_TYPE_HUQIU 2369 +#define MACH_TYPE_MX51_KUNLUN 2370 +#define MACH_TYPE_PMT1G 2371 +#define MACH_TYPE_HTCELF 2372 +#define MACH_TYPE_ARMADILLO420 2373 +#define MACH_TYPE_ARMADILLO440 2374 +#define MACH_TYPE_U_CHIP_DUAL_ARM 2375 +#define MACH_TYPE_CSR_BDB3 2376 +#define MACH_TYPE_DOLBY_CAT1018 2377 +#define MACH_TYPE_HY9307 2378 +#define MACH_TYPE_A_ES 2379 +#define MACH_TYPE_DAVINCI_IRIF 2380 +#define MACH_TYPE_AGAMA9263 2381 +#define MACH_TYPE_MARVELL_JASPER 2382 +#define MACH_TYPE_FLINT 2383 +#define MACH_TYPE_TAVOREVB3 2384 +#define MACH_TYPE_SCH_M490 2386 +#define MACH_TYPE_RBL01 2387 +#define MACH_TYPE_OMNIFI 2388 +#define MACH_TYPE_OTAVALO 2389 +#define MACH_TYPE_SIENNA 2390 +#define MACH_TYPE_HTC_EXCALIBUR_S620 2391 +#define MACH_TYPE_HTC_OPAL 2392 +#define MACH_TYPE_TOUCHBOOK 2393 +#define MACH_TYPE_LATTE 2394 +#define MACH_TYPE_XA200 2395 +#define MACH_TYPE_NIMROD 2396 +#define MACH_TYPE_CC9P9215_3G 2397 +#define MACH_TYPE_CC9P9215_3GJS 2398 +#define MACH_TYPE_TK71 2399 +#define MACH_TYPE_COMHAM3525 2400 +#define MACH_TYPE_MX31EREBUS 2401 +#define MACH_TYPE_MCARDMX27 2402 +#define MACH_TYPE_PARADISE 2403 +#define MACH_TYPE_TIDE 2404 +#define MACH_TYPE_WZL2440 2405 +#define MACH_TYPE_SDRDEMO 2406 +#define MACH_TYPE_ETHERCAN2 2407 +#define MACH_TYPE_ECMIMG20 2408 +#define MACH_TYPE_OMAP_DRAGON 2409 +#define MACH_TYPE_HALO 2410 +#define MACH_TYPE_HUANGSHAN 2411 +#define MACH_TYPE_VL_MA2SC 2412 +#define MACH_TYPE_RAUMFELD_RC 2413 +#define MACH_TYPE_RAUMFELD_CONNECTOR 2414 +#define MACH_TYPE_RAUMFELD_SPEAKER 2415 +#define MACH_TYPE_MULTIBUS_MASTER 2416 +#define MACH_TYPE_MULTIBUS_PBK 2417 +#define MACH_TYPE_TNETV107X 2418 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -19510,14 +19670,14 @@ extern unsigned int __machine_arch_type; # define machine_is_tct_hammer() (0) #endif -#ifdef CONFIG_MACH_HERMES +#ifdef CONFIG_MACH_HERALD # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_HERMES +# define machine_arch_type MACH_TYPE_HERALD # endif -# define machine_is_herald() (machine_arch_type == MACH_TYPE_HERMES) +# define machine_is_herald() (machine_arch_type == MACH_TYPE_HERALD) #else # define machine_is_herald() (0) #endif @@ -23278,16 +23438,16 @@ extern unsigned int __machine_arch_type; # define machine_is_at572d940deb() (0) #endif -#ifdef CONFIG_MACH_DAVINCI_DA8XX_EVM +#ifdef CONFIG_MACH_DAVINCI_DA830_EVM # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_DAVINCI_DA8XX_EVM +# define machine_arch_type MACH_TYPE_DAVINCI_DA830_EVM # endif -# define machine_is_davinci_da8xx_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA8XX_EVM) +# define machine_is_davinci_da830_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM) #else -# define machine_is_davinci_da8xx_evm() (0) +# define machine_is_davinci_da830_evm() (0) #endif #ifdef CONFIG_MACH_EP9302 @@ -25601,9 +25761,9 @@ extern unsigned int __machine_arch_type; # else # define machine_arch_type MACH_TYPE_CPUIMX27 # endif -# define machine_is_cpuimx27() (machine_arch_type == MACH_TYPE_CPUIMX27) +# define machine_is_eukrea_cpuimx27() (machine_arch_type == MACH_TYPE_CPUIMX27) #else -# define machine_is_cpuimx27() (0) +# define machine_is_eukrea_cpuimx27() (0) #endif #ifdef CONFIG_MACH_CHEFLUX @@ -28990,6 +29150,1890 @@ extern unsigned int __machine_arch_type; # define machine_is_mcwebio() (0) #endif +#ifdef CONFIG_MACH_OMAP3_PHRAZER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_PHRAZER +# endif +# define machine_is_omap3_phrazer() (machine_arch_type == MACH_TYPE_OMAP3_PHRAZER) +#else +# define machine_is_omap3_phrazer() (0) +#endif + +#ifdef CONFIG_MACH_DARWIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DARWIN +# endif +# define machine_is_darwin() (machine_arch_type == MACH_TYPE_DARWIN) +#else +# define machine_is_darwin() (0) +#endif + +#ifdef CONFIG_MACH_ORATISCOMU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISCOMU +# endif +# define machine_is_oratiscomu() (machine_arch_type == MACH_TYPE_ORATISCOMU) +#else +# define machine_is_oratiscomu() (0) +#endif + +#ifdef CONFIG_MACH_RTSBC20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RTSBC20 +# endif +# define machine_is_rtsbc20() (machine_arch_type == MACH_TYPE_RTSBC20) +#else +# define machine_is_rtsbc20() (0) +#endif + +#ifdef CONFIG_MACH_I780 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_I780 +# endif +# define machine_is_sgh_i780() (machine_arch_type == MACH_TYPE_I780) +#else +# define machine_is_sgh_i780() (0) +#endif + +#ifdef CONFIG_MACH_GEMINI324 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEMINI324 +# endif +# define machine_is_gemini324() (machine_arch_type == MACH_TYPE_GEMINI324) +#else +# define machine_is_gemini324() (0) +#endif + +#ifdef CONFIG_MACH_ORATISLAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISLAN +# endif +# define machine_is_oratislan() (machine_arch_type == MACH_TYPE_ORATISLAN) +#else +# define machine_is_oratislan() (0) +#endif + +#ifdef CONFIG_MACH_ORATISALOG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISALOG +# endif +# define machine_is_oratisalog() (machine_arch_type == MACH_TYPE_ORATISALOG) +#else +# define machine_is_oratisalog() (0) +#endif + +#ifdef CONFIG_MACH_ORATISMADI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISMADI +# endif +# define machine_is_oratismadi() (machine_arch_type == MACH_TYPE_ORATISMADI) +#else +# define machine_is_oratismadi() (0) +#endif + +#ifdef CONFIG_MACH_ORATISOT16 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISOT16 +# endif +# define machine_is_oratisot16() (machine_arch_type == MACH_TYPE_ORATISOT16) +#else +# define machine_is_oratisot16() (0) +#endif + +#ifdef CONFIG_MACH_ORATISDESK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORATISDESK +# endif +# define machine_is_oratisdesk() (machine_arch_type == MACH_TYPE_ORATISDESK) +#else +# define machine_is_oratisdesk() (0) +#endif + +#ifdef CONFIG_MACH_V2P_CA9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_V2P_CA9 +# endif +# define machine_is_v2_ca9() (machine_arch_type == MACH_TYPE_V2P_CA9) +#else +# define machine_is_v2_ca9() (0) +#endif + +#ifdef CONFIG_MACH_SINTEXO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SINTEXO +# endif +# define machine_is_sintexo() (machine_arch_type == MACH_TYPE_SINTEXO) +#else +# define machine_is_sintexo() (0) +#endif + +#ifdef CONFIG_MACH_CM3389 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM3389 +# endif +# define machine_is_cm3389() (machine_arch_type == MACH_TYPE_CM3389) +#else +# define machine_is_cm3389() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_CIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_CIO +# endif +# define machine_is_omap3_cio() (machine_arch_type == MACH_TYPE_OMAP3_CIO) +#else +# define machine_is_omap3_cio() (0) +#endif + +#ifdef CONFIG_MACH_SGH_I900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SGH_I900 +# endif +# define machine_is_sgh_i900() (machine_arch_type == MACH_TYPE_SGH_I900) +#else +# define machine_is_sgh_i900() (0) +#endif + +#ifdef CONFIG_MACH_BST100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BST100 +# endif +# define machine_is_bst100() (machine_arch_type == MACH_TYPE_BST100) +#else +# define machine_is_bst100() (0) +#endif + +#ifdef CONFIG_MACH_PASSION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PASSION +# endif +# define machine_is_passion() (machine_arch_type == MACH_TYPE_PASSION) +#else +# define machine_is_passion() (0) +#endif + +#ifdef CONFIG_MACH_INDESIGN_AT91SAM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INDESIGN_AT91SAM +# endif +# define machine_is_indesign_at91sam() (machine_arch_type == MACH_TYPE_INDESIGN_AT91SAM) +#else +# define machine_is_indesign_at91sam() (0) +#endif + +#ifdef CONFIG_MACH_C4_BADGER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C4_BADGER +# endif +# define machine_is_c4_badger() (machine_arch_type == MACH_TYPE_C4_BADGER) +#else +# define machine_is_c4_badger() (0) +#endif + +#ifdef CONFIG_MACH_C4_VIPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_C4_VIPER +# endif +# define machine_is_c4_viper() (machine_arch_type == MACH_TYPE_C4_VIPER) +#else +# define machine_is_c4_viper() (0) +#endif + +#ifdef CONFIG_MACH_D2NET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_D2NET +# endif +# define machine_is_d2net() (machine_arch_type == MACH_TYPE_D2NET) +#else +# define machine_is_d2net() (0) +#endif + +#ifdef CONFIG_MACH_BIGDISK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BIGDISK +# endif +# define machine_is_bigdisk() (machine_arch_type == MACH_TYPE_BIGDISK) +#else +# define machine_is_bigdisk() (0) +#endif + +#ifdef CONFIG_MACH_NOTALVISION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NOTALVISION +# endif +# define machine_is_notalvision() (machine_arch_type == MACH_TYPE_NOTALVISION) +#else +# define machine_is_notalvision() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_KBOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_KBOC +# endif +# define machine_is_omap3_kboc() (machine_arch_type == MACH_TYPE_OMAP3_KBOC) +#else +# define machine_is_omap3_kboc() (0) +#endif + +#ifdef CONFIG_MACH_CYCLONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CYCLONE +# endif +# define machine_is_cyclone() (machine_arch_type == MACH_TYPE_CYCLONE) +#else +# define machine_is_cyclone() (0) +#endif + +#ifdef CONFIG_MACH_NINJA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NINJA +# endif +# define machine_is_ninja() (machine_arch_type == MACH_TYPE_NINJA) +#else +# define machine_is_ninja() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G20EK_2MMC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G20EK_2MMC +# endif +# define machine_is_at91sam9g20ek_2mmc() (machine_arch_type == MACH_TYPE_AT91SAM9G20EK_2MMC) +#else +# define machine_is_at91sam9g20ek_2mmc() (0) +#endif + +#ifdef CONFIG_MACH_BCMRING +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCMRING +# endif +# define machine_is_bcmring() (machine_arch_type == MACH_TYPE_BCMRING) +#else +# define machine_is_bcmring() (0) +#endif + +#ifdef CONFIG_MACH_RESOL_DL2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RESOL_DL2 +# endif +# define machine_is_resol_dl2() (machine_arch_type == MACH_TYPE_RESOL_DL2) +#else +# define machine_is_resol_dl2() (0) +#endif + +#ifdef CONFIG_MACH_IFOSW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IFOSW +# endif +# define machine_is_ifosw() (machine_arch_type == MACH_TYPE_IFOSW) +#else +# define machine_is_ifosw() (0) +#endif + +#ifdef CONFIG_MACH_HTCRHODIUM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRHODIUM +# endif +# define machine_is_htcrhodium() (machine_arch_type == MACH_TYPE_HTCRHODIUM) +#else +# define machine_is_htcrhodium() (0) +#endif + +#ifdef CONFIG_MACH_HTCTOPAZ +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCTOPAZ +# endif +# define machine_is_htctopaz() (machine_arch_type == MACH_TYPE_HTCTOPAZ) +#else +# define machine_is_htctopaz() (0) +#endif + +#ifdef CONFIG_MACH_MATRIX504 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MATRIX504 +# endif +# define machine_is_matrix504() (machine_arch_type == MACH_TYPE_MATRIX504) +#else +# define machine_is_matrix504() (0) +#endif + +#ifdef CONFIG_MACH_MRFSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MRFSA +# endif +# define machine_is_mrfsa() (machine_arch_type == MACH_TYPE_MRFSA) +#else +# define machine_is_mrfsa() (0) +#endif + +#ifdef CONFIG_MACH_SC_P270 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SC_P270 +# endif +# define machine_is_sc_p270() (machine_arch_type == MACH_TYPE_SC_P270) +#else +# define machine_is_sc_p270() (0) +#endif + +#ifdef CONFIG_MACH_ATLAS5_EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ATLAS5_EVB +# endif +# define machine_is_atlas5_evb() (machine_arch_type == MACH_TYPE_ATLAS5_EVB) +#else +# define machine_is_atlas5_evb() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_LOBOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_LOBOX +# endif +# define machine_is_pelco_lobox() (machine_arch_type == MACH_TYPE_PELCO_LOBOX) +#else +# define machine_is_pelco_lobox() (0) +#endif + +#ifdef CONFIG_MACH_DILAX_PCU200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DILAX_PCU200 +# endif +# define machine_is_dilax_pcu200() (machine_arch_type == MACH_TYPE_DILAX_PCU200) +#else +# define machine_is_dilax_pcu200() (0) +#endif + +#ifdef CONFIG_MACH_LEONARDO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEONARDO +# endif +# define machine_is_leonardo() (machine_arch_type == MACH_TYPE_LEONARDO) +#else +# define machine_is_leonardo() (0) +#endif + +#ifdef CONFIG_MACH_ZORAN_APPROACH7 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZORAN_APPROACH7 +# endif +# define machine_is_zoran_approach7() (machine_arch_type == MACH_TYPE_ZORAN_APPROACH7) +#else +# define machine_is_zoran_approach7() (0) +#endif + +#ifdef CONFIG_MACH_DP6XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DP6XX +# endif +# define machine_is_dp6xx() (machine_arch_type == MACH_TYPE_DP6XX) +#else +# define machine_is_dp6xx() (0) +#endif + +#ifdef CONFIG_MACH_BCM2153_VESPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCM2153_VESPER +# endif +# define machine_is_bcm2153_vesper() (machine_arch_type == MACH_TYPE_BCM2153_VESPER) +#else +# define machine_is_bcm2153_vesper() (0) +#endif + +#ifdef CONFIG_MACH_MAHIMAHI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAHIMAHI +# endif +# define machine_is_mahimahi() (machine_arch_type == MACH_TYPE_MAHIMAHI) +#else +# define machine_is_mahimahi() (0) +#endif + +#ifdef CONFIG_MACH_CLICKC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CLICKC +# endif +# define machine_is_clickc() (machine_arch_type == MACH_TYPE_CLICKC) +#else +# define machine_is_clickc() (0) +#endif + +#ifdef CONFIG_MACH_ZB_GATEWAY +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ZB_GATEWAY +# endif +# define machine_is_zb_gateway() (machine_arch_type == MACH_TYPE_ZB_GATEWAY) +#else +# define machine_is_zb_gateway() (0) +#endif + +#ifdef CONFIG_MACH_TAZCARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZCARD +# endif +# define machine_is_tazcard() (machine_arch_type == MACH_TYPE_TAZCARD) +#else +# define machine_is_tazcard() (0) +#endif + +#ifdef CONFIG_MACH_TAZDEV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZDEV +# endif +# define machine_is_tazdev() (machine_arch_type == MACH_TYPE_TAZDEV) +#else +# define machine_is_tazdev() (0) +#endif + +#ifdef CONFIG_MACH_ANNAX_CB_ARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANNAX_CB_ARM +# endif +# define machine_is_annax_cb_arm() (machine_arch_type == MACH_TYPE_ANNAX_CB_ARM) +#else +# define machine_is_annax_cb_arm() (0) +#endif + +#ifdef CONFIG_MACH_ANNAX_DM3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANNAX_DM3 +# endif +# define machine_is_annax_dm3() (machine_arch_type == MACH_TYPE_ANNAX_DM3) +#else +# define machine_is_annax_dm3() (0) +#endif + +#ifdef CONFIG_MACH_CEREBRIC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CEREBRIC +# endif +# define machine_is_cerebric() (machine_arch_type == MACH_TYPE_CEREBRIC) +#else +# define machine_is_cerebric() (0) +#endif + +#ifdef CONFIG_MACH_ORCA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ORCA +# endif +# define machine_is_orca() (machine_arch_type == MACH_TYPE_ORCA) +#else +# define machine_is_orca() (0) +#endif + +#ifdef CONFIG_MACH_PC9260 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC9260 +# endif +# define machine_is_pc9260() (machine_arch_type == MACH_TYPE_PC9260) +#else +# define machine_is_pc9260() (0) +#endif + +#ifdef CONFIG_MACH_EMS285A +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EMS285A +# endif +# define machine_is_ems285a() (machine_arch_type == MACH_TYPE_EMS285A) +#else +# define machine_is_ems285a() (0) +#endif + +#ifdef CONFIG_MACH_GEC2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEC2410 +# endif +# define machine_is_gec2410() (machine_arch_type == MACH_TYPE_GEC2410) +#else +# define machine_is_gec2410() (0) +#endif + +#ifdef CONFIG_MACH_GEC2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GEC2440 +# endif +# define machine_is_gec2440() (machine_arch_type == MACH_TYPE_GEC2440) +#else +# define machine_is_gec2440() (0) +#endif + +#ifdef CONFIG_MACH_ARCH_MW903 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARCH_MW903 +# endif +# define machine_is_mw903() (machine_arch_type == MACH_TYPE_ARCH_MW903) +#else +# define machine_is_mw903() (0) +#endif + +#ifdef CONFIG_MACH_MW2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MW2440 +# endif +# define machine_is_mw2440() (machine_arch_type == MACH_TYPE_MW2440) +#else +# define machine_is_mw2440() (0) +#endif + +#ifdef CONFIG_MACH_ECAC2378 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECAC2378 +# endif +# define machine_is_ecac2378() (machine_arch_type == MACH_TYPE_ECAC2378) +#else +# define machine_is_ecac2378() (0) +#endif + +#ifdef CONFIG_MACH_TAZKIOSK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAZKIOSK +# endif +# define machine_is_tazkiosk() (machine_arch_type == MACH_TYPE_TAZKIOSK) +#else +# define machine_is_tazkiosk() (0) +#endif + +#ifdef CONFIG_MACH_WHITERABBIT_MCH +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WHITERABBIT_MCH +# endif +# define machine_is_whiterabbit_mch() (machine_arch_type == MACH_TYPE_WHITERABBIT_MCH) +#else +# define machine_is_whiterabbit_mch() (0) +#endif + +#ifdef CONFIG_MACH_SBOX9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SBOX9263 +# endif +# define machine_is_sbox9263() (machine_arch_type == MACH_TYPE_SBOX9263) +#else +# define machine_is_sbox9263() (0) +#endif + +#ifdef CONFIG_MACH_OREO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OREO +# endif +# define machine_is_oreo() (machine_arch_type == MACH_TYPE_OREO) +#else +# define machine_is_oreo() (0) +#endif + +#ifdef CONFIG_MACH_SMDK6442 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDK6442 +# endif +# define machine_is_smdk6442() (machine_arch_type == MACH_TYPE_SMDK6442) +#else +# define machine_is_smdk6442() (0) +#endif + +#ifdef CONFIG_MACH_OPENRD_BASE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENRD_BASE +# endif +# define machine_is_openrd_base() (machine_arch_type == MACH_TYPE_OPENRD_BASE) +#else +# define machine_is_openrd_base() (0) +#endif + +#ifdef CONFIG_MACH_INCREDIBLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INCREDIBLE +# endif +# define machine_is_incredible() (machine_arch_type == MACH_TYPE_INCREDIBLE) +#else +# define machine_is_incredible() (0) +#endif + +#ifdef CONFIG_MACH_INCREDIBLEC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INCREDIBLEC +# endif +# define machine_is_incrediblec() (machine_arch_type == MACH_TYPE_INCREDIBLEC) +#else +# define machine_is_incrediblec() (0) +#endif + +#ifdef CONFIG_MACH_HEROCT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HEROCT +# endif +# define machine_is_heroct() (machine_arch_type == MACH_TYPE_HEROCT) +#else +# define machine_is_heroct() (0) +#endif + +#ifdef CONFIG_MACH_MMNET1000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MMNET1000 +# endif +# define machine_is_mmnet1000() (machine_arch_type == MACH_TYPE_MMNET1000) +#else +# define machine_is_mmnet1000() (0) +#endif + +#ifdef CONFIG_MACH_DEVKIT8000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEVKIT8000 +# endif +# define machine_is_devkit8000() (machine_arch_type == MACH_TYPE_DEVKIT8000) +#else +# define machine_is_devkit8000() (0) +#endif + +#ifdef CONFIG_MACH_DEVKIT9000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DEVKIT9000 +# endif +# define machine_is_devkit9000() (machine_arch_type == MACH_TYPE_DEVKIT9000) +#else +# define machine_is_devkit9000() (0) +#endif + +#ifdef CONFIG_MACH_MX31TXTR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31TXTR +# endif +# define machine_is_mx31txtr() (machine_arch_type == MACH_TYPE_MX31TXTR) +#else +# define machine_is_mx31txtr() (0) +#endif + +#ifdef CONFIG_MACH_U380 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U380 +# endif +# define machine_is_u380() (machine_arch_type == MACH_TYPE_U380) +#else +# define machine_is_u380() (0) +#endif + +#ifdef CONFIG_MACH_HUALU_BOARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUALU_BOARD +# endif +# define machine_is_oamp3_hualu() (machine_arch_type == MACH_TYPE_HUALU_BOARD) +#else +# define machine_is_oamp3_hualu() (0) +#endif + +#ifdef CONFIG_MACH_NPCMX50 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NPCMX50 +# endif +# define machine_is_npcmx50() (machine_arch_type == MACH_TYPE_NPCMX50) +#else +# define machine_is_npcmx50() (0) +#endif + +#ifdef CONFIG_MACH_MX51_LANGE51 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_LANGE51 +# endif +# define machine_is_mx51_lange51() (machine_arch_type == MACH_TYPE_MX51_LANGE51) +#else +# define machine_is_mx51_lange51() (0) +#endif + +#ifdef CONFIG_MACH_MX51_LANGE52 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_LANGE52 +# endif +# define machine_is_mx51_lange52() (machine_arch_type == MACH_TYPE_MX51_LANGE52) +#else +# define machine_is_mx51_lange52() (0) +#endif + +#ifdef CONFIG_MACH_RIOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RIOM +# endif +# define machine_is_riom() (machine_arch_type == MACH_TYPE_RIOM) +#else +# define machine_is_riom() (0) +#endif + +#ifdef CONFIG_MACH_COMCAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMCAS +# endif +# define machine_is_comcas() (machine_arch_type == MACH_TYPE_COMCAS) +#else +# define machine_is_comcas() (0) +#endif + +#ifdef CONFIG_MACH_WSI_MX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WSI_MX27 +# endif +# define machine_is_wsi_mx27() (machine_arch_type == MACH_TYPE_WSI_MX27) +#else +# define machine_is_wsi_mx27() (0) +#endif + +#ifdef CONFIG_MACH_CM_T35 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CM_T35 +# endif +# define machine_is_cm_t35() (machine_arch_type == MACH_TYPE_CM_T35) +#else +# define machine_is_cm_t35() (0) +#endif + +#ifdef CONFIG_MACH_NET2BIG +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET2BIG +# endif +# define machine_is_net2big() (machine_arch_type == MACH_TYPE_NET2BIG) +#else +# define machine_is_net2big() (0) +#endif + +#ifdef CONFIG_MACH_MOTOROLA_A1600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOTOROLA_A1600 +# endif +# define machine_is_motorola_a1600() (machine_arch_type == MACH_TYPE_MOTOROLA_A1600) +#else +# define machine_is_motorola_a1600() (0) +#endif + +#ifdef CONFIG_MACH_IGEP0020 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGEP0020 +# endif +# define machine_is_igep0020() (machine_arch_type == MACH_TYPE_IGEP0020) +#else +# define machine_is_igep0020() (0) +#endif + +#ifdef CONFIG_MACH_IGEP0010 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IGEP0010 +# endif +# define machine_is_igep0010() (machine_arch_type == MACH_TYPE_IGEP0010) +#else +# define machine_is_igep0010() (0) +#endif + +#ifdef CONFIG_MACH_MV6281GTWGE2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MV6281GTWGE2 +# endif +# define machine_is_mv6281gtwge2() (machine_arch_type == MACH_TYPE_MV6281GTWGE2) +#else +# define machine_is_mv6281gtwge2() (0) +#endif + +#ifdef CONFIG_MACH_SCAT100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCAT100 +# endif +# define machine_is_scat100() (machine_arch_type == MACH_TYPE_SCAT100) +#else +# define machine_is_scat100() (0) +#endif + +#ifdef CONFIG_MACH_SANMINA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SANMINA +# endif +# define machine_is_sanmina() (machine_arch_type == MACH_TYPE_SANMINA) +#else +# define machine_is_sanmina() (0) +#endif + +#ifdef CONFIG_MACH_MOMENTO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MOMENTO +# endif +# define machine_is_momento() (machine_arch_type == MACH_TYPE_MOMENTO) +#else +# define machine_is_momento() (0) +#endif + +#ifdef CONFIG_MACH_NUC9XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC9XX +# endif +# define machine_is_nuc9xx() (machine_arch_type == MACH_TYPE_NUC9XX) +#else +# define machine_is_nuc9xx() (0) +#endif + +#ifdef CONFIG_MACH_NUC910EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC910EVB +# endif +# define machine_is_nuc910evb() (machine_arch_type == MACH_TYPE_NUC910EVB) +#else +# define machine_is_nuc910evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC920EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC920EVB +# endif +# define machine_is_nuc920evb() (machine_arch_type == MACH_TYPE_NUC920EVB) +#else +# define machine_is_nuc920evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC950EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC950EVB +# endif +# define machine_is_nuc950evb() (machine_arch_type == MACH_TYPE_NUC950EVB) +#else +# define machine_is_nuc950evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC945EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC945EVB +# endif +# define machine_is_nuc945evb() (machine_arch_type == MACH_TYPE_NUC945EVB) +#else +# define machine_is_nuc945evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC960EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC960EVB +# endif +# define machine_is_nuc960evb() (machine_arch_type == MACH_TYPE_NUC960EVB) +#else +# define machine_is_nuc960evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC932EVB +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC932EVB +# endif +# define machine_is_nuc932evb() (machine_arch_type == MACH_TYPE_NUC932EVB) +#else +# define machine_is_nuc932evb() (0) +#endif + +#ifdef CONFIG_MACH_NUC900 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NUC900 +# endif +# define machine_is_nuc900() (machine_arch_type == MACH_TYPE_NUC900) +#else +# define machine_is_nuc900() (0) +#endif + +#ifdef CONFIG_MACH_SD1SOC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SD1SOC +# endif +# define machine_is_sd1soc() (machine_arch_type == MACH_TYPE_SD1SOC) +#else +# define machine_is_sd1soc() (0) +#endif + +#ifdef CONFIG_MACH_LN2440BC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LN2440BC +# endif +# define machine_is_ln2440bc() (machine_arch_type == MACH_TYPE_LN2440BC) +#else +# define machine_is_ln2440bc() (0) +#endif + +#ifdef CONFIG_MACH_RSBC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RSBC +# endif +# define machine_is_rsbc() (machine_arch_type == MACH_TYPE_RSBC) +#else +# define machine_is_rsbc() (0) +#endif + +#ifdef CONFIG_MACH_OPENRD_CLIENT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENRD_CLIENT +# endif +# define machine_is_openrd_client() (machine_arch_type == MACH_TYPE_OPENRD_CLIENT) +#else +# define machine_is_openrd_client() (0) +#endif + +#ifdef CONFIG_MACH_HPIPAQ11X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HPIPAQ11X +# endif +# define machine_is_hpipaq11x() (machine_arch_type == MACH_TYPE_HPIPAQ11X) +#else +# define machine_is_hpipaq11x() (0) +#endif + +#ifdef CONFIG_MACH_WAYLAND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WAYLAND +# endif +# define machine_is_wayland() (machine_arch_type == MACH_TYPE_WAYLAND) +#else +# define machine_is_wayland() (0) +#endif + +#ifdef CONFIG_MACH_ACNBSX102 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACNBSX102 +# endif +# define machine_is_acnbsx102() (machine_arch_type == MACH_TYPE_ACNBSX102) +#else +# define machine_is_acnbsx102() (0) +#endif + +#ifdef CONFIG_MACH_HWAT91 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HWAT91 +# endif +# define machine_is_hwat91() (machine_arch_type == MACH_TYPE_HWAT91) +#else +# define machine_is_hwat91() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9263CS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9263CS +# endif +# define machine_is_at91sam9263cs() (machine_arch_type == MACH_TYPE_AT91SAM9263CS) +#else +# define machine_is_at91sam9263cs() (0) +#endif + +#ifdef CONFIG_MACH_CSB732 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSB732 +# endif +# define machine_is_csb732() (machine_arch_type == MACH_TYPE_CSB732) +#else +# define machine_is_csb732() (0) +#endif + +#ifdef CONFIG_MACH_U8500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U8500 +# endif +# define machine_is_u8500() (machine_arch_type == MACH_TYPE_U8500) +#else +# define machine_is_u8500() (0) +#endif + +#ifdef CONFIG_MACH_HUQIU +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUQIU +# endif +# define machine_is_huqiu() (machine_arch_type == MACH_TYPE_HUQIU) +#else +# define machine_is_huqiu() (0) +#endif + +#ifdef CONFIG_MACH_MX51_KUNLUN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX51_KUNLUN +# endif +# define machine_is_mx51_kunlun() (machine_arch_type == MACH_TYPE_MX51_KUNLUN) +#else +# define machine_is_mx51_kunlun() (0) +#endif + +#ifdef CONFIG_MACH_PMT1G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PMT1G +# endif +# define machine_is_pmt1g() (machine_arch_type == MACH_TYPE_PMT1G) +#else +# define machine_is_pmt1g() (0) +#endif + +#ifdef CONFIG_MACH_HTCELF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCELF +# endif +# define machine_is_htcelf() (machine_arch_type == MACH_TYPE_HTCELF) +#else +# define machine_is_htcelf() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO420 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO420 +# endif +# define machine_is_armadillo420() (machine_arch_type == MACH_TYPE_ARMADILLO420) +#else +# define machine_is_armadillo420() (0) +#endif + +#ifdef CONFIG_MACH_ARMADILLO440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARMADILLO440 +# endif +# define machine_is_armadillo440() (machine_arch_type == MACH_TYPE_ARMADILLO440) +#else +# define machine_is_armadillo440() (0) +#endif + +#ifdef CONFIG_MACH_U_CHIP_DUAL_ARM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_U_CHIP_DUAL_ARM +# endif +# define machine_is_u_chip_dual_arm() (machine_arch_type == MACH_TYPE_U_CHIP_DUAL_ARM) +#else +# define machine_is_u_chip_dual_arm() (0) +#endif + +#ifdef CONFIG_MACH_CSR_BDB3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CSR_BDB3 +# endif +# define machine_is_csr_bdb3() (machine_arch_type == MACH_TYPE_CSR_BDB3) +#else +# define machine_is_csr_bdb3() (0) +#endif + +#ifdef CONFIG_MACH_DOLBY_CAT1018 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DOLBY_CAT1018 +# endif +# define machine_is_dolby_cat1018() (machine_arch_type == MACH_TYPE_DOLBY_CAT1018) +#else +# define machine_is_dolby_cat1018() (0) +#endif + +#ifdef CONFIG_MACH_HY9307 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY9307 +# endif +# define machine_is_hy9307() (machine_arch_type == MACH_TYPE_HY9307) +#else +# define machine_is_hy9307() (0) +#endif + +#ifdef CONFIG_MACH_A_ES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_A_ES +# endif +# define machine_is_aspire_easystore() (machine_arch_type == MACH_TYPE_A_ES) +#else +# define machine_is_aspire_easystore() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_IRIF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_IRIF +# endif +# define machine_is_davinci_irif() (machine_arch_type == MACH_TYPE_DAVINCI_IRIF) +#else +# define machine_is_davinci_irif() (0) +#endif + +#ifdef CONFIG_MACH_AGAMA9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AGAMA9263 +# endif +# define machine_is_agama9263() (machine_arch_type == MACH_TYPE_AGAMA9263) +#else +# define machine_is_agama9263() (0) +#endif + +#ifdef CONFIG_MACH_MARVELL_JASPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MARVELL_JASPER +# endif +# define machine_is_marvell_jasper() (machine_arch_type == MACH_TYPE_MARVELL_JASPER) +#else +# define machine_is_marvell_jasper() (0) +#endif + +#ifdef CONFIG_MACH_FLINT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FLINT +# endif +# define machine_is_flint() (machine_arch_type == MACH_TYPE_FLINT) +#else +# define machine_is_flint() (0) +#endif + +#ifdef CONFIG_MACH_TAVOREVB3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TAVOREVB3 +# endif +# define machine_is_tavorevb3() (machine_arch_type == MACH_TYPE_TAVOREVB3) +#else +# define machine_is_tavorevb3() (0) +#endif + +#ifdef CONFIG_MACH_SCH_M490 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SCH_M490 +# endif +# define machine_is_sch_m490() (machine_arch_type == MACH_TYPE_SCH_M490) +#else +# define machine_is_sch_m490() (0) +#endif + +#ifdef CONFIG_MACH_RBL01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RBL01 +# endif +# define machine_is_rbl01() (machine_arch_type == MACH_TYPE_RBL01) +#else +# define machine_is_rbl01() (0) +#endif + +#ifdef CONFIG_MACH_OMNIFI +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMNIFI +# endif +# define machine_is_omnifi() (machine_arch_type == MACH_TYPE_OMNIFI) +#else +# define machine_is_omnifi() (0) +#endif + +#ifdef CONFIG_MACH_OTAVALO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OTAVALO +# endif +# define machine_is_otavalo() (machine_arch_type == MACH_TYPE_OTAVALO) +#else +# define machine_is_otavalo() (0) +#endif + +#ifdef CONFIG_MACH_SIENNA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIENNA +# endif +# define machine_is_sienna() (machine_arch_type == MACH_TYPE_SIENNA) +#else +# define machine_is_sienna() (0) +#endif + +#ifdef CONFIG_MACH_HTC_EXCALIBUR_S620 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_EXCALIBUR_S620 +# endif +# define machine_is_htc_excalibur_s620() (machine_arch_type == MACH_TYPE_HTC_EXCALIBUR_S620) +#else +# define machine_is_htc_excalibur_s620() (0) +#endif + +#ifdef CONFIG_MACH_HTC_OPAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTC_OPAL +# endif +# define machine_is_htc_opal() (machine_arch_type == MACH_TYPE_HTC_OPAL) +#else +# define machine_is_htc_opal() (0) +#endif + +#ifdef CONFIG_MACH_TOUCHBOOK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TOUCHBOOK +# endif +# define machine_is_touchbook() (machine_arch_type == MACH_TYPE_TOUCHBOOK) +#else +# define machine_is_touchbook() (0) +#endif + +#ifdef CONFIG_MACH_LATTE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LATTE +# endif +# define machine_is_latte() (machine_arch_type == MACH_TYPE_LATTE) +#else +# define machine_is_latte() (0) +#endif + +#ifdef CONFIG_MACH_XA200 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_XA200 +# endif +# define machine_is_xa200() (machine_arch_type == MACH_TYPE_XA200) +#else +# define machine_is_xa200() (0) +#endif + +#ifdef CONFIG_MACH_NIMROD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NIMROD +# endif +# define machine_is_nimrod() (machine_arch_type == MACH_TYPE_NIMROD) +#else +# define machine_is_nimrod() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9215_3G +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9215_3G +# endif +# define machine_is_cc9p9215_3g() (machine_arch_type == MACH_TYPE_CC9P9215_3G) +#else +# define machine_is_cc9p9215_3g() (0) +#endif + +#ifdef CONFIG_MACH_CC9P9215_3GJS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CC9P9215_3GJS +# endif +# define machine_is_cc9p9215_3gjs() (machine_arch_type == MACH_TYPE_CC9P9215_3GJS) +#else +# define machine_is_cc9p9215_3gjs() (0) +#endif + +#ifdef CONFIG_MACH_TK71 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TK71 +# endif +# define machine_is_tk71() (machine_arch_type == MACH_TYPE_TK71) +#else +# define machine_is_tk71() (0) +#endif + +#ifdef CONFIG_MACH_COMHAM3525 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_COMHAM3525 +# endif +# define machine_is_comham3525() (machine_arch_type == MACH_TYPE_COMHAM3525) +#else +# define machine_is_comham3525() (0) +#endif + +#ifdef CONFIG_MACH_MX31EREBUS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MX31EREBUS +# endif +# define machine_is_mx31erebus() (machine_arch_type == MACH_TYPE_MX31EREBUS) +#else +# define machine_is_mx31erebus() (0) +#endif + +#ifdef CONFIG_MACH_MCARDMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCARDMX27 +# endif +# define machine_is_mcardmx27() (machine_arch_type == MACH_TYPE_MCARDMX27) +#else +# define machine_is_mcardmx27() (0) +#endif + +#ifdef CONFIG_MACH_PARADISE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PARADISE +# endif +# define machine_is_paradise() (machine_arch_type == MACH_TYPE_PARADISE) +#else +# define machine_is_paradise() (0) +#endif + +#ifdef CONFIG_MACH_TIDE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TIDE +# endif +# define machine_is_tide() (machine_arch_type == MACH_TYPE_TIDE) +#else +# define machine_is_tide() (0) +#endif + +#ifdef CONFIG_MACH_WZL2440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_WZL2440 +# endif +# define machine_is_wzl2440() (machine_arch_type == MACH_TYPE_WZL2440) +#else +# define machine_is_wzl2440() (0) +#endif + +#ifdef CONFIG_MACH_SDRDEMO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SDRDEMO +# endif +# define machine_is_sdrdemo() (machine_arch_type == MACH_TYPE_SDRDEMO) +#else +# define machine_is_sdrdemo() (0) +#endif + +#ifdef CONFIG_MACH_ETHERCAN2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ETHERCAN2 +# endif +# define machine_is_ethercan2() (machine_arch_type == MACH_TYPE_ETHERCAN2) +#else +# define machine_is_ethercan2() (0) +#endif + +#ifdef CONFIG_MACH_ECMIMG20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ECMIMG20 +# endif +# define machine_is_ecmimg20() (machine_arch_type == MACH_TYPE_ECMIMG20) +#else +# define machine_is_ecmimg20() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_DRAGON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_DRAGON +# endif +# define machine_is_omap_dragon() (machine_arch_type == MACH_TYPE_OMAP_DRAGON) +#else +# define machine_is_omap_dragon() (0) +#endif + +#ifdef CONFIG_MACH_HALO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HALO +# endif +# define machine_is_halo() (machine_arch_type == MACH_TYPE_HALO) +#else +# define machine_is_halo() (0) +#endif + +#ifdef CONFIG_MACH_HUANGSHAN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HUANGSHAN +# endif +# define machine_is_huangshan() (machine_arch_type == MACH_TYPE_HUANGSHAN) +#else +# define machine_is_huangshan() (0) +#endif + +#ifdef CONFIG_MACH_VL_MA2SC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VL_MA2SC +# endif +# define machine_is_vl_ma2sc() (machine_arch_type == MACH_TYPE_VL_MA2SC) +#else +# define machine_is_vl_ma2sc() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_RC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_RC +# endif +# define machine_is_raumfeld_rc() (machine_arch_type == MACH_TYPE_RAUMFELD_RC) +#else +# define machine_is_raumfeld_rc() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_CONNECTOR +# endif +# define machine_is_raumfeld_connector() (machine_arch_type == MACH_TYPE_RAUMFELD_CONNECTOR) +#else +# define machine_is_raumfeld_connector() (0) +#endif + +#ifdef CONFIG_MACH_RAUMFELD_SPEAKER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_RAUMFELD_SPEAKER +# endif +# define machine_is_raumfeld_speaker() (machine_arch_type == MACH_TYPE_RAUMFELD_SPEAKER) +#else +# define machine_is_raumfeld_speaker() (0) +#endif + +#ifdef CONFIG_MACH_MULTIBUS_MASTER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIBUS_MASTER +# endif +# define machine_is_multibus_master() (machine_arch_type == MACH_TYPE_MULTIBUS_MASTER) +#else +# define machine_is_multibus_master() (0) +#endif + +#ifdef CONFIG_MACH_MULTIBUS_PBK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MULTIBUS_PBK +# endif +# define machine_is_multibus_pbk() (machine_arch_type == MACH_TYPE_MULTIBUS_PBK) +#else +# define machine_is_multibus_pbk() (0) +#endif + +#ifdef CONFIG_MACH_TNETV107X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNETV107X +# endif +# define machine_is_tnetv107x() (machine_arch_type == MACH_TYPE_TNETV107X) +#else +# define machine_is_tnetv107x() (0) +#endif + /* * These have not yet been registered */ -- cgit v1.2.3 From 5da71efa18e8b4eac9afd8bfa13e3c7e7ddde1d0 Mon Sep 17 00:00:00 2001 From: Eric Millbrandt Date: Thu, 3 Sep 2009 08:09:44 -0500 Subject: Reset i2c slave devices during init on mpc5xxx cpus Reset any i2c devices that may have been interrupted during a system reset. Normally this would be accomplished by clocking the line until SCL and SDA are released and then sending a start condtiion (From an Atmel datasheet). There is no direct access to the i2c pins so instead create start commands through the i2c interface. Send a start command then delay for the SDA Hold time, repeat this by disabling/enabling the bus a total of 9 times. Signed-off-by: Eric Millbrandt --- include/configs/galaxy5200.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index a5b5a03a9a2..f4b520d39f2 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -110,6 +110,7 @@ #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ #define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_INIT_MPC5XXX /* Reset devices on i2c bus */ /* * EEPROM CAT24WC32 configuration -- cgit v1.2.3 From 2abbd31da6d900473ed678ca50789ee58bc9bb00 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 1 Sep 2009 22:01:54 -0500 Subject: ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_ddr_sdram.h | 1 - include/asm-ppc/immap_85xx.h | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index c2e5aeebcbf..69b857b41cd 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -110,7 +110,6 @@ typedef struct fsl_ddr_cfg_regs_s { unsigned int timing_cfg_5; unsigned int ddr_zq_cntl; unsigned int ddr_wrlvl_cntl; - unsigned int ddr_pd_cntl; unsigned int ddr_sr_cntr; unsigned int ddr_sdram_rcw_1; unsigned int ddr_sdram_rcw_2; diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 375d80444f5..e7d412dba23 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -132,7 +132,7 @@ typedef struct ccsr_ddr { char reg8_1a[8]; uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/ uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/ - uint ddr_pd_cntl; /* 0x2178 - DDR pre-drive conditioning control*/ + char reg8_1aa[4]; uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */ uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */ uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */ -- cgit v1.2.3 From 26f4cdba6b51deab4ec99d60be381244068ef950 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 14 Aug 2009 13:37:54 -0500 Subject: 85xx: Add support for setting IVORs to fixed offset defaults In future Book-E implementations IVORs will most likely go away and be replaced with fixed offsets. The IVPR will continue to exist to allow for relocation of the interrupt vectors. This code adds support to setup the IVORs as their fixed offset values per the ISA 2.06 spec when we transition from u-boot to another OS either via 'bootm' or a cpu release. Signed-off-by: Kumar Gala --- include/asm-ppc/processor.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index dcaf8c030a3..78ef4187f23 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -468,6 +468,16 @@ #define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */ #define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */ #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ +#define SPRN_IVOR38 0x1b0 /* Interrupt Vector Offset Register 38 */ +#define SPRN_IVOR39 0x1b1 /* Interrupt Vector Offset Register 39 */ +#define SPRN_IVOR40 0x1b2 /* Interrupt Vector Offset Register 40 */ +#define SPRN_IVOR41 0x1b3 /* Interrupt Vector Offset Register 41 */ +#define SPRN_GIVOR2 0x1b8 /* Guest Interrupt Vector Offset Register 2 */ +#define SPRN_GIVOR3 0x1b9 /* Guest Interrupt Vector Offset Register 3 */ +#define SPRN_GIVOR4 0x1ba /* Guest Interrupt Vector Offset Register 4 */ +#define SPRN_GIVOR8 0x1bb /* Guest Interrupt Vector Offset Register 8 */ +#define SPRN_GIVOR13 0x1bc /* Guest Interrupt Vector Offset Register 13 */ +#define SPRN_GIVOR14 0x1bd /* Guest Interrupt Vector Offset Register 14 */ /* e500 definitions */ #define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ @@ -513,6 +523,8 @@ #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ +#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */ +#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */ #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ #define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ -- cgit v1.2.3 From c2287af1552bd630956568d3957c370f86801b7d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 3 Sep 2009 08:20:24 -0500 Subject: ppc/85xx: Add a simple function to search the TLB Allow us to search the TLB array based on an address. This is useful if we want to change an entry but dont know where it happens to be located. For example, the boot page mapping we use on MP or the flash TLB that we change the WIMGE settings for after we've relocated. Signed-off-by: Kumar Gala --- include/asm-ppc/mmu.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index fa92b90c337..eda2959b7d0 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -387,8 +387,10 @@ extern void print_bats(void); * FSL Book-E support */ -#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000) -#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000) +#define MAS0_TLBSEL_MSK 0x30000000 +#define MAS0_TLBSEL(x) ((x << 28) & MAS0_TLBSEL_MSK) +#define MAS0_ESEL_MSK 0x0FFF0000 +#define MAS0_ESEL(x) ((x << 16) & MAS0_ESEL_MSK) #define MAS0_NV(x) ((x) & 0x00000FFF) #define MAS1_VALID 0x80000000 @@ -474,6 +476,7 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn, extern void disable_tlb(u8 esel); extern void invalidate_tlb(u8 tlb); extern void init_tlbs(void); +extern int find_tlb_idx(void *addr, u8 tlbsel); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); -- cgit v1.2.3 From 3e7b6c1f2db5ec31f9e7dbc3e0cbca602167a46a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 2 Sep 2009 09:03:08 -0500 Subject: ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host Refactor the code into a simple bitmask lookup table that determines if a given PCI controller is enabled and if its in host/root-complex or agent/end-point mode. Each processor in the PQ3/MPC86xx family specified different encodings for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals. Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_pci.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index f625d19ee42..b9972dabe37 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -20,6 +20,11 @@ #ifndef __FSL_PCI_H_ #define __FSL_PCI_H_ +#include + +int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent); +int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel); + void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); void ft_fsl_pci_setup(void *blob, const char *pci_alias, -- cgit v1.2.3 From 58442dc01e47cc8ce42af4f29486a34cad60b9d2 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Wed, 2 Sep 2009 13:35:21 +0530 Subject: ppc/85xx,86xx: Handling Unknown SOC version Incase the system is detected with Unknown SVR, let the system boot with a default value and a proper message. Now with dynamic detection of SOC properties from SVR, this is necessary to prevent a crash. Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- include/asm-ppc/processor.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 78ef4187f23..0a4c66c9d9e 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1034,6 +1034,8 @@ #define SVR_8641 0x809000 #define SVR_8641D 0x809001 +#define SVR_Unknown 0xFFFFFF + #define _GLOBAL(n)\ .globl n;\ n: -- cgit v1.2.3 From c8355b9d9f778bd12ee19c8f34d88e13758a4efd Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Wed, 2 Sep 2009 17:24:57 +0200 Subject: amcc-common.h: Use filenames from environment variables for update procedure. Using a separate "u-boot" environment variable allows to easily specify different filenames for the update procedure. This is also in line with many other board configurations defining an "update" script. Signed-off-by: Detlev Zundel Acked-by: Wolfgang Denk Signed-off-by: Stefan Roese --- include/configs/amcc-common.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index a2b7ee8cfec..51128a3b566 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2008 + * (C) Copyright 2008, 2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * Common configuration options for all AMCC boards @@ -271,7 +271,8 @@ "bootm ${kernel_addr_r}\0" #define CONFIG_AMCC_DEF_ENV_NOR_UPD \ - "load=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "load=tftp 200000 ${u-boot}\0" \ "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \ "era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \ "cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize};" \ @@ -279,7 +280,8 @@ "upd=run load update\0" \ #define CONFIG_AMCC_DEF_ENV_NAND_UPD \ - "nload=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot-nand.bin\0" \ + "u-boot-nand=" xstr(CONFIG_HOSTNAME) "/u-boot-nand.bin\0" \ + "nload=tftp 200000 ${u-boot-nand}\0" \ "nupdate=nand erase 0 100000;nand write 200000 0 100000;" \ "setenv filesize;saveenv\0" \ "nupd=run nload nupdate\0" -- cgit v1.2.3 From 82379b5564819e62624a3c58fbc43f1afedf4f5f Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Mon, 7 Sep 2009 17:00:41 +0200 Subject: ppc4xx: Add CONFIG_PCI_4xx_PTM_OVERWRITE to some esd 4xx boards Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- include/configs/CPCI405.h | 2 ++ include/configs/CPCI4052.h | 2 ++ include/configs/CPCI405AB.h | 2 ++ include/configs/CPCI405DT.h | 2 ++ include/configs/PMC405.h | 2 ++ include/configs/PMC405DE.h | 2 ++ 6 files changed, 12 insertions(+) (limited to 'include') diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index f032a8d7ab2..fca6de0c6bc 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -171,6 +171,8 @@ #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ + /*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index daa3c197d55..fd045660897 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -192,6 +192,8 @@ #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ + /*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 41795a77264..d718ed40a3d 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -189,6 +189,8 @@ #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ + /*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 233320878c0..09df47082b6 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -193,6 +193,8 @@ #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ + /*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index a9e71346e0f..87ea7b6d47e 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -181,6 +181,8 @@ #define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */ #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ +#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ + /* * Start addresses for the final memory configuration * (Set up by the startup code) diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 5232745a0a8..7198632c36b 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -164,6 +164,8 @@ #define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */ #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ +#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ + /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is -- cgit v1.2.3 From 449609f5b11cce6beba7338bc4ce0f3345376a0b Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Sun, 16 Aug 2009 05:28:19 +0530 Subject: tools: mkimage: Fixed build warnings uninitialized retval variable warning fixed crc32 APIs moved to crc.h (newly added) and build warnings fixed Signed-off-by: Prafulla Wadaskar Signed-off-by: Wolfgang Denk --- include/common.h | 4 +--- include/u-boot/crc.h | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 3 deletions(-) create mode 100644 include/u-boot/crc.h (limited to 'include') diff --git a/include/common.h b/include/common.h index 35f12c0b034..f7c93bf5a6d 100644 --- a/include/common.h +++ b/include/common.h @@ -624,9 +624,7 @@ int vsprintf(char *buf, const char *fmt, va_list args); char * strmhz(char *buf, long hz); /* lib_generic/crc32.c */ -uint32_t crc32 (uint32_t, const unsigned char *, uint); -uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint); -uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint); +#include /* common/console.c */ int console_init_f(void); /* Before relocation; uses the serial stuff */ diff --git a/include/u-boot/crc.h b/include/u-boot/crc.h new file mode 100644 index 00000000000..61bce679145 --- /dev/null +++ b/include/u-boot/crc.h @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _UBOOT_CRC_H +#define _UBOOT_CRC_H + +/* lib_generic/crc32.c */ +uint32_t crc32 (uint32_t, const unsigned char *, uint); +uint32_t crc32_wd (uint32_t, const unsigned char *, uint, uint); +uint32_t crc32_no_comp (uint32_t, const unsigned char *, uint); + +#endif /* _UBOOT_CRC_H */ -- cgit v1.2.3 From 3a2003f61ee79ac53d20c24cc896c2637a2dfc24 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 19 Aug 2009 11:42:56 +0200 Subject: tools/mkimage: fix compiler warnings, use "const" This fixes some compiler warnings: tools/default_image.c:141: warning: initialization from incompatible pointer type tools/fit_image.c:202: warning: initialization from incompatible pointer type and changes to code to use "const" attributes in a few places where it's appropriate. Signed-off-by: Wolfgang Denk --- include/image.h | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/include/image.h b/include/image.h index beb3a16cd1f..a62669fc63c 100644 --- a/include/image.h +++ b/include/image.h @@ -333,7 +333,7 @@ static inline uint32_t image_get_header_size (void) } #define image_get_hdr_l(f) \ - static inline uint32_t image_get_##f(image_header_t *hdr) \ + static inline uint32_t image_get_##f(const image_header_t *hdr) \ { \ return uimage_to_cpu (hdr->ih_##f); \ } @@ -346,7 +346,7 @@ image_get_hdr_l (ep); /* image_get_ep */ image_get_hdr_l (dcrc); /* image_get_dcrc */ #define image_get_hdr_b(f) \ - static inline uint8_t image_get_##f(image_header_t *hdr) \ + static inline uint8_t image_get_##f(const image_header_t *hdr) \ { \ return hdr->ih_##f; \ } @@ -355,12 +355,12 @@ image_get_hdr_b (arch); /* image_get_arch */ image_get_hdr_b (type); /* image_get_type */ image_get_hdr_b (comp); /* image_get_comp */ -static inline char *image_get_name (image_header_t *hdr) +static inline char *image_get_name (const image_header_t *hdr) { return (char *)hdr->ih_name; } -static inline uint32_t image_get_data_size (image_header_t *hdr) +static inline uint32_t image_get_data_size (const image_header_t *hdr) { return image_get_size (hdr); } @@ -376,16 +376,16 @@ static inline uint32_t image_get_data_size (image_header_t *hdr) * returns: * image payload data start address */ -static inline ulong image_get_data (image_header_t *hdr) +static inline ulong image_get_data (const image_header_t *hdr) { return ((ulong)hdr + image_get_header_size ()); } -static inline uint32_t image_get_image_size (image_header_t *hdr) +static inline uint32_t image_get_image_size (const image_header_t *hdr) { return (image_get_size (hdr) + image_get_header_size ()); } -static inline ulong image_get_image_end (image_header_t *hdr) +static inline ulong image_get_image_end (const image_header_t *hdr) { return ((ulong)hdr + image_get_image_size (hdr)); } @@ -418,8 +418,8 @@ static inline void image_set_name (image_header_t *hdr, const char *name) strncpy (image_get_name (hdr), name, IH_NMLEN); } -int image_check_hcrc (image_header_t *hdr); -int image_check_dcrc (image_header_t *hdr); +int image_check_hcrc (const image_header_t *hdr); +int image_check_dcrc (const image_header_t *hdr); #ifndef USE_HOSTCC int getenv_yesno (char *var); ulong getenv_bootm_low(void); @@ -427,31 +427,31 @@ phys_size_t getenv_bootm_size(void); void memmove_wd (void *to, void *from, size_t len, ulong chunksz); #endif -static inline int image_check_magic (image_header_t *hdr) +static inline int image_check_magic (const image_header_t *hdr) { return (image_get_magic (hdr) == IH_MAGIC); } -static inline int image_check_type (image_header_t *hdr, uint8_t type) +static inline int image_check_type (const image_header_t *hdr, uint8_t type) { return (image_get_type (hdr) == type); } -static inline int image_check_arch (image_header_t *hdr, uint8_t arch) +static inline int image_check_arch (const image_header_t *hdr, uint8_t arch) { return (image_get_arch (hdr) == arch); } -static inline int image_check_os (image_header_t *hdr, uint8_t os) +static inline int image_check_os (const image_header_t *hdr, uint8_t os) { return (image_get_os (hdr) == os); } -ulong image_multi_count (image_header_t *hdr); -void image_multi_getimg (image_header_t *hdr, ulong idx, +ulong image_multi_count (const image_header_t *hdr); +void image_multi_getimg (const image_header_t *hdr, ulong idx, ulong *data, ulong *len); -void image_print_contents (image_header_t *hdr); +void image_print_contents (const void *hdr); #ifndef USE_HOSTCC -static inline int image_check_target_arch (image_header_t *hdr) +static inline int image_check_target_arch (const image_header_t *hdr) { #if defined(__ARM__) if (!image_check_arch (hdr, IH_ARCH_ARM)) -- cgit v1.2.3 From f666dea8ab215c76c3c2a077ad299f90dd1ace7c Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 7 Sep 2009 14:59:07 +0530 Subject: mkimage: Make genimg_print_size() global Currently it is used by image.c only, but the the function can be used to support additional mkimage types like for example kwbimage, so make this function globally visible. Signed-off-by: Prafulla Wadaskar Edited commit message. Signed-off-by: Wolfgang Denk --- include/image.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/image.h b/include/image.h index a62669fc63c..4a7bf7820a8 100644 --- a/include/image.h +++ b/include/image.h @@ -292,6 +292,7 @@ int genimg_get_os_id (const char *name); int genimg_get_arch_id (const char *name); int genimg_get_type_id (const char *name); int genimg_get_comp_id (const char *name); +void genimg_print_size (uint32_t size); #ifndef USE_HOSTCC /* Image format types, returned by _get_format() routine */ -- cgit v1.2.3 From b029dddc9ae958b1ccf875649f52c6db396a742d Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 7 Sep 2009 14:59:08 +0530 Subject: mkimage: Make table_entry code global - make get_table_entry_id() global - make get_table_entry_name() global - move struct table_entry to image.h Currently this code is used by image.c only. This patch makes this API global so it can be used by other parts of code, too. Signed-off-by: Prafulla Wadaskar Acked-by: Ron Lee Edit comments and commit message. Signed-off-by: Wolfgang Denk --- include/image.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'include') diff --git a/include/image.h b/include/image.h index 4a7bf7820a8..d4cbf8c7093 100644 --- a/include/image.h +++ b/include/image.h @@ -284,6 +284,30 @@ typedef struct bootm_headers { #define uimage_to_cpu(x) be32_to_cpu(x) #define cpu_to_uimage(x) cpu_to_be32(x) +/* + * Translation table for entries of a specific type; used by + * get_table_entry_id() and get_table_entry_name(). + */ +typedef struct table_entry { + int id; + char *sname; /* short (input) name to find table entry */ + char *lname; /* long (output) name to print for messages */ +} table_entry_t; + +/* + * get_table_entry_id() scans the translation table trying to find an + * entry that matches the given short name. If a matching entry is + * found, it's id is returned to the caller. + */ +int get_table_entry_id (table_entry_t *table, + const char *table_name, const char *name); +/* + * get_table_entry_name() scans the translation table trying to find + * an entry that matches the given id. If a matching entry is found, + * its long name is returned to the caller. + */ +char *get_table_entry_name (table_entry_t *table, char *msg, int id); + const char *genimg_get_os_name (uint8_t os); const char *genimg_get_arch_name (uint8_t arch); const char *genimg_get_type_name (uint8_t type); -- cgit v1.2.3 From aa0c7a86cd236b8193218a09e1365c8991bb5ddc Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 7 Sep 2009 15:05:02 +0530 Subject: mkimage: Add Kirkwood Boot Image support (kwbimage) This patch adds support for "kwbimage" (Kirkwood Boot Image) image types to the mkimage code. For details refer to docs/README.kwbimage This patch is tested with Sheevaplug board Signed-off-by: Prafulla Wadaskar Acked-by: Ron Lee Signed-off-by: Prafulla Wadaskar --- include/image.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/image.h b/include/image.h index d4cbf8c7093..5a424e6a942 100644 --- a/include/image.h +++ b/include/image.h @@ -155,6 +155,7 @@ #define IH_TYPE_SCRIPT 6 /* Script file */ #define IH_TYPE_FILESYSTEM 7 /* Filesystem Image (any type) */ #define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ +#define IH_TYPE_KWBIMAGE 9 /* Kirkwood Boot Image */ /* * Compression Types -- cgit v1.2.3 From 45f89f340b4d8aa099fd022260dcb13cf3321b61 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 9 Sep 2009 21:22:08 +0200 Subject: ep8248: add support for device tree and secondary Ethernet interface. Signed-off-by: Marcel Ziswiler --- include/configs/ep8248.h | 49 +++++++++++++++++++----------------------------- 1 file changed, 19 insertions(+), 30 deletions(-) (limited to 'include') diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h index f7b3fdea88d..cb4185a67bb 100644 --- a/include/configs/ep8248.h +++ b/include/configs/ep8248.h @@ -50,50 +50,41 @@ #define CONFIG_SYS_BCSR 0xFA000000 -/* - * Select ethernet configuration - * - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for - * SCC, 1-3 for FCC) - * - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET - * must be unset. - */ +/* Pass open firmware flat device tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc/cpm/serial 11a80" + +/* Select ethernet configuration */ #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ #undef CONFIG_ETHER_NONE /* No external Ethernet */ -#ifdef CONFIG_ETHER_ON_FCC - -#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ - -#if (CONFIG_ETHER_INDEX == 1) +#define CONFIG_NET_MULTI +#define CONFIG_SYS_CPMFCR_RAMTYPE 0 +#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHER_ON_FCC1 1 /* - Rx clock is CLK10 * - Tx clock is CLK11 * - BDs/buffers on 60x bus * - Full duplex */ -#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11) -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#elif (CONFIG_ETHER_INDEX == 2) +#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) +#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11) +#define CONFIG_HAS_ETH1 +#define CONFIG_ETHER_ON_FCC2 1 /* - Rx clock is CLK13 * - Tx clock is CLK14 * - BDs/buffers on 60x bus * - Full duplex */ -#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) -#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) - -#endif /* CONFIG_ETHER_INDEX */ +#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) #define CONFIG_MII /* MII PHY management */ #define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ @@ -113,8 +104,6 @@ #define MIIDELAY udelay(1) -#endif /* CONFIG_ETHER_ON_FCC */ - #ifndef CONFIG_8260_CLKIN #define CONFIG_8260_CLKIN 66000000 /* in Hz */ #endif -- cgit v1.2.3 From c7c1dbbf7159b38f3302b845dd97d28a543ff91b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 9 Sep 2009 21:09:00 +0200 Subject: r7780mp: fix typo in Ethernet chip model number comment. Signed-off-by: Marcel Ziswiler --- include/configs/r7780mp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h index 7738a17b01f..71c570eee90 100644 --- a/include/configs/r7780mp.h +++ b/include/configs/r7780mp.h @@ -154,7 +154,7 @@ #define CONFIG_NET_MULTI #define CONFIG_RTL8169 */ -/* AX88696L Support(NE2000 base chip) */ +/* AX88796L Support(NE2000 base chip) */ #define CONFIG_DRIVER_NE2000 #define CONFIG_DRIVER_AX88796L #define CONFIG_DRIVER_NE2000_BASE 0xA4100000 -- cgit v1.2.3 From d1c3b27525b664e8c4db6bb173eed51bfc8220de Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 9 Sep 2009 16:25:29 +0200 Subject: ppc4xx: Big cleanup of PPC4xx defines This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese --- include/configs/W7OLMC.h | 4 +- include/configs/W7OLMG.h | 4 +- include/ppc405.h | 397 ++++++++++++++----------------------------- include/ppc440.h | 432 +++++++++++++++-------------------------------- include/ppc4xx.h | 106 ++++++------ 5 files changed, 317 insertions(+), 626 deletions(-) (limited to 'include') diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index 553845d6d98..40e4735b681 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -207,9 +207,9 @@ #define CONFIG_SYS_EBC_PB5CR 0xFD21A000 /* bank 6 is unused */ -/* pb6ap = 0 */ +/* PB6AP = 0 */ #define CONFIG_SYS_EBC_PB6AP 0x00000000 -/* pb6cr = 0 */ +/* PB6CR = 0 */ #define CONFIG_SYS_EBC_PB6CR 0x00000000 /* bank 7 is LED register */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 73d6d24b61d..a62f1b4d578 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -214,9 +214,9 @@ #define CONFIG_SYS_EBC_PB5CR 0xFD87A000 /* bank 6 is unused */ -/* pb6ap = 0 */ +/* PB6AP = 0 */ #define CONFIG_SYS_EBC_PB6AP 0x00000000 -/* pb6cr = 0 */ +/* PB6CR = 0 */ #define CONFIG_SYS_EBC_PB6CR 0x00000000 /* bank 7 is LED register */ diff --git a/include/ppc405.h b/include/ppc405.h index 55649e474fc..5e56897819a 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -42,54 +42,39 @@ * DMA ******************************************************************************/ #define DMA_DCR_BASE 0x100 -#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ -#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ -#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ -#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ -#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ -#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ -#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ -#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ -#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ -#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ -#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ -#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ -#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ -#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ -#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ -#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ -#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ -#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ -#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ -#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ -#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ -#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ -#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ +#define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ +#define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define DMADA0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ +#define DMASA0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ +#define DMASB0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ +#define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ +#define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define DMADA1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ +#define DMASA1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ +#define DMASB1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ +#define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ +#define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define DMADA2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ +#define DMASA2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ +#define DMASB2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ +#define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ +#define DMACT3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ +#define DMADA3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ +#define DMASA3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ +#define DMASB3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ +#define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ +#define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ +#define DMAADR (DMA_DCR_BASE+0x24) /* DMA address decode register */ #ifndef CONFIG_405EP /****************************************************************************** * Decompression Controller ******************************************************************************/ #define DECOMP_DCR_BASE 0x14 -#define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ -#define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ - /* values for kiar register - indirect addressing of these regs */ - #define kitor0 0x00 /* index table origin register 0 */ - #define kitor1 0x01 /* index table origin register 1 */ - #define kitor2 0x02 /* index table origin register 2 */ - #define kitor3 0x03 /* index table origin register 3 */ - #define kaddr0 0x04 /* address decode definition regsiter 0 */ - #define kaddr1 0x05 /* address decode definition regsiter 1 */ - #define kconf 0x40 /* decompression core config register */ - #define kid 0x41 /* decompression core ID register */ - #define kver 0x42 /* decompression core version # reg */ - #define kpear 0x50 /* bus error addr reg (PLB addr) */ - #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ - #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ - #define kesr0s 0x53 /* bus error status reg 0 (set) */ - /* There are 0x400 of the following registers, from krom0 to krom3ff*/ - /* Only the first one is given here. */ - #define krom0 0x400 /* SRAM/ROM read/write */ +#define KIAR (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ +#define KIDR (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ +/* values for kiar register - indirect addressing of these regs */ +#define KCONF 0x40 /* decompression core config register */ #endif /****************************************************************************** @@ -100,38 +85,37 @@ #else #define POWERMAN_DCR_BASE 0xb8 #endif -#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ -#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ -#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ +#define CPMSR (POWERMAN_DCR_BASE+0x0) /* Power management status */ +#define CPMER (POWERMAN_DCR_BASE+0x1) /* Power management enable */ +#define CPMFR (POWERMAN_DCR_BASE+0x2) /* Power management force */ /****************************************************************************** * Extrnal Bus Controller ******************************************************************************/ - /* values for ebccfga register - indirect addressing of these regs */ - #define pb0cr 0x00 /* periph bank 0 config reg */ - #define pb1cr 0x01 /* periph bank 1 config reg */ - #define pb2cr 0x02 /* periph bank 2 config reg */ - #define pb3cr 0x03 /* periph bank 3 config reg */ - #define pb4cr 0x04 /* periph bank 4 config reg */ + /* values for EBC0_CFGADDR register - indirect addressing of these regs */ + #define PB0CR 0x00 /* periph bank 0 config reg */ + #define PB1CR 0x01 /* periph bank 1 config reg */ + #define PB2CR 0x02 /* periph bank 2 config reg */ + #define PB3CR 0x03 /* periph bank 3 config reg */ + #define PB4CR 0x04 /* periph bank 4 config reg */ #ifndef CONFIG_405EP - #define pb5cr 0x05 /* periph bank 5 config reg */ - #define pb6cr 0x06 /* periph bank 6 config reg */ - #define pb7cr 0x07 /* periph bank 7 config reg */ + #define PB5CR 0x05 /* periph bank 5 config reg */ + #define PB6CR 0x06 /* periph bank 6 config reg */ + #define PB7CR 0x07 /* periph bank 7 config reg */ #endif - #define pb0ap 0x10 /* periph bank 0 access parameters */ - #define pb1ap 0x11 /* periph bank 1 access parameters */ - #define pb2ap 0x12 /* periph bank 2 access parameters */ - #define pb3ap 0x13 /* periph bank 3 access parameters */ - #define pb4ap 0x14 /* periph bank 4 access parameters */ + #define PB0AP 0x10 /* periph bank 0 access parameters */ + #define PB1AP 0x11 /* periph bank 1 access parameters */ + #define PB2AP 0x12 /* periph bank 2 access parameters */ + #define PB3AP 0x13 /* periph bank 3 access parameters */ + #define PB4AP 0x14 /* periph bank 4 access parameters */ #ifndef CONFIG_405EP - #define pb5ap 0x15 /* periph bank 5 access parameters */ - #define pb6ap 0x16 /* periph bank 6 access parameters */ - #define pb7ap 0x17 /* periph bank 7 access parameters */ + #define PB5AP 0x15 /* periph bank 5 access parameters */ + #define PB6AP 0x16 /* periph bank 6 access parameters */ + #define PB7AP 0x17 /* periph bank 7 access parameters */ #endif - #define pbear 0x20 /* periph bus error addr reg */ - #define pbesr0 0x21 /* periph bus error status reg 0 */ - #define pbesr1 0x22 /* periph bus error status reg 1 */ - #define epcr 0x23 /* external periph control reg */ + #define PBEAR 0x20 /* periph bus error addr reg */ + #define PBESR0 0x21 /* periph bus error status reg 0 */ + #define PBESR1 0x22 /* periph bus error status reg 1 */ #define EBC0_CFG 0x23 /* external bus configuration reg */ #ifdef CONFIG_405EP @@ -139,12 +123,12 @@ * Control ******************************************************************************/ #define CNTRL_DCR_BASE 0x0f0 -#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ -#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ -#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ -#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ -#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ -#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Clock status register */ +#define CPC0_EPCTL (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART control register */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI control register */ #define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ @@ -401,10 +385,10 @@ #define VCO_MIN 500 #define VCO_MAX 1000 #elif defined(CONFIG_405EZ) -#define sdrnand0 0x4000 -#define sdrultra0 0x4040 -#define sdrultra1 0x4050 -#define sdricintstat 0x4510 +#define SDR0_NAND0 0x4000 +#define SDR0_ULTRA0 0x4040 +#define SDR0_ULTRA1 0x4050 +#define SDR0_ICINTSTAT 0x4510 #define SDR_NAND0_NDEN 0x80000000 #define SDR_NAND0_NDBTEN 0x40000000 @@ -429,21 +413,19 @@ #define SDR_ICTX0_STAT 0x40000000 #define SDR_ICTX1_STAT 0x20000000 -#define SDR_PINSTP 0x40 +#define SDR0_PINSTP 0x40 /****************************************************************************** * Control ******************************************************************************/ /* CPR Registers */ -#define cprclkupd 0x020 /* CPR_CLKUPD */ -#define cprpllc 0x040 /* CPR_PLLC */ -#define cprplld 0x060 /* CPR_PLLD */ -#define cprprimad 0x080 /* CPR_PRIMAD */ -#define cprperd0 0x0e0 /* CPR_PERD0 */ -#define cprperd1 0x0e1 /* CPR_PERD1 */ -#define cprperc0 0x180 /* CPR_PERC0 */ -#define cprmisc0 0x181 /* CPR_MISC0 */ -#define cprmisc1 0x182 /* CPR_MISC1 */ +#define CPR0_CLKUP 0x020 /* CPR_CLKUPD */ +#define CPR0_PLLC 0x040 /* CPR_PLLC */ +#define CPR0_PLLD 0x060 /* CPR_PLLD */ +#define CPC0_PRIMAD 0x080 /* CPR_PRIMAD */ +#define CPC0_PERD0 0x0e0 /* CPR_PERD0 */ +#define CPC0_PERD1 0x0e1 /* CPR_PERD1 */ +#define CPC0_PERC0 0x180 /* CPR_PERC0 */ #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ @@ -470,21 +452,14 @@ * Control ******************************************************************************/ #define CNTRL_DCR_BASE 0x0b0 -#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ -#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ -#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ -#define reset (CNTRL_DCR_BASE+0x3) /* reset register */ -#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ - -#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ -#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ +#define CPC0_PLLMR (CNTRL_DCR_BASE + 0x0) /* PLL mode register */ +#define CPC0_CR0 (CNTRL_DCR_BASE + 0x1) /* chip control register 0 */ +#define CPC0_CR1 (CNTRL_DCR_BASE + 0x2) /* chip control register 1 */ +#define CPC0_PSR (CNTRL_DCR_BASE + 0x4) /* chip pin strapping reg */ /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ -#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ -#define CPC0_ECR (0xaa) /* edge conditioner register */ - -#define ecr (0xaa) /* edge conditioner register (405gpr) */ +#define CPC0_EIRR (CNTRL_DCR_BASE + 0x6) /* ext interrupt routing reg */ +#define CPC0_ECR 0xaa /* edge conditioner register */ /* Bit definitions */ #define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ @@ -557,140 +532,38 @@ ******************************************************************************/ #if defined(CONFIG_405EZ) #define MAL_DCR_BASE 0x380 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ -#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -/* 0x08-0x0F Reserved */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ -#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -/* 0x14-0x1F Reserved */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ -#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ -#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ -#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ -#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ -#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ -#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ -#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ -#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ -#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ -#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ -#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ -#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ -#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ -#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ -#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ -#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ -#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ -#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ -#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ -#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ -#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ -#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ -#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ -#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ -#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ -#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ -#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ -#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ -#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ -#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ -#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ -#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ -#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ -#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ -#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ -#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ -#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ -#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ -#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ -#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ -#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ -#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ -#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ -#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ -#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ -#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ -#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ -#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ -#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ -#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ -#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ -#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ -#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ -#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ -#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ -#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ -#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ -#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ -#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ -#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ -#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ -#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ -#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ -#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ -#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ -#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ -#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ -#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ -#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ -#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ -#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ -#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ -#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ -#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ -#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ -#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ -#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ -#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ -#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ -#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ -#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ -#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ -#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ -#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ -#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ -#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ -#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ -#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ -#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ - -#else /* !defined(CONFIG_405EZ) */ - -#define MAL_DCR_BASE 0x180 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ -#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ -#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ -#endif /* defined(CONFIG_405EZ) */ +#else +#define MAL_DCR_BASE 0x180 +#endif +#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ +#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Err Status (Read/Clear)*/ +#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ +#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set)*/ +#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset)*/ +#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/ +#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int reg */ +#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ +#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ +#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/ +#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int reg */ +#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table ptr */ +#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table ptr */ +#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table ptr */ +#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table ptr */ +#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table ptr */ +#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table ptr */ +#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table ptr */ +#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table ptr */ +#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table ptr */ +#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table ptr */ +#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table ptr */ +#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ +#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ +#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ +#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ +#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ +#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ +#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ /*----------------------------------------------------------------------------- | IIC Register Offsets @@ -730,27 +603,19 @@ ******************************************************************************/ #if defined(CONFIG_405EZ) #define OCM_DCR_BASE 0x020 -#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ -#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ -#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ -#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ -#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ -#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ -#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ -#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ -#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ -#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ -#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ -#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ -#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ -#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ -#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ +#define OCM0_PLBCR1 (OCM_DCR_BASE + 0x00) /* OCM PLB3 Bank 1 Config */ +#define OCM0_PLBCR2 (OCM_DCR_BASE + 0x01) /* OCM PLB3 Bank 2 Config */ +#define OCM0_PLBBEAR (OCM_DCR_BASE + 0x02) /* OCM PLB3 Bus Error Add */ +#define OCM0_DSRC1 (OCM_DCR_BASE + 0x08) /* OCM D-side Bank 1 Config */ +#define OCM0_DSRC2 (OCM_DCR_BASE + 0x09) /* OCM D-side Bank 2 Config */ +#define OCM0_ISRC1 (OCM_DCR_BASE + 0x0A) /* OCM I-side Bank 1Config */ +#define OCM0_ISRC2 (OCM_DCR_BASE + 0x0B) /* OCM I-side Bank 2 Config */ +#define OCM0_DISDPC (OCM_DCR_BASE + 0x0C) /* OCM D-/I-side Data Par Chk*/ #else #define OCM_DCR_BASE 0x018 -#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ -#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ -#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ -#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ +#define OCM0_ISCNTL (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ +#define OCM0_DSARC (OCM_DCR_BASE+0x02) /* OCM D-side address compare */ +#define OCM0_DSCNTL (OCM_DCR_BASE+0x03) /* OCM D-side control */ #endif /* CONFIG_405EZ */ /****************************************************************************** @@ -876,9 +741,9 @@ #define SDR0_SRST_AHB PPC_REG_VAL(30, 1) #define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) -#define sdr_uart0 0x0120 /* UART0 Config */ -#define sdr_uart1 0x0121 /* UART1 Config */ -#define sdr_mfr 0x4300 /* SDR0_MFR reg */ +#define SDR0_UART0 0x0120 /* UART0 Config */ +#define SDR0_UART1 0x0121 /* UART1 Config */ +#define SDR0_MFR 0x4300 /* SDR0_MFR reg */ /* Defines for CPC0_EPRCSR register */ #define CPC0_EPRCSR_E0NFE 0x80000000 @@ -890,18 +755,16 @@ #define CPC0_EPRCSR_E1PCI 0x00000002 #define CPC0_EPRCSR_E0PCI 0x00000001 -#define cpr0_clkupd 0x020 -#define cpr0_pllc 0x040 -#define cpr0_plld 0x060 -#define cpr0_cpud 0x080 -#define cpr0_plbd 0x0a0 -#define cpr0_opbd 0x0c0 -#define cpr0_perd 0x0e0 -#define cpr0_ahbd 0x100 -#define cpr0_icfg 0x140 - -#define SDR_PINSTP 0x0040 -#define sdr_sdcs 0x0060 +#define CPR0_CLKUPD 0x020 +#define CPR0_PLLC 0x040 +#define CPR0_PLLD 0x060 +#define CPR0_CPUD 0x080 +#define CPR0_PLBD 0x0a0 +#define CPR0_OPBD 0x0c0 +#define CPR0_PERD 0x0e0 + +#define SDR0_PINSTP 0x0040 +#define SDR0_SDCS0 0x0060 #define SDR0_SDCS_SDD (0x80000000 >> 31) diff --git a/include/ppc440.h b/include/ppc440.h index 7f34fda8cfa..378a9de20a6 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -58,64 +58,55 @@ | Clocking Controller +----------------------------------------------------------------------------*/ /* values for clkcfga register - indirect addressing of these regs */ -#define clk_clkukpd 0x0020 -#define clk_pllc 0x0040 -#define clk_plld 0x0060 -#define clk_primad 0x0080 -#define clk_primbd 0x00a0 -#define clk_opbd 0x00c0 -#define clk_perd 0x00e0 -#define clk_mald 0x0100 -#define clk_spcid 0x0120 -#define clk_icfg 0x0140 +#define CPR0_PLLC 0x0040 +#define CPR0_PLLD 0x0060 +#define CPR0_PRIMAD 0x0080 +#define CPR0_PRIMBD 0x00a0 +#define CPR0_OPBD 0x00c0 +#define CPR0_PERD 0x00e0 +#define CPR0_MALD 0x0100 +#define CPR0_SPCID 0x0120 +#define CPR0_ICFG 0x0140 /* 440gx sdr register definations */ -#define sdr_sdstp0 0x0020 /* */ -#define sdr_sdstp1 0x0021 /* */ -#define SDR_PINSTP 0x0040 -#define sdr_sdcs 0x0060 -#define sdr_ecid0 0x0080 -#define sdr_ecid1 0x0081 -#define sdr_ecid2 0x0082 -#define sdr_jtag 0x00c0 +#define SDR0_SDSTP0 0x0020 /* */ +#define SDR0_SDSTP1 0x0021 /* */ +#define SDR0_PINSTP 0x0040 +#define SDR0_SDCS0 0x0060 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define SDR0_DDRCFG 0x00e0 #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ -#define sdr_ebc 0x0100 -#define sdr_uart0 0x0120 /* UART0 Config */ -#define sdr_uart1 0x0121 /* UART1 Config */ -#define sdr_uart2 0x0122 /* UART2 Config */ -#define sdr_uart3 0x0123 /* UART3 Config */ -#define sdr_cp440 0x0180 -#define sdr_xcr 0x01c0 -#define sdr_xpllc 0x01c1 -#define sdr_xplld 0x01c2 -#define sdr_srst 0x0200 -#define sdr_slpipe 0x0220 -#define sdr_amp0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ -#define sdr_amp1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ -#define sdr_mirq0 0x0260 -#define sdr_mirq1 0x0261 -#define sdr_maltbl 0x0280 -#define sdr_malrbl 0x02a0 -#define sdr_maltbs 0x02c0 -#define sdr_malrbs 0x02e0 -#define sdr_pci0 0x0300 -#define sdr_usb0 0x0320 -#define sdr_cust0 0x4000 -#define sdr_cust1 0x4002 -#define sdr_pfc0 0x4100 /* Pin Function 0 */ -#define sdr_pfc1 0x4101 /* Pin Function 1 */ -#define sdr_plbtr 0x4200 -#define sdr_mfr 0x4300 /* SDR0_MFR reg */ +#define SDR0_EBC 0x0100 +#define SDR0_UART0 0x0120 /* UART0 Config */ +#define SDR0_UART1 0x0121 /* UART1 Config */ +#define SDR0_UART2 0x0122 /* UART2 Config */ +#define SDR0_UART3 0x0123 /* UART3 Config */ +#define SDR0_CP440 0x0180 +#define SDR0_XCR 0x01c0 +#define SDR0_XPLLC 0x01c1 +#define SDR0_XPLLD 0x01c2 +#define SDR0_SRST 0x0200 +#define SD0_AMP0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ +#define SD0_AMP1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define SDR0_PCI0 0x01c0 +#else +#define SDR0_PCI0 0x0300 +#endif +#define SDR0_USB0 0x0320 +#define SDR0_CUST0 0x4000 +#define SDR0_CUST1 0x4002 +#define SDR0_PFC0 0x4100 /* Pin Function 0 */ +#define SDR0_PFC1 0x4101 /* Pin Function 1 */ +#define SDR0_MFR 0x4300 /* SDR0_MFR reg */ #ifdef CONFIG_440GX -#define sdr_amp 0x0240 -#define sdr_xpllc 0x01c1 -#define sdr_xplld 0x01c2 -#define sdr_xcr 0x01c0 -#define sdr_sdstp2 0x4001 -#define sdr_sdstp3 0x4003 +#define SD0_AMP 0x0240 +#define SDR0_XPLLC 0x01c1 +#define SDR0_XPLLD 0x01c2 +#define SDR0_XCR 0x01c0 +#define SDR0_SDSTP2 0x4001 +#define SDR0_SDSTP3 0x4003 #endif /* CONFIG_440GX */ /*----------------------------------------------------------------------------+ @@ -143,101 +134,66 @@ #define MMUCR_STID_MASK 0x000000FF #ifdef CONFIG_440SPE -#undef sdr_sdstp2 -#define sdr_sdstp2 0x0022 -#undef sdr_sdstp3 -#define sdr_sdstp3 0x0023 -#define sdr_ddr0 0x00E1 -#define sdr_uart2 0x0122 -#define sdr_xcr0 0x01c0 -/* #define sdr_xcr1 0x01c3 only one PCIX - SG */ -/* #define sdr_xcr2 0x01c6 only one PCIX - SG */ -#define sdr_xpllc0 0x01c1 -#define sdr_xplld0 0x01c2 -#define sdr_xpllc1 0x01c4 /*notRCW - SG */ -#define sdr_xplld1 0x01c5 /*notRCW - SG */ -#define sdr_xpllc2 0x01c7 /*notRCW - SG */ -#define sdr_xplld2 0x01c8 /*notRCW - SG */ -#define sdr_amp0 0x0240 -#define sdr_amp1 0x0241 -#define sdr_cust2 0x4004 -#define sdr_cust3 0x4006 -#define sdr_sdstp4 0x4001 -#define sdr_sdstp5 0x4003 -#define sdr_sdstp6 0x4005 -#define sdr_sdstp7 0x4007 +#undef SDR0_SDSTP2 +#define SDR0_SDSTP2 0x0022 +#undef SDR0_SDSTP3 +#define SDR0_SDSTP3 0x0023 +#define SDR0_DDR0 0x00E1 +#define SDR0_UART2 0x0122 +#define SDR0_XCR0 0x01c0 +#define SDR0_XCR1 0x01c3 +#define SDR0_XCR2 0x01c6 +#define SDR0_XPLLC0 0x01c1 +#define SDR0_XPLLD0 0x01c2 +#define SDR0_XPLLC1 0x01c4 /*notRCW - SG */ +#define SDR0_XPLLD1 0x01c5 /*notRCW - SG */ +#define SDR0_XPLLC2 0x01c7 /*notRCW - SG */ +#define SDR0_XPLLD2 0x01c8 /*notRCW - SG */ +#define SD0_AMP0 0x0240 +#define SD0_AMP1 0x0241 +#define SDR0_CUST2 0x4004 +#define SDR0_CUST3 0x4006 +#define SDR0_SDSTP4 0x4001 +#define SDR0_SDSTP5 0x4003 +#define SDR0_SDSTP6 0x4005 +#define SDR0_SDSTP7 0x4007 #endif /* CONFIG_440SPE */ /*----------------------------------------------------------------------------- | External Bus Controller +----------------------------------------------------------------------------*/ -/* values for ebccfga register - indirect addressing of these regs */ -#define pb0cr 0x00 /* periph bank 0 config reg */ -#define pb1cr 0x01 /* periph bank 1 config reg */ -#define pb2cr 0x02 /* periph bank 2 config reg */ -#define pb3cr 0x03 /* periph bank 3 config reg */ -#define pb4cr 0x04 /* periph bank 4 config reg */ -#define pb5cr 0x05 /* periph bank 5 config reg */ -#define pb6cr 0x06 /* periph bank 6 config reg */ -#define pb7cr 0x07 /* periph bank 7 config reg */ -#define pb0ap 0x10 /* periph bank 0 access parameters */ -#define pb1ap 0x11 /* periph bank 1 access parameters */ -#define pb2ap 0x12 /* periph bank 2 access parameters */ -#define pb3ap 0x13 /* periph bank 3 access parameters */ -#define pb4ap 0x14 /* periph bank 4 access parameters */ -#define pb5ap 0x15 /* periph bank 5 access parameters */ -#define pb6ap 0x16 /* periph bank 6 access parameters */ -#define pb7ap 0x17 /* periph bank 7 access parameters */ -#define pbear 0x20 /* periph bus error addr reg */ -#define pbesr 0x21 /* periph bus error status reg */ -#define xbcfg 0x23 /* external bus configuration reg */ +/* values for EBC0_CFGADDR register - indirect addressing of these regs */ +#define PB0CR 0x00 /* periph bank 0 config reg */ +#define PB1CR 0x01 /* periph bank 1 config reg */ +#define PB2CR 0x02 /* periph bank 2 config reg */ +#define PB3CR 0x03 /* periph bank 3 config reg */ +#define PB4CR 0x04 /* periph bank 4 config reg */ +#define PB5CR 0x05 /* periph bank 5 config reg */ +#define PB6CR 0x06 /* periph bank 6 config reg */ +#define PB7CR 0x07 /* periph bank 7 config reg */ +#define PB0AP 0x10 /* periph bank 0 access parameters */ +#define PB1AP 0x11 /* periph bank 1 access parameters */ +#define PB2AP 0x12 /* periph bank 2 access parameters */ +#define PB3AP 0x13 /* periph bank 3 access parameters */ +#define PB4AP 0x14 /* periph bank 4 access parameters */ +#define PB5AP 0x15 /* periph bank 5 access parameters */ +#define PB6AP 0x16 /* periph bank 6 access parameters */ +#define PB7AP 0x17 /* periph bank 7 access parameters */ +#define PBEAR 0x20 /* periph bus error addr reg */ +#define PBESR 0x21 /* periph bus error status reg */ #define EBC0_CFG 0x23 /* external bus configuration reg */ -#define xbcid 0x24 /* external bus core id reg */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -/* PLB4 to PLB3 Bridge OUT */ -#define P4P3_DCR_BASE 0x020 -#define p4p3_esr0_read (P4P3_DCR_BASE+0x0) -#define p4p3_esr0_write (P4P3_DCR_BASE+0x1) -#define p4p3_eadr (P4P3_DCR_BASE+0x2) -#define p4p3_euadr (P4P3_DCR_BASE+0x3) -#define p4p3_esr1_read (P4P3_DCR_BASE+0x4) -#define p4p3_esr1_write (P4P3_DCR_BASE+0x5) -#define p4p3_confg (P4P3_DCR_BASE+0x6) -#define p4p3_pic (P4P3_DCR_BASE+0x7) -#define p4p3_peir (P4P3_DCR_BASE+0x8) -#define p4p3_rev (P4P3_DCR_BASE+0xA) - -/* PLB3 to PLB4 Bridge IN */ -#define P3P4_DCR_BASE 0x030 -#define p3p4_esr0_read (P3P4_DCR_BASE+0x0) -#define p3p4_esr0_write (P3P4_DCR_BASE+0x1) -#define p3p4_eadr (P3P4_DCR_BASE+0x2) -#define p3p4_euadr (P3P4_DCR_BASE+0x3) -#define p3p4_esr1_read (P3P4_DCR_BASE+0x4) -#define p3p4_esr1_write (P3P4_DCR_BASE+0x5) -#define p3p4_confg (P3P4_DCR_BASE+0x6) -#define p3p4_pic (P3P4_DCR_BASE+0x7) -#define p3p4_peir (P3P4_DCR_BASE+0x8) -#define p3p4_rev (P3P4_DCR_BASE+0xA) - /* PLB3 Arbiter */ -#define PLB3_DCR_BASE 0x070 -#define plb3_revid (PLB3_DCR_BASE+0x2) -#define plb3_besr (PLB3_DCR_BASE+0x3) -#define plb3_bear (PLB3_DCR_BASE+0x6) -#define plb3_acr (PLB3_DCR_BASE+0x7) +#define PLB3_DCR_BASE 0x070 +#define PLB3_ACR (PLB3_DCR_BASE + 0x7) /* PLB4 Arbiter - PowerPC440EP Pass1 */ -#define PLB4_DCR_BASE 0x080 -#define plb4_acr (PLB4_DCR_BASE+0x1) -#define plb4_revid (PLB4_DCR_BASE+0x2) -#define plb4_besr (PLB4_DCR_BASE+0x4) -#define plb4_bearl (PLB4_DCR_BASE+0x6) -#define plb4_bearh (PLB4_DCR_BASE+0x7) +#define PLB4_DCR_BASE 0x080 +#define PLB4_ACR (PLB4_DCR_BASE + 0x1) #define PLB4_ACR_WRP (0x80000000 >> 7) @@ -578,24 +534,16 @@ #define CNTRL_DCR_BASE 0x0b0 #endif -#define cpc0_er (CNTRL_DCR_BASE+0x00) /* CPM enable register */ -#define cpc0_fr (CNTRL_DCR_BASE+0x01) /* CPM force register */ -#define cpc0_sr (CNTRL_DCR_BASE+0x02) /* CPM status register */ - -#define cpc0_sys0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ -#define cpc0_sys1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ -#define cpc0_cust0 (CNTRL_DCR_BASE+0x32) /* Customer configuration reg 0 */ -#define cpc0_cust1 (CNTRL_DCR_BASE+0x33) /* Customer configuration reg 1 */ +#define CPC0_SYS0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ +#define CPC0_SYS1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ -#define cpc0_strp0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ -#define cpc0_strp1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ -#define cpc0_strp2 (CNTRL_DCR_BASE+0x36) /* Power-on config reg 2 (RO) */ -#define cpc0_strp3 (CNTRL_DCR_BASE+0x37) /* Power-on config reg 3 (RO) */ +#define CPC0_STRP0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ +#define CPC0_STRP1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ -#define cpc0_gpio (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ +#define CPC0_GPIO (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ -#define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ -#define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ +#define CPC0_CR0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ /*----------------------------------------------------------------------------- | DMA @@ -605,91 +553,59 @@ #else #define DMA_DCR_BASE 0x100 #endif -#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ -#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ -#define dmasah0 (DMA_DCR_BASE+0x02) /* DMA source address high 0 */ -#define dmasal0 (DMA_DCR_BASE+0x03) /* DMA source address low 0 */ -#define dmadah0 (DMA_DCR_BASE+0x04) /* DMA destination address high 0 */ -#define dmadal0 (DMA_DCR_BASE+0x05) /* DMA destination address low 0 */ -#define dmasgh0 (DMA_DCR_BASE+0x06) /* DMA scatter/gather desc addr high 0 */ -#define dmasgl0 (DMA_DCR_BASE+0x07) /* DMA scatter/gather desc addr low 0 */ -#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ -#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ -#define dmasah1 (DMA_DCR_BASE+0x0a) /* DMA source address high 1 */ -#define dmasal1 (DMA_DCR_BASE+0x0b) /* DMA source address low 1 */ -#define dmadah1 (DMA_DCR_BASE+0x0c) /* DMA destination address high 1 */ -#define dmadal1 (DMA_DCR_BASE+0x0d) /* DMA destination address low 1 */ -#define dmasgh1 (DMA_DCR_BASE+0x0e) /* DMA scatter/gather desc addr high 1 */ -#define dmasgl1 (DMA_DCR_BASE+0x0f) /* DMA scatter/gather desc addr low 1 */ -#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ -#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ -#define dmasah2 (DMA_DCR_BASE+0x12) /* DMA source address high 2 */ -#define dmasal2 (DMA_DCR_BASE+0x13) /* DMA source address low 2 */ -#define dmadah2 (DMA_DCR_BASE+0x14) /* DMA destination address high 2 */ -#define dmadal2 (DMA_DCR_BASE+0x15) /* DMA destination address low 2 */ -#define dmasgh2 (DMA_DCR_BASE+0x16) /* DMA scatter/gather desc addr high 2 */ -#define dmasgl2 (DMA_DCR_BASE+0x17) /* DMA scatter/gather desc addr low 2 */ -#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */ -#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 2 */ -#define dmasah3 (DMA_DCR_BASE+0x1a) /* DMA source address high 2 */ -#define dmasal3 (DMA_DCR_BASE+0x1b) /* DMA source address low 2 */ -#define dmadah3 (DMA_DCR_BASE+0x1c) /* DMA destination address high 2 */ -#define dmadal3 (DMA_DCR_BASE+0x1d) /* DMA destination address low 2 */ -#define dmasgh3 (DMA_DCR_BASE+0x1e) /* DMA scatter/gather desc addr high 2 */ -#define dmasgl3 (DMA_DCR_BASE+0x1f) /* DMA scatter/gather desc addr low 2 */ -#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ -#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ -#define dmaslp (DMA_DCR_BASE+0x25) /* DMA sleep mode register */ -#define dmapol (DMA_DCR_BASE+0x26) /* DMA polarity configuration register */ +#define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ +#define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ +#define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ +#define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */ +#define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ +#define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ /*----------------------------------------------------------------------------- | Memory Access Layer +----------------------------------------------------------------------------*/ #define MAL_DCR_BASE 0x180 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ -#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -#define maltxtattrr (MAL_DCR_BASE+0x08) /* TX PLB attribute reg */ -#define maltxbattr (MAL_DCR_BASE+0x09) /* TX descriptor base addr reg */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ -#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -#define malrxtattrr (MAL_DCR_BASE+0x14) /* RX PLB attribute reg */ -#define malrxbattr (MAL_DCR_BASE+0x15) /* RX descriptor base addr reg */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ -#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table pointer reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ +#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear) */ +#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ +#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ +#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */ +#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status */ +#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */ +#define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/ +#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ +#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ +#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status */ +#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */ +#define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */ +#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */ +#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */ +#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */ +#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */ +#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */ +#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */ +#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ +#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ #if defined(CONFIG_440GX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */ -#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */ -#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table pointer reg */ -#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table pointer reg */ -#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table pointer reg */ -#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ -#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ -#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ -#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ -#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ +#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table pointer */ +#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table pointer */ +#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table pointer */ +#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table pointer*/ +#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table pointer*/ +#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ +#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ +#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ +#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ +#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ #endif /* CONFIG_440GX */ /*-----------------------------------------------------------------------------+ | SDR0 Bit Settings +-----------------------------------------------------------------------------*/ #if defined(CONFIG_440SP) -#define SDR0_SRST 0x0200 - #define SDR0_DDR0 0x00E1 #define SDR0_DDR0_DPLLRST 0x80000000 #define SDR0_DDR0_DDRM_MASK 0x60000000 @@ -923,79 +839,6 @@ #define SDR0_UART0 0x0120 #define SDR0_UART1 0x0121 #define SDR0_UART2 0x0122 -#define SDR0_UARTX_UXICS_MASK 0xF0000000 -#define SDR0_UARTX_UXICS_PLB 0x20000000 -#define SDR0_UARTX_UXEC_MASK 0x00800000 -#define SDR0_UARTX_UXEC_INT 0x00000000 -#define SDR0_UARTX_UXEC_EXT 0x00800000 -#define SDR0_UARTX_UXDIV_MASK 0x000000FF -#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1) - -#define SDR0_CP440 0x0180 -#define SDR0_CP440_ERPN_MASK 0x30000000 -#define SDR0_CP440_ERPN_MASK_HI 0x3000 -#define SDR0_CP440_ERPN_MASK_LO 0x0000 -#define SDR0_CP440_ERPN_EBC 0x10000000 -#define SDR0_CP440_ERPN_EBC_HI 0x1000 -#define SDR0_CP440_ERPN_EBC_LO 0x0000 -#define SDR0_CP440_ERPN_PCI 0x20000000 -#define SDR0_CP440_ERPN_PCI_HI 0x2000 -#define SDR0_CP440_ERPN_PCI_LO 0x0000 -#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) -#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03) -#define SDR0_CP440_NTO1_MASK 0x00000002 -#define SDR0_CP440_NTO1_NTOP 0x00000000 -#define SDR0_CP440_NTO1_NTO1 0x00000002 -#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) -#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) - -#define SDR0_XCR0 0x01C0 -#define SDR0_XCR1 0x01C3 -#define SDR0_XCR2 0x01C6 -#define SDR0_XCRn_PAE_MASK 0x80000000 -#define SDR0_XCRn_PAE_DISABLE 0x00000000 -#define SDR0_XCRn_PAE_ENABLE 0x80000000 -#define SDR0_XCRn_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) -#define SDR0_XCRn_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) -#define SDR0_XCRn_PHCE_MASK 0x40000000 -#define SDR0_XCRn_PHCE_DISABLE 0x00000000 -#define SDR0_XCRn_PHCE_ENABLE 0x40000000 -#define SDR0_XCRn_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) -#define SDR0_XCRn_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) -#define SDR0_XCRn_PISE_MASK 0x20000000 -#define SDR0_XCRn_PISE_DISABLE 0x00000000 -#define SDR0_XCRn_PISE_ENABLE 0x20000000 -#define SDR0_XCRn_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) -#define SDR0_XCRn_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) -#define SDR0_XCRn_PCWE_MASK 0x10000000 -#define SDR0_XCRn_PCWE_DISABLE 0x00000000 -#define SDR0_XCRn_PCWE_ENABLE 0x10000000 -#define SDR0_XCRn_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) -#define SDR0_XCRn_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) -#define SDR0_XCRn_PPIM_MASK 0x0F000000 -#define SDR0_XCRn_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) -#define SDR0_XCRn_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) -#define SDR0_XCRn_PR64E_MASK 0x00800000 -#define SDR0_XCRn_PR64E_DISABLE 0x00000000 -#define SDR0_XCRn_PR64E_ENABLE 0x00800000 -#define SDR0_XCRn_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) -#define SDR0_XCRn_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) -#define SDR0_XCRn_PXFS_MASK 0x00600000 -#define SDR0_XCRn_PXFS_100_133 0x00000000 -#define SDR0_XCRn_PXFS_66_100 0x00200000 -#define SDR0_XCRn_PXFS_50_66 0x00400000 -#define SDR0_XCRn_PXFS_0_33 0x00600000 -#define SDR0_XCRn_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) -#define SDR0_XCRn_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) - -#define SDR0_XPLLC0 0x01C1 -#define SDR0_XPLLD0 0x01C2 -#define SDR0_XPLLC1 0x01C4 -#define SDR0_XPLLD1 0x01C5 -#define SDR0_XPLLC2 0x01C7 -#define SDR0_XPLLD2 0x01C8 -#define SDR0_SRST 0x0200 #define SDR0_SLPIPE 0x0220 #define SDR0_AMP0 0x0240 @@ -1544,8 +1387,7 @@ #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define SDR0_SRST0 0x0200 -#define SDR0_SRST SDR0_SRST0 /* for compatability reasons */ +#define SDR0_SRST0 SDR0_SRST /* for compatability reasons */ #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ @@ -1607,8 +1449,6 @@ #define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */ #define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */ -#define SDR0_PCI0 0x1c0 /* PCI Configuration Register */ - #else #define SDR0_SRST_BGO 0x80000000 diff --git a/include/ppc4xx.h b/include/ppc4xx.h index a9954aa3de3..086f8fb7ee3 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -65,49 +65,37 @@ #define PLB_ARBITER_BASE 0x80 -#define plb0_revid (PLB_ARBITER_BASE + 0x00) -#define plb0_acr (PLB_ARBITER_BASE + 0x01) -#define plb0_acr_ppm_mask 0xF0000000 -#define plb0_acr_ppm_fixed 0x00000000 -#define plb0_acr_ppm_fair 0xD0000000 -#define plb0_acr_hbu_mask 0x08000000 -#define plb0_acr_hbu_disabled 0x00000000 -#define plb0_acr_hbu_enabled 0x08000000 -#define plb0_acr_rdp_mask 0x06000000 -#define plb0_acr_rdp_disabled 0x00000000 -#define plb0_acr_rdp_2deep 0x02000000 -#define plb0_acr_rdp_3deep 0x04000000 -#define plb0_acr_rdp_4deep 0x06000000 -#define plb0_acr_wrp_mask 0x01000000 -#define plb0_acr_wrp_disabled 0x00000000 -#define plb0_acr_wrp_2deep 0x01000000 - -#define plb0_besrl (PLB_ARBITER_BASE + 0x02) -#define plb0_besrh (PLB_ARBITER_BASE + 0x03) -#define plb0_bearl (PLB_ARBITER_BASE + 0x04) -#define plb0_bearh (PLB_ARBITER_BASE + 0x05) -#define plb0_ccr (PLB_ARBITER_BASE + 0x08) - -#define plb1_acr (PLB_ARBITER_BASE + 0x09) -#define plb1_acr_ppm_mask 0xF0000000 -#define plb1_acr_ppm_fixed 0x00000000 -#define plb1_acr_ppm_fair 0xD0000000 -#define plb1_acr_hbu_mask 0x08000000 -#define plb1_acr_hbu_disabled 0x00000000 -#define plb1_acr_hbu_enabled 0x08000000 -#define plb1_acr_rdp_mask 0x06000000 -#define plb1_acr_rdp_disabled 0x00000000 -#define plb1_acr_rdp_2deep 0x02000000 -#define plb1_acr_rdp_3deep 0x04000000 -#define plb1_acr_rdp_4deep 0x06000000 -#define plb1_acr_wrp_mask 0x01000000 -#define plb1_acr_wrp_disabled 0x00000000 -#define plb1_acr_wrp_2deep 0x01000000 - -#define plb1_besrl (PLB_ARBITER_BASE + 0x0A) -#define plb1_besrh (PLB_ARBITER_BASE + 0x0B) -#define plb1_bearl (PLB_ARBITER_BASE + 0x0C) -#define plb1_bearh (PLB_ARBITER_BASE + 0x0D) +#define PLB0_ACR (PLB_ARBITER_BASE + 0x01) +#define PLB0_ACR_PPM_MASK 0xF0000000 +#define PLB0_ACR_PPM_FIXED 0x00000000 +#define PLB0_ACR_PPM_FAIR 0xD0000000 +#define PLB0_ACR_HBU_MASK 0x08000000 +#define PLB0_ACR_HBU_DISABLED 0x00000000 +#define PLB0_ACR_HBU_ENABLED 0x08000000 +#define PLB0_ACR_RDP_MASK 0x06000000 +#define PLB0_ACR_RDP_DISABLED 0x00000000 +#define PLB0_ACR_RDP_2DEEP 0x02000000 +#define PLB0_ACR_RDP_3DEEP 0x04000000 +#define PLB0_ACR_RDP_4DEEP 0x06000000 +#define PLB0_ACR_WRP_MASK 0x01000000 +#define PLB0_ACR_WRP_DISABLED 0x00000000 +#define PLB0_ACR_WRP_2DEEP 0x01000000 + +#define PLB1_ACR (PLB_ARBITER_BASE + 0x09) +#define PLB1_ACR_PPM_MASK 0xF0000000 +#define PLB1_ACR_PPM_FIXED 0x00000000 +#define PLB1_ACR_PPM_FAIR 0xD0000000 +#define PLB1_ACR_HBU_MASK 0x08000000 +#define PLB1_ACR_HBU_DISABLED 0x00000000 +#define PLB1_ACR_HBU_ENABLED 0x08000000 +#define PLB1_ACR_RDP_MASK 0x06000000 +#define PLB1_ACR_RDP_DISABLED 0x00000000 +#define PLB1_ACR_RDP_2DEEP 0x02000000 +#define PLB1_ACR_RDP_3DEEP 0x04000000 +#define PLB1_ACR_RDP_4DEEP 0x06000000 +#define PLB1_ACR_WRP_MASK 0x01000000 +#define PLB1_ACR_WRP_DISABLED 0x00000000 +#define PLB1_ACR_WRP_2DEEP 0x01000000 #endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/ @@ -156,35 +144,35 @@ line aligned data. */ #define CPR0_DCR_BASE 0x0C -#define cprcfga (CPR0_DCR_BASE+0x0) -#define cprcfgd (CPR0_DCR_BASE+0x1) +#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0) +#define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1) #define SDR_DCR_BASE 0x0E -#define sdrcfga (SDR_DCR_BASE+0x0) -#define sdrcfgd (SDR_DCR_BASE+0x1) +#define SDR0_CFGADDR (SDR_DCR_BASE + 0x0) +#define SDR0_CFGDATA (SDR_DCR_BASE + 0x1) #define SDRAM_DCR_BASE 0x10 -#define memcfga (SDRAM_DCR_BASE+0x0) -#define memcfgd (SDRAM_DCR_BASE+0x1) +#define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0) +#define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) #define EBC_DCR_BASE 0x12 -#define ebccfga (EBC_DCR_BASE+0x0) -#define ebccfgd (EBC_DCR_BASE+0x1) +#define EBC0_CFGADDR (EBC_DCR_BASE + 0x0) +#define EBC0_CFGDATA (EBC_DCR_BASE + 0x1) /* * Macros for indirect DCR access */ -#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) -#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) +#define mtcpr(reg, d) do { mtdcr(CPR0_CFGADDR,reg);mtdcr(CPR0_CFGDATA,d); } while (0) +#define mfcpr(reg, d) do { mtdcr(CPR0_CFGADDR,reg);d = mfdcr(CPR0_CFGDATA); } while (0) -#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) -#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) +#define mtebc(reg, d) do { mtdcr(EBC0_CFGADDR,reg);mtdcr(EBC0_CFGDATA,d); } while (0) +#define mfebc(reg, d) do { mtdcr(EBC0_CFGADDR,reg);d = mfdcr(EBC0_CFGDATA); } while (0) -#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) -#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) +#define mtsdram(reg, d) do { mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,d); } while (0) +#define mfsdram(reg, d) do { mtdcr(SDRAM0_CFGADDR,reg);d = mfdcr(SDRAM0_CFGDATA); } while (0) -#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) -#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) +#define mtsdr(reg, d) do { mtdcr(SDR0_CFGADDR,reg);mtdcr(SDR0_CFGDATA,d); } while (0) +#define mfsdr(reg, d) do { mtdcr(SDR0_CFGADDR,reg);d = mfdcr(SDR0_CFGDATA); } while (0) #ifndef __ASSEMBLY__ -- cgit v1.2.3 From 4c1883670acbf1cc83c04df1876235c3aedde128 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Wed, 9 Sep 2009 12:36:07 +0200 Subject: ppc4xx: Rename compactcenter to intip Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- include/configs/compactcenter.h | 437 ---------------------------------------- include/configs/intip.h | 437 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 437 insertions(+), 437 deletions(-) delete mode 100644 include/configs/compactcenter.h create mode 100644 include/configs/intip.h (limited to 'include') diff --git a/include/configs/compactcenter.h b/include/configs/compactcenter.h deleted file mode 100644 index f8a1bbb9829..00000000000 --- a/include/configs/compactcenter.h +++ /dev/null @@ -1,437 +0,0 @@ -/* - * (C) Copyright 2009 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * Based on include/configs/canyonlands.h - * (C) Copyright 2008 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * compactcenter.h - configuration for CompactCenter (460EX) - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -/* - * This config file is used for CompactCenter and DevCon-Center - */ -#define CONFIG_460EX 1 /* Specific PPC460EX */ -#ifdef CONFIG_DEVCONCENTER -#define CONFIG_HOSTNAME devconcenter -#define CONFIG_IDENT_STRING " devconcenter 0.02" -#else -#define CONFIG_HOSTNAME compactcenter -#define CONFIG_IDENT_STRING " compactcenter 0.02" -#endif -#define CONFIG_440 1 -#define CONFIG_4xx 1 /* ... PPC4xx family */ - -/* - * Include common defines/options for all AMCC eval boards - */ -#include "amcc-common.h" - -#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */ - -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_BOARD_TYPES 1 /* support board types */ -#define CONFIG_FIT -#define CFG_ALT_MEMTEST - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ -#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ -#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE - -/* EBC stuff */ -#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */ -#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* later mapped here */ -#define CONFIG_SYS_FLASH_SIZE (128 << 20) -#else -#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */ -#define CONFIG_SYS_FLASH_SIZE (64 << 20) -#endif - -#define CONFIG_SYS_NVRAM_BASE 0xE0000000 -#define CONFIG_SYS_UART_BASE 0xE0100000 -#define CONFIG_SYS_IO_BASE 0xE0200000 - -#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ -#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 -#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */ -#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xC8000000 -#else -#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000 -#endif -#define CONFIG_SYS_FLASH_BASE_PHYS \ - (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \ - | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) - -#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ -#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ -#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 - -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ - -#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */ - -/* - * Initial RAM & stack pointer (placed in OCM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ -#define CONFIG_SYS_INIT_RAM_END (4 << 10) -#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Serial Port - */ -#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ - -/* - * Environment - */ -/* - * Define here the location of the environment variables (FLASH). - */ -#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */ - -/* - * FLASH related - */ -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */ - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ -#ifdef CONFIG_DEVCONCENTER -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max num of sectors per chip*/ -#else -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ -#endif - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ - -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buff'd writes (20x faster) */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ - -/* - * DDR SDRAM - */ - -#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ - -#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ -#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ -#undef CONFIG_PPC4xx_DDR_METHOD_A - -/* DDR1/2 SDRAM Device Control Register Data Values */ -/* Memory Queue */ -#define CONFIG_SYS_SDRAM_R0BAS 0x0000f800 -#define CONFIG_SYS_SDRAM_R1BAS 0x00000000 -#define CONFIG_SYS_SDRAM_R2BAS 0x00000000 -#define CONFIG_SYS_SDRAM_R3BAS 0x00000000 -#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000 -#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008 -#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C80 -#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80 -#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000 - -/* SDRAM Controller */ -#define CONFIG_SYS_SDRAM0_MB0CF 0x00000201 -#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000 -#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000 -#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000 -#define CONFIG_SYS_SDRAM0_MCOPT1 0x05122000 -#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 -#define CONFIG_SYS_SDRAM0_MODT0 0x00000000 -#define CONFIG_SYS_SDRAM0_MODT1 0x00000000 -#define CONFIG_SYS_SDRAM0_MODT2 0x00000000 -#define CONFIG_SYS_SDRAM0_MODT3 0x00000000 -#define CONFIG_SYS_SDRAM0_CODT 0x00000020 -#define CONFIG_SYS_SDRAM0_RTR 0x06180000 -#define CONFIG_SYS_SDRAM0_INITPLR0 0xA8380000 -#define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400 -#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000 -#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000 -#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010000 -#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000542 -#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400 -#define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000 -#define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000 -#define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000 -#define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000 -#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442 -#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010380 -#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010000 -#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000 -#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000 -#define CONFIG_SYS_SDRAM0_RQDC 0x80000038 -#define CONFIG_SYS_SDRAM0_RFDC 0x003F0000 -#define CONFIG_SYS_SDRAM0_RDCC 0x80000000 -#define CONFIG_SYS_SDRAM0_DLCR 0x00000000 -#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000 -#define CONFIG_SYS_SDRAM0_WRDTR 0x84000800 -#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000 -#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232 -#define CONFIG_SYS_SDRAM0_SDTR3 0x090B0D15 -#define CONFIG_SYS_SDRAM0_MMODE 0x00000442 -#define CONFIG_SYS_SDRAM0_MEMODE 0x00000000 - -#define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */ - -/* - * I2C - */ -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ - -#define CONFIG_SYS_I2C_MULTI_EEPROMS -#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* I2C bootstrap EEPROM */ -#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54 -#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 -#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 - -/* I2C SYSMON */ -#define CONFIG_DTT_LM63 1 /* National LM63 */ -#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ -#define CONFIG_DTT_PWM_LOOKUPTABLE \ - { { 40, 10 }, { 50, 20 }, { 60, 40 } } -#define CONFIG_DTT_TACH_LIMIT 0xa10 - -/* RTC configuration */ -#define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * Ethernet - */ -#define CONFIG_IBM_EMAC4_V4 1 - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 - -#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */ -#define CONFIG_PHY1_ADDR 3 - -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CONFIG_PHY_DYNAMIC_ANEG 1 - -/* - * USB-OHCI - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_USB_STORAGE -#undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors*/ -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */ -#define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */ -#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000) -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -/* - * Default environment variables - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_AMCC_DEF_ENV \ - CONFIG_AMCC_DEF_ENV_POWERPC \ - CONFIG_AMCC_DEF_ENV_NOR_UPD \ - "kernel_addr=fc000000\0" \ - "fdt_addr=fc1e0000\0" \ - "ramdisk_addr=fc200000\0" \ - "pciconfighost=1\0" \ - "pcie_mode=RP:RP\0" \ - "" - -/* - * Commands additional to the ones defined in amcc-common.h - */ -#define CONFIG_CMD_CHIP_CONFIG -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DTT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_PCI -#define CONFIG_CMD_SDRAM -#define CONFIG_CMD_SNTP -#define CONFIG_CMD_USB - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* - * PCI stuff - */ -/* General PCI */ -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_PCI_CONFIG_HOST_BRIDGE -#define CONFIG_PCI_DISABLE_PCIE - -/* Board-specific PCI */ -#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ -#undef CONFIG_SYS_PCI_MASTER_INIT - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ - - -/* - * External Bus Controller (EBC) Setup - */ - -/* - * CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the - * boot EBC mapping only supports a maximum of 16MBytes - * (4.ff00.0000 - 4.ffff.ffff). - * To solve this problem, the FLASH has to get remapped to another - * EBC address which accepts bigger regions: - * - * 0xfc00.0000 -> 4.cc00.0000 - */ - - -/* Memory Bank 0 (NOR-FLASH) initialization */ -#define CONFIG_SYS_EBC_PB0AP 0x10055e00 -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000) - -/* Memory Bank 1 (NVRAM) initialization */ -#define CONFIG_SYS_EBC_PB1AP 0x02815480 -/* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/ -#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NVRAM_BASE | 0x18000) - -/* Memory Bank 2 (UART) initialization */ -#define CONFIG_SYS_EBC_PB2AP 0x02815480 -/* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/ -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_UART_BASE | 0x1A000) - -/* Memory Bank 3 (IO) initialization */ -#define CONFIG_SYS_EBC_PB3AP 0x02815480 -/* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/ -#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_IO_BASE | 0x1A000) - -/* - * PPC4xx GPIO Configuration - */ -/* 460EX: Use USB configuration */ -#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ -{ \ -/* GPIO Core 0 */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \ -{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \ -{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \ -{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \ -{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \ -{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \ -}, \ -{ \ -/* GPIO Core 1 */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \ -{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \ -{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \ -{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 USB_SERVICE_SUSPEND_N */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51 SPI_CSS_N */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52 FPGA_PROGRAM_UC_N */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 FPGA_INIT_UC_N */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54 WD_STROBE */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 LED_2_OUT */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56 LED_1_OUT */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61 STARTUP_FINISHED_N */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62 STARTUP_FINISHED */ \ -{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 SERVICE_PORT_ACTIVE */ \ -} \ -} - -#endif /* __CONFIG_H */ diff --git a/include/configs/intip.h b/include/configs/intip.h new file mode 100644 index 00000000000..4f7bc7e28dc --- /dev/null +++ b/include/configs/intip.h @@ -0,0 +1,437 @@ +/* + * (C) Copyright 2009 + * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de + * + * Based on include/configs/canyonlands.h + * (C) Copyright 2008 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * intip.h - configuration for CompactCenter aka intip (460EX) and DevCon-Center + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +/* + * This config file is used for CompactCenter(codename intip) and DevCon-Center + */ +#define CONFIG_460EX 1 /* Specific PPC460EX */ +#ifdef CONFIG_DEVCONCENTER +#define CONFIG_HOSTNAME devconcenter +#define CONFIG_IDENT_STRING " devconcenter 0.02" +#else +#define CONFIG_HOSTNAME intip +#define CONFIG_IDENT_STRING " intip 0.02" +#endif +#define CONFIG_440 1 +#define CONFIG_4xx 1 /* ... PPC4xx family */ + +/* + * Include common defines/options for all AMCC eval boards + */ +#include "amcc-common.h" + +#define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_TYPES 1 /* support board types */ +#define CONFIG_FIT +#define CFG_ALT_MEMTEST + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ +#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ +#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE + +/* EBC stuff */ +#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */ +#define CONFIG_SYS_FLASH_BASE 0xF8000000 /* later mapped here */ +#define CONFIG_SYS_FLASH_SIZE (128 << 20) +#else +#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped here */ +#define CONFIG_SYS_FLASH_SIZE (64 << 20) +#endif + +#define CONFIG_SYS_NVRAM_BASE 0xE0000000 +#define CONFIG_SYS_UART_BASE 0xE0100000 +#define CONFIG_SYS_IO_BASE 0xE0200000 + +#define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space */ +#define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4 +#ifdef CONFIG_DEVCONCENTER /* Devcon-Center has 128 MB of flash */ +#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xC8000000 +#else +#define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000 +#endif +#define CONFIG_SYS_FLASH_BASE_PHYS \ + (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) \ + | (u64)CONFIG_SYS_FLASH_BASE_PHYS_L) + +#define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ +#define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 + +#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ + +#define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */ + +/* + * Initial RAM & stack pointer (placed in OCM) + */ +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */ +#define CONFIG_SYS_INIT_RAM_END (4 << 10) +#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +/* + * Serial Port + */ +#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ + +/* + * Environment + */ +/* + * Define here the location of the environment variables (FLASH). + */ +#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */ + +/* + * FLASH related + */ +#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ +#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */ + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ +#ifdef CONFIG_DEVCONCENTER +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max num of sectors per chip*/ +#else +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/ +#endif + +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */ + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buff'd writes (20x faster) */ +#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */ + +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector*/ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#endif /* CONFIG_ENV_IS_IN_FLASH */ + +/* + * DDR SDRAM + */ + +#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ + +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ +#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ +#undef CONFIG_PPC4xx_DDR_METHOD_A + +/* DDR1/2 SDRAM Device Control Register Data Values */ +/* Memory Queue */ +#define CONFIG_SYS_SDRAM_R0BAS 0x0000f800 +#define CONFIG_SYS_SDRAM_R1BAS 0x00000000 +#define CONFIG_SYS_SDRAM_R2BAS 0x00000000 +#define CONFIG_SYS_SDRAM_R3BAS 0x00000000 +#define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000 +#define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008 +#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C80 +#define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80 +#define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000 + +/* SDRAM Controller */ +#define CONFIG_SYS_SDRAM0_MB0CF 0x00000201 +#define CONFIG_SYS_SDRAM0_MB1CF 0x00000000 +#define CONFIG_SYS_SDRAM0_MB2CF 0x00000000 +#define CONFIG_SYS_SDRAM0_MB3CF 0x00000000 +#define CONFIG_SYS_SDRAM0_MCOPT1 0x05122000 +#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT0 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT1 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT2 0x00000000 +#define CONFIG_SYS_SDRAM0_MODT3 0x00000000 +#define CONFIG_SYS_SDRAM0_CODT 0x00000020 +#define CONFIG_SYS_SDRAM0_RTR 0x06180000 +#define CONFIG_SYS_SDRAM0_INITPLR0 0xA8380000 +#define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400 +#define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000 +#define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000 +#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010000 +#define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000542 +#define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400 +#define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000 +#define CONFIG_SYS_SDRAM0_INITPLR8 0x8A880000 +#define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000 +#define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000 +#define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442 +#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010380 +#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010000 +#define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000 +#define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000 +#define CONFIG_SYS_SDRAM0_RQDC 0x80000038 +#define CONFIG_SYS_SDRAM0_RFDC 0x003F0000 +#define CONFIG_SYS_SDRAM0_RDCC 0x80000000 +#define CONFIG_SYS_SDRAM0_DLCR 0x00000000 +#define CONFIG_SYS_SDRAM0_CLKTR 0x40000000 +#define CONFIG_SYS_SDRAM0_WRDTR 0x84000800 +#define CONFIG_SYS_SDRAM0_SDTR1 0x80201000 +#define CONFIG_SYS_SDRAM0_SDTR2 0x32204232 +#define CONFIG_SYS_SDRAM0_SDTR3 0x090B0D15 +#define CONFIG_SYS_SDRAM0_MMODE 0x00000442 +#define CONFIG_SYS_SDRAM0_MEMODE 0x00000000 + +#define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */ + +/* + * I2C + */ +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */ + +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C bootstrap EEPROM */ +#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54 +#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 +#define CONFIG_4xx_CONFIG_BLOCKSIZE 16 + +/* I2C SYSMON */ +#define CONFIG_DTT_LM63 1 /* National LM63 */ +#define CONFIG_DTT_SENSORS { 0 } /* Sensor addresses */ +#define CONFIG_DTT_PWM_LOOKUPTABLE \ + { { 40, 10 }, { 50, 20 }, { 60, 40 } } +#define CONFIG_DTT_TACH_LIMIT 0xa10 + +/* RTC configuration */ +#define CONFIG_RTC_DS1337 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * Ethernet + */ +#define CONFIG_IBM_EMAC4_V4 1 + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 + +#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */ +#define CONFIG_PHY1_ADDR 3 + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_DYNAMIC_ANEG 1 + +/* + * USB-OHCI + */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_STORAGE +#undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors*/ +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */ +#define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */ +#define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000) +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 + +/* + * Default environment variables + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + "kernel_addr=fc000000\0" \ + "fdt_addr=fc1e0000\0" \ + "ramdisk_addr=fc200000\0" \ + "pciconfighost=1\0" \ + "pcie_mode=RP:RP\0" \ + "" + +/* + * Commands additional to the ones defined in amcc-common.h + */ +#define CONFIG_CMD_CHIP_CONFIG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_USB + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +/* + * PCI stuff + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_CONFIG_HOST_BRIDGE +#define CONFIG_PCI_DISABLE_PCIE + +/* Board-specific PCI */ +#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ +#undef CONFIG_SYS_PCI_MASTER_INIT + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + + +/* + * External Bus Controller (EBC) Setup + */ + +/* + * CompactCenter has 64MBytes of NOR FLASH (Spansion 29GL512), but the + * boot EBC mapping only supports a maximum of 16MBytes + * (4.ff00.0000 - 4.ffff.ffff). + * To solve this problem, the FLASH has to get remapped to another + * EBC address which accepts bigger regions: + * + * 0xfc00.0000 -> 4.cc00.0000 + */ + + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CONFIG_SYS_EBC_PB0AP 0x10055e00 +#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000) + +/* Memory Bank 1 (NVRAM) initialization */ +#define CONFIG_SYS_EBC_PB1AP 0x02815480 +/* BAS=NVRAM,BS=1MB,BU=R/W,BW=8bit*/ +#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_NVRAM_BASE | 0x18000) + +/* Memory Bank 2 (UART) initialization */ +#define CONFIG_SYS_EBC_PB2AP 0x02815480 +/* BAS=UART,BS=1MB,BU=R/W,BW=16bit*/ +#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_UART_BASE | 0x1A000) + +/* Memory Bank 3 (IO) initialization */ +#define CONFIG_SYS_EBC_PB3AP 0x02815480 +/* BAS=IO,BS=1MB,BU=R/W,BW=16bit*/ +#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_IO_BASE | 0x1A000) + +/* + * PPC4xx GPIO Configuration + */ +/* 460EX: Use USB configuration */ +#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \ +{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \ +}, \ +{ \ +/* GPIO Core 1 */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \ +{GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 USB_SERVICE_SUSPEND_N */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO51 SPI_CSS_N */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO52 FPGA_PROGRAM_UC_N */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 FPGA_INIT_UC_N */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO54 WD_STROBE */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 LED_2_OUT */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO56 LED_1_OUT */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO61 STARTUP_FINISHED_N */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO62 STARTUP_FINISHED */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 SERVICE_PORT_ACTIVE */ \ +} \ +} + +#endif /* __CONFIG_H */ -- cgit v1.2.3 From 2fddd44464d02e0f3ade06dabe0e165835fa61f0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 19 Aug 2009 08:10:08 +0200 Subject: microblaze: Short size of global data and fix malloc size If is full malloc area global, data are rewrite because there was bad size of malloc area. Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 72715f6ed9d..ca071a31bca 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -136,13 +136,13 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x1000) /* global pointer */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x1000 /* size of global data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size of global data */ /* start of global data */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) /* monitor code */ #define SIZE 0x40000 -#define CONFIG_SYS_MONITOR_LEN SIZE +#define CONFIG_SYS_MONITOR_LEN (SIZE - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_MONITOR_LEN) #define CONFIG_SYS_MONITOR_END (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_SYS_MALLOC_LEN SIZE -- cgit v1.2.3 From 3ceba1d45d007144d10368f91ff9e36f3b5f39a1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 20 Aug 2009 22:36:20 +0200 Subject: net: Remove old Xilinx Emac driver Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index ca071a31bca..4ab8ca39919 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -58,10 +58,7 @@ /*#define CONFIG_SYS_RESET_ADDRESS TEXT_BASE*/ /* ethernet */ -#ifdef XILINX_EMAC_BASEADDR - #define CONFIG_XILINX_EMAC 1 - #define CONFIG_SYS_ENET -#elif XILINX_EMACLITE_BASEADDR +#ifdef XILINX_EMACLITE_BASEADDR #define CONFIG_XILINX_EMACLITE 1 #define CONFIG_SYS_ENET #elif XILINX_LLTEMAC_BASEADDR -- cgit v1.2.3 From 13916abf996b127b681ddc26664c236ded28ba7f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 20 Aug 2009 22:44:02 +0200 Subject: microblaze: Remove AtmarkTechno Suzaku board Users should use microblaze-generic platform. This platform is longer not supported. Signed-off-by: Michal Simek --- include/configs/suzaku.h | 110 ----------------------------------------------- 1 file changed, 110 deletions(-) delete mode 100644 include/configs/suzaku.h (limited to 'include') diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h deleted file mode 100644 index 353e8db4270..00000000000 --- a/include/configs/suzaku.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * (C) Copyright 2004 Atmark Techno, Inc. - * - * Yasushi SHOJI - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MICROBLAZE 1 /* This is an MicroBlaze CPU */ -#define CONFIG_SUZAKU 1 /* on an SUZAKU Board */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 -#define CONFIG_SYS_FLASH_BASE 0xfff00000 -#define CONFIG_SYS_FLASH_SIZE 0x00400000 -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - (1024 * 1024)) -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ -#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - (1024 * 1024)) - -#define CONFIG_XILINX_UARTLITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* System Register (GPIO) */ -#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000 -#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0) - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_SAVEENV -#undef CONFIG_CMD_MEMORY -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_MISC - -#define CONFIG_SYS_UART1_BASE (0xFFFF2000) -#define CONFIG_SERIAL_BASE CONFIG_SYS_UART1_BASE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "SUZAKU> " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1 /* max number of sectors on one chip */ - -/*----------------------------------------------------------------------- - * NVRAM organization - */ -#define CONFIG_ENV_IS_NOWHERE 1 -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define XILINX_CLOCK_FREQ 50000000 -#define CONFIG_XILINX_CLOCK_FREQ XILINX_CLOCK_FREQ - -#endif /* __CONFIG_H */ -- cgit v1.2.3 From 0900bee9ab9818439b2d1298fa8909a88f74ec0d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 14 Aug 2009 13:41:17 +0200 Subject: microblaze: Enable hush parser With Hush parser is possible to change command line in dtb Signed-off-by: Michal Simek --- include/configs/microblaze-generic.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 4ab8ca39919..b486c7753c8 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -288,7 +288,7 @@ #define CONFIG_SYS_USR_EXCEP /* user exception */ #define CONFIG_SYS_HZ 1000 -#define CONFIG_PREBOOT "echo U-BOOT for $(hostname);setenv preboot;echo" +#define CONFIG_PREBOOT "echo U-BOOT for ${hostname};setenv preboot;echo" #define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" /* hardware flash protection */\ "nor0=ml401-0\0"\ @@ -298,4 +298,10 @@ #define CONFIG_CMDLINE_EDITING +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + #endif /* __CONFIG_H */ -- cgit v1.2.3 From 02f99901ed1c9d828e3ea117f94ce2264bf8389e Mon Sep 17 00:00:00 2001 From: Simon Kagstrom Date: Mon, 24 Aug 2009 09:09:50 +0200 Subject: Move __set/clear_bit from ubifs.h to bitops.h __set_bit and __clear_bit are defined in ubifs.h as well as in asm/include/bitops.h for some architectures. This patch moves the generic implementation to include/linux/bitops.h and uses that unless it's defined by the architecture. Signed-off-by: Simon Kagstrom --- include/asm-arm/bitops.h | 2 ++ include/asm-blackfin/bitops.h | 1 + include/asm-microblaze/bitops.h | 1 + include/asm-mips/bitops.h | 1 + include/linux/bitops.h | 38 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 43 insertions(+) (limited to 'include') diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index 4b8bab28373..1549da16933 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -29,6 +29,7 @@ static inline void __set_bit(int nr, volatile void *addr) { ((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7)); } +#define __set_bit extern void clear_bit(int nr, volatile void * addr); @@ -36,6 +37,7 @@ static inline void __clear_bit(int nr, volatile void *addr) { ((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7)); } +#define __clear_bit extern void change_bit(int nr, volatile void * addr); diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h index 2e55b6a6199..cc3685d35d7 100644 --- a/include/asm-blackfin/bitops.h +++ b/include/asm-blackfin/bitops.h @@ -79,6 +79,7 @@ static __inline__ void __set_bit(int nr, volatile void *addr) mask = 1 << (nr & 0x1f); *a |= mask; } +#define __set_bit /* * clear_bit() doesn't provide any barrier for the compiler. diff --git a/include/asm-microblaze/bitops.h b/include/asm-microblaze/bitops.h index 04ea0207eea..aac906102ab 100644 --- a/include/asm-microblaze/bitops.h +++ b/include/asm-microblaze/bitops.h @@ -75,6 +75,7 @@ extern __inline__ void __set_bit(int nr, volatile void * addr) mask = 1 << (nr & 0x1f); *a |= mask; } +#define __set_bit /* * clear_bit() doesn't provide any barrier for the compiler. diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 659ac9d3201..0c07b686a2d 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -90,6 +90,7 @@ static __inline__ void __set_bit(int nr, volatile void * addr) *m |= 1UL << (nr & 31); } +#define __set_bit /* * clear_bit - Clears a bit in memory diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 7d41ae62ccf..387a81813b9 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -1,6 +1,7 @@ #ifndef _LINUX_BITOPS_H #define _LINUX_BITOPS_H +#include /* * ffs: find first bit set. This is defined the same way as @@ -66,7 +67,44 @@ static inline unsigned int generic_hweight8(unsigned int w) return (res & 0x0F) + ((res >> 4) & 0x0F); } +#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG)) +#define BIT_WORD(nr) ((nr) / BITS_PER_LONG) + #include +/* linux/include/asm-generic/bitops/non-atomic.h */ + +#ifndef __set_bit +# define __set_bit generic_set_bit +#endif + +#ifndef __clear_bit +# define __clear_bit generic_clear_bit +#endif + +/** + * __set_bit - Set a bit in memory + * @nr: the bit to set + * @addr: the address to start counting from + * + * Unlike set_bit(), this function is non-atomic and may be reordered. + * If it's called on the same region of memory simultaneously, the effect + * may be that only one operation succeeds. + */ +static inline void generic_set_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p |= mask; +} + +static inline void generic_clear_bit(int nr, volatile unsigned long *addr) +{ + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p &= ~mask; +} #endif -- cgit v1.2.3 From 4b15de08fe4d2c9d12a3764394731018a763216b Mon Sep 17 00:00:00 2001 From: Simon Kagstrom Date: Mon, 24 Aug 2009 09:10:03 +0200 Subject: arm: Make arm bitops endianness-independent Bring over the bitop implementations from the Linux include/asm-generic/bitops/non-atomic.h to provide endianness-independence. Signed-off-by: Simon Kagstrom --- include/asm-arm/bitops.h | 47 +++++++++++++++++++---------------------------- 1 file changed, 19 insertions(+), 28 deletions(-) (limited to 'include') diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index 1549da16933..854e225c2f6 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -25,61 +25,52 @@ */ extern void set_bit(int nr, volatile void * addr); -static inline void __set_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7)); -} -#define __set_bit - extern void clear_bit(int nr, volatile void * addr); -static inline void __clear_bit(int nr, volatile void *addr) -{ - ((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7)); -} -#define __clear_bit - extern void change_bit(int nr, volatile void * addr); static inline void __change_bit(int nr, volatile void *addr) { - ((unsigned char *) addr)[nr >> 3] ^= (1U << (nr & 7)); + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + + *p ^= mask; } extern int test_and_set_bit(int nr, volatile void * addr); static inline int __test_and_set_bit(int nr, volatile void *addr) { - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval | mask; - return oldval & mask; + *p = old | mask; + return (old & mask) != 0; } extern int test_and_clear_bit(int nr, volatile void * addr); static inline int __test_and_clear_bit(int nr, volatile void *addr) { - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval & ~mask; - return oldval & mask; + *p = old & ~mask; + return (old & mask) != 0; } extern int test_and_change_bit(int nr, volatile void * addr); static inline int __test_and_change_bit(int nr, volatile void *addr) { - unsigned int mask = 1 << (nr & 7); - unsigned int oldval; + unsigned long mask = BIT_MASK(nr); + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); + unsigned long old = *p; - oldval = ((unsigned char *) addr)[nr >> 3]; - ((unsigned char *) addr)[nr >> 3] = oldval ^ mask; - return oldval & mask; + *p = old ^ mask; + return (old & mask) != 0; } extern int find_first_zero_bit(void * addr, unsigned size); -- cgit v1.2.3 From 52d61227b66d4099b39c8309ab37cb67ee09a405 Mon Sep 17 00:00:00 2001 From: Simon Kagstrom Date: Mon, 24 Aug 2009 09:10:12 +0200 Subject: Define ffs/fls for all architectures UBIFS requires fls(), which is not defined for arm (and some other architectures) and this patch adds it. The implementation is taken from Linux and is generic. ffs() is also defined for those that miss it. Signed-off-by: Simon Kagstrom --- include/asm-i386/bitops.h | 1 + include/asm-m68k/bitops.h | 1 + include/asm-nios/bitops.h | 1 + include/asm-nios2/bitops.h | 1 + include/asm-ppc/bitops.h | 2 ++ include/asm-sh/bitops.h | 2 ++ include/linux/bitops.h | 45 +++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 53 insertions(+) (limited to 'include') diff --git a/include/asm-i386/bitops.h b/include/asm-i386/bitops.h index b768e20fbb6..ac6285aa5f2 100644 --- a/include/asm-i386/bitops.h +++ b/include/asm-i386/bitops.h @@ -349,6 +349,7 @@ static __inline__ int ffs(int x) "1:" : "=r" (r) : "g" (x)); return r+1; } +#define ffs /** * hweightN - returns the hamming weight of a N-bit word diff --git a/include/asm-m68k/bitops.h b/include/asm-m68k/bitops.h index 0f9e8abe9c1..e0c35fa7b05 100644 --- a/include/asm-m68k/bitops.h +++ b/include/asm-m68k/bitops.h @@ -51,6 +51,7 @@ extern __inline__ int ffs(int x) return r; } #define __ffs(x) (ffs(x) - 1) +#define ffs #endif /* __KERNEL__ */ diff --git a/include/asm-nios/bitops.h b/include/asm-nios/bitops.h index 7744212b45a..8315fb7caaf 100644 --- a/include/asm-nios/bitops.h +++ b/include/asm-nios/bitops.h @@ -33,5 +33,6 @@ extern int test_and_set_bit(int nr, volatile void * a); extern int test_and_change_bit(int nr, volatile void * addr); extern int test_bit(int nr, volatile void * a); extern int ffs(int i); +#define ffs #endif /* _ASM_NIOS_BITOPS_H */ diff --git a/include/asm-nios2/bitops.h b/include/asm-nios2/bitops.h index e6c1a850d1b..b01a89d63cd 100644 --- a/include/asm-nios2/bitops.h +++ b/include/asm-nios2/bitops.h @@ -33,5 +33,6 @@ extern int test_and_set_bit(int nr, volatile void * a); extern int test_and_change_bit(int nr, volatile void * addr); extern int test_bit(int nr, volatile void * a); extern int ffs(int i); +#define ffs #endif /* __ASM_NIOS2_BITOPS_H */ diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h index daa66cf9185..9ed2f5d6faa 100644 --- a/include/asm-ppc/bitops.h +++ b/include/asm-ppc/bitops.h @@ -178,6 +178,7 @@ static __inline__ int fls(unsigned int x) { return __ilog2(x) + 1; } +#define fls /** * fls64 - find last set bit in a 64-bit word @@ -230,6 +231,7 @@ extern __inline__ int ffs(int x) { return __ilog2(x & -x) + 1; } +#define ffs /* * hweightN: returns the hamming weight (i.e. the number diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h index 410fba46eff..95167bd45ac 100644 --- a/include/asm-sh/bitops.h +++ b/include/asm-sh/bitops.h @@ -146,6 +146,8 @@ static inline int ffs (int x) } return r; } +#define ffs + #endif /* __KERNEL__ */ #endif /* __ASM_SH_BITOPS_H */ diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 387a81813b9..e14e6c7b14f 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -38,6 +38,43 @@ static inline int generic_ffs(int x) return r; } +/** + * fls - find last (most-significant) bit set + * @x: the word to search + * + * This is defined the same way as ffs. + * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. + */ +static inline int generic_fls(int x) +{ + int r = 32; + + if (!x) + return 0; + if (!(x & 0xffff0000u)) { + x <<= 16; + r -= 16; + } + if (!(x & 0xff000000u)) { + x <<= 8; + r -= 8; + } + if (!(x & 0xf0000000u)) { + x <<= 4; + r -= 4; + } + if (!(x & 0xc0000000u)) { + x <<= 2; + r -= 2; + } + if (!(x & 0x80000000u)) { + x <<= 1; + r -= 1; + } + return r; +} + + /* * hweightN: returns the hamming weight (i.e. the number * of bits set) of a N-bit word @@ -82,6 +119,14 @@ static inline unsigned int generic_hweight8(unsigned int w) # define __clear_bit generic_clear_bit #endif +#ifndef ffs +# define ffs generic_ffs +#endif + +#ifndef fls +# define fls generic_fls +#endif + /** * __set_bit - Set a bit in memory * @nr: the bit to set -- cgit v1.2.3 From a6e19d69f63c14b7672c65ca4b014621c6fd0201 Mon Sep 17 00:00:00 2001 From: Simon Kagstrom Date: Mon, 24 Aug 2009 09:10:16 +0200 Subject: arm: Define test_and_set_bit and test_and_clear bit for ARM Needed for (e.g.) ubifs support to work. Signed-off-by: Simon Kagstrom --- include/asm-arm/bitops.h | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index 854e225c2f6..3c7b00c48d0 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -17,6 +17,8 @@ #ifdef __KERNEL__ +#include + #define smp_mb__before_clear_bit() do { } while (0) #define smp_mb__after_clear_bit() do { } while (0) @@ -37,8 +39,6 @@ static inline void __change_bit(int nr, volatile void *addr) *p ^= mask; } -extern int test_and_set_bit(int nr, volatile void * addr); - static inline int __test_and_set_bit(int nr, volatile void *addr) { unsigned long mask = BIT_MASK(nr); @@ -49,7 +49,17 @@ static inline int __test_and_set_bit(int nr, volatile void *addr) return (old & mask) != 0; } -extern int test_and_clear_bit(int nr, volatile void * addr); +static inline int test_and_set_bit(int nr, volatile void * addr) +{ + unsigned long flags; + int out; + + local_irq_save(flags); + out = __test_and_set_bit(nr, addr); + local_irq_restore(flags); + + return out; +} static inline int __test_and_clear_bit(int nr, volatile void *addr) { @@ -61,6 +71,18 @@ static inline int __test_and_clear_bit(int nr, volatile void *addr) return (old & mask) != 0; } +static inline int test_and_clear_bit(int nr, volatile void * addr) +{ + unsigned long flags; + int out; + + local_irq_save(flags); + out = __test_and_clear_bit(nr, addr); + local_irq_restore(flags); + + return out; +} + extern int test_and_change_bit(int nr, volatile void * addr); static inline int __test_and_change_bit(int nr, volatile void *addr) -- cgit v1.2.3 From 3ca55bce9c8bf00df06a20487fafc16fa2f8084b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 11 Sep 2009 07:50:33 -0400 Subject: mpc8260: remove Ethernet node fixup to use generic FDT code. Remove Ethernet node fixup from mgcoge and muas3001 boards and modify its configs for the common mpc8260 code to use generic Ethernet fixup. Signed-off-by: Marcel Ziswiler Tested-by: Heiko Schocher --- include/configs/mgcoge.h | 1 + include/configs/muas3001.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index ea14948c465..b955749d8fc 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -70,6 +70,7 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_ETHER_INDEX 4 +#define CONFIG_HAS_ETH0 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000 # define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8) diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h index f031a17b271..ae033b2da55 100644 --- a/include/configs/muas3001.h +++ b/include/configs/muas3001.h @@ -74,6 +74,7 @@ #define CONFIG_ETHER_INDEX 1 #define CONFIG_ETHER_ON_FCC1 +#define CONFIG_HAS_ETH0 #define FCC_ENET /* -- cgit v1.2.3 From dcc87dd58db466caa2d66755c5ec9455edf42fe8 Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Thu, 20 Aug 2009 17:45:05 -0500 Subject: ppc/85xx: Ensure that MAS8 is zero when writing TLB entries. Its reset value is random, and we sometimes read uninitialized TLB arrays. Make sure that we don't retain MAS8 from reading such an entry if the VF bit in MAS8 is set, attempts to use the mapping will trap. Signed-off-by: Scott Wood --- include/asm-ppc/processor.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 0a4c66c9d9e..3764a5a51d5 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -518,6 +518,7 @@ #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ +#define SPRN_MAS8 0x155 /* MMU Assist Register 8 */ #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ @@ -720,6 +721,7 @@ #define MAS5 SPRN_MAS5 #define MAS6 SPRN_MAS6 #define MAS7 SPRN_MAS7 +#define MAS8 SPRN_MAS8 #if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx) #define DAR_DEAR DEAR -- cgit v1.2.3 From 0ead6f2ed7cf4e1f70dab5b529ad121e38359485 Mon Sep 17 00:00:00 2001 From: Roy Zang Date: Thu, 10 Sep 2009 14:44:48 +0800 Subject: ppc/85xx: Enable usb ehci support for p2020ds board Signed-off-by: Roy Zang Signed-off-by: Kumar Gala --- include/configs/P2020DS.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 46af7b9b069..2a2b9acf579 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -618,6 +618,15 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_EXT2 #endif +/* + * USB + */ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET + #undef CONFIG_WATCHDOG /* watchdog disabled */ /* -- cgit v1.2.3 From d30f9043539d372cf66406bc2f21bb8c20e67009 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 11 Sep 2009 11:27:00 -0500 Subject: ppc/85xx: Introduce low level write_tlb function Factor out the code we use to actually write a tlb entry. set_tlb is a logical view of the TLB while write_tlb is a low level matching the MAS registers. Signed-off-by: Kumar Gala --- include/asm-ppc/mmu.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index eda2959b7d0..8f382fd6ff8 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -450,6 +450,8 @@ extern void print_bats(void); (((epn) & MAS3_RPN) | (wimge)) #define FSL_BOOKE_MAS3(rpn, user, perms) \ (((rpn) & MAS3_RPN) | (user) | (perms)) +#define FSL_BOOKE_MAS7(rpn) \ + (((u64)(rpn)) >> 32) #define BOOKE_PAGESZ_1K 0 #define BOOKE_PAGESZ_4K 1 @@ -480,6 +482,8 @@ extern int find_tlb_idx(void *addr, u8 tlbsel); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); +extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); + #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \ .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot } -- cgit v1.2.3 From 206af3527c05e520e28d38a48a1d15433e34675d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 11 Sep 2009 11:30:30 -0500 Subject: ppc/85xx: Repack tlb_table to save space We can pack the initial tlb_table in MAS register format and use write_tlb to set things up. This savings can be helpful for NAND style first stage boot loaders. Signed-off-by: Kumar Gala --- include/asm-ppc/mmu.h | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 8f382fd6ff8..a019d0b390b 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -485,19 +485,18 @@ extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); extern void write_tlb(u32 _mas0, u32 _mas1, u32 _mas2, u32 _mas3, u32 _mas7); #define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \ - { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \ - .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot } + { .mas0 = FSL_BOOKE_MAS0(_tlb, _esel, 0), \ + .mas1 = FSL_BOOKE_MAS1(1, _iprot, 0, _ts, _sz), \ + .mas2 = FSL_BOOKE_MAS2(_epn, _wimge), \ + .mas3 = FSL_BOOKE_MAS3(_rpn, 0, _perms), \ + .mas7 = FSL_BOOKE_MAS7(_rpn), } struct fsl_e_tlb_entry { - u8 tlb; - u32 epn; - u64 rpn; - u8 perms; - u8 wimge; - u8 ts; - u8 esel; - u8 tsize; - u8 iprot; + u32 mas0; + u32 mas1; + u32 mas2; + u32 mas3; + u32 mas7; }; extern struct fsl_e_tlb_entry tlb_table[]; -- cgit v1.2.3 From 6e1385d5f8d137e741dfef02465d7dc328040ad7 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Fri, 11 Sep 2009 10:53:08 +0800 Subject: NAND boot: change NAND loader's relocate SP to CONFIG param So that we can set the NAND loader's relocate stack pointer to the value other than the relocate address + 0x10000. Signed-off-by: Mingkai Hu Acked-by: Kim Phillips Acked-by: Scott Wood Signed-off-by: Kumar Gala --- include/configs/MPC8313ERDB.h | 1 + include/configs/SIMPC8313.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 4bf05d20336..76b78942ba9 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -242,6 +242,7 @@ #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 #define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ | (2< Date: Fri, 11 Sep 2009 17:09:45 +0200 Subject: ppc4xx: Enable commands for FDT enabled Linux booting on AMCC Acadia Acadia still used the "old" arch/ppc bootm commands for booting Linux images without FDT. This patch now enables these fdt-aware boot commands for Acadia as well. Signed-off-by: Stefan Roese --- include/configs/acadia.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/acadia.h b/include/configs/acadia.h index b71010769f0..2fb48b641bc 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -225,7 +225,8 @@ */ #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_AMCC_DEF_ENV \ - CONFIG_AMCC_DEF_ENV_PPC \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_PPC_OLD \ CONFIG_AMCC_DEF_ENV_NOR_UPD \ CONFIG_AMCC_DEF_ENV_NAND_UPD \ "kernel_addr=fff10000\0" \ -- cgit v1.2.3 From 0413cfecea350000eab5e591a0965c3e3ee0ff00 Mon Sep 17 00:00:00 2001 From: Simon Kagstrom Date: Thu, 17 Sep 2009 15:15:52 +0200 Subject: Correct ffs/fls regression for PowerPC etc Commits 02f99901ed1c9d828e3ea117f94ce2264bf8389e 52d61227b66d4099b39c8309ab37cb67ee09a405 introduced a regression where platform-specific ffs/fls implementations were defined away. This patch corrects that by using PLATFORM_xxx instead of the name itself. Signed-off-by: Simon Kagstrom Acked-by: Kumar Gala Acked-by: Stefan Roese --- include/asm-arm/bitops.h | 8 -------- include/asm-blackfin/bitops.h | 10 +--------- include/asm-i386/bitops.h | 2 +- include/asm-m68k/bitops.h | 2 +- include/asm-microblaze/bitops.h | 3 ++- include/asm-mips/bitops.h | 13 +------------ include/asm-nios/bitops.h | 2 +- include/asm-nios2/bitops.h | 2 +- include/asm-ppc/bitops.h | 4 ++-- include/asm-sh/bitops.h | 2 +- include/linux/bitops.h | 8 ++++---- 11 files changed, 15 insertions(+), 41 deletions(-) (limited to 'include') diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h index 3c7b00c48d0..270f163eee3 100644 --- a/include/asm-arm/bitops.h +++ b/include/asm-arm/bitops.h @@ -124,14 +124,6 @@ static inline unsigned long ffz(unsigned long word) return k; } -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ - -#define ffs(x) generic_ffs(x) - /* * hweightN: returns the hamming weight (i.e. the number * of bits set) of a N-bit word diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h index cc3685d35d7..ab1fea55c87 100644 --- a/include/asm-blackfin/bitops.h +++ b/include/asm-blackfin/bitops.h @@ -79,7 +79,7 @@ static __inline__ void __set_bit(int nr, volatile void *addr) mask = 1 << (nr & 0x1f); *a |= mask; } -#define __set_bit +#define PLATFORM__SET_BIT /* * clear_bit() doesn't provide any barrier for the compiler. @@ -269,14 +269,6 @@ static __inline__ int find_next_zero_bit(void *addr, int size, int offset) return result + ffz(tmp); } -/* - * ffs: find first bit set. This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ - -#define ffs(x) generic_ffs(x) - /* * hweightN: returns the hamming weight (i.e. the number * of bits set) of a N-bit word diff --git a/include/asm-i386/bitops.h b/include/asm-i386/bitops.h index ac6285aa5f2..c7a38f237a5 100644 --- a/include/asm-i386/bitops.h +++ b/include/asm-i386/bitops.h @@ -349,7 +349,7 @@ static __inline__ int ffs(int x) "1:" : "=r" (r) : "g" (x)); return r+1; } -#define ffs +#define PLATFORM_FFS /** * hweightN - returns the hamming weight of a N-bit word diff --git a/include/asm-m68k/bitops.h b/include/asm-m68k/bitops.h index e0c35fa7b05..ad971b4f31f 100644 --- a/include/asm-m68k/bitops.h +++ b/include/asm-m68k/bitops.h @@ -51,7 +51,7 @@ extern __inline__ int ffs(int x) return r; } #define __ffs(x) (ffs(x) - 1) -#define ffs +#define PLATFORM_FFS #endif /* __KERNEL__ */ diff --git a/include/asm-microblaze/bitops.h b/include/asm-microblaze/bitops.h index aac906102ab..5d814f0eb0e 100644 --- a/include/asm-microblaze/bitops.h +++ b/include/asm-microblaze/bitops.h @@ -23,6 +23,7 @@ extern void __set_bit(int nr, volatile void * addr); extern void clear_bit(int nr, volatile void * addr); #define __clear_bit(nr, addr) clear_bit(nr, addr) +#define PLATFORM__CLEAR_BIT extern void change_bit(int nr, volatile void * addr); extern void __change_bit(int nr, volatile void * addr); @@ -75,7 +76,7 @@ extern __inline__ void __set_bit(int nr, volatile void * addr) mask = 1 << (nr & 0x1f); *a |= mask; } -#define __set_bit +#define PLATFORM__SET_BIT /* * clear_bit() doesn't provide any barrier for the compiler. diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h index 0c07b686a2d..1c8f4c05003 100644 --- a/include/asm-mips/bitops.h +++ b/include/asm-mips/bitops.h @@ -90,7 +90,7 @@ static __inline__ void __set_bit(int nr, volatile void * addr) *m |= 1UL << (nr & 31); } -#define __set_bit +#define PLATFORM__SET_BIT /* * clear_bit - Clears a bit in memory @@ -706,17 +706,6 @@ static __inline__ unsigned long ffz(unsigned long word) #ifdef __KERNEL__ -/** - * ffs - find first bit set - * @x: the word to search - * - * This is defined the same way as - * the libc and compiler builtin ffs routines, therefore - * differs in spirit from the above ffz (man ffs). - */ - -#define ffs(x) generic_ffs(x) - /* * hweightN - returns the hamming weight of a N-bit word * @x: the word to weigh diff --git a/include/asm-nios/bitops.h b/include/asm-nios/bitops.h index 8315fb7caaf..0be74f42b8f 100644 --- a/include/asm-nios/bitops.h +++ b/include/asm-nios/bitops.h @@ -33,6 +33,6 @@ extern int test_and_set_bit(int nr, volatile void * a); extern int test_and_change_bit(int nr, volatile void * addr); extern int test_bit(int nr, volatile void * a); extern int ffs(int i); -#define ffs +#define PLATFORM_FFS #endif /* _ASM_NIOS_BITOPS_H */ diff --git a/include/asm-nios2/bitops.h b/include/asm-nios2/bitops.h index b01a89d63cd..5776bda3e3f 100644 --- a/include/asm-nios2/bitops.h +++ b/include/asm-nios2/bitops.h @@ -33,6 +33,6 @@ extern int test_and_set_bit(int nr, volatile void * a); extern int test_and_change_bit(int nr, volatile void * addr); extern int test_bit(int nr, volatile void * a); extern int ffs(int i); -#define ffs +#define PLATFORM_FFS #endif /* __ASM_NIOS2_BITOPS_H */ diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h index 9ed2f5d6faa..adaf0914921 100644 --- a/include/asm-ppc/bitops.h +++ b/include/asm-ppc/bitops.h @@ -178,7 +178,7 @@ static __inline__ int fls(unsigned int x) { return __ilog2(x) + 1; } -#define fls +#define PLATFORM_FLS /** * fls64 - find last set bit in a 64-bit word @@ -231,7 +231,7 @@ extern __inline__ int ffs(int x) { return __ilog2(x & -x) + 1; } -#define ffs +#define PLATFORM_FFS /* * hweightN: returns the hamming weight (i.e. the number diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h index 95167bd45ac..c57d6284785 100644 --- a/include/asm-sh/bitops.h +++ b/include/asm-sh/bitops.h @@ -146,7 +146,7 @@ static inline int ffs (int x) } return r; } -#define ffs +#define PLATFORM_FFS #endif /* __KERNEL__ */ diff --git a/include/linux/bitops.h b/include/linux/bitops.h index e14e6c7b14f..e7243102986 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -111,19 +111,19 @@ static inline unsigned int generic_hweight8(unsigned int w) /* linux/include/asm-generic/bitops/non-atomic.h */ -#ifndef __set_bit +#ifndef PLATFORM__SET_BIT # define __set_bit generic_set_bit #endif -#ifndef __clear_bit +#ifndef PLATFORM__CLEAR_BIT # define __clear_bit generic_clear_bit #endif -#ifndef ffs +#ifndef PLATFORM_FFS # define ffs generic_ffs #endif -#ifndef fls +#ifndef PLATFORM_FLS # define fls generic_fls #endif -- cgit v1.2.3 From b55ae40249545eabb9d6bfb850b1400a32561b1f Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Wed, 9 Sep 2009 21:18:41 +0200 Subject: FDT: remove obsolete OF_CPU and OF_SOC macros. Signed-off-by: Marcel Ziswiler Acked-by: Guennadi Liakhovetski Acked-by: Heiko Schocher --- include/configs/IDS8247.h | 2 -- include/configs/MPC8260ADS.h | 1 - include/configs/linkstation.h | 2 -- include/configs/mgcoge.h | 2 -- include/configs/mpc7448hpc2.h | 1 - include/configs/muas3001.h | 2 -- include/configs/stxxtc.h | 1 - 7 files changed, 11 deletions(-) (limited to 'include') diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 4c4af054b2a..147a8b267da 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -125,8 +125,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8247@0" -#define OF_SOC "soc@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000" diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 942a4cc4876..677a1439c75 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -209,7 +209,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #if defined(CONFIG_OF_LIBFDT) -#define OF_CPU "cpu@0" #define OF_TBCLK (bd->bi_busfreq / 4) #endif diff --git a/include/configs/linkstation.h b/include/configs/linkstation.h index 2feb3ae31d4..16b464cf6da 100644 --- a/include/configs/linkstation.h +++ b/include/configs/linkstation.h @@ -96,8 +96,6 @@ #define CONFIG_OF_LIBFDT 1 -#define OF_CPU "PowerPC,603e" -#define OF_SOC "soc10x@80000000" #define OF_STDOUT_PATH "/soc10x/serial@80004600" /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ diff --git a/include/configs/mgcoge.h b/include/configs/mgcoge.h index b955749d8fc..55d1fc90fc6 100644 --- a/include/configs/mgcoge.h +++ b/include/configs/mgcoge.h @@ -347,8 +347,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8247@0" -#define OF_SOC "soc@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 4f98ba41a5d..be12186aca0 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -79,7 +79,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,7448@0" #define OF_TSI "tsi108@c0000000" #define OF_TBCLK (bd->bi_busfreq / 8) #define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808" diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h index ae033b2da55..c94daa3d033 100644 --- a/include/configs/muas3001.h +++ b/include/configs/muas3001.h @@ -405,8 +405,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 -#define OF_CPU "PowerPC,8270@0" -#define OF_SOC "soc@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #if defined(CONFIG_MUAS_DEV_BOARD) #define OF_STDOUT_PATH "/soc/cpm/serial@11a90" diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index d16262b6cff..585436604f2 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -509,7 +509,6 @@ typedef unsigned int led_id_t; /* pass open firmware flattened device tree */ #define CONFIG_OF_LIBFDT 1 -#define OF_CPU "PowerPC,MPC870@0" #define OF_TBCLK (MPC8XX_HZ / 16) #endif /* __CONFIG_H */ -- cgit v1.2.3 From 3202d33169df04da5cf3dea8c5ab0a902b90ecaa Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Wed, 16 Sep 2009 21:38:10 -0500 Subject: Remove deprecated 'autoscr' command/variables The more standard 'source' command provides identical functionality to the autoscr command. Environment variable names/values on the MVBC_P, MVBML7, kmeter1, mgcoge, and km8xx boards are updated to no longer refernce 'autoscr'. The 'autoscript' and 'autoscript_uname' environment variables are also removed. Signed-off-by: Peter Tyser Acked-by: Andre Schwarz Acked-by: Heiko Schocher --- include/configs/MVBC_P.h | 14 +++++++------- include/configs/MVBLM7.h | 14 +++++++------- include/configs/keymile-common.h | 6 +++--- 3 files changed, 17 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h index 0c228cb5a0d..8f6b16b93bf 100644 --- a/include/configs/MVBC_P.h +++ b/include/configs/MVBC_P.h @@ -73,8 +73,8 @@ #define MV_INITRD_LENGTH 0x00400000 #define MV_SCRATCH_ADDR 0x00000000 #define MV_SCRATCH_LENGTH MV_INITRD_LENGTH -#define MV_SOURCE_ADDR 0xff840000 -#define MV_SOURCE_ADDR2 0xff850000 +#define MV_SCRIPT_ADDR 0xff840000 +#define MV_SCRIPT_ADDR2 0xff850000 #define MV_DTB_ADDR 0xfffc0000 #define CONFIG_SHOW_BOOT_PROGRESS 1 @@ -130,9 +130,9 @@ #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_RESET_TO_RETRY 1000 -#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \ - then source ${autoscr_addr}; \ - else source ${autoscr_addr2}; \ +#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \ + then source ${script_addr}; \ + else source ${script_addr2}; \ fi;" #define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" @@ -150,8 +150,8 @@ "fpga=0\0" \ "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \ "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \ - "autoscr_addr=" MK_STR(MV_SOURCE_ADDR) "\0" \ - "autoscr_addr2=" MK_STR(MV_SOURCE_ADDR2) "\0" \ + "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \ + "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \ "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \ "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \ "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \ diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 80334bd607e..9835567838f 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -399,8 +399,8 @@ #define MV_FPGA_SIZE 0 #define MV_KERNEL_ADDR 0xff810000 #define MV_INITRD_ADDR 0xffb00000 -#define MV_SOURCE_ADDR 0xff804000 -#define MV_SOURCE_ADDR2 0xff806000 +#define MV_SCRIPT_ADDR 0xff804000 +#define MV_SCRIPT_ADDR2 0xff806000 #define MV_DTB_ADDR 0xff808000 #define MV_INITRD_LENGTH 0x00400000 @@ -410,9 +410,9 @@ #define MV_DTB_ADDR_RAM 0x00600000 #define MV_INITRD_ADDR_RAM 0x01000000 -#define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \ - then source ${autoscr_addr}; \ - else source ${autoscr_addr2}; \ +#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \ + then source ${script_addr}; \ + else source ${script_addr2}; \ fi;" #define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" @@ -425,8 +425,8 @@ "fpga=0\0" \ "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \ "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \ - "autoscr_addr=" MK_STR(MV_SOURCE_ADDR) "\0" \ - "autoscr_addr2=" MK_STR(MV_SOURCE_ADDR2) "\0" \ + "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \ + "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \ "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \ "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \ "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \ diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h index 0cc1b3b59ce..80c41a49688 100644 --- a/include/configs/keymile-common.h +++ b/include/configs/keymile-common.h @@ -171,7 +171,7 @@ "kernel_addr_r=200000\0" \ "fdt_addr_r=600000\0" \ "ram_ws=800000 \0" \ - "autoscr_ws=780000 \0" \ + "script_ws=780000 \0" \ "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \ xstr(CONFIG_HOSTNAME) ".dtb\0" \ "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" \ @@ -253,8 +253,8 @@ "set_new_esw_script=setenv new_esw_script " \ "new_esw_0x${IVM_BoardId}_0x${IVM_HWKey}.scr \0" \ "new_esw=run set_new_esw_script; " \ - "tftp ${autoscr_ws} ${new_esw_script}; " \ - "iminfo ${autoscr_ws}; source ${autoscr_ws} \0" \ + "tftp ${script_ws} ${new_esw_script}; " \ + "iminfo ${script_ws}; source ${script_ws} \0" \ "bootlimit=0 \0" \ CONFIG_KM_DEF_ENV_IOMUX \ CONFIG_KM_DEF_ENV_PRIVATE \ -- cgit v1.2.3 From 3a8f28d0a6d9f8505017680233064c13e4587174 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Wed, 16 Sep 2009 22:03:07 -0500 Subject: ppc: Clean up calling of misc_init_r() during init Remove board-specific #ifdefs for calling misc_init_r() during initializtion Signed-off-by: Peter Tyser Acked-by: Heiko Schocher --- include/configs/CCM.h | 1 + include/configs/CPCI405.h | 1 + include/configs/CPCI4052.h | 1 + include/configs/CPCI405AB.h | 1 + include/configs/CPCI405DT.h | 1 + include/configs/W7OLMC.h | 1 + include/configs/W7OLMG.h | 1 + include/configs/cogent_mpc8260.h | 1 + include/configs/cogent_mpc8xx.h | 1 + include/configs/lwmon.h | 5 +++-- include/configs/pcu_e.h | 2 ++ include/configs/sc3.h | 1 + 12 files changed, 15 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/CCM.h b/include/configs/CCM.h index d1c293ff0ad..8a944207d7f 100644 --- a/include/configs/CCM.h +++ b/include/configs/CCM.h @@ -37,6 +37,7 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU ... */ #define CONFIG_CCM 1 /* on a Card Controller Module */ +#define CONFIG_MISC_INIT_R /* Call misc_init_r() */ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index fca6de0c6bc..d131aeaf43b 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -38,6 +38,7 @@ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index fd045660897..07c4e359955 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -40,6 +40,7 @@ #undef CONFIG_CPCI405_6U /* enable this for 6U boards */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index d718ed40a3d..c78552bbd42 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -40,6 +40,7 @@ #define CONFIG_CPCI405AB 1 /* ...and special AB version */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 09df47082b6..59e0778f6a3 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -39,6 +39,7 @@ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index 40e4735b681..c0179150c2b 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -40,6 +40,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index a62f1b4d578..1d4ad13ed3b 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -40,6 +40,7 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */ +#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h index c580230225d..566565aad2c 100644 --- a/include/configs/cogent_mpc8260.h +++ b/include/configs/cogent_mpc8260.h @@ -38,6 +38,7 @@ #define CONFIG_CPM2 1 /* Has a CPM2 */ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_MISC_INIT_R /* Use misc_init_r() */ /* Cogent Modular Architecture options */ #define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */ diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h index 17bd9a02742..750c0df0c58 100644 --- a/include/configs/cogent_mpc8xx.h +++ b/include/configs/cogent_mpc8xx.h @@ -37,6 +37,7 @@ #define CONFIG_COGENT 1 /* using Cogent Modular Architecture */ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_MISC_INIT_R /* Use misc_init_r() */ /* Cogent Modular Architecture options */ #define CONFIG_CMA286_60_OLD 1 /* ...on an old CMA286-60 CPU module */ diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index 8f00773216a..be20d729095 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -47,8 +47,9 @@ #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 #endif -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f() */ +#define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init() */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ #define CONFIG_LCD 1 /* use LCD controller ... */ #define CONFIG_HLD1045 1 /* ... with a HLD1045 display */ diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h index 65173811706..11ad9ca927f 100644 --- a/include/configs/pcu_e.h +++ b/include/configs/pcu_e.h @@ -42,6 +42,8 @@ #define CONFIG_MPC860T 1 #define CONFIG_PCU_E 1 /* ...on a PCU E board */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ + #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_BAUDRATE 9600 diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 7e00ab8c710..57637607af8 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -63,6 +63,7 @@ #define CONFIG_405GP 1 #define CONFIG_BOARD_EARLY_INIT_F 1 +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ /* * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range -- cgit v1.2.3 From 004eca0c9ba328de457d5dc9ef8805639dfef893 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Wed, 16 Sep 2009 22:03:08 -0500 Subject: ppc: Clean up calling of phy_reset() during init Remove board-specific #ifdefs for calling phy_reset() during initializtion Signed-off-by: Peter Tyser --- include/configs/CCM.h | 1 + include/configs/ELPT860.h | 1 + include/configs/IP860.h | 1 + include/configs/IVML24.h | 2 ++ include/configs/IVMS8.h | 2 ++ include/configs/MPC8260ADS.h | 1 + include/configs/MPC8266ADS.h | 1 + include/configs/MPC8560ADS.h | 1 + include/configs/RPXsuper.h | 1 + include/configs/SBC8540.h | 1 + include/configs/SPD823TS.h | 2 ++ include/configs/pcu_e.h | 1 + include/configs/sbc8560.h | 1 + include/configs/stxgp3.h | 1 + 14 files changed, 17 insertions(+) (limited to 'include') diff --git a/include/configs/CCM.h b/include/configs/CCM.h index 8a944207d7f..3f4a2c103e3 100644 --- a/include/configs/CCM.h +++ b/include/configs/CCM.h @@ -38,6 +38,7 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU ... */ #define CONFIG_CCM 1 /* on a Card Controller Module */ #define CONFIG_MISC_INIT_R /* Call misc_init_r() */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h index ff58ea92237..0f56302003b 100644 --- a/include/configs/ELPT860.h +++ b/include/configs/ELPT860.h @@ -57,6 +57,7 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ /* BOOT arguments */ #define CONFIG_PREBOOT \ diff --git a/include/configs/IP860.h b/include/configs/IP860.h index 125aa6c8025..be63ea5736b 100644 --- a/include/configs/IP860.h +++ b/include/configs/IP860.h @@ -36,6 +36,7 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ #define CONFIG_IP860 1 /* ...on a IP860 board */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #define CONFIG_BAUDRATE 9600 diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h index cd100df0577..1a4924e1e6d 100644 --- a/include/configs/IVML24.h +++ b/include/configs/IVML24.h @@ -52,6 +52,8 @@ #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ #define CONFIG_8xx_GCLK_FREQ 50331648 +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ + #define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */ #if 0 diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h index 125cb4b2037..256cabd0368 100644 --- a/include/configs/IVMS8.h +++ b/include/configs/IVMS8.h @@ -49,6 +49,8 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 115200 +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ + #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ #define CONFIG_8xx_GCLK_FREQ 50331648 diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 677a1439c75..39b8b8fce4f 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -81,6 +81,7 @@ #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ /* allow serial and ethaddr to be overwritten */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index 4fd86d3923f..b0162c3971b 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -54,6 +54,7 @@ #define CONFIG_CPM2 1 /* Has a CPM2 */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ /* allow serial and ethaddr to be overwritten */ #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index c1a1a6d923e..8ddce5c699d 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -48,6 +48,7 @@ #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ /* * sysclk for MPC85xx diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h index e97ef9565ad..da962f3b937 100644 --- a/include/configs/RPXsuper.h +++ b/include/configs/RPXsuper.h @@ -189,6 +189,7 @@ #define CONFIG_CPM2 1 /* Has a CPM2 */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ /* * Miscellaneous configurable options diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 7239f8409de..272b5dd56cb 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -77,6 +77,7 @@ #undef CONFIG_BTB /* toggle branch predition */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h index 4181a400e88..fa77882cfd1 100644 --- a/include/configs/SPD823TS.h +++ b/include/configs/SPD823TS.h @@ -36,6 +36,8 @@ #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ #define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ + #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h index 11ad9ca927f..3aee206ad76 100644 --- a/include/configs/pcu_e.h +++ b/include/configs/pcu_e.h @@ -43,6 +43,7 @@ #define CONFIG_PCU_E 1 /* ...on a PCU E board */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 4fa501da5eb..46c94bf16be 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -71,6 +71,7 @@ #undef CONFIG_BTB /* toggle branch predition */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 0424e2978e3..86b231ca8ee 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -66,6 +66,7 @@ #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -- cgit v1.2.3 From 91d599044caac4a8c228115b16cf3b073f902080 Mon Sep 17 00:00:00 2001 From: Dirk Eibach Date: Mon, 21 Sep 2009 13:27:14 +0200 Subject: ppc4xx: Make DDR2 timing for intip more robust DDR2 timing for intip was on the edge for some of the available chips for this board. Now it is verfied to work with all of them. Signed-off-by: Dirk Eibach Signed-off-by: Stefan Roese --- include/configs/intip.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/configs/intip.h b/include/configs/intip.h index 4f7bc7e28dc..19f12fa770a 100644 --- a/include/configs/intip.h +++ b/include/configs/intip.h @@ -172,7 +172,7 @@ #define CONFIG_SYS_SDRAM_R3BAS 0x00000000 #define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000 #define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008 -#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C80 +#define CONFIG_SYS_SDRAM_CONF1LL 0x80001C00 #define CONFIG_SYS_SDRAM_CONF1HB 0x80001C80 #define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000 @@ -181,7 +181,7 @@ #define CONFIG_SYS_SDRAM0_MB1CF 0x00000000 #define CONFIG_SYS_SDRAM0_MB2CF 0x00000000 #define CONFIG_SYS_SDRAM0_MB3CF 0x00000000 -#define CONFIG_SYS_SDRAM0_MCOPT1 0x05122000 +#define CONFIG_SYS_SDRAM0_MCOPT1 0x05120000 #define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000 #define CONFIG_SYS_SDRAM0_MODT0 0x00000000 #define CONFIG_SYS_SDRAM0_MODT1 0x00000000 @@ -193,7 +193,7 @@ #define CONFIG_SYS_SDRAM0_INITPLR1 0x81900400 #define CONFIG_SYS_SDRAM0_INITPLR2 0x81020000 #define CONFIG_SYS_SDRAM0_INITPLR3 0x81030000 -#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010000 +#define CONFIG_SYS_SDRAM0_INITPLR4 0x81010002 #define CONFIG_SYS_SDRAM0_INITPLR5 0xE4000542 #define CONFIG_SYS_SDRAM0_INITPLR6 0x81900400 #define CONFIG_SYS_SDRAM0_INITPLR7 0x8A880000 @@ -201,21 +201,21 @@ #define CONFIG_SYS_SDRAM0_INITPLR9 0x8A880000 #define CONFIG_SYS_SDRAM0_INITPLR10 0x8A880000 #define CONFIG_SYS_SDRAM0_INITPLR11 0x81000442 -#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010380 -#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010000 +#define CONFIG_SYS_SDRAM0_INITPLR12 0x81010382 +#define CONFIG_SYS_SDRAM0_INITPLR13 0x81010002 #define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000 #define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000 #define CONFIG_SYS_SDRAM0_RQDC 0x80000038 -#define CONFIG_SYS_SDRAM0_RFDC 0x003F0000 -#define CONFIG_SYS_SDRAM0_RDCC 0x80000000 +#define CONFIG_SYS_SDRAM0_RFDC 0x00000257 +#define CONFIG_SYS_SDRAM0_RDCC 0x40000000 #define CONFIG_SYS_SDRAM0_DLCR 0x00000000 #define CONFIG_SYS_SDRAM0_CLKTR 0x40000000 -#define CONFIG_SYS_SDRAM0_WRDTR 0x84000800 +#define CONFIG_SYS_SDRAM0_WRDTR 0x84000823 #define CONFIG_SYS_SDRAM0_SDTR1 0x80201000 #define CONFIG_SYS_SDRAM0_SDTR2 0x32204232 -#define CONFIG_SYS_SDRAM0_SDTR3 0x090B0D15 +#define CONFIG_SYS_SDRAM0_SDTR3 0x090C0D15 #define CONFIG_SYS_SDRAM0_MMODE 0x00000442 -#define CONFIG_SYS_SDRAM0_MEMODE 0x00000000 +#define CONFIG_SYS_SDRAM0_MEMODE 0x00000002 #define CONFIG_SYS_MBYTES_SDRAM 256 /* 256MB */ -- cgit v1.2.3 From c569ad6e1e8768a0fec513ffc156412240b7eb35 Mon Sep 17 00:00:00 2001 From: Werner Pfister Date: Mon, 21 Sep 2009 14:49:56 +0200 Subject: digsy_mtc: Add TCR register value for RTC (DS1339) Signed-off-by: Werner Pfister Signed-off-by: Detlev Zundel --- include/configs/digsy_mtc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/digsy_mtc.h b/include/configs/digsy_mtc.h index 2bdaaace33b..7a1a7c33315 100644 --- a/include/configs/digsy_mtc.h +++ b/include/configs/digsy_mtc.h @@ -244,6 +244,7 @@ */ #define CONFIG_RTC_DS1337 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_DS1339_TCR_VAL 0xAB /* diode + 4k resistor */ /* * Flash configuration -- cgit v1.2.3 From 71ce9bd7f551e44c4ddb4c985c095da6d3452d79 Mon Sep 17 00:00:00 2001 From: Eric Millbrandt Date: Mon, 21 Sep 2009 11:05:55 -0500 Subject: galaxy5200: enable version environment variable Add version environment variable configuration to the galaxy5200 board header file. Signed-off-by: Eric Millbrandt Edited commit message. Signed-off-by: Wolfgang Denk --- include/configs/galaxy5200.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index f4b520d39f2..3b67ea90bcc 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -367,6 +367,8 @@ CONFIG_BOOTP_DNS2 | \ CONFIG_BOOTP_SEND_HOSTNAME ) +#define CONFIG_VERSION_VARIABLE 1 + /* * Various low-level settings */ -- cgit v1.2.3 From 202d94875c98b7b573f136c4f353609758ed9733 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 15 Sep 2009 22:21:58 -0500 Subject: ppc/85xx: Fix LCRR_CLKDIV defines For some reason the CLKDIV field varies between SoC in how it interprets the bit values. All 83xx and early (e500v1) PQ3 devices support: clk/2: CLKDIV = 2 clk/4: CLKDIV = 4 clk/8: CLKDIV = 8 Newer PQ3 (e500v2) and MPC86xx support: clk/4: CLKDIV = 2 clk/8: CLKDIV = 4 clk/16: CLKDIV = 8 Ensure that the MPC86xx and MPC85xx still get the same behavior and make the defines reflect their logical view (not the value of the field). Signed-off-by: Kumar Gala Acked-by: Peter Tyser --- include/asm-ppc/fsl_lbc.h | 8 ++++++++ include/configs/XPEDITE5170.h | 2 +- include/configs/XPEDITE5200.h | 2 +- include/configs/XPEDITE5370.h | 2 +- 4 files changed, 11 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index a28082e56e6..08d31e12e4c 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -311,9 +311,17 @@ */ #define LCRR_CLKDIV 0x0000001F #define LCRR_CLKDIV_SHIFT 0 +#if defined(CONFIG_MPC83xx) || defined (CONFIG_MPC8540) || \ + defined(CONFIG_MPC8541) || defined (CONFIG_MPC8555) || \ + defined(CONFIG_MPC8560) #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 #define LCRR_CLKDIV_8 0x00000008 +#else +#define LCRR_CLKDIV_4 0x00000002 +#define LCRR_CLKDIV_8 0x00000004 +#define LCRR_CLKDIV_16 0x00000008 +#endif /* LTEDR - Transfer Error Check Disable Register */ diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h index 242466ae120..30642cdfef4 100644 --- a/include/configs/XPEDITE5170.h +++ b/include/configs/XPEDITE5170.h @@ -122,7 +122,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_2 | LCRR_EADC_3) +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) /* * NAND flash configuration diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index deda20843af..d79231b8b8b 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -103,7 +103,7 @@ * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) /* * NAND flash configuration diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 3c58ebe39b2..65e1afddc69 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -116,7 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) /* * NAND flash configuration -- cgit v1.2.3 From 0e905ac28b1e039d74e63232293972bff6b5a0ce Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Fri, 18 Sep 2009 11:45:09 +0800 Subject: ppc/85xx: simplify the top makefile for 36-bit config for mpc8536ds Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- include/configs/MPC8536DS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 4746e2ead56..faca8059a1f 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -27,7 +27,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_MPC8536DS_36BIT +#ifdef CONFIG_MK_36BIT #define CONFIG_PHYS_64BIT 1 #endif -- cgit v1.2.3 From f9edcc10e6cb497dd7dcbaf691cfd1859abae27a Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 10 Sep 2009 16:23:45 -0500 Subject: ppc/85xx: Simplify the top makefile for 36-bit config for MPC8572DS Signed-off-by: Kumar Gala --- include/configs/MPC8572DS.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 55c1f29b192..000f8f62d62 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -27,6 +27,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -- cgit v1.2.3 From a0f9e0e0f06033807de0ae017ad4d9cf5ddff84b Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 10 Sep 2009 16:26:37 -0500 Subject: ppc/85xx: Simplify the top makefile for 36-bit config for P2020DS Signed-off-by: Kumar Gala --- include/configs/P2020DS.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 2a2b9acf579..b48c1999f8f 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -27,6 +27,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -- cgit v1.2.3 From 62ca21c442e18fec118ec83e183d64ea49966ce7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 10 Sep 2009 16:31:53 -0500 Subject: ppc/85xx: Simplify the top makefile for P1_P2_RDB boards Signed-off-by: Kumar Gala --- include/configs/P1_P2_RDB.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include') diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 6d44d6c8ddb..8e97ad06819 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -30,6 +30,19 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_MK_P1011RDB +#define CONFIG_P1011 +#endif +#ifdef CONFIG_MK_P1020RDB +#define CONFIG_P1020 +#endif +#ifdef CONFIG_MK_P2010RDB +#define CONFIG_P2010 +#endif +#ifdef CONFIG_MK_P2020RDB +#define CONFIG_P2020 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ -- cgit v1.2.3 From 002741ae862c1c7e3dad89d020e392e6add1c05d Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Sat, 19 Sep 2009 11:20:54 -0500 Subject: ppc/85xx: Clean up use of LAWAR defines On 85xx platforms we shouldn't be using any LAWAR_* defines but using the LAW_* ones provided by fsl-law.h. Rename any such uses and limit the LAWAR_ to the 83xx platform as the only user so we will get compile errors in the future. Signed-off-by: Kumar Gala --- include/asm-ppc/mmu.h | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index a019d0b390b..d516d91403d 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -504,13 +504,7 @@ extern int num_tlb_entries; #endif #endif -#if defined(CONFIG_MPC86xx) -#define LAWBAR_BASE_ADDR 0x00FFFFFF -#define LAWAR_TRGT_IF 0x01F00000 -#else -#define LAWBAR_BASE_ADDR 0x000FFFFF -#define LAWAR_TRGT_IF 0x00F00000 -#endif +#ifdef CONFIG_MPC83xx #define LAWAR_EN 0x80000000 #define LAWAR_SIZE 0x0000003F @@ -554,6 +548,7 @@ extern int num_tlb_entries; #define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22) #define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23) #define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24) +#endif #ifdef CONFIG_440 /* General */ -- cgit v1.2.3 From 7b1f1399e876587e0a268a5a471dd444bfbc3114 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 18 Sep 2009 19:08:39 -0400 Subject: sbc8548: delete unused MPC8548CDS info carried over from port There are a couple defines and PCI bridge quirks related to the PCI backplane of the MPC8548CDS that have no meaning in the context of the port to the sbc8548 board, so delete them. Also, the form factor of the sbc8548 is a standalone board with a single PCI-X and a single PCI-e slot. That pretty much guarantees that it will never be a PCI agent itself, so the host/agent and root complex/end node distinctions have been removed. Similarly, since there is no physical connector mapping to PCI2, so all references of PCI2 in the board support files have been removed as well. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- include/configs/sbc8548.h | 9 --------- 1 file changed, 9 deletions(-) (limited to 'include') diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 838b4db9ad4..3d05afbba16 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -42,7 +42,6 @@ #undef CONFIG_PCI1 /* PCI controller 1 */ #undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO -#undef CONFIG_PCI2 #undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ @@ -343,14 +342,6 @@ #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif -#ifdef CONFIG_LEGACY -#define BRIDGE_ID 17 -#define VIA_ID 2 -#else -#define BRIDGE_ID 28 -#define VIA_ID 4 -#endif - #if defined(CONFIG_PCI) #define CONFIG_NET_MULTI -- cgit v1.2.3 From 9b3ba24f18900633a394416cc056c44a1a6eb754 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 18 Sep 2009 19:08:41 -0400 Subject: sbc8548: enable access to second bank of flash The sbc8548 has a 64MB SODIMM flash module off of CS6 that previously wasn't enumerated by u-boot. There were already BR6/OR6 settings for it [used by cpu_init_f()] but there was no TLB entry and it wasn't in the list of flash banks reported to u-boot. The location of the 64MB flash is "pulled back" 8MB from a 64MB boundary, in order to allow address space for the 8MB boot flash that is at the end of 32 bit address space. This means creating two 4MB TLB entries for the 8MB chunk, and then expanding the original boot flash entry to 64MB in order to cover the 8MB boot flash and the remainder (56MB) of the user flash. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- include/configs/sbc8548.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 3d05afbba16..5c1411f6689 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -163,6 +163,7 @@ */ #define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ +#define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */ #define CONFIG_SYS_BR0_PRELIM 0xff800801 @@ -171,9 +172,10 @@ #define CONFIG_SYS_OR0_PRELIM 0xff806e65 #define CONFIG_SYS_OR6_PRELIM 0xf8006e65 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ + CONFIG_SYS_ALT_FLASH} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ #undef CONFIG_SYS_FLASH_CHECKSUM #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -- cgit v1.2.3 From 11d5a629f8a40f9d7cffc74e58f4e3ed258e56ab Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:04 -0400 Subject: sbc8548: correct local bus SDRAM size from 64M to 128M The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- include/configs/sbc8548.h | 42 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 5c1411f6689..009931df55c 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -197,13 +197,13 @@ #define CONFIG_SYS_EEPROM_BASE 0xf8b00000 /* - * SDRAM on the Local Bus + * SDRAM on the Local Bus (CS3 and CS4) */ #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ /* - * Base Register 3 and Option Register 3 configure SDRAM. + * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. * * For BR3, need: @@ -221,7 +221,7 @@ #define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * * For OR3, need: * 64MB mask for AM, OR3[0:7] = 1111 1100 @@ -236,6 +236,40 @@ #define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 +/* + * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. + * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. + * + * For BR4, need: + * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 + * + */ + +#define CONFIG_SYS_BR4_PRELIM 0xf4001861 + +/* + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR4, need: + * 64MB mask for AM, OR3[0:7] = 1111 1100 + * XAM, OR3[17:18] = 11 + * 10 columns OR3[19-21] = 011 + * 12 rows OR3[23-25] = 011 + * EAD set for extra time OR[31] = 0 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 + */ + +#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 + #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -- cgit v1.2.3 From a8b3e90f798e0cca5f11c912f9d0823a1c5b6c24 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:01 -0400 Subject: fsl_pci: create a SET_STD_PCI_INFO() helper wrapper Recycle the recently added PCI-e wrapper used to reduce board duplication of code by creating a similar version for plain PCI. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_pci.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index b9972dabe37..2790da7ed16 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -173,6 +173,18 @@ struct fsl_pci_info { int fsl_pci_init_port(struct fsl_pci_info *pci_info, struct pci_controller *hose, int busno); +#define SET_STD_PCI_INFO(x, num) \ +{ \ + x.regs = CONFIG_SYS_PCI##num##_ADDR; \ + x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \ + x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \ + x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \ + x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \ + x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \ + x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \ + x.pci_num = num; \ +} + #define SET_STD_PCIE_INFO(x, num) \ { \ x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ -- cgit v1.2.3 From fdc7eb90b504daa020f290604d50da8f7cb70d8a Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:05 -0400 Subject: sbc8548: update PCI/PCI-e support code The PCI/PCI-e support for the sbc8548 was based on an earlier version of what the MPC8548CDS board was using, and in its current state it won't even compile. This re-syncs it to match the latest codebase and makes use of the new shared PCI functions to reduce board duplication. It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and similarly it coalesces the PCI and PCI-e mem into one single TLB. Both PCI-x and PCI-e have been tested with intel e1000 cards under linux (with an accompanying dts change in place) Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- include/configs/sbc8548.h | 45 ++++++++++++++++++++++++--------------------- 1 file changed, 24 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 009931df55c..1f340ed7fba 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -42,7 +42,14 @@ #undef CONFIG_PCI1 /* PCI controller 1 */ #undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO -#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ + +#ifdef CONFIG_PCI +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#endif +#ifdef CONFIG_PCIE1 +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#endif #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -343,31 +350,27 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#ifdef CONFIG_PCI2 -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ -#endif +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ #endif #ifdef CONFIG_RIO @@ -386,7 +389,7 @@ #undef CONFIG_EEPRO100 #undef CONFIG_TULIP -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ -- cgit v1.2.3 From 2738bc8df65ec905094d83f62f87fed123a03b9c Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Sun, 20 Sep 2009 20:36:06 -0400 Subject: sbc8548: allow enabling PCI via a make config option Prior to this commit, to enable PCI, you had to go manually edit the board config header, and if you had 33MHz PCI, you had to manually change CONFIG_SYS_NS16550_CLK too, which was not real user friendly, This adds the typical PCI and clock speed make targets to the toplevel Makefile in accordance with what is being done with other boards (i.e. using the "-t" to mkconfig). Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- include/configs/sbc8548.h | 43 +++++++++++++++++++++++++++++++++---------- 1 file changed, 33 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 1f340ed7fba..d10792a22da 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -1,5 +1,5 @@ /* - * Copyright 2007 Wind River Systems + * Copyright 2007,2009 Wind River Systems * Copyright 2007 Embedded Specialties, Inc. * Copyright 2004, 2007 Freescale Semiconductor. * @@ -24,23 +24,40 @@ /* * sbc8548 board configuration file - * - * Please refer to doc/README.sbc85xx for more info. - * + * Please refer to doc/README.sbc8548 for more info. */ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_PCI +#define CONFIG_PCI +#define CONFIG_PCI1 +#endif + +#ifdef CONFIG_MK_66 +#define CONFIG_SYS_CLK_DIV 1 +#endif + +#ifdef CONFIG_MK_33 +#define CONFIG_SYS_CLK_DIV 2 +#endif + +#ifdef CONFIG_MK_PCIE +#define CONFIG_PCIE1 +#endif + +/* + * High Level Configuration Options + */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_SBC8548 1 /* SBC8548 board specific */ -#undef CONFIG_PCI /* enable any pci type devices */ -#undef CONFIG_PCI1 /* PCI controller 1 */ -#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO #ifdef CONFIG_PCI @@ -58,7 +75,13 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ -#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */ +/* + * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] + */ +#ifndef CONFIG_SYS_CLK_DIV +#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ +#endif +#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) /* * These can be toggled for performance analysis, otherwise use default. @@ -316,7 +339,7 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 400000000 /* get_bus_freq(0) */ +#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} -- cgit v1.2.3 From 928435d11b898870415910efff87a4d6399cecb8 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Mon, 21 Sep 2009 17:19:17 -0400 Subject: sbc85x0: tidy up Makefile to use new configuration script. Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the boards config header. This takes advantage of that for the sbc8540/sbc8560 boards. There were a couple of cheezy comments pointing at incorrect files, or files that don't exist, so I've cleaned those up too. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- include/configs/SBC8540.h | 19 +++++++++++-------- include/configs/sbc8560.h | 17 ++++++++++++----- 2 files changed, 23 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 272b5dd56cb..7cde39bf2a5 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -24,22 +24,25 @@ * MA 02111-1307 USA */ -/* mpc8560ads board configuration file */ -/* please refer to doc/README.mpc85xx for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file +/* + * sbc8540 board configuration file. */ #ifndef __CONFIG_H #define __CONFIG_H -#if XXX -#define DEBUG /* General debug */ -#define ET_DEBUG +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_66 +#define CONFIG_PCI_66 #endif + #define TSEC_DEBUG -/* High Level Configuration Options */ +/* + * High Level Configuration Options + */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 46c94bf16be..a6b15f74c9c 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -24,16 +24,23 @@ * MA 02111-1307 USA */ -/* sbc8560 board configuration file */ -/* please refer to doc/README.sbc8560 for more info */ -/* make sure you change the MAC address and other network params first, - * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file +/* + * sbc8560 board configuration file. */ #ifndef __CONFIG_H #define __CONFIG_H -/* High Level Configuration Options */ +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_66 +#define CONFIG_PCI_66 +#endif + +/* + * High Level Configuration Options + */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ -- cgit v1.2.3 From 266139b88b43ae1d87abb5f5431e6f57b801795f Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Tue, 22 Sep 2009 14:53:34 +0800 Subject: immap_85xx: add porpllsr's plat ratio definition Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- include/asm-ppc/immap_85xx.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index e7d412dba23..39fdb8e94f4 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1542,6 +1542,8 @@ typedef struct ccsr_gur { #endif #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 +#define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e +#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 uint porbmsr; /* 0xe0004 - POR boot mode status register */ #define MPC85xx_PORBMSR_HA 0x00070000 #define MPC85xx_PORBMSR_HA_SHIFT 16 -- cgit v1.2.3 From 01df521217957d77d53c2d570183eded7030938f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 16 Sep 2009 09:43:12 -0500 Subject: ppc/p4080: Add p4080 platform immap definitions The p4080 SoC has a significant amount of commonality with the 85xx/PQ3 platform. We reuse the 85xx immap and just add new definitions for local access and global utils. The global utils is now broken into global utils, clocking and run control/power management. The offsets from CCSR for a number of blocks have also changed. We introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of platform from the new p4080 platform. We don't use QoirQ as there are products (like p2020) that are PQ3 based platforms but have the QoirQ name. Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_lbc.h | 4 + include/asm-ppc/immap_85xx.h | 287 ++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 271 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h index 08d31e12e4c..5723de643a4 100644 --- a/include/asm-ppc/fsl_lbc.h +++ b/include/asm-ppc/fsl_lbc.h @@ -317,6 +317,10 @@ #define LCRR_CLKDIV_2 0x00000002 #define LCRR_CLKDIV_4 0x00000004 #define LCRR_CLKDIV_8 0x00000008 +#elif defined(CONFIG_FSL_CORENET) +#define LCRR_CLKDIV_8 0x00000002 +#define LCRR_CLKDIV_16 0x00000004 +#define LCRR_CLKDIV_32 0x00000008 #else #define LCRR_CLKDIV_4 0x00000002 #define LCRR_CLKDIV_8 0x00000004 diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 39fdb8e94f4..100dfe10692 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -16,6 +16,29 @@ #include #include +typedef struct ccsr_local { + u32 ccsrbarh; /* 0x0 - Control Configuration Status Registers Base Address Register High */ + u32 ccsrbarl; /* 0x4 - Control Configuration Status Registers Base Address Register Low */ + u32 ccsrar; /* 0x8 - Configuration, Control, and Status Attribute Register */ +#define CCSRAR_C 0x80000000 /* Commit */ + u8 res1[4]; + u32 altcbarh; /* 0x10 - Alternate Configuration Base Address Register High */ + u32 altcbarl; /* 0x14 - Alternate Configuration Base Address Register Low */ + u32 altcar; /* 0x18 - Alternate Configuration Attribute Register */ + u8 res2[4]; + u32 bstrh; /* 0x20 - Boot space translation register high */ + u32 bstrl; /* 0x24 - Boot space translation register Low */ + u32 bstrar; /* 0x28 - Boot space translation attributes register */ + u8 res3[0xbd4]; + struct { + u32 lawbarh; /* 0xc00 + n * 0x10 - LAW0 base address register high */ + u32 lawbarl; /* 0xc04 + n * 0x10 - LAW0 base address register low */ + u32 lawar; /* 0xc08 + n * 0x10 - LAW0 attributes register */ + u8 res4[4]; + } law[32]; + u8 res35[0x204]; +} ccsr_local_t; + /* * Local-Access Registers and ECM Registers(0x0000-0x2000) */ @@ -165,7 +188,21 @@ typedef struct ccsr_ddr { uint debug_2; uint debug_3; uint debug_4; - char res12[240]; + uint debug_5; + uint debug_6; + uint debug_7; + uint debug_8; + uint debug_9; + uint debug_10; + uint debug_11; + uint debug_12; + uint debug_13; /* +0xF30 */ + uint debug_14; + uint debug_15; + uint debug_16; + uint debug_17; + uint debug_18; /* +0xF44 */ + char res12[184]; } ccsr_ddr_t; /* @@ -1531,6 +1568,193 @@ typedef struct par_io { /* * Global Utilities Register Block(0xe_0000-0xf_ffff) */ +#ifdef CONFIG_FSL_CORENET +typedef struct ccsr_gur { + u32 porsr1; /* 0xe0000 - POR status register */ + u8 res1[28]; /* 0xe0004 - 0xe001c Reserved: PORSRn */ + u32 gpporcr1; /* 0xe0020 - General-purpose POR configuration register */ + u8 res2[12]; + u32 gpiocr; /* 0xe0030 - GPIO control register */ + u8 res3[12]; + u32 gpoutdr; /* 0xe0040 - General-purpose output data register */ + u8 res4[12]; + u32 gpindr; /* 0xe0050 - General-purpose input data register */ + u8 res5[12]; + u32 pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ + u8 res6[12]; + u32 devdisr; /* 0xe0070 - Device disable control */ +#define FSL_CORENET_DEVDISR_PCIE1 0x80000000 +#define FSL_CORENET_DEVDISR_PCIE2 0x40000000 +#define FSL_CORENET_DEVDISR_PCIE3 0x20000000 +#define FSL_CORENET_DEVDISR_RMU 0x08000000 +#define FSL_CORENET_DEVDISR_SRIO1 0x04000000 +#define FSL_CORENET_DEVDISR_SRIO2 0x02000000 +#define FSL_CORENET_DEVDISR_DMA1 0x00400000 +#define FSL_CORENET_DEVDISR_DMA2 0x00200000 +#define FSL_CORENET_DEVDISR_DDR1 0x00100000 +#define FSL_CORENET_DEVDISR_DDR2 0x00080000 +#define FSL_CORENET_DEVDISR_DBG 0x00010000 +#define FSL_CORENET_DEVDISR_NAL 0x00008000 +#define FSL_CORENET_DEVDISR_ELBC 0x00001000 +#define FSL_CORENET_DEVDISR_USB1 0x00000800 +#define FSL_CORENET_DEVDISR_USB2 0x00000400 +#define FSL_CORENET_DEVDISR_ESDHC 0x00000100 +#define FSL_CORENET_DEVDISR_GPIO 0x00000080 +#define FSL_CORENET_DEVDISR_ESPI 0x00000040 +#define FSL_CORENET_DEVDISR_I2C1 0x00000020 +#define FSL_CORENET_DEVDISR_I2C2 0x00000010 +#define FSL_CORENET_DEVDISR_DUART1 0x00000002 +#define FSL_CORENET_DEVDISR_DUART2 0x00000001 + u8 res7[12]; + u32 powmgtcsr; /* 0xe0080 - Power management status and control register */ + u8 res8[12]; + u32 coredisru; /* 0xe0090 - uppper portion for support of 64 cores */ + u32 coredisrl; /* 0xe0094 - lower portion for support of 64 cores */ + u8 res9[8]; + u32 pvr; /* 0xe00a0 - Processor version register */ + u32 svr; /* 0xe00a4 - System version register */ + u8 res10[8]; + u32 rstcr; /* 0xe00b0 - Reset control register */ + u32 rstrqpblsr; /* 0xe00b4 - Reset request preboot loader status register */ + u8 res11[8]; + u32 rstrqmr1; /* 0xe00c0 - Reset request mask register */ + u8 res12[4]; /* Reserved: RSTRQMR2 */ + u32 rstrqsr1; /* 0xe00c8 - Reset request status register */ + u8 res13[4]; /* Reserved: RSTRQSR2 */ + u8 res14[4]; /* Reserved: RSTRQWDTMRU */ + u32 rstrqwdtmrl; /* 0xe00d4 - Reset request WDT mask register */ + u8 res15[4]; /* Reserved: RSTRQWDTSRU */ + u32 rstrqwdtsrl; /* 0xe00dc - Reset request WDT status register */ + u8 res16[4]; /* Reserved: BRRU max total of 2 for up to 64 cores */ + u32 brrl; /* 0xe00e4 Boot release register */ + u8 res17[24]; + u32 rcwsr[16]; /* 0xe0100 - 0xe013c: Reset control word status register */ +#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 +#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000 +#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15 +#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 +#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 +#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 + u8 res18[192]; /* Reserved: RCWSRn (max total of 64)*/ + u32 scratchrw[4]; /* 0xe0200 - 0xe020c: Scratch Read/Write register */ + u8 res19[240]; /* Reserved: SCRATCHRWn (max total of 64)*/ + u32 scratchw1r[4]; /* 0xe0300 - 0xe030c: Scratch Read register (Write once) */ + u8 res20[240]; /* Reserved: SCRATCHW1Rn (max total of 64)*/ + u32 scrtsr[8]; /* 0xe0400 - 0xe041c: Core reset status register */ + u8 res21[224]; /* Reserved: CRSTSRn (max total of 64 for up to 64 cores)*/ + u32 pex1liodnr; /* 0xe0500 PCI Express 1 Logical I/O Device Number register*/ + u32 pex2liodnr; /* 0xe0504 PCI Express 2 Logical I/O Device Number register*/ + u32 pex3liodnr; /* 0xe0508 PCI Express 3 Logical I/O Device Number register*/ + u32 pex4liodnr; /* 0xe050c PCI Express 4 Logical I/O Device Number register*/ + u32 rio1liodnr; /* 0xe0510 RIO 1 Logical I/O Device Number register*/ + u32 rio2liodnr; /* 0xe0514 RIO 2 Logical I/O Device Number register*/ + u32 rio3liodnr; /* 0xe0518 RIO 3 Logical I/O Device Number register*/ + u32 rio4liodnr; /* 0xe051c RIO 4 Logical I/O Device Number register*/ + u32 usb1liodnr; /* 0xe0520 USB 1 Logical I/O Device Number register*/ + u32 usb2liodnr; /* 0xe0524 USB 2 Logical I/O Device Number register*/ + u32 usb3liodnr; /* 0xe0528 USB 3 Logical I/O Device Number register*/ + u32 usb4liodnr; /* 0xe052c USB 4 Logical I/O Device Number register*/ + u32 sdmmc1liodnr; /* 0xe0530 SD/MMC 1 Logical I/O Device Number register*/ + u32 sdmmc2liodnr; /* 0xe0534 SD/MMC 2 Logical I/O Device Number register*/ + u32 sdmmc3liodnr; /* 0xe0538 SD/MMC 3 Logical I/O Device Number register*/ + u32 sdmmc4liodnr; /* 0xe053c SD/MMC 4 Logical I/O Device Number register*/ + u32 rmuliodnr; /* 0xe0540 RIO Message Unit Logical I/O Device Number register*/ + u32 rduliodnr; /* 0xe0544 RIO Doorbell Unit Logical I/O Device Number register*/ + u32 rpwuliodnr; /* 0xe0548 RIO Port Write Unit Logical I/O Device Number register*/ + u8 res22[52]; /* Reserved: for future LIODN register expansion */ + u32 dma1liodnr; /* 0xe0580 DMA 1 Logical I/O Device Number register*/ + u32 dma2liodnr; /* 0xe0584 DMA 2 Logical I/O Device Number register*/ + u32 dma3liodnr; /* 0xe0588 DMA 3 Logical I/O Device Number register*/ + u32 dma4liodnr; /* 0xe058c DMA 4 Logical I/O Device Number register*/ + u8 res23[48]; /* Reserved: for future LIODN register expansion */ + u8 res24[64]; /* Reserved */ + u32 pblsr; /* 0xe0600 Preboot loader status register*/ + u32 pamubypenr; /* 0xe0604 PAMU bypass enable register*/ + u32 dmacr1; /* 0xe0608 DMA control register*/ + u8 res25[4]; /* Reserved: DMACR2 (max total of 2)*/ + u32 gensr1; /* 0xe0610 General status register*/ + u8 res26[12]; /* Reserved: GENSRn (max total of 4)*/ + u32 gencr1; /* 0xe0620 General control register*/ + u8 res27[12]; /* Reserved: GENCRn (max total of 4)*/ + u8 res28[4]; /* Reserved: CGENSRU (upper portion for support of 64 cores) */ + u32 cgensrl; /* 0xe0634 Core general status register*/ + u8 res29[8]; /* Reserved */ + u8 res30[4]; /* Reserved: CGENCRU (upper portion for support of 64 cores) */ + u32 cgencrl; /* 0xe0634 Core general control register*/ + u8 res31[184]; /* Reserved 0xe0648 - 0xe06fc */ + u32 sriopstecr; /* 0xe0700 SRIO prescaler timer enable control register*/ + u8 res32[2300]; /* Reserved 0xe0704 - 0xe0ffc */ +} ccsr_gur_t; + +typedef struct ccsr_clk { + u32 clkc0csr; /* 0xe1000 - Core 0 Clock control/status register */ + u8 res1[0x1c]; + u32 clkc1csr; /* 0xe1020 - Core 1 Clock control/status register */ + u8 res2[0x1c]; + u32 clkc2csr; /* 0xe1040 - Core 2 Clock control/status register */ + u8 res3[0x1c]; + u32 clkc3csr; /* 0xe1060 - Core 3 Clock control/status register */ + u8 res4[0x1c]; + u32 clkc4csr; /* 0xe1080 - Core 4 Clock control/status register */ + u8 res5[0x1c]; + u32 clkc5csr; /* 0xe10a0 - Core 5 Clock control/status register */ + u8 res6[0x1c]; + u32 clkc6csr; /* 0xe10c0 - Core 6 Clock control/status register */ + u8 res7[0x1c]; + u32 clkc7csr; /* 0xe10e0 - Core 7 Clock control/status register */ + u8 res8[0x71c]; + u32 pllc1gsr; /* 0xe1800 - Cluster PLL 1 General Status Register */ + u8 res10[0x1c]; + u32 pllc2gsr; /* 0xe1820 - Cluster PLL 2 General Status Register */ + u8 res11[0x1c]; + u32 pllc3gsr; /* 0xe1840 - Cluster PLL 3 General Status Register */ + u8 res12[0x1c]; + u32 pllc4gsr; /* 0xe1860 - Cluster PLL 4 General Status Register */ + u8 res13[0x39c]; + u32 pllpgsr; /* 0xe1c00 - Platform PLL General Status Register */ + u8 res14[0x1c]; + u32 plldgsr; /* 0xe1c20 - DDR PLL General Status Register */ + u8 res15[0x3dc]; +} ccsr_clk_t; + +typedef struct ccsr_rcpm { + u8 res1[4]; /* 0xe2000 - Reserved */ + u32 cdozsrl; /* 0xe2004 - Core Doze Status Register */ + u8 res2[4]; /* 0xe2008 - Reserved */ + u32 cdozcrl; /* 0xe200c - Core Doze Control Register */ + u8 res3[4]; /* 0xe2010 - Reserved */ + u32 cnapsrl; /* 0xe2014 - Core Nap Status Register */ + u8 res4[4]; /* 0xe2018 - Reserved */ + u32 cnapcrl; /* 0xe201c - Core Nap Control Register */ + u8 res5[4]; /* 0xe2020 - Reserved */ + u32 cdozpsrl; /* 0xe2024 - Core Doze Previous Status Register */ + u8 res6[4]; /* 0xe2028 - Reserved */ + u32 cdozpcrl; /* 0xe202c - Core Doze Previous Control Register */ + u8 res7[4]; /* 0xe2030 - Reserved */ + u32 cwaitsrl; /* 0xe2034 - Core Wait Status Register */ + u8 res8[8]; /* Reserved */ + u32 powmgtcsr; /* 0xe2040 - Power Mangement Control & Status Register */ + u8 res9[12]; /* Reserved */ + u32 ippdexpcr0; /* 0xe2050 - IP Powerdown Exception Control Register 0 */ + u8 res10[12]; /* Reserved */ + u8 res11[4]; /* Reserved */ + u32 cpmimrl; /* 0xe2064 - Core Power Management Interrupt Masking Register */ + u8 res12[4]; /* Reserved */ + u32 cpmcimrl; /* 0xe206c - Core Power Management Critical Interrupt Masking Register */ + u8 res13[4]; /* Reserved */ + u32 cpmmcimrl; /* 0xe2074 - Core Power Management Machine Check Interrupt Masking Register */ + u8 res14[4]; /* Reserved */ + u32 cpmnmimrl; /* 0xe207c - Core Power Management NMI Masking Register */ + u8 res15[4]; /* Reserved */ + u32 ctbenrl; /* 0xe2084 - Core Time Base Enable Register */ + u8 res16[4]; /* Reserved */ + u32 ctbclkselrl; /* 0xe208c - Core Time Base Clock Select Register */ + u8 res17[4]; /* Reserved */ + u32 ctbhltcrl; /* 0xe2094 - Core Time Base Halt Control Register */ + u8 res18[0xf68]; +} ccsr_rcpm_t; + +#else typedef struct ccsr_gur { uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ #ifdef CONFIG_MPC8536 @@ -1647,42 +1871,65 @@ typedef struct ccsr_gur { uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */ char res15[61648]; /* 0xe0f30 to 0xefffff */ } ccsr_gur_t; +#endif + +#ifdef CONFIG_FSL_CORENET +#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 +#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x9000 +#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 +#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 +#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x100000 +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 +#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 +#define CONFIG_SYS_MPC85xx_QMAN_OFFSET 0x318000 +#define CONFIG_SYS_MPC85xx_BMAN_OFFSET 0x31a000 +#else +#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 +#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000 +#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000 +#define CONFIG_SYS_MPC85xx_DDR2_OFFSET 0x6000 +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000 +#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000 +#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 +#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 +#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 +#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 +#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 +#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 +#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 +#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 +#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 +#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000 +#endif + +#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 +#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 -#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000) +#define CONFIG_SYS_MPC85xx_QMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_QMAN_OFFSET) +#define CONFIG_SYS_MPC85xx_BMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_BMAN_OFFSET) #define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) -#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000) +#define CONFIG_SYS_FSL_CORENET_CCM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) +#define CONFIG_SYS_FSL_CORENET_CLK_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) +#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) #define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) -#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000) #define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) -#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000) #define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) #define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) -#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000) #define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) #define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) #define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) -#define CONFIG_SYS_MPC85xx_GPIO_OFFSET (0xF000) -#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) +#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) #define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) #define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) -#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000) #define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) -#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000) #define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) -#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000) #define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) -#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000) #define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) -#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000) #define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000) #define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100) #define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 #define CONFIG_SYS_MPC85xx_USB_ADDR \ -- cgit v1.2.3 From 418ec8584343f04048e2cc7ee96b6b29be54ad97 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Mar 2009 02:32:23 -0500 Subject: ppc/p4080: Add support for CoreNet style platform LAWs On CoreNet based platforms the LAW address is split between an high & low register and we no longer shift the address. Also, the target IDs on CoreNet platforms have been completely re-assigned. Additionally, added a new find_law() API to which LAW an address hits in. This is need for the CoreNet style boot release code since it will need to determine what the target ID should be set to for boot window translation. Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use it elsewhere. Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_law.h | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/fsl_law.h b/include/asm-ppc/fsl_law.h index e06a1a6e0e1..31bb7545b53 100644 --- a/include/asm-ppc/fsl_law.h +++ b/include/asm-ppc/fsl_law.h @@ -1,8 +1,18 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + #ifndef _FSL_LAW_H_ #define _FSL_LAW_H_ #include +#define LAW_EN 0x80000000 + #define SET_LAW_ENTRY(idx, a, sz, trgt) \ { .index = idx, .addr = a, .size = sz, .trgt_id = trgt } @@ -36,6 +46,25 @@ enum law_size { LAW_SIZE_32G, }; +#ifdef CONFIG_FSL_CORENET +enum law_trgt_if { + LAW_TRGT_IF_PCIE_1 = 0x00, + LAW_TRGT_IF_PCIE_2 = 0x01, + LAW_TRGT_IF_PCIE_3 = 0x02, + LAW_TRGT_IF_RIO_1 = 0x08, + LAW_TRGT_IF_RIO_2 = 0x09, + + LAW_TRGT_IF_DDR_1 = 0x10, + LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */ + LAW_TRGT_IF_DDR_INTRLV = 0x14, + + LAW_TRGT_IF_BMAN = 0x18, + LAW_TRGT_IF_DCSR = 0x1d, + LAW_TRGT_IF_LBC = 0x1f, + LAW_TRGT_IF_QMAN = 0x3c, +}; +#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1 +#else enum law_trgt_if { LAW_TRGT_IF_PCI = 0x00, LAW_TRGT_IF_PCI_2 = 0x01, @@ -64,6 +93,7 @@ enum law_trgt_if { #if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI #endif +#endif /* CONFIG_FSL_CORENET */ struct law_entry { int index; @@ -76,6 +106,7 @@ extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id); extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id); +extern struct law_entry find_law(phys_addr_t addr); extern void disable_law(u8 idx); extern void init_laws(void); extern void print_laws(void); -- cgit v1.2.3 From 7e4259bba4c56536760e42d32dacfb3233f216fd Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Mar 2009 02:39:17 -0500 Subject: ppc/p4080: Add various p4080 related defines (and p4040) There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala --- include/asm-ppc/config.h | 6 ++++-- include/asm-ppc/processor.h | 4 ++++ 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index 5670d06a441..e35b0b77fc8 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -40,9 +40,11 @@ #if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \ defined(CONFIG_P2020) || defined(CONFIG_MPC8641) -#define CONFIG_MAX_CPUS 2 +#define CONFIG_MAX_CPUS 2 +#elif defined(CONFIG_PPC_P4080) +#define CONFIG_MAX_CPUS 8 #else -#define CONFIG_MAX_CPUS 1 +#define CONFIG_MAX_CPUS 1 #endif #endif /* _ASM_CONFIG_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 3764a5a51d5..d009957d8b0 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1031,6 +1031,10 @@ #define SVR_P2010_E 0x80EB00 #define SVR_P2020 0x80E200 #define SVR_P2020_E 0x80EA00 +#define SVR_P4040 0x820100 +#define SVR_P4040_E 0x820900 +#define SVR_P4080 0x820000 +#define SVR_P4080_E 0x820800 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 -- cgit v1.2.3 From 39aaca1f66a0e5b1204b0789f6c0097938c00ad1 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 19 Mar 2009 02:46:19 -0500 Subject: ppc/p4080: Determine various chip frequencies on CoreNet platforms The means to determine the core, bus, and DDR frequencies are completely new on CoreNet style platforms. Additionally on p4080 we can have different frequencies for FMAN and PME IP blocks. We need to keep track of the FMAN & PME frequencies since they are used for time stamping capabilities inside each block. Signed-off-by: Kumar Gala --- include/e500.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/e500.h b/include/e500.h index f8c82661a2d..e1708b9dc95 100644 --- a/include/e500.h +++ b/include/e500.h @@ -15,6 +15,12 @@ typedef struct unsigned long freqDDRBus; unsigned long freqLocalBus; unsigned long freqQE; +#ifdef CONFIG_SYS_DPAA_FMAN + unsigned long freqFMan[CONFIG_SYS_NUM_FMAN]; +#endif +#ifdef CONFIG_SYS_DPAA_PME + unsigned long freqPME; +#endif } MPC85xx_SYS_INFO; #endif /* _ASMLANGUAGE */ -- cgit v1.2.3 From 054197ba8ee5ef1e41694df58531b6e53ec43f2d Mon Sep 17 00:00:00 2001 From: Martha M Stan Date: Mon, 21 Sep 2009 14:07:14 -0400 Subject: mpc512x: Streamlined fixed_sdram() init sequence. Signed-off-by: Martha M Stan Minor cleanup: Re-ordered default_mddrc_config[] to have matching indices. This allows to use the same index "N" for source and target fields; before, we had code like this out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]); which always looked like a copy & paste error because 2 != 3. Also, use NULL when meaning a null pointer. Signed-off-by: Wolfgang Denk --- include/asm-ppc/immap_512x.h | 4 ++++ include/asm-ppc/mpc512x.h | 2 +- include/configs/aria.h | 22 +++++++++------------- include/configs/mecp5123.h | 23 ++++++++++------------- include/configs/mpc5121ads.h | 30 +++++++++++++----------------- 5 files changed, 37 insertions(+), 44 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index 24e6c6934ee..79cdd80298f 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -341,6 +341,10 @@ typedef struct ddr512x { u32 res2[0x3AD]; } ddr512x_t; +/* MDDRC SYS CFG and Timing CFG0 Registers */ +#define MDDRC_SYS_CFG_EN 0xF0000000 +#define MDDRC_SYS_CFG_CMD_MASK 0x10000000 +#define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF /* * DMA/Messaging Unit diff --git a/include/asm-ppc/mpc512x.h b/include/asm-ppc/mpc512x.h index 20456f52f7d..8ef0d9ca6dd 100644 --- a/include/asm-ppc/mpc512x.h +++ b/include/asm-ppc/mpc512x.h @@ -50,7 +50,7 @@ static inline void sync_law(volatile void *addr) /* * Prototypes */ -extern long int fixed_sdram(void); +extern long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz); extern int mpc5121_diu_init(void); extern void ide_set_reset(int idereset); diff --git a/include/configs/aria.h b/include/configs/aria.h index 4211113d9e1..2938eac396d 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -126,7 +126,7 @@ #define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \ (1 << 30) | /* CKE */ \ (1 << 29) | /* CLK_ON */ \ - (1 << 28) | /* CMD_MODE */ \ + (0 << 28) | /* CMD_MODE */ \ (4 << 25) | /* DRAM_ROW_SELECT */ \ (3 << 21) | /* DRAM_BANK_SELECT */ \ (0 << 18) | /* SELF_REF_EN */ \ @@ -143,16 +143,12 @@ (0 << 0) /* FIFO_UV_EN */ \ ) -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN (CONFIG_SYS_MDDRC_SYS_CFG & ~(1 << 28)) +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E #define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x030C3D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 +#define CONFIG_SYS_DDRCMD_NOP 0x01380000 +#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 #define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ (0 << 22) | /* DRAM_CS */ \ (0 << 21) | /* DRAM_RAS */ \ @@ -172,7 +168,7 @@ ) #define CONFIG_SYS_MICRON_EMR2 0x01020000 #define CONFIG_SYS_MICRON_EMR3 0x01030000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 +#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 #define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \ (0 << 22) | /* DRAM_CS */ \ @@ -196,10 +192,10 @@ * Backward compatible definitions, * so we do not have to change cpu/mpc512x/fixed_sdram.c */ -#define CONFIG_SYS_MICRON_EM2 (CONFIG_SYS_MICRON_EMR2) -#define CONFIG_SYS_MICRON_EM3 (CONFIG_SYS_MICRON_EMR3) -#define CONFIG_SYS_MICRON_EN_DLL (CONFIG_SYS_MICRON_EMR) -#define CONFIG_SYS_MICRON_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) +#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) +#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) +#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR) +#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) /* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index 1ecae005ce2..e194c8f7bbe 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -111,22 +111,19 @@ * [09:05] DRAM tRP: * [04:00] DRAM tRPA */ -#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 +#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E #define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EM2 0x01020000 -#define CONFIG_SYS_MICRON_EM3 0x01030000 -#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 + +#define CONFIG_SYS_DDRCMD_NOP 0x01380000 +#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 +#define CONFIG_SYS_DDRCMD_EM2 0x01020000 +#define CONFIG_SYS_DDRCMD_EM3 0x01030000 +#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 +#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 +#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780 /* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 76f174db3fa..0c871c91951 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -131,28 +131,24 @@ * [04:00] DRAM tRPA */ #ifdef CONFIG_MPC5121ADS_REV2 -#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 +#define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00 #define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 #define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 #else -#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 +#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00 +#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 +#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 #endif -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EM2 0x01020000 -#define CONFIG_SYS_MICRON_EM3 0x01030000 -#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 +#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E + +#define CONFIG_SYS_DDRCMD_NOP 0x01380000 +#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 +#define CONFIG_SYS_DDRCMD_EM2 0x01020000 +#define CONFIG_SYS_DDRCMD_EM3 0x01030000 +#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 +#define CONFIG_SYS_DDRCMD_RFSH 0x01080000 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 +#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780 /* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -- cgit v1.2.3 From a5aa3998ab6408a6ac738a3ce8005e647b9465f8 Mon Sep 17 00:00:00 2001 From: Martha M Stan Date: Mon, 21 Sep 2009 14:08:00 -0400 Subject: Add Elpida Memory Configuration to mpc5121ads Boards Signed-off-by: Martha M Stan Minor coding style cleanup. Signed-off-by: Wolfgang Denk --- include/configs/mpc5121ads.h | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 0c871c91951..ebc518c03c1 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -141,14 +141,45 @@ #endif #define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E +#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xEA802B00 +#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189 +#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35310864 + #define CONFIG_SYS_DDRCMD_NOP 0x01380000 #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 #define CONFIG_SYS_DDRCMD_EM2 0x01020000 #define CONFIG_SYS_DDRCMD_EM3 0x01030000 #define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000 #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780 + +#define DDRCMD_EMR_OCD(pr, ohm) ( \ + (1 << 24) | /* MDDRC Command Request */ \ + (1 << 16) | /* MODE Reg BA[2:0] */ \ + (0 << 12) | /* Outputs 0=Enabled */ \ + (0 << 11) | /* RDQS */ \ + (1 << 10) | /* DQS# */ \ + (pr << 7) | /* OCD prog 7=deflt,0=exit */ \ + /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \ + ((ohm & 0x2) << 5)| /* Rtt1 */ \ + (0 << 3) | /* additive posted CAS# */ \ + ((ohm & 0x1) << 2)| /* Rtt0 */ \ + (0 << 0) | /* Output Drive Strength */ \ + (0 << 0)) /* DLL Enable 0=Normal */ + +#define CONFIG_SYS_DDRCMD_OCD_DEFAULT DDRCMD_EMR_OCD(7, 0) +#define CONFIG_SYS_ELPIDA_OCD_EXIT DDRCMD_EMR_OCD(0, 0) + +#define DDRCMD_MODE_REG(cas, wr) ( \ + (1 << 24) | /* MDDRC Command Request */ \ + (0 << 16) | /* MODE Reg BA[2:0] */ \ + ((wr-1) << 9)| /* Write Recovery */ \ + (cas << 4) | /* CAS */ \ + (0 << 3) | /* Burst Type:0=Sequential,1=Interleaved */ \ + (2 << 0)) /* 4 or 8 Burst Length:0x2=4 0x3=8 */ + +#define CONFIG_SYS_MICRON_INIT_DEV_OP DDRCMD_MODE_REG(3, 3) +#define CONFIG_SYS_ELPIDA_INIT_DEV_OP DDRCMD_MODE_REG(4, 4) +#define CONFIG_SYS_ELPIDA_RES_DLL (DDRCMD_MODE_REG(4, 4) | (1 << 8)) /* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -- cgit v1.2.3 From 9d142ea8f787882ab732fa531a34db091bfa363d Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 25 Sep 2009 00:57:49 +0200 Subject: Fix "ppc/85xx: Clean up use of LAWAR defines" breakage Commit 002741ae86 modified include/asm-ppc/mmu.h such that the LAWAR_ defines were only enabled for the 83xx platform, but they are also needed on MPC512x system. Enabling these for E300 systems seems thus more appropriate. Signed-off-by: Wolfgang Denk --- include/asm-ppc/mmu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index d516d91403d..ec22a5058e1 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -504,7 +504,7 @@ extern int num_tlb_entries; #endif #endif -#ifdef CONFIG_MPC83xx +#ifdef CONFIG_E300 #define LAWAR_EN 0x80000000 #define LAWAR_SIZE 0x0000003F -- cgit v1.2.3 From 7f625fc6d3ba8f890e843ac01717804c2462ed53 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 23 Sep 2009 07:56:04 +0200 Subject: mpc5200, mucmc52, uc101: config cleanup - As these boards are similiar, collect common config options in manroland/common.h and manroland/mpc52xx-common.h for mpc5200 specific common options for this manufacturer. - add OF support - update default environment Signed-off-by: Heiko Schocher Minor edit of commit message. Signed-off-by: Wolfgang Denk --- include/configs/manroland/common.h | 141 +++++++++++++++ include/configs/manroland/mpc5200-common.h | 229 +++++++++++++++++++++++++ include/configs/mucmc52.h | 257 +-------------------------- include/configs/uc101.h | 267 ++--------------------------- 4 files changed, 390 insertions(+), 504 deletions(-) create mode 100644 include/configs/manroland/common.h create mode 100644 include/configs/manroland/mpc5200-common.h (limited to 'include') diff --git a/include/configs/manroland/common.h b/include/configs/manroland/common.h new file mode 100644 index 00000000000..c0122b7a695 --- /dev/null +++ b/include/configs/manroland/common.h @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2009 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MANROLAND_COMMON_H +#define __MANROLAND_COMMON_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CONFIG_BOARD_EARLY_INIT_R + +/* Partitions */ +#define CONFIG_DOS_PARTITION + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DISPLAY +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DTT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_NFS +#define CONFIG_CMD_MII +#define CONFIG_CMD_SNTP + +#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addwdt=setenv bootargs ${bootargs} wdt=off\0" \ + "logval=4\0" \ + "addlog=setenv bootargs ${bootargs} loglevel=${logval}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "kernel_addr=ff810000\0" \ + "fdt_addr="xstr(CONFIG_SYS_FLASH_BASE)"\0" \ + "flash_nfs=run nfsargs addip addcon addwdt addlog;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "rootpath=/opt/eldk/ppc_82xx\0" \ + "kernel_addr_r=300000\0" \ + "fdt_addr_r=200000\0" \ + "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \ + xstr(CONFIG_HOSTNAME) ".dtb\0" \ + "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \ + "load_fdt=tftp ${fdt_addr_r} ${fdt_file};\0" \ + "load_kernel=tftp ${kernel_addr_r} ${kernel_file};\0" \ + "addcon=setenv bootargs ${bootargs} console=ttyPSC0,${baudrate}\0"\ + "net_nfs=run load_fdt load_kernel; " \ + "run nfsargs addip addcon addwdt addlog;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" \ + "u-boot_addr_r=200000\0" \ + "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ + "update=protect off " xstr(TEXT_BASE) " +${filesize};" \ + "erase " xstr(TEXT_BASE) " +${filesize};" \ + "cp.b ${u-boot_addr_r} " xstr(TEXT_BASE) \ + " ${filesize};" \ + "protect on " xstr(TEXT_BASE) " +${filesize}\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" + +#define CONFIG_MISC_INIT_R 1 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Enable an alternate, more extensive memory test */ +#define CONFIG_SYS_ALT_MEMTEST + +/* + * Enable loopw command. + */ +#define CONFIG_LOOPW + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#endif /* __MANROLAND_COMMON_H */ diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h new file mode 100644 index 00000000000..2f092b18072 --- /dev/null +++ b/include/configs/manroland/mpc5200-common.h @@ -0,0 +1,229 @@ +/* + * (C) Copyright 2009 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MANROLAND_MPC52XX__COMMON_H +#define __MANROLAND_MPC52XX__COMMON_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ + +#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ + +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200,\ + 230400 } + +#if (TEXT_BASE == 0xFFF00000) /* Boot low */ +# define CONFIG_SYS_LOWBOOT 1 +#endif + +/* + * IPB Bus clocking configuration. + */ +#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ + +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F + +/* + * EEPROM configuration + */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* + * RTC configuration + */ +#define CONFIG_RTC_PCF8563 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 + +/* I2C SYSMON (LM75) */ +#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CONFIG_SYS_DTT_MAX_TEMP 70 +#define CONFIG_SYS_DTT_LOW_TEMP -30 +#define CONFIG_SYS_DTT_HYSTERESIS 3 + +/* + * Flash configuration + */ +#define CONFIG_SYS_FLASH_BASE 0xFF800000 + +#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ + +#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks + (= chip selects) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout [ms]*/ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout [ms]*/ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_CFI_AMD_RESET + +/* + * Environment settings + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* + * Memory map + */ +#define CONFIG_SYS_MBAR 0xF0000000 +#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 + +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END -\ + CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SRAM_BASE 0x80100000 /* CS 1 */ +#define CONFIG_SYS_DISPLAY_BASE 0x80600000 /* CS 3 */ + +/* Settings for XLB = 132 MHz */ +#define SDRAM_DDR 1 +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x714f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +/* Use ON-Chip SRAM until RAM will be available */ +#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE +#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) +# define CONFIG_SYS_RAMBOOT 1 +#endif + +#define CONFIG_SYS_MONITOR_LEN (192 << 10) +#define CONFIG_SYS_MALLOC_LEN (512 << 10) +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_MII 1 + +/*use Hardware WDT */ +#define CONFIG_HW_WATCHDOG + +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ +#endif + +/* + * Various low-level settings + */ +#if defined(CONFIG_MPC5200) +#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI +#define CONFIG_SYS_HID0_FINAL HID0_ICE +#else +#define CONFIG_SYS_HID0_INIT 0 +#define CONFIG_SYS_HID0_FINAL 0 +#endif + +#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE +#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE + +/* 8Mbit SRAM @0x80100000 */ +#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE + +#define CONFIG_SYS_CS_BURST 0x00000000 +#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 + +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ + +#define CONFIG_IDE_PREINIT 1 + +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 + +#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA + +/* Offset for data I/O */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) + +/* Offset for normal register accesses */ +#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) + +/* Interval between registers */ +#define CONFIG_SYS_ATA_STRIDE 4 + +#define CONFIG_ATAPI 1 + +#define OF_CPU "PowerPC,5200@0" +#define OF_SOC "soc5200@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" + +#endif /* __MANROLAND_MPC52XX__COMMON_H */ diff --git a/include/configs/mucmc52.h b/include/configs/mucmc52.h index ae60cd2215f..07ed0461994 100644 --- a/include/configs/mucmc52.h +++ b/include/configs/mucmc52.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2008 + * (C) Copyright 2008-2009 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * (C) Copyright 2003-2005 @@ -32,260 +32,51 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_MUCMC52 1 /* MUCMC52 board */ +#define CONFIG_MUCMC52 1 /* MUCMC52 board */ +#define CONFIG_HOSTNAME mucmc52 -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CONFIG_SYS_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -#define CONFIG_BOARD_EARLY_INIT_R +#include "manroland/common.h" +#include "manroland/mpc5200-common.h" #define CONFIG_LAST_STAGE_INIT - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * Serial console configuration */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ #define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* Partitions */ -#define CONFIG_DOS_PARTITION -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DTT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS #define CONFIG_CMD_PCI -#define CONFIG_CMD_PING -#define CONFIG_CMD_SNTP - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (TEXT_BASE == 0xFFF00000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CONFIG_MISC_INIT_R 1 - -/* - * IPB Bus clocking configuration. - */ -#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 /* * Flash configuration */ -#define CONFIG_SYS_FLASH_BASE 0xFF800000 - -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */ - -#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_AMD_RESET +#define CONFIG_SYS_MAX_FLASH_SECT 67 /* * Environment settings */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x4000 #define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) /* * Memory map */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 -#define CONFIG_SYS_DISPLAY_BASE 0x80600000 #define CONFIG_SYS_STATUS1_BASE 0x80600200 #define CONFIG_SYS_STATUS2_BASE 0x80600300 #define CONFIG_SYS_PMI_UNI_BASE 0x80800000 #define CONFIG_SYS_PMI_BROAD_BASE 0x80810000 -/* Settings for XLB = 132 MHz */ -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 /* MII PHY management */ - /* * GPIO configuration */ #define CONFIG_SYS_GPS_PORT_CONFIG 0x8D550644 -/*use Hardware WDT */ -#define CONFIG_HW_WATCHDOG +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x00f00000 -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CONFIG_SYS_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ +#define CONFIG_SYS_LOAD_ADDR 0x100000 -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -/* - * Enable loopw commando. This has only affect, if CONFIG_SYS_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE #define CONFIG_SYS_BOOTCS_CFG 0x0004FB00 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE /* 8Mbit SRAM @0x80100000 */ -#define CONFIG_SYS_CS1_START 0x80100000 #define CONFIG_SYS_CS1_SIZE 0x00100000 #define CONFIG_SYS_CS1_CFG 0x00019B00 @@ -309,42 +100,12 @@ #define CONFIG_SYS_CS7_SIZE 0x00008000 #define CONFIG_SYS_CS7_CFG 0xFF00F930 -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - /*----------------------------------------------------------------------- * IDE/ATA stuff Supports IDE harddisk *----------------------------------------------------------------------- */ - -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ -#define CONFIG_IDE_PREINIT 1 - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 - /* * PCI Mapping: * 0x40000000 - 0x4fffffff - PCI Memory diff --git a/include/configs/uc101.h b/include/configs/uc101.h index 87cb4e508b1..fc0b103fbb4 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003-2006 + * (C) Copyright 2003-2009 * Heiko Schocher, DENX Software Engineering, hs@denx.de. * * See file CREDITS for list of people who contributed to this @@ -29,29 +29,16 @@ * (easy to change) */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_UC101 1 /* UC101 board */ +#define CONFIG_UC101 1 /* UC101 board */ +#define CONFIG_HOSTNAME uc101 -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_BOARD_EARLY_INIT_R - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#include "manroland/common.h" +#include "manroland/mpc5200-common.h" /* * Serial console configuration */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* Partitions */ -#define CONFIG_DOS_PARTITION - /* * BOOTP options @@ -61,243 +48,40 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DISPLAY -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_DTT -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NFS -#define CONFIG_CMD_MII -#define CONFIG_CMD_SNTP - - -#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ - -#if (TEXT_BASE == 0xFFF00000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addwdt=setenv bootargs ${bootargs} wdt=off" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 300000 ${bootfile};run nfsargs addip addwdt;bootm\0" \ - "rootpath=/opt/eldk/ppc_82xx\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -#define CONFIG_MISC_INIT_R 1 - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ - -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* I2C SYSMON (LM75) */ -#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ -#define CONFIG_SYS_DTT_MAX_TEMP 70 -#define CONFIG_SYS_DTT_LOW_TEMP -30 -#define CONFIG_SYS_DTT_HYSTERESIS 3 - /* * Flash configuration */ -#define CONFIG_SYS_FLASH_BASE 0xFF800000 - -#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ -#define CONFIG_SYS_MAX_FLASH_SECT 140 /* max num of sects on one chip */ - -#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_AMD_RESET +#define CONFIG_SYS_MAX_FLASH_SECT 140 /* * Environment settings */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x4000 #define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) /* * Memory map */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SRAM_BASE 0x80100000 /* CS 1 */ -#define CONFIG_SYS_DISPLAY_BASE 0x80600000 /* CS 3 */ #define CONFIG_SYS_IB_MASTER 0xc0510000 /* CS 6 */ #define CONFIG_SYS_IB_EPLD 0xc0500000 /* CS 7 */ -/* Settings for XLB = 132 MHz */ -#define SDRAM_DDR 1 -#define SDRAM_MODE 0x018D0000 -#define SDRAM_EMODE 0x40090000 -#define SDRAM_CONTROL 0x714f0f00 -#define SDRAM_CONFIG1 0x73722930 -#define SDRAM_CONFIG2 0x47770000 -#define SDRAM_TAPDELAY 0x10000000 - /* SRAM */ -#define SRAM_BASE CONFIG_SYS_SRAM_BASE /* SRAM base address */ +#define SRAM_BASE CONFIG_SYS_SRAM_BASE #define SRAM_LEN 0x1fffff #define SRAM_END (SRAM_BASE + SRAM_LEN) -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - - -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_MPC5xxx_FEC_MII100 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_MII 1 - /* * GPIO configuration */ #define CONFIG_SYS_GPS_PORT_CONFIG 0x4d558044 -/*use Hardware WDT */ -#define CONFIG_HW_WATCHDOG - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00300000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 3 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */ +#define CONFIG_SYS_MEMTEST_START 0x00300000 +#define CONFIG_SYS_MEMTEST_END 0x00f00000 -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_LOAD_ADDR 0x300000 -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Enable loopw command. - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#if defined(CONFIG_MPC5200) -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE -#else -#define CONFIG_SYS_HID0_INIT 0 -#define CONFIG_SYS_HID0_FINAL 0 -#endif - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE #define CONFIG_SYS_BOOTCS_CFG 0x00045D00 -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE /* 8Mbit SRAM @0x80100000 */ -#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE #define CONFIG_SYS_CS1_SIZE 0x00200000 #define CONFIG_SYS_CS1_CFG 0x21D00 @@ -316,41 +100,12 @@ #define CONFIG_SYS_CS7_SIZE 0x00010000 #define CONFIG_SYS_CS7_CFG 0x00081800 -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 - /*----------------------------------------------------------------------- * IDE/ATA stuff Supports IDE harddisk *----------------------------------------------------------------------- */ -#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_LED /* LED for ide not supported */ - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */ - -#define CONFIG_IDE_PREINIT 1 - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) - -/* Interval between registers */ -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_ATAPI 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus*/ /*---------------------------------------------------------------------*/ /* Display addresses */ -- cgit v1.2.3 From 3887c3fbdbbe6bbb4df60ed415c8e1ab9fe56b5e Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 23 Sep 2009 07:56:08 +0200 Subject: mucmc52, uc101: delete ata@3a00 node, if no CF card is detected U-Boot can detect if an IDE device is present or not. If not, and this new config option is activated, U-Boot removes the ATA node from the DTS before booting Linux, so the Linux IDE driver does not probe the device and crash. This is needed for buggy hardware (uc101) where no pull down resistor is connected to the signal IDE5V_DD7. Signed-off-by: Heiko Schocher --- include/configs/manroland/mpc5200-common.h | 1 + include/ide.h | 3 +++ 2 files changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h index 2f092b18072..b29ef9b6559 100644 --- a/include/configs/manroland/mpc5200-common.h +++ b/include/configs/manroland/mpc5200-common.h @@ -225,5 +225,6 @@ #define OF_SOC "soc5200@f0000000" #define OF_TBCLK (bd->bi_busfreq / 4) #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" +#define CONFIG_OF_IDE_FIXUP #endif /* __MANROLAND_MPC52XX__COMMON_H */ diff --git a/include/ide.h b/include/ide.h index ddb9579f8fa..6a1b7ae844f 100644 --- a/include/ide.h +++ b/include/ide.h @@ -54,4 +54,7 @@ void ide_init(void); ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer); ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, void *buffer); +#if defined(CONFIG_OF_IDE_FIXUP) +int ide_device_present(int dev); +#endif #endif /* _IDE_H */ -- cgit v1.2.3 From 89da44ce3fe1638312d71cb3add8c6a6d2c7c1f3 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 16 Sep 2009 23:21:59 +0400 Subject: mpc83xx: mpc8360emds: Use RGMII-ID mode, add workarounds for rev. 2.1 CPUs This patch fixes various ethernet issues with gigabit links handling in U-Boot. The workarounds originally implemented by Kim Phillips for Linux kernel. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- include/configs/MPC8360EMDS.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index b072e84473b..fec7cc58551 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -397,7 +397,7 @@ #define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_GMII +#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID #endif #define CONFIG_UEC_ETH2 /* GETH2 */ @@ -408,7 +408,7 @@ #define CONFIG_SYS_UEC2_TX_CLK QE_CLK4 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_GMII +#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID #endif /* -- cgit v1.2.3 From da6eea0f48c24a318e6de69d6bca0bb5ab70572b Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Wed, 16 Sep 2009 23:22:08 +0400 Subject: mpc83xx: mpc8360emds: Add QE USB device tree fixups With this patch we can change QE USB mode without need to hand-edit the device tree. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- include/configs/MPC8360EMDS.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index fec7cc58551..62cf13be6d1 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -382,6 +382,8 @@ #define CONFIG_NET_MULTI 1 #endif +#define CONFIG_HWCONFIG 1 + /* * QE UEC ethernet configuration */ -- cgit v1.2.3 From 00ec0ff549b8cb6fb6d40e275aeb5a460642a3bd Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Mon, 21 Sep 2009 17:44:51 -0400 Subject: sbc8349: tidy up Makefile to use new configuration script. Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the board config header. This takes advantage of that for the sbc8349 board. Signed-off-by: Paul Gortmaker Signed-off-by: Kim Phillips --- include/configs/sbc8349.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include') diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index e961bb3929f..6f574ca6bf4 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -31,6 +31,21 @@ #ifndef __CONFIG_H #define __CONFIG_H +/* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_PCI +#define CONFIG_PCI +#endif + +#ifdef CONFIG_MK_66 +#define PCI_66M +#endif + +#ifdef CONFIG_MK_33 +#define PCI_33M +#endif + /* * High Level Configuration Options */ -- cgit v1.2.3 From c7190f028fa950d4d36b6d0b4bb3fc72602ec54c Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Fri, 25 Sep 2009 18:19:44 -0500 Subject: mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields some LCRR bits are not documented throughout the 83xx family RMs. New board porters copying similar board configurations might omit setting e.g., DBYP since it was not documented in their SoC's RM. Prevent them bricking their board by retaining power on reset values in bit fields that the board porter doesn't explicitly configure via CONFIG_SYS__ assignments in the board config file. also move LCRR assignment to cpu_init_r[am] to help ensure no transactions are being executed via the local bus while CLKDIV is being modified. also start to use i/o accessors. Signed-off-by: Kim Phillips --- include/configs/MPC8313ERDB.h | 3 ++- include/configs/MPC8315ERDB.h | 3 ++- include/configs/MPC8323ERDB.h | 3 ++- include/configs/MPC832XEMDS.h | 3 ++- include/configs/MPC8349EMDS.h | 3 ++- include/configs/MPC8349ITX.h | 3 ++- include/configs/MPC8360EMDS.h | 3 ++- include/configs/MPC8360ERDK.h | 3 ++- include/configs/MPC837XEMDS.h | 3 ++- include/configs/MPC837XERDB.h | 3 ++- include/configs/MVBLM7.h | 3 ++- include/configs/SIMPC8313.h | 4 +++- include/configs/TQM834x.h | 3 ++- include/configs/kmeter1.h | 4 +++- include/configs/sbc8349.h | 3 ++- include/configs/vme8349.h | 3 ++- 16 files changed, 34 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 76b78942ba9..5927e763974 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -216,7 +216,8 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4 +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF ) /* 0x0004ff0f */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 84cc9fa41ea..8eaff5d06f4 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -182,7 +182,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00040000 /* diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index c40d3d3f4a3..356586c4280 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -170,7 +170,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f16616c0db0..f17f9c7c376 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -159,7 +159,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 9b2d25a0118..6361c459500 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -206,7 +206,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 3b4e3449b0e..eaa59fde41b 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -317,7 +317,8 @@ boards, we say we have two, but don't display a message if we find only one. */ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 62cf13be6d1..852015512c0 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -185,7 +185,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index cb0535c151d..6cee78aa260 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -177,7 +177,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index a190a50ed8a..abeb6a2c60a 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -220,7 +220,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 89fafe7d23d..7ef92f7be1f 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -243,7 +243,8 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 9835567838f..f8b016feed3 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -137,7 +137,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB sdram refresh timer, about 6us */ diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 866ff179e63..f68d834170a 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -111,7 +111,9 @@ /* * Local Bus LCRR and LBCR regs */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 #define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF ) /* 0x0004ff0f */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index da08b7c2134..4c909e61ad0 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -52,7 +52,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 /* board pre init: do not call, nothing to do */ #undef CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 79d8638fe28..bec08dab1ff 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -170,7 +170,9 @@ /* * Local Bus Configuration & Clock Setup */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2 +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 /* * Init Local Bus Memory Controller: diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 6f574ca6bf4..bf7cf82d8eb 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -197,7 +197,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 5304ec94aef..d0690feb173 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -178,7 +178,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ -- cgit v1.2.3 From 952e7760bfc5b0e3b142b9ce34e7fbb7d008c900 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 24 Sep 2009 09:55:50 +0200 Subject: ppc4xx: Convert PPC4xx UIC defines from lower case to upper case The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-uic.h | 86 +++++++++++++++++++------------------------- 1 file changed, 37 insertions(+), 49 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/ppc4xx-uic.h b/include/asm-ppc/ppc4xx-uic.h index c908d424525..782d0454b7e 100644 --- a/include/asm-ppc/ppc4xx-uic.h +++ b/include/asm-ppc/ppc4xx-uic.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2002 Scott McNutt * - * (C) Copyright 2008 + * (C) Copyright 2008-2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this @@ -43,7 +43,7 @@ #define UIC_MAX 1 #endif -#define IRQ_MAX UIC_MAX * 32 +#define IRQ_MAX (UIC_MAX * 32) /* * UIC register @@ -74,53 +74,41 @@ #define UIC3_DCR_BASE 0xf0 #endif -#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ -#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ -#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ -#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ -#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ -#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ -#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ -#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ - -#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */ -#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */ -#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */ -#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ -#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ -#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ -#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */ -#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ - -#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ -#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */ -#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */ -#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */ -#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ -#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ -#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ -#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */ -#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ - -#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ -#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */ -#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */ -#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */ -#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ -#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ -#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ -#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */ -#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ - -/* The following is for compatibility with 405 code */ -#define uicsr uic0sr -#define uicer uic0er -#define uiccr uic0cr -#define uicpr uic0pr -#define uictr uic0tr -#define uicmsr uic0msr -#define uicvr uic0vr -#define uicvcr uic0vcr +#define UIC0SR (UIC0_DCR_BASE+0x0) /* UIC0 status */ +#define UIC0ER (UIC0_DCR_BASE+0x2) /* UIC0 enable */ +#define UIC0CR (UIC0_DCR_BASE+0x3) /* UIC0 critical */ +#define UIC0PR (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ +#define UIC0TR (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ +#define UIC0MSR (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ +#define UIC0VR (UIC0_DCR_BASE+0x7) /* UIC0 vector */ +#define UIC0VCR (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ + +#define UIC1SR (UIC1_DCR_BASE+0x0) /* UIC1 status */ +#define UIC1ER (UIC1_DCR_BASE+0x2) /* UIC1 enable */ +#define UIC1CR (UIC1_DCR_BASE+0x3) /* UIC1 critical */ +#define UIC1PR (UIC1_DCR_BASE+0x4) /* UIC1 polarity */ +#define UIC1TR (UIC1_DCR_BASE+0x5) /* UIC1 triggering */ +#define UIC1MSR (UIC1_DCR_BASE+0x6) /* UIC1 masked status */ +#define UIC1VR (UIC1_DCR_BASE+0x7) /* UIC1 vector */ +#define UIC1VCR (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */ + +#define UIC2SR (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ +#define UIC2ER (UIC2_DCR_BASE+0x2) /* UIC2 enable */ +#define UIC2CR (UIC2_DCR_BASE+0x3) /* UIC2 critical */ +#define UIC2PR (UIC2_DCR_BASE+0x4) /* UIC2 polarity */ +#define UIC2TR (UIC2_DCR_BASE+0x5) /* UIC2 triggering */ +#define UIC2MSR (UIC2_DCR_BASE+0x6) /* UIC2 masked status */ +#define UIC2VR (UIC2_DCR_BASE+0x7) /* UIC2 vector */ +#define UIC2VCR (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */ + +#define UIC3SR (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */ +#define UIC3ER (UIC3_DCR_BASE+0x2) /* UIC3 enable */ +#define UIC3CR (UIC3_DCR_BASE+0x3) /* UIC3 critical */ +#define UIC3PR (UIC3_DCR_BASE+0x4) /* UIC3 polarity */ +#define UIC3TR (UIC3_DCR_BASE+0x5) /* UIC3 triggering */ +#define UIC3MSR (UIC3_DCR_BASE+0x6) /* UIC3 masked status */ +#define UIC3VR (UIC3_DCR_BASE+0x7) /* UIC3 vector */ +#define UIC3VCR (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */ /* * Now the interrupt vector definitions. They are different for most of -- cgit v1.2.3 From 95b602bab5fec2fffab07a01ea3947c70d1bacc1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 24 Sep 2009 13:59:57 +0200 Subject: ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese --- include/asm-ppc/ppc4xx-sdram.h | 86 +++++++++++++++++------------------------- 1 file changed, 35 insertions(+), 51 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 992a3d22105..b6182d4f21a 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -30,32 +30,27 @@ * SDRAM Controller */ -/* - * XXX - ToDo: Revisit file to change all these lower case defines into - * upper case. Also needs to be done in the controller setup code too - * of course. sr, 2008-06-02 - */ #ifndef CONFIG_405EP -#define mem_besra 0x00 /* bus error syndrome reg a */ -#define mem_besrsa 0x04 /* bus error syndrome reg set a */ -#define mem_besrb 0x08 /* bus error syndrome reg b */ -#define mem_besrsb 0x0c /* bus error syndrome reg set b */ -#define mem_bear 0x10 /* bus error address reg */ +#define SDRAM0_BESR0 0x00 /* bus error syndrome reg a */ +#define SDRAM0_BESRS0 0x04 /* bus error syndrome reg set a */ +#define SDRAM0_BESR1 0x08 /* bus error syndrome reg b */ +#define SDRAM0_BESRS1 0x0c /* bus error syndrome reg set b */ +#define SDRAM0_BEAR 0x10 /* bus error address reg */ #endif -#define mem_mcopt1 0x20 /* memory controller options 1 */ -#define mem_status 0x24 /* memory status */ -#define mem_rtr 0x30 /* refresh timer reg */ -#define mem_pmit 0x34 /* power management idle timer */ -#define mem_mb0cf 0x40 /* memory bank 0 configuration */ -#define mem_mb1cf 0x44 /* memory bank 1 configuration */ +#define SDRAM0_CFG 0x20 /* memory controller options 1 */ +#define SDRAM0_STATUS 0x24 /* memory status */ +#define SDRAM0_RTR 0x30 /* refresh timer reg */ +#define SDRAM0_PMIT 0x34 /* power management idle timer */ +#define SDRAM0_B0CR 0x40 /* memory bank 0 configuration */ +#define SDRAM0_B1CR 0x44 /* memory bank 1 configuration */ #ifndef CONFIG_405EP -#define mem_mb2cf 0x48 /* memory bank 2 configuration */ -#define mem_mb3cf 0x4c /* memory bank 3 configuration */ +#define SDRAM0_B2CR 0x48 /* memory bank 2 configuration */ +#define SDRAM0_B3CR 0x4c /* memory bank 3 configuration */ #endif -#define mem_sdtr1 0x80 /* timing reg 1 */ +#define SDRAM0_TR 0x80 /* timing reg 1 */ #ifndef CONFIG_405EP -#define mem_ecccf 0x94 /* ECC configuration */ -#define mem_eccerr 0x98 /* ECC error status */ +#define SDRAM0_ECCCFG 0x94 /* ECC configuration */ +#define SDRAM0_ECCESR 0x98 /* ECC error status */ #endif #endif /* CONFIG_SDRAM_PPC4xx_IBM_SDRAM */ @@ -68,36 +63,25 @@ #define SDRAM_CFG0 0x20 /* memory controller options 0 */ #define SDRAM_CFG1 0x21 /* memory controller options 1 */ -/* - * XXX - ToDo: Revisit file to change all these lower case defines into - * upper case. Also needs to be done in the controller setup code too - * of course. sr, 2008-06-02 - */ -#define mem_besr0_clr 0x0000 /* bus error status reg 0 (clr) */ -#define mem_besr0_set 0x0004 /* bus error status reg 0 (set) */ -#define mem_besr1_clr 0x0008 /* bus error status reg 1 (clr) */ -#define mem_besr1_set 0x000c /* bus error status reg 1 (set) */ -#define mem_bear 0x0010 /* bus error address reg */ -#define mem_mirq_clr 0x0011 /* bus master interrupt (clr) */ -#define mem_mirq_set 0x0012 /* bus master interrupt (set) */ -#define mem_slio 0x0018 /* ddr sdram slave interface options */ -#define mem_cfg0 0x0020 /* ddr sdram options 0 */ -#define mem_cfg1 0x0021 /* ddr sdram options 1 */ -#define mem_devopt 0x0022 /* ddr sdram device options */ -#define mem_mcsts 0x0024 /* memory controller status */ -#define mem_rtr 0x0030 /* refresh timer register */ -#define mem_pmit 0x0034 /* power management idle timer */ -#define mem_uabba 0x0038 /* plb UABus base address */ -#define mem_b0cr 0x0040 /* ddr sdram bank 0 configuration */ -#define mem_b1cr 0x0044 /* ddr sdram bank 1 configuration */ -#define mem_b2cr 0x0048 /* ddr sdram bank 2 configuration */ -#define mem_b3cr 0x004c /* ddr sdram bank 3 configuration */ -#define mem_tr0 0x0080 /* sdram timing register 0 */ -#define mem_tr1 0x0081 /* sdram timing register 1 */ -#define mem_clktr 0x0082 /* ddr clock timing register */ -#define mem_wddctr 0x0083 /* write data/dm/dqs clock timing reg */ -#define mem_dlycal 0x0084 /* delay line calibration register */ -#define mem_eccesr 0x0098 /* ECC error status */ +#define SDRAM0_BEAR 0x0010 /* bus error address reg */ +#define SDRAM0_SLIO 0x0018 /* ddr sdram slave interface options */ +#define SDRAM0_CFG0 0x0020 /* ddr sdram options 0 */ +#define SDRAM0_CFG1 0x0021 /* ddr sdram options 1 */ +#define SDRAM0_DEVOPT 0x0022 /* ddr sdram device options */ +#define SDRAM0_MCSTS 0x0024 /* memory controller status */ +#define SDRAM0_RTR 0x0030 /* refresh timer register */ +#define SDRAM0_PMIT 0x0034 /* power management idle timer */ +#define SDRAM0_UABBA 0x0038 /* plb UABus base address */ +#define SDRAM0_B0CR 0x0040 /* ddr sdram bank 0 configuration */ +#define SDRAM0_B1CR 0x0044 /* ddr sdram bank 1 configuration */ +#define SDRAM0_B2CR 0x0048 /* ddr sdram bank 2 configuration */ +#define SDRAM0_B3CR 0x004c /* ddr sdram bank 3 configuration */ +#define SDRAM0_TR0 0x0080 /* sdram timing register 0 */ +#define SDRAM0_TR1 0x0081 /* sdram timing register 1 */ +#define SDRAM0_CLKTR 0x0082 /* ddr clock timing register */ +#define SDRAM0_WDDCTR 0x0083 /* write data/dm/dqs clock timing reg */ +#define SDRAM0_DLYCAL 0x0084 /* delay line calibration register */ +#define SDRAM0_ECCESR 0x0098 /* ECC error status */ /* * Memory Controller Options 0 -- cgit v1.2.3 From 8280912e0657e96a7b7d8da7003656d62b0fd109 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 28 Sep 2009 21:38:00 -0500 Subject: ppc/85xx: Clean up immap_85xx.h * Converted all white space to tabs * Converted all types to u8/u16/u32 * Reduce lines to fit in 80 columns * Renamed MPC85xx_{Q,B}MAN -> FSL_CORENET_{Q,B}MAN Signed-off-by: Kumar Gala --- include/asm-ppc/immap_85xx.h | 3175 +++++++++++++++++++++--------------------- 1 file changed, 1586 insertions(+), 1589 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 100dfe10692..41942954b80 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -17,197 +17,191 @@ #include typedef struct ccsr_local { - u32 ccsrbarh; /* 0x0 - Control Configuration Status Registers Base Address Register High */ - u32 ccsrbarl; /* 0x4 - Control Configuration Status Registers Base Address Register Low */ - u32 ccsrar; /* 0x8 - Configuration, Control, and Status Attribute Register */ + u32 ccsrbarh; /* CCSR Base Addr High */ + u32 ccsrbarl; /* CCSR Base Addr Low */ + u32 ccsrar; /* CCSR Attr */ #define CCSRAR_C 0x80000000 /* Commit */ u8 res1[4]; - u32 altcbarh; /* 0x10 - Alternate Configuration Base Address Register High */ - u32 altcbarl; /* 0x14 - Alternate Configuration Base Address Register Low */ - u32 altcar; /* 0x18 - Alternate Configuration Attribute Register */ + u32 altcbarh; /* Alternate Configuration Base Addr High */ + u32 altcbarl; /* Alternate Configuration Base Addr Low */ + u32 altcar; /* Alternate Configuration Attr */ u8 res2[4]; - u32 bstrh; /* 0x20 - Boot space translation register high */ - u32 bstrl; /* 0x24 - Boot space translation register Low */ - u32 bstrar; /* 0x28 - Boot space translation attributes register */ + u32 bstrh; /* Boot space translation high */ + u32 bstrl; /* Boot space translation Low */ + u32 bstrar; /* Boot space translation attributes */ u8 res3[0xbd4]; struct { - u32 lawbarh; /* 0xc00 + n * 0x10 - LAW0 base address register high */ - u32 lawbarl; /* 0xc04 + n * 0x10 - LAW0 base address register low */ - u32 lawar; /* 0xc08 + n * 0x10 - LAW0 attributes register */ + u32 lawbarh; /* LAWn base addr high */ + u32 lawbarl; /* LAWn base addr low */ + u32 lawar; /* LAWn attributes */ u8 res4[4]; } law[32]; u8 res35[0x204]; } ccsr_local_t; -/* - * Local-Access Registers and ECM Registers(0x0000-0x2000) - */ +/* Local-Access Registers & ECM Registers */ typedef struct ccsr_local_ecm { - uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */ - char res1[4]; - uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */ - char res2[4]; - uint altcar; /* 0x10 - Alternate Configuration Attribute Register */ - char res3[12]; - uint bptr; /* 0x20 - Boot Page Translation Register */ - char res4[3044]; - uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */ - char res5[4]; - uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */ - char res6[20]; - uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */ - char res7[4]; - uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */ - char res8[20]; - uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */ - char res9[4]; - uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */ - char res10[20]; - uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */ - char res11[4]; - uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */ - char res12[20]; - uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */ - char res13[4]; - uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */ - char res14[20]; - uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */ - char res15[4]; - uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */ - char res16[20]; - uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */ - char res17[4]; - uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */ - char res18[20]; - uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ - char res19[4]; - uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ - char res19_8a[20]; - uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ - char res19_8b[4]; - uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ - char res19_9a[20]; - uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ - char res19_9b[4]; - uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ - char res19_10a[20]; - uint lawbar10; /* 0xd48 - Local Access Window 10 Base Address Register */ - char res19_10b[4]; - uint lawar10; /* 0xd50 - Local Access Window 10 Attributes Register */ - char res19_11a[20]; - uint lawbar11; /* 0xd68 - Local Access Window 11 Base Address Register */ - char res19_11b[4]; - uint lawar11; /* 0xd70 - Local Access Window 11 Attributes Register */ - char res20[652]; - uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */ - char res21[12]; - uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */ - char res22[3564]; - uint eedr; /* 0x1e00 - ECM Error Detect Register */ - char res23[4]; - uint eeer; /* 0x1e08 - ECM Error Enable Register */ - uint eeatr; /* 0x1e0c - ECM Error Attributes Capture Register */ - uint eeadr; /* 0x1e10 - ECM Error Address Capture Register */ - char res24[492]; + u32 ccsrbar; /* CCSR Base Addr */ + u8 res1[4]; + u32 altcbar; /* Alternate Configuration Base Addr */ + u8 res2[4]; + u32 altcar; /* Alternate Configuration Attr */ + u8 res3[12]; + u32 bptr; /* Boot Page Translation */ + u8 res4[3044]; + u32 lawbar0; /* Local Access Window 0 Base Addr */ + u8 res5[4]; + u32 lawar0; /* Local Access Window 0 Attrs */ + u8 res6[20]; + u32 lawbar1; /* Local Access Window 1 Base Addr */ + u8 res7[4]; + u32 lawar1; /* Local Access Window 1 Attrs */ + u8 res8[20]; + u32 lawbar2; /* Local Access Window 2 Base Addr */ + u8 res9[4]; + u32 lawar2; /* Local Access Window 2 Attrs */ + u8 res10[20]; + u32 lawbar3; /* Local Access Window 3 Base Addr */ + u8 res11[4]; + u32 lawar3; /* Local Access Window 3 Attrs */ + u8 res12[20]; + u32 lawbar4; /* Local Access Window 4 Base Addr */ + u8 res13[4]; + u32 lawar4; /* Local Access Window 4 Attrs */ + u8 res14[20]; + u32 lawbar5; /* Local Access Window 5 Base Addr */ + u8 res15[4]; + u32 lawar5; /* Local Access Window 5 Attrs */ + u8 res16[20]; + u32 lawbar6; /* Local Access Window 6 Base Addr */ + u8 res17[4]; + u32 lawar6; /* Local Access Window 6 Attrs */ + u8 res18[20]; + u32 lawbar7; /* Local Access Window 7 Base Addr */ + u8 res19[4]; + u32 lawar7; /* Local Access Window 7 Attrs */ + u8 res19_8a[20]; + u32 lawbar8; /* Local Access Window 8 Base Addr */ + u8 res19_8b[4]; + u32 lawar8; /* Local Access Window 8 Attrs */ + u8 res19_9a[20]; + u32 lawbar9; /* Local Access Window 9 Base Addr */ + u8 res19_9b[4]; + u32 lawar9; /* Local Access Window 9 Attrs */ + u8 res19_10a[20]; + u32 lawbar10; /* Local Access Window 10 Base Addr */ + u8 res19_10b[4]; + u32 lawar10; /* Local Access Window 10 Attrs */ + u8 res19_11a[20]; + u32 lawbar11; /* Local Access Window 11 Base Addr */ + u8 res19_11b[4]; + u32 lawar11; /* Local Access Window 11 Attrs */ + u8 res20[652]; + u32 eebacr; /* ECM CCB Addr Configuration */ + u8 res21[12]; + u32 eebpcr; /* ECM CCB Port Configuration */ + u8 res22[3564]; + u32 eedr; /* ECM Error Detect */ + u8 res23[4]; + u32 eeer; /* ECM Error Enable */ + u32 eeatr; /* ECM Error Attrs Capture */ + u32 eeadr; /* ECM Error Addr Capture */ + u8 res24[492]; } ccsr_local_ecm_t; -/* - * DDR memory controller registers(0x2000-0x3000) - */ +/* DDR memory controller registers */ typedef struct ccsr_ddr { - uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ - char res1[4]; - uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */ - char res2[4]; - uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */ - char res3[4]; - uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */ - char res4[100]; - uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */ - uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ - uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ - uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ - char res4a[48]; - uint cs0_config_2; /* 0x20c0 - DDR Chip Select Configuration 2 */ - uint cs1_config_2; /* 0x20c4 - DDR Chip Select Configuration 2 */ - uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */ - uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */ - char res5[48]; - uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ - uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ - uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ - uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ - uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */ - uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ - uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */ - uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/ - uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */ - uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ - uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */ - char res6[4]; - uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ - char res7[20]; - uint init_addr; /* 0x2148 - DDR training initialization address */ - uint init_ext_addr; /* 0x214C - DDR training initialization extended address */ - char res8_1[16]; - uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */ - uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */ - char reg8_1a[8]; - uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/ - uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/ - char reg8_1aa[4]; - uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */ - uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */ - uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */ - char res8_1b[2456]; - uint ddr_dsr1; /* 0x2B20 - DDR Debug Status Register 1 */ - uint ddr_dsr2; /* 0x2B24 - DDR Debug Status Register 2 */ - uint ddr_cdr1; /* 0x2B28 - DDR Control Driver Register 1 */ - uint ddr_cdr2; /* 0x2B2C - DDR Control Driver Register 2 */ - char res8_1c[200]; - uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ - uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ - char res8_2[512]; - uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ - uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ - uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */ - char res9[20]; - uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */ - uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */ - uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */ - char res10[20]; - uint err_detect; /* 0x2e40 - DDR Memory Error Detect */ - uint err_disable; /* 0x2e44 - DDR Memory Error Disable */ - uint err_int_en; /* 0x2e48 - DDR */ - uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ - uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ - uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ - uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ - char res11[164]; - uint debug_1; /* 0x2f00 */ - uint debug_2; - uint debug_3; - uint debug_4; - uint debug_5; - uint debug_6; - uint debug_7; - uint debug_8; - uint debug_9; - uint debug_10; - uint debug_11; - uint debug_12; - uint debug_13; /* +0xF30 */ - uint debug_14; - uint debug_15; - uint debug_16; - uint debug_17; - uint debug_18; /* +0xF44 */ - char res12[184]; + u32 cs0_bnds; /* Chip Select 0 Memory Bounds */ + u8 res1[4]; + u32 cs1_bnds; /* Chip Select 1 Memory Bounds */ + u8 res2[4]; + u32 cs2_bnds; /* Chip Select 2 Memory Bounds */ + u8 res3[4]; + u32 cs3_bnds; /* Chip Select 3 Memory Bounds */ + u8 res4[100]; + u32 cs0_config; /* Chip Select Configuration */ + u32 cs1_config; /* Chip Select Configuration */ + u32 cs2_config; /* Chip Select Configuration */ + u32 cs3_config; /* Chip Select Configuration */ + u8 res4a[48]; + u32 cs0_config_2; /* Chip Select Configuration 2 */ + u32 cs1_config_2; /* Chip Select Configuration 2 */ + u32 cs2_config_2; /* Chip Select Configuration 2 */ + u32 cs3_config_2; /* Chip Select Configuration 2 */ + u8 res5[48]; + u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ + u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ + u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ + u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ + u32 sdram_cfg; /* SDRAM Control Configuration */ + u32 sdram_cfg_2; /* SDRAM Control Configuration 2 */ + u32 sdram_mode; /* SDRAM Mode Configuration */ + u32 sdram_mode_2; /* SDRAM Mode Configuration 2 */ + u32 sdram_md_cntl; /* SDRAM Mode Control */ + u32 sdram_interval; /* SDRAM Interval Configuration */ + u32 sdram_data_init; /* SDRAM Data initialization */ + u8 res6[4]; + u32 sdram_clk_cntl; /* SDRAM Clock Control */ + u8 res7[20]; + u32 init_addr; /* training init addr */ + u32 init_ext_addr; /* training init extended addr */ + u8 res8_1[16]; + u32 timing_cfg_4; /* SDRAM Timing Configuration 4 */ + u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ + u8 reg8_1a[8]; + u32 ddr_zq_cntl; /* ZQ calibration control*/ + u32 ddr_wrlvl_cntl; /* write leveling control*/ + u8 reg8_1aa[4]; + u32 ddr_sr_cntr; /* self refresh counter */ + u32 ddr_sdram_rcw_1; /* Control Words 1 */ + u32 ddr_sdram_rcw_2; /* Control Words 2 */ + u8 res8_1b[2456]; + u32 ddr_dsr1; /* Debug Status 1 */ + u32 ddr_dsr2; /* Debug Status 2 */ + u32 ddr_cdr1; /* Control Driver 1 */ + u32 ddr_cdr2; /* Control Driver 2 */ + u8 res8_1c[200]; + u32 ip_rev1; /* IP Block Revision 1 */ + u32 ip_rev2; /* IP Block Revision 2 */ + u8 res8_2[512]; + u32 data_err_inject_hi; /* Data Path Err Injection Mask High */ + u32 data_err_inject_lo; /* Data Path Err Injection Mask Low */ + u32 ecc_err_inject; /* Data Path Err Injection Mask ECC */ + u8 res9[20]; + u32 capture_data_hi; /* Data Path Read Capture High */ + u32 capture_data_lo; /* Data Path Read Capture Low */ + u32 capture_ecc; /* Data Path Read Capture ECC */ + u8 res10[20]; + u32 err_detect; /* Error Detect */ + u32 err_disable; /* Error Disable */ + u32 err_int_en; + u32 capture_attributes; /* Error Attrs Capture */ + u32 capture_address; /* Error Addr Capture */ + u32 capture_ext_address; /* Error Extended Addr Capture */ + u32 err_sbe; /* Single-Bit ECC Error Management */ + u8 res11[164]; + u32 debug_1; + u32 debug_2; + u32 debug_3; + u32 debug_4; + u32 debug_5; + u32 debug_6; + u32 debug_7; + u32 debug_8; + u32 debug_9; + u32 debug_10; + u32 debug_11; + u32 debug_12; + u32 debug_13; + u32 debug_14; + u32 debug_15; + u32 debug_16; + u32 debug_17; + u32 debug_18; + u8 res12[184]; } ccsr_ddr_t; -/* - * I2C Registers(0x3000-0x4000) - */ +/* I2C Registers */ typedef struct ccsr_i2c { struct fsl_i2c i2c[1]; u8 res[4096 - 1 * sizeof(struct fsl_i2c)]; @@ -217,176 +211,167 @@ typedef struct ccsr_i2c { || defined(CONFIG_MPC8541) \ || defined(CONFIG_MPC8548) \ || defined(CONFIG_MPC8555) -/* DUART Registers(0x4000-0x5000) */ +/* DUART Registers */ typedef struct ccsr_duart { - char res1[1280]; - u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */ - u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */ - u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */ - u_char ulcr1; /* 0x4503 - UART1 Line Control Register */ - u_char umcr1; /* 0x4504 - UART1 Modem Control Register */ - u_char ulsr1; /* 0x4505 - UART1 Line Status Register */ - u_char umsr1; /* 0x4506 - UART1 Modem Status Register */ - u_char uscr1; /* 0x4507 - UART1 Scratch Register */ - char res2[8]; - u_char udsr1; /* 0x4510 - UART1 DMA Status Register */ - char res3[239]; - u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */ - u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */ - u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */ - u_char ulcr2; /* 0x4603 - UART2 Line Control Register */ - u_char umcr2; /* 0x4604 - UART2 Modem Control Register */ - u_char ulsr2; /* 0x4605 - UART2 Line Status Register */ - u_char umsr2; /* 0x4606 - UART2 Modem Status Register */ - u_char uscr2; /* 0x4607 - UART2 Scratch Register */ - char res4[8]; - u_char udsr2; /* 0x4610 - UART2 DMA Status Register */ - char res5[2543]; + u8 res1[1280]; +/* URBR1, UTHR1, UDLB1 with the same addr */ + u8 urbr1_uthr1_udlb1; +/* UIER1, UDMB1 with the same addr01 */ + u8 uier1_udmb1; +/* UIIR1, UFCR1, UAFR1 with the same addr */ + u8 uiir1_ufcr1_uafr1; + u8 ulcr1; /* UART1 Line Control */ + u8 umcr1; /* UART1 Modem Control */ + u8 ulsr1; /* UART1 Line Status */ + u8 umsr1; /* UART1 Modem Status */ + u8 uscr1; /* UART1 Scratch */ + u8 res2[8]; + u8 udsr1; /* UART1 DMA Status */ + u8 res3[239]; +/* URBR2, UTHR2, UDLB2 with the same addr */ + u8 urbr2_uthr2_udlb2; +/* UIER2, UDMB2 with the same addr */ + u8 uier2_udmb2; +/* UIIR2, UFCR2, UAFR2 with the same addr */ + u8 uiir2_ufcr2_uafr2; + u8 ulcr2; /* UART2 Line Control */ + u8 umcr2; /* UART2 Modem Control */ + u8 ulsr2; /* UART2 Line Status */ + u8 umsr2; /* UART2 Modem Status */ + u8 uscr2; /* UART2 Scratch */ + u8 res4[8]; + u8 udsr2; /* UART2 DMA Status */ + u8 res5[2543]; } ccsr_duart_t; #else /* MPC8560 uses UART on its CPM */ typedef struct ccsr_duart { - char res[4096]; + u8 res[4096]; } ccsr_duart_t; #endif -/* Local Bus Controller Registers(0x5000-0x6000) */ -/* Omitting OCeaN(0x6000) and Reserved(0x7000) block */ - +/* Local Bus Controller Registers */ typedef struct ccsr_lbc { - uint br0; /* 0x5000 - LBC Base Register 0 */ - uint or0; /* 0x5004 - LBC Options Register 0 */ - uint br1; /* 0x5008 - LBC Base Register 1 */ - uint or1; /* 0x500c - LBC Options Register 1 */ - uint br2; /* 0x5010 - LBC Base Register 2 */ - uint or2; /* 0x5014 - LBC Options Register 2 */ - uint br3; /* 0x5018 - LBC Base Register 3 */ - uint or3; /* 0x501c - LBC Options Register 3 */ - uint br4; /* 0x5020 - LBC Base Register 4 */ - uint or4; /* 0x5024 - LBC Options Register 4 */ - uint br5; /* 0x5028 - LBC Base Register 5 */ - uint or5; /* 0x502c - LBC Options Register 5 */ - uint br6; /* 0x5030 - LBC Base Register 6 */ - uint or6; /* 0x5034 - LBC Options Register 6 */ - uint br7; /* 0x5038 - LBC Base Register 7 */ - uint or7; /* 0x503c - LBC Options Register 7 */ - char res1[40]; - uint mar; /* 0x5068 - LBC UPM Address Register */ - char res2[4]; - uint mamr; /* 0x5070 - LBC UPMA Mode Register */ - uint mbmr; /* 0x5074 - LBC UPMB Mode Register */ - uint mcmr; /* 0x5078 - LBC UPMC Mode Register */ - char res3[8]; - uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */ - uint mdr; /* 0x5088 - LBC UPM Data Register */ - char res4[8]; - uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */ - char res5[8]; - uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */ - uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */ - char res6[8]; - uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */ - uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */ - uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */ - uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */ - uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */ - char res7[12]; - uint lbcr; /* 0x50d0 - LBC Configuration Register */ - uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */ - char res8[3880]; + u32 br0; /* LBC Base 0 */ + u32 or0; /* LBC Options 0 */ + u32 br1; /* LBC Base 1 */ + u32 or1; /* LBC Options 1 */ + u32 br2; /* LBC Base 2 */ + u32 or2; /* LBC Options 2 */ + u32 br3; /* LBC Base 3 */ + u32 or3; /* LBC Options 3 */ + u32 br4; /* LBC Base 4 */ + u32 or4; /* LBC Options 4 */ + u32 br5; /* LBC Base 5 */ + u32 or5; /* LBC Options 5 */ + u32 br6; /* LBC Base 6 */ + u32 or6; /* LBC Options 6 */ + u32 br7; /* LBC Base 7 */ + u32 or7; /* LBC Options 7 */ + u8 res1[40]; + u32 mar; /* LBC UPM Addr */ + u8 res2[4]; + u32 mamr; /* LBC UPMA Mode */ + u32 mbmr; /* LBC UPMB Mode */ + u32 mcmr; /* LBC UPMC Mode */ + u8 res3[8]; + u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */ + u32 mdr; /* LBC UPM Data */ + u8 res4[8]; + u32 lsdmr; /* LBC SDRAM Mode */ + u8 res5[8]; + u32 lurt; /* LBC UPM Refresh Timer */ + u32 lsrt; /* LBC SDRAM Refresh Timer */ + u8 res6[8]; + u32 ltesr; /* LBC Transfer Error Status */ + u32 ltedr; /* LBC Transfer Error Disable */ + u32 lteir; /* LBC Transfer Error IRQ */ + u32 lteatr; /* LBC Transfer Error Attrs */ + u32 ltear; /* LBC Transfer Error Addr */ + u8 res7[12]; + u32 lbcr; /* LBC Configuration */ + u32 lcrr; /* LBC Clock Ratio */ + u8 res8[3880]; } ccsr_lbc_t; -/* - * eSPI Registers(0x7000-0x8000) - */ +/* eSPI Registers */ typedef struct ccsr_espi { - uint mode; /* 0x00 - eSPI mode register */ - uint event; /* 0x04 - eSPI event register */ - uint mask; /* 0x08 - eSPI mask register */ - uint com; /* 0x0c - eSPI command register */ - uint tx; /* 0x10 - eSPI transmit FIFO access register */ - uint rx; /* 0x14 - eSPI receive FIFO access register */ - char res1[8]; /* reserved */ - uint csmode[4]; /* 0x20 - 0x2c: sSPI CS0/1/2/3 mode register */ - char res2[4048]; /* fill up to 0x1000 */ + u32 mode; /* eSPI mode */ + u32 event; /* eSPI event */ + u32 mask; /* eSPI mask */ + u32 com; /* eSPI command */ + u32 tx; /* eSPI transmit FIFO access */ + u32 rx; /* eSPI receive FIFO access */ + u8 res1[8]; /* reserved */ + u32 csmode[4]; /* 0x2c: sSPI CS0/1/2/3 mode */ + u8 res2[4048]; /* fill up to 0x1000 */ } ccsr_espi_t; -/* - * PCI Registers(0x8000-0x9000) - */ +/* PCI Registers */ typedef struct ccsr_pcix { - uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */ - uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */ - uint int_ack; /* 0x8008 - PCIX Interrupt Acknowledge Register */ - char res1[3060]; - uint potar0; /* 0x8c00 - PCIX Outbound Transaction Address Register 0 */ - uint potear0; /* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */ - uint powbar0; /* 0x8c08 - PCIX Outbound Window Base Address Register 0 */ - uint powbear0; /* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */ - uint powar0; /* 0x8c10 - PCIX Outbound Window Attributes Register 0 */ - char res2[12]; - uint potar1; /* 0x8c20 - PCIX Outbound Transaction Address Register 1 */ - uint potear1; /* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */ - uint powbar1; /* 0x8c28 - PCIX Outbound Window Base Address Register 1 */ - uint powbear1; /* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */ - uint powar1; /* 0x8c30 - PCIX Outbound Window Attributes Register 1 */ - char res3[12]; - uint potar2; /* 0x8c40 - PCIX Outbound Transaction Address Register 2 */ - uint potear2; /* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */ - uint powbar2; /* 0x8c48 - PCIX Outbound Window Base Address Register 2 */ - uint powbear2; /* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */ - uint powar2; /* 0x8c50 - PCIX Outbound Window Attributes Register 2 */ - char res4[12]; - uint potar3; /* 0x8c60 - PCIX Outbound Transaction Address Register 3 */ - uint potear3; /* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */ - uint powbar3; /* 0x8c68 - PCIX Outbound Window Base Address Register 3 */ - uint powbear3; /* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */ - uint powar3; /* 0x8c70 - PCIX Outbound Window Attributes Register 3 */ - char res5[12]; - uint potar4; /* 0x8c80 - PCIX Outbound Transaction Address Register 4 */ - uint potear4; /* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */ - uint powbar4; /* 0x8c88 - PCIX Outbound Window Base Address Register 4 */ - uint powbear4; /* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */ - uint powar4; /* 0x8c90 - PCIX Outbound Window Attributes Register 4 */ - char res6[268]; - uint pitar3; /* 0x8da0 - PCIX Inbound Translation Address Register 3 */ - uint pitear3; /* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */ - uint piwbar3; /* 0x8da8 - PCIX Inbound Window Base Address Register 3 */ - uint piwbear3; /* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */ - uint piwar3; /* 0x8db0 - PCIX Inbound Window Attributes Register 3 */ - char res7[12]; - uint pitar2; /* 0x8dc0 - PCIX Inbound Translation Address Register 2 */ - uint pitear2; /* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */ - uint piwbar2; /* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */ - uint piwbear2; /* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */ - uint piwar2; /* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */ - char res8[12]; - uint pitar1; /* 0x8de0 - PCIX Inbound Translation Address Register 1 */ - uint pitear1; /* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */ - uint piwbar1; /* 0x8de8 - PCIX Inbound Window Base Address Register 1 */ - char res9[4]; - uint piwar1; /* 0x8df0 - PCIX Inbound Window Attributes Register 1 */ - char res10[12]; - uint pedr; /* 0x8e00 - PCIX Error Detect Register */ - uint pecdr; /* 0x8e04 - PCIX Error Capture Disable Register */ - uint peer; /* 0x8e08 - PCIX Error Enable Register */ - uint peattrcr; /* 0x8e0c - PCIX Error Attributes Capture Register */ - uint peaddrcr; /* 0x8e10 - PCIX Error Address Capture Register */ - uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */ - uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */ - uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */ - uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */ - char res11[476]; + u32 cfg_addr; /* PCIX Configuration Addr */ + u32 cfg_data; /* PCIX Configuration Data */ + u32 int_ack; /* PCIX IRQ Acknowledge */ + u8 res1[3060]; + u32 potar0; /* PCIX Outbound Transaction Addr 0 */ + u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */ + u32 powbar0; /* PCIX Outbound Window Base Addr 0 */ + u32 powbear0; /* PCIX Outbound Window Base Extended Addr 0 */ + u32 powar0; /* PCIX Outbound Window Attrs 0 */ + u8 res2[12]; + u32 potar1; /* PCIX Outbound Transaction Addr 1 */ + u32 potear1; /* PCIX Outbound Translation Extended Addr 1 */ + u32 powbar1; /* PCIX Outbound Window Base Addr 1 */ + u32 powbear1; /* PCIX Outbound Window Base Extended Addr 1 */ + u32 powar1; /* PCIX Outbound Window Attrs 1 */ + u8 res3[12]; + u32 potar2; /* PCIX Outbound Transaction Addr 2 */ + u32 potear2; /* PCIX Outbound Translation Extended Addr 2 */ + u32 powbar2; /* PCIX Outbound Window Base Addr 2 */ + u32 powbear2; /* PCIX Outbound Window Base Extended Addr 2 */ + u32 powar2; /* PCIX Outbound Window Attrs 2 */ + u8 res4[12]; + u32 potar3; /* PCIX Outbound Transaction Addr 3 */ + u32 potear3; /* PCIX Outbound Translation Extended Addr 3 */ + u32 powbar3; /* PCIX Outbound Window Base Addr 3 */ + u32 powbear3; /* PCIX Outbound Window Base Extended Addr 3 */ + u32 powar3; /* PCIX Outbound Window Attrs 3 */ + u8 res5[12]; + u32 potar4; /* PCIX Outbound Transaction Addr 4 */ + u32 potear4; /* PCIX Outbound Translation Extended Addr 4 */ + u32 powbar4; /* PCIX Outbound Window Base Addr 4 */ + u32 powbear4; /* PCIX Outbound Window Base Extended Addr 4 */ + u32 powar4; /* PCIX Outbound Window Attrs 4 */ + u8 res6[268]; + u32 pitar3; /* PCIX Inbound Translation Addr 3 */ + u32 pitear3; /* PCIX Inbound Translation Extended Addr 3 */ + u32 piwbar3; /* PCIX Inbound Window Base Addr 3 */ + u32 piwbear3; /* PCIX Inbound Window Base Extended Addr 3 */ + u32 piwar3; /* PCIX Inbound Window Attrs 3 */ + u8 res7[12]; + u32 pitar2; /* PCIX Inbound Translation Addr 2 */ + u32 pitear2; /* PCIX Inbound Translation Extended Addr 2 */ + u32 piwbar2; /* PCIX Inbound Window Base Addr 2 */ + u32 piwbear2; /* PCIX Inbound Window Base Extended Addr 2 */ + u32 piwar2; /* PCIX Inbound Window Attrs 2 */ + u8 res8[12]; + u32 pitar1; /* PCIX Inbound Translation Addr 1 */ + u32 pitear1; /* PCIX Inbound Translation Extended Addr 1 */ + u32 piwbar1; /* PCIX Inbound Window Base Addr 1 */ + u8 res9[4]; + u32 piwar1; /* PCIX Inbound Window Attrs 1 */ + u8 res10[12]; + u32 pedr; /* PCIX Error Detect */ + u32 pecdr; /* PCIX Error Capture Disable */ + u32 peer; /* PCIX Error Enable */ + u32 peattrcr; /* PCIX Error Attrs Capture */ + u32 peaddrcr; /* PCIX Error Addr Capture */ + u32 peextaddrcr; /* PCIX Error Extended Addr Capture */ + u32 pedlcr; /* PCIX Error Data Low Capture */ + u32 pedhcr; /* PCIX Error Error Data High Capture */ + u32 gas_timr; /* PCIX Gasket Timer */ + u8 res11[476]; } ccsr_pcix_t; -typedef struct ccsr_gpio { - uint gpdir; - uint gpodr; - uint gpdat; - uint gpier; - uint gpimr; - uint gpicr; -} ccsr_gpio_t; - #define PCIX_COMMAND 0x62 #define POWAR_EN 0x80000000 #define POWAR_IO_READ 0x00080000 @@ -403,49 +388,55 @@ typedef struct ccsr_gpio { #define PIWAR_WRITE_SNOOP 0x00005000 #define PIWAR_MEM_2G 0x0000001e +typedef struct ccsr_gpio { + u32 gpdir; + u32 gpodr; + u32 gpdat; + u32 gpier; + u32 gpimr; + u32 gpicr; +} ccsr_gpio_t; -/* - * L2 Cache Registers(0x2_0000-0x2_1000) - */ +/* L2 Cache Registers */ typedef struct ccsr_l2cache { - uint l2ctl; /* 0x20000 - L2 configuration register 0 */ - char res1[12]; - uint l2cewar0; /* 0x20010 - L2 cache external write address register 0 */ - char res2[4]; - uint l2cewcr0; /* 0x20018 - L2 cache external write control register 0 */ - char res3[4]; - uint l2cewar1; /* 0x20020 - L2 cache external write address register 1 */ - char res4[4]; - uint l2cewcr1; /* 0x20028 - L2 cache external write control register 1 */ - char res5[4]; - uint l2cewar2; /* 0x20030 - L2 cache external write address register 2 */ - char res6[4]; - uint l2cewcr2; /* 0x20038 - L2 cache external write control register 2 */ - char res7[4]; - uint l2cewar3; /* 0x20040 - L2 cache external write address register 3 */ - char res8[4]; - uint l2cewcr3; /* 0x20048 - L2 cache external write control register 3 */ - char res9[180]; - uint l2srbar0; /* 0x20100 - L2 memory-mapped SRAM base address register 0 */ - char res10[4]; - uint l2srbar1; /* 0x20108 - L2 memory-mapped SRAM base address register 1 */ - char res11[3316]; - uint l2errinjhi; /* 0x20e00 - L2 error injection mask high register */ - uint l2errinjlo; /* 0x20e04 - L2 error injection mask low register */ - uint l2errinjctl; /* 0x20e08 - L2 error injection tag/ECC control register */ - char res12[20]; - uint l2captdatahi; /* 0x20e20 - L2 error data high capture register */ - uint l2captdatalo; /* 0x20e24 - L2 error data low capture register */ - uint l2captecc; /* 0x20e28 - L2 error ECC capture register */ - char res13[20]; - uint l2errdet; /* 0x20e40 - L2 error detect register */ - uint l2errdis; /* 0x20e44 - L2 error disable register */ - uint l2errinten; /* 0x20e48 - L2 error interrupt enable register */ - uint l2errattr; /* 0x20e4c - L2 error attributes capture register */ - uint l2erraddr; /* 0x20e50 - L2 error address capture register */ - char res14[4]; - uint l2errctl; /* 0x20e58 - L2 error control register */ - char res15[420]; + u32 l2ctl; /* L2 configuration 0 */ + u8 res1[12]; + u32 l2cewar0; /* L2 cache external write addr 0 */ + u8 res2[4]; + u32 l2cewcr0; /* L2 cache external write control 0 */ + u8 res3[4]; + u32 l2cewar1; /* L2 cache external write addr 1 */ + u8 res4[4]; + u32 l2cewcr1; /* L2 cache external write control 1 */ + u8 res5[4]; + u32 l2cewar2; /* L2 cache external write addr 2 */ + u8 res6[4]; + u32 l2cewcr2; /* L2 cache external write control 2 */ + u8 res7[4]; + u32 l2cewar3; /* L2 cache external write addr 3 */ + u8 res8[4]; + u32 l2cewcr3; /* L2 cache external write control 3 */ + u8 res9[180]; + u32 l2srbar0; /* L2 memory-mapped SRAM base addr 0 */ + u8 res10[4]; + u32 l2srbar1; /* L2 memory-mapped SRAM base addr 1 */ + u8 res11[3316]; + u32 l2errinjhi; /* L2 error injection mask high */ + u32 l2errinjlo; /* L2 error injection mask low */ + u32 l2errinjctl; /* L2 error injection tag/ECC control */ + u8 res12[20]; + u32 l2captdatahi; /* L2 error data high capture */ + u32 l2captdatalo; /* L2 error data low capture */ + u32 l2captecc; /* L2 error ECC capture */ + u8 res13[20]; + u32 l2errdet; /* L2 error detect */ + u32 l2errdis; /* L2 error disable */ + u32 l2errinten; /* L2 error interrupt enable */ + u32 l2errattr; /* L2 error attributes capture */ + u32 l2erraddr; /* L2 error addr capture */ + u8 res14[4]; + u32 l2errctl; /* L2 error control */ + u8 res15[420]; } ccsr_l2cache_t; #define MPC85xx_L2CTL_L2E 0x80000000 @@ -453,919 +444,910 @@ typedef struct ccsr_l2cache { #define MPC85xx_L2ERRDIS_MBECC 0x00000008 #define MPC85xx_L2ERRDIS_SBECC 0x00000004 -/* - * DMA Registers(0x2_1000-0x2_2000) - */ +/* DMA Registers */ typedef struct ccsr_dma { - char res1[256]; + u8 res1[256]; struct fsl_dma dma[4]; - uint dgsr; /* 0x21300 - DMA General Status Register */ - char res2[11516]; + u32 dgsr; /* DMA General Status */ + u8 res2[11516]; } ccsr_dma_t; -/* - * tsec1 tsec2: 24000-26000 - */ +/* tsec */ typedef struct ccsr_tsec { - char res1[16]; - uint ievent; /* 0x24010 - Interrupt Event Register */ - uint imask; /* 0x24014 - Interrupt Mask Register */ - uint edis; /* 0x24018 - Error Disabled Register */ - char res2[4]; - uint ecntrl; /* 0x24020 - Ethernet Control Register */ - uint minflr; /* 0x24024 - Minimum Frame Length Register */ - uint ptv; /* 0x24028 - Pause Time Value Register */ - uint dmactrl; /* 0x2402c - DMA Control Register */ - uint tbipa; /* 0x24030 - TBI PHY Address Register */ - char res3[88]; - uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */ - char res4[8]; - uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */ - uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */ - char res5[96]; - uint tctrl; /* 0x24100 - Transmit Control Register */ - uint tstat; /* 0x24104 - Transmit Status Register */ - char res6[4]; - uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */ - char res7[16]; - uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */ - uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */ - char res8[88]; - uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */ - uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */ - char res9[120]; - uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */ - uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */ - char res10[168]; - uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */ - uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */ - uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */ - uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */ - uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */ - uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */ - uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */ - char res11[52]; - uint rctrl; /* 0x24300 - Receive Control Register */ - uint rstat; /* 0x24304 - Receive Status Register */ - char res12[4]; - uint rbdlen; /* 0x2430c - RxBD Data Length Register */ - char res13[16]; - uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */ - uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */ - char res14[24]; - uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ - uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */ - char res15[56]; - uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */ - uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */ - uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */ - uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */ - uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */ - uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */ - uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */ - uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */ - char res16[96]; - uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */ - uint rbase; /* 0x24404 - Receive Descriptor Base Address */ - uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */ - uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */ - uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */ - uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */ - uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */ - uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */ - char res17[224]; - uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */ - uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */ - uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */ - uint hafdup; /* 0x2450c - Half Duplex Register */ - uint maxfrm; /* 0x24510 - Maximum Frame Length Register */ - char res18[12]; - uint miimcfg; /* 0x24520 - MII Management Configuration Register */ - uint miimcom; /* 0x24524 - MII Management Command Register */ - uint miimadd; /* 0x24528 - MII Management Address Register */ - uint miimcon; /* 0x2452c - MII Management Control Register */ - uint miimstat; /* 0x24530 - MII Management Status Register */ - uint miimind; /* 0x24534 - MII Management Indicator Register */ - char res19[4]; - uint ifstat; /* 0x2453c - Interface Status Register */ - uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */ - uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */ - char res20[312]; - uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */ - uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */ - uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */ - uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */ - uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */ - uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */ - uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ - uint rbyt; /* 0x2469c - Receive Byte Counter */ - uint rpkt; /* 0x246a0 - Receive Packet Counter */ - uint rfcs; /* 0x246a4 - Receive FCS Error Counter */ - uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */ - uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */ - uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */ - uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */ - uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */ - uint raln; /* 0x246bc - Receive Alignment Error Counter */ - uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */ - uint rcde; /* 0x246c4 - Receive Code Error Counter */ - uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */ - uint rund; /* 0x246cc - Receive Undersize Packet Counter */ - uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */ - uint rfrg; /* 0x246d4 - Receive Fragments Counter */ - uint rjbr; /* 0x246d8 - Receive Jabber Counter */ - uint rdrp; /* 0x246dc - Receive Drop Counter */ - uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */ - uint tpkt; /* 0x246e4 - Transmit Packet Counter */ - uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */ - uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */ - uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */ - uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */ - uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */ - uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */ - uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */ - uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */ - uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */ - uint tncl; /* 0x2470c - Transmit Total Collision Counter */ - char res21[4]; - uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */ - uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */ - uint tfcs; /* 0x2471c - Transmit FCS Error Counter */ - uint txcf; /* 0x24720 - Transmit Control Frame Counter */ - uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */ - uint tund; /* 0x24728 - Transmit Undersize Frame Counter */ - uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */ - uint car1; /* 0x24730 - Carry Register One */ - uint car2; /* 0x24734 - Carry Register Two */ - uint cam1; /* 0x24738 - Carry Mask Register One */ - uint cam2; /* 0x2473c - Carry Mask Register Two */ - char res22[192]; - uint iaddr0; /* 0x24800 - Indivdual address register 0 */ - uint iaddr1; /* 0x24804 - Indivdual address register 1 */ - uint iaddr2; /* 0x24808 - Indivdual address register 2 */ - uint iaddr3; /* 0x2480c - Indivdual address register 3 */ - uint iaddr4; /* 0x24810 - Indivdual address register 4 */ - uint iaddr5; /* 0x24814 - Indivdual address register 5 */ - uint iaddr6; /* 0x24818 - Indivdual address register 6 */ - uint iaddr7; /* 0x2481c - Indivdual address register 7 */ - char res23[96]; - uint gaddr0; /* 0x24880 - Global address register 0 */ - uint gaddr1; /* 0x24884 - Global address register 1 */ - uint gaddr2; /* 0x24888 - Global address register 2 */ - uint gaddr3; /* 0x2488c - Global address register 3 */ - uint gaddr4; /* 0x24890 - Global address register 4 */ - uint gaddr5; /* 0x24894 - Global address register 5 */ - uint gaddr6; /* 0x24898 - Global address register 6 */ - uint gaddr7; /* 0x2489c - Global address register 7 */ - char res24[96]; - uint pmd0; /* 0x24900 - Pattern Match Data Register */ - char res25[4]; - uint pmask0; /* 0x24908 - Pattern Mask Register */ - char res26[4]; - uint pcntrl0; /* 0x24910 - Pattern Match Control Register */ - char res27[4]; - uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */ - uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd1; /* 0x24920 - Pattern Match Data Register */ - char res28[4]; - uint pmask1; /* 0x24928 - Pattern Mask Register */ - char res29[4]; - uint pcntrl1; /* 0x24930 - Pattern Match Control Register */ - char res30[4]; - uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */ - uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd2; /* 0x24940 - Pattern Match Data Register */ - char res31[4]; - uint pmask2; /* 0x24948 - Pattern Mask Register */ - char res32[4]; - uint pcntrl2; /* 0x24950 - Pattern Match Control Register */ - char res33[4]; - uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */ - uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd3; /* 0x24960 - Pattern Match Data Register */ - char res34[4]; - uint pmask3; /* 0x24968 - Pattern Mask Register */ - char res35[4]; - uint pcntrl3; /* 0x24970 - Pattern Match Control Register */ - char res36[4]; - uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */ - uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd4; /* 0x24980 - Pattern Match Data Register */ - char res37[4]; - uint pmask4; /* 0x24988 - Pattern Mask Register */ - char res38[4]; - uint pcntrl4; /* 0x24990 - Pattern Match Control Register */ - char res39[4]; - uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */ - uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd5; /* 0x249a0 - Pattern Match Data Register */ - char res40[4]; - uint pmask5; /* 0x249a8 - Pattern Mask Register */ - char res41[4]; - uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */ - char res42[4]; - uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */ - uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd6; /* 0x249c0 - Pattern Match Data Register */ - char res43[4]; - uint pmask6; /* 0x249c8 - Pattern Mask Register */ - char res44[4]; - uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */ - char res45[4]; - uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */ - uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd7; /* 0x249e0 - Pattern Match Data Register */ - char res46[4]; - uint pmask7; /* 0x249e8 - Pattern Mask Register */ - char res47[4]; - uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */ - char res48[4]; - uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */ - uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd8; /* 0x24a00 - Pattern Match Data Register */ - char res49[4]; - uint pmask8; /* 0x24a08 - Pattern Mask Register */ - char res50[4]; - uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */ - char res51[4]; - uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */ - uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd9; /* 0x24a20 - Pattern Match Data Register */ - char res52[4]; - uint pmask9; /* 0x24a28 - Pattern Mask Register */ - char res53[4]; - uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */ - char res54[4]; - uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */ - uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd10; /* 0x24a40 - Pattern Match Data Register */ - char res55[4]; - uint pmask10; /* 0x24a48 - Pattern Mask Register */ - char res56[4]; - uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */ - char res57[4]; - uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */ - uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd11; /* 0x24a60 - Pattern Match Data Register */ - char res58[4]; - uint pmask11; /* 0x24a68 - Pattern Mask Register */ - char res59[4]; - uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */ - char res60[4]; - uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */ - uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd12; /* 0x24a80 - Pattern Match Data Register */ - char res61[4]; - uint pmask12; /* 0x24a88 - Pattern Mask Register */ - char res62[4]; - uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */ - char res63[4]; - uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */ - uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd13; /* 0x24aa0 - Pattern Match Data Register */ - char res64[4]; - uint pmask13; /* 0x24aa8 - Pattern Mask Register */ - char res65[4]; - uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */ - char res66[4]; - uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */ - uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd14; /* 0x24ac0 - Pattern Match Data Register */ - char res67[4]; - uint pmask14; /* 0x24ac8 - Pattern Mask Register */ - char res68[4]; - uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */ - char res69[4]; - uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */ - uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */ - uint pmd15; /* 0x24ae0 - Pattern Match Data Register */ - char res70[4]; - uint pmask15; /* 0x24ae8 - Pattern Mask Register */ - char res71[4]; - uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */ - char res72[4]; - uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */ - uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */ - char res73[248]; - uint attr; /* 0x24bf8 - Attributes Register */ - uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */ - char res74[1024]; + u8 res1[16]; + u32 ievent; /* IRQ Event */ + u32 imask; /* IRQ Mask */ + u32 edis; /* Error Disabled */ + u8 res2[4]; + u32 ecntrl; /* Ethernet Control */ + u32 minflr; /* Minimum Frame Len */ + u32 ptv; /* Pause Time Value */ + u32 dmactrl; /* DMA Control */ + u32 tbipa; /* TBI PHY Addr */ + u8 res3[88]; + u32 fifo_tx_thr; /* FIFO transmit threshold */ + u8 res4[8]; + u32 fifo_tx_starve; /* FIFO transmit starve */ + u32 fifo_tx_starve_shutoff; /* FIFO transmit starve shutoff */ + u8 res5[96]; + u32 tctrl; /* TX Control */ + u32 tstat; /* TX Status */ + u8 res6[4]; + u32 tbdlen; /* TX Buffer Desc Data Len */ + u8 res7[16]; + u32 ctbptrh; /* Current TX Buffer Desc Ptr High */ + u32 ctbptr; /* Current TX Buffer Desc Ptr */ + u8 res8[88]; + u32 tbptrh; /* TX Buffer Desc Ptr High */ + u32 tbptr; /* TX Buffer Desc Ptr Low */ + u8 res9[120]; + u32 tbaseh; /* TX Desc Base Addr High */ + u32 tbase; /* TX Desc Base Addr */ + u8 res10[168]; + u32 ostbd; /* Out-of-Sequence(OOS) TX Buffer Desc */ + u32 ostbdp; /* OOS TX Data Buffer Ptr */ + u32 os32tbdp; /* OOS 32 Bytes TX Data Buffer Ptr Low */ + u32 os32iptrh; /* OOS 32 Bytes TX Insert Ptr High */ + u32 os32iptrl; /* OOS 32 Bytes TX Insert Ptr Low */ + u32 os32tbdr; /* OOS 32 Bytes TX Reserved */ + u32 os32iil; /* OOS 32 Bytes TX Insert Idx/Len */ + u8 res11[52]; + u32 rctrl; /* RX Control */ + u32 rstat; /* RX Status */ + u8 res12[4]; + u32 rbdlen; /* RxBD Data Len */ + u8 res13[16]; + u32 crbptrh; /* Current RX Buffer Desc Ptr High */ + u32 crbptr; /* Current RX Buffer Desc Ptr */ + u8 res14[24]; + u32 mrblr; /* Maximum RX Buffer Len */ + u32 mrblr2r3; /* Maximum RX Buffer Len R2R3 */ + u8 res15[56]; + u32 rbptrh; /* RX Buffer Desc Ptr High 0 */ + u32 rbptr; /* RX Buffer Desc Ptr */ + u32 rbptrh1; /* RX Buffer Desc Ptr High 1 */ + u32 rbptrl1; /* RX Buffer Desc Ptr Low 1 */ + u32 rbptrh2; /* RX Buffer Desc Ptr High 2 */ + u32 rbptrl2; /* RX Buffer Desc Ptr Low 2 */ + u32 rbptrh3; /* RX Buffer Desc Ptr High 3 */ + u32 rbptrl3; /* RX Buffer Desc Ptr Low 3 */ + u8 res16[96]; + u32 rbaseh; /* RX Desc Base Addr High 0 */ + u32 rbase; /* RX Desc Base Addr */ + u32 rbaseh1; /* RX Desc Base Addr High 1 */ + u32 rbasel1; /* RX Desc Base Addr Low 1 */ + u32 rbaseh2; /* RX Desc Base Addr High 2 */ + u32 rbasel2; /* RX Desc Base Addr Low 2 */ + u32 rbaseh3; /* RX Desc Base Addr High 3 */ + u32 rbasel3; /* RX Desc Base Addr Low 3 */ + u8 res17[224]; + u32 maccfg1; /* MAC Configuration 1 */ + u32 maccfg2; /* MAC Configuration 2 */ + u32 ipgifg; /* Inter Packet Gap/Inter Frame Gap */ + u32 hafdup; /* Half Duplex */ + u32 maxfrm; /* Maximum Frame Len */ + u8 res18[12]; + u32 miimcfg; /* MII Management Configuration */ + u32 miimcom; /* MII Management Cmd */ + u32 miimadd; /* MII Management Addr */ + u32 miimcon; /* MII Management Control */ + u32 miimstat; /* MII Management Status */ + u32 miimind; /* MII Management Indicator */ + u8 res19[4]; + u32 ifstat; /* Interface Status */ + u32 macstnaddr1; /* Station Addr Part 1 */ + u32 macstnaddr2; /* Station Addr Part 2 */ + u8 res20[312]; + u32 tr64; /* TX & RX 64-byte Frame Counter */ + u32 tr127; /* TX & RX 65-127 byte Frame Counter */ + u32 tr255; /* TX & RX 128-255 byte Frame Counter */ + u32 tr511; /* TX & RX 256-511 byte Frame Counter */ + u32 tr1k; /* TX & RX 512-1023 byte Frame Counter */ + u32 trmax; /* TX & RX 1024-1518 byte Frame Counter */ + u32 trmgv; /* TX & RX 1519-1522 byte Good VLAN Frame */ + u32 rbyt; /* RX Byte Counter */ + u32 rpkt; /* RX Packet Counter */ + u32 rfcs; /* RX FCS Error Counter */ + u32 rmca; /* RX Multicast Packet Counter */ + u32 rbca; /* RX Broadcast Packet Counter */ + u32 rxcf; /* RX Control Frame Packet Counter */ + u32 rxpf; /* RX Pause Frame Packet Counter */ + u32 rxuo; /* RX Unknown OP Code Counter */ + u32 raln; /* RX Alignment Error Counter */ + u32 rflr; /* RX Frame Len Error Counter */ + u32 rcde; /* RX Code Error Counter */ + u32 rcse; /* RX Carrier Sense Error Counter */ + u32 rund; /* RX Undersize Packet Counter */ + u32 rovr; /* RX Oversize Packet Counter */ + u32 rfrg; /* RX Fragments Counter */ + u32 rjbr; /* RX Jabber Counter */ + u32 rdrp; /* RX Drop Counter */ + u32 tbyt; /* TX Byte Counter Counter */ + u32 tpkt; /* TX Packet Counter */ + u32 tmca; /* TX Multicast Packet Counter */ + u32 tbca; /* TX Broadcast Packet Counter */ + u32 txpf; /* TX Pause Control Frame Counter */ + u32 tdfr; /* TX Deferral Packet Counter */ + u32 tedf; /* TX Excessive Deferral Packet Counter */ + u32 tscl; /* TX Single Collision Packet Counter */ + u32 tmcl; /* TX Multiple Collision Packet Counter */ + u32 tlcl; /* TX Late Collision Packet Counter */ + u32 txcl; /* TX Excessive Collision Packet Counter */ + u32 tncl; /* TX Total Collision Counter */ + u8 res21[4]; + u32 tdrp; /* TX Drop Frame Counter */ + u32 tjbr; /* TX Jabber Frame Counter */ + u32 tfcs; /* TX FCS Error Counter */ + u32 txcf; /* TX Control Frame Counter */ + u32 tovr; /* TX Oversize Frame Counter */ + u32 tund; /* TX Undersize Frame Counter */ + u32 tfrg; /* TX Fragments Frame Counter */ + u32 car1; /* Carry One */ + u32 car2; /* Carry Two */ + u32 cam1; /* Carry Mask One */ + u32 cam2; /* Carry Mask Two */ + u8 res22[192]; + u32 iaddr0; /* Indivdual addr 0 */ + u32 iaddr1; /* Indivdual addr 1 */ + u32 iaddr2; /* Indivdual addr 2 */ + u32 iaddr3; /* Indivdual addr 3 */ + u32 iaddr4; /* Indivdual addr 4 */ + u32 iaddr5; /* Indivdual addr 5 */ + u32 iaddr6; /* Indivdual addr 6 */ + u32 iaddr7; /* Indivdual addr 7 */ + u8 res23[96]; + u32 gaddr0; /* Global addr 0 */ + u32 gaddr1; /* Global addr 1 */ + u32 gaddr2; /* Global addr 2 */ + u32 gaddr3; /* Global addr 3 */ + u32 gaddr4; /* Global addr 4 */ + u32 gaddr5; /* Global addr 5 */ + u32 gaddr6; /* Global addr 6 */ + u32 gaddr7; /* Global addr 7 */ + u8 res24[96]; + u32 pmd0; /* Pattern Match Data */ + u8 res25[4]; + u32 pmask0; /* Pattern Mask */ + u8 res26[4]; + u32 pcntrl0; /* Pattern Match Control */ + u8 res27[4]; + u32 pattrb0; /* Pattern Match Attrs */ + u32 pattrbeli0; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd1; /* Pattern Match Data */ + u8 res28[4]; + u32 pmask1; /* Pattern Mask */ + u8 res29[4]; + u32 pcntrl1; /* Pattern Match Control */ + u8 res30[4]; + u32 pattrb1; /* Pattern Match Attrs */ + u32 pattrbeli1; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd2; /* Pattern Match Data */ + u8 res31[4]; + u32 pmask2; /* Pattern Mask */ + u8 res32[4]; + u32 pcntrl2; /* Pattern Match Control */ + u8 res33[4]; + u32 pattrb2; /* Pattern Match Attrs */ + u32 pattrbeli2; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd3; /* Pattern Match Data */ + u8 res34[4]; + u32 pmask3; /* Pattern Mask */ + u8 res35[4]; + u32 pcntrl3; /* Pattern Match Control */ + u8 res36[4]; + u32 pattrb3; /* Pattern Match Attrs */ + u32 pattrbeli3; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd4; /* Pattern Match Data */ + u8 res37[4]; + u32 pmask4; /* Pattern Mask */ + u8 res38[4]; + u32 pcntrl4; /* Pattern Match Control */ + u8 res39[4]; + u32 pattrb4; /* Pattern Match Attrs */ + u32 pattrbeli4; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd5; /* Pattern Match Data */ + u8 res40[4]; + u32 pmask5; /* Pattern Mask */ + u8 res41[4]; + u32 pcntrl5; /* Pattern Match Control */ + u8 res42[4]; + u32 pattrb5; /* Pattern Match Attrs */ + u32 pattrbeli5; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd6; /* Pattern Match Data */ + u8 res43[4]; + u32 pmask6; /* Pattern Mask */ + u8 res44[4]; + u32 pcntrl6; /* Pattern Match Control */ + u8 res45[4]; + u32 pattrb6; /* Pattern Match Attrs */ + u32 pattrbeli6; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd7; /* Pattern Match Data */ + u8 res46[4]; + u32 pmask7; /* Pattern Mask */ + u8 res47[4]; + u32 pcntrl7; /* Pattern Match Control */ + u8 res48[4]; + u32 pattrb7; /* Pattern Match Attrs */ + u32 pattrbeli7; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd8; /* Pattern Match Data */ + u8 res49[4]; + u32 pmask8; /* Pattern Mask */ + u8 res50[4]; + u32 pcntrl8; /* Pattern Match Control */ + u8 res51[4]; + u32 pattrb8; /* Pattern Match Attrs */ + u32 pattrbeli8; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd9; /* Pattern Match Data */ + u8 res52[4]; + u32 pmask9; /* Pattern Mask */ + u8 res53[4]; + u32 pcntrl9; /* Pattern Match Control */ + u8 res54[4]; + u32 pattrb9; /* Pattern Match Attrs */ + u32 pattrbeli9; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd10; /* Pattern Match Data */ + u8 res55[4]; + u32 pmask10; /* Pattern Mask */ + u8 res56[4]; + u32 pcntrl10; /* Pattern Match Control */ + u8 res57[4]; + u32 pattrb10; /* Pattern Match Attrs */ + u32 pattrbeli10; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd11; /* Pattern Match Data */ + u8 res58[4]; + u32 pmask11; /* Pattern Mask */ + u8 res59[4]; + u32 pcntrl11; /* Pattern Match Control */ + u8 res60[4]; + u32 pattrb11; /* Pattern Match Attrs */ + u32 pattrbeli11; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd12; /* Pattern Match Data */ + u8 res61[4]; + u32 pmask12; /* Pattern Mask */ + u8 res62[4]; + u32 pcntrl12; /* Pattern Match Control */ + u8 res63[4]; + u32 pattrb12; /* Pattern Match Attrs */ + u32 pattrbeli12; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd13; /* Pattern Match Data */ + u8 res64[4]; + u32 pmask13; /* Pattern Mask */ + u8 res65[4]; + u32 pcntrl13; /* Pattern Match Control */ + u8 res66[4]; + u32 pattrb13; /* Pattern Match Attrs */ + u32 pattrbeli13; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd14; /* Pattern Match Data */ + u8 res67[4]; + u32 pmask14; /* Pattern Mask */ + u8 res68[4]; + u32 pcntrl14; /* Pattern Match Control */ + u8 res69[4]; + u32 pattrb14; /* Pattern Match Attrs */ + u32 pattrbeli14; /* Pattern Match Attrs Extract Len & Idx */ + u32 pmd15; /* Pattern Match Data */ + u8 res70[4]; + u32 pmask15; /* Pattern Mask */ + u8 res71[4]; + u32 pcntrl15; /* Pattern Match Control */ + u8 res72[4]; + u32 pattrb15; /* Pattern Match Attrs */ + u32 pattrbeli15; /* Pattern Match Attrs Extract Len & Idx */ + u8 res73[248]; + u32 attr; /* Attrs */ + u32 attreli; /* Attrs Extract Len & Idx */ + u8 res74[1024]; } ccsr_tsec_t; -/* - * PIC Registers(0x4_0000-0x8_0000) - */ +/* PIC Registers */ typedef struct ccsr_pic { - char res1[64]; /* 0x40000 */ - uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ - char res2[12]; - uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ - char res3[12]; - uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */ - char res4[12]; - uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */ - char res5[12]; - uint ctpr; /* 0x40080 - Current Task Priority Register */ - char res6[12]; - uint whoami; /* 0x40090 - Who Am I Register */ - char res7[12]; - uint iack; /* 0x400a0 - Interrupt Acknowledge Register */ - char res8[12]; - uint eoi; /* 0x400b0 - End Of Interrupt Register */ - char res9[3916]; - uint frr; /* 0x41000 - Feature Reporting Register */ - char res10[28]; - uint gcr; /* 0x41020 - Global Configuration Register */ -#define MPC85xx_PICGCR_RST 0x80000000 -#define MPC85xx_PICGCR_M 0x20000000 - char res11[92]; - uint vir; /* 0x41080 - Vendor Identification Register */ - char res12[12]; - uint pir; /* 0x41090 - Processor Initialization Register */ - char res13[12]; - uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */ - char res14[12]; - uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */ - char res15[12]; - uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */ - char res16[12]; - uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */ - char res17[12]; - uint svr; /* 0x410e0 - Spurious Vector Register */ - char res18[12]; - uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */ - char res19[12]; - uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */ - char res20[12]; - uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */ - char res21[12]; - uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */ - char res22[12]; - uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */ - char res23[12]; - uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */ - char res24[12]; - uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */ - char res25[12]; - uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */ - char res26[12]; - uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */ - char res27[12]; - uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */ - char res28[12]; - uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */ - char res29[12]; - uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */ - char res30[12]; - uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */ - char res31[12]; - uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */ - char res32[12]; - uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */ - char res33[12]; - uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */ - char res34[12]; - uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */ - char res35[268]; - uint tcr; /* 0x41300 - Timer Control Register */ - char res36[12]; - uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */ - char res37[12]; - uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */ - char res38[12]; - uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */ - char res39[12]; - uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */ - char res40[188]; - uint msgr0; /* 0x41400 - Message Register 0 */ - char res41[12]; - uint msgr1; /* 0x41410 - Message Register 1 */ - char res42[12]; - uint msgr2; /* 0x41420 - Message Register 2 */ - char res43[12]; - uint msgr3; /* 0x41430 - Message Register 3 */ - char res44[204]; - uint mer; /* 0x41500 - Message Enable Register */ - char res45[12]; - uint msr; /* 0x41510 - Message Status Register */ - char res46[60140]; - uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */ - char res47[12]; - uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */ - char res48[12]; - uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */ - char res49[12]; - uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */ - char res50[12]; - uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */ - char res51[12]; - uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */ - char res52[12]; - uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */ - char res53[12]; - uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */ - char res54[12]; - uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */ - char res55[12]; - uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */ - char res56[12]; - uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */ - char res57[12]; - uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */ - char res58[12]; - uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */ - char res59[12]; - uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */ - char res60[12]; - uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */ - char res61[12]; - uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */ - char res62[12]; - uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */ - char res63[12]; - uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */ - char res64[12]; - uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */ - char res65[12]; - uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */ - char res66[12]; - uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */ - char res67[12]; - uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */ - char res68[12]; - uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */ - char res69[12]; - uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */ - char res70[140]; - uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */ - char res71[12]; - uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */ - char res72[12]; - uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */ - char res73[12]; - uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */ - char res74[12]; - uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */ - char res75[12]; - uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */ - char res76[12]; - uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */ - char res77[12]; - uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */ - char res78[12]; - uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */ - char res79[12]; - uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */ - char res80[12]; - uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */ - char res81[12]; - uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */ - char res82[12]; - uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */ - char res83[12]; - uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */ - char res84[12]; - uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */ - char res85[12]; - uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */ - char res86[12]; - uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */ - char res87[12]; - uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */ - char res88[12]; - uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */ - char res89[12]; - uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */ - char res90[12]; - uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */ - char res91[12]; - uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */ - char res92[12]; - uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */ - char res93[12]; - uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */ - char res94[12]; - uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */ - char res95[12]; - uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */ - char res96[12]; - uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */ - char res97[12]; - uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */ - char res98[12]; - uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */ - char res99[12]; - uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */ - char res100[12]; - uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */ - char res101[12]; - uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */ - char res102[12]; - uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */ - char res103[12]; - uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */ - char res104[12]; - uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */ - char res105[12]; - uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */ - char res106[12]; - uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */ - char res107[12]; - uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */ - char res108[12]; - uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */ - char res109[12]; - uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */ - char res110[12]; - uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */ - char res111[12]; - uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */ - char res112[12]; - uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */ - char res113[12]; - uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */ - char res114[12]; - uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */ - char res115[12]; - uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */ - char res116[12]; - uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */ - char res117[12]; - uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */ - char res118[12]; - uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */ - char res119[12]; - uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */ - char res120[12]; - uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */ - char res121[12]; - uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */ - char res122[12]; - uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */ - char res123[12]; - uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */ - char res124[12]; - uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */ - char res125[12]; - uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */ - char res126[12]; - uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */ - char res127[12]; - uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */ - char res128[12]; - uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */ - char res129[12]; - uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */ - char res130[12]; - uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */ - char res131[12]; - uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */ - char res132[12]; - uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */ - char res133[12]; - uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */ - char res134[4108]; - uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */ - char res135[12]; - uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */ - char res136[12]; - uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */ - char res137[12]; - uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */ - char res138[12]; - uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */ - char res139[12]; - uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */ - char res140[12]; - uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */ - char res141[12]; - uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */ - char res142[59852]; - uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */ - char res143[12]; - uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */ - char res144[12]; - uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */ - char res145[12]; - uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */ - char res146[12]; - uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */ - char res147[12]; - uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */ - char res148[12]; - uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */ - char res149[12]; - uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */ - char res150[130892]; + u8 res1[64]; + u32 ipidr0; /* Interprocessor IRQ Dispatch 0 */ + u8 res2[12]; + u32 ipidr1; /* Interprocessor IRQ Dispatch 1 */ + u8 res3[12]; + u32 ipidr2; /* Interprocessor IRQ Dispatch 2 */ + u8 res4[12]; + u32 ipidr3; /* Interprocessor IRQ Dispatch 3 */ + u8 res5[12]; + u32 ctpr; /* Current Task Priority */ + u8 res6[12]; + u32 whoami; /* Who Am I */ + u8 res7[12]; + u32 iack; /* IRQ Acknowledge */ + u8 res8[12]; + u32 eoi; /* End Of IRQ */ + u8 res9[3916]; + u32 frr; /* Feature Reporting */ + u8 res10[28]; + u32 gcr; /* Global Configuration */ +#define MPC85xx_PICGCR_RST 0x80000000 +#define MPC85xx_PICGCR_M 0x20000000 + u8 res11[92]; + u32 vir; /* Vendor Identification */ + u8 res12[12]; + u32 pir; /* Processor Initialization */ + u8 res13[12]; + u32 ipivpr0; /* IPI Vector/Priority 0 */ + u8 res14[12]; + u32 ipivpr1; /* IPI Vector/Priority 1 */ + u8 res15[12]; + u32 ipivpr2; /* IPI Vector/Priority 2 */ + u8 res16[12]; + u32 ipivpr3; /* IPI Vector/Priority 3 */ + u8 res17[12]; + u32 svr; /* Spurious Vector */ + u8 res18[12]; + u32 tfrr; /* Timer Frequency Reporting */ + u8 res19[12]; + u32 gtccr0; /* Global Timer Current Count 0 */ + u8 res20[12]; + u32 gtbcr0; /* Global Timer Base Count 0 */ + u8 res21[12]; + u32 gtvpr0; /* Global Timer Vector/Priority 0 */ + u8 res22[12]; + u32 gtdr0; /* Global Timer Destination 0 */ + u8 res23[12]; + u32 gtccr1; /* Global Timer Current Count 1 */ + u8 res24[12]; + u32 gtbcr1; /* Global Timer Base Count 1 */ + u8 res25[12]; + u32 gtvpr1; /* Global Timer Vector/Priority 1 */ + u8 res26[12]; + u32 gtdr1; /* Global Timer Destination 1 */ + u8 res27[12]; + u32 gtccr2; /* Global Timer Current Count 2 */ + u8 res28[12]; + u32 gtbcr2; /* Global Timer Base Count 2 */ + u8 res29[12]; + u32 gtvpr2; /* Global Timer Vector/Priority 2 */ + u8 res30[12]; + u32 gtdr2; /* Global Timer Destination 2 */ + u8 res31[12]; + u32 gtccr3; /* Global Timer Current Count 3 */ + u8 res32[12]; + u32 gtbcr3; /* Global Timer Base Count 3 */ + u8 res33[12]; + u32 gtvpr3; /* Global Timer Vector/Priority 3 */ + u8 res34[12]; + u32 gtdr3; /* Global Timer Destination 3 */ + u8 res35[268]; + u32 tcr; /* Timer Control */ + u8 res36[12]; + u32 irqsr0; /* IRQ_OUT Summary 0 */ + u8 res37[12]; + u32 irqsr1; /* IRQ_OUT Summary 1 */ + u8 res38[12]; + u32 cisr0; /* Critical IRQ Summary 0 */ + u8 res39[12]; + u32 cisr1; /* Critical IRQ Summary 1 */ + u8 res40[188]; + u32 msgr0; /* Message 0 */ + u8 res41[12]; + u32 msgr1; /* Message 1 */ + u8 res42[12]; + u32 msgr2; /* Message 2 */ + u8 res43[12]; + u32 msgr3; /* Message 3 */ + u8 res44[204]; + u32 mer; /* Message Enable */ + u8 res45[12]; + u32 msr; /* Message Status */ + u8 res46[60140]; + u32 eivpr0; /* External IRQ Vector/Priority 0 */ + u8 res47[12]; + u32 eidr0; /* External IRQ Destination 0 */ + u8 res48[12]; + u32 eivpr1; /* External IRQ Vector/Priority 1 */ + u8 res49[12]; + u32 eidr1; /* External IRQ Destination 1 */ + u8 res50[12]; + u32 eivpr2; /* External IRQ Vector/Priority 2 */ + u8 res51[12]; + u32 eidr2; /* External IRQ Destination 2 */ + u8 res52[12]; + u32 eivpr3; /* External IRQ Vector/Priority 3 */ + u8 res53[12]; + u32 eidr3; /* External IRQ Destination 3 */ + u8 res54[12]; + u32 eivpr4; /* External IRQ Vector/Priority 4 */ + u8 res55[12]; + u32 eidr4; /* External IRQ Destination 4 */ + u8 res56[12]; + u32 eivpr5; /* External IRQ Vector/Priority 5 */ + u8 res57[12]; + u32 eidr5; /* External IRQ Destination 5 */ + u8 res58[12]; + u32 eivpr6; /* External IRQ Vector/Priority 6 */ + u8 res59[12]; + u32 eidr6; /* External IRQ Destination 6 */ + u8 res60[12]; + u32 eivpr7; /* External IRQ Vector/Priority 7 */ + u8 res61[12]; + u32 eidr7; /* External IRQ Destination 7 */ + u8 res62[12]; + u32 eivpr8; /* External IRQ Vector/Priority 8 */ + u8 res63[12]; + u32 eidr8; /* External IRQ Destination 8 */ + u8 res64[12]; + u32 eivpr9; /* External IRQ Vector/Priority 9 */ + u8 res65[12]; + u32 eidr9; /* External IRQ Destination 9 */ + u8 res66[12]; + u32 eivpr10; /* External IRQ Vector/Priority 10 */ + u8 res67[12]; + u32 eidr10; /* External IRQ Destination 10 */ + u8 res68[12]; + u32 eivpr11; /* External IRQ Vector/Priority 11 */ + u8 res69[12]; + u32 eidr11; /* External IRQ Destination 11 */ + u8 res70[140]; + u32 iivpr0; /* Internal IRQ Vector/Priority 0 */ + u8 res71[12]; + u32 iidr0; /* Internal IRQ Destination 0 */ + u8 res72[12]; + u32 iivpr1; /* Internal IRQ Vector/Priority 1 */ + u8 res73[12]; + u32 iidr1; /* Internal IRQ Destination 1 */ + u8 res74[12]; + u32 iivpr2; /* Internal IRQ Vector/Priority 2 */ + u8 res75[12]; + u32 iidr2; /* Internal IRQ Destination 2 */ + u8 res76[12]; + u32 iivpr3; /* Internal IRQ Vector/Priority 3 */ + u8 res77[12]; + u32 iidr3; /* Internal IRQ Destination 3 */ + u8 res78[12]; + u32 iivpr4; /* Internal IRQ Vector/Priority 4 */ + u8 res79[12]; + u32 iidr4; /* Internal IRQ Destination 4 */ + u8 res80[12]; + u32 iivpr5; /* Internal IRQ Vector/Priority 5 */ + u8 res81[12]; + u32 iidr5; /* Internal IRQ Destination 5 */ + u8 res82[12]; + u32 iivpr6; /* Internal IRQ Vector/Priority 6 */ + u8 res83[12]; + u32 iidr6; /* Internal IRQ Destination 6 */ + u8 res84[12]; + u32 iivpr7; /* Internal IRQ Vector/Priority 7 */ + u8 res85[12]; + u32 iidr7; /* Internal IRQ Destination 7 */ + u8 res86[12]; + u32 iivpr8; /* Internal IRQ Vector/Priority 8 */ + u8 res87[12]; + u32 iidr8; /* Internal IRQ Destination 8 */ + u8 res88[12]; + u32 iivpr9; /* Internal IRQ Vector/Priority 9 */ + u8 res89[12]; + u32 iidr9; /* Internal IRQ Destination 9 */ + u8 res90[12]; + u32 iivpr10; /* Internal IRQ Vector/Priority 10 */ + u8 res91[12]; + u32 iidr10; /* Internal IRQ Destination 10 */ + u8 res92[12]; + u32 iivpr11; /* Internal IRQ Vector/Priority 11 */ + u8 res93[12]; + u32 iidr11; /* Internal IRQ Destination 11 */ + u8 res94[12]; + u32 iivpr12; /* Internal IRQ Vector/Priority 12 */ + u8 res95[12]; + u32 iidr12; /* Internal IRQ Destination 12 */ + u8 res96[12]; + u32 iivpr13; /* Internal IRQ Vector/Priority 13 */ + u8 res97[12]; + u32 iidr13; /* Internal IRQ Destination 13 */ + u8 res98[12]; + u32 iivpr14; /* Internal IRQ Vector/Priority 14 */ + u8 res99[12]; + u32 iidr14; /* Internal IRQ Destination 14 */ + u8 res100[12]; + u32 iivpr15; /* Internal IRQ Vector/Priority 15 */ + u8 res101[12]; + u32 iidr15; /* Internal IRQ Destination 15 */ + u8 res102[12]; + u32 iivpr16; /* Internal IRQ Vector/Priority 16 */ + u8 res103[12]; + u32 iidr16; /* Internal IRQ Destination 16 */ + u8 res104[12]; + u32 iivpr17; /* Internal IRQ Vector/Priority 17 */ + u8 res105[12]; + u32 iidr17; /* Internal IRQ Destination 17 */ + u8 res106[12]; + u32 iivpr18; /* Internal IRQ Vector/Priority 18 */ + u8 res107[12]; + u32 iidr18; /* Internal IRQ Destination 18 */ + u8 res108[12]; + u32 iivpr19; /* Internal IRQ Vector/Priority 19 */ + u8 res109[12]; + u32 iidr19; /* Internal IRQ Destination 19 */ + u8 res110[12]; + u32 iivpr20; /* Internal IRQ Vector/Priority 20 */ + u8 res111[12]; + u32 iidr20; /* Internal IRQ Destination 20 */ + u8 res112[12]; + u32 iivpr21; /* Internal IRQ Vector/Priority 21 */ + u8 res113[12]; + u32 iidr21; /* Internal IRQ Destination 21 */ + u8 res114[12]; + u32 iivpr22; /* Internal IRQ Vector/Priority 22 */ + u8 res115[12]; + u32 iidr22; /* Internal IRQ Destination 22 */ + u8 res116[12]; + u32 iivpr23; /* Internal IRQ Vector/Priority 23 */ + u8 res117[12]; + u32 iidr23; /* Internal IRQ Destination 23 */ + u8 res118[12]; + u32 iivpr24; /* Internal IRQ Vector/Priority 24 */ + u8 res119[12]; + u32 iidr24; /* Internal IRQ Destination 24 */ + u8 res120[12]; + u32 iivpr25; /* Internal IRQ Vector/Priority 25 */ + u8 res121[12]; + u32 iidr25; /* Internal IRQ Destination 25 */ + u8 res122[12]; + u32 iivpr26; /* Internal IRQ Vector/Priority 26 */ + u8 res123[12]; + u32 iidr26; /* Internal IRQ Destination 26 */ + u8 res124[12]; + u32 iivpr27; /* Internal IRQ Vector/Priority 27 */ + u8 res125[12]; + u32 iidr27; /* Internal IRQ Destination 27 */ + u8 res126[12]; + u32 iivpr28; /* Internal IRQ Vector/Priority 28 */ + u8 res127[12]; + u32 iidr28; /* Internal IRQ Destination 28 */ + u8 res128[12]; + u32 iivpr29; /* Internal IRQ Vector/Priority 29 */ + u8 res129[12]; + u32 iidr29; /* Internal IRQ Destination 29 */ + u8 res130[12]; + u32 iivpr30; /* Internal IRQ Vector/Priority 30 */ + u8 res131[12]; + u32 iidr30; /* Internal IRQ Destination 30 */ + u8 res132[12]; + u32 iivpr31; /* Internal IRQ Vector/Priority 31 */ + u8 res133[12]; + u32 iidr31; /* Internal IRQ Destination 31 */ + u8 res134[4108]; + u32 mivpr0; /* Messaging IRQ Vector/Priority 0 */ + u8 res135[12]; + u32 midr0; /* Messaging IRQ Destination 0 */ + u8 res136[12]; + u32 mivpr1; /* Messaging IRQ Vector/Priority 1 */ + u8 res137[12]; + u32 midr1; /* Messaging IRQ Destination 1 */ + u8 res138[12]; + u32 mivpr2; /* Messaging IRQ Vector/Priority 2 */ + u8 res139[12]; + u32 midr2; /* Messaging IRQ Destination 2 */ + u8 res140[12]; + u32 mivpr3; /* Messaging IRQ Vector/Priority 3 */ + u8 res141[12]; + u32 midr3; /* Messaging IRQ Destination 3 */ + u8 res142[59852]; + u32 ipi0dr0; /* Processor 0 Interprocessor IRQ Dispatch 0 */ + u8 res143[12]; + u32 ipi0dr1; /* Processor 0 Interprocessor IRQ Dispatch 1 */ + u8 res144[12]; + u32 ipi0dr2; /* Processor 0 Interprocessor IRQ Dispatch 2 */ + u8 res145[12]; + u32 ipi0dr3; /* Processor 0 Interprocessor IRQ Dispatch 3 */ + u8 res146[12]; + u32 ctpr0; /* Current Task Priority for Processor 0 */ + u8 res147[12]; + u32 whoami0; /* Who Am I for Processor 0 */ + u8 res148[12]; + u32 iack0; /* IRQ Acknowledge for Processor 0 */ + u8 res149[12]; + u32 eoi0; /* End Of IRQ for Processor 0 */ + u8 res150[130892]; } ccsr_pic_t; -/* - * CPM Block(0x8_0000-0xc_0000) - */ +/* CPM Block */ #ifndef CONFIG_CPM2 typedef struct ccsr_cpm { - char res[262144]; + u8 res[262144]; } ccsr_cpm_t; #else /* - * 0x8000-0x8ffff:DPARM - * 0x9000-0x90bff: General SIU + * DPARM + * General SIU */ typedef struct ccsr_cpm_siu { - char res1[80]; - uint smaer; - uint smser; - uint smevr; - char res2[4]; - uint lmaer; - uint lmser; - uint lmevr; - char res3[2964]; + u8 res1[80]; + u32 smaer; + u32 smser; + u32 smevr; + u8 res2[4]; + u32 lmaer; + u32 lmser; + u32 lmevr; + u8 res3[2964]; } ccsr_cpm_siu_t; -/* 0x90c00-0x90cff: Interrupt Controller */ +/* IRQ Controller */ typedef struct ccsr_cpm_intctl { - ushort sicr; - char res1[2]; - uint sivec; - uint sipnrh; - uint sipnrl; - uint siprr; - uint scprrh; - uint scprrl; - uint simrh; - uint simrl; - uint siexr; - char res2[88]; - uint sccr; - char res3[124]; + u16 sicr; + u8 res1[2]; + u32 sivec; + u32 sipnrh; + u32 sipnrl; + u32 siprr; + u32 scprrh; + u32 scprrl; + u32 simrh; + u32 simrl; + u32 siexr; + u8 res2[88]; + u32 sccr; + u8 res3[124]; } ccsr_cpm_intctl_t; -/* 0x90d00-0x90d7f: input/output port */ +/* input/output port */ typedef struct ccsr_cpm_iop { - uint pdira; - uint ppara; - uint psora; - uint podra; - uint pdata; - char res1[12]; - uint pdirb; - uint pparb; - uint psorb; - uint podrb; - uint pdatb; - char res2[12]; - uint pdirc; - uint pparc; - uint psorc; - uint podrc; - uint pdatc; - char res3[12]; - uint pdird; - uint ppard; - uint psord; - uint podrd; - uint pdatd; - char res4[12]; + u32 pdira; + u32 ppara; + u32 psora; + u32 podra; + u32 pdata; + u8 res1[12]; + u32 pdirb; + u32 pparb; + u32 psorb; + u32 podrb; + u32 pdatb; + u8 res2[12]; + u32 pdirc; + u32 pparc; + u32 psorc; + u32 podrc; + u32 pdatc; + u8 res3[12]; + u32 pdird; + u32 ppard; + u32 psord; + u32 podrd; + u32 pdatd; + u8 res4[12]; } ccsr_cpm_iop_t; -/* 0x90d80-0x91017: CPM timers */ +/* CPM timers */ typedef struct ccsr_cpm_timer { - u_char tgcr1; - char res1[3]; - u_char tgcr2; - char res2[11]; - ushort tmr1; - ushort tmr2; - ushort trr1; - ushort trr2; - ushort tcr1; - ushort tcr2; - ushort tcn1; - ushort tcn2; - ushort tmr3; - ushort tmr4; - ushort trr3; - ushort trr4; - ushort tcr3; - ushort tcr4; - ushort tcn3; - ushort tcn4; - ushort ter1; - ushort ter2; - ushort ter3; - ushort ter4; - char res3[608]; + u8 tgcr1; + u8 res1[3]; + u8 tgcr2; + u8 res2[11]; + u16 tmr1; + u16 tmr2; + u16 trr1; + u16 trr2; + u16 tcr1; + u16 tcr2; + u16 tcn1; + u16 tcn2; + u16 tmr3; + u16 tmr4; + u16 trr3; + u16 trr4; + u16 tcr3; + u16 tcr4; + u16 tcn3; + u16 tcn4; + u16 ter1; + u16 ter2; + u16 ter3; + u16 ter4; + u8 res3[608]; } ccsr_cpm_timer_t; -/* 0x91018-0x912ff: SDMA */ +/* SDMA */ typedef struct ccsr_cpm_sdma { - uchar sdsr; - char res1[3]; - uchar sdmr; - char res2[739]; + u8 sdsr; + u8 res1[3]; + u8 sdmr; + u8 res2[739]; } ccsr_cpm_sdma_t; -/* 0x91300-0x9131f: FCC1 */ +/* FCC1 */ typedef struct ccsr_cpm_fcc1 { - uint gfmr; - uint fpsmr; - ushort ftodr; - char res1[2]; - ushort fdsr; - char res2[2]; - ushort fcce; - char res3[2]; - ushort fccm; - char res4[2]; - u_char fccs; - char res5[3]; - u_char ftirr_phy[4]; + u32 gfmr; + u32 fpsmr; + u16 ftodr; + u8 res1[2]; + u16 fdsr; + u8 res2[2]; + u16 fcce; + u8 res3[2]; + u16 fccm; + u8 res4[2]; + u8 fccs; + u8 res5[3]; + u8 ftirr_phy[4]; } ccsr_cpm_fcc1_t; -/* 0x91320-0x9133f: FCC2 */ +/* FCC2 */ typedef struct ccsr_cpm_fcc2 { - uint gfmr; - uint fpsmr; - ushort ftodr; - char res1[2]; - ushort fdsr; - char res2[2]; - ushort fcce; - char res3[2]; - ushort fccm; - char res4[2]; - u_char fccs; - char res5[3]; - u_char ftirr_phy[4]; + u32 gfmr; + u32 fpsmr; + u16 ftodr; + u8 res1[2]; + u16 fdsr; + u8 res2[2]; + u16 fcce; + u8 res3[2]; + u16 fccm; + u8 res4[2]; + u8 fccs; + u8 res5[3]; + u8 ftirr_phy[4]; } ccsr_cpm_fcc2_t; -/* 0x91340-0x9137f: FCC3 */ +/* FCC3 */ typedef struct ccsr_cpm_fcc3 { - uint gfmr; - uint fpsmr; - ushort ftodr; - char res1[2]; - ushort fdsr; - char res2[2]; - ushort fcce; - char res3[2]; - ushort fccm; - char res4[2]; - u_char fccs; - char res5[3]; - char res[36]; + u32 gfmr; + u32 fpsmr; + u16 ftodr; + u8 res1[2]; + u16 fdsr; + u8 res2[2]; + u16 fcce; + u8 res3[2]; + u16 fccm; + u8 res4[2]; + u8 fccs; + u8 res5[3]; + u8 res[36]; } ccsr_cpm_fcc3_t; -/* 0x91380-0x9139f: FCC1 extended */ +/* FCC1 extended */ typedef struct ccsr_cpm_fcc1_ext { - uint firper; - uint firer; - uint firsr_h; - uint firsr_l; - u_char gfemr; - char res[15]; + u32 firper; + u32 firer; + u32 firsr_h; + u32 firsr_l; + u8 gfemr; + u8 res[15]; } ccsr_cpm_fcc1_ext_t; -/* 0x913a0-0x913cf: FCC2 extended */ +/* FCC2 extended */ typedef struct ccsr_cpm_fcc2_ext { - uint firper; - uint firer; - uint firsr_h; - uint firsr_l; - u_char gfemr; - char res[31]; + u32 firper; + u32 firer; + u32 firsr_h; + u32 firsr_l; + u8 gfemr; + u8 res[31]; } ccsr_cpm_fcc2_ext_t; -/* 0x913d0-0x913ff: FCC3 extended */ +/* FCC3 extended */ typedef struct ccsr_cpm_fcc3_ext { - u_char gfemr; - char res[47]; + u8 gfemr; + u8 res[47]; } ccsr_cpm_fcc3_ext_t; -/* 0x91400-0x915ef: TC layers */ +/* TC layers */ typedef struct ccsr_cpm_tmp1 { - char res[496]; + u8 res[496]; } ccsr_cpm_tmp1_t; -/* 0x915f0-0x9185f: BRGs:5,6,7,8 */ +/* BRGs:5,6,7,8 */ typedef struct ccsr_cpm_brg2 { - uint brgc5; - uint brgc6; - uint brgc7; - uint brgc8; - char res[608]; + u32 brgc5; + u32 brgc6; + u32 brgc7; + u32 brgc8; + u8 res[608]; } ccsr_cpm_brg2_t; -/* 0x91860-0x919bf: I2C */ +/* I2C */ typedef struct ccsr_cpm_i2c { - u_char i2mod; - char res1[3]; - u_char i2add; - char res2[3]; - u_char i2brg; - char res3[3]; - u_char i2com; - char res4[3]; - u_char i2cer; - char res5[3]; - u_char i2cmr; - char res6[331]; + u8 i2mod; + u8 res1[3]; + u8 i2add; + u8 res2[3]; + u8 i2brg; + u8 res3[3]; + u8 i2com; + u8 res4[3]; + u8 i2cer; + u8 res5[3]; + u8 i2cmr; + u8 res6[331]; } ccsr_cpm_i2c_t; -/* 0x919c0-0x919ef: CPM core */ +/* CPM core */ typedef struct ccsr_cpm_cp { - uint cpcr; - uint rccr; - char res1[14]; - ushort rter; - char res2[2]; - ushort rtmr; - ushort rtscr; - char res3[2]; - uint rtsr; - char res4[12]; + u32 cpcr; + u32 rccr; + u8 res1[14]; + u16 rter; + u8 res2[2]; + u16 rtmr; + u16 rtscr; + u8 res3[2]; + u32 rtsr; + u8 res4[12]; } ccsr_cpm_cp_t; -/* 0x919f0-0x919ff: BRGs:1,2,3,4 */ +/* BRGs:1,2,3,4 */ typedef struct ccsr_cpm_brg1 { - uint brgc1; - uint brgc2; - uint brgc3; - uint brgc4; + u32 brgc1; + u32 brgc2; + u32 brgc3; + u32 brgc4; } ccsr_cpm_brg1_t; -/* 0x91a00-0x91a9f: SCC1-SCC4 */ +/* SCC1-SCC4 */ typedef struct ccsr_cpm_scc { - uint gsmrl; - uint gsmrh; - ushort psmr; - char res1[2]; - ushort todr; - ushort dsr; - ushort scce; - char res2[2]; - ushort sccm; - char res3; - u_char sccs; - char res4[8]; + u32 gsmrl; + u32 gsmrh; + u16 psmr; + u8 res1[2]; + u16 todr; + u16 dsr; + u16 scce; + u8 res2[2]; + u16 sccm; + u8 res3; + u8 sccs; + u8 res4[8]; } ccsr_cpm_scc_t; -/* 0x91a80-0x91a9f */ typedef struct ccsr_cpm_tmp2 { - char res[32]; + u8 res[32]; } ccsr_cpm_tmp2_t; -/* 0x91aa0-0x91aff: SPI */ +/* SPI */ typedef struct ccsr_cpm_spi { - ushort spmode; - char res1[4]; - u_char spie; - char res2[3]; - u_char spim; - char res3[2]; - u_char spcom; - char res4[82]; + u16 spmode; + u8 res1[4]; + u8 spie; + u8 res2[3]; + u8 spim; + u8 res3[2]; + u8 spcom; + u8 res4[82]; } ccsr_cpm_spi_t; -/* 0x91b00-0x91b1f: CPM MUX */ +/* CPM MUX */ typedef struct ccsr_cpm_mux { - u_char cmxsi1cr; - char res1; - u_char cmxsi2cr; - char res2; - uint cmxfcr; - uint cmxscr; - char res3[2]; - ushort cmxuar; - char res4[16]; + u8 cmxsi1cr; + u8 res1; + u8 cmxsi2cr; + u8 res2; + u32 cmxfcr; + u32 cmxscr; + u8 res3[2]; + u16 cmxuar; + u8 res4[16]; } ccsr_cpm_mux_t; -/* 0x91b20-0xbffff: SI,MCC,etc */ +/* SI,MCC,etc */ typedef struct ccsr_cpm_tmp3 { - char res[58592]; + u8 res[58592]; } ccsr_cpm_tmp3_t; typedef struct ccsr_cpm_iram { - unsigned long iram[8192]; - char res[98304]; + u32 iram[8192]; + u8 res[98304]; } ccsr_cpm_iram_t; typedef struct ccsr_cpm { - /* Some references are into the unique and known dpram spaces, + /* Some references are into the unique & known dpram spaces, * others are from the generic base. */ #define im_dprambase im_dpram1 - u_char im_dpram1[16*1024]; - char res1[16*1024]; - u_char im_dpram2[16*1024]; - char res2[16*1024]; - ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ - ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */ - ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ - ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ - ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ + u8 im_dpram1[16*1024]; + u8 res1[16*1024]; + u8 im_dpram2[16*1024]; + u8 res2[16*1024]; + ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ + ccsr_cpm_intctl_t im_cpm_intctl; /* IRQ Controller */ + ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ + ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ + ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ ccsr_cpm_fcc1_t im_cpm_fcc1; ccsr_cpm_fcc2_t im_cpm_fcc2; ccsr_cpm_fcc3_t im_cpm_fcc3; @@ -1386,203 +1368,199 @@ typedef struct ccsr_cpm { } ccsr_cpm_t; #endif -/* - * RapidIO Registers(0xc_0000-0xe_0000) - */ +/* RapidIO Registers */ typedef struct ccsr_rio { - uint didcar; /* 0xc0000 - Device Identity Capability Register */ - uint dicar; /* 0xc0004 - Device Information Capability Register */ - uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ - uint aicar; /* 0xc000c - Assembly Information Capability Register */ - uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ - uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ - uint socar; /* 0xc0018 - Source Operations Capability Register */ - uint docar; /* 0xc001c - Destination Operations Capability Register */ - char res1[32]; - uint msr; /* 0xc0040 - Mailbox Command And Status Register */ - uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ - char res2[4]; - uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ - char res3[12]; - uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ - uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ - char res4[4]; - uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ - uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ - char res5[144]; - uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ - char res6[28]; - uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ - uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ - char res7[20]; - uint pgccsr; /* 0xc013c - Port General Command and Status Register */ - uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ - uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ - uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ - char res8[12]; - uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ - uint pccsr; /* 0xc015c - Port Control Command and Status Register */ - char res9[65184]; - uint cr; /* 0xd0000 - Port Control Command and Status Register */ - char res10[12]; - uint pcr; /* 0xd0010 - Port Configuration Register */ - uint peir; /* 0xd0014 - Port Error Injection Register */ - char res11[3048]; - uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ - char res12[12]; - uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ - char res13[12]; - uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ - char res14[4]; - uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ - char res15[4]; - uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ - char res16[12]; - uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ - char res17[4]; - uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ - char res18[4]; - uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ - char res19[12]; - uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ - char res20[4]; - uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ - char res21[4]; - uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ - char res22[12]; - uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ - char res23[4]; - uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ - char res24[4]; - uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ - char res25[12]; - uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ - char res26[4]; - uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ - char res27[4]; - uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ - char res28[12]; - uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ - char res29[4]; - uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ - char res30[4]; - uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ - char res31[12]; - uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ - char res32[4]; - uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ - char res33[4]; - uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ - char res34[12]; - uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ - char res35[4]; - uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ - char res36[4]; - uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ - char res37[76]; - uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ - char res38[4]; - uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ - char res39[4]; - uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ - char res40[12]; - uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ - char res41[4]; - uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ - char res42[4]; - uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ - char res43[12]; - uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ - char res44[4]; - uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ - char res45[4]; - uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ - char res46[12]; - uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ - char res47[4]; - uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ - char res48[4]; - uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ - char res49[12]; - uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ - char res50[12]; - uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ - char res51[12]; - uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ - uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ - uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ - uint pecr; /* 0xd0e0c - Port Error Control Register */ - uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ - uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ - uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ - char res52[4]; - uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ - char res53[4]; - uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ - uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ - char res54[464]; - uint omr; /* 0xd1000 - Outbound Mode Register */ - uint osr; /* 0xd1004 - Outbound Status Register */ - uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ - uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */ - uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */ - uint osar; /* 0xd1014 - Outbound Unit Source Address Register */ - uint odpr; /* 0xd1018 - Outbound Destination Port Register */ - uint odatr; /* 0xd101c - Outbound Destination Attributes Register */ - uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */ - uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ - uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */ - char res55[52]; - uint imr; /* 0xd1060 - Outbound Mode Register */ - uint isr; /* 0xd1064 - Inbound Status Register */ - uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ - uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */ - uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */ - uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */ - char res56[1000]; - uint dmr; /* 0xd1460 - Doorbell Mode Register */ - uint dsr; /* 0xd1464 - Doorbell Status Register */ - uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */ - uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */ - uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */ - uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */ - char res57[104]; - uint pwmr; /* 0xd14e0 - Port-Write Mode Register */ - uint pwsr; /* 0xd14e4 - Port-Write Status Register */ - uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */ - uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */ - char res58[60176]; + u32 didcar; /* Device Identity Capability */ + u32 dicar; /* Device Information Capability */ + u32 aidcar; /* Assembly Identity Capability */ + u32 aicar; /* Assembly Information Capability */ + u32 pefcar; /* Processing Element Features Capability */ + u32 spicar; /* Switch Port Information Capability */ + u32 socar; /* Source Operations Capability */ + u32 docar; /* Destination Operations Capability */ + u8 res1[32]; + u32 msr; /* Mailbox Cmd And Status */ + u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */ + u8 res2[4]; + u32 pellccsr; /* Processing Element Logic Layer CCSR */ + u8 res3[12]; + u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */ + u32 bdidcsr; /* Base Device ID Cmd & Status */ + u8 res4[4]; + u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */ + u32 ctcsr; /* Component Tag Cmd & Status */ + u8 res5[144]; + u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */ + u8 res6[28]; + u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */ + u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */ + u8 res7[20]; + u32 pgccsr; /* Port General Cmd & Status */ + u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */ + u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */ + u32 plascsr; /* Port Local Ackid Status Cmd & Status */ + u8 res8[12]; + u32 pescsr; /* Port Error & Status Cmd & Status */ + u32 pccsr; /* Port Control Cmd & Status */ + u8 res9[65184]; + u32 cr; /* Port Control Cmd & Status */ + u8 res10[12]; + u32 pcr; /* Port Configuration */ + u32 peir; /* Port Error Injection */ + u8 res11[3048]; + u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */ + u8 res12[12]; + u32 rowar0; /* RIO Outbound Attrs 0 */ + u8 res13[12]; + u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */ + u8 res14[4]; + u32 rowbar1; /* RIO Outbound Window Base Addr 1 */ + u8 res15[4]; + u32 rowar1; /* RIO Outbound Attrs 1 */ + u8 res16[12]; + u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */ + u8 res17[4]; + u32 rowbar2; /* RIO Outbound Window Base Addr 2 */ + u8 res18[4]; + u32 rowar2; /* RIO Outbound Attrs 2 */ + u8 res19[12]; + u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */ + u8 res20[4]; + u32 rowbar3; /* RIO Outbound Window Base Addr 3 */ + u8 res21[4]; + u32 rowar3; /* RIO Outbound Attrs 3 */ + u8 res22[12]; + u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */ + u8 res23[4]; + u32 rowbar4; /* RIO Outbound Window Base Addr 4 */ + u8 res24[4]; + u32 rowar4; /* RIO Outbound Attrs 4 */ + u8 res25[12]; + u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */ + u8 res26[4]; + u32 rowbar5; /* RIO Outbound Window Base Addr 5 */ + u8 res27[4]; + u32 rowar5; /* RIO Outbound Attrs 5 */ + u8 res28[12]; + u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */ + u8 res29[4]; + u32 rowbar6; /* RIO Outbound Window Base Addr 6 */ + u8 res30[4]; + u32 rowar6; /* RIO Outbound Attrs 6 */ + u8 res31[12]; + u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */ + u8 res32[4]; + u32 rowbar7; /* RIO Outbound Window Base Addr 7 */ + u8 res33[4]; + u32 rowar7; /* RIO Outbound Attrs 7 */ + u8 res34[12]; + u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */ + u8 res35[4]; + u32 rowbar8; /* RIO Outbound Window Base Addr 8 */ + u8 res36[4]; + u32 rowar8; /* RIO Outbound Attrs 8 */ + u8 res37[76]; + u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */ + u8 res38[4]; + u32 riwbar4; /* RIO Inbound Window Base Addr 4 */ + u8 res39[4]; + u32 riwar4; /* RIO Inbound Attrs 4 */ + u8 res40[12]; + u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */ + u8 res41[4]; + u32 riwbar3; /* RIO Inbound Window Base Addr 3 */ + u8 res42[4]; + u32 riwar3; /* RIO Inbound Attrs 3 */ + u8 res43[12]; + u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */ + u8 res44[4]; + u32 riwbar2; /* RIO Inbound Window Base Addr 2 */ + u8 res45[4]; + u32 riwar2; /* RIO Inbound Attrs 2 */ + u8 res46[12]; + u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */ + u8 res47[4]; + u32 riwbar1; /* RIO Inbound Window Base Addr 1 */ + u8 res48[4]; + u32 riwar1; /* RIO Inbound Attrs 1 */ + u8 res49[12]; + u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */ + u8 res50[12]; + u32 riwar0; /* RIO Inbound Attrs 0 */ + u8 res51[12]; + u32 pnfedr; /* Port Notification/Fatal Error Detect */ + u32 pnfedir; /* Port Notification/Fatal Error Detect */ + u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */ + u32 pecr; /* Port Error Control */ + u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */ + u32 pepr1; /* Port Error Packet 1 */ + u32 pepr2; /* Port Error Packet 2 */ + u8 res52[4]; + u32 predr; /* Port Recoverable Error Detect */ + u8 res53[4]; + u32 pertr; /* Port Error Recovery Threshold */ + u32 prtr; /* Port Retry Threshold */ + u8 res54[464]; + u32 omr; /* Outbound Mode */ + u32 osr; /* Outbound Status */ + u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */ + u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */ + u32 eosar; /* Extended Outbound Unit Source Addr */ + u32 osar; /* Outbound Unit Source Addr */ + u32 odpr; /* Outbound Destination Port */ + u32 odatr; /* Outbound Destination Attrs */ + u32 odcr; /* Outbound Doubleword Count */ + u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */ + u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */ + u8 res55[52]; + u32 imr; /* Outbound Mode */ + u32 isr; /* Inbound Status */ + u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */ + u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */ + u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */ + u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */ + u8 res56[1000]; + u32 dmr; /* Doorbell Mode */ + u32 dsr; /* Doorbell Status */ + u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */ + u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */ + u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */ + u32 dqhpar; /* Doorbell Queue Head Ptr Addr */ + u8 res57[104]; + u32 pwmr; /* Port-Write Mode */ + u32 pwsr; /* Port-Write Status */ + u32 epwqbar; /* Extended Port-Write Queue Base Addr */ + u32 pwqbar; /* Port-Write Queue Base Addr */ + u8 res58[60176]; } ccsr_rio_t; -/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */ +/* Quick Engine Block Pin Muxing Registers */ typedef struct par_io { - uint cpodr; /* 0x100 */ - uint cpdat; /* 0x104 */ - uint cpdir1; /* 0x108 */ - uint cpdir2; /* 0x10c */ - uint cppar1; /* 0x110 */ - uint cppar2; /* 0x114 */ - char res[8]; -}par_io_t; + u32 cpodr; + u32 cpdat; + u32 cpdir1; + u32 cpdir2; + u32 cppar1; + u32 cppar2; + u8 res[8]; +} par_io_t; -/* - * Global Utilities Register Block(0xe_0000-0xf_ffff) - */ +/* Global Utilities Block */ #ifdef CONFIG_FSL_CORENET typedef struct ccsr_gur { - u32 porsr1; /* 0xe0000 - POR status register */ - u8 res1[28]; /* 0xe0004 - 0xe001c Reserved: PORSRn */ - u32 gpporcr1; /* 0xe0020 - General-purpose POR configuration register */ + u32 porsr1; /* POR status */ + u8 res1[28]; + u32 gpporcr1; /* General-purpose POR configuration */ u8 res2[12]; - u32 gpiocr; /* 0xe0030 - GPIO control register */ + u32 gpiocr; /* GPIO control */ u8 res3[12]; - u32 gpoutdr; /* 0xe0040 - General-purpose output data register */ + u32 gpoutdr; /* General-purpose output data */ u8 res4[12]; - u32 gpindr; /* 0xe0050 - General-purpose input data register */ + u32 gpindr; /* General-purpose input data */ u8 res5[12]; - u32 pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ + u32 pmuxcr; /* Alt function signal multiplex control */ u8 res6[12]; - u32 devdisr; /* 0xe0070 - Device disable control */ + u32 devdisr; /* Device disable control */ #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 #define FSL_CORENET_DEVDISR_PCIE2 0x40000000 #define FSL_CORENET_DEVDISR_PCIE3 0x20000000 @@ -1606,157 +1584,157 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR_DUART1 0x00000002 #define FSL_CORENET_DEVDISR_DUART2 0x00000001 u8 res7[12]; - u32 powmgtcsr; /* 0xe0080 - Power management status and control register */ + u32 powmgtcsr; /* Power management status & control */ u8 res8[12]; - u32 coredisru; /* 0xe0090 - uppper portion for support of 64 cores */ - u32 coredisrl; /* 0xe0094 - lower portion for support of 64 cores */ + u32 coredisru; /* uppper portion for support of 64 cores */ + u32 coredisrl; /* lower portion for support of 64 cores */ u8 res9[8]; - u32 pvr; /* 0xe00a0 - Processor version register */ - u32 svr; /* 0xe00a4 - System version register */ + u32 pvr; /* Processor version */ + u32 svr; /* System version */ u8 res10[8]; - u32 rstcr; /* 0xe00b0 - Reset control register */ - u32 rstrqpblsr; /* 0xe00b4 - Reset request preboot loader status register */ + u32 rstcr; /* Reset control */ + u32 rstrqpblsr; /* Reset request preboot loader status */ u8 res11[8]; - u32 rstrqmr1; /* 0xe00c0 - Reset request mask register */ - u8 res12[4]; /* Reserved: RSTRQMR2 */ - u32 rstrqsr1; /* 0xe00c8 - Reset request status register */ - u8 res13[4]; /* Reserved: RSTRQSR2 */ - u8 res14[4]; /* Reserved: RSTRQWDTMRU */ - u32 rstrqwdtmrl; /* 0xe00d4 - Reset request WDT mask register */ - u8 res15[4]; /* Reserved: RSTRQWDTSRU */ - u32 rstrqwdtsrl; /* 0xe00dc - Reset request WDT status register */ - u8 res16[4]; /* Reserved: BRRU max total of 2 for up to 64 cores */ - u32 brrl; /* 0xe00e4 Boot release register */ + u32 rstrqmr1; /* Reset request mask */ + u8 res12[4]; + u32 rstrqsr1; /* Reset request status */ + u8 res13[4]; + u8 res14[4]; + u32 rstrqwdtmrl; /* Reset request WDT mask */ + u8 res15[4]; + u32 rstrqwdtsrl; /* Reset request WDT status */ + u8 res16[4]; + u32 brrl; /* Boot release */ u8 res17[24]; - u32 rcwsr[16]; /* 0xe0100 - 0xe013c: Reset control word status register */ + u32 rcwsr[16]; /* Reset control word status */ #define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000 #define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000 #define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000 #define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000 - u8 res18[192]; /* Reserved: RCWSRn (max total of 64)*/ - u32 scratchrw[4]; /* 0xe0200 - 0xe020c: Scratch Read/Write register */ - u8 res19[240]; /* Reserved: SCRATCHRWn (max total of 64)*/ - u32 scratchw1r[4]; /* 0xe0300 - 0xe030c: Scratch Read register (Write once) */ - u8 res20[240]; /* Reserved: SCRATCHW1Rn (max total of 64)*/ - u32 scrtsr[8]; /* 0xe0400 - 0xe041c: Core reset status register */ - u8 res21[224]; /* Reserved: CRSTSRn (max total of 64 for up to 64 cores)*/ - u32 pex1liodnr; /* 0xe0500 PCI Express 1 Logical I/O Device Number register*/ - u32 pex2liodnr; /* 0xe0504 PCI Express 2 Logical I/O Device Number register*/ - u32 pex3liodnr; /* 0xe0508 PCI Express 3 Logical I/O Device Number register*/ - u32 pex4liodnr; /* 0xe050c PCI Express 4 Logical I/O Device Number register*/ - u32 rio1liodnr; /* 0xe0510 RIO 1 Logical I/O Device Number register*/ - u32 rio2liodnr; /* 0xe0514 RIO 2 Logical I/O Device Number register*/ - u32 rio3liodnr; /* 0xe0518 RIO 3 Logical I/O Device Number register*/ - u32 rio4liodnr; /* 0xe051c RIO 4 Logical I/O Device Number register*/ - u32 usb1liodnr; /* 0xe0520 USB 1 Logical I/O Device Number register*/ - u32 usb2liodnr; /* 0xe0524 USB 2 Logical I/O Device Number register*/ - u32 usb3liodnr; /* 0xe0528 USB 3 Logical I/O Device Number register*/ - u32 usb4liodnr; /* 0xe052c USB 4 Logical I/O Device Number register*/ - u32 sdmmc1liodnr; /* 0xe0530 SD/MMC 1 Logical I/O Device Number register*/ - u32 sdmmc2liodnr; /* 0xe0534 SD/MMC 2 Logical I/O Device Number register*/ - u32 sdmmc3liodnr; /* 0xe0538 SD/MMC 3 Logical I/O Device Number register*/ - u32 sdmmc4liodnr; /* 0xe053c SD/MMC 4 Logical I/O Device Number register*/ - u32 rmuliodnr; /* 0xe0540 RIO Message Unit Logical I/O Device Number register*/ - u32 rduliodnr; /* 0xe0544 RIO Doorbell Unit Logical I/O Device Number register*/ - u32 rpwuliodnr; /* 0xe0548 RIO Port Write Unit Logical I/O Device Number register*/ - u8 res22[52]; /* Reserved: for future LIODN register expansion */ - u32 dma1liodnr; /* 0xe0580 DMA 1 Logical I/O Device Number register*/ - u32 dma2liodnr; /* 0xe0584 DMA 2 Logical I/O Device Number register*/ - u32 dma3liodnr; /* 0xe0588 DMA 3 Logical I/O Device Number register*/ - u32 dma4liodnr; /* 0xe058c DMA 4 Logical I/O Device Number register*/ - u8 res23[48]; /* Reserved: for future LIODN register expansion */ - u8 res24[64]; /* Reserved */ - u32 pblsr; /* 0xe0600 Preboot loader status register*/ - u32 pamubypenr; /* 0xe0604 PAMU bypass enable register*/ - u32 dmacr1; /* 0xe0608 DMA control register*/ - u8 res25[4]; /* Reserved: DMACR2 (max total of 2)*/ - u32 gensr1; /* 0xe0610 General status register*/ - u8 res26[12]; /* Reserved: GENSRn (max total of 4)*/ - u32 gencr1; /* 0xe0620 General control register*/ - u8 res27[12]; /* Reserved: GENCRn (max total of 4)*/ - u8 res28[4]; /* Reserved: CGENSRU (upper portion for support of 64 cores) */ - u32 cgensrl; /* 0xe0634 Core general status register*/ - u8 res29[8]; /* Reserved */ - u8 res30[4]; /* Reserved: CGENCRU (upper portion for support of 64 cores) */ - u32 cgencrl; /* 0xe0634 Core general control register*/ - u8 res31[184]; /* Reserved 0xe0648 - 0xe06fc */ - u32 sriopstecr; /* 0xe0700 SRIO prescaler timer enable control register*/ - u8 res32[2300]; /* Reserved 0xe0704 - 0xe0ffc */ + u8 res18[192]; + u32 scratchrw[4]; /* Scratch Read/Write */ + u8 res19[240]; + u32 scratchw1r[4]; /* Scratch Read (Write once) */ + u8 res20[240]; + u32 scrtsr[8]; /* Core reset status */ + u8 res21[224]; + u32 pex1liodnr; /* PCI Express 1 LIODN */ + u32 pex2liodnr; /* PCI Express 2 LIODN */ + u32 pex3liodnr; /* PCI Express 3 LIODN */ + u32 pex4liodnr; /* PCI Express 4 LIODN */ + u32 rio1liodnr; /* RIO 1 LIODN */ + u32 rio2liodnr; /* RIO 2 LIODN */ + u32 rio3liodnr; /* RIO 3 LIODN */ + u32 rio4liodnr; /* RIO 4 LIODN */ + u32 usb1liodnr; /* USB 1 LIODN */ + u32 usb2liodnr; /* USB 2 LIODN */ + u32 usb3liodnr; /* USB 3 LIODN */ + u32 usb4liodnr; /* USB 4 LIODN */ + u32 sdmmc1liodnr; /* SD/MMC 1 LIODN */ + u32 sdmmc2liodnr; /* SD/MMC 2 LIODN */ + u32 sdmmc3liodnr; /* SD/MMC 3 LIODN */ + u32 sdmmc4liodnr; /* SD/MMC 4 LIODN */ + u32 rmuliodnr; /* RIO Message Unit LIODN */ + u32 rduliodnr; /* RIO Doorbell Unit LIODN */ + u32 rpwuliodnr; /* RIO Port Write Unit LIODN */ + u8 res22[52]; + u32 dma1liodnr; /* DMA 1 LIODN */ + u32 dma2liodnr; /* DMA 2 LIODN */ + u32 dma3liodnr; /* DMA 3 LIODN */ + u32 dma4liodnr; /* DMA 4 LIODN */ + u8 res23[48]; + u8 res24[64]; + u32 pblsr; /* Preboot loader status */ + u32 pamubypenr; /* PAMU bypass enable */ + u32 dmacr1; /* DMA control */ + u8 res25[4]; + u32 gensr1; /* General status */ + u8 res26[12]; + u32 gencr1; /* General control */ + u8 res27[12]; + u8 res28[4]; + u32 cgensrl; /* Core general status */ + u8 res29[8]; + u8 res30[4]; + u32 cgencrl; /* Core general control */ + u8 res31[184]; + u32 sriopstecr; /* SRIO prescaler timer enable control */ + u8 res32[2300]; } ccsr_gur_t; typedef struct ccsr_clk { - u32 clkc0csr; /* 0xe1000 - Core 0 Clock control/status register */ - u8 res1[0x1c]; - u32 clkc1csr; /* 0xe1020 - Core 1 Clock control/status register */ - u8 res2[0x1c]; - u32 clkc2csr; /* 0xe1040 - Core 2 Clock control/status register */ - u8 res3[0x1c]; - u32 clkc3csr; /* 0xe1060 - Core 3 Clock control/status register */ - u8 res4[0x1c]; - u32 clkc4csr; /* 0xe1080 - Core 4 Clock control/status register */ - u8 res5[0x1c]; - u32 clkc5csr; /* 0xe10a0 - Core 5 Clock control/status register */ - u8 res6[0x1c]; - u32 clkc6csr; /* 0xe10c0 - Core 6 Clock control/status register */ - u8 res7[0x1c]; - u32 clkc7csr; /* 0xe10e0 - Core 7 Clock control/status register */ - u8 res8[0x71c]; - u32 pllc1gsr; /* 0xe1800 - Cluster PLL 1 General Status Register */ - u8 res10[0x1c]; - u32 pllc2gsr; /* 0xe1820 - Cluster PLL 2 General Status Register */ - u8 res11[0x1c]; - u32 pllc3gsr; /* 0xe1840 - Cluster PLL 3 General Status Register */ - u8 res12[0x1c]; - u32 pllc4gsr; /* 0xe1860 - Cluster PLL 4 General Status Register */ - u8 res13[0x39c]; - u32 pllpgsr; /* 0xe1c00 - Platform PLL General Status Register */ - u8 res14[0x1c]; - u32 plldgsr; /* 0xe1c20 - DDR PLL General Status Register */ - u8 res15[0x3dc]; + u32 clkc0csr; /* Core 0 Clock control/status */ + u8 res1[0x1c]; + u32 clkc1csr; /* Core 1 Clock control/status */ + u8 res2[0x1c]; + u32 clkc2csr; /* Core 2 Clock control/status */ + u8 res3[0x1c]; + u32 clkc3csr; /* Core 3 Clock control/status */ + u8 res4[0x1c]; + u32 clkc4csr; /* Core 4 Clock control/status */ + u8 res5[0x1c]; + u32 clkc5csr; /* Core 5 Clock control/status */ + u8 res6[0x1c]; + u32 clkc6csr; /* Core 6 Clock control/status */ + u8 res7[0x1c]; + u32 clkc7csr; /* Core 7 Clock control/status */ + u8 res8[0x71c]; + u32 pllc1gsr; /* Cluster PLL 1 General Status */ + u8 res10[0x1c]; + u32 pllc2gsr; /* Cluster PLL 2 General Status */ + u8 res11[0x1c]; + u32 pllc3gsr; /* Cluster PLL 3 General Status */ + u8 res12[0x1c]; + u32 pllc4gsr; /* Cluster PLL 4 General Status */ + u8 res13[0x39c]; + u32 pllpgsr; /* Platform PLL General Status */ + u8 res14[0x1c]; + u32 plldgsr; /* DDR PLL General Status */ + u8 res15[0x3dc]; } ccsr_clk_t; typedef struct ccsr_rcpm { - u8 res1[4]; /* 0xe2000 - Reserved */ - u32 cdozsrl; /* 0xe2004 - Core Doze Status Register */ - u8 res2[4]; /* 0xe2008 - Reserved */ - u32 cdozcrl; /* 0xe200c - Core Doze Control Register */ - u8 res3[4]; /* 0xe2010 - Reserved */ - u32 cnapsrl; /* 0xe2014 - Core Nap Status Register */ - u8 res4[4]; /* 0xe2018 - Reserved */ - u32 cnapcrl; /* 0xe201c - Core Nap Control Register */ - u8 res5[4]; /* 0xe2020 - Reserved */ - u32 cdozpsrl; /* 0xe2024 - Core Doze Previous Status Register */ - u8 res6[4]; /* 0xe2028 - Reserved */ - u32 cdozpcrl; /* 0xe202c - Core Doze Previous Control Register */ - u8 res7[4]; /* 0xe2030 - Reserved */ - u32 cwaitsrl; /* 0xe2034 - Core Wait Status Register */ - u8 res8[8]; /* Reserved */ - u32 powmgtcsr; /* 0xe2040 - Power Mangement Control & Status Register */ - u8 res9[12]; /* Reserved */ - u32 ippdexpcr0; /* 0xe2050 - IP Powerdown Exception Control Register 0 */ - u8 res10[12]; /* Reserved */ - u8 res11[4]; /* Reserved */ - u32 cpmimrl; /* 0xe2064 - Core Power Management Interrupt Masking Register */ - u8 res12[4]; /* Reserved */ - u32 cpmcimrl; /* 0xe206c - Core Power Management Critical Interrupt Masking Register */ - u8 res13[4]; /* Reserved */ - u32 cpmmcimrl; /* 0xe2074 - Core Power Management Machine Check Interrupt Masking Register */ - u8 res14[4]; /* Reserved */ - u32 cpmnmimrl; /* 0xe207c - Core Power Management NMI Masking Register */ - u8 res15[4]; /* Reserved */ - u32 ctbenrl; /* 0xe2084 - Core Time Base Enable Register */ - u8 res16[4]; /* Reserved */ - u32 ctbclkselrl; /* 0xe208c - Core Time Base Clock Select Register */ - u8 res17[4]; /* Reserved */ - u32 ctbhltcrl; /* 0xe2094 - Core Time Base Halt Control Register */ + u8 res1[4]; + u32 cdozsrl; /* Core Doze Status */ + u8 res2[4]; + u32 cdozcrl; /* Core Doze Control */ + u8 res3[4]; + u32 cnapsrl; /* Core Nap Status */ + u8 res4[4]; + u32 cnapcrl; /* Core Nap Control */ + u8 res5[4]; + u32 cdozpsrl; /* Core Doze Previous Status */ + u8 res6[4]; + u32 cdozpcrl; /* Core Doze Previous Control */ + u8 res7[4]; + u32 cwaitsrl; /* Core Wait Status */ + u8 res8[8]; + u32 powmgtcsr; /* Power Mangement Control & Status */ + u8 res9[12]; + u32 ippdexpcr0; /* IP Powerdown Exception Control 0 */ + u8 res10[12]; + u8 res11[4]; + u32 cpmimrl; /* Core PM IRQ Masking */ + u8 res12[4]; + u32 cpmcimrl; /* Core PM Critical IRQ Masking */ + u8 res13[4]; + u32 cpmmcimrl; /* Core PM Machine Check IRQ Masking */ + u8 res14[4]; + u32 cpmnmimrl; /* Core PM NMI Masking */ + u8 res15[4]; + u32 ctbenrl; /* Core Time Base Enable */ + u8 res16[4]; + u32 ctbclkselrl; /* Core Time Base Clock Select */ + u8 res17[4]; + u32 ctbhltcrl; /* Core Time Base Halt Control */ u8 res18[0xf68]; } ccsr_rcpm_t; #else typedef struct ccsr_gur { - uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ + u32 porpllsr; /* POR PLL ratio status */ #ifdef CONFIG_MPC8536 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 @@ -1767,17 +1745,17 @@ typedef struct ccsr_gur { #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT 25 #define MPC85xx_PORPLLSR_PLAT_RATIO 0x0000003e -#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 - uint porbmsr; /* 0xe0004 - POR boot mode status register */ +#define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT 1 + u32 porbmsr; /* POR boot mode status */ #define MPC85xx_PORBMSR_HA 0x00070000 #define MPC85xx_PORBMSR_HA_SHIFT 16 - uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ - uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ + u32 porimpscr; /* POR I/O impedance status & control */ + u32 pordevsr; /* POR I/O device status regsiter */ #define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 #define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 #define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 #define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 -#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 +#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 #define MPC85xx_PORDEVSR_PCI1 0x00800000 #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 @@ -1789,36 +1767,32 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 #define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 - uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ - uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ + u32 pordbgmsr; /* POR debug mode status */ + u32 pordevsr2; /* POR I/O device status 2 */ /* The 8544 RM says this is bit 26, but it's really bit 24 */ #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 - char res1[8]; - uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ - char res2[12]; - uint gpiocr; /* 0xe0030 - GPIO control register */ - char res3[12]; + u8 res1[8]; + u32 gpporcr; /* General-purpose POR configuration */ + u8 res2[12]; + u32 gpiocr; /* GPIO control */ + u8 res3[12]; #if defined(CONFIG_MPC8569) - uint plppar1; - /* 0xe0040 - Platform port pin assignment register 1 */ - uint plppar2; - /* 0xe0044 - Platform port pin assignment register 2 */ - uint plpdir1; - /* 0xe0048 - Platform port pin direction register 1 */ - uint plpdir2; - /* 0xe004c - Platform port pin direction register 2 */ + u32 plppar1; /* Platform port pin assignment 1 */ + u32 plppar2; /* Platform port pin assignment 2 */ + u32 plpdir1; /* Platform port pin direction 1 */ + u32 plpdir2; /* Platform port pin direction 2 */ #else - uint gpoutdr; /* 0xe0040 - General-purpose output data register */ - char res4[12]; + u32 gpoutdr; /* General-purpose output data */ + u8 res4[12]; #endif - uint gpindr; /* 0xe0050 - General-purpose input data register */ - char res5[12]; - uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ + u32 gpindr; /* General-purpose input data */ + u8 res5[12]; + u32 pmuxcr; /* Alt. function signal multiplex control */ #define MPC85xx_PMUXCR_SD_DATA 0x80000000 #define MPC85xx_PMUXCR_SDHC_CD 0x40000000 #define MPC85xx_PMUXCR_SDHC_WP 0x20000000 - char res6[12]; - uint devdisr; /* 0xe0070 - Device disable control */ + u8 res6[12]; + u32 devdisr; /* Device disable control */ #define MPC85xx_DEVDISR_PCI1 0x80000000 #define MPC85xx_DEVDISR_PCI2 0x40000000 #define MPC85xx_DEVDISR_PCIE 0x20000000 @@ -1842,34 +1816,34 @@ typedef struct ccsr_gur { #define MPC85xx_DEVDISR_TSEC4 0x00000010 #define MPC85xx_DEVDISR_I2C 0x00000004 #define MPC85xx_DEVDISR_DUART 0x00000002 - char res7[12]; - uint powmgtcsr; /* 0xe0080 - Power management status and control register */ - char res8[12]; - uint mcpsumr; /* 0xe0090 - Machine check summary register */ - char res9[12]; - uint pvr; /* 0xe00a0 - Processor version register */ - uint svr; /* 0xe00a4 - System version register */ - char res10a[8]; - uint rstcr; /* 0xe00b0 - Reset control register */ + u8 res7[12]; + u32 powmgtcsr; /* Power management status & control */ + u8 res8[12]; + u32 mcpsumr; /* Machine check summary */ + u8 res9[12]; + u32 pvr; /* Processor version */ + u32 svr; /* System version */ + u8 res10a[8]; + u32 rstcr; /* Reset control */ #if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) - char res10b[76]; - par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */ - char res10c[3136]; + u8 res10b[76]; + par_io_t qe_par_io[7]; + u8 res10c[3136]; #else - char res10b[3404]; + u8 res10b[3404]; #endif - uint clkocr; /* 0xe0e00 - Clock out select register */ - char res11[12]; - uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ - char res12[12]; - uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ - char res13[248]; - uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */ - uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */ - uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */ - uint tsec12ioovcr; /* 0xe0f28 - eTSEC 1/2 IO override control */ - uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */ - char res15[61648]; /* 0xe0f30 to 0xefffff */ + u32 clkocr; /* Clock out select */ + u8 res11[12]; + u32 ddrdllcr; /* DDR DLL control */ + u8 res12[12]; + u32 lbcdllcr; /* LBC DLL control */ + u8 res13[248]; + u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ + u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ + u32 ddrioovcr; /* DDR IO Override Control */ + u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */ + u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */ + u8 res15[61648]; } ccsr_gur_t; #endif @@ -1884,8 +1858,8 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 -#define CONFIG_SYS_MPC85xx_QMAN_OFFSET 0x318000 -#define CONFIG_SYS_MPC85xx_BMAN_OFFSET 0x31a000 +#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 +#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 #else #define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000 @@ -1899,6 +1873,7 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 #define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 #define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 +#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 @@ -1908,31 +1883,53 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 -#define CONFIG_SYS_MPC85xx_QMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_QMAN_OFFSET) -#define CONFIG_SYS_MPC85xx_BMAN_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_BMAN_OFFSET) -#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) -#define CONFIG_SYS_FSL_CORENET_CCM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) -#define CONFIG_SYS_FSL_CORENET_CLK_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) -#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) -#define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) -#define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) -#define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) -#define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) -#define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) -#define CONFIG_SYS_MPC85xx_GPIO_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) -#define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) -#define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) -#define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) -#define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) -#define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) -#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000 +#define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) +#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) +#define CONFIG_SYS_MPC85xx_GUTS_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) +#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) +#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) +#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) +#define CONFIG_SYS_MPC85xx_ECM_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) +#define CONFIG_SYS_MPC85xx_DDR_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) +#define CONFIG_SYS_MPC85xx_DDR2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) +#define CONFIG_SYS_MPC85xx_LBC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) +#define CONFIG_SYS_MPC85xx_ESPI_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) +#define CONFIG_SYS_MPC85xx_PCIX_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) +#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) +#define CONFIG_SYS_MPC85xx_GPIO_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) +#define CONFIG_SYS_MPC85xx_SATA1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) +#define CONFIG_SYS_MPC85xx_SATA2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) +#define CONFIG_SYS_MPC85xx_L2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) +#define CONFIG_SYS_MPC85xx_DMA_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) +#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) +#define CONFIG_SYS_MPC85xx_PIC_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) +#define CONFIG_SYS_MPC85xx_CPM_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) +#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) +#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) #endif /*__IMMAP_85xx__*/ -- cgit v1.2.3 From dd9ca98f2600000e5c2744735040100b770650e7 Mon Sep 17 00:00:00 2001 From: Paul Gortmaker Date: Fri, 25 Sep 2009 11:14:11 -0400 Subject: sbc8548: reclaim wasted sector in boot flash By nature of being based off the MPC8548CDS board, this board inherited an ENV_SIZE setting of 256k. But since it has a smaller flash device (8MB soldered on), it has a native sector size of 128k, and hence the ENV_SIZE was causing 2 sectors to be used for the environment. By removing the unused sector, we can push TEXT_BASE up closer to the end of address space and reclaim that sector for any other application. This also fixes the mismatch between TEXT_BASE and MONITOR_LEN reported by Kumar earlier. Since this board also supports the ability to boot off the 64MB SODIMM flash, this change is forward looking with that in mind; i.e. the settings for MONITOR_LEN and ENV_SIZE will work when the 512k sectors of the SODIMM flash are used for alternate boot in the future. Signed-off-by: Paul Gortmaker Signed-off-by: Kumar Gala --- include/configs/sbc8548.h | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index d10792a22da..aeac2dea3e4 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -330,7 +330,14 @@ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +/* + * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and + * one for env+bootpg (TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM + * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg + * (TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right + * thing for MONITOR_LEN in both cases. + */ +#define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1) #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* Serial Port */ @@ -448,9 +455,16 @@ * Environment */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #define CONFIG_ENV_SIZE 0x2000 +#if TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) +#define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ +#elif TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#else +#warning undefined environment size/location. +#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -- cgit v1.2.3 From 07355700523203c5f72018712cf0d93683f255c8 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Wed, 23 Sep 2009 15:19:32 +0800 Subject: mpc8536: fix board config file line length Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- include/configs/MPC8536DS.h | 147 ++++++++++++++++++++++++-------------------- 1 file changed, 79 insertions(+), 68 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index faca8059a1f..9d45648605b 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -86,8 +86,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ -#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ +#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ +#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* @@ -97,16 +97,16 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ #else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR #endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000) +#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) +#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) +#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000) /* DDR Setup */ #define CONFIG_VERY_BIG_RAM @@ -131,9 +131,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_SPD_BUS_NUM 1 /* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ +#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 @@ -145,7 +145,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ +#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ #define CONFIG_SYS_DDR_CONTROL2 0x04400010 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d @@ -190,21 +190,26 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) +#define CONFIG_SYS_BR0_PRELIM \ + (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ + | BR_PS_16 | BR_V) #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 -#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_BR1_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ + | BR_PS_16 | BR_V) #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ + CONFIG_SYS_FLASH_BASE_PHYS } #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ #undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ @@ -224,7 +229,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ +#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ #define PIXIS_ID 0x0 /* Board ID at offset 0 */ #define PIXIS_VER 0x1 /* Board version at offset 1 */ @@ -270,11 +275,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ #define CONFIG_SYS_NAND_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT @@ -293,42 +299,46 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2< " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) @@ -625,9 +635,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #else #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* @@ -635,7 +646,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * have to be in the first 16 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ /* * Internal Definitions @@ -671,7 +682,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_HOSTNAME unknown #define CONFIG_ROOTPATH /opt/nfsroot #define CONFIG_BOOTFILE uImage -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 -- cgit v1.2.3 From 9a1a0aedbbd56f901bfbc124f18ec6d9dcefe282 Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Wed, 23 Sep 2009 15:20:37 +0800 Subject: NAND boot: MPC8536DS support MPC8536E can support booting from NAND flash which uses the image u-boot-nand.bin. This image contains two parts: a 4K NAND loader and a main U-Boot image. The former is appended to the latter to produce u-boot-nand.bin. The 4K NAND loader includes the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. The main U-Boot image just like a general U-Boot image except the parts that included by CONFIG_SYS_RAMBOOT. When power on, eLBC will automatically load from bank 0 the 4K NAND loader into the FCM buffer RAM where CPU can execute the boot code directly. In the first stage, the NAND loader copies itself to RAM or L2SRAM to free up the FCM buffer RAM, then loads the main image from NAND flash to RAM or L2SRAM and boot from it. This patch implements the NAND loader to load the main image into L2SRAM, so the main image can configure the RAM by using SPD EEPROM. In the first stage, the NAND loader copies itself to the second to last 4K address space, and uses the last 4K address space as the initial RAM for stack. Obviously, the size of L2SRAM shouldn't be less than the size of the image used. If so, the workaround is to generate another image that includes the code to configure the RAM by SPD and load it to L2SRAM first, then relocate the main image to RAM to boot up. Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- include/configs/MPC8536DS.h | 95 ++++++++++++++++++++++++++++++++++++--------- 1 file changed, 77 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 9d45648605b..af369867b95 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -31,6 +31,12 @@ #define CONFIG_PHYS_64BIT 1 #endif +#ifdef CONFIG_MK_NAND +#define CONFIG_NAND_U_BOOT 1 +#define CONFIG_RAMBOOT_NAND 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -90,11 +96,22 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ #define CONFIG_PANIC_HANG /* do not reset board on panic */ +/* + * Config the L2 Cache as L2 SRAM + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull +#else +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#endif +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ @@ -103,6 +120,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR +#else +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#endif + #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000) @@ -190,10 +213,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_BR0_PRELIM \ +#define CONFIG_FLASH_BR_PRELIM \ (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 +#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 #define CONFIG_SYS_BR1_PRELIM \ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ @@ -213,6 +236,12 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_SYS_RAMBOOT +#else +#undef CONFIG_SYS_RAMBOOT +#endif + #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO @@ -265,6 +294,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define PIXIS_VWATCH 0x24 /* Watchdog Register */ #define PIXIS_LED 0x25 /* LED Register */ +#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ + /* old pixis referenced names */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ @@ -282,12 +313,21 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ +#ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull #else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif +#else +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#endif #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ CONFIG_SYS_NAND_BASE + 0x40000, \ CONFIG_SYS_NAND_BASE + 0x80000, \ @@ -298,6 +338,16 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +/* NAND boot: 4K NAND loader config */ +#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) +#define CONFIG_SYS_NAND_U_BOOT_START \ + (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) +#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) +#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) +#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) + /* NAND flash config */ #define CONFIG_NAND_BR_PRELIM \ (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ @@ -314,8 +364,17 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); | OR_FCM_TRLX \ | OR_FCM_EHTR) +#ifdef CONFIG_RAMBOOT_NAND +#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ +#else +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ +#endif #define CONFIG_SYS_BR4_PRELIM \ (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \ @@ -536,15 +595,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_EXT2 #endif -/* - * USB - */ -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI @@ -579,14 +629,23 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); /* * Environment */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 + +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE + #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#endif #else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #define CONFIG_ENV_IS_IN_FLASH 1 + #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 + #define CONFIG_ENV_ADDR 0xfff80000 + #else + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #endif + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -- cgit v1.2.3 From e40ac4870c6e72302044e98338322f45c34435bd Mon Sep 17 00:00:00 2001 From: Mingkai Hu Date: Wed, 23 Sep 2009 15:20:38 +0800 Subject: On-chip ROM boot: MPC8536DS support The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC and boot from eSPI. When power on, the porcessor excutes the ROM code to initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from the memory device that interfaced to the controller, such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it. The memory device should contain a specific data structure with control word and config word at the fixed address. The config word direct the process how to config the memory device, and the control word direct the processor where to find the image on the memory device, or where copy the main image to. The user can use any method to store the data structure to the memory device, only if store it on the assigned address. The on-chip ROM code will map the whole 4GB address space by setting entry0 in the TLB1, so the main image need to switch to Address space 1 to disable this mapping and map the address space again. This patch implements loading the mian U-Boot image into L2SRAM, so the image can configure the system memory by using SPD EEPROM. Signed-off-by: Mingkai Hu Signed-off-by: Kumar Gala --- include/configs/MPC8536DS.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index af369867b95..a8472754622 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -37,6 +37,16 @@ #define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000 #endif +#ifdef CONFIG_MK_SDCARD +#define CONFIG_RAMBOOT_SDCARD 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 +#endif + +#ifdef CONFIG_MK_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH 1 +#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000 +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -236,7 +246,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ -#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) +#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ + || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT #else #undef CONFIG_SYS_RAMBOOT @@ -635,6 +646,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_ENV_IS_IN_NAND 1 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) + #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) + #define CONFIG_ENV_SIZE 0x2000 #endif #else #define CONFIG_ENV_IS_IN_FLASH 1 -- cgit v1.2.3