From 9c4d8767ed672f995bf2d6b7cb2e83823bae9d76 Mon Sep 17 00:00:00 2001 From: Jerry Huang Date: Mon, 24 Jan 2011 17:09:53 +0000 Subject: powerpc/85xx: Add eSDHC support on P2020DS We enable SDHC_CD and SDHC_WP signals (pin muxed with GPIO8 & GPIO9 respectively). We enable EXT2, FAT, and parition support for both MMC & USB configs. Signed-off-by: Jerry Huang Signed-off-by: Jin Qing Signed-off-by: Kumar Gala --- include/configs/P2020DS.h | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index b32a9976f61..d4770f2774a 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -78,6 +78,8 @@ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ + #define CONFIG_ENABLE_36BIT_PHYS 1 #ifdef CONFIG_PHYS_64BIT @@ -605,14 +607,35 @@ /* * USB */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif #undef CONFIG_WATCHDOG /* watchdog disabled */ +/* + * SDHC/MMC + */ +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* * Miscellaneous configurable options */ -- cgit v1.3.1 From ccc4a8d89f8abcd30c25ac67a5aa5e57ac2eb515 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Mon, 24 Jan 2011 17:09:52 +0000 Subject: powerpc/85xx: Update P2020DS default env settings Read MAC address from EEPROM. Add hwconfig settings. Modified the default othbootargs to include the cache-sram-size parameter. This parameter is needed as the L2 as SRAM is ON by default in the P2020RDB kernel and used by the Gianfar driver. Also cleanup some of the boot commands. Signed-off-by: Li Yang Signed-off-by: Zhao Chenhui Signed-off-by: Kumar Gala --- include/configs/P2020DS.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index d4770f2774a..6648d6ea472 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -674,13 +674,8 @@ /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) #define CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:E0:0C:02:00:FD #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD #define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD -#define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD #endif #define CONFIG_IPADDR 192.168.1.254 @@ -703,8 +698,8 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ - "perf_mode=stable\0" \ - "memctl_intlv_ctl=2\0" \ + "perf_mode=performance\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ @@ -713,18 +708,25 @@ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ + "satabootcmd=setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p2020ds/ramdisk.uboot\0" \ "fdtaddr=c00000\0" \ + "othbootargs=cache-sram-size=0x10000\0" \ "fdtfile=p2020ds/p2020ds.dtb\0" \ - "bdev=sda3\0" + "bdev=sda3\0" \ + "partition=scsi 0:0\0" #define CONFIG_HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ + "ext2load $partition $loadaddr $bootfile;" \ + "ext2load $partition $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" #define CONFIG_NFSBOOTCOMMAND \ -- cgit v1.3.1 From 00203c64648bb2a7e20dac8cde850de6c1044db6 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 31 Jan 2011 15:57:01 -0600 Subject: powerpc/85xx: Remove config.mk for nand linker script Move the include of mpc85xx/u-boot-nand.lds to utilize CONFIG_SYS_LDSCRIPT rather than having an explicit config.mk Signed-off-by: Kumar Gala --- board/freescale/mpc8536ds/config.mk | 30 ------------------------------ board/freescale/mpc8569mds/config.mk | 30 ------------------------------ board/freescale/mpc8572ds/config.mk | 30 ------------------------------ board/freescale/p1_p2_rdb/config.mk | 31 ------------------------------- include/configs/MPC8536DS.h | 1 + include/configs/MPC8569MDS.h | 1 + include/configs/MPC8572DS.h | 1 + include/configs/P1_P2_RDB.h | 1 + 8 files changed, 4 insertions(+), 121 deletions(-) delete mode 100644 board/freescale/mpc8536ds/config.mk delete mode 100644 board/freescale/mpc8569mds/config.mk delete mode 100644 board/freescale/mpc8572ds/config.mk delete mode 100644 board/freescale/p1_p2_rdb/config.mk (limited to 'include') diff --git a/board/freescale/mpc8536ds/config.mk b/board/freescale/mpc8536ds/config.mk deleted file mode 100644 index 228d8c07f7e..00000000000 --- a/board/freescale/mpc8536ds/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2008, 2011 Freescale Semiconductor. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# mpc8536ds board -# -ifndef NAND_SPL -ifeq ($(CONFIG_NAND), y) -LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds -endif -endif diff --git a/board/freescale/mpc8569mds/config.mk b/board/freescale/mpc8569mds/config.mk deleted file mode 100644 index 54b2eb1ba1c..00000000000 --- a/board/freescale/mpc8569mds/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright (C) 2009 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# mpc8569mds board -# -ifndef NAND_SPL -ifeq ($(CONFIG_NAND), y) -LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds -endif -endif diff --git a/board/freescale/mpc8572ds/config.mk b/board/freescale/mpc8572ds/config.mk deleted file mode 100644 index 9fd30f9a089..00000000000 --- a/board/freescale/mpc8572ds/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# mpc8572ds board -# -ifndef NAND_SPL -ifeq ($(CONFIG_NAND), y) -LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds -endif -endif diff --git a/board/freescale/p1_p2_rdb/config.mk b/board/freescale/p1_p2_rdb/config.mk deleted file mode 100644 index 076980498cc..00000000000 --- a/board/freescale/p1_p2_rdb/config.mk +++ /dev/null @@ -1,31 +0,0 @@ -# -# Copyright 2009, 2011 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# p1_p2rdb board -# - -ifndef NAND_SPL -ifeq ($(CONFIG_NAND), y) -LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds -endif -endif diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 13300de3eac..333a1ea6ce3 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -40,6 +40,7 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 9e24e129072..b815ed0449b 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -72,6 +72,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif #endif diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index bf2fdd66820..4224229fcac 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -40,6 +40,7 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 95b85e3f657..b67f70f8541 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -50,6 +50,7 @@ #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif /* CONFIG_NAND_SPL */ #endif -- cgit v1.3.1 From 5df4b0ad0dff3cef1bd6660bcc8cba028c80adcb Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 31 Jan 2011 20:36:02 -0600 Subject: powerpc/8xxx: Replace fsl_ddr_get_mem_data_rate with get_ddr_freq() Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq() and every 86xx board uses get_bus_freq(). If implement get_ddr_freq() as a static inline to call get_bus_freq() we can remove fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq() directly. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 2 +- arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 1 - arch/powerpc/cpu/mpc8xxx/ddr/util.c | 6 ++---- board/freescale/corenet_ds/ddr.c | 5 ----- board/freescale/mpc8536ds/ddr.c | 5 ----- board/freescale/mpc8540ads/ddr.c | 8 -------- board/freescale/mpc8541cds/ddr.c | 5 ----- board/freescale/mpc8544ds/ddr.c | 5 ----- board/freescale/mpc8548cds/ddr.c | 5 ----- board/freescale/mpc8555cds/ddr.c | 5 ----- board/freescale/mpc8560ads/ddr.c | 8 -------- board/freescale/mpc8568mds/ddr.c | 6 ------ board/freescale/mpc8569mds/ddr.c | 6 ------ board/freescale/mpc8572ds/ddr.c | 5 ----- board/freescale/mpc8610hpcd/ddr.c | 5 ----- board/freescale/mpc8641hpcn/ddr.c | 7 +------ board/freescale/p1022ds/ddr.c | 5 ----- board/freescale/p2020ds/ddr.c | 5 ----- board/sbc8548/ddr.c | 5 ----- board/sbc8560/ddr.c | 8 -------- board/sbc8641d/ddr.c | 5 ----- board/socrates/ddr.c | 5 ----- board/stx/stxgp3/ddr.c | 8 -------- board/stx/stxssa/ddr.c | 8 -------- board/xes/xpedite517x/ddr.c | 7 +------ board/xes/xpedite520x/ddr.c | 5 ----- board/xes/xpedite537x/ddr.c | 5 ----- board/xes/xpedite550x/ddr.c | 5 ----- include/common.h | 4 ++++ 29 files changed, 9 insertions(+), 150 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c index cefabe769fb..ee7ef0f2141 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -236,7 +236,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, * tAXPD=1, need design to confirm. */ int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */ - unsigned int data_rate = fsl_ddr_get_mem_data_rate(); + unsigned int data_rate = get_ddr_freq(0); tmrd_mclk = 4; /* set the turnaround time */ trwt_mclk = 1; diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index c7c12c1c2f6..1e866fe0353 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -80,5 +80,4 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo); extern unsigned int mclk_to_picos(unsigned int mclk); extern unsigned int get_memory_clk_period_ps(void); extern unsigned int picos_to_mclk(unsigned int picos); -extern unsigned int fsl_ddr_get_mem_data_rate(void); #endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c index 1e2d921286e..815c5e3a9ef 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c @@ -11,8 +11,6 @@ #include "ddr.h" -unsigned int fsl_ddr_get_mem_data_rate(void); - /* * Round mclk_ps to nearest 10 ps in memory controller code. * @@ -24,7 +22,7 @@ unsigned int get_memory_clk_period_ps(void) { unsigned int mclk_ps; - mclk_ps = 2000000000000ULL / fsl_ddr_get_mem_data_rate(); + mclk_ps = 2000000000000ULL / get_ddr_freq(0); /* round to nearest 10 ps */ return 10 * ((mclk_ps + 5) / 10); } @@ -40,7 +38,7 @@ unsigned int picos_to_mclk(unsigned int picos) if (!picos) return 0; - clks = fsl_ddr_get_mem_data_rate() * (unsigned long long) picos; + clks = get_ddr_freq(0) * (unsigned long long) picos; clks_temp = clks; clks = clks / ULL_2e12; if (clks_temp % ULL_2e12) { diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index ee08abb29f7..d83b9bfb6c8 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -118,11 +118,6 @@ static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) } } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c index 2bad787d606..565e2132ae7 100644 --- a/board/freescale/mpc8536ds/ddr.c +++ b/board/freescale/mpc8536ds/ddr.c @@ -17,11 +17,6 @@ static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c index 93d1100717f..64a3ee15baa 100644 --- a/board/freescale/mpc8540ads/ddr.c +++ b/board/freescale/mpc8540ads/ddr.c @@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); } - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c index c84a6cbe1c7..ce08af112df 100644 --- a/board/freescale/mpc8541cds/ddr.c +++ b/board/freescale/mpc8541cds/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c index b8330eb961d..87f0a22bbe0 100644 --- a/board/freescale/mpc8544ds/ddr.c +++ b/board/freescale/mpc8544ds/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c index ab64fa88f26..bc6e71abc77 100644 --- a/board/freescale/mpc8548cds/ddr.c +++ b/board/freescale/mpc8548cds/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c index c84a6cbe1c7..ce08af112df 100644 --- a/board/freescale/mpc8555cds/ddr.c +++ b/board/freescale/mpc8555cds/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c index 93d1100717f..64a3ee15baa 100644 --- a/board/freescale/mpc8560ads/ddr.c +++ b/board/freescale/mpc8560ads/ddr.c @@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); } - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c index 482fd919f54..9a4c5c9ad39 100644 --- a/board/freescale/mpc8568mds/ddr.c +++ b/board/freescale/mpc8568mds/ddr.c @@ -18,12 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } - -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index e3f5b4aa21d..bedbedd4926 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -18,12 +18,6 @@ get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); } - -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c index cdde6ec70fc..52c7d734bfc 100644 --- a/board/freescale/mpc8572ds/ddr.c +++ b/board/freescale/mpc8572ds/ddr.c @@ -17,11 +17,6 @@ static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c index 0117d136bbb..5523c0e13b6 100644 --- a/board/freescale/mpc8610hpcd/ddr.c +++ b/board/freescale/mpc8610hpcd/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_bus_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index 8dc249b99dc..07bb92f769d 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_bus_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { @@ -144,7 +139,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, /* Get clk_adjust, cpo, write_data_delay, according to the board ddr * freqency and n_banks specified in board_specific_parameters table. */ - ddr_freq = fsl_ddr_get_mem_data_rate() / 1000000; + ddr_freq = get_ddr_freq(0) / 1000000; for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { if (pdimm[j].n_ranks > 0) { for (i = 0; i < num_params; i++) { diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c index 7ecfb3e81b5..80c1d63200e 100644 --- a/board/freescale/p1022ds/ddr.c +++ b/board/freescale/p1022ds/ddr.c @@ -15,11 +15,6 @@ #include #include -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { int ret; diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index 9a1b07554fe..b52582f6f63 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -17,11 +17,6 @@ static void get_spd(generic_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index ab64fa88f26..bc6e71abc77 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/sbc8560/ddr.c b/board/sbc8560/ddr.c index 7850794d64f..f7e956afb44 100644 --- a/board/sbc8560/ddr.c +++ b/board/sbc8560/ddr.c @@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); } - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c index 23497f98258..bed94bf3189 100644 --- a/board/sbc8641d/ddr.c +++ b/board/sbc8641d/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_bus_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c index 2b62b847054..455832618b8 100644 --- a/board/socrates/ddr.c +++ b/board/socrates/ddr.c @@ -18,11 +18,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c index 93d1100717f..64a3ee15baa 100644 --- a/board/stx/stxgp3/ddr.c +++ b/board/stx/stxgp3/ddr.c @@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); } - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c index 93d1100717f..64a3ee15baa 100644 --- a/board/stx/stxssa/ddr.c +++ b/board/stx/stxssa/ddr.c @@ -18,14 +18,6 @@ get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); } - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c index 1d57d0909a6..981bf41e096 100644 --- a/board/xes/xpedite517x/ddr.c +++ b/board/xes/xpedite517x/ddr.c @@ -32,11 +32,6 @@ static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_bus_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { @@ -144,7 +139,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, unsigned int datarate; get_sys_info(&sysinfo); - datarate = fsl_ddr_get_mem_data_rate() / 1000000; + datarate = get_ddr_freq(0) / 1000000; for (i = 0; i < ARRAY_SIZE(bopts_ctrl[ctrl_num]); i++) { if ((bopts[i].datarate_mhz_low <= datarate) && diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c index c5616d546b8..f8d945ace3f 100644 --- a/board/xes/xpedite520x/ddr.c +++ b/board/xes/xpedite520x/ddr.c @@ -27,11 +27,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) } } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c index 4d3f255d705..307f875db9b 100644 --- a/board/xes/xpedite537x/ddr.c +++ b/board/xes/xpedite537x/ddr.c @@ -33,11 +33,6 @@ static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) sizeof(ddr2_spd_eeprom_t)); } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c index 38a459715fd..9e6964960c3 100644 --- a/board/xes/xpedite550x/ddr.c +++ b/board/xes/xpedite550x/ddr.c @@ -46,11 +46,6 @@ void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, } } -unsigned int fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - /* * There are traditionally three board-specific SDRAM timing parameters * which must be calculated based on the particular PCB artwork. These are: diff --git a/include/common.h b/include/common.h index 893af5cc10e..54503ed3eba 100644 --- a/include/common.h +++ b/include/common.h @@ -538,6 +538,10 @@ ulong get_ddr_freq (ulong); #if defined(CONFIG_MPC86xx) typedef MPC86xx_SYS_INFO sys_info_t; void get_sys_info ( sys_info_t * ); +static inline ulong get_ddr_freq(ulong dummy) +{ + return get_bus_freq(dummy); +} #endif #if defined(CONFIG_4xx) || defined(CONFIG_IOP480) -- cgit v1.3.1 From c39f44dc6f5ae843d5def511f6e71d4b012dc598 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 31 Jan 2011 22:18:47 -0600 Subject: powerpc/8xxx: Refactor fsl_ddr_get_spd into common code from board Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/ddr/main.c | 63 +++++++++++++++++++++++++++++++++++-- board/freescale/corenet_ds/ddr.c | 27 ---------------- board/freescale/mpc8536ds/ddr.c | 21 ------------- board/freescale/mpc8540ads/ddr.c | 22 ------------- board/freescale/mpc8541cds/ddr.c | 21 ------------- board/freescale/mpc8544ds/ddr.c | 22 ------------- board/freescale/mpc8548cds/ddr.c | 22 ------------- board/freescale/mpc8555cds/ddr.c | 21 ------------- board/freescale/mpc8560ads/ddr.c | 22 ------------- board/freescale/mpc8568mds/ddr.c | 22 ------------- board/freescale/mpc8569mds/ddr.c | 22 ------------- board/freescale/mpc8572ds/ddr.c | 23 -------------- board/freescale/mpc8610hpcd/ddr.c | 21 ------------- board/freescale/mpc8641hpcn/ddr.c | 30 ------------------ board/freescale/p1022ds/ddr.c | 18 ----------- board/freescale/p2020ds/ddr.c | 19 ----------- board/sbc8548/ddr.c | 22 ------------- board/sbc8560/ddr.c | 22 ------------- board/sbc8641d/ddr.c | 30 ------------------ board/socrates/ddr.c | 22 ------------- board/stx/stxgp3/ddr.c | 22 ------------- board/stx/stxssa/ddr.c | 21 ------------- board/xes/xpedite517x/ddr.c | 25 +-------------- board/xes/xpedite520x/ddr.c | 17 +--------- board/xes/xpedite537x/ddr.c | 17 +--------- board/xes/xpedite550x/ddr.c | 15 +-------- include/configs/MPC8569MDS.h | 3 +- include/configs/MPC8610HPCD.h | 2 +- include/configs/P1022DS.h | 2 +- include/configs/P2020DS.h | 2 +- include/configs/xpedite550x.h | 2 +- 31 files changed, 69 insertions(+), 551 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index bb96d66a9df..c8fa123539d 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -13,6 +13,7 @@ */ #include +#include #include #include "ddr.h" @@ -26,9 +27,65 @@ extern void fsl_ddr_set_lawbar( extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num); -/* Board-specific functions defined in each board's ddr.c */ -extern void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num); +#if defined(SPD_EEPROM_ADDRESS) || \ + defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \ + defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4) +#if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS, +}; +#endif +#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS2, /* controller 2 */ +}; +#endif +#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2) +u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = { + [0][0] = SPD_EEPROM_ADDRESS1, /* controller 1 */ + [0][1] = SPD_EEPROM_ADDRESS2, /* controller 1 */ + [1][0] = SPD_EEPROM_ADDRESS3, /* controller 2 */ + [1][1] = SPD_EEPROM_ADDRESS4, /* controller 2 */ +}; +#endif + +static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) +{ + int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, + sizeof(generic_spd_eeprom_t)); + + if (ret) { + printf("DDR: failed to read SPD from address %u\n", i2c_address); + memset(spd, 0, sizeof(generic_spd_eeprom_t)); + } +} + +__attribute__((weak, alias("__get_spd"))) +void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address); + +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ + unsigned int i; + unsigned int i2c_address = 0; + + if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } + + for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { + i2c_address = spd_i2c_addr[ctrl_num][i]; + get_spd(&(ctrl_dimms_spd[i]), i2c_address); + } +} +#else +void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, + unsigned int ctrl_num) +{ +} +#endif /* SPD_EEPROM_ADDRESSx */ /* * ASSUMPTIONS: diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index d83b9bfb6c8..98024c72d7f 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -107,33 +107,6 @@ phys_size_t fixed_sdram(void) return ddr_size; } -static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) -{ - int ret; - - ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); - if (ret) { - debug("DDR: failed to read SPD from address %u\n", i2c_address); - memset(spd, 0, sizeof(ddr3_spd_eeprom_t)); - } -} - -void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) - i2c_address = SPD_EEPROM_ADDRESS1; - else if (ctrl_num == 1 && i == 0) - i2c_address = SPD_EEPROM_ADDRESS2; - - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - typedef struct { u32 datarate_mhz_low; u32 datarate_mhz_high; diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c index 565e2132ae7..d10370c9f20 100644 --- a/board/freescale/mpc8536ds/ddr.c +++ b/board/freescale/mpc8536ds/ddr.c @@ -7,31 +7,10 @@ */ #include -#include #include #include -static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c index 64a3ee15baa..571137443eb 100644 --- a/board/freescale/mpc8540ads/ddr.c +++ b/board/freescale/mpc8540ads/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c index ce08af112df..78d73b0ea88 100644 --- a/board/freescale/mpc8541cds/ddr.c +++ b/board/freescale/mpc8541cds/ddr.c @@ -7,31 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c index 87f0a22bbe0..94219b9471e 100644 --- a/board/freescale/mpc8544ds/ddr.c +++ b/board/freescale/mpc8544ds/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c index bc6e71abc77..996ffe206da 100644 --- a/board/freescale/mpc8548cds/ddr.c +++ b/board/freescale/mpc8548cds/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c index ce08af112df..78d73b0ea88 100644 --- a/board/freescale/mpc8555cds/ddr.c +++ b/board/freescale/mpc8555cds/ddr.c @@ -7,31 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c index 64a3ee15baa..571137443eb 100644 --- a/board/freescale/mpc8560ads/ddr.c +++ b/board/freescale/mpc8560ads/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c index 9a4c5c9ad39..b1f4f1f8481 100644 --- a/board/freescale/mpc8568mds/ddr.c +++ b/board/freescale/mpc8568mds/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c index bedbedd4926..68f686b7e6a 100644 --- a/board/freescale/mpc8569mds/ddr.c +++ b/board/freescale/mpc8569mds/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) - i2c_address = SPD_EEPROM_ADDRESS1; - if (ctrl_num == 0 && i == 1) - i2c_address = SPD_EEPROM_ADDRESS2; - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c index 52c7d734bfc..ab471afb977 100644 --- a/board/freescale/mpc8572ds/ddr.c +++ b/board/freescale/mpc8572ds/ddr.c @@ -7,33 +7,10 @@ */ #include -#include #include #include -static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS1; - } - if (ctrl_num == 1 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS2; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - typedef struct { u32 datarate_mhz_low; u32 datarate_mhz_high; diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c index 5523c0e13b6..94219b9471e 100644 --- a/board/freescale/mpc8610hpcd/ddr.c +++ b/board/freescale/mpc8610hpcd/ddr.c @@ -7,31 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS1; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c index 07bb92f769d..bd0b299d0b4 100644 --- a/board/freescale/mpc8641hpcn/ddr.c +++ b/board/freescale/mpc8641hpcn/ddr.c @@ -7,40 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS1; - } - if (ctrl_num == 0 && i == 1) { - i2c_address = SPD_EEPROM_ADDRESS2; - } - if (ctrl_num == 1 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS3; - } - if (ctrl_num == 1 && i == 1) { - i2c_address = SPD_EEPROM_ADDRESS4; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - typedef struct { u32 datarate_mhz_low; u32 datarate_mhz_high; diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c index 80c1d63200e..20b996e52a9 100644 --- a/board/freescale/p1022ds/ddr.c +++ b/board/freescale/p1022ds/ddr.c @@ -10,28 +10,10 @@ */ #include -#include #include #include -void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) -{ - int ret; - - /* - * The P1022 has only one DDR controller, and the board has only one - * DIMM slot. - */ - ret = i2c_read(SPD_EEPROM_ADDRESS1, 0, 1, (u8 *)ctrl_dimms_spd, - sizeof(ddr3_spd_eeprom_t)); - if (ret) { - debug("DDR: failed to read SPD from address %u\n", - SPD_EEPROM_ADDRESS1); - memset(ctrl_dimms_spd, 0, sizeof(ddr3_spd_eeprom_t)); - } -} - typedef struct { u32 datarate_mhz_low; u32 datarate_mhz_high; diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index b52582f6f63..9bf7d2f587a 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -7,29 +7,10 @@ */ #include -#include #include #include -static void get_spd(generic_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) - i2c_address = SPD_EEPROM_ADDRESS1; - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - typedef struct { u32 datarate_mhz_low; u32 datarate_mhz_high; diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index bc6e71abc77..996ffe206da 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/sbc8560/ddr.c b/board/sbc8560/ddr.c index f7e956afb44..e9babc6477e 100644 --- a/board/sbc8560/ddr.c +++ b/board/sbc8560/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c index bed94bf3189..996ffe206da 100644 --- a/board/sbc8641d/ddr.c +++ b/board/sbc8641d/ddr.c @@ -7,40 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS1; - } - if (ctrl_num == 0 && i == 1) { - i2c_address = SPD_EEPROM_ADDRESS2; - } - if (ctrl_num == 1 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS3; - } - if (ctrl_num == 1 && i == 1) { - i2c_address = SPD_EEPROM_ADDRESS4; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c index 455832618b8..e9db476f483 100644 --- a/board/socrates/ddr.c +++ b/board/socrates/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); -} - -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c index 64a3ee15baa..571137443eb 100644 --- a/board/stx/stxgp3/ddr.c +++ b/board/stx/stxgp3/ddr.c @@ -7,32 +7,10 @@ */ #include -#include #include #include -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c index 64a3ee15baa..56c87b2fc6b 100644 --- a/board/stx/stxssa/ddr.c +++ b/board/stx/stxssa/ddr.c @@ -12,27 +12,6 @@ #include #include -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c index 981bf41e096..3a6e297f457 100644 --- a/board/xes/xpedite517x/ddr.c +++ b/board/xes/xpedite517x/ddr.c @@ -26,35 +26,12 @@ #include #include -static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address) { i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0) { - i2c_address = SPD_EEPROM_ADDRESS1; -#ifdef SPD_EEPROM_ADDRESS2 - } else if (ctrl_num == 1) { - i2c_address = SPD_EEPROM_ADDRESS2; -#endif - } else { - /* An inalid ctrl number was give, use default SPD */ - printf("ERROR: invalid DDR ctrl: %d\n", ctrl_num); - i2c_address = SPD_EEPROM_ADDRESS1; - } - - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - /* * There are four board-specific SDRAM timing parameters which must be * calculated based on the particular PCB artwork. These are: diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c index f8d945ace3f..3671cb8af9a 100644 --- a/board/xes/xpedite520x/ddr.c +++ b/board/xes/xpedite520x/ddr.c @@ -12,8 +12,7 @@ #include #include -static void -get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) { i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); @@ -27,20 +26,6 @@ get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) } } -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - - if (ctrl_num) { - printf("%s: invalid ctrl_num = %d\n", __func__, ctrl_num); - return; - } - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) - get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); -} - void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, unsigned int ctrl_num) diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c index 307f875db9b..d0662b0c57d 100644 --- a/board/xes/xpedite537x/ddr.c +++ b/board/xes/xpedite537x/ddr.c @@ -27,27 +27,12 @@ #include #include -static void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) +void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address) { i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); } -void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0) - i2c_address = SPD_EEPROM_ADDRESS1; - if (ctrl_num == 1) - i2c_address = SPD_EEPROM_ADDRESS2; - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - /* * There are four board-specific SDRAM timing parameters which must be * calculated based on the particular PCB artwork. These are: diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c index 9e6964960c3..3b6e08bfcdd 100644 --- a/board/xes/xpedite550x/ddr.c +++ b/board/xes/xpedite550x/ddr.c @@ -27,25 +27,12 @@ #include #include -static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address) +void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address) { i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd, sizeof(ddr3_spd_eeprom_t)); } -void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) - i2c_address = SPD_EEPROM_ADDRESS1; - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - /* * There are traditionally three board-specific SDRAM timing parameters * which must be calculated based on the particular PCB artwork. These are: diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index b815ed0449b..5f804254fd0 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -139,8 +139,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) /* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ -#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* These are used when DDR doesn't use SPD. */ #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 03ee394b398..7b25e071b75 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -108,7 +108,7 @@ #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* These are used when DDR doesn't use SPD. */ #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 84b7e1d22eb..5f47d1a7a94 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -87,7 +87,7 @@ /* I2C addresses of SPD EEPROMs */ #define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* * Memory map diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 6648d6ea472..1815191f592 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -130,7 +130,7 @@ /* I2C addresses of SPD EEPROMs */ #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* These are used when DDR doesn't use SPD. */ #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ diff --git a/include/configs/xpedite550x.h b/include/configs/xpedite550x.h index a051913ffb2..17aab5a7bbf 100644 --- a/include/configs/xpedite550x.h +++ b/include/configs/xpedite550x.h @@ -67,7 +67,7 @@ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD #define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#define SPD_EEPROM_ADDRESS1 0x54 +#define SPD_EEPROM_ADDRESS 0x54 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 -- cgit v1.3.1 From 24995d829aecc6abca0f1b41443ae0cd9b4fde5a Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Thu, 20 Jan 2011 22:26:31 +0000 Subject: powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs There are some differences between CoreNet (P2040, P3041, P5020, P4080) and and non-CoreNet (P1017, P1023) based SoCs in what features exist and the memory maps. * Rename various immap defines to remove _CORENET_ if they are shared * Added P1023/P1017 specific memory offsets * Only setup LIODNs or LIODN related code on CORENET based SoCs (features doesn't exist on P1023/P1017) Signed-off-by: Haiying Wang Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/Makefile | 2 +- arch/powerpc/cpu/mpc85xx/portals.c | 32 +++++++++++++++++++++++--------- arch/powerpc/cpu/mpc85xx/speed.c | 10 +++++++++- arch/powerpc/include/asm/fsl_liodn.h | 10 +++++----- arch/powerpc/include/asm/immap_85xx.h | 12 ++++++------ include/configs/corenet_ds.h | 1 + 6 files changed, 45 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index cc16db350df..5791be019d6 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -69,7 +69,7 @@ COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS-$(CONFIG_FSL_CORENET) += liodn.o COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_PCI) += pci.o -COBJS-$(CONFIG_FSL_CORENET) += portals.o +COBJS-$(CONFIG_SYS_DPAA_QBMAN) += portals.o # various SoC specific assignments COBJS-$(CONFIG_PPC_P3041) += p3041_ids.o diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index 01aec6e794e..e8d53bb2fd0 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -30,18 +30,13 @@ #include #include -static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_CORENET_QMAN_ADDR; +static ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; void setup_portals(void) { +#ifdef CONFIG_FSL_CORENET int i; - /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ -#ifdef CONFIG_PHYS_64BIT - out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); -#endif - out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); - for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) { u8 sdest = qp_info[i].sdest; u16 fliodn = qp_info[i].fliodn; @@ -53,6 +48,13 @@ void setup_portals(void) /* set frame liodn */ out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn); } +#endif + + /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ +#ifdef CONFIG_PHYS_64BIT + out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32)); +#endif + out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS); } /* Update portal containter to match LAW setup of portal in phy map */ @@ -118,9 +120,12 @@ void fdt_portal(void *blob, const char *compat, const char *container, static int fdt_qportal(void *blob, int off, int id, char *name, enum fsl_dpaa_dev dev, int create) { - int childoff, dev_off, num, ret = 0; + int childoff, dev_off, ret = 0; uint32_t dev_handle; +#ifdef CONFIG_FSL_CORENET + int num; u32 liodns[2]; +#endif childoff = fdt_subnode_offset(blob, off, name); if (create) { @@ -154,9 +159,11 @@ static int fdt_qportal(void *blob, int off, int id, char *name, if (ret < 0) return ret; +#ifdef CONFIG_FSL_CORENET num = get_dpaa_liodn(dev, &liodns[0], id); ret = fdt_setprop(blob, childoff, "fsl,liodn", &liodns[0], sizeof(u32) * num); +#endif } else { return childoff; } @@ -184,7 +191,9 @@ void fdt_fixup_qportals(void *blob) off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal"); while (off != -FDT_ERR_NOTFOUND) { +#ifdef CONFIG_FSL_CORENET u32 liodns[2]; +#endif const int *ci = fdt_getprop(blob, off, "cell-index", NULL); int j, i = *ci; @@ -192,6 +201,7 @@ void fdt_fixup_qportals(void *blob) if (err < 0) goto err; +#ifdef CONFIG_FSL_CORENET liodns[0] = qp_info[i].dliodn; liodns[1] = qp_info[i].fliodn; @@ -199,6 +209,7 @@ void fdt_fixup_qportals(void *blob) &liodns, sizeof(u32) * 2); if (err < 0) goto err; +#endif i++; @@ -207,6 +218,7 @@ void fdt_fixup_qportals(void *blob) if (err < 0) goto err; +#ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_DPAA_PME err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1); if (err < 0) @@ -214,6 +226,8 @@ void fdt_fixup_qportals(void *blob) #else fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0); #endif +#endif + #ifdef CONFIG_SYS_DPAA_FMAN for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) { char name[] = "fman@0"; diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index f2aa8d039d6..9d749c33304 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -162,7 +162,6 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ; } #endif -#endif #ifdef CONFIG_QE qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO) @@ -170,6 +169,15 @@ void get_sys_info (sys_info_t * sysInfo) sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ; #endif +#ifdef CONFIG_SYS_DPAA_FMAN + sysInfo->freqFMan[0] = sysInfo->freqSystemBus / 2; +#if (CONFIG_SYS_NUM_FMAN) == 2 + sysInfo->freqFMan[1] = sysInfo->freqSystemBus / 2; +#endif +#endif + +#endif /* CONFIG_FSL_CORENET */ + #if defined(CONFIG_FSL_LBC) #if defined(CONFIG_SYS_LBC_LCRR) /* We will program LCRR to this value later */ diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 4c17fe232e6..f76676cb001 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -1,5 +1,5 @@ /* - * Copyright 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -85,13 +85,13 @@ extern void fdt_fixup_liodn(void *blob); #define SET_QMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \ - CONFIG_SYS_FSL_CORENET_QMAN_OFFSET, \ - CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) + CONFIG_SYS_FSL_QMAN_OFFSET, \ + CONFIG_SYS_FSL_QMAN_OFFSET) #define SET_BMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \ - CONFIG_SYS_FSL_CORENET_BMAN_OFFSET, \ - CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) + CONFIG_SYS_FSL_BMAN_OFFSET, \ + CONFIG_SYS_FSL_BMAN_OFFSET) #define SET_PME_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index ce27fece02e..d26d648b139 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2204,8 +2204,8 @@ typedef struct ccsr_pme { #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 -#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000 -#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000 +#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 +#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 #define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 @@ -2268,10 +2268,10 @@ typedef struct ccsr_pme { #define CONFIG_SYS_FSL_CPC_ADDR \ (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) -#define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET) -#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET) +#define CONFIG_SYS_FSL_QMAN_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) +#define CONFIG_SYS_FSL_BMAN_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET) #define CONFIG_SYS_FSL_CORENET_PME_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index bff212e40d7..7bafa05b199 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -357,6 +357,7 @@ #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT -- cgit v1.3.1 From 09f9ee1695136045f293dacda915d94c2891d4f0 Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Mon, 7 Feb 2011 15:08:29 +0530 Subject: powerpc/85xx: Use BR_PHYS_ADDR macro to setup BRs on P1_P2_RDB Signed-off-by: Poonam Aggrwal Signed-off-by: Kumar Gala --- include/configs/P1_P2_RDB.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index b67f70f8541..a217bcd08c6 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -264,7 +264,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ +#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2< Date: Tue, 8 Feb 2011 13:13:15 +0530 Subject: powerpc/85xx: Use DDR for RAMBOOT instead of L2 SRAM on p1_p2_rdb Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash boot loaders because: - P1_P2_RDB boards have soldered DDR so no need for SPD - Also P102x has 256K L2 cache size so becomes a limiting factor for size of image that could be loaded in SRAM mode and would require three stage boot loader (TPL). Changes done: 1. CONFIG_SYS_TEXT_BASE to 0x11000000 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc Signed-off-by: Priyanka Jain Signed-off-by: Poonam Aggrwal Signed-off-by: Dipen Dudhat Signed-off-by: Kumar Gala --- board/freescale/p1_p2_rdb/ddr.c | 15 +++++++++++---- board/freescale/p1_p2_rdb/tlb.c | 13 ++++--------- include/configs/P1_P2_RDB.h | 8 ++++---- 3 files changed, 19 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 44faec3a0be..853044e1cfa 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -202,6 +202,17 @@ phys_size_t fixed_sdram (void) struct cpu_type *cpu; ulong ddr_freq, ddr_freq_mhz; + cpu = gd->cpu; + /* P1020 and it's derivatives support max 32bit DDR width */ + if (cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || + cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { + ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); + } else { + ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + } +#if defined(CONFIG_SYS_RAMBOOT) + return ddr_size; +#endif ddr_freq = get_ddr_freq(0); ddr_freq_mhz = ddr_freq / 1000000; @@ -220,16 +231,12 @@ phys_size_t fixed_sdram (void) panic("Unsupported DDR data rate %s MT/s data rate\n", strmhz(buf, ddr_freq)); - cpu = gd->cpu; /* P1020 and it's derivatives support max 32bit DDR width */ if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E || cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) { ddr_cfg_regs.ddr_sdram_cfg |= SDRAM_CFG_32_BE; ddr_cfg_regs.cs[0].bnds = 0x0000001F; - ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2); } - else - ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index a46b1b5670a..9b166b2151c 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -80,15 +80,10 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_1M, 1), -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) - /* *I*G - L2SRAM */ - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256K, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, - CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256K, 1), +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_1G, 1) #endif }; diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index a217bcd08c6..53ec56f211e 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -57,14 +57,14 @@ #ifdef CONFIG_SDCARD #define CONFIG_RAMBOOT_SDCARD 1 -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH 1 -#define CONFIG_SYS_TEXT_BASE 0xf8f80000 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc #endif #ifndef CONFIG_SYS_TEXT_BASE -- cgit v1.3.1 From cac29f25fdda1fcbc962629825d309da87618faf Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Tue, 8 Feb 2011 13:18:34 +0530 Subject: powerpc/85xx: Read board switch settings on p1_p2_rdb PCA9557 is parallel I/O expansion device on I2C bus which stores various board switch settings like NOR Flash-Bank selection, SD Data width. On board: switch SW5[6] is to select width for eSDHC ON - 4-bit [Enable eSPI] OFF - 8-bit [Disable eSPI] switch SW4[8] is to select NOR Flash Bank for Booting OFF - Primary Bank ON - Secondary Bank Read board switch settings on p1_p2_rdb and configure corresponding eSDHC width. Signed-off-by: Priyanka Jain Signed-off-by: Dipen Dudhat Signed-off-by: Kumar Gala --- board/freescale/p1_p2_rdb/p1_p2_rdb.c | 25 +++++++++++++++++++++++++ include/configs/P1_P2_RDB.h | 2 ++ 2 files changed, 27 insertions(+) (limited to 'include') diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index 806d90e6e48..9f57a21925f 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -35,6 +35,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -142,6 +143,30 @@ int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + unsigned int orig_bus = i2c_get_bus_num(); + u8 i2c_data; + + i2c_set_bus_num(1); + if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0, + 1, &i2c_data, sizeof(i2c_data)) == 0) { + if (i2c_data & 0x2) + puts("NOR Flash Bank : Secondary\n"); + else + puts("NOR Flash Bank : Primary\n"); + + if (i2c_data & 0x1) { + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); + puts("SD/MMC : 8-bit Mode\n"); + puts("eSPI : Disabled\n"); + } else { + puts("SD/MMC : 4-bit Mode\n"); + puts("eSPI : Enabled\n"); + } + } else { + puts("Failed reading I2C Chip 0x18 on bus 1\n"); + } + i2c_set_bus_num(orig_bus); /* * Remap Boot flash region to caching-inhibited diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 53ec56f211e..6f2088edd1a 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -362,6 +362,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_BUS_NUM 1 +#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 + #define CONFIG_RTC_DS1337 #define CONFIG_SYS_RTC_DS1337_NOOSC #define CONFIG_SYS_I2C_RTC_ADDR 0x68 -- cgit v1.3.1 From e0082f7cb4985b7fbf3a69fbf884a85bd15af87a Mon Sep 17 00:00:00 2001 From: Poonam Aggrwal Date: Wed, 9 Feb 2011 20:05:29 +0000 Subject: powerpc/85xx: Add 36-bit physical addressing support for P1_P2_RDB Add support for 36-bit address map for NOR, SD, and SPI boot cfgs. Signed-off-by: Poonam Aggrwal Signed-off-by: Priyanka Jain Signed-off-by: Kumar Gala --- board/freescale/p1_p2_rdb/p1_p2_rdb.c | 3 ++ board/freescale/p1_p2_rdb/tlb.c | 9 ++--- boards.cfg | 12 +++++++ include/configs/P1_P2_RDB.h | 67 +++++++++++++++++++++++++++++++++-- 4 files changed, 84 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c b/board/freescale/p1_p2_rdb/p1_p2_rdb.c index d4b4b6811b1..307c3e2564d 100644 --- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c +++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c @@ -107,6 +107,9 @@ int checkboard (void) cpu = gd->cpu; printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev); +#ifdef CONFIG_PHYS_64BIT + puts ("(36-bit addrmap) \n"); +#endif setbits_be32(&pgpio->gpdir, GPIO_DIR); /* diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c index 9b166b2151c..1847935a737 100644 --- a/board/freescale/p1_p2_rdb/tlb.c +++ b/board/freescale/p1_p2_rdb/tlb.c @@ -25,19 +25,20 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), diff --git a/boards.cfg b/boards.cfg index 45c3102b0d5..263c1e6dfe7 100644 --- a/boards.cfg +++ b/boards.cfg @@ -509,15 +509,24 @@ MPC8572DS powerpc mpc85xx mpc8572ds freesca MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND P1011RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB +P1011RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT +P1011RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SDCARD +P1011RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,36BIT,SPIFLASH P1011RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,NAND P1011RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SDCARD P1011RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1011RDB,SPIFLASH P1020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB +P1020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT +P1020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SDCARD +P1020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,36BIT,SPIFLASH P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,NAND P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH P1022DS powerpc mpc85xx p1022ds freescale P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB +P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT +P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD +P2010RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SPIFLASH P2010RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,NAND P2010RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SDCARD P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,SPIFLASH @@ -525,6 +534,9 @@ P2020DS powerpc mpc85xx p2020ds freesca P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2 P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB +P2020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT +P2020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SDCARD +P2020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SPIFLASH P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 6f2088edd1a..4103e8b96bf 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -30,6 +30,10 @@ #ifndef __CONFIG_H #define __CONFIG_H +#ifdef CONFIG_36BIT +#define CONFIG_PHYS_64BIT +#endif + #ifdef CONFIG_P1011RDB #define CONFIG_P1011 #endif @@ -123,6 +127,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ENABLE_36BIT_PHYS 1 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x1fffffff #define CONFIG_PANIC_HANG /* do not reset board on panic */ @@ -144,7 +153,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * actual resources get mapped (not physical addresses) */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#endif /* CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ /* CONFIG_SYS_IMMR */ @@ -197,13 +210,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfef000000ull +#else #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xff000ff7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ @@ -231,6 +248,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ @@ -242,10 +271,20 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #ifndef CONFIG_NAND_SPL #define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull #else -#define CONFIG_SYS_NAND_BASE 0xfff00000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #endif +#else +#define CONFIG_SYS_NAND_BASE 0xfff00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull +#else #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif +#endif + #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 @@ -292,7 +331,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_VSC7385_BASE 0xffb00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull +#else #define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE +#endif #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE) \ | BR_PS_8 | BR_V) @@ -376,23 +419,41 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* controller 2, Slot 2, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_NAME "Slot 1" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 1, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_NAME "Slot 2" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull +#else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 +#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ -- cgit v1.3.1 From 1a66f289160c265a27fba29225aae6c0a1d9116a Mon Sep 17 00:00:00 2001 From: Zhao Chenhui Date: Wed, 2 Mar 2011 16:44:36 +0800 Subject: powerpc/85xx: Replace memctl_intlv_ctl with hwconfig on MPC8572DS Signed-off-by: Zhao Chenhui Signed-off-by: Kumar Gala --- include/configs/MPC8572DS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 4224229fcac..2b0e58ba459 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -741,7 +741,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ - "memctl_intlv_ctl=2\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=bank\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ -- cgit v1.3.1 From 5103d7aa23b33b9c4c5b6221248109eb6672c7b1 Mon Sep 17 00:00:00 2001 From: Zhao Chenhui Date: Wed, 2 Mar 2011 16:44:52 +0800 Subject: powerpc/85xx: Disable ECC in considering performance on MPC8572DS Signed-off-by: Zhao Chenhui Signed-off-by: Kumar Gala --- include/configs/MPC8572DS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 2b0e58ba459..0f419c57238 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -741,7 +741,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=bank\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=bank,ecc=off\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ -- cgit v1.3.1 From 863a3eac23362e70f12a456e6b563c416cbc43fc Mon Sep 17 00:00:00 2001 From: Zhao Chenhui Date: Fri, 4 Mar 2011 16:31:41 +0800 Subject: powerpc/85xx: Add support for ULI1575 PCI EHCI module on MPC8572DS MPC8572DS provides 2 USB ports with ULI1575. We enable USB storage device support using PCI EHCI module. Signed-off-by: Zhao Chenhui Signed-off-by: Kumar Gala --- include/configs/MPC8572DS.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 0f419c57238..8c0d06ab86c 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -672,6 +672,20 @@ #define CONFIG_CMD_EXT2 #endif +/* + * USB + */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI_PCI +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_STORAGE +#define CONFIG_PCI_EHCI_DEVICE 0 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 +#endif + #undef CONFIG_WATCHDOG /* watchdog disabled */ /* -- cgit v1.3.1 From 9899ac1951331b855152f8b5d9a8b540936ee947 Mon Sep 17 00:00:00 2001 From: Jiang Yutang Date: Mon, 24 Jan 2011 18:21:15 +0800 Subject: powerpc/85xx: Add 36-bit address map support to P1022DS Signed-off-by: Jiang Yutang Signed-off-by: Kumar Gala --- board/freescale/p1022ds/p1022ds.c | 3 +++ boards.cfg | 1 + include/configs/P1022DS.h | 46 ++++++++++++++++++++++++++++++++++++++- 3 files changed, 49 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 62beafa71d5..6f20dc3b9b6 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -53,6 +53,9 @@ int checkboard(void) u8 sw; puts("Board: P1022DS "); +#ifdef CONFIG_PHYS_64BIT + puts("(36-bit addrmap) "); +#endif printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); diff --git a/boards.cfg b/boards.cfg index 263c1e6dfe7..2622f787b6f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -523,6 +523,7 @@ P1020RDB_NAND powerpc mpc85xx p1_p2_rdb freesca P1020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SDCARD P1020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P1020RDB,SPIFLASH P1022DS powerpc mpc85xx p1022ds freescale +P1022DS_36BIT powerpc mpc85xx p1022ds freescale - P1022DS:36BIT P2010RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB P2010RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT P2010RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2010RDB,36BIT,SDCARD diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 5f47d1a7a94..c15cb8d2702 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -14,6 +14,10 @@ #include "../board/freescale/common/ics307_clk.h" +#ifdef CONFIG_36BIT +#define CONFIG_PHYS_64BIT +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE /* BOOKE */ #define CONFIG_E500 /* BOOKE e500 family */ @@ -39,10 +43,11 @@ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_PHYS_64BIT +#ifdef CONFIG_PHYS_64BIT #define CONFIG_ENABLE_36BIT_PHYS #define CONFIG_ADDR_MAP #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif #define CONFIG_FSL_LAW /* Use common FSL init code */ @@ -65,7 +70,11 @@ */ #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#endif #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* DDR Setup */ @@ -111,7 +120,11 @@ * Local Bus Definitions */ #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif #define CONFIG_FLASH_BR_PRELIM \ (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) @@ -145,7 +158,11 @@ #define CONFIG_FSL_NGPIXIS #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ +#ifdef CONFIG_PHYS_64BIT #define PIXIS_BASE_PHYS 0xfffdf0000ull +#else +#define PIXIS_BASE_PHYS PIXIS_BASE +#endif #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7) @@ -241,32 +258,59 @@ /* controller 1, Slot 2, tgtid 1, Base address a000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 +#endif #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 +#endif #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 +#endif #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 3, Slot 1, tgtid 3, Base address b000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 +#endif #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 +#endif #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #ifdef CONFIG_PCI -- cgit v1.3.1 From c7fd27ccfb3225ffaf2ad88c44a89eeccc1008ac Mon Sep 17 00:00:00 2001 From: Kyle Moffett Date: Mon, 28 Mar 2011 11:35:48 -0400 Subject: mpc8xxx: DDR2/DDR3: Clean up DIMM-type switch statements The numeric constants in the switch statements are replaced by #defines added to the common ddr_spd.h header. This dramatically improves the readability of the switch statments. In addition, a few of the longer lines were cleaned up, and the DDR2 type for an SO-RDIMM module was added to the DDR2 switch statement. Signed-off-by: Kyle Moffett Cc: Andy Fleming Cc: Kim Phillips Acked-by: York Sun Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c | 23 +++++++------ arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 43 ++++++++++++------------- common/ddr_spd.c | 2 +- include/ddr_spd.h | 28 ++++++++++------ 4 files changed, 53 insertions(+), 43 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c index dcb37cea1f9..b565e338ad3 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr2_dimm_params.c @@ -250,24 +250,27 @@ ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, pdimm->primary_sdram_width = spd->primw; pdimm->ec_sdram_width = spd->ecw; - /* FIXME: what about registered SO-DIMM? */ + /* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */ switch (spd->dimm_type) { - case 0x01: /* RDIMM */ - case 0x10: /* Mini-RDIMM */ - pdimm->registered_dimm = 1; /* register buffered */ + case DDR2_SPD_DIMMTYPE_RDIMM: + case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM: + case DDR2_SPD_DIMMTYPE_MINI_RDIMM: + /* Registered/buffered DIMMs */ + pdimm->registered_dimm = 1; break; - case 0x02: /* UDIMM */ - case 0x04: /* SO-DIMM */ - case 0x08: /* Micro-DIMM */ - case 0x20: /* Mini-UDIMM */ - pdimm->registered_dimm = 0; /* unbuffered */ + case DDR2_SPD_DIMMTYPE_UDIMM: + case DDR2_SPD_DIMMTYPE_SO_DIMM: + case DDR2_SPD_DIMMTYPE_MICRO_DIMM: + case DDR2_SPD_DIMMTYPE_MINI_UDIMM: + /* Unbuffered DIMMs */ + pdimm->registered_dimm = 0; break; + case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM: default: printf("unknown dimm_type 0x%02X\n", spd->dimm_type); return 1; - break; } /* SDRAM device parameters */ diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c index 29cea53266b..756b15f7ab0 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c @@ -128,24 +128,32 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, pdimm->data_width = pdimm->primary_sdram_width + pdimm->ec_sdram_width; - switch (spd->module_type & 0xf) { - case 0x01: /* RDIMM */ - case 0x05: /* Mini-RDIMM */ - pdimm->registered_dimm = 1; /* register buffered */ + /* These are the types defined by the JEDEC DDR3 SPD spec */ + pdimm->mirrored_dimm = 0; + pdimm->registered_dimm = 0; + switch (spd->module_type & DDR3_SPD_MODULETYPE_MASK) { + case DDR3_SPD_MODULETYPE_RDIMM: + case DDR3_SPD_MODULETYPE_MINI_RDIMM: + /* Registered/buffered DIMMs */ + pdimm->registered_dimm = 1; for (i = 0; i < 16; i += 2) { - pdimm->rcw[i] = spd->mod_section.registered.rcw[i/2] & 0x0F; - pdimm->rcw[i+1] = (spd->mod_section.registered.rcw[i/2] >> 4) & 0x0F; + u8 rcw = spd->mod_section.registered.rcw[i/2]; + pdimm->rcw[i] = (rcw >> 0) & 0x0F; + pdimm->rcw[i+1] = (rcw >> 4) & 0x0F; } break; - case 0x02: /* UDIMM */ - case 0x03: /* SO-DIMM */ - case 0x04: /* Micro-DIMM */ - case 0x06: /* Mini-UDIMM */ - pdimm->registered_dimm = 0; /* unbuffered */ + + case DDR3_SPD_MODULETYPE_UDIMM: + case DDR3_SPD_MODULETYPE_SO_DIMM: + case DDR3_SPD_MODULETYPE_MICRO_DIMM: + case DDR3_SPD_MODULETYPE_MINI_UDIMM: + /* Unbuffered DIMMs */ + if (spd->mod_section.unbuffered.addr_mapping & 0x1) + pdimm->mirrored_dimm = 1; break; default: - printf("unknown dimm_type 0x%02X\n", spd->module_type); + printf("unknown module_type 0x%02X\n", spd->module_type); return 1; } @@ -303,16 +311,5 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min) * mtb_ps; - /* - * We need check the address mirror for unbuffered DIMM - * If SPD indicate the address map mirror, The DDR controller - * need care it. - */ - if ((spd->module_type == SPD_MODULETYPE_UDIMM) || - (spd->module_type == SPD_MODULETYPE_SODIMM) || - (spd->module_type == SPD_MODULETYPE_MICRODIMM) || - (spd->module_type == SPD_MODULETYPE_MINIUDIMM)) - pdimm->mirrored_dimm = spd->mod_section.unbuffered.addr_mapping & 0x1; - return 0; } diff --git a/common/ddr_spd.c b/common/ddr_spd.c index a7a30de22bb..7a388bb9fa1 100644 --- a/common/ddr_spd.c +++ b/common/ddr_spd.c @@ -18,7 +18,7 @@ spd_check(const u8 *buf, u8 spd_rev, u8 spd_cksum) /* * Check SPD revision supported - * Rev 1.2 or less supported by this code + * Rev 1.X or less supported by this code */ if (spd_rev >= 0x20) { printf("SPD revision %02X not supported by this code\n", diff --git a/include/ddr_spd.h b/include/ddr_spd.h index 710e5289c73..e895d615a8d 100644 --- a/include/ddr_spd.h +++ b/include/ddr_spd.h @@ -304,14 +304,24 @@ extern unsigned int ddr3_spd_check(const ddr3_spd_eeprom_t *spd); #define SPD_MEMTYPE_DDR2_FBDIMM_PROBE (0x0A) #define SPD_MEMTYPE_DDR3 (0x0B) -/* - * Byte 3 Key Byte / Module Type for DDR3 SPD - */ -#define SPD_MODULETYPE_RDIMM (0x01) -#define SPD_MODULETYPE_UDIMM (0x02) -#define SPD_MODULETYPE_SODIMM (0x03) -#define SPD_MODULETYPE_MICRODIMM (0x04) -#define SPD_MODULETYPE_MINIRDIMM (0x05) -#define SPD_MODULETYPE_MINIUDIMM (0x06) +/* DIMM Type for DDR2 SPD (according to v1.3) */ +#define DDR2_SPD_DIMMTYPE_UNDEFINED (0x00) +#define DDR2_SPD_DIMMTYPE_RDIMM (0x01) +#define DDR2_SPD_DIMMTYPE_UDIMM (0x02) +#define DDR2_SPD_DIMMTYPE_SO_DIMM (0x04) +#define DDR2_SPD_DIMMTYPE_72B_SO_CDIMM (0x06) +#define DDR2_SPD_DIMMTYPE_72B_SO_RDIMM (0x07) +#define DDR2_SPD_DIMMTYPE_MICRO_DIMM (0x08) +#define DDR2_SPD_DIMMTYPE_MINI_RDIMM (0x10) +#define DDR2_SPD_DIMMTYPE_MINI_UDIMM (0x20) + +/* Byte 3 Key Byte / Module Type for DDR3 SPD */ +#define DDR3_SPD_MODULETYPE_MASK (0x0f) +#define DDR3_SPD_MODULETYPE_RDIMM (0x01) +#define DDR3_SPD_MODULETYPE_UDIMM (0x02) +#define DDR3_SPD_MODULETYPE_SO_DIMM (0x03) +#define DDR3_SPD_MODULETYPE_MICRO_DIMM (0x04) +#define DDR3_SPD_MODULETYPE_MINI_RDIMM (0x05) +#define DDR3_SPD_MODULETYPE_MINI_UDIMM (0x06) #endif /* _DDR_SPD_H_ */ -- cgit v1.3.1 From 1ac63e4094eee321266d5e5129077a3247d9439a Mon Sep 17 00:00:00 2001 From: Jerry Huang Date: Mon, 24 Jan 2011 17:09:54 +0000 Subject: powerpc/85xx: Enable eSDHC boot support on P2020 DS We implement our own mmc_get_env_addr since the environment variables are written to just after the u-boot image on SDCard, so we must read the MBR to get the start address and code length of the u-boot image, then calculate the address of the env. Signed-off-by: Jerry Huang Signed-off-by: Zhao Chenhui Signed-off-by: Kumar Gala --- board/freescale/common/Makefile | 1 + board/freescale/common/sdhc_boot.c | 64 ++++++++++++++++++++++++++++++++++++++ board/freescale/p2020ds/tlb.c | 13 +++++++- boards.cfg | 1 + include/configs/P2020DS.h | 25 +++++++++++++++ 5 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 board/freescale/common/sdhc_boot.c (limited to 'include') diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 1abd3e56703..8ea5acb5de4 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -36,6 +36,7 @@ COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o +COBJS-$(CONFIG_ENV_IS_IN_MMC) += sdhc_boot.o COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o COBJS-$(CONFIG_MPC8548CDS) += cds_pci_ft.o diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c new file mode 100644 index 00000000000..964c6b830c1 --- /dev/null +++ b/board/freescale/common/sdhc_boot.c @@ -0,0 +1,64 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * The environment variables are written to just after the u-boot image + * on SDCard, so we must read the MBR to get the start address and code + * length of the u-boot image, then calculate the address of the env. + */ +#define ESDHC_BOOT_IMAGE_SIZE 0x48 +#define ESDHC_BOOT_IMAGE_ADDR 0x50 + +int mmc_get_env_addr(struct mmc *mmc, u32 *env_addr) +{ + u8 *tmp_buf; + u32 blklen, code_offset, code_len, n; + + blklen = mmc->read_bl_len; + tmp_buf = malloc(blklen); + if (!tmp_buf) + return 1; + + /* read out the first block, get the config data information */ + n = mmc->block_dev.block_read(mmc->block_dev.dev, 0, 1, tmp_buf); + if (!n) { + free(tmp_buf); + return 1; + } + + /* Get the Source Address, from offset 0x50 */ + code_offset = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_ADDR); + + /* Get the code size from offset 0x48 */ + code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE); + + *env_addr = code_offset + code_len; + + free(tmp_buf); + + return 0; +} + diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c index 824b3b29f08..fd914a16a8c 100644 --- a/board/freescale/p2020ds/tlb.c +++ b/board/freescale/p2020ds/tlb.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -90,6 +90,17 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_4K, 1), + +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR) + /* *I*G - L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_256K, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 2622f787b6f..a96e7cf5f56 100644 --- a/boards.cfg +++ b/boards.cfg @@ -534,6 +534,7 @@ P2010RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freesca P2020DS powerpc mpc85xx p2020ds freescale P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2 +P2020DS_SDCARD powerpc mpc85xx p2020ds freescale - P2020DS:SDCARD P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB P2020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT P2020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SDCARD diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 1815191f592..30da7b1d45e 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -33,6 +33,13 @@ #define CONFIG_PHYS_64BIT #endif +#ifdef CONFIG_SDCARD +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -92,6 +99,18 @@ #define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_PANIC_HANG /* do not reset board on panic */ +/* + * Config the L2 Cache + */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull +#else +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR +#endif +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) + /* * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) @@ -571,6 +590,11 @@ /* * Environment */ +#if defined(CONFIG_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#else #define CONFIG_ENV_IS_IN_FLASH 1 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 #define CONFIG_ENV_ADDR 0xfff80000 @@ -579,6 +603,7 @@ #endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -- cgit v1.3.1 From 7d3053fbf16caad4745f42f7ae3e38e9d3e964b5 Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 15 Feb 2011 17:09:19 -0600 Subject: powerpc: clean up DIU macro definitions for Freescale reference boards Clean up the macro defintions used to enable DIU (video) support on the MPC8610HPCD and the MPC5121ADS so that they look more like the P1022DS, which is newer. Add software cursor support to all three boards. Also document the CONFIG_FSL_DIU_FB in the README. Signed-off-by: Timur Tabi Acked-by: Anatolij Gustschin Signed-off-by: Kumar Gala --- README | 22 ++++++++++++++++++++++ include/configs/MPC8610HPCD.h | 13 ++++--------- include/configs/P1022DS.h | 3 +-- include/configs/mpc5121ads.h | 9 ++++----- 4 files changed, 31 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/README b/README index 21cd71b2978..bd035235c12 100644 --- a/README +++ b/README @@ -1074,6 +1074,28 @@ The following options need to be configured: and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP or CONFIG_VIDEO_SED13806_16BPP + CONFIG_FSL_DIU_FB + Enable the Freescale DIU video driver. Reference boards for + SOCs that have a DIU should define this macro to enable DIU + support, and should also define these other macros: + + CONFIG_SYS_DIU_ADDR + CONFIG_VIDEO + CONFIG_CMD_BMP + CONFIG_CFB_CONSOLE + CONFIG_VIDEO_SW_CURSOR + CONFIG_VGA_AS_SINGLE_DEVICE + CONFIG_VIDEO_LOGO + CONFIG_VIDEO_BMP_LOGO + + The DIU driver will look for the 'monitor' environment variable, + and if defined, enable the DIU as a console during boot. This + variable should be set to one of these values: + + '0' Output video to the DVI connector + '1' Output video to the LVDS connector + '2' Output video to the Dual-Link LVDS connector + - Keyboard Support: CONFIG_KEYBOARD diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 7b25e071b75..efe03132f79 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -21,14 +21,14 @@ #define CONFIG_SYS_TEXT_BASE 0xfff00000 -#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ /* video */ -#undef CONFIG_VIDEO - -#ifdef CONFIG_VIDEO +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) +#define CONFIG_VIDEO #define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO @@ -88,8 +88,6 @@ #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR+0x2c000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE @@ -494,9 +492,6 @@ #define CONFIG_WATCHDOG /* watchdog enabled */ #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ -/*DIU Configuration*/ -#define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/ - /* * Miscellaneous configurable options */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index c15cb8d2702..e78bcc54c58 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -202,13 +202,12 @@ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* Video */ -#undef CONFIG_FSL_DIU_FB - #ifdef CONFIG_FSL_DIU_FB #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) #define CONFIG_VIDEO #define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index f966325a8e2..e7ef29809a9 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -46,16 +46,16 @@ */ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ -#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ #define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* video */ -#undef CONFIG_VIDEO - -#ifdef CONFIG_VIDEO +#ifdef CONFIG_FSL_DIU_FB +#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR + 0x2100) +#define CONFIG_VIDEO #define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO @@ -74,7 +74,6 @@ #define CONFIG_MISC_INIT_R #define CONFIG_SYS_IMMR 0x80000000 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -- cgit v1.3.1