From 4e97e25723530cc8bf57ca1d0ae17d86895e04c5 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 15 Nov 2017 13:14:52 +0100 Subject: clk: clk_stm32fx: add clock configuration for mmc usage MMC block needs 48Mhz source clock, for that we choose to select the SAI PLL. Update also stm32_clock_get_rate() to retrieve the MMC clock source needed in MMC driver. STM32F4 uses a different RCC variant than STM32F7. For STM32F4 sdmmc clocks bit are located into dckcfgr register whereas there are located into dckcfgr2 registers on STM32F7. In both registers, bits CK48MSEL and SDMMC1SEL are located at the same position. Signed-off-by: Christophe Priouzeau Signed-off-by: Patrice Chotard Reviewed-by: Vikas Manocha --- include/dt-bindings/mfd/stm32f7-rcc.h | 1 + include/stm32_rcc.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/dt-bindings/mfd/stm32f7-rcc.h b/include/dt-bindings/mfd/stm32f7-rcc.h index e36cc69959c..44c09144938 100644 --- a/include/dt-bindings/mfd/stm32f7-rcc.h +++ b/include/dt-bindings/mfd/stm32f7-rcc.h @@ -90,6 +90,7 @@ #define STM32F7_RCC_APB2_TIM8 1 #define STM32F7_RCC_APB2_USART1 4 #define STM32F7_RCC_APB2_USART6 5 +#define STM32F7_RCC_APB2_SDMMC2 7 #define STM32F7_RCC_APB2_ADC1 8 #define STM32F7_RCC_APB2_ADC2 9 #define STM32F7_RCC_APB2_ADC3 10 diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h index 6dfb9cc2574..fb0855268e5 100644 --- a/include/stm32_rcc.h +++ b/include/stm32_rcc.h @@ -37,6 +37,7 @@ struct pll_psc { struct stm32_clk_info { struct pll_psc sys_pll_psc; bool has_overdrive; + bool v2; }; enum soc_family { -- cgit v1.2.3