From ed6fad3e25e945e7042a53e129adde6a27476c90 Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 5 Feb 2016 13:22:10 +0530 Subject: phy: Add phy driver support for xilinx PCS/PMA core Add phy driver support for xilinx PCS/PMA core Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Kedareswara rao Appana Signed-off-by: Michal Simek --- include/phy.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/phy.h b/include/phy.h index 09bbe483a4b..21459a8c809 100644 --- a/include/phy.h +++ b/include/phy.h @@ -264,6 +264,7 @@ int phy_smsc_init(void); int phy_teranetics_init(void); int phy_ti_init(void); int phy_vitesse_init(void); +int phy_xilinx_init(void); int board_phy_config(struct phy_device *phydev); int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id); -- cgit v1.3.1 From 217185b3197ab8d90086ee975a017cea2da8f0bb Mon Sep 17 00:00:00 2001 From: Siva Durga Prasad Paladugu Date: Fri, 5 Feb 2016 13:22:12 +0530 Subject: zynq-common: Enable phy driver for Xilinx PCS/PMA core Add support of Xilinx PCS/PMA core phy for Zynq Signed-off-by: Siva Durga Prasad Paladugu Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index c2ed28af145..9d81b1d3342 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -47,6 +47,7 @@ # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_PHY_MARVELL # define CONFIG_PHY_REALTEK +# define CONFIG_PHY_XILINX # define CONFIG_BOOTP_SERVERIP # define CONFIG_BOOTP_BOOTPATH # define CONFIG_BOOTP_GATEWAY -- cgit v1.3.1 From b7b3efe75a46c3d6bff43b7b314d1fff90ca65ec Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sat, 13 Feb 2016 11:50:03 +0100 Subject: ARM: zynq: Enable option to overwrite default variables Enable overwriting variables out of main config file. Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 9d81b1d3342..0a0517ceecb 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -204,6 +204,7 @@ #endif /* Default environment */ +#ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "fit_image=fit.itb\0" \ "load_addr=0x2000000\0" \ @@ -226,6 +227,7 @@ "load usb 0 ${load_addr} ${fit_image} && " \ "bootm ${load_addr}; fi\0" \ DFU_ALT_INFO +#endif #define CONFIG_BOOTCOMMAND "run $modeboot" #define CONFIG_BOOTDELAY 3 /* -1 to Disable autoboot */ -- cgit v1.3.1 From 996503ef8249ea85f6e50e930b78c989bbf513c4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sat, 13 Feb 2016 10:18:50 +0100 Subject: ARM: zynq: zybo: Enabling reading MAC address from EEPROM Zybo has on board I2C EEPROM which contains preprogrammed MAC address. Signed-off-by: Michal Simek Signed-off-by: Michal Simek --- include/configs/zynq_zybo.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/zynq_zybo.h b/include/configs/zynq_zybo.h index 0882fe36bd8..637b1c5ffe9 100644 --- a/include/configs/zynq_zybo.h +++ b/include/configs/zynq_zybo.h @@ -17,6 +17,9 @@ #define CONFIG_ZYNQ_I2C0 #define CONFIG_ZYNQ_I2C1 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_CMD_EEPROM +#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x50 +#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA #define CONFIG_DISPLAY #define CONFIG_I2C_EDID -- cgit v1.3.1 From a359eaa59857079678a2fa5ff0e4c0894de4ee1d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 15 Feb 2016 13:44:19 +0100 Subject: microblaze: Remove !OF_CONTROL code for timer and interrupt OF_CONTROL is enabled by default that's why this is dead code. Signed-off-by: Michal Simek --- arch/microblaze/cpu/interrupts.c | 9 +-------- arch/microblaze/cpu/timer.c | 14 -------------- board/xilinx/microblaze-generic/xparameters.h | 11 ----------- include/configs/microblaze-generic.h | 12 ------------ 4 files changed, 1 insertion(+), 45 deletions(-) (limited to 'include') diff --git a/arch/microblaze/cpu/interrupts.c b/arch/microblaze/cpu/interrupts.c index e5d8894f544..010ca4a02c4 100644 --- a/arch/microblaze/cpu/interrupts.c +++ b/arch/microblaze/cpu/interrupts.c @@ -115,8 +115,6 @@ static void intc_init(void) int interrupt_init(void) { int i; - -#ifdef CONFIG_OF_CONTROL const void *blob = gd->fdt_blob; int node = 0; @@ -136,12 +134,7 @@ int interrupt_init(void) } else { return node; } -#else -#if defined(CONFIG_SYS_INTC_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM) - intc = (microblaze_intc_t *)CONFIG_SYS_INTC_0_ADDR; - irq_no = CONFIG_SYS_INTC_0_NUM; -#endif -#endif + if (irq_no) { vecs = calloc(1, sizeof(struct irq_action) * irq_no); if (vecs == NULL) { diff --git a/arch/microblaze/cpu/timer.c b/arch/microblaze/cpu/timer.c index c0fc7c0f3ca..8845e07d0e8 100644 --- a/arch/microblaze/cpu/timer.c +++ b/arch/microblaze/cpu/timer.c @@ -31,11 +31,6 @@ void __udelay(unsigned long usec) i = get_timer(0); while ((get_timer(0) - i) < (usec / 1000)) ; - } else { -#ifndef CONFIG_OF_CONTROL - for (i = 0; i < (usec * XILINX_CLOCK_FREQ / 10000000); i++) - ; -#endif } } @@ -51,8 +46,6 @@ int timer_init (void) int irq = -1; u32 preload = 0; u32 ret = 0; - -#ifdef CONFIG_OF_CONTROL const void *blob = gd->fdt_blob; int node = 0; u32 cell[2]; @@ -83,13 +76,6 @@ int timer_init (void) return node; } -#else -#if defined(CONFIG_SYS_TIMER_0_ADDR) && defined(CONFIG_SYS_INTC_0_NUM) - preload = XILINX_CLOCK_FREQ / CONFIG_SYS_HZ; - irq = CONFIG_SYS_TIMER_0_IRQ; - tmr = (microblaze_timer_t *) (CONFIG_SYS_TIMER_0_ADDR); -#endif -#endif if (tmr && preload && irq >= 0) { tmr->loadreg = preload; tmr->control = TIMER_INTERRUPT | TIMER_RESET; diff --git a/board/xilinx/microblaze-generic/xparameters.h b/board/xilinx/microblaze-generic/xparameters.h index ccb528ed926..dc5645bd146 100644 --- a/board/xilinx/microblaze-generic/xparameters.h +++ b/board/xilinx/microblaze-generic/xparameters.h @@ -13,21 +13,10 @@ #define XILINX_BOARD_NAME microblaze-generic -/* System Clock Frequency */ -#define XILINX_CLOCK_FREQ 100000000 - /* Microblaze is microblaze_0 */ #define XILINX_USE_MSR_INSTR 1 #define XILINX_FSL_NUMBER 3 -/* Interrupt controller is opb_intc_0 */ -#define XILINX_INTC_BASEADDR 0x41200000 -#define XILINX_INTC_NUM_INTR_INPUTS 6 - -/* Timer pheriphery is opb_timer_1 */ -#define XILINX_TIMER_BASEADDR 0x41c00000 -#define XILINX_TIMER_IRQ 0 - /* GPIO is LEDs_4Bit*/ #define XILINX_GPIO_BASEADDR 0x40000000 diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 27668f2a891..09bfabcfdf1 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -47,18 +47,6 @@ #endif #define CONFIG_BOARD_LATE_INIT -/* interrupt controller */ -#ifdef XILINX_INTC_BASEADDR -# define CONFIG_SYS_INTC_0_ADDR XILINX_INTC_BASEADDR -# define CONFIG_SYS_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS -#endif - -/* timer */ -#if defined(XILINX_TIMER_BASEADDR) && defined(XILINX_TIMER_IRQ) -# define CONFIG_SYS_TIMER_0_ADDR XILINX_TIMER_BASEADDR -# define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ -#endif - /* watchdog */ #if defined(XILINX_WATCHDOG_BASEADDR) && defined(XILINX_WATCHDOG_IRQ) # define CONFIG_WATCHDOG_BASEADDR XILINX_WATCHDOG_BASEADDR -- cgit v1.3.1 From 5cfd918286a808d82a5002772958013cfdbb23de Mon Sep 17 00:00:00 2001 From: Soren Brinkmann Date: Mon, 1 Feb 2016 14:56:20 -0800 Subject: ARM64: zynqmp: Decrease boot delay Synchronize it with zynq platform. Signed-off-by: Soren Brinkmann Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 4e066cdfd23..b60239614fa 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -168,7 +168,7 @@ #define CONFIG_PREBOOT "run bootargs" #define CONFIG_BOOTCOMMAND "run $modeboot" -#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOTDELAY 3 #define CONFIG_BOARD_LATE_INIT -- cgit v1.3.1 From 46f68e6860cbd1175d89d11229307df8bbfce80f Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 18 Mar 2016 18:10:21 +0100 Subject: ARM64: zynqmp: Enable FAT write and EXT4 write for USB too Enabling writing files to FAT and EXT4 for USB. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index b60239614fa..0ecdc13bfa8 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -93,6 +93,9 @@ # ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ # define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000 # endif +#endif + +#if defined(CONFIG_ZYNQ_SDHCI) || defined(CONFIG_ZYNQMP_USB) # define CONFIG_FAT_WRITE # define CONFIG_CMD_EXT4_WRITE #endif -- cgit v1.3.1 From a3afb4a4bfbe4318ca8398ce7b0e01d8748a111c Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 18 Mar 2016 18:47:28 +0100 Subject: ARM64: Move HUSH enabling from board file to defconfig Simplify board config file. Signed-off-by: Michal Simek --- configs/xilinx_zynqmp_ep_defconfig | 1 + include/configs/xilinx_zynqmp.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/configs/xilinx_zynqmp_ep_defconfig b/configs/xilinx_zynqmp_ep_defconfig index a1f3580f8d0..91ae10ab211 100644 --- a/configs/xilinx_zynqmp_ep_defconfig +++ b/configs/xilinx_zynqmp_ep_defconfig @@ -6,6 +6,7 @@ CONFIG_SYS_TEXT_BASE=0x8000000 CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep108" CONFIG_FIT=y CONFIG_FIT_VERBOSE=y +CONFIG_HUSH_PARSER=y CONFIG_SYS_PROMPT="ZynqMP> " # CONFIG_CMD_CONSOLE is not set # CONFIG_CMD_IMLS is not set diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 0ecdc13bfa8..ed47283c176 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -184,7 +184,6 @@ #define CONFIG_SYS_CBSIZE 2048 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_LONGHELP #define CONFIG_CMDLINE_EDITING -- cgit v1.3.1 From 8d59d7f63bf46dd26fd11039e63e3ba9e2673c95 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 8 Feb 2016 09:34:53 +0100 Subject: ARM64: zynqmp: Read RAM information from DT Read information about memory from DT. This patch simplify life with synchronization between DT and board files. dram_init() only needs maximum RAM size below 4GB that's why please sort banks in memory node. dram_init_banksize() copies memory setup to bi_dram[]. This will avoid reading information from DT twice. Memory test start/end were changed to DDR location to let memtest still compiled. Signed-off-by: Michal Simek --- board/xilinx/zynqmp/zynqmp.c | 121 +++++++++++++++++++++++++++++++++++++ include/configs/xilinx_zynqmp.h | 9 ++- include/configs/xilinx_zynqmp_ep.h | 5 -- 3 files changed, 127 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 44d347ed3bf..0f44b04c1ef 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -50,12 +50,133 @@ int board_early_init_r(void) return 0; } +#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) +/* + * fdt_get_reg - Fill buffer by information from DT + */ +static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf, + const u32 *cell, int n) +{ + int i = 0, b, banks; + int parent_offset = fdt_parent_offset(fdt, nodeoffset); + int address_cells = fdt_address_cells(fdt, parent_offset); + int size_cells = fdt_size_cells(fdt, parent_offset); + char *p = buf; + phys_addr_t val; + phys_size_t vals; + + debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n", + __func__, address_cells, size_cells, buf, cell); + + /* Check memory bank setup */ + banks = n % (address_cells + size_cells); + if (banks) + panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n", + n, address_cells, size_cells); + + banks = n / (address_cells + size_cells); + + for (b = 0; b < banks; b++) { + debug("%s: Bank #%d:\n", __func__, b); + if (address_cells == 2) { + val = cell[i + 1]; + val <<= 32; + val |= cell[i]; + val = fdt64_to_cpu(val); + debug("%s: addr64=%llx, ptr=%p, cell=%p\n", + __func__, val, p, &cell[i]); + *(phys_addr_t *)p = val; + } else { + debug("%s: addr32=%x, ptr=%p\n", + __func__, fdt32_to_cpu(cell[i]), p); + *(phys_addr_t *)p = fdt32_to_cpu(cell[i]); + } + p += sizeof(phys_addr_t); + i += address_cells; + + debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i, + sizeof(phys_addr_t)); + + if (size_cells == 2) { + vals = cell[i + 1]; + vals <<= 32; + vals |= cell[i]; + vals = fdt64_to_cpu(vals); + + debug("%s: size64=%llx, ptr=%p, cell=%p\n", + __func__, vals, p, &cell[i]); + *(phys_size_t *)p = vals; + } else { + debug("%s: size32=%x, ptr=%p\n", + __func__, fdt32_to_cpu(cell[i]), p); + *(phys_size_t *)p = fdt32_to_cpu(cell[i]); + } + p += sizeof(phys_size_t); + i += size_cells; + + debug("%s: ps=%p, i=%x, size=%zu\n", + __func__, p, i, sizeof(phys_size_t)); + } + + /* Return the first address size */ + return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t)); +} + +#define FDT_REG_SIZE sizeof(u32) +/* Temp location for sharing data for storing */ +/* Up to 64-bit address + 64-bit size */ +static u8 tmp[CONFIG_NR_DRAM_BANKS * 16]; + +void dram_init_banksize(void) +{ + int bank; + + memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp)); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + debug("Bank #%d: start %llx\n", bank, + (unsigned long long)gd->bd->bi_dram[bank].start); + debug("Bank #%d: size %llx\n", bank, + (unsigned long long)gd->bd->bi_dram[bank].size); + } +} + +int dram_init(void) +{ + int node, len; + const void *blob = gd->fdt_blob; + const u32 *cell; + + memset(&tmp, 0, sizeof(tmp)); + + /* find or create "/memory" node. */ + node = fdt_subnode_offset(blob, 0, "memory"); + if (node < 0) { + printf("%s: Can't get memory node\n", __func__); + return node; + } + + /* Get pointer to cells and lenght of it */ + cell = fdt_getprop(blob, node, "reg", &len); + if (!cell) { + printf("%s: Can't get reg property\n", __func__); + return -1; + } + + gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE); + + debug("%s: Initial DRAM size %llx\n", __func__, gd->ram_size); + + return 0; +} +#else int dram_init(void) { gd->ram_size = CONFIG_SYS_SDRAM_SIZE; return 0; } +#endif void reset_cpu(ulong addr) { diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index ed47283c176..4062e01824e 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -26,8 +26,11 @@ #define CONFIG_SYS_ALT_MEMTEST #define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE +#ifndef CONFIG_NR_DRAM_BANKS +# define CONFIG_NR_DRAM_BANKS 2 +#endif +#define CONFIG_SYS_MEMTEST_START 0 +#define CONFIG_SYS_MEMTEST_END 1000 /* Have release address at the end of 256MB for now */ #define CPU_RELEASE_ADDR 0xFFFFFF0 @@ -39,7 +42,7 @@ # define CONFIG_IDENT_STRING " Xilinx ZynqMP" #endif -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE /* Flat Device Tree Definitions */ diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index 337312e58c0..aa58b62531d 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -22,11 +22,6 @@ #define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR, \ ZYNQMP_USB1_XHCI_BASEADDR} -/* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 - #define COUNTER_FREQUENCY 4000000 #include -- cgit v1.3.1 From 679b994a2b56c65d53f94ab85baa68c252abdda4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 30 Sep 2015 17:26:55 +0200 Subject: block: Add support for Ceva sata Initial Ceva Sata init code. Signed-off-by: Michal Simek Reviewed-by: Tom Rini --- board/xilinx/zynqmp/zynqmp.c | 4 ++ drivers/block/Makefile | 1 + drivers/block/sata_ceva.c | 113 ++++++++++++++++++++++++++++++++++++++++ include/configs/xilinx_zynqmp.h | 2 +- 4 files changed, 119 insertions(+), 1 deletion(-) create mode 100644 drivers/block/sata_ceva.c (limited to 'include') diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 0f44b04c1ef..087578cb6b9 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -185,6 +186,9 @@ void reset_cpu(ulong addr) #ifdef CONFIG_SCSI_AHCI_PLAT void scsi_init(void) { +#if defined(CONFIG_SATA_CEVA) + init_sata(0); +#endif ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR); scsi_scan(1); } diff --git a/drivers/block/Makefile b/drivers/block/Makefile index b4cbb093441..a43492f2082 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_LIBATA) += libata.o obj-$(CONFIG_MVSATA_IDE) += mvsata_ide.o obj-$(CONFIG_MX51_PATA) += mxc_ata.o obj-$(CONFIG_PATA_BFIN) += pata_bfin.o +obj-$(CONFIG_SATA_CEVA) += sata_ceva.o obj-$(CONFIG_SATA_DWC) += sata_dwc.o obj-$(CONFIG_SATA_MV) += sata_mv.o obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o diff --git a/drivers/block/sata_ceva.c b/drivers/block/sata_ceva.c new file mode 100644 index 00000000000..dcc3b90b17f --- /dev/null +++ b/drivers/block/sata_ceva.c @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2015 - 2016 Xilinx, Inc. + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include + +#include + +/* Vendor Specific Register Offsets */ +#define AHCI_VEND_PCFG 0xA4 +#define AHCI_VEND_PPCFG 0xA8 +#define AHCI_VEND_PP2C 0xAC +#define AHCI_VEND_PP3C 0xB0 +#define AHCI_VEND_PP4C 0xB4 +#define AHCI_VEND_PP5C 0xB8 +#define AHCI_VEND_PAXIC 0xC0 +#define AHCI_VEND_PTC 0xC8 + +/* Vendor Specific Register bit definitions */ +#define PAXIC_ADBW_BW64 0x1 +#define PAXIC_MAWIDD (1 << 8) +#define PAXIC_MARIDD (1 << 16) +#define PAXIC_OTL (0x4 << 20) + +#define PCFG_TPSS_VAL (0x32 << 16) +#define PCFG_TPRS_VAL (0x2 << 12) +#define PCFG_PAD_VAL 0x2 + +#define PPCFG_TTA 0x1FFFE +#define PPCFG_PSSO_EN (1 << 28) +#define PPCFG_PSS_EN (1 << 29) +#define PPCFG_ESDF_EN (1 << 31) + +#define PP2C_CIBGMN 0x0F +#define PP2C_CIBGMX (0x25 << 8) +#define PP2C_CIBGN (0x18 << 16) +#define PP2C_CINMP (0x29 << 24) + +#define PP3C_CWBGMN 0x04 +#define PP3C_CWBGMX (0x0B << 8) +#define PP3C_CWBGN (0x08 << 16) +#define PP3C_CWNMP (0x0F << 24) + +#define PP4C_BMX 0x0a +#define PP4C_BNM (0x08 << 8) +#define PP4C_SFD (0x4a << 16) +#define PP4C_PTST (0x06 << 24) + +#define PP5C_RIT 0x60216 +#define PP5C_RCT (0x7f0 << 20) + +#define PTC_RX_WM_VAL 0x40 +#define PTC_RSVD (1 << 27) + +#define PORT0_BASE 0x100 +#define PORT1_BASE 0x180 + +/* Port Control Register Bit Definitions */ +#define PORT_SCTL_SPD_GEN3 (0x3 << 4) +#define PORT_SCTL_SPD_GEN2 (0x2 << 4) +#define PORT_SCTL_SPD_GEN1 (0x1 << 4) +#define PORT_SCTL_IPM (0x3 << 8) + +#define PORT_BASE 0x100 +#define PORT_OFFSET 0x80 +#define NR_PORTS 2 +#define DRV_NAME "ahci-ceva" +#define CEVA_FLAG_BROKEN_GEN2 1 + +int init_sata(int dev) +{ + ulong tmp; + ulong mmio = ZYNQMP_SATA_BASEADDR; + int i; + + /* + * AXI Data bus width to 64 + * Set Mem Addr Read, Write ID for data transfers + * Transfer limit to 72 DWord + */ + tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL; + writel(tmp, mmio + AHCI_VEND_PAXIC); + + /* Set AHCI Enable */ + tmp = readl(mmio + HOST_CTL); + tmp |= HOST_AHCI_EN; + writel(tmp, mmio + HOST_CTL); + + for (i = 0; i < NR_PORTS; i++) { + /* TPSS TPRS scalars, CISE and Port Addr */ + tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i); + writel(tmp, mmio + AHCI_VEND_PCFG); + + /* Port Phy Cfg register enables */ + tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN; + writel(tmp, mmio + AHCI_VEND_PPCFG); + + /* Rx Watermark setting */ + tmp = PTC_RX_WM_VAL | PTC_RSVD; + writel(tmp, mmio + AHCI_VEND_PTC); + + /* Default to Gen 2 Speed and Gen 1 if Gen2 is broken */ + tmp = PORT_SCTL_SPD_GEN3 | PORT_SCTL_IPM; + writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); + } + return 0; +} diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 4062e01824e..8c760967f6d 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -226,7 +226,7 @@ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) -- cgit v1.3.1 From 4d1ed9c71561becbb9d612fe584bb6332eb24168 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 18 Mar 2016 23:43:39 +0100 Subject: ARM: zynq: Add uEnv.txt support preboot macro load the uEnv.txt from mmc 0 when bootmode is mmc. uenvcmd is executed after load of uEnv.txt if it is defined in the uEnv.txt env text file. The default importbootenv macro reads the uEnv.txt from mmc. Additional to this, usb_loadbootenv is added to support loading uEnv.txt from usb dev 0. Signed-off-by: Jason Wu Signed-off-by: Michal Simek --- include/configs/zynq-common.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'include') diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 0a0517ceecb..d8e3fa4e5a4 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -203,6 +203,9 @@ # define CONFIG_ENV_OFFSET 0xE0000 #endif +/* enable preboot to be loaded before CONFIG_BOOTDELAY */ +#define CONFIG_PREBOOT + /* Default environment */ #ifndef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -213,6 +216,29 @@ "nor_flash_off=0xE2100000\0" \ "fdt_high=0x20000000\0" \ "initrd_high=0x20000000\0" \ + "loadbootenv_addr=0x2000000\0" \ + "bootenv=uEnv.txt\0" \ + "bootenv_dev=mmc\0" \ + "loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \ + "importbootenv=echo Importing environment from ${bootenv_dev} ...; " \ + "env import -t ${loadbootenv_addr} $filesize\0" \ + "bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \ + "setbootenv=if env run bootenv_existence_test; then " \ + "if env run loadbootenv; then " \ + "env run importbootenv; " \ + "fi; " \ + "fi; \0" \ + "sd_loadbootenv=set bootenv_dev mmc && " \ + "run setbootenv \0" \ + "usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv \0" \ + "preboot=if test $modeboot = sdboot; then " \ + "run sd_loadbootenv; " \ + "echo Checking if uenvcmd is set ...; " \ + "if test -n $uenvcmd; then " \ + "echo Running uenvcmd ...; " \ + "run uenvcmd; " \ + "fi; " \ + "fi; \0" \ "norboot=echo Copying FIT from NOR flash to RAM... && " \ "cp.b ${nor_flash_off} ${load_addr} ${fit_size} && " \ "bootm ${load_addr}\0" \ -- cgit v1.3.1 From 07654ba1e37e0de2ee3a5983ad510a8c2dd21035 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 24 Mar 2016 13:16:29 +0100 Subject: ARM64: zynqmp: Enable EFI partition support Enable EFI partition support for ZynqMP. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 8c760967f6d..8cea61080d4 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -71,6 +71,7 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_FS_GENERIC #define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION #define CONFIG_MP #define CONFIG_CMD_MII -- cgit v1.3.1