From abc7d0f75c078524f713cb2d4b4efe1b1a122c60 Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Thu, 28 Jan 2016 15:38:15 +0800 Subject: armv8: ls2080ardb: invert irq pins polarity for AQR405 PHY To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins polarity by setting IRQCR register, because AQR405 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie Reviewed-by: York Sun --- include/configs/ls2080ardb.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index b2c0181132a..14635b7d812 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -355,6 +355,7 @@ unsigned long get_board_sys_clk(void); #define AQ_PHY_ADDR2 0x01 #define AQ_PHY_ADDR3 0x02 #define AQ_PHY_ADDR4 0x03 +#define AQR405_IRQ_MASK 0x36 #define CONFIG_MII #define CONFIG_ETHPRIME "DPNI1" -- cgit v1.3.1 From ed77b7045ef5a287a3b6443a21f17d28d307a295 Mon Sep 17 00:00:00 2001 From: York Sun Date: Mon, 29 Feb 2016 15:58:20 -0800 Subject: boards: ls2080: Fix default bootargs A white space is missing in multiple-line string for bootargs. Signed-off-by: York Sun --- include/configs/ls2080a_common.h | 2 +- include/configs/ls2080ardb.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index c9b0a2f428a..13ce349446d 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -260,7 +260,7 @@ unsigned long long get_qixis_addr(void); " 0x580800000 \0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0500" \ + "earlycon=uart8250,mmio,0x21c0500 " \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=256" #define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580700000 &&" \ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 14635b7d812..59a3f663104 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -333,7 +333,7 @@ unsigned long get_board_sys_clk(void); #undef CONFIG_BOOTARGS #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0600" \ + "earlycon=uart8250,mmio,0x21c0600 " \ "ramdisk_size=0x2000000 default_hugepagesz=2m" \ " hugepagesz=2m hugepages=256" -- cgit v1.3.1 From eeb5b1ad828dfccf51831c87a10cabf6c564a2a2 Mon Sep 17 00:00:00 2001 From: Stuart Yoder Date: Thu, 10 Mar 2016 10:52:18 -0600 Subject: pci: make pci_get_hose_head() available to external users Put pci_get_hose_head() prototype in header so it is available to external users, allowing them to find and iterate over all pci controllers. Signed-off-by: Stuart Yoder Reviewed-by: York Sun --- include/pci.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/pci.h b/include/pci.h index 87de7ab715b..d3c955eb801 100644 --- a/include/pci.h +++ b/include/pci.h @@ -700,6 +700,7 @@ extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags); extern void pci_register_hose(struct pci_controller* hose); extern struct pci_controller* pci_bus_to_hose(int bus); extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr); +extern struct pci_controller *pci_get_hose_head(void); extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev); extern int pci_hose_scan(struct pci_controller *hose); -- cgit v1.3.1 From eb118807a4c1778bda6294c36e379711cb08e198 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Thu, 10 Mar 2016 17:36:56 +0800 Subject: driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete Add support of address parity for DDR4 UDIMM or discrete memory. It requires to configurate corresponding MR5[2:0] and TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig, e.g. hwconfig=fsl_ddr:parity=on. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- doc/README.fsl-ddr | 9 ++++++++ drivers/ddr/fsl/ctrl_regs.c | 55 ++++++++++++++++++++++++++++++++++++++++----- drivers/ddr/fsl/options.c | 15 +++++++++++-- include/fsl_ddr_sdram.h | 11 ++++++++- 4 files changed, 82 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index cd71ec8e169..cec5d94df4a 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -123,6 +123,14 @@ ECC can be turned on/off by hwconfig. Syntax is hwconfig=fsl_ddr:ecc=off + +Memory address parity on/off +============================ +address parity can be turned on/off by hwconfig. +Syntax is: +hwconfig=fsl_ddr:parity=on + + Memory testing options for mpc85xx ================================== 1. Memory test can be done once U-Boot prompt comes up using mtest, or @@ -143,6 +151,7 @@ platform hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on + Table for dynamic ODT for DDR3 ============================== For single-slot system with quad-rank DIMM and dual-slot system, dynamic ODT may diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 0bfcd3413c6..9073917914e 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -895,11 +895,15 @@ static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num, slow = get_ddr_freq(ctrl_num) < 1249000000; #endif - if (popts->registered_dimm_en) { + if (popts->registered_dimm_en) rcw_en = 1; - ap_en = popts->ap_en; - } else { + + /* DDR4 can have address parity for UDIMM and discrete */ + if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) && + (!popts->registered_dimm_en)) { ap_en = 0; + } else { + ap_en = popts->ap_en; } x4_en = popts->x4_en ? 1 : 0; @@ -1135,6 +1139,7 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, unsigned short esdmode5; /* Extended SDRAM mode 5 */ int rtt_park = 0; bool four_cs = false; + const unsigned int mclk_ps = get_memory_clk_period_ps(0); #if CONFIG_CHIP_SELECTS_PER_CTRL == 4 if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) && @@ -1150,6 +1155,19 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, esdmode5 = 0x00000400; /* Data mask enabled */ } + /* set command/address parity latency */ + if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { + if (mclk_ps >= 935) { + /* for DDR4-1600/1866/2133 */ + esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK; + } else if (mclk_ps >= 833) { + /* for DDR4-2400 */ + esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK; + } else { + printf("parity: mclk_ps = %d not supported\n", mclk_ps); + } + } + ddr->ddr_sdram_mode_9 = (0 | ((esdmode4 & 0xffff) << 16) | ((esdmode5 & 0xffff) << 0) @@ -1170,6 +1188,20 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, } else { esdmode5 = 0x00000400; } + + if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { + if (mclk_ps >= 935) { + /* for DDR4-1600/1866/2133 */ + esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK; + } else if (mclk_ps >= 833) { + /* for DDR4-2400 */ + esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK; + } else { + printf("parity: mclk_ps = %d not supported\n", + mclk_ps); + } + } + switch (i) { case 1: ddr->ddr_sdram_mode_11 = (0 @@ -1925,12 +1957,25 @@ static void set_timing_cfg_7(const unsigned int ctrl_num, const common_timing_params_t *common_dimm) { unsigned int txpr, tcksre, tcksrx; - unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd; + unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd; + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000)); tcksre = max(5U, picos_to_mclk(ctrl_num, 10000)); tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000)); - par_lat = 0; + + if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) { + if (mclk_ps >= 935) { + /* parity latency 4 clocks in case of 1600/1866/2133 */ + par_lat = 4; + } else if (mclk_ps >= 833) { + /* parity latency 5 clocks for DDR4-2400 */ + par_lat = 5; + } else { + printf("parity: mclk_ps = %d not supported\n", mclk_ps); + } + } + cs_to_cmd = 0; if (txpr <= 200) diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 791d6441010..d0075ff1fd2 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -1002,8 +1002,19 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm, popts->twot_en = 0; popts->threet_en = 0; - /* for RDIMM, address parity enable */ - popts->ap_en = 1; + /* for RDIMM and DDR4 UDIMM/discrete memory, address parity enable */ + if (popts->registered_dimm_en) + popts->ap_en = 1; /* 0 = disable, 1 = enable */ + else + popts->ap_en = 0; /* disabled for DDR4 UDIMM/discrete default */ + + if (hwconfig_sub_f("fsl_ddr", "parity", buf)) { + if (hwconfig_subarg_cmp_f("fsl_ddr", "parity", "on", buf)) { + if (popts->registered_dimm_en || + (CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4)) + popts->ap_en = 1; + } + } /* * BSTTOPRE precharge interval diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 3699c0408a1..cf316a4665f 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -123,6 +123,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG2_D_INIT 0x00000010 +#define SDRAM_CFG2_AP_EN 0x00000020 #define SDRAM_CFG2_ODT_CFG_MASK 0x00600000 #define SDRAM_CFG2_ODT_NEVER 0 #define SDRAM_CFG2_ODT_ONLY_WRITE 1 @@ -177,6 +178,14 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 #define DDR_CDR2_VREF_RANGE_2 0x00000040 +/* DDR ERR_DISABLE */ +#define DDR_ERR_DISABLE_APED (1 << 8) /* Address parity error disable */ + +/* Mode Registers */ +#define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */ +#define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */ + + #if (defined(CONFIG_SYS_FSL_DDR_VER) && \ (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)) #ifdef CONFIG_SYS_FSL_DDR3L @@ -343,7 +352,7 @@ typedef struct memctl_options_s { /* mirrior DIMMs for DDR3 */ unsigned int mirrored_dimm; unsigned int quad_rank_present; - unsigned int ap_en; /* address parity enable for RDIMM */ + unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */ unsigned int x4_en; /* enable x4 devices */ /* Global Timing Parameters */ -- cgit v1.3.1 From f8008f144b01b6b2f64ccac00dc3f1131687c74e Mon Sep 17 00:00:00 2001 From: Alison Wang Date: Tue, 8 Mar 2016 11:59:59 +0800 Subject: arm: ls102xa: Enable CONFIG_SYS_CONSOLE_IS_IN_ENV support CONFIG_SYS_CONSOLE_IS_IN_ENV needs to be enabled, so we could set stdout environment variable to specify the vga for the console output when LCD/HDMI is connected to the boards. Signed-off-by: Alison Wang Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 1 + include/configs/ls1021atwr.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d7025f63251..62cf6e55532 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -478,6 +478,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_FSL_DIU_CH7301 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index cee62812c1c..b2e431a1c90 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -336,6 +336,7 @@ #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_FSL_DCU_SII9022A #define CONFIG_SYS_I2C_DVI_BUS_NUM 1 -- cgit v1.3.1 From ceded371c8a328cd41cdf55292206e0efb96c660 Mon Sep 17 00:00:00 2001 From: Wenbin Song Date: Wed, 9 Mar 2016 13:38:25 +0800 Subject: armv8/ls1043aqds: Enable ID_EEPROM support for ls1043aqds Signed-off-by: Wenbin Song Reviewed-by: York Sun --- include/configs/ls1043aqds.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 68e00c8bb11..7b99d369707 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -114,6 +114,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DOS_PARTITION #define CONFIG_BOARD_LATE_INIT + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + #define CONFIG_SYS_SATA AHCI_BASE_ADDR #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -- cgit v1.3.1