From ff3b4e9936a720870decd6ddb0e77c7b5d464d5d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 19 Nov 2025 08:55:35 -0600 Subject: s5p4418_nanopi2: Stop disabling device tree relocation Remove setting of fdt_high to ~0, which disables device tree relocation, from the default environment. Doing so prevents U-Boot from correcting problems such as having an unaligned device tree and leads to various failure modes in the OS. Signed-off-by: Tom Rini Signed-off-by: Minkyu Kang --- include/configs/s5p4418_nanopi2.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index fec1bfd50eb..8a8d54daf7b 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -139,7 +139,6 @@ #endif #define CFG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "rootdev=" __stringify(CONFIG_ROOT_DEV) "\0" \ "rootpart=" __stringify(CONFIG_ROOT_PART) "\0" \ -- cgit v1.2.3 From 70ab39e2305f6ab9b7b1752e26b0e4293129009b Mon Sep 17 00:00:00 2001 From: Greg Malysa Date: Wed, 26 Nov 2025 14:50:31 -0500 Subject: board: adi: Fix missing semicolon in nfsroot The nfsroot constructed as part of the default Analog Devices boot strategy is missing a semicolon between the server ip and the root path itself. This adds the missing semicolon. Signed-off-by: Greg Malysa --- include/env/adi/adi_boot.env | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/env/adi/adi_boot.env b/include/env/adi/adi_boot.env index d56b14f5172..7f0dfe15ff9 100644 --- a/include/env/adi/adi_boot.env +++ b/include/env/adi/adi_boot.env @@ -41,7 +41,7 @@ addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmas /* Boot modes are selectable and should be defined in the board env before including */ #if defined(USE_NFS) // rootpath is set by CONFIG_ROOTPATH -nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}${rootpath},tcp,nfsvers=3 ${adi_bootargs} +nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath},tcp,nfsvers=3 ${adi_bootargs} nfsboot=run init_ethernet; tftp ${loadaddr} ${tftp_dir_prefix}${imagefile}; run nfsargs; -- cgit v1.2.3 From 0af9efa7c1873b2d52eaa82d67a8c67351a7f8ca Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 19 Nov 2025 08:55:38 -0600 Subject: socfpga_vining_fpga: Stop disabling device tree relocation Remove setting of fdt_high to ~0, which disables device tree relocation, from the default environment. Doing so prevents U-Boot from correcting problems such as having an unaligned device tree and leads to various failure modes in the OS. Signed-off-by: Tom Rini Reviewed-by: Marek Vasut --- include/configs/socfpga_vining_fpga.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 4bb15cf4629..ad13f1345b0 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -40,7 +40,6 @@ "hostname=vining_fpga\0" \ "kernel_addr_r=0x10000000\0" \ "fdt_addr_r=0x20000000\0" \ - "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "dfu_alt_info=qspi0 sf 0:0;qspi1 sf 0:1\0" \ "mtdparts_0_16m=ff705000.spi.0:" /* 16MiB+128MiB SF config */ \ -- cgit v1.2.3 From ed9ba442ee1f9aea1ab92b10e56c8ac710a770cf Mon Sep 17 00:00:00 2001 From: Kaustabh Chakraborty Date: Fri, 24 Oct 2025 22:58:27 +0530 Subject: board: samsung: add support for Samsung Exynos mobile device boards Add support for a generic platform which intends to support multiple boards powered by ARMv8 Samsung Exynos SoCs. Some important features include: * Fastboot: This is present to provide an open alternative to Samsung's proprietary Odin protocol. The board file configures certain features for fastboot, such as a dynamically allocated fastboot buffer, and standardized (lowercase) partition aliases. * EFI: Kernel image can be loaded from an EFI partition. This adopts a standard booting process, which multiple OS distributions can rely on. Signed-off-by: Kaustabh Chakraborty Signed-off-by: Minkyu Kang --- include/configs/exynos-mobile.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 include/configs/exynos-mobile.h (limited to 'include') diff --git a/include/configs/exynos-mobile.h b/include/configs/exynos-mobile.h new file mode 100644 index 00000000000..862db5779ef --- /dev/null +++ b/include/configs/exynos-mobile.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung Exynos Generic Board Configuration (for mobile devices) + * + * Copyright (C) 2025 Kaustabh Chakraborty + */ + +#ifndef __CONFIG_EXYNOS_MOBILE_H +#define __CONFIG_EXYNOS_MOBILE_H + +#define CPU_RELEASE_ADDR secondary_boot_addr +#define CFG_SYS_BAUDRATE_TABLE {9600, 115200} + +#endif /* __CONFIG_EXYNOS_MOBILE_H */ -- cgit v1.2.3 From b546189a4b515ba5aaf542558e9778d7d2a05b4e Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Tue, 2 Dec 2025 19:34:15 +0100 Subject: arm64: dts: renesas: Add Renesas R-Car X5H R8A78000 SoC DTs Add initial device trees for Renesas R-Car X5H R8A78000 SoC. Include very basic clock, reset, power domain headers which are used to control supported peripherals via SCMI / SCP. The headers are currently kept limited to avoid possible ABI break. A lot of clock are still stubbed via fixed-clock, this is going to be gradually removed over time, as more of the platform is upstreamed. Signed-off-by: Hai Pham Signed-off-by: Khanh Le Signed-off-by: Marek Vasut --- include/dt-bindings/clock/r8a78000-clock-scmi.h | 46 +++++++++++++++++++++++++ include/dt-bindings/power/r8a78000-power-scmi.h | 25 ++++++++++++++ include/dt-bindings/reset/r8a78000-reset-scmi.h | 33 ++++++++++++++++++ 3 files changed, 104 insertions(+) create mode 100644 include/dt-bindings/clock/r8a78000-clock-scmi.h create mode 100644 include/dt-bindings/power/r8a78000-power-scmi.h create mode 100644 include/dt-bindings/reset/r8a78000-reset-scmi.h (limited to 'include') diff --git a/include/dt-bindings/clock/r8a78000-clock-scmi.h b/include/dt-bindings/clock/r8a78000-clock-scmi.h new file mode 100644 index 00000000000..455402ee8cc --- /dev/null +++ b/include/dt-bindings/clock/r8a78000-clock-scmi.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Renesas Electronics Corp. + * + * IDs match SCP 4.27 + */ + +#ifndef __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ +#define __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ + +/* + * These definition indices match the Clock ID defined by SCP FW 4.27. + */ + +#define SCP_CLOCK_ID_MDLC_UFS0 202 +#define SCP_CLOCK_ID_MDLC_UFS1 203 +#define SCP_CLOCK_ID_MDLC_SDHI0 204 + +#define SCP_CLOCK_ID_MDLC_XPCS0 316 +#define SCP_CLOCK_ID_MDLC_XPCS1 317 +#define SCP_CLOCK_ID_MDLC_XPCS2 318 +#define SCP_CLOCK_ID_MDLC_XPCS3 319 +#define SCP_CLOCK_ID_MDLC_XPCS4 320 +#define SCP_CLOCK_ID_MDLC_XPCS5 321 +#define SCP_CLOCK_ID_MDLC_XPCS6 322 +#define SCP_CLOCK_ID_MDLC_XPCS7 323 +#define SCP_CLOCK_ID_MDLC_RSW3 324 +#define SCP_CLOCK_ID_MDLC_RSW3TSN 325 +#define SCP_CLOCK_ID_MDLC_RSW3AES 326 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES0 327 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES1 328 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES2 329 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES3 330 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES4 331 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES5 332 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES6 333 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES7 334 +#define SCP_CLOCK_ID_MDLC_RSW3MFWD 335 + +#define SCP_CLOCK_ID_MDLC_MPPHY01 344 +#define SCP_CLOCK_ID_MDLC_MPPHY11 345 +#define SCP_CLOCK_ID_MDLC_MPPHY21 346 +#define SCP_CLOCK_ID_MDLC_MPPHY31 347 +#define SCP_CLOCK_ID_MDLC_MPPHY02 348 + +#endif /* __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ */ diff --git a/include/dt-bindings/power/r8a78000-power-scmi.h b/include/dt-bindings/power/r8a78000-power-scmi.h new file mode 100644 index 00000000000..2f1cb8e909c --- /dev/null +++ b/include/dt-bindings/power/r8a78000-power-scmi.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Renesas Electronics Corp. + * + * IDs match SCP 4.27 + */ + +#ifndef __DT_BINDINGS_R8A78000_SCMI_POWER_H__ +#define __DT_BINDINGS_R8A78000_SCMI_POWER_H__ + +/* + * These power domain indices match the Power Domain ID defined by SCP FW 4.27. + */ + +#define X5H_POWER_DOMAIN_ID_UFS0 12 +#define X5H_POWER_DOMAIN_ID_UFS1 13 + +#define X5H_POWER_DOMAIN_ID_RSW 15 + +#define X5H_POWER_DOMAIN_ID_MPP0 17 +#define X5H_POWER_DOMAIN_ID_MPP1 18 +#define X5H_POWER_DOMAIN_ID_MPP2 19 +#define X5H_POWER_DOMAIN_ID_MPP3 20 + +#endif /* __DT_BINDINGS_R8A78000_SCMI_POWER_H__ */ diff --git a/include/dt-bindings/reset/r8a78000-reset-scmi.h b/include/dt-bindings/reset/r8a78000-reset-scmi.h new file mode 100644 index 00000000000..e0d10caa589 --- /dev/null +++ b/include/dt-bindings/reset/r8a78000-reset-scmi.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Renesas Electronics Corp. + * + * IDs match SCP 4.27 + */ + +#ifndef __DT_BINDINGS_R8A78000_SCMI_RESET_H__ +#define __DT_BINDINGS_R8A78000_SCMI_RESET_H__ + +/* + * These definition indices match the Reset ID defined by SCP FW 4.27. + */ + +#define SCP_RESET_DOMAIN_ID_UFS0 202 +#define SCP_RESET_DOMAIN_ID_UFS1 203 + +#define SCP_RESET_DOMAIN_ID_XPCS0 316 +#define SCP_RESET_DOMAIN_ID_XPCS1 317 +#define SCP_RESET_DOMAIN_ID_XPCS2 318 +#define SCP_RESET_DOMAIN_ID_XPCS3 319 +#define SCP_RESET_DOMAIN_ID_XPCS4 320 +#define SCP_RESET_DOMAIN_ID_XPCS5 321 +#define SCP_RESET_DOMAIN_ID_XPCS6 322 +#define SCP_RESET_DOMAIN_ID_XPCS7 323 + +#define SCP_RESET_DOMAIN_ID_MPPHY01 344 +#define SCP_RESET_DOMAIN_ID_MPPHY11 345 +#define SCP_RESET_DOMAIN_ID_MPPHY21 346 +#define SCP_RESET_DOMAIN_ID_MPPHY31 347 +#define SCP_RESET_DOMAIN_ID_MPPHY02 348 + +#endif /* __DT_BINDINGS_R8A78000_SCMI_RESET_H__ */ -- cgit v1.2.3 From cf71963778ee1c1ac4b86c78acae138591b4169c Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Tue, 2 Dec 2025 19:34:16 +0100 Subject: arm64: dts: renesas: Add Renesas R-Car X5H R8A78000 Ironhide board code Add initial support for Renesas R-Car X5H R8A78000 Ironhide board. This consists mainly of DTs, Makefile and Kconfig entries and board specific configuration files. The DTs will be gradually switched over to Linux DTs via OF_UPSTREAM once Linux DTs become available upstream, as upstreaming progresses. Signed-off-by: Hai Pham Signed-off-by: Marek Vasut --- include/configs/ironhide.h | 11 +++++++++++ include/configs/rcar-gen5-common.h | 24 ++++++++++++++++++++++++ 2 files changed, 35 insertions(+) create mode 100644 include/configs/ironhide.h create mode 100644 include/configs/rcar-gen5-common.h (limited to 'include') diff --git a/include/configs/ironhide.h b/include/configs/ironhide.h new file mode 100644 index 00000000000..703c1714052 --- /dev/null +++ b/include/configs/ironhide.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#ifndef __IRONHIDE_H +#define __IRONHIDE_H + +#include "rcar-gen5-common.h" + +#endif /* __IRONHIDE_H */ diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h new file mode 100644 index 00000000000..dc28d07c7f9 --- /dev/null +++ b/include/configs/rcar-gen5-common.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Renesas Electronics Corporation + */ + +#ifndef __RCAR_GEN5_COMMON_H +#define __RCAR_GEN5_COMMON_H + +#include + +/* Console */ +#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200, 3250000 } + +/* Memory */ +#define DRAM_RSV_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) +#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) + +/* Environment setting */ +#define CFG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" + +#endif /* __RCAR_GEN5_COMMON_H */ -- cgit v1.2.3