From ff3b4e9936a720870decd6ddb0e77c7b5d464d5d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 19 Nov 2025 08:55:35 -0600 Subject: s5p4418_nanopi2: Stop disabling device tree relocation Remove setting of fdt_high to ~0, which disables device tree relocation, from the default environment. Doing so prevents U-Boot from correcting problems such as having an unaligned device tree and leads to various failure modes in the OS. Signed-off-by: Tom Rini Signed-off-by: Minkyu Kang --- include/configs/s5p4418_nanopi2.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/s5p4418_nanopi2.h b/include/configs/s5p4418_nanopi2.h index fec1bfd50eb..8a8d54daf7b 100644 --- a/include/configs/s5p4418_nanopi2.h +++ b/include/configs/s5p4418_nanopi2.h @@ -139,7 +139,6 @@ #endif #define CFG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "rootdev=" __stringify(CONFIG_ROOT_DEV) "\0" \ "rootpart=" __stringify(CONFIG_ROOT_PART) "\0" \ -- cgit v1.3.1 From 70ab39e2305f6ab9b7b1752e26b0e4293129009b Mon Sep 17 00:00:00 2001 From: Greg Malysa Date: Wed, 26 Nov 2025 14:50:31 -0500 Subject: board: adi: Fix missing semicolon in nfsroot The nfsroot constructed as part of the default Analog Devices boot strategy is missing a semicolon between the server ip and the root path itself. This adds the missing semicolon. Signed-off-by: Greg Malysa --- include/env/adi/adi_boot.env | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/env/adi/adi_boot.env b/include/env/adi/adi_boot.env index d56b14f5172..7f0dfe15ff9 100644 --- a/include/env/adi/adi_boot.env +++ b/include/env/adi/adi_boot.env @@ -41,7 +41,7 @@ addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmas /* Boot modes are selectable and should be defined in the board env before including */ #if defined(USE_NFS) // rootpath is set by CONFIG_ROOTPATH -nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}${rootpath},tcp,nfsvers=3 ${adi_bootargs} +nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath},tcp,nfsvers=3 ${adi_bootargs} nfsboot=run init_ethernet; tftp ${loadaddr} ${tftp_dir_prefix}${imagefile}; run nfsargs; -- cgit v1.3.1 From 0af9efa7c1873b2d52eaa82d67a8c67351a7f8ca Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 19 Nov 2025 08:55:38 -0600 Subject: socfpga_vining_fpga: Stop disabling device tree relocation Remove setting of fdt_high to ~0, which disables device tree relocation, from the default environment. Doing so prevents U-Boot from correcting problems such as having an unaligned device tree and leads to various failure modes in the OS. Signed-off-by: Tom Rini Reviewed-by: Marek Vasut --- include/configs/socfpga_vining_fpga.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 4bb15cf4629..ad13f1345b0 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -40,7 +40,6 @@ "hostname=vining_fpga\0" \ "kernel_addr_r=0x10000000\0" \ "fdt_addr_r=0x20000000\0" \ - "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "dfu_alt_info=qspi0 sf 0:0;qspi1 sf 0:1\0" \ "mtdparts_0_16m=ff705000.spi.0:" /* 16MiB+128MiB SF config */ \ -- cgit v1.3.1 From ed9ba442ee1f9aea1ab92b10e56c8ac710a770cf Mon Sep 17 00:00:00 2001 From: Kaustabh Chakraborty Date: Fri, 24 Oct 2025 22:58:27 +0530 Subject: board: samsung: add support for Samsung Exynos mobile device boards Add support for a generic platform which intends to support multiple boards powered by ARMv8 Samsung Exynos SoCs. Some important features include: * Fastboot: This is present to provide an open alternative to Samsung's proprietary Odin protocol. The board file configures certain features for fastboot, such as a dynamically allocated fastboot buffer, and standardized (lowercase) partition aliases. * EFI: Kernel image can be loaded from an EFI partition. This adopts a standard booting process, which multiple OS distributions can rely on. Signed-off-by: Kaustabh Chakraborty Signed-off-by: Minkyu Kang --- arch/arm/mach-exynos/Kconfig | 11 +- board/samsung/exynos-mobile/Kconfig | 18 ++ board/samsung/exynos-mobile/MAINTAINERS | 6 + board/samsung/exynos-mobile/Makefile | 5 + board/samsung/exynos-mobile/exynos-mobile.c | 287 ++++++++++++++++++++++++++ board/samsung/exynos-mobile/exynos-mobile.env | 18 ++ configs/exynos-mobile_defconfig | 68 ++++++ doc/board/samsung/exynos-mobile.rst | 40 ++++ doc/board/samsung/index.rst | 1 + include/configs/exynos-mobile.h | 14 ++ 10 files changed, 467 insertions(+), 1 deletion(-) create mode 100644 board/samsung/exynos-mobile/Kconfig create mode 100644 board/samsung/exynos-mobile/MAINTAINERS create mode 100644 board/samsung/exynos-mobile/Makefile create mode 100644 board/samsung/exynos-mobile/exynos-mobile.c create mode 100644 board/samsung/exynos-mobile/exynos-mobile.env create mode 100644 configs/exynos-mobile_defconfig create mode 100644 doc/board/samsung/exynos-mobile.rst create mode 100644 include/configs/exynos-mobile.h (limited to 'include') diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 2cd67d02386..b084b7284aa 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -2,7 +2,7 @@ if ARCH_EXYNOS config BOARD_COMMON def_bool y - depends on !TARGET_SMDKV310 && !TARGET_ARNDALE && !TARGET_E850_96 + depends on !TARGET_SMDKV310 && !TARGET_ARNDALE && !TARGET_EXYNOS_MOBILE && !TARGET_E850_96 config SPI_BOOTING bool @@ -252,6 +252,14 @@ config TARGET_E850_96 endchoice endif +config TARGET_EXYNOS_MOBILE + bool "Samsung Exynos Generic Boards (for mobile devices)" + select ARM64 + select BOARD_EARLY_INIT_F + select CLK_EXYNOS + select LINUX_KERNEL_IMAGE_HEADER + select OF_CONTROL + config SYS_SOC default "exynos" @@ -277,5 +285,6 @@ source "board/samsung/smdk5420/Kconfig" source "board/samsung/espresso7420/Kconfig" source "board/samsung/axy17lte/Kconfig" source "board/samsung/e850-96/Kconfig" +source "board/samsung/exynos-mobile/Kconfig" endif diff --git a/board/samsung/exynos-mobile/Kconfig b/board/samsung/exynos-mobile/Kconfig new file mode 100644 index 00000000000..ed7d16b8c6b --- /dev/null +++ b/board/samsung/exynos-mobile/Kconfig @@ -0,0 +1,18 @@ +if TARGET_EXYNOS_MOBILE + +config ENV_SOURCE_FILE + default "exynos-mobile" + +config LNX_KRNL_IMG_TEXT_OFFSET_BASE + default TEXT_BASE + +config SYS_BOARD + default "exynos-mobile" + +config SYS_CONFIG_NAME + default "exynos-mobile" + +config SYS_VENDOR + default "samsung" + +endif # TARGET_EXYNOS_MOBILE diff --git a/board/samsung/exynos-mobile/MAINTAINERS b/board/samsung/exynos-mobile/MAINTAINERS new file mode 100644 index 00000000000..11fea212fb1 --- /dev/null +++ b/board/samsung/exynos-mobile/MAINTAINERS @@ -0,0 +1,6 @@ +Exynos Generic Boards (for mobile devices) +M: Kaustabh Chakraborty +S: Maintained +F: board/samsung/exynos-mobile/ +F: configs/exynos-mobile_defconfig +F: include/configs/exynos-mobile.h diff --git a/board/samsung/exynos-mobile/Makefile b/board/samsung/exynos-mobile/Makefile new file mode 100644 index 00000000000..e049ed217c1 --- /dev/null +++ b/board/samsung/exynos-mobile/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2025 Kaustabh Chakraborty + +obj-y := exynos-mobile.o diff --git a/board/samsung/exynos-mobile/exynos-mobile.c b/board/samsung/exynos-mobile/exynos-mobile.c new file mode 100644 index 00000000000..c16281dbc36 --- /dev/null +++ b/board/samsung/exynos-mobile/exynos-mobile.c @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Exynos Generic Board Source (for mobile devices) + * + * Copyright (c) 2025 Kaustabh Chakraborty + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define lmb_alloc(size, addr) \ + lmb_alloc_mem(LMB_MEM_ALLOC_ANY, SZ_2M, addr, size, LMB_NONE) + +struct exynos_board_info { + const char *name; + const char *chip; + const u64 *const dram_bank_bases; + + char serial[64]; + + int (*const match)(struct exynos_board_info *); + const char *match_model; + const u8 match_max_rev; +}; + +/* + * The memory mapping includes all DRAM banks, along with the + * peripheral block, and a sentinel at the end. This is filled in + * dynamically. + */ +static struct mm_region exynos_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { + { + /* Peripheral MMIO block */ + .virt = 0x10000000UL, + .phys = 0x10000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, +}; + +struct mm_region *mem_map = exynos_mem_map; + +/* + * This array is used for matching the models and revisions with the + * devicetree used by U-Boot. This allows a single U-Boot to work on + * multiple devices. + * + * Entries are kept in lexicographical order of board SoCs, followed by + * board names. + */ +static struct exynos_board_info exynos_board_info_match[] = { +}; + +static void exynos_parse_dram_banks(const struct exynos_board_info *board_info, + const void *fdt_base) +{ + u64 mem_addr, mem_size = 0; + u32 na, ns, i, j; + int offset; + + if (fdt_check_header(fdt_base) < 0) + return; + + /* #address-cells and #size-cells as defined in the fdt root. */ + na = fdt_address_cells(fdt_base, 0); + ns = fdt_size_cells(fdt_base, 0); + + fdt_for_each_subnode(offset, fdt_base, 0) { + if (strncmp(fdt_get_name(fdt_base, offset, NULL), "memory", 6)) + continue; + + for (i = 0; ; i++) { + mem_addr = fdtdec_get_addr_size_fixed(fdt_base, offset, + "reg", i, na, ns, + &mem_size, false); + if (mem_addr == FDT_ADDR_T_NONE) + break; + + if (!mem_size) + continue; + + for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) { + if (board_info->dram_bank_bases[j] != mem_addr) + continue; + + mem_map[j + 1].phys = mem_addr; + mem_map[j + 1].virt = mem_addr; + mem_map[j + 1].size = mem_size; + mem_map[j + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE; + break; + } + } + } +} + +static int exynos_fastboot_setup(void) +{ + struct blk_desc *blk_dev; + struct disk_partition info = {0}; + char buf[128]; + phys_addr_t addr; + int offset, i, j; + + /* Allocate and define buffer address for fastboot interface. */ + if (lmb_alloc(CONFIG_FASTBOOT_BUF_SIZE, &addr)) { + log_err("%s: failed to allocate fastboot buffer\n", __func__); + return -ENOMEM; + } + env_set_hex("fastboot_addr_r", addr); + + blk_dev = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV); + if (!blk_dev) { + log_err("%s: required mmc device not available\n", __func__); + return -ENODEV; + } + + strcpy(buf, "fastboot_partition_alias_"); + offset = strlen(buf); + + for (i = 1; i < CONFIG_EFI_PARTITION_ENTRIES_NUMBERS; i++) { + if (part_get_info(blk_dev, i, &info)) + continue; + + /* + * The partition name must be lowercase (stored in buf[]), + * as is expected in all fastboot partitions ... + */ + strlcpy(buf + offset, info.name, sizeof(buf) - offset); + for (j = offset; buf[j]; j++) + buf[j] = tolower(buf[j]); + if (!strcmp(buf + offset, info.name)) + continue; + /* + * ... However, if that isn't the case, a fastboot + * partition alias must be defined to establish it. + */ + env_set(buf, info.name); + } + + return 0; +} + +int board_fit_config_name_match(const char *name) +{ + struct exynos_board_info *board_info; + char buf[128]; + unsigned int i; + int ret; + + /* + * Iterate over exynos_board_info_match[] to select the + * appropriate board info struct. If not found, exit. + */ + for (i = 0; i < ARRAY_SIZE(exynos_board_info_match); i++) { + board_info = exynos_board_info_match + i; + snprintf(buf, sizeof(buf), "%s-%s", board_info->chip, + board_info->name); + + if (!strcmp(name, buf)) + break; + } + if (i == ARRAY_SIZE(exynos_board_info_match)) + return -1; + + /* + * Execute match logic for the target board. This is separated + * as the process may be different for multiple boards. + */ + ret = board_info->match(board_info); + if (ret) + return ret; + + /* + * Store the correct board info struct in gd->board_type to + * allow other functions to access it. + */ + gd->board_type = (ulong)board_info; + log_debug("%s: device detected: %s\n", __func__, name); + + return 0; +} + +int timer_init(void) +{ + ofnode timer_node; + + /* + * In a lot of Exynos devices, the previous bootloader does not + * set CNTFRQ_EL0 properly. However, the timer node in + * devicetree has the correct frequency, use that instead. + */ + timer_node = ofnode_by_compatible(ofnode_null(), "arm,armv8-timer"); + gd->arch.timer_rate_hz = ofnode_read_u32_default(timer_node, + "clock-frequency", 0); + + return 0; +} + +int board_early_init_f(void) +{ + const struct exynos_board_info *board_info; + + if (!gd->board_type) + return -ENODATA; + board_info = (const struct exynos_board_info *)gd->board_type; + + exynos_parse_dram_banks(board_info, gd->fdt_blob); + /* + * Some devices have multiple variants based on the amount of + * memory and internal storage. The lowest bank base has been + * observed to have the same memory range in all board variants. + * For variants with more memory, the previous bootloader should + * overlay the devicetree with the required extra memory ranges. + */ + exynos_parse_dram_banks(board_info, (const void *)get_prev_bl_fdt_addr()); + + return 0; +} + +int dram_init(void) +{ + unsigned int i; + + /* Select the largest RAM bank for U-Boot. */ + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + if (gd->ram_size < mem_map[i + 1].size) { + gd->ram_base = mem_map[i + 1].phys; + gd->ram_size = mem_map[i + 1].size; + } + } + + return 0; +} + +int dram_init_banksize(void) +{ + unsigned int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = mem_map[i + 1].phys; + gd->bd->bi_dram[i].size = mem_map[i + 1].size; + } + + return 0; +} + +int board_init(void) +{ + return 0; +} + +int misc_init_r(void) +{ + const struct exynos_board_info *board_info; + char buf[128]; + + if (!gd->board_type) + return -ENODATA; + board_info = (const struct exynos_board_info *)gd->board_type; + + env_set("platform", board_info->chip); + env_set("board", board_info->name); + + if (strlen(board_info->serial)) + env_set("serial#", board_info->serial); + + /* EFI booting requires the path to correct dtb, specify it here. */ + snprintf(buf, sizeof(buf), "exynos/%s-%s.dtb", board_info->chip, + board_info->name); + env_set("fdtfile", buf); + + return exynos_fastboot_setup(); +} diff --git a/board/samsung/exynos-mobile/exynos-mobile.env b/board/samsung/exynos-mobile/exynos-mobile.env new file mode 100644 index 00000000000..aa2e89afbac --- /dev/null +++ b/board/samsung/exynos-mobile/exynos-mobile.env @@ -0,0 +1,18 @@ +stdin=serial,button-kbd +stdout=serial,vidconsole +stderr=serial,vidconsole + +bootdelay=0 +bootcmd=bootefi bootmgr; pause; bootmenu + +fastbootcmd=echo "Fastboot Mode"; + fastboot -l $fastboot_addr_r usb 0 + +bootmenu_0=Continue Boot=boot +bootmenu_1=Enter Fastboot Mode=run fastbootcmd +bootmenu_2=UEFI Maintenance Menu=eficonfig +bootmenu_3=Reboot=reset +bootmenu_4=Power Off=poweroff + +button_cmd_0_name=Volume Down Key +button_cmd_0=bootmenu diff --git a/configs/exynos-mobile_defconfig b/configs/exynos-mobile_defconfig new file mode 100644 index 00000000000..2dbf90010ba --- /dev/null +++ b/configs/exynos-mobile_defconfig @@ -0,0 +1,68 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=26000000 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_EXYNOS=y +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x16000 +CONFIG_TARGET_EXYNOS_MOBILE=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_SYS_LOAD_ADDR=0x80000000 +CONFIG_ARMV8_CNTFRQ_BROKEN=y +# CONFIG_PSCI_RESET is not set +CONFIG_BUTTON_CMD=y +CONFIG_SAVE_PREV_BL_FDT_ADDR=y +CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y +CONFIG_SYS_PBSIZE=1024 +CONFIG_BOARD_TYPES=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_MISC_INIT_R=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_EFI_PARTITION=y +CONFIG_OF_UPSTREAM=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_BUTTON=y +CONFIG_BUTTON_REMAP_PHONE_KEYS=y +CONFIG_CLK=y +CONFIG_CLK_CCF=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0xdead0000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_SYS_I2C_S3C24X0=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_MISC=y +CONFIG_MMC_BROKEN_CD=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_DW=y +CONFIG_PHY=y +CONFIG_PHY_EXYNOS_USBDRD=y +CONFIG_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_S2MPS11=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_S2MPS11=y +CONFIG_SOC_SAMSUNG=y +CONFIG_EXYNOS_PMU=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_CMD_POWEROFF=y +CONFIG_SYSRESET_SYSCON=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Samsung" +CONFIG_USB_GADGET_VENDOR_NUM=0x04e8 +CONFIG_USB_GADGET_PRODUCT_NUM=0x6602 +CONFIG_VIDEO=y +CONFIG_VIDEO_SIMPLE=y +CONFIG_FS_EXT4=y +CONFIG_FS_FAT=y diff --git a/doc/board/samsung/exynos-mobile.rst b/doc/board/samsung/exynos-mobile.rst new file mode 100644 index 00000000000..d5c1c83a4e8 --- /dev/null +++ b/doc/board/samsung/exynos-mobile.rst @@ -0,0 +1,40 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Kaustabh Chakraborty + +Samsung Exynos Generic ARMv8 Boards (for mobile devices) +======================================================= + +Overview +-------- +This document describes how to build and run U-Boot for Samsung Exynos generic +boards. Boards are expected to boot with a primary bootloader, such as S-BOOT or +S-LK, which hands off control to U-Boot. Presently, only ARMv8 devices are +supported. + +The U-Boot image is built with all device tree blobs packed in a single FIT +image. During boot, it uses simple heuristics to detect the target board, and +subsequently the appropriate FDT is selected. + +Installation +------------ +Building +^^^^^^^^ +If a cross-compiler is required, install it and set it up like so: + +.. prompt:: bash $ + + export CROSS_COMPILE=aarch64-linux-gnu- + +Then, run the following commands to build U-Boot: + +.. prompt:: bash $ + + make O=.output exynos-mobile_defconfig + make O=.output -j$(nproc) + +If successful, the U-Boot binary will be present in ``.output/u-boot.bin``. + +Preparation and Flashing +^^^^^^^^^^^^^^^^^^^^^^^^ +Since U-Boot supports multiple boards, and devices have different requirements, +this step will vary depending on your target. diff --git a/doc/board/samsung/index.rst b/doc/board/samsung/index.rst index 1b92c9518a5..1fbe88130c0 100644 --- a/doc/board/samsung/index.rst +++ b/doc/board/samsung/index.rst @@ -8,4 +8,5 @@ Samsung axy17lte e850-96 + exynos-mobile n1 diff --git a/include/configs/exynos-mobile.h b/include/configs/exynos-mobile.h new file mode 100644 index 00000000000..862db5779ef --- /dev/null +++ b/include/configs/exynos-mobile.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Samsung Exynos Generic Board Configuration (for mobile devices) + * + * Copyright (C) 2025 Kaustabh Chakraborty + */ + +#ifndef __CONFIG_EXYNOS_MOBILE_H +#define __CONFIG_EXYNOS_MOBILE_H + +#define CPU_RELEASE_ADDR secondary_boot_addr +#define CFG_SYS_BAUDRATE_TABLE {9600, 115200} + +#endif /* __CONFIG_EXYNOS_MOBILE_H */ -- cgit v1.3.1 From b546189a4b515ba5aaf542558e9778d7d2a05b4e Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Tue, 2 Dec 2025 19:34:15 +0100 Subject: arm64: dts: renesas: Add Renesas R-Car X5H R8A78000 SoC DTs Add initial device trees for Renesas R-Car X5H R8A78000 SoC. Include very basic clock, reset, power domain headers which are used to control supported peripherals via SCMI / SCP. The headers are currently kept limited to avoid possible ABI break. A lot of clock are still stubbed via fixed-clock, this is going to be gradually removed over time, as more of the platform is upstreamed. Signed-off-by: Hai Pham Signed-off-by: Khanh Le Signed-off-by: Marek Vasut --- arch/arm/dts/r8a78000-u-boot.dtsi | 139 +++ arch/arm/dts/r8a78000.dtsi | 1164 +++++++++++++++++++++++ include/dt-bindings/clock/r8a78000-clock-scmi.h | 46 + include/dt-bindings/power/r8a78000-power-scmi.h | 25 + include/dt-bindings/reset/r8a78000-reset-scmi.h | 33 + 5 files changed, 1407 insertions(+) create mode 100644 arch/arm/dts/r8a78000-u-boot.dtsi create mode 100644 arch/arm/dts/r8a78000.dtsi create mode 100644 include/dt-bindings/clock/r8a78000-clock-scmi.h create mode 100644 include/dt-bindings/power/r8a78000-power-scmi.h create mode 100644 include/dt-bindings/reset/r8a78000-reset-scmi.h (limited to 'include') diff --git a/arch/arm/dts/r8a78000-u-boot.dtsi b/arch/arm/dts/r8a78000-u-boot.dtsi new file mode 100644 index 00000000000..1bc73252430 --- /dev/null +++ b/arch/arm/dts/r8a78000-u-boot.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source extras for U-Boot on R-Car R8A78000 SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/ { + soc { + bootph-all; + }; + + /* Placeholder clock until the clock provider is in place */ + clk_stub_gpio: clk-stub-gpio { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + + clk_stub_i2c0: clk-stub-i2c0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <150000000>; + }; + + clk_stub_i2c1: clk-stub-i2c1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133333333>; + }; + + clk_stub_mmc: clk-stub-mmc { + compatible = "renesas,compound-clock"; + #clock-cells = <0>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_SDHI0>, + <&scmi_clk 1691>; + clock-names = "mdlc", "per"; + }; +}; + +&cpg { + bootph-all; +}; + +&extal_clk { + bootph-all; +}; + +&extalr_clk { + bootph-all; +}; + +&gpio0 { + clocks = <&clk_stub_gpio>; +}; + +&gpio1 { + clocks = <&clk_stub_gpio>; +}; + +&gpio2 { + clocks = <&clk_stub_gpio>; +}; + +&gpio3 { + clocks = <&clk_stub_gpio>; +}; + +&gpio4 { + clocks = <&clk_stub_gpio>; +}; + +&gpio5 { + clocks = <&clk_stub_gpio>; +}; + +&gpio6 { + clocks = <&clk_stub_gpio>; +}; + +&gpio7 { + clocks = <&clk_stub_gpio>; +}; + +&gpio8 { + clocks = <&clk_stub_gpio>; +}; + +&gpio9 { + clocks = <&clk_stub_gpio>; +}; + +&gpio10 { + clocks = <&clk_stub_gpio>; +}; + +&i2c0 { + clocks = <&clk_stub_i2c0>; +}; + +&i2c1 { + clocks = <&clk_stub_i2c1>; +}; + +&i2c2 { + clocks = <&clk_stub_i2c1>; +}; + +&i2c3 { + clocks = <&clk_stub_i2c1>; +}; + +&i2c4 { + clocks = <&clk_stub_i2c1>; +}; + +&i2c5 { + clocks = <&clk_stub_i2c1>; +}; + +&i2c6 { + clocks = <&clk_stub_i2c1>; +}; + +&i2c7 { + clocks = <&clk_stub_i2c1>; +}; + +&i2c8 { + clocks = <&clk_stub_i2c1>; +}; + +&mmc0 { + clocks = <&clk_stub_mmc>; +}; + +&prr { + bootph-all; +}; diff --git a/arch/arm/dts/r8a78000.dtsi b/arch/arm/dts/r8a78000.dtsi new file mode 100644 index 00000000000..0d0c24503e2 --- /dev/null +++ b/arch/arm/dts/r8a78000.dtsi @@ -0,0 +1,1164 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car X5H (R8A78000) SoC + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +/ { + compatible = "renesas,r8a78000"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&a720_0>; + }; + core1 { + cpu = <&a720_1>; + }; + core2 { + cpu = <&a720_2>; + }; + core3 { + cpu = <&a720_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&a720_4>; + }; + core1 { + cpu = <&a720_5>; + }; + core2 { + cpu = <&a720_6>; + }; + core3 { + cpu = <&a720_7>; + }; + }; + + cluster2 { + core0 { + cpu = <&a720_8>; + }; + core1 { + cpu = <&a720_9>; + }; + core2 { + cpu = <&a720_10>; + }; + core3 { + cpu = <&a720_11>; + }; + }; + + cluster3 { + core0 { + cpu = <&a720_12>; + }; + core1 { + cpu = <&a720_13>; + }; + core2 { + cpu = <&a720_14>; + }; + core3 { + cpu = <&a720_15>; + }; + }; + + cluster4 { + core0 { + cpu = <&a720_16>; + }; + core1 { + cpu = <&a720_17>; + }; + core2 { + cpu = <&a720_18>; + }; + core3 { + cpu = <&a720_19>; + }; + }; + + cluster5 { + core0 { + cpu = <&a720_20>; + }; + core1 { + cpu = <&a720_21>; + }; + core2 { + cpu = <&a720_22>; + }; + core3 { + cpu = <&a720_23>; + }; + }; + + cluster6 { + core0 { + cpu = <&a720_24>; + }; + core1 { + cpu = <&a720_25>; + }; + core2 { + cpu = <&a720_26>; + }; + core3 { + cpu = <&a720_27>; + }; + }; + + cluster7 { + core0 { + cpu = <&a720_28>; + }; + core1 { + cpu = <&a720_29>; + }; + core2 { + cpu = <&a720_30>; + }; + core3 { + cpu = <&a720_31>; + }; + }; + }; + + a720_0: cpu@0 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x0>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_0>; + }; + + a720_1: cpu@100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_1>; + }; + + a720_2: cpu@200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_2>; + }; + + a720_3: cpu@300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_3>; + }; + + a720_4: cpu@10000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x10000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_4>; + }; + + a720_5: cpu@10100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x10100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_5>; + }; + + a720_6: cpu@10200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x10200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_6>; + }; + + a720_7: cpu@10300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x10300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_7>; + }; + + a720_8: cpu@20000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x20000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_8>; + }; + + a720_9: cpu@20100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x20100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_9>; + }; + + a720_10: cpu@20200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x20200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_10>; + }; + + a720_11: cpu@20300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x20300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_11>; + }; + + a720_12: cpu@30000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x30000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_12>; + }; + + a720_13: cpu@30100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x30100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_13>; + }; + + a720_14: cpu@30200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x30200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_14>; + }; + + a720_15: cpu@30300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x30300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_15>; + }; + + a720_16: cpu@40000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x40000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_16>; + }; + + a720_17: cpu@40100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x40100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_17>; + }; + + a720_18: cpu@40200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x40200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_18>; + }; + + a720_19: cpu@40300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x40300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_19>; + }; + + a720_20: cpu@50000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x50000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_20>; + }; + + a720_21: cpu@50100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x50100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_21>; + }; + + a720_22: cpu@50200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x50200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_22>; + }; + + a720_23: cpu@50300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x50300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_23>; + }; + + a720_24: cpu@60000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x60000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_24>; + }; + + a720_25: cpu@60100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x60100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_25>; + }; + + a720_26: cpu@60200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x60200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_26>; + }; + + a720_27: cpu@60300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x60300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_27>; + }; + + a720_28: cpu@70000 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x70000>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_28>; + }; + + a720_29: cpu@70100 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x70100>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_29>; + }; + + a720_30: cpu@70200 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x70200>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_30>; + }; + + a720_31: cpu@70300 { + compatible = "arm,cortex-a720ae"; + reg = <0x0 0x70300>; + device_type = "cpu"; + next-level-cache = <&L2_CA720_31>; + }; + + L2_CA720_0: cache-controller-200 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_0>; + }; + + L2_CA720_1: cache-controller-201 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_0>; + }; + + L2_CA720_2: cache-controller-202 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_0>; + }; + + L2_CA720_3: cache-controller-203 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_0>; + }; + + L2_CA720_4: cache-controller-204 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_1>; + }; + + L2_CA720_5: cache-controller-205 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_1>; + }; + + L2_CA720_6: cache-controller-206 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_1>; + }; + + L2_CA720_7: cache-controller-207 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_1>; + }; + + L2_CA720_8: cache-controller-208 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_2>; + }; + + L2_CA720_9: cache-controller-209 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_2>; + }; + + L2_CA720_10: cache-controller-210 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_2>; + }; + + L2_CA720_11: cache-controller-211 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_2>; + }; + + L2_CA720_12: cache-controller-212 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_3>; + }; + + L2_CA720_13: cache-controller-213 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_3>; + }; + + L2_CA720_14: cache-controller-214 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_3>; + }; + + L2_CA720_15: cache-controller-215 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_3>; + }; + + L2_CA720_16: cache-controller-216 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_4>; + }; + + L2_CA720_17: cache-controller-217 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_4>; + }; + + L2_CA720_18: cache-controller-218 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_4>; + }; + + L2_CA720_19: cache-controller-219 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_4>; + }; + + L2_CA720_20: cache-controller-220 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_5>; + }; + + L2_CA720_21: cache-controller-221 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_5>; + }; + + L2_CA720_22: cache-controller-222 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_5>; + }; + + L2_CA720_23: cache-controller-223 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_5>; + }; + + L2_CA720_24: cache-controller-224 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_6>; + }; + + L2_CA720_25: cache-controller-225 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_6>; + }; + + L2_CA720_26: cache-controller-226 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_6>; + }; + + L2_CA720_27: cache-controller-227 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_6>; + }; + + L2_CA720_28: cache-controller-228 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_7>; + }; + + L2_CA720_29: cache-controller-229 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_7>; + }; + + L2_CA720_30: cache-controller-230 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_7>; + }; + + L2_CA720_31: cache-controller-231 { + compatible = "cache"; + cache-unified; + cache-level = <2>; + next-level-cache = <&L3_CA720_7>; + }; + + L3_CA720_0: cache-controller-30 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_1: cache-controller-31 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_2: cache-controller-32 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_3: cache-controller-33 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_4: cache-controller-34 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_5: cache-controller-35 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_6: cache-controller-36 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + + L3_CA720_7: cache-controller-37 { + compatible = "cache"; + cache-unified; + cache-level = <3>; + }; + }; + + /* + * In the early phase, there is no clock control support, + * so assume that the clocks are enabled by default. + * Therefore, dummy clocks are used. + */ + dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <66666000>; + }; + + dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <266660000>; + }; + + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* clock-frequency must be set on board */ + }; + + extalr_clk: extalr-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* clock-frequency must be set on board */ + }; + + firmware { + scmi { + compatible = "arm,scmi"; + arm,poll-transport; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 0>, <&mailbox 1>; + shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; /* optional */ + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mailbox: mfis_mbox@18842000 { + compatible = "renesas,mfis-mbox"; + #mbox-cells = <1>; + reg = <0 0x18842004 0 0x8>; + interrupts = ; + }; + + prr: chipid@189e0044 { + compatible = "renesas,prr"; + reg = <0 0x189e0044 0 4>; + }; + + /* Application Processors manage View-1 of a GIC-720AE */ + gic: interrupt-controller@39000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x39000000 0 0x10000>, + <0 0x39080000 0 0x800000>; + interrupts = ; + }; + + pfc: pinctrl@c0400000 { + compatible = "renesas,pfc-r8a78000"; + reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>, + <0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>, + <0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>, + <0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>, + <0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>, + <0 0xc9b00800 0 0x104>; + }; + + scif0: serial@c0700000 { + compatible = "renesas,scif-r8a78000", + "renesas,rcar-gen5-scif", "renesas,scif"; + reg = <0 0xc0700000 0 0x40>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + scif1: serial@c0704000 { + compatible = "renesas,scif-r8a78000", + "renesas,rcar-gen5-scif", "renesas,scif"; + reg = <0 0xc0704000 0 0x40>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "okay"; + }; + + scif3: serial@c0708000 { + compatible = "renesas,scif-r8a78000", + "renesas,rcar-gen5-scif", "renesas,scif"; + reg = <0 0xc0708000 0 0x40>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + scif4: serial@c070c000 { + compatible = "renesas,scif-r8a78000", + "renesas,rcar-gen5-scif", "renesas,scif"; + reg = <0 0xc070c000 0 0x40>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + mmc0: mmc@c0880000 { + compatible = "renesas,rcar-gen5-sdhi"; + reg = <0 0xc0880000 0 0x2000>; + clock-names = "core"; + max-frequency = <200000000>; + status = "disabled"; + }; + + ufs0: ufs@c0a80000 { + compatible = "renesas,r8a78000-ufs"; + reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>; + reg-names = "hcr", "phy"; + interrupts = ; + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS0>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS0>; + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS0>; + freq-table-hz = <38400000 38400000>; + status = "disabled"; + }; + + ufs1: ufs@c0a90000 { + compatible = "renesas,r8a78000-ufs"; + reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>; + reg-names = "hcr", "phy"; + interrupts = ; + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS1>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS1>; + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS1>; + freq-table-hz = <38400000 38400000>; + status = "disabled"; + }; + + scp: sram@c1000000 { + compatible = "arm,rcar-sram-ns", "mmio-sram"; + reg = <0x0 0xc1000000 0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xc1000000 0x80000>; + + cpu_scp_lpri0: scp-shmem@60000 { + compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; + reg = <0x61200 0x0100>; + }; + + cpu_scp_hpri0: scp-shmem@60300 { + compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; + reg = <0x61300 0x100>; + }; + }; + + cpg: clock-controller@c64f0000 { + compatible = "renesas,r8a78000-cpg-mssr"; + reg = <0 0xc64f0000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + hscif0: serial@c0710000 { + compatible = "renesas,hscif-r8a78000", + "renesas,rcar-gen5-hscif", "renesas,hscif"; + reg = <0 0xc0710000 0 0x60>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + hscif1: serial@c0714000 { + compatible = "renesas,hscif-r8a78000", + "renesas,rcar-gen5-hscif", "renesas,hscif"; + reg = <0 0xc0714000 0 0x60>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + hscif2: serial@c0718000 { + compatible = "renesas,hscif-r8a78000", + "renesas,rcar-gen5-hscif", "renesas,hscif"; + reg = <0 0xc0718000 0 0x60>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + hscif3: serial@c071c000 { + compatible = "renesas,hscif-r8a78000", + "renesas,rcar-gen5-hscif", "renesas,hscif"; + reg = <0 0xc071c000 0 0x60>; + interrupts = ; + clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + status = "disabled"; + }; + + i2c0: i2c@c11d0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc11d0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@c06c0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06c0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@c06c8000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06c8000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@c06d0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06d0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@c06d8000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06d8000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@c06e0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06e0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@c06e8000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06e8000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@c06f0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06f0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@c06f8000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06f8000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + gpio0: gpio@c1080110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1080110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 28>; + }; + + gpio1: gpio@c1080910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1080910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 22>; + }; + + gpio2: gpio@c1081110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1081110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 29>; + }; + + gpio3: gpio@c0800110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0800110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 17>; + }; + + gpio4: gpio@c0800910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0800910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 16>; + }; + + gpio5: gpio@c0400110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0400110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 23>; + }; + + gpio6: gpio@c0400910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0400910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 31>; + }; + + gpio7: gpio@c0401110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0401110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 31>; + }; + + gpio8: gpio@c0401910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0401910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 256 32>; + gpio-reserved-ranges = <16 10>; + }; + + gpio9: gpio@c9b00110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc9b00110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 288 17>; + }; + + gpio10: gpio@c9b00910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc9b00910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 320 14>; + }; + + mp_phy: mp_phy@c9a00000 { + compatible = "renesas,r8a78000-multi-protocol-phy"; + reg = <0 0xc9a00000 0 0x100000>; + #phy-cells = <2>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY01>, + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY11>, + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY21>, + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY31>, + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY02>; + clock-names = "mpphy01", "mpphy11", "mpphy21", + "mpphy31", "mpphy02"; + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP0>, + <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP1>, + <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP2>, + <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP3>; + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY01>, + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY11>, + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY21>, + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY31>, + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY02>; + status = "disabled"; + }; + + rswitch3: ethernet@c9bc0000 { + compatible = "renesas,r8a78000-ether-switch3", + "renesas,etherswitch"; + reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>; + reg-names = "base", "secure_base"; + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_RSW>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSN>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3AES>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES0>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES1>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES2>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES3>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES4>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES5>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES6>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES7>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3MFWD>; + clock-names = "rsw3", "rsw3tsn", "rsw3aes", + "rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2", + "rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5", + "rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd"; + status = "disabled"; + }; + + eth_pcs: phy@c9c50000 { + compatible = "renesas,r8a78000-ether-pcs"; + reg = <0 0xc9c50000 0 0x4000>; + #phy-cells = <1>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS0>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS1>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS2>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS3>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS4>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS5>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS6>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS7>; + clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", + "xpcs4", "xpcs5", "xpcs6", "xpcs7"; + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS0>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS1>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS2>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS3>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS4>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS5>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS6>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS7>; + reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", + "xpcs4", "xpcs5", "xpcs6", "xpcs7"; + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + , + ; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; diff --git a/include/dt-bindings/clock/r8a78000-clock-scmi.h b/include/dt-bindings/clock/r8a78000-clock-scmi.h new file mode 100644 index 00000000000..455402ee8cc --- /dev/null +++ b/include/dt-bindings/clock/r8a78000-clock-scmi.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Renesas Electronics Corp. + * + * IDs match SCP 4.27 + */ + +#ifndef __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ +#define __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ + +/* + * These definition indices match the Clock ID defined by SCP FW 4.27. + */ + +#define SCP_CLOCK_ID_MDLC_UFS0 202 +#define SCP_CLOCK_ID_MDLC_UFS1 203 +#define SCP_CLOCK_ID_MDLC_SDHI0 204 + +#define SCP_CLOCK_ID_MDLC_XPCS0 316 +#define SCP_CLOCK_ID_MDLC_XPCS1 317 +#define SCP_CLOCK_ID_MDLC_XPCS2 318 +#define SCP_CLOCK_ID_MDLC_XPCS3 319 +#define SCP_CLOCK_ID_MDLC_XPCS4 320 +#define SCP_CLOCK_ID_MDLC_XPCS5 321 +#define SCP_CLOCK_ID_MDLC_XPCS6 322 +#define SCP_CLOCK_ID_MDLC_XPCS7 323 +#define SCP_CLOCK_ID_MDLC_RSW3 324 +#define SCP_CLOCK_ID_MDLC_RSW3TSN 325 +#define SCP_CLOCK_ID_MDLC_RSW3AES 326 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES0 327 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES1 328 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES2 329 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES3 330 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES4 331 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES5 332 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES6 333 +#define SCP_CLOCK_ID_MDLC_RSW3TSNTES7 334 +#define SCP_CLOCK_ID_MDLC_RSW3MFWD 335 + +#define SCP_CLOCK_ID_MDLC_MPPHY01 344 +#define SCP_CLOCK_ID_MDLC_MPPHY11 345 +#define SCP_CLOCK_ID_MDLC_MPPHY21 346 +#define SCP_CLOCK_ID_MDLC_MPPHY31 347 +#define SCP_CLOCK_ID_MDLC_MPPHY02 348 + +#endif /* __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ */ diff --git a/include/dt-bindings/power/r8a78000-power-scmi.h b/include/dt-bindings/power/r8a78000-power-scmi.h new file mode 100644 index 00000000000..2f1cb8e909c --- /dev/null +++ b/include/dt-bindings/power/r8a78000-power-scmi.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Renesas Electronics Corp. + * + * IDs match SCP 4.27 + */ + +#ifndef __DT_BINDINGS_R8A78000_SCMI_POWER_H__ +#define __DT_BINDINGS_R8A78000_SCMI_POWER_H__ + +/* + * These power domain indices match the Power Domain ID defined by SCP FW 4.27. + */ + +#define X5H_POWER_DOMAIN_ID_UFS0 12 +#define X5H_POWER_DOMAIN_ID_UFS1 13 + +#define X5H_POWER_DOMAIN_ID_RSW 15 + +#define X5H_POWER_DOMAIN_ID_MPP0 17 +#define X5H_POWER_DOMAIN_ID_MPP1 18 +#define X5H_POWER_DOMAIN_ID_MPP2 19 +#define X5H_POWER_DOMAIN_ID_MPP3 20 + +#endif /* __DT_BINDINGS_R8A78000_SCMI_POWER_H__ */ diff --git a/include/dt-bindings/reset/r8a78000-reset-scmi.h b/include/dt-bindings/reset/r8a78000-reset-scmi.h new file mode 100644 index 00000000000..e0d10caa589 --- /dev/null +++ b/include/dt-bindings/reset/r8a78000-reset-scmi.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025 Renesas Electronics Corp. + * + * IDs match SCP 4.27 + */ + +#ifndef __DT_BINDINGS_R8A78000_SCMI_RESET_H__ +#define __DT_BINDINGS_R8A78000_SCMI_RESET_H__ + +/* + * These definition indices match the Reset ID defined by SCP FW 4.27. + */ + +#define SCP_RESET_DOMAIN_ID_UFS0 202 +#define SCP_RESET_DOMAIN_ID_UFS1 203 + +#define SCP_RESET_DOMAIN_ID_XPCS0 316 +#define SCP_RESET_DOMAIN_ID_XPCS1 317 +#define SCP_RESET_DOMAIN_ID_XPCS2 318 +#define SCP_RESET_DOMAIN_ID_XPCS3 319 +#define SCP_RESET_DOMAIN_ID_XPCS4 320 +#define SCP_RESET_DOMAIN_ID_XPCS5 321 +#define SCP_RESET_DOMAIN_ID_XPCS6 322 +#define SCP_RESET_DOMAIN_ID_XPCS7 323 + +#define SCP_RESET_DOMAIN_ID_MPPHY01 344 +#define SCP_RESET_DOMAIN_ID_MPPHY11 345 +#define SCP_RESET_DOMAIN_ID_MPPHY21 346 +#define SCP_RESET_DOMAIN_ID_MPPHY31 347 +#define SCP_RESET_DOMAIN_ID_MPPHY02 348 + +#endif /* __DT_BINDINGS_R8A78000_SCMI_RESET_H__ */ -- cgit v1.3.1 From cf71963778ee1c1ac4b86c78acae138591b4169c Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Tue, 2 Dec 2025 19:34:16 +0100 Subject: arm64: dts: renesas: Add Renesas R-Car X5H R8A78000 Ironhide board code Add initial support for Renesas R-Car X5H R8A78000 Ironhide board. This consists mainly of DTs, Makefile and Kconfig entries and board specific configuration files. The DTs will be gradually switched over to Linux DTs via OF_UPSTREAM once Linux DTs become available upstream, as upstreaming progresses. Signed-off-by: Hai Pham Signed-off-by: Marek Vasut --- arch/arm/dts/Makefile | 7 + arch/arm/dts/r8a78000-ironhide-u-boot.dtsi | 8 + arch/arm/dts/r8a78000-ironhide.dts | 257 +++++++++++++++++++++++++++++ arch/arm/mach-renesas/Kconfig.rcar5 | 14 ++ board/renesas/common/Makefile | 4 + board/renesas/common/gen5-common.c | 75 +++++++++ board/renesas/ironhide/Kconfig | 15 ++ configs/r8a78000_ironhide_defconfig | 43 +++++ configs/renesas_rcar5.config | 23 +++ include/configs/ironhide.h | 11 ++ include/configs/rcar-gen5-common.h | 24 +++ 11 files changed, 481 insertions(+) create mode 100644 arch/arm/dts/r8a78000-ironhide-u-boot.dtsi create mode 100644 arch/arm/dts/r8a78000-ironhide.dts create mode 100644 board/renesas/common/gen5-common.c create mode 100644 board/renesas/ironhide/Kconfig create mode 100644 configs/r8a78000_ironhide_defconfig create mode 100644 configs/renesas_rcar5.config create mode 100644 include/configs/ironhide.h create mode 100644 include/configs/rcar-gen5-common.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 865ceb65f9a..fcad6fb2fc7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -918,6 +918,13 @@ dtb-$(CONFIG_RZA1) += \ r7s72100-genmai.dtb \ r7s72100-gr-peach.dtb +dtb-$(CONFIG_RCAR_GEN5) += \ + r8a78000-ironhide.dtb + +ifdef CONFIG_RCAR_GEN5 +DTC_FLAGS += -R 4 -p 0x1000 +endif + dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb diff --git a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi new file mode 100644 index 00000000000..9c72f3e55f4 --- /dev/null +++ b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source extras for U-Boot for the Ironhide board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include "r8a78000-u-boot.dtsi" diff --git a/arch/arm/dts/r8a78000-ironhide.dts b/arch/arm/dts/r8a78000-ironhide.dts new file mode 100644 index 00000000000..601f2740b54 --- /dev/null +++ b/arch/arm/dts/r8a78000-ironhide.dts @@ -0,0 +1,257 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the Ironhide board + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a78000.dtsi" +#include + +/ { + model = "Renesas Ironhide board based on r8a78000"; + compatible = "renesas,ironhide", "renesas,r8a78000"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + mmc0 = &mmc0; + serial0 = &hscif0; + }; + + chosen { + stdout-path = "serial0:1843200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x80000000>; + }; + + memory@1080000000 { + device_type = "memory"; + reg = <0x10 0x80000000 0x0 0x80000000>; + }; + + memory@1200000000 { + device_type = "memory"; + reg = <0x12 0x00000000 0x1 0x00000000>; + }; + + memory@1400000000 { + device_type = "memory"; + reg = <0x14 0x00000000 0x1 0x00000000>; + }; + + memory@1600000000 { + device_type = "memory"; + reg = <0x16 0x00000000 0x1 0x00000000>; + }; + + memory@1800000000 { + device_type = "memory"; + reg = <0x18 0x00000000 0x1 0x00000000>; + }; + + memory@1a00000000 { + device_type = "memory"; + reg = <0x1a 0x00000000 0x1 0x00000000>; + }; + + memory@1c00000000 { + device_type = "memory"; + reg = <0x1c 0x00000000 0x1 0x00000000>; + }; + + memory@1e00000000 { + device_type = "memory"; + reg = <0x1e 0x00000000 0x1 0x00000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&extal_clk { + clock-frequency = <16666600>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +ð_pcs { + phys = <&mp_phy 2 1>; + status = "okay"; +}; + +&mmc0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-1 = <&mmc0_pins>; + pinctrl-names = "default", "state_uhs"; + + bus-width = <8>; + full-pwr-cycle-in-suspend; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sd; + no-sdio; + non-removable; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + + status = "okay"; +}; + +&ufs0 { + status = "okay"; +}; + +&ufs1 { + status = "okay"; +}; + +&mp_phy { + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + eth25g2_pins: eth25g2 { + groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint"; + function = "eth25g2"; + drive-strength = <24>; + }; + + ethes0_pins: ethes0 { + groups = "ethes0_match", "ethes0_capture", "ethes0_pps"; + function = "ethes0"; + drive-strength = <24>; + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + mmc0_pins: mmc0 { + groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds"; + function = "mmc0"; + drive-strength = <24>; + }; + + rsw3_pins: rsw3 { + groups = "rsw3_match", "rsw3_capture", "rsw3_pps"; + function = "rsw3"; + drive-strength = <24>; + }; + + scif_clk_pins: scif-clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&rswitch3 { + pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>; + pinctrl-names = "default"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * NOTE: Only port@4 is configured for R-Car X5H board. + * Other ports (0-3, 5-12) are currently unused or not + * connected. + */ + port@4 { + reg = <4>; + renesas,connect_to_xpcs; + phy-handle = <&dp83869_phy>; + phy-mode = "sgmii"; + phys = <ð_pcs 5>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + dp83869_phy: ethernet-phy@2 { + reg = <2>; + ti,sgmii-interface; + ti,max-output-impedance; + ti,refclk-output-enable; + ti,clk-output-sel = ; + }; + }; + }; + }; +}; + +&scif_clk { + clock-frequency = <26000000>; +}; diff --git a/arch/arm/mach-renesas/Kconfig.rcar5 b/arch/arm/mach-renesas/Kconfig.rcar5 index 34c0ae8772b..528fc5aecc9 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar5 +++ b/arch/arm/mach-renesas/Kconfig.rcar5 @@ -9,4 +9,18 @@ config R8A78000 endmenu +choice + prompt "Renesas ARM64 SoCs board select" + optional + +config TARGET_IRONHIDE + bool "Ironhide board" + imply R8A78000 + help + Support for Renesas R-Car Gen5 Ironhide platform + +endchoice + +source "board/renesas/ironhide/Kconfig" + endif diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile index 1849c995aee..889de8ea9ac 100644 --- a/board/renesas/common/Makefile +++ b/board/renesas/common/Makefile @@ -43,6 +43,10 @@ else obj-y += gen4-common.o endif endif + +ifdef CONFIG_RCAR_GEN5 +obj-y += gen5-common.o +endif endif endif diff --git a/board/renesas/common/gen5-common.c b/board/renesas/common/gen5-common.c new file mode 100644 index 00000000000..a05a3e8abef --- /dev/null +++ b/board/renesas/common/gen5-common.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void init_generic_timer(void) +{ + const u32 freq = CONFIG_SYS_CLK_FREQ; + + /* Update memory mapped and register based freqency */ + asm volatile ("msr cntfrq_el0, %0" :: "r" (freq)); + writel(freq, CNTFID0); + + /* Enable counter */ + setbits_le32(CNTCR_BASE, CNTCR_EN); +} + +static void init_gic_v3(void) +{ + /* GIC v3 power on */ + writel(BIT(1), GICR_LPI_PWRR); + + /* Wait till the WAKER_CA_BIT changes to 0 */ + clrbits_le32(GICR_LPI_WAKER, BIT(1)); + while (readl(GICR_LPI_WAKER) & BIT(2)) + ; + + writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0); +} + +void s_init(void) +{ + if (current_el() == 3) + init_generic_timer(); +} + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + /* Allow WDT reset */ + writel(RST_KCPROT_DIS, RST_RESKCPROT0); + clrbits_le32(RST_WDTRSTCR, RST_WWDT_RSTMSK | RST_RWDT_RSTMSK); + + if (current_el() != 3) + return 0; + init_gic_v3(); + + return 0; +} + +void __weak reset_cpu(void) +{ + writel(RST_KCPROT_DIS, RST_RESKCPROT0); + writel(0x1, RST_SWSRES1A); +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return 0; +} diff --git a/board/renesas/ironhide/Kconfig b/board/renesas/ironhide/Kconfig new file mode 100644 index 00000000000..34b596714f3 --- /dev/null +++ b/board/renesas/ironhide/Kconfig @@ -0,0 +1,15 @@ +if TARGET_IRONHIDE + +config SYS_SOC + default "renesas" + +config SYS_BOARD + default "ironhide" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "ironhide" + +endif diff --git a/configs/r8a78000_ironhide_defconfig b/configs/r8a78000_ironhide_defconfig new file mode 100644 index 00000000000..180704e75af --- /dev/null +++ b/configs/r8a78000_ironhide_defconfig @@ -0,0 +1,43 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_RENESAS=y +CONFIG_RCAR_GEN5=y +CONFIG_TARGET_IRONHIDE=y + +# CONFIG_OF_UPSTREAM is not set +CONFIG_ARMV8_PSCI=y +CONFIG_ARM_SMCCC=y +CONFIG_BAUDRATE=1843200 +CONFIG_BOOTCOMMAND="setexpr dloadaddr ${loadaddr} + 0x200000 && setexpr dloadaddr ${dloadaddr} \\\\& 0xffc00000 && setexpr kloadaddr ${dloadaddr} + 0x200000 && tftp ${dloadaddr} r8a78000-ironhide.dtb && tftp ${kloadaddr} Image && booti ${kloadaddr} - ${dloadaddr}" +CONFIG_DEFAULT_DEVICE_TREE="r8a78000-ironhide" +CONFIG_CLK_CCF=y +CONFIG_CLK_COMPOSITE_CCF=y +CONFIG_CLK_SCMI=y +CONFIG_CMD_CLK=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_SCMI=y +CONFIG_CMD_UFS=y +CONFIG_DM_MAILBOX=y +CONFIG_DM_RESET=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_MMC_DEVICE_INDEX=0 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 +CONFIG_ENV_OFFSET=0xFFFE0000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_FIRMWARE=y +CONFIG_NR_DRAM_BANKS=16 +CONFIG_POWER_DOMAIN=y +CONFIG_RCAR_MFIS_MBOX=y +CONFIG_RESET_SCMI=y +CONFIG_SCMI_AGENT_MAILBOX=y +CONFIG_SCMI_FIRMWARE=y +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_SCSI=y +CONFIG_SYS_ALT_MEMTEST=y +CONFIG_SYS_BARGSIZE=2048 +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_CLK_FREQ=1066666667 +CONFIG_UFS=y +CONFIG_UFS_RENESAS_GEN5=y diff --git a/configs/renesas_rcar5.config b/configs/renesas_rcar5.config new file mode 100644 index 00000000000..fbf158dfdb3 --- /dev/null +++ b/configs/renesas_rcar5.config @@ -0,0 +1,23 @@ +#include + +CONFIG_ARCH_CPU_INIT=y +CONFIG_SYS_LOAD_ADDR=0x9E600000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_USE_BOOTARGS=y +CONFIG_USE_BOOTCOMMAND=y + +CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" +CONFIG_CMD_MMC=y +CONFIG_DM_ETH_PHY=y +# CONFIG_MMC_HS200_SUPPORT is not set +# CONFIG_MMC_IO_VOLTAGE is not set +# CONFIG_MMC_UHS_SUPPORT is not set +CONFIG_PHY_R8A78000_ETHERNET_PCS=y +CONFIG_PHY_R8A78000_MP_PHY=y +CONFIG_PHY_TI_DP83869=y +# CONFIG_PSCI_RESET is not set +CONFIG_RENESAS_ETHER_SWITCH=y +CONFIG_RENESAS_SDHI=y +CONFIG_SPI_FLASH_SPANSION=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SYS_I2C_RCAR_I2C=y diff --git a/include/configs/ironhide.h b/include/configs/ironhide.h new file mode 100644 index 00000000000..703c1714052 --- /dev/null +++ b/include/configs/ironhide.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Renesas Electronics Corp. + */ + +#ifndef __IRONHIDE_H +#define __IRONHIDE_H + +#include "rcar-gen5-common.h" + +#endif /* __IRONHIDE_H */ diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h new file mode 100644 index 00000000000..dc28d07c7f9 --- /dev/null +++ b/include/configs/rcar-gen5-common.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025 Renesas Electronics Corporation + */ + +#ifndef __RCAR_GEN5_COMMON_H +#define __RCAR_GEN5_COMMON_H + +#include + +/* Console */ +#define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200, 3250000 } + +/* Memory */ +#define DRAM_RSV_SIZE 0x08000000 +#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) +#define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) + +/* Environment setting */ +#define CFG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" + +#endif /* __RCAR_GEN5_COMMON_H */ -- cgit v1.3.1