From e9e18353c0c5b8c9d48a143f81d6e8f69eb20d3b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 17 Feb 2016 17:32:14 -0200 Subject: mx6ul_14x14_evk: Select CONFIG_FSL_QSPI Select CONFIG_FSL_QSPI so that the SPI can be probed: => sf probe SF: Detected N25Q256 with page size 256 Bytes, erase size 64 KiB, total 32 MiB Signed-off-by: Fabio Estevam Reviewed-by: Peng Fan --- include/configs/mx6ul_14x14_evk.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 4374c3a41fe..c7e10f91d33 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -195,6 +195,7 @@ #define CONFIG_CMD_CACHE #endif +#define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH -- cgit v1.3.1 From f91e65a74eff93d5187a3b27e1badd80c2a35fed Mon Sep 17 00:00:00 2001 From: Ulises Cardenas Date: Tue, 2 Feb 2016 04:39:39 -0600 Subject: imx: Refactoring CAAM Job Ring structure and Secure Memory for imx7 Refactored data structure for CAAM's job ring and Secure Memory to support i.MX7. The new memory map use macros to resolve SM's offset by version. This will solve the versioning issue caused by the new version of secure memory of i.MX7 Signed-off-by: Ulises Cardenas Reviewed-by: Stefano Babic --- arch/arm/include/asm/arch-mx7/imx-regs.h | 3 ++ drivers/crypto/fsl/jobdesc.c | 30 +++++++++++++------ include/fsl_sec.h | 49 +++++++++++++++++++++++--------- 3 files changed, 59 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 58a25c7b162..105043a46fa 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -216,6 +216,9 @@ #define FEC_QUIRK_ENET_MAC #define SNVS_LPGPR 0x68 +#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR) +#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + 0x1000) + #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include #include diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index 5695bef6fd2..fd0c4f7f2fd 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -14,7 +14,7 @@ #include "jobdesc.h" #include "rsa_caam.h" -#ifdef CONFIG_MX6 +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) /*! * Secure memory run command * @@ -25,10 +25,14 @@ uint32_t secmem_set_cmd(uint32_t sec_mem_cmd) { uint32_t temp_reg; - sec_out32(CAAM_SMCJR0, sec_mem_cmd); + ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid)); + uint32_t jr_id = 0; + + sec_out32(CAAM_SMCJR(sm_vid, jr_id), sec_mem_cmd); do { - temp_reg = sec_in32(CAAM_SMCSJR0); + temp_reg = sec_in32(CAAM_SMCSJR(sm_vid, jr_id)); } while (temp_reg & CMD_COMPLETE); return temp_reg; @@ -51,6 +55,10 @@ int caam_page_alloc(uint8_t page_num, uint8_t partition_num) { uint32_t temp_reg; + ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid)); + uint32_t jr_id = 0; + /* * De-Allocate partition_num if already allocated to ARM core */ @@ -64,9 +72,9 @@ int caam_page_alloc(uint8_t page_num, uint8_t partition_num) } /* set the access rights to allow full access */ - sec_out32(CAAM_SMAG1JR0(partition_num), 0xF); - sec_out32(CAAM_SMAG2JR0(partition_num), 0xF); - sec_out32(CAAM_SMAPJR0(partition_num), 0xFF); + sec_out32(CAAM_SMAG1JR(sm_vid, jr_id, partition_num), 0xF); + sec_out32(CAAM_SMAG2JR(sm_vid, jr_id, partition_num), 0xF); + sec_out32(CAAM_SMAPJR(sm_vid, jr_id, partition_num), 0xFF); /* Now need to allocate partition_num of secure RAM. */ /* De-Allocate page_num by starting with a page inquiry command */ @@ -105,6 +113,10 @@ int caam_page_alloc(uint8_t page_num, uint8_t partition_num) int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt, uint8_t *dek_blob, uint32_t in_sz) { + ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid)); + uint32_t jr_id = 0; + uint32_t ret = 0; u32 aad_w1, aad_w2; /* output blob will have 32 bytes key blob in beginning and @@ -133,9 +145,9 @@ int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt, flush_dcache_range(start, end); /* Now configure the access rights of the partition */ - sec_out32(CAAM_SMAG1JR0(PARTITION_1), KS_G1); /* set group 1 */ - sec_out32(CAAM_SMAG2JR0(PARTITION_1), 0); /* clear group 2 */ - sec_out32(CAAM_SMAPJR0(PARTITION_1), PERM); /* set perm & locks */ + sec_out32(CAAM_SMAG1JR(sm_vid, jr_id, PARTITION_1), KS_G1); + sec_out32(CAAM_SMAG2JR(sm_vid, jr_id, PARTITION_1), 0); + sec_out32(CAAM_SMAPJR(sm_vid, jr_id, PARTITION_1), PERM); /* construct aad for AES */ aad_w1 = (in_sz << OP_ALG_ALGSEL_SHIFT) | KEY_AES_SRC | LD_CCM_MODE; diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 2ddced34ab7..a52110a625c 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -97,19 +97,20 @@ typedef struct ccsr_sec { u32 drr; /* DECO Reset Register */ u8 res5[0x4d8]; struct rng4tst rng; /* RNG Registers */ - u8 res11[0x8a0]; + u8 res6[0x8a0]; u32 crnr_ms; /* CHA Revision Number Register, MS */ u32 crnr_ls; /* CHA Revision Number Register, LS */ u32 ctpr_ms; /* Compile Time Parameters Register, MS */ u32 ctpr_ls; /* Compile Time Parameters Register, LS */ - u8 res6[0x10]; + u8 res7[0x10]; u32 far_ms; /* Fault Address Register, MS */ u32 far_ls; /* Fault Address Register, LS */ u32 falr; /* Fault Address LIODN Register */ u32 fadr; /* Fault Address Detail Register */ - u8 res7[0x4]; + u8 res8[0x4]; u32 csta; /* CAAM Status Register */ - u8 res8[0x8]; + u32 smpart; /* Secure Memory Partition Parameters */ + u32 smvid; /* Secure Memory Version ID */ u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/ u32 ccbvid; /* CHA Cluster Block Version ID Register */ u32 chavid_ms; /* CHA Version ID Register, MS */ @@ -147,7 +148,8 @@ typedef struct ccsr_sec { #define CONFIG_JRSTARTR_JR0 0x00000001 struct jr_regs { -#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6) +#if defined(CONFIG_SYS_FSL_SEC_LE) && \ + !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) u32 irba_l; u32 irba_h; #else @@ -160,7 +162,8 @@ struct jr_regs { u32 irsa; u32 rsvd3; u32 irja; -#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6) +#if defined(CONFIG_SYS_FSL_SEC_LE) && \ + !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) u32 orba_l; u32 orba_h; #else @@ -192,7 +195,8 @@ struct jr_regs { * related information */ struct sg_entry { -#if defined(CONFIG_SYS_FSL_SEC_LE) && !defined(CONFIG_MX6) +#if defined(CONFIG_SYS_FSL_SEC_LE) && \ + !(defined(CONFIG_MX6) || defined(CONFIG_MX7)) uint32_t addr_lo; /* Memory Address - lo */ uint32_t addr_hi; /* Memory Address of start of buffer - hi */ #else @@ -211,26 +215,43 @@ struct sg_entry { #define SG_ENTRY_OFFSET_SHIFT 0 }; -#ifdef CONFIG_MX6 +#if defined(CONFIG_MX6) || defined(CONFIG_MX7) +/* Job Ring Base Address */ +#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) +/* Secure Memory Offset varies accross versions */ +#define SM_V1_OFFSET 0x0f4 +#define SM_V2_OFFSET 0xa00 +/*Secure Memory Versioning */ +#define SMVID_V2 0x20105 +#define SM_VERSION(x) (x < SMVID_V2 ? 1 : 2) +#define SM_OFFSET(x) (x == 1 ? SM_V1_OFFSET : SM_V2_OFFSET) /* CAAM Job Ring 0 Registers */ /* Secure Memory Partition Owner register */ #define SMCSJR_PO (3 << 6) /* JR Allocation Error */ #define SMCSJR_AERR (3 << 12) /* Secure memory partition 0 page 0 owner register */ -#define CAAM_SMPO_0 CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC +#define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC) /* Secure memory command register */ -#define CAAM_SMCJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10f4 +#define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v)) /* Secure memory command status register */ -#define CAAM_SMCSJR0 CONFIG_SYS_FSL_SEC_ADDR + 0x10fc +#define CAAM_SMCSJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_STATUS(v)) /* Secure memory access permissions register */ -#define CAAM_SMAPJR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16) +#define CAAM_SMAPJR(v, jr, y) \ + (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_PERM(v) + y * 16) /* Secure memory access group 2 register */ -#define CAAM_SMAG2JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16) +#define CAAM_SMAG2JR(v, jr, y) \ + (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP2(v) + y * 16) /* Secure memory access group 1 register */ -#define CAAM_SMAG1JR0(y) (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16) +#define CAAM_SMAG1JR(v, jr, y) \ + (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_GROUP1(v) + y * 16) /* Commands and macros for secure memory */ +#define SM_CMD(v) (v == 1 ? 0x0 : 0x1E4) +#define SM_STATUS(v) (v == 1 ? 0x8 : 0x1EC) +#define SM_PERM(v) (v == 1 ? 0x10 : 0x4) +#define SM_GROUP2(v) (v == 1 ? 0x14 : 0x8) +#define SM_GROUP1(v) (v == 1 ? 0x18 : 0xC) #define CMD_PAGE_ALLOC 0x1 #define CMD_PAGE_DEALLOC 0x2 #define CMD_PART_DEALLOC 0x3 -- cgit v1.3.1 From a668436051e497da18ab79ad26649e26d8a08433 Mon Sep 17 00:00:00 2001 From: Soeren Moch Date: Thu, 4 Feb 2016 14:41:16 +0100 Subject: board: tbs2910: Autoselect environment device when booting from SD Implement board specific functions to select the environment device and partition when booting from SD/MMC. SD2: mmc 0 0 SD3: mmc 1 0 eMMC: mmc 2 1 Signed-off-by: Soeren Moch --- board/tbs/tbs2910/tbs2910.c | 11 +++++++++++ include/configs/tbs2910.h | 4 ++-- 2 files changed, 13 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c index 0b509b6dd90..d302fc23b6c 100644 --- a/board/tbs/tbs2910/tbs2910.c +++ b/board/tbs/tbs2910/tbs2910.c @@ -257,6 +257,17 @@ int board_mmc_init(bd_t *bis) } return 0; } + +/* set environment device to boot device when booting from SD */ +int board_mmc_get_env_dev(int devno) +{ + return devno - 1; +} + +int board_mmc_get_env_part(int devno) +{ + return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */ +} #endif /* CONFIG_FSL_ESDHC */ #ifdef CONFIG_VIDEO_IPUV3 diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 17b0213362e..0f230346908 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -176,8 +176,8 @@ /* Environment organization */ #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 2 -#define CONFIG_SYS_MMC_ENV_PART 1 +#define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */ +#define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */ #define CONFIG_ENV_SIZE (8 * 1024) #define CONFIG_ENV_OFFSET (384 * 1024) #define CONFIG_ENV_OVERWRITE -- cgit v1.3.1 From 3fe0b104604e267aadc8d9197097421cc02ca103 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 Jan 2016 16:55:06 +0800 Subject: imx: mx6sxsabresd: add command and macros for boot m4 core Introduce macros and command to support booting M4 core for i.MX6SX SabreSD board. Signed-off-by: Ye.Li Signed-off-by: Peng Fan --- include/configs/mx6sxsabresd.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'include') diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 29e9c0898fc..fdf2396c148 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -26,7 +26,31 @@ #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE +#ifdef CONFIG_IMX_BOOTAUX +/* Set to QSPI2 B flash at default */ +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 +#define CONFIG_CMD_SETEXPR + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 1:0; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + #define CONFIG_EXTRA_ENV_SETTINGS \ + UPDATE_M4_ENV \ "script=boot.scr\0" \ "image=zImage\0" \ "console=ttymxc0\0" \ -- cgit v1.3.1 From 79e355fb685803a245c3f0165c07faa5a3fbf808 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Thu, 28 Jan 2016 16:55:08 +0800 Subject: imx: mx7dsabresd: add command and macros for boot m4 core Introduce macros and command to support booting M4 core for i.MX7D SabreSD board. Signed-off-by: Ye.Li Signed-off-by: Peng Fan --- include/configs/mx7dsabresd.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'include') diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index d23e4f3c407..2c981e0939f 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -57,6 +57,29 @@ #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 +#ifdef CONFIG_IMX_BOOTAUX +/* Set to QSPI1 A flash at default */ +#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 +#define CONFIG_CMD_SETEXPR + +#define UPDATE_M4_ENV \ + "m4image=m4_qspi.bin\0" \ + "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ + "update_m4_from_sd=" \ + "if sf probe 0:0; then " \ + "if run loadm4image; then " \ + "setexpr fw_sz ${filesize} + 0xffff; " \ + "setexpr fw_sz ${fw_sz} / 0x10000; " \ + "setexpr fw_sz ${fw_sz} * 0x10000; " \ + "sf erase 0x0 ${fw_sz}; " \ + "sf write ${loadaddr} 0x0 ${filesize}; " \ + "fi; " \ + "fi\0" \ + "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" +#else +#define UPDATE_M4_ENV "" +#endif + #define CONFIG_MFG_ENV_SETTINGS \ "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ "rdinit=/linuxrc " \ @@ -76,6 +99,7 @@ "rootfs part 0 2\0" \ #define CONFIG_EXTRA_ENV_SETTINGS \ + UPDATE_M4_ENV \ CONFIG_MFG_ENV_SETTINGS \ CONFIG_DFU_ENV_SETTINGS \ "script=boot.scr\0" \ -- cgit v1.3.1