From ef4547176d0fa4d43d060a58c0c902add7fe0aed Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Fri, 5 Sep 2014 19:02:47 +0300 Subject: dma: keystone_nav: move keystone_nav driver to driver/dma/ The keystone_nav is used by drivers/net/keystone_net.c driver to send and receive packets, but currently it's placed at keystone arch sources. So it should be in the drivers directory also. It's separate driver that can be used for sending and receiving pktdma packets by others drivers also. This patch just move this driver to appropriate directory and doesn't add any functional changes. Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- include/configs/k2hk_evm.h | 1 + include/configs/ks2_evm.h | 29 +++++++++++++++++++++++++++++ 2 files changed, 30 insertions(+) (limited to 'include') diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 8aa616da0e0..c3139075bc3 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -36,5 +36,6 @@ /* Network */ #define CONFIG_DRIVER_TI_KEYSTONE_NET +#define CONFIG_TI_KSNAV #endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index 51926f721f1..60f8ffd5623 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -104,6 +104,35 @@ #define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 #define CONFIG_SYS_SGMII_RATESCALE 2 +/* Keyston Navigator Configuration */ +#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS +#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE +#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE +#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE +#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE +#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE +#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE +#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE +#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE +#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE +#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE +#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE +#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM +#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM + +/* NETCP pktdma */ +#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE +#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE +#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM +#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE +#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM +#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE +#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE +#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM +#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE +#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE +#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE + /* AEMIF */ #define CONFIG_TI_AEMIF #define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE -- cgit v1.3.1 From 9ea9021ac466f5ccc8b6238cbce37428bb58f887 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Fri, 5 Sep 2014 19:02:48 +0300 Subject: dma: keystone_nav: generalize driver usage The keystone_nav driver is general driver intended to be used for working with queue manager and pktdma for different IPs like NETCP, AIF, FFTC, etc. So the it's API shouldn't be named like it works only with one of them, it should be general names. The names with prefix like netcp_* rather do for drivers/net/keystone_net.c driver. So it's good to generalize this driver to be used for different IP's and delete confusion with real NETCP driver. The current netcp_* functions of keystone navigator can be used for other settings of pktdma, not only for NETCP. The API of this driver is used by the keystone_net driver to work with NETCP, so net driver also should be corrected. For convenience collect pkdma configurations in drivers/dma/keystone_nav_cfg.c. Acked-by: Vitaly Andrianov Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/ti-common/keystone_nav.h | 12 ++- drivers/dma/Makefile | 2 +- drivers/dma/keystone_nav.c | 132 +++++++++++--------------- drivers/dma/keystone_nav_cfg.c | 27 ++++++ drivers/net/keystone_net.c | 13 +-- include/configs/k2hk_evm.h | 1 + 6 files changed, 98 insertions(+), 89 deletions(-) create mode 100644 drivers/dma/keystone_nav_cfg.c (limited to 'include') diff --git a/arch/arm/include/asm/ti-common/keystone_nav.h b/arch/arm/include/asm/ti-common/keystone_nav.h index 646c2f3a569..696d8c6fc09 100644 --- a/arch/arm/include/asm/ti-common/keystone_nav.h +++ b/arch/arm/include/asm/ti-common/keystone_nav.h @@ -169,6 +169,8 @@ struct pktdma_cfg { u32 rx_flow; /* flow that is used for RX */ }; +extern struct pktdma_cfg netcp_pktdma; + /* * packet dma user allocates memory for rx buffers * and describe it in the following structure @@ -180,10 +182,10 @@ struct rx_buff_desc { u32 rx_flow; }; -int netcp_close(void); -int netcp_init(struct rx_buff_desc *rx_buffers); -int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2); -void *netcp_recv(u32 **pkt, int *num_bytes); -void netcp_release_rxhd(void *hd); +int ksnav_close(struct pktdma_cfg *pktdma); +int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers); +int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2); +void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes); +void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd); #endif /* _KEYSTONE_NAV_H_ */ diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 519dd0d3475..15b0780b5d9 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -8,4 +8,4 @@ obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o obj-$(CONFIG_APBH_DMA) += apbh_dma.o obj-$(CONFIG_FSL_DMA) += fsl_dma.o -obj-$(CONFIG_TI_KSNAV) += keystone_nav.o +obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o diff --git a/drivers/dma/keystone_nav.c b/drivers/dma/keystone_nav.c index d960fbb2663..77707c21098 100644 --- a/drivers/dma/keystone_nav.c +++ b/drivers/dma/keystone_nav.c @@ -156,35 +156,20 @@ void queue_close(u32 qnum) /** * DMA API */ -struct pktdma_cfg netcp_pktdma = { - .global = (void *)CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE, - .tx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_TX_BASE, - .tx_ch_num = CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM, - .rx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_BASE, - .rx_ch_num = CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM, - .tx_sched = (u32 *)CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE, - .rx_flows = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE, - .rx_flow_num = CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM, - .rx_free_q = CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE, - .rx_rcv_q = CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE, - .tx_snd_q = CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE, -}; - -struct pktdma_cfg *netcp; -static int netcp_rx_disable(void) +static int ksnav_rx_disable(struct pktdma_cfg *pktdma) { u32 j, v, k; - for (j = 0; j < netcp->rx_ch_num; j++) { - v = readl(&netcp->rx_ch[j].cfg_a); + for (j = 0; j < pktdma->rx_ch_num; j++) { + v = readl(&pktdma->rx_ch[j].cfg_a); if (!(v & CPDMA_CHAN_A_ENABLE)) continue; - writel(v | CPDMA_CHAN_A_TDOWN, &netcp->rx_ch[j].cfg_a); + writel(v | CPDMA_CHAN_A_TDOWN, &pktdma->rx_ch[j].cfg_a); for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) { udelay(100); - v = readl(&netcp->rx_ch[j].cfg_a); + v = readl(&pktdma->rx_ch[j].cfg_a); if (!(v & CPDMA_CHAN_A_ENABLE)) continue; } @@ -192,33 +177,33 @@ static int netcp_rx_disable(void) } /* Clear all of the flow registers */ - for (j = 0; j < netcp->rx_flow_num; j++) { - writel(0, &netcp->rx_flows[j].control); - writel(0, &netcp->rx_flows[j].tags); - writel(0, &netcp->rx_flows[j].tag_sel); - writel(0, &netcp->rx_flows[j].fdq_sel[0]); - writel(0, &netcp->rx_flows[j].fdq_sel[1]); - writel(0, &netcp->rx_flows[j].thresh[0]); - writel(0, &netcp->rx_flows[j].thresh[1]); - writel(0, &netcp->rx_flows[j].thresh[2]); + for (j = 0; j < pktdma->rx_flow_num; j++) { + writel(0, &pktdma->rx_flows[j].control); + writel(0, &pktdma->rx_flows[j].tags); + writel(0, &pktdma->rx_flows[j].tag_sel); + writel(0, &pktdma->rx_flows[j].fdq_sel[0]); + writel(0, &pktdma->rx_flows[j].fdq_sel[1]); + writel(0, &pktdma->rx_flows[j].thresh[0]); + writel(0, &pktdma->rx_flows[j].thresh[1]); + writel(0, &pktdma->rx_flows[j].thresh[2]); } return QM_OK; } -static int netcp_tx_disable(void) +static int ksnav_tx_disable(struct pktdma_cfg *pktdma) { u32 j, v, k; - for (j = 0; j < netcp->tx_ch_num; j++) { - v = readl(&netcp->tx_ch[j].cfg_a); + for (j = 0; j < pktdma->tx_ch_num; j++) { + v = readl(&pktdma->tx_ch[j].cfg_a); if (!(v & CPDMA_CHAN_A_ENABLE)) continue; - writel(v | CPDMA_CHAN_A_TDOWN, &netcp->tx_ch[j].cfg_a); + writel(v | CPDMA_CHAN_A_TDOWN, &pktdma->tx_ch[j].cfg_a); for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) { udelay(100); - v = readl(&netcp->tx_ch[j].cfg_a); + v = readl(&pktdma->tx_ch[j].cfg_a); if (!(v & CPDMA_CHAN_A_ENABLE)) continue; } @@ -228,19 +213,17 @@ static int netcp_tx_disable(void) return QM_OK; } -static int _netcp_init(struct pktdma_cfg *netcp_cfg, - struct rx_buff_desc *rx_buffers) +int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers) { u32 j, v; struct qm_host_desc *hd; u8 *rx_ptr; - if (netcp_cfg == NULL || rx_buffers == NULL || + if (pktdma == NULL || rx_buffers == NULL || rx_buffers->buff_ptr == NULL || qm_cfg == NULL) return QM_ERR; - netcp = netcp_cfg; - netcp->rx_flow = rx_buffers->rx_flow; + pktdma->rx_flow = rx_buffers->rx_flow; /* init rx queue */ rx_ptr = rx_buffers->buff_ptr; @@ -250,69 +233,64 @@ static int _netcp_init(struct pktdma_cfg *netcp_cfg, if (hd == NULL) return QM_ERR; - qm_buff_push(hd, netcp->rx_free_q, + qm_buff_push(hd, pktdma->rx_free_q, rx_ptr, rx_buffers->buff_len); rx_ptr += rx_buffers->buff_len; } - netcp_rx_disable(); + ksnav_rx_disable(pktdma); /* configure rx channels */ - v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, netcp->rx_rcv_q); - writel(v, &netcp->rx_flows[netcp->rx_flow].control); - writel(0, &netcp->rx_flows[netcp->rx_flow].tags); - writel(0, &netcp->rx_flows[netcp->rx_flow].tag_sel); + v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, pktdma->rx_rcv_q); + writel(v, &pktdma->rx_flows[pktdma->rx_flow].control); + writel(0, &pktdma->rx_flows[pktdma->rx_flow].tags); + writel(0, &pktdma->rx_flows[pktdma->rx_flow].tag_sel); - v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, netcp->rx_free_q, 0, - netcp->rx_free_q); + v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, pktdma->rx_free_q, 0, + pktdma->rx_free_q); - writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[0]); - writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[1]); - writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[0]); - writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[1]); - writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[2]); + writel(v, &pktdma->rx_flows[pktdma->rx_flow].fdq_sel[0]); + writel(v, &pktdma->rx_flows[pktdma->rx_flow].fdq_sel[1]); + writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[0]); + writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[1]); + writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[2]); - for (j = 0; j < netcp->rx_ch_num; j++) - writel(CPDMA_CHAN_A_ENABLE, &netcp->rx_ch[j].cfg_a); + for (j = 0; j < pktdma->rx_ch_num; j++) + writel(CPDMA_CHAN_A_ENABLE, &pktdma->rx_ch[j].cfg_a); /* configure tx channels */ /* Disable loopback in the tx direction */ - writel(0, &netcp->global->emulation_control); + writel(0, &pktdma->global->emulation_control); /* Set QM base address, only for K2x devices */ - writel(CONFIG_KSNAV_QM_BASE_ADDRESS, &netcp->global->qm_base_addr[0]); + writel(CONFIG_KSNAV_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]); /* Enable all channels. The current state isn't important */ - for (j = 0; j < netcp->tx_ch_num; j++) { - writel(0, &netcp->tx_ch[j].cfg_b); - writel(CPDMA_CHAN_A_ENABLE, &netcp->tx_ch[j].cfg_a); + for (j = 0; j < pktdma->tx_ch_num; j++) { + writel(0, &pktdma->tx_ch[j].cfg_b); + writel(CPDMA_CHAN_A_ENABLE, &pktdma->tx_ch[j].cfg_a); } return QM_OK; } -int netcp_init(struct rx_buff_desc *rx_buffers) -{ - return _netcp_init(&netcp_pktdma, rx_buffers); -} - -int netcp_close(void) +int ksnav_close(struct pktdma_cfg *pktdma) { - if (!netcp) + if (!pktdma) return QM_ERR; - netcp_tx_disable(); - netcp_rx_disable(); + ksnav_tx_disable(pktdma); + ksnav_rx_disable(pktdma); - queue_close(netcp->rx_free_q); - queue_close(netcp->rx_rcv_q); - queue_close(netcp->tx_snd_q); + queue_close(pktdma->rx_free_q); + queue_close(pktdma->rx_rcv_q); + queue_close(pktdma->tx_snd_q); return QM_OK; } -int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2) +int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2) { struct qm_host_desc *hd; @@ -324,16 +302,16 @@ int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2) hd->swinfo[2] = swinfo2; hd->packet_info = qm_cfg->qpool_num; - qm_buff_push(hd, netcp->tx_snd_q, pkt, num_bytes); + qm_buff_push(hd, pktdma->tx_snd_q, pkt, num_bytes); return QM_OK; } -void *netcp_recv(u32 **pkt, int *num_bytes) +void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes) { struct qm_host_desc *hd; - hd = qm_pop(netcp->rx_rcv_q); + hd = qm_pop(pktdma->rx_rcv_q); if (!hd) return NULL; @@ -343,12 +321,12 @@ void *netcp_recv(u32 **pkt, int *num_bytes) return hd; } -void netcp_release_rxhd(void *hd) +void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd) { struct qm_host_desc *_hd = (struct qm_host_desc *)hd; _hd->buff_len = _hd->orig_buff_len; _hd->buff_ptr = _hd->orig_buff_ptr; - qm_push(_hd, netcp->rx_free_q); + qm_push(_hd, pktdma->rx_free_q); } diff --git a/drivers/dma/keystone_nav_cfg.c b/drivers/dma/keystone_nav_cfg.c new file mode 100644 index 00000000000..bdd30a02625 --- /dev/null +++ b/drivers/dma/keystone_nav_cfg.c @@ -0,0 +1,27 @@ +/* + * Multicore Navigator driver for TI Keystone 2 devices. + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#ifdef CONFIG_KSNAV_PKTDMA_NETCP +/* NETCP Pktdma */ +struct pktdma_cfg netcp_pktdma = { + .global = (void *)CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE, + .tx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_TX_BASE, + .tx_ch_num = CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM, + .rx_ch = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_BASE, + .rx_ch_num = CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM, + .tx_sched = (u32 *)CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE, + .rx_flows = (void *)CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE, + .rx_flow_num = CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM, + .rx_free_q = CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE, + .rx_rcv_q = CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE, + .tx_snd_q = CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE, +}; +#endif diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 1cfe6542d89..66532eef205 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -393,7 +393,8 @@ int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num) if (num_bytes < EMAC_MIN_ETHERNET_PKT_SIZE) num_bytes = EMAC_MIN_ETHERNET_PKT_SIZE; - return netcp_send(buffer, num_bytes, (slave_port_num) << 16); + return ksnav_send(&netcp_pktdma, buffer, + num_bytes, (slave_port_num) << 16); } /* Eth device open */ @@ -431,7 +432,7 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) printf("ERROR: qm_init()\n"); return -1; } - if (netcp_init(&net_rx_buffs)) { + if (ksnav_init(&netcp_pktdma, &net_rx_buffs)) { qm_close(); printf("ERROR: netcp_init()\n"); return -1; @@ -456,7 +457,7 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) link = keystone_get_link_status(dev); if (link == 0) { - netcp_close(); + ksnav_close(&netcp_pktdma); qm_close(); return -1; } @@ -483,7 +484,7 @@ void keystone2_eth_close(struct eth_device *dev) ethss_stop(); - netcp_close(); + ksnav_close(&netcp_pktdma); qm_close(); emac_open = 0; @@ -530,13 +531,13 @@ static int keystone2_eth_rcv_packet(struct eth_device *dev) int pkt_size; u32 *pkt; - hd = netcp_recv(&pkt, &pkt_size); + hd = ksnav_recv(&netcp_pktdma, &pkt, &pkt_size); if (hd == NULL) return 0; NetReceive((uchar *)pkt, pkt_size); - netcp_release_rxhd(hd); + ksnav_release_rxhd(&netcp_pktdma, hd); return pkt_size; } diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index c3139075bc3..d0c5ff17afd 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -37,5 +37,6 @@ /* Network */ #define CONFIG_DRIVER_TI_KEYSTONE_NET #define CONFIG_TI_KSNAV +#define CONFIG_KSNAV_PKTDMA_NETCP #endif /* __CONFIG_K2HK_EVM_H */ -- cgit v1.3.1 From bc0e8d7c5d189c1566a73affad0087ccbe511bc9 Mon Sep 17 00:00:00 2001 From: WingMan Kwok Date: Fri, 5 Sep 2014 22:26:23 +0300 Subject: keystone: usb: add support of usb xhci MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support of usb xhci. xHCI controls all USB speeds of the Host mode, that is, the SS through the SS PHY, as well as the HS, FS, and LS through the USB2 PHY. xHCI replaces and supersedes all previous host HCIs (HS-only EHCI, FS/LS OHCI and UHCI), and is therefore not backwards compatible with any of them. The USB3SS’s USB Controller is fully compliant with xHC. Acked-by: Vitaly Andrianov Signed-off-by: WingMan Kwok Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/arch-keystone/hardware.h | 6 + arch/arm/include/asm/arch-keystone/xhci-keystone.h | 21 ++ drivers/usb/host/Makefile | 1 + drivers/usb/host/xhci-keystone.c | 329 +++++++++++++++++++++ include/configs/ks2_evm.h | 15 + include/linux/usb/dwc3.h | 8 +- 6 files changed, 379 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-keystone/xhci-keystone.h create mode 100644 drivers/usb/host/xhci-keystone.c (limited to 'include') diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index ddc4be3b2ff..c1642a59a05 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -163,6 +163,12 @@ typedef volatile unsigned int *dv_reg_p; /* MSMC control */ #define KS2_MSMC_CTRL_BASE 0x0bc00000 +/* USB */ +#define KS2_USB_SS_BASE 0x02680000 +#define KS2_USB_HOST_XHCI_BASE (KS2_USB_SS_BASE + 0x10000) +#define KS2_DEV_USB_PHY_BASE 0x02620738 +#define KS2_USB_PHY_CFG_BASE 0x02630000 + #ifdef CONFIG_SOC_K2HK #include #endif diff --git a/arch/arm/include/asm/arch-keystone/xhci-keystone.h b/arch/arm/include/asm/arch-keystone/xhci-keystone.h new file mode 100644 index 00000000000..3aab4e045f1 --- /dev/null +++ b/arch/arm/include/asm/arch-keystone/xhci-keystone.h @@ -0,0 +1,21 @@ +/* + * USB 3.0 DRD Controller + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#define USB3_PHY_REF_SSP_EN BIT(29) +#define USB3_PHY_OTG_VBUSVLDECTSEL BIT(16) + +/* KEYSTONE2 XHCI PHY register structure */ +struct keystone_xhci_phy { + unsigned int phy_utmi; /* ctl0 */ + unsigned int phy_pipe; /* ctl1 */ + unsigned int phy_param_ctrl_1; /* ctl2 */ + unsigned int phy_param_ctrl_2; /* ctl3 */ + unsigned int phy_clock; /* ctl4 */ + unsigned int phy_pll; /* ctl5 */ +}; diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index c4f5157a843..3d3a0c42a5c 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -43,5 +43,6 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o # xhci obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o +obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o diff --git a/drivers/usb/host/xhci-keystone.c b/drivers/usb/host/xhci-keystone.c new file mode 100644 index 00000000000..05d338f261c --- /dev/null +++ b/drivers/usb/host/xhci-keystone.c @@ -0,0 +1,329 @@ +/* + * USB 3.0 DRD Controller + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "xhci.h" + +struct kdwc3_irq_regs { + u32 revision; /* 0x000 */ + u32 rsvd0[3]; + u32 sysconfig; /* 0x010 */ + u32 rsvd1[1]; + u32 irq_eoi; + u32 rsvd2[1]; + struct { + u32 raw_status; + u32 status; + u32 enable_set; + u32 enable_clr; + } irqs[16]; +}; + +struct keystone_xhci { + struct xhci_hccr *hcd; + struct dwc3 *dwc3_reg; + struct xhci_hcor *hcor; + struct kdwc3_irq_regs *usbss; + struct keystone_xhci_phy *phy; +}; + +struct keystone_xhci keystone; + +static void keystone_xhci_phy_set(struct keystone_xhci_phy *phy) +{ + u32 val; + + /* + * VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't. + * It should always be cleared because our USB PHY has an onchip VBUS + * analog comparator. + */ + val = readl(&phy->phy_clock); + /* quit selecting the vbusvldextsel by default! */ + val &= ~USB3_PHY_OTG_VBUSVLDECTSEL; + writel(val, &phy->phy_clock); +} + +static void keystone_xhci_phy_unset(struct keystone_xhci_phy *phy) +{ + u32 val; + + /* Disable the PHY REFCLK clock gate */ + val = readl(&phy->phy_clock); + val &= ~USB3_PHY_REF_SSP_EN; + writel(val, &phy->phy_clock); +} + +static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) +{ + clrsetbits_le32(&dwc3_reg->g_ctl, + DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), + DWC3_GCTL_PRTCAPDIR(mode)); +} + +static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg) +{ + /* Before Resetting PHY, put Core in Reset */ + setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); + + /* Assert USB3 PHY reset */ + setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); + + /* Assert USB2 PHY reset */ + setbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST); + + mdelay(100); + + /* Clear USB3 PHY reset */ + clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST); + + /* Clear USB2 PHY reset */ + clrbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST); + + /* After PHYs are stable we can take Core out of reset state */ + clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET); +} + +static int dwc3_core_init(struct dwc3 *dwc3_reg) +{ + u32 revision, val; + unsigned long t_rst; + unsigned int dwc3_hwparams1; + + revision = readl(&dwc3_reg->g_snpsid); + /* This should read as U3 followed by revision number */ + if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) { + puts("this is not a DesignWare USB3 DRD Core\n"); + return -EINVAL; + } + + /* issue device SoftReset too */ + writel(DWC3_DCTL_CSFTRST, &dwc3_reg->d_ctl); + + t_rst = get_timer(0); + do { + val = readl(&dwc3_reg->d_ctl); + if (!(val & DWC3_DCTL_CSFTRST)) + break; + WATCHDOG_RESET(); + } while (get_timer(t_rst) < 500); + + if (val & DWC3_DCTL_CSFTRST) { + debug("Reset timed out\n"); + return -2; + } + + dwc3_core_soft_reset(dwc3_reg); + + dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1); + + val = readl(&dwc3_reg->g_ctl); + val &= ~DWC3_GCTL_SCALEDOWN_MASK; + val &= ~DWC3_GCTL_DISSCRAMBLE; + switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) { + case DWC3_GHWPARAMS1_EN_PWROPT_CLK: + val &= ~DWC3_GCTL_DSBLCLKGTNG; + break; + default: + printf("No power optimization available\n"); + } + + /* + * WORKAROUND: DWC3 revisions <1.90a have a bug + * where the device can fail to connect at SuperSpeed + * and falls back to high-speed mode which causes + * the device to enter a Connect/Disconnect loop + */ + if ((revision & DWC3_REVISION_MASK) < 0x190a) + val |= DWC3_GCTL_U2RSTECN; + + writel(val, &dwc3_reg->g_ctl); + + return 0; +} + +static int keystone_xhci_core_init(struct dwc3 *dwc3_reg) +{ + int ret; + + ret = dwc3_core_init(dwc3_reg); + if (ret) { + debug("failed to initialize core\n"); + return -EINVAL; + } + + /* We are hard-coding DWC3 core to Host Mode */ + dwc3_set_mode(dwc3_reg, DWC3_GCTL_PRTCAP_HOST); + + return 0; +} + +int xhci_hcd_init(int index, + struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor) +{ + u32 val; + int ret; + struct xhci_hccr *hcd; + struct xhci_hcor *hcor; + struct kdwc3_irq_regs *usbss; + struct keystone_xhci_phy *phy; + + usbss = (struct kdwc3_irq_regs *)CONFIG_USB_SS_BASE; + phy = (struct keystone_xhci_phy *)CONFIG_DEV_USB_PHY_BASE; + + /* Enable the PHY REFCLK clock gate with phy_ref_ssp_en = 1 */ + val = readl(&(phy->phy_clock)); + val |= USB3_PHY_REF_SSP_EN; + writel(val, &phy->phy_clock); + + mdelay(100); + + /* Release USB from reset */ + ret = psc_enable_module(KS2_LPSC_USB); + if (ret) { + puts("Cannot enable USB module"); + return -1; + } + + mdelay(100); + + /* Initialize usb phy */ + keystone_xhci_phy_set(phy); + + /* soft reset usbss */ + writel(1, &usbss->sysconfig); + while (readl(&usbss->sysconfig) & 1) + ; + + val = readl(&usbss->revision); + debug("usbss revision %x\n", val); + + /* Initialize usb core */ + hcd = (struct xhci_hccr *)CONFIG_USB_HOST_XHCI_BASE; + keystone.dwc3_reg = (struct dwc3 *)(CONFIG_USB_HOST_XHCI_BASE + + DWC3_REG_OFFSET); + + keystone_xhci_core_init(keystone.dwc3_reg); + + /* set register addresses */ + hcor = (struct xhci_hcor *)((uint32_t)hcd + + HC_LENGTH(readl(&hcd->cr_capbase))); + + debug("Keystone2-xhci: init hccr %08x and hcor %08x hc_length %d\n", + (u32)hcd, (u32)hcor, + (u32)HC_LENGTH(xhci_readl(&hcd->cr_capbase))); + + keystone.usbss = usbss; + keystone.phy = phy; + keystone.hcd = hcd; + keystone.hcor = hcor; + + *ret_hccr = hcd; + *ret_hcor = hcor; + + return 0; +} + +static int keystone_xhci_phy_suspend(void) +{ + int loop_cnt = 0; + struct xhci_hcor *hcor; + uint32_t *portsc_1 = NULL; + uint32_t *portsc_2 = NULL; + u32 val, usb2_pls, usb3_pls, event_q; + struct dwc3 *dwc3_reg = keystone.dwc3_reg; + + /* set register addresses */ + hcor = keystone.hcor; + + /* Bypass Scrambling and Set Shorter Training sequence for simulation */ + val = DWC3_GCTL_PWRDNSCALE(0x4b0) | DWC3_GCTL_PRTCAPDIR(0x2); + writel(val, &dwc3_reg->g_ctl); + + /* GUSB2PHYCFG */ + val = readl(&dwc3_reg->g_usb2phycfg[0]); + + /* assert bit 6 (SusPhy) */ + val |= DWC3_GUSB2PHYCFG_SUSPHY; + writel(val, &dwc3_reg->g_usb2phycfg[0]); + + /* GUSB3PIPECTL */ + val = readl(&dwc3_reg->g_usb3pipectl[0]); + + /* + * assert bit 29 to allow PHY to go to suspend when idle + * and cause the USB3 SS PHY to enter suspend mode + */ + val |= (BIT(29) | DWC3_GUSB3PIPECTL_SUSPHY); + writel(val, &dwc3_reg->g_usb3pipectl[0]); + + /* + * Steps necessary to allow controller to suspend even when + * VBUS is HIGH: + * - Init DCFG[2:0] (DevSpd) to: 1=FS + * - Init GEVNTADR0 to point to an eventQ + * - Init GEVNTSIZ0 to 0x0100 to specify the size of the eventQ + * - Init DCTL::Run_nStop = 1 + */ + writel(0x00020001, &dwc3_reg->d_cfg); + /* TODO: local2global( (Uint32) eventQ )? */ + writel((u32)&event_q, &dwc3_reg->g_evnt_buf[0].g_evntadrlo); + writel(0, &dwc3_reg->g_evnt_buf[0].g_evntadrhi); + writel(0x4, &dwc3_reg->g_evnt_buf[0].g_evntsiz); + /* Run */ + writel(DWC3_DCTL_RUN_STOP, &dwc3_reg->d_ctl); + + mdelay(100); + + /* Wait for USB2 & USB3 PORTSC::PortLinkState to indicate suspend */ + portsc_1 = (uint32_t *)(&hcor->portregs[0].or_portsc); + portsc_2 = (uint32_t *)(&hcor->portregs[1].or_portsc); + usb2_pls = 0; + usb3_pls = 0; + do { + ++loop_cnt; + usb2_pls = (readl(portsc_1) & PORT_PLS_MASK) >> 5; + usb3_pls = (readl(portsc_2) & PORT_PLS_MASK) >> 5; + } while (((usb2_pls != 0x4) || (usb3_pls != 0x4)) && loop_cnt < 1000); + + if (usb2_pls != 0x4 || usb3_pls != 0x4) { + debug("USB suspend failed - PLS USB2=%02x, USB3=%02x\n", + usb2_pls, usb3_pls); + return -1; + } + + debug("USB2 and USB3 PLS - Disabled, loop_cnt=%d\n", loop_cnt); + return 0; +} + +void xhci_hcd_stop(int index) +{ + /* Disable USB */ + if (keystone_xhci_phy_suspend()) + return; + + if (psc_disable_module(KS2_LPSC_USB)) { + debug("PSC disable module USB failed!\n"); + return; + } + + /* Disable PHY */ + keystone_xhci_phy_unset(keystone.phy); + +/* memset(&keystone, 0, sizeof(struct keystone_xhci)); */ + debug("xhci_hcd_stop OK.\n"); +} diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index 60f8ffd5623..21646175841 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -183,6 +183,20 @@ "1024k(bootloader)ro,512k(params)ro," \ "-(ubifs)" +/* USB Configuration */ +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_KEYSTONE +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_FS_FAT +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_USB_SS_BASE KS2_USB_SS_BASE +#define CONFIG_USB_HOST_XHCI_BASE KS2_USB_HOST_XHCI_BASE +#define CONFIG_DEV_USB_PHY_BASE KS2_DEV_USB_PHY_BASE +#define CONFIG_USB_PHY_CFG_BASE KS2_USB_PHY_CFG_BASE + /* U-Boot command configuration */ #include #define CONFIG_CMD_ASKENV @@ -196,6 +210,7 @@ #define CONFIG_CMD_UBIFS #define CONFIG_CMD_SF #define CONFIG_CMD_EEPROM +#define CONFIG_CMD_USB /* U-Boot general configuration */ #define CONFIG_SYS_GENERIC_BOARD diff --git a/include/linux/usb/dwc3.h b/include/linux/usb/dwc3.h index 97d179a6e9e..7edc760c7b2 100644 --- a/include/linux/usb/dwc3.h +++ b/include/linux/usb/dwc3.h @@ -41,7 +41,8 @@ #define DWC3_REG_OFFSET 0xC100 struct g_event_buffer { - u64 g_evntadr; + u32 g_evntadrlo; + u32 g_evntadrhi; u32 g_evntsiz; u32 g_evntcount; }; @@ -185,4 +186,9 @@ struct dwc3 { /* offset: 0xC100 */ #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff) #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000) +/* Device Control Register */ +#define DWC3_DCTL_RUN_STOP (1 << 31) +#define DWC3_DCTL_CSFTRST (1 << 30) +#define DWC3_DCTL_LSFTRST (1 << 29) + #endif /* __DWC3_H_ */ -- cgit v1.3.1 From 345af534561a2c111ef1160cb8f25ba787d7e949 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 22 Oct 2014 16:32:33 +0300 Subject: keystone2: k2l-evm: add board support This patch adds Keystone II Lammar (K2L) EVM board support. Acked-by: Vitaly Andrianov Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/Kconfig | 3 ++ arch/arm/include/asm/arch-keystone/clock-k2l.h | 6 +++ board/ti/ks2_evm/Kconfig | 16 ++++++ board/ti/ks2_evm/MAINTAINERS | 2 + board/ti/ks2_evm/Makefile | 2 + board/ti/ks2_evm/board_k2l.c | 72 ++++++++++++++++++++++++++ board/ti/ks2_evm/ddr3_cfg.c | 36 +++++++++++++ board/ti/ks2_evm/ddr3_cfg.h | 3 ++ board/ti/ks2_evm/ddr3_k2l.c | 38 ++++++++++++++ configs/k2l_evm_defconfig | 4 ++ include/configs/k2l_evm.h | 37 +++++++++++++ 11 files changed, 219 insertions(+) create mode 100644 board/ti/ks2_evm/board_k2l.c create mode 100644 board/ti/ks2_evm/ddr3_k2l.c create mode 100644 configs/k2l_evm_defconfig create mode 100644 include/configs/k2l_evm.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/keystone/Kconfig b/arch/arm/cpu/armv7/keystone/Kconfig index 8249b5e2703..393885f710d 100644 --- a/arch/arm/cpu/armv7/keystone/Kconfig +++ b/arch/arm/cpu/armv7/keystone/Kconfig @@ -9,6 +9,9 @@ config TARGET_K2HK_EVM config TARGET_K2E_EVM bool "TI Keystone 2 Edison EVM" +config TARGET_K2L_EVM + bool "TI Keystone 2 Lamar EVM" + endchoice config SYS_CPU diff --git a/arch/arm/include/asm/arch-keystone/clock-k2l.h b/arch/arm/include/asm/arch-keystone/clock-k2l.h index ad2e40747ad..bb9a5c4dcf3 100644 --- a/arch/arm/include/asm/arch-keystone/clock-k2l.h +++ b/arch/arm/include/asm/arch-keystone/clock-k2l.h @@ -70,7 +70,9 @@ enum { #define CORE_PLL_799 {CORE_PLL, 13, 1, 2} #define CORE_PLL_983 {CORE_PLL, 16, 1, 2} +#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2} #define CORE_PLL_1167 {CORE_PLL, 19, 1, 2} +#define CORE_PLL_1198 {CORE_PLL, 39, 2, 2} #define CORE_PLL_1228 {CORE_PLL, 20, 1, 2} #define PASS_PLL_1228 {PASS_PLL, 20, 1, 2} #define PASS_PLL_983 {PASS_PLL, 16, 1, 2} @@ -79,8 +81,12 @@ enum { #define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2} #define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2} #define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2} +#define TETRIS_PLL_1000 {TETRIS_PLL, 114, 7, 2} #define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2} +#define TETRIS_PLL_1198 {TETRIS_PLL, 39, 2, 2} #define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2} +#define TETRIS_PLL_1352 {TETRIS_PLL, 22, 1, 2} +#define TETRIS_PLL_1401 {TETRIS_PLL, 114, 5, 2} #define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2} #define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4} #define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2} diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig index 9c1e103a20f..96c5f22eade 100644 --- a/board/ti/ks2_evm/Kconfig +++ b/board/ti/ks2_evm/Kconfig @@ -23,3 +23,19 @@ config SYS_CONFIG_NAME default "k2hk_evm" endif + +if TARGET_K2L_EVM + +config SYS_BOARD + string + default "ks2_evm" + +config SYS_VENDOR + string + default "ti" + +config SYS_CONFIG_NAME + string + default "k2l_evm" + +endif diff --git a/board/ti/ks2_evm/MAINTAINERS b/board/ti/ks2_evm/MAINTAINERS index 595a80a8bc6..87c36c9d14a 100644 --- a/board/ti/ks2_evm/MAINTAINERS +++ b/board/ti/ks2_evm/MAINTAINERS @@ -6,3 +6,5 @@ F: include/configs/k2hk_evm.h F: configs/k2hk_evm_defconfig F: include/configs/k2e_evm.h F: configs/k2e_evm_defconfig +F: include/configs/k2l_evm.h +F: configs/k2l_evm_defconfig diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile index 00f1164833c..071dbee180a 100644 --- a/board/ti/ks2_evm/Makefile +++ b/board/ti/ks2_evm/Makefile @@ -11,3 +11,5 @@ obj-$(CONFIG_K2HK_EVM) += board_k2hk.o obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o obj-$(CONFIG_K2E_EVM) += board_k2e.o obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o +obj-$(CONFIG_K2L_EVM) += board_k2l.o +obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c new file mode 100644 index 00000000000..559d20ca88e --- /dev/null +++ b/board/ti/ks2_evm/board_k2l.c @@ -0,0 +1,72 @@ +/* + * K2L EVM : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = 122880000, + [alt_core_clk] = 100000000, + [pa_clk] = 122880000, + [tetris_clk] = 122880000, + [ddr3_clk] = 100000000, + [pcie_clk] = 100000000, + [sgmii_clk] = 156250000, + [usb_clk] = 100000000, +}; + +static struct pll_init_data core_pll_config[] = { + CORE_PLL_799, + CORE_PLL_1000, + CORE_PLL_1198, +}; + +static struct pll_init_data tetris_pll_config[] = { + TETRIS_PLL_799, + TETRIS_PLL_1000, + TETRIS_PLL_1198, + TETRIS_PLL_1352, + TETRIS_PLL_1401, +}; + +static struct pll_init_data pa_pll_config = + PASS_PLL_983; + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + int speed; + + speed = get_max_dev_speed(); + init_pll(&core_pll_config[speed]); + + init_pll(&pa_pll_config); + + speed = get_max_arm_speed(); + init_pll(&tetris_pll_config[speed]); + + return 0; +} +#endif + +#ifdef CONFIG_SPL_BUILD +static struct pll_init_data spl_pll_config[] = { + CORE_PLL_799, + TETRIS_PLL_491, +}; + +void spl_init_keystone_plls(void) +{ + init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config); +} +#endif diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c index f7da9f2bcba..ab44676793c 100644 --- a/board/ti/ks2_evm/ddr3_cfg.c +++ b/board/ti/ks2_evm/ddr3_cfg.c @@ -133,6 +133,42 @@ struct ddr3_emif_config ddr3_1600_4g = { }; #endif +struct ddr3_phy_config ddr3phy_1600_2g = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x9D5CBB66ul, + .dtpr1 = 0x12868300ul, + .dtpr2 = 0x5002D200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +struct ddr3_emif_config ddr3_1600_2g = { + .sdcfg = 0x6200CE62ul, + .sdtim1 = 0x166C9855ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x435DFF53ul, + .sdtim4 = 0x543F0CFFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001869ul, +}; + int ddr3_get_dimm_params(char *dimm_name) { int ret; diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h index 15fcf52ef19..5bd786cff8e 100644 --- a/board/ti/ks2_evm/ddr3_cfg.h +++ b/board/ti/ks2_evm/ddr3_cfg.h @@ -19,6 +19,9 @@ extern struct ddr3_emif_config ddr3_1333_2g; extern struct ddr3_phy_config ddr3phy_1600_4g; extern struct ddr3_emif_config ddr3_1600_4g; +extern struct ddr3_phy_config ddr3phy_1600_2g; +extern struct ddr3_emif_config ddr3_1600_2g; + int ddr3_get_dimm_params(char *dimm_name); #endif /* __DDR3_CFG_H */ diff --git a/board/ti/ks2_evm/ddr3_k2l.c b/board/ti/ks2_evm/ddr3_k2l.c new file mode 100644 index 00000000000..15a14f2aafe --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2l.c @@ -0,0 +1,38 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include "ddr3_cfg.h" +#include + +static int ddr3_size; +static struct pll_init_data ddr3_400 = DDR3_PLL_400; + +void ddr3_init(void) +{ + init_pll(&ddr3_400); + + /* No SO-DIMM, 2GB discreet DDR */ + printf("DRAM: 2 GiB\n"); + ddr3_size = 2; + + /* Reset DDR3 PHY after PLL enabled */ + ddr3_reset_ddrphy(); + + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g); +} + +/** + * ddr3_get_size - return ddr3 size in GiB + */ +int ddr3_get_size(void) +{ + return ddr3_size; +} diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig new file mode 100644 index 00000000000..45399cea6b7 --- /dev/null +++ b/configs/k2l_evm_defconfig @@ -0,0 +1,4 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_KEYSTONE=y ++S:CONFIG_TARGET_K2L_EVM=y diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h new file mode 100644 index 00000000000..0e1f7251b3a --- /dev/null +++ b/include/configs/k2l_evm.h @@ -0,0 +1,37 @@ +/* + * Configuration header file for TI's k2l-evm + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_K2L_EVM_H +#define __CONFIG_K2L_EVM_H + +/* Platform type */ +#define CONFIG_SOC_K2L +#define CONFIG_K2L_EVM + +/* U-Boot general configuration */ +#define CONFIG_SYS_PROMPT "K2L EVM # " + +#define KS2_ARGS_UBI "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs "\ + "root=ubi0:rootfs rootflags=sync rw ubi.mtd=2,4096\0" + +#define KS2_FDT_NAME "name_fdt=k2l-evm.dtb\0" +#define KS2_ADDR_MON "addr_mon=0x0c140000\0" +#define KS2_NAME_MON "name_mon=skern-k2l-evm.bin\0" +#define NAME_UBOOT "name_uboot=u-boot-spi-k2l-evm.gph\0" +#define NAME_UBI "name_ubi=k2l-evm-ubifs.ubi\0" + +#include + +/* SPL SPI Loader Configuration */ +#define CONFIG_SPL_TEXT_BASE 0x0c100000 + +/* NAND Configuration */ +#define CONFIG_SYS_NAND_PAGE_4K + +#endif /* __CONFIG_K2L_EVM_H */ -- cgit v1.3.1 From 8347210a3f158f0d40ced048673d8602802ed9cc Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Fri, 26 Sep 2014 15:42:30 +0300 Subject: configs: ks2_evm: enable misc_init_r Currently keystone has misc_init_r where all DSPS are turned off by default. So enable this function. Signed-off-by: Ivan Khoronzhuk --- include/configs/ks2_evm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index 21646175841..6e6755a314d 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -214,6 +214,7 @@ /* U-Boot general configuration */ #define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_MISC_INIT_R #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_PBSIZE 2048 #define CONFIG_SYS_MAXARGS 16 -- cgit v1.3.1 From e3114c9a06e4c4a1fd93967288e28f6f0d61f49d Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Mon, 29 Sep 2014 22:17:21 +0300 Subject: net: keystone_net: add support for NETCP v1.5 Currently the network driver is used only by k2hk evm board. The k2hk SoC contains NETCP v1.0, but Keystone2 SoCs, like k2e contain NETCP v1.5. So driver should be able to work with such kind of NETCP. This commit adds this opportunity. The main difference in masks and some registers, the logic is the same, so only definitions should be changed. To differentiate between versions add KS2_NETCP_V1_0 and KS2_NETCP_V1_5. Also remove unused and no more needed defines. The port number is specific for each board so move this parameter to configuration. Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/arch-keystone/emac_defs.h | 156 +++++++++++++-------- arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 3 + include/configs/k2hk_evm.h | 1 + 3 files changed, 98 insertions(+), 62 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-keystone/emac_defs.h b/arch/arm/include/asm/arch-keystone/emac_defs.h index 47e0ada9074..34502460418 100644 --- a/arch/arm/include/asm/arch-keystone/emac_defs.h +++ b/arch/arm/include/asm/arch-keystone/emac_defs.h @@ -13,20 +13,44 @@ #include #include +/* EMAC */ +#ifdef KS2_NETCP_V1_0 + #define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900) #define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300) #define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100) +#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x)*0x040) + +/* Register offsets */ +#define CPGMACSL_REG_CTL 0x04 +#define CPGMACSL_REG_STATUS 0x08 +#define CPGMACSL_REG_RESET 0x0c +#define CPGMACSL_REG_MAXLEN 0x10 + +#elif defined KS2_NETCP_V1_5 + +#define CPGMACSL_REG_RX_PRI_MAP 0x020 +#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00222000) +#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00200f00) +#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00200100) +#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000) + +/* Register offsets */ +#define CPGMACSL_REG_CTL 0x330 +#define CPGMACSL_REG_STATUS 0x334 +#define CPGMACSL_REG_RESET 0x338 +#define CPGMACSL_REG_MAXLEN 0x024 + +#endif #define KEYSTONE2_EMAC_GIG_ENABLE #define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110) -#ifdef CONFIG_SOC_K2HK /* MDIO module input frequency */ #define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk)) /* MDIO clock output frequency */ #define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */ -#endif /* MII Status Register */ #define MII_STATUS_REG 1 @@ -86,17 +110,8 @@ struct mac_sl_cfg { #define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3 #define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4 -/* Register offsets */ -#define CPGMACSL_REG_ID 0x00 -#define CPGMACSL_REG_CTL 0x04 -#define CPGMACSL_REG_STATUS 0x08 -#define CPGMACSL_REG_RESET 0x0c -#define CPGMACSL_REG_MAXLEN 0x10 -#define CPGMACSL_REG_BOFF 0x14 -#define CPGMACSL_REG_RX_PAUSE 0x18 -#define CPGMACSL_REG_TX_PAURSE 0x1c -#define CPGMACSL_REG_EM_CTL 0x20 -#define CPGMACSL_REG_PRI 0x24 +/* EMAC SL register definitions */ +#define DEVICE_EMACSL_RESET_POLL_COUNT 100 /* Soft reset register values */ #define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0) @@ -105,6 +120,7 @@ struct mac_sl_cfg { /* Maxlen register values */ #define CPGMAC_REG_MAXLEN_LEN 0x3fff +/* CPSW */ /* Control bitfields */ #define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5) #define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4) @@ -113,24 +129,39 @@ struct mac_sl_cfg { #define CPSW_CTL_VLAN_AWARE (1 << 1) #define CPSW_CTL_FIFO_LOOPBACK (1 << 0) -#define DEVICE_CPSW_NUM_PORTS 5 /* 5 switch ports */ -#define DEVICE_CPSW_BASE (0x02090800) -#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */ -#define SWITCH_MAX_PKT_SIZE 9000 +#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS +#define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1) + +#ifdef KS2_NETCP_V1_0 + +#define DEVICE_CPSW_BASE (KS2_PASS_BASE + 0x00090800) +#define CPSW_REG_CTL 0x004 +#define CPSW_REG_STAT_PORT_EN 0x00c +#define CPSW_REG_MAXLEN 0x040 +#define CPSW_REG_ALE_CONTROL 0x608 +#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4) +#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf + +#elif defined KS2_NETCP_V1_5 + +#define DEVICE_CPSW_BASE (KS2_PASS_BASE + 0x00220000) +#define CPSW_REG_CTL 0x00004 +#define CPSW_REG_STAT_PORT_EN 0x00014 +#define CPSW_REG_MAXLEN 0x01024 +#define CPSW_REG_ALE_CONTROL 0x1e008 +#define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4) +#define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff + +#endif -/* Register offsets */ -#define CPSW_REG_CTL 0x004 -#define CPSW_REG_STAT_PORT_EN 0x00c -#define CPSW_REG_MAXLEN 0x040 -#define CPSW_REG_ALE_CONTROL 0x608 -#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4) - -/* Register values */ -#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf #define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000) #define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010) #define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3 +#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */ +#define SWITCH_MAX_PKT_SIZE 9000 + +/* SGMII */ #define SGMII_REG_STATUS_LOCK BIT(4) #define SGMII_REG_STATUS_LINK BIT(0) #define SGMII_REG_STATUS_AUTONEG BIT(2) @@ -147,40 +178,46 @@ struct mac_sl_cfg { #define SGMII_LINK_MAC_FIBER 3 #define SGMII_LINK_MAC_PHY_FORCED 4 -#define TARGET_SGMII_BASE KS2_PASS_BASE + 0x00090100 -#define TARGET_SGMII_BASE_ADDRESSES {KS2_PASS_BASE + 0x00090100, \ - KS2_PASS_BASE + 0x00090200, \ - KS2_PASS_BASE + 0x00090400, \ - KS2_PASS_BASE + 0x00090500} - +#ifdef KS2_NETCP_V1_0 #define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100)) - -/* - * SGMII registers - */ -#define SGMII_IDVER_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x000) -#define SGMII_SRESET_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x004) -#define SGMII_CTL_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x010) -#define SGMII_STATUS_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x014) -#define SGMII_MRADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x018) -#define SGMII_LPADV_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x020) -#define SGMII_TXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x030) -#define SGMII_RXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x034) -#define SGMII_AUXCFG_REG(x) (TARGET_SGMII_BASE + SGMII_OFFSET(x) + 0x038) - -#define DEVICE_EMACSL_BASE(x) (KS2_PASS_BASE + 0x00090900 + (x) * 0x040) -#define DEVICE_N_GMACSL_PORTS 4 -#define DEVICE_EMACSL_RESET_POLL_COUNT 100 - -#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604) - -#ifdef CONFIG_SOC_K2HK -#define DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI 0x06060606 +#elif defined KS2_NETCP_V1_5 +#define SGMII_OFFSET(x) ((x) * 0x100) #endif -#define hw_config_streaming_switch() \ - writel(DEVICE_PSTREAM_CFG_REG_VAL_ROUTE_CPPI,\ - DEVICE_PSTREAM_CFG_REG_ADDR); +#define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000) +#define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004) +#define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010) +#define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014) +#define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018) +#define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020) +#define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030) +#define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034) +#define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038) + +/* PSS */ +#ifdef KS2_NETCP_V1_0 + +#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604) +#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606 +#define hw_config_streaming_switch()\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR); + +#elif defined KS2_NETCP_V1_5 + +#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x500) +#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0 + +#define hw_config_streaming_switch()\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+4);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+8);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+12); + +#endif /* EMAC MDIO Registers Structure */ struct mdio_regs { @@ -202,9 +239,6 @@ struct mdio_regs { dv_reg userphysel1; }; -#define SGMII_ACCESS(port, reg) \ - *((volatile unsigned int *)(sgmiis[port] + reg)) - struct eth_priv_t { char int_name[32]; int rx_flow; @@ -213,8 +247,6 @@ struct eth_priv_t { int sgmii_link_type; }; -extern struct eth_priv_t eth_priv_cfg[]; - int keystone2_emac_initialize(struct eth_priv_t *eth_priv); void sgmii_serdes_setup_156p25mhz(void); void sgmii_serdes_shutdown(void); diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index 2db806c37fa..6cfed3aff9e 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -95,4 +95,7 @@ #define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002 #define KS2_NETCP_PDMA_TX_SND_QUEUE 648 +/* NETCP version */ +#define KS2_NETCP_V1_0 + #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index d0c5ff17afd..15cebb97182 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -38,5 +38,6 @@ #define CONFIG_DRIVER_TI_KEYSTONE_NET #define CONFIG_TI_KSNAV #define CONFIG_KSNAV_PKTDMA_NETCP +#define CONFIG_KSNET_CPSW_NUM_PORTS 5 #endif /* __CONFIG_K2HK_EVM_H */ -- cgit v1.3.1 From 0935cac6855626f9de6af9583a30b6463e8bab95 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Mon, 29 Sep 2014 22:17:22 +0300 Subject: net: keystone_net: move header file from arch to ti-common The header file for the driver should be in correct place. So move it to "arch/arm/include/asm/ti-common/keystone_net.h" and correct driver's external dependencies. At the same time align and correct some definitions. Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/arch-keystone/emac_defs.h | 254 --------------------- arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 4 +- arch/arm/include/asm/arch-keystone/hardware.h | 2 + arch/arm/include/asm/ti-common/keystone_net.h | 248 ++++++++++++++++++++ board/ti/ks2_evm/board.c | 2 +- board/ti/ks2_evm/board.h | 2 +- board/ti/ks2_evm/board_k2hk.c | 2 +- drivers/net/keystone_net.c | 2 +- include/configs/k2hk_evm.h | 1 + include/configs/ks2_evm.h | 4 + 10 files changed, 261 insertions(+), 260 deletions(-) delete mode 100644 arch/arm/include/asm/arch-keystone/emac_defs.h create mode 100644 arch/arm/include/asm/ti-common/keystone_net.h (limited to 'include') diff --git a/arch/arm/include/asm/arch-keystone/emac_defs.h b/arch/arm/include/asm/arch-keystone/emac_defs.h deleted file mode 100644 index 34502460418..00000000000 --- a/arch/arm/include/asm/arch-keystone/emac_defs.h +++ /dev/null @@ -1,254 +0,0 @@ -/* - * emac definitions for keystone2 devices - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _EMAC_DEFS_H_ -#define _EMAC_DEFS_H_ - -#include -#include - -/* EMAC */ -#ifdef KS2_NETCP_V1_0 - -#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00090900) -#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00090300) -#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00090100) -#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x)*0x040) - -/* Register offsets */ -#define CPGMACSL_REG_CTL 0x04 -#define CPGMACSL_REG_STATUS 0x08 -#define CPGMACSL_REG_RESET 0x0c -#define CPGMACSL_REG_MAXLEN 0x10 - -#elif defined KS2_NETCP_V1_5 - -#define CPGMACSL_REG_RX_PRI_MAP 0x020 -#define EMAC_EMACSL_BASE_ADDR (KS2_PASS_BASE + 0x00222000) -#define EMAC_MDIO_BASE_ADDR (KS2_PASS_BASE + 0x00200f00) -#define EMAC_SGMII_BASE_ADDR (KS2_PASS_BASE + 0x00200100) -#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000) - -/* Register offsets */ -#define CPGMACSL_REG_CTL 0x330 -#define CPGMACSL_REG_STATUS 0x334 -#define CPGMACSL_REG_RESET 0x338 -#define CPGMACSL_REG_MAXLEN 0x024 - -#endif - -#define KEYSTONE2_EMAC_GIG_ENABLE - -#define MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110) - -/* MDIO module input frequency */ -#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk)) -/* MDIO clock output frequency */ -#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */ - -/* MII Status Register */ -#define MII_STATUS_REG 1 -#define MII_STATUS_LINK_MASK (0x4) - -/* Marvell 88E1111 PHY ID */ -#define PHY_MARVELL_88E1111 (0x01410cc0) - -#define MDIO_CONTROL_IDLE (0x80000000) -#define MDIO_CONTROL_ENABLE (0x40000000) -#define MDIO_CONTROL_FAULT_ENABLE (0x40000) -#define MDIO_CONTROL_FAULT (0x80000) -#define MDIO_USERACCESS0_GO (0x80000000) -#define MDIO_USERACCESS0_WRITE_READ (0x0) -#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) -#define MDIO_USERACCESS0_ACK (0x20000000) - -#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) -#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) -#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) -#define EMAC_MACCONTROL_GIGFORCE (1 << 17) -#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) - -#define EMAC_MIN_ETHERNET_PKT_SIZE 60 - -struct mac_sl_cfg { - u_int32_t max_rx_len; /* Maximum receive packet length. */ - u_int32_t ctl; /* Control bitfield */ -}; - -/* - * Definition: Control bitfields used in the ctl field of hwGmacSlCfg_t - */ -#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES (1 << 24) -#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES (1 << 23) -#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES (1 << 22) -#define GMACSL_RX_ENABLE_EXT_CTL (1 << 18) -#define GMACSL_RX_ENABLE_GIG_FORCE (1 << 17) -#define GMACSL_RX_ENABLE_IFCTL_B (1 << 16) -#define GMACSL_RX_ENABLE_IFCTL_A (1 << 15) -#define GMACSL_RX_ENABLE_CMD_IDLE (1 << 11) -#define GMACSL_TX_ENABLE_SHORT_GAP (1 << 10) -#define GMACSL_ENABLE_GIG_MODE (1 << 7) -#define GMACSL_TX_ENABLE_PACE (1 << 6) -#define GMACSL_ENABLE (1 << 5) -#define GMACSL_TX_ENABLE_FLOW_CTL (1 << 4) -#define GMACSL_RX_ENABLE_FLOW_CTL (1 << 3) -#define GMACSL_ENABLE_LOOPBACK (1 << 1) -#define GMACSL_ENABLE_FULL_DUPLEX (1 << 0) - -/* - * DEFINTITION: function return values - */ -#define GMACSL_RET_OK 0 -#define GMACSL_RET_INVALID_PORT -1 -#define GMACSL_RET_WARN_RESET_INCOMPLETE -2 -#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3 -#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4 - -/* EMAC SL register definitions */ -#define DEVICE_EMACSL_RESET_POLL_COUNT 100 - -/* Soft reset register values */ -#define CPGMAC_REG_RESET_VAL_RESET_MASK (1 << 0) -#define CPGMAC_REG_RESET_VAL_RESET (1 << 0) - -/* Maxlen register values */ -#define CPGMAC_REG_MAXLEN_LEN 0x3fff - -/* CPSW */ -/* Control bitfields */ -#define CPSW_CTL_P2_PASS_PRI_TAGGED (1 << 5) -#define CPSW_CTL_P1_PASS_PRI_TAGGED (1 << 4) -#define CPSW_CTL_P0_PASS_PRI_TAGGED (1 << 3) -#define CPSW_CTL_P0_ENABLE (1 << 2) -#define CPSW_CTL_VLAN_AWARE (1 << 1) -#define CPSW_CTL_FIFO_LOOPBACK (1 << 0) - -#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS -#define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1) - -#ifdef KS2_NETCP_V1_0 - -#define DEVICE_CPSW_BASE (KS2_PASS_BASE + 0x00090800) -#define CPSW_REG_CTL 0x004 -#define CPSW_REG_STAT_PORT_EN 0x00c -#define CPSW_REG_MAXLEN 0x040 -#define CPSW_REG_ALE_CONTROL 0x608 -#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x)*4) -#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf - -#elif defined KS2_NETCP_V1_5 - -#define DEVICE_CPSW_BASE (KS2_PASS_BASE + 0x00220000) -#define CPSW_REG_CTL 0x00004 -#define CPSW_REG_STAT_PORT_EN 0x00014 -#define CPSW_REG_MAXLEN 0x01024 -#define CPSW_REG_ALE_CONTROL 0x1e008 -#define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4) -#define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff - -#endif - -#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000) -#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010) -#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3 - -#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE /* Enable port 0 */ -#define SWITCH_MAX_PKT_SIZE 9000 - -/* SGMII */ -#define SGMII_REG_STATUS_LOCK BIT(4) -#define SGMII_REG_STATUS_LINK BIT(0) -#define SGMII_REG_STATUS_AUTONEG BIT(2) -#define SGMII_REG_CONTROL_AUTONEG BIT(0) -#define SGMII_REG_CONTROL_MASTER BIT(5) -#define SGMII_REG_MR_ADV_ENABLE BIT(0) -#define SGMII_REG_MR_ADV_LINK BIT(15) -#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12) -#define SGMII_REG_MR_ADV_GIG_MODE BIT(11) - -#define SGMII_LINK_MAC_MAC_AUTONEG 0 -#define SGMII_LINK_MAC_PHY 1 -#define SGMII_LINK_MAC_MAC_FORCED 2 -#define SGMII_LINK_MAC_FIBER 3 -#define SGMII_LINK_MAC_PHY_FORCED 4 - -#ifdef KS2_NETCP_V1_0 -#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100)) -#elif defined KS2_NETCP_V1_5 -#define SGMII_OFFSET(x) ((x) * 0x100) -#endif - -#define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000) -#define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004) -#define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010) -#define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014) -#define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018) -#define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020) -#define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030) -#define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034) -#define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038) - -/* PSS */ -#ifdef KS2_NETCP_V1_0 - -#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x604) -#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606 -#define hw_config_streaming_switch()\ - writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR); - -#elif defined KS2_NETCP_V1_5 - -#define DEVICE_PSTREAM_CFG_REG_ADDR (KS2_PASS_BASE + 0x500) -#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0 - -#define hw_config_streaming_switch()\ - writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ - DEVICE_PSTREAM_CFG_REG_ADDR);\ - writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ - DEVICE_PSTREAM_CFG_REG_ADDR+4);\ - writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ - DEVICE_PSTREAM_CFG_REG_ADDR+8);\ - writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ - DEVICE_PSTREAM_CFG_REG_ADDR+12); - -#endif - -/* EMAC MDIO Registers Structure */ -struct mdio_regs { - dv_reg version; - dv_reg control; - dv_reg alive; - dv_reg link; - dv_reg linkintraw; - dv_reg linkintmasked; - u_int8_t rsvd0[8]; - dv_reg userintraw; - dv_reg userintmasked; - dv_reg userintmaskset; - dv_reg userintmaskclear; - u_int8_t rsvd1[80]; - dv_reg useraccess0; - dv_reg userphysel0; - dv_reg useraccess1; - dv_reg userphysel1; -}; - -struct eth_priv_t { - char int_name[32]; - int rx_flow; - int phy_addr; - int slave_port; - int sgmii_link_type; -}; - -int keystone2_emac_initialize(struct eth_priv_t *eth_priv); -void sgmii_serdes_setup_156p25mhz(void); -void sgmii_serdes_shutdown(void); - -#endif /* _EMAC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index 6cfed3aff9e..706b21d09a4 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -95,7 +95,7 @@ #define KS2_NETCP_PDMA_RX_RCV_QUEUE 4002 #define KS2_NETCP_PDMA_TX_SND_QUEUE 648 -/* NETCP version */ -#define KS2_NETCP_V1_0 +/* NETCP */ +#define KS2_NETCP_BASE 0x02000000 #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 08a7c700383..0441b291cc8 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -175,6 +175,8 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_DEV_USB_PHY_BASE 0x02620738 #define KS2_USB_PHY_CFG_BASE 0x02630000 +#define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110) + #ifdef CONFIG_SOC_K2HK #include #endif diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h new file mode 100644 index 00000000000..7769d7b7f70 --- /dev/null +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -0,0 +1,248 @@ +/* + * emac definitions for keystone2 devices + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _KEYSTONE_NET_H_ +#define _KEYSTONE_NET_H_ + +#include + +/* EMAC */ +#ifdef CONFIG_KSNET_NETCP_V1_0 + +#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000) +#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900) +#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300) +#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100) +#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x040) + +/* Register offsets */ +#define CPGMACSL_REG_CTL 0x04 +#define CPGMACSL_REG_STATUS 0x08 +#define CPGMACSL_REG_RESET 0x0c +#define CPGMACSL_REG_MAXLEN 0x10 + +#elif defined CONFIG_KSNET_NETCP_V1_5 + +#define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000) +#define CPGMACSL_REG_RX_PRI_MAP 0x020 +#define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x22000) +#define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x00f00) +#define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x00100) +#define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x1000) + +/* Register offsets */ +#define CPGMACSL_REG_CTL 0x330 +#define CPGMACSL_REG_STATUS 0x334 +#define CPGMACSL_REG_RESET 0x338 +#define CPGMACSL_REG_MAXLEN 0x024 + +#endif + +#define KEYSTONE2_EMAC_GIG_ENABLE + +#define MAC_ID_BASE_ADDR CONFIG_KSNET_MAC_ID_BASE + +/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ (clk_get_rate(pass_pll_clk)) +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 1000000 /* 1.0 MHz */ + +/* MII Status Register */ +#define MII_STATUS_REG 1 +#define MII_STATUS_LINK_MASK 0x4 + +#define MDIO_CONTROL_IDLE 0x80000000 +#define MDIO_CONTROL_ENABLE 0x40000000 +#define MDIO_CONTROL_FAULT_ENABLE 0x40000 +#define MDIO_CONTROL_FAULT 0x80000 +#define MDIO_USERACCESS0_GO 0x80000000 +#define MDIO_USERACCESS0_WRITE_READ 0x0 +#define MDIO_USERACCESS0_WRITE_WRITE 0x40000000 +#define MDIO_USERACCESS0_ACK 0x20000000 + +#define EMAC_MACCONTROL_MIIEN_ENABLE 0x20 +#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE 0x1 +#define EMAC_MACCONTROL_GIGABIT_ENABLE BIT(7) +#define EMAC_MACCONTROL_GIGFORCE BIT(17) +#define EMAC_MACCONTROL_RMIISPEED_100 BIT(15) + +#define EMAC_MIN_ETHERNET_PKT_SIZE 60 + +struct mac_sl_cfg { + u_int32_t max_rx_len; /* Maximum receive packet length. */ + u_int32_t ctl; /* Control bitfield */ +}; + +/** + * Definition: Control bitfields used in the ctl field of mac_sl_cfg + */ +#define GMACSL_RX_ENABLE_RCV_CONTROL_FRAMES BIT(24) +#define GMACSL_RX_ENABLE_RCV_SHORT_FRAMES BIT(23) +#define GMACSL_RX_ENABLE_RCV_ERROR_FRAMES BIT(22) +#define GMACSL_RX_ENABLE_EXT_CTL BIT(18) +#define GMACSL_RX_ENABLE_GIG_FORCE BIT(17) +#define GMACSL_RX_ENABLE_IFCTL_B BIT(16) +#define GMACSL_RX_ENABLE_IFCTL_A BIT(15) +#define GMACSL_RX_ENABLE_CMD_IDLE BIT(11) +#define GMACSL_TX_ENABLE_SHORT_GAP BIT(10) +#define GMACSL_ENABLE_GIG_MODE BIT(7) +#define GMACSL_TX_ENABLE_PACE BIT(6) +#define GMACSL_ENABLE BIT(5) +#define GMACSL_TX_ENABLE_FLOW_CTL BIT(4) +#define GMACSL_RX_ENABLE_FLOW_CTL BIT(3) +#define GMACSL_ENABLE_LOOPBACK BIT(1) +#define GMACSL_ENABLE_FULL_DUPLEX BIT(0) + +/* EMAC SL function return values */ +#define GMACSL_RET_OK 0 +#define GMACSL_RET_INVALID_PORT -1 +#define GMACSL_RET_WARN_RESET_INCOMPLETE -2 +#define GMACSL_RET_WARN_MAXLEN_TOO_BIG -3 +#define GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE -4 + +/* EMAC SL register definitions */ +#define DEVICE_EMACSL_RESET_POLL_COUNT 100 + +/* Soft reset register values */ +#define CPGMAC_REG_RESET_VAL_RESET_MASK BIT(0) +#define CPGMAC_REG_RESET_VAL_RESET BIT(0) +#define CPGMAC_REG_MAXLEN_LEN 0x3fff + +/* CPSW */ +/* Control bitfields */ +#define CPSW_CTL_P2_PASS_PRI_TAGGED BIT(5) +#define CPSW_CTL_P1_PASS_PRI_TAGGED BIT(4) +#define CPSW_CTL_P0_PASS_PRI_TAGGED BIT(3) +#define CPSW_CTL_P0_ENABLE BIT(2) +#define CPSW_CTL_VLAN_AWARE BIT(1) +#define CPSW_CTL_FIFO_LOOPBACK BIT(0) + +#define DEVICE_CPSW_NUM_PORTS CONFIG_KSNET_CPSW_NUM_PORTS +#define DEVICE_N_GMACSL_PORTS (DEVICE_CPSW_NUM_PORTS - 1) + +#ifdef CONFIG_KSNET_NETCP_V1_0 + +#define DEVICE_CPSW_BASE (GBETH_BASE + 0x800) +#define CPSW_REG_CTL 0x004 +#define CPSW_REG_STAT_PORT_EN 0x00c +#define CPSW_REG_MAXLEN 0x040 +#define CPSW_REG_ALE_CONTROL 0x608 +#define CPSW_REG_ALE_PORTCTL(x) (0x640 + (x) * 4) +#define CPSW_REG_VAL_STAT_ENABLE_ALL 0xf + +#elif defined CONFIG_KSNET_NETCP_V1_5 + +#define DEVICE_CPSW_BASE (GBETH_BASE + 0x20000) +#define CPSW_REG_CTL 0x00004 +#define CPSW_REG_STAT_PORT_EN 0x00014 +#define CPSW_REG_MAXLEN 0x01024 +#define CPSW_REG_ALE_CONTROL 0x1e008 +#define CPSW_REG_ALE_PORTCTL(x) (0x1e040 + (x) * 4) +#define CPSW_REG_VAL_STAT_ENABLE_ALL 0x1ff + +#endif + +#define CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE ((u_int32_t)0xc0000000) +#define CPSW_REG_VAL_ALE_CTL_BYPASS ((u_int32_t)0x00000010) +#define CPSW_REG_VAL_PORTCTL_FORWARD_MODE 0x3 + +#define target_get_switch_ctl() CPSW_CTL_P0_ENABLE +#define SWITCH_MAX_PKT_SIZE 9000 + +/* SGMII */ +#define SGMII_REG_STATUS_LOCK BIT(4) +#define SGMII_REG_STATUS_LINK BIT(0) +#define SGMII_REG_STATUS_AUTONEG BIT(2) +#define SGMII_REG_CONTROL_AUTONEG BIT(0) +#define SGMII_REG_CONTROL_MASTER BIT(5) +#define SGMII_REG_MR_ADV_ENABLE BIT(0) +#define SGMII_REG_MR_ADV_LINK BIT(15) +#define SGMII_REG_MR_ADV_FULL_DUPLEX BIT(12) +#define SGMII_REG_MR_ADV_GIG_MODE BIT(11) + +#define SGMII_LINK_MAC_MAC_AUTONEG 0 +#define SGMII_LINK_MAC_PHY 1 +#define SGMII_LINK_MAC_MAC_FORCED 2 +#define SGMII_LINK_MAC_FIBER 3 +#define SGMII_LINK_MAC_PHY_FORCED 4 + +#ifdef CONFIG_KSNET_NETCP_V1_0 +#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : ((x * 0x100) + 0x100)) +#elif defined CONFIG_KSNET_NETCP_V1_5 +#define SGMII_OFFSET(x) ((x) * 0x100) +#endif + +#define SGMII_IDVER_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x000) +#define SGMII_SRESET_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x004) +#define SGMII_CTL_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x010) +#define SGMII_STATUS_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x014) +#define SGMII_MRADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x018) +#define SGMII_LPADV_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x020) +#define SGMII_TXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x030) +#define SGMII_RXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x034) +#define SGMII_AUXCFG_REG(x) (EMAC_SGMII_BASE_ADDR + SGMII_OFFSET(x) + 0x038) + +/* PSS */ +#ifdef CONFIG_KSNET_NETCP_V1_0 + +#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x604) +#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x06060606 +#define hw_config_streaming_switch()\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI, DEVICE_PSTREAM_CFG_REG_ADDR); + +#elif defined CONFIG_KSNET_NETCP_V1_5 + +#define DEVICE_PSTREAM_CFG_REG_ADDR (CONFIG_KSNET_NETCP_BASE + 0x500) +#define DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI 0x0 + +#define hw_config_streaming_switch()\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+4);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+8);\ + writel(DEVICE_PSTREAM_CFG_VAL_ROUTE_CPPI,\ + DEVICE_PSTREAM_CFG_REG_ADDR+12); + +#endif + +/* EMAC MDIO Registers Structure */ +struct mdio_regs { + u32 version; + u32 control; + u32 alive; + u32 link; + u32 linkintraw; + u32 linkintmasked; + u32 rsvd0[2]; + u32 userintraw; + u32 userintmasked; + u32 userintmaskset; + u32 userintmaskclear; + u32 rsvd1[20]; + u32 useraccess0; + u32 userphysel0; + u32 useraccess1; + u32 userphysel1; +}; + +struct eth_priv_t { + char int_name[32]; + int rx_flow; + int phy_addr; + int slave_port; + int sgmii_link_type; +}; + +int keystone2_emac_initialize(struct eth_priv_t *eth_priv); +void sgmii_serdes_setup_156p25mhz(void); +void sgmii_serdes_shutdown(void); + +#endif /* _KEYSTONE_NET_H_ */ diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index c07d2848ba5..e1771d253a1 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -13,8 +13,8 @@ #include #include #include -#include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h index 7a613ac817b..2bbd79245ba 100644 --- a/board/ti/ks2_evm/board.h +++ b/board/ti/ks2_evm/board.h @@ -10,7 +10,7 @@ #ifndef _KS2_BOARD #define _KS2_BOARD -#include +#include extern struct eth_priv_t eth_priv_cfg[]; diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index d7dd29281ce..ed181f44b89 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 4abde57cc80..edd2bb03bba 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -12,9 +12,9 @@ #include #include #include -#include #include #include +#include unsigned int emac_dbg; diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 15cebb97182..45bd72d2de8 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -38,6 +38,7 @@ #define CONFIG_DRIVER_TI_KEYSTONE_NET #define CONFIG_TI_KSNAV #define CONFIG_KSNAV_PKTDMA_NETCP +#define CONFIG_KSNET_NETCP_V1_0 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 #endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index 6e6755a314d..ec3f72effd7 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -133,6 +133,10 @@ #define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE +/* Keystone net */ +#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR +#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE + /* AEMIF */ #define CONFIG_TI_AEMIF #define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE -- cgit v1.3.1 From a43febde4452f254621c0c95d452c89ad498e959 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Wed, 22 Oct 2014 17:18:21 +0300 Subject: soc: keystone_serdes: create a separate SGMII SerDes driver This patch split the Keystone II SGMII SerDes related code from Ethernet driver and create a separate SGMII SerDes driver. The SerDes driver can be used by others keystone subsystems like PCI, sRIO, so move it to driver/soc/keystone directory. Add soc specific drivers directory like in the Linux kernel. It is going to be used by keysotone soc specific drivers. Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/ti-common/keystone_serdes.h | 15 +++ drivers/Makefile | 2 + drivers/net/keystone_net.c | 143 +---------------------- drivers/soc/Makefile | 5 + drivers/soc/keystone/Makefile | 1 + drivers/soc/keystone/keystone_serdes.c | 127 ++++++++++++++++++++ include/configs/k2hk_evm.h | 3 + 7 files changed, 158 insertions(+), 138 deletions(-) create mode 100644 arch/arm/include/asm/ti-common/keystone_serdes.h create mode 100644 drivers/soc/Makefile create mode 100644 drivers/soc/keystone/Makefile create mode 100644 drivers/soc/keystone/keystone_serdes.c (limited to 'include') diff --git a/arch/arm/include/asm/ti-common/keystone_serdes.h b/arch/arm/include/asm/ti-common/keystone_serdes.h new file mode 100644 index 00000000000..2e12b05d05b --- /dev/null +++ b/arch/arm/include/asm/ti-common/keystone_serdes.h @@ -0,0 +1,15 @@ +/* + * Texas Instruments Keystone SerDes driver + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TI_KEYSTONE_SERDES_H__ +#define __TI_KEYSTONE_SERDES_H__ + +void ks2_serdes_sgmii_156p25mhz_setup(void); + +#endif /* __TI_KEYSTONE_SERDES_H__ */ diff --git a/drivers/Makefile b/drivers/Makefile index d8361d95fd1..33227c8bd6d 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -19,3 +19,5 @@ obj-$(CONFIG_QE) += qe/ obj-y += memory/ obj-y += pwm/ obj-y += input/ +# SOC specific infrastructure drivers. +obj-y += soc/ diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 33197f95b9e..63f33611cb6 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -14,6 +14,7 @@ #include #include #include +#include unsigned int emac_open; static unsigned int sys_has_mdio = 1; @@ -38,6 +39,7 @@ struct rx_buff_desc net_rx_buffs = { }; static void keystone2_eth_mdio_enable(void); +static void keystone2_net_serdes_setup(void); static int gen_get_link_speed(int phy_addr); @@ -406,7 +408,7 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) sys_has_mdio = (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) ? 1 : 0; - sgmii_serdes_setup_156p25mhz(); + keystone2_net_serdes_setup(); if (sys_has_mdio) keystone2_eth_mdio_enable(); @@ -552,142 +554,7 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv) return 0; } -void sgmii_serdes_setup_156p25mhz(void) +static void keystone2_net_serdes_setup(void) { - unsigned int cnt; - - /* - * configure Serializer/Deserializer (SerDes) hardware. SerDes IP - * hardware vendor published only register addresses and their values - * to be used for configuring SerDes. So had to use hardcoded values - * below. - */ - clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000); - clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282); - clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438); - clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700); - clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000); - - clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080); - clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000); - clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000); - clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000); - clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8); - clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4); - clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400); - clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800); - clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082); - clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385); - - clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080); - clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000); - clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000); - clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000); - clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8); - clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4); - clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400); - clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800); - clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082); - clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385); - - clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080); - clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000); - clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000); - clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000); - clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8); - clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4); - clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400); - clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800); - clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082); - clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385); - - clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080); - clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000); - clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000); - clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000); - clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8); - clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4); - clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400); - clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800); - clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082); - clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385); - - clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800); - clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000); - clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00); - clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600); - clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000); - clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000); - clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000); - clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b); - clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000); - clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e); - clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003); - clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f); - - clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00); - clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72); - clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100); - clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060); - clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000); - clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220); - clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602); - clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1); - clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989); - clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001); - clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000); - clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000); - clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d); - - /*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/ - clrbits_le32(0x0232a010, 1 << 28); - - /* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */ - clrbits_le32(0x0232a228, 1 << 29); - writel(0xF800F8C0, 0x0232bfe0); - clrbits_le32(0x0232a428, 1 << 29); - writel(0xF800F8C0, 0x0232bfe4); - clrbits_le32(0x0232a628, 1 << 29); - writel(0xF800F8C0, 0x0232bfe8); - clrbits_le32(0x0232a828, 1 << 29); - writel(0xF800F8C0, 0x0232bfec); - - /*Enable pll via the pll_ctrl 0x0014*/ - writel(0xe0000000, 0x0232bff4) - ; - - /*Waiting for SGMII Serdes PLL lock.*/ - for (cnt = 10000; cnt > 0 && ((readl(0x02090114) & 0x10) == 0); cnt--) - ; - - for (cnt = 10000; cnt > 0 && ((readl(0x02090214) & 0x10) == 0); cnt--) - ; - - for (cnt = 10000; cnt > 0 && ((readl(0x02090414) & 0x10) == 0); cnt--) - ; - - for (cnt = 10000; cnt > 0 && ((readl(0x02090514) & 0x10) == 0); cnt--) - ; - - udelay(45000); -} - -void sgmii_serdes_shutdown(void) -{ - /* - * shutdown SerDes hardware. SerDes hardware vendor published only - * register addresses and their values. So had to use hardcoded - * values below. - */ - clrbits_le32(0x0232bfe0, 3 << 29 | 3 << 13); - setbits_le32(0x02320228, 1 << 29); - clrbits_le32(0x0232bfe4, 3 << 29 | 3 << 13); - setbits_le32(0x02320428, 1 << 29); - clrbits_le32(0x0232bfe8, 3 << 29 | 3 << 13); - setbits_le32(0x02320628, 1 << 29); - clrbits_le32(0x0232bfec, 3 << 29 | 3 << 13); - setbits_le32(0x02320828, 1 << 29); - - clrbits_le32(0x02320034, 3 << 29); - setbits_le32(0x02320010, 1 << 28); + ks2_serdes_sgmii_156p25mhz_setup(); } diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile new file mode 100644 index 00000000000..3d4baa51d62 --- /dev/null +++ b/drivers/soc/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for the U-boot SOC specific device drivers. +# + +obj-$(CONFIG_ARCH_KEYSTONE) += keystone/ diff --git a/drivers/soc/keystone/Makefile b/drivers/soc/keystone/Makefile new file mode 100644 index 00000000000..c000ecac760 --- /dev/null +++ b/drivers/soc/keystone/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_TI_KEYSTONE_SERDES) += keystone_serdes.o diff --git a/drivers/soc/keystone/keystone_serdes.c b/drivers/soc/keystone/keystone_serdes.c new file mode 100644 index 00000000000..dc4e78d5758 --- /dev/null +++ b/drivers/soc/keystone/keystone_serdes.c @@ -0,0 +1,127 @@ +/* + * TI serdes driver for keystone2. + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +void ks2_serdes_sgmii_156p25mhz_setup(void) +{ + unsigned int cnt; + + /* + * configure Serializer/Deserializer (SerDes) hardware. SerDes IP + * hardware vendor published only register addresses and their values + * to be used for configuring SerDes. So had to use hardcoded values + * below. + */ + clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000); + clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282); + clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438); + clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700); + clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000); + + clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080); + clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000); + clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000); + clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000); + clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8); + clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4); + clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400); + clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800); + clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082); + clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385); + + clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080); + clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000); + clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000); + clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000); + clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8); + clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4); + clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400); + clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800); + clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082); + clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385); + + clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080); + clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000); + clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000); + clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000); + clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8); + clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4); + clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400); + clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800); + clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082); + clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385); + + clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080); + clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000); + clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000); + clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000); + clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8); + clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4); + clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400); + clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800); + clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082); + clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385); + + clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800); + clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000); + clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00); + clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600); + clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000); + clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000); + clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000); + clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b); + clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000); + clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e); + clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003); + clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f); + + clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00); + clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72); + clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100); + clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060); + clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000); + clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220); + clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602); + clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1); + clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989); + clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001); + clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000); + clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000); + clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d); + + /*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/ + clrbits_le32(0x0232a010, 1 << 28); + + /* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */ + clrbits_le32(0x0232a228, 1 << 29); + writel(0xF800F8C0, 0x0232bfe0); + clrbits_le32(0x0232a428, 1 << 29); + writel(0xF800F8C0, 0x0232bfe4); + clrbits_le32(0x0232a628, 1 << 29); + writel(0xF800F8C0, 0x0232bfe8); + clrbits_le32(0x0232a828, 1 << 29); + writel(0xF800F8C0, 0x0232bfec); + + /*Enable pll via the pll_ctrl 0x0014*/ + writel(0xe0000000, 0x0232bff4) + ; + + /*Waiting for SGMII Serdes PLL lock.*/ + for (cnt = 10000; cnt > 0 && ((readl(0x02090114) & 0x10) == 0); cnt--) + ; + for (cnt = 10000; cnt > 0 && ((readl(0x02090214) & 0x10) == 0); cnt--) + ; + for (cnt = 10000; cnt > 0 && ((readl(0x02090414) & 0x10) == 0); cnt--) + ; + for (cnt = 10000; cnt > 0 && ((readl(0x02090514) & 0x10) == 0); cnt--) + ; + + udelay(45000); +} diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h index 45bd72d2de8..034cbfd4d78 100644 --- a/include/configs/k2hk_evm.h +++ b/include/configs/k2hk_evm.h @@ -41,4 +41,7 @@ #define CONFIG_KSNET_NETCP_V1_0 #define CONFIG_KSNET_CPSW_NUM_PORTS 5 +/* SerDes */ +#define CONFIG_TI_KEYSTONE_SERDES + #endif /* __CONFIG_K2HK_EVM_H */ -- cgit v1.3.1 From 95f74dad912563181e4701dc4bc163c49c2bd3b3 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 22 Oct 2014 17:18:22 +0300 Subject: soc: keystone_serdes: enhance to use cmu/comlane/lane specific configurations Enhance the driver to use cmu/comlane/lane specific configurations instead of 1 big array of configuration. Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 3 + arch/arm/include/asm/arch-keystone/hardware.h | 3 + drivers/soc/keystone/keystone_serdes.c | 166 +++++++++++---------- include/configs/ks2_evm.h | 4 + 4 files changed, 94 insertions(+), 82 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h index 706b21d09a4..28de3f50107 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h @@ -79,6 +79,9 @@ #define KS2_DDR3B_EMIF_DATA_BASE 0x60000000 #define KS2_DDR3B_DDRPHYC 0x02328000 +/* SGMII SerDes */ +#define KS2_LANES_PER_SGMII_SERDES 4 + /* Number of DSP cores */ #define KS2_NUM_DSPS 8 diff --git a/arch/arm/include/asm/arch-keystone/hardware.h b/arch/arm/include/asm/arch-keystone/hardware.h index 0441b291cc8..6e2e939bf49 100644 --- a/arch/arm/include/asm/arch-keystone/hardware.h +++ b/arch/arm/include/asm/arch-keystone/hardware.h @@ -177,6 +177,9 @@ typedef volatile unsigned int *dv_reg_p; #define KS2_MAC_ID_BASE_ADDR (KS2_DEVICE_STATE_CTRL_BASE + 0x110) +/* SGMII SerDes */ +#define KS2_SGMII_SERDES_BASE 0x0232a000 + #ifdef CONFIG_SOC_K2HK #include #endif diff --git a/drivers/soc/keystone/keystone_serdes.c b/drivers/soc/keystone/keystone_serdes.c index dc4e78d5758..3632c22be29 100644 --- a/drivers/soc/keystone/keystone_serdes.c +++ b/drivers/soc/keystone/keystone_serdes.c @@ -9,92 +9,94 @@ #include +#define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x))) + +struct serdes_cfg { + u32 ofs; + u32 val; + u32 mask; +}; + +static struct serdes_cfg cfg_cmu_156p25m_5g[] = { + {0x0000, 0x00800000, 0xffff0000}, + {0x0014, 0x00008282, 0x0000ffff}, + {0x0060, 0x00142438, 0x00ffffff}, + {0x0064, 0x00c3c700, 0x00ffff00}, + {0x0078, 0x0000c000, 0x0000ff00} +}; + +static struct serdes_cfg cfg_comlane_156p25m_5g[] = { + {0x0a00, 0x00000800, 0x0000ff00}, + {0x0a08, 0x38a20000, 0xffff0000}, + {0x0a30, 0x008a8a00, 0x00ffff00}, + {0x0a84, 0x00000600, 0x0000ff00}, + {0x0a94, 0x10000000, 0xff000000}, + {0x0aa0, 0x81000000, 0xff000000}, + {0x0abc, 0xff000000, 0xff000000}, + {0x0ac0, 0x0000008b, 0x000000ff}, + {0x0b08, 0x583f0000, 0xffff0000}, + {0x0b0c, 0x0000004e, 0x000000ff} +}; + +static struct serdes_cfg cfg_lane_156p25mhz_5g[] = { + {0x0004, 0x38000080, 0xff0000ff}, + {0x0008, 0x00000000, 0x000000ff}, + {0x000c, 0x02000000, 0xff000000}, + {0x0010, 0x1b000000, 0xff000000}, + {0x0014, 0x00006fb8, 0x0000ffff}, + {0x0018, 0x758000e4, 0xffff00ff}, + {0x00ac, 0x00004400, 0x0000ff00}, + {0x002c, 0x00100800, 0x00ffff00}, + {0x0080, 0x00820082, 0x00ff00ff}, + {0x0084, 0x1d0f0385, 0xffffffff} + +}; + +static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask) +{ + writel(((readl(addr) & (~mask)) | (value & mask)), addr); +} + +static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size) +{ + u32 i; + + for (i = 0; i < size; i++) + ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask); +} + +static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane, + u32 size, u32 lane) +{ + u32 i; + + for (i = 0; i < size; i++) + ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane), + cfg_lane[i].val, cfg_lane[i].mask); +} + +static int ks2_serdes_init_156p25m_5g(u32 base, u32 num_lanes) +{ + u32 i; + + ks2_serdes_cfg_setup(base, cfg_cmu_156p25m_5g, + ARRAY_SIZE(cfg_cmu_156p25m_5g)); + ks2_serdes_cfg_setup(base, cfg_comlane_156p25m_5g, + ARRAY_SIZE(cfg_comlane_156p25m_5g)); + + for (i = 0; i < num_lanes; i++) + ks2_serdes_lane_config(base, cfg_lane_156p25mhz_5g, + ARRAY_SIZE(cfg_lane_156p25mhz_5g), i); + + return 0; +} + void ks2_serdes_sgmii_156p25mhz_setup(void) { unsigned int cnt; - /* - * configure Serializer/Deserializer (SerDes) hardware. SerDes IP - * hardware vendor published only register addresses and their values - * to be used for configuring SerDes. So had to use hardcoded values - * below. - */ - clrsetbits_le32(0x0232a000, 0xffff0000, 0x00800000); - clrsetbits_le32(0x0232a014, 0x0000ffff, 0x00008282); - clrsetbits_le32(0x0232a060, 0x00ffffff, 0x00142438); - clrsetbits_le32(0x0232a064, 0x00ffff00, 0x00c3c700); - clrsetbits_le32(0x0232a078, 0x0000ff00, 0x0000c000); - - clrsetbits_le32(0x0232a204, 0xff0000ff, 0x38000080); - clrsetbits_le32(0x0232a208, 0x000000ff, 0x00000000); - clrsetbits_le32(0x0232a20c, 0xff000000, 0x02000000); - clrsetbits_le32(0x0232a210, 0xff000000, 0x1b000000); - clrsetbits_le32(0x0232a214, 0x0000ffff, 0x00006fb8); - clrsetbits_le32(0x0232a218, 0xffff00ff, 0x758000e4); - clrsetbits_le32(0x0232a2ac, 0x0000ff00, 0x00004400); - clrsetbits_le32(0x0232a22c, 0x00ffff00, 0x00200800); - clrsetbits_le32(0x0232a280, 0x00ff00ff, 0x00820082); - clrsetbits_le32(0x0232a284, 0xffffffff, 0x1d0f0385); - - clrsetbits_le32(0x0232a404, 0xff0000ff, 0x38000080); - clrsetbits_le32(0x0232a408, 0x000000ff, 0x00000000); - clrsetbits_le32(0x0232a40c, 0xff000000, 0x02000000); - clrsetbits_le32(0x0232a410, 0xff000000, 0x1b000000); - clrsetbits_le32(0x0232a414, 0x0000ffff, 0x00006fb8); - clrsetbits_le32(0x0232a418, 0xffff00ff, 0x758000e4); - clrsetbits_le32(0x0232a4ac, 0x0000ff00, 0x00004400); - clrsetbits_le32(0x0232a42c, 0x00ffff00, 0x00200800); - clrsetbits_le32(0x0232a480, 0x00ff00ff, 0x00820082); - clrsetbits_le32(0x0232a484, 0xffffffff, 0x1d0f0385); - - clrsetbits_le32(0x0232a604, 0xff0000ff, 0x38000080); - clrsetbits_le32(0x0232a608, 0x000000ff, 0x00000000); - clrsetbits_le32(0x0232a60c, 0xff000000, 0x02000000); - clrsetbits_le32(0x0232a610, 0xff000000, 0x1b000000); - clrsetbits_le32(0x0232a614, 0x0000ffff, 0x00006fb8); - clrsetbits_le32(0x0232a618, 0xffff00ff, 0x758000e4); - clrsetbits_le32(0x0232a6ac, 0x0000ff00, 0x00004400); - clrsetbits_le32(0x0232a62c, 0x00ffff00, 0x00200800); - clrsetbits_le32(0x0232a680, 0x00ff00ff, 0x00820082); - clrsetbits_le32(0x0232a684, 0xffffffff, 0x1d0f0385); - - clrsetbits_le32(0x0232a804, 0xff0000ff, 0x38000080); - clrsetbits_le32(0x0232a808, 0x000000ff, 0x00000000); - clrsetbits_le32(0x0232a80c, 0xff000000, 0x02000000); - clrsetbits_le32(0x0232a810, 0xff000000, 0x1b000000); - clrsetbits_le32(0x0232a814, 0x0000ffff, 0x00006fb8); - clrsetbits_le32(0x0232a818, 0xffff00ff, 0x758000e4); - clrsetbits_le32(0x0232a8ac, 0x0000ff00, 0x00004400); - clrsetbits_le32(0x0232a82c, 0x00ffff00, 0x00200800); - clrsetbits_le32(0x0232a880, 0x00ff00ff, 0x00820082); - clrsetbits_le32(0x0232a884, 0xffffffff, 0x1d0f0385); - - clrsetbits_le32(0x0232aa00, 0x0000ff00, 0x00000800); - clrsetbits_le32(0x0232aa08, 0xffff0000, 0x38a20000); - clrsetbits_le32(0x0232aa30, 0x00ffff00, 0x008a8a00); - clrsetbits_le32(0x0232aa84, 0x0000ff00, 0x00000600); - clrsetbits_le32(0x0232aa94, 0xff000000, 0x10000000); - clrsetbits_le32(0x0232aaa0, 0xff000000, 0x81000000); - clrsetbits_le32(0x0232aabc, 0xff000000, 0xff000000); - clrsetbits_le32(0x0232aac0, 0x000000ff, 0x0000008b); - clrsetbits_le32(0x0232ab08, 0xffff0000, 0x583f0000); - clrsetbits_le32(0x0232ab0c, 0x000000ff, 0x0000004e); - clrsetbits_le32(0x0232a000, 0x000000ff, 0x00000003); - clrsetbits_le32(0x0232aa00, 0x000000ff, 0x0000005f); - - clrsetbits_le32(0x0232aa48, 0x00ffff00, 0x00fd8c00); - clrsetbits_le32(0x0232aa54, 0x00ffffff, 0x002fec72); - clrsetbits_le32(0x0232aa58, 0xffffff00, 0x00f92100); - clrsetbits_le32(0x0232aa5c, 0xffffffff, 0x00040060); - clrsetbits_le32(0x0232aa60, 0xffffffff, 0x00008000); - clrsetbits_le32(0x0232aa64, 0xffffffff, 0x0c581220); - clrsetbits_le32(0x0232aa68, 0xffffffff, 0xe13b0602); - clrsetbits_le32(0x0232aa6c, 0xffffffff, 0xb8074cc1); - clrsetbits_le32(0x0232aa70, 0xffffffff, 0x3f02e989); - clrsetbits_le32(0x0232aa74, 0x000000ff, 0x00000001); - clrsetbits_le32(0x0232ab20, 0x00ff0000, 0x00370000); - clrsetbits_le32(0x0232ab1c, 0xff000000, 0x37000000); - clrsetbits_le32(0x0232ab20, 0x000000ff, 0x0000005d); + ks2_serdes_init_156p25m_5g(CONFIG_KS2_SERDES_SGMII_BASE, + CONFIG_KS2_SERDES_LANES_PER_SGMII); /*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/ clrbits_le32(0x0232a010, 1 << 28); diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index ec3f72effd7..8037c3e6e29 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -319,4 +319,8 @@ which is NOT applicable for DDR ECC test */ #define CONFIG_MAX_UBOOT_MEM_SIZE (4 << 20) /* 4 MiB */ +/* SGMII SerDes */ +#define CONFIG_KS2_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE +#define CONFIG_KS2_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES + #endif /* __CONFIG_KS2_EVM_H */ -- cgit v1.3.1 From 92a16c81f5c5b43779520dbc7278f3d7cfb24684 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 22 Oct 2014 17:18:23 +0300 Subject: soc: keystone_serdes: generalize to be used by other sub systems SerDes driver is used by other sub systems like PCI, sRIO etc. So modify it to be more general. The SerDes driver provides common API's that can also be extended for other peripherals SerDes configurations. Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/ti-common/keystone_serdes.h | 42 +++++++- drivers/net/keystone_net.c | 15 ++- drivers/soc/keystone/keystone_serdes.c | 131 +++++++++++++++++------ include/configs/ks2_evm.h | 10 +- 4 files changed, 156 insertions(+), 42 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/ti-common/keystone_serdes.h b/arch/arm/include/asm/ti-common/keystone_serdes.h index 2e12b05d05b..2e92411404b 100644 --- a/arch/arm/include/asm/ti-common/keystone_serdes.h +++ b/arch/arm/include/asm/ti-common/keystone_serdes.h @@ -10,6 +10,46 @@ #ifndef __TI_KEYSTONE_SERDES_H__ #define __TI_KEYSTONE_SERDES_H__ -void ks2_serdes_sgmii_156p25mhz_setup(void); +/* SERDES Reference clock */ +enum ks2_serdes_clock { + SERDES_CLOCK_100M, /* 100 MHz */ + SERDES_CLOCK_122P88M, /* 122.88 MHz */ + SERDES_CLOCK_125M, /* 125 MHz */ + SERDES_CLOCK_156P25M, /* 156.25 MHz */ + SERDES_CLOCK_312P5M, /* 312.5 MHz */ +}; + +/* SERDES Lane Baud Rate */ +enum ks2_serdes_rate { + SERDES_RATE_4P9152G, /* 4.9152 GBaud */ + SERDES_RATE_5G, /* 5 GBaud */ + SERDES_RATE_6P144G, /* 6.144 GBaud */ + SERDES_RATE_6P25G, /* 6.25 GBaud */ + SERDES_RATE_10p3125g, /* 10.3215 GBaud */ + SERDES_RATE_12p5g, /* 12.5 GBaud */ +}; + +/* SERDES Lane Rate Mode */ +enum ks2_serdes_rate_mode { + SERDES_FULL_RATE, + SERDES_HALF_RATE, + SERDES_QUARTER_RATE, +}; + +/* SERDES PHY TYPE */ +enum ks2_serdes_interface { + SERDES_PHY_SGMII, + SERDES_PHY_PCSR, /* XGE SERDES */ +}; + +struct ks2_serdes { + enum ks2_serdes_clock clk; + enum ks2_serdes_rate rate; + enum ks2_serdes_rate_mode rate_mode; + enum ks2_serdes_interface intf; + u32 loopback; +}; + +int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes); #endif /* __TI_KEYSTONE_SERDES_H__ */ diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 63f33611cb6..8a45fbd88f8 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -554,7 +554,20 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv) return 0; } +struct ks2_serdes ks2_serdes_sgmii_156p25mhz = { + .clk = SERDES_CLOCK_156P25M, + .rate = SERDES_RATE_5G, + .rate_mode = SERDES_QUARTER_RATE, + .intf = SERDES_PHY_SGMII, + .loopback = 0, +}; + static void keystone2_net_serdes_setup(void) { - ks2_serdes_sgmii_156p25mhz_setup(); + ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE, + &ks2_serdes_sgmii_156p25mhz, + CONFIG_KSNET_SERDES_LANES_PER_SGMII); + + /* wait till setup */ + udelay(5000); } diff --git a/drivers/soc/keystone/keystone_serdes.c b/drivers/soc/keystone/keystone_serdes.c index 3632c22be29..84ed9ba4e8a 100644 --- a/drivers/soc/keystone/keystone_serdes.c +++ b/drivers/soc/keystone/keystone_serdes.c @@ -7,9 +7,27 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include +#include +#define SERDES_CMU_REGS(x) (0x0000 + (0x0c00 * (x))) #define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x))) +#define SERDES_COMLANE_REGS 0x0a00 +#define SERDES_WIZ_REGS 0x1fc0 + +#define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000) +#define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010) +#define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000) +#define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000) +#define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028) +#define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x))) +#define SERDES_PLL_CTL_REG (SERDES_WIZ_REGS + 0x0034) + +#define SERDES_RESET BIT(28) +#define SERDES_LANE_RESET BIT(29) +#define SERDES_LANE_LOOPBACK BIT(30) +#define SERDES_LANE_EN_VAL(x, y, z) (x[y] | (z << 26) | (z << 10)) struct serdes_cfg { u32 ofs; @@ -17,6 +35,18 @@ struct serdes_cfg { u32 mask; }; +/* SERDES PHY lane enable configuration value, indexed by PHY interface */ +static u32 serdes_cfg_lane_enable[] = { + 0xf000f0c0, /* SGMII */ + 0xf0e9f038, /* PCSR */ +}; + +/* SERDES PHY PLL enable configuration value, indexed by PHY interface */ +static u32 serdes_cfg_pll_enable[] = { + 0xe0000000, /* SGMII */ + 0xee000000, /* PCSR */ +}; + static struct serdes_cfg cfg_cmu_156p25m_5g[] = { {0x0000, 0x00800000, 0xffff0000}, {0x0014, 0x00008282, 0x0000ffff}, @@ -91,39 +121,72 @@ static int ks2_serdes_init_156p25m_5g(u32 base, u32 num_lanes) return 0; } -void ks2_serdes_sgmii_156p25mhz_setup(void) +static void ks2_serdes_cmu_comlane_enable(u32 base, struct ks2_serdes *serdes) +{ + /* Bring SerDes out of Reset */ + ks2_serdes_rmw(base + SERDES_CMU_REG_010(0), 0x0, SERDES_RESET); + if (serdes->intf == SERDES_PHY_PCSR) + ks2_serdes_rmw(base + SERDES_CMU_REG_010(1), 0x0, SERDES_RESET); + + /* Enable CMU and COMLANE */ + ks2_serdes_rmw(base + SERDES_CMU_REG_000(0), 0x03, 0x000000ff); + if (serdes->intf == SERDES_PHY_PCSR) + ks2_serdes_rmw(base + SERDES_CMU_REG_000(1), 0x03, 0x000000ff); + + ks2_serdes_rmw(base + SERDES_COMLANE_REG_000, 0x5f, 0x000000ff); +} + +static void ks2_serdes_pll_enable(u32 base, struct ks2_serdes *serdes) +{ + writel(serdes_cfg_pll_enable[serdes->intf], + base + SERDES_PLL_CTL_REG); +} + +static void ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane) { - unsigned int cnt; - - ks2_serdes_init_156p25m_5g(CONFIG_KS2_SERDES_SGMII_BASE, - CONFIG_KS2_SERDES_LANES_PER_SGMII); - - /*Bring SerDes out of Reset if SerDes is Shutdown & is in Reset Mode*/ - clrbits_le32(0x0232a010, 1 << 28); - - /* Enable TX and RX via the LANExCTL_STS 0x0000 + x*4 */ - clrbits_le32(0x0232a228, 1 << 29); - writel(0xF800F8C0, 0x0232bfe0); - clrbits_le32(0x0232a428, 1 << 29); - writel(0xF800F8C0, 0x0232bfe4); - clrbits_le32(0x0232a628, 1 << 29); - writel(0xF800F8C0, 0x0232bfe8); - clrbits_le32(0x0232a828, 1 << 29); - writel(0xF800F8C0, 0x0232bfec); - - /*Enable pll via the pll_ctrl 0x0014*/ - writel(0xe0000000, 0x0232bff4) - ; - - /*Waiting for SGMII Serdes PLL lock.*/ - for (cnt = 10000; cnt > 0 && ((readl(0x02090114) & 0x10) == 0); cnt--) - ; - for (cnt = 10000; cnt > 0 && ((readl(0x02090214) & 0x10) == 0); cnt--) - ; - for (cnt = 10000; cnt > 0 && ((readl(0x02090414) & 0x10) == 0); cnt--) - ; - for (cnt = 10000; cnt > 0 && ((readl(0x02090514) & 0x10) == 0); cnt--) - ; - - udelay(45000); + if (reset) + ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane), + 0x1, SERDES_LANE_RESET); + else + ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane), + 0x0, SERDES_LANE_RESET); +} + +static void ks2_serdes_lane_enable(u32 base, + struct ks2_serdes *serdes, u32 lane) +{ + /* Bring lane out of reset */ + ks2_serdes_lane_reset(base, 0, lane); + + writel(SERDES_LANE_EN_VAL(serdes_cfg_lane_enable, serdes->intf, + serdes->rate_mode), + base + SERDES_LANE_CTL_STATUS_REG(lane)); + + /* Set NES bit if Loopback Enabled */ + if (serdes->loopback) + ks2_serdes_rmw(base + SERDES_LANE_REG_000(lane), + 0x1, SERDES_LANE_LOOPBACK); +} + +int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes) +{ + int i; + int ret = 0; + + /* The driver currently supports 5GBaud rate with ref clock 156.25MHz */ + if (serdes->clk == SERDES_CLOCK_156P25M) + if (serdes->rate == SERDES_RATE_5G) + ret = ks2_serdes_init_156p25m_5g(base, num_lanes); + else + return -EINVAL; + else + return -EINVAL; + + ks2_serdes_cmu_comlane_enable(base, serdes); + for (i = 0; i < num_lanes; i++) + ks2_serdes_lane_enable(base, serdes, i); + + ks2_serdes_pll_enable(base, serdes); + + return ret; } diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index 8037c3e6e29..5ba975c60c2 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -134,8 +134,10 @@ #define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE /* Keystone net */ -#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR -#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE +#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR +#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE +#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE +#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES /* AEMIF */ #define CONFIG_TI_AEMIF @@ -319,8 +321,4 @@ which is NOT applicable for DDR ECC test */ #define CONFIG_MAX_UBOOT_MEM_SIZE (4 << 20) /* 4 MiB */ -/* SGMII SerDes */ -#define CONFIG_KS2_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE -#define CONFIG_KS2_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES - #endif /* __CONFIG_KS2_EVM_H */ -- cgit v1.3.1 From 3fe93623cc5f5c5373fe0c0b7fe331f8800f4350 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Fri, 17 Oct 2014 20:44:35 +0300 Subject: net: keystone_net: register eth PHYs on MDIO bus As MDIO bus has been added we can register PHYs with it. After registration, the PHY driver will be probed according to the hardware on board. Startup PHY at the ethernet open. Use phy_startup() instead of keystone_get_link_status() when eth open, as it verifies PHY link inside and SGMII link is checked before. For K2HK evm PHY configuration at init was absent, so don't enable phy config at init for k2hk evm. Acked-by: Vitaly Andrianov Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/ti-common/keystone_net.h | 1 + drivers/net/keystone_net.c | 24 +++++++++++++++++++++--- include/configs/ks2_evm.h | 2 ++ 3 files changed, 24 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/ti-common/keystone_net.h b/arch/arm/include/asm/ti-common/keystone_net.h index e56759dc104..011c03cf888 100644 --- a/arch/arm/include/asm/ti-common/keystone_net.h +++ b/arch/arm/include/asm/ti-common/keystone_net.h @@ -239,6 +239,7 @@ struct eth_priv_t { int phy_addr; int slave_port; int sgmii_link_type; + struct phy_device *phy_dev; }; int keystone2_emac_initialize(struct eth_priv_t *eth_priv); diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 265530ad621..fa8e1ef3ce5 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -398,8 +399,8 @@ int32_t cpmac_drv_send(u32 *buffer, int num_bytes, int slave_port_num) /* Eth device open */ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) { - int link; struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + struct phy_device *phy_dev = eth_priv->phy_dev; debug("+ emac_open\n"); @@ -439,8 +440,8 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) if (sys_has_mdio) { keystone2_mdio_reset(mdio_bus); - link = keystone_get_link_status(dev); - if (link == 0) { + phy_startup(phy_dev); + if (phy_dev->link == 0) { ksnav_close(&netcp_pktdma); qm_close(); return -1; @@ -461,6 +462,9 @@ static int keystone2_eth_open(struct eth_device *dev, bd_t *bis) /* Eth device close */ void keystone2_eth_close(struct eth_device *dev) { + struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + struct phy_device *phy_dev = eth_priv->phy_dev; + debug("+ emac_close\n"); if (!emac_open) @@ -470,6 +474,7 @@ void keystone2_eth_close(struct eth_device *dev) ksnav_close(&netcp_pktdma); qm_close(); + phy_shutdown(phy_dev); emac_open = 0; @@ -522,6 +527,7 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv) { int res; struct eth_device *dev; + struct phy_device *phy_dev; dev = malloc(sizeof(struct eth_device)); if (dev == NULL) @@ -556,6 +562,18 @@ int keystone2_emac_initialize(struct eth_priv_t *eth_priv) return res; } + /* Create phy device and bind it with driver */ +#ifdef CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE + phy_dev = phy_connect(mdio_bus, eth_priv->phy_addr, + dev, PHY_INTERFACE_MODE_SGMII); + phy_config(phy_dev); +#else + phy_dev = phy_find_by_mask(mdio_bus, 1 << eth_priv->phy_addr, + PHY_INTERFACE_MODE_SGMII); + phy_dev->dev = dev; +#endif + eth_priv->phy_dev = phy_dev; + return 0; } diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index 5ba975c60c2..5b3d68b7aaa 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -92,6 +92,8 @@ #define CONFIG_SYS_SPI2_NUM_CS 4 /* Network Configuration */ +#define CONFIG_PHYLIB +#define CONFIG_PHY_MARVELL #define CONFIG_MII #define CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTP_DNS -- cgit v1.3.1 From a4d2adee110d1534705d84c573a41e6d7877f0d7 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Fri, 17 Oct 2014 20:44:36 +0300 Subject: net: keystone_net: use general get link function The phy framework has function to get link, so use it instead of own implementation. There is no reason to check SGMII link while sending each packet, phy link is enough. Check SGMII link only while ethernet open. Acked-by: Vitaly Andrianov Signed-off-by: Ivan Khoronzhuk --- drivers/net/keystone_net.c | 50 +++++----------------------------------------- include/configs/ks2_evm.h | 1 - 2 files changed, 5 insertions(+), 46 deletions(-) (limited to 'include') diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index fa8e1ef3ce5..13a1778298a 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -42,8 +42,6 @@ struct rx_buff_desc net_rx_buffs = { static void keystone2_net_serdes_setup(void); -static int gen_get_link_speed(int phy_addr); - int keystone2_eth_read_mac_addr(struct eth_device *dev) { struct eth_priv_t *eth_priv; @@ -137,19 +135,6 @@ static int keystone2_mdio_write(struct mii_dev *bus, return 0; } -/* PHY functions for a generic PHY */ -static int gen_get_link_speed(int phy_addr) -{ - u_int16_t tmp; - - tmp = mdio_bus->read(mdio_bus, phy_addr, - MDIO_DEVAD_NONE, MII_STATUS_REG); - if (tmp & 0x04) - return 0; - - return -1; -} - static void __attribute__((unused)) keystone2_eth_gigabit_enable(struct eth_device *dev) { @@ -180,35 +165,8 @@ int keystone_sgmii_link_status(int port) status = __raw_readl(SGMII_STATUS_REG(port)); - return status & SGMII_REG_STATUS_LINK; -} - - -int keystone_get_link_status(struct eth_device *dev) -{ - struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; - int sgmii_link; - int link_state = 0; -#if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1 - int j; - - for (j = 0; (j < CONFIG_GET_LINK_STATUS_ATTEMPTS) && (link_state == 0); - j++) { -#endif - sgmii_link = - keystone_sgmii_link_status(eth_priv->slave_port - 1); - - if (sgmii_link) { - link_state = 1; - - if (eth_priv->sgmii_link_type == SGMII_LINK_MAC_PHY) - if (gen_get_link_speed(eth_priv->phy_addr)) - link_state = 0; - } -#if CONFIG_GET_LINK_STATUS_ATTEMPTS > 1 - } -#endif - return link_state; + return (status & SGMII_REG_STATUS_LOCK) && + (status & SGMII_REG_STATUS_LINK); } int keystone_sgmii_config(int port, int interface) @@ -490,8 +448,10 @@ static int keystone2_eth_send_packet(struct eth_device *dev, { int ret_status = -1; struct eth_priv_t *eth_priv = (struct eth_priv_t *)dev->priv; + struct phy_device *phy_dev = eth_priv->phy_dev; - if (keystone_get_link_status(dev) == 0) + genphy_update_link(phy_dev); + if (phy_dev->link == 0) return -1; if (cpmac_drv_send((u32 *)packet, length, eth_priv->slave_port) != 0) diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index 5b3d68b7aaa..fe197dc25a9 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -101,7 +101,6 @@ #define CONFIG_BOOTP_SEND_HOSTNAME #define CONFIG_NET_RETRY_COUNT 32 #define CONFIG_NET_MULTI -#define CONFIG_GET_LINK_STATUS_ATTEMPTS 5 #define CONFIG_SYS_SGMII_REFCLK_MHZ 312 #define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 #define CONFIG_SYS_SGMII_RATESCALE 2 -- cgit v1.3.1 From 3c61502aad85e8b25b75e349dfd5a5a7eee22301 Mon Sep 17 00:00:00 2001 From: "Khoronzhuk, Ivan" Date: Fri, 17 Oct 2014 21:01:13 +0300 Subject: net: keystone_serdes: add keystone K2E SoC support Keystone2 Edison SoC uses the same keystone SerDes driver. This patch adds support for K2E SoCs. Acked-by: Vitaly Andrianov Acked-by: Murali Karicheri Signed-off-by: Ivan Khoronzhuk --- arch/arm/include/asm/arch-keystone/hardware-k2e.h | 4 ++++ drivers/net/keystone_net.c | 6 ++++++ include/configs/k2e_evm.h | 3 +++ include/configs/ks2_evm.h | 1 + 4 files changed, 14 insertions(+) (limited to 'include') diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2e.h b/arch/arm/include/asm/arch-keystone/hardware-k2e.h index fba701f5cd9..1d6fd11d03a 100644 --- a/arch/arm/include/asm/arch-keystone/hardware-k2e.h +++ b/arch/arm/include/asm/arch-keystone/hardware-k2e.h @@ -41,6 +41,10 @@ #define KS2_CIC2_DDR3_ECC_IRQ_NUM -1 /* not defined in K2E */ #define KS2_CIC2_DDR3_ECC_CHAN_NUM -1 /* not defined in K2E */ +/* SGMII SerDes */ +#define KS2_SGMII_SERDES2_BASE 0x02324000 +#define KS2_LANES_PER_SGMII_SERDES 4 + /* Number of DSP cores */ #define KS2_NUM_DSPS 1 diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 13a1778298a..43c263e612e 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -551,6 +551,12 @@ static void keystone2_net_serdes_setup(void) &ks2_serdes_sgmii_156p25mhz, CONFIG_KSNET_SERDES_LANES_PER_SGMII); +#ifdef CONFIG_SOC_K2E + ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE, + &ks2_serdes_sgmii_156p25mhz, + CONFIG_KSNET_SERDES_LANES_PER_SGMII); +#endif + /* wait till setup */ udelay(5000); } diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index 3502d104720..fd45d61fe74 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -34,4 +34,7 @@ /* NAND Configuration */ #define CONFIG_SYS_NAND_PAGE_2K +/* SerDes */ +#define CONFIG_TI_KEYSTONE_SERDES + #endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index fe197dc25a9..7c6392a3b8c 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -138,6 +138,7 @@ #define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR #define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE #define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE +#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE #define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES /* AEMIF */ -- cgit v1.3.1 From 00b821f16e65d1242b026dcc9834ddeab2fffcab Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Fri, 17 Oct 2014 21:01:17 +0300 Subject: board: k2e_evm: add network support This patch adds network support code and enables keystone_net driver usage for k2e_evm evaluation board. Acked-by: Vitaly Andrianov Acked-by: Murali Karicheri Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- board/ti/ks2_evm/board_k2e.c | 68 +++++++++++++++++++++++++++++++++++++++++++- include/configs/k2e_evm.h | 8 ++++++ 2 files changed, 75 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index 810a8e26eae..43dfc48a53d 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -10,6 +10,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -35,10 +36,75 @@ static struct pll_init_data core_pll_config[] = { CORE_PLL_1500, }; - static struct pll_init_data pa_pll_config = PASS_PLL_1000; +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +struct eth_priv_t eth_priv_cfg[] = { + { + .int_name = "K2E_EMAC0", + .rx_flow = 0, + .phy_addr = 0, + .slave_port = 1, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2E_EMAC1", + .rx_flow = 8, + .phy_addr = 1, + .slave_port = 2, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2E_EMAC2", + .rx_flow = 16, + .phy_addr = 2, + .slave_port = 3, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC3", + .rx_flow = 24, + .phy_addr = 3, + .slave_port = 4, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC4", + .rx_flow = 32, + .phy_addr = 4, + .slave_port = 5, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC5", + .rx_flow = 40, + .phy_addr = 5, + .slave_port = 6, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC6", + .rx_flow = 48, + .phy_addr = 6, + .slave_port = 7, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2E_EMAC7", + .rx_flow = 56, + .phy_addr = 7, + .slave_port = 8, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, +}; + +int get_num_eth_ports(void) +{ + return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); +} +#endif + #if defined(CONFIG_BOARD_EARLY_INIT_F) int board_early_init_f(void) { diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h index fd45d61fe74..7c8065ad187 100644 --- a/include/configs/k2e_evm.h +++ b/include/configs/k2e_evm.h @@ -34,6 +34,14 @@ /* NAND Configuration */ #define CONFIG_SYS_NAND_PAGE_2K +/* Network */ +#define CONFIG_DRIVER_TI_KEYSTONE_NET +#define CONFIG_TI_KSNAV +#define CONFIG_KSNAV_PKTDMA_NETCP +#define CONFIG_KSNET_NETCP_V1_5 +#define CONFIG_KSNET_CPSW_NUM_PORTS 9 +#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE + /* SerDes */ #define CONFIG_TI_KEYSTONE_SERDES -- cgit v1.3.1 From 26459488b70fdc40081bbff193d58be663274d51 Mon Sep 17 00:00:00 2001 From: Hao Zhang Date: Wed, 22 Oct 2014 17:47:59 +0300 Subject: ARM: keystone: cmd_ddr3: add ddr3 commands to test ddr Add ddr3 commands: test - test DDR from start\n address to end address\n ddr compare -\n compare DDR data of (size) bytes from start address to end address\n ddr ecc_err - generate bit errors\n in DDR data at , the command will read a 32-bit data\n from , and write (data ^ bit_err) back to \n Delete CONFIG_MAX_UBOOT_MEM_SIZE, as it was supposed to be used for ddr3 commands and for now it's not needed any more. Signed-off-by: Hao Zhang Signed-off-by: Ivan Khoronzhuk --- arch/arm/cpu/armv7/keystone/Makefile | 2 +- arch/arm/cpu/armv7/keystone/cmd_ddr3.c | 248 +++++++++++++++++++++++++++++++++ include/configs/ks2_evm.h | 4 - 3 files changed, 249 insertions(+), 5 deletions(-) create mode 100644 arch/arm/cpu/armv7/keystone/cmd_ddr3.c (limited to 'include') diff --git a/arch/arm/cpu/armv7/keystone/Makefile b/arch/arm/cpu/armv7/keystone/Makefile index 57f6ea6dee9..ed030db2c88 100644 --- a/arch/arm/cpu/armv7/keystone/Makefile +++ b/arch/arm/cpu/armv7/keystone/Makefile @@ -14,5 +14,5 @@ obj-$(CONFIG_SOC_K2L) += clock-k2l.o obj-y += cmd_clock.o obj-y += cmd_mon.o obj-y += msmc.o -obj-y += ddr3.o +obj-y += ddr3.o cmd_ddr3.o obj-y += keystone.o diff --git a/arch/arm/cpu/armv7/keystone/cmd_ddr3.c b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c new file mode 100644 index 00000000000..ea78ad8fd53 --- /dev/null +++ b/arch/arm/cpu/armv7/keystone/cmd_ddr3.c @@ -0,0 +1,248 @@ +/* + * Keystone2: DDR3 test commands + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define DDR_MIN_ADDR CONFIG_SYS_SDRAM_BASE + +#define DDR_REMAP_ADDR 0x80000000 +#define ECC_START_ADDR1 ((DDR_MIN_ADDR - DDR_REMAP_ADDR) >> 17) + +#define ECC_END_ADDR1 (((gd->start_addr_sp - DDR_REMAP_ADDR - \ + CONFIG_STACKSIZE) >> 17) - 2) + +#define DDR_TEST_BURST_SIZE 1024 + +static int ddr_memory_test(u32 start_address, u32 end_address, int quick) +{ + u32 index_start, value, index; + + index_start = start_address; + + while (1) { + /* Write a pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 4) + __raw_writel(index, index); + + /* Read and check the pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 4) { + value = __raw_readl(index); + if (value != index) { + printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n", + index, value, __raw_readl(index)); + + return -1; + } + } + + index_start += DDR_TEST_BURST_SIZE; + if (index_start >= end_address) + break; + + if (quick) + continue; + + /* Write a pattern for complementary values */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 4) + __raw_writel((u32)~index, index); + + /* Read and check the pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 4) { + value = __raw_readl(index); + if (value != ~index) { + printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n", + index, value, __raw_readl(index)); + + return -1; + } + } + + index_start += DDR_TEST_BURST_SIZE; + if (index_start >= end_address) + break; + + /* Write a pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 2) + __raw_writew((u16)index, index); + + /* Read and check the pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 2) { + value = __raw_readw(index); + if (value != (u16)index) { + printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n", + index, value, __raw_readw(index)); + + return -1; + } + } + + index_start += DDR_TEST_BURST_SIZE; + if (index_start >= end_address) + break; + + /* Write a pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 1) + __raw_writeb((u8)index, index); + + /* Read and check the pattern */ + for (index = index_start; + index < index_start + DDR_TEST_BURST_SIZE; + index += 1) { + value = __raw_readb(index); + if (value != (u8)index) { + printf("ddr_memory_test: Failed at address index = 0x%x value = 0x%x *(index) = 0x%x\n", + index, value, __raw_readb(index)); + + return -1; + } + } + + index_start += DDR_TEST_BURST_SIZE; + if (index_start >= end_address) + break; + } + + puts("ddr memory test PASSED!\n"); + return 0; +} + +static int ddr_memory_compare(u32 address1, u32 address2, u32 size) +{ + u32 index, value, index2, value2; + + for (index = address1, index2 = address2; + index < address1 + size; + index += 4, index2 += 4) { + value = __raw_readl(index); + value2 = __raw_readl(index2); + + if (value != value2) { + printf("ddr_memory_test: Compare failed at address = 0x%x value = 0x%x, address2 = 0x%x value2 = 0x%x\n", + index, value, index2, value2); + + return -1; + } + } + + puts("ddr memory compare PASSED!\n"); + return 0; +} + +static int ddr_memory_ecc_err(u32 base, u32 address, u32 ecc_err) +{ + u32 value1, value2, value3; + + puts("Disabling DDR ECC ...\n"); + ddr3_disable_ecc(base); + + value1 = __raw_readl(address); + value2 = value1 ^ ecc_err; + __raw_writel(value2, address); + + value3 = __raw_readl(address); + printf("ECC err test, addr 0x%x, read data 0x%x, wrote data 0x%x, err pattern: 0x%x, read after write data 0x%x\n", + address, value1, value2, ecc_err, value3); + + __raw_writel(ECC_START_ADDR1 | (ECC_END_ADDR1 << 16), + base + KS2_DDR3_ECC_ADDR_RANGE1_OFFSET); + + puts("Enabling DDR ECC ...\n"); + ddr3_enable_ecc(base, 1); + + value1 = __raw_readl(address); + printf("ECC err test, addr 0x%x, read data 0x%x\n", address, value1); + + ddr3_check_ecc_int(base); + return 0; +} + +static int do_ddr_test(cmd_tbl_t *cmdtp, + int flag, int argc, char * const argv[]) +{ + u32 start_addr, end_addr, size, ecc_err; + + if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) { + if (!ddr3_ecc_support_rmw(KS2_DDR3A_EMIF_CTRL_BASE)) { + puts("ECC RMW isn't supported for this SOC\n"); + return 1; + } + + start_addr = simple_strtoul(argv[2], NULL, 16); + ecc_err = simple_strtoul(argv[3], NULL, 16); + + if ((start_addr < CONFIG_SYS_SDRAM_BASE) || + (start_addr > (CONFIG_SYS_SDRAM_BASE + + CONFIG_MAX_RAM_BANK_SIZE - 1))) { + puts("Invalid address!\n"); + return cmd_usage(cmdtp); + } + + ddr_memory_ecc_err(KS2_DDR3A_EMIF_CTRL_BASE, + start_addr, ecc_err); + return 0; + } + + if (!(((argc == 4) && (strncmp(argv[1], "test", 5) == 0)) || + ((argc == 5) && (strncmp(argv[1], "compare", 8) == 0)))) + return cmd_usage(cmdtp); + + start_addr = simple_strtoul(argv[2], NULL, 16); + end_addr = simple_strtoul(argv[3], NULL, 16); + + if ((start_addr < CONFIG_SYS_SDRAM_BASE) || + (start_addr > (CONFIG_SYS_SDRAM_BASE + + CONFIG_MAX_RAM_BANK_SIZE - 1)) || + (end_addr < CONFIG_SYS_SDRAM_BASE) || + (end_addr > (CONFIG_SYS_SDRAM_BASE + + CONFIG_MAX_RAM_BANK_SIZE - 1)) || (start_addr >= end_addr)) { + puts("Invalid start or end address!\n"); + return cmd_usage(cmdtp); + } + + puts("Please wait ...\n"); + if (argc == 5) { + size = simple_strtoul(argv[4], NULL, 16); + ddr_memory_compare(start_addr, end_addr, size); + } else { + ddr_memory_test(start_addr, end_addr, 0); + } + + return 0; +} + +U_BOOT_CMD(ddr, 5, 1, do_ddr_test, + "DDR3 test", + "test - test DDR from start\n" + " address to end address\n" + "ddr compare -\n" + " compare DDR data of (size) bytes from start address to end\n" + " address\n" + "ddr ecc_err - generate bit errors\n" + " in DDR data at , the command will read a 32-bit data\n" + " from , and write (data ^ bit_err) back to \n" +); diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h index 7c6392a3b8c..5dae40921c8 100644 --- a/include/configs/ks2_evm.h +++ b/include/configs/ks2_evm.h @@ -319,8 +319,4 @@ #include #define CONFIG_SYS_HZ_CLOCK clk_get_rate(KS2_CLK1_6) -/* Maximum memory size for relocated U-boot at the end of the DDR3 memory - which is NOT applicable for DDR ECC test */ -#define CONFIG_MAX_UBOOT_MEM_SIZE (4 << 20) /* 4 MiB */ - #endif /* __CONFIG_KS2_EVM_H */ -- cgit v1.3.1 From f2565a551c001f0441dbe51dc31438961fce7b53 Mon Sep 17 00:00:00 2001 From: Stefan Herbrechtsmeier Date: Tue, 16 Sep 2014 17:51:06 +0200 Subject: omap3: overo: Call bootm only after successful nand read Signed-off-by: Stefan Herbrechtsmeier --- include/configs/omap3_overo.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index b17e495f5f7..d042eea1b04 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -131,8 +131,9 @@ "bootz ${loadaddr} - ${fdtaddr}\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ - "nand read ${loadaddr} linux; " \ - "bootm ${loadaddr}\0" \ + "if nand read ${loadaddr} linux; then " \ + "bootm ${loadaddr};" \ + "fi;\0" \ #define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ -- cgit v1.3.1 From f5c30c1b1c69b235f28d34f8ee1670b2028152ff Mon Sep 17 00:00:00 2001 From: Stefan Herbrechtsmeier Date: Tue, 16 Sep 2014 17:51:09 +0200 Subject: omap3: overo: Add usb host support Signed-off-by: Stefan Herbrechtsmeier --- board/overo/overo.c | 34 ++++++++++++++++++++++++++++++++++ include/configs/omap3_overo.h | 8 ++++++++ 2 files changed, 42 insertions(+) (limited to 'include') diff --git a/board/overo/overo.c b/board/overo/overo.c index 488246bcc57..66146eead5f 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -25,6 +25,11 @@ #include #include "overo.h" +#ifdef CONFIG_USB_EHCI +#include +#include +#endif + DECLARE_GLOBAL_DATA_PTR; #define TWL4030_I2C_BUS 0 @@ -474,3 +479,32 @@ int board_mmc_init(bd_t *bis) return omap_mmc_init(0, 0, 0, -1, -1); } #endif + +#if defined(CONFIG_USB_EHCI) && !defined(CONFIG_SPL_BUILD) +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED, + .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, + .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED +}; + +#define GUMSTIX_GPIO_USBH_CPEN 168 +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + /* Enable USB power */ + if (!gpio_request(GUMSTIX_GPIO_USBH_CPEN, "usbh_cpen")) + gpio_direction_output(GUMSTIX_GPIO_USBH_CPEN, 1); + + return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(void) +{ + /* Disable USB power */ + gpio_set_value(GUMSTIX_GPIO_USBH_CPEN, 0); + gpio_free(GUMSTIX_GPIO_USBH_CPEN); + + return omap_ehci_hcd_stop(); +} + +#endif /* CONFIG_USB_EHCI */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index d042eea1b04..c58636a5417 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -35,6 +35,13 @@ /* TWL4030 LED */ #define CONFIG_TWL4030_LED +/* USB EHCI */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +#define CONFIG_USB_STORAGE +#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 183 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + /* Initialize GPIOs by default */ #define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO Bank 2 */ #define CONFIG_OMAP3_GPIO_3 /* GPIO64..95 is in GPIO Bank 3 */ @@ -44,6 +51,7 @@ /* commands to include */ #define CONFIG_CMD_CACHE +#define CONFIG_CMD_USB #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ #undef CONFIG_CMD_IMI /* iminfo */ #undef CONFIG_CMD_NFS /* NFS support */ -- cgit v1.3.1 From 76bfd1625a27d72bcfeec6c1b239b70495f5fa78 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Tue, 23 Sep 2014 10:44:18 -0500 Subject: arm: am43xx: switch over to CONFIG_ENV_IS_IN_FAT By using CONFIG_ENV_IS_IN_FAT it's far easier to have a private, minimal environment for e.g. booting off of network or mounting rootfs on NFS without having to modify the configuration header. Signed-off-by: Felipe Balbi --- include/configs/am43xx_evm.h | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index 070782774d9..4472c3e5558 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -11,6 +11,9 @@ #define CONFIG_AM43XX +#define CONFIG_CMD_FAT +#define CONFIG_CMD_SAVEENV + #define CONFIG_BOARD_LATE_INIT #define CONFIG_ARCH_CPU_INIT #define CONFIG_SYS_CACHELINE_SIZE 32 @@ -82,7 +85,11 @@ /* NS16550 Configuration */ #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_FAT_WRITE #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" @@ -103,7 +110,7 @@ #ifdef CONFIG_QSPI_BOOT #define CONFIG_SYS_TEXT_BASE 0x30000000 -#undef CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_IS_IN_FAT #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED -- cgit v1.3.1 From 05180fc7085681b6c09e7b67d7a890c25e474e9d Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 9 Oct 2014 11:01:16 -0400 Subject: am335x_evm: Correct "raw" portions of DFU alt into Signed-off-by: Tom Rini --- include/configs/am335x_evm.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 476430ddd08..1ec783daf4f 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -352,10 +352,10 @@ "boot part 0 1;" \ "rootfs part 0 2;" \ "MLO fat 0 1;" \ - "MLO.raw mmc 0x100 0x100;" \ - "u-boot.img.raw mmc 0x300 0x400;" \ - "spl-os-args.raw mmc 0x80 0x80;" \ - "spl-os-image.raw mmc 0x900 0x2000;" \ + "MLO.raw raw 0x100 0x100;" \ + "u-boot.img.raw raw 0x300 0x400;" \ + "spl-os-args.raw raw 0x80 0x80;" \ + "spl-os-image.raw raw 0x900 0x2000;" \ "spl-os-args fat 0 1;" \ "spl-os-image fat 0 1;" \ "u-boot.img fat 0 1;" \ @@ -382,7 +382,7 @@ "fdt ram 0x80F80000 0x80000;" \ "ramdisk ram 0x81000000 0x4000000\0" #define DFUARGS \ - "dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \ + "dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \ DFU_ALT_INFO_MMC \ DFU_ALT_INFO_RAM \ DFU_ALT_INFO_NAND -- cgit v1.3.1