From b427decccfe983eda4f815ddcf5dcbe733cd04f6 Mon Sep 17 00:00:00 2001
From: Tom Rini <trini@konsulko.com>
Date: Mon, 20 Apr 2026 09:28:25 -0600
Subject: Squashed 'dts/upstream/' changes from 258d5b0e2447..0f7b6a4fa8c5

0f7b6a4fa8c5 Merge tag 'v7.0-dts-raw'
2ee059ad64bc Merge tag 'sound-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
0e5e2595317a Merge tag 'net-7.0-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
3d8eb1e4ab16 Merge tag 'hid-for-linus-2026040801' of git://git.kernel.org/pub/scm/linux/kernel/git/hid/hid
c65c7bc04464 Merge tag 'soc-fixes-7.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
89ac80ac458e ASoC: dt-bindings: ti,tas2552: Add sound-dai-cells
886c87e1d20d Merge tag 'v7.0-rc7-dts-raw'
ab2fb67b93ff Merge tag 'usb-7.0-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
cedc3ce5a407 Merge tag 'at91-fixes-7.0' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/fixes
c0bd3803eea5 dt-bindings: net: Fix Tegra234 MGBE PTP clock
6f80847c7834 Merge tag 'gpio-fixes-for-v7.0-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
7254a1c879c8 Merge tag 'auxdisplay-v7.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-auxdisplay
ae38f964b0e9 Merge tag 'qcom-arm64-fixes-for-7.0-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes
4ac746a07cd1 Merge tag 'sunxi-fixes-for-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes
45d8428a0506 Merge tag 'renesas-fixes-for-v7.0-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes
205268038e36 Merge tag 'hisi-dts-fixes-for-7.0' of https://github.com/hisilicon/linux-hisi into arm/fixes
250c64641844 Merge tag 'reset-fixes-for-v7.0-2' of https://git.pengutronix.de/git/pza/linux into arm/fixes
6f42528db7ff dt-bindings: connector: add pd-disable dependency
95e5d15bf904 Merge tag 'v7.0-rc6-dts-raw'
255618d9c419 arm64: dts: qcom: hamoa: Fix incomplete Root Port property migration
d02507a2f43d dt-bindings: gpio: fix microchip #interrupt-cells
fe62c4380d42 Input: add keycodes for contextual AI usages (HUTRR119)
ecf92feb8ef2 Merge tag 'v7.0-rockchip-dtsfixes1-v2' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes
04f90a9fb494 Merge tag 'imx-fixes-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into arm/fixes
f73f1b9408b8 dt-bindings: display/msm: qcm2290-mdss: Fix missing ranges in example
5ecb37d519a4 ASoC: adau1372: Fix error handling in adau1372_set_power()
9909a4af67ac arm64: dts: renesas: sparrow-hawk: Reserve first 128 MiB of DRAM
230b81813707 ASoC: dt-bindings: stm32: Fix incorrect compatible string in stm32h7-sai match
e26149984a37 arm64: dts: qcom: agatti: Fix IOMMU DT properties
f7978b1d9e30 dt-bindings: media: venus: Fix iommus property
671b5c92b402 dt-bindings: display: msm: qcm2290-mdss: Fix iommus property
449ff6626b43 arm64: dts: allwinner: sun55i: Fix r-spi DMA
b1402f1dc2e2 reset: spacemit: k3: Decouple composite reset lines
b15317e7accc ARM: dts: microchip: sam9x7: fix gpio-lines count for pioB
1c8975c65a4b Merge tag 'v7.0-rc5-dts-raw'
6d87e2bc2c27 arm64: dts: hisilicon: hi3798cv200: Add missing dma-ranges
175b76680d3e arm64: dts: hisilicon: poplar: Correct PCIe reset GPIO polarity
83fb5283a386 Merge tag 'regulator-fix-v7.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
eeb1c67582b8 Merge tag 'mtd/fixes-for-7.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
0d188ae18393 Merge tag 'soc-fixes-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
f984219e1c2a arm64: dts: qcom: monaco: Reserve full Gunyah metadata region
df0a8f8037b9 arm64: dts: imx8mq-librem5: Bump BUCK1 suspend voltage up to 0.85V
20dcc98b93ee Revert "arm64: dts: imx8mq-librem5: Set the DVS voltages lower"
29e5e850cab9 Revert "ARM: dts: imx: move nand related property under nand@0"
f30193c4453e regulator: dt-bindings: fix typos in regulator-uv-* descriptions
c631fcd413bc ASoC: dt-bindings: rockchip: Add compatible for RK3576 SPDIF
6285a7235b0d Merge tag 'v7.0-rc4-dts-raw'
d44f2d912bd2 Merge tag 'i2c-for-7.0-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
6ce3b78df9af Merge tag 'renesas-fixes-for-v7.0-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/fixes
02045255e368 Merge tag 'drm-fixes-2026-03-14' of https://gitlab.freedesktop.org/drm/kernel
25d9d22d1150 Merge tag 'spi-fix-v7.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
714d6872b448 Merge tag 'drm-msm-fixes-2026-03-06' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
ef094460269a Merge tag 'powerpc-7.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
eadcbbfb08db dt-bindings: mtd: st,spear600-smi: Fix example
f9d4680ccb75 dt-bindings: mtd: st,spear600-smi: #address/size-cells is mandatory
b08c91776a9f dt-bindings: mtd: st,spear600-smi: Fix description
1e28ec3f1d54 spi: dt-bindings: sun6i: Allow Dual SPI and Quad SPI for newer SoCs
4622b3cb6da6 dt-bindings: i2c: dw: Update maintainer
d43401f40fa6 Merge tag 'v7.0-rc3-dts-raw'
bb60ef867d32 Merge tag 'hwmon-for-v7.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
29ca806b0f5e powerpc: dts: mpc83xx: Add unit addresses to /memory
ad5ff447814f powerpc: dts: mpc8315erdb: Add missing #cells properties to SPI bus
bb87ffb59ac7 powerpc: dts: mpc8315erdb: Rename LED nodes to comply with schema
4c8ef8cc4349 powerpc: dts: mpc8315erdb: Use IRQ_TYPE_* macros
7df07ab447d2 powerpc: dts: mpc8313erdb: Use IRQ_TYPE_* macros
18d294f660a5 dt-bindings: powerpc: Add Freescale/NXP MPC83xx SoCs
5a3981e886f4 Merge tag 'sound-7.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
5d4c6f999c79 arm64: dts: renesas: r8a78000: Fix out-of-range SPI interrupt numbers
fd633fa28212 arm64: dts: renesas: rzg3s-smarc-som: Set bypass for Versa3 PLL2
7b10299bc62f arm64: dts: renesas: r9a09g087: Fix CPG register region sizes
3367a3da5512 arm64: dts: renesas: r9a09g077: Fix CPG register region sizes
a0216b8c62e7 arm64: dts: renesas: r9a09g057: Remove wdt{0,2,3} nodes
0ea8548222a4 arm64: dts: renesas: rzv2-evk-cn15-sd: Add ramp delay for SD0 regulator
bfbd4713207b arm64: dts: renesas: rzt2h-n2h-evk: Add ramp delay for SD0 card regulator
8f7f462e855b dt-bindings: display/msm: qcom,sm8750-mdss: Fix model typo
b0105bf2ff13 dt-bindings: display: msm: Fix reg ranges and clocks on Glymur
bb1688d262d5 Merge tag 'net-7.0-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
5ea472f3bf7c Merge tag 'riscv-soc-fixes-for-v7.0-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes
0b25fad21c5f arm64: dts: qcom: monaco: Fix UART10 pinconf
ebd44a7a8f1e ASoC: dt-bindings: renesas,rz-ssi: Document RZ/G3L SoC
43a6310e0b23 powerpc: dts: fsl: Drop unused .dtsi files
9a329fe2d894 dt-bindings: auxdisplay: ht16k33: Use unevaluatedProperties to fix common property warning
1d251b587dea dt-bindings: hwmon: sl28cpld: Drop sa67mcu compatible
8fc9fac8b677 ASoC: dt-bindings: tegra: Add compatible for Tegra238 sound card
f7a31219fbe7 dt-bindings: net: can: nxp,sja1000: add reference to mc-peripheral-props.yaml
a394424f72ae Merge tag 'v7.0-rc2-dts-raw'
d08d81384b5e Merge tag 'spi-fix-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
4a0fd4211639 arm64: dts: imx93-tqma9352: improve eMMC pad configuration
9cbc1d4aa426 arm64: dts: imx91-tqma9131: improve eMMC pad configuration
59794ebc677e arm64: dts: imx93-9x9-qsb: change usdhc tuning step for eMMC and SD
fec240ccc5a0 arm64: dts: imx8mq: Set the correct gpu_ahb clock frequency
172138635790 spi: dt-bindings: snps,dw-abp-ssi: Remove unused bindings
2dc6354f4af3 arm64: dts: qcom: qcm6490-idp: Fix WCD9370 reset GPIO polarity
e35289a71311 arm64: dts: qcom: hamoa/x1: fix idle exit latency
81f7574087fe Merge tag 'v7.0-rc1-dts-raw'
eb816f7677f7 regulator: dt-bindings: mt6359: make regulator names unique
4956bc4ca9de Revert "arm64: dts: rockchip: Further describe the WiFi for the Pinebook Pro"
f71d66625968 Merge tag 'rtc-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
ea14902fe993 Merge tag 'i2c-for-7.0-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
30b331d4b38e Merge tag 'sound-fix-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
7f20326eebd0 Merge branch 'i2c/i2c-host-2' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
f058abf5b2ca Merge tag 'asoc-fix-v7.0-merge-window' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
47b192965593 ASoC: dt-bindings: asahi-kasei,ak5558: Fix the supply names
8e3ff6b6e0f1 ASoC: dt-bindings: asahi-kasei,ak4458: Fix the supply names
1bdcb99a73c9 ASoC: dt-bindings: asahi-kasei,ak4458: set unevaluatedProperties:false
2bbbeb0e7579 Merge tag 'dmaengine-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
70a572693eca Merge tag 'phy-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
80d9b9833242 Merge tag 'soundwire-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire
fc094c09d520 Merge tag 'usb-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
3af47c3138ac Merge tag 'tty-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty
323c63de0303 Merge tag 'char-misc-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
2c1f5f24e9ef Merge tag 'linux-watchdog-6.20-rc1' of git://www.linux-watchdog.org/linux-watchdog
c824dfdf99bf Merge tag 'leds-next-6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds
d24edeef0cd3 Merge tag 'backlight-next-6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight
38ba39a8a02c Merge tag 'mfd-next-6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
7f0f8d32fbbc Merge tag 'pinctrl-v7.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
3ed15538ea59 Merge tag 'mips_7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
87344539d55d Merge tag 'i2c-for-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
2c01127cb7fe Merge tag 'input-for-v7.0-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
ae6287628368 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
68cca576a098 Merge branch 'next' into for-linus
e8ae3c914195 Merge tag 'loongarch-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
4bd56abfed21 Merge tag 'rproc-v7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux
469ab8f87279 Merge tag 'mailbox-v6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
279461aa2ca1 Merge branches 'clk-aspeed' and 'clk-qcom' into clk-next
bb87a0437342 Merge branches 'clk-imx', 'clk-divider', 'clk-rockchip' and 'clk-microchip' into clk-next
a44cbb15f262 Merge branches 'clk-amlogic', 'clk-thead', 'clk-mediatek' and 'clk-samsung' into clk-next
d66f354507f5 Merge branches 'clk-renesas', 'clk-cleanup', 'clk-spacemit' and 'clk-tegra' into clk-next
64f131e35069 Merge tag 'mtd/for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
2ea8429cb6c7 Merge tag 'nand/for-7.0' into mtd/next
c97375b771ff Merge tag 'riscv-for-linus-7.0-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
0bef48a293b0 Merge tag 'for-v7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply
2485149cfe0d Merge tag 'ata-6.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux
e937a56c89b0 Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
b837f21c681a Merge tag 'for-linus' of https://github.com/openrisc/linux
9fa7d35f68c2 ASoC: dt-bindings: asahi-kasei,ak5558: Reference common DAI properties
a023f11b1edb Merge tag 'net-next-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next
b86161c7e1ec Merge tag 'devicetree-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
15103153d3f7 Merge tag 'pci-v7.0-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
a35a7827d08e Merge tag 'drm-next-2026-02-11' of https://gitlab.freedesktop.org/drm/kernel
2a8556f9eecc Merge tag 'media/v7.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media
b93c5ab0b805 Merge tag 'sound-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
243a1edd6d09 Merge tag 'hwmon-for-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging
507ddba63e3f Merge tag 'gpio-updates-for-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
2ee644a1dc90 Merge tag 'pwrseq-updates-for-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
8e02b14f6c91 Merge tag 'pwm/for-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
68edd291177b Merge tag 'spi-v6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
b31400b246c8 Merge tag 'regulator-v6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator
81ece41ce8ae dt-bindings: net: dsa: add MaxLinear MxL862xx
8f967c541482 Merge tag 'soc-dt-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
6e7f6ca4e88c Merge tag 'soc-drivers-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
aa32a0ebc3a7 dt-bindings: interrupt-controller: Add compatiblie string fsl,imx(1|25|27|31|35)-avic
4a9ee4ae797f Merge tag 'irq-drivers-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
e3eae9ec4856 ASoC: Merge up release
decaee82cb13 Merge tag 'v7.0-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
29d6648cce9a LoongArch: dts: loongson-2k1000: Add nand controller support
2046ea79bada LoongArch: dts: loongson-2k0500: Add nand controller support
e6e0d1a06767 dt-bindings: net: dsa: lantiq,gswip: reference common PHY properties
495e7f9e2b7d dt-bindings: input: qcom,pm8941-pwrkey: Document PMM8654AU
f2611a8ac07e Merge tag 'thermal-6.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
4e6206cce433 dt-bindings: soc: imx: add fsl,aips and fsl,emi compatible strings
ed2533566b6f dt-bindings: display: bridge: lt8912b: Drop reset gpio requirement
9777625ba13d Merge tag 'pm-6.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
f9b1cda42d68 Merge tag 'asoc-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-linus
440b93b165c2 dt-bindings: trivial-devices: Add hitron,hac300s
6c474d901a04 dt-bindings: i2c: Add CP2112 HID USB to SMBus Bridge
9a9a07c8d8f1 Merge branch 'pci/controller/dwc-qcom-ep'
6d8625fbc93c Merge branch 'pci/controller/dwc-imx6'
148c83cf986b Merge branch 'pci/controller/aspeed'
6a588260a00e riscv: dts: microchip: add can resets to mpfs
df86f7273fc0 ASoC: dt-bindings: fsl,imx-asrc: Add support for i.MX952 platform
8b04664b116a spi: cadence-qspi: Add Renesas RZ/N1 support
15351a537c20 spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list
a65f196bd27f Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
0e8afdb51c12 dt-bindings: usb: renesas,usbhs: Add RZ/G3E SoC support
52032279a84b Merge tag 'wireless-next-2026-02-04' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
0db094276416 dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/G3L RMII{tx,rx} clocks
44492dbc45e6 dt-bindings: net: nxp,s32-dwmac: Use the GPR syscon
7ce5faa19695 ASoC: ti: davinci-mcasp: Add asynchronous mode
86668f9ec320 Samsung S2MPG10 regulator and S2MPG11 PMIC drivers
f4fd1ca09f1a ASoC: dt-bindings: davinci-mcasp: Add properties for asynchronous mode
83340f50b750 dt-bindings: dma: qcom,gpi: Update max interrupts lines to 16
c356e9e09dc8 dt-bindings: i2c: qcom-cci: Document qcs8300 compatible
9218d5618630 dt-bindings: phy: ti,control-phy-otghs: convert to DT schema
8934b08a621e dt-bindings: phy: ti,phy-usb3: convert to DT schema
cb0b26459316 ASoC: dt-bindings: fsl_rpmsg: Add compatible string for i.MX952
cd392ac6ba7d ASoC: dt-bindings: fsl_rpmsg: Add compatible string for i.MX94
b5f6cd4eae79 regulator: dt-bindings: add s2mpg11-pmic regulators
dd1a48948b7c regulator: dt-bindings: add s2mpg10-pmic regulators
7cb79dceffc0 dt-bindings: firmware: google,gs101-acpm-ipc: convert regulators to lowercase
a707e0922d03 dt-bindings: mfd: da9055: Fix dead link to codec binding
83da84647e2a dt-bindings: input: touchscreen: imagis: allow linux,keycodes for ist3038
c37dc965dde0 dt-bindings: leds: Convert ti,lm3697 to DT schema
93c05dbec2bb dt-bindings: mfd: Add samsung,s2mpg11-pmic
aa62dfb78f24 dt-bindings: mfd: samsung,s2mpg10-pmic: Link to its regulators
dfdbbb234175 dt-bindings: mfd: samsung,s2mps11: Split s2mpg10-pmic into separate file
4699e70cc981 dt-bindings: backlight: qcom-wled: Document ovp values for PMI8950
12098b970450 dt-bindings: backlight: qcom-wled: Document ovp values for PMI8994
a4f601b4b83a dt-bindings: interrupt-controller: sifive,plic: Clarify the riscv,ndev meaning in PLIC
b34cf04f8fff dt-bindings: leds: Add new as3668 support
54c72cac692d dt-bindings: leds: qcom,spmi-flash-led: Add PMH0101 compatible
f573a833305f dt-bindings: leds: leds-qcom-lpg: Add support for PMH0101 PWM
210e33780610 dt-bindings: leds: Allow differently named multicolor LEDs
0a514b51f7e8 dt-bindings: leds: add TI/National Semiconductor LP5812 LED Driver
dcab4d11d3d1 dt-bindings: leds: Add issi,is31fl3293 to leds-is31fl32xx
dc07d15b4ce3 Merge tag 'soc_fsl-6.20-1' of https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux into soc/drivers
69547b8ff1ab Merge tag 'socfpga_dts_updates_for_v6.20_v3' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
4da7192337e7 dt-bindings: clock: aspeed: Add VIDEO reset definition
0f8478e9fd54 dt-bindings: firmware: fsl,scu: Mark multi-channel MU layouts as deprecated
7af06f6732db dt-bindings: Fix emails with spaces or missing brackets
912a24228bf6 scripts/dtc: Update to upstream version v1.7.2-62-ga26ef6400bd8
b45398f9313a dt-bindings: crypto: inside-secure,safexcel: Mandate only ring IRQs
de1e0845cd7a dt-bindings: crypto: inside-secure,safexcel: Add SoC compatibles
b9cdb24e70f8 dt-bindings: display/lvds-codec: Document OnSemi FIN3385
83226b0d27c4 dt-bindings: eeprom: at25: Document Microchip 25AA010A
df9ef8a7ea46 dt-bindings: display: bridge: nxp,tda998x: Add missing clocks
9ab7ad07fb14 dt-bindings: omap: ti,prm-inst: Convert to DT schema
1e1d998bf71f dt-bindings: display: mediatek: Fix typo 'hardwares' to 'hardware'
4b0a6a44b1ae dt-bindings: mfd: Add Realtek RTD1xxx system controllers
a2e45807633d dt-bindings: mediatek: Replace Tinghan Shen in maintainers
ab9efcd5b4d8 dt-bindings: Fix I2C bus node names in examples
ea4479bba282 dt-bindings: display: google,goldfish-fb: Convert to DT schema
50fcb2d67f08 dt-bindings: display: bridge: tc358867: mark port 0 and 1 configuration as valid
a2be43cbd73a docs: dt: submitting-patches: Document prefixes for SCSI and UFS
91b31105e870 dt-bindings: display: bridge: ldb: Add check for reg and reg-names
37e7a9a4d189 dt-bindings: Add IEI vendor prefix and IEI WT61P803 PUZZLE driver bindings
b212fd6852bf dt-bindings: trivial-devices: Add some more undocumented devices
27fef65a6743 dt-bindings: interrupt-controller: loongson,pch-pic: Document address-cells
a7865d05a69e dt-bindings: interrupt-controller: loongson,eiointc: Document address-cells
ce188cc0a6b5 dt-bindings: interrupt-controller: loongson,liointc: Document address-cells
94a7b2f99ab9 dt-bindings: power: syscon-poweroff: Allow "reg" property
02fb67f1073a dt-bindings: reset: syscon-reboot: Allow both 'reg' and 'offset'
ee58ad218d78 dt-bindings: mediatek: Drop inactive MandyJH Liu
33ae9e289d97 dt-bindings: arm: Drop obsolete brcm,vulcan-soc binding
c545c28a92fa dt-bindings: net: brcm,amac: Allow "dma-coherent" property
6c2903f6738c dt-bindings: raspberrypi,bcm2835-firmware: Add 'power' and gpio-hog nodes
49bb56c3e9db dt-bindings: firmware: Convert cznic,turris-mox-rwtm to DT schema
a6b60a4d1020 dt-bindings: trivial-devices: Add socionext,uniphier-smpctrl
c105f1786874 dt-bindings: firmware: xilinx: Add conditional pinctrl schema
e9fd71a307d0 dt-bindings: firmware: xilinx: Add xlnx,zynqmp-firmware compatible
2909e69780fb dt-bindings: Remove unused includes
c661f5a650e8 dt-bindings: bus: stm32mp25-rifsc: Allow 2 size cells
530a274b1478 dt-bindings: arm: vexpress-config: Update clock and regulator node names
21658b9cc7b8 dt-bindings: arm,vexpress-juno: Allow interrupt-map properties in bus node
93864a267471 Merge tag 'i2c-host-6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow
84dea826479a dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property
e327cd40e3da dt-bindings: spi: Add binding for Faraday FTSSP010
9382fcae3b33 dt-bindings: net: renesas,rzv2h-gbeth: Document Renesas RZ/G3L SoC
da8c0cc63159 dt-bindings: intel: Add Agilex eMMC support
395dec8b9e96 dt-bindings: ptp: Add amazon,vmclock
a03e77de0210 dt-bindings: clk: rs9: Fix DIF pattern match
deb3391513da dt-bindings: pinctrl: spacemit: fix drive-strength check warning
ab6224bd25a0 Anbernic RG-DS AW87391 Speaker Amps
ba961ac73236 spi: add multi-lane support
716bd68da03b Merge tag 'ath-next-20260202' of git://git.kernel.org/pub/scm/linux/kernel/git/ath/ath
b47c8ccd309d Merge tag 'iio-for-7.0a' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next
17926b594c18 ASoC: dt-bindings: aw87390: Add Anbernic RG-DS Amplifier
ccac1121bf5d spi: dt-bindings: adi,axi-spi-engine: add multi-lane support
90e272c43203 spi: dt-bindings: add spi-{tx,rx}-lane-map properties
89b0a2b708ca spi: dt-bindings: change spi-{rx,tx}-bus-width to arrays
cd5ffacefa9c dt-bindings: mailbox: sprd: add compatible for UMS9230
db37cc33492c Merge tag 'linux-can-next-for-6.20-20260131' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next
e8ed1e9c377d dt-bindings: hwmon: ti,tmp108: Add P3T1035,P3T2030
365e8a1582ea dt-bindings: hwmon: add STEF48H28
997d978c1b6d dt-bindings: hwmon: Convert aspeed,ast2400-pwm-tacho to DT schema
690c98671a72 dt-bindings: hwmon: Add mps mp5926 driver bindings
564ddb6df33f dt-bindings: hwmon: sparx5: add microchip,lan9691-temp
1d92dd74de54 dt-bindings: crypto: atmel,at91sam9g46-sha: add microchip,lan9691-sha
cd9c2e267512 dt-bindings: crypto: atmel,at91sam9g46-aes: add microchip,lan9691-aes
02798af51a1f dt-bindings: crypto: qcom,inline-crypto-engine: document the Milos ICE
d2455b901b36 dt-bindings: rtc: loongson: Document Loongson-2K0300 compatible
bc6078cc0df8 dt-bindings: rtc: loongson: Correct Loongson-1C interrupts property
9bef11db9e5d dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2N support
18d100dd8bed Merge tag 'ib-mfd-clk-gpio-power-regulator-rtc-v6.20' into psy-next
7ee840ee2bb4 dt-bindings: power: supply: google,goldfish-battery: Convert to DT schema
b95dfde1e21c Merge tag 'icc-6.20-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next
495473158a94 arm64: dts: socfpga: agilex: add emmc support
f2e2a903f7c4 arm64: dts: intel: agilex5: Add simple-bus node on top of dma controller node
3c1d9adbbb4f ARM: dts: socfpga: fix dtbs_check warning for fpga-region
4f486b92adf8 ARM: dts: socfpga: add #address-cells and #size-cells for sram node
c14992693977 dt-bindings: altera: document syscon as fallback for sys-mgr
d61c18c961fd arm64: dts: altera: Use lowercase hex
ffa2813091d4 dt-bindings: arm: altera: combine Intel's SoCFPGA into altera.yaml
7d049975239c arm64: dts: socfpga: agilex5: Add IOMMUS property for ethernet nodes
0c92577cfcce arm64: dts: socfpga: agilex5: add support for modular board
e115510a1af8 dt-bindings: intel: Add Agilex5 SoCFPGA modular board
c13f5487f5c8 arm64: dts: socfpga: agilex5: Add dma-coherent property
65ea42aefdeb dt-bindings: net: wireless: ath11k-pci: deprecate 'firmware-name' property
5fb812de23e3 MIPS: Loongson64: dts: fix phy-related definition of LS7A GMAC
a777939415eb Merge tag 'wireless-next-2026-01-29' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next
5b25d9c784d6 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
17229d6a4193 dt-bindings: mtd: mxic,multi-itfc-v009-nand-controller: convert to DT schema
ddb90395af99 dt-bindings: mtd: st,spear600-smi: convert to DT schema
d1f4e3e6577c dt-bindings: bluetooth: qcom,wcn7850-bt: Deprecate old supplies
40407758b2c0 dt-bindings: bluetooth: qcom,wcn7850-bt: Split to separate schema
a9dd4631cf9f dt-bindings: bluetooth: qcom,wcn6855-bt: Deprecate old supplies
c4f851db3817 dt-bindings: bluetooth: qcom,wcn6855-bt: Split to separate schema
d710994f6078 dt-bindings: bluetooth: qcom,wcn6750-bt: Deprecate old supplies
33043a03d1d0 dt-bindings: bluetooth: qcom,wcn6750-bt: Split to separate schema
640efe2d3365 dt-bindings: bluetooth: qcom,wcn3990-bt: Split to separate schema
bca7304e36f5 dt-bindings: bluetooth: qcom,wcn3950-bt: Split to separate schema
630bedc470e1 dt-bindings: bluetooth: qcom,qca6390-bt: Split to separate schema
184210b27185 dt-bindings: bluetooth: qcom,qca9377-bt: Split to separate schema
8ef4770b2049 dt-bindings: bluetooth: qcom,qca2066-bt: Split to separate schema
f2f34664c2bb dt-bindings: rtc: cpcap: convert to schema
aa5a96523dc7 Merge tag 'ti-k3-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt
ad228b618c5c Merge tag 'reset-for-v6.20' of https://git.pengutronix.de/git/pza/linux into soc/drivers
2c4ab1bdec23 Merge tag 'memory-controller-drv-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
8b32c00a7d34 Merge tag 'mtk-soc-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers
2439f10093a3 dt-bindings: gpio: Add Tegra264 support
f0df035c0c45 Merge tag 'riscv-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt
1c97c2610a0b arm64: dts: realtek: Add Kent SoC and EVB device trees
1f33f7c43645 dt-bindings: arm: realtek: Add Kent Soc family compatibles
6605244467ae spi: dt-bindings: cdns,qspi-nor: Drop label in example
265917026231 Merge tag 'qcom-arm32-for-6.20-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
c00f9fa57059 Merge tag 'qcom-arm64-for-6.20-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
325bb381f318 Merge tag 'v6.20-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
555ee47a2399 Merge tag 'v6.20-rockchip-dts32-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
de2a0ddc7b4b Merge tag 'cix-dt-binding-v6.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix into soc/dt
4492b3dafd64 Merge tag 'at91-dt-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
060ef5aec09b Merge tag 'cix-dt-v6.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix into soc/dt
ac68fadae144 Merge tag 'mvebu-dt64-6.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
845fb01169db Merge tag 'mtk-dts64-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
057d6e3b56bc Merge tag 'omap-for-v6.20/dt-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt
1b67d2271cf1 Merge tag 'sunxi-dt-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt
08dfcf6a3c7a Merge tag 'amlogic-arm-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
0b0db6acc294 Merge tag 'amlogic-arm64-dt-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt
4875ee63a5f6 Merge tag 'spacemit-dt-for-6.20-1' of https://github.com/spacemit-com/linux into soc/dt
5afe3cf7196c Merge tag 'samsung-dt64-6.20-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
cc40d0637dfb Merge tag 'arm-soc/for-6.20/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
84a304b3617b Merge tag 'arm-soc/for-6.20/devicetree' of https://github.com/Broadcom/stblinux into soc/dt
5780a44b19e3 Merge tag 'riscv-sophgo-dt-for-v6.20' of https://github.com/sophgo/linux into soc/dt
0b183bbc2f6e Merge tag 'stm32-dt-for-v6.20-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
ce1a9421c509 Merge tag 'imx-dt64-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
21b1bcafcaca Merge tag 'imx-bindings-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
86816d60ae02 Merge tag 'tegra-for-6.20-dt-bindings-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
ed7af28da2c5 spi: aspeed: Improve handling of shared SPI
a665daba0d97 Merge tag 'drm-msm-next-2026-01-23' of https://gitlab.freedesktop.org/drm/msm into drm-next
16ee8d7989d5 BackMerge tag 'v6.19-rc7' into drm-next
1853af96d104 ASoC: sophgo: add CV1800 I2S controllers support
780880d26b9d ASoC: codec: Remove ak4641/pxa2xx-ac97 and convert to
bff1a05b39e9 ASoC: fsl_audmix: Support the i.MX952 platform
d0ef9cf11b6c Merge tag 'cpufreq-arm-updates-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm
a523ea22f5ca ASoC: dt-bindings: sophgo,cv1800b: add ADC/DAC codec
b1d4ce2ec63d ASoC: dt-bindings: sophgo,cv1800b: add I2S/TDM controller
40a6f1af07a1 dt-bindings: net: dsa: lantiq,gswip: add Intel GSW150
f0bd27beed6b dt-bindings: net: dsa: lantiq,gswip: use correct node name
865b8eb5f662 dt-bindings: gpio: aspeed,sgpio: Support ast2700
0baa9004dc14 dt-bindings: pinctrl: pinctrl-microchip-sgpio: add LAN969x
c64e8b8c5daa dt-bindings: pinctrl: ocelot: Add LAN9645x SoC support
3ee75e871f21 dt-bindings: cpufreq: qcom-hw: document Milos CPUFREQ Hardware
a02f9ab1778c ASoC: dt-bindings: fsl,mqs: make gpr optional for SM-based SoCs
42533ee12386 Merge tag 'imx-dt-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt
dc8c5878de8a dt-bindings: nvmem: qfprom: Add sm8750 compatible
7d952fdf2bad dt-bindings: interrupt-controller: ti,sci-intr: Per-line interrupt-types
5d44654a0b87 Merge tag 'qcom-arm64-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
2ae181b8dafe Merge tag 'qcom-arm32-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
14de830eba79 Merge tag 'zynqmp-dt-for-6.20' of https://github.com/Xilinx/linux-xlnx into soc/dt
dbc7a3043d1b Merge tag 'tegra-for-6.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
86fccd1393e0 Merge tag 'tegra-for-6.20-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
b3bbbd413424 ARM: dts: samsung: Drop s3c6400.dtsi
56ffd66515b6 ARM: dts: nuvoton: Minor whitespace cleanup
2d6d64b741fe Merge tag 'samsung-dt64-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
f7832d977951 Merge tag 'dt64-cleanup-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
0bf8d0a20391 Merge tag 'renesas-dts-for-v6.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
41635a78d26e Merge tag 'renesas-dt-bindings-for-v6.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
6b08b2fbfdba ASoC: dt-bindings: fsl,sai: Add AUDMIX mode support on i.MX952
0369e048eed5 ASoC: dt-bindings: fsl,audmix: Add support for i.MX952 platform
3bfdd9e93746 Merge tag 'coresight-next-v7.0' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next
78fc6e7674cb Merge 6.19-rc7 into char-misc-next
6c694a1d3492 dt-bindings: riscv: document zicfilp and zicfiss in extensions.yaml
e896bfea195a dt-bindings: net: dsa: fix typos in bindings docs
a717efe4904c dt-bindings: input: touchscreen: tsc2007: document '#io-channel-cells'
8a5cf8346b98 dt-bindings: mailbox: xlnx,zynqmp-ipi-mailbox: Document msg region requirement
e625e7e40aad dt-bindings: soc: spacemit: Add K3 reset support and IDs
bed4a6ca81d3 Merge tag 'at24-updates-for-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into i2c/for-mergewindow
1cc20aca3cb4 scsi: ufs: dt-bindings: Document bindings for SA8255P UFS Host Controller
324a883d1ce7 dt-bindings: spmi: spmi-mtk-pmif: Add compatible for MT8189 SoC
f399c85dbf55 dt-bindings: spmi: add support for glymur-spmi-pmic-arb (arbiter v8)
3d1d144c4506 dt-bindings: spmi: split out common QCOM SPMI PMIC arbiter properties
f7d8363b0843 dt-bindings: spmi: Add MediaTek MT8196 SPMI 2 Arbiter/Controllers
46e850238166 dt-bindings: serial: renesas,scif: Document RZ/G3L SoC
d52ec46dfea8 ASoC: dt-bindings: Convert ti,tas2552 to DT schema
67237f73e2ea arm64: dts: a7k: add COM Express boards
997674eb03ed dt-bindings: connector: Add PCIe M.2 Mechanical Key M connector
fad4d61f0c13 dt-bindings: iio: dac: Add max22007
24b1b9c62f63 ARM: dts: microchip: Drop usb_a9g20-dab-mmx.dtsi
3e03f55262c8 dt-bindings: crypto: Mark zynqmp-aes as Deprecated
2972aa85ad35 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
93faaa70d9fd Merge tag 'drm-misc-next-2026-01-22' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
a06faf23cf0d dt-bindings: clock: mediatek,mt7622-pciesys: Remove syscon compatible
e64d84f2a956 dt-bindings: iio: adc: ad7768-1: add new supported parts
7863431b12b7 arm64: dts: rockchip: Fix rk3588 PCIe range mappings
23e93403e47f arm64: dts: rockchip: Fix rk356x PCIe range mappings
e855bd09b3f1 arm64: dts: rockchip: Add Anbernic RG-DS
edf7453bfcce dt-bindings: input: touchscreen: goodix: Add "panel" property
35bee1b28956 dt-bindings: arm: rockchip: Add Anbernic RG-DS
438f1fe833e0 arm64: dts: rockchip: Explicitly request UFS reset pin on RK3576
e8b033a60c3a arm64: dts: rockchip: Add TPS65185 for PineNote
f4b46b8ffd28 riscv: dts: allwinner: d1: Add CPU thermal sensor and zone
1bb5decc55c6 dt-bindings: mfd: qcom,spmi-pmic: Document PMICs present on Glymur and Kaanapali
e9550eb87e31 dt-bindings: mfd: Document smp-memram subnode for aspeed,ast2x00-scu
949de4abbc1e dt-bindings: mfd: mediatek: mt6397: Add missing MT6331 regulator compat
6fedf06a87f0 dt-bindings: mfd: mediatek,mt8195-scpsys: Add mediatek,mt6795-scpsys
3d469bea90a9 dt-bindings: mfd: atmel,sama5d2-flexcom: Add microchip,lan9691-flexcom
41693d50a7e8 dt-bindings: mfd: syscon: Allow syscon compatible for mediatek,mt7981-topmisc
75d41d817735 dt-bindings: mfd: qnap,ts433-mcu: Add qnap,ts133-mcu compatible
c7b860543f2d dt-bindings: mfd: nxp: Add NXP LPC32xx System Control Block
d165e31e20f7 dt-bindings: mfd: Add Bitmain BM1880 System Controller
bc0ece5d642e dt-bindings: mfd: atmel,hlcdc: Add sama7d65 compatible string
02f34a00c311 dt-bindings: mfd: syscon: Document the GPR syscon for the NXP S32 SoCs
cbb75857f755 Merge branches 'ib-mfd-clk-gpio-power-regulator-rtc-6.20', 'ib-mfd-regulator-6.20' and 'ib-mfd-rtc-6.20' into ibs-for-mfd-merged
4ed80af4e800 dt-bindings: mtd: partitions: Combine simple partition bindings
cd4daa0abfd5 dt-bindings: mtd: partitions: Convert brcm,trx to DT schema
7796aed329eb dt-bindings: mtd: fixed-partitions: Restrict undefined properties
2fee48751e05 dt-bindings: mtd: Ensure partition node properties are documented
cf39a935bc6f dt-bindings: mtd: partitions: Drop partitions.yaml
ab71d51e949d dt-bindings: mtd: partitions: Define "#{address,size}-cells" in specific schemas
35da943e3f8d dt-bindings: mtd: partitions: Allow "nvmem-layout" in generic partition nodes
f3e4abc0c3cc dt-bindings: mtd: partitions: Move "sercomm,scpart-id" to partition.yaml
3f3e27254a33 dt-bindings: mtd: fixed-partitions: Move "compression" to partition node
57f96b737a5a dt-bindings: mtd: brcm,brcmnand: Drop "brcm,brcmnand" compatible for iProc
f88b437888f0 Merge tag 'apple-soc-dt-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/dt
612c4f9fdb49 Merge tag 'lpc32xx-dt-for-6.20' of https://github.com/vzapolskiy/linux-lpc32xx into soc/dt
dc6ece796b86 Merge tag 'aspeed-6.20-devicetree-1' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
55e9e95b7d41 Merge tag 'nuvoton-arm64-6.20-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
ef282680695f arm64: dts: marvell: Add SoC specific compatibles to SafeXcel crypto
708378216fa0 Merge tag 'v6.20-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
9543fe54b8c1 Merge tag 'v6.20-rockchip-dts32-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
fd0c3637dece Merge tag 'juno-updates-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt
9ce8d18f3e3e dt-bindings: net: pcs: mediatek,sgmiisys: deprecate "mediatek,pnswap"
11fb43148bc5 dt-bindings: net: airoha,en8811h: deprecate "airoha,pnswap-rx" and "airoha,pnswap-tx"
6c8d104996f2 dt-bindings: net: airoha: npu: Add firmware-name property
c0e2edfaf4e0 dt-bindings: touchscreen: trivial-touch: Drop 'interrupts' requirement for old Ilitek
0b946423208a dt-bindings: input: i2c-hid: Introduce FocalTech FT8112
ee15a65fc46e ARM: dts: qcom: switch to RPMPD_* indices
c24b5ac17de5 arm64: dts: qcom: sm6115: Add CX_MEM/DBGC GPU regions
f4aa4553a6f4 arm64: dts: qcom: agatti: Add CX_MEM/DBGC GPU regions
02d1cd46bdf2 arm64: dts: qcom: sm8750: add ADSP fastrpc-compute-cb nodes
9d42975778ea arm64: dts: qcom: sm8750: add memory node for adsp fastrpc
230606847d7d arm64: dts: qcom: switch to RPMPD_* indices
a6b35c9c693b dt-bindings: thermal: r9a09g047-tsu: document RZ/T2H and RZ/N2H
0ec54c733653 dt-bindings: thermal: r9a09g047-tsu: Document RZ/V2N TSU
ac680fe53467 arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable SDIO interface
04ad85e91e0e Merge tag 'qcom-drivers-for-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers
47cf549e361f Merge tag 'samsung-drivers-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers
eacf9bb0ce61 arm64: dts: qcom: oneplus-enchilada: Specify i2c4 clock frequency
a027ea136749 arm64: dts: qcom: sm6350: Add clocks for aggre1 & aggre2 NoC
ef5b8a86c529 arm64: dts: qcom: agatti: enable FastRPC on the ADSP
719449cdbc04 dt-bindings: pinctrl: document polarfire soc mssio pin controller
da54d367c877 dt-bindings: pinctrl: qcom,glymur-tlmm: Document Mahua TLMM block
286e264e593d media: dt-bindings: add rockchip mipi csi-2 receiver
b1a1cf5123de dt-bindings: display: bridge: simple: document the Algoltek AG6311 DP-to-HDMI bridge
6994a15275b1 dt-bindings: vendor-prefixes: Add AlgolTek
ba3c253fb0d5 dt-bindings: interconnect: qcom-bwmon: Document Glymur BWMONs
6e74c2f165c9 dt-bindings: eeprom: at24: Add compatible for Puya P24C128F
32e5ee28ac99 dt-bindings: phy: renesas,usb2-phy: Document RZ/G3E SoC
c09e9126d56c dt-bindings: phy: renesas,usb2-phy: Document mux-states property
f40c647c0d90 dt-bindings: phy: renesas,usb2-phy: Document USB VBUS regulator
bcb394aa1cc7 media: dt-bindings: media: renesas,fcp: Allow three clocks for RZ/V2N SoC
5b33c502ea7b dt-bindings: net: micrel: Convert micrel-ksz90x1.txt to DT schema
982acc2e14ed dt-bindings: net: micrel: Convert to DT schema
63070365f58b dt-bindings: net: sparx5: do not require phys when RGMII is used
002e8d7735ee riscv: dts: spacemit: Disable ETH PHY sleep mode for OrangePi
4f9b26619be1 dt-bindings: display/msm: qcom, kaanapali-mdss: Add Kaanapali
0d9bc6aa9d8f dt-bindings: display/msm: dsi-controller-main: Add Kaanapali
4b6d795f96c4 dt-bindings: display/msm: dsi-phy-7nm: Add Kaanapali DSI PHY
e6b595f95f13 dt-bindings: display/msm: qcom, kaanapali-dpu: Add Kaanapali
3964d858d90f Merge tag 'v6.19-rc1' into msm-next
38a99a817ad7 dt-bindings: input: google,goldfish-events-keypad: Convert to DT schema
d9192729652c dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for MT7987
9c11b43017f0 dt-bindings: nvmem: mediatek: efuse: Add support for MT8196
de3c5fe53427 dt-bindings: thermal: mediatek: Add LVTS thermal controller support for MT8196
695720024214 dt-bindings: input: touchscreen: edt-ft5x06: Add FocalTech FT3518
aa63f9776715 ASoC: renesas: rz-ssi: Cleanups
7c7e2cdfd3c3 spi: xilinx: make IRQs optional
4da8a7ec04d2 dt-bindings: pwm: nxp,lpc32xx-pwm: Specify clocks property as mandatory
70824cca4e4a dt-bindings: mfd: Add rk801 binding
55e728580ead riscv: dts: spacemit: pinctrl: update register and IO power
d04eca503075 riscv: dts: spacemit: add K3 Pico-ITX board support
21e575fedb50 riscv: dts: spacemit: add initial support for K3 SoC
27ee007b967d dt-bindings: riscv: spacemit: add K3 and Pico-ITX board bindings
61b7fb5df7fb dt-bindings: interrupt-controller: add SpacemiT K3 IMSIC
d33981a1add4 dt-bindings: interrupt-controller: add SpacemiT K3 APLIC
ae5532959fcb dt-bindings: timer: add SpacemiT K3 CLINT
e2d340aa025b dt-bindings: riscv: add SpacemiT X100 CPU compatible
a585497ee055 riscv: dts: spacemit: k1: Add "b" ISA extension
06b93bbd2215 riscv: dts: spacemit: Enable USB3.0 on BananaPi-F3
340cd332be59 riscv: dts: spacemit: Add DWC3 USB 3.0 controller node for K1
a6c9e830b026 riscv: dts: spacemit: Add USB2 PHY node for K1
10935534c858 riscv: dts: spacemit: sdhci: add reset support
943a3e884eb2 riscv: dts: spacemit: add reset property
f8f9dd79d671 spi: dt-bindings: nxp,imx94-xspi: add nxp,imx952-xspi
5227871b94c8 dt-bindings: display: panel: Add compatible for Anbernic RG-DS
b978b018d7e1 ARM: dts: rockchip: rk3036: remove mshc aliases
ec280a19bf3e arm64: dts: rockchip: Do not enable hdmi_sound node on Pinebook Pro
442c21c2fe40 arm64: dts: rockchip: Fix imx258 variant on pinephone pro
6567ba439a82 arm/arm64: dts: st: Drop unused .dtsi
72898ec8d065 arm64: dts: st: Minor whitespace cleanup
5a25c60f7778 arm64: dts: st: Use hyphen in node names
bad0d9112b83 arm64: dts: st: add power-domain of dcmipp in stm32mp231.dtsi
ea9d4b95cbb3 arm64: dts: st: add power-domain of dcmipp in stm32mp251.dtsi
f2d478648a9c dt-bindings: media: st: dcmipp: add 'power-domains' property
e5435ff3b5aa arm64: dts: st: add power-domain of csi in stm32mp231.dtsi
81460acf00c3 arm64: dts: st: add power-domain of csi in stm32mp251.dtsi
dea5c1b19f24 dt-bindings: media: st: csi: add 'power-domains' property
15b8d5b148fb ARM: dts: stm32: add spi1 sleep state pinctrl on stm32mp157c-ev1
23bd1dd935f0 arm64: dts: st: add DDR channel to stm32mp257f-ev1 board
1073f0cfc9cf arm64: dts: st: add LPDDR channel to stm32mp257f-dk board
ec0680b409b7 arm64: dts: st: enable i2c analog-filter in stm32mp231.dtsi
19745354672a arm64: dts: st: enable i2c analog-filter in stm32mp251.dtsi
eb2ffaa4d91d arm64: dts: st: add power-domains in all i2c of stm32mp231.dtsi
b768c686e770 arm64: dts: st: add power-domains in all i2c of stm32mp251.dtsi
10ebfd2c3959 dt-bindings: i2c: st,stm32-i2c: add 'power-domains' property
a09b11b2817f arm64: dts: st: add power-domains in all spi of stm32mp231.dtsi
05b85f24fe27 arm64: dts: st: add power-domains in all spi of stm32mp251.dtsi
30b02e4ca2cb arm64: dts: st: Add boot-led for stm32mp2 ST boards
5e5deb2316bd ARM: dts: stm32: Add boot-led for stm32mp1 ST boards
2bf2ef567959 ARM: dts: stm32: Add boot-led for stm32 MCU ST boards
bd859993cc6d arm64: dts: st: Add green and orange LED for stm32mp2 ST boards
56b9f7fc9fde ARM: dts: stm32: Update LED node for stm32mp15xx-dkx board
0e2cd6d0cf14 ARM: dts: stm32: Add red LED for stm32mp157c-ed1 board
e1c842fb48ff ARM: dts: stm32: Add red LED for stm32mp135f-dk board
b025c0be8d16 ARM: dts: stm32: Add LED support for stm32h743i-eval
4b522a720f19 ARM: dts: stm32: Add LED support for stm32h743i-disco
39a3d28582ab ARM: dts: stm32: Update LED nodes for stm32 MCU boards
d549902a2f8f arm64: dts: amlogic: add the type-c controller on Radxa Zero 2
0e110c9846e6 arm64: dts: amlogic: meson-sm1-odroid: Eliminate Odroid HC4 power glitches during boot.
beaa0522e5f9 arm64: dts: amlogic: meson-s4-s905y4-khadas-vim1s: enable eMMC storage
6a2f6b9b373a riscv: dts: sophgo: sg2044: Add "b" ISA extension
add5431b0e85 riscv: dts: sophgo: fix the node order of SG2042 peripheral
ac0ba8a30821 riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi
7c0e3963484a dt-bindings: pinctrl: spacemit: add syscon property
5596787e9479 spi: dt-bindings: xilinx: make interrupts optional
78046c205134 arm64: qcom: dts: sm8750: add coresight nodes
9f7cc53066ad arm64: dts: qcom: talos: Drop opp-shared from QUP OPP table
ce61799a7f23 arm64: dts: qcom: x1-el2: Enable the APSS watchdog
cd6f4fa8d2eb arm64: dts: qcom: hamoa: Add the APSS watchdog
1e4b8c7e87d9 dt-bindings: watchdog: Document X1E80100 compatible
b3fd7b873f1c ARM: dts: qcom: msm8960: expressatt: Add Accelerometer
9e7e58ab94e1 ARM: dts: qcom: msm8960: expressatt: Add Magnetometer
c2df47ae20b9 ARM: dts: qcom: msm8960: expressatt: Add NFC
35bce974b172 ARM: dts: qcom: msm8960: expressatt: Add Light/Proximity Sensor
2e5966453c77 ARM: dts: qcom: msm8960: Add GSBI2 & GSBI7
fd72dcfface9 arm64: dts: qcom: sdm632-fairphone-fp3: Enable CCI and add EEPROM
a986521752b2 arm64: dts: qcom: sdm632-fairphone-fp3: Add camera fixed regulators
26b9815fb37d arm64: dts: qcom: msm8953: Add CCI nodes
d39c16e042a1 arm64: dts: qcom: msm8953: Re-sort tlmm pinctrl states
dab43170e734 dt-bindings: net: dsa: lantiq,gswip: add MaxLinear R(G)MII slew rate
05ab1b20da91 ARM: dts: qcom: msm8974: Start using rpmpd for power domains
9be5f27bd8a8 ARM: dts: qcom: msm8974: Sort header includes alphabetically
018c6554c99c dt-bindings: regulator: mark regulator-suspend-microvolt as deprecated
9f9686624b29 arm64: dts: mediatek: mt8192: Rename mt8192-afe-pcm to audio-controller
f98ac8fd4a35 dt-bindings: arm: mediatek: audsys: Support mt8192-audsys variant
7a53eaaf914c dt-bindings: arm: qcom: Add Coresight Interconnect TNOC
cbcfbcb9d555 dt-bindings: mtd: st,spi-fsm: convert to DT schema
c954d2f5b479 dt-bindings: mtd: microchip,mchp23k256: convert to DT schema
9c50822512d8 dt-bindings: mtd: nvidia,tegra20-nand: convert to DT schema
e7bb20485fd6 riscv: dts: anlogic: dr1v90: Add "b" ISA extension
7b7fabb5ece3 Merge 6.19-rc6 usb-next
a55b4820bea8 ARM: dts: allwinner: Replace status "failed" with "fail"
9b3f945edd5b Merge tag 'mediatek-drm-next-20260117' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next
e2732701ee10 Merge tag 'samsung-pinctrl-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel
318f21421b67 Merge tag 'renesas-pinctrl-for-v6.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
5d4b95cb22f8 dt-bindings: mbox: add pic64gx mailbox compatibility to mpfs mailbox
e9535087ef08 dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings for Kaanapali
7b834b22a4f3 dt-bindings: mailbox: mediatek,mt8196-vcp-mbox: add mtk vcp-mbox document
4abfb76fac38 dt-bindings: display/msm/gpu: Straighten out reg-names on A619L/610/702
7b9953464554 dt-bindings: watchdog: qcom-wdt: Document Glymur watchdog
f3e32711d1f9 dt-bindings: watchdog: Convert mpc8xxx-wdt to YAML
4e1009c422e4 dt-bindings: watchdog: samsung-wdt: Split if:then: and constrain more
76ef81f60554 dt-bindings: watchdog: samsung-wdt: Drop S3C2410
f21fec63b372 dt-bindings: watchdog: samsung-wdt: Define cluster constraints top-level
947ec2a7a061 arm64: dts: freescale: imx95: Add support for i.MX95 15x15 FRDM board
1e2f6fe09a0a dt-bindings: arm: fsl: Add compatible for i.MX95 15x15 FRDM board
da896e6aeb6e arm64: dts: imx91-11x11-frdm: fix CAN transceiver gpio
9a799b6dcf66 arm64: dts: imx93-11x11-frdm: enable additional devices
c320d1ee2c31 ARM: dts: imx: e60k02: add tps65185
f23d7747e2fc ARM: dts: imx50-kobo-aura: add epd pmic description
a5187a07278f ARM: dts: imx: tolino-shine2: add tps65185
def2bad12ad5 arm64: dts: imx93-11x11-frdm: Add MQS audio support
326f80d72a57 arm64: dts: imx952-evk: Add nxp,ctrl-ids for scmi misc
708a298bdf32 arm64: dts: imx952-evk: Add flexcan support
76ad6957eac5 arm64: dts: imx952-evk: Enable TPM[3,6]
99d8f14ea5bd arm64: dts: imx952-evk: Enable wdog3
53d10193fd4a arm64: dts: imx952-evk: Enable USB[1,2]
d8663a7f9769 arm64: dts: imx952-evk: Enable SPI7
34e233786a5f arm64: dts: imx952-evk: Enable UART5
92bb376249bb arm64: dts: imx952-evk: Enable I2C[2,3,4,6,7] bus
dd58a0f13f18 arm64: dts: imx952-evk: Change the usdhc1_200mhz drive strength to DSE4
f32e871ca957 arm64: dts: imx952: Add idle-states node
4e976b781b68 arm64: dts: imx8mn: Add ifm VHIP4 EvalBoard v1 and v2
501d4b54ac14 arm64: dts: imx8mn: Add SNVS LPGPR
67e6d92ddfdd arm64: dts: imx8mq-librem5: Don't set mic-cfg for wm8962
083f756b87a3 arm64: dts: imx8mq-librem5: Set cap-power-off-card for usdhc2
3dd550990418 arm64: dts: imx8mq-librem5: Limit uSDHC2 frequency to 50MHz
814565e7b271 arm64: dts: imx8mq-librem5: Enable SNVS RTC
6118d1871535 arm64: dts: imx8mq-librem5: Set vibrator's PWM frequency to 20kHz
6c8d0e9696b0 arm64: dts: imx8mq-librem5: Enable I2C recovery
df87f60ac610 dt-bindings: net: pcs: renesas,rzn1-miic: Add phy_link property
a007152b42f7 dt-bindings: mailbox: qcom: Add IPCC support for Kaanapali and Glymur Platforms
f17db6ab33fe arm64: dts: exynos: gs101: add cmu_dpu and sysreg_dpu dt nodes
af824b164001 Merge branch 'for-v6.20/dt-bindings-clk' into next/dt64
7f5d058c91d5 dt-bindings: samsung: exynos-sysreg: add gs101 dpu compatible
03e693827f91 Merge branch 'for-v6.20/dt-bindings-clk' into next/clk
914545f99d20 dt-bindings: clock: google,gs101-clock: Add DPU clock management unit
989b6eeea3ac dt-bindings: clock: google,gs101-clock: fix alphanumeric ordering
c95c9060cf20 dt-bindings: arm: fsl: Document ifm VHIP4 EvalBoard v1 and v2
d11258fd262f dt-bindings: vendor-prefixes: Document ifm electronic gmbh
9af150b1d5ac arm64: dts: imx95: Use GPU_CGC as core clock for GPU
9ca53be594b1 ARM: dts: imx: move nand related property under nand@0
515b1852fc1d ARM: dts: imx6sx: update gpmi #size-cells to 0
bfc8a89eae3d ARM: dts: imx6qdl: add '#address-cells' and '#size-cells' for gpmi-nand
f1f26baa4790 arm64: dts: imx91: Add thermal-sensor and thermal-zone support
ec7bfa4a6cc6 dt-bindings: display: tegra: document Tegra30 VI and VIP
d4fb3d68c52e dt-bindings: display: tegra: document Tegra132 MIPI calibration device
36cd72893c12 ARM: tegra: Adjust DSI nodes for Tegra20/Tegra30
2822dc9ca7f1 arm64: tegra: smaug: Add usb-role-switch support
c8a97be57fe4 arm64: tegra: smaug: Complete and enable tegra-udc node
b48949517e5f arm64: tegra: smaug: Enable DisplayPort via USB-C port
4b86a80e2733 dt-bindings: phy: mediatek,hdmi-phy: Document extra clocks for MT8195
ba7055ce7670 dt-bindings: phy: mediatek,hdmi-phy: Add support for MT8188 SoC
2c497b05d60f arm64: tegra: Correct CPU compatibles on Tegra264
3fd0fa38597d arm64: tegra: Drop unneeded status=okay on Tegra264
94fddcbb5edb arm64: tegra: Drop unneeded status=okay on Tegra234
8bc40459d4b1 arm64: tegra: Drop unneeded status=okay on Tegra194
a751ddaf7368 arm64: tegra: Drop unneeded status=okay on Tegra186
7e68f45e9d71 arm64: tegra: Add nodes for CMDQV
2dcabc6b8618 arm64: tegra: Add DBB clock to EMC on Tegra264
9c2cb35536e3 dt-bindings: phy: mediatek,hdmi-phy: Fix clock output names for MT8195
b99d0eb7564e arm64: dts: broadcom: bcm4906-netgear-r8000p: Drop unnecessary "ranges" in partition node
5e7a803f25cb arm64: dts: broadcom: northstar2: Drop "arm,cci-400-pmu" fallback compatible
495f35c2c98f arm64: dts: broadcom: northstar2: Drop QSPI "clock-names"
7f3ad038566f arm64: dts: broadcom: northstar2: Drop unused and undocumented "brcm,pcie-ob-oarr-size" properties
4db81b905c2b arm64: dts: broadcom: northstar2: Rework clock nodes
01cfa0ec34b9 arm64: dts: broadcom: ns2-svk: Use non-deprecated at25 properties
fcd62ea160ad arm64: dts: broadcom: Use preferred node names
d9fec9189e6b arm64: dts: broadcom: stingray: Move raid nodes out of bus
ab4ed1dc0d04 arm64: dts: broadcom: stingray: Fix 'simple-bus' node names
cc9550ca574b arm64: dts: broadcom: stingray: Rework clock nodes
708a5b2c0fe4 arm64: dts: broadcom: Remove unused and undocumented nodes
862b765f1108 dt-bindings: can: renesas,rcar-canfd: Document RZ/T2H and RZ/N2H SoCs
4ec77a68120b dt-bindings: can: renesas,rcar-canfd: Document RZ/V2H(P) and RZ/V2N SoCs
14ae60e3097d dt-bindings: can: renesas,rcar-canfd: Specify reset-names
e7c67c8a4413 dt-bindings: can: renesas,rcar-canfd: Document renesas,fd-only property
6d45bea6e3af dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings for Kaanapali
cecc020569a4 dt-bindings: mtd: nvidia,tegra20-nand: convert to DT schema
be3f0a7db3f8 dt-bindings: dma: Update ADMA bindings for tegra264
7f2243e51e32 openrisc: dts: Add de0 nano multicore config and devicetree
013156b1bde9 openrisc: dts: Split simple smp dts to dts and dtsi
6fe2a6550f5f openrisc: dts: Add de0 nano config and devicetree
67fb31a7cd6b arm64: dts: qcom: lemans: enable static TPDM
ed6dd716b980 arm64: dts: qcom: kodiak: Add memory region for audiopd
c5bfde36ba99 arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: add HDMI nodes
580b3f4a68b5 arm64: dts: qcom: x1e: bus is 40-bits (fix 64GB models)
2ea2ad35b316 arm64: dts: rockchip: Add the Video-Demo overlay for Lion Haikou
c06349a10fff arm64: dts: rockchip: Enable pwm1 on rk3368-lion-haikou
06befd3e2967 arm64: dts: rockchip: Enable HDMI output on RK3368-Lion-Haikou
e47d90e6728a arm64: dts: rockchip: Add HDMI node to RK3368
aeff6a608b6c arm64: dts: rockchip: Use phandle for i2c_lvds_blc on rk3368-lion haikou
a656170a31fc arm64: dts: rockchip: Fix SD card support for RK3576 Nanopi R76s
1de10acec651 arm64: dts: rockchip: Fix SD card support for RK3576 EVB1
d7416ad948d1 dt-bindings: serial: google,goldfish-tty: Convert to DT schema
f84445bb1270 dt-bindings: serial: sh-sci: Fold single-entry compatibles into enum
90acfa9f6742 dt-bindings: serial: renesas,rsci: Document RZ/V2H(P) and RZ/V2N SoCs
630e7963f59d dt-bindings: PCI: qcom: Document the Glymur PCIe Controller
79e31b907d76 dt-bindings: misc: google,android-pipe: Convert to DT schema
b577c2abb1d4 dt-bindings: usb: Add binding for WCH CH334/CH335 hub controller
455fa431ed46 dt-bindings: iommu: Add NVIDIA Tegra CMDQV support
b137b22a98b3 dt-bindings: memory: tegra: Document DBB clock for Tegra264
d8b05403d10c dt-bindings: tegra: pmc: Update aotag as an optional aperture
48296655ff9f arm64: dts: ti: k3-am67a-kontron-sa67-base: Fix SD card regulator
29eaf3445321 arm64: dts: ti: k3-am67a-kontron-sa67-base: Fix CMA node
74379f1a5e5f arm64: dts: ti: k3-am62p-j722s-common-main: Add HSM M4F node
c5512f936aff arm64: dts: ti: k3-{j784s4-j742s2/j721s2}-mcu-wakeup: Add HSM M4F node
974e346cc223 arm64: dts: renesas: rzt2h-rzn2h-evk: Reorder ADC nodes
141816132f7b dt-bindings: clock: mpfs-clkcfg: Add pic64gx compatibility
023006616a86 dt-bindings: clock: mpfs-ccc: Add pic64gx compatibility
2cf21f13e040 dt-bindings: net: airoha: npu: Add BA memory region
4c961b745f1f dt-bindings: net: adi,adin: document LP Termination property
1da46de73792 Merge tag 'phy_common_properties' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
b5b08104dda9 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
74d0ef2610f3 dt-bindings: net: wireless: ath11k: Combine two if:then: clauses
f10bf8779ec6 Merge tag 'drm-misc-next-2026-01-15' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
b73740fc9de1 dt-bindings: display/msm/rgmu: Document A612 RGMU
dca9618a1d32 dt-bindings: display/msm: gpu: Document A612 GPU
0d6547833df6 dt-bindings: display/msm: gpu: Simplify conditional schema logic
81ce5f5864eb arm64: dts: qcom: lemans; Add EL2 overlay
8681a97e8eb3 arm64: dts: qcom: sm8150: add uart13
201bf4da11e6 arm64: dts: qcom: sdm845-db845c: specify power for WiFi CH1
38cc99dc1f1c arm64: dts: qcom: sdm845-db845c: drop CS from SPIO0
c58414174a89 arm64: dts: qcom: qrb4210-rb2: Fix UART3 wakeup IRQ storm
7a952883ade4 ASoC: dt-bindings: mt8192-afe-pcm: Fix clocks and clock-names
4950c913b7d5 dt-bindings: gpio-mmio: Correct opencores GPIO
b682394899eb Merge tag 'ib-mfd-clk-gpio-power-regulator-rtc-v6.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into gpio/for-next
14a86e737e7d arm64: dts: mediatek: mt7988a: Fix PCI-Express T-PHY node address
43c9e46a90ba arm64: dts: meson-s4-s905y4-khadas-vim1s: add initial device tree
047fbc9e905a arm64: dts: meson-s4-aq222: update compatible string with s805x2
562fa59f8326 dt-bindings: arm: amlogic: introduce specific compatibles for S4 family
c2ffdb01e074 arm64: dts: mediatek: mt8186-evb: Add vproc fixed regulator
fdda1b0b1ba0 ARM: dts: r9a06g032: Add support for GPIO interrupts
6c5ab649ab2f ARM: dts: r9a06g032: Add GPIO controllers
8edb33f4827a arm64: dts: renesas: rzg3e-smarc-som: Enable I3C support
4409a3e81288 dt-bindings: soc: renesas: Document RZ/N1 GPIO Interrupt Multiplexer
6880f32f6442 arm64: dts: mediatek: mt7981b-openwrt-one: Add address/size cells to eth
515f976d0ce9 arm64: dts: amlogic: Enable the npu node on Radxa Zero 2
d3108d4cb1dc arm64: dts: amlogic: g12: assign the MMC A signal clock
6c24c785f2f3 arm64: dts: amlogic: g12: assign the MMC B and C signal clocks
d70bd7d65c47 arm64: dts: amlogic: gx: assign the MMC signal clocks
2f5f8f725290 arm64: dts: amlogic: axg: assign the MMC signal clocks
389ec29c282d arm64: dts: amlogic: a1: align the mmc clock setup
5561343a9359 arm64: dts: amlogic: c3: assign the MMC signal clocks
e7927bfb9594 riscv: dts: sophgo: enable hardware clock (RTC) on the Milk-V Pioneer
b1e14936e730 media: dt-bindings: ti,omap3isp: Convert to DT schema
ea20b4c79f4c media: dt-bindings: i2c: toshiba,et8ek8: Convert to DT schema
fc53e67381e3 dt-bindings: media: ov5647: Allow props from video-interface-devices
855f0e943b6a dt-bindings: media: ov5647: Add optional regulators
2995b9b04133 arm64: dts: qcom: sm6125-ginkgo: Fix missing msm-id subtype
2d1968d218f6 sound: codecs: tlv320adcx140: assorted patches
391d32897d0f ASoC: codecs: aw88261: add dvdd-supply property
d27446108ca4 arm64: dts: ti: k3-j784s4-j742s2-main-common.dtsi: Refactor watchdog instances for j784s4
bcf34bb0f9a7 arm64: dts: ti: k3-j784s4-main.dtsi: Move c71_3 node to appropriate order
f9747b110fc4 arm64: dts: ti: k3-am69-aquila-clover: Change main_spi2 CS0 to GPIO mode
da6e384db047 arm64: dts: ti: k3-am69-aquila: Change main_spi0/2 CS to GPIO mode
b327f12239ae dt-bindings: phy: google: Add Google Tensor G5 USB PHY
0bf24893ebdc dt-bindings: pinctrl: spacemit: k3: fix drive-strength doc
d14b8962ef3b dt-bindings: sound: google,goldfish-audio: Convert to DT schema
40732ea3b5cd ASoC: dt-bindings: document dvdd-supply property for awinic,aw88261
2551501b8eb4 ASoC: dt-bindings: add avdd and iovdd supply
8793bb577f2f ASoC: dt-bindings: clarify areg-supply documentation
184e81f0216e Merge tag 'phy_common_properties' into next
ee419f4a90cc dt-bindings: phy-common-props: RX and TX lane polarity inversion
9d0ca379b4d7 dt-bindings: phy-common-props: ensure protocol-names are unique
387a58af46f8 dt-bindings: phy-common-props: create a reusable "protocol-names" definition
ebcd7b8610c6 dt-bindings: phy: rename transmit-amplitude.yaml to phy-common-props.yaml
41ccdde910d4 arm64: dts: amlogic: s4: fix mmc clock assignment
d4460e04fa48 arm64: dts: amlogic: s4: assign mmc b clock to 24MHz
1cfe09dac9a0 arm64: dts: amlogic: drop useless assigned-clock-parents
b270a7272aa7 dt-bindings: ata: sata: Document the graph port
7d3c2e8aaae2 dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: Add QMP UFS PHY compatible
4facd5bf21a3 dt-bindings: phy: qcom,m31-eusb2-phy: Document M31 eUSB2 PHY for Kaanapali
dfc1771a6f91 dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Kaanapali QMP PHY
4d783b51113f dt-bindings: phy: Add PHY_TYPE_XAUI definition
fa414004e411 arm64: dts: mediatek: mt8183-kukui: Clean up IT6505 regulator supply
803da859257f dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the Milos QMP UFS PHY
cefe660cbbf3 arm64: dts: mediatek: mt7986a: Change compatible for SafeXcel crypto
7a3f7afcef9e arm64: dts: mediatek: mt8173-evb: Add interrupts to DA9211 regulator
206b6aecc2e6 arm64: dts: mediatek: mt6795-xperia-m5: Rename PMIC leds node
c36276a3b23d arm64: dts: mediatek: mt6795: Fix issues in SCPSYS node
0f3176276ef7 arm64: dts: mediatek: mt6331: Fix VCAM IO regulator name
48f536cf5421 dt-bindings: i2c: i2c-mt65xx: Add compatible for MT8189 SoC
38f6981ab699 Merge branch '20260105-kvmrprocv10-v10-0-022e96815380@oss.qualcomm.com' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into rproc-next
7b66bb79b113 Merge branch '20260105-kvmrprocv10-v10-0-022e96815380@oss.qualcomm.com' into drivers-for-6.20
6266a22d68f6 dt-bindings: net: dp83822: Deprecate ti,fiber-mode
9e1e99cc0fcc dt-bindings: net: Introduce the ethernet-connector description
d8dbb43cdd3a dt-bindings: riscv: extensions: Drop unnecessary select schema
4b9e5aa4a542 dt-bindings: riscv: Add Sha and its comprised extensions
fe7098988625 dt-bindings: riscv: Add Ssccptr, Sscounterenw, Sstvala, Sstvecd, Ssu64xl
8722a58217dd dt-bindings: riscv: Add descriptions for Za64rs, Ziccamoa, Ziccif, and Zicclsm
b3ec41ca5d55 dt-bindings: riscv: Add B ISA extension description
0957ff98c67a dt-bindings: riscv: update ratified version of h, svinval, svnapot, svpbmt
65d424e95f5a dt-bindings: remoteproc: qcom,pas: Add iommus property
85cfc581b357 arm64: dts: qcom: qcs8300: Add GPU cooling
d9deaa855e4b dt-bindings: remoteproc: fsl,imx-rproc: Add support for i.MX95
d9a30a00d06b riscv: dts: allwinner: d1: Add RGB LEDs to boards
4905d5900f35 riscv: dts: allwinner: d1: Add LED controller node
a12da48d8f20 regulator: dt-bindings: rpi-panel: Mark 7" Raspberry Pi as GPIO controller
85ffea24a11c arm64: dts: allwinner: a100: Add LED controller node
6c8cc1716e52 mtd: spinand: Octal DTR support
49926bd040f4 dt-bindings: gpu: mali-valhall-csf: Add shader-present nvmem cell
8786767941ac arm64: dts: qcom: sa8775p: Add reg and clocks for QoS configuration
d2fe66895e41 dt-bindings: PCI: qcom,sa8255p-pcie-ep: Document firmware managed PCIe endpoint
19b8532647c2 Merge branch 'icc-mtk' into icc-next
1460edbbf157 dt-bindings: interconnect: qcom,qcs615-rpmh: Drop IPA interconnects
59ff855455ce Axiado AX3000 SoC SPI DB controller driver
c6443a18e84c arm64: dts: rockchip: Add Radxa CM3J on RPi CM4 IO Board
0032df604fa6 arm64: dts: rockchip: Add Radxa CM3J
9125f8bb75bc dt-bindings: arm: rockchip: Add Radxa CM3J on RPi CM4 IO Board
1ee79eb39a92 arm64: dts: rockchip: Make eeprom read-only for Radxa ROCK 3C/5A/5C
12369df303aa arm64: dts: rockchip: Add TS133 variant of the QNAP NAS series
0ebe988da929 dt-bindings: arm: rockchip: add TS133 to RK356x-based QNAP NAS devices
f05a74784e3e arm64: dts: rockchip: Move copy-key to TSx33 board files
65cc1beff5b0 arm64: dts: rockchip: Fix the common combophy + SATA on QNAP TSx33 devices
5876ba248e99 arm64: dts: rockchip: Move SoC include to individual QNAP TSx33 boards
5eacb4f2bc3f dt-bindings: PCI: loongson: Document msi-parent property
018ef4ed75bc regulator: dt-bindings: mediatek,mt6331: Add missing ldo-vio28 vreg
8dc33138e8ce dt-bindings: leds: bd72720: Add BD72720
6f2f719011e5 dt-bindings: mfd: ROHM BD72720
e501fa17eb6b dt-bindings: battery: Voltage drop properties
d0729ca80a5a dt-bindings: battery: Add trickle-charge upper limit
1ac445386209 dt-bindings: battery: Clarify trickle-charge
ea07ebf0f94f dt-bindings: regulator: ROHM BD72720
a639de753758 ASoC: Update rtq9128 document and source file
7e5fb31ab397 regulator: Add TPS65185
c03a7bad76e6 dt-bindings: media: Add qcom,sm6150-camss
abbdbd1e88b3 dt-bindings: media: Correct camss supply description
a51c86a499bc dt-bindings: media: qcom,qcs8300-camss: Add missing power supplies
2ff42615a39e dt-bindings: media: ti: vpe: Add support for Video Input Port
063740f57f5b media: dt-bindings: adi,adv7180: add VPP and CSI register maps
3bc58308e013 dt-bindings: display: panel-simple: Allow "data-mapping" for "yes-optoelectronics,ytc700tlag-05-201c"
55197c2320e8 dt-bindings: display: simple: Add Innolux G150XGE-L05 panel
e89cec70ef26 arm64: dts: amlogic: move CPU OPP table and clock assignment to SoC.dtsi
0c2c59fa78c8 Merge patch series "arm64: dts: apple: Add integrated USB Type-C ports"
4bd1c26ba442 arm64: dts: apple: t60xx: Add nodes for integrated USB Type-C ports
a689f58bb9ca arm64: dts: apple: t8112: Add nodes for integrated USB Type-C ports
74042f340f78 arm64: dts: apple: t8103: Add nodes for integrated USB Type-C ports
dc70ad22e366 arm64: dts: apple: t8103: Add ps_pmp dependency to ps_gfx
0d2a0dbe95c5 arm64: dts: apple: t8103: Mark ATC USB AON domains as always-on
774daf7ba17a arm64: dts: apple: t8112-j473: Keep the HDMI port powered on
44f172d1b273 arm64: dts: apple: Add chassis-type property for Apple iMacs
5da589e80ed1 arm64: dts: apple: Add chassis-type property for Mac Pro
82b1e893e129 arm64: dts: apple: Add chassis-type property for Apple desktop devices
cd25b3aae2dc arm64: dts: apple: Add chassis-type property for all Macbooks
f3560e52d9a5 ASoC: dt-bindings: rtq9128: Add rtq9154 backward compatible
891c28cf3f3d arm64: dts: mediatek: mt6795-xperia-m5: Add UHS pins for MMC1 and 2
7ff21e13c458 arm64: dts: mediatek: mt8192-asurada: Remove unused clock-stretch-ns
504f1e61dc1c arm64: dts: mediatek: mt8173-elm: Remove regulators from thermal node
2da6bb860185 arm64: dts: mediatek: mt8173-elm: Fix dsi0 ports warning
134783da2fc5 arm64: dts: mediatek: mt8173-elm: Fix bluetooth node name and reorder
2f5a04231651 arm64: dts: mediatek: mt8183-pumpkin: Fix pinmux node names
d923b4f4f8a8 arm64: dts: mediatek: mt8183-jacuzzi-pico6: Fix typo in pinmux node
ec3f36045cf2 arm64: dts: mediatek: mt7981b-openwrt-one: Remove useless cells from flash@0
4b1cd354d614 arm64: dts: mediatek: mt8183-evb: Fix dtbs_check warnings
999cdbf9bc2a arm64: dts: mediatek: mt8173: Fix pinctrl node names and cleanup
39a89aef4b4f arm64: dts: mediatek: mt8188-geralt: drop firmware-name from first SCP core
cf3c5bf2fb8b regulator: dt-bindings: Document TI TPS65185
358401e15811 regulator: core: allow regulator_register() with
e7e731d90b00 spi: dt-bindings: nxp,lpc3220-spi: Add DMA specific properties
0efd42e88787 ASoC: dt-bindings: Convert realtek,rt5651 to DT schema
21889177c7e9 arm64: dts: renesas: Use lowercase hex
acc2d46ba016 Merge tag 'v6.19-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next
cd05027f3228 arm64: dts: renesas: Use hyphens in node names
7add41540117 arm/arm64: dts: renesas: Drop unused .dtsi
005f9e3644ac Merge 6.19-rc5 into char-misc-next
696aea94d3fa dt-bindings: media: i2c: Add os05b10 sensor
fa6b02de574e dt-bindings: media: i2c: Add Samsung S5K3M5 image sensor
1a6970d37718 dt-bindings: media: i2c: Add Samsung S5KJN1 image sensor
396be428d48f arm64: dts: cix: Add OrangePi 6 Plus board support
388222cbc6e4 dt-bindings: arm: cix: add OrangePi 6 Plus board
8a1b971219d9 dt-bindings: iio: adc: Add AD4134
c616ef5fc880 dt-bindings: iio: proximity: Add RF Digital RFD77402 ToF sensor
1b072533efef dt-bindings: pinctrl: samsung: Add exynos9610-wakeup-eint node
d556b2a250a8 dt-bindings: pinctrl: samsung: Add exynos9610-pinctrl compatible
fee6f4f2ebd5 dt-bindings: soc: fsl: qe: Add an interrupt controller for QUICC Engine Ports
315d0a210ccd arm: dts: lpc32xx: add interrupts property to Motor Control PWM
2d4703cc39d8 arm: dts: lpc32xx: add clocks property to Motor Control PWM device tree node
59acbfb08c7a dt-bindings: net: rockchip-dwmac: Allow "dma-coherent"
e7978fa23e73 arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576
3d9752b5ffdb arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588
713151648ba2 arm64: dts: qcom: hamoa-iot-evk: Enable TPM (ST33) on SPI11
752008e5ef84 arm64: dts: rockchip: Add rk3588s-orangepi-cm5-base device tree
0d591d49d504 dt-bindings: arm: rockchip: Add Orange Pi CM5 Base
823ad7ab4830 arm64: dts: rockchip: Enable second HDMI output on CM3588
9ed66b32c4b9 arm64: dts: rockchip: Add HDMI to Gameforce Ace
afeffdef654c dt-bindings: display: rockchip: Add no-hpd for dw-hdmi-qp controller
374a2610a844 arm64: dts: qcom: talos: Add PMU support
1bb6f872a948 arm64: dts: qcom: talos: switch to interrupt-cells 4 to add PPI partitions
1495b12dd18b arm64: dts: qcom: ipq9574: Complete USB DWC3 wrapper interrupts
60db44f9ab1c arm64: dts: qcom: ipq5018: Correct USB DWC3 wrapper interrupts
3a94f2e147d6 arm64: dts: qcom: monaco: Add CTCU and ETR nodes
61978b63d7cb arm64: dts: qcom: Add PCIe3 and PCIe5 regulators for HAMAO-IOT-EVK board
2f0230be089a arm64: dts: qcom: Add PCIe3 and PCIe5 support for HAMOA-IOT-SOM platform
d7af35972d49 arm64: dts: qcom: hamoa: Move PHY, PERST, and Wake GPIOs to PCIe port nodes and add port Nodes for all PCIe ports
e917dcc44a65 arm64: dts: qcom: sdm630: Add LPASS LPI TLMM
a9576e1975bb arm64: dts: qcom: kodiak: Add missing clock votes for lpass_tlmm
2ce6dac0afda dt-bindings: gpu: img: Add AM62P SoC specific compatible
843442f35eac spi: dt-bindings: axiado,ax3000-spi: Add binding for Axiado SPI DB controller
ce1545686ac4 arm64: dts: renesas: rzt2h-n2h-evk-common: Use GPIO for SD0 write protect
b38c2837a4c1 arm64: dts: renesas: r9a09g057: Add CANFD node
71b05c0fbb1e arm64: dts: renesas: r9a09g056: Add CANFD node
f2826e02dec3 arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Enable CANFD
c3a5ef1971c9 arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Enable CANFD
57507f1ab100 arm64: dts: renesas: r9a09g087: Add CANFD node
2dd586ebf433 arm64: dts: renesas: r9a09g077: Add CANFD node
24a639a75379 Merge tag 'renesas-r9a09g077-dt-binding-defs-tag6' into renesas-dts-for-v6.20
70eb29ba7308 dt-bindings: pinctrl: renesas,r9a09g077-pinctrl: Document GPIO IRQ
7c1e6cdb540c arm64: dts: renesas: r9a09g057: Add RSCI nodes
12bab8609e25 arm64: dts: renesas: r9a09g056: Add RSCI nodes
55d259b32fe2 arm64: dts: renesas: r9a09g087m44-rzn2h-evk: Add GPIO keys
330035930524 arm64: dts: renesas: r9a09g077m44-rzt2h-evk: Add GPIO keys
0274e6aa8e7b arm64: dts: renesas: r9a09g087: Add GPIO IRQ support
cf741d2e8a0e arm64: dts: renesas: r9a09g077: Add GPIO IRQ support
7ec7d3107ad1 arm64: dts: renesas: r9a09g087: Add TSU and thermal zones support
b78ee53481d3 arm64: dts: renesas: r9a09g077: Add TSU and thermal zones support
fb523ea0cebf arm64: dts: renesas: r9a09g087: Add OPP table
ccc606135698 arm64: dts: renesas: r9a09g077: Add OPP table
3d3158f552ec Merge tag 'renesas-r9a09g077-dt-binding-defs-tag6' into renesas-clk-for-v6.20
e61a166730f3 dt-bindings: pinctrl: intel: keembay: fix typo
c52b56ea765a ARM: dts: lpc32xx: Add missing properties to I2S device tree nodes
590f92e52b6e ARM: dts: lpc32xx: Declare the second AHB master support on PL080 DMA controller
0c473c8d6f5d ARM: dts: lpc32xx: Add missing DMA properties
f9aa3eb38496 ARM: dts: lpc32xx: Use syscon for system control block
c379c6892d86 ARM: dts: lpc32xx: describe FLASH_INT of SLC NAND controller
75d9c48a2ba6 ARM: dts: lpc32xx: change NAND controllers node names
d9f691453182 ARM: dts: lpc32xx: Update spi clock properties
3abca592bfe1 ARM: dts: Add support for pcb8385
5f8db3730de7 dt-bindings: arm: at91: add lan966 pcb8385 board
958a9657c7d0 dt-bindings: soc: spacemit: k3: add clock support
a45c091e89a1 dt-bindings: net: dsa: microchip: Make pinctrl 'reset' optional
4e1af11215ee arm64: dts: qcom: qrb2210-rb1: Add overlay for vision mezzanine
e4a1630d3b05 arm64: dts: qcom: qrb2210-rb1: Add PM8008 node
41cb6b05e684 arm64: dts: qcom: qcm2290: Add pin configuration for mclks
f685535f806c arm64: dts: apple: s8001: Add DWI backlight for J98a, J99a
75911f2b072f dt-bindings: display: rockchip,vop: Add compatible for rk3506
7fa529d7f444 dt-bindings: display: rockchip,dw-mipi-dsi: Add compatible for rk3506
6122699e76e7 arm64: dts: broadcom: bcm2712: Add watchdog DT node
914987690831 arm64: dts: broadcom: bcm2712: Enable RNG
0f70c810948d ARM: dts: broadcom: bcm2711: Fix 'simple-bus' node names
726a4988206c ARM: dts: stm32: reorder nodes for stm32429i-eval
85b19a129954 arm64: dts: mediatek: add device tree for Tungsten 700 board
1b97285c0e24 arm64: dts: mediatek: add device tree for Tungsten 510 board
3ed0b28d2918 arm64: dts: mediatek: mt8188: switch mmc nodes to interrupts-extended
59a95bd89011 dt-bindings: arm: mediatek: Add Ezurio Tungsten entries
7e1cf0227843 dt-bindings: vendor-prefixes: Add Ezurio LLC
3e91aecad546 arm64: dts: mediatek: mt8395-genio-common: Add HDMI sound output support
62d02baa6a31 arm64: dts: mediatek: mt8395-genio-common: Enable HDMI output
37eb6fa3a0ad arm64: dts: mediatek: mt8395-radxa-nio-12l: Add HDMI sound output support
0dd940a9c0eb arm64: dts: mediatek: mt8395-radxa-nio-12l: Enable HDMI output
7be855ab6141 arm64: dts: mediatek: mt8390-genio-common: Add HDMI sound output support
684a136b3284 arm64: dts: mediatek: mt8390-genio-common: Enable HDMI output
5ceb3efd9bd7 arm64: dts: mediatek: mt8188: Add DPI1, HDMI, HDMI PHY/DDC nodes
9acd664ae667 arm64: dts: mediatek: mt8195: Add DPI1, HDMI, HDMI PHY/DDC nodes
2f438874517f arm64: dts: mediatek: mt7981b-openwrt-one: Enable wifi
79d0264a56fd arm64: dts: mediatek: mt7981b: Add wifi memory region
813bc92a5a7e arm64: dts: mediatek: mt7981b: Disable wifi by default
b5f804e52428 arm64: dts: mediatek: mt7981b-openwrt-one: Enable Ethernet
4a64fe860e70 arm64: dts: mediatek: mt7981b: Add Ethernet and WiFi offload support
c5b6d809e976 arm64: dts: mediatek: mt7981b-openwrt-one: Enable PCIe and USB
ce656f4eb178 arm64: dts: mediatek: mt7981b: Add PCIe and USB support
c7b4ce20856b arm64: dts: mediatek: mt8183: Add missing endpoint IDs to display graph
9f78fe613d0a dt-bindings: leds: Add LP5860 LED controller
1490903291a0 ARM: dts: aspeed: ibm: Use non-deprecated AT25 properties
666a578e38ce dt-bindings: soc: mediatek: dvfsrc: Document clock
0a000d225d77 riscv: dts: renesas: r9a07g043f: Move interrupt-parent to top node
22bcb33f74c0 dt-bindings: clock: renesas,r9a09g077/87: Add PCLKCAN ID
38d74c781461 dt-bindings: ata: ahci-platform: Drop unnecessary select schema
6c3f2d145bdf ARM: dts: microchip: sama7d65: add missing flexcom nodes
5d84ec142574 ARM: dts: microchip: sama7d65: add fifo-size to usart
78064bb3efab ARM: dts: microchip: sama7d65: add dma properties to usart6
b88e699ac98c arm64: dts: nuvoton: Add missing "device_type" property on memory node
972220e64030 ARM: dts: aspeed: add device tree for ASRock Rack ALTRAD8 BMC
ca9702b1c660 dt-bindings: arm: aspeed: add ASRock Rack ALTRAD8 board
ef7b87ccb63c ARM: dts: aspeed: bletchley: Remove try-power-role from connectors
9534fb1326fa ARM: dts: aspeed: Add Facebook Anacapa platform
e42ed37d5c01 dt-bindings: arm: aspeed: Add compatible for Facebook Anacapa BMC
77be93774ce5 dt-bindings: i2c: atmel,at91sam: add microchip,lan9691-i2c
9a70246b5079 dt-bindings: i2c: spacemit: add optional resets
89715b572f22 Merge tag 'renesas-dts-for-v6.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
a49e947cb82d Merge tag 'aspeed-6.20-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
b0a6b2163d84 Merge tag 'arm-soc/for-6.19/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
109d342a9d8c arm64: dts: marvell: change regulator-gpio to regulator-fixed
aebc5bb7e5e0 arm64: dts: marvell: cn9131-cf-solidwan: Add missing GPIO properties on "nxp,pca9536"
327f06a60d50 arm64: dts: marvell: Fix stray and typo "pinctrl-names" properties
f5b9b2c9e4b0 arm64: dts: marvell: Add missing "#phy-cells" to "usb-nop-xceiv"
2d48b886ad30 Merge branch '20260107-kaanapali-mmcc-v3-v3-0-8e10adc236a8@oss.qualcomm.com' into clk-for-6.20
a4ecfeacab64 dt-bindings: clock: qcom: document the Kaanapali GPU Clock Controller
d561bab67763 dt-bindings: clock: qcom: Add Kaanapali video clock controller
d5e064fd178d dt-bindings: clock: qcom: Add support for CAMCC for Kaanapali
c7c41265356a dt-bindings: clock: qcom: document Kaanapali DISPCC clock controller
8e073d33637a Merge branch '20251202-sm8750_camcc-v1-2-b3f7ef6723f1@oss.qualcomm.com' into clk-for-6.20
bf41478fce67 dt-bindings: clock: qcom: Add camera clock controller for SM8750 SoC
3c947a7e450a dt-bindings: clock: qcom: Add SDM439 Global Clock Controller
76fb317d3b51 dt-bindings: clock: qcom: Add MSM8940 Global Clock Controller
4ba4ffd81153 dt-bindings: remoteproc: Add HSM M4F core on TI K3 SoCs
7a5c4216a1c0 arm64: dts: qcom: qcs615: Drop IPA interconnects
69fb7ec26313 dt-bindings: usb: Add Socionext Uniphier DWC3 controller
8c743972ba19 dt-bindings: usb: Add Microchip LAN969x support
cdc01d91cdae dt-bindings: pinctrl: sunxi: Allow pinmux sub-pattern with leading numbers
52e36f69f85c dt-bindings: pinctrl: spacemit: add K3 SoC support
e4814cfbf128 dt-bindings: pinctrl: spacemit: convert drive strength to schema format
0e58ef414308 arm64: dts: amlogic: Use lowercase hex
fa33bb953bdc arm64: dts: amlogic: Use hyphen in node names
7da1cd217a9a ARM: dts: meson: drop iio-hwmon in favour of generic-adc-thermal
2951b17ddd23 dt-bindings: PCI: mediatek-gen3: Add MT7981 PCIe compatible
303e6869def2 arm64: dts: airoha: Use hyphen in node names
ef45fa08c122 regulator: dt-bindings: qcom,wcn3990-pmu: describe PMUs on WCN39xx
49ce882257aa ASoC: ES8389: Add some members and update
eb8511c0c383 arm64: dts: rockchip: Enable analog sound on RK3576 EVB1
849e6bb5169a arm64: dts: rockchip: Enable HDMI sound on RK3576 EVB1
144748745031 arm64: dts: rockchip: Enable HDMI sound on Luckfox Core3576
cea146581f75 arm64: dts: rockchip: Enable HDMI sound on FriendlyElec NanoPi M5
f32a74a77a1c arm64: dts: rockchip: Use a readable audio card name on NanoPi M5
7884b9f5136e arm64: dts: rockchip: enable NPU on rk3588-jaguar
6a46cc7da3d5 arm64: dts: rockchip: enable NPU on rk3588-tiger
1186cfe20ff6 dt-bindings: arm: rockchip: fix description for Radxa CM5
e701f00f60df dt-bindings: arm: rockchip: fix description for Radxa CM3I
d1d09800d87e arm64: dts: rockchip: Add missing everest,es8388 supplies to rk3399-roc-pc-plus
a558de474d84 arm64: dts: rockchip: Enable PCIe for ArmSoM Sige1
d7624078afea arm64: dts: rockchip: Enable the NPU on Turing RK1
df697d66f669 arm64: dts: rockchip: Enable the NPU on FriendlyElec CM3588
5682b1ad021c arm64: dts: rockchip: Enable the NPU on NanoPC T6/T6-LTS
d9f2b91a7b6c arm64: dts: rockchip: enable UFS controller on FriendlyElec NanoPi M5
e2debfad11d2 arm64: dts: rockchip: Add light/proximity sensor to Pinephone Pro
a26d68c1f8db arm64: dts: rockchip: Add magnetometer sensor to Pinephone Pro
0454d9dc8e56 ARM: dts: allwinner: sun5i-a13-utoo-p66: delete "power-gpios" property
3b4e2f9477be spi: st: use pm_ptr and remove __maybe_unused
8b01839fd7d8 arm64: dts: qcom: qcs615-ride: Enable DisplayPort
357ceb356d84 arm64: dts: qcom: talos: Add DisplayPort and QMP USB3-DP PHY
4e8ac02c90d2 arm64: dts: qcom: sm8750-qrd: Enable Iris codec
33f47143bfd1 arm64: dts: qcom: sm8750-mtp: Enable Iris codec
2aa74e476b84 arm64: dts: qcom: sm8750: Add Iris VPU v3.5
4501ac6fb0c8 dt-bindings: gpio: spacemit: add compatible name for K3 SoC
23cf8652240b arm64: zynqmp: Remove ina260 IIO description
dc06a3f283f1 arm64: dts: xilinx: Drop "label" property on dlg,slg7xl45106
bcfd0d929956 dt-bindings: soc: samsung: exynos-pmu: Drop unnecessary select schema
dd378a30dc54 dt-bindings: display: msm: document DSI controller and phy on QCS8300
3a283e84dbbc dt-bindings: msm: dsi-controller-main: document the QCS8300 DSI CTRL
6a4139dbc9be dt-bindings: display: msm-dsi-phy-7nm: document the QCS8300 DSI PHY
6f23a1829c95 arm64: dts: qcom: Add The Fairphone (Gen. 6)
a7438709761b arm64: dts: qcom: Add initial Milos dtsi
8165839b6501 arm64: dts: qcom: Add PMIV0104 PMIC
ca80589ab27c arm64: dts: qcom: Add PM7550 PMIC
9f874cd47174 arm64: dts: qcom: pm8550vs: Disable different PMIC SIDs by default
5253149fd5ee dt-bindings: arm: qcom: Add Milos and The Fairphone (Gen. 6)
2f681c6aa973 dt-bindings: qcom,pdc: document the Milos Power Domain Controller
7b2b07fc1c7d dt-bindings: crypto: qcom,prng: document Milos
1d4c234a7b5a ARM: dts: omap: dra7: Remove bogus #syscon-cells property
36bf7bcd26ce ARM: dts: ti/omap: omap*: fix watchdog node names
29f8d2affca6 ARM: dts: ti: Drop unused .dtsi
a1cceab259c1 ARM: dts: Drop am335x-base0033 devicetree
615ae4f85f0a ARM: dts: tps65910: Add gpio & interrupt properties
ead7e6e24f53 ARM: dts: omap: enable panic-indicator option
4f8825fbdb65 ARM: dts: ti/omap: omap4-epson-embt2ws: add powerbutton
1dae4dc95b72 arm64: dts: ti: Use lowercase hex
2aaacb2fbb3d arm64: dts: ti: Minor whitespace cleanup
8fbd19905cb1 arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1.
0585c2d3a38e arm64: dts: qcom: qcs8300-ride: enable pcie1 interface
c1c61f7b3cc0 arm64: dts: qcom: qcs8300: enable pcie1
359703ffd6a7 arm64: dts: qcom: qcs8300-ride: enable pcie0 interface
7d4282239989 arm64: dts: qcom: qcs8300: enable pcie0
8964374fadd9 arm64: dts: qcom: x1e80100: add TRNG node
dbffc86d5286 arm64: dts: qcom: sm8750: Fix BAM DMA probing
57591184f103 arm64: dts: qcom: monaco: add QCrypto node
5134a4c0be3d arm64: dts: qcom: lemans: add QCrypto node
9adce3539e71 arm64: dts: qcom: x1e80100-medion-sprchrgd-14-s1: correct firmware paths
4bf4a52efdb2 arm64: dts: qcom: msm8994-octagon: Fix Analog Devices vendor prefix of AD7147
38cc65257d59 arm64: dts: qcom: x1e80100: Add missing TCSR ref clock to the DP PHYs
5e25679a8251 arm64: dts: qcom: sm8750-mtp: Add eusb2 repeater tuning parameters
2176323db071 arm64: dts: qcom: msm8939: Add camss and cci
4c1cd0ce8367 arm64: dts: qcom: qcs6490-rb3gen2: Add TC9563 PCIe switch node
6fa474797f18 dt-bindings: cache: qcom,llcc: Remove duplicate llcc7_base for Glymur
efdc29224d43 media: dt-bindings: nxp,imx8-jpeg: Document optional SRAM support
a335ccfc867a arm64: dts: renesas: r8a779h0: Add WWDT nodes
52dc7f70ec4f arm64: dts: renesas: r8a779g0: Add WWDT nodes
8c5dddeaaeb7 arm64: dts: renesas: r8a779f0: Add WWDT nodes
6d625d11625f arm64: dts: renesas: r8a779a0: Add WWDT nodes
c776bb79ad41 arm64: dts: renesas: r8a77980: Add WWDT nodes
aaa9bd7ed5ca arm64: dts: renesas: r8a77970: Add WWDT nodes
7a90b2901668 arm64: dts: renesas: condor/v3hsk: Mark SWDT as reserved
aba65d6a28dc arm64: dts: renesas: r8a77980: Add SWDT node
dcaa888deaf1 arm64: dts: renesas: r9a09g056: Add TSU nodes
0e50629424cf arm64: dts: renesas: r9a09g087: Add DMAC support
d8a8b28b928c arm64: dts: renesas: r9a09g077: Add DMAC support
9d0b0c6918ad arm64: dts: renesas: r9a09g087: Add ICU support
47563af9e68d arm64: dts: renesas: r9a09g077: Add ICU support
db8c163135cf arm64: dts: renesas: r9a09g047e57-smarc: Enable rsci{2,4,9} nodes
305334f1f6be arm64: dts: renesas: renesas-smarc2: Move aliases to board DTS
a4dad3cab31a arm64: dts: renesas: r9a09g047: Add RSCI nodes
c8bb3fb9de1b ARM: dts: renesas: r9a06g032: Add Ethernet switch interrupts
6f9e11e7930c arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Add NMI wakeup button support
885176dbb7a6 arm64: dts: renesas: r9a09g056: Add RSPI nodes
e3bec0d47373 arm64: dts: renesas: r9a09g056: Add DMAC nodes
a65765461adf arm64: dts: renesas: r9a09g056: Add ICU node
5fcf901b614d arm64: dts: renesas: r9a09g047e57-smarc: Remove duplicate SW_LCD_EN
4d006a67e1c9 arm64: dts: renesas: r9a09g087: Add SPI nodes
70302041c4f0 arm64: dts: renesas: r9a09g077: Add SPI nodes
701acfab3819 arm64: dts: renesas: rzg3s-smarc: Enable PCIe
78bef1b4e046 arm64: dts: renesas: rzg3s-smarc-som: Add PCIe reference clock
2bef06d981fb arm64: dts: renesas: r9a08g045: Add PCIe node
2a9a9a7001bf arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable USB3.0 PHY and xHCI controller
aca0b5f6febb arm64: dts: renesas: r9a09g056: Add USB3 PHY/Host nodes
e21281585f19 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable USB3.0 PHYs and xHCI controllers
0c0335f6219a arm64: dts: renesas: r9a09g057: Add USB3 PHY/Host nodes
3c8761e141e7 arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable DU and DSI
2f3cc92c2800 arm64: dts: renesas: r9a09g056: Add DU and DSI nodes
65481a831b2e arm64: dts: renesas: r9a09g056: Add FCPV and VSPD nodes
3d6ad94f4adb arm64: dts: renesas: r9a09g057h48-kakip: Enable SPI NOR Flash
107fa1054cc8 arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable DU and DSI
35318a57a21b arm64: dts: renesas: r9a09g057: Add DU and DSI nodes
7f864a85f515 arm64: dts: renesas: r9a09g057: Add FCPV and VSPD nodes
59b3eee55f4f arm64: dts: renesas: rzt2h-n2h-evk: Add note about SD1 1.8V modes
4f02a02eb8bf spi: dt-bindings: at91: add microchip,lan9691-spi
d9589406774c ASoC: dt-bindings: realtek,rt5575: add support for ALC5575
b6baf8f15f6d ASoC: dt-bindings: ES8389: Add property about power supply
6d6470b98cac dt-bindings: PCI: qcom,pcie-apq8084: Move APQ8084 to dedicated schema
a36eadc896b3 dt-bindings: PCI: qcom,pcie-msm8996: Move MSM8996 to dedicated schema
0a6e47a4e25e dt-bindings: PCI: qcom,pcie-apq8064: Move APQ8064 to dedicated schema
587d0c36a682 dt-bindings: PCI: qcom,pcie-ipq9574: Move IPQ9574 to dedicated schema
3637b5946a3b dt-bindings: PCI: qcom,pcie-ipq4019: Move IPQ4019 to dedicated schema
9e64f603f5e6 dt-bindings: PCI: qcom,pcie-ipq8074: Move IPQ8074 to dedicated schema
148b98a0492b dt-bindings: PCI: qcom,pcie-ipq6018: Move IPQ6018 and IPQ8074 Gen3 to dedicated schema
2ff81d7e9fde dt-bindings: PCI: qcom,pcie-ipq5018: Move IPQ5018 to dedicated schema
27d8931ad218 dt-bindings: PCI: qcom,pcie-qcs404: Move QCS404 to dedicated schema
af4a42c35454 dt-bindings: PCI: qcom,pcie-sdm845: Move SDM845 to dedicated schema
e2592855c941 dt-bindings: PCI: qcom,pcie-sdx55: Move SDX55 to dedicated schema
b3bac4176ed4 dt-bindings: PCI: qcom,pcie-sm8150: Merge SC8180x into SM8150
af0daceaaadd dt-bindings: net: mscc-miim: add microchip,lan9691-miim
76b09e6295e1 arm64: dts: qcom: x1e80100: Fix USB combo PHYs SS1 and SS2 ref clocks
db07dcaaf4e9 arm64: dts: qcom: qcs8300: Add support for camss
b9335058da90 arm64: dts: qcom: sdm630: Add FastRPC nodes to ADSP
d22a889cb06f arm64: dts: qcom: sdm630: Add missing vote clock and GDSC to lpass_smmu
8043fa6a46ed arm64: dts: qcom: sdm630/660: Add CDSP-related nodes
724d10cf16e7 arm64: dts: qcom: hamoa-iot-evk: Add backlight support for eDP panel
272a014d1ac9 arm64: dts: qcom: hamoa-iot-evk: enable PWM RG LEDs
ecb7e38a5372 arm64: dts: qcom: msm8937: add reset for display subsystem
3a7b9a40fa23 arm64: dts: qcom: msm8917: add reset for display subsystem
1f020ad9b23b Merge branch '20251117-mdss-resets-msm8917-msm8937-v2-1-a7e9bbdaac96@mainlining.org' into HEAD
31e5ff1e20df arm64: dts: qcom: sdm845-oneplus: Mark l14a regulator as boot-on
fd5ed3423780 arm64: dts: qcom: sdm845-oneplus: Don't keep panel regulator always on
34a812a5f443 arm64: dts: qcom: sdm845-oneplus: Don't mark ts supply boot-on
73bd09554cba arm64: dts: qcom: sdm630: Add missing MDSS reset
c641ab7ba076 arm64: dts: qcom: ipq5018: Remove tsens v1 fallback compatible
4ac3d77913f9 arm64: dts: qcom: qrb2210: add dts for Arduino unoq
3283b13450f4 arm64: dts: qcom: agatti: add uart2 node
aa5f3c8a2fbf dt-bindings: arm: qcom: Add arduino imola, UnoQ codename
33d0a5dd67ab dt-bindings: vendor-prefixes: Add Arduino name
3daa37ff10a1 arm64: dts: qcom: Add qcs6490-rubikpi3 board dts
fe60d92de48d dt-bindings: arm: qcom: Add Thundercomm RUBIK Pi 3
598c096bc2e7 arm64: dts: qcom: lemans-evk: Add OTG support for primary USB controller
1638c980cb23 arm64: dts: qcom: sm8750-qrd: Add SDC2 node for sm8750 qrd board
a2c70dbeda4b arm64: dts: qcom: sm8750-mtp: Add SDC2 node for sm8750 mtp board
cca4ddfad433 arm64: dts: qcom: sm8750: Add SDC2 nodes for sm8750 soc
2fe969d9aadc arm64: dts: qcom: monaco-evk: Enable AMC6821 fan controller
73f68df4dfa2 arm64: dts: qcom: sdm845-xiaomi-beryllium: Add placeholders and sort
0d455c5e6b6f arm64: dts: qcom: sdm845-xiaomi-beryllium: Adjust firmware paths
4d171519043d arm64: dts: qcom: sdm845-xiaomi-beryllium: Enable SLPI
12ba95e3d7a7 arm64: dts: qcom: sdm845-oneplus: Add framebuffer
898ab8b9df3a arm64: dts: qcom: sdm845-oneplus-enchilada: Sort nodes alphabetically
085b3f85d3ff ARM: dts: qcom: msm8974-hammerhead: Update model property
6b296b50e9a6 arm64: dts: qcom: sdm850-huawei-matebook-e-2019: Correct ipa_fw_mem for the driver to load successfully
b7f781bfd930 arm64: dts: qcom: sdm850-huawei-matebook-e-2019: Remove duplicate reserved-memroy nodes
9ba9390130ff arm64: dts: qcom: hamoa-iot-evk: Add WLAN node for Hamoa IoT EVK board
43da1a95f1e3 arm64: dts: qcom: monaco-evk: Enable TPM (ST33)
dcf9ec139e0f arm64: dts: qcom: lemans-evk: Enable TPM (ST33)
d7a186f5dfa7 arm64: dts: qcom: lemans: Enable cpufreq cooling devices
4e2a153d23fc arm64: dts: qcom: monaco: Enable cpufreq cooling devices
03cb5b83d7a0 arm64: dts: qcom: Add support for Pixel 3 and Pixel 3 XL
e13a8a086724 dt-bindings: arm: qcom: Add Pixel 3 and 3 XL
31b92cd46b99 arm64: dts: qcom: sm8250-hdk: specify ZAP firmware name
d670f3c7f759 arm64: dts: qcom: sm8150-hdk,mtp: specify ZAP firmware name
b76977a01121 arm64: dts: qcom: sdm630: fix gpu_speed_bin size
08b986f449ef arm64: dts: qcom: sdm845-shift-axolotl: Add ath10k calibration variant
a04d37747b02 arm64: dts: qcom: sdm845-xiaomi-beryllium: Add ath10k calibration variant
4a1ff78c123e arm64: dts: qcom: sdm845-oneplus: add ath10k calibration variant
21fefb193e57 arm64: dts: qcom: sm7225-fairphone-fp4: Enable CCI pull-up
1674d6b26d4b arm64: dts: qcom: sm7225-fairphone-fp4: Add camera fixed regulators
8625b9a3127d arm64: dts: qcom: sm7225-fairphone-fp4: Add camera EEPROMs
17db2e966944 arm64: dts: qcom: SM8750: Enable CPUFreq support
2244f56b4c75 dt-bindings: mailbox: qcom: Document SM8750 CPUCP mailbox controller
db27b48bf1d4 arm64: dts: qcom: msm8939-asus-z00t: add hall sensor
512dea79e7b5 arm64: dts: qcom: msm8939-asus-z00t: add battery
21c4b46736a2 arm64: dts: qcom: x1e78100-t14s: Add audio playback over DisplayPort
8fac08b9bd33 arm64: dts: qcom: hamoa: Add sound DAI prefixes for DP
ae9e038fa854 arm64: dts: qcom: x1e80100-vivobook-s15: enable IRIS
fd267437f7c1 arm64: dts: qcom: x1e80100-vivobook-s15: add HDMI port
915a658aed2b arm64: dts: qcom: x1e80100-vivobook-s15: enable ps8830 retimers
68ca50543870 arm64: dts: qcom: sm8550-hdk-rear-camera-card: remove optional property
a7acf61fb13d arm64: dts: qcom: sm8550-hdk-rear-camera-card: rename supply properties
76783dfe7293 arm64: dts: qcom: sm8550-qrd: remove data-lanes property of image sensor
edaa8fefff5a arm64: dts: qcom: sm8550-qrd: rename image sensor supply properties
0606f7440187 arm64: dts: qcom: qcs8300-ride: Enable Display Port
ea42eceb35bc arm64: dts: qcom: qcs8300: add display dt nodes for MDSS, DPU, DisplayPort and eDP PHY
156a79d201cb arm64: dts: qcom: Use lowercase hex
d3047ae03e25 arm64: dts: qcom: Use hyphen in node names
877f6c418809 arm64: dts: qcom: Minor whitespace cleanup
8b7f9308dc11 arm64: dts: qcom: Add support for X1-based Surface Pro 11
549d1069e37d dt-bindings: arm: qcom: Document Microsoft Surface Pro 11
d57f7a29a719 arm64: dts: qcom: hamoa-iot-evk: Add vbus regulator support for Type-A ports
9f9a912174f7 arm64: dts: qcom: sdm845-xiaomi-polaris: Update firmware paths
088719338dda arm64: dts: qcom: sdm845-samsung-starqltechn: Update firmware paths
59721bb424ca arm64: dts: qcom: sdm845-axolotl: Update firmware paths
562f8c32c5eb arm64: dts: qcom: sdm845-oneplus: Update firmware paths
f5da59b7943a dt-bindings: remoteproc: qcom,sm8550-pas: Drop SM8750 ADSP from if-branch
88d1d6f92d38 arm64: dts: qcom: lemans-ride: Enable Adreno 663 GPU
0527619279f9 arm64: dts: qcom: lemans-evk: Enable Adreno 663 GPU
87d58e78dc67 arm64: dts: qcom: lemans: Add GPU cooling
7ee25117a21a arm64: dts: qcom: lemans: Add gpu and gmu nodes
61bd7199186c dt-bindings: remoteproc: qcom,adsp: Allow cx-supply on qcom,sdm845-slpi-pas
5eceae41c6d8 arm64: dts: qcom: sm8650-hdk: Add support for the Rear Camera Card overlay
c0edc9174808 arm64: dts: qcom: sm8650-qrd: Enable CAMSS and Samsung S5KJN1 camera sensor
cf956196ece0 arm64: dts: qcom: sm8650: Add description of MCLK pins
c9ddee7b0511 arm64: dts: qcom: sm8650: Add CAMSS device tree node
fda8e8debc98 arm64: dts: qcom: qcs8300: Enable TSENS support for QCS8300 SoC
77c41ebbdaaa arm64: dts: qcom: x1p42100-lenovo-thinkbook-16: add hdmi bridge with enable pin
09009c00f252 arm64: dts: qcom: x1p42100-lenovo-thinkbook-16: force usb2-only mode on usb_1_ss2_dwc3
f5d0c008df3e arm64: dts: qcom: hamoa: Extend the gcc input clock list
a22ceb6b7a1a Merge branch '20260103-ufs_symbol_clk-v2-1-51828cc76236@oss.qualcomm.com' into arm64-for-6.20
474356f70da3 Merge branch '20260103-ufs_symbol_clk-v2-1-51828cc76236@oss.qualcomm.com' into clk-for-6.20
69b5452282c0 dt-bindings: clock: qcom,x1e80100-gcc: Add missing UFS mux clocks
145e0a5201cb dt-bindings: gpio: add gpio-line-mux controller
c83e70e854f7 arm64: dts: arm: Use hyphen in node names
d209535a2215 dt-bindings: dma: atmel: add microchip,lan9691-dma
0eef03ce74ad dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5
72eddc8ea8bf dt-bindings: dma: pl08x: Do not use plural form of a proper noun PrimeCell
d78249fb43f5 dt-bindings: phy: Add DP PHY compatible for Glymur
055a94568c8e dt-bindings: phy: qcom-edp: Add missing clock for X Elite
8646a829f188 dt-bindings: phy: sc8280xp-qmp-pcie: Document Glymur PCIe Gen4 2-lanes PHY
23e55d439590 dt-bindings: phy: spacemit: add K1 USB2 PHY
403485907a74 dt-bindings: iio: adc: Add adi,ad4062
7e6a040da1bd arm64: dts: freescale: Add FRDM-IMX91 basic support
684abbc2df5b dt-bindings: arm: fsl: Add FRDM-IMX91 board
5117ca7e076f arm64: dts: imx8mp: Update Data Modul i.MX8M Plus eDM SBC DT to rev.903
c73456d398d4 dt-bindings: tpm: Add st,st33tphf2ei2c
7886adca522a arm64: dts: imx8mp-evk: add camera ov5640 and related nodes
262c3a71c374 arm64: dts: colibri-imx8x: Add cma memory
3c336bc649ea arm64: dts: colibri-imx8x: Add wi-fi 32kHz clock
e55847bd6e28 arm64: dts: colibri-imx8x: Add backlight
877922c5b151 dt-bindings: PCI: socionext,uniphier-pcie: Fix interrupt controller node name
66f0c0a17712 ARM: dts: imx: imx6sl: fix lcdif compatible
79a7d6846e08 ARM: dts: imx: imx6sll-kobo-clara2e: add regulator for EPD
0f98d63aeddb ARM: dts: imx: imx6sll: fix lcdif compatible
6d6926f24d25 dt-bindings: arm: fsl: Add Apalis iMX8QP
5066e222c45a arm64: dts: freescale: Add Apalis iMX8QP
25e7a5b1860c arm64: dts: freescale: Add NXP i.MX8QP SoC dtsi
5f992de15d2e arm64: dts: imx8qm: Add CPU cluster labels
cfb57cee6955 arm64: dts: freescale: Use lowercase hex
da35f24d5e4c arm64: dts: freescale: Minor whitespace cleanup
f4720b2ac3bc arm64: dts: freescale: Use hyphen in node names
99a5eada4037 arm64: dts: imx94: add mt35xu512aba spi nor support
d4ff990102a0 arm64: dts: imx94: add xspi device node
bf18a0f083bd arm64: dts: freescale: Add i.MX952 EVK basic device tree
3546aa155a84 arm64: dts: freescale: Add initial device tree for i.MX952
d8a61a7faedd dt-bindings: arm: fsl: add i.MX952 EVK board
849d046516eb arm64: dts: imx8mm-phycore-som: Update eth phy impedance
5696083f98bf arm64: dts: freescale: add support for NXP i.MX93 FRDM
065f6fa5617f dt-bindings: arm: fsl: add i.MX93 11x11 FRDM board
1a1ea4cc09ec arm64: dts: mb-smarc-2: Add PCIe support
055375ce9c0a arm64: dts: imx8mn-tqma8mqnl: fix LDO5 power off
8fa9e7b88ea0 arm64: dts: imx8mn-tqma8mqnl: remove virtual 1.8V regulator
39f4744a17ef arm64: dts: imx8mn-tqma8mqnl: remove virtual 3.3V regulator
531f8f3ea7b6 arm64: dts: imx8mm-tqma8mqml: fix LDO5 power off
685d79e7a0a2 arm64: dts: imx8mm-tqma8mqml: remove superfluous line
1c4004034c8b arm64: dts: imx8mm-tqma8mqml: remove virtual 1.8V regulator
28b9c486bbe5 arm64: dts: imx8mm-tqma8mqml: remove virtual 3.3V regulator
e9d1570ab83e arm64: dts: imx8mp-var-som: Add support for TSC2046 touchscreen
f253aed62f06 arm64: dts: imx8mp-var-som: Add support for WM8904 audio codec
730d6ed15b37 arm64: dts: imx8mp-var-som: Add WiFi and Bluetooth support
4827360c2c62 arm64: dts: imx8mp-var-som: Move UART2 description to Symphony carrier
fd9b983b0a5c arm64: dts: imx8mp-var-som: Move PCA9534 GPIO expander to Symphony carrier
98b561dd8a84 arm64: dts: imx8mp-var-som: Move USDHC2 support to Symphony carrier
b8b15223e313 arm64: dts: imx93-11x11-evk: Use phys to replace xceiver-supply
a35f3452022a arm64: dts: imx8mp-evk: Use phys to replace xceiver-supply
c731fb199e0c arm64: dts: imx95-15x15-evk: Use phys to replace xceiver-supply
2aa50e68d77c ARM: dts: imx6qdl: Add default GIC address cells
f749887b005d dt-bindings: power: fsl,imx-gpc: Document address-cells
fc5612e37c5c arm64: dts: imx8m{m,p}-venice-gw71xx: Add Magetometer
dfa8da65b542 arm64: dts: tqma8mpql-mba8mp-ras314: Add HDMI audio output support
fc93ef416a95 arm64: dts: tqma8mpql-mba8mp-ras314: Fix HDMI CEC pad control settings
05a087be0a3b arm64: dts: tqma8mpql-mba8mp-ras314: Fix Ethernet PHY IRQ support
265db33a1dc1 arm64: dts: tqma8mpql-mba8mpxl: Configure IEEE 1588 event out signal
d6330d919482 arm64: dts: tqma8mpql-mba8mpxl: Add HDMI audio output support
bcd6a3e5924c arm64: dts: tqma8mpql-mba8mpxl: Fix HDMI CEC pad control settings
ec64595818bc arm64: dts: tqma8mpql-mba8mpxl: Fix Ethernet PHY IRQ support
c8e421dbe62c arm64: dts: tqma8mpql-mba8mpxl: Adjust copyright text format
4b50dfe18fca arm64: dts: freescale: imx8mp-toradex-smarc: enable hdmi_pai device
ae6866e9e3ce arm64: dts: freescale: imx8mp-verdin: enable hdmi_pai device
00d3bccff648 arm64: dts: freescale: imx8mp-verdin: Remove obsolete TODO comments
dcf72f23ce11 arm64: dts: freescale: imx8-apalis: Add ethernet alias
0f0ad209f6d3 arm64: dts: imx93-var-som-symphony: Enable LPSPI6 controller
7ebd76fb18f3 arm64: dts: imx93-var-som-symphony: Add USB support
f124d4b6be32 arm64: dts: imx93-var-som-symphony: Add support for ft5x06 touch controller
a390238e4c05 arm64: dts: imx93-var-som-symphony: Update gpio aliases
1d6dfe10f3dc arm64: dts: imx8mp-phyboard-pollux: add PEB-WLBT-05 expansion board
e1e04d304210 arm64: dts: imx8mp-phyboard-pollux: Enable i2c3
53a79ec7e9ba arm64: dts: imx8mp-phycore-som: add spi-nor supply vcc
16bd398bad83 arm64: dts: imx8mp-phyboard-pollux: add fan-supply
4839861015c7 arm64: dts: imx91-11x11-evk: Add audio XCVR sound card support
0476fe3182c9 arm64: dts: imx91-11x11-evk: Add PDM microphone sound card support
84984b65264f arm64: dts: imx91-11x11-evk: Add WM8962 sound card support
fd45e8bd8d31 arm64: dts: imx91-11x11-evk: Add bt-sco sound card support
c7331a3e80a7 arm64: dts: imx91-11x11-evk: Refine label and node name of WM8962
d4831b59c96d arm64: dts: imx93-9x9-qsb: add CAN support overlay file
c7db72e1efdb arm64: dts: tqmls1046a: Move BMAN/QMAN buffers to DRAM1 area
e65fd05850b8 arm64: dts: cix: Use lowercase hex
3b0a1a86c1b0 arm64: dts: imx93-14x14-evk: Add audio XCVR sound card
f878699bd535 arm64: dts: imx93-14x14-evk: Add bt-sco sound card support
4ca9daec40bf arm64: dts: imx8ulp: add sim lpav node
8a7d32705460 arm64: dts: imx943-evk: add flexcan support
b8352dd72243 arm64: dts: imx8mm: Add label to thermal-zones
e28f3872d30f arm64: dts: add support for NXP i.MX8MP FRDM board
f4799a46389e arm64: dts: tqma8xxs-mb-smarc-2: replace 0 with IMX_LPCG_CLK_0 for lpcg indices
3a900199eb02 arm64: dts: tqma8xxs: replace 0 with IMX_LPCG_CLK_0 for lpcg indices
1519c352d6e3 arm64: dts: imx8qxp-mek: Add sensors under i2c1 bus
c5b9031ad104 arm64: dts: mba8xx: replace 0 with IMX_LPCG_CLK_0 for lpcg indices
93ef7b95e9bc dt-bindings: arm: fsl: Add i.MX8MP FRDM board
25160b69b379 dt-bindings: misc: qcom,fastrpc: Add compatible for Kaanapali
45a9a8710de2 Merge 6.19-rc3 into tty-next
43a9632e8426 Merge 6.19-rc3 into usb-next
d5e356ff7786 dt-bindings: arm: fsl: add TQ-Systems boards MBLS1028A and MBLS1028A-IND
094056360f84 arm64: dts: ls1028a: Add mbls1028a and mbls1028a-ind devicetrees
5269188d0ca0 arm64: dts: imx8mp libra: add peb-av-10 expansion board overlay
bad56036e188 arm64: dts: imx8mp libra: add and update display overlays
b4142775992e arm64: dts: imx943-evk: add ENETC, EMDIO and PTP Timer support
40fb558610ef arm64: dts: imx94: add basic NETC related nodes
269ec450562e arm64: dts: imx8dxl-ss-ddr: Add DB (system interconnects) pmu support for i.MX8DXL
e627f343ceb1 arm64: dts: imx8qm: add ddr perf device node
07248d41718a arm64: dts: exynos: gs101: add OTP node
81d5997ca8d3 dt-bindings: nvmem: add google,gs101-otp
c694f553fb48 dt-bindings: iio: dac: adding support for Microchip MCP47FEB02
baa9b8795d02 Merge tag 'drm-misc-next-2025-12-19' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
2dddaeb4ed59 ARM: dts: lpc3250-phy3250: replace deprecated at25 properties with new ones
3f6a920fb331 ARM: dts: lpc3250-phy3250: rename nodename at@0 to eeprom@0
8d3a3fc961d4 ARM: dts: lpc3250-ea3250: add key- prefix for gpio-keys
d7397e8437a3 ARM: dts: lpc32xx: remove usb bus and elevate all children nodes
5eb1ee981504 dt-bindings: clock: gcc-msm8917: Add missing MDSS reset
7f914b108e76 dt-bindings: phy: qcom,snps-eusb2-repeater: Add squelch param update
eea24368accb dt-bindings: phy: samsung,usb3-drd-phy: add power-domains
bcad7586c788 dt-bindings: phy: samsung,ufs-phy: add power-domains
597ea40a76ae riscv: dts: sophgo: cv180x: fix USB dwc2 FIFO sizes
82844859906d riscv: dts: spacemit: PCIe and PHY-related updates
4528d80729b6 riscv: dts: spacemit: Add a PCIe regulator
b1f43a24fb20 dt-bindings: phy: qcom,snps-eusb2-repeater: Add SMB2370 compatible
5dcfc273efb3 dt-bindings: phy: qcom-m31-eusb2: Add Glymur compatible
060d5204040d dt-bindings: phy: qcom,qmp-usb: Add Glymur USB UNI PHY compatible
84efb1e46493 dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp-phy: Add Glymur compatible
811070d10e20 dt-bindings: phy: lynx-28g: permit lane OF PHY providers
e716226b983b dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 combo ssphy
b07e2e09fd23 dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 combo hsphy
083f077a2b17 dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 HS phy compatible
a9d698d40a9c dt-bindings: phy: Add Apple Type-C PHY
faf30921471d dt-bindings: phy: Add QMP USB3+DP PHY for QCS615
1a150e32de4a dt-bindings: phy: ti,tcan104x-can: Document TI TCAN1046
65b515887eae dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add Kaanapali compatible
f6d21ccdb27e dt-bindings: phy: spacemit: Introduce PCIe PHY
b7bd9e297bcd dt-bindings: phy: spacemit: Add SpacemiT PCIe/combo PHY
640dd142b842 dt-bindings: phy: mediatek,hdmi-phy: Document extra clocks for MT8195
41ed45d831cc dt-bindings: phy: mediatek,hdmi-phy: Add support for MT8188 SoC
b7fffd6e649e dt-bindings: phy: mediatek,hdmi-phy: Fix clock output names for MT8195
5a6e565b06a3 dt-bindings: phy: renesas,rzg3e-usb3-phy: Add RZ/V2H(P) and RZ/V2N support
d568354c566c dt-bindings: PCI: Add ASPEED PCIe RC support
5f02e7e1f2a1 arm64: dts: allwinner: t527: orangepi-4a: Enable SPI-NOR flash
c9e70c9d70e7 arm64: dts: allwinner: sun55i: Add SPI controllers
b12e9e62106b dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3
018c8aea1016 dt-bindings: PCI: pci-imx6: Add external reference clock input
3d35ea1e2ed3 dt-bindings: PCI: dwc: Add external reference clock input
704b4787797c dt-bindings: dma: Update ADMA bindings for tegra264
a528e85719be dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Kaanapali and Glymur SoCs
878e36b07992 dt-bindings: dma: mediatek,uart-dma: Support all SoC generations
f45d6fde6cbd dt-bindings: dma: mediatek,uart-dma: Deprecate mediatek,dma-33bits
8f55e05a74a1 dt-bindings: dma: mediatek,uart-dma: Allow MT6795 single compatible
2eb7fe5323ab dt-bindings: serial: 8250: add SpacemiT K3 UART compatible
4fe4f5ca30b4 dt-bindings: soundwire: qcom: Add SoundWire v2.2.0 compatible
fbc706fb5108 arm64: dts: rockchip: Add support for CM5 IO carrier
062bfe1397e9 arm64: dts: rockchip: Add rk3588 based Radxa CM5
f95977b0c89a dt-bindings: arm: rockchip: Add Radxa CM5 IO board
b800c6b8a524 arm64: dts: rockchip: Fix Bluetooth on the RockPro64 board
351b6d4535a3 arm64: dts: rockchip: Correctly describe the ethernet phy on rk3368-lion
e005a6a6a483 arm64: dts: rockchip: add mdio subnode to gmac on rk3368
fea9c338acb6 arm64: dts: rockchip: add gmac reset property to rk3368
8b02f4f94875 arm64: dts: rockchip: add dma-coherent for pcie and gmac of RK3576
8565a1b32b70 arm64: dts: rockchip: Add EEPROMs for Radxa rk35xx boards
2316ac21f151 arm64: dts: rockchip: Add EEPROMs for Radxa ROCK 4 boards
1a397cae6d40 arm64: dts: rockchip: Add PCIe clkreq stuff for RK3588 EVB1
0580a73b73b5 arm64: dts: rockchip: enable saradc for ArmSoM Sige5
2283d2ef65a2 arm64: dts: rockchip: fix hp-det pin for ArmSoM Sige5
de6ba2504f41 arm64: dts: rockchip: remove rtc regulator for ArmSoM Sige5
14f6e356e5b6 arm64: dts: exynos: gs101: add samsung,sysreg property to CMU nodes
ce643d4bfeb7 dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required
b4fd7c4c07a9 arm64: dts: apm: Drop "dma" device_type
63e0adf9b981 arm64: dts: apm: Add "reg" to "syscon-reboot" and "syscon-poweroff"
daad4f62b2b8 arm64: dts: apm: Use recommended i2c node names
52f4e21d542a arm64: dts: apm/shadowcat: More clock clean-ups
c8dd6502b734 ARM: dts: vexpress/v2m-rs1: Use documented arm,vexpress,config-bus child node names
b616a8da152b arm64: dts: cavium: Drop thunder2
63d6abf9c58b arm64: dts: cavium: thunder-88xx: Add missing PL011 "uartclk"
56c2fd6d1110 arm64: dts: toshiba: Use recommended node names
9e34a4ebc868 arm64: dts: sprd: Use recommended node names
65c0c408742a arm64: dts: lg: Use recommended simple-bus node name
5bf46036b630 Add Richtek RT8092 support
07fbf0c472b7 dt-bindings: trivial-devices: add MEMSIC 3-axis magnetometer
09798c6c1e79 dt-bindings: iio: adc: Add TI ADS1018/ADS1118
50d0d702a0e7 arm64: dts: exynosautov920: add CMU_MFD clock DT nodes
64be690333c9 dt-bindings: clock: exynosautov920: add MFD clock definitions
26b539517189 dt-bindings: interconnect: mt8183-emi: Add support for MT8196 EMI
87946bb208d2 dt-bindings: iio: pressure: add honeywell,abp2030pa
b0874cc0cb01 dt-bindings: adc: ad9467: add support for ad9211
ae9b78f3b0f6 dt-bindings: iio: adc: Allow interrupts property for AST2600
38d4132cff68 dt-bindings: iio: amplifiers: add adl8113
732bb830616b dt-bindings: iio: frequency: adf4377: add clk provider
0c7fa39fd1d9 dt-bindings: iio: adc: Add the NXP SAR ADC for s32g2/3 platforms
7feadcfcf024 bindings: iio: adc: Add bindings for TI ADS131M0x ADCs
2a35d3e2047c riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite eMMC board
7d4b65c97dc7 riscv: dts: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board
ff4ff1c946da dt-bindings: riscv: starfive: Append JH-7110 SoC compatible to VisionFive 2 Lite board
0f73f72f1047 riscv: dts: microchip: convert clock and reset to use syscon
37c111e32113 riscv: dts: microchip: fix mailbox description
beaed6606d0d riscv: dts: spacemit: Define the P1 PMIC regulators for Milk-V Jupiter
ec6196767c82 riscv: dts: spacemit: Define fixed regulators for Milk-V Jupiter
ee403823f721 riscv: dts: spacemit: Enable i2c8 adapter for Milk-V Jupiter
15c7d2ad67b7 dt-bindings: arm: add CTCU device for monaco
8ffd14a98368 regulator: dt-bindings: rt5739: Add compatible for rt8092
fbe3420b01ce dt-bindings: crypto: qcom,prng: document x1e80100
dd856b778007 dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock
4b6c9d1fcf45 dt-bindings: memory: SDRAM channel: standardise node name
88fb21f0ef05 dt-bindings: memory: add DDR4 channel compatible
9c419da2b200 dt-bindings: memory: factorise LPDDR channel binding into SDRAM channel
6df6c46201b7 dt-bindings: memory: introduce DDR4
0382002144ff dt-bindings: memory: factorise LPDDR props into SDRAM props
db9dced71118 arm64: dts: qcom: kaanapali: Add base QRD board
f7ca89348e89 arm64: dts: qcom: kaanapali: Add base MTP board
164f7fd40b0a arm64: dts: qcom: Introduce Kaanapali SoC
60c72b6368ad dt-bindings: gpio-mmio: Add compatible string for opencores,gpio
f41679bfdea2 dt-binding: Update oss email address for Coresight documents
68c9fde54b6f dt-bindings: gpio: gpio-pca95xx: Add tcal6408 and tcal6416
f4011c42cddc spi: atcspi200: Add support for Andes ATCSPI200 SPI
af22e45e02bd Add support for NXP XSPI
334b71418b40 dt-bindings: sram: Document qcom,kaanapali-imem and its child node
93a34c934bcb dt-bindings: interrupt-controller: qcom,pdc: Document Kaanapali Power Domain Controller
9c6317967505 arm64: dts: qcom: glymur: Add header file for IPCC physical client IDs
3dbd10723da9 arm64: dts: qcom: kaanapali: Add header file for IPCC physical client IDs
359dc79529e1 dt-bindings: arm: qcom: Document Kaanapali SoC and its reference boards
1c3b4ebde5d9 dt-bindings: kbuild: Support single binding targets
0bb6369246cd dt-bindings: serial: renesas,rsci: Document RZ/G3E support
cc984eb3ac47 dt-bindings: usb: ehci/ohci: Allow "dma-coherent"
fda6a3af2717 dt-bindings: usb: aspeed,usb-vhub: Add ast2700 support
77288092704a spi: dt-bindings: Add support for ATCSPI200 SPI controller
850fc833f4de spi: dt-bindings: nxp,imx94-xspi: Document imx94 xspi
e428cef4e510 dt-bindings: eeprom: at24: Add compatible for Giantec GT24P64A
939e665c98f4 dt-bindings: eeprom: at24: Add compatible for Belling BL24C04A/BL24C16F
b2ddd1407bd8 arm64: dts: nuvoton: npcm845: Minor whitespace cleanup
369ea92a0ba8 ARM: dts: aspeed: bletchley: Fix ADC vref property names
6c97c266b7e2 ARM: dts: aspeed: bletchley: Remove unused i2c13 property
d5bef6c517be ARM: dts: aspeed: bletchley: Remove unused pca9539 properties
503ba8c17489 ARM: dts: aspeed: bletchley: Fix SPI GPIO property names
b0fc72d0fd4f ARM: dts: aspeed: bletchley: Use generic node names
69f6a0439d1c arm64: dts: qcom: Add dts for Medion SPRCHRGD 14 S1
902f98ec4c7e dt-bindings: arm: qcom: Add Medion SPRCHRGD device
7002cccbca31 dt-bindings: vendor-prefixes: Add Medion AG
5db94f229c4d dt-bindings: arm: qcom: Add TUXEDO Computers device
a4260e9a499e dt-bindings: vendor-prefixes: Add prefix for TUXEDO Computers GmbH
de01f35c5a1c arm64: dts: qcom: x1e80100: Add crypto engine
b446b4ec2c90 dt-bindings: cache: qcom,llcc: Document Glymur LLCC block
742958230ddd dt-bindings: dma: rz-dmac: Document RZ/V2N SoC support
0a67d1f7abec arm64: dts: apple: t8103,t60xx,t8112: Add SMC RTC node
175e8d07552c arm64: dts: ti: am62p-verdin: Fix SD regulator startup delay
b69aee46fbd4 arm64: dts: ti: k3-am69-aquila-clover: Fix USB-C Sink PDO
a06a6c103830 arm64: dts: ti: k3-am69-aquila-dev: Fix USB-C Sink PDO
4c6ed1fbc802 arm64: dts: ti: k3-am62(a)-phycore-som: Add bootphase tag to phy_gmii_sel
3643b0cdb050 arm64: dts: ti: k3-am62a-phycore-som: Add bootphase tag to cpsw_mac_syscon
360af8e29a09 arm64: dts: ti: k3-am62-phycore-som: Add bootphase tag to cpsw_mac_syscon
5cf13d2361a0 dt-bindings: display: simple: Add HannStar HSD156JUW2
9de19890d586 dt-bindings: panel: sw43408: adjust to reflect the DDIC and panel used
3530205b3d2d dt-bindings: display: panel: document Samsung LTL106HL02 MIPI DSI panel
c4eeea27c179 dt-bindings: panel: s6e3fc2x01: Sort and remove unnecessary properties
9545482937e1 dt-bindings: display: bridge: renesas,dsi: Document RZ/V2H(P) and RZ/V2N
acafbf556c58 arm64: dts: exynos: gs101: remove syscon compatible from pmu node
dd8272ff3d82 dt-bindings: soc: samsung: exynos-pmu: remove syscon for google,gs101-pmu
1687936de261 arm64: dts: exynos: gs101: add TRNG node
287bd1d9dc3d dt-bindings: rng: add google,gs101-trng compatible
df87acc301ed arm64: dts: toshiba: tmpv7708: Align node names with DT bindings
3f0637678adc dt-bindings: input: touchscreen: sitronix,st1232: Add Sitronix ST1624
71b378318155 arm64: dts: renesas: r9a09g087: Add ICU support
4d00bb62d078 arm64: dts: renesas: r9a09g077: Add ICU support
e93a0c58d942 dt-bindings: interrupt-controller: Document RZ/{T2H,N2H} ICU
19045e6732f7 dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/V2N SoC
ece61d4846f5 dt-bindings: display: sitronix,st7920: Add DT schema
32d3ab0dc516 Revert "arm64: zynqmp: Add an OP-TEE node to the device tree"
f13b85a2d2b1 dt-bindings: samsung: exynos-pmu: Add compatible for ARTPEC-9 SoC
50cf13d13467 dt-bindings: crypto: Document aspeed,ahbc property for Aspeed ACRY
1f24cf665d53 dt-bindings: bus: aspeed: Require syscon for AST2600 AHB controller
ee4930d07cd8 spi: dt-bindings: st,stm32-spi: add 'power-domains' property
7087598fc395 dt-bindings: display: rockchip: dw-hdmi: Add compatible for RK3368 HDMI
611d4c06a52b dt-bindings: display: sitronix,st7571: add example for SPI
1de14357fd3e arm64: dts: rockchip: Add accelerometer sensor to Pinephone Pro
7a509b4cc03a arm64: dts: rockchip: Enable SPDIF audio on Rock 5 ITX
42cd507a2b60 arm64: dts: rockchip: Add overlay for the PCIe slot on RK3576 EVB1
a1d0aa733c95 ARM: dts: rockchip: Add vdec node for RK3288
8118230e468a Merge tag 'renesas-r9a09g077-dt-binding-defs-tag5' into renesas-clk-for-v6.20
8fca00ce3ded arm64: dts: renesas: r9a09g047e57-smarc: Enable USB3HOST
8417721829a8 arm64: dts: renesas: r9a09g047: Add USB3 PHY/Host nodes
69eed72c5fb4 arm64: dts: morello: Add CMN PMU
7b95e57087a3 dt-bindings: clock: add video clock indices for Amlogic S4 SoC
31830fbb34cd dt-bindings: clock: add Amlogic T7 peripherals clock controller
ef0b78ba80e2 dt-bindings: clock: add Amlogic T7 SCMI clock controller
72e85902bc50 dt-bindings: clock: add Amlogic T7 PLL clock controller
5398a2b25b76 arm64: dts: xilinx: fix zynqmp opp-table-cpu
20e8d5272d35 dt-bindings: watchdog: xlnx,versal-wwdt: Add optional power-domains property
3a2f82d65ea4 arm64: dts: xilinx: add soc-specific spi compatibles for zynqmp/versal-net
85688947778b dt-bindings: remoteproc: Fix dead link to Keystone DSP GPIO binding
ec50d9b41883 spi: dt-bindings: renesas,rzv2h-rspi: document optional support for DMA
0a1bf0f89da3 regulator: dt-bindings: Add MAX77675 regulator
58a97f574841 ARM: dts: aspeed: g6: Drop clocks property from arm,armv7-timer
b58c36147430 ARM: dts: aspeed: ast2600-evb: Tidy up A0 work-around for UART5
a6437be91962 ARM: dts: aspeed: g6: Drop unspecified aspeed,ast2600-udma node
1c058c935dba ARM: dts: aspeed: Drop syscon compatible from EDAC in g6 dtsi
0eba8928dd9b ARM: dts: aspeed: Use specified wp-inverted property for AST2600 EVB
e58b7c23f328 ARM: dts: aspeed: Remove sdhci-drive-type property from AST2600 EVB
d977cfd7e272 ARM: dts: aspeed: Add NVIDIA MSX4 HPM
7af30bbc499b dt-bindings: arm: aspeed: Add NVIDIA MSX4 board
c7ad566648eb ARM: dts: aspeed: clemente: move hdd_led to its own gpio-leds group
1ab4552ceea7 ARM: dts: aspeed: clemente: add gpio line name to io expander
9dd33e615ac1 ARM: dts: aspeed: santabarbara: Enable ipmb device for OCP debug card
0243b6d087e0 ARM: dts: aspeed: santabarbara: Add swb IO expander and gpio line names
5392ed835618 ARM: dts: aspeed: clemente: Add EEPROMs for boot and data drive FRUs
7cae5ebf72c1 ARM: dts: aspeed: harma: add fanboard presence sgpio
e1000bea7203 ARM: dts: aspeed: bletchley: remove WDTRST1 assertion from wdt1
17d42cb3766f Merge tag 'ib-mfd-input-power-regulator-v6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into next
7f5b334c61b7 Merge tag 'v6.18' into next
69c26d595c11 dt-bindings: clock: renesas,r9a09g077/87: Add XSPI0/1 IDs
7327e6ab013e arm64: dts: broadcom: bcm2712: Add watchdog DT node
2bdb3ae4c5fb arm64: dts: broadcom: bcm2712: Enable RNG

git-subtree-dir: dts/upstream
git-subtree-split: 0f7b6a4fa8c5f6f5aa14c31aa7918e3f9d70688c
---
 .../clock/amlogic,s4-peripherals-clkc.h            |  11 +
 .../clock/amlogic,t7-peripherals-clkc.h            | 228 ++++++++++++
 include/dt-bindings/clock/amlogic,t7-pll-clkc.h    |  56 +++
 include/dt-bindings/clock/amlogic,t7-scmi.h        |  47 +++
 include/dt-bindings/clock/aspeed-clock.h           |   1 +
 include/dt-bindings/clock/google,gs101.h           |  36 ++
 include/dt-bindings/clock/oxsemi,ox810se.h         |  19 -
 include/dt-bindings/clock/oxsemi,ox820.h           |  29 --
 include/dt-bindings/clock/qcom,gcc-msm8917.h       |   2 +
 .../clock/qcom,kaanapali-cambistmclkcc.h           |  33 ++
 include/dt-bindings/clock/qcom,kaanapali-camcc.h   | 147 ++++++++
 include/dt-bindings/clock/qcom,kaanapali-dispcc.h  | 109 ++++++
 include/dt-bindings/clock/qcom,kaanapali-gpucc.h   |  47 +++
 .../dt-bindings/clock/qcom,kaanapali-gxclkctl.h    |  13 +
 include/dt-bindings/clock/qcom,kaanapali-videocc.h |  58 +++
 include/dt-bindings/clock/qcom,mss-sc7180.h        |  12 -
 .../dt-bindings/clock/qcom,sm8750-cambistmclkcc.h  |  30 ++
 include/dt-bindings/clock/qcom,sm8750-camcc.h      | 151 ++++++++
 include/dt-bindings/clock/qcom,x1e80100-gcc.h      |   3 +
 .../dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h |   3 +
 .../dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h |   3 +
 include/dt-bindings/clock/samsung,exynosautov920.h |   4 +
 include/dt-bindings/clock/spacemit,k3-clocks.h     | 390 +++++++++++++++++++++
 include/dt-bindings/clock/thead,th1520-clk-ap.h    |   1 +
 include/dt-bindings/clock/xlnx-versal-clk.h        | 123 -------
 include/dt-bindings/clock/xlnx-zynqmp-clk.h        | 133 -------
 include/dt-bindings/dma/jz4775-dma.h               |  44 ---
 include/dt-bindings/dma/x2000-dma.h                |  54 ---
 include/dt-bindings/gce/mt6779-gce.h               | 222 ------------
 include/dt-bindings/gpio/nvidia,tegra264-gpio.h    |  61 ++++
 include/dt-bindings/input/linux-event-codes.h      |   4 +
 include/dt-bindings/interconnect/mediatek,mt8196.h |  48 +++
 include/dt-bindings/memory/mt6779-larb-port.h      | 206 -----------
 include/dt-bindings/mux/ti-serdes.h                | 190 ----------
 include/dt-bindings/phy/phy.h                      |   5 +
 include/dt-bindings/pinctrl/mt6397-pinfunc.h       | 257 --------------
 .../regulator/samsung,s2mpg10-regulator.h          |  53 +++
 include/dt-bindings/reset/bcm6318-reset.h          |  20 --
 include/dt-bindings/reset/imx8ulp-pcc-reset.h      |  59 ----
 include/dt-bindings/reset/oxsemi,ox810se.h         |  42 ---
 include/dt-bindings/reset/oxsemi,ox820.h           |  42 ---
 include/dt-bindings/reset/spacemit,k3-resets.h     | 195 +++++++++++
 include/dt-bindings/sound/audio-jack-events.h      |  10 -
 .../dt-bindings/thermal/mediatek,lvts-thermal.h    |  29 ++
 44 files changed, 1768 insertions(+), 1462 deletions(-)
 create mode 100644 include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
 create mode 100644 include/dt-bindings/clock/amlogic,t7-pll-clkc.h
 create mode 100644 include/dt-bindings/clock/amlogic,t7-scmi.h
 delete mode 100644 include/dt-bindings/clock/oxsemi,ox810se.h
 delete mode 100644 include/dt-bindings/clock/oxsemi,ox820.h
 create mode 100644 include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h
 create mode 100644 include/dt-bindings/clock/qcom,kaanapali-camcc.h
 create mode 100644 include/dt-bindings/clock/qcom,kaanapali-dispcc.h
 create mode 100644 include/dt-bindings/clock/qcom,kaanapali-gpucc.h
 create mode 100644 include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h
 create mode 100644 include/dt-bindings/clock/qcom,kaanapali-videocc.h
 delete mode 100644 include/dt-bindings/clock/qcom,mss-sc7180.h
 create mode 100644 include/dt-bindings/clock/qcom,sm8750-cambistmclkcc.h
 create mode 100644 include/dt-bindings/clock/qcom,sm8750-camcc.h
 create mode 100644 include/dt-bindings/clock/spacemit,k3-clocks.h
 delete mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h
 delete mode 100644 include/dt-bindings/clock/xlnx-zynqmp-clk.h
 delete mode 100644 include/dt-bindings/dma/jz4775-dma.h
 delete mode 100644 include/dt-bindings/dma/x2000-dma.h
 delete mode 100644 include/dt-bindings/gce/mt6779-gce.h
 create mode 100644 include/dt-bindings/gpio/nvidia,tegra264-gpio.h
 create mode 100644 include/dt-bindings/interconnect/mediatek,mt8196.h
 delete mode 100644 include/dt-bindings/memory/mt6779-larb-port.h
 delete mode 100644 include/dt-bindings/mux/ti-serdes.h
 delete mode 100644 include/dt-bindings/pinctrl/mt6397-pinfunc.h
 create mode 100644 include/dt-bindings/regulator/samsung,s2mpg10-regulator.h
 delete mode 100644 include/dt-bindings/reset/bcm6318-reset.h
 delete mode 100644 include/dt-bindings/reset/imx8ulp-pcc-reset.h
 delete mode 100644 include/dt-bindings/reset/oxsemi,ox810se.h
 delete mode 100644 include/dt-bindings/reset/oxsemi,ox820.h
 create mode 100644 include/dt-bindings/reset/spacemit,k3-resets.h
 delete mode 100644 include/dt-bindings/sound/audio-jack-events.h

(limited to 'include')

diff --git a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
index 861a331963a..b0fc549f53e 100644
--- a/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
+++ b/include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h
@@ -232,5 +232,16 @@
 #define CLKID_HDCP22_SKPCLK_SEL		222
 #define CLKID_HDCP22_SKPCLK_DIV		223
 #define CLKID_HDCP22_SKPCLK		224
+#define CLKID_CTS_ENCL_SEL		225
+#define CLKID_CTS_ENCL			226
+#define CLKID_CDAC_SEL			227
+#define CLKID_CDAC_DIV			228
+#define CLKID_CDAC			229
+#define CLKID_DEMOD_CORE_SEL		230
+#define CLKID_DEMOD_CORE_DIV		231
+#define CLKID_DEMOD_CORE		232
+#define CLKID_ADC_EXTCLK_IN_SEL		233
+#define CLKID_ADC_EXTCLK_IN_DIV		234
+#define CLKID_ADC_EXTCLK_IN		235
 
 #endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H */
diff --git a/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
new file mode 100644
index 00000000000..32c4b62037d
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,t7-peripherals-clkc.h
@@ -0,0 +1,228 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_PERIPHERALS_CLKC_H
+#define __T7_PERIPHERALS_CLKC_H
+
+#define CLKID_RTC_DUALDIV_IN		0
+#define CLKID_RTC_DUALDIV_DIV		1
+#define CLKID_RTC_DUALDIV_SEL		2
+#define CLKID_RTC_DUALDIV		3
+#define CLKID_RTC			4
+#define CLKID_CECA_DUALDIV_IN		5
+#define CLKID_CECA_DUALDIV_DIV		6
+#define CLKID_CECA_DUALDIV_SEL		7
+#define CLKID_CECA_DUALDIV		8
+#define CLKID_CECA			9
+#define CLKID_CECB_DUALDIV_IN		10
+#define CLKID_CECB_DUALDIV_DIV		11
+#define CLKID_CECB_DUALDIV_SEL		12
+#define CLKID_CECB_DUALDIV		13
+#define CLKID_CECB			14
+#define CLKID_SC_SEL			15
+#define CLKID_SC_DIV			16
+#define CLKID_SC			17
+#define CLKID_DSPA_0_SEL		18
+#define CLKID_DSPA_0_DIV		19
+#define CLKID_DSPA_0			20
+#define CLKID_DSPA_1_SEL		21
+#define CLKID_DSPA_1_DIV		22
+#define CLKID_DSPA_1			23
+#define CLKID_DSPA			24
+#define CLKID_DSPB_0_SEL		25
+#define CLKID_DSPB_0_DIV		26
+#define CLKID_DSPB_0			27
+#define CLKID_DSPB_1_SEL		28
+#define CLKID_DSPB_1_DIV		29
+#define CLKID_DSPB_1			30
+#define CLKID_DSPB			31
+#define CLKID_24M			32
+#define CLKID_24M_DIV2			33
+#define CLKID_12M			34
+#define CLKID_25M_DIV			35
+#define CLKID_25M			36
+#define CLKID_ANAKIN_0_SEL		37
+#define CLKID_ANAKIN_0_DIV		38
+#define CLKID_ANAKIN_0			39
+#define CLKID_ANAKIN_1_SEL		40
+#define CLKID_ANAKIN_1_DIV		41
+#define CLKID_ANAKIN_1			42
+#define CLKID_ANAKIN_01_SEL		43
+#define CLKID_ANAKIN			44
+#define CLKID_TS_DIV			45
+#define CLKID_TS			46
+#define CLKID_MIPI_CSI_PHY_0_SEL	47
+#define CLKID_MIPI_CSI_PHY_0_DIV	48
+#define CLKID_MIPI_CSI_PHY_0		49
+#define CLKID_MIPI_CSI_PHY_1_SEL	50
+#define CLKID_MIPI_CSI_PHY_1_DIV	51
+#define CLKID_MIPI_CSI_PHY_1		52
+#define CLKID_MIPI_CSI_PHY		53
+#define CLKID_MIPI_ISP_SEL		54
+#define CLKID_MIPI_ISP_DIV		55
+#define CLKID_MIPI_ISP			56
+#define CLKID_MALI_0_SEL		57
+#define CLKID_MALI_0_DIV		58
+#define CLKID_MALI_0			59
+#define CLKID_MALI_1_SEL		60
+#define CLKID_MALI_1_DIV		61
+#define CLKID_MALI_1			62
+#define CLKID_MALI			63
+#define CLKID_ETH_RMII_SEL		64
+#define CLKID_ETH_RMII_DIV		65
+#define CLKID_ETH_RMII			66
+#define CLKID_FCLK_DIV2_DIV8		67
+#define CLKID_ETH_125M			68
+#define CLKID_SD_EMMC_A_SEL		69
+#define CLKID_SD_EMMC_A_DIV		70
+#define CLKID_SD_EMMC_A			71
+#define CLKID_SD_EMMC_B_SEL		72
+#define CLKID_SD_EMMC_B_DIV		73
+#define CLKID_SD_EMMC_B			74
+#define CLKID_SD_EMMC_C_SEL		75
+#define CLKID_SD_EMMC_C_DIV		76
+#define CLKID_SD_EMMC_C			77
+#define CLKID_SPICC0_SEL		78
+#define CLKID_SPICC0_DIV		79
+#define CLKID_SPICC0			80
+#define CLKID_SPICC1_SEL		81
+#define CLKID_SPICC1_DIV		82
+#define CLKID_SPICC1			83
+#define CLKID_SPICC2_SEL		84
+#define CLKID_SPICC2_DIV		85
+#define CLKID_SPICC2			86
+#define CLKID_SPICC3_SEL		87
+#define CLKID_SPICC3_DIV		88
+#define CLKID_SPICC3			89
+#define CLKID_SPICC4_SEL		90
+#define CLKID_SPICC4_DIV		91
+#define CLKID_SPICC4			92
+#define CLKID_SPICC5_SEL		93
+#define CLKID_SPICC5_DIV		94
+#define CLKID_SPICC5			95
+#define CLKID_SARADC_SEL		96
+#define CLKID_SARADC_DIV		97
+#define CLKID_SARADC			98
+#define CLKID_PWM_A_SEL			99
+#define CLKID_PWM_A_DIV			100
+#define CLKID_PWM_A			101
+#define CLKID_PWM_B_SEL			102
+#define CLKID_PWM_B_DIV			103
+#define CLKID_PWM_B			104
+#define CLKID_PWM_C_SEL			105
+#define CLKID_PWM_C_DIV			106
+#define CLKID_PWM_C			107
+#define CLKID_PWM_D_SEL			108
+#define CLKID_PWM_D_DIV			109
+#define CLKID_PWM_D			110
+#define CLKID_PWM_E_SEL			111
+#define CLKID_PWM_E_DIV			112
+#define CLKID_PWM_E			113
+#define CLKID_PWM_F_SEL			114
+#define CLKID_PWM_F_DIV			115
+#define CLKID_PWM_F			116
+#define CLKID_PWM_AO_A_SEL		117
+#define CLKID_PWM_AO_A_DIV		118
+#define CLKID_PWM_AO_A			119
+#define CLKID_PWM_AO_B_SEL		120
+#define CLKID_PWM_AO_B_DIV		121
+#define CLKID_PWM_AO_B			122
+#define CLKID_PWM_AO_C_SEL		123
+#define CLKID_PWM_AO_C_DIV		124
+#define CLKID_PWM_AO_C			125
+#define CLKID_PWM_AO_D_SEL		126
+#define CLKID_PWM_AO_D_DIV		127
+#define CLKID_PWM_AO_D			128
+#define CLKID_PWM_AO_E_SEL		129
+#define CLKID_PWM_AO_E_DIV		130
+#define CLKID_PWM_AO_E			131
+#define CLKID_PWM_AO_F_SEL		132
+#define CLKID_PWM_AO_F_DIV		133
+#define CLKID_PWM_AO_F			134
+#define CLKID_PWM_AO_G_SEL		135
+#define CLKID_PWM_AO_G_DIV		136
+#define CLKID_PWM_AO_G			137
+#define CLKID_PWM_AO_H_SEL		138
+#define CLKID_PWM_AO_H_DIV		139
+#define CLKID_PWM_AO_H			140
+#define CLKID_SYS_DDR			141
+#define CLKID_SYS_DOS			142
+#define CLKID_SYS_MIPI_DSI_A		143
+#define CLKID_SYS_MIPI_DSI_B		144
+#define CLKID_SYS_ETHPHY		145
+#define CLKID_SYS_MALI			146
+#define CLKID_SYS_AOCPU			147
+#define CLKID_SYS_AUCPU			148
+#define CLKID_SYS_CEC			149
+#define CLKID_SYS_GDC			150
+#define CLKID_SYS_DESWARP		151
+#define CLKID_SYS_AMPIPE_NAND		152
+#define CLKID_SYS_AMPIPE_ETH		153
+#define CLKID_SYS_AM2AXI0		154
+#define CLKID_SYS_AM2AXI1		155
+#define CLKID_SYS_AM2AXI2		156
+#define CLKID_SYS_SD_EMMC_A		157
+#define CLKID_SYS_SD_EMMC_B		158
+#define CLKID_SYS_SD_EMMC_C		159
+#define CLKID_SYS_SMARTCARD		160
+#define CLKID_SYS_ACODEC		161
+#define CLKID_SYS_SPIFC			162
+#define CLKID_SYS_MSR_CLK		163
+#define CLKID_SYS_IR_CTRL		164
+#define CLKID_SYS_AUDIO			165
+#define CLKID_SYS_ETH			166
+#define CLKID_SYS_UART_A		167
+#define CLKID_SYS_UART_B		168
+#define CLKID_SYS_UART_C		169
+#define CLKID_SYS_UART_D		170
+#define CLKID_SYS_UART_E		171
+#define CLKID_SYS_UART_F		172
+#define CLKID_SYS_AIFIFO		173
+#define CLKID_SYS_SPICC2		174
+#define CLKID_SYS_SPICC3		175
+#define CLKID_SYS_SPICC4		176
+#define CLKID_SYS_TS_A73		177
+#define CLKID_SYS_TS_A53		178
+#define CLKID_SYS_SPICC5		179
+#define CLKID_SYS_G2D			180
+#define CLKID_SYS_SPICC0		181
+#define CLKID_SYS_SPICC1		182
+#define CLKID_SYS_PCIE			183
+#define CLKID_SYS_USB			184
+#define CLKID_SYS_PCIE_PHY		185
+#define CLKID_SYS_I2C_AO_A		186
+#define CLKID_SYS_I2C_AO_B		187
+#define CLKID_SYS_I2C_M_A		188
+#define CLKID_SYS_I2C_M_B		189
+#define CLKID_SYS_I2C_M_C		190
+#define CLKID_SYS_I2C_M_D		191
+#define CLKID_SYS_I2C_M_E		192
+#define CLKID_SYS_I2C_M_F		193
+#define CLKID_SYS_HDMITX_APB		194
+#define CLKID_SYS_I2C_S_A		195
+#define CLKID_SYS_HDMIRX_PCLK		196
+#define CLKID_SYS_MMC_APB		197
+#define CLKID_SYS_MIPI_ISP_PCLK		198
+#define CLKID_SYS_RSA			199
+#define CLKID_SYS_PCLK_SYS_APB		200
+#define CLKID_SYS_A73PCLK_APB		201
+#define CLKID_SYS_DSPA			202
+#define CLKID_SYS_DSPB			203
+#define CLKID_SYS_VPU_INTR		204
+#define CLKID_SYS_SAR_ADC		205
+#define CLKID_SYS_GIC			206
+#define CLKID_SYS_TS_GPU		207
+#define CLKID_SYS_TS_NNA		208
+#define CLKID_SYS_TS_VPU		209
+#define CLKID_SYS_TS_HEVC		210
+#define CLKID_SYS_PWM_AB		211
+#define CLKID_SYS_PWM_CD		212
+#define CLKID_SYS_PWM_EF		213
+#define CLKID_SYS_PWM_AO_AB		214
+#define CLKID_SYS_PWM_AO_CD		215
+#define CLKID_SYS_PWM_AO_EF		216
+#define CLKID_SYS_PWM_AO_GH		217
+
+#endif /* __T7_PERIPHERALS_CLKC_H */
diff --git a/include/dt-bindings/clock/amlogic,t7-pll-clkc.h b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
new file mode 100644
index 00000000000..e2481f2f116
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,t7-pll-clkc.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_PLL_CLKC_H
+#define __T7_PLL_CLKC_H
+
+/* GP0 */
+#define CLKID_GP0_PLL_DCO	0
+#define CLKID_GP0_PLL		1
+
+/* GP1 */
+#define CLKID_GP1_PLL_DCO	0
+#define CLKID_GP1_PLL		1
+
+/* HIFI */
+#define CLKID_HIFI_PLL_DCO	0
+#define CLKID_HIFI_PLL		1
+
+/* PCIE */
+#define CLKID_PCIE_PLL_DCO	0
+#define CLKID_PCIE_PLL_DCO_DIV2	1
+#define CLKID_PCIE_PLL_OD	2
+#define CLKID_PCIE_PLL		3
+
+/* MPLL */
+#define CLKID_MPLL_PREDIV	0
+#define CLKID_MPLL0_DIV		1
+#define CLKID_MPLL0		2
+#define CLKID_MPLL1_DIV		3
+#define CLKID_MPLL1		4
+#define CLKID_MPLL2_DIV		5
+#define CLKID_MPLL2		6
+#define CLKID_MPLL3_DIV		7
+#define CLKID_MPLL3		8
+
+/* HDMI */
+#define CLKID_HDMI_PLL_DCO	0
+#define CLKID_HDMI_PLL_OD	1
+#define CLKID_HDMI_PLL		2
+
+/* MCLK */
+#define CLKID_MCLK_PLL_DCO	0
+#define CLKID_MCLK_PRE		1
+#define CLKID_MCLK_PLL		2
+#define CLKID_MCLK_0_SEL	3
+#define CLKID_MCLK_0_DIV2	4
+#define CLKID_MCLK_0_PRE	5
+#define CLKID_MCLK_0		6
+#define CLKID_MCLK_1_SEL	7
+#define CLKID_MCLK_1_DIV2	8
+#define CLKID_MCLK_1_PRE	9
+#define CLKID_MCLK_1		10
+
+#endif /* __T7_PLL_CLKC_H */
diff --git a/include/dt-bindings/clock/amlogic,t7-scmi.h b/include/dt-bindings/clock/amlogic,t7-scmi.h
new file mode 100644
index 00000000000..27bd257bd4e
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,t7-scmi.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
+/*
+ * Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
+ */
+
+#ifndef __T7_SCMI_CLKC_H
+#define __T7_SCMI_CLKC_H
+
+#define CLKID_DDR_PLL_OSC			0
+#define CLKID_AUD_PLL_OSC			1
+#define CLKID_TOP_PLL_OSC			2
+#define CLKID_TCON_PLL_OSC			3
+#define CLKID_USB_PLL0_OSC			4
+#define CLKID_USB_PLL1_OSC			5
+#define CLKID_MCLK_PLL_OSC			6
+#define CLKID_PCIE_OSC				7
+#define CLKID_ETH_PLL_OSC			8
+#define CLKID_PCIE_REFCLK_PLL_OSC		9
+#define CLKID_EARC_OSC				10
+#define CLKID_SYS1_PLL_OSC			11
+#define CLKID_HDMI_PLL_OSC			12
+#define CLKID_SYS_CLK				13
+#define CLKID_AXI_CLK				14
+#define CLKID_FIXED_PLL_DCO			15
+#define CLKID_FIXED_PLL				16
+#define CLKID_FCLK_DIV2_DIV			17
+#define CLKID_FCLK_DIV2				18
+#define CLKID_FCLK_DIV2P5_DIV			19
+#define CLKID_FCLK_DIV2P5			20
+#define CLKID_FCLK_DIV3_DIV			21
+#define CLKID_FCLK_DIV3				22
+#define CLKID_FCLK_DIV4_DIV			23
+#define CLKID_FCLK_DIV4				24
+#define CLKID_FCLK_DIV5_DIV			25
+#define CLKID_FCLK_DIV5				26
+#define CLKID_FCLK_DIV7_DIV			27
+#define CLKID_FCLK_DIV7				28
+#define CLKID_FCLK_50M_DIV			29
+#define CLKID_FCLK_50M				30
+#define CLKID_CPU_CLK				31
+#define CLKID_A73_CLK				32
+#define CLKID_CPU_CLK_DIV16_DIV			33
+#define CLKID_CPU_CLK_DIV16			34
+#define CLKID_A73_CLK_DIV16_DIV			35
+#define CLKID_A73_CLK_DIV16			36
+
+#endif /* __T7_SCMI_CLKC_H */
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
index 06d568382c7..671e5a476ea 100644
--- a/include/dt-bindings/clock/aspeed-clock.h
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -53,5 +53,6 @@
 #define ASPEED_RESET_AHB		8
 #define ASPEED_RESET_CRT1		9
 #define ASPEED_RESET_HACE		10
+#define ASPEED_RESET_VIDEO		11
 
 #endif
diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
index 442f9e9037d..7a14dcb9f17 100644
--- a/include/dt-bindings/clock/google,gs101.h
+++ b/include/dt-bindings/clock/google,gs101.h
@@ -313,6 +313,42 @@
 #define CLK_APM_PLL_DIV4_APM				70
 #define CLK_APM_PLL_DIV16_APM				71
 
+/* CMU_DPU */
+#define CLK_MOUT_DPU_BUS_USER				1
+#define CLK_DOUT_DPU_BUSP				2
+#define CLK_GOUT_DPU_PCLK				3
+#define CLK_GOUT_DPU_CLK_DPU_OSCCLK_CLK			4
+#define CLK_GOUT_DPU_AD_APB_DPU_DMA_PCLKM		5
+#define CLK_GOUT_DPU_DPUF_ACLK_DMA			6
+#define CLK_GOUT_DPU_DPUF_ACLK_DPP			7
+#define CLK_GOUT_DPU_D_TZPC_DPU_PCLK			8
+#define CLK_GOUT_DPU_GPC_DPU_PCLK			9
+#define CLK_GOUT_DPU_LHM_AXI_P_DPU_I_CLK		10
+#define CLK_GOUT_DPU_LHS_AXI_D0_DPU_I_CLK		11
+#define CLK_GOUT_DPU_LHS_AXI_D1_DPU_I_CLK		12
+#define CLK_GOUT_DPU_LHS_AXI_D2_DPU_I_CLK		13
+#define CLK_GOUT_DPU_PPMU_DPUD0_ACLK			14
+#define CLK_GOUT_DPU_PPMU_DPUD0_PCLK			15
+#define CLK_GOUT_DPU_PPMU_DPUD1_ACLK			16
+#define CLK_GOUT_DPU_PPMU_DPUD1_PCLK			17
+#define CLK_GOUT_DPU_PPMU_DPUD2_ACLK			18
+#define CLK_GOUT_DPU_PPMU_DPUD2_PCLK			19
+#define CLK_GOUT_DPU_CLK_DPU_BUSD_CLK			20
+#define CLK_GOUT_DPU_CLK_DPU_BUSP_CLK			21
+#define CLK_GOUT_DPU_SSMT_DPU0_ACLK			22
+#define CLK_GOUT_DPU_SSMT_DPU0_PCLK			23
+#define CLK_GOUT_DPU_SSMT_DPU1_ACLK			24
+#define CLK_GOUT_DPU_SSMT_DPU1_PCLK			25
+#define CLK_GOUT_DPU_SSMT_DPU2_ACLK			26
+#define CLK_GOUT_DPU_SSMT_DPU2_PCLK			27
+#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S1		28
+#define CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S2		29
+#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S1		30
+#define CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S2		31
+#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S1		32
+#define CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S2		33
+#define CLK_GOUT_DPU_SYSREG_DPU_PCLK			34
+
 /* CMU_HSI0 */
 #define CLK_FOUT_USB_PLL					1
 #define CLK_MOUT_PLL_USB					2
diff --git a/include/dt-bindings/clock/oxsemi,ox810se.h b/include/dt-bindings/clock/oxsemi,ox810se.h
deleted file mode 100644
index 7256365160f..00000000000
--- a/include/dt-bindings/clock/oxsemi,ox810se.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef DT_CLOCK_OXSEMI_OX810SE_H
-#define DT_CLOCK_OXSEMI_OX810SE_H
-
-#define CLK_810_LEON		0
-#define CLK_810_DMA_SGDMA	1
-#define CLK_810_CIPHER		2
-#define CLK_810_SATA		3
-#define CLK_810_AUDIO		4
-#define CLK_810_USBMPH		5
-#define CLK_810_ETHA		6
-#define CLK_810_PCIEA		7
-#define CLK_810_NAND		8
-
-#endif /* DT_CLOCK_OXSEMI_OX810SE_H */
diff --git a/include/dt-bindings/clock/oxsemi,ox820.h b/include/dt-bindings/clock/oxsemi,ox820.h
deleted file mode 100644
index 55f4226e2f3..00000000000
--- a/include/dt-bindings/clock/oxsemi,ox820.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef DT_CLOCK_OXSEMI_OX820_H
-#define DT_CLOCK_OXSEMI_OX820_H
-
-/* PLLs */
-#define CLK_820_PLLA		0
-#define CLK_820_PLLB		1
-
-/* Gate Clocks */
-#define CLK_820_LEON		2
-#define CLK_820_DMA_SGDMA	3
-#define CLK_820_CIPHER		4
-#define CLK_820_SD		5
-#define CLK_820_SATA		6
-#define CLK_820_AUDIO		7
-#define CLK_820_USBMPH		8
-#define CLK_820_ETHA		9
-#define CLK_820_PCIEA		10
-#define CLK_820_NAND		11
-#define CLK_820_PCIEB		12
-#define CLK_820_ETHB		13
-#define CLK_820_REF600		14
-#define CLK_820_USBDEV		15
-
-#endif /* DT_CLOCK_OXSEMI_OX820_H */
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8917.h b/include/dt-bindings/clock/qcom,gcc-msm8917.h
index 4e3897b3669..c592682d5ba 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8917.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8917.h
@@ -187,6 +187,7 @@
 #define MSM8937_GCC_MDSS_PCLK1_CLK			179
 #define MSM8937_GCC_OXILI_AON_CLK			180
 #define MSM8937_GCC_OXILI_TIMER_CLK			181
+#define MSM8940_GCC_IPA_TBU_CLK				182
 
 /* GCC block resets */
 #define GCC_CAMSS_MICRO_BCR			0
@@ -194,6 +195,7 @@
 #define GCC_QUSB2_PHY_BCR			2
 #define GCC_USB_HS_BCR				3
 #define GCC_USB2_HS_PHY_ONLY_BCR		4
+#define GCC_MDSS_BCR				5
 
 /* GDSCs */
 #define CPP_GDSC				0
diff --git a/include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h b/include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h
new file mode 100644
index 00000000000..ddb083b5289
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_KAANAPALI_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_KAANAPALI_H
+
+/* CAM_BIST_MCLK_CC clocks */
+#define CAM_BIST_MCLK_CC_DEBUG_CLK				0
+#define CAM_BIST_MCLK_CC_DEBUG_DIV_CLK_SRC			1
+#define CAM_BIST_MCLK_CC_MCLK0_CLK				2
+#define CAM_BIST_MCLK_CC_MCLK0_CLK_SRC				3
+#define CAM_BIST_MCLK_CC_MCLK1_CLK				4
+#define CAM_BIST_MCLK_CC_MCLK1_CLK_SRC				5
+#define CAM_BIST_MCLK_CC_MCLK2_CLK				6
+#define CAM_BIST_MCLK_CC_MCLK2_CLK_SRC				7
+#define CAM_BIST_MCLK_CC_MCLK3_CLK				8
+#define CAM_BIST_MCLK_CC_MCLK3_CLK_SRC				9
+#define CAM_BIST_MCLK_CC_MCLK4_CLK				10
+#define CAM_BIST_MCLK_CC_MCLK4_CLK_SRC				11
+#define CAM_BIST_MCLK_CC_MCLK5_CLK				12
+#define CAM_BIST_MCLK_CC_MCLK5_CLK_SRC				13
+#define CAM_BIST_MCLK_CC_MCLK6_CLK				14
+#define CAM_BIST_MCLK_CC_MCLK6_CLK_SRC				15
+#define CAM_BIST_MCLK_CC_MCLK7_CLK				16
+#define CAM_BIST_MCLK_CC_MCLK7_CLK_SRC				17
+#define CAM_BIST_MCLK_CC_PLL0					18
+#define CAM_BIST_MCLK_CC_PLL_TEST_CLK				19
+#define CAM_BIST_MCLK_CC_PLL_TEST_DIV_CLK_SRC			20
+#define CAM_BIST_MCLK_CC_SLEEP_CLK				21
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,kaanapali-camcc.h b/include/dt-bindings/clock/qcom,kaanapali-camcc.h
new file mode 100644
index 00000000000..58835136b35
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,kaanapali-camcc.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_KAANAPALI_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_KAANAPALI_H
+
+/* CAM_CC clocks */
+#define CAM_CC_CAM_TOP_AHB_CLK					0
+#define CAM_CC_CAM_TOP_FAST_AHB_CLK				1
+#define CAM_CC_CAMNOC_DCD_XO_CLK				2
+#define CAM_CC_CAMNOC_NRT_AXI_CLK				3
+#define CAM_CC_CAMNOC_NRT_CRE_CLK				4
+#define CAM_CC_CAMNOC_NRT_IPE_NPS_CLK				5
+#define CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK				6
+#define CAM_CC_CAMNOC_RT_AXI_CLK				7
+#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC				8
+#define CAM_CC_CAMNOC_RT_IFE_LITE_CLK				9
+#define CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK				10
+#define CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK				11
+#define CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK				12
+#define CAM_CC_CAMNOC_XO_CLK					13
+#define CAM_CC_CCI_0_CLK					14
+#define CAM_CC_CCI_0_CLK_SRC					15
+#define CAM_CC_CCI_1_CLK					16
+#define CAM_CC_CCI_1_CLK_SRC					17
+#define CAM_CC_CCI_2_CLK					18
+#define CAM_CC_CCI_2_CLK_SRC					19
+#define CAM_CC_CORE_AHB_CLK					20
+#define CAM_CC_CPHY_RX_CLK_SRC					21
+#define CAM_CC_CRE_AHB_CLK					22
+#define CAM_CC_CRE_CLK						23
+#define CAM_CC_CRE_CLK_SRC					24
+#define CAM_CC_CSI0PHYTIMER_CLK					25
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC				26
+#define CAM_CC_CSI1PHYTIMER_CLK					27
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC				28
+#define CAM_CC_CSI2PHYTIMER_CLK					29
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC				30
+#define CAM_CC_CSI3PHYTIMER_CLK					31
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC				32
+#define CAM_CC_CSI4PHYTIMER_CLK					33
+#define CAM_CC_CSI4PHYTIMER_CLK_SRC				34
+#define CAM_CC_CSI5PHYTIMER_CLK					35
+#define CAM_CC_CSI5PHYTIMER_CLK_SRC				36
+#define CAM_CC_CSID_CLK						37
+#define CAM_CC_CSID_CLK_SRC					38
+#define CAM_CC_CSID_CSIPHY_RX_CLK				39
+#define CAM_CC_CSIPHY0_CLK					40
+#define CAM_CC_CSIPHY1_CLK					41
+#define CAM_CC_CSIPHY2_CLK					42
+#define CAM_CC_CSIPHY3_CLK					43
+#define CAM_CC_CSIPHY4_CLK					44
+#define CAM_CC_CSIPHY5_CLK					45
+#define CAM_CC_DRV_AHB_CLK					46
+#define CAM_CC_DRV_XO_CLK					47
+#define CAM_CC_FAST_AHB_CLK_SRC					48
+#define CAM_CC_GDSC_CLK						49
+#define CAM_CC_ICP_0_AHB_CLK					50
+#define CAM_CC_ICP_0_CLK					51
+#define CAM_CC_ICP_0_CLK_SRC					52
+#define CAM_CC_ICP_1_AHB_CLK					53
+#define CAM_CC_ICP_1_CLK					54
+#define CAM_CC_ICP_1_CLK_SRC					55
+#define CAM_CC_IFE_LITE_AHB_CLK					56
+#define CAM_CC_IFE_LITE_CLK					57
+#define CAM_CC_IFE_LITE_CLK_SRC					58
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK				59
+#define CAM_CC_IFE_LITE_CSID_CLK				60
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC				61
+#define CAM_CC_IPE_NPS_AHB_CLK					62
+#define CAM_CC_IPE_NPS_CLK					63
+#define CAM_CC_IPE_NPS_CLK_SRC					64
+#define CAM_CC_IPE_NPS_FAST_AHB_CLK				65
+#define CAM_CC_IPE_PPS_CLK					66
+#define CAM_CC_IPE_PPS_FAST_AHB_CLK				67
+#define CAM_CC_JPEG_CLK						68
+#define CAM_CC_JPEG_CLK_SRC					69
+#define CAM_CC_OFE_AHB_CLK					70
+#define CAM_CC_OFE_ANCHOR_CLK					71
+#define CAM_CC_OFE_ANCHOR_FAST_AHB_CLK				72
+#define CAM_CC_OFE_CLK_SRC					73
+#define CAM_CC_OFE_HDR_CLK					74
+#define CAM_CC_OFE_HDR_FAST_AHB_CLK				75
+#define CAM_CC_OFE_MAIN_CLK					76
+#define CAM_CC_OFE_MAIN_FAST_AHB_CLK				77
+#define CAM_CC_PLL0						78
+#define CAM_CC_PLL0_OUT_EVEN					79
+#define CAM_CC_PLL0_OUT_ODD					80
+#define CAM_CC_PLL1						81
+#define CAM_CC_PLL1_OUT_EVEN					82
+#define CAM_CC_PLL2						83
+#define CAM_CC_PLL2_OUT_EVEN					84
+#define CAM_CC_PLL3						85
+#define CAM_CC_PLL3_OUT_EVEN					86
+#define CAM_CC_PLL4						87
+#define CAM_CC_PLL4_OUT_EVEN					88
+#define CAM_CC_PLL5						89
+#define CAM_CC_PLL5_OUT_EVEN					90
+#define CAM_CC_PLL6						91
+#define CAM_CC_PLL6_OUT_EVEN					92
+#define CAM_CC_PLL6_OUT_ODD					93
+#define CAM_CC_PLL7						94
+#define CAM_CC_PLL7_OUT_EVEN					95
+#define CAM_CC_QDSS_DEBUG_CLK					96
+#define CAM_CC_QDSS_DEBUG_CLK_SRC				97
+#define CAM_CC_QDSS_DEBUG_XO_CLK				98
+#define CAM_CC_SLEEP_CLK					99
+#define CAM_CC_SLOW_AHB_CLK_SRC					100
+#define CAM_CC_TFE_0_BAYER_CLK					101
+#define CAM_CC_TFE_0_BAYER_FAST_AHB_CLK				102
+#define CAM_CC_TFE_0_CLK_SRC					103
+#define CAM_CC_TFE_0_MAIN_CLK					104
+#define CAM_CC_TFE_0_MAIN_FAST_AHB_CLK				105
+#define CAM_CC_TFE_1_BAYER_CLK					106
+#define CAM_CC_TFE_1_BAYER_FAST_AHB_CLK				107
+#define CAM_CC_TFE_1_CLK_SRC					108
+#define CAM_CC_TFE_1_MAIN_CLK					109
+#define CAM_CC_TFE_1_MAIN_FAST_AHB_CLK				110
+#define CAM_CC_TFE_2_BAYER_CLK					111
+#define CAM_CC_TFE_2_BAYER_FAST_AHB_CLK				112
+#define CAM_CC_TFE_2_CLK_SRC					113
+#define CAM_CC_TFE_2_MAIN_CLK					114
+#define CAM_CC_TFE_2_MAIN_FAST_AHB_CLK				115
+#define CAM_CC_TRACENOC_TPDM_1_CMB_CLK				116
+#define CAM_CC_XO_CLK_SRC					117
+
+/* CAM_CC power domains */
+#define CAM_CC_IPE_0_GDSC					0
+#define CAM_CC_OFE_GDSC						1
+#define CAM_CC_TFE_0_GDSC					2
+#define CAM_CC_TFE_1_GDSC					3
+#define CAM_CC_TFE_2_GDSC					4
+#define CAM_CC_TITAN_TOP_GDSC					5
+
+/* CAM_CC resets */
+#define CAM_CC_DRV_BCR						0
+#define CAM_CC_ICP_BCR						1
+#define CAM_CC_IPE_0_BCR					2
+#define CAM_CC_OFE_BCR						3
+#define CAM_CC_QDSS_DEBUG_BCR					4
+#define CAM_CC_TFE_0_BCR					5
+#define CAM_CC_TFE_1_BCR					6
+#define CAM_CC_TFE_2_BCR					7
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,kaanapali-dispcc.h b/include/dt-bindings/clock/qcom,kaanapali-dispcc.h
new file mode 100644
index 00000000000..05146f9dfe0
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,kaanapali-dispcc.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_KAANAPALI_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_KAANAPALI_H
+
+/* DISP_CC clocks */
+#define DISP_CC_ESYNC0_CLK					0
+#define DISP_CC_ESYNC0_CLK_SRC					1
+#define DISP_CC_ESYNC1_CLK					2
+#define DISP_CC_ESYNC1_CLK_SRC					3
+#define DISP_CC_MDSS_ACCU_SHIFT_CLK				4
+#define DISP_CC_MDSS_AHB1_CLK					5
+#define DISP_CC_MDSS_AHB_CLK					6
+#define DISP_CC_MDSS_AHB_CLK_SRC				7
+#define DISP_CC_MDSS_AHB_SWI_CLK				8
+#define DISP_CC_MDSS_AHB_SWI_DIV_CLK_SRC			9
+#define DISP_CC_MDSS_BYTE0_CLK					10
+#define DISP_CC_MDSS_BYTE0_CLK_SRC				11
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				12
+#define DISP_CC_MDSS_BYTE0_INTF_CLK				13
+#define DISP_CC_MDSS_BYTE1_CLK					14
+#define DISP_CC_MDSS_BYTE1_CLK_SRC				15
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				16
+#define DISP_CC_MDSS_BYTE1_INTF_CLK				17
+#define DISP_CC_MDSS_DPTX0_AUX_CLK				18
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC				19
+#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK				20
+#define DISP_CC_MDSS_DPTX0_LINK_CLK				21
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC				22
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC			23
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK			24
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK				25
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC			26
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK				27
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC			28
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK		29
+#define DISP_CC_MDSS_DPTX1_AUX_CLK				30
+#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC				31
+#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK				32
+#define DISP_CC_MDSS_DPTX1_LINK_CLK				33
+#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC				34
+#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC			35
+#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK			36
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK				37
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC			38
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK				39
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC			40
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK		41
+#define DISP_CC_MDSS_DPTX2_AUX_CLK				42
+#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC				43
+#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK				44
+#define DISP_CC_MDSS_DPTX2_LINK_CLK				45
+#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC				46
+#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC			47
+#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK			48
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK				49
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC			50
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK				51
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC			52
+#define DISP_CC_MDSS_DPTX3_AUX_CLK				53
+#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC				54
+#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK				55
+#define DISP_CC_MDSS_DPTX3_LINK_CLK				56
+#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC				57
+#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC			58
+#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK			59
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK				60
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC			61
+#define DISP_CC_MDSS_ESC0_CLK					62
+#define DISP_CC_MDSS_ESC0_CLK_SRC				63
+#define DISP_CC_MDSS_ESC1_CLK					64
+#define DISP_CC_MDSS_ESC1_CLK_SRC				65
+#define DISP_CC_MDSS_MDP1_CLK					66
+#define DISP_CC_MDSS_MDP_CLK					67
+#define DISP_CC_MDSS_MDP_CLK_SRC				68
+#define DISP_CC_MDSS_MDP_LUT1_CLK				69
+#define DISP_CC_MDSS_MDP_LUT_CLK				70
+#define DISP_CC_MDSS_MDP_SS_IP_CLK				71
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				72
+#define DISP_CC_MDSS_PCLK0_CLK					73
+#define DISP_CC_MDSS_PCLK0_CLK_SRC				74
+#define DISP_CC_MDSS_PCLK1_CLK					75
+#define DISP_CC_MDSS_PCLK1_CLK_SRC				76
+#define DISP_CC_MDSS_PCLK2_CLK					77
+#define DISP_CC_MDSS_PCLK2_CLK_SRC				78
+#define DISP_CC_MDSS_VSYNC1_CLK					79
+#define DISP_CC_MDSS_VSYNC_CLK					80
+#define DISP_CC_MDSS_VSYNC_CLK_SRC				81
+#define DISP_CC_OSC_CLK						82
+#define DISP_CC_OSC_CLK_SRC					83
+#define DISP_CC_PLL0						84
+#define DISP_CC_PLL1						85
+#define DISP_CC_PLL2						86
+#define DISP_CC_SLEEP_CLK					87
+#define DISP_CC_XO_CLK						88
+
+/* DISP_CC power domains */
+#define DISP_CC_MDSS_CORE_GDSC					0
+#define DISP_CC_MDSS_CORE_INT2_GDSC				1
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR					0
+#define DISP_CC_MDSS_CORE_INT2_BCR				1
+#define DISP_CC_MDSS_RSCC_BCR					2
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,kaanapali-gpucc.h b/include/dt-bindings/clock/qcom,kaanapali-gpucc.h
new file mode 100644
index 00000000000..e8dc2009c71
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,kaanapali-gpucc.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_KAANAPALI_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_KAANAPALI_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK						0
+#define GPU_CC_CB_CLK						1
+#define GPU_CC_CX_ACCU_SHIFT_CLK				2
+#define GPU_CC_CX_GMU_CLK					3
+#define GPU_CC_CXO_AON_CLK					4
+#define GPU_CC_CXO_CLK						5
+#define GPU_CC_DEMET_CLK					6
+#define GPU_CC_DPM_CLK						7
+#define GPU_CC_FF_CLK_SRC					8
+#define GPU_CC_FREQ_MEASURE_CLK					9
+#define GPU_CC_GMU_CLK_SRC					10
+#define GPU_CC_GPU_SMMU_VOTE_CLK				11
+#define GPU_CC_GX_ACCU_SHIFT_CLK				12
+#define GPU_CC_GX_GMU_CLK					13
+#define GPU_CC_HUB_AON_CLK					14
+#define GPU_CC_HUB_CLK_SRC					15
+#define GPU_CC_HUB_CX_INT_CLK					16
+#define GPU_CC_HUB_DIV_CLK_SRC					17
+#define GPU_CC_MEMNOC_GFX_CLK					18
+#define GPU_CC_PLL0						19
+#define GPU_CC_PLL0_OUT_EVEN					20
+#define GPU_CC_RSCC_HUB_AON_CLK					21
+#define GPU_CC_RSCC_XO_AON_CLK					22
+#define GPU_CC_SLEEP_CLK					23
+
+/* GPU_CC power domains */
+#define GPU_CC_CX_GDSC						0
+
+/* GPU_CC resets */
+#define GPU_CC_CB_BCR						0
+#define GPU_CC_CX_BCR						1
+#define GPU_CC_FAST_HUB_BCR					2
+#define GPU_CC_FF_BCR						3
+#define GPU_CC_GMU_BCR						4
+#define GPU_CC_GX_BCR						5
+#define GPU_CC_XO_BCR						6
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h b/include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h
new file mode 100644
index 00000000000..f32dade67cf
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GX_CLKCTL_KAANAPALI_H
+#define _DT_BINDINGS_CLK_QCOM_GX_CLKCTL_KAANAPALI_H
+
+/* GX_CLKCTL power domains */
+#define GX_CLKCTL_GX_GDSC				0
+#define GX_CLKCTL_GX_SLICE_GDSC				1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,kaanapali-videocc.h b/include/dt-bindings/clock/qcom,kaanapali-videocc.h
new file mode 100644
index 00000000000..cc0d41b895c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,kaanapali-videocc.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_KAANAPALI_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_KAANAPALI_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_AHB_CLK					0
+#define VIDEO_CC_AHB_CLK_SRC					1
+#define VIDEO_CC_MVS0_CLK					2
+#define VIDEO_CC_MVS0_CLK_SRC					3
+#define VIDEO_CC_MVS0_FREERUN_CLK				4
+#define VIDEO_CC_MVS0_SHIFT_CLK					5
+#define VIDEO_CC_MVS0_VPP0_CLK					6
+#define VIDEO_CC_MVS0_VPP0_FREERUN_CLK				7
+#define VIDEO_CC_MVS0_VPP1_CLK					8
+#define VIDEO_CC_MVS0_VPP1_FREERUN_CLK				9
+#define VIDEO_CC_MVS0A_CLK					10
+#define VIDEO_CC_MVS0A_CLK_SRC					11
+#define VIDEO_CC_MVS0A_FREERUN_CLK				12
+#define VIDEO_CC_MVS0B_CLK					13
+#define VIDEO_CC_MVS0B_CLK_SRC					14
+#define VIDEO_CC_MVS0B_FREERUN_CLK				15
+#define VIDEO_CC_MVS0C_CLK					16
+#define VIDEO_CC_MVS0C_CLK_SRC					17
+#define VIDEO_CC_MVS0C_FREERUN_CLK				18
+#define VIDEO_CC_MVS0C_SHIFT_CLK				19
+#define VIDEO_CC_PLL0						20
+#define VIDEO_CC_PLL1						21
+#define VIDEO_CC_PLL2						22
+#define VIDEO_CC_PLL3						23
+#define VIDEO_CC_SLEEP_CLK					24
+#define VIDEO_CC_TS_XO_CLK					25
+#define VIDEO_CC_XO_CLK						26
+#define VIDEO_CC_XO_CLK_SRC					27
+
+/* VIDEO_CC power domains */
+#define VIDEO_CC_MVS0A_GDSC					0
+#define VIDEO_CC_MVS0_GDSC					1
+#define VIDEO_CC_MVS0_VPP1_GDSC					2
+#define VIDEO_CC_MVS0_VPP0_GDSC					3
+#define VIDEO_CC_MVS0C_GDSC					4
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_INTERFACE_BCR					0
+#define VIDEO_CC_MVS0_BCR					1
+#define VIDEO_CC_MVS0_VPP0_BCR					2
+#define VIDEO_CC_MVS0_VPP1_BCR					3
+#define VIDEO_CC_MVS0A_BCR					4
+#define VIDEO_CC_MVS0C_CLK_ARES					5
+#define VIDEO_CC_MVS0C_BCR					6
+#define VIDEO_CC_MVS0_FREERUN_CLK_ARES				7
+#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES				8
+#define VIDEO_CC_XO_CLK_ARES					9
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,mss-sc7180.h b/include/dt-bindings/clock/qcom,mss-sc7180.h
deleted file mode 100644
index f15a9ded296..00000000000
--- a/include/dt-bindings/clock/qcom,mss-sc7180.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
- */
-
-#ifndef _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H
-#define _DT_BINDINGS_CLK_QCOM_MSS_SC7180_H
-
-#define MSS_AXI_CRYPTO_CLK	0
-#define MSS_AXI_NAV_CLK		1
-
-#endif
diff --git a/include/dt-bindings/clock/qcom,sm8750-cambistmclkcc.h b/include/dt-bindings/clock/qcom,sm8750-cambistmclkcc.h
new file mode 100644
index 00000000000..51615bee307
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8750-cambistmclkcc.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_SM8750_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_BIST_MCLK_CC_SM8750_H
+
+/* CAM_BIST_MCLK_CC clocks */
+#define CAM_BIST_MCLK_CC_MCLK0_CLK				0
+#define CAM_BIST_MCLK_CC_MCLK0_CLK_SRC				1
+#define CAM_BIST_MCLK_CC_MCLK1_CLK				2
+#define CAM_BIST_MCLK_CC_MCLK1_CLK_SRC				3
+#define CAM_BIST_MCLK_CC_MCLK2_CLK				4
+#define CAM_BIST_MCLK_CC_MCLK2_CLK_SRC				5
+#define CAM_BIST_MCLK_CC_MCLK3_CLK				6
+#define CAM_BIST_MCLK_CC_MCLK3_CLK_SRC				7
+#define CAM_BIST_MCLK_CC_MCLK4_CLK				8
+#define CAM_BIST_MCLK_CC_MCLK4_CLK_SRC				9
+#define CAM_BIST_MCLK_CC_MCLK5_CLK				10
+#define CAM_BIST_MCLK_CC_MCLK5_CLK_SRC				11
+#define CAM_BIST_MCLK_CC_MCLK6_CLK				12
+#define CAM_BIST_MCLK_CC_MCLK6_CLK_SRC				13
+#define CAM_BIST_MCLK_CC_MCLK7_CLK				14
+#define CAM_BIST_MCLK_CC_MCLK7_CLK_SRC				15
+#define CAM_BIST_MCLK_CC_PLL0					16
+#define CAM_BIST_MCLK_CC_SLEEP_CLK				17
+#define CAM_BIST_MCLK_CC_SLEEP_CLK_SRC				18
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,sm8750-camcc.h b/include/dt-bindings/clock/qcom,sm8750-camcc.h
new file mode 100644
index 00000000000..dae788247af
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8750-camcc.h
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8750_H
+#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8750_H
+
+/* CAM_CC clocks */
+#define CAM_CC_CAM_TOP_AHB_CLK					0
+#define CAM_CC_CAM_TOP_FAST_AHB_CLK				1
+#define CAM_CC_CAMNOC_DCD_XO_CLK				2
+#define CAM_CC_CAMNOC_NRT_AXI_CLK				3
+#define CAM_CC_CAMNOC_NRT_CRE_CLK				4
+#define CAM_CC_CAMNOC_NRT_IPE_NPS_CLK				5
+#define CAM_CC_CAMNOC_NRT_OFE_ANCHOR_CLK			6
+#define CAM_CC_CAMNOC_NRT_OFE_HDR_CLK				7
+#define CAM_CC_CAMNOC_NRT_OFE_MAIN_CLK				8
+#define CAM_CC_CAMNOC_RT_AXI_CLK				9
+#define CAM_CC_CAMNOC_RT_AXI_CLK_SRC				10
+#define CAM_CC_CAMNOC_RT_IFE_LITE_CLK				11
+#define CAM_CC_CAMNOC_RT_TFE_0_BAYER_CLK			12
+#define CAM_CC_CAMNOC_RT_TFE_0_MAIN_CLK				13
+#define CAM_CC_CAMNOC_RT_TFE_1_BAYER_CLK			14
+#define CAM_CC_CAMNOC_RT_TFE_1_MAIN_CLK				15
+#define CAM_CC_CAMNOC_RT_TFE_2_BAYER_CLK			16
+#define CAM_CC_CAMNOC_RT_TFE_2_MAIN_CLK				17
+#define CAM_CC_CAMNOC_XO_CLK					18
+#define CAM_CC_CCI_0_CLK					19
+#define CAM_CC_CCI_0_CLK_SRC					20
+#define CAM_CC_CCI_1_CLK					21
+#define CAM_CC_CCI_1_CLK_SRC					22
+#define CAM_CC_CCI_2_CLK					23
+#define CAM_CC_CCI_2_CLK_SRC					24
+#define CAM_CC_CORE_AHB_CLK					25
+#define CAM_CC_CPHY_RX_CLK_SRC					26
+#define CAM_CC_CRE_AHB_CLK					27
+#define CAM_CC_CRE_CLK						28
+#define CAM_CC_CRE_CLK_SRC					29
+#define CAM_CC_CSI0PHYTIMER_CLK					30
+#define CAM_CC_CSI0PHYTIMER_CLK_SRC				31
+#define CAM_CC_CSI1PHYTIMER_CLK					32
+#define CAM_CC_CSI1PHYTIMER_CLK_SRC				33
+#define CAM_CC_CSI2PHYTIMER_CLK					34
+#define CAM_CC_CSI2PHYTIMER_CLK_SRC				35
+#define CAM_CC_CSI3PHYTIMER_CLK					36
+#define CAM_CC_CSI3PHYTIMER_CLK_SRC				37
+#define CAM_CC_CSI4PHYTIMER_CLK					38
+#define CAM_CC_CSI4PHYTIMER_CLK_SRC				39
+#define CAM_CC_CSI5PHYTIMER_CLK					40
+#define CAM_CC_CSI5PHYTIMER_CLK_SRC				41
+#define CAM_CC_CSID_CLK						42
+#define CAM_CC_CSID_CLK_SRC					43
+#define CAM_CC_CSID_CSIPHY_RX_CLK				44
+#define CAM_CC_CSIPHY0_CLK					45
+#define CAM_CC_CSIPHY1_CLK					46
+#define CAM_CC_CSIPHY2_CLK					47
+#define CAM_CC_CSIPHY3_CLK					48
+#define CAM_CC_CSIPHY4_CLK					49
+#define CAM_CC_CSIPHY5_CLK					50
+#define CAM_CC_DRV_AHB_CLK					51
+#define CAM_CC_DRV_XO_CLK					52
+#define CAM_CC_FAST_AHB_CLK_SRC					53
+#define CAM_CC_GDSC_CLK						54
+#define CAM_CC_ICP_0_AHB_CLK					55
+#define CAM_CC_ICP_0_CLK					56
+#define CAM_CC_ICP_0_CLK_SRC					57
+#define CAM_CC_ICP_1_AHB_CLK					58
+#define CAM_CC_ICP_1_CLK					59
+#define CAM_CC_ICP_1_CLK_SRC					60
+#define CAM_CC_IFE_LITE_AHB_CLK					61
+#define CAM_CC_IFE_LITE_CLK					62
+#define CAM_CC_IFE_LITE_CLK_SRC					63
+#define CAM_CC_IFE_LITE_CPHY_RX_CLK				64
+#define CAM_CC_IFE_LITE_CSID_CLK				65
+#define CAM_CC_IFE_LITE_CSID_CLK_SRC				66
+#define CAM_CC_IPE_NPS_AHB_CLK					67
+#define CAM_CC_IPE_NPS_CLK					68
+#define CAM_CC_IPE_NPS_CLK_SRC					69
+#define CAM_CC_IPE_NPS_FAST_AHB_CLK				70
+#define CAM_CC_IPE_PPS_CLK					71
+#define CAM_CC_IPE_PPS_FAST_AHB_CLK				72
+#define CAM_CC_JPEG_0_CLK					73
+#define CAM_CC_JPEG_1_CLK					74
+#define CAM_CC_JPEG_CLK_SRC					75
+#define CAM_CC_OFE_AHB_CLK					76
+#define CAM_CC_OFE_ANCHOR_CLK					77
+#define CAM_CC_OFE_ANCHOR_FAST_AHB_CLK				78
+#define CAM_CC_OFE_CLK_SRC					79
+#define CAM_CC_OFE_HDR_CLK					80
+#define CAM_CC_OFE_HDR_FAST_AHB_CLK				81
+#define CAM_CC_OFE_MAIN_CLK					82
+#define CAM_CC_OFE_MAIN_FAST_AHB_CLK				83
+#define CAM_CC_PLL0						84
+#define CAM_CC_PLL0_OUT_EVEN					85
+#define CAM_CC_PLL0_OUT_ODD					86
+#define CAM_CC_PLL1						87
+#define CAM_CC_PLL1_OUT_EVEN					88
+#define CAM_CC_PLL2						89
+#define CAM_CC_PLL2_OUT_EVEN					90
+#define CAM_CC_PLL3						91
+#define CAM_CC_PLL3_OUT_EVEN					92
+#define CAM_CC_PLL4						93
+#define CAM_CC_PLL4_OUT_EVEN					94
+#define CAM_CC_PLL5						95
+#define CAM_CC_PLL5_OUT_EVEN					96
+#define CAM_CC_PLL6						97
+#define CAM_CC_PLL6_OUT_EVEN					98
+#define CAM_CC_PLL6_OUT_ODD					99
+#define CAM_CC_QDSS_DEBUG_CLK					100
+#define CAM_CC_QDSS_DEBUG_CLK_SRC				101
+#define CAM_CC_QDSS_DEBUG_XO_CLK				102
+#define CAM_CC_SLEEP_CLK					103
+#define CAM_CC_SLEEP_CLK_SRC					104
+#define CAM_CC_SLOW_AHB_CLK_SRC					105
+#define CAM_CC_TFE_0_BAYER_CLK					106
+#define CAM_CC_TFE_0_BAYER_FAST_AHB_CLK				107
+#define CAM_CC_TFE_0_CLK_SRC					108
+#define CAM_CC_TFE_0_MAIN_CLK					109
+#define CAM_CC_TFE_0_MAIN_FAST_AHB_CLK				110
+#define CAM_CC_TFE_1_BAYER_CLK					111
+#define CAM_CC_TFE_1_BAYER_FAST_AHB_CLK				112
+#define CAM_CC_TFE_1_CLK_SRC					113
+#define CAM_CC_TFE_1_MAIN_CLK					114
+#define CAM_CC_TFE_1_MAIN_FAST_AHB_CLK				115
+#define CAM_CC_TFE_2_BAYER_CLK					116
+#define CAM_CC_TFE_2_BAYER_FAST_AHB_CLK				117
+#define CAM_CC_TFE_2_CLK_SRC					118
+#define CAM_CC_TFE_2_MAIN_CLK					119
+#define CAM_CC_TFE_2_MAIN_FAST_AHB_CLK				120
+#define CAM_CC_XO_CLK_SRC					121
+
+/* CAM_CC power domains */
+#define CAM_CC_TITAN_TOP_GDSC					0
+#define CAM_CC_IPE_0_GDSC					1
+#define CAM_CC_OFE_GDSC						2
+#define CAM_CC_TFE_0_GDSC					3
+#define CAM_CC_TFE_1_GDSC					4
+#define CAM_CC_TFE_2_GDSC					5
+
+/* CAM_CC resets */
+#define CAM_CC_DRV_BCR						0
+#define CAM_CC_ICP_BCR						1
+#define CAM_CC_IPE_0_BCR					2
+#define CAM_CC_OFE_BCR						3
+#define CAM_CC_QDSS_DEBUG_BCR					4
+#define CAM_CC_TFE_0_BCR					5
+#define CAM_CC_TFE_1_BCR					6
+#define CAM_CC_TFE_2_BCR					7
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,x1e80100-gcc.h b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
index 62aa1242559..d905804e646 100644
--- a/include/dt-bindings/clock/qcom,x1e80100-gcc.h
+++ b/include/dt-bindings/clock/qcom,x1e80100-gcc.h
@@ -387,6 +387,9 @@
 #define GCC_USB4_2_PHY_RX0_CLK_SRC				377
 #define GCC_USB4_2_PHY_RX1_CLK_SRC				378
 #define GCC_USB4_2_PHY_SYS_CLK_SRC				379
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC				380
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC				381
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC				382
 
 /* GCC power domains */
 #define GCC_PCIE_0_TUNNEL_GDSC					0
diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
index 2a805e06487..c4863e44445 100644
--- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h
@@ -31,5 +31,8 @@
 #define R9A09G077_ETCLKC		19
 #define R9A09G077_ETCLKD		20
 #define R9A09G077_ETCLKE		21
+#define R9A09G077_XSPI_CLK0		22
+#define R9A09G077_XSPI_CLK1		23
+#define R9A09G077_PCLKCAN		24
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */
diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
index 09da0ad33be..0d53f1e6507 100644
--- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
+++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h
@@ -31,5 +31,8 @@
 #define R9A09G087_ETCLKC		19
 #define R9A09G087_ETCLKD		20
 #define R9A09G087_ETCLKE		21
+#define R9A09G087_XSPI_CLK0		22
+#define R9A09G087_XSPI_CLK1		23
+#define R9A09G087_PCLKCAN		24
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */
diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h
index 970d05167fc..06dec27a8c7 100644
--- a/include/dt-bindings/clock/samsung,exynosautov920.h
+++ b/include/dt-bindings/clock/samsung,exynosautov920.h
@@ -305,4 +305,8 @@
 #define CLK_MOUT_MFC_WFD_USER           2
 #define CLK_DOUT_MFC_NOCP               3
 
+/* CMU_MFD */
+#define CLK_MOUT_MFD_NOC_USER           1
+#define CLK_DOUT_MFD_NOCP               2
+
 #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */
diff --git a/include/dt-bindings/clock/spacemit,k3-clocks.h b/include/dt-bindings/clock/spacemit,k3-clocks.h
new file mode 100644
index 00000000000..b22336f3ae4
--- /dev/null
+++ b/include/dt-bindings/clock/spacemit,k3-clocks.h
@@ -0,0 +1,390 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_
+#define _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_
+
+/* APBS (PLL) clocks */
+#define CLK_PLL1                 0
+#define CLK_PLL2                 1
+#define CLK_PLL3                 2
+#define CLK_PLL4                 3
+#define CLK_PLL5                 4
+#define CLK_PLL6                 5
+#define CLK_PLL7                 6
+#define CLK_PLL8                 7
+#define CLK_PLL1_D2              8
+#define CLK_PLL1_D3              9
+#define CLK_PLL1_D4              10
+#define CLK_PLL1_D5              11
+#define CLK_PLL1_D6              12
+#define CLK_PLL1_D7              13
+#define CLK_PLL1_D8              14
+#define CLK_PLL1_DX              15
+#define CLK_PLL1_D64             16
+#define CLK_PLL1_D10_AUD         17
+#define CLK_PLL1_D100_AUD        18
+#define CLK_PLL2_D1              19
+#define CLK_PLL2_D2              20
+#define CLK_PLL2_D3              21
+#define CLK_PLL2_D4              22
+#define CLK_PLL2_D5              23
+#define CLK_PLL2_D6              24
+#define CLK_PLL2_D7              25
+#define CLK_PLL2_D8              26
+#define CLK_PLL2_66              27
+#define CLK_PLL2_33              28
+#define CLK_PLL2_50              29
+#define CLK_PLL2_25              30
+#define CLK_PLL2_20              31
+#define CLK_PLL2_D24_125         32
+#define CLK_PLL2_D120_25         33
+#define CLK_PLL3_D1              34
+#define CLK_PLL3_D2              35
+#define CLK_PLL3_D3              36
+#define CLK_PLL3_D4              37
+#define CLK_PLL3_D5              38
+#define CLK_PLL3_D6              39
+#define CLK_PLL3_D7              40
+#define CLK_PLL3_D8              41
+#define CLK_PLL4_D1              42
+#define CLK_PLL4_D2              43
+#define CLK_PLL4_D3              44
+#define CLK_PLL4_D4              45
+#define CLK_PLL4_D5              46
+#define CLK_PLL4_D6              47
+#define CLK_PLL4_D7              48
+#define CLK_PLL4_D8              49
+#define CLK_PLL5_D1              50
+#define CLK_PLL5_D2              51
+#define CLK_PLL5_D3              52
+#define CLK_PLL5_D4              53
+#define CLK_PLL5_D5              54
+#define CLK_PLL5_D6              55
+#define CLK_PLL5_D7              56
+#define CLK_PLL5_D8              57
+#define CLK_PLL6_D1              58
+#define CLK_PLL6_D2              59
+#define CLK_PLL6_D3              60
+#define CLK_PLL6_D4              61
+#define CLK_PLL6_D5              62
+#define CLK_PLL6_D6              63
+#define CLK_PLL6_D7              64
+#define CLK_PLL6_D8              65
+#define CLK_PLL6_80              66
+#define CLK_PLL6_40              67
+#define CLK_PLL6_20              68
+#define CLK_PLL7_D1              69
+#define CLK_PLL7_D2              70
+#define CLK_PLL7_D3              71
+#define CLK_PLL7_D4              72
+#define CLK_PLL7_D5              73
+#define CLK_PLL7_D6              74
+#define CLK_PLL7_D7              75
+#define CLK_PLL7_D8              76
+#define CLK_PLL8_D1              77
+#define CLK_PLL8_D2              78
+#define CLK_PLL8_D3              79
+#define CLK_PLL8_D4              80
+#define CLK_PLL8_D5              81
+#define CLK_PLL8_D6              82
+#define CLK_PLL8_D7              83
+#define CLK_PLL8_D8              84
+
+/* MPMU clocks */
+#define CLK_MPMU_PLL1_307P2      0
+#define CLK_MPMU_PLL1_76P8       1
+#define CLK_MPMU_PLL1_61P44      2
+#define CLK_MPMU_PLL1_153P6      3
+#define CLK_MPMU_PLL1_102P4      4
+#define CLK_MPMU_PLL1_51P2       5
+#define CLK_MPMU_PLL1_51P2_AP    6
+#define CLK_MPMU_PLL1_57P6       7
+#define CLK_MPMU_PLL1_25P6       8
+#define CLK_MPMU_PLL1_12P8       9
+#define CLK_MPMU_PLL1_12P8_WDT   10
+#define CLK_MPMU_PLL1_6P4        11
+#define CLK_MPMU_PLL1_3P2        12
+#define CLK_MPMU_PLL1_1P6        13
+#define CLK_MPMU_PLL1_0P8        14
+#define CLK_MPMU_PLL1_409P6      15
+#define CLK_MPMU_PLL1_204P8      16
+#define CLK_MPMU_PLL1_491        17
+#define CLK_MPMU_PLL1_245P76     18
+#define CLK_MPMU_PLL1_614        19
+#define CLK_MPMU_PLL1_47P26      20
+#define CLK_MPMU_PLL1_31P5       21
+#define CLK_MPMU_PLL1_819        22
+#define CLK_MPMU_PLL1_1228       23
+#define CLK_MPMU_APB             24
+#define CLK_MPMU_SLOW_UART       25
+#define CLK_MPMU_SLOW_UART1      26
+#define CLK_MPMU_SLOW_UART2      27
+#define CLK_MPMU_WDT             28
+#define CLK_MPMU_WDT_BUS         29
+#define CLK_MPMU_RIPC            30
+#define CLK_MPMU_I2S_153P6       31
+#define CLK_MPMU_I2S_153P6_BASE  32
+#define CLK_MPMU_I2S_SYSCLK_SRC  33
+#define CLK_MPMU_I2S1_SYSCLK     34
+#define CLK_MPMU_I2S_BCLK        35
+#define CLK_MPMU_I2S0_SYSCLK_SEL 36
+#define CLK_MPMU_I2S2_SYSCLK_SEL 37
+#define CLK_MPMU_I2S3_SYSCLK_SEL 38
+#define CLK_MPMU_I2S4_SYSCLK_SEL 39
+#define CLK_MPMU_I2S5_SYSCLK_SEL 40
+#define CLK_MPMU_I2S0_SYSCLK_DIV 41
+#define CLK_MPMU_I2S2_SYSCLK_DIV 42
+#define CLK_MPMU_I2S3_SYSCLK_DIV 43
+#define CLK_MPMU_I2S4_SYSCLK_DIV 44
+#define CLK_MPMU_I2S5_SYSCLK_DIV 45
+#define CLK_MPMU_I2S0_SYSCLK     46
+#define CLK_MPMU_I2S2_SYSCLK     47
+#define CLK_MPMU_I2S3_SYSCLK     48
+#define CLK_MPMU_I2S4_SYSCLK     49
+#define CLK_MPMU_I2S5_SYSCLK     50
+
+/* APBC clocks */
+#define CLK_APBC_UART0           0
+#define CLK_APBC_UART2           1
+#define CLK_APBC_UART3           2
+#define CLK_APBC_UART4           3
+#define CLK_APBC_UART5           4
+#define CLK_APBC_UART6           5
+#define CLK_APBC_UART7           6
+#define CLK_APBC_UART8           7
+#define CLK_APBC_UART9           8
+#define CLK_APBC_UART10          9
+#define CLK_APBC_UART0_BUS       10
+#define CLK_APBC_UART2_BUS       11
+#define CLK_APBC_UART3_BUS       12
+#define CLK_APBC_UART4_BUS       13
+#define CLK_APBC_UART5_BUS       14
+#define CLK_APBC_UART6_BUS       15
+#define CLK_APBC_UART7_BUS       16
+#define CLK_APBC_UART8_BUS       17
+#define CLK_APBC_UART9_BUS       18
+#define CLK_APBC_UART10_BUS      19
+#define CLK_APBC_GPIO            20
+#define CLK_APBC_GPIO_BUS        21
+#define CLK_APBC_PWM0            22
+#define CLK_APBC_PWM1            23
+#define CLK_APBC_PWM2            24
+#define CLK_APBC_PWM3            25
+#define CLK_APBC_PWM4            26
+#define CLK_APBC_PWM5            27
+#define CLK_APBC_PWM6            28
+#define CLK_APBC_PWM7            29
+#define CLK_APBC_PWM8            30
+#define CLK_APBC_PWM9            31
+#define CLK_APBC_PWM10           32
+#define CLK_APBC_PWM11           33
+#define CLK_APBC_PWM12           34
+#define CLK_APBC_PWM13           35
+#define CLK_APBC_PWM14           36
+#define CLK_APBC_PWM15           37
+#define CLK_APBC_PWM16           38
+#define CLK_APBC_PWM17           39
+#define CLK_APBC_PWM18           40
+#define CLK_APBC_PWM19           41
+#define CLK_APBC_PWM0_BUS        42
+#define CLK_APBC_PWM1_BUS        43
+#define CLK_APBC_PWM2_BUS        44
+#define CLK_APBC_PWM3_BUS        45
+#define CLK_APBC_PWM4_BUS        46
+#define CLK_APBC_PWM5_BUS        47
+#define CLK_APBC_PWM6_BUS        48
+#define CLK_APBC_PWM7_BUS        49
+#define CLK_APBC_PWM8_BUS        50
+#define CLK_APBC_PWM9_BUS        51
+#define CLK_APBC_PWM10_BUS       52
+#define CLK_APBC_PWM11_BUS       53
+#define CLK_APBC_PWM12_BUS       54
+#define CLK_APBC_PWM13_BUS       55
+#define CLK_APBC_PWM14_BUS       56
+#define CLK_APBC_PWM15_BUS       57
+#define CLK_APBC_PWM16_BUS       58
+#define CLK_APBC_PWM17_BUS       59
+#define CLK_APBC_PWM18_BUS       60
+#define CLK_APBC_PWM19_BUS       61
+#define CLK_APBC_SPI0_I2S_BCLK   62
+#define CLK_APBC_SPI1_I2S_BCLK   63
+#define CLK_APBC_SPI3_I2S_BCLK   64
+#define CLK_APBC_SPI0            65
+#define CLK_APBC_SPI1            66
+#define CLK_APBC_SPI3            67
+#define CLK_APBC_SPI0_BUS        68
+#define CLK_APBC_SPI1_BUS        69
+#define CLK_APBC_SPI3_BUS        70
+#define CLK_APBC_RTC             71
+#define CLK_APBC_RTC_BUS         72
+#define CLK_APBC_TWSI0           73
+#define CLK_APBC_TWSI1           74
+#define CLK_APBC_TWSI2           75
+#define CLK_APBC_TWSI4           76
+#define CLK_APBC_TWSI5           77
+#define CLK_APBC_TWSI6           78
+#define CLK_APBC_TWSI8           79
+#define CLK_APBC_TWSI0_BUS       80
+#define CLK_APBC_TWSI1_BUS       81
+#define CLK_APBC_TWSI2_BUS       82
+#define CLK_APBC_TWSI4_BUS       83
+#define CLK_APBC_TWSI5_BUS       84
+#define CLK_APBC_TWSI6_BUS       85
+#define CLK_APBC_TWSI8_BUS       86
+#define CLK_APBC_TIMERS0         87
+#define CLK_APBC_TIMERS1         88
+#define CLK_APBC_TIMERS2         89
+#define CLK_APBC_TIMERS3         90
+#define CLK_APBC_TIMERS4         91
+#define CLK_APBC_TIMERS5         92
+#define CLK_APBC_TIMERS6         93
+#define CLK_APBC_TIMERS7         94
+#define CLK_APBC_TIMERS0_BUS     95
+#define CLK_APBC_TIMERS1_BUS     96
+#define CLK_APBC_TIMERS2_BUS     97
+#define CLK_APBC_TIMERS3_BUS     98
+#define CLK_APBC_TIMERS4_BUS     99
+#define CLK_APBC_TIMERS5_BUS     100
+#define CLK_APBC_TIMERS6_BUS     101
+#define CLK_APBC_TIMERS7_BUS     102
+#define CLK_APBC_AIB             103
+#define CLK_APBC_AIB_BUS         104
+#define CLK_APBC_ONEWIRE         105
+#define CLK_APBC_ONEWIRE_BUS     106
+#define CLK_APBC_I2S0_BCLK       107
+#define CLK_APBC_I2S1_BCLK       108
+#define CLK_APBC_I2S2_BCLK       109
+#define CLK_APBC_I2S3_BCLK       110
+#define CLK_APBC_I2S4_BCLK       111
+#define CLK_APBC_I2S5_BCLK       112
+#define CLK_APBC_I2S0            113
+#define CLK_APBC_I2S1            114
+#define CLK_APBC_I2S2            115
+#define CLK_APBC_I2S3            116
+#define CLK_APBC_I2S4            117
+#define CLK_APBC_I2S5            118
+#define CLK_APBC_I2S0_BUS        119
+#define CLK_APBC_I2S1_BUS        120
+#define CLK_APBC_I2S2_BUS        121
+#define CLK_APBC_I2S3_BUS        122
+#define CLK_APBC_I2S4_BUS        123
+#define CLK_APBC_I2S5_BUS        124
+#define CLK_APBC_DRO             125
+#define CLK_APBC_IR0             126
+#define CLK_APBC_IR1             127
+#define CLK_APBC_TSEN            128
+#define CLK_APBC_TSEN_BUS        129
+#define CLK_APBC_IPC_AP2RCPU      130
+#define CLK_APBC_IPC_AP2RCPU_BUS  131
+#define CLK_APBC_CAN0            132
+#define CLK_APBC_CAN1            133
+#define CLK_APBC_CAN2            134
+#define CLK_APBC_CAN3            135
+#define CLK_APBC_CAN4            136
+#define CLK_APBC_CAN0_BUS        137
+#define CLK_APBC_CAN1_BUS        138
+#define CLK_APBC_CAN2_BUS        139
+#define CLK_APBC_CAN3_BUS        140
+#define CLK_APBC_CAN4_BUS        141
+
+/* APMU clocks */
+#define CLK_APMU_AXICLK          0
+#define CLK_APMU_CCI550          1
+#define CLK_APMU_CPU_C0_CORE     2
+#define CLK_APMU_CPU_C1_CORE     3
+#define CLK_APMU_CPU_C2_CORE     4
+#define CLK_APMU_CPU_C3_CORE     5
+#define CLK_APMU_CCIC2PHY        6
+#define CLK_APMU_CCIC3PHY        7
+#define CLK_APMU_CSI             8
+#define CLK_APMU_ISP_BUS         9
+#define CLK_APMU_D1P_1228P8      10
+#define CLK_APMU_D1P_819P2       11
+#define CLK_APMU_D1P_614P4       12
+#define CLK_APMU_D1P_491P52      13
+#define CLK_APMU_D1P_409P6       14
+#define CLK_APMU_D1P_307P2       15
+#define CLK_APMU_D1P_245P76      16
+#define CLK_APMU_V2D             17
+#define CLK_APMU_DSI_ESC         18
+#define CLK_APMU_LCD_HCLK        19
+#define CLK_APMU_LCD_DSC         20
+#define CLK_APMU_LCD_PXCLK       21
+#define CLK_APMU_LCD_MCLK        22
+#define CLK_APMU_CCIC_4X         23
+#define CLK_APMU_CCIC1PHY        24
+#define CLK_APMU_SC2_HCLK        25
+#define CLK_APMU_SDH_AXI         26
+#define CLK_APMU_SDH0            27
+#define CLK_APMU_SDH1            28
+#define CLK_APMU_SDH2            29
+#define CLK_APMU_USB2_BUS        30
+#define CLK_APMU_USB3_PORTA_BUS  31
+#define CLK_APMU_USB3_PORTB_BUS  32
+#define CLK_APMU_USB3_PORTC_BUS  33
+#define CLK_APMU_USB3_PORTD_BUS  34
+#define CLK_APMU_QSPI            35
+#define CLK_APMU_QSPI_BUS        36
+#define CLK_APMU_DMA             37
+#define CLK_APMU_AES_WTM         38
+#define CLK_APMU_VPU             39
+#define CLK_APMU_DTC             40
+#define CLK_APMU_GPU             41
+#define CLK_APMU_MC_AHB          42
+#define CLK_APMU_TOP_DCLK        43
+#define CLK_APMU_UCIE            44
+#define CLK_APMU_UCIE_SBCLK      45
+#define CLK_APMU_RCPU            46
+#define CLK_APMU_DSI4LN2_DSI_ESC 47
+#define CLK_APMU_DSI4LN2_LCD_DSC 48
+#define CLK_APMU_DSI4LN2_LCD_PXCLK 49
+#define CLK_APMU_DSI4LN2_LCD_MCLK 50
+#define CLK_APMU_DSI4LN2_DPU_ACLK 51
+#define CLK_APMU_DPU_ACLK        52
+#define CLK_APMU_UFS_ACLK        53
+#define CLK_APMU_EDP0_PXCLK      54
+#define CLK_APMU_EDP1_PXCLK      55
+#define CLK_APMU_PCIE_PORTA_MSTE 56
+#define CLK_APMU_PCIE_PORTA_SLV  57
+#define CLK_APMU_PCIE_PORTB_MSTE 58
+#define CLK_APMU_PCIE_PORTB_SLV  59
+#define CLK_APMU_PCIE_PORTC_MSTE 60
+#define CLK_APMU_PCIE_PORTC_SLV  61
+#define CLK_APMU_PCIE_PORTD_MSTE 62
+#define CLK_APMU_PCIE_PORTD_SLV  63
+#define CLK_APMU_PCIE_PORTE_MSTE 64
+#define CLK_APMU_PCIE_PORTE_SLV  65
+#define CLK_APMU_EMAC0_BUS       66
+#define CLK_APMU_EMAC0_REF       67
+#define CLK_APMU_EMAC0_1588      68
+#define CLK_APMU_EMAC0_RGMII_TX  69
+#define CLK_APMU_EMAC1_BUS       70
+#define CLK_APMU_EMAC1_REF       71
+#define CLK_APMU_EMAC1_1588      72
+#define CLK_APMU_EMAC1_RGMII_TX  73
+#define CLK_APMU_EMAC2_BUS       74
+#define CLK_APMU_EMAC2_REF       75
+#define CLK_APMU_EMAC2_1588      76
+#define CLK_APMU_EMAC2_RGMII_TX  77
+#define CLK_APMU_ESPI_SCLK_SRC   78
+#define CLK_APMU_ESPI_SCLK       79
+#define CLK_APMU_ESPI_MCLK       80
+#define CLK_APMU_CAM_SRC1        81
+#define CLK_APMU_CAM_SRC2        82
+#define CLK_APMU_CAM_SRC3        83
+#define CLK_APMU_CAM_SRC4        84
+#define CLK_APMU_ISIM_VCLK0      85
+#define CLK_APMU_ISIM_VCLK1      86
+#define CLK_APMU_ISIM_VCLK2      87
+#define CLK_APMU_ISIM_VCLK3      88
+
+/* DCIU clocks */
+#define CLK_DCIU_HDMA            0
+#define CLK_DCIU_DMA350          1
+#define CLK_DCIU_C2_TCM_PIPE     2
+#define CLK_DCIU_C3_TCM_PIPE     3
+
+#endif /* _DT_BINDINGS_CLOCK_SPACEMIT_K3_CLOCKS_H_ */
diff --git a/include/dt-bindings/clock/thead,th1520-clk-ap.h b/include/dt-bindings/clock/thead,th1520-clk-ap.h
index 09a9aa7b3ab..68b35cc6120 100644
--- a/include/dt-bindings/clock/thead,th1520-clk-ap.h
+++ b/include/dt-bindings/clock/thead,th1520-clk-ap.h
@@ -93,6 +93,7 @@
 #define CLK_SRAM3		83
 #define CLK_PLL_GMAC_100M	84
 #define CLK_UART_SCLK		85
+#define CLK_C910_BUS		86
 
 /* VO clocks */
 #define CLK_AXI4_VO_ACLK		0
diff --git a/include/dt-bindings/clock/xlnx-versal-clk.h b/include/dt-bindings/clock/xlnx-versal-clk.h
deleted file mode 100644
index 264d634d226..00000000000
--- a/include/dt-bindings/clock/xlnx-versal-clk.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- *  Copyright (C) 2019 Xilinx Inc.
- *
- */
-
-#ifndef _DT_BINDINGS_CLK_VERSAL_H
-#define _DT_BINDINGS_CLK_VERSAL_H
-
-#define PMC_PLL					1
-#define APU_PLL					2
-#define RPU_PLL					3
-#define CPM_PLL					4
-#define NOC_PLL					5
-#define PLL_MAX					6
-#define PMC_PRESRC				7
-#define PMC_POSTCLK				8
-#define PMC_PLL_OUT				9
-#define PPLL					10
-#define NOC_PRESRC				11
-#define NOC_POSTCLK				12
-#define NOC_PLL_OUT				13
-#define NPLL					14
-#define APU_PRESRC				15
-#define APU_POSTCLK				16
-#define APU_PLL_OUT				17
-#define APLL					18
-#define RPU_PRESRC				19
-#define RPU_POSTCLK				20
-#define RPU_PLL_OUT				21
-#define RPLL					22
-#define CPM_PRESRC				23
-#define CPM_POSTCLK				24
-#define CPM_PLL_OUT				25
-#define CPLL					26
-#define PPLL_TO_XPD				27
-#define NPLL_TO_XPD				28
-#define APLL_TO_XPD				29
-#define RPLL_TO_XPD				30
-#define EFUSE_REF				31
-#define SYSMON_REF				32
-#define IRO_SUSPEND_REF				33
-#define USB_SUSPEND				34
-#define SWITCH_TIMEOUT				35
-#define RCLK_PMC				36
-#define RCLK_LPD				37
-#define WDT					38
-#define TTC0					39
-#define TTC1					40
-#define TTC2					41
-#define TTC3					42
-#define GEM_TSU					43
-#define GEM_TSU_LB				44
-#define MUXED_IRO_DIV2				45
-#define MUXED_IRO_DIV4				46
-#define PSM_REF					47
-#define GEM0_RX					48
-#define GEM0_TX					49
-#define GEM1_RX					50
-#define GEM1_TX					51
-#define CPM_CORE_REF				52
-#define CPM_LSBUS_REF				53
-#define CPM_DBG_REF				54
-#define CPM_AUX0_REF				55
-#define CPM_AUX1_REF				56
-#define QSPI_REF				57
-#define OSPI_REF				58
-#define SDIO0_REF				59
-#define SDIO1_REF				60
-#define PMC_LSBUS_REF				61
-#define I2C_REF					62
-#define TEST_PATTERN_REF			63
-#define DFT_OSC_REF				64
-#define PMC_PL0_REF				65
-#define PMC_PL1_REF				66
-#define PMC_PL2_REF				67
-#define PMC_PL3_REF				68
-#define CFU_REF					69
-#define SPARE_REF				70
-#define NPI_REF					71
-#define HSM0_REF				72
-#define HSM1_REF				73
-#define SD_DLL_REF				74
-#define FPD_TOP_SWITCH				75
-#define FPD_LSBUS				76
-#define ACPU					77
-#define DBG_TRACE				78
-#define DBG_FPD					79
-#define LPD_TOP_SWITCH				80
-#define ADMA					81
-#define LPD_LSBUS				82
-#define CPU_R5					83
-#define CPU_R5_CORE				84
-#define CPU_R5_OCM				85
-#define CPU_R5_OCM2				86
-#define IOU_SWITCH				87
-#define GEM0_REF				88
-#define GEM1_REF				89
-#define GEM_TSU_REF				90
-#define USB0_BUS_REF				91
-#define UART0_REF				92
-#define UART1_REF				93
-#define SPI0_REF				94
-#define SPI1_REF				95
-#define CAN0_REF				96
-#define CAN1_REF				97
-#define I2C0_REF				98
-#define I2C1_REF				99
-#define DBG_LPD					100
-#define TIMESTAMP_REF				101
-#define DBG_TSTMP				102
-#define CPM_TOPSW_REF				103
-#define USB3_DUAL_REF				104
-#define OUTCLK_MAX				105
-#define REF_CLK					106
-#define PL_ALT_REF_CLK				107
-#define MUXED_IRO				108
-#define PL_EXT					109
-#define PL_LB					110
-#define MIO_50_OR_51				111
-#define MIO_24_OR_25				112
-
-#endif
diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h
deleted file mode 100644
index f0f7ddd3dcb..00000000000
--- a/include/dt-bindings/clock/xlnx-zynqmp-clk.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Xilinx Zynq MPSoC Firmware layer
- *
- *  Copyright (C) 2014-2018 Xilinx, Inc.
- *
- */
-
-#ifndef _DT_BINDINGS_CLK_ZYNQMP_H
-#define _DT_BINDINGS_CLK_ZYNQMP_H
-
-/*
- * These bindings are deprecated, because they do not match the actual
- * concept of bindings but rather contain pure firmware values.
- * Instead include the header in the DTS source directory.
- */
-#warning "These bindings are deprecated. Instead use the header in the DTS source directory."
-
-#define IOPLL			0
-#define RPLL			1
-#define APLL			2
-#define DPLL			3
-#define VPLL			4
-#define IOPLL_TO_FPD		5
-#define RPLL_TO_FPD		6
-#define APLL_TO_LPD		7
-#define DPLL_TO_LPD		8
-#define VPLL_TO_LPD		9
-#define ACPU			10
-#define ACPU_HALF		11
-#define DBF_FPD			12
-#define DBF_LPD			13
-#define DBG_TRACE		14
-#define DBG_TSTMP		15
-#define DP_VIDEO_REF		16
-#define DP_AUDIO_REF		17
-#define DP_STC_REF		18
-#define GDMA_REF		19
-#define DPDMA_REF		20
-#define DDR_REF			21
-#define SATA_REF		22
-#define PCIE_REF		23
-#define GPU_REF			24
-#define GPU_PP0_REF		25
-#define GPU_PP1_REF		26
-#define TOPSW_MAIN		27
-#define TOPSW_LSBUS		28
-#define GTGREF0_REF		29
-#define LPD_SWITCH		30
-#define LPD_LSBUS		31
-#define USB0_BUS_REF		32
-#define USB1_BUS_REF		33
-#define USB3_DUAL_REF		34
-#define USB0			35
-#define USB1			36
-#define CPU_R5			37
-#define CPU_R5_CORE		38
-#define CSU_SPB			39
-#define CSU_PLL			40
-#define PCAP			41
-#define IOU_SWITCH		42
-#define GEM_TSU_REF		43
-#define GEM_TSU			44
-#define GEM0_TX			45
-#define GEM1_TX			46
-#define GEM2_TX			47
-#define GEM3_TX			48
-#define GEM0_RX			49
-#define GEM1_RX			50
-#define GEM2_RX			51
-#define GEM3_RX			52
-#define QSPI_REF		53
-#define SDIO0_REF		54
-#define SDIO1_REF		55
-#define UART0_REF		56
-#define UART1_REF		57
-#define SPI0_REF		58
-#define SPI1_REF		59
-#define NAND_REF		60
-#define I2C0_REF		61
-#define I2C1_REF		62
-#define CAN0_REF		63
-#define CAN1_REF		64
-#define CAN0			65
-#define CAN1			66
-#define DLL_REF			67
-#define ADMA_REF		68
-#define TIMESTAMP_REF		69
-#define AMS_REF			70
-#define PL0_REF			71
-#define PL1_REF			72
-#define PL2_REF			73
-#define PL3_REF			74
-#define WDT			75
-#define IOPLL_INT		76
-#define IOPLL_PRE_SRC		77
-#define IOPLL_HALF		78
-#define IOPLL_INT_MUX		79
-#define IOPLL_POST_SRC		80
-#define RPLL_INT		81
-#define RPLL_PRE_SRC		82
-#define RPLL_HALF		83
-#define RPLL_INT_MUX		84
-#define RPLL_POST_SRC		85
-#define APLL_INT		86
-#define APLL_PRE_SRC		87
-#define APLL_HALF		88
-#define APLL_INT_MUX		89
-#define APLL_POST_SRC		90
-#define DPLL_INT		91
-#define DPLL_PRE_SRC		92
-#define DPLL_HALF		93
-#define DPLL_INT_MUX		94
-#define DPLL_POST_SRC		95
-#define VPLL_INT		96
-#define VPLL_PRE_SRC		97
-#define VPLL_HALF		98
-#define VPLL_INT_MUX		99
-#define VPLL_POST_SRC		100
-#define CAN0_MIO		101
-#define CAN1_MIO		102
-#define ACPU_FULL		103
-#define GEM0_REF		104
-#define GEM1_REF		105
-#define GEM2_REF		106
-#define GEM3_REF		107
-#define GEM0_REF_UNG		108
-#define GEM1_REF_UNG		109
-#define GEM2_REF_UNG		110
-#define GEM3_REF_UNG		111
-#define LPD_WDT			112
-
-#endif
diff --git a/include/dt-bindings/dma/jz4775-dma.h b/include/dt-bindings/dma/jz4775-dma.h
deleted file mode 100644
index 8d27e2c69dc..00000000000
--- a/include/dt-bindings/dma/jz4775-dma.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * This header provides macros for JZ4775 DMA bindings.
- *
- * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
- */
-
-#ifndef __DT_BINDINGS_DMA_JZ4775_DMA_H__
-#define __DT_BINDINGS_DMA_JZ4775_DMA_H__
-
-/*
- * Request type numbers for the JZ4775 DMA controller (written to the DRTn
- * register for the channel).
- */
-#define JZ4775_DMA_I2S0_TX	0x6
-#define JZ4775_DMA_I2S0_RX	0x7
-#define JZ4775_DMA_AUTO		0x8
-#define JZ4775_DMA_SADC_RX	0x9
-#define JZ4775_DMA_UART3_TX	0x0e
-#define JZ4775_DMA_UART3_RX	0x0f
-#define JZ4775_DMA_UART2_TX	0x10
-#define JZ4775_DMA_UART2_RX	0x11
-#define JZ4775_DMA_UART1_TX	0x12
-#define JZ4775_DMA_UART1_RX	0x13
-#define JZ4775_DMA_UART0_TX	0x14
-#define JZ4775_DMA_UART0_RX	0x15
-#define JZ4775_DMA_SSI0_TX	0x16
-#define JZ4775_DMA_SSI0_RX	0x17
-#define JZ4775_DMA_MSC0_TX	0x1a
-#define JZ4775_DMA_MSC0_RX	0x1b
-#define JZ4775_DMA_MSC1_TX	0x1c
-#define JZ4775_DMA_MSC1_RX	0x1d
-#define JZ4775_DMA_MSC2_TX	0x1e
-#define JZ4775_DMA_MSC2_RX	0x1f
-#define JZ4775_DMA_PCM0_TX	0x20
-#define JZ4775_DMA_PCM0_RX	0x21
-#define JZ4775_DMA_SMB0_TX	0x24
-#define JZ4775_DMA_SMB0_RX	0x25
-#define JZ4775_DMA_SMB1_TX	0x26
-#define JZ4775_DMA_SMB1_RX	0x27
-#define JZ4775_DMA_SMB2_TX	0x28
-#define JZ4775_DMA_SMB2_RX	0x29
-
-#endif /* __DT_BINDINGS_DMA_JZ4775_DMA_H__ */
diff --git a/include/dt-bindings/dma/x2000-dma.h b/include/dt-bindings/dma/x2000-dma.h
deleted file mode 100644
index db2cd4830b0..00000000000
--- a/include/dt-bindings/dma/x2000-dma.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * This header provides macros for X2000 DMA bindings.
- *
- * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
- */
-
-#ifndef __DT_BINDINGS_DMA_X2000_DMA_H__
-#define __DT_BINDINGS_DMA_X2000_DMA_H__
-
-/*
- * Request type numbers for the X2000 DMA controller (written to the DRTn
- * register for the channel).
- */
-#define X2000_DMA_AUTO		0x8
-#define X2000_DMA_UART5_TX	0xa
-#define X2000_DMA_UART5_RX	0xb
-#define X2000_DMA_UART4_TX	0xc
-#define X2000_DMA_UART4_RX	0xd
-#define X2000_DMA_UART3_TX	0xe
-#define X2000_DMA_UART3_RX	0xf
-#define X2000_DMA_UART2_TX	0x10
-#define X2000_DMA_UART2_RX	0x11
-#define X2000_DMA_UART1_TX	0x12
-#define X2000_DMA_UART1_RX	0x13
-#define X2000_DMA_UART0_TX	0x14
-#define X2000_DMA_UART0_RX	0x15
-#define X2000_DMA_SSI0_TX	0x16
-#define X2000_DMA_SSI0_RX	0x17
-#define X2000_DMA_SSI1_TX	0x18
-#define X2000_DMA_SSI1_RX	0x19
-#define X2000_DMA_I2C0_TX	0x24
-#define X2000_DMA_I2C0_RX	0x25
-#define X2000_DMA_I2C1_TX	0x26
-#define X2000_DMA_I2C1_RX	0x27
-#define X2000_DMA_I2C2_TX	0x28
-#define X2000_DMA_I2C2_RX	0x29
-#define X2000_DMA_I2C3_TX	0x2a
-#define X2000_DMA_I2C3_RX	0x2b
-#define X2000_DMA_I2C4_TX	0x2c
-#define X2000_DMA_I2C4_RX	0x2d
-#define X2000_DMA_I2C5_TX	0x2e
-#define X2000_DMA_I2C5_RX	0x2f
-#define X2000_DMA_UART6_TX	0x30
-#define X2000_DMA_UART6_RX	0x31
-#define X2000_DMA_UART7_TX	0x32
-#define X2000_DMA_UART7_RX	0x33
-#define X2000_DMA_UART8_TX	0x34
-#define X2000_DMA_UART8_RX	0x35
-#define X2000_DMA_UART9_TX	0x36
-#define X2000_DMA_UART9_RX	0x37
-#define X2000_DMA_SADC_RX	0x38
-
-#endif /* __DT_BINDINGS_DMA_X2000_DMA_H__ */
diff --git a/include/dt-bindings/gce/mt6779-gce.h b/include/dt-bindings/gce/mt6779-gce.h
deleted file mode 100644
index 06101316ace..00000000000
--- a/include/dt-bindings/gce/mt6779-gce.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019 MediaTek Inc.
- * Author: Dennis-YC Hsieh <dennis-yc.hsieh@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_GCE_MT6779_H
-#define _DT_BINDINGS_GCE_MT6779_H
-
-#define CMDQ_NO_TIMEOUT		0xffffffff
-
-/* GCE HW thread priority */
-#define CMDQ_THR_PRIO_LOWEST	0
-#define CMDQ_THR_PRIO_1		1
-#define CMDQ_THR_PRIO_2		2
-#define CMDQ_THR_PRIO_3		3
-#define CMDQ_THR_PRIO_4		4
-#define CMDQ_THR_PRIO_5		5
-#define CMDQ_THR_PRIO_6		6
-#define CMDQ_THR_PRIO_HIGHEST	7
-
-/* GCE subsys table */
-#define SUBSYS_1300XXXX		0
-#define SUBSYS_1400XXXX		1
-#define SUBSYS_1401XXXX		2
-#define SUBSYS_1402XXXX		3
-#define SUBSYS_1502XXXX		4
-#define SUBSYS_1880XXXX		5
-#define SUBSYS_1881XXXX		6
-#define SUBSYS_1882XXXX		7
-#define SUBSYS_1883XXXX		8
-#define SUBSYS_1884XXXX		9
-#define SUBSYS_1000XXXX		10
-#define SUBSYS_1001XXXX		11
-#define SUBSYS_1002XXXX		12
-#define SUBSYS_1003XXXX		13
-#define SUBSYS_1004XXXX		14
-#define SUBSYS_1005XXXX		15
-#define SUBSYS_1020XXXX		16
-#define SUBSYS_1028XXXX		17
-#define SUBSYS_1700XXXX		18
-#define SUBSYS_1701XXXX		19
-#define SUBSYS_1702XXXX		20
-#define SUBSYS_1703XXXX		21
-#define SUBSYS_1800XXXX		22
-#define SUBSYS_1801XXXX		23
-#define SUBSYS_1802XXXX		24
-#define SUBSYS_1804XXXX		25
-#define SUBSYS_1805XXXX		26
-#define SUBSYS_1808XXXX		27
-#define SUBSYS_180aXXXX		28
-#define SUBSYS_180bXXXX		29
-#define CMDQ_SUBSYS_OFF		32
-
-/* GCE hardware events */
-#define CMDQ_EVENT_DISP_RDMA0_SOF		0
-#define CMDQ_EVENT_DISP_RDMA1_SOF		1
-#define CMDQ_EVENT_MDP_RDMA0_SOF		2
-#define CMDQ_EVENT_MDP_RDMA1_SOF		3
-#define CMDQ_EVENT_MDP_RSZ0_SOF			4
-#define CMDQ_EVENT_MDP_RSZ1_SOF			5
-#define CMDQ_EVENT_MDP_TDSHP_SOF		6
-#define CMDQ_EVENT_MDP_WROT0_SOF		7
-#define CMDQ_EVENT_MDP_WROT1_SOF		8
-#define CMDQ_EVENT_DISP_OVL0_SOF		9
-#define CMDQ_EVENT_DISP_2L_OVL0_SOF		10
-#define CMDQ_EVENT_DISP_2L_OVL1_SOF		11
-#define CMDQ_EVENT_DISP_WDMA0_SOF		12
-#define CMDQ_EVENT_DISP_COLOR0_SOF		13
-#define CMDQ_EVENT_DISP_CCORR0_SOF		14
-#define CMDQ_EVENT_DISP_AAL0_SOF		15
-#define CMDQ_EVENT_DISP_GAMMA0_SOF		16
-#define CMDQ_EVENT_DISP_DITHER0_SOF		17
-#define CMDQ_EVENT_DISP_PWM0_SOF		18
-#define CMDQ_EVENT_DISP_DSI0_SOF		19
-#define CMDQ_EVENT_DISP_DPI0_SOF		20
-#define CMDQ_EVENT_DISP_POSTMASK0_SOF		21
-#define CMDQ_EVENT_DISP_RSZ0_SOF		22
-#define CMDQ_EVENT_MDP_AAL_SOF			23
-#define CMDQ_EVENT_MDP_CCORR_SOF		24
-#define CMDQ_EVENT_DISP_DBI0_SOF		25
-#define CMDQ_EVENT_ISP_RELAY_SOF		26
-#define CMDQ_EVENT_IPU_RELAY_SOF		27
-#define CMDQ_EVENT_DISP_RDMA0_EOF		28
-#define CMDQ_EVENT_DISP_RDMA1_EOF		29
-#define CMDQ_EVENT_MDP_RDMA0_EOF		30
-#define CMDQ_EVENT_MDP_RDMA1_EOF		31
-#define CMDQ_EVENT_MDP_RSZ0_EOF			32
-#define CMDQ_EVENT_MDP_RSZ1_EOF			33
-#define CMDQ_EVENT_MDP_TDSHP_EOF		34
-#define CMDQ_EVENT_MDP_WROT0_W_EOF		35
-#define CMDQ_EVENT_MDP_WROT1_W_EOF		36
-#define CMDQ_EVENT_DISP_OVL0_EOF		37
-#define CMDQ_EVENT_DISP_2L_OVL0_EOF		38
-#define CMDQ_EVENT_DISP_2L_OVL1_EOF		39
-#define CMDQ_EVENT_DISP_WDMA0_EOF		40
-#define CMDQ_EVENT_DISP_COLOR0_EOF		41
-#define CMDQ_EVENT_DISP_CCORR0_EOF		42
-#define CMDQ_EVENT_DISP_AAL0_EOF		43
-#define CMDQ_EVENT_DISP_GAMMA0_EOF		44
-#define CMDQ_EVENT_DISP_DITHER0_EOF		45
-#define CMDQ_EVENT_DISP_DSI0_EOF		46
-#define CMDQ_EVENT_DISP_DPI0_EOF		47
-#define CMDQ_EVENT_DISP_RSZ0_EOF		49
-#define CMDQ_EVENT_MDP_AAL_FRAME_DONE		50
-#define CMDQ_EVENT_MDP_CCORR_FRAME_DONE		51
-#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE	52
-#define CMDQ_EVENT_MUTEX0_STREAM_EOF		130
-#define CMDQ_EVENT_MUTEX1_STREAM_EOF		131
-#define CMDQ_EVENT_MUTEX2_STREAM_EOF		132
-#define CMDQ_EVENT_MUTEX3_STREAM_EOF		133
-#define CMDQ_EVENT_MUTEX4_STREAM_EOF		134
-#define CMDQ_EVENT_MUTEX5_STREAM_EOF		135
-#define CMDQ_EVENT_MUTEX6_STREAM_EOF		136
-#define CMDQ_EVENT_MUTEX7_STREAM_EOF		137
-#define CMDQ_EVENT_MUTEX8_STREAM_EOF		138
-#define CMDQ_EVENT_MUTEX9_STREAM_EOF		139
-#define CMDQ_EVENT_MUTEX10_STREAM_EOF		140
-#define CMDQ_EVENT_MUTEX11_STREAM_EOF		141
-#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN		142
-#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN		143
-#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN		144
-#define CMDQ_EVENT_DISP_RDMA3_UNDERRUN		145
-#define CMDQ_EVENT_DSI0_TE			146
-#define CMDQ_EVENT_DSI0_IRQ_EVENT		147
-#define CMDQ_EVENT_DSI0_DONE_EVENT		148
-#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE	150
-#define CMDQ_EVENT_DISP_WDMA0_RST_DONE		151
-#define CMDQ_EVENT_MDP_WROT0_RST_DONE		153
-#define CMDQ_EVENT_MDP_RDMA0_RST_DONE		154
-#define CMDQ_EVENT_DISP_OVL0_RST_DONE		155
-#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE	156
-#define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE	157
-#define CMDQ_EVENT_DIP_CQ_THREAD0_EOF		257
-#define CMDQ_EVENT_DIP_CQ_THREAD1_EOF		258
-#define CMDQ_EVENT_DIP_CQ_THREAD2_EOF		259
-#define CMDQ_EVENT_DIP_CQ_THREAD3_EOF		260
-#define CMDQ_EVENT_DIP_CQ_THREAD4_EOF		261
-#define CMDQ_EVENT_DIP_CQ_THREAD5_EOF		262
-#define CMDQ_EVENT_DIP_CQ_THREAD6_EOF		263
-#define CMDQ_EVENT_DIP_CQ_THREAD7_EOF		264
-#define CMDQ_EVENT_DIP_CQ_THREAD8_EOF		265
-#define CMDQ_EVENT_DIP_CQ_THREAD9_EOF		266
-#define CMDQ_EVENT_DIP_CQ_THREAD10_EOF		267
-#define CMDQ_EVENT_DIP_CQ_THREAD11_EOF		268
-#define CMDQ_EVENT_DIP_CQ_THREAD12_EOF		269
-#define CMDQ_EVENT_DIP_CQ_THREAD13_EOF		270
-#define CMDQ_EVENT_DIP_CQ_THREAD14_EOF		271
-#define CMDQ_EVENT_DIP_CQ_THREAD15_EOF		272
-#define CMDQ_EVENT_DIP_CQ_THREAD16_EOF		273
-#define CMDQ_EVENT_DIP_CQ_THREAD17_EOF		274
-#define CMDQ_EVENT_DIP_CQ_THREAD18_EOF		275
-#define CMDQ_EVENT_DIP_DMA_ERR_EVENT		276
-#define CMDQ_EVENT_AMD_FRAME_DONE		277
-#define CMDQ_EVENT_MFB_DONE			278
-#define CMDQ_EVENT_WPE_A_EOF			279
-#define CMDQ_EVENT_VENC_EOF			289
-#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE		290
-#define CMDQ_EVENT_JPEG_ENC_EOF			291
-#define CMDQ_EVENT_VENC_MB_DONE			292
-#define CMDQ_EVENT_VENC_128BYTE_CNT_DONE	293
-#define CMDQ_EVENT_ISP_FRAME_DONE_A		321
-#define CMDQ_EVENT_ISP_FRAME_DONE_B		322
-#define CMDQ_EVENT_ISP_FRAME_DONE_C		323
-#define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE	324
-#define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE	325
-#define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE	326
-#define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE	327
-#define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE	328
-#define CMDQ_EVENT_ISP_TSF_DONE			329
-#define CMDQ_EVENT_SENINF_0_FIFO_FULL		330
-#define CMDQ_EVENT_SENINF_1_FIFO_FULL		331
-#define CMDQ_EVENT_SENINF_2_FIFO_FULL		332
-#define CMDQ_EVENT_SENINF_3_FIFO_FULL		333
-#define CMDQ_EVENT_SENINF_4_FIFO_FULL		334
-#define CMDQ_EVENT_SENINF_5_FIFO_FULL		335
-#define CMDQ_EVENT_SENINF_6_FIFO_FULL		336
-#define CMDQ_EVENT_SENINF_7_FIFO_FULL		337
-#define CMDQ_EVENT_TG_OVRUN_A_INT_DLY		338
-#define CMDQ_EVENT_TG_OVRUN_B_INT_DLY		339
-#define CMDQ_EVENT_TG_OVRUN_C_INT		340
-#define CMDQ_EVENT_TG_GRABERR_A_INT_DLY		341
-#define CMDQ_EVENT_TG_GRABERR_B_INT_DLY		342
-#define CMDQ_EVENT_TG_GRABERR_C_INT		343
-#define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY		344
-#define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY		345
-#define CMDQ_EVENT_CQ_VR_SNAP_C_INT		346
-#define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY	347
-#define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY	348
-#define CMDQ_EVENT_DMA_R1_ERROR_C_INT		349
-#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0	353
-#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1	354
-#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2	355
-#define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3	356
-#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0	385
-#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1	386
-#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2	387
-#define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3	388
-#define CMDQ_EVENT_VDEC_EVENT_0			416
-#define CMDQ_EVENT_VDEC_EVENT_1			417
-#define CMDQ_EVENT_VDEC_EVENT_2			418
-#define CMDQ_EVENT_VDEC_EVENT_3			419
-#define CMDQ_EVENT_VDEC_EVENT_4			420
-#define CMDQ_EVENT_VDEC_EVENT_5			421
-#define CMDQ_EVENT_VDEC_EVENT_6			422
-#define CMDQ_EVENT_VDEC_EVENT_7			423
-#define CMDQ_EVENT_VDEC_EVENT_8			424
-#define CMDQ_EVENT_VDEC_EVENT_9			425
-#define CMDQ_EVENT_VDEC_EVENT_10		426
-#define CMDQ_EVENT_VDEC_EVENT_11		427
-#define CMDQ_EVENT_VDEC_EVENT_12		428
-#define CMDQ_EVENT_VDEC_EVENT_13		429
-#define CMDQ_EVENT_VDEC_EVENT_14		430
-#define CMDQ_EVENT_VDEC_EVENT_15		431
-#define CMDQ_EVENT_FDVT_DONE			449
-#define CMDQ_EVENT_FE_DONE			450
-#define CMDQ_EVENT_RSC_EOF			451
-#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT		452
-#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT		453
-#define CMDQ_EVENT_DSI0_TE_INFRA		898
-
-#endif
diff --git a/include/dt-bindings/gpio/nvidia,tegra264-gpio.h b/include/dt-bindings/gpio/nvidia,tegra264-gpio.h
new file mode 100644
index 00000000000..25fb66f9710
--- /dev/null
+++ b/include/dt-bindings/gpio/nvidia,tegra264-gpio.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */
+
+/*
+ * This header provides constants for binding nvidia,tegra264-gpio*.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA264_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA264_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA264_MAIN_GPIO_PORT_T  0
+#define TEGRA264_MAIN_GPIO_PORT_U  1
+#define TEGRA264_MAIN_GPIO_PORT_V  2
+#define TEGRA264_MAIN_GPIO_PORT_W  3
+#define TEGRA264_MAIN_GPIO_PORT_AL 4
+#define TEGRA264_MAIN_GPIO_PORT_Y  5
+#define TEGRA264_MAIN_GPIO_PORT_Z  6
+#define TEGRA264_MAIN_GPIO_PORT_X  7
+#define TEGRA264_MAIN_GPIO_PORT_H  8
+#define TEGRA264_MAIN_GPIO_PORT_J  9
+#define TEGRA264_MAIN_GPIO_PORT_K  10
+#define TEGRA264_MAIN_GPIO_PORT_L  11
+#define TEGRA264_MAIN_GPIO_PORT_M  12
+#define TEGRA264_MAIN_GPIO_PORT_P  13
+#define TEGRA264_MAIN_GPIO_PORT_Q  14
+#define TEGRA264_MAIN_GPIO_PORT_R  15
+#define TEGRA264_MAIN_GPIO_PORT_S  16
+#define TEGRA264_MAIN_GPIO_PORT_F  17
+#define TEGRA264_MAIN_GPIO_PORT_G  18
+
+#define TEGRA264_MAIN_GPIO(port, offset) \
+	((TEGRA264_MAIN_GPIO_PORT_##port * 8) + (offset))
+
+/* GPIOs implemented by AON GPIO controller */
+#define TEGRA264_AON_GPIO_PORT_AA  0
+#define TEGRA264_AON_GPIO_PORT_BB  1
+#define TEGRA264_AON_GPIO_PORT_CC  2
+#define TEGRA264_AON_GPIO_PORT_DD  3
+#define TEGRA264_AON_GPIO_PORT_EE  4
+
+#define TEGRA264_AON_GPIO(port, offset) \
+	((TEGRA264_AON_GPIO_PORT_##port * 8) + (offset))
+
+#define TEGRA264_UPHY_GPIO_PORT_A  0
+#define TEGRA264_UPHY_GPIO_PORT_B  1
+#define TEGRA264_UPHY_GPIO_PORT_C  2
+#define TEGRA264_UPHY_GPIO_PORT_D  3
+#define TEGRA264_UPHY_GPIO_PORT_E  4
+
+#define TEGRA264_UPHY_GPIO(port, offset) \
+	((TEGRA264_UPHY_GPIO_PORT_##port * 8) + (offset))
+
+#endif
diff --git a/include/dt-bindings/input/linux-event-codes.h b/include/dt-bindings/input/linux-event-codes.h
index 4bdb6a16598..3528168f7c6 100644
--- a/include/dt-bindings/input/linux-event-codes.h
+++ b/include/dt-bindings/input/linux-event-codes.h
@@ -643,6 +643,10 @@
 #define KEY_EPRIVACY_SCREEN_ON		0x252
 #define KEY_EPRIVACY_SCREEN_OFF		0x253
 
+#define KEY_ACTION_ON_SELECTION		0x254	/* AL Action on Selection (HUTRR119) */
+#define KEY_CONTEXTUAL_INSERT		0x255	/* AL Contextual Insertion (HUTRR119) */
+#define KEY_CONTEXTUAL_QUERY		0x256	/* AL Contextual Query (HUTRR119) */
+
 #define KEY_KBDINPUTASSIST_PREV		0x260
 #define KEY_KBDINPUTASSIST_NEXT		0x261
 #define KEY_KBDINPUTASSIST_PREVGROUP		0x262
diff --git a/include/dt-bindings/interconnect/mediatek,mt8196.h b/include/dt-bindings/interconnect/mediatek,mt8196.h
new file mode 100644
index 00000000000..de700fa7322
--- /dev/null
+++ b/include/dt-bindings/interconnect/mediatek,mt8196.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 Collabora Ltd.
+ *                    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8196_H
+#define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8196_H
+
+#define SLAVE_DDR_EMI		0
+#define MASTER_MCUSYS		1
+#define MASTER_MCU_0		2
+#define MASTER_MCU_1		3
+#define MASTER_MCU_2		4
+#define MASTER_MCU_3		5
+#define MASTER_MCU_4		6
+#define MASTER_GPUSYS		7
+#define MASTER_MMSYS		8
+#define MASTER_MM_VPU		9
+#define MASTER_MM_DISP		10
+#define MASTER_MM_VDEC		11
+#define MASTER_MM_VENC		12
+#define MASTER_MM_CAM		13
+#define MASTER_MM_IMG		14
+#define MASTER_MM_MDP		15
+#define MASTER_VPUSYS		16
+#define MASTER_VPU_0		17
+#define MASTER_VPU_1		18
+#define MASTER_MDLASYS		19
+#define MASTER_MDLA_0		20
+#define MASTER_UFS		21
+#define MASTER_PCIE		22
+#define MASTER_USB		23
+#define MASTER_WIFI		24
+#define MASTER_BT		25
+#define MASTER_NETSYS		26
+#define MASTER_DBGIF		27
+#define SLAVE_HRT_DDR_EMI	28
+#define MASTER_HRT_MMSYS	29
+#define MASTER_HRT_MM_DISP	30
+#define MASTER_HRT_MM_VDEC	31
+#define MASTER_HRT_MM_VENC	32
+#define MASTER_HRT_MM_CAM	33
+#define MASTER_HRT_MM_IMG	34
+#define MASTER_HRT_MM_MDP	35
+#define MASTER_HRT_ADSP		36
+#define MASTER_HRT_DBGIF	37
+#endif
diff --git a/include/dt-bindings/memory/mt6779-larb-port.h b/include/dt-bindings/memory/mt6779-larb-port.h
deleted file mode 100644
index 3fb438a96e3..00000000000
--- a/include/dt-bindings/memory/mt6779-larb-port.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2019 MediaTek Inc.
- * Author: Chao Hao <chao.hao@mediatek.com>
- */
-
-#ifndef _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_
-#define _DT_BINDINGS_MEMORY_MT6779_LARB_PORT_H_
-
-#include <dt-bindings/memory/mtk-memory-port.h>
-
-#define M4U_LARB0_ID			 0
-#define M4U_LARB1_ID			 1
-#define M4U_LARB2_ID			 2
-#define M4U_LARB3_ID			 3
-#define M4U_LARB4_ID			 4
-#define M4U_LARB5_ID			 5
-#define M4U_LARB6_ID			 6
-#define M4U_LARB7_ID			 7
-#define M4U_LARB8_ID			 8
-#define M4U_LARB9_ID			 9
-#define M4U_LARB10_ID			 10
-#define M4U_LARB11_ID			 11
-
-/* larb0 */
-#define M4U_PORT_DISP_POSTMASK0		 MTK_M4U_ID(M4U_LARB0_ID, 0)
-#define M4U_PORT_DISP_OVL0_HDR		 MTK_M4U_ID(M4U_LARB0_ID, 1)
-#define M4U_PORT_DISP_OVL1_HDR		 MTK_M4U_ID(M4U_LARB0_ID, 2)
-#define M4U_PORT_DISP_OVL0		 MTK_M4U_ID(M4U_LARB0_ID, 3)
-#define M4U_PORT_DISP_OVL1		 MTK_M4U_ID(M4U_LARB0_ID, 4)
-#define M4U_PORT_DISP_PVRIC0		 MTK_M4U_ID(M4U_LARB0_ID, 5)
-#define M4U_PORT_DISP_RDMA0		 MTK_M4U_ID(M4U_LARB0_ID, 6)
-#define M4U_PORT_DISP_WDMA0		 MTK_M4U_ID(M4U_LARB0_ID, 7)
-#define M4U_PORT_DISP_FAKE0		 MTK_M4U_ID(M4U_LARB0_ID, 8)
-
-/* larb1 */
-#define M4U_PORT_DISP_OVL0_2L_HDR	 MTK_M4U_ID(M4U_LARB1_ID, 0)
-#define M4U_PORT_DISP_OVL1_2L_HDR	 MTK_M4U_ID(M4U_LARB1_ID, 1)
-#define M4U_PORT_DISP_OVL0_2L		 MTK_M4U_ID(M4U_LARB1_ID, 2)
-#define M4U_PORT_DISP_OVL1_2L		 MTK_M4U_ID(M4U_LARB1_ID, 3)
-#define M4U_PORT_DISP_RDMA1		 MTK_M4U_ID(M4U_LARB1_ID, 4)
-#define M4U_PORT_MDP_PVRIC0		 MTK_M4U_ID(M4U_LARB1_ID, 5)
-#define M4U_PORT_MDP_PVRIC1		 MTK_M4U_ID(M4U_LARB1_ID, 6)
-#define M4U_PORT_MDP_RDMA0		 MTK_M4U_ID(M4U_LARB1_ID, 7)
-#define M4U_PORT_MDP_RDMA1		 MTK_M4U_ID(M4U_LARB1_ID, 8)
-#define M4U_PORT_MDP_WROT0_R		 MTK_M4U_ID(M4U_LARB1_ID, 9)
-#define M4U_PORT_MDP_WROT0_W		 MTK_M4U_ID(M4U_LARB1_ID, 10)
-#define M4U_PORT_MDP_WROT1_R		 MTK_M4U_ID(M4U_LARB1_ID, 11)
-#define M4U_PORT_MDP_WROT1_W		 MTK_M4U_ID(M4U_LARB1_ID, 12)
-#define M4U_PORT_DISP_FAKE1		 MTK_M4U_ID(M4U_LARB1_ID, 13)
-
-/* larb2-VDEC */
-#define M4U_PORT_HW_VDEC_MC_EXT          MTK_M4U_ID(M4U_LARB2_ID, 0)
-#define M4U_PORT_HW_VDEC_UFO_EXT         MTK_M4U_ID(M4U_LARB2_ID, 1)
-#define M4U_PORT_HW_VDEC_PP_EXT          MTK_M4U_ID(M4U_LARB2_ID, 2)
-#define M4U_PORT_HW_VDEC_PRED_RD_EXT     MTK_M4U_ID(M4U_LARB2_ID, 3)
-#define M4U_PORT_HW_VDEC_PRED_WR_EXT     MTK_M4U_ID(M4U_LARB2_ID, 4)
-#define M4U_PORT_HW_VDEC_PPWRAP_EXT      MTK_M4U_ID(M4U_LARB2_ID, 5)
-#define M4U_PORT_HW_VDEC_TILE_EXT        MTK_M4U_ID(M4U_LARB2_ID, 6)
-#define M4U_PORT_HW_VDEC_VLD_EXT         MTK_M4U_ID(M4U_LARB2_ID, 7)
-#define M4U_PORT_HW_VDEC_VLD2_EXT        MTK_M4U_ID(M4U_LARB2_ID, 8)
-#define M4U_PORT_HW_VDEC_AVC_MV_EXT      MTK_M4U_ID(M4U_LARB2_ID, 9)
-#define M4U_PORT_HW_VDEC_UFO_ENC_EXT     MTK_M4U_ID(M4U_LARB2_ID, 10)
-#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB2_ID, 11)
-
-/* larb3-VENC */
-#define M4U_PORT_VENC_RCPU		 MTK_M4U_ID(M4U_LARB3_ID, 0)
-#define M4U_PORT_VENC_REC		 MTK_M4U_ID(M4U_LARB3_ID, 1)
-#define M4U_PORT_VENC_BSDMA		 MTK_M4U_ID(M4U_LARB3_ID, 2)
-#define M4U_PORT_VENC_SV_COMV		 MTK_M4U_ID(M4U_LARB3_ID, 3)
-#define M4U_PORT_VENC_RD_COMV		 MTK_M4U_ID(M4U_LARB3_ID, 4)
-#define M4U_PORT_VENC_NBM_RDMA		 MTK_M4U_ID(M4U_LARB3_ID, 5)
-#define M4U_PORT_VENC_NBM_RDMA_LITE	 MTK_M4U_ID(M4U_LARB3_ID, 6)
-#define M4U_PORT_JPGENC_Y_RDMA		 MTK_M4U_ID(M4U_LARB3_ID, 7)
-#define M4U_PORT_JPGENC_C_RDMA		 MTK_M4U_ID(M4U_LARB3_ID, 8)
-#define M4U_PORT_JPGENC_Q_TABLE		 MTK_M4U_ID(M4U_LARB3_ID, 9)
-#define M4U_PORT_JPGENC_BSDMA		 MTK_M4U_ID(M4U_LARB3_ID, 10)
-#define M4U_PORT_JPGDEC_WDMA		 MTK_M4U_ID(M4U_LARB3_ID, 11)
-#define M4U_PORT_JPGDEC_BSDMA		 MTK_M4U_ID(M4U_LARB3_ID, 12)
-#define M4U_PORT_VENC_NBM_WDMA		 MTK_M4U_ID(M4U_LARB3_ID, 13)
-#define M4U_PORT_VENC_NBM_WDMA_LITE	 MTK_M4U_ID(M4U_LARB3_ID, 14)
-#define M4U_PORT_VENC_CUR_LUMA		 MTK_M4U_ID(M4U_LARB3_ID, 15)
-#define M4U_PORT_VENC_CUR_CHROMA	 MTK_M4U_ID(M4U_LARB3_ID, 16)
-#define M4U_PORT_VENC_REF_LUMA		 MTK_M4U_ID(M4U_LARB3_ID, 17)
-#define M4U_PORT_VENC_REF_CHROMA	 MTK_M4U_ID(M4U_LARB3_ID, 18)
-
-/* larb4-dummy */
-
-/* larb5-IMG */
-#define M4U_PORT_IMGI_D1		 MTK_M4U_ID(M4U_LARB5_ID, 0)
-#define M4U_PORT_IMGBI_D1		 MTK_M4U_ID(M4U_LARB5_ID, 1)
-#define M4U_PORT_DMGI_D1		 MTK_M4U_ID(M4U_LARB5_ID, 2)
-#define M4U_PORT_DEPI_D1		 MTK_M4U_ID(M4U_LARB5_ID, 3)
-#define M4U_PORT_LCEI_D1		 MTK_M4U_ID(M4U_LARB5_ID, 4)
-#define M4U_PORT_SMTI_D1		 MTK_M4U_ID(M4U_LARB5_ID, 5)
-#define M4U_PORT_SMTO_D2		 MTK_M4U_ID(M4U_LARB5_ID, 6)
-#define M4U_PORT_SMTO_D1		 MTK_M4U_ID(M4U_LARB5_ID, 7)
-#define M4U_PORT_CRZO_D1		 MTK_M4U_ID(M4U_LARB5_ID, 8)
-#define M4U_PORT_IMG3O_D1		 MTK_M4U_ID(M4U_LARB5_ID, 9)
-#define M4U_PORT_VIPI_D1		 MTK_M4U_ID(M4U_LARB5_ID, 10)
-#define M4U_PORT_WPE_RDMA1		 MTK_M4U_ID(M4U_LARB5_ID, 11)
-#define M4U_PORT_WPE_RDMA0		 MTK_M4U_ID(M4U_LARB5_ID, 12)
-#define M4U_PORT_WPE_WDMA		 MTK_M4U_ID(M4U_LARB5_ID, 13)
-#define M4U_PORT_TIMGO_D1		 MTK_M4U_ID(M4U_LARB5_ID, 14)
-#define M4U_PORT_MFB_RDMA0		 MTK_M4U_ID(M4U_LARB5_ID, 15)
-#define M4U_PORT_MFB_RDMA1		 MTK_M4U_ID(M4U_LARB5_ID, 16)
-#define M4U_PORT_MFB_RDMA2		 MTK_M4U_ID(M4U_LARB5_ID, 17)
-#define M4U_PORT_MFB_RDMA3		 MTK_M4U_ID(M4U_LARB5_ID, 18)
-#define M4U_PORT_MFB_WDMA		 MTK_M4U_ID(M4U_LARB5_ID, 19)
-#define M4U_PORT_RESERVE1		 MTK_M4U_ID(M4U_LARB5_ID, 20)
-#define M4U_PORT_RESERVE2		 MTK_M4U_ID(M4U_LARB5_ID, 21)
-#define M4U_PORT_RESERVE3		 MTK_M4U_ID(M4U_LARB5_ID, 22)
-#define M4U_PORT_RESERVE4		 MTK_M4U_ID(M4U_LARB5_ID, 23)
-#define M4U_PORT_RESERVE5		 MTK_M4U_ID(M4U_LARB5_ID, 24)
-#define M4U_PORT_RESERVE6		 MTK_M4U_ID(M4U_LARB5_ID, 25)
-
-/* larb6-IMG-VPU */
-#define M4U_PORT_IMG_IPUO		 MTK_M4U_ID(M4U_LARB6_ID, 0)
-#define M4U_PORT_IMG_IPU3O		 MTK_M4U_ID(M4U_LARB6_ID, 1)
-#define M4U_PORT_IMG_IPUI		 MTK_M4U_ID(M4U_LARB6_ID, 2)
-
-/* larb7-DVS */
-#define M4U_PORT_DVS_RDMA		 MTK_M4U_ID(M4U_LARB7_ID, 0)
-#define M4U_PORT_DVS_WDMA		 MTK_M4U_ID(M4U_LARB7_ID, 1)
-#define M4U_PORT_DVP_RDMA		 MTK_M4U_ID(M4U_LARB7_ID, 2)
-#define M4U_PORT_DVP_WDMA		 MTK_M4U_ID(M4U_LARB7_ID, 3)
-
-/* larb8-IPESYS */
-#define M4U_PORT_FDVT_RDA		 MTK_M4U_ID(M4U_LARB8_ID, 0)
-#define M4U_PORT_FDVT_RDB		 MTK_M4U_ID(M4U_LARB8_ID, 1)
-#define M4U_PORT_FDVT_WRA		 MTK_M4U_ID(M4U_LARB8_ID, 2)
-#define M4U_PORT_FDVT_WRB		 MTK_M4U_ID(M4U_LARB8_ID, 3)
-#define M4U_PORT_FE_RD0			 MTK_M4U_ID(M4U_LARB8_ID, 4)
-#define M4U_PORT_FE_RD1			 MTK_M4U_ID(M4U_LARB8_ID, 5)
-#define M4U_PORT_FE_WR0			 MTK_M4U_ID(M4U_LARB8_ID, 6)
-#define M4U_PORT_FE_WR1			 MTK_M4U_ID(M4U_LARB8_ID, 7)
-#define M4U_PORT_RSC_RDMA0		 MTK_M4U_ID(M4U_LARB8_ID, 8)
-#define M4U_PORT_RSC_WDMA		 MTK_M4U_ID(M4U_LARB8_ID, 9)
-
-/* larb9-CAM */
-#define M4U_PORT_CAM_IMGO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 0)
-#define M4U_PORT_CAM_RRZO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 1)
-#define M4U_PORT_CAM_LSCI_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 2)
-#define M4U_PORT_CAM_BPCI_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 3)
-#define M4U_PORT_CAM_YUVO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 4)
-#define M4U_PORT_CAM_UFDI_R2_C		 MTK_M4U_ID(M4U_LARB9_ID, 5)
-#define M4U_PORT_CAM_RAWI_R2_C		 MTK_M4U_ID(M4U_LARB9_ID, 6)
-#define M4U_PORT_CAM_RAWI_R5_C		 MTK_M4U_ID(M4U_LARB9_ID, 7)
-#define M4U_PORT_CAM_CAMSV_1		 MTK_M4U_ID(M4U_LARB9_ID, 8)
-#define M4U_PORT_CAM_CAMSV_2		 MTK_M4U_ID(M4U_LARB9_ID, 9)
-#define M4U_PORT_CAM_CAMSV_3		 MTK_M4U_ID(M4U_LARB9_ID, 10)
-#define M4U_PORT_CAM_CAMSV_4		 MTK_M4U_ID(M4U_LARB9_ID, 11)
-#define M4U_PORT_CAM_CAMSV_5		 MTK_M4U_ID(M4U_LARB9_ID, 12)
-#define M4U_PORT_CAM_CAMSV_6		 MTK_M4U_ID(M4U_LARB9_ID, 13)
-#define M4U_PORT_CAM_AAO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 14)
-#define M4U_PORT_CAM_AFO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 15)
-#define M4U_PORT_CAM_FLKO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 16)
-#define M4U_PORT_CAM_LCESO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 17)
-#define M4U_PORT_CAM_CRZO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 18)
-#define M4U_PORT_CAM_LTMSO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 19)
-#define M4U_PORT_CAM_RSSO_R1_C		 MTK_M4U_ID(M4U_LARB9_ID, 20)
-#define M4U_PORT_CAM_CCUI		 MTK_M4U_ID(M4U_LARB9_ID, 21)
-#define M4U_PORT_CAM_CCUO		 MTK_M4U_ID(M4U_LARB9_ID, 22)
-#define M4U_PORT_CAM_FAKE		 MTK_M4U_ID(M4U_LARB9_ID, 23)
-
-/* larb10-CAM_A */
-#define M4U_PORT_CAM_IMGO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 0)
-#define M4U_PORT_CAM_RRZO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 1)
-#define M4U_PORT_CAM_LSCI_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 2)
-#define M4U_PORT_CAM_BPCI_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 3)
-#define M4U_PORT_CAM_YUVO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 4)
-#define M4U_PORT_CAM_UFDI_R2_A		 MTK_M4U_ID(M4U_LARB10_ID, 5)
-#define M4U_PORT_CAM_RAWI_R2_A		 MTK_M4U_ID(M4U_LARB10_ID, 6)
-#define M4U_PORT_CAM_RAWI_R5_A		 MTK_M4U_ID(M4U_LARB10_ID, 7)
-#define M4U_PORT_CAM_IMGO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 8)
-#define M4U_PORT_CAM_RRZO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 9)
-#define M4U_PORT_CAM_LSCI_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 10)
-#define M4U_PORT_CAM_BPCI_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 11)
-#define M4U_PORT_CAM_YUVO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 12)
-#define M4U_PORT_CAM_UFDI_R2_B		 MTK_M4U_ID(M4U_LARB10_ID, 13)
-#define M4U_PORT_CAM_RAWI_R2_B		 MTK_M4U_ID(M4U_LARB10_ID, 14)
-#define M4U_PORT_CAM_RAWI_R5_B		 MTK_M4U_ID(M4U_LARB10_ID, 15)
-#define M4U_PORT_CAM_CAMSV_0		 MTK_M4U_ID(M4U_LARB10_ID, 16)
-#define M4U_PORT_CAM_AAO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 17)
-#define M4U_PORT_CAM_AFO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 18)
-#define M4U_PORT_CAM_FLKO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 19)
-#define M4U_PORT_CAM_LCESO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 20)
-#define M4U_PORT_CAM_CRZO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 21)
-#define M4U_PORT_CAM_AAO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 22)
-#define M4U_PORT_CAM_AFO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 23)
-#define M4U_PORT_CAM_FLKO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 24)
-#define M4U_PORT_CAM_LCESO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 25)
-#define M4U_PORT_CAM_CRZO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 26)
-#define M4U_PORT_CAM_LTMSO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 27)
-#define M4U_PORT_CAM_RSSO_R1_A		 MTK_M4U_ID(M4U_LARB10_ID, 28)
-#define M4U_PORT_CAM_LTMSO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 29)
-#define M4U_PORT_CAM_RSSO_R1_B		 MTK_M4U_ID(M4U_LARB10_ID, 30)
-
-/* larb11-CAM-VPU */
-#define M4U_PORT_CAM_IPUO		 MTK_M4U_ID(M4U_LARB11_ID, 0)
-#define M4U_PORT_CAM_IPU2O		 MTK_M4U_ID(M4U_LARB11_ID, 1)
-#define M4U_PORT_CAM_IPU3O		 MTK_M4U_ID(M4U_LARB11_ID, 2)
-#define M4U_PORT_CAM_IPUI		 MTK_M4U_ID(M4U_LARB11_ID, 3)
-#define M4U_PORT_CAM_IPU2I		 MTK_M4U_ID(M4U_LARB11_ID, 4)
-
-#endif
diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h
deleted file mode 100644
index b0b1091aad6..00000000000
--- a/include/dt-bindings/mux/ti-serdes.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * This header provides constants for SERDES MUX for TI SoCs
- */
-
-#ifndef _DT_BINDINGS_MUX_TI_SERDES
-#define _DT_BINDINGS_MUX_TI_SERDES
-
-/*
- * These bindings are deprecated, because they do not match the actual
- * concept of bindings but rather contain pure constants values used only
- * in DTS board files.
- * Instead include the header in the DTS source directory.
- */
-#warning "These bindings are deprecated. Instead, use the header in the DTS source directory."
-
-/* J721E */
-
-#define J721E_SERDES0_LANE0_QSGMII_LANE1	0x0
-#define J721E_SERDES0_LANE0_PCIE0_LANE0		0x1
-#define J721E_SERDES0_LANE0_USB3_0_SWAP		0x2
-#define J721E_SERDES0_LANE0_IP4_UNUSED		0x3
-
-#define J721E_SERDES0_LANE1_QSGMII_LANE2	0x0
-#define J721E_SERDES0_LANE1_PCIE0_LANE1		0x1
-#define J721E_SERDES0_LANE1_USB3_0		0x2
-#define J721E_SERDES0_LANE1_IP4_UNUSED		0x3
-
-#define J721E_SERDES1_LANE0_QSGMII_LANE3	0x0
-#define J721E_SERDES1_LANE0_PCIE1_LANE0		0x1
-#define J721E_SERDES1_LANE0_USB3_1_SWAP		0x2
-#define J721E_SERDES1_LANE0_SGMII_LANE0		0x3
-
-#define J721E_SERDES1_LANE1_QSGMII_LANE4	0x0
-#define J721E_SERDES1_LANE1_PCIE1_LANE1		0x1
-#define J721E_SERDES1_LANE1_USB3_1		0x2
-#define J721E_SERDES1_LANE1_SGMII_LANE1		0x3
-
-#define J721E_SERDES2_LANE0_IP1_UNUSED		0x0
-#define J721E_SERDES2_LANE0_PCIE2_LANE0		0x1
-#define J721E_SERDES2_LANE0_USB3_1_SWAP		0x2
-#define J721E_SERDES2_LANE0_SGMII_LANE0		0x3
-
-#define J721E_SERDES2_LANE1_IP1_UNUSED		0x0
-#define J721E_SERDES2_LANE1_PCIE2_LANE1		0x1
-#define J721E_SERDES2_LANE1_USB3_1		0x2
-#define J721E_SERDES2_LANE1_SGMII_LANE1		0x3
-
-#define J721E_SERDES3_LANE0_IP1_UNUSED		0x0
-#define J721E_SERDES3_LANE0_PCIE3_LANE0		0x1
-#define J721E_SERDES3_LANE0_USB3_0_SWAP		0x2
-#define J721E_SERDES3_LANE0_IP4_UNUSED		0x3
-
-#define J721E_SERDES3_LANE1_IP1_UNUSED		0x0
-#define J721E_SERDES3_LANE1_PCIE3_LANE1		0x1
-#define J721E_SERDES3_LANE1_USB3_0		0x2
-#define J721E_SERDES3_LANE1_IP4_UNUSED		0x3
-
-#define J721E_SERDES4_LANE0_EDP_LANE0		0x0
-#define J721E_SERDES4_LANE0_IP2_UNUSED		0x1
-#define J721E_SERDES4_LANE0_QSGMII_LANE5	0x2
-#define J721E_SERDES4_LANE0_IP4_UNUSED		0x3
-
-#define J721E_SERDES4_LANE1_EDP_LANE1		0x0
-#define J721E_SERDES4_LANE1_IP2_UNUSED		0x1
-#define J721E_SERDES4_LANE1_QSGMII_LANE6	0x2
-#define J721E_SERDES4_LANE1_IP4_UNUSED		0x3
-
-#define J721E_SERDES4_LANE2_EDP_LANE2		0x0
-#define J721E_SERDES4_LANE2_IP2_UNUSED		0x1
-#define J721E_SERDES4_LANE2_QSGMII_LANE7	0x2
-#define J721E_SERDES4_LANE2_IP4_UNUSED		0x3
-
-#define J721E_SERDES4_LANE3_EDP_LANE3		0x0
-#define J721E_SERDES4_LANE3_IP2_UNUSED		0x1
-#define J721E_SERDES4_LANE3_QSGMII_LANE8	0x2
-#define J721E_SERDES4_LANE3_IP4_UNUSED		0x3
-
-/* J7200 */
-
-#define J7200_SERDES0_LANE0_QSGMII_LANE3	0x0
-#define J7200_SERDES0_LANE0_PCIE1_LANE0		0x1
-#define J7200_SERDES0_LANE0_IP3_UNUSED		0x2
-#define J7200_SERDES0_LANE0_IP4_UNUSED		0x3
-
-#define J7200_SERDES0_LANE1_QSGMII_LANE4	0x0
-#define J7200_SERDES0_LANE1_PCIE1_LANE1		0x1
-#define J7200_SERDES0_LANE1_IP3_UNUSED		0x2
-#define J7200_SERDES0_LANE1_IP4_UNUSED		0x3
-
-#define J7200_SERDES0_LANE2_QSGMII_LANE1	0x0
-#define J7200_SERDES0_LANE2_PCIE1_LANE2		0x1
-#define J7200_SERDES0_LANE2_IP3_UNUSED		0x2
-#define J7200_SERDES0_LANE2_IP4_UNUSED		0x3
-
-#define J7200_SERDES0_LANE3_QSGMII_LANE2	0x0
-#define J7200_SERDES0_LANE3_PCIE1_LANE3		0x1
-#define J7200_SERDES0_LANE3_USB			0x2
-#define J7200_SERDES0_LANE3_IP4_UNUSED		0x3
-
-/* AM64 */
-
-#define AM64_SERDES0_LANE0_PCIE0		0x0
-#define AM64_SERDES0_LANE0_USB			0x1
-
-/* J721S2 */
-
-#define J721S2_SERDES0_LANE0_EDP_LANE0		0x0
-#define J721S2_SERDES0_LANE0_PCIE1_LANE0	0x1
-#define J721S2_SERDES0_LANE0_IP3_UNUSED		0x2
-#define J721S2_SERDES0_LANE0_IP4_UNUSED		0x3
-
-#define J721S2_SERDES0_LANE1_EDP_LANE1		0x0
-#define J721S2_SERDES0_LANE1_PCIE1_LANE1	0x1
-#define J721S2_SERDES0_LANE1_USB		0x2
-#define J721S2_SERDES0_LANE1_IP4_UNUSED		0x3
-
-#define J721S2_SERDES0_LANE2_EDP_LANE2		0x0
-#define J721S2_SERDES0_LANE2_PCIE1_LANE2	0x1
-#define J721S2_SERDES0_LANE2_IP3_UNUSED		0x2
-#define J721S2_SERDES0_LANE2_IP4_UNUSED		0x3
-
-#define J721S2_SERDES0_LANE3_EDP_LANE3		0x0
-#define J721S2_SERDES0_LANE3_PCIE1_LANE3	0x1
-#define J721S2_SERDES0_LANE3_USB		0x2
-#define J721S2_SERDES0_LANE3_IP4_UNUSED		0x3
-
-/* J784S4 */
-
-#define J784S4_SERDES0_LANE0_IP1_UNUSED		0x0
-#define J784S4_SERDES0_LANE0_PCIE1_LANE0	0x1
-#define J784S4_SERDES0_LANE0_IP3_UNUSED		0x2
-#define J784S4_SERDES0_LANE0_IP4_UNUSED		0x3
-
-#define J784S4_SERDES0_LANE1_IP1_UNUSED		0x0
-#define J784S4_SERDES0_LANE1_PCIE1_LANE1	0x1
-#define J784S4_SERDES0_LANE1_IP3_UNUSED		0x2
-#define J784S4_SERDES0_LANE1_IP4_UNUSED		0x3
-
-#define J784S4_SERDES0_LANE2_PCIE3_LANE0	0x0
-#define J784S4_SERDES0_LANE2_PCIE1_LANE2	0x1
-#define J784S4_SERDES0_LANE2_IP3_UNUSED		0x2
-#define J784S4_SERDES0_LANE2_IP4_UNUSED		0x3
-
-#define J784S4_SERDES0_LANE3_PCIE3_LANE1	0x0
-#define J784S4_SERDES0_LANE3_PCIE1_LANE3	0x1
-#define J784S4_SERDES0_LANE3_USB		0x2
-#define J784S4_SERDES0_LANE3_IP4_UNUSED		0x3
-
-#define J784S4_SERDES1_LANE0_QSGMII_LANE3	0x0
-#define J784S4_SERDES1_LANE0_PCIE0_LANE0	0x1
-#define J784S4_SERDES1_LANE0_IP3_UNUSED		0x2
-#define J784S4_SERDES1_LANE0_IP4_UNUSED		0x3
-
-#define J784S4_SERDES1_LANE1_QSGMII_LANE4	0x0
-#define J784S4_SERDES1_LANE1_PCIE0_LANE1	0x1
-#define J784S4_SERDES1_LANE1_IP3_UNUSED		0x2
-#define J784S4_SERDES1_LANE1_IP4_UNUSED		0x3
-
-#define J784S4_SERDES1_LANE2_QSGMII_LANE1	0x0
-#define J784S4_SERDES1_LANE2_PCIE0_LANE2	0x1
-#define J784S4_SERDES1_LANE2_PCIE2_LANE0	0x2
-#define J784S4_SERDES1_LANE2_IP4_UNUSED		0x3
-
-#define J784S4_SERDES1_LANE3_QSGMII_LANE2	0x0
-#define J784S4_SERDES1_LANE3_PCIE0_LANE3	0x1
-#define J784S4_SERDES1_LANE3_PCIE2_LANE1	0x2
-#define J784S4_SERDES1_LANE3_IP4_UNUSED		0x3
-
-#define J784S4_SERDES2_LANE0_QSGMII_LANE5	0x0
-#define J784S4_SERDES2_LANE0_IP2_UNUSED		0x1
-#define J784S4_SERDES2_LANE0_IP3_UNUSED		0x2
-#define J784S4_SERDES2_LANE0_IP4_UNUSED		0x3
-
-#define J784S4_SERDES2_LANE1_QSGMII_LANE6	0x0
-#define J784S4_SERDES2_LANE1_IP2_UNUSED		0x1
-#define J784S4_SERDES2_LANE1_IP3_UNUSED		0x2
-#define J784S4_SERDES2_LANE1_IP4_UNUSED		0x3
-
-#define J784S4_SERDES2_LANE2_QSGMII_LANE7	0x0
-#define J784S4_SERDES2_LANE2_QSGMII_LANE1	0x1
-#define J784S4_SERDES2_LANE2_IP3_UNUSED		0x2
-#define J784S4_SERDES2_LANE2_IP4_UNUSED		0x3
-
-#define J784S4_SERDES2_LANE3_QSGMII_LANE8	0x0
-#define J784S4_SERDES2_LANE3_QSGMII_LANE2	0x1
-#define J784S4_SERDES2_LANE3_IP3_UNUSED		0x2
-#define J784S4_SERDES2_LANE3_IP4_UNUSED		0x3
-
-#endif /* _DT_BINDINGS_MUX_TI_SERDES */
diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
index 6b901b34234..979b5dfd835 100644
--- a/include/dt-bindings/phy/phy.h
+++ b/include/dt-bindings/phy/phy.h
@@ -23,5 +23,10 @@
 #define PHY_TYPE_DPHY		10
 #define PHY_TYPE_CPHY		11
 #define PHY_TYPE_USXGMII	12
+#define PHY_TYPE_XAUI		13
+
+#define PHY_POL_NORMAL		0
+#define PHY_POL_INVERT		1
+#define PHY_POL_AUTO		2
 
 #endif /* _DT_BINDINGS_PHY */
diff --git a/include/dt-bindings/pinctrl/mt6397-pinfunc.h b/include/dt-bindings/pinctrl/mt6397-pinfunc.h
deleted file mode 100644
index f393fbd6890..00000000000
--- a/include/dt-bindings/pinctrl/mt6397-pinfunc.h
+++ /dev/null
@@ -1,257 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __DTS_MT6397_PINFUNC_H
-#define __DTS_MT6397_PINFUNC_H
-
-#include <dt-bindings/pinctrl/mt65xx.h>
-
-#define MT6397_PIN_0_INT__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
-#define MT6397_PIN_0_INT__FUNC_INT (MTK_PIN_NO(0) | 1)
-
-#define MT6397_PIN_1_SRCVOLTEN__FUNC_GPIO1 (MTK_PIN_NO(1) | 0)
-#define MT6397_PIN_1_SRCVOLTEN__FUNC_SRCVOLTEN (MTK_PIN_NO(1) | 1)
-#define MT6397_PIN_1_SRCVOLTEN__FUNC_TEST_CK1 (MTK_PIN_NO(1) | 6)
-
-#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_GPIO2 (MTK_PIN_NO(2) | 0)
-#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_SRCLKEN_PERI (MTK_PIN_NO(2) | 1)
-#define MT6397_PIN_2_SRCLKEN_PERI__FUNC_TEST_CK2 (MTK_PIN_NO(2) | 6)
-
-#define MT6397_PIN_3_RTC_32K1V8__FUNC_GPIO3 (MTK_PIN_NO(3) | 0)
-#define MT6397_PIN_3_RTC_32K1V8__FUNC_RTC_32K1V8 (MTK_PIN_NO(3) | 1)
-#define MT6397_PIN_3_RTC_32K1V8__FUNC_TEST_CK3 (MTK_PIN_NO(3) | 6)
-
-#define MT6397_PIN_4_WRAP_EVENT__FUNC_GPIO4 (MTK_PIN_NO(4) | 0)
-#define MT6397_PIN_4_WRAP_EVENT__FUNC_WRAP_EVENT (MTK_PIN_NO(4) | 1)
-
-#define MT6397_PIN_5_SPI_CLK__FUNC_GPIO5 (MTK_PIN_NO(5) | 0)
-#define MT6397_PIN_5_SPI_CLK__FUNC_SPI_CLK (MTK_PIN_NO(5) | 1)
-
-#define MT6397_PIN_6_SPI_CSN__FUNC_GPIO6 (MTK_PIN_NO(6) | 0)
-#define MT6397_PIN_6_SPI_CSN__FUNC_SPI_CSN (MTK_PIN_NO(6) | 1)
-
-#define MT6397_PIN_7_SPI_MOSI__FUNC_GPIO7 (MTK_PIN_NO(7) | 0)
-#define MT6397_PIN_7_SPI_MOSI__FUNC_SPI_MOSI (MTK_PIN_NO(7) | 1)
-
-#define MT6397_PIN_8_SPI_MISO__FUNC_GPIO8 (MTK_PIN_NO(8) | 0)
-#define MT6397_PIN_8_SPI_MISO__FUNC_SPI_MISO (MTK_PIN_NO(8) | 1)
-
-#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_GPIO9 (MTK_PIN_NO(9) | 0)
-#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_AUD_CLK (MTK_PIN_NO(9) | 1)
-#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_IN0 (MTK_PIN_NO(9) | 6)
-#define MT6397_PIN_9_AUD_CLK_MOSI__FUNC_TEST_OUT0 (MTK_PIN_NO(9) | 7)
-
-#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_GPIO10 (MTK_PIN_NO(10) | 0)
-#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_AUD_MISO (MTK_PIN_NO(10) | 1)
-#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_IN1 (MTK_PIN_NO(10) | 6)
-#define MT6397_PIN_10_AUD_DAT_MISO__FUNC_TEST_OUT1 (MTK_PIN_NO(10) | 7)
-
-#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_GPIO11 (MTK_PIN_NO(11) | 0)
-#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_AUD_MOSI (MTK_PIN_NO(11) | 1)
-#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_IN2 (MTK_PIN_NO(11) | 6)
-#define MT6397_PIN_11_AUD_DAT_MOSI__FUNC_TEST_OUT2 (MTK_PIN_NO(11) | 7)
-
-#define MT6397_PIN_12_COL0__FUNC_GPIO12 (MTK_PIN_NO(12) | 0)
-#define MT6397_PIN_12_COL0__FUNC_COL0_USBDL (MTK_PIN_NO(12) | 1)
-#define MT6397_PIN_12_COL0__FUNC_EINT10_1X (MTK_PIN_NO(12) | 2)
-#define MT6397_PIN_12_COL0__FUNC_PWM1_3X (MTK_PIN_NO(12) | 3)
-#define MT6397_PIN_12_COL0__FUNC_TEST_IN3 (MTK_PIN_NO(12) | 6)
-#define MT6397_PIN_12_COL0__FUNC_TEST_OUT3 (MTK_PIN_NO(12) | 7)
-
-#define MT6397_PIN_13_COL1__FUNC_GPIO13 (MTK_PIN_NO(13) | 0)
-#define MT6397_PIN_13_COL1__FUNC_COL1 (MTK_PIN_NO(13) | 1)
-#define MT6397_PIN_13_COL1__FUNC_EINT11_1X (MTK_PIN_NO(13) | 2)
-#define MT6397_PIN_13_COL1__FUNC_SCL0_2X (MTK_PIN_NO(13) | 3)
-#define MT6397_PIN_13_COL1__FUNC_TEST_IN4 (MTK_PIN_NO(13) | 6)
-#define MT6397_PIN_13_COL1__FUNC_TEST_OUT4 (MTK_PIN_NO(13) | 7)
-
-#define MT6397_PIN_14_COL2__FUNC_GPIO14 (MTK_PIN_NO(14) | 0)
-#define MT6397_PIN_14_COL2__FUNC_COL2 (MTK_PIN_NO(14) | 1)
-#define MT6397_PIN_14_COL2__FUNC_EINT12_1X (MTK_PIN_NO(14) | 2)
-#define MT6397_PIN_14_COL2__FUNC_SDA0_2X (MTK_PIN_NO(14) | 3)
-#define MT6397_PIN_14_COL2__FUNC_TEST_IN5 (MTK_PIN_NO(14) | 6)
-#define MT6397_PIN_14_COL2__FUNC_TEST_OUT5 (MTK_PIN_NO(14) | 7)
-
-#define MT6397_PIN_15_COL3__FUNC_GPIO15 (MTK_PIN_NO(15) | 0)
-#define MT6397_PIN_15_COL3__FUNC_COL3 (MTK_PIN_NO(15) | 1)
-#define MT6397_PIN_15_COL3__FUNC_EINT13_1X (MTK_PIN_NO(15) | 2)
-#define MT6397_PIN_15_COL3__FUNC_SCL1_2X (MTK_PIN_NO(15) | 3)
-#define MT6397_PIN_15_COL3__FUNC_TEST_IN6 (MTK_PIN_NO(15) | 6)
-#define MT6397_PIN_15_COL3__FUNC_TEST_OUT6 (MTK_PIN_NO(15) | 7)
-
-#define MT6397_PIN_16_COL4__FUNC_GPIO16 (MTK_PIN_NO(16) | 0)
-#define MT6397_PIN_16_COL4__FUNC_COL4 (MTK_PIN_NO(16) | 1)
-#define MT6397_PIN_16_COL4__FUNC_EINT14_1X (MTK_PIN_NO(16) | 2)
-#define MT6397_PIN_16_COL4__FUNC_SDA1_2X (MTK_PIN_NO(16) | 3)
-#define MT6397_PIN_16_COL4__FUNC_TEST_IN7 (MTK_PIN_NO(16) | 6)
-#define MT6397_PIN_16_COL4__FUNC_TEST_OUT7 (MTK_PIN_NO(16) | 7)
-
-#define MT6397_PIN_17_COL5__FUNC_GPIO17 (MTK_PIN_NO(17) | 0)
-#define MT6397_PIN_17_COL5__FUNC_COL5 (MTK_PIN_NO(17) | 1)
-#define MT6397_PIN_17_COL5__FUNC_EINT15_1X (MTK_PIN_NO(17) | 2)
-#define MT6397_PIN_17_COL5__FUNC_SCL2_2X (MTK_PIN_NO(17) | 3)
-#define MT6397_PIN_17_COL5__FUNC_TEST_IN8 (MTK_PIN_NO(17) | 6)
-#define MT6397_PIN_17_COL5__FUNC_TEST_OUT8 (MTK_PIN_NO(17) | 7)
-
-#define MT6397_PIN_18_COL6__FUNC_GPIO18 (MTK_PIN_NO(18) | 0)
-#define MT6397_PIN_18_COL6__FUNC_COL6 (MTK_PIN_NO(18) | 1)
-#define MT6397_PIN_18_COL6__FUNC_EINT16_1X (MTK_PIN_NO(18) | 2)
-#define MT6397_PIN_18_COL6__FUNC_SDA2_2X (MTK_PIN_NO(18) | 3)
-#define MT6397_PIN_18_COL6__FUNC_GPIO32K_0 (MTK_PIN_NO(18) | 4)
-#define MT6397_PIN_18_COL6__FUNC_GPIO26M_0 (MTK_PIN_NO(18) | 5)
-#define MT6397_PIN_18_COL6__FUNC_TEST_IN9 (MTK_PIN_NO(18) | 6)
-#define MT6397_PIN_18_COL6__FUNC_TEST_OUT9 (MTK_PIN_NO(18) | 7)
-
-#define MT6397_PIN_19_COL7__FUNC_GPIO19 (MTK_PIN_NO(19) | 0)
-#define MT6397_PIN_19_COL7__FUNC_COL7 (MTK_PIN_NO(19) | 1)
-#define MT6397_PIN_19_COL7__FUNC_EINT17_1X (MTK_PIN_NO(19) | 2)
-#define MT6397_PIN_19_COL7__FUNC_PWM2_3X (MTK_PIN_NO(19) | 3)
-#define MT6397_PIN_19_COL7__FUNC_GPIO32K_1 (MTK_PIN_NO(19) | 4)
-#define MT6397_PIN_19_COL7__FUNC_GPIO26M_1 (MTK_PIN_NO(19) | 5)
-#define MT6397_PIN_19_COL7__FUNC_TEST_IN10 (MTK_PIN_NO(19) | 6)
-#define MT6397_PIN_19_COL7__FUNC_TEST_OUT10 (MTK_PIN_NO(19) | 7)
-
-#define MT6397_PIN_20_ROW0__FUNC_GPIO20 (MTK_PIN_NO(20) | 0)
-#define MT6397_PIN_20_ROW0__FUNC_ROW0 (MTK_PIN_NO(20) | 1)
-#define MT6397_PIN_20_ROW0__FUNC_EINT18_1X (MTK_PIN_NO(20) | 2)
-#define MT6397_PIN_20_ROW0__FUNC_SCL0_3X (MTK_PIN_NO(20) | 3)
-#define MT6397_PIN_20_ROW0__FUNC_TEST_IN11 (MTK_PIN_NO(20) | 6)
-#define MT6397_PIN_20_ROW0__FUNC_TEST_OUT11 (MTK_PIN_NO(20) | 7)
-
-#define MT6397_PIN_21_ROW1__FUNC_GPIO21 (MTK_PIN_NO(21) | 0)
-#define MT6397_PIN_21_ROW1__FUNC_ROW1 (MTK_PIN_NO(21) | 1)
-#define MT6397_PIN_21_ROW1__FUNC_EINT19_1X (MTK_PIN_NO(21) | 2)
-#define MT6397_PIN_21_ROW1__FUNC_SDA0_3X (MTK_PIN_NO(21) | 3)
-#define MT6397_PIN_21_ROW1__FUNC_AUD_TSTCK (MTK_PIN_NO(21) | 4)
-#define MT6397_PIN_21_ROW1__FUNC_TEST_IN12 (MTK_PIN_NO(21) | 6)
-#define MT6397_PIN_21_ROW1__FUNC_TEST_OUT12 (MTK_PIN_NO(21) | 7)
-
-#define MT6397_PIN_22_ROW2__FUNC_GPIO22 (MTK_PIN_NO(22) | 0)
-#define MT6397_PIN_22_ROW2__FUNC_ROW2 (MTK_PIN_NO(22) | 1)
-#define MT6397_PIN_22_ROW2__FUNC_EINT20_1X (MTK_PIN_NO(22) | 2)
-#define MT6397_PIN_22_ROW2__FUNC_SCL1_3X (MTK_PIN_NO(22) | 3)
-#define MT6397_PIN_22_ROW2__FUNC_TEST_IN13 (MTK_PIN_NO(22) | 6)
-#define MT6397_PIN_22_ROW2__FUNC_TEST_OUT13 (MTK_PIN_NO(22) | 7)
-
-#define MT6397_PIN_23_ROW3__FUNC_GPIO23 (MTK_PIN_NO(23) | 0)
-#define MT6397_PIN_23_ROW3__FUNC_ROW3 (MTK_PIN_NO(23) | 1)
-#define MT6397_PIN_23_ROW3__FUNC_EINT21_1X (MTK_PIN_NO(23) | 2)
-#define MT6397_PIN_23_ROW3__FUNC_SDA1_3X (MTK_PIN_NO(23) | 3)
-#define MT6397_PIN_23_ROW3__FUNC_TEST_IN14 (MTK_PIN_NO(23) | 6)
-#define MT6397_PIN_23_ROW3__FUNC_TEST_OUT14 (MTK_PIN_NO(23) | 7)
-
-#define MT6397_PIN_24_ROW4__FUNC_GPIO24 (MTK_PIN_NO(24) | 0)
-#define MT6397_PIN_24_ROW4__FUNC_ROW4 (MTK_PIN_NO(24) | 1)
-#define MT6397_PIN_24_ROW4__FUNC_EINT22_1X (MTK_PIN_NO(24) | 2)
-#define MT6397_PIN_24_ROW4__FUNC_SCL2_3X (MTK_PIN_NO(24) | 3)
-#define MT6397_PIN_24_ROW4__FUNC_TEST_IN15 (MTK_PIN_NO(24) | 6)
-#define MT6397_PIN_24_ROW4__FUNC_TEST_OUT15 (MTK_PIN_NO(24) | 7)
-
-#define MT6397_PIN_25_ROW5__FUNC_GPIO25 (MTK_PIN_NO(25) | 0)
-#define MT6397_PIN_25_ROW5__FUNC_ROW5 (MTK_PIN_NO(25) | 1)
-#define MT6397_PIN_25_ROW5__FUNC_EINT23_1X (MTK_PIN_NO(25) | 2)
-#define MT6397_PIN_25_ROW5__FUNC_SDA2_3X (MTK_PIN_NO(25) | 3)
-#define MT6397_PIN_25_ROW5__FUNC_TEST_IN16 (MTK_PIN_NO(25) | 6)
-#define MT6397_PIN_25_ROW5__FUNC_TEST_OUT16 (MTK_PIN_NO(25) | 7)
-
-#define MT6397_PIN_26_ROW6__FUNC_GPIO26 (MTK_PIN_NO(26) | 0)
-#define MT6397_PIN_26_ROW6__FUNC_ROW6 (MTK_PIN_NO(26) | 1)
-#define MT6397_PIN_26_ROW6__FUNC_EINT24_1X (MTK_PIN_NO(26) | 2)
-#define MT6397_PIN_26_ROW6__FUNC_PWM3_3X (MTK_PIN_NO(26) | 3)
-#define MT6397_PIN_26_ROW6__FUNC_GPIO32K_2 (MTK_PIN_NO(26) | 4)
-#define MT6397_PIN_26_ROW6__FUNC_GPIO26M_2 (MTK_PIN_NO(26) | 5)
-#define MT6397_PIN_26_ROW6__FUNC_TEST_IN17 (MTK_PIN_NO(26) | 6)
-#define MT6397_PIN_26_ROW6__FUNC_TEST_OUT17 (MTK_PIN_NO(26) | 7)
-
-#define MT6397_PIN_27_ROW7__FUNC_GPIO27 (MTK_PIN_NO(27) | 0)
-#define MT6397_PIN_27_ROW7__FUNC_ROW7 (MTK_PIN_NO(27) | 1)
-#define MT6397_PIN_27_ROW7__FUNC_EINT3_1X (MTK_PIN_NO(27) | 2)
-#define MT6397_PIN_27_ROW7__FUNC_CBUS (MTK_PIN_NO(27) | 3)
-#define MT6397_PIN_27_ROW7__FUNC_GPIO32K_3 (MTK_PIN_NO(27) | 4)
-#define MT6397_PIN_27_ROW7__FUNC_GPIO26M_3 (MTK_PIN_NO(27) | 5)
-#define MT6397_PIN_27_ROW7__FUNC_TEST_IN18 (MTK_PIN_NO(27) | 6)
-#define MT6397_PIN_27_ROW7__FUNC_TEST_OUT18 (MTK_PIN_NO(27) | 7)
-
-#define MT6397_PIN_28_PWM1__FUNC_GPIO28 (MTK_PIN_NO(28) | 0)
-#define MT6397_PIN_28_PWM1__FUNC_PWM1 (MTK_PIN_NO(28) | 1)
-#define MT6397_PIN_28_PWM1__FUNC_EINT4_1X (MTK_PIN_NO(28) | 2)
-#define MT6397_PIN_28_PWM1__FUNC_GPIO32K_4 (MTK_PIN_NO(28) | 4)
-#define MT6397_PIN_28_PWM1__FUNC_GPIO26M_4 (MTK_PIN_NO(28) | 5)
-#define MT6397_PIN_28_PWM1__FUNC_TEST_IN19 (MTK_PIN_NO(28) | 6)
-#define MT6397_PIN_28_PWM1__FUNC_TEST_OUT19 (MTK_PIN_NO(28) | 7)
-
-#define MT6397_PIN_29_PWM2__FUNC_GPIO29 (MTK_PIN_NO(29) | 0)
-#define MT6397_PIN_29_PWM2__FUNC_PWM2 (MTK_PIN_NO(29) | 1)
-#define MT6397_PIN_29_PWM2__FUNC_EINT5_1X (MTK_PIN_NO(29) | 2)
-#define MT6397_PIN_29_PWM2__FUNC_GPIO32K_5 (MTK_PIN_NO(29) | 4)
-#define MT6397_PIN_29_PWM2__FUNC_GPIO26M_5 (MTK_PIN_NO(29) | 5)
-#define MT6397_PIN_29_PWM2__FUNC_TEST_IN20 (MTK_PIN_NO(29) | 6)
-#define MT6397_PIN_29_PWM2__FUNC_TEST_OUT20 (MTK_PIN_NO(29) | 7)
-
-#define MT6397_PIN_30_PWM3__FUNC_GPIO30 (MTK_PIN_NO(30) | 0)
-#define MT6397_PIN_30_PWM3__FUNC_PWM3 (MTK_PIN_NO(30) | 1)
-#define MT6397_PIN_30_PWM3__FUNC_EINT6_1X (MTK_PIN_NO(30) | 2)
-#define MT6397_PIN_30_PWM3__FUNC_COL0 (MTK_PIN_NO(30) | 3)
-#define MT6397_PIN_30_PWM3__FUNC_GPIO32K_6 (MTK_PIN_NO(30) | 4)
-#define MT6397_PIN_30_PWM3__FUNC_GPIO26M_6 (MTK_PIN_NO(30) | 5)
-#define MT6397_PIN_30_PWM3__FUNC_TEST_IN21 (MTK_PIN_NO(30) | 6)
-#define MT6397_PIN_30_PWM3__FUNC_TEST_OUT21 (MTK_PIN_NO(30) | 7)
-
-#define MT6397_PIN_31_SCL0__FUNC_GPIO31 (MTK_PIN_NO(31) | 0)
-#define MT6397_PIN_31_SCL0__FUNC_SCL0 (MTK_PIN_NO(31) | 1)
-#define MT6397_PIN_31_SCL0__FUNC_EINT7_1X (MTK_PIN_NO(31) | 2)
-#define MT6397_PIN_31_SCL0__FUNC_PWM1_2X (MTK_PIN_NO(31) | 3)
-#define MT6397_PIN_31_SCL0__FUNC_TEST_IN22 (MTK_PIN_NO(31) | 6)
-#define MT6397_PIN_31_SCL0__FUNC_TEST_OUT22 (MTK_PIN_NO(31) | 7)
-
-#define MT6397_PIN_32_SDA0__FUNC_GPIO32 (MTK_PIN_NO(32) | 0)
-#define MT6397_PIN_32_SDA0__FUNC_SDA0 (MTK_PIN_NO(32) | 1)
-#define MT6397_PIN_32_SDA0__FUNC_EINT8_1X (MTK_PIN_NO(32) | 2)
-#define MT6397_PIN_32_SDA0__FUNC_TEST_IN23 (MTK_PIN_NO(32) | 6)
-#define MT6397_PIN_32_SDA0__FUNC_TEST_OUT23 (MTK_PIN_NO(32) | 7)
-
-#define MT6397_PIN_33_SCL1__FUNC_GPIO33 (MTK_PIN_NO(33) | 0)
-#define MT6397_PIN_33_SCL1__FUNC_SCL1 (MTK_PIN_NO(33) | 1)
-#define MT6397_PIN_33_SCL1__FUNC_EINT9_1X (MTK_PIN_NO(33) | 2)
-#define MT6397_PIN_33_SCL1__FUNC_PWM2_2X (MTK_PIN_NO(33) | 3)
-#define MT6397_PIN_33_SCL1__FUNC_TEST_IN24 (MTK_PIN_NO(33) | 6)
-#define MT6397_PIN_33_SCL1__FUNC_TEST_OUT24 (MTK_PIN_NO(33) | 7)
-
-#define MT6397_PIN_34_SDA1__FUNC_GPIO34 (MTK_PIN_NO(34) | 0)
-#define MT6397_PIN_34_SDA1__FUNC_SDA1 (MTK_PIN_NO(34) | 1)
-#define MT6397_PIN_34_SDA1__FUNC_EINT0_1X (MTK_PIN_NO(34) | 2)
-#define MT6397_PIN_34_SDA1__FUNC_TEST_IN25 (MTK_PIN_NO(34) | 6)
-#define MT6397_PIN_34_SDA1__FUNC_TEST_OUT25 (MTK_PIN_NO(34) | 7)
-
-#define MT6397_PIN_35_SCL2__FUNC_GPIO35 (MTK_PIN_NO(35) | 0)
-#define MT6397_PIN_35_SCL2__FUNC_SCL2 (MTK_PIN_NO(35) | 1)
-#define MT6397_PIN_35_SCL2__FUNC_EINT1_1X (MTK_PIN_NO(35) | 2)
-#define MT6397_PIN_35_SCL2__FUNC_PWM3_2X (MTK_PIN_NO(35) | 3)
-#define MT6397_PIN_35_SCL2__FUNC_TEST_IN26 (MTK_PIN_NO(35) | 6)
-#define MT6397_PIN_35_SCL2__FUNC_TEST_OUT26 (MTK_PIN_NO(35) | 7)
-
-#define MT6397_PIN_36_SDA2__FUNC_GPIO36 (MTK_PIN_NO(36) | 0)
-#define MT6397_PIN_36_SDA2__FUNC_SDA2 (MTK_PIN_NO(36) | 1)
-#define MT6397_PIN_36_SDA2__FUNC_EINT2_1X (MTK_PIN_NO(36) | 2)
-#define MT6397_PIN_36_SDA2__FUNC_TEST_IN27 (MTK_PIN_NO(36) | 6)
-#define MT6397_PIN_36_SDA2__FUNC_TEST_OUT27 (MTK_PIN_NO(36) | 7)
-
-#define MT6397_PIN_37_HDMISD__FUNC_GPIO37 (MTK_PIN_NO(37) | 0)
-#define MT6397_PIN_37_HDMISD__FUNC_HDMISD (MTK_PIN_NO(37) | 1)
-#define MT6397_PIN_37_HDMISD__FUNC_TEST_IN28 (MTK_PIN_NO(37) | 6)
-#define MT6397_PIN_37_HDMISD__FUNC_TEST_OUT28 (MTK_PIN_NO(37) | 7)
-
-#define MT6397_PIN_38_HDMISCK__FUNC_GPIO38 (MTK_PIN_NO(38) | 0)
-#define MT6397_PIN_38_HDMISCK__FUNC_HDMISCK (MTK_PIN_NO(38) | 1)
-#define MT6397_PIN_38_HDMISCK__FUNC_TEST_IN29 (MTK_PIN_NO(38) | 6)
-#define MT6397_PIN_38_HDMISCK__FUNC_TEST_OUT29 (MTK_PIN_NO(38) | 7)
-
-#define MT6397_PIN_39_HTPLG__FUNC_GPIO39 (MTK_PIN_NO(39) | 0)
-#define MT6397_PIN_39_HTPLG__FUNC_HTPLG (MTK_PIN_NO(39) | 1)
-#define MT6397_PIN_39_HTPLG__FUNC_TEST_IN30 (MTK_PIN_NO(39) | 6)
-#define MT6397_PIN_39_HTPLG__FUNC_TEST_OUT30 (MTK_PIN_NO(39) | 7)
-
-#define MT6397_PIN_40_CEC__FUNC_GPIO40 (MTK_PIN_NO(40) | 0)
-#define MT6397_PIN_40_CEC__FUNC_CEC (MTK_PIN_NO(40) | 1)
-#define MT6397_PIN_40_CEC__FUNC_TEST_IN31 (MTK_PIN_NO(40) | 6)
-#define MT6397_PIN_40_CEC__FUNC_TEST_OUT31 (MTK_PIN_NO(40) | 7)
-
-#endif /* __DTS_MT6397_PINFUNC_H */
diff --git a/include/dt-bindings/regulator/samsung,s2mpg10-regulator.h b/include/dt-bindings/regulator/samsung,s2mpg10-regulator.h
new file mode 100644
index 00000000000..d9c16bba4d8
--- /dev/null
+++ b/include/dt-bindings/regulator/samsung,s2mpg10-regulator.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2021 Google LLC
+ * Copyright 2025 Linaro Ltd.
+ *
+ * Device Tree binding constants for the Samsung S2MPG1x PMIC regulators
+ */
+
+#ifndef _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H
+#define _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H
+
+/*
+ * Several regulators may be controlled via external signals instead of via
+ * software. These constants describe the possible signals for such regulators
+ * and generally correspond to the respecitve on-chip pins.
+ *
+ * S2MPG10 regulators supporting these are:
+ * - buck1m .. buck7m buck10m
+ * - ldo3m .. ldo19m
+ *
+ * ldo20m supports external control, but using a different set of control
+ * signals.
+ *
+ * S2MPG11 regulators supporting these are:
+ * - buck1s .. buck3s buck5s buck8s buck9s bucka buckd
+ * - ldo1s ldo2s ldo8s ldo13s
+ */
+#define S2MPG10_EXTCTRL_PWREN       0 /* PWREN pin */
+#define S2MPG10_EXTCTRL_PWREN_MIF   1 /* PWREN_MIF pin */
+#define S2MPG10_EXTCTRL_AP_ACTIVE_N 2 /* ~AP_ACTIVE_N pin */
+#define S2MPG10_EXTCTRL_CPUCL1_EN   3 /* CPUCL1_EN pin */
+#define S2MPG10_EXTCTRL_CPUCL1_EN2  4 /* CPUCL1_EN & PWREN pins */
+#define S2MPG10_EXTCTRL_CPUCL2_EN   5 /* CPUCL2_EN pin */
+#define S2MPG10_EXTCTRL_CPUCL2_EN2  6 /* CPUCL2_E2 & PWREN pins */
+#define S2MPG10_EXTCTRL_TPU_EN      7 /* TPU_EN pin */
+#define S2MPG10_EXTCTRL_TPU_EN2     8 /* TPU_EN & ~AP_ACTIVE_N pins */
+#define S2MPG10_EXTCTRL_TCXO_ON     9 /* TCXO_ON pin */
+#define S2MPG10_EXTCTRL_TCXO_ON2    10 /* TCXO_ON & ~AP_ACTIVE_N pins */
+
+#define S2MPG10_EXTCTRL_LDO20M_EN2  11 /* VLDO20M_EN & LDO20M_SFR */
+#define S2MPG10_EXTCTRL_LDO20M_EN   12 /* VLDO20M_EN pin */
+
+#define S2MPG11_EXTCTRL_PWREN       0 /* PWREN pin */
+#define S2MPG11_EXTCTRL_PWREN_MIF   1 /* PWREN_MIF pin */
+#define S2MPG11_EXTCTRL_AP_ACTIVE_N 2 /* ~AP_ACTIVE_N pin */
+#define S2MPG11_EXTCTRL_G3D_EN      3 /* G3D_EN pin */
+#define S2MPG11_EXTCTRL_G3D_EN2     4 /* G3D_EN & ~AP_ACTIVE_N pins */
+#define S2MPG11_EXTCTRL_AOC_VDD     5 /* AOC_VDD pin */
+#define S2MPG11_EXTCTRL_AOC_RET     6 /* AOC_RET pin */
+#define S2MPG11_EXTCTRL_UFS_EN      7 /* UFS_EN pin */
+#define S2MPG11_EXTCTRL_LDO13S_EN   8 /* VLDO13S_EN pin */
+
+#endif /* _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H */
diff --git a/include/dt-bindings/reset/bcm6318-reset.h b/include/dt-bindings/reset/bcm6318-reset.h
deleted file mode 100644
index f882662505e..00000000000
--- a/include/dt-bindings/reset/bcm6318-reset.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-
-#ifndef __DT_BINDINGS_RESET_BCM6318_H
-#define __DT_BINDINGS_RESET_BCM6318_H
-
-#define BCM6318_RST_SPI		0
-#define BCM6318_RST_EPHY	1
-#define BCM6318_RST_SAR		2
-#define BCM6318_RST_ENETSW	3
-#define BCM6318_RST_USBD	4
-#define BCM6318_RST_USBH	5
-#define BCM6318_RST_PCIE_CORE	6
-#define BCM6318_RST_PCIE	7
-#define BCM6318_RST_PCIE_EXT	8
-#define BCM6318_RST_PCIE_HARD	9
-#define BCM6318_RST_ADSL	10
-#define BCM6318_RST_PHYMIPS	11
-#define BCM6318_RST_HOSTMIPS	12
-
-#endif /* __DT_BINDINGS_RESET_BCM6318_H */
diff --git a/include/dt-bindings/reset/imx8ulp-pcc-reset.h b/include/dt-bindings/reset/imx8ulp-pcc-reset.h
deleted file mode 100644
index e99a4735c3c..00000000000
--- a/include/dt-bindings/reset/imx8ulp-pcc-reset.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright 2021 NXP
- */
-
-#ifndef DT_BINDING_PCC_RESET_IMX8ULP_H
-#define DT_BINDING_PCC_RESET_IMX8ULP_H
-
-/* PCC3 */
-#define PCC3_WDOG3_SWRST	0
-#define PCC3_WDOG4_SWRST	1
-#define PCC3_LPIT1_SWRST	2
-#define PCC3_TPM4_SWRST		3
-#define PCC3_TPM5_SWRST		4
-#define PCC3_FLEXIO1_SWRST	5
-#define PCC3_I3C2_SWRST		6
-#define PCC3_LPI2C4_SWRST	7
-#define PCC3_LPI2C5_SWRST	8
-#define PCC3_LPUART4_SWRST	9
-#define PCC3_LPUART5_SWRST	10
-#define PCC3_LPSPI4_SWRST	11
-#define PCC3_LPSPI5_SWRST	12
-
-/* PCC4 */
-#define PCC4_FLEXSPI2_SWRST	0
-#define PCC4_TPM6_SWRST		1
-#define PCC4_TPM7_SWRST		2
-#define PCC4_LPI2C6_SWRST	3
-#define PCC4_LPI2C7_SWRST	4
-#define PCC4_LPUART6_SWRST	5
-#define PCC4_LPUART7_SWRST	6
-#define PCC4_SAI4_SWRST		7
-#define PCC4_SAI5_SWRST		8
-#define PCC4_USDHC0_SWRST	9
-#define PCC4_USDHC1_SWRST	10
-#define PCC4_USDHC2_SWRST	11
-#define PCC4_USB0_SWRST		12
-#define PCC4_USB0_PHY_SWRST	13
-#define PCC4_USB1_SWRST		14
-#define PCC4_USB1_PHY_SWRST	15
-#define PCC4_ENET_SWRST		16
-
-/* PCC5 */
-#define PCC5_TPM8_SWRST		0
-#define PCC5_SAI6_SWRST		1
-#define PCC5_SAI7_SWRST		2
-#define PCC5_SPDIF_SWRST	3
-#define PCC5_ISI_SWRST		4
-#define PCC5_CSI_REGS_SWRST	5
-#define PCC5_CSI_SWRST		6
-#define PCC5_DSI_SWRST		7
-#define PCC5_WDOG5_SWRST	8
-#define PCC5_EPDC_SWRST		9
-#define PCC5_PXP_SWRST		10
-#define PCC5_GPU2D_SWRST	11
-#define PCC5_GPU3D_SWRST	12
-#define PCC5_DC_NANO_SWRST	13
-
-#endif /*DT_BINDING_RESET_IMX8ULP_H */
diff --git a/include/dt-bindings/reset/oxsemi,ox810se.h b/include/dt-bindings/reset/oxsemi,ox810se.h
deleted file mode 100644
index e943187e652..00000000000
--- a/include/dt-bindings/reset/oxsemi,ox810se.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef DT_RESET_OXSEMI_OX810SE_H
-#define DT_RESET_OXSEMI_OX810SE_H
-
-#define RESET_ARM	0
-#define RESET_COPRO	1
-/* Reserved		2 */
-/* Reserved		3 */
-#define RESET_USBHS	4
-#define RESET_USBHSPHY	5
-#define RESET_MAC	6
-#define RESET_PCI	7
-#define RESET_DMA	8
-#define RESET_DPE	9
-#define RESET_DDR	10
-#define RESET_SATA	11
-#define RESET_SATA_LINK	12
-#define RESET_SATA_PHY	13
- /* Reserved		14 */
-#define RESET_NAND	15
-#define RESET_GPIO	16
-#define RESET_UART1	17
-#define RESET_UART2	18
-#define RESET_MISC	19
-#define RESET_I2S	20
-#define RESET_AHB_MON	21
-#define RESET_UART3	22
-#define RESET_UART4	23
-#define RESET_SGDMA	24
-/* Reserved		25 */
-/* Reserved		26 */
-/* Reserved		27 */
-/* Reserved		28 */
-/* Reserved		29 */
-/* Reserved		30 */
-#define RESET_BUS	31
-
-#endif /* DT_RESET_OXSEMI_OX810SE_H */
diff --git a/include/dt-bindings/reset/oxsemi,ox820.h b/include/dt-bindings/reset/oxsemi,ox820.h
deleted file mode 100644
index 54b58e09c1c..00000000000
--- a/include/dt-bindings/reset/oxsemi,ox820.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
- */
-
-#ifndef DT_RESET_OXSEMI_OX820_H
-#define DT_RESET_OXSEMI_OX820_H
-
-#define RESET_SCU	0
-#define RESET_LEON	1
-#define RESET_ARM0	2
-#define RESET_ARM1	3
-#define RESET_USBHS	4
-#define RESET_USBPHYA	5
-#define RESET_MAC	6
-#define RESET_PCIEA	7
-#define RESET_SGDMA	8
-#define RESET_CIPHER	9
-#define RESET_DDR	10
-#define RESET_SATA	11
-#define RESET_SATA_LINK	12
-#define RESET_SATA_PHY	13
-#define RESET_PCIEPHY	14
-#define RESET_NAND	15
-#define RESET_GPIO	16
-#define RESET_UART1	17
-#define RESET_UART2	18
-#define RESET_MISC	19
-#define RESET_I2S	20
-#define RESET_SD	21
-#define RESET_MAC_2	22
-#define RESET_PCIEB	23
-#define RESET_VIDEO	24
-#define RESET_DDR_PHY	25
-#define RESET_USBPHYB	26
-#define RESET_USBDEV	27
-/* Reserved		29 */
-#define RESET_ARMDBG	29
-#define RESET_PLLA	30
-#define RESET_PLLB	31
-
-#endif /* DT_RESET_OXSEMI_OX820_H */
diff --git a/include/dt-bindings/reset/spacemit,k3-resets.h b/include/dt-bindings/reset/spacemit,k3-resets.h
new file mode 100644
index 00000000000..dc1ef009ba7
--- /dev/null
+++ b/include/dt-bindings/reset/spacemit,k3-resets.h
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 SpacemiT Technology Co. Ltd
+ */
+
+#ifndef _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_
+#define _DT_BINDINGS_RESET_SPACEMIT_K3_RESETS_H_
+
+/* MPMU resets */
+#define RESET_MPMU_WDT           0
+#define RESET_MPMU_RIPC          1
+
+/* APBC resets */
+#define RESET_APBC_UART0         0
+#define RESET_APBC_UART2         1
+#define RESET_APBC_UART3         2
+#define RESET_APBC_UART4         3
+#define RESET_APBC_UART5         4
+#define RESET_APBC_UART6         5
+#define RESET_APBC_UART7         6
+#define RESET_APBC_UART8         7
+#define RESET_APBC_UART9         8
+#define RESET_APBC_UART10        9
+#define RESET_APBC_GPIO          10
+#define RESET_APBC_PWM0          11
+#define RESET_APBC_PWM1          12
+#define RESET_APBC_PWM2          13
+#define RESET_APBC_PWM3          14
+#define RESET_APBC_PWM4          15
+#define RESET_APBC_PWM5          16
+#define RESET_APBC_PWM6          17
+#define RESET_APBC_PWM7          18
+#define RESET_APBC_PWM8          19
+#define RESET_APBC_PWM9          20
+#define RESET_APBC_PWM10         21
+#define RESET_APBC_PWM11         22
+#define RESET_APBC_PWM12         23
+#define RESET_APBC_PWM13         24
+#define RESET_APBC_PWM14         25
+#define RESET_APBC_PWM15         26
+#define RESET_APBC_PWM16         27
+#define RESET_APBC_PWM17         28
+#define RESET_APBC_PWM18         29
+#define RESET_APBC_PWM19         30
+#define RESET_APBC_SPI0          31
+#define RESET_APBC_SPI1          32
+#define RESET_APBC_SPI3          33
+#define RESET_APBC_RTC           34
+#define RESET_APBC_TWSI0         35
+#define RESET_APBC_TWSI1         36
+#define RESET_APBC_TWSI2         37
+#define RESET_APBC_TWSI4         38
+#define RESET_APBC_TWSI5         39
+#define RESET_APBC_TWSI6         40
+#define RESET_APBC_TWSI8         41
+#define RESET_APBC_TIMERS0       42
+#define RESET_APBC_TIMERS1       43
+#define RESET_APBC_TIMERS2       44
+#define RESET_APBC_TIMERS3       45
+#define RESET_APBC_TIMERS4       46
+#define RESET_APBC_TIMERS5       47
+#define RESET_APBC_TIMERS6       48
+#define RESET_APBC_TIMERS7       49
+#define RESET_APBC_AIB           50
+#define RESET_APBC_ONEWIRE       51
+#define RESET_APBC_I2S0          52
+#define RESET_APBC_I2S1          53
+#define RESET_APBC_I2S2          54
+#define RESET_APBC_I2S3          55
+#define RESET_APBC_I2S4          56
+#define RESET_APBC_I2S5          57
+#define RESET_APBC_DRO           58
+#define RESET_APBC_IR0           59
+#define RESET_APBC_IR1           60
+#define RESET_APBC_TSEN          61
+#define RESET_IPC_AP2AUD         62
+#define RESET_APBC_CAN0          63
+#define RESET_APBC_CAN1          64
+#define RESET_APBC_CAN2          65
+#define RESET_APBC_CAN3          66
+#define RESET_APBC_CAN4          67
+
+/* APMU resets */
+#define RESET_APMU_CSI           0
+#define RESET_APMU_CCIC2PHY      1
+#define RESET_APMU_CCIC3PHY      2
+#define RESET_APMU_ISP_CIBUS     3
+#define RESET_APMU_DSI_ESC       4
+#define RESET_APMU_LCD           5
+#define RESET_APMU_V2D           6
+#define RESET_APMU_LCD_MCLK      7
+#define RESET_APMU_LCD_DSCCLK    8
+#define RESET_APMU_SC2_HCLK      9
+#define RESET_APMU_CCIC_4X       10
+#define RESET_APMU_CCIC1_PHY     11
+#define RESET_APMU_SDH_AXI       12
+#define RESET_APMU_SDH0          13
+#define RESET_APMU_SDH1          14
+#define RESET_APMU_SDH2          15
+#define RESET_APMU_USB2_AHB      16
+#define RESET_APMU_USB2_VCC      17
+#define RESET_APMU_USB2_PHY      18
+#define RESET_APMU_USB3_A_AHB    19
+#define RESET_APMU_USB3_A_VCC    20
+#define RESET_APMU_QSPI          21
+#define RESET_APMU_QSPI_BUS      22
+#define RESET_APMU_DMA           23
+#define RESET_APMU_AES_WTM       24
+#define RESET_APMU_MCB_DCLK      25
+#define RESET_APMU_MCB_ACLK      26
+#define RESET_APMU_VPU           27
+#define RESET_APMU_DTC           28
+#define RESET_APMU_GPU           29
+#define RESET_APMU_ALZO          30
+#define RESET_APMU_MC            31
+#define RESET_APMU_CPU0_POP      32
+#define RESET_APMU_CPU0_SW       33
+#define RESET_APMU_CPU1_POP      34
+#define RESET_APMU_CPU1_SW       35
+#define RESET_APMU_CPU2_POP      36
+#define RESET_APMU_CPU2_SW       37
+#define RESET_APMU_CPU3_POP      38
+#define RESET_APMU_CPU3_SW       39
+#define RESET_APMU_C0_MPSUB_SW   40
+#define RESET_APMU_CPU4_POP      41
+#define RESET_APMU_CPU4_SW       42
+#define RESET_APMU_CPU5_POP      43
+#define RESET_APMU_CPU5_SW       44
+#define RESET_APMU_CPU6_POP      45
+#define RESET_APMU_CPU6_SW       46
+#define RESET_APMU_CPU7_POP      47
+#define RESET_APMU_CPU7_SW       48
+#define RESET_APMU_C1_MPSUB_SW   49
+#define RESET_APMU_MPSUB_DBG     50
+#define RESET_APMU_USB3_A_PHY    51	/* USB3 A */
+#define RESET_APMU_USB3_B_AHB    52
+#define RESET_APMU_DSI4LN2_ESCCLK     53
+#define RESET_APMU_DSI4LN2_LCD_SW     54
+#define RESET_APMU_DSI4LN2_LCD_MCLK   55
+#define RESET_APMU_DSI4LN2_LCD_DSCCLK 56
+#define RESET_APMU_DSI4LN2_DPU_ACLK   57
+#define RESET_APMU_DPU_ACLK      58
+#define RESET_APMU_UFS_ACLK      59
+#define RESET_APMU_EDP0          60
+#define RESET_APMU_EDP1          61
+#define RESET_APMU_USB3_B_VCC    62	/* USB3 B */
+#define RESET_APMU_USB3_B_PHY    63
+#define RESET_APMU_USB3_C_AHB    64
+#define RESET_APMU_USB3_C_VCC    65
+#define RESET_APMU_USB3_C_PHY    66
+#define RESET_APMU_EMAC0         67
+#define RESET_APMU_EMAC1         68
+#define RESET_APMU_EMAC2         69
+#define RESET_APMU_ESPI_MCLK     70
+#define RESET_APMU_ESPI_SCLK     71
+#define RESET_APMU_USB3_D_AHB    72	/* USB3 D */
+#define RESET_APMU_USB3_D_VCC    73
+#define RESET_APMU_USB3_D_PHY    74
+#define RESET_APMU_UCIE_IP       75
+#define RESET_APMU_UCIE_HOT      76
+#define RESET_APMU_UCIE_MON      77
+#define RESET_APMU_RCPU_AUDIO_SYS     78
+#define RESET_APMU_RCPU_MCU_CORE      79
+#define RESET_APMU_RCPU_AUDIO_APMU    80
+#define RESET_APMU_PCIE_A_DBI    81
+#define RESET_APMU_PCIE_A_SLAVE  82
+#define RESET_APMU_PCIE_A_MASTER 83
+#define RESET_APMU_PCIE_B_DBI    84
+#define RESET_APMU_PCIE_B_SLAVE  85
+#define RESET_APMU_PCIE_B_MASTER 86
+#define RESET_APMU_PCIE_C_DBI    87
+#define RESET_APMU_PCIE_C_SLAVE  88
+#define RESET_APMU_PCIE_C_MASTER 89
+#define RESET_APMU_PCIE_D_DBI    90
+#define RESET_APMU_PCIE_D_SLAVE  91
+#define RESET_APMU_PCIE_D_MASTER 92
+#define RESET_APMU_PCIE_E_DBI    93
+#define RESET_APMU_PCIE_E_SLAVE  94
+#define RESET_APMU_PCIE_E_MASTER 95
+
+/* DCIU resets*/
+#define RESET_DCIU_HDMA          0
+#define RESET_DCIU_DMA350        1
+#define RESET_DCIU_DMA350_0      2
+#define RESET_DCIU_DMA350_1      3
+#define RESET_DCIU_AXIDMA0       4
+#define RESET_DCIU_AXIDMA1       5
+#define RESET_DCIU_AXIDMA2       6
+#define RESET_DCIU_AXIDMA3       7
+#define RESET_DCIU_AXIDMA4       8
+#define RESET_DCIU_AXIDMA5       9
+#define RESET_DCIU_AXIDMA6       10
+#define RESET_DCIU_AXIDMA7       11
+
+#endif /* _DT_BINDINGS_RESET_SPACEMIT_K3_H_ */
diff --git a/include/dt-bindings/sound/audio-jack-events.h b/include/dt-bindings/sound/audio-jack-events.h
deleted file mode 100644
index 1b29b295126..00000000000
--- a/include/dt-bindings/sound/audio-jack-events.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __AUDIO_JACK_EVENTS_H
-#define __AUDIO_JACK_EVENTS_H
-
-#define JACK_HEADPHONE		1
-#define JACK_MICROPHONE		2
-#define JACK_LINEOUT		3
-#define JACK_LINEIN		4
-
-#endif /* __AUDIO_JACK_EVENTS_H */
diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
index ddc7302a510..350f98178b2 100644
--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
@@ -7,6 +7,9 @@
 #ifndef __MEDIATEK_LVTS_DT_H
 #define __MEDIATEK_LVTS_DT_H
 
+#define MT7987_CPU		0
+#define MT7987_ETH2P5G		1
+
 #define MT7988_CPU_0		0
 #define MT7988_CPU_1		1
 #define MT7988_ETH2P5G_0	2
@@ -80,4 +83,30 @@
 #define MT8192_AP_MD1   15
 #define MT8192_AP_MD2   16
 
+#define MT8196_MCU_MEDIUM_CPU6_0        0
+#define MT8196_MCU_MEDIUM_CPU6_1        1
+#define MT8196_MCU_DSU2                 2
+#define MT8196_MCU_DSU3                 3
+#define MT8196_MCU_LITTLE_CPU3          4
+#define MT8196_MCU_LITTLE_CPU0          5
+#define MT8196_MCU_LITTLE_CPU1          6
+#define MT8196_MCU_LITTLE_CPU2          7
+#define MT8196_MCU_MEDIUM_CPU4_0        8
+#define MT8196_MCU_MEDIUM_CPU4_1        9
+#define MT8196_MCU_MEDIUM_CPU5_0        10
+#define MT8196_MCU_MEDIUM_CPU5_1        11
+#define MT8196_MCU_DSU0                 12
+#define MT8196_MCU_DSU1                 13
+#define MT8196_MCU_BIG_CPU7_0           14
+#define MT8196_MCU_BIG_CPU7_1           15
+
+#define MT8196_AP_TOP0                  0
+#define MT8196_AP_TOP1                  1
+#define MT8196_AP_TOP2                  2
+#define MT8196_AP_TOP3                  3
+#define MT8196_AP_BOT0                  4
+#define MT8196_AP_BOT1                  5
+#define MT8196_AP_BOT2                  6
+#define MT8196_AP_BOT3                  7
+
 #endif /* __MEDIATEK_LVTS_DT_H */
-- 
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