From e6027e6f45ff6924ee5b068f3fff628ecaacadc9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 23 Apr 2018 20:24:06 +0200 Subject: ARM: rmobile: Update H2 Lager The H2 Lager port was broken since some time. This patch updates the H2 Lager port to use modern frameworks, DM, DT probing, SPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- include/configs/lager.h | 65 +++++++++++++++---------------------------------- 1 file changed, 19 insertions(+), 46 deletions(-) (limited to 'include') diff --git a/include/configs/lager.h b/include/configs/lager.h index 97f7b2c7e78..3bd4d51fc30 100644 --- a/include/configs/lager.h +++ b/include/configs/lager.h @@ -15,14 +15,9 @@ #include "rcar-gen2-common.h" -/* STACK */ -#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT) -#define CONFIG_SYS_INIT_SP_ADDR 0xB003FFFC -#else -#define CONFIG_SYS_INIT_SP_ADDR 0xE827FFFC -#endif -#define STACK_AREA_SIZE 0xC000 -#define LOW_LEVEL_MERAM_STACK \ +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 +#define LOW_LEVEL_MERAM_STACK \ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ @@ -32,60 +27,38 @@ /* SCIF */ -/* SPI */ +/* FLASH */ #define CONFIG_SPI /* SH Ether */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0x1 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_RCAR -#define CONFIG_SYS_RCAR_I2C0_SPEED 400000 -#define CONFIG_SYS_RCAR_I2C1_SPEED 400000 -#define CONFIG_SYS_RCAR_I2C2_SPEED 400000 -#define CONFIG_SYS_RCAR_I2C3_SPEED 400000 -#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 - -#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ - /* Board Clock */ #define RMOBILE_XTAL_CLK 20000000u #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK -#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ -#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) -#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2) -#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15) -#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12) +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) #define CONFIG_SYS_TMU_CLK_DIV 4 -/* USB */ -#define CONFIG_USB_EHCI_RMOBILE -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 - -/* MMC */ -#define CONFIG_SH_MMCIF_ADDR 0xEE220000 -#define CONFIG_SH_MMCIF_CLK 97500000 - -/* Module stop status bits */ -/* INTC-RT */ -#define CONFIG_SMSTP0_ENA 0x00400000 -/* MSIF */ -#define CONFIG_SMSTP2_ENA 0x00002000 -/* INTC-SYS, IRQC */ -#define CONFIG_SMSTP4_ENA 0x00000180 -/* SCIF0 */ -#define CONFIG_SMSTP7_ENA 0x00200000 - -/* SDHI */ -#define CONFIG_SH_SDHI_FREQ 97500000 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" + +/* SPL support */ +#define CONFIG_SPL_TEXT_BASE 0xe6300000 +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF0 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif #endif /* __LAGER_H */ -- cgit v1.2.3 From 49aefe300a6f52e49eeb66c9edbc45b688518fdd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 23 Apr 2018 20:24:10 +0200 Subject: ARM: rmobile: Update M2-N Gose The M2-N Gose port was broken since some time. This patch updates the M2-N Gose port to use modern frameworks, DM, DT probing, SPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- include/configs/gose.h | 64 +++++++++++++++++--------------------------------- 1 file changed, 21 insertions(+), 43 deletions(-) (limited to 'include') diff --git a/include/configs/gose.h b/include/configs/gose.h index 3531621910e..af6189e4c1f 100644 --- a/include/configs/gose.h +++ b/include/configs/gose.h @@ -14,21 +14,15 @@ #include "rcar-gen2-common.h" -/* STACK */ -#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) -#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC -#else -#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC -#endif - -#define STACK_AREA_SIZE 0xC000 -#define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) /* MEMORY */ #define RCAR_GEN2_SDRAM_BASE 0x40000000 -#define RCAR_GEN2_SDRAM_SIZE 0x40000000 -#define RCAR_GEN2_UBOOT_SDRAM_SIZE 0x20000000 +#define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024) /* SCIF */ @@ -41,45 +35,29 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 /* Board Clock */ #define RMOBILE_XTAL_CLK 20000000u #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) -#define CONFIG_SYS_TMU_CLK_DIV 4 -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 -#define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SYS_I2C_SH_SPEED1 400000 -#define CONFIG_SYS_I2C_SH_SPEED2 400000 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 10000000 - -#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ - -/* USB */ -#define CONFIG_USB_EHCI_RMOBILE -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* Module stop status bits */ -/* INTC-RT */ -#define CONFIG_SMSTP0_ENA 0x00400000 -/* MSIF */ -#define CONFIG_SMSTP2_ENA 0x00002000 -/* INTC-SYS, IRQC */ -#define CONFIG_SMSTP4_ENA 0x00000180 -/* SCIF0 */ -#define CONFIG_SMSTP7_ENA 0x00200000 +#define CONFIG_SYS_TMU_CLK_DIV 4 -/* SDHI */ -#define CONFIG_SH_SDHI_FREQ 97500000 +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" + +/* SPL support */ +#define CONFIG_SPL_TEXT_BASE 0xe6300000 +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF0 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif #endif /* __GOSE_H */ -- cgit v1.2.3 From bb6d2ff2ac96a6b3d83f7f65483a2f8087d1f902 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 23 Apr 2018 20:24:16 +0200 Subject: ARM: rmobile: Update E2 Alt The E2 Alt port was broken since some time. This patch updates the E2 Alt port to use modern frameworks, DM, DT probing, SPL for the preloading and puts it on par with the M2 Porter board. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- include/configs/alt.h | 71 ++++++++++++++++----------------------------------- 1 file changed, 22 insertions(+), 49 deletions(-) (limited to 'include') diff --git a/include/configs/alt.h b/include/configs/alt.h index d6236870b9d..619660b2bd8 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -15,12 +15,8 @@ #include "rcar-gen2-common.h" -#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) -#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC -#else -#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC -#endif -#define STACK_AREA_SIZE 0xC000 +#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 +#define STACK_AREA_SIZE 0x00100000 #define LOW_LEVEL_MERAM_STACK \ (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) @@ -41,52 +37,29 @@ #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII #define CONFIG_SH_ETHER_CACHE_WRITEBACK #define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 #define CONFIG_BITBANGMII #define CONFIG_BITBANGMII_MULTI /* Board Clock */ -#define RMOBILE_XTAL_CLK 20000000u -#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK -#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ -#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) -#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) - -#define CONFIG_SYS_TMU_CLK_DIV 4 - -/* i2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 -#define CONFIG_SYS_I2C_SH_SPEED0 400000 -#define CONFIG_SYS_I2C_SH_SPEED1 400000 -#define CONFIG_SYS_I2C_SH_SPEED2 400000 -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 10000000 - -#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ - -/* USB */ -#define CONFIG_USB_EHCI_RMOBILE -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* MMCIF */ -#define CONFIG_SH_MMCIF_ADDR 0xee200000 -#define CONFIG_SH_MMCIF_CLK 48000000 - -/* Module stop status bits */ -/* INTC-RT */ -#define CONFIG_SMSTP0_ENA 0x00400000 -/* MSIF */ -#define CONFIG_SMSTP2_ENA 0x00002000 -/* INTC-SYS, IRQC */ -#define CONFIG_SMSTP4_ENA 0x00000180 -/* SCIF2 */ -#define CONFIG_SMSTP7_ENA 0x00080000 - -/* SDHI */ -#define CONFIG_SH_SDHI_FREQ 97500000 +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) + +#define CONFIG_SYS_TMU_CLK_DIV 4 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" + +/* SPL support */ +#define CONFIG_SPL_TEXT_BASE 0xe6300000 +#define CONFIG_SPL_STACK 0xe6340000 +#define CONFIG_SPL_MAX_SIZE 0x4000 +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_CONS_SCIF2 +#define CONFIG_SH_SCIF_CLK_FREQ 65000000 +#endif #endif /* __ALT_H */ -- cgit v1.2.3