From e07f4a8033b6270b8103049adb6456f660ff4a89 Mon Sep 17 00:00:00 2001 From: Ricardo Ribalda Delgado Date: Mon, 1 Sep 2008 13:09:39 -0400 Subject: ppc44x: Unification of virtex5 pp440 boards This patch provides an unificated way of handling xilinx v5 ppc440 boards. It unificates 3 different things: 1) Source code A new board called ppc440-generic has been created. This board includes a generic tlb initialization (Maps the whole memory into virtual) and defines board_pre_init, checkboard, initdram and get_sys_info weakly, so, they can be replaced by specific functions. If a new board needs to redefine any of the previous functions (specific initialization) it can create a new directory with the specific initializations needed. (see the example ml507 board). 2) Configuration file Common configurations are located under configs/xilinx-ppc440.h, this header file interpretes the xparameters file generated by EDK and configurates u-boot in correspondence. Example: if there is a Temac, allows CMD_CONFIG_NET Specific configuration are located under specific configuration file. (see the example ml507 board) 3) Makefile Some work has been done in order to not duplicate work in the Main Makefile. Please see the attached code. In order to support new boards they can be implemented in the next way: a) Simple Generic Board (90% of the time) Using EDK generates a new xparameters.h file, replace ppc440-generic/xparameters.h and run make xilinx-ppc440-generic_config && make b) Simple Boards with special u-boot parameters (9 % of the time) Create a new file under configs for it (use ml507.h as example) and change your paramaters. Create a new Makefile paragraph and compile c) Complex boards (1% of the time) Create a new folder for the board, like the ml507 Finally, it adds support for the Avnet FX30T Evaluation board, following the new generic structure: Cheap board by Avnet for evaluating the Virtex5 FX technology. This patch adds support for: - UartLite - 16MB Flash - 64MB RAM Prior using U-boot in this board, read carefully the ERRATA by Avnet to solve some memory initialization issues. Signed-off-by: Ricardo Ribalda Delgado Signed-off-by: Stefan Roese --- include/configs/ml507.h | 91 +++------------------------ include/configs/v5fx30teval.h | 49 +++++++++++++++ include/configs/xilinx-ppc440-generic.h | 49 +++++++++++++++ include/configs/xilinx-ppc440.h | 106 ++++++++++++++++++++++++++++++++ 4 files changed, 213 insertions(+), 82 deletions(-) create mode 100644 include/configs/v5fx30teval.h create mode 100644 include/configs/xilinx-ppc440-generic.h create mode 100644 include/configs/xilinx-ppc440.h (limited to 'include') diff --git a/include/configs/ml507.h b/include/configs/ml507.h index f8cd499985b..37d93bb3c70 100644 --- a/include/configs/ml507.h +++ b/include/configs/ml507.h @@ -17,106 +17,33 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* -#define DEBUG -#define ET_DEBUG -*/ - /*CPU*/ -#define CONFIG_XILINX_ML507 1 -#define CONFIG_XILINX_440 1 + +/*CPU*/ #define CONFIG_440 1 -#define CONFIG_4xx 1 +#define CONFIG_XILINX_ML507 1 #include "../board/xilinx/ml507/xparameters.h" /*Mem Map*/ -#define CFG_SDRAM_BASE 0x0 #define CFG_SDRAM_SIZE_MB 256 -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN ( 192 * 1024 ) -#define CFG_MALLOC_LEN ( CFG_ENV_SIZE + 128 * 1024 ) - -/*Uart*/ -#define CONFIG_XILINX_UARTLITE -#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE -#define CFG_BAUDRATE_TABLE { XPAR_UARTLITE_0_BAUDRATE } -#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR - -/*Cmd*/ -#include -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_ELF -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_JFFS2 -#define CONFIG_JFFS2_CMDLINE -#undef CONFIG_CMD_I2C -#undef CONFIG_CMD_DTT -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_PING -#undef CONFIG_CMD_DHCP -#undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_IMLS /*Env*/ -#define CFG_ENV_IS_IN_FLASH +#define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 0x20000 #define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_OFFSET 0x340000 -#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET) +#define CFG_ENV_OFFSET 0x340000 +#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET) /*Misc*/ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "board:/# " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CFG_PBSIZE ( CFG_CBSIZE + sizeof( CFG_PROMPT ) + 16 ) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ -#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00400000 /* default load address */ -#define CFG_EXTBDINFO 1 /* Extended board_into (bd_t) */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ -#define CONFIG_CMDLINE_EDITING /* add command line history */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ -#define CONFIG_LOOPW /* enable loopw command */ -#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_VERSION_VARIABLE /* include version env variable */ -#define CFG_CONSOLE_INFO_QUIET /* don't print console @ startup */ -#define CFG_HUSH_PARSER /* Use the HUSH parser */ -#define CFG_PROMPT_HUSH_PS2 "> " -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ -#define CFG_BOOTMAPSZ ( 8 << 20 ) /* Initial Memory map for Linux */ +#define CFG_PROMPT "ml507:/# " /* Monitor Command Prompt */ #define CONFIG_PREBOOT "echo U-Boot is up and runnining;" -/*Stack*/ -#define CFG_INIT_RAM_ADDR 0x800000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CFG_GBL_DATA_OFFSET ( CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE ) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -/*Speed*/ -#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ - /*Flash*/ -#define CFG_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR #define CFG_FLASH_SIZE (32*1024*1024) -#define CFG_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CFG_FLASH_EMPTY_INFO 1 -#define CFG_MAX_FLASH_BANKS 1 #define CFG_MAX_FLASH_SECT 259 -#define CFG_FLASH_PROTECTION #define MTDIDS_DEFAULT "nor0=ml507-flash" #define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)" +/*Generic Configs*/ +#include #endif /* __CONFIG_H */ diff --git a/include/configs/v5fx30teval.h b/include/configs/v5fx30teval.h new file mode 100644 index 00000000000..67d8d7f6314 --- /dev/null +++ b/include/configs/v5fx30teval.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*CPU*/ +#define CONFIG_440 1 +#define CONFIG_XILINX_ML507 1 +#include "../board/avnet/v5fx30teval/xparameters.h" + +/*Mem Map*/ +#define CFG_SDRAM_SIZE_MB 64 + +/*Env*/ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x20000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_OFFSET 0x1A0000 +#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET) + +/*Misc*/ +#define CFG_PROMPT "v5fx30t:/# " /* Monitor Command Prompt */ +#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" + +/*Flash*/ +#define CFG_FLASH_SIZE (16*1024*1024) +#define CFG_MAX_FLASH_SECT 131 +#define MTDIDS_DEFAULT "nor0=v5fx30t-flash" +#define MTDPARTS_DEFAULT "mtdparts=v5fx30t-flash:-(user)" + +/*Generic Configs*/ +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/xilinx-ppc440-generic.h b/include/configs/xilinx-ppc440-generic.h new file mode 100644 index 00000000000..4e8080bf6bf --- /dev/null +++ b/include/configs/xilinx-ppc440-generic.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*CPU*/ +#define CONFIG_440 1 +#define CONFIG_XILINX_PPC440_GENERIC 1 +#include "../board/xilinx/ppc440-generic/xparameters.h" + +/*Mem Map*/ +#define CFG_SDRAM_SIZE_MB 256 + +/*Env*/ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x20000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_OFFSET 0x340000 +#define CFG_ENV_ADDR (XPAR_FLASH_MEM0_BASEADDR+CFG_ENV_OFFSET) + +/*Misc*/ +#define CFG_PROMPT "board:/# " /* Monitor Command Prompt */ +#define CONFIG_PREBOOT "echo U-Boot is up and runnining;" + +/*Flash*/ +#define CFG_FLASH_SIZE (32*1024*1024) +#define CFG_MAX_FLASH_SECT 259 +#define MTDIDS_DEFAULT "nor0=ml507-flash" +#define MTDPARTS_DEFAULT "mtdparts=ml507-flash:-(user)" + +/*Generic Configs*/ +#include + +#endif /* __CONFIG_H */ diff --git a/include/configs/xilinx-ppc440.h b/include/configs/xilinx-ppc440.h new file mode 100644 index 00000000000..40293cd8429 --- /dev/null +++ b/include/configs/xilinx-ppc440.h @@ -0,0 +1,106 @@ +/* + * (C) Copyright 2008 + * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@uam.es + * This work has been supported by: QTechnology http://qtec.com/ + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . +*/ + +#ifndef __CONFIG_GEN_H +#define __CONFIG_GEN_H +/* +#define DEBUG +#define ET_DEBUG +*/ + /*CPU*/ +#define CONFIG_XILINX_440 1 +#define CONFIG_440 1 +#define CONFIG_4xx 1 + +/*Mem Map*/ +#define CFG_SDRAM_BASE 0x0 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (192 * 1024) +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024) + +/*Uart*/ +#define CONFIG_XILINX_UARTLITE +#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE +#define CFG_BAUDRATE_TABLE { XPAR_UARTLITE_0_BAUDRATE } +#define CONFIG_SERIAL_BASE XPAR_UARTLITE_0_BASEADDR + +/*Cmd*/ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_JFFS2 +#define CONFIG_JFFS2_CMDLINE +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_PING +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_IMLS + +/*Misc*/ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CFG_LONGHELP /* undef to save memory */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00C00000 /* 4 ... 12 MB in DRAM */ +#define CFG_LOAD_ADDR 0x00400000 /* default load address */ +#define CFG_EXTBDINFO 1 /* Extended board_into (bd_t) */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_LOOPW /* enable loopw command */ +#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE /* include version env variable */ +#define CFG_CONSOLE_INFO_QUIET /* don't print console @ startup */ +#define CFG_HUSH_PARSER /* Use the HUSH parser */ +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ +#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */ + +/*Stack*/ +#define CFG_INIT_RAM_ADDR 0x800000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +/*Speed*/ +#define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ + +/*Flash*/ +#define CFG_FLASH_BASE XPAR_FLASH_MEM0_BASEADDR +#define CFG_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_EMPTY_INFO 1 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_FLASH_PROTECTION + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From f6b6c45840f9b4671d2d97243a12a1f3ffb64765 Mon Sep 17 00:00:00 2001 From: Adam Graham Date: Wed, 3 Sep 2008 12:26:59 -0700 Subject: ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routines Signed-off-by: Adam Graham Signed-off-by: Stefan Roese --- cpu/ppc4xx/44x_spd_ddr2.c | 158 +++++++++++++++++++++++++---------------- cpu/ppc4xx/Makefile | 3 + include/asm-ppc/ppc4xx-sdram.h | 3 +- include/common.h | 21 ++++++ include/configs/kilauea.h | 19 +++++ include/ppc440.h | 13 ---- include/ppc4xx.h | 13 ++++ 7 files changed, 153 insertions(+), 77 deletions(-) (limited to 'include') diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 15250d470da..f1d76840f21 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -60,8 +60,6 @@ "SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \ } while (0) -static inline void ppc4xx_ibm_ddr2_register_dump(void); - #if defined(CONFIG_SPD_EEPROM) /*-----------------------------------------------------------------------------+ @@ -260,62 +258,19 @@ static void program_ecc_addr(unsigned long start_address, unsigned long num_bytes, unsigned long tlb_word2_i_value); #endif +#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) static void program_DQS_calibration(unsigned long *dimm_populated, - unsigned char *iic0_dimm_addr, - unsigned long num_dimm_banks); + unsigned char *iic0_dimm_addr, + unsigned long num_dimm_banks); #ifdef HARD_CODED_DQS /* calibration test with hardvalues */ static void test(void); #else static void DQS_calibration_process(void); #endif +#endif int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); void dcbz_area(u32 start_address, u32 num_bytes); -static u32 mfdcr_any(u32 dcr) -{ - u32 val; - - switch (dcr) { - case SDRAM_R0BAS + 0: - val = mfdcr(SDRAM_R0BAS + 0); - break; - case SDRAM_R0BAS + 1: - val = mfdcr(SDRAM_R0BAS + 1); - break; - case SDRAM_R0BAS + 2: - val = mfdcr(SDRAM_R0BAS + 2); - break; - case SDRAM_R0BAS + 3: - val = mfdcr(SDRAM_R0BAS + 3); - break; - default: - printf("DCR %d not defined in case statement!!!\n", dcr); - val = 0; /* just to satisfy the compiler */ - } - - return val; -} - -static void mtdcr_any(u32 dcr, u32 val) -{ - switch (dcr) { - case SDRAM_R0BAS + 0: - mtdcr(SDRAM_R0BAS + 0, val); - break; - case SDRAM_R0BAS + 1: - mtdcr(SDRAM_R0BAS + 1, val); - break; - case SDRAM_R0BAS + 2: - mtdcr(SDRAM_R0BAS + 2, val); - break; - case SDRAM_R0BAS + 3: - mtdcr(SDRAM_R0BAS + 3, val); - break; - default: - printf("DCR %d not defined in case statement!!!\n", dcr); - } -} - static unsigned char spd_read(uchar chip, uint addr) { unsigned char data[2]; @@ -609,7 +564,11 @@ phys_size_t initdram(int board_type) /*------------------------------------------------------------------ * DQS calibration. *-----------------------------------------------------------------*/ +#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) + DQS_autocalibration(); +#else program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks); +#endif #ifdef CONFIG_DDR_ECC /*------------------------------------------------------------------ @@ -2329,18 +2288,6 @@ static unsigned long is_ecc_enabled(void) return ecc; } -static void blank_string(int size) -{ - int i; - - for (i=0; i>2) +#if !defined(CONFIG_405EX) /* * Memory queue defines */ @@ -293,7 +295,6 @@ #define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */ -#if !defined(CONFIG_405EX) /* * Memory Bank 0-7 configuration */ diff --git a/include/common.h b/include/common.h index a394988b5ce..2516bfd30c0 100644 --- a/include/common.h +++ b/include/common.h @@ -287,6 +287,27 @@ void pciinfo (int, int); #endif #endif +/* + * Prototypes + */ +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) +void blank_string(int); +inline void ppc4xx_ibm_ddr2_register_dump(void); +#if defined(CONFIG_440) +u32 mfdcr_any(u32); +void mtdcr_any(u32, u32); +#endif +#if defined(CONFIG_SPD_EEPROM) +u32 ddr_wrdtr(u32); +u32 ddr_clktr(u32); +void spd_ddr_init_hang(void); +#endif +#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) */ + +#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) +u32 DQS_autocalibration(void); +#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ + int misc_init_f (void); int misc_init_r (void); diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index a475f97e625..f9eaa777725 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -223,6 +223,22 @@ *----------------------------------------------------------------------*/ #define CFG_MBYTES_SDRAM (256) /* 256MB */ +/* + * CONFIG_PPC4xx_DDR_AUTOCALIBRATION + * + * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx + * SDRAM Controller DDR autocalibration values and takes a lot longer + * to run than Method_B. + * (See the Method_A and Method_B algorithm discription in the file: + * cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c) + * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A + * + * DDR Autocalibration Method_B is the default. + */ +#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */ +#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */ +#undef CONFIG_PPC4xx_DDR_METHOD_A + #define CFG_SDRAM0_MB0CF_BASE (( 0 << 20) + CFG_SDRAM_BASE) /* DDR1/2 SDRAM Device Control Register Data Values */ @@ -386,6 +402,9 @@ #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ #define CONFIG_PHY1_ADDR 2 +/* Debug messages for the DDR autocalibration */ +#define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */ + /* * Default environment variables */ diff --git a/include/ppc440.h b/include/ppc440.h index 3584fd24e82..be8d3ffef79 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -2064,19 +2064,6 @@ #ifndef __ASSEMBLY__ -static inline u32 get_mcsr(void) -{ - u32 val; - - asm volatile("mfspr %0, 0x23c" : "=r" (val) :); - return val; -} - -static inline void set_mcsr(u32 val) -{ - asm volatile("mtspr 0x23c, %0" : "=r" (val) :); -} - #endif /* _ASMLANGUAGE */ #endif /* __PPC440_H__ */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 59a3b06b71c..e216663a86d 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -203,6 +203,19 @@ typedef struct unsigned long pllPlbDiv; } PPC4xx_SYS_INFO; +static inline u32 get_mcsr(void) +{ + u32 val; + + asm volatile("mfspr %0, 0x23c" : "=r" (val) :); + return val; +} + +static inline void set_mcsr(u32 val) +{ + asm volatile("mtspr 0x23c, %0" : "=r" (val) :); +} + #endif /* __ASSEMBLY__ */ #endif /* __PPC4XX_H__ */ -- cgit v1.3.1 From 78d78236896d62bb8ca7302af38d8f1493eb2651 Mon Sep 17 00:00:00 2001 From: Victor Gallardo Date: Thu, 4 Sep 2008 23:49:36 -0700 Subject: ppc4xx: Add support for GPCS, SGMII and M88E1112 PHY This patch adds GPCS, SGMII and M88E1112 PHY support for the AMCC PPC460GT/EX processors. Signed-off-by: Victor Gallardo Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 159 +++++++++++++++++++++++++++++++++++++++++++++++++- cpu/ppc4xx/miiphy.c | 41 ++++++++++++- include/ppc4xx_enet.h | 3 + 3 files changed, 198 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 8a3833513e2..071ac0a9677 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -198,6 +198,7 @@ #define BI_PHYMODE_RMII 8 #endif #endif +#define BI_PHYMODE_SGMII 9 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ @@ -216,6 +217,52 @@ #define MAL_RX_CHAN_MUL 1 #endif +/*--------------------------------------------------------------------+ + * Fixed PHY (PHY-less) support for Ethernet Ports. + *--------------------------------------------------------------------*/ + +/* + * Some boards do not have a PHY for each ethernet port. These ports + * are known as Fixed PHY (or PHY-less) ports. For such ports, set + * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and + * then define CFG_FIXED_PHY_PORTS to define what the speed and + * duplex should be for these ports in the board configuration + * file. + * + * For Example: + * #define CONFIG_FIXED_PHY 0xFFFFFFFF + * + * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY + * #define CONFIG_PHY1_ADDR 1 + * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY + * #define CONFIG_PHY3_ADDR 3 + * + * #define CFG_FIXED_PHY_PORT(devnum,speed,duplex) \ + * {devnum, speed, duplex}, + * + * #define CFG_FIXED_PHY_PORTS \ + * CFG_FIXED_PHY_PORT(0,1000,FULL) \ + * CFG_FIXED_PHY_PORT(2,100,HALF) + */ + +#ifndef CONFIG_FIXED_PHY +#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */ +#endif + +#ifndef CFG_FIXED_PHY_PORTS +#define CFG_FIXED_PHY_PORTS /* default is an empty array */ +#endif + +struct fixed_phy_port { + unsigned int devnum; /* ethernet port */ + unsigned int speed; /* specified speed 10,100 or 1000 */ + unsigned int duplex; /* specified duplex FULL or HALF */ +}; + +static const struct fixed_phy_port fixed_phy_port[] = { + CFG_FIXED_PHY_PORTS /* defined in board configuration file */ +}; + /*-----------------------------------------------------------------------------+ * Global variables. TX and RX descriptors and buffers. *-----------------------------------------------------------------------------*/ @@ -611,8 +658,17 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) #if defined(CONFIG_460EX) mode = 9; + mfsdr(SDR0_ETH_CFG, eth_cfg); + if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) && + ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0)) + mode = 11; /* config SGMII */ #else mode = 10; + mfsdr(SDR0_ETH_CFG, eth_cfg); + if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) && + ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) && + ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0)) + mode = 12; /* config SGMII */ #endif /* TODO: @@ -635,6 +691,8 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) /* * Right now only 2*RGMII is supported. Please extend when needed. * sr - 2008-02-19 + * Add SGMII support. + * vg - 2008-07-28 */ switch (mode) { case 1: @@ -761,6 +819,20 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) bis->bi_phymode[2] = BI_PHYMODE_RGMII; bis->bi_phymode[3] = BI_PHYMODE_RGMII; break; + case 11: + /* 2 SGMII - 460EX */ + bis->bi_phymode[0] = BI_PHYMODE_SGMII; + bis->bi_phymode[1] = BI_PHYMODE_SGMII; + bis->bi_phymode[2] = BI_PHYMODE_NONE; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; + case 12: + /* 3 SGMII - 460GT */ + bis->bi_phymode[0] = BI_PHYMODE_SGMII; + bis->bi_phymode[1] = BI_PHYMODE_SGMII; + bis->bi_phymode[2] = BI_PHYMODE_SGMII; + bis->bi_phymode[3] = BI_PHYMODE_NONE; + break; default: break; } @@ -945,6 +1017,48 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ +#if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \ + defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR) + if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) { + /* + * In SGMII mode, GPCS access is needed for + * communication with the internal SGMII SerDes. + */ + switch (devnum) { +#if defined(CONFIG_GPCS_PHY_ADDR) + case 0: + reg = CONFIG_GPCS_PHY_ADDR; + break; +#endif +#if defined(CONFIG_GPCS_PHY1_ADDR) + case 1: + reg = CONFIG_GPCS_PHY1_ADDR; + break; +#endif +#if defined(CONFIG_GPCS_PHY2_ADDR) + case 2: + reg = CONFIG_GPCS_PHY2_ADDR; + break; +#endif +#if defined(CONFIG_GPCS_PHY3_ADDR) + case 3: + reg = CONFIG_GPCS_PHY3_ADDR; + break; +#endif + } + + mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); + mode_reg |= EMAC_M1_MF_1000GPCS | EMAC_M1_IPPA_SET(reg); + out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); + + /* Configure GPCS interface to recommended setting for SGMII */ + miiphy_reset(dev->name, reg); + miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */ + miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */ + miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */ + } +#endif /* defined(CONFIG_GPCS_PHY_ADDR) */ + /* wait for PHY to complete auto negotiation */ reg_short = 0; #ifndef CONFIG_CS8952_PHY @@ -974,6 +1088,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) bis->bi_phynum[devnum] = reg; + if (reg == CONFIG_FIXED_PHY) + goto get_speed; + #if defined(CONFIG_PHY_RESET) /* * Reset the phy, only if its the first time through @@ -986,6 +1103,27 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) miiphy_write (dev->name, reg, 0x09, 0x0e00); miiphy_write (dev->name, reg, 0x04, 0x01e1); #endif +#if defined(CONFIG_M88E1112_PHY) + if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) { + /* + * Marvell 88E1112 PHY needs to have the SGMII MAC + * interace (page 2) properly configured to + * communicate with the 460EX/GT GPCS interface. + */ + + /* Set access to Page 2 */ + miiphy_write(dev->name, reg, 0x16, 0x0002); + + miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */ + miiphy_read(dev->name, reg, 0x1a, ®_short); + reg_short |= 0x8000; /* bypass Auto-Negotiation */ + miiphy_write(dev->name, reg, 0x1a, reg_short); + miiphy_reset(dev->name, reg); /* reset MAC interface */ + + /* Reset access to Page 0 */ + miiphy_write(dev->name, reg, 0x16, 0x0000); + } +#endif /* defined(CONFIG_M88E1112_PHY) */ miiphy_reset (dev->name, reg); #if defined(CONFIG_440GX) || \ @@ -1080,8 +1218,25 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) } #endif /* #ifndef CONFIG_CS8952_PHY */ - speed = miiphy_speed (dev->name, reg); - duplex = miiphy_duplex (dev->name, reg); +get_speed: + if (reg == CONFIG_FIXED_PHY) { + for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) { + if (devnum == fixed_phy_port[i].devnum) { + speed = fixed_phy_port[i].speed; + duplex = fixed_phy_port[i].duplex; + break; + } + } + + if (i == ARRAY_SIZE(fixed_phy_port)) { + printf("ERROR: PHY (%s) not configured correctly!\n", + dev->name); + return -1; + } + } else { + speed = miiphy_speed(dev->name, reg); + duplex = miiphy_duplex(dev->name, reg); + } if (hw_p->print_speed) { hw_p->print_speed = 0; diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index c8827201e98..d303598118d 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -180,8 +180,10 @@ int phy_setup_aneg (char *devname, unsigned char addr) * * sr: Currently on 460EX only EMAC0 works with MDIO, so we always * return EMAC0 offset here + * vg: For 460EX/460GT if internal GPCS PHY address is specified + * return appropriate EMAC offset */ -unsigned int miiphy_getemac_offset (void) +unsigned int miiphy_getemac_offset(u8 addr) { #if (defined(CONFIG_440) && \ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ @@ -233,6 +235,39 @@ unsigned int miiphy_getemac_offset (void) return 0x100; #endif +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + u32 mode_reg; + u32 eoffset = 0; + + switch (addr) { +#if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR) + case CONFIG_GPCS_PHY1_ADDR: + mode_reg = in_be32((void *)EMAC_M1 + 0x100); + if (addr == EMAC_M1_IPPA_GET(mode_reg)) + eoffset = 0x100; + break; +#endif +#if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR) + case CONFIG_GPCS_PHY2_ADDR: + mode_reg = in_be32((void *)EMAC_M1 + 0x300); + if (addr == EMAC_M1_IPPA_GET(mode_reg)) + eoffset = 0x300; + break; +#endif +#if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR) + case CONFIG_GPCS_PHY3_ADDR: + mode_reg = in_be32((void *)EMAC_M1 + 0x400); + if (addr == EMAC_M1_IPPA_GET(mode_reg)) + eoffset = 0x400; + break; +#endif + default: + eoffset = 0; + break; + } + return eoffset; +#endif + return 0; #endif } @@ -262,7 +297,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value) u32 emac_reg; u32 sta_reg; - emac_reg = miiphy_getemac_offset(); + emac_reg = miiphy_getemac_offset(addr); /* wait for completion */ if (emac_miiphy_wait(emac_reg) != 0) @@ -311,7 +346,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg, unsigned long sta_reg; unsigned long emac_reg; - emac_reg = miiphy_getemac_offset (); + emac_reg = miiphy_getemac_offset(addr); if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0) return -1; diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index b74c6fcafde..00669a717aa 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -376,6 +376,7 @@ typedef struct emac_4xx_hw_st { #define EMAC_M1_APP (0x08000000) #define EMAC_M1_RSVD (0x06000000) #define EMAC_M1_IST (0x01000000) +#define EMAC_M1_MF_1000GPCS (0x00C00000) #define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ #define EMAC_M1_MF_100MBPS (0x00400000) #define EMAC_M1_RFS_MASK (0x00380000) @@ -394,6 +395,8 @@ typedef struct emac_4xx_hw_st { #define EMAC_M1_MWSW (0x00007000) #define EMAC_M1_JUMBO_ENABLE (0x00000800) #define EMAC_M1_IPPA (0x000007c0) +#define EMAC_M1_IPPA_SET(id) (((id) & 0x1f) << 6) +#define EMAC_M1_IPPA_GET(id) (((id) >> 6) & 0x1f) #define EMAC_M1_OBCI_GT100 (0x00000020) #define EMAC_M1_OBCI_100 (0x00000018) #define EMAC_M1_OBCI_83 (0x00000010) -- cgit v1.3.1 From f071f01fd09e9bf1cf09de37a7416aacce71bae1 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 8 Sep 2008 10:01:48 +0200 Subject: ppc4xx: Remove CONFIG_CS8952_PHY define Since this define is only used on one board that was never really in production, removing this compile time option doesn't hurt and makes the code more readable. Signed-off-by: Stefan Roese --- cpu/ppc4xx/4xx_enet.c | 2 -- include/configs/PIP405.h | 1 - 2 files changed, 3 deletions(-) (limited to 'include') diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 52486fd7d9a..6d4d043e041 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -1187,7 +1187,6 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) } #endif /* defined(CONFIG_PHY_RESET) */ -#if !defined(CONFIG_CS8952_PHY) miiphy_read (dev->name, reg, PHY_BMSR, ®_short); /* @@ -1215,7 +1214,6 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) puts (" done\n"); udelay (500000); /* another 500 ms (results in faster booting) */ } -#endif /* !defined(CONFIG_CS8952_PHY) */ get_speed: if (reg == CONFIG_FIXED_PHY) { diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 2ceda001cab..86ea6c69b93 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -281,7 +281,6 @@ ***********************************************************/ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ -#define CONFIG_CS8952_PHY 1 /* its a CS8952 PHY */ /************************************************************ * RTC ***********************************************************/ -- cgit v1.3.1 From ac53ee8318678190bf3c68da477a84a657d86fb0 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Fri, 5 Sep 2008 15:34:04 +0200 Subject: ppc4xx: Update CPCI405(AB) configuration This patch add FDT support and command line editing capabilities for CPCI405 and CPCI405AB boards. Signed-off-by: Matthias Fuchs Signed-off-by: Stefan Roese --- include/configs/CPCI4052.h | 6 ++++++ include/configs/CPCI405AB.h | 6 ++++++ 2 files changed, 12 insertions(+) (limited to 'include') diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index fd49f569aeb..9ec1721897b 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -146,6 +146,8 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING /* add command line history */ + #define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ @@ -219,6 +221,10 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + /*----------------------------------------------------------------------- * FLASH organization */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 55dd6296de0..78995984f78 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -144,6 +144,8 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING /* add command line history */ + #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ @@ -215,6 +217,10 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + /*----------------------------------------------------------------------- * FLASH organization */ -- cgit v1.3.1 From 5ff889349d2ace13f10c9335e09365fcec8247cc Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 8 Sep 2008 14:11:12 +0200 Subject: ppc4xx: Move ppc4xx specific prototypes to ppc4xx header This patch moves some 4xx specific prototypes out of include common.h to a ppc4xx specific header. Signed-off-by: Stefan Roese --- board/netstal/hcu5/sdram.c | 2 +- include/asm-ppc/ppc4xx-sdram.h | 14 ++++++++++++++ include/common.h | 21 --------------------- 3 files changed, 15 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 66a958c78ae..e5df62ef7ad 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -122,7 +122,7 @@ void sdram_panic(const char *reason) } #ifdef CONFIG_DDR_ECC -static void blank_string(int size) +void blank_string(int size) { int i; diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index a1ef0290e5f..8efa557972e 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -1402,4 +1402,18 @@ #endif /* CONFIG_SDRAM_PPC4xx_DENALI_DDR2 */ +#ifndef __ASSEMBLY__ +/* + * Prototypes + */ +void inline blank_string(int size); +inline void ppc4xx_ibm_ddr2_register_dump(void); +u32 mfdcr_any(u32); +void mtdcr_any(u32, u32); +u32 ddr_wrdtr(u32); +u32 ddr_clktr(u32); +void spd_ddr_init_hang(void); +u32 DQS_autocalibration(void); +#endif /* __ASSEMBLY__ */ + #endif /* _PPC4xx_SDRAM_H_ */ diff --git a/include/common.h b/include/common.h index 2516bfd30c0..a394988b5ce 100644 --- a/include/common.h +++ b/include/common.h @@ -287,27 +287,6 @@ void pciinfo (int, int); #endif #endif -/* - * Prototypes - */ -#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) -void blank_string(int); -inline void ppc4xx_ibm_ddr2_register_dump(void); -#if defined(CONFIG_440) -u32 mfdcr_any(u32); -void mtdcr_any(u32, u32); -#endif -#if defined(CONFIG_SPD_EEPROM) -u32 ddr_wrdtr(u32); -u32 ddr_clktr(u32); -void spd_ddr_init_hang(void); -#endif -#endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) */ - -#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) -u32 DQS_autocalibration(void); -#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ - int misc_init_f (void); int misc_init_r (void); -- cgit v1.3.1 From 4394f9a8c42bb1b0abc4fc04bd582d4db5f8b726 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 8 Sep 2008 22:37:45 +0200 Subject: BMW, PCIPPC2, PCIPPC6, RBC82: fix compile warnings missing doc_probe() prototype. Signed-off-by: Wolfgang Denk --- include/common.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/common.h b/include/common.h index a394988b5ce..33c6e1087d1 100644 --- a/include/common.h +++ b/include/common.h @@ -236,6 +236,9 @@ int autoscript (ulong addr, const char *fit_uname); extern ulong load_addr; /* Default Load Address */ +/* common/cmd_doc.c */ +void doc_probe(unsigned long physadr); + /* common/cmd_nvedit.c */ int env_init (void); void env_relocate (void); -- cgit v1.3.1 From 3221b074a0ab199f6ae47c19cc22f42ddf3ef819 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 9 Sep 2008 00:59:40 +0200 Subject: onenand_uboot: fix warning: 'struct mtd_oob_ops' declared inside parameter list Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/onenand_uboot.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h index 6605e4f218d..e9602574b78 100644 --- a/include/onenand_uboot.h +++ b/include/onenand_uboot.h @@ -15,6 +15,7 @@ #define __UBOOT_ONENAND_H #include +#include struct mtd_info; struct erase_info; -- cgit v1.3.1 From 965de106ba8900372c8b16dc60d5acab7f925e38 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 9 Sep 2008 10:03:47 +0200 Subject: NETTA2: remove empty CONFIG_SHOW_ACTIVITY functions Signed-off-by: Wolfgang Denk --- board/netta2/netta2.c | 14 -------------- include/configs/NETTA2.h | 1 - 2 files changed, 15 deletions(-) (limited to 'include') diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c index a97c14cee77..1dbdde1156d 100644 --- a/board/netta2/netta2.c +++ b/board/netta2/netta2.c @@ -620,20 +620,6 @@ void hw_watchdog_reset(void) #endif -#ifdef CONFIG_SHOW_ACTIVITY - -/* called from timer interrupt every 1/CFG_HZ sec */ -void board_show_activity(ulong timestamp) -{ -} - -/* called when looping */ -void show_activity(int arg) -{ -} - -#endif - #if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE) int overwrite_console(void) { diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index 9a1f1d6da5c..ea5d1604cc9 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -745,7 +745,6 @@ typedef unsigned int led_id_t; /* use board specific hardware */ #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_HW_WATCHDOG -#define CONFIG_SHOW_ACTIVITY /*************************************************************************************************/ -- cgit v1.3.1 From fe876787f8743883ce58fed61525eaa2f34da4c5 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 9 Sep 2008 10:06:44 +0200 Subject: stxxtc: remove empty CONFIG_SHOW_ACTIVITY functions Signed-off-by: Wolfgang Denk --- board/stxxtc/stxxtc.c | 14 -------------- include/configs/stxxtc.h | 1 - 2 files changed, 15 deletions(-) (limited to 'include') diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c index a7503743934..4bb2d6873f1 100644 --- a/board/stxxtc/stxxtc.c +++ b/board/stxxtc/stxxtc.c @@ -599,20 +599,6 @@ void hw_watchdog_reset(void) #endif -#ifdef CONFIG_SHOW_ACTIVITY - -/* called from timer interrupt every 1/CFG_HZ sec */ -void board_show_activity(ulong timestamp) -{ -} - -/* called when looping */ -void show_activity(int arg) -{ -} - -#endif - #if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE) int overwrite_console(void) { diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index 37a52cf7edb..0dc9f8a010d 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -580,7 +580,6 @@ typedef unsigned int led_id_t; /* use board specific hardware */ #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_HW_WATCHDOG -#define CONFIG_SHOW_ACTIVITY /*****************************************************************************/ -- cgit v1.3.1 From e8d18541c6ceab821f75faab031740b33fdbfa4b Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 18 Jul 2008 16:52:23 +0200 Subject: Update Freescale 85xx boards to sys_eeprom.c The new sys_eeprom.c supports both the old CCID EEPROM format and the new NXID format, and so it obsoletes board/freescale/common/cds_eeprom.c. Freescale 86xx boards already use sys_eeprom.c, so this patch migrates the remaining Freescale 85xx boards to use it as well. cds_eeprom.c is deleted. Signed-off-by: Timur Tabi --- board/freescale/common/Makefile | 1 - board/freescale/common/cds_eeprom.c | 60 ------------------------------------- include/configs/MPC8541CDS.h | 9 ++++-- include/configs/MPC8548CDS.h | 9 ++++-- include/configs/MPC8555CDS.h | 10 +++++-- 5 files changed, 22 insertions(+), 67 deletions(-) delete mode 100644 board/freescale/common/cds_eeprom.c (limited to 'include') diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 8584374f387..02a824d9f46 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -30,7 +30,6 @@ endif LIB = $(obj)lib$(VENDOR).a COBJS-${CONFIG_FSL_CADMUS} += cadmus.o -COBJS-${CONFIG_FSL_CDS_EEPROM} += cds_eeprom.o COBJS-${CONFIG_FSL_VIA} += cds_via.o COBJS-${CONFIG_FSL_DIU_FB} += fsl_diu_fb.o fsl_logo_bmp.o COBJS-${CONFIG_FSL_PIXIS} += pixis.o diff --git a/board/freescale/common/cds_eeprom.c b/board/freescale/common/cds_eeprom.c deleted file mode 100644 index 5034e0ca2e1..00000000000 --- a/board/freescale/common/cds_eeprom.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2004 Freescale Semiconductor. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include -#include - -#include "eeprom.h" - - -typedef struct { - char idee_pcbid[4]; /* "CCID" for CDC v1.X */ - u8 idee_major; - u8 idee_minor; - char idee_serial[10]; - char idee_errata[2]; - char idee_date[8]; /* yyyymmdd */ - /* The rest of the EEPROM space is reserved */ -} id_eeprom_t; - - -unsigned int -get_cpu_board_revision(void) -{ - uint major = 0; - uint minor = 0; - - id_eeprom_t id_eeprom; - - i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, - (uchar *) &id_eeprom, sizeof(id_eeprom)); - - major = id_eeprom.idee_major; - minor = id_eeprom.idee_minor; - - if (major == 0xff && minor == 0xff) { - major = minor = 0; - } - - return MPC85XX_CPU_BOARD_REV(major,minor); -} diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 29dff32ea75..bfd86f50696 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -44,7 +44,6 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_FSL_VIA -#define CONFIG_FSL_CDS_EEPROM /* * When initializing flash, if we cannot find the manufacturer ID, @@ -328,11 +327,17 @@ extern unsigned long get_clock_freq(void); #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CFG_I2C_EEPROM_CCID +#define CFG_ID_EEPROM +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_EEPROM_ADDR_LEN 2 + /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index ec0b4ffc660..06965ed4b49 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -50,7 +50,6 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_FSL_VIA -#define CONFIG_FSL_CDS_EEPROM /* * When initializing flash, if we cannot find the manufacturer ID, @@ -352,11 +351,17 @@ extern unsigned long get_clock_freq(void); #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CFG_I2C_EEPROM_CCID +#define CFG_ID_EEPROM +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_EEPROM_ADDR_LEN 2 + /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index c07a725f9b0..a92c0fe301f 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -43,7 +43,7 @@ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_FSL_VIA -#define CONFIG_FSL_CDS_EEPROM + /* * When initializing flash, if we cannot find the manufacturer ID, @@ -325,11 +325,17 @@ extern unsigned long get_clock_freq(void); #define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CFG_I2C_EEPROM_ADDR 0x57 #define CFG_I2C_SLAVE 0x7F #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CFG_I2C_EEPROM_CCID +#define CFG_ID_EEPROM +#define CFG_I2C_EEPROM_ADDR 0x57 +#define CFG_I2C_EEPROM_ADDR_LEN 2 + /* * General PCI * Addresses are mapped 1-1. -- cgit v1.3.1 From 3e79b588b5199f35016f178fc0d5d1266382097f Mon Sep 17 00:00:00 2001 From: Detlev Zundel Date: Fri, 15 Aug 2008 15:42:12 +0200 Subject: 85xx: Socrates: Major code update. - Update the local bus ranges in the FDT for Linux for the various devices connected to the local bus via chip-select. - Set the LCRR_DBYP bit in the LCRR for local bus frequencies lower than 66 MHz and uses I/O accessor functions consequently. - UPM data update. - Update of default environment and configuration. Use I2C multibus as we do have two I2C buses. Also enable sdram and ext2 commands. Signed-off-by: Wolfgang Grandegger Signed-off-by: Sergei Poselenov Signed-off-by: Detlev Zundel --- board/socrates/socrates.c | 82 +++++++++++++++++++-------------- board/socrates/upm_table.h | 32 ++++++------- include/configs/socrates.h | 110 +++++++++++++++++++++++++++------------------ 3 files changed, 132 insertions(+), 92 deletions(-) (limited to 'include') diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index d791f1135f1..63694a73d21 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -37,9 +37,8 @@ #include #include -#if defined(CFG_FPGA_BASE) #include "upm_table.h" -#endif + DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[]; /* FLASH chips info */ @@ -50,6 +49,7 @@ ulong flash_get_size (ulong base, int banknum); int checkboard (void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + char *src; int f; char *s = getenv("serial#"); @@ -79,10 +79,6 @@ int checkboard (void) * Initialize local bus. */ local_bus_init (); -#if defined(CFG_FPGA_BASE) - /* Init UPMA for FPGA access */ - upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); -#endif return 0; } @@ -149,15 +145,34 @@ int misc_init_r (void) */ void local_bus_init (void) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); + sys_info_t sysinfo; + uint clkdiv; + uint lbc_mhz; + uint lcrr = CFG_LBC_LCRR; + + get_sys_info (&sysinfo); + clkdiv = lbc->lcrr & 0x0f; + lbc_mhz = sysinfo.freqSystemBus / 1000000 / clkdiv; + + /* Disable PLL bypass for Local Bus Clock >= 66 MHz */ + if (lbc_mhz >= 66) + lcrr &= ~LCRR_DBYP; /* DLL Enabled */ + else + lcrr |= LCRR_DBYP; /* DLL Bypass */ + + out_be32 (&lbc->lcrr, lcrr); + asm ("sync;isync;msync"); - lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */ - lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */ - ecm->eedr = 0xffffffff; /* Clear ecm errors */ - ecm->eeer = 0xffffffff; /* Enable ecm errors */ + out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */ + out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */ + out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */ + out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */ + /* Init UPMA for FPGA access */ + out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */ + upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); } #if defined(CONFIG_PCI) @@ -197,9 +212,14 @@ void pci_init_board (void) #ifdef CONFIG_BOARD_EARLY_INIT_R int board_early_init_r (void) { -#ifdef CONFIG_PS2MULT - ps2mult_early_init(); -#endif /* CONFIG_PS2MULT */ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + + /* set and reset the GPIO pin 2 which will reset the W83782G chip */ + out_8((unsigned char*)&gur->gpoutdr, 0x3F ); + out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */ + udelay(200); + out_8( (unsigned char*)&gur->gpoutdr, 0x1F ); + return (0); } #endif /* CONFIG_BOARD_EARLY_INIT_R */ @@ -208,31 +228,27 @@ int board_early_init_r (void) void ft_board_setup(void *blob, bd_t *bd) { - u32 val[4]; - int rc; + u32 val[12]; + int rc, i = 0; ft_cpu_setup(blob, bd); - /* Fixup NOR mapping */ - val[0] = 0; /* chip select number */ - val[1] = 0; /* always 0 */ - val[2] = gd->bd->bi_flashstart; - val[3] = gd->bd->bi_flashsize; + /* Fixup NOR FLASH mapping */ + val[i++] = 0; /* chip select number */ + val[i++] = 0; /* always 0 */ + val[i++] = gd->bd->bi_flashstart; + val[i++] = gd->bd->bi_flashsize; - rc = fdt_find_and_setprop(blob, "/localbus", "ranges", - val, sizeof(val), 1); - if (rc) - printf("Unable to update property NOR mapping, err=%s\n", - fdt_strerror(rc)); + /* Fixup FPGA mapping */ + val[i++] = 3; /* chip select number */ + val[i++] = 0; /* always 0 */ + val[i++] = CFG_FPGA_BASE; + val[i++] = CFG_FPGA_SIZE; -#if defined (CFG_FPGA_BASE) - memset(val, 0, sizeof(val)); - val[0] = CFG_FPGA_BASE; - rc = fdt_find_and_setprop(blob, "/localbus/fpga", "virtual-reg", - val, sizeof(val), 1); + rc = fdt_find_and_setprop(blob, "/localbus", "ranges", + val, i * sizeof(u32), 1); if (rc) - printf("Unable to update property \"fpga\", err=%s\n", + printf("Unable to update localbus ranges, err=%s\n", fdt_strerror(rc)); -#endif } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h index ea64a59a0cb..ed8f887cb09 100644 --- a/board/socrates/upm_table.h +++ b/board/socrates/upm_table.h @@ -34,22 +34,22 @@ /* UPM Table Configuration Code for FPGA access */ static const unsigned int UPMTableA[] = { - 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, /* Words 0 to 3 */ - 0x00fcfc00, 0x00fcfc00, 0x00fcfc00, 0x00fcfc05, /* Words 4 to 7 */ - 0x00fcfc00, 0x00fcfc00, 0x00fcfc04, 0x00fcfc04, /* Words 8 to 11 */ - 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, 0x00fcfc04, /* Words 12 to 15 */ - 0x00fcfc04, 0x00fcfc04, 0x00fcfc00, 0xfffffc00, /* Words 16 to 19 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 20 to 23 */ - 0x0ffffc00, 0x0ffffc00, 0x0ffffc00, 0x00f3fc04, /* Words 24 to 27 */ - 0x0ffffc00, 0xfffffc01, 0xfffffc00, 0xfffffc01, /* Words 28 to 31 */ - 0x0ffffc00, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, /* Words 32 to 35 */ - 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, 0x00f3fc04, /* Words 36 to 39 */ - 0x00f3fc04, 0x0ffffc00, 0xfffffc00, 0xfffffc00, /* Words 40 to 43 */ - 0xfffffc01, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 44 to 47 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ - 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 /* Words 60 to 63 */ + 0x00fcec00, 0x00fcec00, 0x00fcec00, 0x00fcec00, /* Words 0 to 3 */ + 0x00fcec00, 0x00fcfc00, 0x00fcfc00, 0x00fcec05, /* Words 4 to 7 */ + 0x00fcec00, 0x00fcec00, 0x00fcec04, 0x00fcec04, /* Words 8 to 11 */ + 0x00fcec04, 0x00fcec04, 0x00fcec04, 0x00fcec04, /* Words 12 to 15 */ + 0x00fcec04, 0x00fcec04, 0x0fffec00, 0xffffec00, /* Words 16 to 19 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 20 to 23 */ + 0x00ffec00, 0x00ffec00, 0x00f3ec00, 0x0fffec00, /* Words 24 to 27 */ + 0x0ffffc04, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 28 to 31 */ + 0x00ffec00, 0x00ffec00, 0x00f3ec04, 0x00f3ec04, /* Words 32 to 35 */ + 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, 0x00f3ec04, /* Words 36 to 39 */ + 0x00f3ec04, 0x00f3ec04, 0x0fffec00, 0xffffec00, /* Words 40 to 43 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 44 to 47 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 48 to 51 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec00, /* Words 52 to 55 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01, /* Words 56 to 59 */ + 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01 /* Words 60 to 63 */ }; #endif diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 5cc4213debc..197ed78d5db 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -45,6 +45,7 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ @@ -141,13 +142,12 @@ #define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ #define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */ -#define CFG_OR0_PRELIM 0xfe000ff7 /* 32MB Flash */ +#define CFG_OR0_PRELIM 0xfe000030 /* 32MB Flash */ #define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */ -#define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */ +#define CFG_OR1_PRELIM 0xfe000030 /* 32MB Flash */ #define CFG_FLASH_CFI /* flash is CFI compat. */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/ -#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ #define CFG_MAX_FLASH_SECT 256 /* sectors per device */ @@ -157,7 +157,7 @@ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ -#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ +#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */ #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ @@ -171,8 +171,20 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */ +#define CFG_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ + +/* FPGA and NAND */ +#define CFG_FPGA_BASE 0xc0000000 +#define CFG_FPGA_SIZE 0x00100000 /* 1 MB */ +#define CFG_HMI_BASE 0xc0010000 +#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ +#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */ + +#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70) +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_CMD_NAND /* Serial Port */ @@ -204,11 +216,14 @@ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SPEED 102124 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C2_OFFSET 0x3100 + /* I2C RTC */ #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ #define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */ @@ -302,18 +317,18 @@ #define CONFIG_CMD_DTT #undef CONFIG_CMD_EEPROM #define CONFIG_CMD_I2C +#define CONFIG_CMD_SDRAM #define CONFIG_CMD_MII #define CONFIG_CMD_NFS #define CONFIG_CMD_PING #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB - +#define CONFIG_CMD_EXT2 /* EXT2 Support */ #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI #endif - #undef CONFIG_WATCHDOG /* watchdog disabled */ /* @@ -357,50 +372,69 @@ #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ -#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ +#define CONFIG_BOOTDELAY 1 /* -1 disables auto-boot */ #define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ + "echo Welcome on the ABB Socrates Board;" \ "echo" #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootfile=$hostname/uImage\0" \ "netdev=eth0\0" \ "consdev=ttyS0\0" \ - "hostname=socrates\0" \ + "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ + "bootfile=/home/tftp/syscon3/uImage\0" \ + "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ + "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ + "uboot_addr=FFFA0000\0" \ + "kernel_addr=FE000000\0" \ + "fdt_addr=FE1E0000\0" \ + "ramdisk_addr=FE200000\0" \ + "fdt_addr_r=B00000\0" \ + "kernel_addr_r=200000\0" \ + "ramdisk_addr_r=400000\0" \ + "rootpath=/opt/eldk/ppc_85xxDP\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addcons=setenv bootargs $bootargs " \ + "console=$consdev,$baudrate\0" \ "addip=setenv bootargs $bootargs " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ ":$hostname:$netdev:off panic=1\0" \ - "addcons=setenv bootargs $bootargs " \ - "console=$consdev,$baudrate\0" \ - "flash_self=run ramargs addip addcons;" \ + "boot_nor=run ramargs addcons;" \ "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ "tftp ${fdt_addr_r} ${fdt_file}; " \ "run nfsargs addip addcons;" \ "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "fdt_file=$hostname/socrates.dtb\0" \ - "fdt_addr_r=B00000\0" \ - "fdt_addr=FC1E0000\0" \ - "rootpath=/opt/eldk/ppc_85xxDP\0" \ - "kernel_addr=FC000000\0" \ - "kernel_addr_r=200000\0" \ - "ramdisk_addr=FC200000\0" \ - "ramdisk_addr_r=400000\0" \ - "load=tftp 100000 $hostname/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ + "update_uboot=tftp 100000 ${uboot_file};" \ + "protect off fffa0000 ffffffff;" \ + "era fffa0000 ffffffff;" \ + "cp.b 100000 fffa0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "update_kernel=tftp 100000 ${bootfile};" \ + "era fe000000 fe1dffff;" \ + "cp.b 100000 fe000000 ${filesize};" \ "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ + "update_fdt=tftp 100000 ${fdt_file};" \ + "era fe1e0000 fe1fffff;" \ + "cp.b 100000 fe1e0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "update_initrd=tftp 100000 ${initrd_file};" \ + "era fe200000 fe9fffff;" \ + "cp.b 100000 fe200000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "clean_data=era fea00000 fff5ffff\0" \ + "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ + "load_usb=usb start;" \ + "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ + "boot_usb=run load_usb usbargs addcons;" \ + "bootm ${kernel_addr_r} - ${fdt_addr};" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ "" -#define CONFIG_BOOTCOMMAND "run flash_self" +#define CONFIG_BOOTCOMMAND "run boot_nor" /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 @@ -417,14 +451,4 @@ #define CONFIG_DOS_PARTITION 1 #define CONFIG_USB_STORAGE 1 -/* FPGA and NAND */ -#define CFG_FPGA_BASE 0xc0000000 -#define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ -#define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */ - -#define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70) -#define CFG_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_CMD_NAND - #endif /* __CONFIG_H */ -- cgit v1.3.1 From e64987a892353f3d49eb242d997820ef8f538912 Mon Sep 17 00:00:00 2001 From: Anatolij Gustschin Date: Fri, 15 Aug 2008 15:42:13 +0200 Subject: 85xx: socrates: Enable Lime support. This patch adds Lime GDC support together with support for the PWM backlight control through the w83782d chip. The reset pin of the latter is attached to GPIO, so we need to reset it in early_board_init_r. Signed-off-by: Anatolij Gustschin --- board/socrates/law.c | 4 +- board/socrates/socrates.c | 198 +++++++++++++++++++++++++++++++++++++++++++++ board/socrates/tlb.c | 13 ++- board/socrates/upm_table.h | 20 +++++ drivers/video/mb862xx.c | 3 +- include/configs/socrates.h | 24 ++++++ 6 files changed, 259 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/socrates/law.c b/board/socrates/law.c index 35c4a900a9b..89b446f6a1a 100644 --- a/board/socrates/law.c +++ b/board/socrates/law.c @@ -36,6 +36,7 @@ * 0x0000_0000 0x2fff_ffff DDR 512M * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xc000_0000 0xc00f_ffff FPGA 1M + * 0xc800_0000 0xcbff_ffff LIME 64M * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR) * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M * 0xfc00_0000 0xffff_ffff FLASH 64M @@ -48,11 +49,12 @@ struct law_entry law_table[] = { SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC), SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), #if defined(CFG_FPGA_BASE) SET_LAW(CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC), #endif + SET_LAW(CFG_LIME_BASE, LAWAR_SIZE_64M, LAW_TRGT_IF_LBC), }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 63694a73d21..73a2d9d709e 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -173,6 +173,12 @@ void local_bus_init (void) /* Init UPMA for FPGA access */ out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */ upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); + + if (getenv("lime")) { + /* Init UPMB for Lime controller access */ + out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */ + upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int)); + } } #if defined(CONFIG_PCI) @@ -239,6 +245,14 @@ ft_board_setup(void *blob, bd_t *bd) val[i++] = gd->bd->bi_flashstart; val[i++] = gd->bd->bi_flashsize; + if (getenv("lime")) { + /* Fixup LIME mapping */ + val[i++] = 2; /* chip select number */ + val[i++] = 0; /* always 0 */ + val[i++] = CFG_LIME_BASE; + val[i++] = CFG_LIME_SIZE; + } + /* Fixup FPGA mapping */ val[i++] = 3; /* chip select number */ val[i++] = 0; /* always 0 */ @@ -252,3 +266,187 @@ ft_board_setup(void *blob, bd_t *bd) fdt_strerror(rc)); } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +#include +#include +#include + +#define CFG_LIME_SRST ((CFG_LIME_BASE) + 0x01FC002C) +#define CFG_LIME_CCF ((CFG_LIME_BASE) + 0x01FC0038) +#define CFG_LIME_MMR ((CFG_LIME_BASE) + 0x01FCFFFC) +/* Lime clock frequency */ +#define CFG_LIME_CLK_100MHZ 0x00000 +#define CFG_LIME_CLK_133MHZ 0x10000 +/* SDRAM parameter */ +#define CFG_LIME_MMR_VALUE 0x4157BA63 + +#define DISPLAY_WIDTH 800 +#define DISPLAY_HEIGHT 480 +#define DEFAULT_BRIGHTNESS 25 +#define BACKLIGHT_ENABLE (1 << 31) + +extern GraphicDevice mb862xx; + +static const gdc_regs init_regs [] = +{ + {0x0100, 0x00010f00}, + {0x0020, 0x801901df}, + {0x0024, 0x00000000}, + {0x0028, 0x00000000}, + {0x002c, 0x00000000}, + {0x0110, 0x00000000}, + {0x0114, 0x00000000}, + {0x0118, 0x01df0320}, + {0x0004, 0x041f0000}, + {0x0008, 0x031f031f}, + {0x000c, 0x017f0349}, + {0x0010, 0x020c0000}, + {0x0014, 0x01df01e9}, + {0x0018, 0x00000000}, + {0x001c, 0x01e00320}, + {0x0100, 0x80010f00}, + {0x0, 0x0} +}; + +const gdc_regs *board_get_regs (void) +{ + return init_regs; +} + +/* Returns Lime base address */ +unsigned int board_video_init (void) +{ + + if (!getenv("lime")) + return 0; + + /* + * Reset Lime controller + */ + out_be32((void *)CFG_LIME_SRST, 0x1); + udelay(200); + + /* Set Lime clock to 133MHz */ + out_be32((void *)CFG_LIME_CCF, CFG_LIME_CLK_133MHZ); + /* Delay required */ + udelay(300); + /* Set memory parameters */ + out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); + + mb862xx.winSizeX = DISPLAY_WIDTH; + mb862xx.winSizeY = DISPLAY_HEIGHT; + mb862xx.gdfIndex = GDF_15BIT_555RGB; + mb862xx.gdfBytesPP = 2; + + return CFG_LIME_BASE; +} + +#define W83782D_REG_CFG 0x40 +#define W83782D_REG_BANK_SEL 0x4e +#define W83782D_REG_ADCCLK 0x4b +#define W83782D_REG_BEEP_CTRL 0x4d +#define W83782D_REG_BEEP_CTRL2 0x57 +#define W83782D_REG_PWMOUT1 0x5b +#define W83782D_REG_VBAT 0x5d + +static int w83782d_hwmon_init(void) +{ + u8 buf; + + if (i2c_read(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1)) + return -1; + + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80); + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0); + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40); + + buf = i2c_reg_read(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL); + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL, + buf | 0x80); + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0); + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47); + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01); + + buf = i2c_reg_read(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG); + i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, + (buf & 0xf4) | 0x01); + return 0; +} + +static void board_backlight_brightness(int br) +{ + u32 reg; + u8 buf; + u8 old_buf; + + /* Select bank 0 */ + if (i2c_read(CFG_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) + goto err; + else + buf = old_buf & 0xf8; + + if (i2c_write(CFG_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1)) + goto err; + + if (br > 0) { + /* PWMOUT1 duty cycle ctrl */ + buf = 255 / (100 / br); + if (i2c_write(CFG_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) + goto err; + + /* LEDs on */ + reg = in_be32((void *)(CFG_FPGA_BASE + 0x0c)); + if (!(reg & BACKLIGHT_ENABLE)); + out_be32((void *)(CFG_FPGA_BASE + 0x0c), + reg | BACKLIGHT_ENABLE); + } else { + buf = 0; + if (i2c_write(CFG_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) + goto err; + + /* LEDs off */ + reg = in_be32((void *)(CFG_FPGA_BASE + 0x0c)); + reg &= ~BACKLIGHT_ENABLE; + out_be32((void *)(CFG_FPGA_BASE + 0x0c), reg); + } + /* Restore previous bank setting */ + if (i2c_write(CFG_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) + goto err; + + return; +err: + printf("W83782G I2C access failed\n"); +} + +void board_backlight_switch (int flag) +{ + char * param; + int rc; + + if (w83782d_hwmon_init()) + printf ("hwmon IC init failed\n"); + + if (flag) { + param = getenv("brightness"); + rc = param ? simple_strtol(param, NULL, 10) : -1; + if (rc < 0) + rc = DEFAULT_BRIGHTNESS; + } else { + rc = 0; + } + board_backlight_brightness(rc); +} + +#if defined(CONFIG_CONSOLE_EXTRA_INFO) +/* + * Return text to be printed besides the logo. + */ +void video_get_info_str (int line_number, char *info) +{ + if (line_number == 1) { + strcpy (info, " Board: Socrates"); + } else { + info [0] = '\0'; + } +} +#endif diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c index aea99ada20a..d255cea15e5 100644 --- a/board/socrates/tlb.c +++ b/board/socrates/tlb.c @@ -46,7 +46,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* - * TLB 0: 64M Non-cacheable, guarded + * TLB 1: 64M Non-cacheable, guarded * 0xfc000000 64M FLASH * Out of reset this entry is only 4K. */ @@ -80,6 +80,17 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 4, BOOKE_PAGESZ_1M, 1), #endif + /* + * TLB 5: 64M Non-cacheable, guarded + * 0xc8000000 16M LIME GDC framebuffer + * 0xc9fc0000 256K LIME GDC MMIO + * (0xcbfc0000 256K LIME GDC MMIO) + * MMIO is relocatable and could be at 0xcbfc0000 + */ + SET_TLB_ENTRY(1, CFG_LIME_BASE, CFG_LIME_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64M, 1), + /* * TLB 6: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR diff --git a/board/socrates/upm_table.h b/board/socrates/upm_table.h index ed8f887cb09..2a89c963efe 100644 --- a/board/socrates/upm_table.h +++ b/board/socrates/upm_table.h @@ -52,4 +52,24 @@ static const unsigned int UPMTableA[] = 0xffffec00, 0xffffec00, 0xffffec00, 0xffffec01 /* Words 60 to 63 */ }; +/* LIME UPM B Table Configuration Code */ +static unsigned int UPMTableB[] = +{ + 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 0 to 3 */ + 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffffc01, /* Words 4 to 7 */ + 0x0ffefc00, 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc00, /* Words 8 to 11 */ + 0x0ffcfc00, 0x0ffcfc00, 0x0ffcfc04, 0x0ffcfc04, /* Words 12 to 15 */ + 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, 0x0ffcfc04, /* Words 16 to 19 */ + 0x0ffcfc04, 0x0ffcfc04, 0x0ffffc00, 0xfffffc01, /* Words 20 to 23 */ + 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 24 to 27 */ + 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x0ffffc01, /* Words 28 to 31 */ + 0x0cfffc00, 0x00fffc00, 0x00fffc00, 0x00fffc00, /* Words 32 to 35 */ + 0x00fffc00, 0x00fffc00, 0x00fffc04, 0x00fffc04, /* Words 36 to 39 */ + 0x00fffc04, 0x00fffc04, 0x00fffc04, 0x00fffc04, /* Words 40 to 43 */ + 0x00fffc04, 0x00fffc04, 0x0ffffc00, 0xfffffc01, /* Words 44 to 47 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */ + 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 /* Words 60 to 63 */ +}; #endif diff --git a/drivers/video/mb862xx.c b/drivers/video/mb862xx.c index 6c14b0d688c..d47cb035817 100644 --- a/drivers/video/mb862xx.c +++ b/drivers/video/mb862xx.c @@ -357,7 +357,8 @@ void *video_hw_init (void) board_disp_init(); #endif -#if defined(CONFIG_LWMON5) && !(CONFIG_POST & CFG_POST_SYSMON) +#if (defined(CONFIG_LWMON5) || \ + defined(CONFIG_SOCRATES)) && !(CONFIG_POST & CFG_POST_SYSMON) /* Lamp on */ board_backlight_switch (1); #endif diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 197ed78d5db..a981a8fe953 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -186,6 +186,26 @@ #define NAND_MAX_CHIPS 1 #define CONFIG_CMD_NAND +/* LIME GDC */ +#define CFG_LIME_BASE 0xc8000000 +#define CFG_LIME_SIZE 0x04000000 /* 64 MB */ +#define CFG_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ +#define CFG_OR2_PRELIM 0xfc000000 /* 64 MB */ + +#define CONFIG_VIDEO +#define CONFIG_VIDEO_MB862xx +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_CONSOLE_EXTRA_INFO +#define VIDEO_FB_16BPP_PIXEL_SWAP +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CFG_CONSOLE_IS_IN_ENV +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_SPLASH_SCREEN +#define CONFIG_VIDEO_BMP_GZIP +#define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ + /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -228,6 +248,9 @@ #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ #define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */ +/* I2C W83782G HW-Monitoring IC */ +#define CFG_I2C_W83782G_ADDR 0x28 /* W83782G address */ + /* I2C temp sensor */ /* Socrates uses Maxim's DS75, which is compatible with LM75 */ #define CONFIG_DTT_LM75 1 @@ -324,6 +347,7 @@ #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB #define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_BMP #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI -- cgit v1.3.1 From 3ef96ded38a8d33b58b9fab9cd879d51ddac4cbd Mon Sep 17 00:00:00 2001 From: Graeme Russ Date: Sun, 7 Sep 2008 07:08:42 +1000 Subject: Update i386 code (sc520_cdp) Attempt to bring i386 / sc520 inline with master Signed-off-by: Graeme Russ --- board/sc520_cdp/sc520_cdp.c | 10 +++++----- drivers/mtd/mw_eeprom.c | 2 +- examples/82559_eeprom.c | 16 ++++++++++------ include/asm-i386/byteorder.h | 4 ++-- include/asm-i386/global_data.h | 4 ++-- include/asm-i386/ic/ssi.h | 34 ++++++++++++++++++++++++++++++++++ include/asm-i386/pci.h | 1 - include/asm-i386/string.h | 2 ++ include/configs/sc520_cdp.h | 24 ++++++++++++++++++++++++ lib_i386/bios_setup.c | 6 ++++-- lib_i386/board.c | 13 ++++++++----- lib_i386/bootm.c | 2 +- lib_i386/video_bios.c | 3 +++ 13 files changed, 96 insertions(+), 25 deletions(-) create mode 100644 include/asm-i386/ic/ssi.h (limited to 'include') diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c index f21c73002fc..99debde50ee 100644 --- a/board/sc520_cdp/sc520_cdp.c +++ b/board/sc520_cdp/sc520_cdp.c @@ -114,7 +114,7 @@ static void irq_init(void) } - +#ifdef CONFIG_PCI /* PCI stuff */ static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { @@ -129,7 +129,7 @@ static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) }; static int next_irq_index=0; - char tmp_pin; + uchar tmp_pin; int pin; pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin); @@ -193,7 +193,7 @@ void pci_init_board(void) { pci_sc520_init(&sc520_cdp_hose); } - +#endif static void silence_uart(int port) { @@ -563,12 +563,12 @@ void spi_eeprom_probe(int x) { } -int spi_eeprom_read(int x, int offset, char *buffer, int len) +int spi_eeprom_read(int x, int offset, uchar *buffer, int len) { return 0; } -int spi_eeprom_write(int x, int offset, char *buffer, int len) +int spi_eeprom_write(int x, int offset, uchar *buffer, int len) { return 0; } diff --git a/drivers/mtd/mw_eeprom.c b/drivers/mtd/mw_eeprom.c index f32ced4c2e0..f7791b51a04 100644 --- a/drivers/mtd/mw_eeprom.c +++ b/drivers/mtd/mw_eeprom.c @@ -1,7 +1,7 @@ /* Three-wire (MicroWire) serial eeprom driver (for 93C46 and compatibles) */ #include -#include +#include /* * Serial EEPROM opcodes, including start bit diff --git a/examples/82559_eeprom.c b/examples/82559_eeprom.c index 1a121d42874..d99af26fe49 100644 --- a/examples/82559_eeprom.c +++ b/examples/82559_eeprom.c @@ -51,13 +51,17 @@ static inline unsigned short swap16(unsigned short x) } -static inline void *memcpy(void *dst, const void *src, unsigned int len) +void * memcpy(void * dest,const void *src,size_t count) { - void * ret = dst; - while (len-- > 0) *((char *)dst)++ = *((char *)src)++; - return ret; + char *tmp = (char *) dest, *s = (char *) src; + + while (count--) + *tmp++ = *s++; + + return dest; } + /* The EEPROM commands include the alway-set leading bit. */ #define EE_WRITE_CMD (5) #define EE_READ_CMD (6) @@ -156,7 +160,7 @@ static int reset_eeprom(unsigned long ioaddr, unsigned char *hwaddr) int size_test; int i; - printf("Resetting i82559 EEPROM @ 0x%08x ... ", ioaddr); + printf("Resetting i82559 EEPROM @ 0x%08lx ... ", ioaddr); size_test = do_eeprom_cmd(ioaddr, (EE_READ_CMD << 8) << 16, 27); eeprom_addr_size = (size_test & 0xffe0000) == 0xffe0000 ? 8 : 6; @@ -305,7 +309,7 @@ write_config_word(int bus, int dev, int func, int reg, u16 data) int main (int argc, char *argv[]) { unsigned char *eth_addr; - char buf[6]; + uchar buf[6]; int instance; app_startup(argv); diff --git a/include/asm-i386/byteorder.h b/include/asm-i386/byteorder.h index a9c69d5b1f2..7dfeb8bbed2 100644 --- a/include/asm-i386/byteorder.h +++ b/include/asm-i386/byteorder.h @@ -6,7 +6,7 @@ #ifdef __GNUC__ -static __inline__ __const__ __u32 ___arch__swab32(__u32 x) +static __inline__ __u32 ___arch__swab32(__u32 x) { #ifdef CONFIG_X86_BSWAP __asm__("bswap %0" : "=r" (x) : "0" (x)); @@ -20,7 +20,7 @@ static __inline__ __const__ __u32 ___arch__swab32(__u32 x) return x; } -static __inline__ __const__ __u16 ___arch__swab16(__u16 x) +static __inline__ __u16 ___arch__swab16(__u16 x) { __asm__("xchgb %b0,%h0" /* swap bytes */ \ : "=q" (x) \ diff --git a/include/asm-i386/global_data.h b/include/asm-i386/global_data.h index 35bad23c17c..cc30689d210 100644 --- a/include/asm-i386/global_data.h +++ b/include/asm-i386/global_data.h @@ -59,8 +59,8 @@ typedef struct { #define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ #define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ -extern gd_t *global_data; +extern gd_t *gd; -#define DECLARE_GLOBAL_DATA_PTR gd_t *gd = global_data +#define DECLARE_GLOBAL_DATA_PTR #endif /* __ASM_GBL_DATA_H */ diff --git a/include/asm-i386/ic/ssi.h b/include/asm-i386/ic/ssi.h new file mode 100644 index 00000000000..bd48eab1610 --- /dev/null +++ b/include/asm-i386/ic/ssi.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2008 + * Graeme Russ . + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_IC_SSI_H_ +#define _ASM_IC_SSI_H_ 1 + +int ssi_set_interface(int, int, int, int); +void ssi_chip_select(int); +u8 ssi_txrx_byte(u8); +void ssi_tx_byte(u8); +u8 ssi_rx_byte(void); + + +#endif diff --git a/include/asm-i386/pci.h b/include/asm-i386/pci.h index bde95509a4b..050a2bb8683 100644 --- a/include/asm-i386/pci.h +++ b/include/asm-i386/pci.h @@ -31,5 +31,4 @@ int pci_enable_legacy_video_ports(struct pci_controller* hose); int pci_shadow_rom(pci_dev_t dev, unsigned char *dest); void pci_remove_rom_window(struct pci_controller* hose, u32 addr); u32 pci_get_rom_window(struct pci_controller* hose, int size); - #endif diff --git a/include/asm-i386/string.h b/include/asm-i386/string.h index 91a23f951ca..3643a79fdfc 100644 --- a/include/asm-i386/string.h +++ b/include/asm-i386/string.h @@ -5,6 +5,8 @@ * We don't do inline string functions, since the * optimised inline asm versions are not small. */ +#undef __HAVE_ARCH_STRNCPY +extern char *strncpy(char *__dest, __const__ char *__src, __kernel_size_t __n); #undef __HAVE_ARCH_STRRCHR extern char * strrchr(const char * s, int c); diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index e29655e6362..dfe7b7d3e49 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -28,6 +28,7 @@ #ifndef __CONFIG_H #define __CONFIG_H +#define GRUSS_TESTING /* * High Level Configuration Options * (easy to change) @@ -81,7 +82,11 @@ #include #define CONFIG_CMD_PCI +#ifndef GRUSS_TESTING #define CONFIG_CMD_SATA +#else +#undef CONFIG_CMD_SATA +#endif #define CONFIG_CMD_JFFS2 #define CONFIG_CMD_NET #define CONFIG_CMD_EEPROM @@ -175,10 +180,18 @@ /************************************************************ *SATA/Native Stuff ************************************************************/ +#ifndef GRUSS_TESTING #define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */ #define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */ #define CFG_SATA_MAX_DEVICE (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS) #define CONFIG_ATA_PIIX 1 /*Supports ata_piix driver */ +#else +#undef CFG_SATA_MAXBUS +#undef CFG_SATA_DEVS_PER_BUS +#undef CFG_SATA_MAX_DEVICE +#undef CONFIG_ATA_PIIX +#endif + /************************************************************ * DISK Partition support @@ -190,7 +203,11 @@ /************************************************************ * Video/Keyboard support ************************************************************/ +#ifndef GRUSS_TESTING #define CONFIG_VIDEO /* To enable video controller support */ +#else +#undef CONFIG_VIDEO +#endif #define CONFIG_I8042_KBD #define CFG_ISA_IO 0 @@ -203,6 +220,7 @@ /* * PCI stuff */ +#ifndef GRUSS_TESTING #define CONFIG_PCI /* include pci support */ #define CONFIG_PCI_PNP /* pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW @@ -211,5 +229,11 @@ #define CFG_SECOND_PCI_IRQ 9 #define CFG_THIRD_PCI_IRQ 11 #define CFG_FORTH_PCI_IRQ 15 +#else +#undef CONFIG_PCI +#undef CONFIG_PCI_PNP +#undef CONFIG_PCI_SCAN_SHOW +#endif + #endif /* __CONFIG_H */ diff --git a/lib_i386/bios_setup.c b/lib_i386/bios_setup.c index 75f04a01fe6..33c842c6a0a 100644 --- a/lib_i386/bios_setup.c +++ b/lib_i386/bios_setup.c @@ -140,8 +140,9 @@ int bios_setup(void) { static int done=0; int vector; +#ifdef CONFIG_PCI struct pci_controller *pri_hose; - +#endif if (done) { return 0; } @@ -223,12 +224,13 @@ int bios_setup(void) * (This, ofcause break on multi hose systems, * but our PCI BIOS only support one hose anyway) */ +#ifdef CONFIG_PCI pri_hose = pci_bus_to_hose(0); if (NULL != pri_hose) { /* fill in last pci bus number for use by the realmode * PCI BIOS */ RELOC_16_BYTE(0xf000, pci_last_bus) = pri_hose->last_busno; } - +#endif return 0; } diff --git a/lib_i386/board.c b/lib_i386/board.c index 55fa42af424..f3da0a292c2 100644 --- a/lib_i386/board.c +++ b/lib_i386/board.c @@ -213,7 +213,7 @@ init_fnc_t *init_sequence[] = { NULL, }; -gd_t *global_data; +gd_t *gd; void start_i386boot (void) { @@ -226,7 +226,7 @@ void start_i386boot (void) show_boot_progress(0x21); - gd = global_data = &gd_data; + gd = &gd_data; /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory"); @@ -266,7 +266,7 @@ void start_i386boot (void) int i; ulong reg; char *s, *e; - uchar tmp[64]; + char tmp[64]; i = getenv_r ("ethaddr", tmp, sizeof (tmp)); s = (i > 0) ? tmp : NULL; @@ -412,7 +412,10 @@ void hang (void) unsigned long do_go_exec (ulong (*entry)(int, char *[]), int argc, char *argv[]) { /* - * Nios function pointers are address >> 1 + * TODO: Test this function - changed to fix compiler error. + * Original code was: + * return (entry >> 1) (argc, argv); + * with a comment about Nios function pointers are address >> 1 */ - return (entry >> 1) (argc, argv); + return (entry) (argc, argv); } diff --git a/lib_i386/bootm.c b/lib_i386/bootm.c index 522d7ad8ee8..613e339a5f2 100644 --- a/lib_i386/bootm.c +++ b/lib_i386/bootm.c @@ -34,7 +34,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) void *base_ptr; ulong os_data, os_len; image_header_t *hdr; - int ret; + #if defined(CONFIG_FIT) const void *data; size_t len; diff --git a/lib_i386/video_bios.c b/lib_i386/video_bios.c index 45f78e22faa..ce96a3e058f 100644 --- a/lib_i386/video_bios.c +++ b/lib_i386/video_bios.c @@ -136,6 +136,8 @@ static u32 probe_pci_video(void) #endif +#ifdef CONFIG_VIDEO + static int probe_isa_video(void) { u32 ptr; @@ -217,3 +219,4 @@ int video_bios_init(void) return 1; } +#endif -- cgit v1.3.1 From 48d0192fe869948fef14b460b5f0c85bca933693 Mon Sep 17 00:00:00 2001 From: Andreas Engel Date: Mon, 8 Sep 2008 14:30:53 +0200 Subject: Moved conditional compile into Makefile Signed-off-by: Andreas Engel --- README | 4 ++-- drivers/serial/Makefile | 3 ++- drivers/serial/serial_pl01x.c | 15 +++++---------- include/configs/integratorap.h | 2 +- include/configs/integratorcp.h | 2 +- include/configs/versatile.h | 2 +- 6 files changed, 12 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/README b/README index ec164ade228..2cdb2686497 100644 --- a/README +++ b/README @@ -380,11 +380,11 @@ The following options need to be configured: param header, the default value is zero if undefined. - Serial Ports: - CFG_PL010_SERIAL + CONFIG_PL010_SERIAL Define this if you want support for Amba PrimeCell PL010 UARTs. - CFG_PL011_SERIAL + CONFIG_PL011_SERIAL Define this if you want support for Amba PrimeCell PL011 UARTs. diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 3cc19991bb6..b370828caa4 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -33,7 +33,8 @@ COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o COBJS-$(CONFIG_S3C64XX) += s3c64xx.o COBJS-y += serial.o COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o -COBJS-y += serial_pl01x.o +COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o +COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o COBJS-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index d0497ec4180..c645cef8765 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -25,14 +25,11 @@ * MA 02111-1307 USA */ -/* Simple U-Boot driver for the PrimeCell PL011 UARTs on the IntegratorCP */ -/* Should be fairly simple to make it work with the PL010 as well */ +/* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */ #include #include -#if defined(CFG_PL010_SERIAL) || defined(CFG_PL011_SERIAL) - #include "serial_pl01x.h" #define IO_WRITE(addr, val) (*(volatile unsigned int *)(addr) = (val)) @@ -52,7 +49,7 @@ static void pl01x_putc (int portnum, char c); static int pl01x_getc (int portnum); static int pl01x_tstc (int portnum); -#ifdef CFG_PL010_SERIAL +#ifdef CONFIG_PL010_SERIAL int serial_init (void) { @@ -110,9 +107,9 @@ int serial_init (void) return 0; } -#endif /* CFG_PL010_SERIAL */ +#endif /* CONFIG_PL010_SERIAL */ -#ifdef CFG_PL011_SERIAL +#ifdef CONFIG_PL011_SERIAL int serial_init (void) { @@ -157,7 +154,7 @@ int serial_init (void) return 0; } -#endif /* CFG_PL011_SERIAL */ +#endif /* CONFIG_PL011_SERIAL */ void serial_putc (const char c) { @@ -224,5 +221,3 @@ static int pl01x_tstc (int portnum) return !(IO_READ (port[portnum] + UART_PL01x_FR) & UART_PL01x_FR_RXFE); } - -#endif diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 1452bf2c467..ba3c5315e9f 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -58,7 +58,7 @@ /* * PL010 Configuration */ -#define CFG_PL010_SERIAL +#define CONFIG_PL010_SERIAL #define CONFIG_CONS_INDEX 0 #define CONFIG_BAUDRATE 38400 #define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) } diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 347fa0201d0..5340f7c2d1d 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -61,7 +61,7 @@ /* * NS16550 Configuration */ -#define CFG_PL011_SERIAL +#define CONFIG_PL011_SERIAL #define CONFIG_PL011_CLOCK 14745600 #define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 } #define CONFIG_CONS_INDEX 0 diff --git a/include/configs/versatile.h b/include/configs/versatile.h index a88d356b17c..c18a248147e 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -86,7 +86,7 @@ /* * NS16550 Configuration */ -#define CFG_PL011_SERIAL +#define CONFIG_PL011_SERIAL #define CONFIG_PL011_CLOCK 24000000 #define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 } #define CONFIG_CONS_INDEX 0 -- cgit v1.3.1 From 9ba2e2c8191353d75b2d535e672a125be7b84c03 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 8 Sep 2008 13:57:12 -0500 Subject: Remove support for booting ARTOS images Pantelis Antoniou stated: AFAIK, it is still used but the products using PPC are long gone. Nuke it plz (from orbit). So remove it since it cleans up a usage of env_get_char outside of the environment code. Signed-off-by: Kumar Gala --- README | 4 +- common/cmd_bootm.c | 99 ----------------------------------- common/image.c | 3 -- doc/uImage.FIT/source_file_format.txt | 2 +- include/configs/NETPHONE.h | 2 - include/configs/NETTA.h | 2 - include/configs/NETTA2.h | 2 - include/configs/NETVIA.h | 2 - 8 files changed, 3 insertions(+), 113 deletions(-) (limited to 'include') diff --git a/README b/README index 2cdb2686497..402ded303ca 100644 --- a/README +++ b/README @@ -3030,8 +3030,8 @@ details; basically, the header defines the following image properties: * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD, 4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks, - LynxOS, pSOS, QNX, RTEMS, ARTOS; - Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, ARTOS, LynxOS). + LynxOS, pSOS, QNX, RTEMS; + Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS). * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86, IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit; Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC). diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 8dbab02b87e..08a014f4484 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -108,9 +108,6 @@ static boot_os_fn do_bootm_qnxelf; int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); #endif -#if defined(CONFIG_ARTOS) && defined(CONFIG_PPC) -static boot_os_fn do_bootm_artos; -#endif ulong load_addr = CFG_LOAD_ADDR; /* Default Load Address */ static bootm_headers_t images; /* pointers to os/initrd/fdt images */ @@ -455,11 +452,6 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; #endif -#ifdef CONFIG_ARTOS - case IH_OS_ARTOS: - do_bootm_artos (0, argc, argv, &images); - break; -#endif } show_boot_progress (-9); @@ -1152,94 +1144,3 @@ static int do_bootm_qnxelf(int flag, int argc, char *argv[], return 1; } #endif - -#if defined(CONFIG_ARTOS) && defined(CONFIG_PPC) -static int do_bootm_artos (int flag, int argc, char *argv[], - bootm_headers_t *images) -{ - ulong top; - char *s, *cmdline; - char **fwenv, **ss; - int i, j, nxt, len, envno, envsz; - bd_t *kbd; - void (*entry)(bd_t *bd, char *cmdline, char **fwenv, ulong top); - -#if defined(CONFIG_FIT) - if (!images->legacy_hdr_valid) { - fit_unsupported_reset ("ARTOS"); - return 1; - } -#endif - - /* - * Booting an ARTOS kernel image + application - */ - - /* this used to be the top of memory, but was wrong... */ -#ifdef CONFIG_PPC - /* get stack pointer */ - asm volatile ("mr %0,1" : "=r"(top) ); -#endif - debug ("## Current stack ends at 0x%08lX ", top); - - top -= 2048; /* just to be sure */ - if (top > CFG_BOOTMAPSZ) - top = CFG_BOOTMAPSZ; - top &= ~0xF; - - debug ("=> set upper limit to 0x%08lX\n", top); - - /* first check the artos specific boot args, then the linux args*/ - if ((s = getenv( "abootargs")) == NULL && (s = getenv ("bootargs")) == NULL) - s = ""; - - /* get length of cmdline, and place it */ - len = strlen (s); - top = (top - (len + 1)) & ~0xF; - cmdline = (char *)top; - debug ("## cmdline at 0x%08lX ", top); - strcpy (cmdline, s); - - /* copy bdinfo */ - top = (top - sizeof (bd_t)) & ~0xF; - debug ("## bd at 0x%08lX ", top); - kbd = (bd_t *)top; - memcpy (kbd, gd->bd, sizeof (bd_t)); - - /* first find number of env entries, and their size */ - envno = 0; - envsz = 0; - for (i = 0; env_get_char (i) != '\0'; i = nxt + 1) { - for (nxt = i; env_get_char (nxt) != '\0'; ++nxt) - ; - envno++; - envsz += (nxt - i) + 1; /* plus trailing zero */ - } - envno++; /* plus the terminating zero */ - debug ("## %u envvars total size %u ", envno, envsz); - - top = (top - sizeof (char **) * envno) & ~0xF; - fwenv = (char **)top; - debug ("## fwenv at 0x%08lX ", top); - - top = (top - envsz) & ~0xF; - s = (char *)top; - ss = fwenv; - - /* now copy them */ - for (i = 0; env_get_char (i) != '\0'; i = nxt + 1) { - for (nxt = i; env_get_char (nxt) != '\0'; ++nxt) - ; - *ss++ = s; - for (j = i; j < nxt; ++j) - *s++ = env_get_char (j); - *s++ = '\0'; - } - *ss++ = NULL; /* terminate */ - - entry = (void (*)(bd_t *, char *, char **, ulong))images->ep; - (*entry) (kbd, cmdline, fwenv, top); - - return 1; -} -#endif diff --git a/common/image.c b/common/image.c index 94f01ad455d..78efe2ebb73 100644 --- a/common/image.c +++ b/common/image.c @@ -105,9 +105,6 @@ static table_entry_t uimage_arch[] = { static table_entry_t uimage_os[] = { { IH_OS_INVALID, NULL, "Invalid OS", }, -#if defined(CONFIG_ARTOS) || defined(USE_HOSTCC) - { IH_OS_ARTOS, "artos", "ARTOS", }, -#endif { IH_OS_LINUX, "linux", "Linux", }, #if defined(CONFIG_LYNXKDI) || defined(USE_HOSTCC) { IH_OS_LYNXOS, "lynxos", "LynxOS", }, diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt index c1244fbadae..1e30d22005a 100644 --- a/doc/uImage.FIT/source_file_format.txt +++ b/doc/uImage.FIT/source_file_format.txt @@ -169,7 +169,7 @@ the '/images' node should have the following layout: - os : OS name, mandatory for type="kernel", valid OS names are: "openbsd", "netbsd", "freebsd", "4_4bsd", "linux", "svr4", "esix", "solaris", "irix", "sco", "dell", "ncr", "lynxos", "vxworks", "psos", "qnx", "u_boot", - "rtems", "artos", "unity". + "rtems", "unity". - arch : Architecture name, mandatory for types: "standalone", "kernel", "firmware", "ramdisk" and "fdt". Valid architecture names are: "alpha", "arm", "i386", "ia64", "mips", "mips64", "ppc", "s390", "sh", "sparc", diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h index 6c18b816914..1494190bf97 100644 --- a/include/configs/NETPHONE.h +++ b/include/configs/NETPHONE.h @@ -487,8 +487,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_ARTOS /* include ARTOS support */ - #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ /****************************************************************/ diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 1f1bc540bb4..64806342aeb 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -496,8 +496,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_ARTOS /* include ARTOS support */ - #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ /*********************************************************************************************************** diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index ea5d1604cc9..efa91e304a2 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -488,8 +488,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CONFIG_ARTOS /* include ARTOS support */ - #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ /****************************************************************/ diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index c0295941870..40e09fba620 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -357,8 +357,6 @@ /* Ethernet at SCC2 */ #define CONFIG_SCC2_ENET -#define CONFIG_ARTOS /* include ARTOS support */ - /****************************************************************/ #define DSP_SIZE 0x00010000 /* 64K */ -- cgit v1.3.1 From f5ed9e39088ecfa5a5f3ef47b08e5bda7890d764 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Mon, 8 Sep 2008 14:56:49 -0500 Subject: Add support for booting of INTEGRITY operating system uImages Signed-off-by: Peter Tyser --- README | 5 +++-- common/cmd_bootm.c | 38 +++++++++++++++++++++++++++++++++++ common/image.c | 3 +++ doc/uImage.FIT/source_file_format.txt | 2 +- include/image.h | 1 + 5 files changed, 46 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/README b/README index 402ded303ca..b5e40862b99 100644 --- a/README +++ b/README @@ -3030,8 +3030,9 @@ details; basically, the header defines the following image properties: * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD, 4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks, - LynxOS, pSOS, QNX, RTEMS; - Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS). + LynxOS, pSOS, QNX, RTEMS, INTEGRITY; + Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS, + INTEGRITY). * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86, IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit; Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC). diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 08a014f4484..b023e2635e1 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -108,6 +108,9 @@ static boot_os_fn do_bootm_qnxelf; int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); #endif +#if defined(CONFIG_INTEGRITY) +static boot_os_fn do_bootm_integrity; +#endif ulong load_addr = CFG_LOAD_ADDR; /* Default Load Address */ static bootm_headers_t images; /* pointers to os/initrd/fdt images */ @@ -452,6 +455,11 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; #endif +#ifdef CONFIG_INTEGRITY + case IH_OS_INTEGRITY: + do_bootm_integrity (0, argc, argv, &images); + break; +#endif } show_boot_progress (-9); @@ -1144,3 +1152,33 @@ static int do_bootm_qnxelf(int flag, int argc, char *argv[], return 1; } #endif + +#ifdef CONFIG_INTEGRITY +static int do_bootm_integrity (int flag, int argc, char *argv[], + bootm_headers_t *images) +{ + void (*entry_point)(void); + +#if defined(CONFIG_FIT) + if (!images->legacy_hdr_valid) { + fit_unsupported_reset ("INTEGRITY"); + return 1; + } +#endif + + entry_point = (void (*)(void))images->ep; + + printf ("## Transferring control to INTEGRITY (at address %08lx) ...\n", + (ulong)entry_point); + + show_boot_progress (15); + + /* + * INTEGRITY Parameters: + * None + */ + (*entry_point)(); + + return 1; +} +#endif diff --git a/common/image.c b/common/image.c index 78efe2ebb73..b0119327b5f 100644 --- a/common/image.c +++ b/common/image.c @@ -116,6 +116,9 @@ static table_entry_t uimage_os[] = { { IH_OS_QNX, "qnx", "QNX", }, { IH_OS_VXWORKS, "vxworks", "VxWorks", }, #endif +#if defined(CONFIG_INTEGRITY) || defined(USE_HOSTCC) + { IH_OS_INTEGRITY,"integrity", "INTEGRITY", }, +#endif #ifdef USE_HOSTCC { IH_OS_4_4BSD, "4_4bsd", "4_4BSD", }, { IH_OS_DELL, "dell", "Dell", }, diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt index 1e30d22005a..157936ed531 100644 --- a/doc/uImage.FIT/source_file_format.txt +++ b/doc/uImage.FIT/source_file_format.txt @@ -169,7 +169,7 @@ the '/images' node should have the following layout: - os : OS name, mandatory for type="kernel", valid OS names are: "openbsd", "netbsd", "freebsd", "4_4bsd", "linux", "svr4", "esix", "solaris", "irix", "sco", "dell", "ncr", "lynxos", "vxworks", "psos", "qnx", "u_boot", - "rtems", "unity". + "rtems", "unity", "integrity". - arch : Architecture name, mandatory for types: "standalone", "kernel", "firmware", "ramdisk" and "fdt". Valid architecture names are: "alpha", "arm", "i386", "ia64", "mips", "mips64", "ppc", "s390", "sh", "sparc", diff --git a/include/image.h b/include/image.h index 9be806e12d7..46544858c86 100644 --- a/include/image.h +++ b/include/image.h @@ -85,6 +85,7 @@ #define IH_OS_RTEMS 18 /* RTEMS */ #define IH_OS_ARTOS 19 /* ARTOS */ #define IH_OS_UNITY 20 /* Unity OS */ +#define IH_OS_INTEGRITY 21 /* INTEGRITY */ /* * CPU Architecture Codes (supported by Linux) -- cgit v1.3.1 From 919f550dc11a13abf01c6bc713c968de790b8d7c Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Tue, 9 Sep 2008 12:58:15 +0200 Subject: FIT: add ability to check hashes of all images in FIT, improve output - add function fit_all_image_check_hashes() that verifies if all hashes of all images in the FIT are valid - improve output of fit_image_check_hashes() when the hash check fails Signed-off-by: Bartlomiej Sieka --- common/image.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++----- include/image.h | 1 + 2 files changed, 57 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/common/image.c b/common/image.c index b0119327b5f..f7e8606ccad 100644 --- a/common/image.c +++ b/common/image.c @@ -2645,27 +2645,29 @@ int fit_image_check_hashes (const void *fit, int image_noffset) continue; if (fit_image_hash_get_algo (fit, noffset, &algo)) { - err_msg = "Can't get hash algo property"; + err_msg = " error!\nCan't get hash algo " + "property"; goto error; } printf ("%s", algo); if (fit_image_hash_get_value (fit, noffset, &fit_value, &fit_value_len)) { - err_msg = "Can't get hash value property"; + err_msg = " error!\nCan't get hash value " + "property"; goto error; } if (calculate_hash (data, size, algo, value, &value_len)) { - err_msg = "Unsupported hash algorithm"; + err_msg = " error!\nUnsupported hash algorithm"; goto error; } if (value_len != fit_value_len) { - err_msg = "Bad hash value len"; + err_msg = " error !\nBad hash value len"; goto error; } else if (memcmp (value, fit_value, value_len) != 0) { - err_msg = "Bad hash value"; + err_msg = " error!\nBad hash value"; goto error; } printf ("+ "); @@ -2681,6 +2683,55 @@ error: return 0; } +/** + * fit_all_image_check_hashes - verify data intergity for all images + * @fit: pointer to the FIT format image header + * + * fit_all_image_check_hashes() goes over all images in the FIT and + * for every images checks if all it's hashes are valid. + * + * returns: + * 1, if all hashes of all images are valid + * 0, otherwise (or on error) + */ +int fit_all_image_check_hashes (const void *fit) +{ + int images_noffset; + int noffset; + int ndepth; + int count; + + /* Find images parent node offset */ + images_noffset = fdt_path_offset (fit, FIT_IMAGES_PATH); + if (images_noffset < 0) { + printf ("Can't find images parent node '%s' (%s)\n", + FIT_IMAGES_PATH, fdt_strerror (images_noffset)); + return 0; + } + + /* Process all image subnodes, check hashes for each */ + printf ("## Checking hash(es) for FIT Image at %08lx ...\n", + (ulong)fit); + for (ndepth = 0, count = 0, + noffset = fdt_next_node (fit, images_noffset, &ndepth); + (noffset >= 0) && (ndepth > 0); + noffset = fdt_next_node (fit, noffset, &ndepth)) { + if (ndepth == 1) { + /* + * Direct child node of the images parent node, + * i.e. component image node. + */ + printf (" Hash(es) for Image %u (%s): ", count++, + fit_get_name (fit, noffset, NULL)); + + if (!fit_image_check_hashes (fit, noffset)) + return 0; + printf ("\n"); + } + } + return 1; +} + /** * fit_image_check_os - check whether image node is of a given os type * @fit: pointer to the FIT format image header diff --git a/include/image.h b/include/image.h index 46544858c86..8c63686d4de 100644 --- a/include/image.h +++ b/include/image.h @@ -574,6 +574,7 @@ int fit_image_hash_set_value (void *fit, int noffset, uint8_t *value, int value_len); int fit_image_check_hashes (const void *fit, int noffset); +int fit_all_image_check_hashes (const void *fit); int fit_image_check_os (const void *fit, int noffset, uint8_t os); int fit_image_check_arch (const void *fit, int noffset, uint8_t arch); int fit_image_check_type (const void *fit, int noffset, uint8_t type); -- cgit v1.3.1