From 4c26de2eea6bcf5f27b13da0372d27d767cd38e3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 1 May 2025 10:47:21 -0600 Subject: fs.h: Switch to using rtc_def.h This file only needs the definition of 'struct rtc_time' and that is found in . Use that instead of pulling in rtc.h to pull in rtc_def.h as rtc.h includes many other include files. Signed-off-by: Tom Rini --- include/fs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/fs.h b/include/fs.h index 731aaa02637..bec02117737 100644 --- a/include/fs.h +++ b/include/fs.h @@ -5,7 +5,7 @@ #ifndef _FS_H #define _FS_H -#include +#include struct cmd_tbl; -- cgit v1.3.1 From 5b82721337e271609419dce490884392085d8d1f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 14 May 2025 13:38:54 -0600 Subject: include/command.h: Drop Now that all of the cases of code that relied on to provide (or one of the headers that it includes, and so forth) have been fixed, we can drop the include from here. Signed-off-by: Tom Rini --- include/command.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/command.h b/include/command.h index 4158ca11b0e..5d225cd197f 100644 --- a/include/command.h +++ b/include/command.h @@ -10,7 +10,6 @@ #ifndef __COMMAND_H #define __COMMAND_H -#include #include #include -- cgit v1.3.1 From a6b479b7ad6d78811e6b5cc69a8704727a50fa62 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 27 May 2025 09:02:20 -0600 Subject: Squashed 'dts/upstream/' changes from 955176a4ff59..fe2d6c49bb4e fe2d6c49bb4e Merge tag 'v6.15-dts-raw' 3109849be809 Merge tag 'soc-fixes-6.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 75e59270f7c5 Merge tag 'mvebu-fixes-6.15-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/fixes 69a2cec41405 Merge tag 'sunxi-fixes-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/fixes 64a925d7605a dt-bindings: can: microchip,mcp2510: Fix $id path 50d5bacc52a4 Merge tag 'v6.15-rc7-dts-raw' b8973c10564b Merge tag 'soc-fixes-6.15-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc c88fc0f02e78 arm64: dts: marvell: uDPU: define pinctrl state for alarm LEDs 63756d9a84f8 Merge tag 'v6.15-rc6-dts-raw' 8de495f56dbd Merge tag 'input-for-v6.15-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input 7346db7cb1f5 Merge tag 'imx-fixes-6.15-2' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes a12444223f6a arm64: dts: amazon: Fix simple-bus node name schema warnings e605d5d7fe3d Merge tag 'asahi-soc-fixes-6.15' of https://github.com/AsahiLinux/linux into arm/fixes fff11fe6a218 Merge tag 'riscv-sophgo-dt-fixes-for-v6.15-rc1' of https://github.com/sophgo/linux into arm/fixes cbdc7e808a47 Merge tag 'amlogic-fixes-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into arm/fixes 6569e1afaabb Merge tag 'v6.15-rockchip-dtsfixes1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/fixes bad970d505c7 arm64: dts: imx8mp-var-som: Fix LDO5 shutdown causing SD card timeout 2498aef1d581 arm64: dts: imx8mp: use 800MHz NoC OPP for nominal drive mode 930a058ee559 Merge tag 'net-6.15-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 75e6b42a413a dt-bindings: net: ethernet-controller: Add informative text about RGMII delays 2fb1a42d2ab9 Merge tag 'soc-fixes-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 95bd2a8dfcd9 arm64: dts: amlogic: dreambox: fix missing clkc_audio node 84ef7812cc93 Merge tag 'v6.15-rc5-dts-raw' 724862669eee Merge tag 'spi-fix-v6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi e56b01802fc8 riscv: dts: sophgo: fix DMA data-width configuration for CV18xx f6364dd1ac42 arm64: dts: rockchip: fix Sige5 RTC interrupt pin b6c1f156299d arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp23 SoCs 40c14b9e5f5e arm64: dts: st: Adjust interrupt-controller for stm32mp23 SoCs 62bf1a9664d4 arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp21 SoCs fccc8448c30a arm64: dts: st: Adjust interrupt-controller for stm32mp21 SoCs ad0c99d174ea arm64: dts: st: Use 128kB size for aliased GIC400 register access on stm32mp25 SoCs 282b9c077aae arm64: dts: st: Adjust interrupt-controller for stm32mp25 SoCs 3755c90eab9c Merge tag 'imx-fixes-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes b4c1abf11ff1 Merge tag 'juno-fix-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/fixes c7c3c68f3ce7 dt-bindings: mediatek,mt6779-keypad: Update Mattijs' email address e4820115982e Merge tag 'v6.15-rc4-dts-raw' 5a4f16f09fb5 arm64: dts: imx8mm-verdin: Link reg_usdhc2_vqmmc to usdhc2 98e5be0c34f6 Revert "arm64: dts: allwinner: h6: Use RSB for AXP805 PMIC connection" d6354f04cfe0 arm64: dts: rockchip: Assign RT5616 MCLK rate on rk3588-friendlyelec-cm3588 22b5bf714835 arm64: dts: rockchip: Align wifi node name with bindings in CB2 f7cb03107c26 Merge tag 'char-misc-6.15-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc 4acdc261f422 spi: dt-bindings: snps,dw-apb-ssi: Add compatible for SOPHGO SG2042 SoC 2ebbc79f9b14 spi: dt-bindings: snps,dw-apb-ssi: Merge duplicate compatible entry 08939b65ca58 arm64: dts: amlogic: g12: fix reference to unknown/untested PWM clock 73915dad61e7 arm64: dts: amlogic: gx: fix reference to unknown/untested PWM clock fb321fd7cecd ARM: dts: amlogic: meson8b: fix reference to unknown/untested PWM clock 1499bef2c3a6 ARM: dts: amlogic: meson8: fix reference to unknown/untested PWM clock a831b6c1c6b9 ARM: dts: opos6ul: add ksz8081 phy properties 3ae5c171fc05 arm64: dts: imx95: Correct the range of PCIe app-reg region f118c5265c25 arm64: dts: imx8mp: configure GPU and NPU clocks in nominal DTSI e281122066ea Merge tag 'v6.15-rc3-dts-raw' 1d7ab1ed4277 arm64: dts: apple: touchbar: Mark ps_dispdfr_be as always-on b0dbfc0c19d7 dt-bindings: soc: fsl: fsl,ls1028a-reset: Fix maintainer entry 775d526af58f dt-bindings: timer: renesas,tpu: remove obsolete binding 739bb43d33b7 dt-bindings: nvmem: Add compatible for MSM8960 52f7f735cf15 dt-bindings: nvmem: Add compatible for IPQ5018 aeb6cb0b5324 dt-bindings: nvmem: fixed-cell: increase bits start value to 31 3a7b208d9e79 dt-bindings: nvmem: Add compatible for MS8937 1c27fc6ffa8e dt-bindings: nvmem: qfprom: Add X1E80100 compatible d35d917d5816 dt-bindings: nvmem: rockchip,otp: Add compatible for RK3576 759e7828fe78 dt-bindings: nvmem: rockchip,otp: add missing limits for clock-names e73a3d952883 arm64: dts: morello: Fix-up cache nodes 8386b46f9eda arm64: dts: rockchip: Fix mmc-pwrseq clock name on rock-pi-4 6b71f5ae1a2a arm64: dts: rockchip: Use "regulator-fixed" for btreg on px30-engicam for vcc3v3-btreg 2ed5901a514b dt-bindings: timer: nxp,sysctr-timer: Add i.MX94 support e58a2db4c38c dt-bindings: interrupt-controller: fsl,irqsteer: Add i.MX94 support 622ce6b1ba08 dt-bindings: display: nwl-dsi: Allow 'data-lanes' property for port@1 e0ef023c67c0 dt-bindings: xilinx: Remove myself from maintainership 0449e8973a84 Merge tag 'v6.15-rc1-dts-raw' b2db21710501 arm64: dts: rockchip: Add pinmuxing for eMMC on QNAP TS433 28265b46ce50 arm64: dts: rockchip: Remove overdrive-mode OPPs from RK3588J SoC dtsi 314cea8948b0 arm64: dts: rockchip: Allow Turing RK1 cooling fan to spin down 4314a01898d6 Merge tag 'input-for-v6.15-rc0' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input fcf2048dc9de Merge branch 'next' into for-linus ba6c6579c9bd Merge tag 'riscv-for-linus-6.15-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux 58f1d4c158c0 Merge tag 'rtc-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux 29912193033d Merge tag 'usb-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb 937ed4db2ab8 Merge tag 'tty-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty ac589474b57a Merge tag 'thermal-6.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm 6879712ce88d Merge tag 'i3c/for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux af2574352383 Merge tag 'linux-watchdog-6.15-rc1' of git://www.linux-watchdog.org/linux-watchdog e81f3d825b82 Merge tag 'i2c-for-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux bd876bc870df Merge tag 'dmaengine-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 42065dec6c72 Merge tag 'phy-for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy 301007542d03 Merge tag 'char-misc-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc 33b10181f970 Merge tag 'mm-nonmm-stable-2025-03-30-18-23' of git://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm d4643a038924 Merge patch series "Add some validation for vector, vector crypto and fp stuff" cac1aa08f484 dt-bindings: rtc: max31335: Add max31331 support 26e04cf9cc79 Merge tag 'mailbox-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox 576a6900f13c Merge tag 'for-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply 78a2eae6cb86 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 4194f888d6d6 Merge tag 'rproc-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux c96994fe39c1 Merge tag 'pinctrl-v6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl a42296696853 Merge tag 'backlight-next-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight 6d0f08e93b76 Merge tag 'leds-next-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/leds 3bb45cc2ceab Merge tag 'mfd-next-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd 72713c04060a Merge tag 'mips_6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 17102f25116b Merge tag 'devicetree-for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux e44d9139748a Merge tag 'v6.15-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6 b727a6e37d16 Merge tag 'pci-v6.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci b1ec05cb6a63 Merge tag 'drm-next-2025-03-28' of https://gitlab.freedesktop.org/drm/kernel 34c876511338 Merge tag 'for-6.15/io_uring-reg-vec-20250327' of git://git.kernel.dk/linux ddb37d4776e9 Merge tag 'for-6.15/io_uring-rx-zc-20250325' of git://git.kernel.dk/linux c0a3226a4218 dt-bindings: i2c: snps,designware-i2c: describe Renesas RZ/N1D variant f8da42670dd8 Merge tag 'powerpc-6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux 38106689da03 dt-bindings: edac: altera: socfpga: Convert to YAML 7fa97aa2cc14 dt-bindings: pps: gpio: Correct indentation and style in DTS example bc13b6ac45ca Merge branch 'pci/controller/xilinx-cpm' 51fe3683d562 Merge branch 'pci/controller/qcom' 14635816113e Merge branch 'pci/controller/mediatek' c27d458c9018 Merge branch 'pci/controller/brcmstb' 910bd393ba5a Merge branch 'pci/controller/amd-mdb' 99abd782f5d4 Merge branch 'pci/controller/altera' 2b19e48fbedc Merge branch 'pci/dt-bindings' ce77e68fec79 Merge tag 'soc-arm-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc c849f132da6e Merge tag 'soc-drivers-6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 253861a5926a Merge tag 'soc-dt-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc b171384a2380 Merge tag 'net-next-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next 725971c9baeb Merge tag 'iommu-updates-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux f39cd579edb7 Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi 7f1c5dc0d96a Merge tag 'ata-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux 1262e5915578 dt-bindings: mailbox: qcom: add compatible for MSM8226 SoC e81c74aaf2e0 dt-bindings: mailbox: fsl,mu: Add i.MX94 compatible f4f5865e81fd dt-bindings: mailbox: mediatek: Add support for MT8196 GCE mailbox e054cac9ae6e Merge tag 'timers-clocksource-2025-03-26' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip b03526c21450 Merge branches 'clk-allwinner', 'clk-amlogic' and 'clk-qcom' into clk-next a50392a2baf3 Merge branches 'clk-rockchip', 'clk-samsung' and 'clk-imx' into clk-next e595cb4e5772 Merge branches 'clk-parent', 'clk-renesas', 'clk-mediatek' and 'clk-cleanup' into clk-next dbd546c62c5c Merge tag 'mtd/for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux 2eecb8cbb591 Merge tag 'platform-drivers-x86-v6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86 9d2cd6a3b1d5 Merge tag 'nand/for-6.15' into mtd/next bd76b77d4e2c Merge tag 'sound-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound 2f3a8d13a1be Merge tag 'media/v6.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media 01edfbe94231 Merge tag 'pmdomain-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm 33e6daed2dcb Merge tag 'mmc-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc f661bbffece6 Merge tag 'gpio-updates-for-v6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux d98043246fc3 Merge tag 'hwmon-for-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging f88a116702ac Merge tag 'pwm/for-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux c1e80718e7c0 Merge tag 'spi-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 903bc8c7edc1 Merge tag 'regulator-v6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator 34d2a8ce3d44 Merge tag 'pm-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm be3477545a1b Merge tag 'for-net-next-2025-03-25' of git://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next f46587488060 dt-bindings: thermal: Correct indentation and style in DTS example ed91ea537f6b dt-bindings: thermal: Update for BCM74110 b56a3bd46a79 dt-bindings: thermal: tsens: Add ipq5332, ipq5424 compatible 408f714c8807 Merge tag 'irq-drivers-2025-03-23' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 2c7bdd5acc6a dt-bindings: net: bluetooth: nxp: Add support to set BD address c878bbbc7198 dt-bindings: net: bluetooth: qualcomm: document WCN3950 3ddbb8fb8fe6 dt-bindings: net: bluetooth: nxp: Add wakeup pin properties a4c451f881ed dt-bindings: net: qcom,ipa: Correct indentation and style in DTS example 86a6733d63fe Merge tag 'wireless-next-2025-03-20' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next 8604a4e6caa1 dt-bindings: net: rockchip-dwmac: Add compatible string for RK3528 cacfdfd63704 dt-bindings: riscv: document vector crypto requirements c9835a4f0732 dt-bindings: riscv: add vector sub-extension dependencies b21477b0a350 dt-bindings: riscv: d requires f a77e47812f3f dt-bindings: watchdog: sunxi: add Allwinner A523 compatible string bf3232c697af Merge tag 'i2c-host-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux into i2c/for-mergewindow 8f6d11a83a0a Merge tag 'docs-6.15' of git://git.lwn.net/linux 35477e322ba4 dt-bindings: PCI: Add common schema for devices accessible through PCI BARs a345b6688502 Merge tag 'asoc-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound into for-next 2baf484b277c Merge branch 'pm-cpufreq' 67a34184ddf2 dt-bindings: timer: Add SiFive CLINT2 2ddeb4d36e67 Merge tag 'cpufreq-arm-updates-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm f8ec1f1d1cc5 dt-bindings: remoteproc: Consolidate SC8180X and SM8150 PAS files 98322a22c22a dt-bindings: hwmon: Add Microchip emc2305 support e80e09439582 media: dt-bindings: mediatek,vcodec-encoder: Drop assigned-clock properties d8cea587c006 docs: dt-bindings: Specify ordering for properties within groups 83d44c13a32f dt-bindings: hwmon: Drop stray blank line in the header 28e3e5da1d38 dt-bindings: mfd: syscon: Add microchip,sama7d65-sfrbu cdb8f10e1aaa dt-bindings: mfd: syscon: Add microchip,sama7d65-ddr3phy 723b3cd19dd1 dt-bindings: i2c: spacemit: add support for K1 SoC c8e7edc109e3 dt-bindings: i2c: omap: Add mux-states property 6cd4c93c1892 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 0e19f27df8f7 Merge tag 'amlogic-arm-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt c65eff2dbcf7 Merge tag 'amlogic-arm64-dt-for-v6.15-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/dt bebc6d8370bf ASoC: wm8904: Add DMIC and DRC support 23803d09fa1b dt-bindings: serial: snps-dw-apb-uart: document RZ/N1 binding without DMA eb71e94b0058 dt-bindings: serial: snps-dw-apb-uart: Add support for rk3562 819c0d972e58 dt-bindings: serial: fsl-lpuart: support i.MX94 da1dc4f87d0d dt-bindings: serial: samsung: add exynos7870-uart compatible 0791859ab251 Merge tag 'coresight-next-v6.15' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/coresight/linux into char-misc-next 1c289ddb61bc ASoC: dt-bindings: wm8904: Add DMIC, GPIO, MIC and EQ support 64345bc61380 spi: dt-bindings: cdns,qspi-nor: Require some peripheral properties 00c70a06c714 spi: dt-bindings: cdns,qspi-nor: Deprecate the Cadence compatible alone c7b9fed01f76 spi: dt-bindings: cdns,qspi-nor: Be more descriptive regarding what this controller is 2951fd5da291 arm64: dts: Add gpio_intc node for Amlogic A5 SoCs b7ea7dda1e2e arm64: dts: Add gpio_intc node for Amlogic A4 SoCs 06138f903a3c Merge branches 'apple/dart', 'arm/smmu/updates', 'arm/smmu/bindings', 'rockchip', 's390', 'core', 'intel/vt-d' and 'amd/amd-vi' into next 8495ad389173 Merge tag 'dt-cleanup-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt a301f99cf614 Merge tag 'tegra-for-6.15-arm-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt cd03551a294d dt-bindings: gpu: arm,mali-midgard: add exynos7870-mali compatible 5b84d726ddaf Merge tag 'qcom-drivers-for-6.15-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers f10573df66cb Merge tag 'qcom-drivers-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers fa143ab38af1 Merge tag 'amlogic-drivers-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/drivers bab3f090d9d3 Merge tag 'reset-for-v6.15' of git://git.pengutronix.de/pza/linux into soc/drivers e13001093d96 Merge tag 'samsung-drivers-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers 56c3ca45c2c7 Merge tag 'at91-soc-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/arm 3b1e6f959fee Merge tag 'hisi-arm64-dt-for-6.15' of https://github.com/hisilicon/linux-hisi into soc/dt 75357dfed634 Merge tag 'riscv-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt 9737b7a849d5 Merge tag 'omap-for-v6.15/dt-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt 6432c5392792 Merge tag 'riscv-sophgo-dt-for-v6.15' of https://github.com/sophgo/linux into soc/dt 481e67465dc8 Merge tag 'mvebu-dt64-6.15-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt 96e8744cc103 Merge tag 'v6.15-rockchip-dts64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt 81ed54132fc0 Merge tag 'zynq-dt-for-6.15' of https://github.com/Xilinx/linux-xlnx into soc/dt 0a2824017157 Merge tag 'zynqmp-dt-for-6.14' of https://github.com/Xilinx/linux-xlnx into soc/dt 4e48222bf65f Merge tag 'sunxi-dt-for-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/dt b831e4e9bb20 Merge tag 'at91-dt-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt 6faf8a6c4970 Merge tag 'stm32-dt-for-v6.15-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt 29c62c6339a6 dt-bindings: deprecate "snps,en-tx-lpi-clockgating" property ac676ad15ceb ARM: dts: stm32: remove "snps,en-tx-lpi-clockgating" property a3aeb65b5e21 riscv: dts: starfive: remove "snps,en-tx-lpi-clockgating" property 86032de3cc2d Merge tag 'ieee802154-for-net-next-2025-03-10' of git://git.kernel.org/pub/scm/linux/kernel/git/wpan/wpan-next e3ae9db04517 dt-bindings: riscv: add Zaamo and Zalrsc ISA extension description 0cb4c6d785dc dt-bindings: i2c: i2c-rk3x: Add rk3562 support 3b5a8c070c44 dt-bindings: i2c: imx-lpi2c: add i.MX94 LPI2C ce1e60e777db dt-bindings: i2c: qup: Document interconnects ac988bf5af32 dt-bindings: i2c: qcom,i2c-qup: Document power-domains 9bcf0325b6ae dt-bindings: i2c: exynos5: add exynos7870-hsi2c compatible 497c36ba820d dt-bindings: i2c: samsung,s3c2410: add exynos7870-i2c compatible 2ba4ea354217 dt-bindings: mtd: atmel,dataflash: convert txt to yaml 3813b6843768 dt-bindings: mtd: gpmi-nand: Add compatible string for i.MX8 chips 4ba959479642 ASoC: codecs: Add aw88166 amplifier driver 559db5bb3df6 add sof support on imx95 f42c1e48e1ea dt-bindings: hwmon: Add description for sensor HTU31 3e54d6806c68 spi: Merge up fixes c4c47e5bb42f regulator: dt-bindings: rtq2208: Cleanup whitespace 1aae375c7c42 regulator: dt-bindings: rtq2208: Mark fixed LDO VOUT property as deprecated 6cf18ee31953 Merge patch series "riscv: Add bfloat16 instruction support" f306f44643f3 dt-bindings: riscv: add bfloat16 ISA extension description d1349a8d0aa7 arm64: dts: hi3660: Add property for fixing CPUIdle 8283ad10d5c2 Merge tag 'samsung-pinctrl-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel bba239dcd4d7 Merge net-next/main to resolve conflicts ee0acddba296 dt-bindings: rtc: pcf2127: Reference spi-peripheral-props.yaml eb3c4568ad0b dt-bindings: hwmon: ti,ina2xx: Add INA233 device 26e91a5c1c4d ASoC: dt-bindings: audio-graph-card2: add widgets and hp-det-gpios support 20f74f1fc993 ASoC: dt-bindings: support imx95's CM7 core 79ab7f994af8 Merge branch '20250313110359.242491-1-quic_mmanikan@quicinc.com' into clk-for-6.15 1a7ee5fd2be3 dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions 7665c77f7cdb dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX 832929f7a52a dt-bindings: hwmon: ltc2978: add support for LT717x 7758dfded334 dt-bindings: pinctrl: qcom: Add egpio function for sa8775p f2341866dbb8 dt-bindings: pinctrl: airoha: Add missing gpio-ranges property 9abb426254c5 dt-bindings: pinctrl: at91-pio4: add microchip,sama7d65-pinctrl d3812cbd3cf5 dt-bindings: rtc: qcom-pm8xxx: document qcom,no-alarm flag d2d31cf30f25 dt-bindings: interrupt-controller: Add support for Amlogic A4 and A5 SoCs 91922237393f Merge tag 'v6.14-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-next 49186c87530a dt-bindings: thermal: give OS some leeway in absence of critical-action b7e2002c7f37 dt-bindings: cpufreq: cpufreq-qcom-hw: Narrow properties on SDX75, SA8775p and SM8650 d3db8a0a1e18 dt-bindings: cpufreq: cpufreq-qcom-hw: Drop redundant minItems:1 9b493bef6c64 dt-bindings: cpufreq: cpufreq-qcom-hw: Add missing constraint for interrupt-names a0842ec452cb dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCS8300 compatible 08344f6cf323 dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps b58d82c6f35a ASoC: dt-bindings: fsl,sai: Add i.MX94 support 52fcce301d62 regulator: dt-bindings: pca9450: Add nxp,pf9453 compatible string 5a327e9ff15c ASoC: dt-bindings: mediatek,mt8188-mt6359: Add mediatek,accdet 9d8dfb82b770 ASoC: dt-bindings: Add schema for "awinic,aw88166" b21759520198 dt-bindings: phy: rockchip: Add rk3562 naneng-combophy compatible 3f127f8b13cf dt-bindings: phy: Add Rockchip MIPI C-/D-PHY schema 7fdfaa5e1649 arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0 e532d69208c3 arm64: dts: marvell: Use preferred node names for "simple-bus" 36438541d5f0 arm64: dts: marvell: Drop unused CP11X_TYPE define a6ee6a6bd390 arm64: dts: marvell: Move arch timer and pmu nodes to top-level dc3b5c12e6a4 dt-bindings: rng: rockchip,rk3588-rng: Drop unnecessary status from example 2df156046328 Merge tag 'ti-k3-dt-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt f57059f434cd Merge tag 'imx-dt64-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt 4378c7352b85 Merge tag 'imx-dt-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt 81231b09fca0 Merge tag 'imx-bindings-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt f185c678c9a4 Merge tag 'spacemit-dt-for-6.15-1' of https://github.com/spacemit-com/linux into soc/dt c18007158dda Merge tag 'davinci-updates-for-v6.15-rc1' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into soc/dt d24528c09c20 arm64: dts: rockchip: Fix PWM pinctrl names 2e5608c86650 arm64: dts: rockchip: fix RK3576 SCMI clock IDs 52dc545f0788 dt-bindings: clock: rk3576: add SCMI clocks 24b2d3f6703c arm64: dts: rockchip: Fix pcie reset gpio on Orange Pi 5 Max 8f7a008a36a0 Merge tag 'samsung-dt64-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt 02def44715b4 Merge tag 'asahi-soc-dt-6.15-v3' of https://github.com/AsahiLinux/linux into soc/dt 50a5056a0fbc Merge tag 'v6.15-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt abd4cba3fc31 Merge tag 'tegra-for-6.15-arm64-dt-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt a8cb4de20f8e Merge tag 'tegra-for-6.15-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt 920fc9d1facb arm64: dts: amd/seattle: Drop undocumented "spi-controller" properties 7303c3977e4a arm64: dts: amd/seattle: Fix bus, mmc, and ethernet node names bdc46b592528 arm64: dts: amd/seattle: Move and simplify fixed clocks 5767b5ef37dc arm64: dts: amd/seattle: Base Overdrive B1 on top of B0 version f66a26fc5063 Merge tag 'renesas-dts-for-v6.15-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt f94bc208615f dt-bindings: mfd: syscon: Add the pbus-csr node for Airoha EN7581 SoC a6586b520e84 bindings: pinctrl: ingenic: add x1600 c5f11db1dc9c dt-bindings: mfd: syscon: Add rk3528 QoS register compatible 99b871852f02 dt-bindings: mfd: atmel,sama5d2-flexcom: Add microchip,sama7d65-flexcom cee62549c1cf dt-bindings: mfd: qcom,tcsr: Add compatible for MSM8937 4b2dbbdb1106 dt-bindings: mfd: samsung,s2mps11: Add compatible for s2mpu05-pmic e53b55f7425b dt-bindings: regulator: Add TI TPS65214 PMIC bindings b70d9d3353c8 dt-bindings: regulator: Add TI TPS65215 PMIC bindings f8f2120feff1 dt-bindings: mfd: Convert fsl,mcu-mpc8349emitx binding to YAML fabf15359158 dt-bindings: mfd: stm32-timers: Add support for stm32mp25 27070527c9da Merge branches 'ib-mfd-input-leds-power-6.15', 'ib-mfd-power-6.15' and 'ib-mfd-regulator-6.15' into ibs-for-mfd-merged 3cfc089d7aee dt-bindings: can: fsl,flexcan: add i.MX94 support e0c8c7d1cba3 dt-bindings: can: fsl,flexcan: add transceiver capabilities 867ef82b4496 dt-bindings: usb: qcom,dwc3: Synchronize minItems for interrupts and -names 4cfef97e6f55 Merge tag 'iio-for-6.15a' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/jic23/iio into char-misc-next 2bbf5d333bbb Merge tag 'mediatek-drm-next-6.15-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next 1e57f81382d5 arm64: dts: freescale: Add support for the GOcontroll Moduline Display 5eb64fd18835 ASoC: sun4i-codec: add headphone dectection for 7818917a7583 dt-bindings: clocks: atmel,at91rm9200-pmc: add missing compatibles 6144fc934c1d dt-bindings: reset: fix double id on rk3562-cru reset ids cb698afb24b8 dt-bindings: spi: add compatibles for mt7988 c6d6437dbad2 dt-bindings: remoteproc: Add SM8750 MPSS 16f807a2f799 dt-bindings: power: qcom,kpss-acc-v2: add qcom,msm8916-acc compatible 9f908c3d4e3d ASoC: dt-bindings: sun4i-a10-codec: add hp-det-gpios 1cf4588d69c5 dt-bindings: connector: Add the GOcontroll Moduline module slot bindings dcf3f572da06 dt-bindings: vendor-prefixes: add GOcontroll fac0b8b2d03e ASoC: dt-bindings: tas2770: add compatible for TAS5770L 8af38e87bf30 ASoC: dt-bindings: tas27xx: add compatible for SN012776 7aa416c35ed5 arm64: dts: rockchip: Enable HDMI audio output for ArmSoM Sige7 bd4c8a1c08f9 arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C db7a99c423de arm64: dts: rockchip: Add SDHCI controller for RK3528 29d894b16a31 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net 5857b1d7ade2 arm64: dts: rockchip: Remove bluetooth node from rock-3a 8464126790be arm64: dts: rockchip: Move rk356x scmi SHMEM to reserved memory 208e3a0a442e dt-bindings: clock: qcom: Add compatible for QCM6490 boards b92c36eff4bf dt-bindings: clock: ti: Convert ti-clkctrl.txt to json-schema 0e87b6717e3c dt-bindings: dsp: fsl,dsp: Add resets property 6cc91fdea94d dt-bindings: reset: audiomix: Add reset ids for EARC and DSP 28a2aabbb6c4 dt-bindings: pinctrl: add compatible for Allwinner A523/T527 6b4d5de72979 dt-bindings: power: Add TH1520 SoC power domains a441545e25fc dt-bindings: firmware: thead,th1520: Add support for firmware node ecbefc112b34 regulator: dt-bindings: add documentation for s2mpu05-pmic regulators 678f2f84e7f4 dt-bindings: net: Define interrupt constraints for DWMAC vendor bindings 228d9ce5d3bb dt-bindings: net: rockchip-dwmac: Require rockchip,grf and rockchip,php-grf 20bbb3d2c8e7 dt-bindings: firmware: imx: add property reset-controller 5ba7b84e7bf0 dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7 568847bfd352 dt-bindings: display: mediatek: dpi: add power-domains example 32e09f864be1 arm64: dts: st: add stm32mp215f-dk board support 559d24b54b4e dt-bindings: stm32: document stm32mp215f-dk board da2175c8eedc arm64: dts: st: introduce stm32mp21 SoCs family 050105727605 arm64: dts: st: add stm32mp235f-dk board support 8a79caa82a70 dt-bindings: stm32: document stm32mp235f-dk board 6abc5bf17ba1 arm64: dts: st: introduce stm32mp23 SoCs family e95c2526d6e9 dt-bindings: stm32: add STM32MP21 and STM32MP23 compatibles for syscon c8aa9617a955 arm64: dts: st: add stm32mp257f-dk board support 5a615c7759c9 dt-bindings: stm32: document stm32mp257f-dk board fa94a630d90d dt-bindings: watchdog: renesas,wdt: Document RZ/G3E support c0aabcef7b8d dt-bindings: mmc: sunxi: add compatible strings for Allwinner A523 2486f6c1b421 dt-bindings: mmc: sunxi: Simplify compatible string listing 8ca3040b05de dt-bindings: mmc: sdhci-of-dwcmhsc: Add compatible string for RK3528 5b36bb4f4707 dt-bindings: mmc: rockchip-dw-mshc: Add compatible string for RK3528 8462dd3e6881 dt-bindings: mmc: renesas,sdhi: Document RZ/G3E support d274a3df0a12 dt-bindings: mmc: rockchip-dw-mshc: Add support for rk3562 56b744861176 dt-bindings: mmc: Add support for rk3562 eMMC eb9b6eec2dda arm64: dts: rockchip: Add AP6275P wireless support to ArmSoM Sige7 906b8cbb8d43 arm64: dts: rockchip: Enable HDMI audio outputs for Orange Pi 5 Plus 19e0533172f2 arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 Plus 0bbaa0ff4c09 arm64: dts: rockchip: Enable HDMI audio outputs for Orange Pi 5 Max 173563eb6666 arm64: dts: rockchip: Enable HDMI0 audio output for Orange Pi 5/5B 9895a2f169dd dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs b8f6cd67f8b3 dt-bindings: trivial-devices: Add Maxim max15301, max15303, and max20751 fc5147dfc750 dt-bindings: fsi: ibm,p9-scom: Add "ibm,fsi2pib" compatible 5f06f892eb53 Backmerge tag 'v6.14-rc6' into drm-next fb0e8021a68f dt-bindings: iio: adc: Add i.MX94 and i.MX95 support e15adeb19f02 dt-bindings: iio: adc: add AD7191 33496024fc8e dt-bindings: mmc: atmel,hsmci: Convert to json schema 7ab9faf87206 dt-bindings: mmc: mmc-slot: Make compatible property optional ff4a69b28cf8 dt-bindings: mmc: fsl-imx-esdhc: Add i.MX94 support b6c174fc7de2 dt-bindings: mmc: Change to additionalProperties to fix fail detect Unevaluated property 502377fe32de dt-bindings: mmc: samsung,exynos-dw-mshc: add exynos7870 support d6ee3c852b25 dt-bindings: PCI: xilinx-cpm: Add compatible string for CPM5NC Versal Net host a19185cc15d1 Merge tag 'at24-updates-for-v6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux into i2c/for-mergewindow 0677248b0e32 dt-bindings: arm-smmu: Document QCS8300 GPU SMMU efd6b0348bfa dt-bindings: spi: add SG2044 SPI NOR controller driver d0f43207a01a dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2 8d4b83e94b40 dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the SM8750 QMP UFS PHY eeae88998b40 dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy 26a91c680522 ARM: dts: stm32: Add Plymovent AQM devicetree 4c21b9c842e3 ARM: dts: stm32: Add pinmux groups for Plymovent AQM board 904f0d522b88 dt-bindings: arm: stm32: Add Plymovent AQM board a3a3221056c9 dt-bindings: sound: convert ICS-43432 binding to YAML 2f91de2a490b ARM: dts: apalis/colibri-imx6: Add support for v1.2 9eb0618252aa ARM: dts: apalis/colibri-imx6: Enable STMPE811 TS f758e0d13235 dt-bindings: arm: fsl: Add VAR-SOM-MX6UL SoM and Concerto board f76216ee5bc2 ARM: dts: imx6ul: Add Variscite Concerto board support dd6e0d48db76 ARM: dts: imx6ul: Add Variscite VAR-SOM-MX6UL SoM support b3d9184831ad arm64: dts: imx8qm-apalis: Remove compatible from SoM dtsi 517caee96f7e ARM: dts: vf610-colibri: Remove compatible from SoM dtsi 5656930f43b4 ARM: dts: imx6qdl-apalis/colibri: Remove compatible from SoM dtsi fad232a946b4 dt-bindings: arm: fsl: drop usage of Toradex SOMs compatible alone ea11d8d98354 arm64: dts: imx8mp: change AUDIO_AXI_CLK_ROOT freq. to 800MHz 0b17f7c82b59 arm64: dts: imx8mp: add AUDIO_AXI_CLK_ROOT to AUDIOMIX block 2bc9da478485 arm64: dts: imx93: add ddr edac support ab9bf8d19072 arm64: dts: imx95: add ref clock for pcie nodes 1ad5ffe68e35 arm64: dts: mba8xx: Remove invalid property disable-gpio ef030623665a ARM: dts: imx6ul-tqma6ul1: Change include order to disable fec2 node 1c284ff7a69f arm64: dts: imx8qm-ss-hsio: Wire up DMA IRQ for PCIe 4456f7d29f3a arm64: dts: im8mq-librem5: move dwc3 usb port under ports 9a66f214f03d arm64: dts: mba8mx: change sound card model name 4749d122ddde arm64: dts: imx8mp-tqma8mpql-mba8mpxl: change sound card model name 5269104e27e3 arm64: dts: s32g: add FlexCAN[0..3] support for s32g2 and s32g3 71b653961ab8 dt-bindings: arm: fsl: add i.MX95 15x15 EVK board 1ebef3515785 arm64: dts: imx95: Add imx95-15x15-evk support 9726256fedee arm64: dts: imx95: Add i3c1 and i3c2 94ef2b4371a4 arm64: dts: imx95: Add #io-channel-cells = <1> for adc node d73e4f93cd40 ARM: dts: imx53-mba53: Fix the PCA9554 compatible acd5a974e760 ARM: dts: imx31: Use nand-controller as node name 81ad2fe2f7b5 ARM: dts: vfxxx: Fix the order of the DMA entries 5447ae84fa8f ARM: dts: tqma7: Add partitions subnode to spi-nor 1ccfa18431b4 ARM: dts: imx7-tqma7: Add vcc-supply for spi-nor 1743d93ea655 ARM: dts: tqma6ul: Add partitions subnode to spi-nor acde6cbf9cdf ARM: dts: imx6ul-tqma6ul: Add vcc-supply for spi-nor c3ce52f0a98e ARM: dts: imx6ul-tqma6ul: Order DT properties 83b725debc91 ARM: dts: imx6qdl-tqma6: Add partitions subnode to spi-nor 4169f66d2bb7 ARM: dts: imx6qdl-tqma6: use sw4_reg as 3.3V supply 851b1c7d93cb ARM: dts: imx6qdl-tqma6: limit PMIC SW4 to 3.3V 2cb7d799b230 ARM: dts: imx6qdl-tqma6: Order DT properties d4c064aa4ec4 arm64: dts: imx8mp-skov: support new 7" panel board c8cb767887b4 arm64: dts: imx8mp-skov: add revC BD500 board ea4b50b721d7 arm64: dts: imx8mp-skov: describe I2C bus recovery for all controllers 93fe81be94fe arm64: dts: imx8mp-skov: move I2C2 pin control group into DTSI 4e3e1bd5602f arm64: dts: imx8mp-skov: add basic board as fallback 26e62120b67b dt-bindings: arm: fsl: add more compatibles for Skov i.MX8MP variants d9eebb23bec4 arm64: dts: freescale: imx8mp-skov: operate SoC in nominal mode 1dd517527ec2 arm64: dts: freescale: imx8mp-skov: configure LDB clock automatically 9fe870aa5fbb arm64: dts: imx8mp: add fsl,nominal-mode property into nominal.dtsi 36d591413641 arm64: dts: imx8mp: Add optional nominal drive mode DTSI 04b0ce30ed9a Merge patch series "scsi: ufs: renesas: Add support for R-Car S4-8 ES1.2" c0c684cc130f scsi: ufs: dt-bindings: renesas,ufs: Add calibration data fc09bffd40a1 arm64: dts: imx8mp: configure GPU and NPU clocks to overdrive rate bd3329807adb arm64: dts: freescale: ten64: add usb hub definition 4057bd794cb2 Merge tag 'drm-msm-next-2025-03-09' of https://gitlab.freedesktop.org/drm/msm into drm-next 31ae3a9262da dt-bindings: dma: snps,dw-axi-dmac: Allow devices to be marked as noncoherent 1b13b0914156 dt-bindings: dma: Convert fsl,elo*-dma to YAML c3ed4efc2e50 dt-bindings: dma: fsl-mxs-dma: Add compatible string for i.MX8 chips aa353c2ac5c5 dt-bindings: input: goodix,gt9916: Document gt9897 compatible 6eb8cce7644b dt-bindings: pwm: imx: Add i.MX93, i.MX94 and i.MX95 support cbd6df2de511 ARM: dts: stm32: Add support for STM32MP13xx DHCOR SoM and DHSBC rev.200 board 3167db834dfa ARM: dts: stm32: use IRQ_TYPE_EDGE_FALLING on stm32mp157c-dk2 b83d9874fa79 dt-bindings: gpio: vf610: Add i.MX94 support 58ce3a6f5491 Merge v6.14-rc6 into usb-next ee4310889b80 dt-bindings: phy: document Allwinner A523 USB-2.0 PHY e2e13ecd8aa4 dt-bindings: soc: samsung: exynos-usi: Drop unnecessary status from example 13c7fa153448 dt-bindings: watchdog: fsl-imx7ulp-wdt: Add i.MX94 support 6fc9ef1dce8b ASoC: dmic: add regulator support f33253da3ed0 dt-bindings: pwm: rockchip: Add rockchip,rk3528-pwm df96b42ccaa5 arm64: dts: rockchip: Add SPI NOR device on the ROCK 4D 8af8429d4741 arm64: dts: rockchip: Add SFC nodes for rk3576 460ef5b623e5 arm64: dts: rockchip: Add maskrom button to Radxa E20C 8ba64ba5cb30 arm64: dts: rockchip: Add SARADC node for RK3528 6793b56b79df arm64: dts: rockchip: Add user button to Radxa E20C a3556ede6b48 arm64: dts: rockchip: Add leds node to Radxa E20C 4dc91efae86b arm64: dts: rockchip: Add HDMI support for rock-4d 6e03c7e28e2d arm64: dts: rockchip: enable SCMI clk for RK3528 SoC 2bdc1b582fc5 arm64: dts: rockchip: Enable HDMI receiver on rock-5b be8c63cd54f8 arm64: dts: rockchip: Add device tree support for HDMI RX Controller 9ee90dfd6957 arm64: dts: rockchip: Add rk3528 QoS register node cc3c4cf475e2 dt-bindings: mfd: syscon: Add rk3528 QoS register compatible de0d9c50f68f ASoC: dt-bindings: fsl,imx-asrc: Document audio graph port 2e3ffd78169f ASoC: dt-bindings: add regulator support to dmic codec 0946c7535fed dt-bindings: PCI: fsl,layerscape-pcie-ep: Drop unnecessary status from example 0d08b7785cbf dt-bindings: PCI: fsl,layerscape-pcie-ep: Drop deprecated windows 499ff8f6f00e dt-bindings: crypto: qcom,prng: document QCS615 137ebe3e9e23 dt-bindings: crypto: inside-secure,safexcel: Allow dma-coherent 19a0ed3478a5 dt-bindings: net: Add support for Sophgo SG2044 dwmac 01ec431b0809 dt-bindings: display/msm: dsi-controller-main: Add missing minItems 899bbe0128ad dt-bindings: display/msm: dsi-controller-main: Combine if:then: entries b6b83575709d dt-bindings: memory-controllers: qcom,ebi2: Enforce child props 7a5a115214b1 dt-bindings: memory-controllers: samsung,exynos4210-srom: Enforce child props 5cbcded3d915 arm64: tegra: p2180: Add TMP451 temperature sensor node bb4e0081de49 arm64: tegra: p2597: Enable TCA9539 as IRQ controllers 64bca56d40df arm64: tegra: Define pinmuxing for gpio pads on Tegra210 a2afd5dbc694 arm64: tegra: p2597: Fix gpio for vdd-1v8-dis regulator 3074f948c0f0 arm64: tegra: Resize aperture for the IGX PCIe C5 slot 0556e73ad468 arm64: tegra: Remove the Orin NX/Nano suspend key 5075ae527c32 dt-bindings: timer: exynos4210-mct: add samsung,exynos2200-mct-peris compatible b2d611510011 dt-bindings: timer: exynos4210-mct: Add samsung,exynos990-mct compatible e25abb336b06 dt-bindings: timer: Correct indentation and style in DTS example 27659631b1ab ARM: dts: marvell: armada: Align GPIO hog name with bindings 45d76d30bd18 ARM: dts: marvell: kirkwood-openrd: Align GPIO hog name with bindings ed88cf59518a arm64: dts: marvell: armada-8040: Align GPIO hog name with bindings fd8985afa234 dt-bindings: Document Tegra114 HDA support 514aa1e9d711 dt-bindings: display: tegra: Document Tegra124 MIPI 6f895e2fc34b Merge branch 'for-6.15/io_uring-rx-zc' into for-6.15/io_uring-reg-vec 783a9ff2b877 arm64: dts: tesla: Change labels to lower-case fb95fa637210 arm64: dts: exynos: gs101: Change labels to lower-case 8bb1ecf374d2 arm64: dts: ti: k3-am62a-phycore-som: Reorder properties per DTS coding style b7183e25919b arm64: dts: ti: k3-am642-phyboard-electra: Reorder properties per DTS coding style d3e54c73fad8 arm64: dts: ti: k3-am642-phyboard-electra: Add boot phase tags c198a9892aee arm64: dts: ti: k3-am62a-phycore-som: Add boot phase tags 7adcaf738ea2 arm64: dts: ti: k3-am62x-phyboard-lyra: Add boot phase tags 08a8be409da1 Merge tag 'ath-next-20250305' of git://git.kernel.org/pub/scm/linux/kernel/git/ath/ath b6eb736bdac9 dt-bindings: irq: sun7i-nmi: Document the Allwinner A523 NMI controller 29c23eb9e1e4 dt-bindings: net: Add FSD EQoS device tree bindings 7fcf7786e3c1 dt-bindings: ieee802154: ca8210: Update polarity of the reset pin 63f785ba85d6 dt-bindings: i3c: silvaco: Add npcm845 compatible string 4e7d4a0a5a98 dt-bindings: i3c: dw: Add power-domains 60779b9e5efd arm64: dts: apple: t8015: Add backlight nodes d1c2cf3d6db3 arm64: dts: apple: t8010: Add backlight nodes c493ad2b695a arm64: dts: apple: s800-0-3: Add backlight nodes 2a527cb076cb arm64: dts: apple: t7000: Add backlight nodes 8c09890d8a3a arm64: dts: apple: s5l8960x: Add backlight nodes 644d720366d7 spi: dt-bindings: fsl-lpspi: Add i.MX94 support 43baf3d00dd4 ARM: tegra: tf101: Add al3000a illuminance sensor node 01ff58401e94 dt-bindings: display: mitsubishi,aa104xd12: Adjust allowed and required properties 76f79fd8d2e1 dt-bindings: display: mitsubishi,aa104xd12: Allow jeida-18 for data-mapping 753638f98d53 ARM: tegra: Add DSI-A and DSI-B nodes on Tegra124 0dc63e559158 ARM: tegra: Add HDA node on Tegra114 c21c9d411a7b ARM: tegra: Add ARM PMU node on Tegra114 c169b6a13648 ARM: tegra: Switch DSI-B clock parent to PLLD on Tegra114 ce08790716a2 dt-bindings: media: mediatek,vcodec: Revise description 1d7d1f1bb863 dt-bindings: media: mediatek,jpeg: Relax IOMMU max item count 84ee1a870bac Merge tag 'mtk-dts64-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt aded2fb69436 arm64: dts: nvidia: Remove unused and undocumented "regulator-ramp-delay-scale" property ee85d6d69363 Merge tag 'juno-updates-6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/dt 9591e80db9de Merge tag 'asahi-soc-dt-6.15-v2' of https://github.com/AsahiLinux/linux into soc/dt c078f53218f7 Merge tag 'renesas-dts-for-v6.15-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt ba3eae2fe133 Merge tag 'renesas-dt-bindings-for-v6.15-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt 3077a635de45 Merge tag 'ixp4xx-dts-soc-for-v6.15' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into soc/dt 5dc02a7bec60 Merge tag 'asahi-soc-dt-6.15' of https://github.com/AsahiLinux/linux into soc/dt 131231dc887a arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable Mali-G31 f6f80ad2a1f4 arm64: dts: renesas: r9a09g057: Add Mali-G31 GPU node bbda080c8952 arm64: dts: rockchip: add MNT Reform 2 laptop eb0d04e0938d dt-bindings: arm: rockchip: Add MNT Reform 2 (RCORE) ef01ba18d719 dt-bindings: soc: rockchip: Add RK3528 VPU GRF syscon 9d39d8aa54eb dt-bindings: soc: rockchip: Add RK3528 VO GRF syscon 2f989dc849ab dt-bindings: PCI: fsl,imx6q-pcie: Add optional DMA interrupt f139ea2f5a06 dt-bindings: PCI: Convert fsl,mpc83xx-pcie to YAML 1dfe7500437d dt-bindings: PCI: qcom: Document the IPQ5332 PCIe controller f83683dd6f9e arm64: dts: mediatek: mt8395-radxa-nio-12l: Add Radxa 8 HD panel 9595aadd9a31 arm64: dts: mediatek: mt8395-nio-12l: Prepare MIPI DSI port 9f598f6af2a3 arm64: dts: mediatek: mt8390-genio-common: Add delay codec for DMIC b152da61f6cd arm64: dts: mediatek: mt8390-genio-common: Add routes for DMIC 7f5ef01f6c71 arm64: dts: mediatek: mt8395-nio-12l: Preconfigure DSI0 pipeline 7cefb6741548 arm64: mediatek: mt8195-cherry: Add graph for eDP and DP displays bd0418035afa arm64: dts: mediatek: mt8195: Add base display controller graph 67a479e22dd9 arm64: dts: airoha: en7581: Fix clock-controller address 9f3a44607c09 arm64: dts: airoha: en7581: Add more nodes to EN7581 SoC evaluation board 6d3ac809c14a arm64: dts: mediatek: mt8390-genio-common: Configure touch vreg pins f607df354b84 arm64: dts: mediatek: mt8188-geralt: Add graph for DSI and DP displays b62844c6033e arm64: dts: rockchip: Enable hdmi out display for rk3576-evb-v10 70636ab4c427 dt-bindings: PCI: altera: Add binding for Agilex 5f2ac732a000 dt-bindings: qcom: geni-se: Add 'firmware-name' property for firmware loading eb0afea35cd3 ASoC: Merge up fixes a7fdc3022cc4 dt-bindings: soc: samsung: exynos-pmu: add exynos7870-pmu compatible 09611d37a4a2 dt-bindings: media: Document bindings for HDMI RX Controller 5733784ecab2 dt-bindings: gpio: loongson: Add new loongson gpio chip compatible bde0820c0330 dt-bindings: pinctrl: Add bindings for BCM21664 pin controller 99ef71a02c72 dt-bindings: input: matrix_keypad - add wakeup-source property 6cc85963b28f arm64: dts: ti: k3-j722s-evm: Add camera peripherals f57767d39255 arm64: dts: ti: k3-j722s-main: Add CSI2RX nodes 5f079de69dbc arm64: dts: ti: k3-j722s-main: Add BCDMA CSI overrides fc74dd76227a arm64: dts: ti: k3-j722s: fix pinctrl settings 5916cffba231 arm64: dts: ti: k3-am62p: fix pinctrl settings d442b5177760 arm64: dts: ti: am64-phyboard-electra: Add DT overlay for X27 connector 598a53f305e4 dt-bindings: remoteproc: qcom,wcnss-pil: Add support for single power-domain platforms cda103526016 dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8926 893c449685ce dt-bindings: remoteproc: qcom,msm8916-mss-pil: Add MSM8226 e9fa3e49686b dt-bindings: remoteproc: qcom,msm8916-mss-pil: Support platforms with one power domain c9ba86664ced dt-bindings: remoteproc: Add SM8750 CDSP 0727f5f07392 dt-bindings: display/msm: qcom, sa8775p-mdss: Add missing eDP phy 0e759e398167 dt-bindings: remoteproc: qcom,sm6115-pas: Use recommended MBN firmware format in DTS example ad59df2a8e47 dt-bindings: net: Convert fsl,gianfar to YAML ecac8517df71 dt-bindings: net: fsl,gianfar-mdio: Update information about TBI 9f27542c356c dt-bindings: net: Convert fsl,gianfar-{mdio,tbi} to YAML f3d1127d6da2 arm64: dts: rockchip: Enable hdmi display on sige5 4353815d5413 arm64: dts: rockchip: Add hdmi for rk3576 e898135e14ac arm64: dts: rockchip: Add vop for rk3576 c4a8c85028f9 ARM: dts: microchip: sama7g5: add ADC hw trigger edge type e415d0ace351 ASoC: fsl_audmix: support audio graph card for audmix 81dd10b4d87c dt-bindings: arm: Add Coresight TMC Control Unit hardware 5ffae977c446 Merge tag 'wireless-next-2025-03-04-v2' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next 8cdbfaccfe40 dt-bindings: iio: adc: ad7380: add adaq4381-4 compatible parts c35357650277 dt-bindings: iio: adc: Add rockchip,rk3562-saradc string ffdcbd963d7a dt-bindings: iio: adc: Add rockchip,rk3528-saradc variant 9ca8f9827434 arm64: dts: rockchip: Add ES8388 audio codec fallback on RK3588 boards f8fb45ddefb3 arm64: dts: rockchip: Add ES8388 audio codec fallback on RK3399 ROC PC PLUS 45ccbb3708d1 dt-bindings: iio: light: al3010: add al3000a support 2dcb97b015ba Add STM32MP25 SPI NOR support 663e168d3026 ASoC: dt-bindings: everest,es8328: Require reg property 5973f33d36e4 ASoC: dt-bindings: everest,es8328: Mark ES8388 compatible with ES8328 d5fdb2909430 dt-bindings: net: airoha: Add airoha,npu phandle property 4b02ac198dfd dt-bindings: net: airoha: Add the NPU node for EN7581 SoC 9bcf6ccdd87c arm64: dts: rockchip: Add uart0 pinctrl to Radxa E20C 89a24fa2e923 arm64: dts: rockchip: Add pinctrl and gpio nodes for RK3528 340a7d991681 dt-bindings: soc: rockchip: Add RK3528 ioc grf syscon 2484bd1527c8 dt-bindings: mtd: physmap: Ensure all properties are defined 9a114f2cbbc5 dt-bindings: mtd: mxc-nand: Document fsl,imx31-nand 33bcbf56e498 dt-bindings: gpio: mvebu: Add missing 'gpio-ranges' property and hog nodes 9a17c1dc8a52 dt-bindings: pinctrl: Add pinctrl support for RK3528 a8fac5afd00e dt-bindings: clock: qcom: sm8450-camcc: Remove qcom,x1e80100-camcc leftover 3d038aa84fac dt-bindings: display: vop2: Add rk3576 support 539c3db87e49 dt-bindings: display: vop2: Add missing rockchip,grf property for rk3566/8 fc2f169c14d8 dt-bindings: display: vop2: describe constraint SoC by SoC a9175c1faaf6 arm64: dts: apple: Add touchbar screen nodes 0a30c2fb605b dt-bindings: PCI: mediatek-gen3: Add mediatek,pbus-csr phandle array property 6c0991dfe309 ARM: dts: microchip: sama7d65: Add watchdog for sama7d65 3a5c0b5439e4 arm64: dts: corstone1000: Add definitions for secondary CPU cores 760344eaf4df dt-bindings: clock: imx8m: document nominal/overdrive properties 3ebf9fab8556 dt-bindings: display: Add Apple pre-DCP display controller 45f020c2ff12 dt-bindings: clock: imx8mp: add axi clock 25a9aae37c46 ASoC: dt-bindings: fsl,audmix: make 'dais' property to be optional 39ab44f1f451 ASoC: dt-bindings: fsl,audmix: Document audio graph port 751e72c4a42f ASoC: dt-bindings: fsl,sai: Document audio graph port 375185829d56 spi: dt-bindings: Introduce qcom,spi-qpic-snand ca5abc134e5c dt-bindings: spi: Add STM32 OSPI controller 18e6b1036205 dt-bindings: PCI: amd-mdb: Add AMD Versal2 MDB PCIe Root Port Bridge f8432e8085b8 dt-bindings: PCI: dwc: Add AMD Versal2 MDB SLCR support f3240bd9ff15 dt-bindings: usb: samsung,exynos-dwc3: add exynos7870 support 578e6366fe17 dt-bindings: usb: dwc3: Add support for rk3562 9c7380c08c12 dt-bindings: usb: generic-xhci: Allow dma-coherent f5355ed2d30b dt-bindings: usb: richtek,rt1711h: Add missing vbus power supply 2fecbb897235 dt-bindings: pinctrl: samsung: add exynos7870-wakeup-eint compatible 6acd675fdb2b dt-bindings: pinctrl: samsung: add exynos7870-pinctrl compatible 64247b825e83 arm64: dts: qcom: gaokun3: Add Embedded Controller node 0de83bdbd702 dt-bindings: platform: Add Huawei Matebook E Go EC 8c7e026bceb2 arm64: dts: ti: k3-j784s4-j742s2-main-common: Fix serdes_ln_ctrl reg-masks b0f3437e4eed arm64: dts: ti: k3-am62p: Enable AUDIO_REFCLKx 7abf45296c55 dt-bindings: hwmon: gpio-fan: Add optional regulator support ad715d63d5b9 dt-bindings: hwmon: Add UCD90320 gpio description 94282ccb3f77 dt-bindings: hwmon: ntc-thermistor: fix typo regarding the deprecation of the ntc, compatibles 37c47e53b269 dt-bindings: display: mediatek: dsc: Add MT8188 compatible a880ab46aaf3 ARM: dts: microchip: sama7d65: Enable shutdown controller 5bf0dfe3a93e ARM: dts: microchip: sama7d65: Add SFRBU support to sama7d65 ceb3ca267777 ARM: dts: microchip: sama7d65: Add RTC support for sama7d65 33d484179e01 ARM: dts: microchip: sama7d65: Add Shutdown controller support 3a833187b48a ARM: dts: microchip: sama7d65: Add Reset Controller to sama7d65 SoC cb7d22318d14 arm64: dts: ti: k3-am62-phycore-som: Reserve RTOS IPC memory de40a5c334d5 arm64: dts: ti: k3-am64-phycore-som: Reserve RTOS IPC memory c1de68dfb465 arm64: dts: ti: k3-am62p5-sk: Add serial alias fc3a3408782e arm64: dts: ti: k3-am62a7-sk: Add serial alias 89fb433abb4a arm64: dts: ti: k3-am62x-sk-common: Add serial aliases b40599be6e89 arm64: dts: ti: k3-am62p5-sk: Support SoC wakeup using USB1 wakeup 4e21f0928a3c arm64: dts: ti: k3-am625-beagleplay: Reserve 128MiB of global CMA 0e6efc73fbc4 arm64: dts: ti: k3-j721e-sk: Add boot phase tag to SERDES3 e62cc3a65c52 arm64: dts: ti: k3-j721e-common-proc-board: Add boot phase tag to SERDES3 df13b922a34e arm64: dts: ti: k3-am62p-j722s-common-wakeup: Configure ti-sysc for wkup_uart0 d5e905102b12 arm64: dts: ti: k3-am62a7-sk: Add alias for RTC f0a08fa6651e arm64: dts: ti: k3-j721s2-som-p0: Add flash partition details 49435c1a2a18 arm64: dts: ti: k3-am62-verdin-dahlia: add Microphone Jack to sound card dbb5bd13ad09 arm64: dts: ti: k3-j784s4-j742s2-main-common: Correct the GICD size e42f6f652b25 arm64: dts: ti: k3-am62p5-sk: Add boot phase tag for USB0 d6d559bbf2a6 arm64: dts: ti: k3-am62a7-sk: Add boot phase tag for USB0 26e1b575e84d dt-bindings: display: mediatek: dpi: Add MT8195 and MT8188 compat c32424d952a8 dt-bindings: crypto: Convert fsl,sec-2.0 to YAML 83100c586db1 dt-bindings: clock: add clock definitions and documentation for exynos7870 CMU 839f40a5722d dt-bindings: clock: add Exynos2200 SoC 22fe2b154172 dt-bindings: iommu: qcom,iommu: Add MSM8937 IOMMU to SMMUv1 compatibles 34189497288b dt-bindings: pwm: rockchip: Add rockchip,rk3562-pwm 9afffc8f0f22 dt-bindings: interrupt-controller: Convert nxp,lpc3220-mic.txt to yaml format 7fa643245f20 dt-bindings: gpu: Add rockchip,rk3562-mali compatible 3abda087dbf6 Merge branch 'v6.15-shared/clkids' into v6.15-clk/next 8cd451e705ff dt-bindings: clock: Add RK3562 cru 1f94b7afa565 arm64: dts: rockchip: add usb typec host support to rk3588-jaguar 05453dc67f58 dt-bindings: wireless: ath12k: Strip ath12k prefix from calibration property da3621d60f14 dt-bindings: wireless: ath11k: Strip ath11k prefix from calibration property 6fdc1d052416 dt-bindings: wireless: ath10k: Strip ath10k prefix from calibration properties 9861592542dd dt-bindings: display/msm/gmu: Add Adreno 623 GMU 8e07cd8d79b5 arm64: dts: rockchip: Add GPU power domain regulator dependency for RK3588 4c6cdea070ff mdomain: Merge branch dt into next af3fb092d876 dt-bindings: power: rockchip: add regulator support 1de33272f6b5 pmdomain: Merge tag 'v6.14-rc4' from Linus into next 922c569881d6 ARM: dts: microchip: fix faulty ohci/ehci node names 2a4f0bc75929 ARM: dts: microchip: usb_a9263: fix wrong vendor 22c00bf9a9ec dt-bindings: ARM: at91: add Calao USB boards 00a259802c74 dt-bindings: ARM: at91: make separate entry for Olimex board f7ecad4dfdba arm64: dts: amlogic: g12: switch to the new PWM controller binding e594907dbba0 arm64: dts: amlogic: axg: switch to the new PWM controller binding 0db68c194ba8 arm64: dts: amlogic: gx: switch to the new PWM controller binding 07569029f06a ARM: dts: amlogic: meson8b: switch to the new PWM controller binding 45a895b33ca6 ARM: dts: amlogic: meson8: switch to the new PWM controller binding ecad1190684f dt-bindings: input: matrix_keypad - add missing property 7a5e2e594dcc Merge branch 'ib-amlogic-a4' into devel 84ad7c66e08d dt-bindings: pinctrl: Add support for Amlogic A4 SoC 81d115cd787a Merge branch 'ib-sophgo' into devel 2fb57a80ac82 dt-bindings: pinctrl: Add pinctrl for Sophgo SG2042 series SoC d25e98a2e1d9 dt-bindings: clock: mediatek: Add SMI LARBs reset for MT8188 9d4fce6bf871 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net b0f9f15fa3eb arm64: dts: rockchip: Enable HDMI1 audio output for Orange Pi 5 Ultra cb7a017df5cc arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 Ultra 7a10dcdcf5dd arm64: dts: rockchip: Add Orange Pi 5 Ultra board bb2d35f7447a dt-bindings: arm: rockchip: Add Xunlong Orange Pi 5 Ultra c61a839ade98 arm64: dts: rockchip: Adapt to differences between Orange Pi 5 Max and Ultra f46eeb290a49 arm64: dts: rockchip: add hdmi1 support to ROCK 5 ITX 8abf4e075936 arm64: dts: rockchip: Enable HDMI audio outputs for Rock 5B a779ebd82fb1 arm64: dts: rockchip: Add HDMI audio outputs for rk3588 b0c3cbe5b68d arm64: dts: rockchip: Enable HDMI1 on rk3588-evb1 40f977e4d24d arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on RK3588 2f30db59cf45 arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588 027b0ef80afb spi: dt-bindings: Add rk3562 support 2533797ddce2 arm64: dts: morello: Add support for fvp dts 9f5663971e1f arm64: dts: morello: Add support for soc dts 3ff25bf13939 arm64: dts: morello: Add support for common functionalities 64de0a722178 dt-bindings: arm-pmu: Add support for ARM Rainier PMU 503c66e651f9 dt-bindings: arm: Add Rainier compatibility f67be59b2a9a dt-bindings: arm: Add Morello fvp compatibility 9cb3ba5bb59e dt-bindings: arm: Add Morello compatibility 910e9d8438ef mips: dts: ralink: mt7628a: update system controller node and its consumers 0e7913ce1f04 dt-bindings: display: panel: Add Visionox RM692E5 33660ef35f42 dt-bindings: display: panel: Add Raydium RM67200 b9abbea75728 ARM: dts: stm32: add usr3 LED node to stm32f769-disco 972663879bc7 ARM: dts: stm32: rename LEDs nodes for stm32f769-disco f5f056e5d15d ARM: dts: stm32: add push button to stm32f746 Discovery board 9209e9fa6ca9 ARM: dts: stm32: add led to stm32f746 Discovery board c572b069bf16 dt-bindings: dma: fsl,edma: Add i.MX94 support 421f8d787226 dt-bindings: dma: atmel: add microchip,sama7d65-dma 3630c655aafd dt-bindings: clock: mediatek,mt8188: Add VDO1_DPI1_HDMI clock 8f22583cbe0b arm64: dts: rockchip: Enable USB3 OTG on rk3588s Cool Pi 4B 175b6ab4addb docs: dt: submitting-patches: Document sending DTS patches 12f69f638472 arm64: dts: rockchip: Add UART clocks for RK3528 SoC 60741472b42e arm64: dts: rockchip: Add clock generators for RK3528 SoC 9d809a089686 Merge branch 'v6.15-shared/clkids' into v6.15-armsoc/dts64 4b92d7bf7d17 Merge branch 'v6.15-shared/clkids' into v6.15-clk/next 8768d063e732 dt-bindings: clock: Document clock and reset unit of RK3528 eb4fa305444d powerpc/microwatt: Add SMP support eb2feccfe7cb powerpc/microwatt: Device-tree updates b01ec0c00687 arm64: dts: apple: Add touchbar digitizer nodes 99a9210485d1 ARM: dts: stm32: Add Priva E-Measuringbox devicetree db39291d4cd4 ARM: dts: stm32: Add thermal support for STM32MP131 736b25b842a6 dt-bindings: arm: stm32: Add Priva E-Measuringbox board ac84513b3de1 dt-bindings: vendor-prefixes: Add prefix for Priva 153d1dded8e2 ASoC: dt-bindings: xlnx,spdif: Convert to json-schema 1dfc9272871a ASoC: dt-bindings: xlnx,audio-formatter: Convert to json-schema c05b804fd27e ASoC: dt-bindings: xlnx,i2s: Convert to json-schema e6b5549e2ea1 dt-bindings: coresight: qcom,coresight-tpdm: Fix too many 'reg' 81c7d959642a dt-bindings: coresight: qcom,coresight-tpda: Fix too many 'reg' d788495c297e dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E SoC ef078fa51469 dt-bindings: gpio: nxp,pcf8575: add reset GPIO e60b526a254b dt-bindings: display: qcom,sm8650-mdss: explicitly document mdp0-mem and cpu-cfg interconnect paths 5f6c7f3a882b dt-bindings: display: qcom,sm8550-mdss: explicitly document mdp0-mem and cpu-cfg interconnect paths 564ffb04cbff dt-bindings: display/msm/dsi-phy: Add header with exposed clock IDs dfe70ec7cf52 riscv: sophgo: dts: Add msi controller for SG2042 05d993f3a6ec dt-bindings: interrupt-controller: Add Sophgo SG2042 MSI a3b737ca15b2 Merge tag 'v6.14-rc4' into next f3b5bc2ab93f dt-bindings: display/lvds-codec: add ti,sn65lvds822 b20b0aace0f0 dt-bindings: input: matrix_keypad: add settle time after enabling all columns c6644ddbabe0 dt-bindings: input: matrix_keypad: convert to YAML 0204ceb1dac8 Enable DMIC for Genio 700/510 EVK aaa0adb4e4ba dt-bindings: input: Correct indentation and style in DTS example 1bd35f025a98 ASoC: dt-bindings: fsl: Reference common DAI 9d01b52dd742 ASoC: dt-bindings: mediatek,mt8188-mt6359: Add DMIC backend to dai-link 4b7def7c217f Fix RK3588 power domain problems 02d8831bddbd ASoC: dt-bindings: fsl,imx-asrc: Reference common DAI properties 2756dbc5dccb ASoC: dt-bindings: fsl,easrc: Reference common DAI properties be1e7ad12db3 Merge drm/drm-next into drm-misc-next 9876c6970616 dt-bindings: display: simple: Add BOE AV123Z7M-N17 panel 740d6f024cb4 dt-bindings: display: simple: add BOE AV101HDT-A10 panel 695f9094dd3e arm64: dts: mediatek: mt8188: Add base display controller graph d953922a6352 arm64: dts: mediatek: mt8390-genio-700: Add USB, TypeC Controller, MUX 4a972b5813a9 arm64: dts: mediatek: mt8188: Add MTU3 nodes and correctly describe USB c926d7135987 dt-bindings: usb: mediatek,mtk-xhci: Add port for SuperSpeed EP 3479b8607126 arm64: dts: mediatek: mt8395-genio-1200-evk: add support for TCPC port 1ea007fec939 dt-bindings: usb: mtu3: Add ports property 81bb891f02a1 arm64: dts: mediatek: mt8390-genio-common: Fix duplicated regulator name c2ee67f8f91c arm64: dts: mediatek: mt8183: Switch to Elan touchscreen driver 1480b2b9c163 Merge tag 'v6.14-rc4' into drm-next 19566af01522 arm64: dts: imx8mm-phycore-som: Add overlay to disable SPI NOR flash 4d957d8455fd arm64: dts: imx8mm-phycore-som: Add no-eth phy overlay e38b34b397ca arm64: dts: imx8mm-phycore-som: Add overlay for rproc 1d49d21dd81e arm64: dts: imx8mm-phyboard-polis: Add overlay for PEB-EVAL-01 3e8bdd2e0853 arm64: dts: imx8mm-phyboard-polis: Add support for PEB-AV-10 ea91b13eb856 arm64: dts: imx8mm-phyboard-polis: Assign missing regulator for bluetooth 884d4632d049 arm64: dts: imx8mm: move bulk of rtc properties to carrierboards 3bfc2236c593 arm64: dts: imx8mm-phygate-tauri-l: Set RTC as wakeup-source 1ca2b9c5de6b arm64: dts: imx8mm-phyboard-polis: Set RTC as wakeup-source 2a508a6ff135 arm64: dts: imx8mm-phyboard-polis: add RTC description b9ef6209b80f arm64: dts: imx8mm-phycore-som: add descriptions to nodes fa73714ac0c3 arm64: dts: imx8mm-phycore-som: Assign regulator for dsi to lvds bridge b37946788b2f arm64: dts: imx8mm-phycore-som: Remove magic-packet property 8016d32846f7 arm64: dts: imx8mm-phycore-som: Fix bluetooth wakeup source 9d8e0c3c4f7c arm64: dts: imx8mm-phycore-som: Keep LDO3 on in suspend b69b4e83993e arm64: dts: freescale: imx8mm-verdin: Remove LVDS panel and backlight 47beab578f6c arm64: dts: colibri-imx8x: Add missing gpio-line-names 20c64688c512 arm64: dts: s32g: add the eDMA nodes a17008eb460a arm64: dts: imx95: add PCIe's msi-map and iommu-map property 13bbffb4e884 arm64: dts: imx8q: add PCIe EP overlay file for i.MX8QXP mek board 55a2bc97a378 arm64: dts: imx8q: add PCIe EP for i.MX8QM and i.MX8QXP 5e82dd84d613 arm64: dts: imx8-ss-hsio: fix indentation in pcie node 6114dc137559 arm64: dts: freescale: tqma8mqnl: Add vcc-supply for spi-nor aa74db634145 arm64: dts: freescale: tqma8mqml: Add vcc-supply for spi-nor 8ac725ad672e arm64: dts: freescale: tqma8mq: Add vcc-supply for spi-nor 0b92969081bc arm64: dts: freescale: tqma8mpql: Add vcc-supply for spi-nor e82710a7796c arm64: dts: imx8-apalis: add clock configuration for 44.1 kHz hdmi audio 05db5bdaa953 arm64: dts: s32g399a-rdb3: Add INA231 sensor entry over I2C4 50df896ee8a8 arm64: dts: s32g: add common 'S32G-EVB' and 'S32G-RDB' board support e01e9b9dd62f arm64: dts: s32g: add I2C[0..2] support for s32g2 and s32g3 8be8d6f5fd39 arm64: dts: imx8qxp-mek: Complete WM8960 power supplies 1f7da937625a arm64: dts: imx8qm-mek: Complete WM8960 power supplies 6cb4cf4a8959 arm64: dts: imx8dxl-evk: Complete WM8960 power supplies a823b8504cfc arm64: dts: imx8mp-evk: Complete WM8960 power supplies f0fb71d2bfd2 arm64: dts: tqma9352-mba93xx[cl]a: swap ethernet aliases e6c58c4e34f5 arm64: dts: mba93xxca: Do not assert power-down pins 34a0e3de0c9d arm64: dts: freescale: imx93-tqma9352-mba93xxca: sort pinctrl nodes b41df0cb89cc arm64: dts: mba8xx: Add PCIe support d0a618f195f1 arm64: dts: tqma8xx: Remove GPU TODO 43419b7de367 arm64: dts: tqma8xx: enable jpeg encode and decode 8eaabcf5b237 arm64: dts: tqma8xx: Add vcc-supply for spi-nor a1706580b459 arm64: dts: imx8-ss-hsio: Wire up DMA IRQ for PCIe abcd89649f74 arm64: dts: imx8mn-bsh-smm-s2pro: Remove invalid audio codec clock 73b9c2a4d2cf arm64: dts: imx8mp-skov: increase I2C clock frequency for RTC 15dad674cdf5 arm64: dts: imx8mp-skov: fix phy-mode 35f9d08e683e arm64: dts: imx8mp-skov: describe mains fail detection 918eb1e7f304 arm64: dts: imx8mp-skov: configure uart1 for RS485 b1c4121e92da arm64: dts: imx8mp-skov: describe LVDS display pipeline 4f3d28e9954c arm64: dts: imx8mp-skov: describe HDMI display pipeline 74ff20266638 arm64: dts: imx8mp-skov: use I2C5 for DDC 5ee605182ffa arm64: dts: imx8mp-skov: operate CPU at 850 mV by default b9feeafd2708 arm64: dts: imx8mp-skov: correct PMIC board limits 6a3290b43d38 arm64: dts: imx8mp-kontron: Add support for reading SD_VSEL signal afb10648ca50 arm64: dts: imx93-kontron: Fix SD card IO voltage control 7822c3bd0f88 arm64: dts: imx8mm-kontron: Add support for reading SD_VSEL signal b90dec14cbfd ARM: dts: imx7d-sdb: Complete WM8960 power supplies 96289b986803 ARM: dts: imx6ul-14x14-evk: Complete WM8960 power supplies baa99fba4fbd scsi: arm64: dts: rockchip: Add UFS support for RK3576 SoC e1e953869373 scsi: ufs: dt-bindings: Document Rockchip UFS host controller af1e5d055507 dt-bindings: PCI: brcmstb: Update bindings for PCIe on BCM2712 88b7337af159 dt-bindings: interrupt-controller: Add BCM2712 MSI-X bindings e08f82eefaa7 dt-bindings: PCI: qcom-ep: Add SAR2130P compatible 4fd2560c686b dt-bindings: PCI: qcom-ep: Consolidate DMA vs non-DMA cases 652e3a3e15ee dt-bindings: PCI: qcom-ep: Enable DMA for SM8450 ffe279433d99 dt-bindings: PCI: qcom-ep: Describe optional IOMMU cb5305df80d2 dt-bindings: PCI: qcom-ep: Describe optional dma-coherent property 9585b1fcf51a ASoC: dt-bindings: imx-card: Add playback-only and capture-only property ed671a626791 dt-bindings: atmel-sysreg: Add SAMA7D65 Chip ID 6096197138a9 ARM: dts: microchip: sama7d65: Enable DMAs e76971437b8a arm64: dts: ti: k3-j722s-evm: Fix USB2.0_MUX_SEL to select Type-C ad4c5c253cfc ARM: dts: microchip: sama7d65: Add DMAs to sama7d65 SoC 21d60212633f ARM: dts: microchip: sama7d65: Add chipID for sama7d65 0ce77a32a2e4 arm64: dts: ti: k3-j784s4-evm-quad-port-eth-exp1: Remove duplicate hogs b2c185c86ce6 arm64: dts: ti: k3-am62a-mcu: enable mcu domain pinmux 34a41a24c946 Merge tag 'v6.14-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into HEAD 1a8fe57c561b arm64: dts: exynosautov920: add ufs phy for ExynosAutov920 SoC 53d1e146b05c ARM: dts: imx28-sps1: Fix GPIO LEDs description 10884a5224f4 ARM: dts: vf610-bk4: Use the more specific "lwn,bk4-spi" edd698009292 arm64: dts: rockchip: disable I2C2 bus by default on RK3588 Tiger 9be02103e21d arm64: dts: rockchip: enable I2C3 in Haikou carrierboard, not Ringneck DTSI 5743a9dda2c4 arm64: dts: rockchip: enable Ethernet in Haikou carrierboard, not Puma DTSI 2420a6d5e78c arm64: dts: rockchip: add EEPROM found on RK3399 Puma Haikou 529f82cf3ce9 arm64: dts: rockchip: enable I2S0 in Haikou carrierboard, not Puma DTSI 28cf8608f8d9 arm64: dts: rockchip: disable I2C6 on Puma DTSI a7b506f792bf arm64: dts: rockchip: move I2C6 from Haikou carrierboard to Puma DTSI 55a866e88323 arm64: dts: rockchip: move DDC bus from Haikou carrierboard to RK3399 Puma DTSI 27fd1de71a59 arm64: dts: rockchip: enable UART5 on RK3588 Tiger Haikou 6c3bb559bac0 arm64: dts: rockchip: Add Radxa ROCK 4D device tree 3544351bd438 dt-bindings: arm: rockchip: Add Radxa ROCK 4D board d67cf6de8aac arm64: dts: rockchip: add rk3576 otp node 231a534cd743 arm64: dts: rockchip: add overlay for RK3399 Puma Haikou Video Demo adapter abbc13f77a26 arm64: dts: rockchip: add overlay for PX30 Ringneck Haikou Video Demo adapter 046e0c70c93b arm64: dts: rockchip: add support for HAIKOU-LVDS-9904379 adapter for PX30 Ringneck 88fdb1f81232 dt-bindings: clock: sun50i-h616-ccu: Add LCD TCON clk and reset 4bb141531379 arm64: dts: allwinner: a100: Add CPU Operating Performance Points table 9fa5a7a0ef3c arm64: dts: allwinner: rg35xx: Add no-thermistor property for battery 31b4873bc1a6 arm64: dts: allwinner: h700: Add USB Host for RG35XX-H a8a5f54af77e arm64: dts: allwinner: h700: Add LED1 for Anbernic RG35XX d2ec9636e0dc arm64: dts: allwinner: h700: Set cpusldo to always-on for RG35XX 0e8ebe2be1eb dt-bindings: iio: Add adis16550 bindings 6ad196cd05d5 ARM: dts: mba6ul: change sound card model name 8ae441d65592 ARM: dts: imx7-mba7: change sound card model name 69323e39dc4e ARM: dts: imx6qdl-mba6: change sound card model name 6653d0117e05 dt-bindings: crypto: qcom-qce: Document the X1E80100 crypto engine 2c0efa8b0af1 dt-bindings: rng: add binding for Rockchip RK3588 RNG 23feff06013d dt-bindings: reset: Add SCMI reset IDs for RK3588 5b54b653b964 dt-bindings: gpu: mali-bifrost: Add Allwinner H616 compatible cd5fe0987644 dt-bindings: trivial-devices: Add ti,tps53681 2be45ede3cbe dt-bindings: net: Add Realtek MDIO controller afae7a251c1c dt-bindings: net: Add switch ports and interrupts to RTL9300 91d08b436193 dt-bindings: net: Move realtek,rtl9301-switch to net aaf093926eff dt-bindings: gpu: mali-bifrost: Add compatible for RZ/V2H(P) SoC 2819855d187d mips: dts: ralink: mt7620a: update system controller node and its consumers a2166e814c84 mips: dts: ralink: rt3883: update system controller node and its consumers 339e08846279 mips: dts: ralink: rt3050: update system controller node and its consumers d3abcf7cf3ae mips: dts: ralink: rt2880: update system controller node and its consumers 84e9b0c2fff8 dt-bindings: clock: add clock definitions for Ralink SoCs c28b259be385 dt-bindings: arm: coresight-tmc: Add "memory-region" property f1546685ce0f ARM: dts: renesas: r9a06g032: Fix UART dma channel order 6a6883b926ad arm64: dts: renesas: rzg2: Add boot phase tags 9abb2281477d arm64: dts: renesas: rcar: Add boot phase tags 7795d76bbbc2 ARM: dts: renesas: rcar-gen2: Add boot phase tags 9e0d9f1c47ea arm64: dts: renesas: white-hawk-csi-dsi: Use names for CSI-2 data line orders dc4f388ab13e arm64: dts: renesas: ulcb/kf: Use TDM Split Mode for capture 7dbc206c43da arm64: dts: renesas: Add initial support for MYIR Remi Pi ee00ebca3993 arm64: dts: renesas: r9a08g045: Add OPP table 61c8b03d8ef2 arm64: dts: renesas: r9a09g057: Enable SYS node 0815ca2096bf arm64: dts: renesas: r9a09g047: Add SYS node c36b3a2f01df arm64: dts: renesas: r9a08g045: Enable SYS node e6d40d0d2cfb arm64: dts: renesas: r8a779f0: Disable rswitch ports by default 44cb5b4c5426 arm64: dts: renesas: r9a08g045s33-smarc-pmod: Add overlay for SCIF1 703f038f08d8 arm64: dts: renesas: rzg3s-smarc: Enable SCIF3 6706d23f287c arm64: dts: renesas: rzg3s-smarc-switches: Add a header to describe different switches 90d900e27288 arm64: dts: renesas: r8a779g0: Restore sort order 78dba0214fc6 arm64: dts: renesas: s4sk: Fix ethernet0 alias for rswitch 65e95070b6ba arm64: dts: renesas: spider-ethernet: Add ethernetN aliases for rswitch caed2eab1bd4 arm64: dts: renesas: s4sk: Access rswitch ports via phandles 1cacb8200b69 arm64: dts: renesas: spider-ethernet: Access rswitch ports via phandles a7c45e21fd00 arm64: dts: renesas: r8a779f0: Add labels for rswitch ports d4ed59cf46f5 arm64: dts: renesas: Add initial device tree for Yuridenki-Shokai Kakip board e359d28948ce arm64: dts: renesas: eagle-function-expansion: Align GPIO hog name with bindings 3d56ae096af8 arm64: dts: renesas: r8a779h0: Add VSPX instance ae94b3852fbe arm64: dts: renesas: r8a779h0: Add FCPVX instance ba28a5391cc6 arm64: dts: renesas: rzg3e-smarc-som: Enable watchdog bb86f1ab211a arm64: dts: renesas: r9a09g047: Add WDT1-WDT3 nodes bdfecb224c52 arm64: dts: renesas: gray-hawk-single: Restore sort order 149c2679df26 arm64: dts: renesas: r8a779a0: Add VSPX instances afdd241afcbc arm64: dts: renesas: r8a779a0: Add FCPVX instances 6c91cfa7eda2 arm64: dts: renesas: gray-hawk-single: Describe AVB1 and AVB2 a6305fea1136 arm64: dts: renesas: r8a779h0: Remove #address- and #size-cells from AVB[0-2] e384ea6d2c06 arm64: dts: renesas: r8a77990: Re-add voltages to OPP table b94a86f224ed arm64: dts: renesas: r8a774c0: Re-add voltages to OPP table 73035ca45197 mips: dts: realtek: Add restart to Cisco SG220-26P da5e72c52240 mips: dts: realtek: Add RTL838x SoC peripherals e1258dbdceed mips: dts: realtek: Replace uart clock property 05fddbb7ebd9 mips: dts: realtek: Correct uart interrupt-parent a457e7128f11 mips: dts: realtek: Add SoC IRQ node for RTL838x 57bde8194b75 mips: dts: realtek: Fold rtl83xx into rtl838x 64c98fba1502 mips: dts: realtek: Add address to SoC node name 9f6b4016f45a mips: dts: realtek: Clean up CPU clocks a015cd4a0443 mips: dts: realtek: Decouple RTL930x base DTSI e452c3447525 MIPS: mobileye: dts: eyeq6h: Enable cluster support 4913d71e6942 dt-bindings: mips: mips-cm: Add a new compatible string for EyeQ6 0b2d5fd80af4 dt-bindings: mips: Document mti,mips-cm a429699ec2e2 dt-bindings: ata: Convert fsl,pq-sata to YAML ac47e5894fc3 dt-bindings: hwinfo: samsung,exynos-chipid: add exynos7870-chipid compatible 93b63c5675fe media: dt-bindings: adv7180: Document the 'interrupts' property a1c70718bc0f media: dt-bindings: aspeed,video-engine: Convert to json schema 4da9a2e40dd4 dt-bindings: media: st,stmipid02: correct lane-polarities maxItems ae847cba005e mips: dts: ingenic: Switch to simple-audio-card,hp-det-gpios f72623fbd64c arm64: dts: rockchip: rk356x: Move PCIe MSI to use GIC ITS instead of MBI 573d01eb7714 arm64: dts: rockchip: rk356x: Add MSI controller node a62671cb3851 dt-bindings: xilinx: Deprecate header with firmware constants d48d272341e2 arm64: zynqmp: Use DT header for firmware constants c2265415c9c1 dt-bindings: power: supply: axp20x-battery: Add x-powers,no-thermistor 1c2d49b11f41 dt-bindings: vendor-prefixes: Document the 'pciclass' prefix 8fe54d8c1e6a dt-bindings: trivial-devices: Add ti,tps546b24 0c947a496323 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net ea5adb18bcaf dt-bindings: mfd: Add maxim,max77705 f5071bfa82eb dt-bindings: power: supply: add maxim,max77705 charger 26b6ca520742 dt-bindings: leds: qcom-lpg: Document PM8937 PWM compatible 115f06126ec6 dt-bindings: leds: backlight: apple,dwi-bl: Add Apple DWI backlight ec6ae18eb982 spi: dt-bindings: Convert Freescale SPI bindings to YAML b24a6dbfc7c3 Merge tag 'linux-can-next-for-6.15-20250219' of git://git.kernel.org/pub/scm/linux/kernel/git/mkl/linux-can-next a17a9095c7fa ARM: dts: nxp: vf: Align GPIO hog name with bindings 90cfeb11e6bd dt-bindings: net: dsa: b53: add BCM53101 support 6df8500248bb dt-bindings: power: reset: xilinx: Make "interrupts" property optional 84dd8dd4c6b0 dt-bindings: power: reset: atmel,sama5d2-shdwc: Add microchip,sama7d65-shdwc 24ab1372bbf2 dt-bindings: input: touchscreen: Add Z2 controller 2dbbd7ff619b ASoC: dt-bindings: atmel-at91sam9g20ek: convert to json-schema 2e73e48c20e4 dt-bindings: usb: samsung,exynos-dwc3 Add exynos990 compatible c554695fa890 USB: docs: Fix typo in aspeed-lpc.yaml 6f18dd0694b2 dt-bindings: usb: usb-device: Replace free-form 'reg' with constraints f57d58abdd1f dt-bindings: usb: microchip,usb2514: add support for USB2512/USB2513 22c582f7410c dt-bindings: usb: microchip,usb2514: add support for vdda bbd705c2b5f9 dt-binding: can: mcp251xfd: remove duplicate word 5ccbb5ed0811 dt-bindings: can: fsl,flexcan: add S32G2/S32G3 SoC support b3155d3e94f8 dt-bindings: pinctrl: samsung: add exynos2200 compatible b6ea4790ddc5 dt-bindings: pinctrl: samsung: add exynos2200-wakeup-eint compatible c7b5bd42aef7 dt-bindings: hwinfo: samsung,exynos-chipid: add exynos2200 compatible 85d161c64b09 dt-bindings: soc: samsung: exynos-pmu: add exynos2200 compatible 467349660659 dt-bindings: soc: samsung: exynos-sysreg: add sysreg compatibles for exynos2200 f3a49191d711 arm64: dts: apple: Add SPI NOR nvram partition to all devices 32fb252ce1f3 arm64: dts: apple: t600x: Add spi controller nodes 7b672e8683fb arm64: dts: apple: t8112: Add spi controller nodes 11383e8e5d7f arm64: dts: apple: t8103: Add spi controller nodes df2301056fc8 arm64: dts: apple: t8103: Fix spi4 power domain sort order 588bf84fbfc5 riscv: dts: starfive: jh7110-pine64-star64: enable USB 3.0 port 2260adebc79d riscv: dts: starfive: jh7110: pciephy0 USB 3.0 configuration registers d46cea021cfc riscv: dts: starfive: fml13v01: enable pcie1 aca9a5c6177d riscv: dts: starfive: remove non-existent dac from jh7110 714ea90c3680 arm64: dts: apple: t7000: Add missing CPU p-state 7 for J96 and J97 b27dd2587832 ARM: dts: imx5: Fix the CCM interrupts description 028660f03192 ARM: dts: vfxxx: Fix the CAAM job ring node names 18d135dfe74a arm64: dts: mediatek: mt6359: fix dtbs_check error for audio-codec 1341f30d43e8 Merge drm/drm-next into drm-misc-next 4e43cbdb48d1 ARM: dts: imx53-ppd: Fix touchscreen reset-gpios 4ba7c5cec4fc ARM: dts: imx7s: Move csi-mux to below root 1d0f023c6ebe riscv: sophgo: dts: add cooling maps for Milk-V Pioneer 67fd41fa38f7 riscv: sophgo: dts: add pwm-fan for Milk-V Pioneer af97acf23d50 dt-bindings: net: ethernet-phy: add property tx-amplitude-100base-tx-percent 3c2fcb7fd8f4 arm64: versal-net: Add description for b2197-00 revA board 51a5e958e52c dt-bindings: soc: Add new VN-X board description based on Versal NET b3d3914cdb96 ASoC: tas2764: Random patches from the Asahi Linux 17494bd5ec3e riscv: dts: spacemit: Add Milk-V Jupiter board device tree 7154a6c8889d dt-bindings: riscv: spacemit: Add Milk-V Jupiter board compatible b42bf3977a7b Merge commit '71f0dd5a3293d75d26d405ffbaedfdda4836af32' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next into for-6.15/io_uring-rx-zc 7faa56193b95 ASoC: dt-bindings: wlf,wm8960: add 'port' property eaa850920663 arm64: dts: imx95-19x19-evk: add typec nodes and enable usb3 node d145eb78bb29 arm64: dts: imx95: add usb3 related nodes 9e8c9998017c ARM: dts: mxs: Add descriptions for imx287 based btt3-[012] devices 327f79156245 dt-bindings: arm: Document the btt3 i.MX28 based board 77f03f406681 arm64: dts: imx8qm-mek: add audio-codec cs42888 and related nodes f55a6cd37037 arm64: dts: imx8mq-librem5: remove undocument property 'extcon' for usb-pd@3f cfac8cba2afb ARM: dts: microchip: sama7d65_curiosity: Add power monitor support 713b56b62a21 arm64: dts: exynosautov920: add CPU cache information 95afa38c66b5 ARM: dts: microchip: sama7d65: Add flexcom 10 node 11815f2bda26 ARM: dts: at91: usb_a9g20_lpw: use proper mmc node name f2f5d8164a85 ARM: dts: at91: calao_usb: fix button nodes 4320615849bc ARM: dts: at91: use correct vendor name for Calao boards fc606a98fb4c ARM: dts: at91: calao_usb: remove heartbeat for User LEDs adf5d3205c13 ARM: dts: at91: calao_usb: fix wrong polarity for LED 02b371776f9f Merge 6.14-rc3 into usb-next c79ef81e8b3f Merge 6.14-rc3 into tty-next 5d5087e055bc dt-bindings: iio: adc: Introduce ADS7138 81b74faf1bbd dt-bindings: iio: adc: add ADI ad4030, ad4630 and ad4632 4800c4aaad00 arm64: dts: rockchip: Add rng node to RK3588 fb5624b3aff6 dt-bindings: iio: adc: add ad4851 29c6d2f72796 dt-bindings: iio: adc: add ad485x axi variant 2aa06934b04b arm64: dts: exynos: gs101: add ACPM protocol node 9a410d40fffc arm64: dts: exynos: gs101: add AP to APM mailbox node f67a8cbbc893 arm64: dts: exynos: gs101: add SRAM node fd1eea66f8ff dt-bindings: firmware: add google,gs101-acpm-ipc 0c84b9a92cd8 dt-bindings: media: clarify stm32 csi & simplify example cb82b9a812fb arm64: dts: exynos: gs101: add reboot-mode support (SYSIP_DAT0) cafb5b1128f9 arm64: dts: exynos: gs101: align poweroff writes with downstream b7103d0c00e2 arm64: dts: exynos: gs101: drop explicit regmap from reboot nodes 388e7272d092 arm64: dts: rockchip: Add devicetree for the ROC-RK3576-PC 89026942ddd0 dt-bindings: arm: rockchip: Add Firefly ROC-RK3576-PC binding 11054a56eb5e arm64: dts: rockchip: minimal support for Pre-ICT tester adapter for RK3588 Jaguar fa30dcce2020 dt-bindings: soc: qcom: qcom,pmic-glink: Document SM8750 compatible df945fcbeec5 Merge branch '20250109-qcs8300-mm-patches-new-v4-0-63e8ac268b02@quicinc.com' into clk-for-6.15 7c12a4b2f62e dt-bindings: clock: qcom: Add QCS8300 video clock controller 1f3bb677cac5 dt-bindings: clock: qcom: Add CAMCC clocks for QCS8300 d11f22ad6f0e dt-bindings: clock: qcom: Add GPU clocks for QCS8300 fd809190482c Merge branch '20250203063427.358327-2-alexeymin@postmarketos.org' into clk-for-6.15 5980968a3736 dt-bindings: clock: gcc-sdm660: Add missing SDCC resets 024211d099c3 dt-bindings: clock: gcc-sdm660: Add missing SDCC resets b8807b3e1cb2 dt-bindings: clock: qcom,rpmcc: Add SDM429 5bce17b9c9ff pmdomain: Merge branch dt into next 82ed9883247a dt-bindings: power: add V853 ppu bindings 68169a0560d8 dt-bindings: serial: Add bindings for nvidia,tegra264-utc 668773b787ac dt-bindings: serial: Allow fsl,ns16550 with broken FIFOs 9648d88104e5 dt-bindings: usb: Add Parade PS8830 Type-C retimer bindings 0c7c8b465ec2 dt-bindings: usb: dwc3: Add a property to reserve endpoints e939f6d880e2 Merge tag 'drm-misc-next-2025-02-12' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next 03f675fb2209 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net a1e21c6557d7 dt-bindings: imx: fsl,aips-bus: Ensure all properties are defined 9367c9acdab1 dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings 4e5d9b054e9d dt-bindings: phy: samsung,usb3-drd-phy: gs101: require Type-C properties 7aa26eec3f52 dt-bindings: phy: samsung,usb3-drd-phy: add blank lines between DT properties 8fc192d8c786 dt-bindings: display: bridge: sn65dsi83: Add interrupt 27bd4bb30fdc dt-bindings: power: rpmpd: Fix comment for SM6375 2a0abedef196 arm64: dts: mediatek: mt8188: Add tertiary eMMC/SD/SDIO controller 58186cbc681f arm64: dts: mediatek: mt8188: Add VDO0's DSC and MERGE block nodes 9385b92b564a arm64: dts: mediatek: mt8188: Assign apll1 clock as parent to avoid hang 04c7795892af ARM: dts: ixp4xx: Add Netgear WG302 v1 GPIOs e672efae7f1f ARM: dts: ixp4xx: Fix up PCI on WG302 dfe984c10836 ARM: dts: Properly assign NPE to ethA 47c38f7af771 loongarch: dts: remove non-existent DAC from 2k1000-ref aecbe697ed9a ARM: dts: cirrus: ep7211: Align GPIO hog name with bindings a950ae069eeb arm64: dts: exynos8895: Rename PMU nodes to fixup sorting 6aebfac1f2e6 arm64: dts: mediatek: add device-tree for Genio 510 EVK board 0a53b5690395 arm64: dts: mediatek: mt8390-genio-700-evk: Move common parts to dtsi cd85db03d191 arm64: dts: marvell: Add missing board compatible for IEI-Puzzle-M801 37f65442ac9b arm64: dts: marvell: Fix missing/incorrect "marvell,armada3710" compatible 3f3f0055504c arm64: dts: marvell: Drop incomplete root compatible/model properties 900bc3ca59b4 dt-bindings: marvell: armada-7k-8k: Add missing 7040 and 8040 board compatibles fdd9abb2b187 dt-bindings: marvell: armada-7k-8k: Move Armada 8KPlus to schema 42c1447c23e2 dt-bindings: marvell: armada-37xx: Add glinet,gl-mv1000 compatible 94879a4116ea arm64: dts: rockchip: Enable HDMI1 on Orange Pi 5 Max 2a8407332ac4 dt-bindings: pwm: Add support for PWM nexus node 481e9de30692 riscv: dts: starfive: Unify regulator naming scheme a93373b7988b dt-bindings: media: camss: Add qcom,sdm670-camss 909002479174 arm64: dts: rockchip: linewrap gmac assigned-clocks on Quartz64 Model A/B files a bit 8457c997e974 arm64: dts: rockchip: remove rk3588 optee node 47e426fb98b2 dt-bindings: iio: dac: adi-axi-adc: add ad7606 variant 5116c83b9333 dt-bindings: iio: adc: adi,ad4695: add SPI offload properties 3ca14f0620da dt-bindings: leds: Convert leds-tlc591xx.txt to yaml format e96e93245d76 dt-bindings: net: rfkill-gpio: enable booting in blocked state 1bf0b9eea5fd arm64: dts: rockchip: Enable HDMI1 out for Edgeble-6TOPS Modules b0d56064489f arm64: dts: rockchip: Enable HDMI1 on rock-5b 873d0d388c38 arm64: dts: rockchip: Add HDMI1 node on RK3588 8716e9c85925 arm64: dts: rockchip: Add PHY node for HDMI1 TX port on RK3588 ad3eee0eda32 arm64: dts: rockchip: Enable SPDIF output on H96 Max V58 e51f476b2549 arm64: dts: rockchip: Add SPDIF nodes to RK3588(s) device trees 71a14fc267ad dt-bindings: net: smsc,lan9115: Ensure all properties are defined 5de2b7dc7768 dt-bindings: memory-controllers: samsung,exynos4210-srom: Split out child node properties cd66a94e6d99 dt-bindings: memory-controllers: qcom,ebi2: Split out child node properties 0c6820b22794 dt-bindings: memory-controllers: Move qcom,ebi2 from bindings/bus/ 94d614fdbd9a Merge tag 'spi-offload' into togreg 92fae782ee1d Documentation: Remove repeated word in docs cf9f02118fe1 dt-bindings: phy: qcom,qmp-pcie: Drop reset number constraints 37229c163579 dt-bindings: phy: qcom,qmp-pcie: Add X1P42100 PCIe Gen4x4 PHY 913df9ddc676 dt-bindings: phy: Add rk3576 hdptx phy 33ebb61a9413 dt-bindings: display: panel: Add KD110N11-51IE and 2082109QFH040022-50E d7efe5059077 dt-bindings: ASoC: rockchip: Add compatible for RK3588 SPDIF 9dd06b8dd8ac dt-bindings: dma: convert atmel-dma.txt to YAML b25933f5b573 dt-bindings: vendor-prefixes: Update rockchip company name a8e1f2c3f715 arm64: dts: rockchip: add dts for Ariaboard Photonicat RK3568 0b22b27cde74 dt-bindings: arm: rockchip: Add Ariaboard Photonicat RK3568 7ce8f717740a dt-bindings: vendor-prefixes: Add prefix for Ariaboard 17038a66bb8b arm64: dts: rockchip: switch Rock 5C to PMIC-based TSHUT reset a7fde791ce29 arm64: dts: rockchip: add 'chassis-type' property on PineNote acd8eab1d823 dt-bindings: clock: rk3188-common: add PCLK_CIF0/PCLK_CIF1 7d004cf97e38 dt-bindings: soc: renesas: Document MYIR Remi Pi board d798bb42d18b arm64: dts: apple: t8015: Add cpufreq nodes 142ff02c87ca arm64: dts: apple: t8012: Add cpufreq nodes 423ad63e9ff5 arm64: dts: apple: t8011: Add cpufreq nodes 6fd3a983e7aa arm64: dts: apple: t8010: Add cpufreq nodes 2327e547433d arm64: dts: apple: s8001: Add cpufreq nodes a5f95a9c11ca arm64: dts: apple: Add cpufreq nodes for S8000/S8003 d48321d9c0a2 arm64: dts: apple: t7001: Add cpufreq nodes 5af5ae6d020a arm64: dts: apple: t7000: Add cpufreq nodes 62a511b2e51a arm64: dts: apple: s5l8960x: Add cpufreq nodes 66b42d66b597 arm64: dts: apple: t8015: Add PMGR nodes 0f7c9deb5489 arm64: dts: apple: t8012: Add PMGR nodes 0f9f2a165a57 arm64: dts: apple: t8011: Add PMGR nodes cc770ee797ee arm64: dts: apple: t8010: Add PMGR nodes ab8f4186a843 arm64: dts: apple: s8001: Add PMGR nodes b5e2aa91fa41 arm64: dts: apple: s800-0-3: Add PMGR nodes 262b4c2c6b63 arm64: dts: apple: t7001: Add PMGR node 4eccd0ed15e8 arm64: dts: apple: t7000: Add PMGR node 5cad2b1f1511 arm64: dts: apple: s5l8960x: Add PMGR node 3ae627f53660 dt-bindings: arm: apple: apple,pmgr-pwrstate: Add A7-A11, T2 compatibles cf1acfdcd1ab dt-bindings: arm: apple: apple,pmgr: Add A7-A11, T2 compatibles e6b8b4eb2893 arm64: dts: apple: Add T2 devices 3635f84149d5 dt-bindings: arm: apple: Add T2 devices ecb90807423a arm64: dts: apple: Split s8000/s8003 SoC DTS files 0332b153fa3e dt-bindings: crypto: Add Inside Secure SafeXcel EIP-93 crypto engine ad30fd49aa1e ARM: dts: sunxi: add support for NetCube Systems Kumquat 0463c05da755 ARM: dts: sunxi: add uart1_pe pinctrl for sun8i-v3s 64ab025e91c5 dt-bindings: arm: sunxi: Add NetCube Systems Kumquat board 135ecb1c0900 dt-bindings: vendor-prefixes: Add NetCube Systems Austria name ba07d9983cd2 dt-bindings: iio: adf4371: add refin mode 95eb7af6dfd3 dt-bindings: iio: light: Add APDS9160 binding 32ed0be023c0 dt-bindings: iio: magnetometer: add binding for Si7210 3d902b3b97b5 riscv: sophgo: dts: add pwm controller for SG2042 SoC c6a0c59c390f spi: dt-bindings: axi-spi-engine: add SPI offload properties 26ad965c5d62 dt-bindings: trigger-source: add generic PWM trigger source 69e102cfc84d dt-bindings: display: panel: Add compatible for CSOT PNA957QT1-1 a854ffec9ddf dt-bindings: vendor-prefixes: add csot 66fd41e84bce dt-bindings: mtd: arasan,nand-controller: Ensure all properties are defined e0661cab113c dt-bindings: media: Add video support for QCOM SM8550 SoC 1e83da324d74 Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net d30a4e7e782c Add static channel mapping between soundwire master f9d3323c1b73 ASoC: cpcap: Implement jack headset detection 926489106ec0 This is continued work on Samsung S9(SM-9600) 0332d1781ba7 dt-bindings: media: camss: Add qcom,sm8550-camss binding c6a4614b770b media: dt-bindings: update clocks for sc7280-camss 4c1200c39b8f Merge drm/drm-next into drm-misc-next 70de7a1b60f4 ASoC: dt-bindings: wcd937x-sdw: Add static channel mapping support 33c6fb10fda1 arm64: dts: mediatek: add support for MT8370 SoC 3d0e1130cf33 dt-bindings: arm: mediatek: add mt8370-evk board d2d62c5d0e90 arm64: dts: rockchip: Fix label name of hdptxphy for RK3588 6605f13b8e1b arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588 f962971332b4 arm64: dts: rockchip: Enable HDMI0 PHY clk provider on RK3588 1d392f374a7e dt-bindings: display: vop2: Add optional PLL clock properties 5ab646d63942 dt-bindings: display: rockchip: Fix label name of hdptxphy for RK3588 HDMI TX Controller c2cc31a23d6c Revert "dt-bindings: serial: 8250: Add Airoha compatibles" 41f6c94c3fb4 ARM: dts: omap4-panda-a4: Add missing model and compatible properties 464c5f08f7cf dt-bindings: omap: Add TI Pandaboard A4 variant 66677d9f9b16 ARM: dts: ti/omap: omap4-serial: fix interrupts syntax a6f47d7ebfcc ARM: dts: ti: omap: Align GPIO hog name with bindings ffdbb206b0a5 arm64: dts: exynos8895-dreamlte: enable support for the touchscreen 21356aba4c79 arm64: dts: exynos8895-dreamlte: enable support for microSD storage 4b146b3f86ce arm64: dts: exynos8895: add a node for mmc 6a0044cd3e17 arm64: dts: exynos8895: define all usi nodes 2d75cfaed428 arm64: dts: exynos8895: add syscon nodes for peric0/1 and fsys0/1 9649031bcf98 Merge branch 'for-v6.15/samsung-soc-dt-bindings' into next/dt64 5a27c5397796 arm64: dts: exynos990: Rename and sort PMU nodes fad948b46dc1 arm64: dts: exynos990: Add CMU_PERIS and MCT nodes f51ef9e1e5ee Merge branch 'for-v6.15/samsung-clk-dt-bindings' into next/dt64 a517cff67d7a dt-bindings: soc: samsung: usi: add USIv1 and samsung,exynos8895-usi 0f0ca5993559 arm64: dts: mediatek: add display support for mt8365-evk 08a19a12abe1 arm64: dts: mediatek: add display blocks support for the MT8365 SoC cbbc4673a9d2 arm64: dts: mediatek: mt8173: Fix some node names 5b7068d50a96 arm64: dts: mediatek: mt8173: Fix disp-pwm compatible string 3bc44bb385f8 arm64: dts: mediatek: mt8173-elm: Drop pmic's #address-cells and #size-cells e8d00ab25c72 arm64: dts: airoha: en7581: Add default partition table for EVB board d8075291fd7f arm64: dts: airoha: en7581: Add SNAND node 63cd70f67e52 arm64: dts: airoha: en7581: Add Clock Controller node 1e23fdb8aebc ASoC: dt-bindings: atmel,at91-ssc: Convert to YAML format f092663478cd dt-bindings: pwm: sophgo: add PWM controller for SG2042 1f3f3de0aec6 dt-bindings: eeprom: at24: Add compatible for Giantec GT24P128E 4fba896db2e6 dt-bindings: eeprom: at24: Add compatible for Puya P24C64F 6392d4e28d8d dt-bindings: gpio: ast2400-gpio: Add hogs parsing 138b4d48b94a dt-bindings: net: faraday,ftgmac100: Add phys mode b570187febfc riscv: dts: microchip: update pcie reg properties to new format 42dcb803b930 ASoC: dt-bindings: Add bindings for WCD934x DAIs 09c3b9df3660 dt-bindings: serial: pl011: Add optional power-domains property 4f0c7d1b5ac2 dt-bindings: serial: 8250: Add Airoha compatibles ee81474fbc7b dt-bindings: serial: Add a new compatible string for UMS9632 9b704b0c3665 dt-bindings: clock: exynos990: Add CMU_PERIS block a9c4ff6507a2 arm64: dts: exynos: gs101-raven: add new board file a7bb8998ddf1 arm64: dts: exynos: gs101-oriole: move common Pixel6 & 6Pro parts into a .dtsi da0ca70f88e6 arm64: dts: exynos: gs101-oriole: configure simple-framebuffer dac1e08cdece dt-bindings: arm: google: add gs101-raven 080186bec3c2 arm64: dts: exynos: gs101: disable pinctrl_gsacore node 7c74bfc98c0c ARM: zynq: Do not define address/size-cells for nand-controller ff5e3b12865d dt-bindings: iio: accel: mc3230: document mc3510c 4fc3fd99ee16 dt-bindings: iio: Correct indentation and style in DTS example 3af3fc397fdf dt-bindings: xilinx: Remove desciption for 16550 uart a4e34a5b5e49 dt-bindings: xilinx: Remove description for SystemACE 7f8cc3643d7a dt-bindings: xilinx: Remove uartlite from xilinx.txt 666456d4cf96 arm64: zynqmp: add clock-output-names property in clock nodes 8a33cbb41574 ARM: zynq: Remove ethernet0 alias from Microzed 8dfe6851b546 ARM: zynq: Add sdhci to alias node 9ddc09b7b0df ARM: zynq: Enable QSPIs on platforms 6d73675978fe ARM: zynq: Fix fpga region DT nodes name 6c76353caff0 ARM: zynq: Rename i2c?-gpio to i2c?-gpio-grp 15fafeb17cb9 ARM: zynq: Define rtc alias on zc702/zc706 831329e67d45 ARM: zynq: Point via nvmem0 alias to eeprom on zc702/zc706 a4f4075bb7d0 ARM: zynq: Define u-boot bootscrip addr via DT 7f8aedee7529 ARM: zynq: Wire smcc with nand/nor memories on zc770 platform 8bcb31d8083c ARM: zynq: Mark boot-phase-specific device nodes ef23211239f5 ARM: zynq: DT: List OCM memory for all platforms 85f3e03e1434 ARM: zynq: Remove deprecated device_type property 7e6f927d6b95 ARM: zynq: Replace 'io-standard' with 'power-source' property 83abe9885c89 dt-bindings: interrupt-controller: Add risc-v,aplic hart indexes c05988583566 ARM: dts: stm32: lxa-fairytux2: add Linux Automation GmbH FairyTux 2 f2edad670168 dt-bindings: arm: stm32: add compatible strings for Linux Automation GmbH LXA FairyTux 2 3b3bc35e81ac dt-bindings: soc: renesas: Add RZ/G3E variant SYS binding cb2e0436ada7 dt-bindings: soc: renesas: Document Yuridenki-Shokai Kakip board 6057199eb478 dt-bindings: vendor-prefixes: Add Yuridenki-Shokai Co. Ltd. 3c4392efd5f9 dt-bindings: soc: renesas: Document more Renesas RZ/V2H SoC variants c09fc0ef8abe arm64: dts: rockchip: Use "dma-noncoherent" in base RK3588 SoC dtsi ec750fb661af arm64: dts: rockchip: Describe why is HWRNG disabled in RK356x base dtsi 3aee8aaf8a6c arm64: dts: rockchip: Enable HDMI on armsom-sige7 1660f72aa147 arm64: dts: rockchip: Enable automatic fan control on Radxa Rock 5C 55073acc624c arm64: dts: rockchip: Add finer-grained PWM states for the fan on Rock 5C b112f324c2a9 arm64: dts: rockchip: Enable USB OTG for Radxa ROCK Pi E 41123c761619 arm64: dts: rockchip: add support for sound output over HDMI on RK3399 Puma Haikou edc802632427 ARM: dts: ti: davinci: Align GPIO hog name with bindings 8bdeb1cbd5b4 dt-bindings: hwmon: lm90: Add support for NCT7716, NCT7717 and NCT7718 5502124072e1 dt-bindings: hwmon: ltc2978: add support for ltm4673 eb140dbbba76 arm64: dts: imx8mp-skov-reva: Use hardware signal for SD card VSELECT 63a6c68df7cb dt-bindings: regulator: pca9450: Add properties for handling LDO5 cb0906024c41 dt-bindings: mfd: motorola-cpcap: Document audio-codec interrupts c0cfd3272eb3 dt-bindings: display: renesas,du: add top-level constraints dba95e8dd801 dt-bindings: display: renesas,du: narrow interrupts and resets per variants b1ac75c9a524 dt-bindings: display: rockchip: Add rk3576 hdmi controller git-subtree-dir: dts/upstream git-subtree-split: fe2d6c49bb4e11ab4de4d2f9bd9234d1407c4f65 --- Bindings/arm/apple.yaml | 41 + Bindings/arm/apple/apple,pmgr.yaml | 5 + Bindings/arm/arm,coresight-tmc.yaml | 26 + Bindings/arm/arm,morello.yaml | 35 + Bindings/arm/atmel-at91.yaml | 33 +- Bindings/arm/atmel-sysregs.txt | 1 + Bindings/arm/cpus.yaml | 1 + Bindings/arm/fsl.yaml | 27 +- Bindings/arm/google.yaml | 3 +- Bindings/arm/marvell/armada-37xx.yaml | 1 + Bindings/arm/marvell/armada-7k-8k.yaml | 25 + Bindings/arm/marvell/armada-8kp.txt | 15 - Bindings/arm/mediatek.yaml | 5 + Bindings/arm/pmu.yaml | 1 + Bindings/arm/qcom,coresight-ctcu.yaml | 84 ++ Bindings/arm/qcom,coresight-tpda.yaml | 3 +- Bindings/arm/qcom,coresight-tpdm.yaml | 3 +- Bindings/arm/rockchip.yaml | 25 +- Bindings/arm/stm32/st,stm32-syscon.yaml | 2 + Bindings/arm/stm32/stm32.yaml | 22 + Bindings/arm/sunxi.yaml | 5 + Bindings/arm/ti/omap.yaml | 7 + Bindings/ata/ceva,ahci-1v84.yaml | 5 +- Bindings/ata/fsl,pq-sata.yaml | 60 + Bindings/ata/fsl-sata.txt | 28 - Bindings/bus/qcom,ebi2.yaml | 239 ---- Bindings/clock/allwinner,sun55i-a523-ccu.yaml | 103 ++ Bindings/clock/atmel,at91rm9200-pmc.yaml | 4 + Bindings/clock/imx8m-clock.yaml | 8 + Bindings/clock/imx8mp-audiomix.yaml | 10 +- Bindings/clock/mediatek,mt8188-clock.yaml | 21 + Bindings/clock/mediatek,mtmips-sysc.yaml | 11 +- Bindings/clock/qcom,ipq9574-nsscc.yaml | 98 ++ Bindings/clock/qcom,rpmcc.yaml | 2 + Bindings/clock/qcom,sc7280-lpasscorecc.yaml | 5 +- Bindings/clock/qcom,sm8450-camcc.yaml | 1 - Bindings/clock/qcom,x1e80100-camcc.yaml | 9 +- Bindings/clock/rockchip,rk3528-cru.yaml | 64 + Bindings/clock/rockchip,rk3562-cru.yaml | 55 + Bindings/clock/samsung,exynos2200-cmu.yaml | 247 ++++ Bindings/clock/samsung,exynos7870-cmu.yaml | 227 ++++ Bindings/clock/samsung,exynos990-clock.yaml | 19 + Bindings/clock/ti,clkctrl.yaml | 65 + Bindings/clock/ti-clkctrl.txt | 63 - .../connector/gocontroll,moduline-module-slot.yaml | 88 ++ Bindings/cpufreq/cpufreq-qcom-hw.yaml | 35 +- Bindings/crypto/fsl,sec2.0.yaml | 144 ++ Bindings/crypto/fsl-sec2.txt | 65 - Bindings/crypto/inside-secure,safexcel-eip93.yaml | 67 + Bindings/crypto/inside-secure,safexcel.yaml | 2 + Bindings/crypto/qcom,prng.yaml | 1 + Bindings/crypto/qcom-qce.yaml | 1 + Bindings/display/apple,h7-display-pipe-mipi.yaml | 83 ++ Bindings/display/apple,h7-display-pipe.yaml | 88 ++ Bindings/display/bridge/lvds-codec.yaml | 1 + Bindings/display/bridge/nwl-dsi.yaml | 18 +- Bindings/display/bridge/ti,sn65dsi83.yaml | 3 + Bindings/display/mediatek/mediatek,dpi.yaml | 7 + Bindings/display/mediatek/mediatek,dsc.yaml | 3 + Bindings/display/msm/dsi-controller-main.yaml | 70 +- Bindings/display/msm/dsi-phy-common.yaml | 2 + Bindings/display/msm/gmu.yaml | 1 + Bindings/display/msm/qcom,sa8775p-mdss.yaml | 32 +- Bindings/display/msm/qcom,sm8550-mdss.yaml | 14 +- Bindings/display/msm/qcom,sm8650-mdss.yaml | 13 +- Bindings/display/panel/apple,summit.yaml | 58 + Bindings/display/panel/himax,hx83102.yaml | 6 + Bindings/display/panel/mitsubishi,aa104xd12.yaml | 6 +- .../panel/panel-simple-lvds-dual-ports.yaml | 2 + Bindings/display/panel/panel-simple.yaml | 2 + Bindings/display/panel/raydium,rm67200.yaml | 72 + Bindings/display/panel/visionox,rm692e5.yaml | 77 ++ Bindings/display/renesas,du.yaml | 36 +- .../rockchip/rockchip,rk3588-dw-hdmi-qp.yaml | 3 +- Bindings/display/rockchip/rockchip-vop2.yaml | 103 +- Bindings/display/tegra/nvidia,tegra114-mipi.yaml | 1 + Bindings/dma/atmel,at91sam9g45-dma.yaml | 68 + Bindings/dma/atmel,sama5d4-dma.yaml | 3 + Bindings/dma/atmel-dma.txt | 42 - Bindings/dma/fsl,edma.yaml | 8 + Bindings/dma/fsl,elo-dma.yaml | 137 ++ Bindings/dma/fsl,elo3-dma.yaml | 125 ++ Bindings/dma/fsl,eloplus-dma.yaml | 132 ++ Bindings/dma/fsl,mxs-dma.yaml | 6 + Bindings/dma/snps,dw-axi-dmac.yaml | 2 + Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml | 3 +- Bindings/dsp/fsl,dsp.yaml | 24 +- Bindings/dts-coding-style.rst | 8 +- Bindings/edac/altr,socfpga-ecc-manager.yaml | 323 +++++ Bindings/edac/socfpga-eccmgr.txt | 383 ------ Bindings/eeprom/at24.yaml | 5 +- Bindings/firmware/fsl,scu.yaml | 12 + Bindings/firmware/google,gs101-acpm-ipc.yaml | 50 + Bindings/firmware/thead,th1520-aon.yaml | 53 + Bindings/fsi/ibm,p9-scom.yaml | 1 + Bindings/gpio/aspeed,ast2400-gpio.yaml | 6 + Bindings/gpio/gpio-mvebu.yaml | 10 + Bindings/gpio/gpio-vf610.yaml | 1 + Bindings/gpio/loongson,ls-gpio.yaml | 3 + Bindings/gpio/nxp,pcf8575.yaml | 37 + Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml | 1 - Bindings/gpu/arm,mali-bifrost.yaml | 4 + Bindings/gpu/arm,mali-midgard.yaml | 5 +- Bindings/hwinfo/samsung,exynos-chipid.yaml | 2 + Bindings/hwmon/adi,ad741x.yaml | 1 - Bindings/hwmon/adi,adm1275.yaml | 1 - Bindings/hwmon/adi,ltc2991.yaml | 1 - Bindings/hwmon/gpio-fan.yaml | 3 + Bindings/hwmon/lltc,ltc2978.yaml | 5 + Bindings/hwmon/maxim,max20730.yaml | 1 - Bindings/hwmon/maxim,max6639.yaml | 1 - Bindings/hwmon/maxim,max6650.yaml | 1 - Bindings/hwmon/microchip,emc2305.yaml | 111 ++ Bindings/hwmon/national,lm90.yaml | 6 + Bindings/hwmon/ntc-thermistor.yaml | 2 +- Bindings/hwmon/nuvoton,nct6775.yaml | 1 - Bindings/hwmon/nuvoton,nct7363.yaml | 1 - Bindings/hwmon/nuvoton,nct7802.yaml | 1 - Bindings/hwmon/pmbus/ti,ucd90320.yaml | 9 + Bindings/hwmon/ti,adc128d818.yaml | 1 - Bindings/hwmon/ti,ads7828.yaml | 1 - Bindings/hwmon/ti,ina2xx.yaml | 31 +- Bindings/hwmon/ti,lm87.yaml | 1 - Bindings/hwmon/ti,tmp513.yaml | 1 - Bindings/hwmon/ti,tps23861.yaml | 1 - Bindings/hwmon/winbond,w83781d.yaml | 1 - Bindings/i2c/i2c-exynos5.yaml | 1 + Bindings/i2c/i2c-imx-lpi2c.yaml | 1 + Bindings/i2c/i2c-rk3x.yaml | 1 + Bindings/i2c/qcom,i2c-qup.yaml | 14 + Bindings/i2c/samsung,s3c2410-i2c.yaml | 1 + Bindings/i2c/snps,designware-i2c.yaml | 5 + Bindings/i2c/spacemit,k1-i2c.yaml | 61 + Bindings/i2c/ti,omap4-i2c.yaml | 6 + Bindings/i3c/silvaco,i3c-master.yaml | 4 +- Bindings/i3c/snps,dw-i3c-master.yaml | 3 + Bindings/iio/adc/adi,ad4030.yaml | 110 ++ Bindings/iio/adc/adi,ad4695.yaml | 13 + Bindings/iio/adc/adi,ad4851.yaml | 153 +++ Bindings/iio/adc/adi,ad7191.yaml | 149 +++ Bindings/iio/adc/adi,ad7380.yaml | 4 + Bindings/iio/adc/adi,axi-adc.yaml | 72 +- Bindings/iio/adc/nxp,imx93-adc.yaml | 9 +- Bindings/iio/adc/rockchip-saradc.yaml | 2 + Bindings/iio/adc/ti,ads7138.yaml | 63 + Bindings/iio/adc/xlnx,zynqmp-ams.yaml | 3 +- Bindings/iio/dac/adi,ad5380.yaml | 18 +- Bindings/iio/frequency/adf4371.yaml | 5 +- Bindings/iio/humidity/sciosense,ens210.yaml | 12 +- Bindings/iio/imu/adi,adis16550.yaml | 74 ++ Bindings/iio/light/brcm,apds9160.yaml | 78 ++ Bindings/iio/light/dynaimage,al3010.yaml | 6 +- Bindings/iio/magnetometer/silabs,si7210.yaml | 48 + Bindings/iio/temperature/maxim,max31865.yaml | 20 +- Bindings/iio/temperature/ti,tmp117.yaml | 6 +- Bindings/input/gpio-matrix-keypad.txt | 49 - Bindings/input/gpio-matrix-keypad.yaml | 103 ++ Bindings/input/mediatek,mt6779-keypad.yaml | 2 +- Bindings/input/qcom,pm8921-keypad.yaml | 46 +- Bindings/input/qcom,pm8921-pwrkey.yaml | 36 +- .../input/touchscreen/apple,z2-multitouch.yaml | 70 + Bindings/input/touchscreen/goodix,gt9916.yaml | 1 + Bindings/input/touchscreen/ti,ads7843.yaml | 32 +- .../allwinner,sun7i-a20-sc-nmi.yaml | 1 + .../amlogic,meson-gpio-intc.yaml | 19 +- .../interrupt-controller/brcm,bcm2712-msix.yaml | 60 + Bindings/interrupt-controller/fsl,irqsteer.yaml | 1 + Bindings/interrupt-controller/nxp,lpc3220-mic.txt | 58 - Bindings/interrupt-controller/nxp,lpc3220-mic.yaml | 68 + .../interrupt-controller/renesas,rzv2h-icu.yaml | 6 +- Bindings/interrupt-controller/riscv,aplic.yaml | 8 + .../interrupt-controller/sophgo,sg2042-msi.yaml | 61 + Bindings/iommu/arm,smmu.yaml | 3 +- Bindings/iommu/qcom,iommu.yaml | 1 + Bindings/leds/backlight/apple,dwi-bl.yaml | 57 + Bindings/leds/leds-qcom-lpg.yaml | 4 + Bindings/leds/leds-tlc591xx.txt | 40 - Bindings/leds/ti,tlc59116.yaml | 90 ++ Bindings/mailbox/fsl,mu.yaml | 7 +- Bindings/mailbox/mediatek,gce-mailbox.yaml | 4 + Bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 + Bindings/media/aspeed,video-engine.yaml | 70 + Bindings/media/aspeed-video.txt | 33 - Bindings/media/i2c/adv7180.yaml | 4 + Bindings/media/i2c/st,st-mipid02.yaml | 2 +- Bindings/media/mediatek,vcodec-encoder.yaml | 6 - Bindings/media/mediatek,vcodec-subdev-decoder.yaml | 100 +- Bindings/media/mediatek-jpeg-decoder.yaml | 3 +- Bindings/media/mediatek-jpeg-encoder.yaml | 2 +- Bindings/media/qcom,sc7280-camss.yaml | 10 +- Bindings/media/qcom,sdm670-camss.yaml | 318 +++++ Bindings/media/qcom,sm8550-camss.yaml | 597 +++++++++ Bindings/media/qcom,sm8550-iris.yaml | 158 +++ Bindings/media/snps,dw-hdmi-rx.yaml | 132 ++ Bindings/media/st,stm32mp25-csi.yaml | 5 +- Bindings/memory-controllers/exynos-srom.yaml | 36 +- .../memory-controllers/mc-peripheral-props.yaml | 2 + .../qcom,ebi2-peripheral-props.yaml | 91 ++ Bindings/memory-controllers/qcom,ebi2.yaml | 156 +++ .../samsung,exynos4210-srom-peripheral-props.yaml | 35 + Bindings/mfd/aspeed-lpc.yaml | 2 +- Bindings/mfd/atmel,sama5d2-flexcom.yaml | 9 +- Bindings/mfd/fsl,mcu-mpc8349emitx.yaml | 53 + Bindings/mfd/maxim,max77705.yaml | 158 +++ Bindings/mfd/motorola-cpcap.txt | 6 + Bindings/mfd/qcom,tcsr.yaml | 1 + Bindings/mfd/realtek,rtl9301-switch.yaml | 114 -- Bindings/mfd/samsung,s2mps11.yaml | 13 + Bindings/mfd/st,stm32-timers.yaml | 18 +- Bindings/mfd/syscon.yaml | 8 + Bindings/mips/mti,mips-cm.yaml | 57 + Bindings/misc/atmel-ssc.txt | 50 - Bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 38 +- Bindings/mmc/amlogic,meson-mx-sdio.yaml | 3 + Bindings/mmc/atmel,hsmci.yaml | 106 ++ Bindings/mmc/atmel-hsmci.txt | 73 - Bindings/mmc/fsl-imx-esdhc.yaml | 1 + Bindings/mmc/mmc-controller.yaml | 2 +- Bindings/mmc/mmc-slot.yaml | 1 - Bindings/mmc/renesas,sdhi.yaml | 16 + Bindings/mmc/rockchip-dw-mshc.yaml | 2 + Bindings/mmc/samsung,exynos-dw-mshc.yaml | 2 + Bindings/mmc/snps,dwcmshc-sdhci.yaml | 5 +- Bindings/mtd/arasan,nand-controller.yaml | 2 +- Bindings/mtd/atmel,dataflash.yaml | 55 + Bindings/mtd/atmel-dataflash.txt | 17 - Bindings/mtd/gpmi-nand.yaml | 7 + Bindings/mtd/mtd-physmap.yaml | 5 +- Bindings/mtd/mxc-nand.yaml | 8 +- Bindings/net/airoha,en7581-eth.yaml | 10 + Bindings/net/airoha,en7581-npu.yaml | 84 ++ Bindings/net/amlogic,meson-dwmac.yaml | 6 + Bindings/net/bluetooth/nxp,88w8987-bt.yaml | 18 +- Bindings/net/bluetooth/qualcomm-bluetooth.yaml | 2 + Bindings/net/can/fsl,flexcan.yaml | 57 +- Bindings/net/can/microchip,mcp2510.yaml | 2 +- Bindings/net/can/microchip,mcp251xfd.yaml | 2 +- Bindings/net/cdns,macb.yaml | 7 +- Bindings/net/dsa/brcm,b53.yaml | 2 + Bindings/net/ethernet-controller.yaml | 97 +- Bindings/net/ethernet-phy.yaml | 6 + Bindings/net/faraday,ftgmac100.yaml | 3 + Bindings/net/fsl,gianfar-mdio.yaml | 112 ++ Bindings/net/fsl,gianfar.yaml | 248 ++++ Bindings/net/fsl-tsec-phy.txt | 80 +- Bindings/net/ieee802154/ca8210.txt | 2 +- Bindings/net/intel,dwmac-plat.yaml | 6 + Bindings/net/mediatek-dwmac.yaml | 6 + Bindings/net/nxp,dwmac-imx.yaml | 8 + Bindings/net/qcom,ipa.yaml | 128 +- Bindings/net/realtek,rtl9301-mdio.yaml | 86 ++ Bindings/net/realtek,rtl9301-switch.yaml | 175 +++ Bindings/net/rfkill-gpio.yaml | 5 + Bindings/net/rockchip-dwmac.yaml | 47 +- Bindings/net/smsc,lan9115.yaml | 6 +- Bindings/net/snps,dwmac.yaml | 10 +- Bindings/net/sophgo,sg2044-dwmac.yaml | 126 ++ Bindings/net/stm32-dwmac.yaml | 10 + Bindings/net/tesla,fsd-ethqos.yaml | 118 ++ Bindings/net/toshiba,visconti-dwmac.yaml | 6 + Bindings/net/wireless/qcom,ath10k.yaml | 21 + Bindings/net/wireless/qcom,ath11k-pci.yaml | 9 +- Bindings/net/wireless/qcom,ath11k.yaml | 7 + Bindings/net/wireless/qcom,ath12k-wsi.yaml | 13 +- Bindings/nvmem/layouts/fixed-cell.yaml | 2 +- Bindings/nvmem/qcom,qfprom.yaml | 4 + Bindings/nvmem/rockchip,otp.yaml | 25 + Bindings/pci/altr,pcie-root-port.yaml | 10 + Bindings/pci/amd,versal2-mdb-host.yaml | 121 ++ Bindings/pci/brcm,stb-pcie.yaml | 6 +- Bindings/pci/fsl,imx6q-pcie.yaml | 4 + Bindings/pci/fsl,layerscape-pcie-ep.yaml | 3 - Bindings/pci/fsl,mpc8xxx-pci.yaml | 113 ++ Bindings/pci/fsl,pci.txt | 27 - Bindings/pci/mediatek-pcie-gen3.yaml | 17 + Bindings/pci/pci-ep-bus.yaml | 58 + Bindings/pci/qcom,pcie-ep.yaml | 100 +- Bindings/pci/qcom,pcie.yaml | 8 +- Bindings/pci/snps,dw-pcie.yaml | 2 + Bindings/pci/xilinx-versal-cpm.yaml | 1 + Bindings/phy/allwinner,sun50i-a64-usb-phy.yaml | 4 +- Bindings/phy/phy-rockchip-naneng-combphy.yaml | 1 + Bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml | 76 ++ Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 11 +- Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml | 2 + Bindings/phy/rockchip,rk3588-hdptx-phy.yaml | 62 +- Bindings/phy/rockchip,rk3588-mipi-dcphy.yaml | 87 ++ Bindings/phy/samsung,ufs-phy.yaml | 1 + Bindings/phy/samsung,usb3-drd-phy.yaml | 21 +- Bindings/pinctrl/airoha,en7581-pinctrl.yaml | 3 + .../pinctrl/allwinner,sun55i-a523-pinctrl.yaml | 175 +++ Bindings/pinctrl/amlogic,pinctrl-a4.yaml | 126 ++ Bindings/pinctrl/atmel,at91-pio4-pinctrl.txt | 1 + Bindings/pinctrl/brcm,bcm21664-pinctrl.yaml | 152 +++ Bindings/pinctrl/ingenic,pinctrl.yaml | 2 + Bindings/pinctrl/qcom,sa8775p-tlmm.yaml | 2 +- Bindings/pinctrl/rockchip,pinctrl.yaml | 1 + .../pinctrl/samsung,pinctrl-wakeup-interrupt.yaml | 3 + Bindings/pinctrl/samsung,pinctrl.yaml | 2 + Bindings/pinctrl/sophgo,sg2042-pinctrl.yaml | 129 ++ Bindings/platform/huawei,gaokun-ec.yaml | 124 ++ Bindings/power/allwinner,sun20i-d1-ppu.yaml | 1 + Bindings/power/apple,pmgr-pwrstate.yaml | 5 + Bindings/power/qcom,kpss-acc-v2.yaml | 4 +- Bindings/power/reset/atmel,sama5d2-shdwc.yaml | 5 + Bindings/power/reset/xlnx,zynqmp-power.yaml | 1 - Bindings/power/rockchip,power-controller.yaml | 3 + Bindings/power/supply/maxim,max77705.yaml | 50 + .../x-powers,axp20x-battery-power-supply.yaml | 20 +- Bindings/power/wakeup-source.txt | 2 +- Bindings/powerpc/fsl/dma.txt | 204 --- Bindings/powerpc/fsl/mcu-mpc8349emitx.txt | 17 - Bindings/pps/pps-gpio.yaml | 22 +- Bindings/pwm/imx-tpm-pwm.yaml | 11 +- Bindings/pwm/pwm-nexus-node.yaml | 65 + Bindings/pwm/pwm-rockchip.yaml | 2 + Bindings/pwm/renesas,tpu-pwm.yaml | 9 - Bindings/pwm/sophgo,sg2042-pwm.yaml | 58 + Bindings/regulator/nxp,pca9450-regulator.yaml | 51 +- Bindings/regulator/richtek,rtq2208.yaml | 3 +- Bindings/regulator/samsung,s2mpu05.yaml | 47 + Bindings/regulator/ti,tps65219.yaml | 27 +- Bindings/remoteproc/qcom,msm8916-mss-pil.yaml | 64 +- Bindings/remoteproc/qcom,sc8180x-pas.yaml | 96 -- Bindings/remoteproc/qcom,sm6115-pas.yaml | 2 +- Bindings/remoteproc/qcom,sm8150-pas.yaml | 7 + Bindings/remoteproc/qcom,sm8550-pas.yaml | 46 +- Bindings/remoteproc/qcom,wcnss-pil.yaml | 45 +- Bindings/reset/atmel,at91sam9260-reset.yaml | 4 + Bindings/reset/xlnx,zynqmp-reset.yaml | 1 - Bindings/riscv/extensions.yaml | 149 +++ Bindings/riscv/spacemit.yaml | 1 + Bindings/rng/rockchip,rk3588-rng.yaml | 59 + Bindings/rtc/adi,max31335.yaml | 4 +- Bindings/rtc/nxp,pcf2127.yaml | 3 +- Bindings/rtc/qcom-pm8xxx-rtc.yaml | 5 + Bindings/serial/8250.yaml | 2 +- Bindings/serial/fsl-lpuart.yaml | 1 + Bindings/serial/nvidia,tegra264-utc.yaml | 73 + Bindings/serial/pl011.yaml | 3 + Bindings/serial/samsung_uart.yaml | 4 + Bindings/serial/snps-dw-apb-uart.yaml | 21 + Bindings/serial/sprd-uart.yaml | 9 +- Bindings/soc/fsl/fsl,ls1028a-reset.yaml | 2 +- Bindings/soc/imx/fsl,aips-bus.yaml | 5 +- Bindings/soc/qcom/qcom,geni-se.yaml | 5 + Bindings/soc/qcom/qcom,pmic-glink.yaml | 1 + Bindings/soc/renesas/renesas,r9a09g057-sys.yaml | 5 +- Bindings/soc/renesas/renesas.yaml | 16 + Bindings/soc/rockchip/grf.yaml | 3 + Bindings/soc/samsung/exynos-pmu.yaml | 2 + Bindings/soc/samsung/exynos-usi.yaml | 100 +- Bindings/soc/samsung/samsung,exynos-sysreg.yaml | 5 + Bindings/soc/xilinx/xilinx.yaml | 11 +- Bindings/sound/allwinner,sun4i-a10-codec.yaml | 6 + Bindings/sound/atmel,at91-ssc.yaml | 104 ++ Bindings/sound/atmel,at91sam9g20ek-wm8731.yaml | 72 + .../sound/atmel-at91sam9g20ek-wm8731-audio.txt | 26 - Bindings/sound/audio-graph-card2.yaml | 4 + Bindings/sound/awinic,aw88395.yaml | 1 + Bindings/sound/dmic-codec.yaml | 3 + Bindings/sound/everest,es8328.yaml | 11 +- Bindings/sound/fsl,audmix.yaml | 61 +- Bindings/sound/fsl,easrc.yaml | 5 +- Bindings/sound/fsl,imx-asrc.yaml | 15 +- Bindings/sound/fsl,imx95-cm7-sof.yaml | 64 + Bindings/sound/fsl,sai.yaml | 55 + Bindings/sound/fsl,sof-cpu.yaml | 27 + Bindings/sound/ics43432.txt | 19 - Bindings/sound/imx-audio-card.yaml | 14 + Bindings/sound/invensense,ics43432.yaml | 51 + Bindings/sound/mediatek,mt8188-mt6359.yaml | 9 + Bindings/sound/nvidia,tegra30-hda.yaml | 1 + Bindings/sound/qcom,wcd937x-sdw.yaml | 36 + Bindings/sound/rockchip-spdif.yaml | 4 + Bindings/sound/ti,tas2770.yaml | 1 + Bindings/sound/ti,tas27xx.yaml | 1 + Bindings/sound/wlf,wm8904.yaml | 129 ++ Bindings/sound/wlf,wm8960.yaml | 4 + Bindings/sound/xlnx,audio-formatter.txt | 29 - Bindings/sound/xlnx,audio-formatter.yaml | 72 + Bindings/sound/xlnx,i2s.txt | 28 - Bindings/sound/xlnx,i2s.yaml | 65 + Bindings/sound/xlnx,spdif.txt | 28 - Bindings/sound/xlnx,spdif.yaml | 77 ++ Bindings/spi/adi,axi-spi-engine.yaml | 24 + Bindings/spi/cdns,qspi-nor.yaml | 25 +- Bindings/spi/fsl,espi.yaml | 65 + Bindings/spi/fsl,spi.yaml | 74 ++ Bindings/spi/fsl-spi.txt | 62 - Bindings/spi/mediatek,spi-mt65xx.yaml | 2 + Bindings/spi/qcom,spi-qpic-snand.yaml | 83 ++ Bindings/spi/snps,dw-apb-ssi.yaml | 19 +- Bindings/spi/spi-fsl-lpspi.yaml | 1 + Bindings/spi/spi-rockchip.yaml | 1 + Bindings/spi/spi-sg2044-nor.yaml | 52 + Bindings/spi/spi-zynqmp-qspi.yaml | 3 +- Bindings/spi/st,stm32mp25-ospi.yaml | 105 ++ Bindings/submitting-patches.rst | 19 +- Bindings/thermal/allwinner,sun8i-a83t-ths.yaml | 48 +- Bindings/thermal/brcm,avs-tmon.yaml | 1 + Bindings/thermal/imx-thermal.yaml | 40 +- Bindings/thermal/imx8mm-thermal.yaml | 8 +- Bindings/thermal/qcom-tsens.yaml | 18 + Bindings/thermal/thermal-zones.yaml | 5 +- Bindings/timer/arm,twd-timer.yaml | 6 +- Bindings/timer/nxp,sysctr-timer.yaml | 11 +- Bindings/timer/renesas,cmt.yaml | 44 +- Bindings/timer/renesas,em-sti.yaml | 10 +- Bindings/timer/renesas,mtu2.yaml | 14 +- Bindings/timer/renesas,ostm.yaml | 10 +- Bindings/timer/renesas,tmu.yaml | 22 +- Bindings/timer/renesas,tpu.yaml | 56 - Bindings/timer/samsung,exynos4210-mct.yaml | 4 + Bindings/timer/sifive,clint.yaml | 24 +- Bindings/trigger-source/pwm-trigger.yaml | 37 + Bindings/trivial-devices.yaml | 13 + Bindings/ufs/renesas,ufs.yaml | 12 + Bindings/ufs/rockchip,rk3576-ufshc.yaml | 105 ++ Bindings/usb/dwc3-xilinx.yaml | 4 +- Bindings/usb/generic-xhci.yaml | 2 + Bindings/usb/mediatek,mtk-xhci.yaml | 4 + Bindings/usb/mediatek,mtu3.yaml | 12 + Bindings/usb/microchip,usb2514.yaml | 35 +- Bindings/usb/microchip,usb5744.yaml | 1 - Bindings/usb/parade,ps8830.yaml | 140 ++ Bindings/usb/qcom,dwc3.yaml | 2 + Bindings/usb/richtek,rt1711h.yaml | 3 + Bindings/usb/rockchip,dwc3.yaml | 19 + Bindings/usb/samsung,exynos-dwc3.yaml | 44 +- Bindings/usb/snps,dwc3-common.yaml | 11 + Bindings/usb/usb-device.yaml | 6 +- Bindings/usb/xlnx,usb2.yaml | 1 - Bindings/vendor-prefixes.yaml | 16 +- Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 2 + Bindings/watchdog/fsl-imx7ulp-wdt.yaml | 4 + Bindings/watchdog/renesas,wdt.yaml | 4 + Bindings/xilinx.txt | 26 - include/dt-bindings/clock/mediatek,mt8188-clk.h | 2 +- include/dt-bindings/clock/mediatek,mtmips-sysc.h | 130 ++ include/dt-bindings/clock/qcom,dsi-phy-28nm.h | 9 + include/dt-bindings/clock/qcom,gcc-sdm660.h | 2 + include/dt-bindings/clock/qcom,ipq9574-gcc.h | 1 + include/dt-bindings/clock/qcom,ipq9574-nsscc.h | 152 +++ include/dt-bindings/clock/qcom,rpmcc.h | 4 + include/dt-bindings/clock/rk3188-cru-common.h | 2 + include/dt-bindings/clock/rockchip,rk3528-cru.h | 453 +++++++ include/dt-bindings/clock/rockchip,rk3562-cru.h | 379 ++++++ include/dt-bindings/clock/rockchip,rk3576-cru.h | 5 + include/dt-bindings/clock/samsung,exynos2200-cmu.h | 431 ++++++ include/dt-bindings/clock/samsung,exynos7870-cmu.h | 324 +++++ include/dt-bindings/clock/samsung,exynos990.h | 21 + include/dt-bindings/clock/sun50i-h616-ccu.h | 4 + include/dt-bindings/clock/sun55i-a523-ccu.h | 189 +++ include/dt-bindings/clock/sun55i-a523-r-ccu.h | 37 + include/dt-bindings/clock/xlnx-zynqmp-clk.h | 7 + include/dt-bindings/iio/adc/adi,ad4695.h | 7 + include/dt-bindings/pinctrl/amlogic,pinctrl.h | 46 + include/dt-bindings/pinctrl/pinctrl-sg2042.h | 196 +++ include/dt-bindings/pinctrl/pinctrl-sg2044.h | 221 ++++ .../dt-bindings/power/allwinner,sun8i-v853-ppu.h | 10 + include/dt-bindings/power/qcom-rpmpd.h | 2 +- include/dt-bindings/power/thead,th1520-power.h | 19 + include/dt-bindings/reset/imx8mp-reset-audiomix.h | 13 + include/dt-bindings/reset/qcom,ipq9574-nsscc.h | 134 ++ include/dt-bindings/reset/rockchip,rk3528-cru.h | 241 ++++ include/dt-bindings/reset/rockchip,rk3562-cru.h | 358 +++++ include/dt-bindings/reset/rockchip,rk3588-cru.h | 41 +- include/dt-bindings/reset/sun50i-h616-ccu.h | 2 + include/dt-bindings/reset/sun55i-a523-ccu.h | 88 ++ include/dt-bindings/reset/sun55i-a523-r-ccu.h | 25 + include/dt-bindings/soc/samsung,exynos-usi.h | 17 +- include/dt-bindings/sound/qcom,wcd934x.h | 16 + src/arm/allwinner/sun8i-v3s-netcube-kumquat.dts | 276 ++++ src/arm/allwinner/sun8i-v3s.dtsi | 6 + src/arm/amlogic/meson8.dtsi | 18 +- src/arm/amlogic/meson8b-ec100.dts | 2 - src/arm/amlogic/meson8b-mxq.dts | 2 - src/arm/amlogic/meson8b-odroidc1.dts | 2 - src/arm/amlogic/meson8b.dtsi | 18 +- src/arm/cirrus/ep7211-edb7211.dts | 2 +- src/arm/intel/ixp/intel-ixp42x-netgear-wg302v1.dts | 40 +- src/arm/intel/ixp/intel-ixp4xx.dtsi | 2 +- src/arm/marvell/armada-385-clearfog-gtr.dtsi | 8 +- src/arm/marvell/armada-388-clearfog-base.dts | 2 +- src/arm/marvell/kirkwood-openrd.dtsi | 4 +- src/arm/microchip/aks-cdu.dts | 2 +- src/arm/microchip/animeo_ip.dts | 2 +- src/arm/microchip/at91-foxg20.dts | 2 +- src/arm/microchip/at91-qil_a9260.dts | 2 +- src/arm/microchip/at91-sam9_l9260.dts | 2 +- src/arm/microchip/at91-sama5d27_som1_ek.dts | 4 +- src/arm/microchip/at91-sama5d2_ptc_ek.dts | 4 +- src/arm/microchip/at91-sama5d2_xplained.dts | 4 +- src/arm/microchip/at91-sama5d3_xplained.dts | 4 +- src/arm/microchip/at91-sama5d4_ma5d4evk.dts | 4 +- src/arm/microchip/at91-sama5d4_xplained.dts | 4 +- src/arm/microchip/at91-sama5d4ek.dts | 4 +- src/arm/microchip/at91-sama7d65_curiosity.dts | 73 + src/arm/microchip/at91-sama7g5ek.dts | 1 + src/arm/microchip/at91-vinco.dts | 4 +- src/arm/microchip/at91rm9200.dtsi | 2 +- src/arm/microchip/at91rm9200ek.dts | 2 +- src/arm/microchip/at91sam9260.dtsi | 2 +- src/arm/microchip/at91sam9260ek.dts | 2 +- src/arm/microchip/at91sam9261.dtsi | 2 +- src/arm/microchip/at91sam9261ek.dts | 2 +- src/arm/microchip/at91sam9263.dtsi | 2 +- src/arm/microchip/at91sam9263ek.dts | 2 +- src/arm/microchip/at91sam9g20ek_common.dtsi | 2 +- src/arm/microchip/at91sam9g45.dtsi | 4 +- src/arm/microchip/at91sam9m10g45ek.dts | 4 +- src/arm/microchip/at91sam9n12.dtsi | 2 +- src/arm/microchip/at91sam9n12ek.dts | 2 +- src/arm/microchip/at91sam9x5.dtsi | 4 +- src/arm/microchip/ethernut5.dts | 2 +- src/arm/microchip/evk-pro3.dts | 2 +- src/arm/microchip/mpa1600.dts | 2 +- src/arm/microchip/pm9g45.dts | 4 +- src/arm/microchip/sam9x60.dtsi | 4 +- src/arm/microchip/sama5d2.dtsi | 4 +- src/arm/microchip/sama5d3.dtsi | 4 +- src/arm/microchip/sama5d3xmb.dtsi | 4 +- src/arm/microchip/sama5d4.dtsi | 4 +- src/arm/microchip/sama7d65.dtsi | 95 ++ src/arm/microchip/tny_a9260.dts | 2 +- src/arm/microchip/tny_a9260_common.dtsi | 2 +- src/arm/microchip/tny_a9263.dts | 2 +- src/arm/microchip/tny_a9g20.dts | 2 +- src/arm/microchip/usb_a9260.dts | 2 +- src/arm/microchip/usb_a9260_common.dtsi | 11 +- src/arm/microchip/usb_a9263.dts | 11 +- src/arm/microchip/usb_a9g20-dab-mmx.dtsi | 10 +- src/arm/microchip/usb_a9g20.dts | 2 +- src/arm/microchip/usb_a9g20_common.dtsi | 2 +- src/arm/microchip/usb_a9g20_lpw.dts | 4 +- src/arm/nvidia/tegra114.dtsi | 34 +- src/arm/nvidia/tegra124.dtsi | 40 + src/arm/nvidia/tegra20-asus-tf101.dts | 11 + src/arm/nxp/imx/imx31.dtsi | 2 +- src/arm/nxp/imx/imx50.dtsi | 2 +- src/arm/nxp/imx/imx51.dtsi | 2 +- src/arm/nxp/imx/imx53-mba53.dts | 2 +- src/arm/nxp/imx/imx53-ppd.dts | 2 +- src/arm/nxp/imx/imx53.dtsi | 2 +- src/arm/nxp/imx/imx6dl-colibri-v1.2-aster.dts | 11 + src/arm/nxp/imx/imx6dl-colibri-v1.2-eval-v3.dts | 11 + src/arm/nxp/imx/imx6dl-colibri-v1.2-iris-v2.dts | 11 + src/arm/nxp/imx/imx6dl-colibri-v1.2-iris.dts | 11 + src/arm/nxp/imx/imx6q-apalis-v1.2-eval-v1.2.dts | 11 + src/arm/nxp/imx/imx6q-apalis-v1.2-eval.dts | 11 + src/arm/nxp/imx/imx6q-apalis-v1.2-ixora-v1.1.dts | 11 + src/arm/nxp/imx/imx6q-apalis-v1.2-ixora-v1.2.dts | 11 + src/arm/nxp/imx/imx6q-apalis-v1.2-ixora.dts | 11 + src/arm/nxp/imx/imx6qdl-apalis-v1.2.dtsi | 57 + src/arm/nxp/imx/imx6qdl-apalis.dtsi | 2 - src/arm/nxp/imx/imx6qdl-colibri-v1.2.dtsi | 57 + src/arm/nxp/imx/imx6qdl-colibri.dtsi | 2 - src/arm/nxp/imx/imx6qdl-mba6.dtsi | 2 +- src/arm/nxp/imx/imx6qdl-tqma6.dtsi | 25 +- src/arm/nxp/imx/imx6qdl-tqma6a.dtsi | 4 +- src/arm/nxp/imx/imx6qdl-tqma6b.dtsi | 4 +- src/arm/nxp/imx/imx6ul-14x14-evk.dtsi | 32 + src/arm/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi | 3 + src/arm/nxp/imx/imx6ul-tqma6ul-common.dtsi | 11 +- src/arm/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts | 3 +- src/arm/nxp/imx/imx6ul-tqma6ul1.dtsi | 2 - src/arm/nxp/imx/imx6ul-var-som-concerto.dts | 320 +++++ src/arm/nxp/imx/imx6ul-var-som.dtsi | 233 ++++ src/arm/nxp/imx/imx7-mba7.dtsi | 2 +- src/arm/nxp/imx/imx7-tqma7.dtsi | 7 + src/arm/nxp/imx/imx7d-sdb.dts | 32 + src/arm/nxp/imx/imx7s.dtsi | 56 +- src/arm/nxp/imx/mba6ulx.dtsi | 2 +- src/arm/nxp/mxs/imx28-btt3-0.dts | 12 + src/arm/nxp/mxs/imx28-btt3-1.dts | 8 + src/arm/nxp/mxs/imx28-btt3-2.dts | 39 + src/arm/nxp/mxs/imx28-btt3.dtsi | 313 +++++ src/arm/nxp/mxs/imx28-sps1.dts | 13 +- src/arm/nxp/vf/vf610-bk4.dts | 4 +- src/arm/nxp/vf/vf610-colibri.dtsi | 1 - src/arm/nxp/vf/vf610-zii-dev-rev-c.dts | 4 +- src/arm/nxp/vf/vfxxx.dtsi | 21 +- src/arm/renesas/r8a7790-lager.dts | 1 + src/arm/renesas/r8a7790-stout.dts | 1 + src/arm/renesas/r8a7790.dtsi | 7 + src/arm/renesas/r8a7791-koelsch.dts | 1 + src/arm/renesas/r8a7791-porter.dts | 1 + src/arm/renesas/r8a7791.dtsi | 7 + src/arm/renesas/r8a7792-blanche.dts | 1 + src/arm/renesas/r8a7792-wheat.dts | 1 + src/arm/renesas/r8a7792.dtsi | 6 + src/arm/renesas/r8a7793-gose.dts | 1 + src/arm/renesas/r8a7793.dtsi | 7 + src/arm/renesas/r8a7794-alt.dts | 1 + src/arm/renesas/r8a7794-silk.dts | 1 + src/arm/renesas/r8a7794.dtsi | 7 + src/arm/renesas/r9a06g032.dtsi | 20 +- src/arm/st/stm32f746-disco.dts | 18 + src/arm/st/stm32f769-disco.dts | 7 +- src/arm/st/stm32mp131.dtsi | 35 + src/arm/st/stm32mp133c-prihmb.dts | 496 +++++++ src/arm/st/stm32mp135f-dhcor-dhsbc.dts | 30 +- src/arm/st/stm32mp15-pinctrl.dtsi | 292 ++++ src/arm/st/stm32mp151.dtsi | 1 - src/arm/st/stm32mp151c-plyaqm.dts | 376 ++++++ src/arm/st/stm32mp153c-lxa-fairytux2-gen1.dts | 103 ++ src/arm/st/stm32mp153c-lxa-fairytux2-gen2.dts | 147 ++ src/arm/st/stm32mp153c-lxa-fairytux2.dtsi | 397 ++++++ src/arm/st/stm32mp157c-dk2.dts | 2 +- src/arm/ti/davinci/da850-lego-ev3.dts | 10 +- src/arm/ti/omap/omap3-evm-processor-common.dtsi | 2 +- src/arm/ti/omap/omap4-l4.dtsi | 8 +- src/arm/ti/omap/omap4-panda-a4.dts | 5 + src/arm/xilinx/zynq-7000.dtsi | 33 +- src/arm/xilinx/zynq-cc108.dts | 41 +- src/arm/xilinx/zynq-ebaz4205.dts | 2 + src/arm/xilinx/zynq-microzed.dts | 10 +- src/arm/xilinx/zynq-parallella.dts | 1 - src/arm/xilinx/zynq-zc702.dts | 85 +- src/arm/xilinx/zynq-zc706.dts | 67 +- src/arm/xilinx/zynq-zc770-xm010.dts | 39 +- src/arm/xilinx/zynq-zc770-xm011.dts | 31 + src/arm/xilinx/zynq-zc770-xm012.dts | 35 + src/arm/xilinx/zynq-zc770-xm013.dts | 41 +- src/arm/xilinx/zynq-zed.dts | 43 +- src/arm/xilinx/zynq-zturn-common.dtsi | 8 + src/arm/xilinx/zynq-zybo-z7.dts | 10 +- src/arm/xilinx/zynq-zybo.dts | 9 +- src/arm64/airoha/en7581-evb.dts | 44 + src/arm64/airoha/en7581.dtsi | 91 ++ .../allwinner/sun50i-a100-allwinner-perf1.dts | 5 + src/arm64/allwinner/sun50i-a100-cpu-opp.dtsi | 90 ++ src/arm64/allwinner/sun50i-a100.dtsi | 8 + src/arm64/allwinner/sun50i-h6-beelink-gs1.dts | 38 +- src/arm64/allwinner/sun50i-h6-orangepi-3.dts | 14 +- src/arm64/allwinner/sun50i-h6-orangepi.dtsi | 22 +- .../allwinner/sun50i-h700-anbernic-rg35xx-2024.dts | 18 +- .../allwinner/sun50i-h700-anbernic-rg35xx-h.dts | 23 + src/arm64/amazon/alpine-v2.dtsi | 2 +- src/arm64/amazon/alpine-v3.dtsi | 2 +- src/arm64/amd/amd-overdrive-rev-b0.dts | 2 +- src/arm64/amd/amd-overdrive-rev-b1.dts | 61 +- src/arm64/amd/amd-seattle-clks.dtsi | 24 +- src/arm64/amd/amd-seattle-soc.dtsi | 8 +- src/arm64/amd/amd-seattle-xgbe-b.dtsi | 32 +- src/arm64/amlogic/amlogic-a4.dtsi | 21 + src/arm64/amlogic/amlogic-a5.dtsi | 12 + src/arm64/amlogic/meson-axg.dtsi | 24 +- src/arm64/amlogic/meson-g12-common.dtsi | 33 +- src/arm64/amlogic/meson-g12a-fbx8am.dts | 4 - src/arm64/amlogic/meson-g12a-radxa-zero.dts | 4 - src/arm64/amlogic/meson-g12a-sei510.dts | 4 - src/arm64/amlogic/meson-g12a-u200.dts | 2 - src/arm64/amlogic/meson-g12a-x96-max.dts | 4 - .../amlogic/meson-g12b-a311d-libretech-cc.dts | 2 - src/arm64/amlogic/meson-g12b-bananapi-cm4.dtsi | 4 - src/arm64/amlogic/meson-g12b-bananapi.dtsi | 4 - src/arm64/amlogic/meson-g12b-dreambox.dtsi | 4 + src/arm64/amlogic/meson-g12b-khadas-vim3.dtsi | 4 - src/arm64/amlogic/meson-g12b-odroid.dtsi | 4 - src/arm64/amlogic/meson-g12b-radxa-zero2.dts | 8 - src/arm64/amlogic/meson-g12b-w400.dtsi | 6 - src/arm64/amlogic/meson-gx-libretech-pc.dtsi | 6 - src/arm64/amlogic/meson-gx-p23x-q20x.dtsi | 2 - src/arm64/amlogic/meson-gx.dtsi | 8 +- src/arm64/amlogic/meson-gxbb-nanopi-k2.dts | 2 - src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts | 2 - src/arm64/amlogic/meson-gxbb-p20x.dtsi | 2 - src/arm64/amlogic/meson-gxbb-vega-s95.dtsi | 2 - src/arm64/amlogic/meson-gxbb-wetek.dtsi | 2 - src/arm64/amlogic/meson-gxbb.dtsi | 25 + src/arm64/amlogic/meson-gxl-s805x-p241.dts | 2 - .../amlogic/meson-gxl-s905w-jethome-jethub-j80.dts | 2 - .../amlogic/meson-gxl-s905x-hwacom-amazetv.dts | 2 - src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts | 2 - src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts | 2 - src/arm64/amlogic/meson-gxl-s905x-p212.dtsi | 2 - src/arm64/amlogic/meson-gxl.dtsi | 25 + src/arm64/amlogic/meson-gxm-khadas-vim2.dts | 4 - src/arm64/amlogic/meson-gxm-rbox-pro.dts | 2 - src/arm64/amlogic/meson-libretech-cottonwood.dtsi | 6 - src/arm64/amlogic/meson-sm1-ac2xx.dtsi | 6 - src/arm64/amlogic/meson-sm1-bananapi.dtsi | 2 - src/arm64/amlogic/meson-sm1-khadas-vim3l.dts | 2 - src/arm64/amlogic/meson-sm1-odroid.dtsi | 2 - src/arm64/amlogic/meson-sm1-sei610.dts | 6 - src/arm64/apple/s5l8960x-5s.dtsi | 9 + src/arm64/apple/s5l8960x-air1.dtsi | 5 + src/arm64/apple/s5l8960x-mini2.dtsi | 5 + src/arm64/apple/s5l8960x-opp.dtsi | 45 + src/arm64/apple/s5l8960x-pmgr.dtsi | 610 +++++++++ src/arm64/apple/s5l8960x.dtsi | 30 + src/arm64/apple/s5l8965x-opp.dtsi | 45 + src/arm64/apple/s800-0-3-common.dtsi | 4 + src/arm64/apple/s800-0-3-pmgr.dtsi | 757 +++++++++++ src/arm64/apple/s800-0-3.dtsi | 179 +++ src/arm64/apple/s8000.dtsi | 162 +-- src/arm64/apple/s8001-common.dtsi | 1 + src/arm64/apple/s8001-j98a-j99a.dtsi | 26 + src/arm64/apple/s8001-j98a.dts | 1 + src/arm64/apple/s8001-j99a.dts | 1 + src/arm64/apple/s8001-pmgr.dtsi | 822 ++++++++++++ src/arm64/apple/s8001.dtsi | 81 ++ src/arm64/apple/s8003.dtsi | 63 +- src/arm64/apple/s800x-6s.dtsi | 4 + src/arm64/apple/s800x-ipad5.dtsi | 4 + src/arm64/apple/s800x-se.dtsi | 4 + src/arm64/apple/spi1-nvram.dtsi | 39 + src/arm64/apple/t600x-common.dtsi | 7 + src/arm64/apple/t600x-die0.dtsi | 28 + src/arm64/apple/t600x-gpio-pins.dtsi | 14 + src/arm64/apple/t600x-j314-j316.dtsi | 2 + src/arm64/apple/t600x-j375.dtsi | 2 + src/arm64/apple/t7000-6.dtsi | 8 + src/arm64/apple/t7000-handheld.dtsi | 4 + src/arm64/apple/t7000-j42d.dts | 5 + src/arm64/apple/t7000-mini4.dtsi | 12 + src/arm64/apple/t7000-n102.dts | 4 + src/arm64/apple/t7000-pmgr.dtsi | 641 +++++++++ src/arm64/apple/t7000.dtsi | 73 + src/arm64/apple/t7001-air2.dtsi | 1 + src/arm64/apple/t7001-pmgr.dtsi | 650 +++++++++ src/arm64/apple/t7001.dtsi | 65 + src/arm64/apple/t8010-7.dtsi | 12 + src/arm64/apple/t8010-common.dtsi | 4 + src/arm64/apple/t8010-ipad6.dtsi | 12 + src/arm64/apple/t8010-n112.dts | 4 + src/arm64/apple/t8010-pmgr.dtsi | 772 +++++++++++ src/arm64/apple/t8010.dtsi | 115 ++ src/arm64/apple/t8011-common.dtsi | 1 + src/arm64/apple/t8011-pmgr.dtsi | 806 +++++++++++ src/arm64/apple/t8011-pro2.dtsi | 8 + src/arm64/apple/t8011.dtsi | 101 ++ src/arm64/apple/t8012-j132.dts | 14 + src/arm64/apple/t8012-j137.dts | 14 + src/arm64/apple/t8012-j140a.dts | 14 + src/arm64/apple/t8012-j140k.dts | 14 + src/arm64/apple/t8012-j152f.dts | 15 + src/arm64/apple/t8012-j160.dts | 14 + src/arm64/apple/t8012-j174.dts | 14 + src/arm64/apple/t8012-j185.dts | 14 + src/arm64/apple/t8012-j185f.dts | 14 + src/arm64/apple/t8012-j213.dts | 15 + src/arm64/apple/t8012-j214k.dts | 15 + src/arm64/apple/t8012-j215.dts | 15 + src/arm64/apple/t8012-j223.dts | 15 + src/arm64/apple/t8012-j230k.dts | 14 + src/arm64/apple/t8012-j680.dts | 15 + src/arm64/apple/t8012-j780.dts | 15 + src/arm64/apple/t8012-jxxx.dtsi | 44 + src/arm64/apple/t8012-pmgr.dtsi | 837 ++++++++++++ src/arm64/apple/t8012-touchbar.dtsi | 20 + src/arm64/apple/t8012.dtsi | 281 ++++ src/arm64/apple/t8015-8.dtsi | 4 + src/arm64/apple/t8015-common.dtsi | 1 + src/arm64/apple/t8015-pmgr.dtsi | 931 +++++++++++++ src/arm64/apple/t8015.dtsi | 151 +++ src/arm64/apple/t8103-j293.dts | 68 + src/arm64/apple/t8103-jxxx.dtsi | 2 + src/arm64/apple/t8103-pmgr.dtsi | 18 +- src/arm64/apple/t8103.dtsi | 137 ++ src/arm64/apple/t8112-j493.dts | 64 + src/arm64/apple/t8112-jxxx.dtsi | 2 + src/arm64/apple/t8112.dtsi | 105 +- src/arm64/arm/corstone1000-fvp.dts | 26 + src/arm64/arm/corstone1000.dtsi | 3 +- src/arm64/arm/morello-fvp.dts | 77 ++ src/arm64/arm/morello-sdp.dts | 157 +++ src/arm64/arm/morello.dtsi | 323 +++++ src/arm64/exynos/exynos8895-dreamlte.dts | 72 + src/arm64/exynos/exynos8895.dtsi | 956 +++++++++++++- src/arm64/exynos/exynos990.dtsi | 92 +- src/arm64/exynos/exynosautov920.dtsi | 138 ++ src/arm64/exynos/google/gs101-oriole.dts | 267 +--- src/arm64/exynos/google/gs101-pixel-common.dtsi | 294 ++++ src/arm64/exynos/google/gs101-raven.dts | 29 + src/arm64/exynos/google/gs101.dtsi | 66 +- src/arm64/freescale/fsl-ls1088a-ten64.dts | 44 + src/arm64/freescale/imx8-apalis-v1.1.dtsi | 16 + src/arm64/freescale/imx8-ss-hsio.dtsi | 30 +- src/arm64/freescale/imx8dxl-evk.dts | 42 + src/arm64/freescale/imx8mm-kontron-bl.dts | 10 +- src/arm64/freescale/imx8mm-kontron-osm-s.dtsi | 7 +- .../freescale/imx8mm-phyboard-polis-peb-av-10.dtso | 237 ++++ .../imx8mm-phyboard-polis-peb-eval-01.dtso | 72 + src/arm64/freescale/imx8mm-phyboard-polis-rdk.dts | 17 +- src/arm64/freescale/imx8mm-phycore-no-eth.dtso | 12 + .../freescale/imx8mm-phycore-no-spiflash.dtso | 16 + src/arm64/freescale/imx8mm-phycore-rpmsg.dtso | 58 + src/arm64/freescale/imx8mm-phycore-som.dtsi | 22 +- src/arm64/freescale/imx8mm-phygate-tauri-l.dts | 11 + src/arm64/freescale/imx8mm-tqma8mqml.dtsi | 1 + src/arm64/freescale/imx8mm-verdin.dtsi | 46 +- src/arm64/freescale/imx8mn-bsh-smm-s2pro.dts | 1 - src/arm64/freescale/imx8mn-tqma8mqnl.dtsi | 1 + src/arm64/freescale/imx8mp-evk.dts | 22 + src/arm64/freescale/imx8mp-kontron-osm-s.dtsi | 7 +- src/arm64/freescale/imx8mp-nominal.dtsi | 92 ++ src/arm64/freescale/imx8mp-skov-basic.dts | 10 + src/arm64/freescale/imx8mp-skov-reva.dtsi | 131 +- src/arm64/freescale/imx8mp-skov-revb-hdmi.dts | 45 +- src/arm64/freescale/imx8mp-skov-revb-lt6.dts | 60 + .../freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts | 30 +- src/arm64/freescale/imx8mp-skov-revc-bd500.dts | 91 ++ .../freescale/imx8mp-skov-revc-tian-g07017.dts | 81 ++ src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts | 2 +- src/arm64/freescale/imx8mp-tqma8mpql.dtsi | 1 + src/arm64/freescale/imx8mp-var-som.dtsi | 12 +- src/arm64/freescale/imx8mp.dtsi | 29 +- src/arm64/freescale/imx8mq-librem5-devkit.dts | 25 +- src/arm64/freescale/imx8mq-librem5.dtsi | 26 +- src/arm64/freescale/imx8mq-tqma8mq.dtsi | 1 + src/arm64/freescale/imx8qm-apalis-v1.1.dtsi | 2 - src/arm64/freescale/imx8qm-apalis.dtsi | 2 - src/arm64/freescale/imx8qm-mek.dts | 112 ++ src/arm64/freescale/imx8qm-ss-hsio.dtsi | 24 +- src/arm64/freescale/imx8qxp-mek-pcie-ep.dtso | 22 + src/arm64/freescale/imx8qxp-mek.dts | 32 + src/arm64/freescale/imx8x-colibri.dtsi | 4 +- src/arm64/freescale/imx93-kontron-osm-s.dtsi | 5 +- src/arm64/freescale/imx93-tqma9352-mba93xxca.dts | 54 +- src/arm64/freescale/imx93-tqma9352-mba93xxla.dts | 6 +- src/arm64/freescale/imx93.dtsi | 8 + src/arm64/freescale/imx95-15x15-evk.dts | 1130 ++++++++++++++++ src/arm64/freescale/imx95-19x19-evk.dts | 83 ++ src/arm64/freescale/imx95.dtsi | 116 +- src/arm64/freescale/mba8mx.dtsi | 2 +- src/arm64/freescale/mba8xx.dtsi | 31 +- src/arm64/freescale/s32g2.dtsi | 141 ++ src/arm64/freescale/s32g274a-evb.dts | 1 + src/arm64/freescale/s32g274a-rdb2.dts | 1 + src/arm64/freescale/s32g3.dtsi | 150 +++ src/arm64/freescale/s32g399a-rdb3.dts | 9 + src/arm64/freescale/s32gxxxa-evb.dtsi | 222 ++++ src/arm64/freescale/s32gxxxa-rdb.dtsi | 170 +++ src/arm64/freescale/tqma8xx.dtsi | 12 +- src/arm64/hisilicon/hi3660-coresight.dtsi | 8 + src/arm64/marvell/ac5-98dx25xx.dtsi | 2 +- src/arm64/marvell/armada-371x.dtsi | 17 - src/arm64/marvell/armada-3720-db.dts | 2 +- src/arm64/marvell/armada-3720-espressobin-emmc.dts | 2 +- .../marvell/armada-3720-espressobin-ultra.dts | 2 +- .../marvell/armada-3720-espressobin-v7-emmc.dts | 2 +- src/arm64/marvell/armada-3720-espressobin-v7.dts | 2 +- src/arm64/marvell/armada-3720-espressobin.dts | 2 +- src/arm64/marvell/armada-3720-gl-mv1000.dts | 2 +- src/arm64/marvell/armada-3720-turris-mox.dts | 2 +- src/arm64/marvell/armada-3720-uDPU.dtsi | 8 +- src/arm64/marvell/armada-372x.dtsi | 3 - src/arm64/marvell/armada-37xx.dtsi | 4 +- src/arm64/marvell/armada-7020.dtsi | 6 - src/arm64/marvell/armada-7040.dtsi | 6 - src/arm64/marvell/armada-8020.dtsi | 6 - src/arm64/marvell/armada-8040-clearfog-gt-8k.dts | 8 +- src/arm64/marvell/armada-8040-puzzle-m801.dts | 2 +- src/arm64/marvell/armada-8040.dtsi | 6 - src/arm64/marvell/armada-8080.dtsi | 6 - src/arm64/marvell/armada-ap806-dual.dtsi | 3 - src/arm64/marvell/armada-ap806-quad.dtsi | 3 - src/arm64/marvell/armada-ap806.dtsi | 6 - src/arm64/marvell/armada-ap807-quad.dtsi | 3 - src/arm64/marvell/armada-ap807.dtsi | 6 - src/arm64/marvell/armada-ap80x.dtsi | 33 +- src/arm64/marvell/armada-ap810-ap0-octa-core.dtsi | 1 - src/arm64/marvell/armada-ap810-ap0.dtsi | 24 +- src/arm64/marvell/armada-cp110.dtsi | 4 - src/arm64/marvell/armada-cp115.dtsi | 4 - src/arm64/marvell/armada-cp11x.dtsi | 4 +- src/arm64/marvell/cn9130-sr-som.dtsi | 3 - src/arm64/mediatek/mt6359.dtsi | 3 +- src/arm64/mediatek/mt8173-elm.dtsi | 2 - src/arm64/mediatek/mt8173.dtsi | 12 +- src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts | 9 +- .../mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts | 8 +- .../mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts | 8 +- .../mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts | 8 +- src/arm64/mediatek/mt8188-geralt.dtsi | 173 ++- src/arm64/mediatek/mt8188.dtsi | 307 ++++- src/arm64/mediatek/mt8195-cherry.dtsi | 184 ++- src/arm64/mediatek/mt8195.dtsi | 129 ++ src/arm64/mediatek/mt8365-evk.dts | 245 +++- src/arm64/mediatek/mt8365.dtsi | 336 +++++ src/arm64/mediatek/mt8370-genio-510-evk.dts | 19 + src/arm64/mediatek/mt8370.dtsi | 64 + src/arm64/mediatek/mt8390-genio-700-evk.dts | 1033 +-------------- src/arm64/mediatek/mt8390-genio-common.dtsi | 1223 +++++++++++++++++ src/arm64/mediatek/mt8395-genio-1200-evk.dts | 102 ++ .../mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso | 84 ++ src/arm64/mediatek/mt8395-radxa-nio-12l.dts | 71 + src/arm64/nvidia/tegra210-p2180.dtsi | 13 + src/arm64/nvidia/tegra210-p2597.dtsi | 20 +- src/arm64/nvidia/tegra210-p3450-0000.dts | 10 - src/arm64/nvidia/tegra210.dtsi | 10 + .../nvidia/tegra234-p3740-0002+p3701-0008.dts | 10 + src/arm64/nvidia/tegra234-p3768-0000+p3767.dtsi | 7 - src/arm64/qcom/sc8280xp-huawei-gaokun3.dts | 163 +++ src/arm64/renesas/beacon-renesom-som.dtsi | 1 + src/arm64/renesas/condor-common.dtsi | 1 + src/arm64/renesas/draak.dtsi | 1 + src/arm64/renesas/ebisu.dtsi | 1 + src/arm64/renesas/hihope-common.dtsi | 1 + src/arm64/renesas/r8a774a1.dtsi | 8 + src/arm64/renesas/r8a774b1.dtsi | 8 + src/arm64/renesas/r8a774c0-cat874.dts | 1 + src/arm64/renesas/r8a774c0.dtsi | 11 + src/arm64/renesas/r8a774e1.dtsi | 8 + src/arm64/renesas/r8a77951.dtsi | 7 + src/arm64/renesas/r8a77960.dtsi | 8 + src/arm64/renesas/r8a77961.dtsi | 8 + src/arm64/renesas/r8a77965.dtsi | 8 + .../renesas/r8a77970-eagle-function-expansion.dtso | 2 +- src/arm64/renesas/r8a77970-eagle.dts | 1 + src/arm64/renesas/r8a77970-v3msk.dts | 1 + src/arm64/renesas/r8a77970.dtsi | 7 + src/arm64/renesas/r8a77980-v3hsk.dts | 1 + src/arm64/renesas/r8a77980.dtsi | 7 + src/arm64/renesas/r8a77990.dtsi | 11 + src/arm64/renesas/r8a77995.dtsi | 7 + src/arm64/renesas/r8a779a0-falcon-cpu.dtsi | 1 + src/arm64/renesas/r8a779a0.dtsi | 88 ++ src/arm64/renesas/r8a779f0-spider-cpu.dtsi | 1 + src/arm64/renesas/r8a779f0-spider-ethernet.dtsi | 104 +- src/arm64/renesas/r8a779f0.dtsi | 17 +- src/arm64/renesas/r8a779f4-s4sk.dts | 69 +- src/arm64/renesas/r8a779g0.dtsi | 88 +- src/arm64/renesas/r8a779h0-gray-hawk-single.dts | 154 ++- src/arm64/renesas/r8a779h0.dtsi | 34 +- src/arm64/renesas/r9a07g044l2-remi-pi.dts | 339 +++++ src/arm64/renesas/r9a08g045.dtsi | 29 +- .../renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso | 48 + src/arm64/renesas/r9a09g047.dtsi | 37 + src/arm64/renesas/r9a09g057.dtsi | 52 +- src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts | 15 + src/arm64/renesas/r9a09g057h48-kakip.dts | 136 ++ src/arm64/renesas/rzg3e-smarc-som.dtsi | 4 + src/arm64/renesas/rzg3s-smarc-som.dtsi | 20 +- src/arm64/renesas/rzg3s-smarc-switches.h | 40 + src/arm64/renesas/rzg3s-smarc.dtsi | 13 + src/arm64/renesas/salvator-common.dtsi | 1 + .../ulcb-kf-audio-graph-card-mix+split.dtsi | 73 +- .../ulcb-kf-audio-graph-card2-mix+split.dtsi | 66 +- .../ulcb-kf-simple-audio-card-mix+split.dtsi | 53 +- src/arm64/renesas/ulcb.dtsi | 1 + src/arm64/renesas/white-hawk-cpu-common.dtsi | 1 + src/arm64/renesas/white-hawk-csi-dsi.dtsi | 8 +- src/arm64/rockchip/px30-engicam-common.dtsi | 3 +- src/arm64/rockchip/px30-engicam-ctouch2.dtsi | 2 +- .../rockchip/px30-engicam-px30-core-edimm2.2.dts | 2 +- .../px30-ringneck-haikou-lvds-9904379.dtso | 130 ++ .../rockchip/px30-ringneck-haikou-video-demo.dtso | 190 +++ src/arm64/rockchip/px30-ringneck-haikou.dts | 2 + src/arm64/rockchip/px30-ringneck.dtsi | 4 - src/arm64/rockchip/rk3308-roc-cc.dts | 2 +- src/arm64/rockchip/rk3318-a95x-z2.dts | 4 +- src/arm64/rockchip/rk3328-rock-pi-e.dts | 8 + src/arm64/rockchip/rk3399-nanopi4.dtsi | 2 +- .../rockchip/rk3399-puma-haikou-video-demo.dtso | 166 +++ src/arm64/rockchip/rk3399-puma-haikou.dts | 26 +- src/arm64/rockchip/rk3399-puma.dtsi | 10 +- src/arm64/rockchip/rk3399-roc-pc-plus.dts | 2 +- src/arm64/rockchip/rk3399-rock-pi-4.dtsi | 2 +- src/arm64/rockchip/rk3528-pinctrl.dtsi | 1397 ++++++++++++++++++++ src/arm64/rockchip/rk3528-radxa-e20c.dts | 133 ++ src/arm64/rockchip/rk3528.dtsi | 378 +++++- src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi | 2 +- src/arm64/rockchip/rk3566-pinenote.dtsi | 2 + src/arm64/rockchip/rk3566-quartz64-a.dts | 8 +- src/arm64/rockchip/rk3566-quartz64-b.dts | 8 +- src/arm64/rockchip/rk3568-photonicat.dts | 588 ++++++++ src/arm64/rockchip/rk3568-qnap-ts433.dts | 2 + src/arm64/rockchip/rk3568-rock-3a.dts | 14 - src/arm64/rockchip/rk356x-base.dtsi | 44 +- src/arm64/rockchip/rk3576-armsom-sige5.dts | 52 +- src/arm64/rockchip/rk3576-evb1-v10.dts | 47 + src/arm64/rockchip/rk3576-roc-pc.dts | 736 +++++++++++ src/arm64/rockchip/rk3576-rock-4d.dts | 751 +++++++++++ src/arm64/rockchip/rk3576.dtsi | 229 +++- src/arm64/rockchip/rk3588-armsom-lm7.dtsi | 4 + src/arm64/rockchip/rk3588-armsom-sige7.dts | 75 ++ src/arm64/rockchip/rk3588-base.dtsi | 110 +- src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts | 2 +- src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts | 2 +- src/arm64/rockchip/rk3588-coolpi-cm5.dtsi | 4 + .../rockchip/rk3588-edgeble-neu6a-common.dtsi | 4 + src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi | 47 + src/arm64/rockchip/rk3588-evb1-v10.dts | 50 +- src/arm64/rockchip/rk3588-extra.dtsi | 186 +++ src/arm64/rockchip/rk3588-fet3588-c.dtsi | 4 + src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi | 4 + src/arm64/rockchip/rk3588-firefly-icore-3588q.dtsi | 443 +++++++ src/arm64/rockchip/rk3588-firefly-itx-3588j.dts | 2 +- .../rockchip/rk3588-friendlyelec-cm3588-nas.dts | 2 +- src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi | 8 + src/arm64/rockchip/rk3588-h96-max-v58.dts | 30 +- .../rockchip/rk3588-jaguar-pre-ict-tester.dtso | 171 +++ src/arm64/rockchip/rk3588-jaguar.dts | 224 +++- src/arm64/rockchip/rk3588-mnt-reform2.dts | 336 +++++ src/arm64/rockchip/rk3588-nanopc-t6.dtsi | 6 +- src/arm64/rockchip/rk3588-ok3588-c.dts | 4 + src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi | 11 +- src/arm64/rockchip/rk3588-orangepi-5-max.dts | 67 +- src/arm64/rockchip/rk3588-orangepi-5-plus.dts | 56 +- src/arm64/rockchip/rk3588-orangepi-5-ultra.dts | 83 ++ src/arm64/rockchip/rk3588-orangepi-5.dtsi | 6 +- src/arm64/rockchip/rk3588-quartzpro64.dts | 6 +- src/arm64/rockchip/rk3588-rock-5-itx.dts | 53 + src/arm64/rockchip/rk3588-rock-5b.dts | 83 +- src/arm64/rockchip/rk3588-tiger-haikou.dts | 4 +- src/arm64/rockchip/rk3588-tiger.dtsi | 5 +- src/arm64/rockchip/rk3588-toybrick-x0.dts | 4 + src/arm64/rockchip/rk3588-turing-rk1.dtsi | 6 + src/arm64/rockchip/rk3588j.dtsi | 53 +- src/arm64/rockchip/rk3588s-coolpi-4b.dts | 31 +- src/arm64/rockchip/rk3588s-evb1-v10.dts | 6 +- src/arm64/rockchip/rk3588s-gameforce-ace.dts | 6 +- src/arm64/rockchip/rk3588s-indiedroid-nova.dts | 8 +- src/arm64/rockchip/rk3588s-khadas-edge2.dts | 4 + src/arm64/rockchip/rk3588s-nanopi-r6.dtsi | 6 +- src/arm64/rockchip/rk3588s-odroid-m2.dts | 6 +- src/arm64/rockchip/rk3588s-orangepi-5.dtsi | 16 +- src/arm64/rockchip/rk3588s-rock-5a.dts | 6 +- src/arm64/rockchip/rk3588s-rock-5c.dts | 42 +- src/arm64/st/stm32mp211.dtsi | 128 ++ src/arm64/st/stm32mp213.dtsi | 9 + src/arm64/st/stm32mp215.dtsi | 9 + src/arm64/st/stm32mp215f-dk.dts | 49 + src/arm64/st/stm32mp21xc.dtsi | 8 + src/arm64/st/stm32mp21xf.dtsi | 8 + src/arm64/st/stm32mp231.dtsi | 1213 +++++++++++++++++ src/arm64/st/stm32mp233.dtsi | 94 ++ src/arm64/st/stm32mp235.dtsi | 16 + src/arm64/st/stm32mp235f-dk.dts | 113 ++ src/arm64/st/stm32mp23xc.dtsi | 8 + src/arm64/st/stm32mp23xf.dtsi | 8 + src/arm64/st/stm32mp251.dtsi | 9 +- src/arm64/st/stm32mp257f-dk.dts | 113 ++ src/arm64/tesla/fsd.dtsi | 26 +- src/arm64/ti/k3-am62-phycore-som.dtsi | 25 +- src/arm64/ti/k3-am62-verdin-dahlia.dtsi | 6 +- src/arm64/ti/k3-am625-beagleplay.dts | 8 + src/arm64/ti/k3-am62a-mcu.dtsi | 1 - src/arm64/ti/k3-am62a-phycore-som.dtsi | 19 +- src/arm64/ti/k3-am62a7-sk.dts | 4 + src/arm64/ti/k3-am62p-j722s-common-mcu.dtsi | 8 - src/arm64/ti/k3-am62p-j722s-common-wakeup.dtsi | 36 +- src/arm64/ti/k3-am62p-main.dtsi | 26 +- src/arm64/ti/k3-am62p5-sk.dts | 4 +- src/arm64/ti/k3-am62x-phyboard-lyra.dtsi | 9 + src/arm64/ti/k3-am62x-sk-common.dtsi | 2 + src/arm64/ti/k3-am64-phycore-som.dtsi | 33 +- src/arm64/ti/k3-am642-phyboard-electra-rdk.dts | 19 +- ...m642-phyboard-electra-x27-gpio1-spi1-uart3.dtso | 63 + src/arm64/ti/k3-j721e-common-proc-board.dts | 1 + src/arm64/ti/k3-j721e-sk.dts | 1 + src/arm64/ti/k3-j721s2-som-p0.dtsi | 41 + src/arm64/ti/k3-j722s-evm.dts | 30 +- src/arm64/ti/k3-j722s-main.dtsi | 208 ++- src/arm64/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso | 7 - src/arm64/ti/k3-j784s4-j742s2-main-common.dtsi | 6 +- src/arm64/xilinx/versal-net-clk.dtsi | 231 ++++ src/arm64/xilinx/versal-net-vn-x-b2197-01-revA.dts | 116 ++ src/arm64/xilinx/versal-net.dtsi | 752 +++++++++++ src/arm64/xilinx/xlnx-zynqmp-clk.h | 126 ++ src/arm64/xilinx/zynqmp-clk-ccf.dtsi | 17 +- src/loongarch/loongson-2k1000-ref.dts | 5 - src/mips/ingenic/gcw0.dts | 2 +- src/mips/ingenic/rs90.dts | 2 +- src/mips/mobileye/eyeq6h.dtsi | 4 + src/mips/ralink/gardena_smart_gateway_mt7688.dts | 2 +- src/mips/ralink/mt7620a.dtsi | 10 +- src/mips/ralink/mt7620a_eval.dts | 2 +- src/mips/ralink/mt7628a.dtsi | 40 +- src/mips/ralink/omega2p.dts | 2 +- src/mips/ralink/rt2880.dtsi | 10 +- src/mips/ralink/rt2880_eval.dts | 2 +- src/mips/ralink/rt3050.dtsi | 10 +- src/mips/ralink/rt3883.dtsi | 10 +- src/mips/ralink/rt3883_eval.dts | 2 +- src/mips/realtek/cisco_sg220-26.dts | 10 +- src/mips/realtek/rtl838x.dtsi | 111 +- src/mips/realtek/rtl83xx.dtsi | 59 - src/mips/realtek/rtl930x.dtsi | 136 +- src/powerpc/microwatt.dts | 107 +- src/riscv/microchip/mpfs-icicle-kit-fabric.dtsi | 5 +- src/riscv/microchip/mpfs-m100pfs-fabric.dtsi | 5 +- src/riscv/microchip/mpfs-polarberry-fabric.dtsi | 5 +- src/riscv/sophgo/cv18xx.dtsi | 2 +- src/riscv/sophgo/sg2042-milkv-pioneer.dts | 36 + src/riscv/sophgo/sg2042.dtsi | 19 + src/riscv/spacemit/k1-milkv-jupiter.dts | 27 + src/riscv/starfive/jh7110-common.dtsi | 8 +- .../starfive/jh7110-deepcomputing-fml13v01.dts | 34 + src/riscv/starfive/jh7110-pine64-star64.dts | 5 + src/riscv/starfive/jh7110.dtsi | 4 +- 1095 files changed, 51463 insertions(+), 5916 deletions(-) create mode 100644 Bindings/arm/arm,morello.yaml delete mode 100644 Bindings/arm/marvell/armada-8kp.txt create mode 100644 Bindings/arm/qcom,coresight-ctcu.yaml create mode 100644 Bindings/ata/fsl,pq-sata.yaml delete mode 100644 Bindings/ata/fsl-sata.txt delete mode 100644 Bindings/bus/qcom,ebi2.yaml create mode 100644 Bindings/clock/allwinner,sun55i-a523-ccu.yaml create mode 100644 Bindings/clock/qcom,ipq9574-nsscc.yaml create mode 100644 Bindings/clock/rockchip,rk3528-cru.yaml create mode 100644 Bindings/clock/rockchip,rk3562-cru.yaml create mode 100644 Bindings/clock/samsung,exynos2200-cmu.yaml create mode 100644 Bindings/clock/samsung,exynos7870-cmu.yaml create mode 100644 Bindings/clock/ti,clkctrl.yaml delete mode 100644 Bindings/clock/ti-clkctrl.txt create mode 100644 Bindings/connector/gocontroll,moduline-module-slot.yaml create mode 100644 Bindings/crypto/fsl,sec2.0.yaml delete mode 100644 Bindings/crypto/fsl-sec2.txt create mode 100644 Bindings/crypto/inside-secure,safexcel-eip93.yaml create mode 100644 Bindings/display/apple,h7-display-pipe-mipi.yaml create mode 100644 Bindings/display/apple,h7-display-pipe.yaml create mode 100644 Bindings/display/panel/apple,summit.yaml create mode 100644 Bindings/display/panel/raydium,rm67200.yaml create mode 100644 Bindings/display/panel/visionox,rm692e5.yaml create mode 100644 Bindings/dma/atmel,at91sam9g45-dma.yaml delete mode 100644 Bindings/dma/atmel-dma.txt create mode 100644 Bindings/dma/fsl,elo-dma.yaml create mode 100644 Bindings/dma/fsl,elo3-dma.yaml create mode 100644 Bindings/dma/fsl,eloplus-dma.yaml create mode 100644 Bindings/edac/altr,socfpga-ecc-manager.yaml delete mode 100644 Bindings/edac/socfpga-eccmgr.txt create mode 100644 Bindings/firmware/google,gs101-acpm-ipc.yaml create mode 100644 Bindings/firmware/thead,th1520-aon.yaml create mode 100644 Bindings/hwmon/microchip,emc2305.yaml create mode 100644 Bindings/i2c/spacemit,k1-i2c.yaml create mode 100644 Bindings/iio/adc/adi,ad4030.yaml create mode 100644 Bindings/iio/adc/adi,ad4851.yaml create mode 100644 Bindings/iio/adc/adi,ad7191.yaml create mode 100644 Bindings/iio/adc/ti,ads7138.yaml create mode 100644 Bindings/iio/imu/adi,adis16550.yaml create mode 100644 Bindings/iio/light/brcm,apds9160.yaml create mode 100644 Bindings/iio/magnetometer/silabs,si7210.yaml delete mode 100644 Bindings/input/gpio-matrix-keypad.txt create mode 100644 Bindings/input/gpio-matrix-keypad.yaml create mode 100644 Bindings/input/touchscreen/apple,z2-multitouch.yaml create mode 100644 Bindings/interrupt-controller/brcm,bcm2712-msix.yaml delete mode 100644 Bindings/interrupt-controller/nxp,lpc3220-mic.txt create mode 100644 Bindings/interrupt-controller/nxp,lpc3220-mic.yaml create mode 100644 Bindings/interrupt-controller/sophgo,sg2042-msi.yaml create mode 100644 Bindings/leds/backlight/apple,dwi-bl.yaml delete mode 100644 Bindings/leds/leds-tlc591xx.txt create mode 100644 Bindings/leds/ti,tlc59116.yaml create mode 100644 Bindings/media/aspeed,video-engine.yaml delete mode 100644 Bindings/media/aspeed-video.txt create mode 100644 Bindings/media/qcom,sdm670-camss.yaml create mode 100644 Bindings/media/qcom,sm8550-camss.yaml create mode 100644 Bindings/media/qcom,sm8550-iris.yaml create mode 100644 Bindings/media/snps,dw-hdmi-rx.yaml create mode 100644 Bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml create mode 100644 Bindings/memory-controllers/qcom,ebi2.yaml create mode 100644 Bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml create mode 100644 Bindings/mfd/fsl,mcu-mpc8349emitx.yaml create mode 100644 Bindings/mfd/maxim,max77705.yaml delete mode 100644 Bindings/mfd/realtek,rtl9301-switch.yaml create mode 100644 Bindings/mips/mti,mips-cm.yaml delete mode 100644 Bindings/misc/atmel-ssc.txt create mode 100644 Bindings/mmc/atmel,hsmci.yaml delete mode 100644 Bindings/mmc/atmel-hsmci.txt create mode 100644 Bindings/mtd/atmel,dataflash.yaml delete mode 100644 Bindings/mtd/atmel-dataflash.txt create mode 100644 Bindings/net/airoha,en7581-npu.yaml create mode 100644 Bindings/net/fsl,gianfar-mdio.yaml create mode 100644 Bindings/net/fsl,gianfar.yaml create mode 100644 Bindings/net/realtek,rtl9301-mdio.yaml create mode 100644 Bindings/net/realtek,rtl9301-switch.yaml create mode 100644 Bindings/net/sophgo,sg2044-dwmac.yaml create mode 100644 Bindings/net/tesla,fsd-ethqos.yaml create mode 100644 Bindings/pci/amd,versal2-mdb-host.yaml create mode 100644 Bindings/pci/fsl,mpc8xxx-pci.yaml delete mode 100644 Bindings/pci/fsl,pci.txt create mode 100644 Bindings/pci/pci-ep-bus.yaml create mode 100644 Bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml create mode 100644 Bindings/phy/rockchip,rk3588-mipi-dcphy.yaml create mode 100644 Bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml create mode 100644 Bindings/pinctrl/amlogic,pinctrl-a4.yaml create mode 100644 Bindings/pinctrl/brcm,bcm21664-pinctrl.yaml create mode 100644 Bindings/pinctrl/sophgo,sg2042-pinctrl.yaml create mode 100644 Bindings/platform/huawei,gaokun-ec.yaml create mode 100644 Bindings/power/supply/maxim,max77705.yaml delete mode 100644 Bindings/powerpc/fsl/dma.txt delete mode 100644 Bindings/powerpc/fsl/mcu-mpc8349emitx.txt create mode 100644 Bindings/pwm/pwm-nexus-node.yaml create mode 100644 Bindings/pwm/sophgo,sg2042-pwm.yaml create mode 100644 Bindings/regulator/samsung,s2mpu05.yaml delete mode 100644 Bindings/remoteproc/qcom,sc8180x-pas.yaml create mode 100644 Bindings/rng/rockchip,rk3588-rng.yaml create mode 100644 Bindings/serial/nvidia,tegra264-utc.yaml create mode 100644 Bindings/sound/atmel,at91-ssc.yaml create mode 100644 Bindings/sound/atmel,at91sam9g20ek-wm8731.yaml delete mode 100644 Bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt create mode 100644 Bindings/sound/fsl,imx95-cm7-sof.yaml create mode 100644 Bindings/sound/fsl,sof-cpu.yaml delete mode 100644 Bindings/sound/ics43432.txt create mode 100644 Bindings/sound/invensense,ics43432.yaml delete mode 100644 Bindings/sound/xlnx,audio-formatter.txt create mode 100644 Bindings/sound/xlnx,audio-formatter.yaml delete mode 100644 Bindings/sound/xlnx,i2s.txt create mode 100644 Bindings/sound/xlnx,i2s.yaml delete mode 100644 Bindings/sound/xlnx,spdif.txt create mode 100644 Bindings/sound/xlnx,spdif.yaml create mode 100644 Bindings/spi/fsl,espi.yaml create mode 100644 Bindings/spi/fsl,spi.yaml delete mode 100644 Bindings/spi/fsl-spi.txt create mode 100644 Bindings/spi/qcom,spi-qpic-snand.yaml create mode 100644 Bindings/spi/spi-sg2044-nor.yaml create mode 100644 Bindings/spi/st,stm32mp25-ospi.yaml delete mode 100644 Bindings/timer/renesas,tpu.yaml create mode 100644 Bindings/trigger-source/pwm-trigger.yaml create mode 100644 Bindings/ufs/rockchip,rk3576-ufshc.yaml create mode 100644 Bindings/usb/parade,ps8830.yaml create mode 100644 include/dt-bindings/clock/mediatek,mtmips-sysc.h create mode 100644 include/dt-bindings/clock/qcom,dsi-phy-28nm.h create mode 100644 include/dt-bindings/clock/qcom,ipq9574-nsscc.h create mode 100644 include/dt-bindings/clock/rockchip,rk3528-cru.h create mode 100644 include/dt-bindings/clock/rockchip,rk3562-cru.h create mode 100644 include/dt-bindings/clock/samsung,exynos2200-cmu.h create mode 100644 include/dt-bindings/clock/samsung,exynos7870-cmu.h create mode 100644 include/dt-bindings/clock/sun55i-a523-ccu.h create mode 100644 include/dt-bindings/clock/sun55i-a523-r-ccu.h create mode 100644 include/dt-bindings/pinctrl/amlogic,pinctrl.h create mode 100644 include/dt-bindings/pinctrl/pinctrl-sg2042.h create mode 100644 include/dt-bindings/pinctrl/pinctrl-sg2044.h create mode 100644 include/dt-bindings/power/allwinner,sun8i-v853-ppu.h create mode 100644 include/dt-bindings/power/thead,th1520-power.h create mode 100644 include/dt-bindings/reset/imx8mp-reset-audiomix.h create mode 100644 include/dt-bindings/reset/qcom,ipq9574-nsscc.h create mode 100644 include/dt-bindings/reset/rockchip,rk3528-cru.h create mode 100644 include/dt-bindings/reset/rockchip,rk3562-cru.h create mode 100644 include/dt-bindings/reset/sun55i-a523-ccu.h create mode 100644 include/dt-bindings/reset/sun55i-a523-r-ccu.h create mode 100644 include/dt-bindings/sound/qcom,wcd934x.h create mode 100644 src/arm/allwinner/sun8i-v3s-netcube-kumquat.dts create mode 100644 src/arm/nxp/imx/imx6dl-colibri-v1.2-aster.dts create mode 100644 src/arm/nxp/imx/imx6dl-colibri-v1.2-eval-v3.dts create mode 100644 src/arm/nxp/imx/imx6dl-colibri-v1.2-iris-v2.dts create mode 100644 src/arm/nxp/imx/imx6dl-colibri-v1.2-iris.dts create mode 100644 src/arm/nxp/imx/imx6q-apalis-v1.2-eval-v1.2.dts create mode 100644 src/arm/nxp/imx/imx6q-apalis-v1.2-eval.dts create mode 100644 src/arm/nxp/imx/imx6q-apalis-v1.2-ixora-v1.1.dts create mode 100644 src/arm/nxp/imx/imx6q-apalis-v1.2-ixora-v1.2.dts create mode 100644 src/arm/nxp/imx/imx6q-apalis-v1.2-ixora.dts create mode 100644 src/arm/nxp/imx/imx6qdl-apalis-v1.2.dtsi create mode 100644 src/arm/nxp/imx/imx6qdl-colibri-v1.2.dtsi create mode 100644 src/arm/nxp/imx/imx6ul-var-som-concerto.dts create mode 100644 src/arm/nxp/imx/imx6ul-var-som.dtsi create mode 100644 src/arm/nxp/mxs/imx28-btt3-0.dts create mode 100644 src/arm/nxp/mxs/imx28-btt3-1.dts create mode 100644 src/arm/nxp/mxs/imx28-btt3-2.dts create mode 100644 src/arm/nxp/mxs/imx28-btt3.dtsi create mode 100644 src/arm/st/stm32mp133c-prihmb.dts create mode 100644 src/arm/st/stm32mp151c-plyaqm.dts create mode 100644 src/arm/st/stm32mp153c-lxa-fairytux2-gen1.dts create mode 100644 src/arm/st/stm32mp153c-lxa-fairytux2-gen2.dts create mode 100644 src/arm/st/stm32mp153c-lxa-fairytux2.dtsi create mode 100644 src/arm64/allwinner/sun50i-a100-cpu-opp.dtsi create mode 100644 src/arm64/apple/s5l8960x-opp.dtsi create mode 100644 src/arm64/apple/s5l8960x-pmgr.dtsi create mode 100644 src/arm64/apple/s5l8965x-opp.dtsi create mode 100644 src/arm64/apple/s800-0-3-pmgr.dtsi create mode 100644 src/arm64/apple/s800-0-3.dtsi create mode 100644 src/arm64/apple/s8001-j98a-j99a.dtsi create mode 100644 src/arm64/apple/s8001-pmgr.dtsi create mode 100644 src/arm64/apple/spi1-nvram.dtsi create mode 100644 src/arm64/apple/t7000-pmgr.dtsi create mode 100644 src/arm64/apple/t7001-pmgr.dtsi create mode 100644 src/arm64/apple/t8010-pmgr.dtsi create mode 100644 src/arm64/apple/t8011-pmgr.dtsi create mode 100644 src/arm64/apple/t8012-j132.dts create mode 100644 src/arm64/apple/t8012-j137.dts create mode 100644 src/arm64/apple/t8012-j140a.dts create mode 100644 src/arm64/apple/t8012-j140k.dts create mode 100644 src/arm64/apple/t8012-j152f.dts create mode 100644 src/arm64/apple/t8012-j160.dts create mode 100644 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src/arm64/exynos/google/gs101-raven.dts create mode 100644 src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10.dtso create mode 100644 src/arm64/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso create mode 100644 src/arm64/freescale/imx8mm-phycore-no-eth.dtso create mode 100644 src/arm64/freescale/imx8mm-phycore-no-spiflash.dtso create mode 100644 src/arm64/freescale/imx8mm-phycore-rpmsg.dtso create mode 100644 src/arm64/freescale/imx8mp-nominal.dtsi create mode 100644 src/arm64/freescale/imx8mp-skov-basic.dts create mode 100644 src/arm64/freescale/imx8mp-skov-revc-bd500.dts create mode 100644 src/arm64/freescale/imx8mp-skov-revc-tian-g07017.dts create mode 100644 src/arm64/freescale/imx8qxp-mek-pcie-ep.dtso create mode 100644 src/arm64/freescale/imx95-15x15-evk.dts create mode 100644 src/arm64/freescale/s32gxxxa-evb.dtsi create mode 100644 src/arm64/freescale/s32gxxxa-rdb.dtsi delete mode 100644 src/arm64/marvell/armada-371x.dtsi create mode 100644 src/arm64/mediatek/mt8370-genio-510-evk.dts create mode 100644 src/arm64/mediatek/mt8370.dtsi create mode 100644 src/arm64/mediatek/mt8390-genio-common.dtsi create mode 100644 src/arm64/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso create mode 100644 src/arm64/renesas/r9a07g044l2-remi-pi.dts create mode 100644 src/arm64/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso create mode 100644 src/arm64/renesas/r9a09g057h48-kakip.dts create mode 100644 src/arm64/renesas/rzg3s-smarc-switches.h create mode 100644 src/arm64/rockchip/px30-ringneck-haikou-lvds-9904379.dtso create mode 100644 src/arm64/rockchip/px30-ringneck-haikou-video-demo.dtso create mode 100644 src/arm64/rockchip/rk3399-puma-haikou-video-demo.dtso create mode 100644 src/arm64/rockchip/rk3528-pinctrl.dtsi create mode 100644 src/arm64/rockchip/rk3568-photonicat.dts create mode 100644 src/arm64/rockchip/rk3576-roc-pc.dts create mode 100644 src/arm64/rockchip/rk3576-rock-4d.dts create mode 100644 src/arm64/rockchip/rk3588-firefly-icore-3588q.dtsi create mode 100644 src/arm64/rockchip/rk3588-jaguar-pre-ict-tester.dtso create mode 100644 src/arm64/rockchip/rk3588-mnt-reform2.dts create mode 100644 src/arm64/rockchip/rk3588-orangepi-5-ultra.dts create mode 100644 src/arm64/st/stm32mp211.dtsi create mode 100644 src/arm64/st/stm32mp213.dtsi create mode 100644 src/arm64/st/stm32mp215.dtsi create mode 100644 src/arm64/st/stm32mp215f-dk.dts create mode 100644 src/arm64/st/stm32mp21xc.dtsi create mode 100644 src/arm64/st/stm32mp21xf.dtsi create mode 100644 src/arm64/st/stm32mp231.dtsi create mode 100644 src/arm64/st/stm32mp233.dtsi create mode 100644 src/arm64/st/stm32mp235.dtsi create mode 100644 src/arm64/st/stm32mp235f-dk.dts create mode 100644 src/arm64/st/stm32mp23xc.dtsi create mode 100644 src/arm64/st/stm32mp23xf.dtsi create mode 100644 src/arm64/st/stm32mp257f-dk.dts create mode 100644 src/arm64/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso create mode 100644 src/arm64/xilinx/versal-net-clk.dtsi create mode 100644 src/arm64/xilinx/versal-net-vn-x-b2197-01-revA.dts create mode 100644 src/arm64/xilinx/versal-net.dtsi create mode 100644 src/arm64/xilinx/xlnx-zynqmp-clk.h delete mode 100644 src/mips/realtek/rtl83xx.dtsi create mode 100644 src/riscv/spacemit/k1-milkv-jupiter.dts (limited to 'include') diff --git a/Bindings/arm/apple.yaml b/Bindings/arm/apple.yaml index dc9aab19ff1..da60e9de1cf 100644 --- a/Bindings/arm/apple.yaml +++ b/Bindings/arm/apple.yaml @@ -57,6 +57,25 @@ description: | - iPad Pro (2nd Generation) (10.5 Inch) - iPad Pro (2nd Generation) (12.9 Inch) + Devices based on the "T2" SoC: + + - Apple T2 MacBookPro15,2 (j132) + - Apple T2 iMacPro1,1 (j137) + - Apple T2 MacBookAir8,2 (j140a) + - Apple T2 MacBookAir8,1 (j140k) + - Apple T2 MacBookPro16,1 (j152f) + - Apple T2 MacPro7,1 (j160) + - Apple T2 Macmini8,1 (j174) + - Apple T2 iMac20,1 (j185) + - Apple T2 iMac20,2 (j185f) + - Apple T2 MacBookPro15,4 (j213) + - Apple T2 MacBookPro16,2 (j214k) + - Apple T2 MacBookPro16,4 (j215) + - Apple T2 MacBookPro16,3 (j223) + - Apple T2 MacBookAir9,1 (j230k) + - Apple T2 MacBookPro15,1 (j680) + - Apple T2 MacBookPro15,3 (j780) + Devices based on the "A11" SoC: - iPhone 8 @@ -211,6 +230,28 @@ properties: - const: apple,t8011 - const: apple,arm-platform + - description: Apple T2 SoC based platforms + items: + - enum: + - apple,j132 # Apple T2 MacBookPro15,2 (j132) + - apple,j137 # Apple T2 iMacPro1,1 (j137) + - apple,j140a # Apple T2 MacBookAir8,2 (j140a) + - apple,j140k # Apple T2 MacBookAir8,1 (j140k) + - apple,j152f # Apple T2 MacBookPro16,1 (j152f) + - apple,j160 # Apple T2 MacPro7,1 (j160) + - apple,j174 # Apple T2 Macmini8,1 (j174) + - apple,j185 # Apple T2 iMac20,1 (j185) + - apple,j185f # Apple T2 iMac20,2 (j185f) + - apple,j213 # Apple T2 MacBookPro15,4 (j213) + - apple,j214k # Apple T2 MacBookPro16,2 (j214k) + - apple,j215 # Apple T2 MacBookPro16,4 (j215) + - apple,j223 # Apple T2 MacBookPro16,3 (j223) + - apple,j230k # Apple T2 MacBookAir9,1 (j230k) + - apple,j680 # Apple T2 MacBookPro15,1 (j680) + - apple,j780 # Apple T2 MacBookPro15,3 (j780) + - const: apple,t8012 + - const: apple,arm-platform + - description: Apple A11 SoC based platforms items: - enum: diff --git a/Bindings/arm/apple/apple,pmgr.yaml b/Bindings/arm/apple/apple,pmgr.yaml index 673277a7a22..5001f4d5a0d 100644 --- a/Bindings/arm/apple/apple,pmgr.yaml +++ b/Bindings/arm/apple/apple,pmgr.yaml @@ -22,6 +22,11 @@ properties: compatible: items: - enum: + - apple,s5l8960x-pmgr + - apple,t7000-pmgr + - apple,s8000-pmgr + - apple,t8010-pmgr + - apple,t8015-pmgr - apple,t8103-pmgr - apple,t8112-pmgr - apple,t6000-pmgr diff --git a/Bindings/arm/arm,coresight-tmc.yaml b/Bindings/arm/arm,coresight-tmc.yaml index cb8dceaca70..4787d7c6bac 100644 --- a/Bindings/arm/arm,coresight-tmc.yaml +++ b/Bindings/arm/arm,coresight-tmc.yaml @@ -101,6 +101,29 @@ properties: and ETF configurations. $ref: /schemas/graph.yaml#/properties/port + memory-region: + items: + - description: Reserved trace buffer memory for ETR and ETF sinks. + For ETR, this reserved memory region is used for trace data capture. + Same region is used for trace data retention as well after a panic + or watchdog reset. + This reserved memory region is used as trace buffer or used for trace + data retention only if specifically selected by the user in sysfs + interface. + The default memory usage models for ETR in sysfs/perf modes are + otherwise unaltered. + + For ETF, this reserved memory region is used by default for + retention of trace data synced from internal SRAM after a panic + or watchdog reset. + - description: Reserved meta data memory. Used for ETR and ETF sinks + for storing metadata. + + memory-region-names: + items: + - const: tracedata + - const: metadata + required: - compatible - reg @@ -115,6 +138,9 @@ examples: etr@20070000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x20070000 0x1000>; + memory-region = <&etr_trace_mem_reserved>, + <&etr_mdata_mem_reserved>; + memory-region-names = "tracedata", "metadata"; clocks = <&oscclk6a>; clock-names = "apb_pclk"; diff --git a/Bindings/arm/arm,morello.yaml b/Bindings/arm/arm,morello.yaml new file mode 100644 index 00000000000..e843b97fa48 --- /dev/null +++ b/Bindings/arm/arm,morello.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,morello.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Morello Platforms + +maintainers: + - Vincenzo Frascino + +description: |+ + The Morello architecture is an experimental extension to Armv8.2-A, + which extends the AArch64 state with the principles proposed in + version 7 of the Capability Hardware Enhanced RISC Instructions + (CHERI) ISA. + + ARM's Morello Platforms are built as a research project to explore + capability architectures based on arm. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Arm Morello System Platforms + items: + - enum: + - arm,morello-sdp + - arm,morello-fvp + - const: arm,morello + +additionalProperties: true + +... diff --git a/Bindings/arm/atmel-at91.yaml b/Bindings/arm/atmel-at91.yaml index 0ec29366e6c..3a34b7a2e8d 100644 --- a/Bindings/arm/atmel-at91.yaml +++ b/Bindings/arm/atmel-at91.yaml @@ -22,8 +22,6 @@ properties: - items: - const: atmel,at91rm9200 - items: - - enum: - - olimex,sam9-l9260 - enum: - atmel,at91sam9260 - atmel,at91sam9261 @@ -36,6 +34,37 @@ properties: - atmel,at91sam9x60 - const: atmel,at91sam9 + - description: Olimex SAM9-L9260 + items: + - const: olimex,sam9-l9260 + - const: atmel,at91sam9260 + - const: atmel,at91sam9 + + - description: Calao USB A9260 + items: + - const: calao,usb-a9260 + - const: atmel,at91sam9260 + - const: atmel,at91sam9 + + - description: Calao USB A9263 + items: + - const: calao,usb-a9263 + - const: atmel,at91sam9263 + - const: atmel,at91sam9 + + - description: Calao USB A9G20 + items: + - const: calao,usb-a9g20 + - const: atmel,at91sam9g20 + - const: atmel,at91sam9 + + - description: Calao USB A9G20-LPW + items: + - const: calao,usb-a9g20-lpw + - const: calao,usb-a9g20 + - const: atmel,at91sam9g20 + - const: atmel,at91sam9 + - items: - enum: - overkiz,kizboxmini-base # Overkiz kizbox Mini Base Board diff --git a/Bindings/arm/atmel-sysregs.txt b/Bindings/arm/atmel-sysregs.txt index 1a173e92bb1..d3821f651e7 100644 --- a/Bindings/arm/atmel-sysregs.txt +++ b/Bindings/arm/atmel-sysregs.txt @@ -2,6 +2,7 @@ Atmel system registers Chipid required properties: - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" + "microchip,sama7d65-chipid" - reg : Should contain registers location and length PIT Timer required properties: diff --git a/Bindings/arm/cpus.yaml b/Bindings/arm/cpus.yaml index 73dd73d2d4f..2e666b2a4dc 100644 --- a/Bindings/arm/cpus.yaml +++ b/Bindings/arm/cpus.yaml @@ -177,6 +177,7 @@ properties: - arm,neoverse-v2 - arm,neoverse-v3 - arm,neoverse-v3ae + - arm,rainier - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan diff --git a/Bindings/arm/fsl.yaml b/Bindings/arm/fsl.yaml index 0db2cbd7891..1b90870958a 100644 --- a/Bindings/arm/fsl.yaml +++ b/Bindings/arm/fsl.yaml @@ -97,6 +97,7 @@ properties: - i2se,duckbill - i2se,duckbill-2 - karo,tx28 # Ka-Ro electronics TX28 module + - lwn,imx28-btt3 - lwn,imx28-xea - msr,m28cu3 # M28 SoM with custom base board - schulercontrol,imx28-sps1 @@ -296,7 +297,6 @@ properties: - technexion,imx6q-pico-pi # TechNexion i.MX6Q Pico-Pi - technologic,imx6q-ts4900 - technologic,imx6q-ts7970 - - toradex,apalis_imx6q # Apalis iMX6 Modules - udoo,imx6q-udoo # Udoo i.MX6 Quad Board - uniwest,imx6q-evi # Uniwest Evi - variscite,dt6customboard @@ -490,7 +490,6 @@ properties: - technexion,imx6dl-pico-pi # TechNexion i.MX6DL Pico-Pi - technologic,imx6dl-ts4900 - technologic,imx6dl-ts7970 - - toradex,colibri_imx6dl # Colibri iMX6 Modules - udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board - vdl,lanmcu # Van der Laan LANMCU board - wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board @@ -688,6 +687,12 @@ properties: - const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL - const: fsl,imx6ul + - description: i.MX6UL Variscite VAR-SOM-MX6 Boards + items: + - const: variscite,mx6ulconcerto + - const: variscite,var-som-imx6ul + - const: fsl,imx6ul + - description: Kontron BL i.MX6UL (N631X S) Board items: - const: kontron,bl-imx6ul # Kontron BL i.MX6UL Carrier Board @@ -730,9 +735,6 @@ properties: - joz,jozacp # JOZ Access Point - kontron,sl-imx6ull # Kontron SL i.MX6ULL SoM - myir,imx6ull-mys-6ulx-eval # MYiR Tech iMX6ULL Evaluation Board - - toradex,colibri-imx6ull # Colibri iMX6ULL Modules - - toradex,colibri-imx6ull-emmc # Colibri iMX6ULL 1GB (eMMC) Module - - toradex,colibri-imx6ull-wifi # Colibri iMX6ULL Wi-Fi / BT Modules - uni-t,uti260b # UNI-T UTi260B Thermal Camera - const: fsl,imx6ull @@ -891,8 +893,6 @@ properties: - technexion,imx7d-pico-hobbit # TechNexion i.MX7D Pico-Hobbit - technexion,imx7d-pico-nymph # TechNexion i.MX7D Pico-Nymph - technexion,imx7d-pico-pi # TechNexion i.MX7D Pico-Pi - - toradex,colibri-imx7d # Colibri iMX7D Module - - toradex,colibri-imx7d-emmc # Colibri iMX7D 1GB (eMMC) Module - zii,imx7d-rmu2 # ZII RMU2 Board - zii,imx7d-rpu2 # ZII RPU2 Board - const: fsl,imx7d @@ -962,9 +962,6 @@ properties: - innocomm,wb15-evk # i.MX8MM Innocomm EVK board with WB15 SoM - kontron,imx8mm-sl # i.MX8MM Kontron SL (N801X) SOM - kontron,imx8mm-osm-s # i.MX8MM Kontron OSM-S (N802X) SOM - - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules - - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT - - toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules - prt,prt8mm # i.MX8MM Protonic PRT8MM Board - const: fsl,imx8mm @@ -1098,12 +1095,12 @@ properties: - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board - gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board - gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board + - skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate - skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel - skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel - skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel - - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules - - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT - - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules + - skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control with LED frontplate + - skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate control with 7" panel - ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board - const: fsl,imx8mp @@ -1273,8 +1270,6 @@ properties: - enum: - fsl,imx8qm-mek # i.MX8QM MEK Board - fsl,imx8qm-mek-revd # i.MX8QM MEK Rev D Board - - toradex,apalis-imx8 # Apalis iMX8 Modules - - toradex,apalis-imx8-v1.1 # Apalis iMX8 V1.1 Modules - const: fsl,imx8qm - description: i.MX8QM Boards with Toradex Apalis iMX8 Modules @@ -1355,6 +1350,7 @@ properties: - description: i.MX95 based Boards items: - enum: + - fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board - const: fsl,imx95 @@ -1435,7 +1431,6 @@ properties: - fsl,vf610-twr # VF610 Tower Board - lwn,bk4 # Liebherr BK4 controller - phytec,vf610-cosmic # PHYTEC Cosmic/Cosmic+ Board - - toradex,vf610-colibri_vf61 # Colibri VF61 Modules - const: fsl,vf610 - description: Toradex Colibri VF61 Module on Colibri Evaluation Board diff --git a/Bindings/arm/google.yaml b/Bindings/arm/google.yaml index e20b5c9b16b..99961e5282e 100644 --- a/Bindings/arm/google.yaml +++ b/Bindings/arm/google.yaml @@ -34,10 +34,11 @@ properties: const: '/' compatible: oneOf: - - description: Google Pixel 6 / Oriole + - description: Google Pixel 6 or 6 Pro (Oriole or Raven) items: - enum: - google,gs101-oriole + - google,gs101-raven - const: google,gs101 # Bootloader requires empty ect node to be present diff --git a/Bindings/arm/marvell/armada-37xx.yaml b/Bindings/arm/marvell/armada-37xx.yaml index 6905d29f310..51e1386f0e0 100644 --- a/Bindings/arm/marvell/armada-37xx.yaml +++ b/Bindings/arm/marvell/armada-37xx.yaml @@ -18,6 +18,7 @@ properties: items: - enum: - cznic,turris-mox + - glinet,gl-mv1000 - globalscale,espressobin - marvell,armada-3720-db - methode,edpu diff --git a/Bindings/arm/marvell/armada-7k-8k.yaml b/Bindings/arm/marvell/armada-7k-8k.yaml index 538d91be885..4bc7454a5d3 100644 --- a/Bindings/arm/marvell/armada-7k-8k.yaml +++ b/Bindings/arm/marvell/armada-7k-8k.yaml @@ -23,6 +23,9 @@ properties: - description: Armada 7040 SoC items: + - enum: + - globalscale,mochabin + - marvell,armada7040-db - const: marvell,armada7040 - const: marvell,armada-ap806-quad - const: marvell,armada-ap806 @@ -35,10 +38,32 @@ properties: - description: Armada 8040 SoC items: + - enum: + - iei,puzzle-m801 + - marvell,armada8040-db + - solidrun,clearfog-gt-8k - const: marvell,armada8040 - const: marvell,armada-ap806-quad - const: marvell,armada-ap806 + - description: Armada 8040 SoC MACCHIATOBin Boards + items: + - enum: + - marvell,armada8040-mcbin-doubleshot + - marvell,armada8040-mcbin-singleshot + - const: marvell,armada8040-mcbin + - const: marvell,armada8040 + - const: marvell,armada-ap806-quad + - const: marvell,armada-ap806 + + - description: Armada 8080 SoC + items: + - enum: + - marvell,armada-8080-db + - const: marvell,armada-8080 + - const: marvell,armada-ap810-octa + - const: marvell,armada-ap810 + - description: Armada CN9130 SoC with no external CP items: - const: marvell,cn9130 diff --git a/Bindings/arm/marvell/armada-8kp.txt b/Bindings/arm/marvell/armada-8kp.txt deleted file mode 100644 index f3e9624534c..00000000000 --- a/Bindings/arm/marvell/armada-8kp.txt +++ /dev/null @@ -1,15 +0,0 @@ -Marvell Armada 8KPlus Platforms Device Tree Bindings ----------------------------------------------------- - -Boards using a SoC of the Marvell Armada 8KP families must carry -the following root node property: - - - compatible, with one of the following values: - - - "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810" - when the SoC being used is the Armada 8080 - -Example: - -compatible = "marvell,armada-8080-db", "marvell,armada-8080", - "marvell,armada-ap810-octa", "marvell,armada-ap810" diff --git a/Bindings/arm/mediatek.yaml b/Bindings/arm/mediatek.yaml index 3ce34d68c21..108ae5e0185 100644 --- a/Bindings/arm/mediatek.yaml +++ b/Bindings/arm/mediatek.yaml @@ -412,6 +412,11 @@ properties: - enum: - mediatek,mt8365-evk - const: mediatek,mt8365 + - items: + - enum: + - mediatek,mt8370-evk + - const: mediatek,mt8370 + - const: mediatek,mt8188 - items: - enum: - mediatek,mt8390-evk diff --git a/Bindings/arm/pmu.yaml b/Bindings/arm/pmu.yaml index a148ff54f2b..295963a3cae 100644 --- a/Bindings/arm/pmu.yaml +++ b/Bindings/arm/pmu.yaml @@ -67,6 +67,7 @@ properties: - arm,neoverse-v2-pmu - arm,neoverse-v3-pmu - arm,neoverse-v3ae-pmu + - arm,rainier-pmu - brcm,vulcan-pmu - cavium,thunder-pmu - nvidia,denver-pmu diff --git a/Bindings/arm/qcom,coresight-ctcu.yaml b/Bindings/arm/qcom,coresight-ctcu.yaml new file mode 100644 index 00000000000..843b52eaf87 --- /dev/null +++ b/Bindings/arm/qcom,coresight-ctcu.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/qcom,coresight-ctcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CoreSight TMC Control Unit + +maintainers: + - Yuanfang Zhang + - Mao Jinlong + - Jie Gan + +description: | + The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB), + Embedded Trace FIFO(ETF) and Embedded Trace Router(ETR) configurations. + The configuration mode (ETB, ETF, ETR) is discovered at boot time when + the device is probed. + + The Coresight TMC Control unit controls various Coresight behaviors. + It works as a helper device when connected to TMC ETR device. + It is responsible for controlling the data filter function based on + the source device's Trace ID for TMC ETR device. The trace data with + that Trace id can get into ETR's buffer while other trace data gets + ignored. + +properties: + compatible: + enum: + - qcom,sa8775p-ctcu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + in-ports: + $ref: /schemas/graph.yaml#/properties/ports + + patternProperties: + '^port(@[0-1])?$': + description: Input connections from CoreSight Trace bus + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - reg + - in-ports + +additionalProperties: false + +examples: + - | + ctcu@1001000 { + compatible = "qcom,sa8775p-ctcu"; + reg = <0x1001000 0x1000>; + + clocks = <&aoss_qmp>; + clock-names = "apb"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ctcu_in_port0: endpoint { + remote-endpoint = <&etr0_out_port>; + }; + }; + + port@1 { + reg = <1>; + ctcu_in_port1: endpoint { + remote-endpoint = <&etr1_out_port>; + }; + }; + }; + }; diff --git a/Bindings/arm/qcom,coresight-tpda.yaml b/Bindings/arm/qcom,coresight-tpda.yaml index 76163abed65..5ed40f21b8e 100644 --- a/Bindings/arm/qcom,coresight-tpda.yaml +++ b/Bindings/arm/qcom,coresight-tpda.yaml @@ -55,8 +55,7 @@ properties: - const: arm,primecell reg: - minItems: 1 - maxItems: 2 + maxItems: 1 clocks: maxItems: 1 diff --git a/Bindings/arm/qcom,coresight-tpdm.yaml b/Bindings/arm/qcom,coresight-tpdm.yaml index 8eec07d9d45..07d21a3617f 100644 --- a/Bindings/arm/qcom,coresight-tpdm.yaml +++ b/Bindings/arm/qcom,coresight-tpdm.yaml @@ -41,8 +41,7 @@ properties: - const: arm,primecell reg: - minItems: 1 - maxItems: 2 + maxItems: 1 qcom,dsb-element-bits: description: diff --git a/Bindings/arm/rockchip.yaml b/Bindings/arm/rockchip.yaml index 522a6f0450e..650fb833d96 100644 --- a/Bindings/arm/rockchip.yaml +++ b/Bindings/arm/rockchip.yaml @@ -49,6 +49,11 @@ properties: - anbernic,rg-arc-s - const: rockchip,rk3566 + - description: Ariaboard Photonicat + items: + - const: ariaboard,photonicat + - const: rockchip,rk3568 + - description: ArmSoM Sige5 board items: - const: armsom,sige5 @@ -178,6 +183,13 @@ properties: - const: engicam,px30-core - const: rockchip,px30 + - description: Firefly iCore-3588Q-based boards + items: + - enum: + - mntre,reform2-rcore + - const: firefly,icore-3588q + - const: rockchip,rk3588 + - description: Firefly Core-3588J-based boards items: - enum: @@ -236,6 +248,11 @@ properties: - firefly,roc-rk3399-pc-plus - const: rockchip,rk3399 + - description: Firefly ROC-RK3576-PC + items: + - const: firefly,roc-rk3576-pc + - const: rockchip,rk3576 + - description: Firefly Station M2 items: - const: firefly,rk3566-roc-pc @@ -862,6 +879,11 @@ properties: - const: radxa,rock-4c-plus - const: rockchip,rk3399 + - description: Radxa ROCK 4D + items: + - const: radxa,rock-4d + - const: rockchip,rk3576 + - description: Radxa ROCK 4SE items: - const: radxa,rock-4se @@ -1136,11 +1158,12 @@ properties: - const: xunlong,orangepi-3b - const: rockchip,rk3566 - - description: Xunlong Orange Pi 5 Max/Plus + - description: Xunlong Orange Pi 5 Max/Plus/Ultra items: - enum: - xunlong,orangepi-5-max - xunlong,orangepi-5-plus + - xunlong,orangepi-5-ultra - const: rockchip,rk3588 - description: Xunlong Orange Pi R1 Plus / LTS diff --git a/Bindings/arm/stm32/st,stm32-syscon.yaml b/Bindings/arm/stm32/st,stm32-syscon.yaml index d083d8ad48b..ed97652c849 100644 --- a/Bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Bindings/arm/stm32/st,stm32-syscon.yaml @@ -21,6 +21,8 @@ properties: - st,stm32f4-gcan - st,stm32mp151-pwr-mcu - st,stm32mp157-syscfg + - st,stm32mp21-syscfg + - st,stm32mp23-syscfg - st,stm32mp25-syscfg - const: syscon - items: diff --git a/Bindings/arm/stm32/stm32.yaml b/Bindings/arm/stm32/stm32.yaml index b6c56d4ce6b..5fee2f38ff2 100644 --- a/Bindings/arm/stm32/stm32.yaml +++ b/Bindings/arm/stm32/stm32.yaml @@ -51,9 +51,16 @@ properties: - st,stm32mp135f-dk - const: st,stm32mp135 + - description: ST STM32MP133 based Boards + items: + - enum: + - pri,prihmb # Priva E-Measuringbox board + - const: st,stm32mp133 + - description: ST STM32MP151 based Boards items: - enum: + - ply,plyaqm # Plymovent AQM board - prt,mecio1r0 # Protonic MECIO1r0 - prt,mect1s # Protonic MECT1S - prt,prtt1a # Protonic PRTT1A @@ -94,6 +101,8 @@ properties: - description: Octavo OSD32MP153 System-in-Package based boards items: - enum: + - lxa,stm32mp153c-fairytux2-gen1 # Linux Automation FairyTux 2 (Generation 1) + - lxa,stm32mp153c-fairytux2-gen2 # Linux Automation FairyTux 2 (Generation 2) - lxa,stm32mp153c-tac-gen3 # Linux Automation TAC (Generation 3) - const: oct,stm32mp153x-osd32 - const: st,stm32mp153 @@ -178,9 +187,22 @@ properties: - description: ST STM32MP257 based Boards items: - enum: + - st,stm32mp257f-dk - st,stm32mp257f-ev1 - const: st,stm32mp257 + - description: ST STM32MP235 based Boards + items: + - enum: + - st,stm32mp235f-dk + - const: st,stm32mp235 + + - description: ST STM32MP215 based Boards + items: + - enum: + - st,stm32mp215f-dk + - const: st,stm32mp215 + additionalProperties: true ... diff --git a/Bindings/arm/sunxi.yaml b/Bindings/arm/sunxi.yaml index 046536d0270..f536cdd2c1a 100644 --- a/Bindings/arm/sunxi.yaml +++ b/Bindings/arm/sunxi.yaml @@ -589,6 +589,11 @@ properties: - const: emlid,neutis-n5h3 - const: allwinner,sun8i-h3 + - description: NetCube Systems Kumquat + items: + - const: netcube,kumquat + - const: allwinner,sun8i-v3s + - description: NextThing Co. CHIP items: - const: nextthing,chip diff --git a/Bindings/arm/ti/omap.yaml b/Bindings/arm/ti/omap.yaml index 93e04a109a1..3603edd7361 100644 --- a/Bindings/arm/ti/omap.yaml +++ b/Bindings/arm/ti/omap.yaml @@ -141,6 +141,13 @@ properties: - const: ti,omap4430 - const: ti,omap4 + - description: OMAP4 PandaBoard Revision A4 and later + items: + - const: ti,omap4-panda-a4 + - const: ti,omap4-panda + - const: ti,omap4430 + - const: ti,omap4 + - description: OMAP4 DuoVero with Parlor expansion board/daughter board items: - const: gumstix,omap4-duovero-parlor diff --git a/Bindings/ata/ceva,ahci-1v84.yaml b/Bindings/ata/ceva,ahci-1v84.yaml index 9952e0ef776..c92341888a2 100644 --- a/Bindings/ata/ceva,ahci-1v84.yaml +++ b/Bindings/ata/ceva,ahci-1v84.yaml @@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Ceva AHCI SATA Controller maintainers: - - Mubin Sayyed - Radhey Shyam Pandey description: | @@ -163,11 +162,9 @@ additionalProperties: false examples: - | - #include #include #include #include - #include #include sata: ahci@fd0c0000 { @@ -175,7 +172,7 @@ examples: reg = <0xfd0c0000 0x200>; interrupt-parent = <&gic>; interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&zynqmp_clk SATA_REF>; + clocks = <&zynqmp_clk 22>; ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>; ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>; ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>; diff --git a/Bindings/ata/fsl,pq-sata.yaml b/Bindings/ata/fsl,pq-sata.yaml new file mode 100644 index 00000000000..1d19ee832f0 --- /dev/null +++ b/Bindings/ata/fsl,pq-sata.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ata/fsl,pq-sata.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale 8xxx/3.0 Gb/s SATA nodes + +maintainers: + - J. Neuschäfer + +description: + SATA nodes are defined to describe on-chip Serial ATA controllers. + Each SATA controller should have its own node. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,mpc8377-sata + - fsl,mpc8536-sata + - fsl,mpc8315-sata + - fsl,mpc8379-sata + - const: fsl,pq-sata + - const: fsl,pq-sata-v2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3, 4] + description: | + 1 for controller @ 0x18000 + 2 for controller @ 0x19000 + 3 for controller @ 0x1a000 + 4 for controller @ 0x1b000 + +required: + - compatible + - interrupts + - cell-index + +additionalProperties: false + +examples: + - | + #include + sata@18000 { + compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; + reg = <0x18000 0x1000>; + cell-index = <1>; + interrupts = <44 IRQ_TYPE_LEVEL_LOW>; + }; + +... diff --git a/Bindings/ata/fsl-sata.txt b/Bindings/ata/fsl-sata.txt deleted file mode 100644 index fd63bb3becc..00000000000 --- a/Bindings/ata/fsl-sata.txt +++ /dev/null @@ -1,28 +0,0 @@ -* Freescale 8xxx/3.0 Gb/s SATA nodes - -SATA nodes are defined to describe on-chip Serial ATA controllers. -Each SATA port should have its own node. - -Required properties: -- compatible : compatible list, contains 2 entries, first is - "fsl,CHIP-sata", where CHIP is the processor - (mpc8315, mpc8379, etc.) and the second is - "fsl,pq-sata" -- interrupts : -- cell-index : controller index. - 1 for controller @ 0x18000 - 2 for controller @ 0x19000 - 3 for controller @ 0x1a000 - 4 for controller @ 0x1b000 - -Optional properties: -- reg : - -Example: - sata@18000 { - compatible = "fsl,mpc8379-sata", "fsl,pq-sata"; - reg = <0x18000 0x1000>; - cell-index = <1>; - interrupts = <2c 8>; - interrupt-parent = < &ipic >; - }; diff --git a/Bindings/bus/qcom,ebi2.yaml b/Bindings/bus/qcom,ebi2.yaml deleted file mode 100644 index 1b1fb3538e6..00000000000 --- a/Bindings/bus/qcom,ebi2.yaml +++ /dev/null @@ -1,239 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/bus/qcom,ebi2.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm External Bus Interface 2 (EBI2) - -description: | - The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any - external memory (such as NAND or other memory-mapped peripherals) whereas - LCDC handles LCD displays. - - As it says it connects devices to an external bus interface, meaning address - lines (up to 9 address lines so can only address 1KiB external memory space), - data lines (16 bits), OE (output enable), ADV (address valid, used on some - NOR flash memories), WE (write enable). This on top of 6 different chip selects - (CS0 thru CS5) so that in theory 6 different devices can be connected. - - Apparently this bus is clocked at 64MHz. It has dedicated pins on the package - and the bus can only come out on these pins, however if some of the pins are - unused they can be left unconnected or remuxed to be used as GPIO or in some - cases other orthogonal functions as well. - - Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me. - - The chip selects have the following memory range assignments. This region of - memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big. - - Chip Select Physical address base - CS0 GPIO134 0x1a800000-0x1b000000 (8MB) - CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB) - CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB) - CS3 GPIO133 0x1d000000-0x25000000 (128 MB) - CS4 GPIO132 0x1c800000-0x1d000000 (8MB) - CS5 GPIO131 0x1c000000-0x1c800000 (8MB) - - The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A, - August 6, 2012 contains some incomplete documentation of the EBI2. - - FIXME: the manual mentions "write precharge cycles" and "precharge cycles". - We have not been able to figure out which bit fields these correspond to - in the hardware, or what valid values exist. The current hypothesis is that - this is something just used on the FAST chip selects and that the SLOW - chip selects are understood fully. There is also a "byte device enable" - flag somewhere for 8bit memories. - - FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit - unclear what this means, if they are mutually exclusive or can be used - together, or if some chip selects are hardwired to be FAST and others are SLOW - by design. - - The XMEM registers are totally undocumented but could be partially decoded - because the Cypress AN49576 Antioch Westbridge apparently has suspiciously - similar register layout, see: http://www.cypress.com/file/105771/download - -maintainers: - - Bjorn Andersson - -properties: - compatible: - enum: - - qcom,apq8060-ebi2 - - qcom,msm8660-ebi2 - - reg: - items: - - description: EBI2 config region - - description: XMEM config region - - reg-names: - items: - - const: ebi2 - - const: xmem - - ranges: true - - clocks: - items: - - description: EBI_2X clock - - description: EBI clock - - clock-names: - items: - - const: ebi2x - - const: ebi2 - - '#address-cells': - const: 2 - - '#size-cells': - const: 1 - -required: - - compatible - - reg - - reg-names - - ranges - - clocks - - clock-names - - '#address-cells' - - '#size-cells' - -patternProperties: - "^.*@[0-5],[0-9a-f]+$": - type: object - additionalProperties: true - properties: - reg: - maxItems: 1 - - # SLOW chip selects - qcom,xmem-recovery-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The time the memory continues to drive the data bus after OE - is de-asserted, in order to avoid contention on the data bus. - They are inserted when reading one CS and switching to another - CS or read followed by write on the same CS. Minimum value is - actually 1, so a value of 0 will still yield 1 recovery cycle. - minimum: 0 - maximum: 15 - - qcom,xmem-write-hold-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The extra cycles inserted after every write minimum 1. The - data out is driven from the time WE is asserted until CS is - asserted. With a hold of 1 (value = 0), the CS stays active - for 1 extra cycle, etc. - minimum: 0 - maximum: 15 - - qcom,xmem-write-delta-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The initial latency for write cycles inserted for the first - write to a page or burst memory. - minimum: 0 - maximum: 255 - - qcom,xmem-read-delta-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The initial latency for read cycles inserted for the first - read to a page or burst memory. - minimum: 0 - maximum: 255 - - qcom,xmem-write-wait-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The number of wait cycles for every write access. - minimum: 0 - maximum: 15 - - qcom,xmem-read-wait-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The number of wait cycles for every read access. - minimum: 0 - maximum: 15 - - - # FAST chip selects - qcom,xmem-address-hold-enable: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - Holds the address for an extra cycle to meet hold time - requirements with ADV assertion, when set to 1. - enum: [ 0, 1 ] - - qcom,xmem-adv-to-oe-recovery-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The number of cycles elapsed before an OE assertion, with - respect to the cycle where ADV (address valid) is asserted. - minimum: 0 - maximum: 3 - - qcom,xmem-read-hold-cycles: - $ref: /schemas/types.yaml#/definitions/uint32 - description: > - The length in cycles of the first segment of a read transfer. - For a single read transfer this will be the time from CS - assertion to OE assertion. - minimum: 0 - maximum: 15 - - required: - - reg - -additionalProperties: false - -examples: - - | - #include - #include - #include - - external-bus@1a100000 { - compatible = "qcom,msm8660-ebi2"; - reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; - reg-names = "ebi2", "xmem"; - ranges = <0 0x0 0x1a800000 0x00800000>, - <1 0x0 0x1b000000 0x00800000>, - <2 0x0 0x1b800000 0x00800000>, - <3 0x0 0x1d000000 0x08000000>, - <4 0x0 0x1c800000 0x00800000>, - <5 0x0 0x1c000000 0x00800000>; - - clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; - clock-names = "ebi2x", "ebi2"; - - #address-cells = <2>; - #size-cells = <1>; - - ethernet@2,0 { - compatible = "smsc,lan9221", "smsc,lan9115"; - reg = <2 0x0 0x100>; - - interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>, - <&tlmm 29 IRQ_TYPE_EDGE_RISING>; - reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; - - phy-mode = "mii"; - reg-io-width = <2>; - smsc,force-external-phy; - smsc,irq-push-pull; - - /* SLOW chipselect config */ - qcom,xmem-recovery-cycles = <0>; - qcom,xmem-write-hold-cycles = <3>; - qcom,xmem-write-delta-cycles = <31>; - qcom,xmem-read-delta-cycles = <28>; - qcom,xmem-write-wait-cycles = <9>; - qcom,xmem-read-wait-cycles = <9>; - }; - }; diff --git a/Bindings/clock/allwinner,sun55i-a523-ccu.yaml b/Bindings/clock/allwinner,sun55i-a523-ccu.yaml new file mode 100644 index 00000000000..f5f62e9a10a --- /dev/null +++ b/Bindings/clock/allwinner,sun55i-a523-ccu.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun55i-a523-ccu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A523 Clock Control Unit + +maintainers: + - Andre Przywara + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + enum: + - allwinner,sun55i-a523-ccu + - allwinner,sun55i-a523-r-ccu + + reg: + maxItems: 1 + + clocks: + minItems: 4 + maxItems: 5 + + clock-names: + minItems: 4 + maxItems: 5 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (usually at 24MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Low Frequency Oscillator fanout + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: losc-fanout + + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-r-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (usually at 24MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Peripherals PLL + - description: Audio PLL + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: pll-periph + - const: pll-audio + +additionalProperties: false + +examples: + - | + clock-controller@2001000 { + compatible = "allwinner,sun55i-a523-ccu"; + reg = <0x02001000 0x1000>; + clocks = <&osc24M>, <&osc32k>, <&iosc>, <&r_ccu 1>; + clock-names = "hosc", "losc", "iosc", "losc-fanout"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/Bindings/clock/atmel,at91rm9200-pmc.yaml b/Bindings/clock/atmel,at91rm9200-pmc.yaml index 885d47dd572..e803a1fc368 100644 --- a/Bindings/clock/atmel,at91rm9200-pmc.yaml +++ b/Bindings/clock/atmel,at91rm9200-pmc.yaml @@ -34,6 +34,8 @@ properties: - enum: - atmel,at91rm9200-pmc - atmel,at91sam9260-pmc + - atmel,at91sam9261-pmc + - atmel,at91sam9263-pmc - atmel,at91sam9g45-pmc - atmel,at91sam9n12-pmc - atmel,at91sam9rl-pmc @@ -111,6 +113,8 @@ allOf: enum: - atmel,at91rm9200-pmc - atmel,at91sam9260-pmc + - atmel,at91sam9261-pmc + - atmel,at91sam9263-pmc - atmel,at91sam9g20-pmc then: properties: diff --git a/Bindings/clock/imx8m-clock.yaml b/Bindings/clock/imx8m-clock.yaml index c643d4a8147..4fec5583270 100644 --- a/Bindings/clock/imx8m-clock.yaml +++ b/Bindings/clock/imx8m-clock.yaml @@ -43,6 +43,13 @@ properties: ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h for the full list of i.MX8M clock IDs. + fsl,operating-mode: + $ref: /schemas/types.yaml#/definitions/string + enum: [nominal, overdrive] + description: + The operating mode of the SoC. This affects the maximum clock rates that + can safely be configured by the clock controller. + required: - compatible - reg @@ -109,6 +116,7 @@ examples: <&clk_ext3>, <&clk_ext4>; clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", "clk_ext3", "clk_ext4"; + fsl,operating-mode = "nominal"; }; - | diff --git a/Bindings/clock/imx8mp-audiomix.yaml b/Bindings/clock/imx8mp-audiomix.yaml index 6588a17a7d9..0272c952703 100644 --- a/Bindings/clock/imx8mp-audiomix.yaml +++ b/Bindings/clock/imx8mp-audiomix.yaml @@ -24,8 +24,8 @@ properties: maxItems: 1 clocks: - minItems: 7 - maxItems: 7 + minItems: 8 + maxItems: 8 clock-names: items: @@ -36,6 +36,7 @@ properties: - const: sai5 - const: sai6 - const: sai7 + - const: axi '#clock-cells': const: 1 @@ -72,10 +73,11 @@ examples: <&clk IMX8MP_CLK_SAI3>, <&clk IMX8MP_CLK_SAI5>, <&clk IMX8MP_CLK_SAI6>, - <&clk IMX8MP_CLK_SAI7>; + <&clk IMX8MP_CLK_SAI7>, + <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; clock-names = "ahb", "sai1", "sai2", "sai3", - "sai5", "sai6", "sai7"; + "sai5", "sai6", "sai7", "axi"; power-domains = <&pgc_audio>; }; diff --git a/Bindings/clock/mediatek,mt8188-clock.yaml b/Bindings/clock/mediatek,mt8188-clock.yaml index 86057032054..2985c8c717d 100644 --- a/Bindings/clock/mediatek,mt8188-clock.yaml +++ b/Bindings/clock/mediatek,mt8188-clock.yaml @@ -57,6 +57,27 @@ required: - reg - '#clock-cells' +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8188-camsys-rawa + - mediatek,mt8188-camsys-rawb + - mediatek,mt8188-camsys-yuva + - mediatek,mt8188-camsys-yuvb + - mediatek,mt8188-imgsys-wpe1 + - mediatek,mt8188-imgsys-wpe2 + - mediatek,mt8188-imgsys-wpe3 + - mediatek,mt8188-imgsys1-dip-nr + - mediatek,mt8188-imgsys1-dip-top + - mediatek,mt8188-ipesys + + then: + required: + - '#reset-cells' + additionalProperties: false examples: diff --git a/Bindings/clock/mediatek,mtmips-sysc.yaml b/Bindings/clock/mediatek,mtmips-sysc.yaml index ba7ffc5b16a..83c1803ffd1 100644 --- a/Bindings/clock/mediatek,mtmips-sysc.yaml +++ b/Bindings/clock/mediatek,mtmips-sysc.yaml @@ -18,6 +18,12 @@ description: | These SoCs have an XTAL from where the cpu clock is provided as well as derived clocks for the bus and the peripherals. + Each clock is assigned an identifier and client nodes use this identifier + to specify the clock which they consume. + + All these identifiers could be found in: + [1]: . + properties: compatible: items: @@ -38,7 +44,8 @@ properties: '#clock-cells': description: - The first cell indicates the clock number. + The first cell indicates the clock number, see [1] for available + clocks. const: 1 '#reset-cells': @@ -56,6 +63,8 @@ additionalProperties: false examples: - | + #include + syscon@0 { compatible = "ralink,rt5350-sysc", "syscon"; reg = <0x0 0x100>; diff --git a/Bindings/clock/qcom,ipq9574-nsscc.yaml b/Bindings/clock/qcom,ipq9574-nsscc.yaml new file mode 100644 index 00000000000..17252b6ea3b --- /dev/null +++ b/Bindings/clock/qcom,ipq9574-nsscc.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 + +maintainers: + - Bjorn Andersson + - Anusha Rao + +description: | + Qualcomm networking sub system clock control module provides the clocks, + resets on IPQ9574 + + See also:: + include/dt-bindings/clock/qcom,ipq9574-nsscc.h + include/dt-bindings/reset/qcom,ipq9574-nsscc.h + +properties: + compatible: + const: qcom,ipq9574-nsscc + + clocks: + items: + - description: Board XO source + - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source + - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source + - description: GCC GPLL0 OUT AUX clock source + - description: Uniphy0 NSS Rx clock source + - description: Uniphy0 NSS Tx clock source + - description: Uniphy1 NSS Rx clock source + - description: Uniphy1 NSS Tx clock source + - description: Uniphy2 NSS Rx clock source + - description: Uniphy2 NSS Tx clock source + - description: GCC NSSCC clock source + + '#interconnect-cells': + const: 1 + + clock-names: + items: + - const: xo + - const: nss_1200 + - const: ppe_353 + - const: gpll0_out + - const: uniphy0_rx + - const: uniphy0_tx + - const: uniphy1_rx + - const: uniphy1_tx + - const: uniphy2_rx + - const: uniphy2_tx + - const: bus + +required: + - compatible + - clocks + - clock-names + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + clock-controller@39b00000 { + compatible = "qcom,ipq9574-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&xo_board_clk>, + <&cmn_pll NSS_1200MHZ_CLK>, + <&cmn_pll PPE_353MHZ_CLK>, + <&gcc GPLL0_OUT_AUX>, + <&uniphy 0>, + <&uniphy 1>, + <&uniphy 2>, + <&uniphy 3>, + <&uniphy 4>, + <&uniphy 5>, + <&gcc GCC_NSSCC_CLK>; + clock-names = "xo", + "nss_1200", + "ppe_353", + "gpll0_out", + "uniphy0_rx", + "uniphy0_tx", + "uniphy1_rx", + "uniphy1_tx", + "uniphy2_rx", + "uniphy2_tx", + "bus"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/Bindings/clock/qcom,rpmcc.yaml b/Bindings/clock/qcom,rpmcc.yaml index be3835e2e04..90cd3feab5f 100644 --- a/Bindings/clock/qcom,rpmcc.yaml +++ b/Bindings/clock/qcom,rpmcc.yaml @@ -44,6 +44,7 @@ properties: - qcom,rpmcc-msm8998 - qcom,rpmcc-qcm2290 - qcom,rpmcc-qcs404 + - qcom,rpmcc-sdm429 - qcom,rpmcc-sdm660 - qcom,rpmcc-sm6115 - qcom,rpmcc-sm6125 @@ -123,6 +124,7 @@ allOf: - qcom,rpmcc-msm8998 - qcom,rpmcc-qcm2290 - qcom,rpmcc-qcs404 + - qcom,rpmcc-sdm429 - qcom,rpmcc-sdm660 - qcom,rpmcc-sm6115 - qcom,rpmcc-sm6125 diff --git a/Bindings/clock/qcom,sc7280-lpasscorecc.yaml b/Bindings/clock/qcom,sc7280-lpasscorecc.yaml index 488d6395942..99ab9106009 100644 --- a/Bindings/clock/qcom,sc7280-lpasscorecc.yaml +++ b/Bindings/clock/qcom,sc7280-lpasscorecc.yaml @@ -20,6 +20,7 @@ description: | properties: compatible: enum: + - qcom,qcm6490-lpassaudiocc - qcom,sc7280-lpassaoncc - qcom,sc7280-lpassaudiocc - qcom,sc7280-lpasscorecc @@ -68,7 +69,9 @@ allOf: properties: compatible: contains: - const: qcom,sc7280-lpassaudiocc + enum: + - qcom,qcm6490-lpassaudiocc + - qcom,sc7280-lpassaudiocc then: properties: diff --git a/Bindings/clock/qcom,sm8450-camcc.yaml b/Bindings/clock/qcom,sm8450-camcc.yaml index b88b6c9b399..9e79f8fec43 100644 --- a/Bindings/clock/qcom,sm8450-camcc.yaml +++ b/Bindings/clock/qcom,sm8450-camcc.yaml @@ -64,7 +64,6 @@ allOf: - qcom,sc8280xp-camcc - qcom,sm8450-camcc - qcom,sm8550-camcc - - qcom,x1e80100-camcc then: required: - required-opps diff --git a/Bindings/clock/qcom,x1e80100-camcc.yaml b/Bindings/clock/qcom,x1e80100-camcc.yaml index 5bbbaa15a26..938a2f1ff3f 100644 --- a/Bindings/clock/qcom,x1e80100-camcc.yaml +++ b/Bindings/clock/qcom,x1e80100-camcc.yaml @@ -40,9 +40,9 @@ properties: - description: A phandle to the MMCX power-domain required-opps: - maxItems: 1 - description: - A phandle to an OPP node describing MMCX performance points. + items: + - description: A phandle to an OPP node describing MXC performance points + - description: A phandle to an OPP node describing MMCX performance points required: - compatible @@ -66,7 +66,8 @@ examples: <&sleep_clk>; power-domains = <&rpmhpd RPMHPD_MXC>, <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/Bindings/clock/rockchip,rk3528-cru.yaml b/Bindings/clock/rockchip,rk3528-cru.yaml new file mode 100644 index 00000000000..5a3ec902351 --- /dev/null +++ b/Bindings/clock/rockchip,rk3528-cru.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3528 Clock and Reset Controller + +maintainers: + - Yao Zi + +description: | + The RK3528 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example, it provides SCLK_UART0 and + PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART + module. + Each clock is assigned an identifier, consumer nodes can use it to specify + the clock. All available clock and reset IDs are defined in dt-binding + headers. + +properties: + compatible: + const: rockchip,rk3528-cru + + reg: + maxItems: 1 + + clocks: + items: + - description: External 24MHz oscillator clock + - description: > + 50MHz clock generated by PHY module, for generating GMAC0 clocks only. + + clock-names: + items: + - const: xin24m + - const: gmac0 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ff4a0000 { + compatible = "rockchip,rk3528-cru"; + reg = <0xff4a0000 0x30000>; + clocks = <&xin24m>, <&gmac0_clk>; + clock-names = "xin24m", "gmac0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Bindings/clock/rockchip,rk3562-cru.yaml b/Bindings/clock/rockchip,rk3562-cru.yaml new file mode 100644 index 00000000000..36a353f5c42 --- /dev/null +++ b/Bindings/clock/rockchip,rk3562-cru.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3562-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip rk3562 Clock and Reset Control Module + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +description: + The RK3562 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example it provides SCLK_UART2 and + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART + module. + +properties: + compatible: + const: rockchip,rk3562-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: xin24m + - const: xin32k + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@ff100000 { + compatible = "rockchip,rk3562-cru"; + reg = <0xff100000 0x40000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Bindings/clock/samsung,exynos2200-cmu.yaml b/Bindings/clock/samsung,exynos2200-cmu.yaml new file mode 100644 index 00000000000..89433e6d351 --- /dev/null +++ b/Bindings/clock/samsung,exynos2200-cmu.yaml @@ -0,0 +1,247 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos2200-cmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos2200 SoC clock controller + +maintainers: + - Ivaylo Ivanov + - Chanwoo Choi + - Krzysztof Kozlowski + +description: | + Exynos2200 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clocks in that root tree + are two external clocks: XTCXO (76.8 MHz) and RTCCLK (32768 Hz). XTCXO must be + defined as a fixed-rate clock in dts, whereas RTCCLK originates from PMIC. + + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and + dividers; all other clocks of function blocks (other CMUs) are usually + derived from CMU_TOP. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + 'include/dt-bindings/clock/samsung,exynos2200-cmu.h' header. + +properties: + compatible: + enum: + - samsung,exynos2200-cmu-alive + - samsung,exynos2200-cmu-cmgp + - samsung,exynos2200-cmu-hsi0 + - samsung,exynos2200-cmu-peric0 + - samsung,exynos2200-cmu-peric1 + - samsung,exynos2200-cmu-peric2 + - samsung,exynos2200-cmu-peris + - samsung,exynos2200-cmu-top + - samsung,exynos2200-cmu-ufs + - samsung,exynos2200-cmu-vts + + clocks: + minItems: 1 + maxItems: 6 + + clock-names: + minItems: 1 + maxItems: 6 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - reg + - "#clock-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-alive + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_ALIVE NOC clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-cmgp + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_CMGP NOC clock (from CMU_TOP) + - description: CMU_CMGP PERI clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: peri + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-hsi0 + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: External RTC clock (32768 Hz) + - description: CMU_HSI0 NOC clock (from CMU_TOP) + - description: CMU_HSI0 DPGTC clock (from CMU_TOP) + - description: CMU_HSI0 DPOSC clock (from CMU_TOP) + - description: CMU_HSI0 USB32DRD clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: rtcclk + - const: noc + - const: dpgtc + - const: dposc + - const: usb + + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos2200-cmu-peric0 + - samsung,exynos2200-cmu-peric1 + - samsung,exynos2200-cmu-peric2 + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_PERICn NOC clock (from CMU_TOP) + - description: CMU_PERICn IP0 clock (from CMU_TOP) + - description: CMU_PERICn IP1 clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: ip0 + - const: ip1 + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (25.6 MHz) + - description: CMU_PERIS NOC clock (from CMU_TOP) + - description: CMU_PERIS GIC clock (from CMU_TOP) + + clock-names: + items: + - const: tcxo_div3 + - const: noc + - const: gic + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-top + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-ufs + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_UFS NOC clock (from CMU_TOP) + - description: CMU_UFS MMC clock (from CMU_TOP) + - description: CMU_UFS UFS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: noc + - const: mmc + - const: ufs + + - if: + properties: + compatible: + contains: + const: samsung,exynos2200-cmu-vts + + then: + properties: + clocks: + items: + - description: External reference clock (76.8 MHz) + - description: CMU_VTS DMIC clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dmic + +additionalProperties: false + +examples: + - | + #include + + cmu_vts: clock-controller@15300000 { + compatible = "samsung,exynos2200-cmu-vts"; + reg = <0x15300000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_VTS_DMIC>; + clock-names = "oscclk", "dmic"; + }; + +... diff --git a/Bindings/clock/samsung,exynos7870-cmu.yaml b/Bindings/clock/samsung,exynos7870-cmu.yaml new file mode 100644 index 00000000000..3c58712f12b --- /dev/null +++ b/Bindings/clock/samsung,exynos7870-cmu.yaml @@ -0,0 +1,227 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/samsung,exynos7870-cmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos7870 SoC clock controller + +maintainers: + - Kaustabh Chakraborty + +description: | + Exynos7870 clock controller is comprised of several CMU units, generating + clocks for different domains. Those CMU units are modeled as separate device + tree nodes, and might depend on each other. The root clock in that root tree + is an external clock: OSCCLK (26 MHz). This external clock must be defined + as a fixed-rate clock in dts. + + Each clock is assigned an identifier and client nodes can use this identifier + to specify the clock which they consume. All clocks available for usage + in clock consumer nodes are defined as preprocessor macros in + include/dt-bindings/clock/samsung,exynos7870-cmu.h header. + +properties: + compatible: + enum: + - samsung,exynos7870-cmu-mif + - samsung,exynos7870-cmu-dispaud + - samsung,exynos7870-cmu-fsys + - samsung,exynos7870-cmu-g3d + - samsung,exynos7870-cmu-isp + - samsung,exynos7870-cmu-mfcmscl + - samsung,exynos7870-cmu-peri + + clocks: + minItems: 1 + maxItems: 10 + + clock-names: + minItems: 1 + maxItems: 10 + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - clocks + - clock-names + - "#clock-cells" + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-mif + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + + clock-names: + items: + - const: oscclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-dispaud + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_DISPAUD bus clock (from CMU_MIF) + - description: DECON external clock (from CMU_MIF) + - description: DECON vertical clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: bus + - const: decon_eclk + - const: decon_vclk + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-fsys + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_FSYS bus clock (from CMU_MIF) + - description: USB20DRD clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: bus + - const: usb20drd + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-g3d + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: G3D switch clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: switch + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-isp + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: ISP camera clock (from CMU_MIF) + - description: ISP clock (from CMU_MIF) + - description: ISP VRA clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: cam + - const: isp + - const: vra + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-mfcmscl + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: MSCL clock (from CMU_MIF) + - description: MFC clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: mfc + - const: mscl + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-cmu-peri + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERI bus clock (from CMU_MIF) + - description: SPI0 clock (from CMU_MIF) + - description: SPI1 clock (from CMU_MIF) + - description: SPI2 clock (from CMU_MIF) + - description: SPI3 clock (from CMU_MIF) + - description: SPI4 clock (from CMU_MIF) + - description: UART0 clock (from CMU_MIF) + - description: UART1 clock (from CMU_MIF) + - description: UART2 clock (from CMU_MIF) + + clock-names: + items: + - const: oscclk + - const: bus + - const: spi0 + - const: spi1 + - const: spi2 + - const: spi3 + - const: spi4 + - const: uart0 + - const: uart1 + - const: uart2 + +additionalProperties: false + +examples: + - | + #include + + cmu_peri: clock-controller@101f0000 { + compatible = "samsung,exynos7870-cmu-peri"; + reg = <0x101f0000 0x1000>; + #clock-cells = <1>; + + clock-names = "oscclk", "bus", "spi0", "spi1", "spi2", + "spi3", "spi4", "uart0", "uart1", "uart2"; + clocks = <&oscclk>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_BUS>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI0>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI1>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI2>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI3>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_SPI4>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART0>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART1>, + <&cmu_mif CLK_GOUT_MIF_CMU_PERI_UART2>; + }; + +... diff --git a/Bindings/clock/samsung,exynos990-clock.yaml b/Bindings/clock/samsung,exynos990-clock.yaml index 9e7944b5f13..c15cc1752b0 100644 --- a/Bindings/clock/samsung,exynos990-clock.yaml +++ b/Bindings/clock/samsung,exynos990-clock.yaml @@ -31,6 +31,7 @@ properties: compatible: enum: - samsung,exynos990-cmu-hsi0 + - samsung,exynos990-cmu-peris - samsung,exynos990-cmu-top clocks: @@ -79,6 +80,24 @@ allOf: - const: usbdp_debug - const: dpgtc + - if: + properties: + compatible: + contains: + const: samsung,exynos990-cmu-peris + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: CMU_PERIS BUS clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: bus + - if: properties: compatible: diff --git a/Bindings/clock/ti,clkctrl.yaml b/Bindings/clock/ti,clkctrl.yaml new file mode 100644 index 00000000000..49787550ce4 --- /dev/null +++ b/Bindings/clock/ti,clkctrl.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,clkctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments clkctrl clock + +maintainers: + - Tony Lindgren + - Andreas Kemnade + +description: | + Texas Instruments SoCs can have a clkctrl clock controller for each + interconnect target module. The clkctrl clock controller manages functional + and interface clocks for each module. Each clkctrl controller can also + gate one or more optional functional clocks for a module, and can have one + or more clock muxes. There is a clkctrl clock controller typically for each + interconnect target module on omap4 and later variants. + + The clock consumers can specify the index of the clkctrl clock using + the hardware offset from the clkctrl instance register space. The optional + clocks can be specified by clkctrl hardware offset and the index of the + optional clock. + +properties: + compatible: + enum: + - ti,clkctrl + - ti,clkctrl-l4-cfg + - ti,clkctrl-l4-per + - ti,clkctrl-l4-secure + - ti,clkctrl-l4-wkup + + "#clock-cells": + const: 2 + + clock-output-names: + maxItems: 1 + + reg: + minItems: 1 + maxItems: 8 # arbitrary, should be enough + +required: + - compatible + - "#clock-cells" + - clock-output-names + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <1>; + + clock@20 { + compatible = "ti,clkctrl"; + clock-output-names = "l4_per"; + reg = <0x20 0x1b0>; + #clock-cells = <2>; + }; + }; diff --git a/Bindings/clock/ti-clkctrl.txt b/Bindings/clock/ti-clkctrl.txt deleted file mode 100644 index d20db7974a3..00000000000 --- a/Bindings/clock/ti-clkctrl.txt +++ /dev/null @@ -1,63 +0,0 @@ -Texas Instruments clkctrl clock binding - -Texas Instruments SoCs can have a clkctrl clock controller for each -interconnect target module. The clkctrl clock controller manages functional -and interface clocks for each module. Each clkctrl controller can also -gate one or more optional functional clocks for a module, and can have one -or more clock muxes. There is a clkctrl clock controller typically for each -interconnect target module on omap4 and later variants. - -The clock consumers can specify the index of the clkctrl clock using -the hardware offset from the clkctrl instance register space. The optional -clocks can be specified by clkctrl hardware offset and the index of the -optional clock. - -For more information, please see the Linux clock framework binding at -Documentation/devicetree/bindings/clock/clock-bindings.txt. - -Required properties : -- compatible : shall be "ti,clkctrl" or a clock domain specific name: - "ti,clkctrl-l4-cfg" - "ti,clkctrl-l4-per" - "ti,clkctrl-l4-secure" - "ti,clkctrl-l4-wkup" -- clock-output-names : from common clock binding -- #clock-cells : shall contain 2 with the first entry being the instance - offset from the clock domain base and the second being the - clock index -- reg : clock registers - -Example: Clock controller node on omap 4430: - -&cm2 { - l4per: cm@1400 { - cm_l4per@0 { - cm_l4per_clkctrl: clock@20 { - compatible = "ti,clkctrl"; - clock-output-names = "l4_per"; - reg = <0x20 0x1b0>; - #clock-cells = <2>; - }; - }; - }; -}; - -Example: Preprocessor helper macros in dt-bindings/clock/ti-clkctrl.h - -#define OMAP4_CLKCTRL_OFFSET 0x20 -#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) -#define MODULEMODE_HWCTRL 1 -#define MODULEMODE_SWCTRL 2 - -#define OMAP4_GPTIMER10_CLKTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_GPTIMER11_CLKTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_GPTIMER2_CLKTRL OMAP4_CLKCTRL_INDEX(0x38) -... -#define OMAP4_GPIO2_CLKCTRL OMAP_CLKCTRL_INDEX(0x60) - -Example: Clock consumer node for GPIO2: - -&gpio2 { - clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0 - &cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 8>; -}; diff --git a/Bindings/connector/gocontroll,moduline-module-slot.yaml b/Bindings/connector/gocontroll,moduline-module-slot.yaml new file mode 100644 index 00000000000..a16ae2762d1 --- /dev/null +++ b/Bindings/connector/gocontroll,moduline-module-slot.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/connector/gocontroll,moduline-module-slot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GOcontroll Moduline Module slot + +maintainers: + - Maud Spierings + +description: + The GOcontroll Moduline module slot represents a connector that fullfills the + Moduline slot specification, and can thus house any IO module that is also + built to this spec. + +properties: + compatible: + const: gocontroll,moduline-module-slot + + reg: + maxItems: 1 + + interrupts: + description: indicates readiness, high means busy. + maxItems: 1 + reset-gpios: + description: resets the module, active low. + maxItems: 1 + sync-gpios: + description: sync line between all module slots. + maxItems: 1 + + vdd-supply: + description: low power 3v3 supply generally for the microcontroller. + vddp-supply: + description: medium power 5v0 supply for on module low power peripherals. + vddhpp-supply: + description: high power 6v-8v supply for on module high power peripherals. + power-supply: + description: high power 6v-30v supply for high power module circuits. + + i2c-bus: + description: i2c bus shared between module slots and the SoC + $ref: /schemas/types.yaml#/definitions/phandle + + slot-number: + description: + The number of the module slot representing the location of on the pcb. + This enables access to the modules based on slot location. + $ref: /schemas/types.yaml#/definitions/uint32 + + spi-max-frequency: true + +required: + - compatible + - reg + - reset-gpios + - interrupts + - sync-gpios + - i2c-bus + - slot-number + +additionalProperties: false + +examples: + - | + #include + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + reg = <0>; + compatible = "gocontroll,moduline-module-slot"; + reset-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; + sync-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio4>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <®_3v3_per>; + vddp-supply = <®_5v0>; + vddhpp-supply = <®_6v4>; + i2c-bus = <&i2c2>; + slot-number = <1>; + }; + }; diff --git a/Bindings/cpufreq/cpufreq-qcom-hw.yaml b/Bindings/cpufreq/cpufreq-qcom-hw.yaml index e937eb7355e..e0242bed334 100644 --- a/Bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -34,6 +34,7 @@ properties: - description: v2 of CPUFREQ HW (EPSS) items: - enum: + - qcom,qcs8300-cpufreq-epss - qcom,qdu1000-cpufreq-epss - qcom,sa8255p-cpufreq-epss - qcom,sa8775p-cpufreq-epss @@ -111,22 +112,20 @@ allOf: enum: - qcom,qcm2290-cpufreq-hw - qcom,sar2130p-cpufreq-epss + - qcom,sdx75-cpufreq-epss then: properties: reg: - minItems: 1 maxItems: 1 reg-names: - minItems: 1 maxItems: 1 interrupts: - minItems: 1 maxItems: 1 interrupt-names: - minItems: 1 + maxItems: 1 - if: properties: @@ -135,6 +134,7 @@ allOf: enum: - qcom,qdu1000-cpufreq-epss - qcom,sa8255p-cpufreq-epss + - qcom,sa8775p-cpufreq-epss - qcom,sc7180-cpufreq-hw - qcom,sc8180x-cpufreq-hw - qcom,sc8280xp-cpufreq-epss @@ -160,12 +160,14 @@ allOf: interrupt-names: minItems: 2 + maxItems: 2 - if: properties: compatible: contains: enum: + - qcom,qcs8300-cpufreq-epss - qcom,sc7280-cpufreq-epss - qcom,sm8250-cpufreq-epss - qcom,sm8350-cpufreq-epss @@ -187,6 +189,7 @@ allOf: interrupt-names: minItems: 3 + maxItems: 3 - if: properties: @@ -211,7 +214,31 @@ allOf: interrupt-names: minItems: 2 + maxItems: 2 + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8650-cpufreq-epss + then: + properties: + reg: + minItems: 4 + maxItems: 4 + + reg-names: + minItems: 4 + maxItems: 4 + + interrupts: + minItems: 4 + maxItems: 4 + + interrupt-names: + minItems: 4 + maxItems: 4 examples: - | diff --git a/Bindings/crypto/fsl,sec2.0.yaml b/Bindings/crypto/fsl,sec2.0.yaml new file mode 100644 index 00000000000..2091b89bb72 --- /dev/null +++ b/Bindings/crypto/fsl,sec2.0.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/fsl,sec2.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale SoC SEC Security Engines versions 1.x-2.x-3.x + +maintainers: + - J. Neuschäfer + +properties: + compatible: + description: + Should contain entries for this and backward compatible SEC versions, + high to low. Warning - SEC1 and SEC2 are mutually exclusive. + oneOf: + - items: + - const: fsl,sec3.3 + - const: fsl,sec3.1 + - const: fsl,sec3.0 + - const: fsl,sec2.4 + - const: fsl,sec2.2 + - const: fsl,sec2.1 + - const: fsl,sec2.0 + - items: + - const: fsl,sec3.1 + - const: fsl,sec3.0 + - const: fsl,sec2.4 + - const: fsl,sec2.2 + - const: fsl,sec2.1 + - const: fsl,sec2.0 + - items: + - const: fsl,sec3.0 + - const: fsl,sec2.4 + - const: fsl,sec2.2 + - const: fsl,sec2.1 + - const: fsl,sec2.0 + - items: + - const: fsl,sec2.4 + - const: fsl,sec2.2 + - const: fsl,sec2.1 + - const: fsl,sec2.0 + - items: + - const: fsl,sec2.2 + - const: fsl,sec2.1 + - const: fsl,sec2.0 + - items: + - const: fsl,sec2.1 + - const: fsl,sec2.0 + - items: + - const: fsl,sec2.0 + - items: + - const: fsl,sec1.2 + - const: fsl,sec1.0 + - items: + - const: fsl,sec1.0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + fsl,num-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 4 ] + description: An integer representing the number of channels available. + + fsl,channel-fifo-len: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 100 + description: + An integer representing the number of descriptor pointers each channel + fetch fifo can hold. + + fsl,exec-units-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 0xfff + description: | + The bitmask representing what execution units (EUs) are available. + EU information should be encoded following the SEC's Descriptor Header + Dword EU_SEL0 field documentation, i.e. as follows: + + bit 0 = reserved - should be 0 + bit 1 = set if SEC has the ARC4 EU (AFEU) + bit 2 = set if SEC has the DES/3DES EU (DEU) + bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A) + bit 4 = set if SEC has the random number generator EU (RNG) + bit 5 = set if SEC has the public key EU (PKEU) + bit 6 = set if SEC has the AES EU (AESU) + bit 7 = set if SEC has the Kasumi EU (KEU) + bit 8 = set if SEC has the CRC EU (CRCU) + bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B) + + remaining bits are reserved for future SEC EUs. + + fsl,descriptor-types-mask: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + The bitmask representing what descriptors are available. Descriptor type + information should be encoded following the SEC's Descriptor Header Dword + DESC_TYPE field documentation, i.e. as follows: + + bit 0 = SEC supports descriptor type aesu_ctr_nonsnoop + bit 1 = SEC supports descriptor type ipsec_esp + bit 2 = SEC supports descriptor type common_nonsnoop + bit 3 = SEC supports descriptor type 802.11i AES ccmp + bit 4 = SEC supports descriptor type hmac_snoop_no_afeu + bit 5 = SEC supports descriptor type srtp + bit 6 = SEC supports descriptor type non_hmac_snoop_no_afeu + bit 7 = SEC supports descriptor type pkeu_assemble + bit 8 = SEC supports descriptor type aesu_key_expand_output + bit 9 = SEC supports descriptor type pkeu_ptmul + bit 10 = SEC supports descriptor type common_nonsnoop_afeu + bit 11 = SEC supports descriptor type pkeu_ptadd_dbl + + ..and so on and so forth. + +required: + - compatible + - reg + - fsl,num-channels + - fsl,channel-fifo-len + - fsl,exec-units-mask + - fsl,descriptor-types-mask + +unevaluatedProperties: false + +examples: + - | + /* MPC8548E */ + crypto@30000 { + compatible = "fsl,sec2.1", "fsl,sec2.0"; + reg = <0x30000 0x10000>; + interrupts = <29 2>; + interrupt-parent = <&mpic>; + fsl,num-channels = <4>; + fsl,channel-fifo-len = <24>; + fsl,exec-units-mask = <0xfe>; + fsl,descriptor-types-mask = <0x12b0ebf>; + }; + +... diff --git a/Bindings/crypto/fsl-sec2.txt b/Bindings/crypto/fsl-sec2.txt deleted file mode 100644 index 125f155d00d..00000000000 --- a/Bindings/crypto/fsl-sec2.txt +++ /dev/null @@ -1,65 +0,0 @@ -Freescale SoC SEC Security Engines versions 1.x-2.x-3.x - -Required properties: - -- compatible : Should contain entries for this and backward compatible - SEC versions, high to low, e.g., "fsl,sec2.1", "fsl,sec2.0" (SEC2/3) - e.g., "fsl,sec1.2", "fsl,sec1.0" (SEC1) - warning: SEC1 and SEC2 are mutually exclusive -- reg : Offset and length of the register set for the device -- interrupts : the SEC's interrupt number -- fsl,num-channels : An integer representing the number of channels - available. -- fsl,channel-fifo-len : An integer representing the number of - descriptor pointers each channel fetch fifo can hold. -- fsl,exec-units-mask : The bitmask representing what execution units - (EUs) are available. It's a single 32-bit cell. EU information - should be encoded following the SEC's Descriptor Header Dword - EU_SEL0 field documentation, i.e. as follows: - - bit 0 = reserved - should be 0 - bit 1 = set if SEC has the ARC4 EU (AFEU) - bit 2 = set if SEC has the DES/3DES EU (DEU) - bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A) - bit 4 = set if SEC has the random number generator EU (RNG) - bit 5 = set if SEC has the public key EU (PKEU) - bit 6 = set if SEC has the AES EU (AESU) - bit 7 = set if SEC has the Kasumi EU (KEU) - bit 8 = set if SEC has the CRC EU (CRCU) - bit 11 = set if SEC has the message digest EU extended alg set (MDEU-B) - -remaining bits are reserved for future SEC EUs. - -- fsl,descriptor-types-mask : The bitmask representing what descriptors - are available. It's a single 32-bit cell. Descriptor type information - should be encoded following the SEC's Descriptor Header Dword DESC_TYPE - field documentation, i.e. as follows: - - bit 0 = set if SEC supports the aesu_ctr_nonsnoop desc. type - bit 1 = set if SEC supports the ipsec_esp descriptor type - bit 2 = set if SEC supports the common_nonsnoop desc. type - bit 3 = set if SEC supports the 802.11i AES ccmp desc. type - bit 4 = set if SEC supports the hmac_snoop_no_afeu desc. type - bit 5 = set if SEC supports the srtp descriptor type - bit 6 = set if SEC supports the non_hmac_snoop_no_afeu desc.type - bit 7 = set if SEC supports the pkeu_assemble descriptor type - bit 8 = set if SEC supports the aesu_key_expand_output desc.type - bit 9 = set if SEC supports the pkeu_ptmul descriptor type - bit 10 = set if SEC supports the common_nonsnoop_afeu desc. type - bit 11 = set if SEC supports the pkeu_ptadd_dbl descriptor type - - ..and so on and so forth. - -Example: - - /* MPC8548E */ - crypto@30000 { - compatible = "fsl,sec2.1", "fsl,sec2.0"; - reg = <0x30000 0x10000>; - interrupts = <29 2>; - interrupt-parent = <&mpic>; - fsl,num-channels = <4>; - fsl,channel-fifo-len = <24>; - fsl,exec-units-mask = <0xfe>; - fsl,descriptor-types-mask = <0x12b0ebf>; - }; diff --git a/Bindings/crypto/inside-secure,safexcel-eip93.yaml b/Bindings/crypto/inside-secure,safexcel-eip93.yaml new file mode 100644 index 00000000000..997bf9717f9 --- /dev/null +++ b/Bindings/crypto/inside-secure,safexcel-eip93.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/inside-secure,safexcel-eip93.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Inside Secure SafeXcel EIP-93 cryptographic engine + +maintainers: + - Christian Marangi + +description: | + The Inside Secure SafeXcel EIP-93 is a cryptographic engine IP block + integrated in varios devices with very different and generic name from + PKTE to simply vendor+EIP93. The real IP under the hood is actually + developed by Inside Secure and given to license to vendors. + + The IP block is sold with different model based on what feature are + needed and are identified with the final letter. Each letter correspond + to a specific set of feature and multiple letter reflect the sum of the + feature set. + + EIP-93 models: + - EIP-93i: (basic) DES/Triple DES, AES, PRNG, IPsec ESP, SRTP, SHA1 + - EIP-93ie: i + SHA224/256, AES-192/256 + - EIP-93is: i + SSL/DTLS/DTLS, MD5, ARC4 + - EIP-93ies: i + e + s + - EIP-93iw: i + AES-XCB-MAC, AES-CCM + +properties: + compatible: + oneOf: + - items: + - const: airoha,en7581-eip93 + - const: inside-secure,safexcel-eip93ies + - items: + - not: {} + description: Need a SoC specific compatible + - enum: + - inside-secure,safexcel-eip93i + - inside-secure,safexcel-eip93ie + - inside-secure,safexcel-eip93is + - inside-secure,safexcel-eip93iw + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + + crypto@1e004000 { + compatible = "airoha,en7581-eip93", "inside-secure,safexcel-eip93ies"; + reg = <0x1fb70000 0x1000>; + + interrupts = ; + }; diff --git a/Bindings/crypto/inside-secure,safexcel.yaml b/Bindings/crypto/inside-secure,safexcel.yaml index ef07258d16c..343e2d04c79 100644 --- a/Bindings/crypto/inside-secure,safexcel.yaml +++ b/Bindings/crypto/inside-secure,safexcel.yaml @@ -47,6 +47,8 @@ properties: - const: core - const: reg + dma-coherent: true + required: - reg - interrupts diff --git a/Bindings/crypto/qcom,prng.yaml b/Bindings/crypto/qcom,prng.yaml index 5e6f8b64254..ed7e16bd11d 100644 --- a/Bindings/crypto/qcom,prng.yaml +++ b/Bindings/crypto/qcom,prng.yaml @@ -20,6 +20,7 @@ properties: - qcom,ipq5332-trng - qcom,ipq5424-trng - qcom,ipq9574-trng + - qcom,qcs615-trng - qcom,qcs8300-trng - qcom,sa8255p-trng - qcom,sa8775p-trng diff --git a/Bindings/crypto/qcom-qce.yaml b/Bindings/crypto/qcom-qce.yaml index 3ed56d9d378..3f35122f787 100644 --- a/Bindings/crypto/qcom-qce.yaml +++ b/Bindings/crypto/qcom-qce.yaml @@ -55,6 +55,7 @@ properties: - qcom,sm8550-qce - qcom,sm8650-qce - qcom,sm8750-qce + - qcom,x1e80100-qce - const: qcom,sm8150-qce - const: qcom,qce diff --git a/Bindings/display/apple,h7-display-pipe-mipi.yaml b/Bindings/display/apple,h7-display-pipe-mipi.yaml new file mode 100644 index 00000000000..5e6da66499a --- /dev/null +++ b/Bindings/display/apple,h7-display-pipe-mipi.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/apple,h7-display-pipe-mipi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple pre-DCP display controller MIPI interface + +maintainers: + - Sasha Finkelstein + +description: + The MIPI controller part of the pre-DCP Apple display controller + +allOf: + - $ref: dsi-controller.yaml# + +properties: + compatible: + items: + - enum: + - apple,t8112-display-pipe-mipi + - apple,t8103-display-pipe-mipi + - const: apple,h7-display-pipe-mipi + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input port. Always connected to the primary controller + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output MIPI DSI port to the panel + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - ports + +unevaluatedProperties: false + +examples: + - | + dsi@28200000 { + compatible = "apple,t8103-display-pipe-mipi", "apple,h7-display-pipe-mipi"; + reg = <0x28200000 0xc000>; + power-domains = <&ps_dispdfr_mipi>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dfr_adp_out_mipi: endpoint { + remote-endpoint = <&dfr_adp_out_mipi>; + }; + }; + + port@1 { + reg = <1>; + + dfr_panel_in: endpoint { + remote-endpoint = <&dfr_mipi_out_panel>; + }; + }; + }; + }; +... diff --git a/Bindings/display/apple,h7-display-pipe.yaml b/Bindings/display/apple,h7-display-pipe.yaml new file mode 100644 index 00000000000..102fb1804c0 --- /dev/null +++ b/Bindings/display/apple,h7-display-pipe.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/apple,h7-display-pipe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple pre-DCP display controller + +maintainers: + - Sasha Finkelstein + +description: + A secondary display controller used to drive the "touchbar" on + certain Apple laptops. + +properties: + compatible: + items: + - enum: + - apple,t8112-display-pipe + - apple,t8103-display-pipe + - const: apple,h7-display-pipe + + reg: + items: + - description: Primary register block, controls planes and blending + - description: + Contains other configuration registers like interrupt + and FIFO control + + reg-names: + items: + - const: be + - const: fe + + power-domains: + description: + Phandles to pmgr entries that are needed for this controller to turn on. + Aside from that, their specific functions are unknown + maxItems: 2 + + interrupts: + items: + - description: Unknown function + - description: Primary interrupt. Vsync events are reported via it + + interrupt-names: + items: + - const: be + - const: fe + + iommus: + maxItems: 1 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Output port. Always connected to apple,h7-display-pipe-mipi + +required: + - compatible + - reg + - interrupts + - port + +additionalProperties: false + +examples: + - | + #include + display-pipe@28200000 { + compatible = "apple,t8103-display-pipe", "apple,h7-display-pipe"; + reg = <0x28200000 0xc000>, + <0x28400000 0x4000>; + reg-names = "be", "fe"; + power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>; + interrupt-parent = <&aic>; + interrupts = , + ; + interrupt-names = "be", "fe"; + iommus = <&displaydfr_dart 0>; + + port { + dfr_adp_out_mipi: endpoint { + remote-endpoint = <&dfr_mipi_in_adp>; + }; + }; + }; +... diff --git a/Bindings/display/bridge/lvds-codec.yaml b/Bindings/display/bridge/lvds-codec.yaml index 6ceeed76e88..0487bbffd7f 100644 --- a/Bindings/display/bridge/lvds-codec.yaml +++ b/Bindings/display/bridge/lvds-codec.yaml @@ -41,6 +41,7 @@ properties: - enum: - ti,ds90cf364a # For the DS90CF364A FPD-Link LVDS Receiver - ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver + - ti,sn65lvds822 # For the SN65LVDS822 FlatLink LVDS Receiver - ti,sn65lvds94 # For the SN65DS94 LVDS serdes - const: lvds-decoder # Generic LVDS decoders compatible fallback - enum: diff --git a/Bindings/display/bridge/nwl-dsi.yaml b/Bindings/display/bridge/nwl-dsi.yaml index 350fb8f400f..5952e6448ed 100644 --- a/Bindings/display/bridge/nwl-dsi.yaml +++ b/Bindings/display/bridge/nwl-dsi.yaml @@ -111,11 +111,27 @@ properties: unevaluatedProperties: false port@1: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: DSI output port node to the panel or the next bridge in the chain + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + required: - port@0 - port@1 diff --git a/Bindings/display/bridge/ti,sn65dsi83.yaml b/Bindings/display/bridge/ti,sn65dsi83.yaml index bad6f5c81b0..9b5f3f3eab1 100644 --- a/Bindings/display/bridge/ti,sn65dsi83.yaml +++ b/Bindings/display/bridge/ti,sn65dsi83.yaml @@ -35,6 +35,9 @@ properties: vcc-supply: description: A 1.8V power supply (see regulator/regulator.yaml). + interrupts: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/Bindings/display/mediatek/mediatek,dpi.yaml b/Bindings/display/mediatek/mediatek,dpi.yaml index 0f1e556dc8e..b659d79393a 100644 --- a/Bindings/display/mediatek/mediatek,dpi.yaml +++ b/Bindings/display/mediatek/mediatek,dpi.yaml @@ -27,6 +27,7 @@ properties: - mediatek,mt8188-dp-intf - mediatek,mt8192-dpi - mediatek,mt8195-dp-intf + - mediatek,mt8195-dpi - items: - enum: - mediatek,mt6795-dpi @@ -35,6 +36,10 @@ properties: - enum: - mediatek,mt8365-dpi - const: mediatek,mt8192-dpi + - items: + - enum: + - mediatek,mt8188-dpi + - const: mediatek,mt8195-dpi reg: maxItems: 1 @@ -116,11 +121,13 @@ examples: - | #include #include + #include dpi: dpi@1401d000 { compatible = "mediatek,mt8173-dpi"; reg = <0x1401d000 0x1000>; interrupts = ; + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DPI_PIXEL>, <&mmsys CLK_MM_DPI_ENGINE>, <&apmixedsys CLK_APMIXED_TVDPLL>; diff --git a/Bindings/display/mediatek/mediatek,dsc.yaml b/Bindings/display/mediatek/mediatek,dsc.yaml index 846de6c17d9..a5b88eb97e3 100644 --- a/Bindings/display/mediatek/mediatek,dsc.yaml +++ b/Bindings/display/mediatek/mediatek,dsc.yaml @@ -22,6 +22,9 @@ properties: oneOf: - enum: - mediatek,mt8195-disp-dsc + - items: + - const: mediatek,mt8188-disp-dsc + - const: mediatek,mt8195-disp-dsc reg: maxItems: 1 diff --git a/Bindings/display/msm/dsi-controller-main.yaml b/Bindings/display/msm/dsi-controller-main.yaml index ffbd1dc9470..2aab33cd001 100644 --- a/Bindings/display/msm/dsi-controller-main.yaml +++ b/Bindings/display/msm/dsi-controller-main.yaml @@ -231,6 +231,7 @@ allOf: then: properties: clocks: + minItems: 7 maxItems: 7 clock-names: items: @@ -248,29 +249,12 @@ allOf: contains: enum: - qcom,msm8916-dsi-ctrl - then: - properties: - clocks: - maxItems: 6 - clock-names: - items: - - const: mdp_core - - const: iface - - const: bus - - const: byte - - const: pixel - - const: core - - - if: - properties: - compatible: - contains: - enum: - qcom,msm8953-dsi-ctrl - qcom,msm8976-dsi-ctrl then: properties: clocks: + minItems: 6 maxItems: 6 clock-names: items: @@ -291,6 +275,7 @@ allOf: then: properties: clocks: + minItems: 7 maxItems: 7 clock-names: items: @@ -311,6 +296,7 @@ allOf: then: properties: clocks: + minItems: 7 maxItems: 7 clock-names: items: @@ -328,28 +314,13 @@ allOf: contains: enum: - qcom,msm8998-dsi-ctrl - - qcom,sm6125-dsi-ctrl - - qcom,sm6350-dsi-ctrl - then: - properties: - clocks: - maxItems: 6 - clock-names: - items: - - const: byte - - const: byte_intf - - const: pixel - - const: core - - const: iface - - const: bus - - - if: - properties: - compatible: - contains: - enum: - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl + - qcom,sdm845-dsi-ctrl + - qcom,sm6115-dsi-ctrl + - qcom,sm6125-dsi-ctrl + - qcom,sm6350-dsi-ctrl + - qcom,sm6375-dsi-ctrl - qcom,sm6150-dsi-ctrl - qcom,sm7150-dsi-ctrl - qcom,sm8150-dsi-ctrl @@ -361,6 +332,7 @@ allOf: then: properties: clocks: + minItems: 6 maxItems: 6 clock-names: items: @@ -380,6 +352,7 @@ allOf: then: properties: clocks: + minItems: 9 maxItems: 9 clock-names: items: @@ -393,27 +366,6 @@ allOf: - const: pixel - const: core - - if: - properties: - compatible: - contains: - enum: - - qcom,sdm845-dsi-ctrl - - qcom,sm6115-dsi-ctrl - - qcom,sm6375-dsi-ctrl - then: - properties: - clocks: - maxItems: 6 - clock-names: - items: - - const: byte - - const: byte_intf - - const: pixel - - const: core - - const: iface - - const: bus - unevaluatedProperties: false examples: diff --git a/Bindings/display/msm/dsi-phy-common.yaml b/Bindings/display/msm/dsi-phy-common.yaml index 6b57ce41c95..d0ce85a08b6 100644 --- a/Bindings/display/msm/dsi-phy-common.yaml +++ b/Bindings/display/msm/dsi-phy-common.yaml @@ -15,6 +15,8 @@ description: properties: "#clock-cells": const: 1 + description: + See include/dt-bindings/clock/qcom,dsi-phy-28nm.h for clock IDs. "#phy-cells": const: 0 diff --git a/Bindings/display/msm/gmu.yaml b/Bindings/display/msm/gmu.yaml index ab884e23642..4392aa7a4ff 100644 --- a/Bindings/display/msm/gmu.yaml +++ b/Bindings/display/msm/gmu.yaml @@ -123,6 +123,7 @@ allOf: compatible: contains: enum: + - qcom,adreno-gmu-623.0 - qcom,adreno-gmu-635.0 - qcom,adreno-gmu-660.1 - qcom,adreno-gmu-663.0 diff --git a/Bindings/display/msm/qcom,sa8775p-mdss.yaml b/Bindings/display/msm/qcom,sa8775p-mdss.yaml index a90a8b3f1a9..5fac3e26670 100644 --- a/Bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -52,6 +52,13 @@ patternProperties: items: - const: qcom,sa8775p-dp + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sa8775p-edp-phy + required: - compatible @@ -61,6 +68,7 @@ examples: - | #include #include + #include #include #include #include @@ -158,6 +166,26 @@ examples: }; }; + mdss0_dp0_phy: phy@aec2a00 { + compatible = "qcom,sa8775p-edp-phy"; + + reg = <0x0aec2a00 0x200>, + <0x0aec2200 0xd0>, + <0x0aec2600 0xd0>, + <0x0aec2000 0x1c8>; + + clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + clock-names = "aux", + "cfg_ahb"; + + #clock-cells = <1>; + #phy-cells = <0>; + + vdda-phy-supply = <&vreg_l1c>; + vdda-pll-supply = <&vreg_l4a>; + }; + displayport-controller@af54000 { compatible = "qcom,sa8775p-dp"; @@ -186,9 +214,9 @@ examples: assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, <&dispcc_mdss_dptx0_pixel0_clk_src>; - assigned-clock-parents = <&mdss0_edp_phy 0>, <&mdss0_edp_phy 1>; + assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; - phys = <&mdss0_edp_phy>; + phys = <&mdss0_dp0_phy>; phy-names = "dp"; operating-points-v2 = <&dp_opp_table>; diff --git a/Bindings/display/msm/qcom,sm8550-mdss.yaml b/Bindings/display/msm/qcom,sm8550-mdss.yaml index 1ea50a2c7c8..59192c59ddb 100644 --- a/Bindings/display/msm/qcom,sm8550-mdss.yaml +++ b/Bindings/display/msm/qcom,sm8550-mdss.yaml @@ -30,10 +30,14 @@ properties: maxItems: 1 interconnects: - maxItems: 2 + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: - maxItems: 2 + items: + - const: mdp0-mem + - const: cpu-cfg patternProperties: "^display-controller@[0-9a-f]+$": @@ -91,9 +95,9 @@ examples: reg = <0x0ae00000 0x1000>; reg-names = "mdss"; - interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, - <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; - interconnect-names = "mdp0-mem", "mdp1-mem"; + interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>; + interconnect-names = "mdp0-mem", "cpu-cfg"; resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; diff --git a/Bindings/display/msm/qcom,sm8650-mdss.yaml b/Bindings/display/msm/qcom,sm8650-mdss.yaml index 24cece1e888..a1c53e19103 100644 --- a/Bindings/display/msm/qcom,sm8650-mdss.yaml +++ b/Bindings/display/msm/qcom,sm8650-mdss.yaml @@ -29,10 +29,14 @@ properties: maxItems: 1 interconnects: - maxItems: 2 + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus interconnect-names: - maxItems: 2 + items: + - const: mdp0-mem + - const: cpu-cfg patternProperties: "^display-controller@[0-9a-f]+$": @@ -75,12 +79,17 @@ examples: #include #include #include + #include display-subsystem@ae00000 { compatible = "qcom,sm8650-mdss"; reg = <0x0ae00000 0x1000>; reg-names = "mdss"; + interconnects = <&mmss_noc MASTER_MDP 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_DISPLAY_CFG 0>; + interconnect-names = "mdp0-mem", "cpu-cfg"; + resets = <&dispcc_core_bcr>; power-domains = <&dispcc_gdsc>; diff --git a/Bindings/display/panel/apple,summit.yaml b/Bindings/display/panel/apple,summit.yaml new file mode 100644 index 00000000000..f081755325e --- /dev/null +++ b/Bindings/display/panel/apple,summit.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/apple,summit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple "Summit" display panel + +maintainers: + - Sasha Finkelstein + +description: + An OLED panel used as a touchbar on certain Apple laptops. + Contains a backlight device, which controls brightness of the panel itself. + The backlight common properties are included for this reason + +allOf: + - $ref: panel-common.yaml# + - $ref: /schemas/leds/backlight/common.yaml# + +properties: + compatible: + items: + - enum: + - apple,j293-summit + - apple,j493-summit + - const: apple,summit + + reg: + maxItems: 1 + +required: + - compatible + - reg + - max-brightness + - port + +unevaluatedProperties: false + +examples: + - | + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "apple,j293-summit", "apple,summit"; + reg = <0>; + max-brightness = <255>; + + port { + endpoint { + remote-endpoint = <&dfr_bridge_out>; + }; + }; + }; + }; +... diff --git a/Bindings/display/panel/himax,hx83102.yaml b/Bindings/display/panel/himax,hx83102.yaml index c649fb08583..e4c1aa5deab 100644 --- a/Bindings/display/panel/himax,hx83102.yaml +++ b/Bindings/display/panel/himax,hx83102.yaml @@ -18,8 +18,14 @@ properties: - enum: # Boe nv110wum-l60 11.0" WUXGA TFT LCD panel - boe,nv110wum-l60 + # CSOT pna957qt1-1 10.95" WUXGA TFT LCD panel + - csot,pna957qt1-1 # IVO t109nw41 11.0" WUXGA TFT LCD panel - ivo,t109nw41 + # KINGDISPLAY KD110N11-51IE 10.95" WUXGA TFT LCD panel + - kingdisplay,kd110n11-51ie + # STARRY 2082109QFH040022-50E 10.95" WUXGA TFT LCD panel + - starry,2082109qfh040022-50e # STARRY himax83102-j02 10.51" WUXGA TFT LCD panel - starry,himax83102-j02 - const: himax,hx83102 diff --git a/Bindings/display/panel/mitsubishi,aa104xd12.yaml b/Bindings/display/panel/mitsubishi,aa104xd12.yaml index 3623ffa6518..96621b89ae9 100644 --- a/Bindings/display/panel/mitsubishi,aa104xd12.yaml +++ b/Bindings/display/panel/mitsubishi,aa104xd12.yaml @@ -33,7 +33,9 @@ properties: description: Reference to the regulator powering the panel VCC pins. data-mapping: - const: jeida-24 + enum: + - jeida-18 + - jeida-24 width-mm: const: 210 @@ -41,6 +43,7 @@ properties: height-mm: const: 158 + backlight: true panel-timing: true port: true @@ -48,7 +51,6 @@ additionalProperties: false required: - compatible - - vcc-supply - data-mapping - width-mm - height-mm diff --git a/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml b/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml index e80fc700698..548f5ac1450 100644 --- a/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml +++ b/Bindings/display/panel/panel-simple-lvds-dual-ports.yaml @@ -40,6 +40,8 @@ properties: - auo,g185han01 # AU Optronics Corporation 19.0" (1280x1024) TFT LCD panel - auo,g190ean01 + # BOE AV123Z7M-N17 12.3" (1920x720) LVDS TFT LCD panel + - boe,av123z7m-n17 # Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel - koe,tx26d202vm0bwa # Lincoln Technology Solutions, LCD185-101CT 10.1" TFT 1920x1200 diff --git a/Bindings/display/panel/panel-simple.yaml b/Bindings/display/panel/panel-simple.yaml index e3ee3a332bb..b0de4fd6f3d 100644 --- a/Bindings/display/panel/panel-simple.yaml +++ b/Bindings/display/panel/panel-simple.yaml @@ -63,6 +63,8 @@ properties: - auo,t215hvn01 # Shanghai AVIC Optoelectronics 7" 1024x600 color TFT-LCD panel - avic,tm070ddh03 + # BOE AV101HDT-a10 10.1" 1280x720 LVDS panel + - boe,av101hdt-a10 # BOE BP082WX1-100 8.2" WXGA (1280x800) LVDS panel - boe,bp082wx1-100 # BOE BP101WX1-100 10.1" WXGA (1280x800) LVDS panel diff --git a/Bindings/display/panel/raydium,rm67200.yaml b/Bindings/display/panel/raydium,rm67200.yaml new file mode 100644 index 00000000000..54c9c0ef45e --- /dev/null +++ b/Bindings/display/panel/raydium,rm67200.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/raydium,rm67200.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Raydium RM67200 based MIPI-DSI panels + +maintainers: + - Sebastian Reichel + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - wanchanglong,w552793baa + - const: raydium,rm67200 + + reg: + maxItems: 1 + + vdd-supply: + description: 2.8V Logic voltage + + iovcc-supply: + description: 1.8V IO voltage + + vsp-supply: + description: positive 5.5V voltage + + vsn-supply: + description: negative 5.5V voltage + + backlight: true + port: true + reset-gpios: true + +required: + - compatible + - port + - reg + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "wanchanglong,w552793baa", "raydium,rm67200"; + reg = <0>; + + vdd-supply = <®ulator1>; + iovcc-supply = <®ulator2>; + vsp-supply = <®ulator3>; + vsn-supply = <®ulator4>; + reset-gpios = <&gpiobank 42 GPIO_ACTIVE_LOW>; + + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/Bindings/display/panel/visionox,rm692e5.yaml b/Bindings/display/panel/visionox,rm692e5.yaml new file mode 100644 index 00000000000..d4b4672815f --- /dev/null +++ b/Bindings/display/panel/visionox,rm692e5.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/visionox,rm692e5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Visionox RM692E5 6.55" 2400x1080 120Hz MIPI-DSI Panel + +maintainers: + - Danila Tikhonov + +description: + The Visionox RM692E5 is a generic DSI Panel IC used to control + AMOLED panels. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + oneOf: + - enum: + - visionox,rm692e5 + - items: + - enum: + - nothing,rm692e5-spacewar + - const: visionox,rm692e5 + + reg: + maxItems: 1 + + vdd-supply: + description: 3.3V source voltage rail + + vddio-supply: + description: 1.8V I/O source voltage rail + + reset-gpios: true + port: true + +required: + - compatible + - reg + - reset-gpios + - vdd-supply + - vddio-supply + - port + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "nothing,rm692e5-spacewar", + "visionox,rm692e5"; + reg = <0>; + + reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>; + + vdd-supply = <&vdd_oled>; + vddio-supply = <&vdd_io_oled>; + + port { + panel_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; + }; + +... diff --git a/Bindings/display/renesas,du.yaml b/Bindings/display/renesas,du.yaml index 3880b4c2ea9..c27dfea7fc6 100644 --- a/Bindings/display/renesas,du.yaml +++ b/Bindings/display/renesas,du.yaml @@ -47,12 +47,26 @@ properties: maxItems: 1 # See compatible-specific constraints below. - clocks: true - clock-names: true + clocks: + minItems: 1 + maxItems: 8 + + clock-names: + minItems: 1 + maxItems: 8 + interrupts: + minItems: 1 + maxItems: 4 description: Interrupt specifiers, one per DU channel - resets: true - reset-names: true + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + minItems: 1 + maxItems: 2 power-domains: maxItems: 1 @@ -74,7 +88,7 @@ properties: renesas,cmms: $ref: /schemas/types.yaml#/definitions/phandle-array - minItems: 1 + minItems: 2 maxItems: 4 items: maxItems: 1 @@ -174,6 +188,7 @@ allOf: - pattern: '^dclkin\.[01]$' interrupts: + minItems: 2 maxItems: 2 resets: @@ -229,6 +244,7 @@ allOf: - pattern: '^dclkin\.[01]$' interrupts: + minItems: 2 maxItems: 2 resets: @@ -282,6 +298,7 @@ allOf: - pattern: '^dclkin\.[01]$' interrupts: + minItems: 2 maxItems: 2 resets: @@ -336,6 +353,7 @@ allOf: - pattern: '^dclkin\.[01]$' interrupts: + minItems: 2 maxItems: 2 resets: @@ -397,6 +415,7 @@ allOf: - pattern: '^dclkin\.[012]$' interrupts: + minItems: 3 maxItems: 3 resets: @@ -461,9 +480,11 @@ allOf: - pattern: '^dclkin\.[0123]$' interrupts: + minItems: 4 maxItems: 4 resets: + minItems: 2 maxItems: 2 reset-names: @@ -534,9 +555,11 @@ allOf: - pattern: '^dclkin\.[012]$' interrupts: + minItems: 3 maxItems: 3 resets: + minItems: 2 maxItems: 2 reset-names: @@ -605,9 +628,11 @@ allOf: - pattern: '^dclkin\.[013]$' interrupts: + minItems: 3 maxItems: 3 resets: + minItems: 2 maxItems: 2 reset-names: @@ -726,6 +751,7 @@ allOf: - pattern: '^dclkin\.[01]$' interrupts: + minItems: 2 maxItems: 2 resets: diff --git a/Bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml b/Bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml index d8e761865f2..96b4b088eeb 100644 --- a/Bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml +++ b/Bindings/display/rockchip/rockchip,rk3588-dw-hdmi-qp.yaml @@ -29,6 +29,7 @@ allOf: properties: compatible: enum: + - rockchip,rk3576-dw-hdmi-qp - rockchip,rk3588-dw-hdmi-qp reg: @@ -156,7 +157,7 @@ examples: , ; interrupt-names = "avp", "cec", "earc", "main", "hpd"; - phys = <&hdptxphy_hdmi0>; + phys = <&hdptxphy0>; power-domains = <&power RK3588_PD_VO1>; resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; reset-names = "ref", "hdp"; diff --git a/Bindings/display/rockchip/rockchip-vop2.yaml b/Bindings/display/rockchip/rockchip-vop2.yaml index 2531726af30..f546d481b7e 100644 --- a/Bindings/display/rockchip/rockchip-vop2.yaml +++ b/Bindings/display/rockchip/rockchip-vop2.yaml @@ -14,12 +14,14 @@ description: maintainers: - Sandy Huang - Heiko Stuebner + - Andy Yan properties: compatible: enum: - rockchip,rk3566-vop - rockchip,rk3568-vop + - rockchip,rk3576-vop - rockchip,rk3588-vop reg: @@ -37,10 +39,21 @@ properties: - const: gamma-lut interrupts: - maxItems: 1 + minItems: 1 + maxItems: 4 description: - The VOP interrupt is shared by several interrupt sources, such as - frame start (VSYNC), line flag and other status interrupts. + For VOP version under rk3576, the interrupt is shared by several interrupt + sources, such as frame start (VSYNC), line flag and other interrupt status. + For VOP version from rk3576 there is a system interrupt for bus error, and + every video port has it's independent interrupts for vsync and other video + port related error interrupts. + + interrupt-names: + items: + - const: sys + - const: vp0 + - const: vp1 + - const: vp2 # See compatible-specific constraints below. clocks: @@ -53,6 +66,8 @@ properties: - description: Pixel clock for video port 2. - description: Pixel clock for video port 3. - description: Peripheral(vop grf/dsi) clock. + - description: Alternative pixel clock provided by HDMI0 PHY PLL. + - description: Alternative pixel clock provided by HDMI1 PHY PLL. clock-names: minItems: 5 @@ -64,6 +79,8 @@ properties: - const: dclk_vp2 - const: dclk_vp3 - const: pclk_vop + - const: pll_hdmiphy0 + - const: pll_hdmiphy1 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle @@ -120,43 +137,100 @@ allOf: properties: compatible: contains: - const: rockchip,rk3588-vop + enum: + - rockchip,rk3566-vop + - rockchip,rk3568-vop then: properties: clocks: - minItems: 7 + maxItems: 5 + clock-names: - minItems: 7 + maxItems: 5 + + interrupts: + maxItems: 1 + + interrupt-names: false ports: required: - port@0 - port@1 - port@2 - - port@3 + + rockchip,vo1-grf: false + rockchip,vop-grf: false + rockchip,pmu: false required: - rockchip,grf - - rockchip,vo1-grf - - rockchip,vop-grf - - rockchip,pmu - else: + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3576-vop + then: properties: + clocks: + maxItems: 5 + + clock-names: + maxItems: 5 + + interrupts: + minItems: 4 + + interrupt-names: + minItems: 4 + + ports: + required: + - port@0 + - port@1 + - port@2 + rockchip,vo1-grf: false rockchip,vop-grf: false - rockchip,pmu: false + required: + - rockchip,grf + - rockchip,pmu + + - if: + properties: + compatible: + contains: + const: rockchip,rk3588-vop + then: + properties: clocks: - maxItems: 5 + minItems: 7 + maxItems: 9 + clock-names: - maxItems: 5 + minItems: 7 + maxItems: 9 + + interrupts: + maxItems: 1 + + interrupt-names: false ports: required: - port@0 - port@1 - port@2 + - port@3 + + required: + - rockchip,grf + - rockchip,vo1-grf + - rockchip,vop-grf + - rockchip,pmu additionalProperties: false @@ -184,6 +258,7 @@ examples: "dclk_vp1", "dclk_vp2"; power-domains = <&power RK3568_PD_VO>; + rockchip,grf = <&grf>; iommus = <&vop_mmu>; vop_out: ports { #address-cells = <1>; diff --git a/Bindings/display/tegra/nvidia,tegra114-mipi.yaml b/Bindings/display/tegra/nvidia,tegra114-mipi.yaml index f448624dd77..193ddb10528 100644 --- a/Bindings/display/tegra/nvidia,tegra114-mipi.yaml +++ b/Bindings/display/tegra/nvidia,tegra114-mipi.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - nvidia,tegra114-mipi + - nvidia,tegra124-mipi - nvidia,tegra210-mipi - nvidia,tegra186-mipi diff --git a/Bindings/dma/atmel,at91sam9g45-dma.yaml b/Bindings/dma/atmel,at91sam9g45-dma.yaml new file mode 100644 index 00000000000..a58dc407311 --- /dev/null +++ b/Bindings/dma/atmel,at91sam9g45-dma.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/atmel,at91sam9g45-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Direct Memory Access Controller (DMA) + +maintainers: + - Ludovic Desroches + +description: + The Atmel Direct Memory Access Controller (DMAC) transfers data from a source + peripheral to a destination peripheral over one or more AMBA buses. One channel + is required for each source/destination pair. In the most basic configuration, + the DMAC has one master interface and one channel. The master interface reads + the data from a source and writes it to a destination. Two AMBA transfers are + required for each DMAC data transfer. This is also known as a dual-access transfer. + The DMAC is programmed via the APB interface. + +properties: + compatible: + enum: + - atmel,at91sam9g45-dma + - atmel,at91sam9rl-dma + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#dma-cells": + description: + Must be <2>, used to represent the number of integer cells in the dma + property of client devices. The two cells in order are + 1. The first cell represents the channel number. + 2. The second cell is 0 for RX and 1 for TX transfers. + const: 2 + + clocks: + maxItems: 1 + + clock-names: + const: dma_clk + +required: + - compatible + - reg + - interrupts + - "#dma-cells" + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + dma-controller@ffffec00 { + compatible = "atmel,at91sam9g45-dma"; + reg = <0xffffec00 0x200>; + interrupts = <21>; + #dma-cells = <2>; + clocks = <&pmc 2 20>; + clock-names = "dma_clk"; + }; + +... diff --git a/Bindings/dma/atmel,sama5d4-dma.yaml b/Bindings/dma/atmel,sama5d4-dma.yaml index 9ca1c5d1f00..73fc13b902b 100644 --- a/Bindings/dma/atmel,sama5d4-dma.yaml +++ b/Bindings/dma/atmel,sama5d4-dma.yaml @@ -32,6 +32,9 @@ properties: - microchip,sam9x60-dma - microchip,sam9x7-dma - const: atmel,sama5d4-dma + - items: + - const: microchip,sama7d65-dma + - const: microchip,sama7g5-dma "#dma-cells": description: | diff --git a/Bindings/dma/atmel-dma.txt b/Bindings/dma/atmel-dma.txt deleted file mode 100644 index f69bcf5a634..00000000000 --- a/Bindings/dma/atmel-dma.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Atmel Direct Memory Access Controller (DMA) - -Required properties: -- compatible: Should be "atmel,-dma". -- reg: Should contain DMA registers location and length. -- interrupts: Should contain DMA interrupt. -- #dma-cells: Must be <2>, used to represent the number of integer cells in -the dmas property of client devices. - -Example: - -dma0: dma@ffffec00 { - compatible = "atmel,at91sam9g45-dma"; - reg = <0xffffec00 0x200>; - interrupts = <21>; - #dma-cells = <2>; -}; - -DMA clients connected to the Atmel DMA controller must use the format -described in the dma.txt file, using a three-cell specifier for each channel: -a phandle plus two integer cells. -The three cells in order are: - -1. A phandle pointing to the DMA controller. -2. The memory interface (16 most significant bits), the peripheral interface -(16 less significant bits). -3. Parameters for the at91 DMA configuration register which are device -dependent: - - bit 7-0: peripheral identifier for the hardware handshaking interface. The - identifier can be different for tx and rx. - - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP. - -Example: - -i2c0@i2c@f8010000 { - compatible = "atmel,at91sam9x5-i2c"; - reg = <0xf8010000 0x100>; - interrupts = <9 4 6>; - dmas = <&dma0 1 7>, - <&dma0 1 8>; - dma-names = "tx", "rx"; -}; diff --git a/Bindings/dma/fsl,edma.yaml b/Bindings/dma/fsl,edma.yaml index 4f925469533..950e8fa4f4a 100644 --- a/Bindings/dma/fsl,edma.yaml +++ b/Bindings/dma/fsl,edma.yaml @@ -27,6 +27,14 @@ properties: - fsl,imx93-edma4 - fsl,imx95-edma5 - nxp,s32g2-edma + - items: + - enum: + - fsl,imx94-edma3 + - const: fsl,imx93-edma3 + - items: + - enum: + - fsl,imx94-edma5 + - const: fsl,imx95-edma5 - items: - const: fsl,ls1028a-edma - const: fsl,vf610-edma diff --git a/Bindings/dma/fsl,elo-dma.yaml b/Bindings/dma/fsl,elo-dma.yaml new file mode 100644 index 00000000000..92288d76d51 --- /dev/null +++ b/Bindings/dma/fsl,elo-dma.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/fsl,elo-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Elo DMA Controller + +maintainers: + - J. Neuschäfer + +description: + This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx + series chips such as mpc8315, mpc8349, mpc8379 etc. + +properties: + compatible: + items: + - enum: + - fsl,mpc8313-dma + - fsl,mpc8315-dma + - fsl,mpc8323-dma + - fsl,mpc8347-dma + - fsl,mpc8349-dma + - fsl,mpc8360-dma + - fsl,mpc8377-dma + - fsl,mpc8378-dma + - fsl,mpc8379-dma + - const: fsl,elo-dma + + reg: + items: + - description: + DMA General Status Register, i.e. DGSR which contains status for + all the 4 DMA channels. + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Controller index. 0 for controller @ 0x8100. + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + interrupts: + maxItems: 1 + description: Controller interrupt. + +required: + - compatible + - reg + +patternProperties: + "^dma-channel@[0-9a-f]+$": + type: object + additionalProperties: false + + properties: + compatible: + oneOf: + # native DMA channel + - items: + - enum: + - fsl,mpc8315-dma-channel + - fsl,mpc8323-dma-channel + - fsl,mpc8347-dma-channel + - fsl,mpc8349-dma-channel + - fsl,mpc8360-dma-channel + - fsl,mpc8377-dma-channel + - fsl,mpc8378-dma-channel + - fsl,mpc8379-dma-channel + - const: fsl,elo-dma-channel + + # audio DMA channel, see fsl,ssi.yaml + - const: fsl,ssi-dma-channel + + reg: + maxItems: 1 + + cell-index: + description: DMA channel index starts at 0. + + interrupts: + maxItems: 1 + description: + Per-channel interrupt. Only necessary if no controller interrupt has + been provided. + +additionalProperties: false + +examples: + - | + #include + + dma@82a8 { + compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x8100 0x1a4>; + interrupts = <71 IRQ_TYPE_LEVEL_LOW>; + cell-index = <0>; + + dma-channel@0 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0 0x80>; + cell-index = <0>; + interrupts = <71 IRQ_TYPE_LEVEL_LOW>; + }; + + dma-channel@80 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupts = <71 IRQ_TYPE_LEVEL_LOW>; + }; + + dma-channel@100 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupts = <71 IRQ_TYPE_LEVEL_LOW>; + }; + + dma-channel@180 { + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupts = <71 IRQ_TYPE_LEVEL_LOW>; + }; + }; + +... diff --git a/Bindings/dma/fsl,elo3-dma.yaml b/Bindings/dma/fsl,elo3-dma.yaml new file mode 100644 index 00000000000..0f5e475657a --- /dev/null +++ b/Bindings/dma/fsl,elo3-dma.yaml @@ -0,0 +1,125 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/fsl,elo3-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Elo3 DMA Controller + +maintainers: + - J. Neuschäfer + +description: + DMA controller which has same function as EloPlus except that Elo3 has 8 + channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx + series chips, such as t1040, t4240, b4860. + +properties: + compatible: + const: fsl,elo3-dma + + reg: + items: + - description: + DMA General Status Registers starting from DGSR0, for channel 1~4 + - description: + DMA General Status Registers starting from DGSR1, for channel 5~8 + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + interrupts: + maxItems: 1 + +patternProperties: + "^dma-channel@[0-9a-f]+$": + type: object + additionalProperties: false + + properties: + compatible: + enum: + # native DMA channel + - fsl,eloplus-dma-channel + + # audio DMA channel, see fsl,ssi.yaml + - fsl,ssi-dma-channel + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + description: + Per-channel interrupt. Only necessary if no controller interrupt has + been provided. + +additionalProperties: false + +examples: + - | + #include + + dma@100300 { + compatible = "fsl,elo3-dma"; + reg = <0x100300 0x4>, + <0x100600 0x4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x100100 0x500>; + + dma-channel@0 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x0 0x80>; + interrupts = <28 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + + dma-channel@80 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + + dma-channel@100 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + + dma-channel@180 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + interrupts = <31 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + + dma-channel@300 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x300 0x80>; + interrupts = <76 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + + dma-channel@380 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x380 0x80>; + interrupts = <77 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + + dma-channel@400 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x400 0x80>; + interrupts = <78 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + + dma-channel@480 { + compatible = "fsl,eloplus-dma-channel"; + reg = <0x480 0x80>; + interrupts = <79 IRQ_TYPE_EDGE_FALLING 0 0>; + }; + }; + +... diff --git a/Bindings/dma/fsl,eloplus-dma.yaml b/Bindings/dma/fsl,eloplus-dma.yaml new file mode 100644 index 00000000000..8992f244c4d --- /dev/null +++ b/Bindings/dma/fsl,eloplus-dma.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/fsl,eloplus-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale EloPlus DMA Controller + +maintainers: + - J. Neuschäfer + +description: + This is a 4-channel DMA controller with extended addresses and chaining, + mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as + mpc8540, mpc8641 p4080, bsc9131 etc. + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,mpc8540-dma + - fsl,mpc8541-dma + - fsl,mpc8548-dma + - fsl,mpc8555-dma + - fsl,mpc8560-dma + - fsl,mpc8572-dma + - fsl,mpc8641-dma + - const: fsl,eloplus-dma + - const: fsl,eloplus-dma + + reg: + items: + - description: + DMA General Status Register, i.e. DGSR which contains + status for all the 4 DMA channels + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000 + + ranges: true + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + interrupts: + maxItems: 1 + description: Controller interrupt. + +patternProperties: + "^dma-channel@[0-9a-f]+$": + type: object + additionalProperties: false + + properties: + compatible: + oneOf: + # native DMA channel + - items: + - enum: + - fsl,mpc8540-dma-channel + - fsl,mpc8541-dma-channel + - fsl,mpc8548-dma-channel + - fsl,mpc8555-dma-channel + - fsl,mpc8560-dma-channel + - fsl,mpc8572-dma-channel + - const: fsl,eloplus-dma-channel + + # audio DMA channel, see fsl,ssi.yaml + - const: fsl,ssi-dma-channel + + reg: + maxItems: 1 + + cell-index: + description: DMA channel index starts at 0. + + interrupts: + maxItems: 1 + description: + Per-channel interrupt. Only necessary if no controller interrupt has + been provided. + +additionalProperties: false + +examples: + - | + #include + + dma@21300 { + compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; + reg = <0x21300 4>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x21100 0x200>; + cell-index = <0>; + + dma-channel@0 { + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; + reg = <0 0x80>; + cell-index = <0>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + }; + + dma-channel@80 { + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; + reg = <0x80 0x80>; + cell-index = <1>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; + }; + + dma-channel@100 { + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; + reg = <0x100 0x80>; + cell-index = <2>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; + }; + + dma-channel@180 { + compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; + reg = <0x180 0x80>; + cell-index = <3>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + }; + }; + +... diff --git a/Bindings/dma/fsl,mxs-dma.yaml b/Bindings/dma/fsl,mxs-dma.yaml index a17cf2360dd..75a7d955669 100644 --- a/Bindings/dma/fsl,mxs-dma.yaml +++ b/Bindings/dma/fsl,mxs-dma.yaml @@ -31,6 +31,12 @@ properties: - fsl,imx6q-dma-apbh - fsl,imx6sx-dma-apbh - fsl,imx7d-dma-apbh + - fsl,imx8dxl-dma-apbh + - fsl,imx8mm-dma-apbh + - fsl,imx8mn-dma-apbh + - fsl,imx8mp-dma-apbh + - fsl,imx8mq-dma-apbh + - fsl,imx8qm-dma-apbh - fsl,imx8qxp-dma-apbh - const: fsl,imx28-dma-apbh - enum: diff --git a/Bindings/dma/snps,dw-axi-dmac.yaml b/Bindings/dma/snps,dw-axi-dmac.yaml index 525f5f3932f..935735a59af 100644 --- a/Bindings/dma/snps,dw-axi-dmac.yaml +++ b/Bindings/dma/snps,dw-axi-dmac.yaml @@ -59,6 +59,8 @@ properties: minimum: 1 maximum: 8 + dma-noncoherent: true + resets: minItems: 1 maxItems: 2 diff --git a/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml b/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml index ac3198953b8..b5399c65a73 100644 --- a/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml +++ b/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml @@ -75,7 +75,6 @@ additionalProperties: false examples: - | - #include fpd_dma_chan1: dma-controller@fd500000 { compatible = "xlnx,zynqmp-dma-1.0"; @@ -84,7 +83,7 @@ examples: interrupts = <0 117 0x4>; #dma-cells = <1>; clock-names = "clk_main", "clk_apb"; - clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; + clocks = <&zynqmp_clk 19>, <&zynqmp_clk 31>; xlnx,bus-width = <128>; dma-coherent; }; diff --git a/Bindings/dsp/fsl,dsp.yaml b/Bindings/dsp/fsl,dsp.yaml index ab93ffd3d2e..b8693e4b4b0 100644 --- a/Bindings/dsp/fsl,dsp.yaml +++ b/Bindings/dsp/fsl,dsp.yaml @@ -82,6 +82,15 @@ properties: description: Phandle to syscon block which provide access for processor enablement + resets: + minItems: 1 + + reset-names: + minItems: 1 + items: + - const: runstall + - const: softreset + required: - compatible - reg @@ -164,6 +173,17 @@ allOf: - const: txdb1 - const: rxdb0 - const: rxdb1 + - if: + properties: + compatible: + contains: + enum: + - fsl,imx8mp-dsp + - fsl,imx8mp-hifi4 + then: + required: + - resets + - reset-names additionalProperties: false @@ -186,6 +206,7 @@ examples: }; - | #include + #include dsp_reserved: dsp@92400000 { reg = <0x92400000 0x1000000>; no-map; @@ -220,5 +241,6 @@ examples: <&mu2 3 0>; memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>, <&dsp_vdev0vring1>, <&dsp_reserved>; - fsl,dsp-ctrl = <&audio_blk_ctrl>; + resets = <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>; + reset-names = "runstall"; }; diff --git a/Bindings/dts-coding-style.rst b/Bindings/dts-coding-style.rst index 4772ded8a98..202acac0507 100644 --- a/Bindings/dts-coding-style.rst +++ b/Bindings/dts-coding-style.rst @@ -133,6 +133,9 @@ The above-described ordering follows this approach: 3. Status is the last information to annotate that device node is or is not finished (board resources are needed). +The individual properties inside each group shall use natural sort order by +the property name. + Example:: /* SoC DTSI */ @@ -158,7 +161,10 @@ Example:: /* Board DTS */ &device_node { - vdd-supply = <&board_vreg1>; + vdd-0v9-supply = <&board_vreg1>; + vdd-1v8-supply = <&board_vreg4>; + vdd-3v3-supply = <&board_vreg2>; + vdd-12v-supply = <&board_vreg3>; status = "okay"; } diff --git a/Bindings/edac/altr,socfpga-ecc-manager.yaml b/Bindings/edac/altr,socfpga-ecc-manager.yaml new file mode 100644 index 00000000000..ec4634c5fa8 --- /dev/null +++ b/Bindings/edac/altr,socfpga-ecc-manager.yaml @@ -0,0 +1,323 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (C) 2025 Altera Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/altr,socfpga-ecc-manager.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera SoCFPGA ECC Manager + +maintainers: + - Matthew Gerlach + +description: + This binding describes the device tree nodes required for the Altera SoCFPGA + ECC Manager for the Cyclone5, Arria5, Arria10, Stratix10, and Agilex chip + families. + +properties: + + compatible: + oneOf: + - items: + - const: altr,socfpga-s10-ecc-manager + - const: altr,socfpga-a10-ecc-manager + - const: altr,socfpga-a10-ecc-manager + - const: altr,socfpga-ecc-manager + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + ranges: true + + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to Stratix10 System Manager Block with the ECC manager registers + + sdramedac: + type: object + additionalProperties: false + + properties: + compatible: + enum: + - altr,sdram-edac-a10 + - altr,sdram-edac-s10 + + interrupts: + minItems: 1 + maxItems: 2 + + altr,sdr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to SDRAM parent + + required: + - compatible + - interrupts + - altr,sdr-syscon + +patternProperties: + "^ocram-ecc@[a-f0-9]+$": + type: object + additionalProperties: false + + properties: + compatible: + oneOf: + - items: + - const: altr,socfpga-s10-ocram-ecc + - const: altr,socfpga-a10-ocram-ecc + - const: altr,socfpga-a10-ocram-ecc + - const: altr,socfpga-ocram-ecc + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + iram: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to OCRAM parent + + altr,ecc-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to OCRAM parent + + required: + - compatible + - reg + - interrupts + + "^usb[0-9]-ecc@[a-f0-9]+$": + type: object + additionalProperties: false + + properties: + compatible: + oneOf: + - items: + - const: altr,socfpga-s10-usb-ecc + - const: altr,socfpga-usb-ecc + - const: altr,socfpga-usb-ecc + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + altr,ecc-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to USB parent + + required: + - compatible + - reg + - interrupts + - altr,ecc-parent + + "^emac[0-9]-[t,r]x-ecc@[a-f0-9]+$": + type: object + additionalProperties: false + + properties: + compatible: + oneOf: + - items: + - const: altr,socfpga-s10-eth-mac-ecc + - const: altr,socfpga-eth-mac-ecc + - const: altr,socfpga-eth-mac-ecc + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + altr,ecc-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to ethernet parent + + required: + - compatible + - reg + - interrupts + - altr,ecc-parent + + "^sdmmc[a-f]-ecc@[a-f0-9]+$": + type: object + additionalProperties: false + + properties: + compatible: + oneOf: + - items: + - const: altr,socfpga-s10-sdmmc-ecc + - const: altr,socfpga-sdmmc-ecc + - const: altr,socfpga-sdmmc-ecc + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 4 + + altr,ecc-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to SD/MMC parent + + required: + - compatible + - reg + - interrupts + - altr,ecc-parent + + "^l2-ecc@[a-f0-9]+$": + type: object + additionalProperties: false + + properties: + compatible: + enum: + - altr,socfpga-a10-l2-ecc + - altr,socfpga-l2-ecc + + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + required: + - compatible + - reg + - interrupts + + "^dma-ecc@[a-f0-9]+$": + type: object + additionalProperties: false + + properties: + compatible: + const: altr,socfpga-dma-ecc + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + altr,ecc-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to SD/MMC parent + + required: + - compatible + - reg + - interrupts + - altr,ecc-parent + +if: + properties: + compatible: + contains: + const: altr,socfpga-ecc-manager +then: + required: + - compatible + - "#address-cells" + - "#size-cells" + - ranges + +else: + required: + - compatible + - "#address-cells" + - "#size-cells" + - interrupts + - interrupt-controller + - "#interrupt-cells" + - ranges + - altr,sysmgr-syscon + +additionalProperties: false + +examples: + - | + #include + #include + eccmgr { + compatible = "altr,socfpga-s10-ecc-manager", + "altr,socfpga-a10-ecc-manager"; + altr,sysmgr-syscon = <&sysmgr>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + ranges; + + sdramedac { + compatible = "altr,sdram-edac-s10"; + altr,sdr-syscon = <&sdr>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + }; + + ocram-ecc@ff8cc000 { + compatible = "altr,socfpga-s10-ocram-ecc", + "altr,socfpga-a10-ocram-ecc"; + reg = <0xff8cc000 0x100>; + altr,ecc-parent = <&ocram>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + }; + + usb0-ecc@ff8c4000 { + compatible = "altr,socfpga-s10-usb-ecc", + "altr,socfpga-usb-ecc"; + reg = <0xff8c4000 0x100>; + altr,ecc-parent = <&usb0>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-rx-ecc@ff8c0000 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0000 0x100>; + altr,ecc-parent = <&gmac0>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + }; + + emac0-tx-ecc@ff8c0400 { + compatible = "altr,socfpga-s10-eth-mac-ecc", + "altr,socfpga-eth-mac-ecc"; + reg = <0xff8c0400 0x100>; + altr,ecc-parent = <&gmac0>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + }; + + sdmmca-ecc@ff8c8c00 { + compatible = "altr,socfpga-s10-sdmmc-ecc", + "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c8c00 0x100>; + altr,ecc-parent = <&mmc>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, + <15 IRQ_TYPE_LEVEL_HIGH>; + }; + }; diff --git a/Bindings/edac/socfpga-eccmgr.txt b/Bindings/edac/socfpga-eccmgr.txt deleted file mode 100644 index 8f52206cfd2..00000000000 --- a/Bindings/edac/socfpga-eccmgr.txt +++ /dev/null @@ -1,383 +0,0 @@ -Altera SoCFPGA ECC Manager -This driver uses the EDAC framework to implement the SOCFPGA ECC Manager. -The ECC Manager counts and corrects single bit errors and counts/handles -double bit errors which are uncorrectable. - -Cyclone5 and Arria5 ECC Manager -Required Properties: -- compatible : Should be "altr,socfpga-ecc-manager" -- #address-cells: must be 1 -- #size-cells: must be 1 -- ranges : standard definition, should translate from local addresses - -Subcomponents: - -L2 Cache ECC -Required Properties: -- compatible : Should be "altr,socfpga-l2-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. Note the rising edge type. - -On Chip RAM ECC -Required Properties: -- compatible : Should be "altr,socfpga-ocram-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- iram : phandle to On-Chip RAM definition. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. Note the rising edge type. - -Example: - - eccmgr: eccmgr@ffd08140 { - compatible = "altr,socfpga-ecc-manager"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - l2-ecc@ffd08140 { - compatible = "altr,socfpga-l2-ecc"; - reg = <0xffd08140 0x4>; - interrupts = <0 36 1>, <0 37 1>; - }; - - ocram-ecc@ffd08144 { - compatible = "altr,socfpga-ocram-ecc"; - reg = <0xffd08144 0x4>; - iram = <&ocram>; - interrupts = <0 178 1>, <0 179 1>; - }; - }; - -Arria10 SoCFPGA ECC Manager -The Arria10 SoC ECC Manager handles the IRQs for each peripheral -in a shared register instead of individual IRQs like the Cyclone5 -and Arria5. Therefore the device tree is different as well. - -Required Properties: -- compatible : Should be "altr,socfpga-a10-ecc-manager" -- altr,sysgr-syscon : phandle to Arria10 System Manager Block - containing the ECC manager registers. -- #address-cells: must be 1 -- #size-cells: must be 1 -- interrupts : Should be single bit error interrupt, then double bit error - interrupt. -- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller -- #interrupt-cells : must be set to 2. -- ranges : standard definition, should translate from local addresses - -Subcomponents: - -L2 Cache ECC -Required Properties: -- compatible : Should be "altr,socfpga-a10-l2-ecc" -- reg : Address and size for ECC error interrupt clear registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -On-Chip RAM ECC -Required Properties: -- compatible : Should be "altr,socfpga-a10-ocram-ecc" -- reg : Address and size for ECC block registers. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -Ethernet FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-eth-mac-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent Ethernet node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -NAND FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-nand-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent NAND node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -DMA FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-dma-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent DMA node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -USB FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-usb-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent USB node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -QSPI FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-qspi-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent QSPI node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order. - -SDMMC FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-sdmmc-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent SD/MMC node. -- interrupts : Should be single bit error interrupt, then double bit error - interrupt, in this order for port A, and then single bit error interrupt, - then double bit error interrupt in this order for port B. - -Example: - - eccmgr: eccmgr@ffd06000 { - compatible = "altr,socfpga-a10-ecc-manager"; - altr,sysmgr-syscon = <&sysmgr>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, - <0 0 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - l2-ecc@ffd06010 { - compatible = "altr,socfpga-a10-l2-ecc"; - reg = <0xffd06010 0x4>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, - <32 IRQ_TYPE_LEVEL_HIGH>; - }; - - ocram-ecc@ff8c3000 { - compatible = "altr,socfpga-a10-ocram-ecc"; - reg = <0xff8c3000 0x90>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, - <33 IRQ_TYPE_LEVEL_HIGH> ; - }; - - emac0-rx-ecc@ff8c0800 { - compatible = "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0800 0x400>; - altr,ecc-parent = <&gmac0>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, - <36 IRQ_TYPE_LEVEL_HIGH>; - }; - - emac0-tx-ecc@ff8c0c00 { - compatible = "altr,socfpga-eth-mac-ecc"; - reg = <0xff8c0c00 0x400>; - altr,ecc-parent = <&gmac0>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, - <37 IRQ_TYPE_LEVEL_HIGH>; - }; - - nand-buf-ecc@ff8c2000 { - compatible = "altr,socfpga-nand-ecc"; - reg = <0xff8c2000 0x400>; - altr,ecc-parent = <&nand>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>, - <43 IRQ_TYPE_LEVEL_HIGH>; - }; - - nand-rd-ecc@ff8c2400 { - compatible = "altr,socfpga-nand-ecc"; - reg = <0xff8c2400 0x400>; - altr,ecc-parent = <&nand>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>, - <45 IRQ_TYPE_LEVEL_HIGH>; - }; - - nand-wr-ecc@ff8c2800 { - compatible = "altr,socfpga-nand-ecc"; - reg = <0xff8c2800 0x400>; - altr,ecc-parent = <&nand>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, - <44 IRQ_TYPE_LEVEL_HIGH>; - }; - - dma-ecc@ff8c8000 { - compatible = "altr,socfpga-dma-ecc"; - reg = <0xff8c8000 0x400>; - altr,ecc-parent = <&pdma>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, - <42 IRQ_TYPE_LEVEL_HIGH>; - - usb0-ecc@ff8c8800 { - compatible = "altr,socfpga-usb-ecc"; - reg = <0xff8c8800 0x400>; - altr,ecc-parent = <&usb0>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, - <34 IRQ_TYPE_LEVEL_HIGH>; - }; - - qspi-ecc@ff8c8400 { - compatible = "altr,socfpga-qspi-ecc"; - reg = <0xff8c8400 0x400>; - altr,ecc-parent = <&qspi>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, - <46 IRQ_TYPE_LEVEL_HIGH>; - }; - - sdmmc-ecc@ff8c2c00 { - compatible = "altr,socfpga-sdmmc-ecc"; - reg = <0xff8c2c00 0x400>; - altr,ecc-parent = <&mmc>; - interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, - <47 IRQ_TYPE_LEVEL_HIGH>, - <16 IRQ_TYPE_LEVEL_HIGH>, - <48 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - -Stratix10 SoCFPGA ECC Manager (ARM64) -The Stratix10 SoC ECC Manager handles the IRQs for each peripheral -in a shared register similar to the Arria10. However, Stratix10 ECC -requires access to registers that can only be read from Secure Monitor -with SMC calls. Therefore the device tree is slightly different. Note -that only 1 interrupt is sent in Stratix10 because the double bit errors -are treated as SErrors in ARM64 instead of IRQs in ARM32. - -Required Properties: -- compatible : Should be "altr,socfpga-s10-ecc-manager" -- altr,sysgr-syscon : phandle to Stratix10 System Manager Block - containing the ECC manager registers. -- interrupts : Should be single bit error interrupt. -- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller -- #interrupt-cells : must be set to 2. -- #address-cells: must be 1 -- #size-cells: must be 1 -- ranges : standard definition, should translate from local addresses - -Subcomponents: - -SDRAM ECC -Required Properties: -- compatible : Should be "altr,sdram-edac-s10" -- interrupts : Should be single bit error interrupt. - -On-Chip RAM ECC -Required Properties: -- compatible : Should be "altr,socfpga-s10-ocram-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent OCRAM node. -- interrupts : Should be single bit error interrupt. - -Ethernet FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-s10-eth-mac-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent Ethernet node. -- interrupts : Should be single bit error interrupt. - -NAND FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-s10-nand-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent NAND node. -- interrupts : Should be single bit error interrupt. - -DMA FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-s10-dma-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent DMA node. -- interrupts : Should be single bit error interrupt. - -USB FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-s10-usb-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent USB node. -- interrupts : Should be single bit error interrupt. - -SDMMC FIFO ECC -Required Properties: -- compatible : Should be "altr,socfpga-s10-sdmmc-ecc" -- reg : Address and size for ECC block registers. -- altr,ecc-parent : phandle to parent SD/MMC node. -- interrupts : Should be single bit error interrupt for port A - and then single bit error interrupt for port B. - -Example: - - eccmgr { - compatible = "altr,socfpga-s10-ecc-manager"; - altr,sysmgr-syscon = <&sysmgr>; - #address-cells = <1>; - #size-cells = <1>; - interrupts = <0 15 4>; - interrupt-controller; - #interrupt-cells = <2>; - ranges; - - sdramedac { - compatible = "altr,sdram-edac-s10"; - interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; - }; - - ocram-ecc@ff8cc000 { - compatible = "altr,socfpga-s10-ocram-ecc"; - reg = ; - altr,ecc-parent = <&ocram>; - interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; - }; - - emac0-rx-ecc@ff8c0000 { - compatible = "altr,socfpga-s10-eth-mac-ecc"; - reg = <0xff8c0000 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; - }; - - emac0-tx-ecc@ff8c0400 { - compatible = "altr,socfpga-s10-eth-mac-ecc"; - reg = <0xff8c0400 0x100>; - altr,ecc-parent = <&gmac0>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>' - }; - - nand-buf-ecc@ff8c8000 { - compatible = "altr,socfpga-s10-nand-ecc"; - reg = <0xff8c8000 0x100>; - altr,ecc-parent = <&nand>; - interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; - }; - - nand-rd-ecc@ff8c8400 { - compatible = "altr,socfpga-s10-nand-ecc"; - reg = <0xff8c8400 0x100>; - altr,ecc-parent = <&nand>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; - }; - - nand-wr-ecc@ff8c8800 { - compatible = "altr,socfpga-s10-nand-ecc"; - reg = <0xff8c8800 0x100>; - altr,ecc-parent = <&nand>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; - }; - - dma-ecc@ff8c9000 { - compatible = "altr,socfpga-s10-dma-ecc"; - reg = <0xff8c9000 0x100>; - altr,ecc-parent = <&pdma>; - interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; - - usb0-ecc@ff8c4000 { - compatible = "altr,socfpga-s10-usb-ecc"; - reg = <0xff8c4000 0x100>; - altr,ecc-parent = <&usb0>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; - }; - - sdmmc-ecc@ff8c8c00 { - compatible = "altr,socfpga-s10-sdmmc-ecc"; - reg = <0xff8c8c00 0x100>; - altr,ecc-parent = <&mmc>; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, - <15 IRQ_TYPE_LEVEL_HIGH>; - }; - }; diff --git a/Bindings/eeprom/at24.yaml b/Bindings/eeprom/at24.yaml index c9e4afbdc44..0ac68646c07 100644 --- a/Bindings/eeprom/at24.yaml +++ b/Bindings/eeprom/at24.yaml @@ -130,10 +130,13 @@ properties: - const: giantec,gt24c32a - const: atmel,24c32 - items: - - const: onnn,n24s64b + - enum: + - onnn,n24s64b + - puya,p24c64f - const: atmel,24c64 - items: - enum: + - giantec,gt24p128e - giantec,gt24p128f - renesas,r1ex24128 - samsung,s524ad0xd1 diff --git a/Bindings/firmware/fsl,scu.yaml b/Bindings/firmware/fsl,scu.yaml index 557e524786c..f9ba18f0636 100644 --- a/Bindings/firmware/fsl,scu.yaml +++ b/Bindings/firmware/fsl,scu.yaml @@ -45,6 +45,18 @@ properties: Keys provided by the SCU $ref: /schemas/input/fsl,scu-key.yaml + reset-controller: + type: object + properties: + compatible: + const: fsl,imx-scu-reset + '#reset-cells': + const: 1 + required: + - compatible + - '#reset-cells' + additionalProperties: false + mboxes: description: A list of phandles of TX MU channels followed by a list of phandles of diff --git a/Bindings/firmware/google,gs101-acpm-ipc.yaml b/Bindings/firmware/google,gs101-acpm-ipc.yaml new file mode 100644 index 00000000000..2cdad1bbae7 --- /dev/null +++ b/Bindings/firmware/google,gs101-acpm-ipc.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/google,gs101-acpm-ipc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos ACPM mailbox protocol + +maintainers: + - Tudor Ambarus + +description: | + ACPM (Alive Clock and Power Manager) is a firmware that operates on the + APM (Active Power Management) module that handles overall power management + activities. ACPM and masters regard each other as independent hardware + component and communicate with each other using mailbox messages and + shared memory. + + This binding is intended to define the interface the firmware implementing + ACPM provides for OSPM in the device tree. + +properties: + compatible: + const: google,gs101-acpm-ipc + + mboxes: + maxItems: 1 + + shmem: + description: + List of phandle pointing to the shared memory (SHM) area. The memory + contains channels configuration data and the TX/RX ring buffers that + are used for passing messages to/from the ACPM firmware. + maxItems: 1 + +required: + - compatible + - mboxes + - shmem + +additionalProperties: false + +examples: + - | + power-management { + compatible = "google,gs101-acpm-ipc"; + mboxes = <&ap2apm_mailbox>; + shmem = <&apm_sram>; + }; diff --git a/Bindings/firmware/thead,th1520-aon.yaml b/Bindings/firmware/thead,th1520-aon.yaml new file mode 100644 index 00000000000..bbc18320040 --- /dev/null +++ b/Bindings/firmware/thead,th1520-aon.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/thead,th1520-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: T-HEAD TH1520 AON (Always-On) Firmware + +description: | + The Always-On (AON) subsystem in the TH1520 SoC is responsible for managing + low-power states, system wakeup events, and power management tasks. It is + designed to operate independently in a dedicated power domain, allowing it to + remain functional even during the SoC's deep sleep states. + + At the heart of the AON subsystem is the E902, a low-power core that executes + firmware responsible for coordinating tasks such as power domain control, + clock management, and system wakeup signaling. Communication between the main + SoC and the AON subsystem is handled through a mailbox interface, which + enables message-based interactions with the AON firmware. + +maintainers: + - Michal Wilczynski + +properties: + compatible: + const: thead,th1520-aon + + mboxes: + maxItems: 1 + + mbox-names: + items: + - const: aon + + "#power-domain-cells": + const: 1 + +required: + - compatible + - mboxes + - mbox-names + - "#power-domain-cells" + +additionalProperties: false + +examples: + - | + aon: aon { + compatible = "thead,th1520-aon"; + mboxes = <&mbox_910t 1>; + mbox-names = "aon"; + #power-domain-cells = <1>; + }; diff --git a/Bindings/fsi/ibm,p9-scom.yaml b/Bindings/fsi/ibm,p9-scom.yaml index 8cd14a70bed..b106f5212ea 100644 --- a/Bindings/fsi/ibm,p9-scom.yaml +++ b/Bindings/fsi/ibm,p9-scom.yaml @@ -16,6 +16,7 @@ description: properties: compatible: enum: + - ibm,fsi2pib - ibm,p9-scom - ibm,i2cr-scom diff --git a/Bindings/gpio/aspeed,ast2400-gpio.yaml b/Bindings/gpio/aspeed,ast2400-gpio.yaml index b9afd07a9d2..b16273e69df 100644 --- a/Bindings/gpio/aspeed,ast2400-gpio.yaml +++ b/Bindings/gpio/aspeed,ast2400-gpio.yaml @@ -46,6 +46,12 @@ properties: minimum: 12 maximum: 232 +patternProperties: + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + required: - compatible - reg diff --git a/Bindings/gpio/gpio-mvebu.yaml b/Bindings/gpio/gpio-mvebu.yaml index 33d4e471651..7ed5f9c4dde 100644 --- a/Bindings/gpio/gpio-mvebu.yaml +++ b/Bindings/gpio/gpio-mvebu.yaml @@ -72,6 +72,9 @@ properties: "#gpio-cells": const: 2 + gpio-ranges: + maxItems: 1 + marvell,pwm-offset: $ref: /schemas/types.yaml#/definitions/uint32 description: Offset in the register map for the pwm registers (in bytes) @@ -96,6 +99,13 @@ properties: - const: axi minItems: 1 +patternProperties: + "^(.+-hog(-[0-9]+)?)$": + type: object + + required: + - gpio-hog + required: - compatible - gpio-controller diff --git a/Bindings/gpio/gpio-vf610.yaml b/Bindings/gpio/gpio-vf610.yaml index cabda2eab4a..4fb32e9aec0 100644 --- a/Bindings/gpio/gpio-vf610.yaml +++ b/Bindings/gpio/gpio-vf610.yaml @@ -28,6 +28,7 @@ properties: - items: - enum: - fsl,imx93-gpio + - fsl,imx94-gpio - fsl,imx95-gpio - const: fsl,imx8ulp-gpio diff --git a/Bindings/gpio/loongson,ls-gpio.yaml b/Bindings/gpio/loongson,ls-gpio.yaml index cf3b1b270aa..b68159600e2 100644 --- a/Bindings/gpio/loongson,ls-gpio.yaml +++ b/Bindings/gpio/loongson,ls-gpio.yaml @@ -20,7 +20,10 @@ properties: - loongson,ls2k2000-gpio1 - loongson,ls2k2000-gpio2 - loongson,ls3a5000-gpio + - loongson,ls3a6000-gpio # Loongson-3A6000 node GPIO - loongson,ls7a-gpio + - loongson,ls7a2000-gpio1 # LS7A2000 chipset GPIO + - loongson,ls7a2000-gpio2 # LS7A2000 ACPI GPIO - items: - const: loongson,ls2k1000-gpio - const: loongson,ls2k-gpio diff --git a/Bindings/gpio/nxp,pcf8575.yaml b/Bindings/gpio/nxp,pcf8575.yaml index 3718103e966..8bca574bb66 100644 --- a/Bindings/gpio/nxp,pcf8575.yaml +++ b/Bindings/gpio/nxp,pcf8575.yaml @@ -73,6 +73,43 @@ properties: wakeup-source: true + reset-gpios: + maxItems: 1 + description: + GPIO controlling the (reset active LOW) RESET# pin. + + The active polarity of the GPIO must translate to the low state of the + RESET# pin on the IC, i.e. if a GPIO is directly routed to the RESET# pin + without any inverter, GPIO_ACTIVE_LOW is expected. + + Performing a reset makes all lines initialized to their input (pulled-up) + state. + +allOf: + - if: + properties: + compatible: + not: + contains: + enum: + - nxp,pca9670 + - nxp,pca9671 + - nxp,pca9672 + - nxp,pca9673 + then: + properties: + reset-gpios: false + + # lines-initial-states XOR reset-gpios + # Performing a reset reinitializes all lines to a known state which + # may not match passed lines-initial-states + - if: + required: + - lines-initial-states + then: + properties: + reset-gpios: false + patternProperties: "^(.+-hog(-[0-9]+)?)$": type: object diff --git a/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml b/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml index bb93baa8887..e13e9d6dd14 100644 --- a/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml +++ b/Bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml @@ -12,7 +12,6 @@ description: PS_MODE). Every pin can be configured as input/output. maintainers: - - Mubin Sayyed - Radhey Shyam Pandey properties: diff --git a/Bindings/gpu/arm,mali-bifrost.yaml b/Bindings/gpu/arm,mali-bifrost.yaml index 735c7f06c24..019bd28a29f 100644 --- a/Bindings/gpu/arm,mali-bifrost.yaml +++ b/Bindings/gpu/arm,mali-bifrost.yaml @@ -17,6 +17,7 @@ properties: oneOf: - items: - enum: + - allwinner,sun50i-h616-mali - amlogic,meson-g12a-mali - mediatek,mt8183-mali - mediatek,mt8183b-mali @@ -24,7 +25,9 @@ properties: - realtek,rtd1619-mali - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a09g057-mali - rockchip,px30-mali + - rockchip,rk3562-mali - rockchip,rk3568-mali - rockchip,rk3576-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable @@ -142,6 +145,7 @@ allOf: enum: - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a09g057-mali then: properties: interrupts: diff --git a/Bindings/gpu/arm,mali-midgard.yaml b/Bindings/gpu/arm,mali-midgard.yaml index 0801da33a38..48daba21a89 100644 --- a/Bindings/gpu/arm,mali-midgard.yaml +++ b/Bindings/gpu/arm,mali-midgard.yaml @@ -45,12 +45,15 @@ properties: - samsung,exynos7-mali - const: samsung,exynos5433-mali - const: arm,mali-t760 + - items: + - enum: + - samsung,exynos7870-mali + - const: arm,mali-t830 - items: - enum: - rockchip,rk3399-mali - const: arm,mali-t860 - # "arm,mali-t830" # "arm,mali-t880" reg: diff --git a/Bindings/hwinfo/samsung,exynos-chipid.yaml b/Bindings/hwinfo/samsung,exynos-chipid.yaml index 385aac7161a..383020450d7 100644 --- a/Bindings/hwinfo/samsung,exynos-chipid.yaml +++ b/Bindings/hwinfo/samsung,exynos-chipid.yaml @@ -19,9 +19,11 @@ properties: - enum: - samsung,exynos5433-chipid - samsung,exynos7-chipid + - samsung,exynos7870-chipid - const: samsung,exynos4210-chipid - items: - enum: + - samsung,exynos2200-chipid - samsung,exynos7885-chipid - samsung,exynos8895-chipid - samsung,exynos9810-chipid diff --git a/Bindings/hwmon/adi,ad741x.yaml b/Bindings/hwmon/adi,ad741x.yaml index ce7f8ce9da0..236d8b52ef8 100644 --- a/Bindings/hwmon/adi,ad741x.yaml +++ b/Bindings/hwmon/adi,ad741x.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/adi,ad741x.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/hwmon/adi,adm1275.yaml b/Bindings/hwmon/adi,adm1275.yaml index fd79bf2e0d1..ddb72857c84 100644 --- a/Bindings/hwmon/adi,adm1275.yaml +++ b/Bindings/hwmon/adi,adm1275.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/adi,adm1275.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/hwmon/adi,ltc2991.yaml b/Bindings/hwmon/adi,ltc2991.yaml index 011e5b65c79..1ff44cb22ef 100644 --- a/Bindings/hwmon/adi,ltc2991.yaml +++ b/Bindings/hwmon/adi,ltc2991.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/adi,ltc2991.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/hwmon/gpio-fan.yaml b/Bindings/hwmon/gpio-fan.yaml index 7f30cfc8735..4faebbb4c7a 100644 --- a/Bindings/hwmon/gpio-fan.yaml +++ b/Bindings/hwmon/gpio-fan.yaml @@ -23,6 +23,9 @@ properties: alarm-gpios: maxItems: 1 + fan-supply: + description: Power supply for fan + gpio-fan,speed-map: $ref: /schemas/types.yaml#/definitions/uint32-matrix minItems: 2 diff --git a/Bindings/hwmon/lltc,ltc2978.yaml b/Bindings/hwmon/lltc,ltc2978.yaml index 37e1dc9c7dd..aa801ef1640 100644 --- a/Bindings/hwmon/lltc,ltc2978.yaml +++ b/Bindings/hwmon/lltc,ltc2978.yaml @@ -12,6 +12,8 @@ maintainers: properties: compatible: enum: + - lltc,lt7170 + - lltc,lt7171 - lltc,ltc2972 - lltc,ltc2974 - lltc,ltc2975 @@ -30,6 +32,7 @@ properties: - lltc,ltc7880 - lltc,ltm2987 - lltc,ltm4664 + - lltc,ltm4673 - lltc,ltm4675 - lltc,ltm4676 - lltc,ltm4677 @@ -46,6 +49,7 @@ properties: description: | list of regulators provided by this controller. Valid names of regulators depend on number of supplies supported per device: + * lt7170, lt7171 : vout0 * ltc2972 vout0 - vout1 * ltc2974, ltc2975 : vout0 - vout3 * ltc2977, ltc2979, ltc2980, ltm2987 : vout0 - vout7 @@ -55,6 +59,7 @@ properties: * ltc7880 : vout0 - vout1 * ltc3883 : vout0 * ltm4664 : vout0 - vout1 + * ltm4673 : vout0 - vout3 * ltm4675, ltm4676, ltm4677, ltm4678 : vout0 - vout1 * ltm4680, ltm4686 : vout0 - vout1 * ltm4700 : vout0 - vout1 diff --git a/Bindings/hwmon/maxim,max20730.yaml b/Bindings/hwmon/maxim,max20730.yaml index 93e86e3b460..8af0d7458e6 100644 --- a/Bindings/hwmon/maxim,max20730.yaml +++ b/Bindings/hwmon/maxim,max20730.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/maxim,max20730.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/hwmon/maxim,max6639.yaml b/Bindings/hwmon/maxim,max6639.yaml index 4f5837a3077..139a95e00fe 100644 --- a/Bindings/hwmon/maxim,max6639.yaml +++ b/Bindings/hwmon/maxim,max6639.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/maxim,max6639.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/hwmon/maxim,max6650.yaml b/Bindings/hwmon/maxim,max6650.yaml index 2c26104a5e1..24c7697fdc1 100644 --- a/Bindings/hwmon/maxim,max6650.yaml +++ b/Bindings/hwmon/maxim,max6650.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/maxim,max6650.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/hwmon/microchip,emc2305.yaml b/Bindings/hwmon/microchip,emc2305.yaml new file mode 100644 index 00000000000..d3f06ebc19f --- /dev/null +++ b/Bindings/hwmon/microchip,emc2305.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/microchip,emc2305.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip EMC2305 SMBus compliant PWM fan controller + +maintainers: + - Michael Shych + +description: + Microchip EMC2301/2/3/5 pwm controller which supports up to five programmable + fan control circuits. + +properties: + compatible: + oneOf: + - enum: + - microchip,emc2305 + - items: + - enum: + - microchip,emc2303 + - microchip,emc2302 + - microchip,emc2301 + - const: microchip,emc2305 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + '#pwm-cells': + const: 3 + description: | + Number of cells in a PWM specifier. + - cell 0: The PWM frequency + - cell 1: The PWM polarity: 0 or PWM_POLARITY_INVERTED + - cell 2: The PWM output config: + - 0 (Open-Drain) + - 1 (Push-Pull) + +patternProperties: + '^fan@[0-4]$': + $ref: fan-common.yaml# + unevaluatedProperties: false + properties: + reg: + description: + The fan number used to determine the associated PWM channel. + maxItems: 1 + + required: + - reg + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + fan_controller: fan-controller@2f { + compatible = "microchip,emc2305"; + reg = <0x2f>; + #address-cells = <1>; + #size-cells = <0>; + #pwm-cells = <3>; + + fan@0 { + reg = <0x0>; + pwms = <&fan_controller 26000 PWM_POLARITY_INVERTED 1>; + #cooling-cells = <2>; + }; + + fan@1 { + reg = <0x1>; + pwms = <&fan_controller 26000 0 1>; + #cooling-cells = <2>; + }; + + fan@2 { + reg = <0x2>; + pwms = <&fan_controller 26000 0 1>; + #cooling-cells = <2>; + }; + + fan@3 { + reg = <0x3>; + pwms = <&fan_controller 26000 0 1>; + #cooling-cells = <2>; + }; + + fan@4 { + reg = <0x4>; + pwms = <&fan_controller 26000 0 1>; + #cooling-cells = <2>; + }; + }; + }; +... diff --git a/Bindings/hwmon/national,lm90.yaml b/Bindings/hwmon/national,lm90.yaml index 6e59c8fdef3..4feb7691940 100644 --- a/Bindings/hwmon/national,lm90.yaml +++ b/Bindings/hwmon/national,lm90.yaml @@ -32,6 +32,9 @@ properties: - national,lm89 - national,lm90 - national,lm99 + - nuvoton,nct7716 + - nuvoton,nct7717 + - nuvoton,nct7718 - nxp,sa56004 - onnn,nct1008 - ti,tmp451 @@ -120,6 +123,8 @@ allOf: - dallas,max6659 - dallas,max6695 - dallas,max6696 + - nuvoton,nct7716 + - nuvoton,nct7717 then: patternProperties: "^channel@([0-2])$": @@ -155,6 +160,7 @@ allOf: - national,lm89 - national,lm90 - national,lm99 + - nuvoton,nct7718 - nxp,sa56004 - winbond,w83l771 then: diff --git a/Bindings/hwmon/ntc-thermistor.yaml b/Bindings/hwmon/ntc-thermistor.yaml index 3d0146e20d3..b8e500e6cd9 100644 --- a/Bindings/hwmon/ntc-thermistor.yaml +++ b/Bindings/hwmon/ntc-thermistor.yaml @@ -76,7 +76,7 @@ properties: - const: murata,ncp03wf104 - const: murata,ncp15xh103 - const: samsung,1404-001221 - # Deprecated "ntp," compatible strings + # Deprecated "ntc," compatible strings - const: ntc,ncp15wb473 deprecated: true - const: ntc,ncp18wb473 diff --git a/Bindings/hwmon/nuvoton,nct6775.yaml b/Bindings/hwmon/nuvoton,nct6775.yaml index e3db642878d..24447028289 100644 --- a/Bindings/hwmon/nuvoton,nct6775.yaml +++ b/Bindings/hwmon/nuvoton,nct6775.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/nuvoton,nct6775.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/hwmon/nuvoton,nct7363.yaml b/Bindings/hwmon/nuvoton,nct7363.yaml index c1e5dedc2f6..625fcf5d3b5 100644 --- a/Bindings/hwmon/nuvoton,nct7363.yaml +++ b/Bindings/hwmon/nuvoton,nct7363.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/nuvoton,nct7363.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/hwmon/nuvoton,nct7802.yaml b/Bindings/hwmon/nuvoton,nct7802.yaml index cd8dcd79703..c16a33227e9 100644 --- a/Bindings/hwmon/nuvoton,nct7802.yaml +++ b/Bindings/hwmon/nuvoton,nct7802.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/nuvoton,nct7802.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/hwmon/pmbus/ti,ucd90320.yaml b/Bindings/hwmon/pmbus/ti,ucd90320.yaml index e8feee38c76..f8bea1c0e94 100644 --- a/Bindings/hwmon/pmbus/ti,ucd90320.yaml +++ b/Bindings/hwmon/pmbus/ti,ucd90320.yaml @@ -28,6 +28,15 @@ properties: reg: maxItems: 1 + gpio-controller: true + + gpio-line-names: + minItems: 84 + maxItems: 84 + + '#gpio-cells': + const: 1 + required: - compatible - reg diff --git a/Bindings/hwmon/ti,adc128d818.yaml b/Bindings/hwmon/ti,adc128d818.yaml index a32035409ce..78e3d97e2ae 100644 --- a/Bindings/hwmon/ti,adc128d818.yaml +++ b/Bindings/hwmon/ti,adc128d818.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/ti,adc128d818.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/hwmon/ti,ads7828.yaml b/Bindings/hwmon/ti,ads7828.yaml index 926be9a2904..fb80456120e 100644 --- a/Bindings/hwmon/ti,ads7828.yaml +++ b/Bindings/hwmon/ti,ads7828.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/ti,ads7828.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/hwmon/ti,ina2xx.yaml b/Bindings/hwmon/ti,ina2xx.yaml index 05a9cb36cd8..bc03781342c 100644 --- a/Bindings/hwmon/ti,ina2xx.yaml +++ b/Bindings/hwmon/ti,ina2xx.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/ti,ina2xx.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# @@ -27,6 +26,7 @@ properties: - ti,ina226 - ti,ina230 - ti,ina231 + - ti,ina233 - ti,ina237 - ti,ina238 - ti,ina260 @@ -75,12 +75,41 @@ properties: the alert polarity to active-high. $ref: /schemas/types.yaml#/definitions/flag + ti,maximum-expected-current-microamp: + description: | + This value indicates the maximum current in microamps that you can + expect to measure with ina233 in your circuit. + + This value will be used to calculate the Current_LSB and current/power + coefficient for the pmbus and to calibrate the IC. + minimum: 32768 + maximum: 4294967295 + default: 32768000 + required: - compatible - reg allOf: - $ref: hwmon-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - silergy,sy24655 + - ti,ina209 + - ti,ina219 + - ti,ina220 + - ti,ina226 + - ti,ina230 + - ti,ina231 + - ti,ina237 + - ti,ina238 + - ti,ina260 + then: + properties: + ti,maximum-expected-current-microamp: false unevaluatedProperties: false diff --git a/Bindings/hwmon/ti,lm87.yaml b/Bindings/hwmon/ti,lm87.yaml index f553235a732..63d8cf46780 100644 --- a/Bindings/hwmon/ti,lm87.yaml +++ b/Bindings/hwmon/ti,lm87.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/ti,lm87.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/hwmon/ti,tmp513.yaml b/Bindings/hwmon/ti,tmp513.yaml index 227858e7605..cba5b4a1b81 100644 --- a/Bindings/hwmon/ti,tmp513.yaml +++ b/Bindings/hwmon/ti,tmp513.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/ti,tmp513.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/hwmon/ti,tps23861.yaml b/Bindings/hwmon/ti,tps23861.yaml index f58248c29e2..ee7de53e191 100644 --- a/Bindings/hwmon/ti,tps23861.yaml +++ b/Bindings/hwmon/ti,tps23861.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/ti,tps23861.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/hwmon/winbond,w83781d.yaml b/Bindings/hwmon/winbond,w83781d.yaml index 31ce77a4b08..6971ecb314e 100644 --- a/Bindings/hwmon/winbond,w83781d.yaml +++ b/Bindings/hwmon/winbond,w83781d.yaml @@ -1,7 +1,6 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- - $id: http://devicetree.org/schemas/hwmon/winbond,w83781d.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# diff --git a/Bindings/i2c/i2c-exynos5.yaml b/Bindings/i2c/i2c-exynos5.yaml index 70cc2ee9ee2..8d47b290b4e 100644 --- a/Bindings/i2c/i2c-exynos5.yaml +++ b/Bindings/i2c/i2c-exynos5.yaml @@ -30,6 +30,7 @@ properties: - items: - enum: - samsung,exynos5433-hsi2c + - samsung,exynos7870-hsi2c - tesla,fsd-hsi2c - const: samsung,exynos7-hsi2c - items: diff --git a/Bindings/i2c/i2c-imx-lpi2c.yaml b/Bindings/i2c/i2c-imx-lpi2c.yaml index 1dcb9c78de3..969030a6f82 100644 --- a/Bindings/i2c/i2c-imx-lpi2c.yaml +++ b/Bindings/i2c/i2c-imx-lpi2c.yaml @@ -26,6 +26,7 @@ properties: - fsl,imx8qm-lpi2c - fsl,imx8ulp-lpi2c - fsl,imx93-lpi2c + - fsl,imx94-lpi2c - fsl,imx95-lpi2c - const: fsl,imx7ulp-lpi2c diff --git a/Bindings/i2c/i2c-rk3x.yaml b/Bindings/i2c/i2c-rk3x.yaml index a9dae5b52f2..8101afa6f14 100644 --- a/Bindings/i2c/i2c-rk3x.yaml +++ b/Bindings/i2c/i2c-rk3x.yaml @@ -37,6 +37,7 @@ properties: - rockchip,px30-i2c - rockchip,rk3308-i2c - rockchip,rk3328-i2c + - rockchip,rk3562-i2c - rockchip,rk3568-i2c - rockchip,rk3576-i2c - rockchip,rk3588-i2c diff --git a/Bindings/i2c/qcom,i2c-qup.yaml b/Bindings/i2c/qcom,i2c-qup.yaml index f43947514d4..758d8f6321e 100644 --- a/Bindings/i2c/qcom,i2c-qup.yaml +++ b/Bindings/i2c/qcom,i2c-qup.yaml @@ -40,6 +40,9 @@ properties: - const: tx - const: rx + interconnects: + maxItems: 1 + interrupts: maxItems: 1 @@ -52,9 +55,15 @@ properties: - const: default - const: sleep + power-domains: + maxItems: 1 + reg: maxItems: 1 + required-opps: + maxItems: 1 + required: - compatible - clock-names @@ -67,7 +76,9 @@ unevaluatedProperties: false examples: - | #include + #include #include + #include i2c@c175000 { compatible = "qcom,i2c-qup-v2.2.1"; @@ -82,6 +93,9 @@ examples: pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_i2c1_default>; pinctrl-1 = <&blsp1_i2c1_sleep>; + power-domains = <&rpmpd MSM8909_VDDCX>; + required-opps = <&rpmpd_opp_svs_krait>; + interconnects = <&pnoc MASTER_BLSP_1 &bimc SLAVE_EBI_CH0>; clock-frequency = <400000>; #address-cells = <1>; diff --git a/Bindings/i2c/samsung,s3c2410-i2c.yaml b/Bindings/i2c/samsung,s3c2410-i2c.yaml index bbc56848562..6ba7d793504 100644 --- a/Bindings/i2c/samsung,s3c2410-i2c.yaml +++ b/Bindings/i2c/samsung,s3c2410-i2c.yaml @@ -22,6 +22,7 @@ properties: - samsung,exynos5-sata-phy-i2c - items: - enum: + - samsung,exynos7870-i2c - samsung,exynos7885-i2c - samsung,exynos850-i2c - const: samsung,s3c2440-i2c diff --git a/Bindings/i2c/snps,designware-i2c.yaml b/Bindings/i2c/snps,designware-i2c.yaml index e5d05263c45..bc5d0fb5abf 100644 --- a/Bindings/i2c/snps,designware-i2c.yaml +++ b/Bindings/i2c/snps,designware-i2c.yaml @@ -27,6 +27,11 @@ properties: oneOf: - description: Generic Synopsys DesignWare I2C controller const: snps,designware-i2c + - description: Renesas RZ/N1D I2C controller + items: + - const: renesas,r9a06g032-i2c # RZ/N1D + - const: renesas,rzn1-i2c # RZ/N1 + - const: snps,designware-i2c - description: Microsemi Ocelot SoCs I2C controller items: - const: mscc,ocelot-i2c diff --git a/Bindings/i2c/spacemit,k1-i2c.yaml b/Bindings/i2c/spacemit,k1-i2c.yaml new file mode 100644 index 00000000000..3d6aefb0d0f --- /dev/null +++ b/Bindings/i2c/spacemit,k1-i2c.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/spacemit,k1-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: I2C controller embedded in SpacemiT's K1 SoC + +maintainers: + - Troy Mitchell + +properties: + compatible: + const: spacemit,k1-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: I2C Functional Clock + - description: APB Bus Clock + + clock-names: + items: + - const: func + - const: bus + + clock-frequency: + description: | + K1 support three different modes which running different frequencies + standard speed mode: up to 100000 (100Hz) + fast speed mode : up to 400000 (400Hz) + high speed mode : up to 3300000 (3.3Mhz) + default: 400000 + maximum: 3300000 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + i2c@d4010800 { + compatible = "spacemit,k1-i2c"; + reg = <0xd4010800 0x38>; + interrupt-parent = <&plic>; + interrupts = <36>; + clocks =<&ccu 32>, <&ccu 84>; + clock-names = "func", "bus"; + clock-frequency = <100000>; + }; + +... diff --git a/Bindings/i2c/ti,omap4-i2c.yaml b/Bindings/i2c/ti,omap4-i2c.yaml index 8c2e35fabf5..58d32ceeacf 100644 --- a/Bindings/i2c/ti,omap4-i2c.yaml +++ b/Bindings/i2c/ti,omap4-i2c.yaml @@ -47,6 +47,11 @@ properties: $ref: /schemas/types.yaml#/definitions/string deprecated: true + mux-states: + description: + mux controller node to route the I2C signals from SoC to clients. + maxItems: 1 + required: - compatible - reg @@ -87,4 +92,5 @@ examples: interrupts = ; #address-cells = <1>; #size-cells = <0>; + mux-states = <&i2c_mux 1>; }; diff --git a/Bindings/i3c/silvaco,i3c-master.yaml b/Bindings/i3c/silvaco,i3c-master.yaml index c56ff77677f..4fbdcdac0ae 100644 --- a/Bindings/i3c/silvaco,i3c-master.yaml +++ b/Bindings/i3c/silvaco,i3c-master.yaml @@ -14,7 +14,9 @@ allOf: properties: compatible: - const: silvaco,i3c-master-v1 + enum: + - nuvoton,npcm845-i3c + - silvaco,i3c-master-v1 reg: maxItems: 1 diff --git a/Bindings/i3c/snps,dw-i3c-master.yaml b/Bindings/i3c/snps,dw-i3c-master.yaml index 4fc13e3c0f7..5f646737581 100644 --- a/Bindings/i3c/snps,dw-i3c-master.yaml +++ b/Bindings/i3c/snps,dw-i3c-master.yaml @@ -34,6 +34,9 @@ properties: interrupts: maxItems: 1 + power-domains: + maxItems: 1 + required: - compatible - reg diff --git a/Bindings/iio/adc/adi,ad4030.yaml b/Bindings/iio/adc/adi,ad4030.yaml new file mode 100644 index 00000000000..54e7349317b --- /dev/null +++ b/Bindings/iio/adc/adi,ad4030.yaml @@ -0,0 +1,110 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Analog Devices Inc. +# Copyright 2024 BayLibre, SAS. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4030.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4030 and AD4630 ADC families + +maintainers: + - Michael Hennerich + - Nuno Sa + +description: | + Analog Devices AD4030 single channel and AD4630/AD4632 dual channel precision + SAR ADC families + + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad4030-24-4032-24.pdf + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad4630-24_ad4632-24.pdf + * https://www.analog.com/media/en/technical-documentation/data-sheets/ad4630-16-4632-16.pdf + +properties: + compatible: + enum: + - adi,ad4030-24 + - adi,ad4032-24 + - adi,ad4630-16 + - adi,ad4630-24 + - adi,ad4632-16 + - adi,ad4632-24 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 102040816 + + spi-rx-bus-width: + enum: [1, 2, 4] + + vdd-5v-supply: true + vdd-1v8-supply: true + vio-supply: true + + ref-supply: + description: + Optional External unbuffered reference. Used when refin-supply is not + connected. + + refin-supply: + description: + Internal buffered Reference. Used when ref-supply is not connected. + + cnv-gpios: + description: + The Convert Input (CNV). It initiates the sampling conversions. + maxItems: 1 + + reset-gpios: + description: + The Reset Input (/RST). Used for asynchronous device reset. + maxItems: 1 + + interrupts: + description: + The BUSY pin is used to signal that the conversions results are available + to be transferred when in SPI Clocking Mode. This nodes should be + connected to an interrupt that is triggered when the BUSY line goes low. + maxItems: 1 + + interrupt-names: + const: busy + +required: + - compatible + - reg + - vdd-5v-supply + - vdd-1v8-supply + - vio-supply + - cnv-gpios + +oneOf: + - required: + - ref-supply + - required: + - refin-supply + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad4030-24"; + reg = <0>; + spi-max-frequency = <80000000>; + vdd-5v-supply = <&supply_5V>; + vdd-1v8-supply = <&supply_1_8V>; + vio-supply = <&supply_1_8V>; + ref-supply = <&supply_5V>; + cnv-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Bindings/iio/adc/adi,ad4695.yaml b/Bindings/iio/adc/adi,ad4695.yaml index 7d2229dee44..cbde7a0505d 100644 --- a/Bindings/iio/adc/adi,ad4695.yaml +++ b/Bindings/iio/adc/adi,ad4695.yaml @@ -84,6 +84,10 @@ properties: description: The Reset Input (RESET). Should be configured GPIO_ACTIVE_LOW. maxItems: 1 + pwms: + description: PWM signal connected to the CNV pin. + maxItems: 1 + interrupts: minItems: 1 items: @@ -106,6 +110,15 @@ properties: The first cell is the GPn number: 0 to 3. The second cell takes standard GPIO flags. + '#trigger-source-cells': + description: | + First cell indicates the output signal: 0 = BUSY, 1 = ALERT. + Second cell indicates which GPn pin is used: 0, 2 or 3. + + For convenience, macros for these values are available in + dt-bindings/iio/adc/adi,ad4695.h. + const: 2 + "#address-cells": const: 1 diff --git a/Bindings/iio/adc/adi,ad4851.yaml b/Bindings/iio/adc/adi,ad4851.yaml new file mode 100644 index 00000000000..c6676d91b4e --- /dev/null +++ b/Bindings/iio/adc/adi,ad4851.yaml @@ -0,0 +1,153 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4851.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD485X family + +maintainers: + - Sergiu Cuciurean + - Dragos Bogdan + - Antoniu Miclaus + +description: | + Analog Devices AD485X fully buffered, 8-channel simultaneous sampling, + 16/20-bit, 1 MSPS data acquisition system (DAS) with differential, wide + common-mode range inputs. + + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4855.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4856.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4857.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4858.pdf + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad4851 + - adi,ad4852 + - adi,ad4853 + - adi,ad4854 + - adi,ad4855 + - adi,ad4856 + - adi,ad4857 + - adi,ad4858 + - adi,ad4858i + + reg: + maxItems: 1 + + vcc-supply: true + + vee-supply: true + + vdd-supply: true + + vddh-supply: true + + vddl-supply: true + + vio-supply: true + + vrefbuf-supply: true + + vrefio-supply: true + + pwms: + description: PWM connected to the CNV pin. + maxItems: 1 + + io-backends: + maxItems: 1 + + pd-gpios: + maxItems: 1 + + spi-max-frequency: + maximum: 25000000 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^channel(@[0-7])?$": + $ref: adc.yaml + type: object + description: Represents the channels which are connected to the ADC. + + properties: + reg: + description: + The channel number, as specified in the datasheet (from 0 to 7). + minimum: 0 + maximum: 7 + + diff-channels: + description: + Each channel can be configured as a bipolar differential channel. + The ADC uses the same positive and negative inputs for this. + This property must be specified as 'reg' (or the channel number) for + both positive and negative inputs (i.e. diff-channels = ). + Since the configuration is bipolar differential, the 'bipolar' + property is required. + items: + minimum: 0 + maximum: 7 + + bipolar: true + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - vcc-supply + - vee-supply + - vdd-supply + - vio-supply + - pwms + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0{ + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad4858"; + reg = <0>; + spi-max-frequency = <10000000>; + vcc-supply = <&vcc>; + vdd-supply = <&vdd>; + vee-supply = <&vee>; + vddh-supply = <&vddh>; + vddl-supply = <&vddl>; + vio-supply = <&vio>; + pwms = <&pwm_gen 0 0>; + io-backends = <&iio_backend>; + + channel@0 { + reg = <0>; + diff-channels = <0 0>; + bipolar; + }; + + channel@1 { + reg = <1>; + }; + }; + }; +... diff --git a/Bindings/iio/adc/adi,ad7191.yaml b/Bindings/iio/adc/adi,ad7191.yaml new file mode 100644 index 00000000000..801ed319ee8 --- /dev/null +++ b/Bindings/iio/adc/adi,ad7191.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2025 Analog Devices Inc. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad7191.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD7191 ADC + +maintainers: + - Alisa-Dariana Roman + +description: | + Bindings for the Analog Devices AD7191 ADC device. Datasheet can be + found here: + https://www.analog.com/media/en/technical-documentation/data-sheets/AD7191.pdf + The device's PDOWN pin must be connected to the SPI controller's chip select + pin. + +properties: + compatible: + enum: + - adi,ad7191 + + reg: + maxItems: 1 + + spi-cpol: true + + spi-cpha: true + + clocks: + maxItems: 1 + description: + Must be present when CLKSEL pin is tied HIGH to select external clock + source (either a crystal between MCLK1 and MCLK2 pins, or a + CMOS-compatible clock driving MCLK2 pin). Must be absent when CLKSEL pin + is tied LOW to use the internal 4.92MHz clock. + + interrupts: + maxItems: 1 + + avdd-supply: + description: AVdd voltage supply + + dvdd-supply: + description: DVdd voltage supply + + vref-supply: + description: Vref voltage supply + + odr-gpios: + description: + ODR1 and ODR2 pins for output data rate selection. Should be defined if + adi,odr-value is absent. + minItems: 2 + maxItems: 2 + + adi,odr-value: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Should be present if ODR pins are pin-strapped. Possible values: + 120 Hz (ODR1=0, ODR2=0) + 60 Hz (ODR1=0, ODR2=1) + 50 Hz (ODR1=1, ODR2=0) + 10 Hz (ODR1=1, ODR2=1) + If defined, odr-gpios must be absent. + enum: [120, 60, 50, 10] + + pga-gpios: + description: + PGA1 and PGA2 pins for gain selection. Should be defined if adi,pga-value + is absent. + minItems: 2 + maxItems: 2 + + adi,pga-value: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Should be present if PGA pins are pin-strapped. Possible values: + Gain 1 (PGA1=0, PGA2=0) + Gain 8 (PGA1=0, PGA2=1) + Gain 64 (PGA1=1, PGA2=0) + Gain 128 (PGA1=1, PGA2=1) + If defined, pga-gpios must be absent. + enum: [1, 8, 64, 128] + + temp-gpios: + description: TEMP pin for temperature sensor enable. + maxItems: 1 + + chan-gpios: + description: CHAN pin for input channel selection. + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - avdd-supply + - dvdd-supply + - vref-supply + - spi-cpol + - spi-cpha + - temp-gpios + - chan-gpios + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - oneOf: + - required: + - adi,odr-value + - required: + - odr-gpios + - oneOf: + - required: + - adi,pga-value + - required: + - pga-gpios + +unevaluatedProperties: false + +examples: + - | + #include + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad7191"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cpol; + spi-cpha; + clocks = <&ad7191_mclk>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; + avdd-supply = <&avdd>; + dvdd-supply = <&dvdd>; + vref-supply = <&vref>; + adi,pga-value = <1>; + odr-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>, <&gpio 24 GPIO_ACTIVE_HIGH>; + temp-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + chan-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Bindings/iio/adc/adi,ad7380.yaml b/Bindings/iio/adc/adi,ad7380.yaml index ada08005b3c..ff4f5c21c54 100644 --- a/Bindings/iio/adc/adi,ad7380.yaml +++ b/Bindings/iio/adc/adi,ad7380.yaml @@ -27,6 +27,7 @@ description: | * https://www.analog.com/en/products/ad7388-4.html * https://www.analog.com/en/products/adaq4370-4.html * https://www.analog.com/en/products/adaq4380-4.html + * https://www.analog.com/en/products/adaq4381-4.html $ref: /schemas/spi/spi-peripheral-props.yaml# @@ -50,6 +51,7 @@ properties: - adi,ad7388-4 - adi,adaq4370-4 - adi,adaq4380-4 + - adi,adaq4381-4 reg: maxItems: 1 @@ -201,6 +203,7 @@ allOf: - adi,ad7380-4 - adi,adaq4370-4 - adi,adaq4380-4 + - adi,adaq4381-4 then: properties: refio-supply: false @@ -218,6 +221,7 @@ allOf: enum: - adi,adaq4370-4 - adi,adaq4380-4 + - adi,adaq4381-4 then: required: - vs-p-supply diff --git a/Bindings/iio/adc/adi,axi-adc.yaml b/Bindings/iio/adc/adi,axi-adc.yaml index e1f450b80db..cf74f84d610 100644 --- a/Bindings/iio/adc/adi,axi-adc.yaml +++ b/Bindings/iio/adc/adi,axi-adc.yaml @@ -17,13 +17,25 @@ description: | interface for the actual ADC, while this IP core will interface to the data-lines of the ADC and handle the streaming of data into memory via DMA. + In some cases, the AXI ADC interface is used to perform specialized + operation to a particular ADC, e.g access the physical bus through + specific registers to write ADC registers. + In this case, we use a different compatible which indicates the target + IP core's name. + The following IP is currently supported: + - AXI AD7606x: specialized version of the IP core for all the chips from + the ad7606 family. https://wiki.analog.com/resources/fpga/docs/axi_adc_ip + https://analogdevicesinc.github.io/hdl/library/axi_ad485x/index.html + http://analogdevicesinc.github.io/hdl/library/axi_ad7606x/index.html properties: compatible: enum: - adi,axi-adc-10.0.a + - adi,axi-ad7606x + - adi,axi-ad485x reg: maxItems: 1 @@ -47,17 +59,48 @@ properties: '#io-backend-cells': const: 0 + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^adc@[0-9a-f]+$": + type: object + properties: + reg: + maxItems: 1 + additionalProperties: true + required: + - compatible + - reg + required: - compatible - dmas - reg - clocks +allOf: + - if: + properties: + compatible: + not: + contains: + const: adi,axi-ad7606x + then: + properties: + '#address-cells': false + '#size-cells': false + patternProperties: + "^adc@[0-9a-f]+$": false + additionalProperties: false examples: - | - axi-adc@44a00000 { + adc@44a00000 { compatible = "adi,axi-adc-10.0.a"; reg = <0x44a00000 0x10000>; dmas = <&rx_dma 0>; @@ -65,4 +108,31 @@ examples: clocks = <&axi_clk>; #io-backend-cells = <0>; }; + - | + #include + parallel_bus_controller@44a00000 { + compatible = "adi,axi-ad7606x"; + reg = <0x44a00000 0x10000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + clocks = <&ext_clk>; + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad7606b"; + reg = <0>; + pwms = <&axi_pwm_gen 0 0>; + pwm-names = "convst1"; + avcc-supply = <&adc_vref>; + vdrive-supply = <&vdd_supply>; + reset-gpios = <&gpio0 91 GPIO_ACTIVE_HIGH>; + standby-gpios = <&gpio0 90 GPIO_ACTIVE_LOW>; + adi,range-gpios = <&gpio0 89 GPIO_ACTIVE_HIGH>; + adi,oversampling-ratio-gpios = <&gpio0 88 GPIO_ACTIVE_HIGH + &gpio0 87 GPIO_ACTIVE_HIGH + &gpio0 86 GPIO_ACTIVE_HIGH>; + io-backends = <¶llel_bus_controller>; + }; + }; ... diff --git a/Bindings/iio/adc/nxp,imx93-adc.yaml b/Bindings/iio/adc/nxp,imx93-adc.yaml index dfc3f512918..c2e5ff41892 100644 --- a/Bindings/iio/adc/nxp,imx93-adc.yaml +++ b/Bindings/iio/adc/nxp,imx93-adc.yaml @@ -19,7 +19,14 @@ description: properties: compatible: - const: nxp,imx93-adc + oneOf: + - enum: + - nxp,imx93-adc + - items: + - enum: + - nxp,imx94-adc + - nxp,imx95-adc + - const: nxp,imx93-adc reg: maxItems: 1 diff --git a/Bindings/iio/adc/rockchip-saradc.yaml b/Bindings/iio/adc/rockchip-saradc.yaml index fd93ed3991e..41e0c56ef8e 100644 --- a/Bindings/iio/adc/rockchip-saradc.yaml +++ b/Bindings/iio/adc/rockchip-saradc.yaml @@ -15,6 +15,8 @@ properties: - const: rockchip,saradc - const: rockchip,rk3066-tsadc - const: rockchip,rk3399-saradc + - const: rockchip,rk3528-saradc + - const: rockchip,rk3562-saradc - const: rockchip,rk3588-saradc - items: - const: rockchip,rk3576-saradc diff --git a/Bindings/iio/adc/ti,ads7138.yaml b/Bindings/iio/adc/ti,ads7138.yaml new file mode 100644 index 00000000000..a51893e207d --- /dev/null +++ b/Bindings/iio/adc/ti,ads7138.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/ti,ads7138.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments ADS7128/ADS7138 analog-to-digital converter (ADC) + +maintainers: + - Tobias Sperling + +description: | + The ADS7128 and ADS7138 chips are 12-bit, 8 channel analog-to-digital + converters (ADC) with build-in digital window comparator (DWC), using the + I2C interface. + ADS7128 differs in the addition of further hardware features, like a + root-mean-square (RMS) and a zero-crossing-detect (ZCD) module. + + Datasheets: + https://www.ti.com/product/ADS7128 + https://www.ti.com/product/ADS7138 + +properties: + compatible: + enum: + - ti,ads7128 + - ti,ads7138 + + reg: + maxItems: 1 + + avdd-supply: + description: + The regulator used as analog supply voltage as well as reference voltage. + + interrupts: + description: + Interrupt on ALERT pin, triggers on low level. + maxItems: 1 + +required: + - compatible + - reg + - avdd-supply + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + adc@10 { + compatible = "ti,ads7138"; + reg = <0x10>; + avdd-supply = <®_stb_3v3>; + interrupt-parent = <&gpio2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + }; + }; +... diff --git a/Bindings/iio/adc/xlnx,zynqmp-ams.yaml b/Bindings/iio/adc/xlnx,zynqmp-ams.yaml index 8cbad7e792b..a403392fb26 100644 --- a/Bindings/iio/adc/xlnx,zynqmp-ams.yaml +++ b/Bindings/iio/adc/xlnx,zynqmp-ams.yaml @@ -193,7 +193,6 @@ additionalProperties: false examples: - | - #include bus { #address-cells = <2>; @@ -204,7 +203,7 @@ examples: interrupt-parent = <&gic>; interrupts = <0 56 4>; reg = <0x0 0xffa50000 0x0 0x800>; - clocks = <&zynqmp_clk AMS_REF>; + clocks = <&zynqmp_clk 70>; #address-cells = <1>; #size-cells = <1>; #io-channel-cells = <1>; diff --git a/Bindings/iio/dac/adi,ad5380.yaml b/Bindings/iio/dac/adi,ad5380.yaml index 9eb9928500e..3e323f1a545 100644 --- a/Bindings/iio/dac/adi,ad5380.yaml +++ b/Bindings/iio/dac/adi,ad5380.yaml @@ -55,18 +55,18 @@ examples: #address-cells = <1>; #size-cells = <0>; dac@0 { - reg = <0>; - compatible = "adi,ad5390-5"; - vref-supply = <&dacvref>; + reg = <0>; + compatible = "adi,ad5390-5"; + vref-supply = <&dacvref>; }; }; - | i2c { - #address-cells = <1>; - #size-cells = <0>; - dac@42 { - reg = <0x42>; - compatible = "adi,ad5380-3"; - }; + #address-cells = <1>; + #size-cells = <0>; + dac@42 { + reg = <0x42>; + compatible = "adi,ad5380-3"; + }; }; ... diff --git a/Bindings/iio/frequency/adf4371.yaml b/Bindings/iio/frequency/adf4371.yaml index 1cb2adaf66f..53d60744161 100644 --- a/Bindings/iio/frequency/adf4371.yaml +++ b/Bindings/iio/frequency/adf4371.yaml @@ -30,8 +30,9 @@ properties: clock-names: description: - Must be "clkin" - maxItems: 1 + Must be "clkin" if the input reference is single ended or "clkin-diff" + if the input reference is differential. + enum: [clkin, clkin-diff] adi,mute-till-lock-en: type: boolean diff --git a/Bindings/iio/humidity/sciosense,ens210.yaml b/Bindings/iio/humidity/sciosense,ens210.yaml index ed0ea938f7f..1e25cf781cf 100644 --- a/Bindings/iio/humidity/sciosense,ens210.yaml +++ b/Bindings/iio/humidity/sciosense,ens210.yaml @@ -43,13 +43,13 @@ additionalProperties: false examples: - | i2c { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - temperature-sensor@43 { - compatible = "sciosense,ens210"; - reg = <0x43>; - }; + temperature-sensor@43 { + compatible = "sciosense,ens210"; + reg = <0x43>; + }; }; ... diff --git a/Bindings/iio/imu/adi,adis16550.yaml b/Bindings/iio/imu/adi,adis16550.yaml new file mode 100644 index 00000000000..a4c273c7a67 --- /dev/null +++ b/Bindings/iio/imu/adi,adis16550.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/imu/adi,adis16550.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices ADIS16550 and similar IMUs + +maintainers: + - Nuno Sa + - Ramona Gradinariu + - Antoniu Miclaus + - Robert Budai + +properties: + compatible: + enum: + - adi,adis16550 + + reg: + maxItems: 1 + + spi-cpha: true + + spi-cpol: true + + spi-max-frequency: + maximum: 15000000 + + vdd-supply: true + + interrupts: + maxItems: 1 + + reset-gpios: + description: + Active low RESET pin. + maxItems: 1 + + clocks: + description: If not provided, then the internal clock is used. + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - spi-cpha + - spi-cpol + - spi-max-frequency + - vdd-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +additionalProperties: false + +examples: + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + imu@0 { + compatible = "adi,adis16550"; + reg = <0>; + spi-max-frequency = <15000000>; + spi-cpol; + spi-cpha; + vdd-supply = <&vdd>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpio>; + }; + }; diff --git a/Bindings/iio/light/brcm,apds9160.yaml b/Bindings/iio/light/brcm,apds9160.yaml new file mode 100644 index 00000000000..bb1cc4404a5 --- /dev/null +++ b/Bindings/iio/light/brcm,apds9160.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/light/brcm,apds9160.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom Combined Proximity & Ambient light sensor + +maintainers: + - Mikael Gonella-Bolduc + +description: | + Datasheet: https://docs.broadcom.com/docs/APDS-9160-003-DS + +properties: + compatible: + enum: + - brcm,apds9160 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: true + + ps-cancellation-duration: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Proximity sensor cancellation pulse duration in half clock cycles. + This parameter determines a cancellation pulse duration. + The cancellation is applied in the integration phase to cancel out + unwanted reflected light from very near objects such as tempered glass + in front of the sensor. + default: 0 + maximum: 63 + + ps-cancellation-current-picoamp: + description: + Proximity sensor crosstalk cancellation current in picoampere. + This parameter adjusts the current in steps of 2400 pA up to 276000 pA. + The provided value must be a multiple of 2400 and in one of these ranges + [60000 - 96000] + [120000 - 156000] + [180000 - 216000] + [240000 - 276000] + This parameter is used in conjunction with the cancellation duration. + minimum: 60000 + maximum: 276000 + multipleOf: 2400 + +required: + - compatible + - reg + - vdd-supply + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + light-sensor@53 { + compatible = "brcm,apds9160"; + reg = <0x53>; + vdd-supply = <&vdd_reg>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&pinctrl>; + ps-cancellation-duration = <10>; + ps-cancellation-current-picoamp = <62400>; + }; + }; +... diff --git a/Bindings/iio/light/dynaimage,al3010.yaml b/Bindings/iio/light/dynaimage,al3010.yaml index a3a979553e3..f1048c30e73 100644 --- a/Bindings/iio/light/dynaimage,al3010.yaml +++ b/Bindings/iio/light/dynaimage,al3010.yaml @@ -4,14 +4,16 @@ $id: http://devicetree.org/schemas/iio/light/dynaimage,al3010.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Dyna-Image AL3010 sensor +title: Dyna-Image AL3000a/AL3010 sensor maintainers: - David Heidelberg properties: compatible: - const: dynaimage,al3010 + enum: + - dynaimage,al3000a + - dynaimage,al3010 reg: maxItems: 1 diff --git a/Bindings/iio/magnetometer/silabs,si7210.yaml b/Bindings/iio/magnetometer/silabs,si7210.yaml new file mode 100644 index 00000000000..d4a3f7981c3 --- /dev/null +++ b/Bindings/iio/magnetometer/silabs,si7210.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/magnetometer/silabs,si7210.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Si7210 magnetic position and temperature sensor + +maintainers: + - Antoni Pokusinski + +description: | + Silabs Si7210 I2C Hall effect magnetic position and temperature sensor. + https://www.silabs.com/documents/public/data-sheets/si7210-datasheet.pdf + +properties: + compatible: + const: silabs,si7210 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: + description: Regulator that provides power to the sensor + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + magnetometer@30 { + compatible = "silabs,si7210"; + reg = <0x30>; + interrupt-parent = <&gpio1>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&vdd_3v3_reg>; + }; + }; diff --git a/Bindings/iio/temperature/maxim,max31865.yaml b/Bindings/iio/temperature/maxim,max31865.yaml index 7cc365e0ebc..7c0c6ab6fc6 100644 --- a/Bindings/iio/temperature/maxim,max31865.yaml +++ b/Bindings/iio/temperature/maxim,max31865.yaml @@ -40,15 +40,15 @@ unevaluatedProperties: false examples: - | spi { - #address-cells = <1>; - #size-cells = <0>; - - temperature-sensor@0 { - compatible = "maxim,max31865"; - reg = <0>; - spi-max-frequency = <400000>; - spi-cpha; - maxim,3-wire; - }; + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@0 { + compatible = "maxim,max31865"; + reg = <0>; + spi-max-frequency = <400000>; + spi-cpha; + maxim,3-wire; + }; }; ... diff --git a/Bindings/iio/temperature/ti,tmp117.yaml b/Bindings/iio/temperature/ti,tmp117.yaml index 58aa1542776..fbba5e93486 100644 --- a/Bindings/iio/temperature/ti,tmp117.yaml +++ b/Bindings/iio/temperature/ti,tmp117.yaml @@ -44,8 +44,8 @@ examples: #size-cells = <0>; tmp117@48 { - compatible = "ti,tmp117"; - reg = <0x48>; - vcc-supply = <&pmic_reg_3v3>; + compatible = "ti,tmp117"; + reg = <0x48>; + vcc-supply = <&pmic_reg_3v3>; }; }; diff --git a/Bindings/input/gpio-matrix-keypad.txt b/Bindings/input/gpio-matrix-keypad.txt deleted file mode 100644 index 570dc10f0cd..00000000000 --- a/Bindings/input/gpio-matrix-keypad.txt +++ /dev/null @@ -1,49 +0,0 @@ -* GPIO driven matrix keypad device tree bindings - -GPIO driven matrix keypad is used to interface a SoC with a matrix keypad. -The matrix keypad supports multiple row and column lines, a key can be -placed at each intersection of a unique row and a unique column. The matrix -keypad can sense a key-press and key-release by means of GPIO lines and -report the event using GPIO interrupts to the cpu. - -Required Properties: -- compatible: Should be "gpio-matrix-keypad" -- row-gpios: List of gpios used as row lines. The gpio specifier - for this property depends on the gpio controller to - which these row lines are connected. -- col-gpios: List of gpios used as column lines. The gpio specifier - for this property depends on the gpio controller to - which these column lines are connected. -- linux,keymap: The definition can be found at - bindings/input/matrix-keymap.txt - -Optional Properties: -- linux,no-autorepeat: do no enable autorepeat feature. -- wakeup-source: use any event on keypad as wakeup event. - (Legacy property supported: "linux,wakeup") -- debounce-delay-ms: debounce interval in milliseconds -- col-scan-delay-us: delay, measured in microseconds, that is needed - before we can scan keypad after activating column gpio -- drive-inactive-cols: drive inactive columns during scan, - default is to turn inactive columns into inputs. - -Example: - matrix-keypad { - compatible = "gpio-matrix-keypad"; - debounce-delay-ms = <5>; - col-scan-delay-us = <2>; - - row-gpios = <&gpio2 25 0 - &gpio2 26 0 - &gpio2 27 0>; - - col-gpios = <&gpio2 21 0 - &gpio2 22 0>; - - linux,keymap = <0x0000008B - 0x0100009E - 0x02000069 - 0x0001006A - 0x0101001C - 0x0201006C>; - }; diff --git a/Bindings/input/gpio-matrix-keypad.yaml b/Bindings/input/gpio-matrix-keypad.yaml new file mode 100644 index 00000000000..ebfff9e42a3 --- /dev/null +++ b/Bindings/input/gpio-matrix-keypad.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/input/gpio-matrix-keypad.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GPIO matrix keypad + +maintainers: + - Marek Vasut + +description: + GPIO driven matrix keypad is used to interface a SoC with a matrix keypad. + The matrix keypad supports multiple row and column lines, a key can be + placed at each intersection of a unique row and a unique column. The matrix + keypad can sense a key-press and key-release by means of GPIO lines and + report the event using GPIO interrupts to the cpu. + +allOf: + - $ref: /schemas/input/matrix-keymap.yaml# + +properties: + compatible: + const: gpio-matrix-keypad + + row-gpios: + description: + List of GPIOs used as row lines. The gpio specifier for this property + depends on the gpio controller to which these row lines are connected. + + col-gpios: + description: + List of GPIOs used as column lines. The gpio specifier for this property + depends on the gpio controller to which these column lines are connected. + + linux,keymap: true + + linux,no-autorepeat: + type: boolean + description: Do not enable autorepeat feature. + + gpio-activelow: + type: boolean + description: + Force GPIO polarity to active low. + In the absence of this property GPIOs are treated as active high. + + debounce-delay-ms: + description: Debounce interval in milliseconds. + default: 0 + + col-scan-delay-us: + description: + Delay, measured in microseconds, that is needed + before we can scan keypad after activating column gpio. + default: 0 + + all-cols-on-delay-us: + description: + Delay, measured in microseconds, that is needed + after activating all column gpios. + default: 0 + + drive-inactive-cols: + type: boolean + description: + Drive inactive columns during scan, + default is to turn inactive columns into inputs. + + wakeup-source: true + +required: + - compatible + - row-gpios + - col-gpios + - linux,keymap + +additionalProperties: false + +examples: + - | + matrix-keypad { + compatible = "gpio-matrix-keypad"; + debounce-delay-ms = <5>; + col-scan-delay-us = <2>; + + row-gpios = <&gpio2 25 0 + &gpio2 26 0 + &gpio2 27 0>; + + col-gpios = <&gpio2 21 0 + &gpio2 22 0>; + + linux,keymap = <0x0000008B + 0x0100009E + 0x02000069 + 0x0001006A + 0x0101001C + 0x0201006C>; + + wakeup-source; + }; diff --git a/Bindings/input/mediatek,mt6779-keypad.yaml b/Bindings/input/mediatek,mt6779-keypad.yaml index 517a4ac1bea..e365413732e 100644 --- a/Bindings/input/mediatek,mt6779-keypad.yaml +++ b/Bindings/input/mediatek,mt6779-keypad.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Mediatek's Keypad Controller maintainers: - - Mattijs Korpershoek + - Mattijs Korpershoek allOf: - $ref: /schemas/input/matrix-keymap.yaml# diff --git a/Bindings/input/qcom,pm8921-keypad.yaml b/Bindings/input/qcom,pm8921-keypad.yaml index 88764adcd69..e03611eef93 100644 --- a/Bindings/input/qcom,pm8921-keypad.yaml +++ b/Bindings/input/qcom,pm8921-keypad.yaml @@ -62,28 +62,28 @@ unevaluatedProperties: false examples: - | - #include - #include - pmic { - #address-cells = <1>; - #size-cells = <0>; + #include + #include + pmic { + #address-cells = <1>; + #size-cells = <0>; - keypad@148 { - compatible = "qcom,pm8921-keypad"; - reg = <0x148>; - interrupt-parent = <&pmicintc>; - interrupts = <74 IRQ_TYPE_EDGE_RISING>, <75 IRQ_TYPE_EDGE_RISING>; - linux,keymap = < - MATRIX_KEY(0, 0, KEY_VOLUMEUP) - MATRIX_KEY(0, 1, KEY_VOLUMEDOWN) - MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS) - MATRIX_KEY(0, 3, KEY_CAMERA) - >; - keypad,num-rows = <1>; - keypad,num-columns = <5>; - debounce = <15>; - scan-delay = <32>; - row-hold = <91500>; - }; - }; + keypad@148 { + compatible = "qcom,pm8921-keypad"; + reg = <0x148>; + interrupt-parent = <&pmicintc>; + interrupts = <74 IRQ_TYPE_EDGE_RISING>, <75 IRQ_TYPE_EDGE_RISING>; + linux,keymap = < + MATRIX_KEY(0, 0, KEY_VOLUMEUP) + MATRIX_KEY(0, 1, KEY_VOLUMEDOWN) + MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS) + MATRIX_KEY(0, 3, KEY_CAMERA) + >; + keypad,num-rows = <1>; + keypad,num-columns = <5>; + debounce = <15>; + scan-delay = <32>; + row-hold = <91500>; + }; + }; ... diff --git a/Bindings/input/qcom,pm8921-pwrkey.yaml b/Bindings/input/qcom,pm8921-pwrkey.yaml index 12c74c08325..64590894857 100644 --- a/Bindings/input/qcom,pm8921-pwrkey.yaml +++ b/Bindings/input/qcom,pm8921-pwrkey.yaml @@ -52,24 +52,24 @@ unevaluatedProperties: false examples: - | - #include - ssbi { - #address-cells = <1>; - #size-cells = <0>; + #include + ssbi { + #address-cells = <1>; + #size-cells = <0>; - pmic@0 { - reg = <0x0>; - #address-cells = <1>; - #size-cells = <0>; + pmic@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; - pwrkey@1c { - compatible = "qcom,pm8921-pwrkey"; - reg = <0x1c>; - interrupt-parent = <&pmicint>; - interrupts = <50 IRQ_TYPE_EDGE_RISING>, <51 IRQ_TYPE_EDGE_RISING>; - debounce = <15625>; - pull-up; - }; - }; - }; + pwrkey@1c { + compatible = "qcom,pm8921-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pmicint>; + interrupts = <50 IRQ_TYPE_EDGE_RISING>, <51 IRQ_TYPE_EDGE_RISING>; + debounce = <15625>; + pull-up; + }; + }; + }; ... diff --git a/Bindings/input/touchscreen/apple,z2-multitouch.yaml b/Bindings/input/touchscreen/apple,z2-multitouch.yaml new file mode 100644 index 00000000000..402ca6bffd3 --- /dev/null +++ b/Bindings/input/touchscreen/apple,z2-multitouch.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/apple,z2-multitouch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple touchscreens attached using the Z2 protocol + +maintainers: + - Sasha Finkelstein + +description: A series of touschscreen controllers used in Apple products + +allOf: + - $ref: touchscreen.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - apple,j293-touchbar + - apple,j493-touchbar + + interrupts: + maxItems: 1 + + reset-gpios: + maxItems: 1 + + firmware-name: + maxItems: 1 + + apple,z2-cal-blob: + $ref: /schemas/types.yaml#/definitions/uint8-array + maxItems: 4096 + description: + Calibration blob supplied by the bootloader + +required: + - compatible + - interrupts + - reset-gpios + - firmware-name + - touchscreen-size-x + - touchscreen-size-y + +unevaluatedProperties: false + +examples: + - | + #include + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@0 { + compatible = "apple,j293-touchbar"; + reg = <0>; + spi-max-frequency = <11500000>; + reset-gpios = <&pinctrl_ap 139 GPIO_ACTIVE_LOW>; + interrupts-extended = <&pinctrl_ap 194 IRQ_TYPE_EDGE_FALLING>; + firmware-name = "apple/dfrmtfw-j293.bin"; + touchscreen-size-x = <23045>; + touchscreen-size-y = <640>; + }; + }; + +... diff --git a/Bindings/input/touchscreen/goodix,gt9916.yaml b/Bindings/input/touchscreen/goodix,gt9916.yaml index d90f045ac06..c40d92b7f4a 100644 --- a/Bindings/input/touchscreen/goodix,gt9916.yaml +++ b/Bindings/input/touchscreen/goodix,gt9916.yaml @@ -19,6 +19,7 @@ allOf: properties: compatible: enum: + - goodix,gt9897 - goodix,gt9916 reg: diff --git a/Bindings/input/touchscreen/ti,ads7843.yaml b/Bindings/input/touchscreen/ti,ads7843.yaml index 604921733d2..8f6335d7da1 100644 --- a/Bindings/input/touchscreen/ti,ads7843.yaml +++ b/Bindings/input/touchscreen/ti,ads7843.yaml @@ -164,20 +164,20 @@ examples: #size-cells = <0>; touchscreen@0 { - compatible = "ti,tsc2046"; - reg = <0>; /* CS0 */ - interrupt-parent = <&gpio1>; - interrupts = <8 0>; /* BOOT6 / GPIO 8 */ - pendown-gpio = <&gpio1 8 0>; - spi-max-frequency = <1000000>; - vcc-supply = <®_vcc3>; - wakeup-source; - - ti,pressure-max = /bits/ 16 <255>; - ti,x-max = /bits/ 16 <8000>; - ti,x-min = /bits/ 16 <0>; - ti,x-plate-ohms = /bits/ 16 <40>; - ti,y-max = /bits/ 16 <4800>; - ti,y-min = /bits/ 16 <0>; - }; + compatible = "ti,tsc2046"; + reg = <0>; /* CS0 */ + interrupt-parent = <&gpio1>; + interrupts = <8 0>; /* BOOT6 / GPIO 8 */ + pendown-gpio = <&gpio1 8 0>; + spi-max-frequency = <1000000>; + vcc-supply = <®_vcc3>; + wakeup-source; + + ti,pressure-max = /bits/ 16 <255>; + ti,x-max = /bits/ 16 <8000>; + ti,x-min = /bits/ 16 <0>; + ti,x-plate-ohms = /bits/ 16 <40>; + ti,y-max = /bits/ 16 <4800>; + ti,y-min = /bits/ 16 <0>; + }; }; diff --git a/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml index f49b43f45f3..06e3621a8c0 100644 --- a/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml +++ b/Bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml @@ -26,6 +26,7 @@ properties: deprecated: true - const: allwinner,sun7i-a20-sc-nmi - const: allwinner,sun9i-a80-nmi + - const: allwinner,sun55i-a523-nmi - items: - enum: - allwinner,sun8i-v3s-nmi diff --git a/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml index a9374476378..3d60d9e9e20 100644 --- a/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml +++ b/Bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml @@ -35,6 +35,9 @@ properties: - amlogic,meson-sm1-gpio-intc - amlogic,meson-a1-gpio-intc - amlogic,meson-s4-gpio-intc + - amlogic,a4-gpio-intc + - amlogic,a4-gpio-ao-intc + - amlogic,a5-gpio-intc - amlogic,c3-gpio-intc - amlogic,t7-gpio-intc - const: amlogic,meson-gpio-intc @@ -49,7 +52,7 @@ properties: amlogic,channel-interrupts: description: Array with the upstream hwirq numbers - minItems: 8 + minItems: 2 maxItems: 12 $ref: /schemas/types.yaml#/definitions/uint32-array @@ -60,6 +63,20 @@ required: - "#interrupt-cells" - amlogic,channel-interrupts +if: + properties: + compatible: + contains: + const: amlogic,a4-gpio-ao-intc +then: + properties: + amlogic,channel-interrupts: + maxItems: 2 +else: + properties: + amlogic,channel-interrupts: + minItems: 8 + additionalProperties: false examples: diff --git a/Bindings/interrupt-controller/brcm,bcm2712-msix.yaml b/Bindings/interrupt-controller/brcm,bcm2712-msix.yaml new file mode 100644 index 00000000000..c84614663b5 --- /dev/null +++ b/Bindings/interrupt-controller/brcm,bcm2712-msix.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2712-msix.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom bcm2712 MSI-X Interrupt Peripheral support + +maintainers: + - Stanimir Varbanov + +description: + This interrupt controller is used to provide interrupt vectors to the + generic interrupt controller (GIC) on bcm2712. It will be used as + external MSI-X controller for PCIe root complex. + +allOf: + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + const: brcm,bcm2712-mip + + reg: + items: + - description: Base register address + - description: PCIe message address + + "#msi-cells": + const: 0 + + brcm,msi-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Shift the allocated MSI's. + +unevaluatedProperties: false + +required: + - compatible + - reg + - msi-controller + - msi-ranges + +examples: + - | + #include + + axi { + #address-cells = <2>; + #size-cells = <2>; + + msi-controller@1000130000 { + compatible = "brcm,bcm2712-mip"; + reg = <0x10 0x00130000 0x00 0xc0>, + <0xff 0xfffff000 0x00 0x1000>; + msi-controller; + #msi-cells = <0>; + msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>; + }; + }; diff --git a/Bindings/interrupt-controller/fsl,irqsteer.yaml b/Bindings/interrupt-controller/fsl,irqsteer.yaml index 6076ddf56bb..c49688be105 100644 --- a/Bindings/interrupt-controller/fsl,irqsteer.yaml +++ b/Bindings/interrupt-controller/fsl,irqsteer.yaml @@ -19,6 +19,7 @@ properties: - fsl,imx8mp-irqsteer - fsl,imx8qm-irqsteer - fsl,imx8qxp-irqsteer + - fsl,imx94-irqsteer - const: fsl,imx-irqsteer reg: diff --git a/Bindings/interrupt-controller/nxp,lpc3220-mic.txt b/Bindings/interrupt-controller/nxp,lpc3220-mic.txt deleted file mode 100644 index 0bfb3ba55f4..00000000000 --- a/Bindings/interrupt-controller/nxp,lpc3220-mic.txt +++ /dev/null @@ -1,58 +0,0 @@ -* NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers - -Required properties: -- compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic". -- reg: should contain IC registers location and length. -- interrupt-controller: identifies the node as an interrupt controller. -- #interrupt-cells: the number of cells to define an interrupt, should be 2. - The first cell is the IRQ number, the second cell is used to specify - one of the supported IRQ types: - IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, - IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, - IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, - IRQ_TYPE_LEVEL_LOW = active low level-sensitive. - Reset value is IRQ_TYPE_LEVEL_LOW. - -Optional properties: -- interrupts: empty for MIC interrupt controller, cascaded MIC - hardware interrupts for SIC1 and SIC2 - -Examples: - - /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */ - mic: interrupt-controller@40008000 { - compatible = "nxp,lpc3220-mic"; - reg = <0x40008000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - sic1: interrupt-controller@4000c000 { - compatible = "nxp,lpc3220-sic"; - reg = <0x4000c000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&mic>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>, - <30 IRQ_TYPE_LEVEL_LOW>; - }; - - sic2: interrupt-controller@40010000 { - compatible = "nxp,lpc3220-sic"; - reg = <0x40010000 0x4000>; - interrupt-controller; - #interrupt-cells = <2>; - - interrupt-parent = <&mic>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>, - <31 IRQ_TYPE_LEVEL_LOW>; - }; - - /* ADC */ - adc@40048000 { - compatible = "nxp,lpc3220-adc"; - reg = <0x40048000 0x1000>; - interrupt-parent = <&sic1>; - interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; - }; diff --git a/Bindings/interrupt-controller/nxp,lpc3220-mic.yaml b/Bindings/interrupt-controller/nxp,lpc3220-mic.yaml new file mode 100644 index 00000000000..724c869e3c4 --- /dev/null +++ b/Bindings/interrupt-controller/nxp,lpc3220-mic.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/nxp,lpc3220-mic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers + +maintainers: + - Vladimir Zapolskiy + +properties: + compatible: + enum: + - nxp,lpc3220-mic + - nxp,lpc3220-sic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + items: + - description: Regular interrupt request + - description: Fast interrupt request + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + +allOf: + - if: + properties: + compatible: + contains: + const: nxp,lpc3220-sic + then: + required: + - interrupts + +additionalProperties: false + +examples: + - | + #include + + mic: interrupt-controller@40008000 { + compatible = "nxp,lpc3220-mic"; + reg = <0x40008000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + interrupt-controller@4000c000 { + compatible = "nxp,lpc3220-sic"; + reg = <0x4000c000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&mic>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>, + <30 IRQ_TYPE_LEVEL_LOW>; + }; diff --git a/Bindings/interrupt-controller/renesas,rzv2h-icu.yaml b/Bindings/interrupt-controller/renesas,rzv2h-icu.yaml index d7ef4f1323a..3f99c864576 100644 --- a/Bindings/interrupt-controller/renesas,rzv2h-icu.yaml +++ b/Bindings/interrupt-controller/renesas,rzv2h-icu.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzv2h-icu.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/V2H(P) Interrupt Control Unit +title: Renesas RZ/{G3E,V2H(P)} Interrupt Control Unit maintainers: - Fabrizio Castro @@ -20,7 +20,9 @@ description: properties: compatible: - const: renesas,r9a09g057-icu # RZ/V2H(P) + enum: + - renesas,r9a09g047-icu # RZ/G3E + - renesas,r9a09g057-icu # RZ/V2H(P) '#interrupt-cells': description: The first cell is the SPI number of the NMI or the diff --git a/Bindings/interrupt-controller/riscv,aplic.yaml b/Bindings/interrupt-controller/riscv,aplic.yaml index 190a6499c93..bef00521d5d 100644 --- a/Bindings/interrupt-controller/riscv,aplic.yaml +++ b/Bindings/interrupt-controller/riscv,aplic.yaml @@ -91,6 +91,14 @@ properties: Firmware must configure interrupt delegation registers based on interrupt delegation list. + riscv,hart-indexes: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 16384 + description: + A list of hart indexes that APLIC should use to address each hart + that is mentioned in the "interrupts-extended" + dependencies: riscv,delegation: [ "riscv,children" ] diff --git a/Bindings/interrupt-controller/sophgo,sg2042-msi.yaml b/Bindings/interrupt-controller/sophgo,sg2042-msi.yaml new file mode 100644 index 00000000000..e1ffd55fa7b --- /dev/null +++ b/Bindings/interrupt-controller/sophgo,sg2042-msi.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/sophgo,sg2042-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 MSI Controller + +maintainers: + - Chen Wang + +description: + This interrupt controller is in Sophgo SG2042 for transforming interrupts from + PCIe MSI to PLIC interrupts. + +allOf: + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + const: sophgo,sg2042-msi + + reg: + items: + - description: clear register + - description: msi doorbell address + + reg-names: + items: + - const: clr + - const: doorbell + + msi-controller: true + + msi-ranges: + maxItems: 1 + + "#msi-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - msi-controller + - msi-ranges + - "#msi-cells" + +unevaluatedProperties: false + +examples: + - | + #include + msi-controller@30000000 { + compatible = "sophgo,sg2042-msi"; + reg = <0x30000000 0x4>, <0x30000008 0x4>; + reg-names = "clr", "doorbell"; + msi-controller; + #msi-cells = <0>; + msi-ranges = <&plic 64 IRQ_TYPE_LEVEL_HIGH 32>; + }; diff --git a/Bindings/iommu/arm,smmu.yaml b/Bindings/iommu/arm,smmu.yaml index 032fdc27127..7b9d5507d6c 100644 --- a/Bindings/iommu/arm,smmu.yaml +++ b/Bindings/iommu/arm,smmu.yaml @@ -90,6 +90,7 @@ properties: - enum: - qcom,qcm2290-smmu-500 - qcom,qcs615-smmu-500 + - qcom,qcs8300-smmu-500 - qcom,sa8255p-smmu-500 - qcom,sa8775p-smmu-500 - qcom,sar2130p-smmu-500 @@ -397,6 +398,7 @@ allOf: compatible: contains: enum: + - qcom,qcs8300-smmu-500 - qcom,sa8775p-smmu-500 - qcom,sc7280-smmu-500 - qcom,sc8280xp-smmu-500 @@ -581,7 +583,6 @@ allOf: - cavium,smmu-v2 - marvell,ap806-smmu-500 - nvidia,smmu-500 - - qcom,qcs8300-smmu-500 - qcom,qdu1000-smmu-500 - qcom,sa8255p-smmu-500 - qcom,sc7180-smmu-500 diff --git a/Bindings/iommu/qcom,iommu.yaml b/Bindings/iommu/qcom,iommu.yaml index 5ae9a628261..3e5623edd20 100644 --- a/Bindings/iommu/qcom,iommu.yaml +++ b/Bindings/iommu/qcom,iommu.yaml @@ -22,6 +22,7 @@ properties: - enum: - qcom,msm8916-iommu - qcom,msm8917-iommu + - qcom,msm8937-iommu - qcom,msm8953-iommu - const: qcom,msm-iommu-v1 - items: diff --git a/Bindings/leds/backlight/apple,dwi-bl.yaml b/Bindings/leds/backlight/apple,dwi-bl.yaml new file mode 100644 index 00000000000..29caeb356e6 --- /dev/null +++ b/Bindings/leds/backlight/apple,dwi-bl.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/apple,dwi-bl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple DWI 2-Wire Interface Backlight Controller + +maintainers: + - Nick Chan + +description: + Apple SoCs contain a 2-wire interface called DWI. On some Apple iPhones, + iPads and iPod touches with a LCD display, 1-2 backlight controllers + are connected via DWI. Interfacing with DWI controls all backlight + controllers at the same time. As such, the backlight controllers are + treated as a single controller regardless of the underlying + configuration. + +allOf: + - $ref: common.yaml# + +properties: + compatible: + items: + - enum: + - apple,s5l8960x-dwi-bl + - apple,t7000-dwi-bl + - apple,s8000-dwi-bl + - apple,t8010-dwi-bl + - apple,t8015-dwi-bl + - const: apple,dwi-bl + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + dwi_bl: backlight@20e200010 { + compatible = "apple,s5l8960x-dwi-bl", "apple,dwi-bl"; + reg = <0x2 0x0e200010 0x0 0x8>; + power-domains = <&ps_dwi>; + }; + }; diff --git a/Bindings/leds/leds-qcom-lpg.yaml b/Bindings/leds/leds-qcom-lpg.yaml index 8b82c45d1a4..841a0229c47 100644 --- a/Bindings/leds/leds-qcom-lpg.yaml +++ b/Bindings/leds/leds-qcom-lpg.yaml @@ -39,6 +39,10 @@ properties: - enum: - qcom,pm8550-pwm - const: qcom,pm8350c-pwm + - items: + - enum: + - qcom,pm8937-pwm + - const: qcom,pm8916-pwm "#pwm-cells": const: 2 diff --git a/Bindings/leds/leds-tlc591xx.txt b/Bindings/leds/leds-tlc591xx.txt deleted file mode 100644 index 3bbbf702441..00000000000 --- a/Bindings/leds/leds-tlc591xx.txt +++ /dev/null @@ -1,40 +0,0 @@ -LEDs connected to tlc59116 or tlc59108 - -Required properties -- compatible: should be "ti,tlc59116" or "ti,tlc59108" -- #address-cells: must be 1 -- #size-cells: must be 0 -- reg: typically 0x68 - -Each led is represented as a sub-node of the ti,tlc59116. -See Documentation/devicetree/bindings/leds/common.txt - -LED sub-node properties: -- reg: number of LED line, 0 to 15 or 0 to 7 -- label: (optional) name of LED -- linux,default-trigger : (optional) - -Examples: - -tlc59116@68 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "ti,tlc59116"; - reg = <0x68>; - - wan@0 { - label = "wrt1900ac:amber:wan"; - reg = <0x0>; - }; - - 2g@2 { - label = "wrt1900ac:white:2g"; - reg = <0x2>; - }; - - alive@9 { - label = "wrt1900ac:green:alive"; - reg = <0x9>; - linux,default_trigger = "heartbeat"; - }; -}; diff --git a/Bindings/leds/ti,tlc59116.yaml b/Bindings/leds/ti,tlc59116.yaml new file mode 100644 index 00000000000..ce971379390 --- /dev/null +++ b/Bindings/leds/ti,tlc59116.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/ti,tlc59116.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LEDs connected to tlc59116 or tlc59108 + +maintainers: + - Andrew Lunn + +properties: + compatible: + enum: + - ti,tlc59108 + - ti,tlc59116 + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^led@[0-9a-f]$": + type: object + $ref: common.yaml# + properties: + reg: + items: + minimum: 0 + maximum: 15 + + unevaluatedProperties: false + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +allOf: + - if: + properties: + compatible: + contains: + const: ti,tlc59108 + then: + patternProperties: + "^led@[0-9a-f]$": + properties: + reg: + items: + maximum: 7 + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@68 { + compatible = "ti,tlc59116"; + reg = <0x68>; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0x0>; + label = "wrt1900ac:amber:wan"; + }; + + led@2 { + reg = <0x2>; + label = "wrt1900ac:white:2g"; + }; + + led@9 { + reg = <0x9>; + label = "wrt1900ac:green:alive"; + linux,default-trigger = "heartbeat"; + }; + }; + }; + diff --git a/Bindings/mailbox/fsl,mu.yaml b/Bindings/mailbox/fsl,mu.yaml index 00631afcd51..581425aacdc 100644 --- a/Bindings/mailbox/fsl,mu.yaml +++ b/Bindings/mailbox/fsl,mu.yaml @@ -54,6 +54,10 @@ properties: - fsl,imx8qm-mu - fsl,imx8qxp-mu - const: fsl,imx6sx-mu + - items: + - enum: + - fsl,imx94-mu + - const: fsl,imx95-mu reg: maxItems: 1 @@ -142,7 +146,8 @@ allOf: not: properties: compatible: - const: fsl,imx95-mu + contains: + const: fsl,imx95-mu then: patternProperties: "^sram@[a-f0-9]+": false diff --git a/Bindings/mailbox/mediatek,gce-mailbox.yaml b/Bindings/mailbox/mediatek,gce-mailbox.yaml index cef9d760139..73d6db34d64 100644 --- a/Bindings/mailbox/mediatek,gce-mailbox.yaml +++ b/Bindings/mailbox/mediatek,gce-mailbox.yaml @@ -25,6 +25,7 @@ properties: - mediatek,mt8188-gce - mediatek,mt8192-gce - mediatek,mt8195-gce + - mediatek,mt8196-gce - items: - const: mediatek,mt6795-gce - const: mediatek,mt8173-gce @@ -49,6 +50,9 @@ properties: items: - const: gce + iommus: + maxItems: 1 + required: - compatible - "#mbox-cells" diff --git a/Bindings/mailbox/qcom,apcs-kpss-global.yaml b/Bindings/mailbox/qcom,apcs-kpss-global.yaml index 78f68dacd02..a58a018f3f7 100644 --- a/Bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -26,6 +26,7 @@ properties: - const: qcom,ipq6018-apcs-apps-global - items: - enum: + - qcom,msm8226-apcs-kpss-global - qcom,qcs404-apcs-apps-global - const: qcom,msm8916-apcs-kpss-global - const: syscon diff --git a/Bindings/media/aspeed,video-engine.yaml b/Bindings/media/aspeed,video-engine.yaml new file mode 100644 index 00000000000..682bba20778 --- /dev/null +++ b/Bindings/media/aspeed,video-engine.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/aspeed,video-engine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED Video Engine + +maintainers: + - Eddie James + +description: + The Video Engine (VE) embedded in the ASPEED SOCs can be configured to + capture and compress video data from digital or analog sources. + +properties: + compatible: + enum: + - aspeed,ast2400-video-engine + - aspeed,ast2500-video-engine + - aspeed,ast2600-video-engine + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: vclk + - const: eclk + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + memory-region: + maxItems: 1 + description: | + Phandle to the reserved memory nodes to be associated with the + VE. VE will acquires memory space for 3 purposes: + 1. JPEG header + 2. Compressed result + 3. Temporary transformed image data + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + + video@1e700000 { + compatible = "aspeed,ast2600-video-engine"; + reg = <0x1e700000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_VCLK>, + <&syscon ASPEED_CLK_GATE_ECLK>; + clock-names = "vclk", "eclk"; + interrupts = ; + }; diff --git a/Bindings/media/aspeed-video.txt b/Bindings/media/aspeed-video.txt deleted file mode 100644 index d2ca3251227..00000000000 --- a/Bindings/media/aspeed-video.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Device tree bindings for Aspeed Video Engine - -The Video Engine (VE) embedded in the Aspeed AST2400/2500/2600 SOCs can -capture and compress video data from digital or analog sources. - -Required properties: - - compatible: "aspeed,ast2400-video-engine" or - "aspeed,ast2500-video-engine" or - "aspeed,ast2600-video-engine" - - reg: contains the offset and length of the VE memory region - - clocks: clock specifiers for the syscon clocks associated with - the VE (ordering must match the clock-names property) - - clock-names: "vclk" and "eclk" - - resets: reset specifier for the syscon reset associated with - the VE - - interrupts: the interrupt associated with the VE on this platform - -Optional properties: - - memory-region: - phandle to a memory region to allocate from, as defined in - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt - -Example: - -video-engine@1e700000 { - compatible = "aspeed,ast2500-video-engine"; - reg = <0x1e700000 0x20000>; - clocks = <&syscon ASPEED_CLK_GATE_VCLK>, <&syscon ASPEED_CLK_GATE_ECLK>; - clock-names = "vclk", "eclk"; - resets = <&syscon ASPEED_RESET_VIDEO>; - interrupts = <7>; - memory-region = <&video_engine_memory>; -}; diff --git a/Bindings/media/i2c/adv7180.yaml b/Bindings/media/i2c/adv7180.yaml index 4371a0ef276..9ee1483775f 100644 --- a/Bindings/media/i2c/adv7180.yaml +++ b/Bindings/media/i2c/adv7180.yaml @@ -49,6 +49,10 @@ properties: Indicates that the output is a BT.656-4 compatible stream. type: boolean + interrupts: + items: + - description: The GPIO connected to the INTRQ pin. + port: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false diff --git a/Bindings/media/i2c/st,st-mipid02.yaml b/Bindings/media/i2c/st,st-mipid02.yaml index b68141264c0..4d40e75b4e1 100644 --- a/Bindings/media/i2c/st,st-mipid02.yaml +++ b/Bindings/media/i2c/st,st-mipid02.yaml @@ -71,7 +71,7 @@ properties: description: Any lane can be inverted or not. minItems: 1 - maxItems: 2 + maxItems: 3 required: - data-lanes diff --git a/Bindings/media/mediatek,vcodec-encoder.yaml b/Bindings/media/mediatek,vcodec-encoder.yaml index 110e8f5f1f9..ebc615584f9 100644 --- a/Bindings/media/mediatek,vcodec-encoder.yaml +++ b/Bindings/media/mediatek,vcodec-encoder.yaml @@ -41,10 +41,6 @@ properties: minItems: 1 maxItems: 5 - assigned-clocks: true - - assigned-clock-parents: true - iommus: minItems: 1 maxItems: 32 @@ -78,8 +74,6 @@ required: - clocks - clock-names - iommus - - assigned-clocks - - assigned-clock-parents allOf: - if: diff --git a/Bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Bindings/media/mediatek,vcodec-subdev-decoder.yaml index 5865e6f0be8..bf8082d87ac 100644 --- a/Bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -4,52 +4,70 @@ $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Mediatek Video Decode Accelerator With Multi Hardware +title: MediaTek Video Decode Accelerator With Multi Hardware maintainers: - Yunfei Dong description: | - Mediatek Video Decode is the video decode hardware present in Mediatek - SoCs which supports high resolution decoding functionalities. Required - parent and child device node. - - About the Decoder Hardware Block Diagram, please check below: - - +------------------------------------------------+-------------------------------------+ - | | | - | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output | - | || || | || | - +------------||-------------||-------------------+---------------------||--------------+ - || lat || | core workqueue - -------------||-------------||-------------------|---------------------||--------------- - ||<------------||----------------HW index---------------->|| - \/ \/ \/ - +-------------------------------------------------------------+ - | enable/disable | - | clk power irq iommu | - | (lat/lat soc/core0/core1) | - +-------------------------------------------------------------+ - - As above, there are parent and child devices, child mean each hardware. The child device - controls the information of each hardware independent which include clk/power/irq. - - There are two workqueues in parent device: lat workqueue and core workqueue. They are used - to lat and core hardware decoder. Lat workqueue need to get input bitstream and lat buffer, - then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode - done. Core workqueue need to get lat buffer and output buffer, then enable core to decode, - writing the result to output buffer, disable hardware when core decode done. These two - hardwares will decode each frame cyclically. - - For the smi common may not the same for each hardware, can't combine all hardware in one node, - or leading to iommu fault when access dram data. - - Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195 - platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and - clock when lat start to work, don't have interrupt. - - mt8195: lat soc HW + lat HW + core HW - mt8192: lat HW + core HW + MediaTek Video Decode Accelerator is the video decoding hardware present in + MediaTek SoCs that supports high-resolution decoding functionalities. + It consists of parent and child nodes. + + The decoder hardware block diagram is shown below: + + +------------------------------------------------+------------------------------+ + | | | + | input -> LAT-SoC HW -> LAT HW -> LAT buffer --|--> Core HW -> output buffer | + | || || | || | + +--------------||-----------||-------------------+-------||---------------------+ + LAT Workqueue | Core Workqueue + ---------------||-----------||-------------------|-------||---------------------- + ||<----------||---------HW index--------->|| + \/ \/ \/ + +-------------------------------------------------------------+ + | enable/disable | + | clk power irq iommu | + | (lat/lat-soc/core0/core1) | + +-------------------------------------------------------------+ + + The child nodes represent the individual hardware blocks within the decoding + pipeline, such as LAT-SoC, LAT and Core. + Each child node is responsible for managing the dedicated resources of the + hardware, such as clocks, power domains, interrupts and IOMMUs. + + The parent node is a central point of control for the child nodes. + It identifies the specific video decoding pipeline architecture used by the + SoC, manages the shared resources like workqueues and platform data, and + handles V4L2 API calls on behalf of the underlying hardware. + + The parent utilizes two workqueues to manage the decoding process. + 1. LAT Workqueue, for LAT-SoC and LAT decoder: + Its workers take input bitstream and LAT buffer, enable the hardware for + decoding tasks, write the result to LAT buffer, and disable the hardware + after the LAT decoding is done. + 2. Core Workqueue, for Core decoder: + Its workers take LAT buffer and output buffer, enable the hardware for + decoding tasks, write the result to output buffer, and disable the hardware + after the Core decoding is done. + + These hardware decode each frame cyclically. + + The hardware might be associated with different SMI-common devices. + To prevent IOMMU faults during DRAM access in such cases, each hardware with + the unique SMI-common device must be placed under a separate parent node in + the device tree. + + LAT-SoC refers to another hardware block that connected to additional LARB + (local arbiter) ports, such as RDMA and UFO. + It requires independent power and clock control to work with LAT decoder, and + it doesn't have a dedicated interrupt. + + The used video decoding pipeline architecture across various Mediatek SoC: + MT8195: LAT-SoC + LAT + Core + MT8192: LAT + Core + MT8188: LAT + Core + MT8186: Core properties: compatible: diff --git a/Bindings/media/mediatek-jpeg-decoder.yaml b/Bindings/media/mediatek-jpeg-decoder.yaml index cfabf360f27..a4aacd3eb18 100644 --- a/Bindings/media/mediatek-jpeg-decoder.yaml +++ b/Bindings/media/mediatek-jpeg-decoder.yaml @@ -44,7 +44,8 @@ properties: maxItems: 1 iommus: - maxItems: 2 + minItems: 2 + maxItems: 32 description: | Points to the respective IOMMU block with master port as argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. diff --git a/Bindings/media/mediatek-jpeg-encoder.yaml b/Bindings/media/mediatek-jpeg-encoder.yaml index 83c020a673d..5b15f8977f6 100644 --- a/Bindings/media/mediatek-jpeg-encoder.yaml +++ b/Bindings/media/mediatek-jpeg-encoder.yaml @@ -39,7 +39,7 @@ properties: iommus: minItems: 2 - maxItems: 4 + maxItems: 32 description: | Points to the respective IOMMU block with master port as argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. diff --git a/Bindings/media/qcom,sc7280-camss.yaml b/Bindings/media/qcom,sc7280-camss.yaml index e11141b812a..ee35e3bc97f 100644 --- a/Bindings/media/qcom,sc7280-camss.yaml +++ b/Bindings/media/qcom,sc7280-camss.yaml @@ -55,8 +55,8 @@ properties: - const: csiphy3_timer - const: csiphy4 - const: csiphy4_timer - - const: gcc_camera_ahb - - const: gcc_cam_hf_axi + - const: gcc_axi_hf + - const: gcc_axi_sf - const: icp_ahb - const: vfe0 - const: vfe0_axi @@ -310,8 +310,8 @@ examples: <&camcc CAM_CC_CSI3PHYTIMER_CLK>, <&camcc CAM_CC_CSIPHY4_CLK>, <&camcc CAM_CC_CSI4PHYTIMER_CLK>, - <&gcc GCC_CAMERA_AHB_CLK>, <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, <&camcc CAM_CC_ICP_AHB_CLK>, <&camcc CAM_CC_IFE_0_CLK>, <&camcc CAM_CC_IFE_0_AXI_CLK>, @@ -343,8 +343,8 @@ examples: "csiphy3_timer", "csiphy4", "csiphy4_timer", - "gcc_camera_ahb", - "gcc_cam_hf_axi", + "gcc_axi_hf", + "gcc_axi_sf", "icp_ahb", "vfe0", "vfe0_axi", diff --git a/Bindings/media/qcom,sdm670-camss.yaml b/Bindings/media/qcom,sdm670-camss.yaml new file mode 100644 index 00000000000..35c40fe2237 --- /dev/null +++ b/Bindings/media/qcom,sdm670-camss.yaml @@ -0,0 +1,318 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sdm670-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM670 Camera Subsystem (CAMSS) + +maintainers: + - Richard Acayan + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sdm670-camss + + reg: + maxItems: 9 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite + + interrupts: + maxItems: 9 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite + + clocks: + maxItems: 22 + + clock-names: + items: + - const: camnoc_axi + - const: cpas_ahb + - const: csi0 + - const: csi1 + - const: csi2 + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: gcc_camera_ahb + - const: gcc_camera_axi + - const: soc_ahb + - const: vfe0 + - const: vfe0_axi + - const: vfe0_cphy_rx + - const: vfe1 + - const: vfe1_axi + - const: vfe1_cphy_rx + - const: vfe_lite + - const: vfe_lite_cphy_rx + + iommus: + maxItems: 4 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: top + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY0. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY1. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data from CSIPHY2. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - clock-lanes + - data-lanes + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - clock-names + - iommus + - power-domains + - power-domain-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@acb3000 { + compatible = "qcom,sdm670-camss"; + + reg = <0 0x0acb3000 0 0x1000>, + <0 0x0acba000 0 0x1000>, + <0 0x0acc8000 0 0x1000>, + <0 0x0ac65000 0 0x1000>, + <0 0x0ac66000 0 0x1000>, + <0 0x0ac67000 0 0x1000>, + <0 0x0acaf000 0 0x4000>, + <0 0x0acb6000 0 0x4000>, + <0 0x0acc4000 0 0x4000>; + reg-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite"; + + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csiphy0", + "csiphy1", + "csiphy2", + "vfe0", + "vfe1", + "vfe_lite"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAM_CC_SOC_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "csi0", + "csi1", + "csi2", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "gcc_camera_ahb", + "gcc_camera_axi", + "soc_ahb", + "vfe0", + "vfe0_axi", + "vfe0_cphy_rx", + "vfe1", + "vfe1_axi", + "vfe1_cphy_rx", + "vfe_lite", + "vfe_lite_cphy_rx"; + + iommus = <&apps_smmu 0x808 0x0>, + <&apps_smmu 0x810 0x8>, + <&apps_smmu 0xc08 0x0>, + <&apps_smmu 0xc10 0x8>; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "top"; + + vdda-phy-supply = <&vreg_l1a_1p225>; + vdda-pll-supply = <&vreg_l8a_1p8>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy_ep0: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&front_sensor_ep>; + }; + }; + }; + }; + }; diff --git a/Bindings/media/qcom,sm8550-camss.yaml b/Bindings/media/qcom,sm8550-camss.yaml new file mode 100644 index 00000000000..cd34f14916b --- /dev/null +++ b/Bindings/media/qcom,sm8550-camss.yaml @@ -0,0 +1,597 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8550-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8550 Camera Subsystem (CAMSS) + +maintainers: + - Depeng Shao + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sm8550-camss + + reg: + maxItems: 19 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_wrapper + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: csiphy6 + - const: csiphy7 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + clocks: + maxItems: 36 + + clock-names: + items: + - const: camnoc_axi + - const: cpas_ahb + - const: cpas_fast_ahb_clk + - const: cpas_ife_lite + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: cpas_vfe2 + - const: csid + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: csiphy5 + - const: csiphy5_timer + - const: csiphy6 + - const: csiphy6_timer + - const: csiphy7 + - const: csiphy7_timer + - const: csiphy_rx + - const: gcc_axi_hf + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe2 + - const: vfe2_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 18 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: csiphy5 + - const: csiphy6 + - const: csiphy7 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: ahb + - const: hf_0_mnoc + + iommus: + maxItems: 1 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.2V regulator supply to PHY refclk pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI0. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI1. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI2. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI3. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@4: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI4. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@5: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI5. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@6: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI6. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + + port@7: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSI7. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + clock-lanes: + maxItems: 1 + + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - clock-lanes + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@acb7000 { + compatible = "qcom,sm8550-camss"; + + reg = <0 0x0acb7000 0 0xd00>, + <0 0x0acb9000 0 0xd00>, + <0 0x0acbb000 0 0xd00>, + <0 0x0acca000 0 0xa00>, + <0 0x0acce000 0 0xa00>, + <0 0x0acb6000 0 0x1000>, + <0 0x0ace4000 0 0x2000>, + <0 0x0ace6000 0 0x2000>, + <0 0x0ace8000 0 0x2000>, + <0 0x0acea000 0 0x2000>, + <0 0x0acec000 0 0x2000>, + <0 0x0acee000 0 0x2000>, + <0 0x0acf0000 0 0x2000>, + <0 0x0acf2000 0 0x2000>, + <0 0x0ac62000 0 0xf000>, + <0 0x0ac71000 0 0xf000>, + <0 0x0ac80000 0 0xf000>, + <0 0x0accb000 0 0x1800>, + <0 0x0accf000 0 0x1800>; + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csid_wrapper", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csiphy6", + "csiphy7", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CPAS_IFE_2_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY6_CLK>, + <&camcc CAM_CC_CSI6PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY7_CLK>, + <&camcc CAM_CC_CSI7PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_ife_lite", + "cpas_vfe0", + "cpas_vfe1", + "cpas_vfe2", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "csiphy6", + "csiphy6_timer", + "csiphy7", + "csiphy7_timer", + "csiphy_rx", + "gcc_axi_hf", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe2", + "vfe2_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csiphy6", + "csiphy7", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0_mnoc"; + + iommus = <&apps_smmu 0x800 0x20>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "ife0", + "ife1", + "ife2", + "top"; + + vdda-phy-supply = <&vreg_l1e_0p88>; + vdda-pll-supply = <&vreg_l3e_1p2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + csiphy_ep0: endpoint@0 { + reg = <0>; + clock-lanes = <7>; + data-lanes = <0 1>; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + }; diff --git a/Bindings/media/qcom,sm8550-iris.yaml b/Bindings/media/qcom,sm8550-iris.yaml new file mode 100644 index 00000000000..e424ea84c21 --- /dev/null +++ b/Bindings/media/qcom,sm8550-iris.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8550-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm iris video encode and decode accelerators + +maintainers: + - Vikash Garodia + - Dikshita Agarwal + +description: + The iris video processing unit is a video encode and decode accelerator + present on Qualcomm platforms. + +allOf: + - $ref: qcom,venus-common.yaml# + +properties: + compatible: + const: qcom,sm8550-iris + + power-domains: + maxItems: 4 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mxc + - const: mmcx + + clocks: + maxItems: 3 + + clock-names: + items: + - const: iface + - const: core + - const: vcodec0_core + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + resets: + maxItems: 1 + + reset-names: + items: + - const: bus + + iommus: + maxItems: 2 + + dma-coherent: true + + operating-points-v2: true + + opp-table: + type: object + +required: + - compatible + - power-domain-names + - interconnects + - interconnect-names + - resets + - reset-names + - iommus + - dma-coherent + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + #include + + video-codec@aa00000 { + compatible = "qcom,sm8550-iris"; + reg = <0x0aa00000 0xf0000>; + interrupts = ; + + power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, + <&videocc VIDEO_CC_MVS0_GDSC>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", "vcodec0", "mxc", "mmcx"; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc VIDEO_CC_MVS0C_CLK>, + <&videocc VIDEO_CC_MVS0_CLK>; + clock-names = "iface", "core", "vcodec0_core"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", "video-mem"; + + memory-region = <&video_mem>; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; + reset-names = "bus"; + + iommus = <&apps_smmu 0x1940 0x0000>, + <&apps_smmu 0x1947 0x0000>; + dma-coherent; + + operating-points-v2 = <&iris_opp_table>; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-366000000 { + opp-hz = /bits/ 64 <366000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + + opp-533333334 { + opp-hz = /bits/ 64 <533333334>; + required-opps = <&rpmhpd_opp_turbo_l1>, + <&rpmhpd_opp_turbo_l1>; + }; + }; + }; +... diff --git a/Bindings/media/snps,dw-hdmi-rx.yaml b/Bindings/media/snps,dw-hdmi-rx.yaml new file mode 100644 index 00000000000..510e94e9ca3 --- /dev/null +++ b/Bindings/media/snps,dw-hdmi-rx.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Device Tree bindings for Synopsys DesignWare HDMI RX Controller + +--- +$id: http://devicetree.org/schemas/media/snps,dw-hdmi-rx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synopsys DesignWare HDMI RX Controller + +maintainers: + - Shreeya Patel + +description: + Synopsys DesignWare HDMI Input Controller preset on RK3588 SoCs + allowing devices to receive and decode high-resolution video streams + from external sources like media players, cameras, laptops, etc. + +properties: + compatible: + items: + - const: rockchip,rk3588-hdmirx-ctrler + - const: snps,dw-hdmi-rx + + reg: + maxItems: 1 + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: cec + - const: hdmi + - const: dma + + clocks: + maxItems: 7 + + clock-names: + items: + - const: aclk + - const: audio + - const: cr_para + - const: pclk + - const: ref + - const: hclk_s_hdmirx + - const: hclk_vo1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 4 + + reset-names: + items: + - const: axi + - const: apb + - const: ref + - const: biu + + memory-region: + maxItems: 1 + + hpd-gpios: + description: GPIO specifier for HPD. + maxItems: 1 + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the general register file + containing HDMIRX PHY status bits. + + rockchip,vo1-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle of the syscon node for the Video Output GRF register + to enable EDID transfer through SDAIN and SCLIN. + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + - pinctrl-0 + - hpd-gpios + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + hdmi_receiver: hdmi-receiver@fdee0000 { + compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; + reg = <0xfdee0000 0x6000>; + interrupts = , + , + ; + interrupt-names = "cec", "hdmi", "dma"; + clocks = <&cru ACLK_HDMIRX>, + <&cru CLK_HDMIRX_AUD>, + <&cru CLK_CR_PARA>, + <&cru PCLK_HDMIRX>, + <&cru CLK_HDMIRX_REF>, + <&cru PCLK_S_HDMIRX>, + <&cru HCLK_VO1>; + clock-names = "aclk", + "audio", + "cr_para", + "pclk", + "ref", + "hclk_s_hdmirx", + "hclk_vo1"; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, + <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; + reset-names = "axi", "apb", "ref", "biu"; + memory-region = <&hdmi_receiver_cma>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_5v_detection>; + pinctrl-names = "default"; + hpd-gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; + }; diff --git a/Bindings/media/st,stm32mp25-csi.yaml b/Bindings/media/st,stm32mp25-csi.yaml index 33bedfe4192..e9fa3cfea5d 100644 --- a/Bindings/media/st,stm32mp25-csi.yaml +++ b/Bindings/media/st,stm32mp25-csi.yaml @@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: STMicroelectronics STM32 CSI controller description: - The STM32 CSI controller allows connecting a CSI based - camera to the DCMIPP camera pipeline. + The STM32 CSI controller, coupled with a D-PHY allows connecting a CSI-2 + based camera to the DCMIPP camera pipeline. maintainers: - Alain Volmat @@ -109,7 +109,6 @@ examples: endpoint { remote-endpoint = <&imx335_ep>; data-lanes = <1 2>; - bus-type = ; }; }; diff --git a/Bindings/memory-controllers/exynos-srom.yaml b/Bindings/memory-controllers/exynos-srom.yaml index a5598ade399..1578514ec58 100644 --- a/Bindings/memory-controllers/exynos-srom.yaml +++ b/Bindings/memory-controllers/exynos-srom.yaml @@ -38,50 +38,16 @@ properties: patternProperties: "^.*@[0-3],[a-f0-9]+$": type: object + $ref: mc-peripheral-props.yaml# additionalProperties: true - description: - The actual device nodes should be added as subnodes to the SROMc node. - These subnodes, in addition to regular device specification, should - contain the following properties, describing configuration - of the relevant SROM bank. properties: - reg: - description: - Bank number, base address (relative to start of the bank) and size - of the memory mapped for the device. Note that base address will be - typically 0 as this is the start of the bank. - maxItems: 1 - reg-io-width: enum: [1, 2] description: Data width in bytes (1 or 2). If omitted, default of 1 is used. - samsung,srom-page-mode: - description: - If page mode is set, 4 data page mode will be configured, - else normal (1 data) page mode will be set. - type: boolean - - samsung,srom-timing: - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 6 - maxItems: 6 - description: | - Array of 6 integers, specifying bank timings in the following order: - Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. - Each value is specified in cycles and has the following meaning - and valid range: - Tacp: Page mode access cycle at Page mode (0 - 15) - Tcah: Address holding time after CSn (0 - 15) - Tcoh: Chip selection hold on OEn (0 - 15) - Tacc: Access cycle (0 - 31, the actual time is N + 1) - Tcos: Chip selection set-up before OEn (0 - 15) - Tacs: Address set-up before CSn (0 - 15) - required: - - reg - samsung,srom-timing required: diff --git a/Bindings/memory-controllers/mc-peripheral-props.yaml b/Bindings/memory-controllers/mc-peripheral-props.yaml index 00deeb09f87..73a6dac946b 100644 --- a/Bindings/memory-controllers/mc-peripheral-props.yaml +++ b/Bindings/memory-controllers/mc-peripheral-props.yaml @@ -36,6 +36,8 @@ allOf: - $ref: st,stm32-fmc2-ebi-props.yaml# - $ref: ingenic,nemc-peripherals.yaml# - $ref: intel,ixp4xx-expansion-peripheral-props.yaml# + - $ref: qcom,ebi2-peripheral-props.yaml# + - $ref: samsung,exynos4210-srom-peripheral-props.yaml# - $ref: ti,gpmc-child.yaml# - $ref: fsl/fsl,imx-weim-peripherals.yaml diff --git a/Bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml b/Bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml new file mode 100644 index 00000000000..29f8c30e8a8 --- /dev/null +++ b/Bindings/memory-controllers/qcom,ebi2-peripheral-props.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2-peripheral-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral Properties for Qualcomm External Bus Interface 2 (EBI2) + +maintainers: + - Bjorn Andersson + +properties: + # SLOW chip selects + qcom,xmem-recovery-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The time the memory continues to drive the data bus after OE + is de-asserted, in order to avoid contention on the data bus. + They are inserted when reading one CS and switching to another + CS or read followed by write on the same CS. Minimum value is + actually 1, so a value of 0 will still yield 1 recovery cycle. + minimum: 0 + maximum: 15 + + qcom,xmem-write-hold-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The extra cycles inserted after every write minimum 1. The + data out is driven from the time WE is asserted until CS is + asserted. With a hold of 1 (value = 0), the CS stays active + for 1 extra cycle, etc. + minimum: 0 + maximum: 15 + + qcom,xmem-write-delta-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The initial latency for write cycles inserted for the first + write to a page or burst memory. + minimum: 0 + maximum: 255 + + qcom,xmem-read-delta-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The initial latency for read cycles inserted for the first + read to a page or burst memory. + minimum: 0 + maximum: 255 + + qcom,xmem-write-wait-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The number of wait cycles for every write access. + minimum: 0 + maximum: 15 + + qcom,xmem-read-wait-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The number of wait cycles for every read access. + minimum: 0 + maximum: 15 + + + # FAST chip selects + qcom,xmem-address-hold-enable: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + Holds the address for an extra cycle to meet hold time + requirements with ADV assertion, when set to 1. + enum: [ 0, 1 ] + + qcom,xmem-adv-to-oe-recovery-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The number of cycles elapsed before an OE assertion, with + respect to the cycle where ADV (address valid) is asserted. + minimum: 0 + maximum: 3 + + qcom,xmem-read-hold-cycles: + $ref: /schemas/types.yaml#/definitions/uint32 + description: > + The length in cycles of the first segment of a read transfer. + For a single read transfer this will be the time from CS + assertion to OE assertion. + minimum: 0 + maximum: 15 + +additionalProperties: true diff --git a/Bindings/memory-controllers/qcom,ebi2.yaml b/Bindings/memory-controllers/qcom,ebi2.yaml new file mode 100644 index 00000000000..423d7a75134 --- /dev/null +++ b/Bindings/memory-controllers/qcom,ebi2.yaml @@ -0,0 +1,156 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/qcom,ebi2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm External Bus Interface 2 (EBI2) + +description: | + The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any + external memory (such as NAND or other memory-mapped peripherals) whereas + LCDC handles LCD displays. + + As it says it connects devices to an external bus interface, meaning address + lines (up to 9 address lines so can only address 1KiB external memory space), + data lines (16 bits), OE (output enable), ADV (address valid, used on some + NOR flash memories), WE (write enable). This on top of 6 different chip selects + (CS0 thru CS5) so that in theory 6 different devices can be connected. + + Apparently this bus is clocked at 64MHz. It has dedicated pins on the package + and the bus can only come out on these pins, however if some of the pins are + unused they can be left unconnected or remuxed to be used as GPIO or in some + cases other orthogonal functions as well. + + Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me. + + The chip selects have the following memory range assignments. This region of + memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big. + + Chip Select Physical address base + CS0 GPIO134 0x1a800000-0x1b000000 (8MB) + CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB) + CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB) + CS3 GPIO133 0x1d000000-0x25000000 (128 MB) + CS4 GPIO132 0x1c800000-0x1d000000 (8MB) + CS5 GPIO131 0x1c000000-0x1c800000 (8MB) + + The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A, + August 6, 2012 contains some incomplete documentation of the EBI2. + + FIXME: the manual mentions "write precharge cycles" and "precharge cycles". + We have not been able to figure out which bit fields these correspond to + in the hardware, or what valid values exist. The current hypothesis is that + this is something just used on the FAST chip selects and that the SLOW + chip selects are understood fully. There is also a "byte device enable" + flag somewhere for 8bit memories. + + FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit + unclear what this means, if they are mutually exclusive or can be used + together, or if some chip selects are hardwired to be FAST and others are SLOW + by design. + + The XMEM registers are totally undocumented but could be partially decoded + because the Cypress AN49576 Antioch Westbridge apparently has suspiciously + similar register layout, see: http://www.cypress.com/file/105771/download + +maintainers: + - Bjorn Andersson + +properties: + compatible: + enum: + - qcom,apq8060-ebi2 + - qcom,msm8660-ebi2 + + reg: + items: + - description: EBI2 config region + - description: XMEM config region + + reg-names: + items: + - const: ebi2 + - const: xmem + + ranges: true + + clocks: + items: + - description: EBI_2X clock + - description: EBI clock + + clock-names: + items: + - const: ebi2x + - const: ebi2 + + '#address-cells': + const: 2 + + '#size-cells': + const: 1 + +required: + - compatible + - reg + - reg-names + - ranges + - clocks + - clock-names + - '#address-cells' + - '#size-cells' + +patternProperties: + "^.*@[0-5],[0-9a-f]+$": + type: object + $ref: mc-peripheral-props.yaml# + additionalProperties: true + +additionalProperties: false + +examples: + - | + #include + #include + #include + + external-bus@1a100000 { + compatible = "qcom,msm8660-ebi2"; + reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; + reg-names = "ebi2", "xmem"; + ranges = <0 0x0 0x1a800000 0x00800000>, + <1 0x0 0x1b000000 0x00800000>, + <2 0x0 0x1b800000 0x00800000>, + <3 0x0 0x1d000000 0x08000000>, + <4 0x0 0x1c800000 0x00800000>, + <5 0x0 0x1c000000 0x00800000>; + + clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; + clock-names = "ebi2x", "ebi2"; + + #address-cells = <2>; + #size-cells = <1>; + + ethernet@2,0 { + compatible = "smsc,lan9221", "smsc,lan9115"; + reg = <2 0x0 0x100>; + + interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>, + <&tlmm 29 IRQ_TYPE_EDGE_RISING>; + reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>; + + phy-mode = "mii"; + reg-io-width = <2>; + smsc,force-external-phy; + smsc,irq-push-pull; + + /* SLOW chipselect config */ + qcom,xmem-recovery-cycles = <0>; + qcom,xmem-write-hold-cycles = <3>; + qcom,xmem-write-delta-cycles = <31>; + qcom,xmem-read-delta-cycles = <28>; + qcom,xmem-write-wait-cycles = <9>; + qcom,xmem-read-wait-cycles = <9>; + }; + }; diff --git a/Bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml b/Bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml new file mode 100644 index 00000000000..c474f90846e --- /dev/null +++ b/Bindings/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/samsung,exynos4210-srom-peripheral-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Peripheral Properties for Samsung Exynos SoC SROM Controller + +maintainers: + - Krzysztof Kozlowski + +properties: + samsung,srom-page-mode: + description: + If page mode is set, 4 data page mode will be configured, + else normal (1 data) page mode will be set. + type: boolean + + samsung,srom-timing: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 6 + maxItems: 6 + description: | + Array of 6 integers, specifying bank timings in the following order: + Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs. + Each value is specified in cycles and has the following meaning + and valid range: + Tacp: Page mode access cycle at Page mode (0 - 15) + Tcah: Address holding time after CSn (0 - 15) + Tcoh: Chip selection hold on OEn (0 - 15) + Tacc: Access cycle (0 - 31, the actual time is N + 1) + Tcos: Chip selection set-up before OEn (0 - 15) + Tacs: Address set-up before CSn (0 - 15) + +additionalProperties: true diff --git a/Bindings/mfd/aspeed-lpc.yaml b/Bindings/mfd/aspeed-lpc.yaml index 5dfe77aca16..d88854e60b7 100644 --- a/Bindings/mfd/aspeed-lpc.yaml +++ b/Bindings/mfd/aspeed-lpc.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# # Copyright (c) 2021 Aspeed Tehchnology Inc. +# # Copyright (c) 2021 Aspeed Technology Inc. %YAML 1.2 --- $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml# diff --git a/Bindings/mfd/atmel,sama5d2-flexcom.yaml b/Bindings/mfd/atmel,sama5d2-flexcom.yaml index 0dc6a40b63f..c7d6cf96796 100644 --- a/Bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -19,12 +19,11 @@ properties: oneOf: - const: atmel,sama5d2-flexcom - items: - - const: microchip,sam9x7-flexcom + - enum: + - microchip,sam9x7-flexcom + - microchip,sama7d65-flexcom + - microchip,sama7g5-flexcom - const: atmel,sama5d2-flexcom - - items: - - const: microchip,sama7g5-flexcom - - const: atmel,sama5d2-flexcom - reg: maxItems: 1 diff --git a/Bindings/mfd/fsl,mcu-mpc8349emitx.yaml b/Bindings/mfd/fsl,mcu-mpc8349emitx.yaml new file mode 100644 index 00000000000..8beb2ed9edb --- /dev/null +++ b/Bindings/mfd/fsl,mcu-mpc8349emitx.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/fsl,mcu-mpc8349emitx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MPC8349E-mITX-compatible Power Management Micro Controller Unit (MCU) + +maintainers: + - J. Neuschäfer + +properties: + compatible: + oneOf: + - items: + - enum: + - fsl,mc9s08qg8-mpc8315erdb + - fsl,mc9s08qg8-mpc8349emitx + - fsl,mc9s08qg8-mpc8377erdb + - fsl,mc9s08qg8-mpc8378erdb + - fsl,mc9s08qg8-mpc8379erdb + - const: fsl,mcu-mpc8349emitx + + reg: + maxItems: 1 + + "#gpio-cells": + const: 2 + + gpio-controller: true + +required: + - compatible + - reg + - "#gpio-cells" + - gpio-controller + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + mcu@a { + #gpio-cells = <2>; + compatible = "fsl,mc9s08qg8-mpc8349emitx", + "fsl,mcu-mpc8349emitx"; + reg = <0x0a>; + gpio-controller; + }; + }; diff --git a/Bindings/mfd/maxim,max77705.yaml b/Bindings/mfd/maxim,max77705.yaml new file mode 100644 index 00000000000..0ec89f0adc6 --- /dev/null +++ b/Bindings/mfd/maxim,max77705.yaml @@ -0,0 +1,158 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/maxim,max77705.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX77705 Companion Power Management and USB Type-C interface + +maintainers: + - Dzmitry Sankouski + +description: | + This is a part of device tree bindings for Maxim MAX77705. + + Maxim MAX77705 is a Companion Power Management and Type-C + interface IC which includes charger, fuelgauge, LED, haptic motor driver and + Type-C management. + +properties: + compatible: + const: maxim,max77705 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + haptic: + type: object + additionalProperties: false + + properties: + compatible: + const: maxim,max77705-haptic + + haptic-supply: true + + pwms: + maxItems: 1 + + required: + - compatible + - haptic-supply + - pwms + + leds: + type: object + additionalProperties: false + description: + Up to 4 LED channels supported. + + properties: + compatible: + const: maxim,max77705-rgb + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + multi-led: + type: object + $ref: /schemas/leds/leds-class-multicolor.yaml# + unevaluatedProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^led@[0-3]$": + type: object + $ref: /schemas/leds/common.yaml# + unevaluatedProperties: false + + properties: + reg: + maxItems: 1 + + required: + - reg + + patternProperties: + "^led@[0-3]$": + type: object + $ref: /schemas/leds/common.yaml# + unevaluatedProperties: false + + properties: + reg: + maxItems: 1 + + required: + - reg + + required: + - compatible + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@66 { + compatible = "maxim,max77705"; + reg = <0x66>; + interrupt-parent = <&pm8998_gpios>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&chg_int_default>; + pinctrl-names = "default"; + + leds { + compatible = "maxim,max77705-rgb"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + }; + + led@2 { + reg = <2>; + color = ; + }; + + led@3 { + reg = <3>; + color = ; + }; + }; + }; + + haptic { + compatible = "maxim,max77705-haptic"; + haptic-supply = <&vib_regulator>; + pwms = <&vib_pwm 0 50000>; + }; + }; + }; diff --git a/Bindings/mfd/motorola-cpcap.txt b/Bindings/mfd/motorola-cpcap.txt index 190230216de..f00827c9b67 100644 --- a/Bindings/mfd/motorola-cpcap.txt +++ b/Bindings/mfd/motorola-cpcap.txt @@ -31,6 +31,10 @@ node must be named "audio-codec". Required properties for the audio-codec subnode: - #sound-dai-cells = <1>; +- interrupts : should contain jack detection interrupts, with headset + detect interrupt matching "hs" and microphone bias 2 + detect interrupt matching "mb2" in interrupt-names. +- interrupt-names : Contains "hs", "mb2" The audio-codec provides two DAIs. The first one is connected to the Stereo HiFi DAC and the second one is connected to the Voice DAC. @@ -52,6 +56,8 @@ Example: audio-codec { #sound-dai-cells = <1>; + interrupts-extended = <&cpcap 9 0>, <&cpcap 10 0>; + interrupt-names = "hs", "mb2"; /* HiFi */ port@0 { diff --git a/Bindings/mfd/qcom,tcsr.yaml b/Bindings/mfd/qcom,tcsr.yaml index a503b67f2db..7e7225aadae 100644 --- a/Bindings/mfd/qcom,tcsr.yaml +++ b/Bindings/mfd/qcom,tcsr.yaml @@ -52,6 +52,7 @@ properties: - qcom,tcsr-msm8660 - qcom,tcsr-msm8916 - qcom,tcsr-msm8917 + - qcom,tcsr-msm8937 - qcom,tcsr-msm8953 - qcom,tcsr-msm8960 - qcom,tcsr-msm8974 diff --git a/Bindings/mfd/realtek,rtl9301-switch.yaml b/Bindings/mfd/realtek,rtl9301-switch.yaml deleted file mode 100644 index f053303ab1e..00000000000 --- a/Bindings/mfd/realtek,rtl9301-switch.yaml +++ /dev/null @@ -1,114 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/mfd/realtek,rtl9301-switch.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Realtek Switch with Internal CPU - -maintainers: - - Chris Packham - -description: - The RTL9300 is a series of is an Ethernet switches with an integrated CPU. A - number of different peripherals are accessed through a common register block, - represented here as a syscon node. - -properties: - compatible: - items: - - enum: - - realtek,rtl9301-switch - - realtek,rtl9302b-switch - - realtek,rtl9302c-switch - - realtek,rtl9303-switch - - const: syscon - - const: simple-mfd - - reg: - maxItems: 1 - - '#address-cells': - const: 1 - - '#size-cells': - const: 1 - -patternProperties: - 'reboot@[0-9a-f]+$': - $ref: /schemas/power/reset/syscon-reboot.yaml# - - 'i2c@[0-9a-f]+$': - $ref: /schemas/i2c/realtek,rtl9301-i2c.yaml# - -required: - - compatible - - reg - -additionalProperties: false - -examples: - - | - ethernet-switch@1b000000 { - compatible = "realtek,rtl9301-switch", "syscon", "simple-mfd"; - reg = <0x1b000000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - - reboot@c { - compatible = "syscon-reboot"; - reg = <0x0c 0x4>; - value = <0x01>; - }; - - i2c@36c { - compatible = "realtek,rtl9301-i2c"; - reg = <0x36c 0x14>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - gpio@20 { - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; - }; - - i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - gpio@20 { - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; - }; - }; - - i2c@388 { - compatible = "realtek,rtl9301-i2c"; - reg = <0x388 0x14>; - #address-cells = <1>; - #size-cells = <0>; - - i2c@7 { - reg = <7>; - #address-cells = <1>; - #size-cells = <0>; - gpio@20 { - compatible = "nxp,pca9555"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x20>; - }; - }; - }; - }; - diff --git a/Bindings/mfd/samsung,s2mps11.yaml b/Bindings/mfd/samsung,s2mps11.yaml index a4be642de33..ac5d0c14979 100644 --- a/Bindings/mfd/samsung,s2mps11.yaml +++ b/Bindings/mfd/samsung,s2mps11.yaml @@ -25,6 +25,7 @@ properties: - samsung,s2mps14-pmic - samsung,s2mps15-pmic - samsung,s2mpu02-pmic + - samsung,s2mpu05-pmic clocks: $ref: /schemas/clock/samsung,s2mps11.yaml @@ -125,6 +126,18 @@ allOf: samsung,s2mps11-acokb-ground: false samsung,s2mps11-wrstbi-ground: false + - if: + properties: + compatible: + contains: + const: samsung,s2mpu05-pmic + then: + properties: + regulators: + $ref: /schemas/regulator/samsung,s2mpu05.yaml + samsung,s2mps11-acokb-ground: false + samsung,s2mps11-wrstbi-ground: false + examples: - | #include diff --git a/Bindings/mfd/st,stm32-timers.yaml b/Bindings/mfd/st,stm32-timers.yaml index b0e438ff495..66aa1550a4e 100644 --- a/Bindings/mfd/st,stm32-timers.yaml +++ b/Bindings/mfd/st,stm32-timers.yaml @@ -21,7 +21,9 @@ maintainers: properties: compatible: - const: st,stm32-timers + enum: + - st,stm32-timers + - st,stm32mp25-timers reg: maxItems: 1 @@ -36,6 +38,9 @@ properties: resets: maxItems: 1 + power-domains: + maxItems: 1 + dmas: minItems: 1 maxItems: 7 @@ -77,7 +82,9 @@ properties: properties: compatible: - const: st,stm32-pwm + enum: + - st,stm32-pwm + - st,stm32mp25-pwm "#pwm-cells": const: 3 @@ -113,7 +120,9 @@ properties: properties: compatible: - const: st,stm32-timer-counter + enum: + - st,stm32-timer-counter + - st,stm32mp25-timer-counter required: - compatible @@ -128,12 +137,13 @@ patternProperties: enum: - st,stm32-timer-trigger - st,stm32h7-timer-trigger + - st,stm32mp25-timer-trigger reg: description: Identify trigger hardware block. items: minimum: 0 - maximum: 16 + maximum: 19 required: - compatible diff --git a/Bindings/mfd/syscon.yaml b/Bindings/mfd/syscon.yaml index 4d67ff26d44..c6bbb19c3e3 100644 --- a/Bindings/mfd/syscon.yaml +++ b/Bindings/mfd/syscon.yaml @@ -27,6 +27,7 @@ select: compatible: contains: enum: + - airoha,en7581-pbus-csr - al,alpine-sysfabric-service - allwinner,sun8i-a83t-system-controller - allwinner,sun8i-h3-system-controller @@ -90,6 +91,8 @@ select: - microchip,lan966x-cpu-syscon - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr + - microchip,sama7d65-ddr3phy + - microchip,sama7d65-sfrbu - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon - mstar,msc313-pmsleep @@ -103,6 +106,7 @@ select: - rockchip,rk3288-qos - rockchip,rk3368-qos - rockchip,rk3399-qos + - rockchip,rk3528-qos - rockchip,rk3562-qos - rockchip,rk3568-qos - rockchip,rk3576-qos @@ -126,6 +130,7 @@ properties: compatible: items: - enum: + - airoha,en7581-pbus-csr - al,alpine-sysfabric-service - allwinner,sun8i-a83t-system-controller - allwinner,sun8i-h3-system-controller @@ -189,6 +194,8 @@ properties: - microchip,lan966x-cpu-syscon - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr + - microchip,sama7d65-ddr3phy + - microchip,sama7d65-sfrbu - microchip,sama7g5-ddr3phy - mscc,ocelot-cpu-syscon - mstar,msc313-pmsleep @@ -202,6 +209,7 @@ properties: - rockchip,rk3288-qos - rockchip,rk3368-qos - rockchip,rk3399-qos + - rockchip,rk3528-qos - rockchip,rk3562-qos - rockchip,rk3568-qos - rockchip,rk3576-qos diff --git a/Bindings/mips/mti,mips-cm.yaml b/Bindings/mips/mti,mips-cm.yaml new file mode 100644 index 00000000000..d129d638284 --- /dev/null +++ b/Bindings/mips/mti,mips-cm.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/mti,mips-cm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Coherence Manager + +description: + The Coherence Manager (CM) is responsible for establishing the + global ordering of requests from all elements of the system and + sending the correct data back to the requester. It supports Cache + to Cache transfers. + https://training.mips.com/cps_mips/PDF/CPS_Introduction.pdf + https://training.mips.com/cps_mips/PDF/Coherency_Manager.pdf + +maintainers: + - Jiaxun Yang + +properties: + compatible: + oneOf: + - const: mti,mips-cm + - const: mobileye,eyeq6-cm + description: + On EyeQ6 the HCI (Hardware Cache Initialization) information for + the L2 cache in multi-cluster configuration is broken. + + reg: + description: + Base address and size of the Global Configuration Registers + referred to as CMGCR.They are the system programmer's interface + to the Coherency Manager. Their location in the memory map is + determined at core build time. In a functional system, the base + address is provided by the Coprocessor 0, but some + System-on-Chip (SoC) designs may not provide an accurate address + that needs to be described statically. + + maxItems: 1 + +required: + - compatible + +additionalProperties: false + +examples: + - | + coherency-manager@1fbf8000 { + compatible = "mti,mips-cm"; + reg = <0x1bde8000 0x8000>; + }; + + - | + coherency-manager { + compatible = "mobileye,eyeq6-cm"; + }; +... diff --git a/Bindings/misc/atmel-ssc.txt b/Bindings/misc/atmel-ssc.txt deleted file mode 100644 index f9fb412642f..00000000000 --- a/Bindings/misc/atmel-ssc.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Atmel SSC driver. - -Required properties: -- compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc" - - atmel,at91rm9200-ssc: support pdc transfer - - atmel,at91sam9g45-ssc: support dma transfer -- reg: Should contain SSC registers location and length -- interrupts: Should contain SSC interrupt -- clock-names: tuple listing input clock names. - Required elements: "pclk" -- clocks: phandles to input clocks. - - -Required properties for devices compatible with "atmel,at91sam9g45-ssc": -- dmas: DMA specifier, consisting of a phandle to DMA controller node, - the memory interface and SSC DMA channel ID (for tx and rx). - See Documentation/devicetree/bindings/dma/atmel-dma.txt for details. -- dma-names: Must be "tx", "rx". - -Optional properties: - - atmel,clk-from-rk-pin: bool property. - - When SSC works in slave mode, according to the hardware design, the - clock can get from TK pin, and also can get from RK pin. So, add - this parameter to choose where the clock from. - - By default the clock is from TK pin, if the clock from RK pin, this - property is needed. - - #sound-dai-cells: Should contain <0>. - - This property makes the SSC into an automatically registered DAI. - -Examples: -- PDC transfer: -ssc0: ssc@fffbc000 { - compatible = "atmel,at91rm9200-ssc"; - reg = <0xfffbc000 0x4000>; - interrupts = <14 4 5>; - clocks = <&ssc0_clk>; - clock-names = "pclk"; -}; - -- DMA transfer: -ssc0: ssc@f0010000 { - compatible = "atmel,at91sam9g45-ssc"; - reg = <0xf0010000 0x4000>; - interrupts = <28 4 5>; - dmas = <&dma0 1 13>, - <&dma0 1 14>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; -}; diff --git a/Bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Bindings/mmc/allwinner,sun4i-a10-mmc.yaml index 0ccd632d562..9f3b1edacaa 100644 --- a/Bindings/mmc/allwinner,sun4i-a10-mmc.yaml +++ b/Bindings/mmc/allwinner,sun4i-a10-mmc.yaml @@ -30,38 +30,34 @@ properties: - const: allwinner,sun50i-a100-emmc - const: allwinner,sun50i-a100-mmc - items: - - const: allwinner,sun8i-a83t-mmc + - enum: + - allwinner,sun8i-a83t-mmc + - allwinner,suniv-f1c100s-mmc - const: allwinner,sun7i-a20-mmc - items: - - const: allwinner,sun8i-r40-emmc + - enum: + - allwinner,sun8i-r40-emmc + - allwinner,sun50i-h5-emmc + - allwinner,sun50i-h6-emmc - const: allwinner,sun50i-a64-emmc - items: - - const: allwinner,sun8i-r40-mmc + - enum: + - allwinner,sun8i-r40-mmc + - allwinner,sun50i-h5-mmc + - allwinner,sun50i-h6-mmc - const: allwinner,sun50i-a64-mmc - items: - - const: allwinner,sun50i-h5-emmc - - const: allwinner,sun50i-a64-emmc - - items: - - const: allwinner,sun50i-h5-mmc - - const: allwinner,sun50i-a64-mmc - - items: - - const: allwinner,sun50i-h6-emmc - - const: allwinner,sun50i-a64-emmc - - items: - - const: allwinner,sun50i-h6-mmc - - const: allwinner,sun50i-a64-mmc - - items: - - const: allwinner,sun20i-d1-emmc - - const: allwinner,sun50i-a100-emmc - - items: - - const: allwinner,sun50i-h616-emmc + - enum: + - allwinner,sun20i-d1-emmc + - allwinner,sun50i-h616-emmc + - allwinner,sun55i-a523-emmc - const: allwinner,sun50i-a100-emmc - items: - const: allwinner,sun50i-h616-mmc - const: allwinner,sun50i-a100-mmc - items: - - const: allwinner,suniv-f1c100s-mmc - - const: allwinner,sun7i-a20-mmc + - const: allwinner,sun55i-a523-mmc + - const: allwinner,sun20i-d1-mmc reg: maxItems: 1 diff --git a/Bindings/mmc/amlogic,meson-mx-sdio.yaml b/Bindings/mmc/amlogic,meson-mx-sdio.yaml index 022682a977c..0d4d9ca6a8d 100644 --- a/Bindings/mmc/amlogic,meson-mx-sdio.yaml +++ b/Bindings/mmc/amlogic,meson-mx-sdio.yaml @@ -60,6 +60,9 @@ patternProperties: bus-width: enum: [1, 4] + required: + - compatible + unevaluatedProperties: false required: diff --git a/Bindings/mmc/atmel,hsmci.yaml b/Bindings/mmc/atmel,hsmci.yaml new file mode 100644 index 00000000000..151b414b9d2 --- /dev/null +++ b/Bindings/mmc/atmel,hsmci.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/atmel,hsmci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel High-Speed MultiMedia Card Interface (HSMCI) + +description: + The Atmel HSMCI controller provides an interface for MMC, SD, and SDIO memory + cards. + +maintainers: + - Nicolas Ferre + - Aubin Constans + +allOf: + - $ref: mmc-controller.yaml + +properties: + compatible: + const: atmel,hsmci + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + dmas: + maxItems: 1 + + dma-names: + const: rxtx + + clocks: + maxItems: 1 + + clock-names: + const: mci_clk + + "#address-cells": + const: 1 + description: Used for slot IDs. + + "#size-cells": + const: 0 + +patternProperties: + "slot@[0-2]$": + $ref: mmc-slot.yaml + description: A slot node representing an MMC, SD, or SDIO slot. + + properties: + reg: + enum: [0, 1] + + required: + - reg + - bus-width + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#address-cells" + - "#size-cells" + +anyOf: + - required: + - slot@0 + - required: + - slot@1 + +unevaluatedProperties: false + +examples: + - | + #include + #include + mmc@f0008000 { + compatible = "atmel,hsmci"; + reg = <0xf0008000 0x600>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + #address-cells = <1>; + #size-cells = <0>; + + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioD 15 0>; + cd-inverted; + }; + + slot@1 { + reg = <1>; + bus-width = <4>; + }; + }; +... diff --git a/Bindings/mmc/atmel-hsmci.txt b/Bindings/mmc/atmel-hsmci.txt deleted file mode 100644 index 07ad02075a9..00000000000 --- a/Bindings/mmc/atmel-hsmci.txt +++ /dev/null @@ -1,73 +0,0 @@ -* Atmel High Speed MultiMedia Card Interface - -This controller on atmel products provides an interface for MMC, SD and SDIO -types of memory cards. - -This file documents differences between the core properties described -by mmc.txt and the properties used by the atmel-mci driver. - -1) MCI node - -Required properties: -- compatible: should be "atmel,hsmci" -- #address-cells: should be one. The cell is the slot id. -- #size-cells: should be zero. -- at least one slot node -- clock-names: tuple listing input clock names. - Required elements: "mci_clk" -- clocks: phandles to input clocks. - -The node contains child nodes for each slot that the platform uses - -Example MCI node: - -mmc0: mmc@f0008000 { - compatible = "atmel,hsmci"; - reg = <0xf0008000 0x600>; - interrupts = <12 4>; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "mci_clk"; - clocks = <&mci0_clk>; - - [ child node definitions...] -}; - -2) slot nodes - -Required properties: -- reg: should contain the slot id. -- bus-width: number of data lines connected to the controller - -Optional properties: -- cd-gpios: specify GPIOs for card detection -- cd-inverted: invert the value of external card detect gpio line -- wp-gpios: specify GPIOs for write protection - -Example slot node: - -slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 15 0> - cd-inverted; -}; - -Example full MCI node: -mmc0: mmc@f0008000 { - compatible = "atmel,hsmci"; - reg = <0xf0008000 0x600>; - interrupts = <12 4>; - #address-cells = <1>; - #size-cells = <0>; - slot@0 { - reg = <0>; - bus-width = <4>; - cd-gpios = <&pioD 15 0> - cd-inverted; - }; - slot@1 { - reg = <1>; - bus-width = <4>; - }; -}; diff --git a/Bindings/mmc/fsl-imx-esdhc.yaml b/Bindings/mmc/fsl-imx-esdhc.yaml index b9b99957052..b98a84f9327 100644 --- a/Bindings/mmc/fsl-imx-esdhc.yaml +++ b/Bindings/mmc/fsl-imx-esdhc.yaml @@ -57,6 +57,7 @@ properties: - fsl,imx8mp-usdhc - fsl,imx8ulp-usdhc - fsl,imx93-usdhc + - fsl,imx94-usdhc - fsl,imx95-usdhc - const: fsl,imx8mm-usdhc - items: diff --git a/Bindings/mmc/mmc-controller.yaml b/Bindings/mmc/mmc-controller.yaml index 9d7a1298c45..26e4f0f8dc1 100644 --- a/Bindings/mmc/mmc-controller.yaml +++ b/Bindings/mmc/mmc-controller.yaml @@ -24,7 +24,7 @@ properties: $nodename: pattern: "^mmc(@.*)?$" -unevaluatedProperties: true +additionalProperties: true examples: - | diff --git a/Bindings/mmc/mmc-slot.yaml b/Bindings/mmc/mmc-slot.yaml index 1f066782806..ca3d0114bfc 100644 --- a/Bindings/mmc/mmc-slot.yaml +++ b/Bindings/mmc/mmc-slot.yaml @@ -29,7 +29,6 @@ properties: maxItems: 1 required: - - compatible - reg unevaluatedProperties: false diff --git a/Bindings/mmc/renesas,sdhi.yaml b/Bindings/mmc/renesas,sdhi.yaml index af378b9ff3f..773baa6c265 100644 --- a/Bindings/mmc/renesas,sdhi.yaml +++ b/Bindings/mmc/renesas,sdhi.yaml @@ -68,6 +68,9 @@ properties: - renesas,sdhi-r9a08g045 # RZ/G3S - renesas,sdhi-r9a09g011 # RZ/V2M - const: renesas,rzg2l-sdhi + - items: + - const: renesas,sdhi-r9a09g047 # RZ/G3E + - const: renesas,sdhi-r9a09g057 # RZ/V2H(P) reg: maxItems: 1 @@ -211,6 +214,19 @@ allOf: sectioned off to be run by a separate second clock source to allow the main core clock to be turned off to save power. + - if: + properties: + compatible: + contains: + const: renesas,sdhi-r9a09g057 + then: + properties: + vqmmc-regulator: + type: object + description: VQMMC SD regulator + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + required: - compatible - reg diff --git a/Bindings/mmc/rockchip-dw-mshc.yaml b/Bindings/mmc/rockchip-dw-mshc.yaml index 06df1269f24..bf273115235 100644 --- a/Bindings/mmc/rockchip-dw-mshc.yaml +++ b/Bindings/mmc/rockchip-dw-mshc.yaml @@ -38,6 +38,8 @@ properties: - rockchip,rk3328-dw-mshc - rockchip,rk3368-dw-mshc - rockchip,rk3399-dw-mshc + - rockchip,rk3528-dw-mshc + - rockchip,rk3562-dw-mshc - rockchip,rk3568-dw-mshc - rockchip,rk3588-dw-mshc - rockchip,rv1108-dw-mshc diff --git a/Bindings/mmc/samsung,exynos-dw-mshc.yaml b/Bindings/mmc/samsung,exynos-dw-mshc.yaml index ef2d1d7c92f..e8bd49d4679 100644 --- a/Bindings/mmc/samsung,exynos-dw-mshc.yaml +++ b/Bindings/mmc/samsung,exynos-dw-mshc.yaml @@ -24,6 +24,8 @@ properties: - samsung,exynos5420-dw-mshc-smu - samsung,exynos7-dw-mshc - samsung,exynos7-dw-mshc-smu + - samsung,exynos7870-dw-mshc + - samsung,exynos7870-dw-mshc-smu - items: - enum: - samsung,exynos5433-dw-mshc-smu diff --git a/Bindings/mmc/snps,dwcmshc-sdhci.yaml b/Bindings/mmc/snps,dwcmshc-sdhci.yaml index c3d5e0230af..e6e604072d3 100644 --- a/Bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -14,7 +14,10 @@ properties: compatible: oneOf: - items: - - const: rockchip,rk3576-dwcmshc + - enum: + - rockchip,rk3528-dwcmshc + - rockchip,rk3562-dwcmshc + - rockchip,rk3576-dwcmshc - const: rockchip,rk3588-dwcmshc - enum: - rockchip,rk3568-dwcmshc diff --git a/Bindings/mtd/arasan,nand-controller.yaml b/Bindings/mtd/arasan,nand-controller.yaml index 15b63bbb82a..b90d3b48c2f 100644 --- a/Bindings/mtd/arasan,nand-controller.yaml +++ b/Bindings/mtd/arasan,nand-controller.yaml @@ -42,7 +42,7 @@ required: - clock-names - interrupts -unevaluatedProperties: true +unevaluatedProperties: false examples: - | diff --git a/Bindings/mtd/atmel,dataflash.yaml b/Bindings/mtd/atmel,dataflash.yaml new file mode 100644 index 00000000000..8c72fa346e3 --- /dev/null +++ b/Bindings/mtd/atmel,dataflash.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/atmel,dataflash.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel DataFlash + +maintainers: + - Nayab Sayed + +description: + The Atmel DataFlash is a low pin-count serial interface sequential access + Flash memory, compatible with SPI standard. The device tree may optionally + contain sub-nodes describing partitions of the address space. + +properties: + compatible: + oneOf: + - items: + - enum: + - atmel,at45db321d + - atmel,at45db041e + - atmel,at45db642d + - atmel,at45db021d + - const: atmel,at45 + - const: atmel,dataflash + - items: + - const: atmel,at45 + - const: atmel,dataflash + + reg: + maxItems: 1 + +required: + - compatible + - reg + +allOf: + - $ref: mtd.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + flash@1 { + compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; + reg = <1>; + }; + }; diff --git a/Bindings/mtd/atmel-dataflash.txt b/Bindings/mtd/atmel-dataflash.txt deleted file mode 100644 index 1889a4db5b7..00000000000 --- a/Bindings/mtd/atmel-dataflash.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Atmel Data Flash - -Required properties: -- compatible : "atmel,", "atmel,", "atmel,dataflash". - -The device tree may optionally contain sub-nodes describing partitions of the -address space. See partition.txt for more detail. - -Example: - -flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <25000000>; - reg = <1>; -}; diff --git a/Bindings/mtd/gpmi-nand.yaml b/Bindings/mtd/gpmi-nand.yaml index f9eb1868ca1..0badb2e978c 100644 --- a/Bindings/mtd/gpmi-nand.yaml +++ b/Bindings/mtd/gpmi-nand.yaml @@ -29,7 +29,14 @@ properties: - enum: - fsl,imx8mm-gpmi-nand - fsl,imx8mn-gpmi-nand + - fsl,imx8mp-gpmi-nand + - fsl,imx8mq-gpmi-nand - const: fsl,imx7d-gpmi-nand + - items: + - enum: + - fsl,imx8dxl-gpmi-nand + - fsl,imx8qm-gpmi-nand + - const: fsl,imx8qxp-gpmi-nand reg: items: diff --git a/Bindings/mtd/mtd-physmap.yaml b/Bindings/mtd/mtd-physmap.yaml index 18f6733408b..1b375dee83b 100644 --- a/Bindings/mtd/mtd-physmap.yaml +++ b/Bindings/mtd/mtd-physmap.yaml @@ -122,6 +122,8 @@ properties: '#size-cells': const: 1 + ranges: true + big-endian: true little-endian: true @@ -143,8 +145,7 @@ then: required: - syscon -# FIXME: A parent bus may define timing properties -additionalProperties: true +unevaluatedProperties: false examples: - | diff --git a/Bindings/mtd/mxc-nand.yaml b/Bindings/mtd/mxc-nand.yaml index cf4198e43d7..bd8f7b68395 100644 --- a/Bindings/mtd/mxc-nand.yaml +++ b/Bindings/mtd/mxc-nand.yaml @@ -14,8 +14,12 @@ allOf: properties: compatible: - const: fsl,imx27-nand - + oneOf: + - const: fsl,imx27-nand + - items: + - enum: + - fsl,imx31-nand + - const: fsl,imx27-nand reg: maxItems: 1 diff --git a/Bindings/net/airoha,en7581-eth.yaml b/Bindings/net/airoha,en7581-eth.yaml index c578637c582..0fdd1126541 100644 --- a/Bindings/net/airoha,en7581-eth.yaml +++ b/Bindings/net/airoha,en7581-eth.yaml @@ -63,6 +63,14 @@ properties: "#size-cells": const: 0 + airoha,npu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the node used to configure the NPU module. + The Airoha Network Processor Unit (NPU) provides a configuration + interface to implement hardware flow offloading programming Packet + Processor Engine (PPE) flow table. + patternProperties: "^ethernet@[1-4]$": type: object @@ -132,6 +140,8 @@ examples: , ; + airoha,npu = <&npu>; + #address-cells = <1>; #size-cells = <0>; diff --git a/Bindings/net/airoha,en7581-npu.yaml b/Bindings/net/airoha,en7581-npu.yaml new file mode 100644 index 00000000000..76dd97c3fb4 --- /dev/null +++ b/Bindings/net/airoha,en7581-npu.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/airoha,en7581-npu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha Network Processor Unit for EN7581 SoC + +maintainers: + - Lorenzo Bianconi + +description: + The Airoha Network Processor Unit (NPU) provides a configuration interface + to implement wired and wireless hardware flow offloading programming Packet + Processor Engine (PPE) flow table. + +properties: + compatible: + enum: + - airoha,en7581-npu + + reg: + maxItems: 1 + + interrupts: + items: + - description: mbox host irq line + - description: watchdog0 irq line + - description: watchdog1 irq line + - description: watchdog2 irq line + - description: watchdog3 irq line + - description: watchdog4 irq line + - description: watchdog5 irq line + - description: watchdog6 irq line + - description: watchdog7 irq line + - description: wlan irq line0 + - description: wlan irq line1 + - description: wlan irq line2 + - description: wlan irq line3 + - description: wlan irq line4 + - description: wlan irq line5 + + memory-region: + maxItems: 1 + description: + Memory used to store NPU firmware binary. + +required: + - compatible + - reg + - interrupts + - memory-region + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + npu@1e900000 { + compatible = "airoha,en7581-npu"; + reg = <0 0x1e900000 0 0x313000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + memory-region = <&npu_binary>; + }; + }; diff --git a/Bindings/net/amlogic,meson-dwmac.yaml b/Bindings/net/amlogic,meson-dwmac.yaml index 798a4c19f18..0cd78d71768 100644 --- a/Bindings/net/amlogic,meson-dwmac.yaml +++ b/Bindings/net/amlogic,meson-dwmac.yaml @@ -152,6 +152,12 @@ properties: The second range is is for the Amlogic specific configuration (for example the PRG_ETHERNET register range on Meson8b and newer) + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + required: - compatible - reg diff --git a/Bindings/net/bluetooth/nxp,88w8987-bt.yaml b/Bindings/net/bluetooth/nxp,88w8987-bt.yaml index 0a2d7baf5db..d02e9dd847e 100644 --- a/Bindings/net/bluetooth/nxp,88w8987-bt.yaml +++ b/Bindings/net/bluetooth/nxp,88w8987-bt.yaml @@ -17,6 +17,9 @@ description: maintainers: - Neeraj Sanjay Kale +allOf: + - $ref: bluetooth-controller.yaml# + properties: compatible: enum: @@ -40,10 +43,20 @@ properties: Host-To-Chip power save mechanism is driven by this GPIO connected to BT_WAKE_IN pin of the NXP chipset. + nxp,wakein-pin: + $ref: /schemas/types.yaml#/definitions/uint8 + description: + The GPIO number of the NXP chipset used for BT_WAKE_IN. + + nxp,wakeout-pin: + $ref: /schemas/types.yaml#/definitions/uint8 + description: + The GPIO number of the NXP chipset used for BT_WAKE_OUT. + required: - compatible -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -54,5 +67,8 @@ examples: fw-init-baudrate = <3000000>; firmware-name = "uartuart8987_bt_v0.bin"; device-wakeup-gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; + nxp,wakein-pin = /bits/ 8 <18>; + nxp,wakeout-pin = /bits/ 8 <19>; + local-bd-address = [66 55 44 33 22 11]; }; }; diff --git a/Bindings/net/bluetooth/qualcomm-bluetooth.yaml b/Bindings/net/bluetooth/qualcomm-bluetooth.yaml index a72152f7e29..6353a336f38 100644 --- a/Bindings/net/bluetooth/qualcomm-bluetooth.yaml +++ b/Bindings/net/bluetooth/qualcomm-bluetooth.yaml @@ -19,6 +19,7 @@ properties: - qcom,qca2066-bt - qcom,qca6174-bt - qcom,qca9377-bt + - qcom,wcn3950-bt - qcom,wcn3988-bt - qcom,wcn3990-bt - qcom,wcn3991-bt @@ -138,6 +139,7 @@ allOf: compatible: contains: enum: + - qcom,wcn3950-bt - qcom,wcn3988-bt - qcom,wcn3990-bt - qcom,wcn3991-bt diff --git a/Bindings/net/can/fsl,flexcan.yaml b/Bindings/net/can/fsl,flexcan.yaml index 97dd1a7c5ed..f81d56f7c12 100644 --- a/Bindings/net/can/fsl,flexcan.yaml +++ b/Bindings/net/can/fsl,flexcan.yaml @@ -10,9 +10,6 @@ title: maintainers: - Marc Kleine-Budde -allOf: - - $ref: can-controller.yaml# - properties: compatible: oneOf: @@ -28,6 +25,7 @@ properties: - fsl,vf610-flexcan - fsl,ls1021ar2-flexcan - fsl,lx2160ar1-flexcan + - nxp,s32g2-flexcan - items: - enum: - fsl,imx53-flexcan @@ -43,12 +41,25 @@ properties: - enum: - fsl,ls1028ar1-flexcan - const: fsl,lx2160ar1-flexcan + - items: + - enum: + - nxp,s32g3-flexcan + - const: nxp,s32g2-flexcan + - items: + - enum: + - fsl,imx94-flexcan + - const: fsl,imx95-flexcan reg: maxItems: 1 interrupts: - maxItems: 1 + minItems: 1 + maxItems: 4 + + interrupt-names: + minItems: 1 + maxItems: 4 clocks: maxItems: 2 @@ -70,6 +81,9 @@ properties: xceiver-supply: description: Regulator that powers the CAN transceiver. + phys: + maxItems: 1 + big-endian: $ref: /schemas/types.yaml#/definitions/flag description: | @@ -136,6 +150,41 @@ required: - reg - interrupts +allOf: + - $ref: can-controller.yaml# + - if: + properties: + compatible: + contains: + const: nxp,s32g2-flexcan + then: + properties: + interrupts: + items: + - description: Message Buffer interrupt for mailboxes 0-7 and Enhanced RX FIFO + - description: Device state change + - description: Bus Error detection + - description: Message Buffer interrupt for mailboxes 8-127 + interrupt-names: + items: + - const: mb-0 + - const: state + - const: berr + - const: mb-1 + required: + - interrupt-names + else: + properties: + interrupts: + maxItems: 1 + interrupt-names: false + - if: + required: + - xceiver-supply + then: + properties: + phys: false + additionalProperties: false examples: diff --git a/Bindings/net/can/microchip,mcp2510.yaml b/Bindings/net/can/microchip,mcp2510.yaml index e0ec53bc10c..1525a50ded4 100644 --- a/Bindings/net/can/microchip,mcp2510.yaml +++ b/Bindings/net/can/microchip,mcp2510.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/can/microchip,mcp2510.yaml# +$id: http://devicetree.org/schemas/net/can/microchip,mcp2510.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Microchip MCP251X stand-alone CAN controller diff --git a/Bindings/net/can/microchip,mcp251xfd.yaml b/Bindings/net/can/microchip,mcp251xfd.yaml index 2a98b26630c..c155c9c6db3 100644 --- a/Bindings/net/can/microchip,mcp251xfd.yaml +++ b/Bindings/net/can/microchip,mcp251xfd.yaml @@ -40,7 +40,7 @@ properties: microchip,rx-int-gpios: description: - GPIO phandle of GPIO connected to to INT1 pin of the MCP251XFD, which + GPIO phandle of GPIO connected to INT1 pin of the MCP251XFD, which signals a pending RX interrupt. maxItems: 1 diff --git a/Bindings/net/cdns,macb.yaml b/Bindings/net/cdns,macb.yaml index 3c30dd23cd4..8d69846b2e0 100644 --- a/Bindings/net/cdns,macb.yaml +++ b/Bindings/net/cdns,macb.yaml @@ -197,7 +197,6 @@ examples: }; - | - #include #include #include #include @@ -210,9 +209,9 @@ examples: interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; reg = <0x0 0xff0c0000 0x0 0x1000>; - clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>, - <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>, - <&zynqmp_clk GEM_TSU>; + clocks = <&zynqmp_clk 31>, <&zynqmp_clk 105>, + <&zynqmp_clk 51>, <&zynqmp_clk 50>, + <&zynqmp_clk 44>; clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; #address-cells = <1>; #size-cells = <0>; diff --git a/Bindings/net/dsa/brcm,b53.yaml b/Bindings/net/dsa/brcm,b53.yaml index 4c78c546343..d6c957a33b4 100644 --- a/Bindings/net/dsa/brcm,b53.yaml +++ b/Bindings/net/dsa/brcm,b53.yaml @@ -16,6 +16,7 @@ properties: compatible: oneOf: - const: brcm,bcm5325 + - const: brcm,bcm53101 - const: brcm,bcm53115 - const: brcm,bcm53125 - const: brcm,bcm53128 @@ -77,6 +78,7 @@ allOf: contains: enum: - brcm,bcm5325 + - brcm,bcm53101 - brcm,bcm53115 - brcm,bcm53125 - brcm,bcm53128 diff --git a/Bindings/net/ethernet-controller.yaml b/Bindings/net/ethernet-controller.yaml index 45819b23580..a2d4c626f65 100644 --- a/Bindings/net/ethernet-controller.yaml +++ b/Bindings/net/ethernet-controller.yaml @@ -74,19 +74,17 @@ properties: - rev-rmii - moca - # RX and TX delays are added by the MAC when required + # RX and TX delays are provided by the PCB. See below - rgmii - # RGMII with internal RX and TX delays provided by the PHY, - # the MAC should not add the RX or TX delays in this case + # RX and TX delays are not provided by the PCB. This is the most + # frequent case. See below - rgmii-id - # RGMII with internal RX delay provided by the PHY, the MAC - # should not add an RX delay in this case + # TX delay is provided by the PCB. See below - rgmii-rxid - # RGMII with internal TX delay provided by the PHY, the MAC - # should not add an TX delay in this case + # RX delay is provided by the PCB. See below - rgmii-txid - rtbi - smii @@ -286,4 +284,89 @@ allOf: additionalProperties: true +# Informative +# =========== +# +# 'phy-modes' & 'phy-connection-type' properties 'rgmii', 'rgmii-id', +# 'rgmii-rxid', and 'rgmii-txid' are frequently used wrongly by +# developers. This informative section clarifies their usage. +# +# The RGMII specification requires a 2ns delay between the data and +# clock signals on the RGMII bus. How this delay is implemented is not +# specified. +# +# One option is to make the clock traces on the PCB longer than the +# data traces. A sufficiently difference in length can provide the 2ns +# delay. If both the RX and TX delays are implemented in this manner, +# 'rgmii' should be used, so indicating the PCB adds the delays. +# +# If the PCB does not add these delays via extra long traces, +# 'rgmii-id' should be used. Here, 'id' refers to 'internal delay', +# where either the MAC or PHY adds the delay. +# +# If only one of the two delays are implemented via extra long clock +# lines, either 'rgmii-rxid' or 'rgmii-txid' should be used, +# indicating the MAC or PHY should implement one of the delays +# internally, while the PCB implements the other delay. +# +# Device Tree describes hardware, and in this case, it describes the +# PCB between the MAC and the PHY, if the PCB implements delays or +# not. +# +# In practice, very few PCBs make use of extra long clock lines. Hence +# any RGMII phy mode other than 'rgmii-id' is probably wrong, and is +# unlikely to be accepted during review without details provided in +# the commit description and comments in the .dts file. +# +# When the PCB does not implement the delays, the MAC or PHY must. As +# such, this is software configuration, and so not described in Device +# Tree. +# +# The following describes how Linux implements the configuration of +# the MAC and PHY to add these delays when the PCB does not. As stated +# above, developers often get this wrong, and the aim of this section +# is reduce the frequency of these errors by Linux developers. Other +# users of the Device Tree may implement it differently, and still be +# consistent with both the normative and informative description +# above. +# +# By default in Linux, when using phylib/phylink, the MAC is expected +# to read the 'phy-mode' from Device Tree, not implement any delays, +# and pass the value to the PHY. The PHY will then implement delays as +# specified by the 'phy-mode'. The PHY should always be reconfigured +# to implement the needed delays, replacing any setting performed by +# strapping or the bootloader, etc. +# +# Experience to date is that all PHYs which implement RGMII also +# implement the ability to add or not add the needed delays. Hence +# this default is expected to work in all cases. Ignoring this default +# is likely to be questioned by Reviews, and require a strong argument +# to be accepted. +# +# There are a small number of cases where the MAC has hard coded +# delays which cannot be disabled. The 'phy-mode' only describes the +# PCB. The inability to disable the delays in the MAC does not change +# the meaning of 'phy-mode'. It does however mean that a 'phy-mode' of +# 'rgmii' is now invalid, it cannot be supported, since both the PCB +# and the MAC and PHY adding delays cannot result in a functional +# link. Thus the MAC should report a fatal error for any modes which +# cannot be supported. When the MAC implements the delay, it must +# ensure that the PHY does not also implement the same delay. So it +# must modify the phy-mode it passes to the PHY, removing the delay it +# has added. Failure to remove the delay will result in a +# non-functioning link. +# +# Sometimes there is a need to fine tune the delays. Often the MAC or +# PHY can perform this fine tuning. In the MAC node, the Device Tree +# properties 'rx-internal-delay-ps' and 'tx-internal-delay-ps' should +# be used to indicate fine tuning performed by the MAC. The values +# expected here are small. A value of 2000ps, i.e 2ns, and a phy-mode +# of 'rgmii' will not be accepted by Reviewers. +# +# If the PHY is to perform fine tuning, the properties +# 'rx-internal-delay-ps' and 'tx-internal-delay-ps' in the PHY node +# should be used. When the PHY is implementing delays, e.g. 'rgmii-id' +# these properties should have a value near to 2000ps. If the PCB is +# implementing delays, e.g. 'rgmii', a small value can be used to fine +# tune the delay added by the PCB. ... diff --git a/Bindings/net/ethernet-phy.yaml b/Bindings/net/ethernet-phy.yaml index 2c71454ae8e..824bbe4333b 100644 --- a/Bindings/net/ethernet-phy.yaml +++ b/Bindings/net/ethernet-phy.yaml @@ -232,6 +232,12 @@ properties: PHY's that have configurable TX internal delays. If this property is present then the PHY applies the TX delay. + tx-amplitude-100base-tx-percent: + description: + Transmit amplitude gain applied for 100BASE-TX. 100% matches 2V + peak-to-peak specified in ANSI X3.263. When omitted, the PHYs default + will be left as is. + leds: type: object diff --git a/Bindings/net/faraday,ftgmac100.yaml b/Bindings/net/faraday,ftgmac100.yaml index 9bcbacb6640..55d6a837902 100644 --- a/Bindings/net/faraday,ftgmac100.yaml +++ b/Bindings/net/faraday,ftgmac100.yaml @@ -44,6 +44,9 @@ properties: phy-mode: enum: - rgmii + - rgmii-id + - rgmii-rxid + - rgmii-txid - rmii phy-handle: true diff --git a/Bindings/net/fsl,gianfar-mdio.yaml b/Bindings/net/fsl,gianfar-mdio.yaml new file mode 100644 index 00000000000..03c819bc701 --- /dev/null +++ b/Bindings/net/fsl,gianfar-mdio.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/fsl,gianfar-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Gianfar (TSEC) MDIO Device + +description: + This binding describes the MDIO is a bus to which the PHY devices are + connected. For each device that exists on this bus, a child node should be + created. + + Some TSECs are associated with an internal Ten-Bit Interface (TBI) PHY. This + PHY is accessed through the local MDIO bus. These buses are defined similarly + to the mdio buses, except they are compatible with "fsl,gianfar-tbi". The TBI + PHYs underneath them are similar to normal PHYs, but the reg property is + considered instructive, rather than descriptive. The reg property should be + chosen so it doesn't interfere with other PHYs on the bus. + +maintainers: + - J. Neuschäfer + +# This is needed to distinguish gianfar.yaml and gianfar-mdio.yaml, because +# both use compatible = "gianfar" (with different device_type values) +select: + oneOf: + - properties: + compatible: + contains: + const: gianfar + device_type: + const: mdio + required: + - device_type + + - properties: + compatible: + contains: + enum: + - fsl,gianfar-tbi + - fsl,gianfar-mdio + - fsl,etsec2-tbi + - fsl,etsec2-mdio + - fsl,ucc-mdio + - ucc_geth_phy + + required: + - compatible + +properties: + compatible: + enum: + - fsl,gianfar-tbi + - fsl,gianfar-mdio + - fsl,etsec2-tbi + - fsl,etsec2-mdio + - fsl,ucc-mdio + - gianfar + - ucc_geth_phy + + reg: + minItems: 1 + items: + - description: + Offset and length of the register set for the device + + - description: + Optionally, the offset and length of the TBIPA register (TBI PHY + address register). If TBIPA register is not specified, the driver + will attempt to infer it from the register set specified (your + mileage may vary). + + device_type: + const: mdio + +required: + - reg + - "#address-cells" + - "#size-cells" + +allOf: + - $ref: mdio.yaml# + + - if: + properties: + compatible: + contains: + const: ucc_geth_phy + then: + required: + - device_type + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <1>; + #size-cells = <1>; + + mdio@24520 { + reg = <0x24520 0x20>; + compatible = "fsl,gianfar-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + reg = <0>; + }; + }; + }; diff --git a/Bindings/net/fsl,gianfar.yaml b/Bindings/net/fsl,gianfar.yaml new file mode 100644 index 00000000000..f92f284aa05 --- /dev/null +++ b/Bindings/net/fsl,gianfar.yaml @@ -0,0 +1,248 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/fsl,gianfar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Three-Speed Ethernet Controller (TSEC), "Gianfar" + +maintainers: + - J. Neuschäfer + +# This is needed to distinguish gianfar.yaml and gianfar-mdio.yaml, because +# both use compatible = "gianfar" (with different device_type values) +select: + oneOf: + - properties: + compatible: + contains: + const: gianfar + device_type: + const: network + required: + - device_type + + - properties: + compatible: + const: fsl,etsec2 + + required: + - compatible + +properties: + compatible: + enum: + - gianfar + - fsl,etsec2 + + device_type: + const: network + + model: + enum: + - FEC + - TSEC + - eTSEC + + reg: + maxItems: 1 + + ranges: true + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + + interrupts: + minItems: 1 + items: + - description: Transmit interrupt or single combined interrupt + - description: Receive interrupt + - description: Error interrupt + + dma-coherent: true + + fsl,magic-packet: + type: boolean + description: + If present, indicates that the hardware supports waking up via magic packet. + + fsl,wake-on-filer: + type: boolean + description: + If present, indicates that the hardware supports waking up by Filer + General Purpose Interrupt (FGPI) asserted on the Rx int line. This is + an advanced power management capability allowing certain packet types + (user) defined by filer rules to wake up the system. + + bd-stash: + type: boolean + description: + If present, indicates that the hardware supports stashing buffer + descriptors in the L2. + + rx-stash-len: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Denotes the number of bytes of a received buffer to stash in the L2. + + rx-stash-idx: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Denotes the index of the first byte from the received buffer to stash in + the L2. + + fsl,num_rx_queues: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of receive queues + const: 8 + + fsl,num_tx_queues: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of transmit queues + const: 8 + + tbi-handle: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference (phandle) to the TBI node + +required: + - compatible + - model + +patternProperties: + "^mdio@[0-9a-f]+$": + $ref: /schemas/net/fsl,gianfar-mdio.yaml# + +allOf: + - $ref: ethernet-controller.yaml# + + # eTSEC2 controller nodes have "queue group" subnodes and don't need a "reg" + # property. + - if: + properties: + compatible: + contains: + const: fsl,etsec2 + then: + patternProperties: + "^queue-group@[0-9a-f]+$": + type: object + + properties: + reg: + maxItems: 1 + + interrupts: + items: + - description: Transmit interrupt + - description: Receive interrupt + - description: Error interrupt + + required: + - reg + - interrupts + + additionalProperties: false + else: + required: + - reg + + # TSEC and eTSEC devices require three interrupts + - if: + properties: + model: + contains: + enum: [ TSEC, eTSEC ] + then: + properties: + interrupts: + items: + - description: Transmit interrupt + - description: Receive interrupt + - description: Error interrupt + + + +unevaluatedProperties: false + +examples: + - | + ethernet@24000 { + device_type = "network"; + model = "TSEC"; + compatible = "gianfar"; + reg = <0x24000 0x1000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <29 2>, <30 2>, <34 2>; + interrupt-parent = <&mpic>; + phy-handle = <&phy0>; + }; + + - | + #include + + ethernet@24000 { + compatible = "gianfar"; + reg = <0x24000 0x1000>; + ranges = <0x0 0x24000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + cell-index = <0>; + device_type = "network"; + model = "eTSEC"; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <32 IRQ_TYPE_LEVEL_LOW>, + <33 IRQ_TYPE_LEVEL_LOW>, + <34 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&ipic>; + + mdio@520 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,gianfar-mdio"; + reg = <0x520 0x20>; + }; + }; + + - | + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + ethernet { + compatible = "fsl,etsec2"; + ranges; + device_type = "network"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + model = "eTSEC"; + fsl,magic-packet; + dma-coherent; + + queue-group@2d10000 { + reg = <0x0 0x2d10000 0x0 0x1000>; + interrupts = , + , + ; + }; + + queue-group@2d14000 { + reg = <0x0 0x2d14000 0x0 0x1000>; + interrupts = , + , + ; + }; + }; + }; + +... diff --git a/Bindings/net/fsl-tsec-phy.txt b/Bindings/net/fsl-tsec-phy.txt index 9c9668c1b6a..b18bb4c997e 100644 --- a/Bindings/net/fsl-tsec-phy.txt +++ b/Bindings/net/fsl-tsec-phy.txt @@ -1,88 +1,14 @@ * MDIO IO device -The MDIO is a bus to which the PHY devices are connected. For each -device that exists on this bus, a child node should be created. See -the definition of the PHY node in booting-without-of.txt for an example -of how to define a PHY. - -Required properties: - - reg : Offset and length of the register set for the device, and optionally - the offset and length of the TBIPA register (TBI PHY address - register). If TBIPA register is not specified, the driver will - attempt to infer it from the register set specified (your mileage may - vary). - - compatible : Should define the compatible device type for the - mdio. Currently supported strings/devices are: - - "fsl,gianfar-tbi" - - "fsl,gianfar-mdio" - - "fsl,etsec2-tbi" - - "fsl,etsec2-mdio" - - "fsl,ucc-mdio" - - "fsl,fman-mdio" - When device_type is "mdio", the following strings are also considered: - - "gianfar" - - "ucc_geth_phy" - -Example: - - mdio@24520 { - reg = <24520 20>; - compatible = "fsl,gianfar-mdio"; - - ethernet-phy@0 { - ...... - }; - }; +Refer to Documentation/devicetree/bindings/net/fsl,gianfar-mdio.yaml * TBI Internal MDIO bus -As of this writing, every tsec is associated with an internal TBI PHY. -This PHY is accessed through the local MDIO bus. These buses are defined -similarly to the mdio buses, except they are compatible with "fsl,gianfar-tbi". -The TBI PHYs underneath them are similar to normal PHYs, but the reg property -is considered instructive, rather than descriptive. The reg property should -be chosen so it doesn't interfere with other PHYs on the bus. +Refer to Documentation/devicetree/bindings/net/fsl,gianfar-mdio.yaml * Gianfar-compatible ethernet nodes -Properties: - - - device_type : Should be "network" - - model : Model of the device. Can be "TSEC", "eTSEC", or "FEC" - - compatible : Should be "gianfar" - - reg : Offset and length of the register set for the device - - interrupts : For FEC devices, the first interrupt is the device's - interrupt. For TSEC and eTSEC devices, the first interrupt is - transmit, the second is receive, and the third is error. - - phy-handle : See ethernet.txt file in the same directory. - - fixed-link : See fixed-link.txt in the same directory. - - phy-connection-type : See ethernet.txt file in the same directory. - This property is only really needed if the connection is of type - "rgmii-id", as all other connection types are detected by hardware. - - fsl,magic-packet : If present, indicates that the hardware supports - waking up via magic packet. - - fsl,wake-on-filer : If present, indicates that the hardware supports - waking up by Filer General Purpose Interrupt (FGPI) asserted on the - Rx int line. This is an advanced power management capability allowing - certain packet types (user) defined by filer rules to wake up the system. - - bd-stash : If present, indicates that the hardware supports stashing - buffer descriptors in the L2. - - rx-stash-len : Denotes the number of bytes of a received buffer to stash - in the L2. - - rx-stash-idx : Denotes the index of the first byte from the received - buffer to stash in the L2. - -Example: - ethernet@24000 { - device_type = "network"; - model = "TSEC"; - compatible = "gianfar"; - reg = <0x24000 0x1000>; - local-mac-address = [ 00 E0 0C 00 73 00 ]; - interrupts = <29 2 30 2 34 2>; - interrupt-parent = <&mpic>; - phy-handle = <&phy0> - }; +Refer to Documentation/devicetree/bindings/net/fsl,gianfar.yaml * Gianfar PTP clock nodes diff --git a/Bindings/net/ieee802154/ca8210.txt b/Bindings/net/ieee802154/ca8210.txt index a1046e636fa..f1bd07a0097 100644 --- a/Bindings/net/ieee802154/ca8210.txt +++ b/Bindings/net/ieee802154/ca8210.txt @@ -20,7 +20,7 @@ Example: reg = <0>; spi-max-frequency = <3000000>; spi-cpol; - reset-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; + reset-gpio = <&gpio1 1 GPIO_ACTIVE_LOW>; irq-gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; extclock-enable; extclock-freq = 16000000; diff --git a/Bindings/net/intel,dwmac-plat.yaml b/Bindings/net/intel,dwmac-plat.yaml index 42a0bc94312..62c1da36a2b 100644 --- a/Bindings/net/intel,dwmac-plat.yaml +++ b/Bindings/net/intel,dwmac-plat.yaml @@ -41,6 +41,12 @@ properties: - const: ptp_ref - const: tx_clk + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + required: - compatible - clocks diff --git a/Bindings/net/mediatek-dwmac.yaml b/Bindings/net/mediatek-dwmac.yaml index ed9d845f600..3aab21b8e8d 100644 --- a/Bindings/net/mediatek-dwmac.yaml +++ b/Bindings/net/mediatek-dwmac.yaml @@ -64,6 +64,12 @@ properties: - const: rmii_internal - const: mac_cg + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + power-domains: maxItems: 1 diff --git a/Bindings/net/nxp,dwmac-imx.yaml b/Bindings/net/nxp,dwmac-imx.yaml index 87bc4416ead..e5db346beca 100644 --- a/Bindings/net/nxp,dwmac-imx.yaml +++ b/Bindings/net/nxp,dwmac-imx.yaml @@ -56,6 +56,14 @@ properties: - tx - mem + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: macirq + - const: eth_wake_irq + intf_mode: $ref: /schemas/types.yaml#/definitions/phandle-array items: diff --git a/Bindings/net/qcom,ipa.yaml b/Bindings/net/qcom,ipa.yaml index 1a46d80a66e..b4a79912d47 100644 --- a/Bindings/net/qcom,ipa.yaml +++ b/Bindings/net/qcom,ipa.yaml @@ -210,70 +210,70 @@ additionalProperties: false examples: - | - #include - #include - #include - - smp2p-mpss { - compatible = "qcom,smp2p"; - interrupts = ; - mboxes = <&apss_shared 6>; - qcom,smem = <94>, <432>; - qcom,local-pid = <0>; - qcom,remote-pid = <5>; - - ipa_smp2p_out: ipa-ap-to-modem { - qcom,entry-name = "ipa"; - #qcom,smem-state-cells = <1>; - }; - - ipa_smp2p_in: ipa-modem-to-ap { - qcom,entry-name = "ipa"; - interrupt-controller; - #interrupt-cells = <2>; - }; + #include + #include + #include + + smp2p-mpss { + compatible = "qcom,smp2p"; + interrupts = ; + mboxes = <&apss_shared 6>; + qcom,smem = <94>, <432>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; }; - ipa@1e40000 { - compatible = "qcom,sc7180-ipa"; - - qcom,gsi-loader = "self"; - memory-region = <&ipa_fw_mem>; - firmware-name = "qcom/sc7180-trogdor/modem/modem.mbn"; - - iommus = <&apps_smmu 0x440 0x0>, - <&apps_smmu 0x442 0x0>; - reg = <0x1e40000 0x7000>, - <0x1e47000 0x2000>, - <0x1e04000 0x2c000>; - reg-names = "ipa-reg", - "ipa-shared", - "gsi"; - - interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, - <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, - <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "ipa", - "gsi", - "ipa-clock-query", - "ipa-setup-ready"; - - clocks = <&rpmhcc RPMH_IPA_CLK>; - clock-names = "core"; - - interconnects = - <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, - <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, - <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; - interconnect-names = "memory", - "imem", - "config"; - - qcom,qmp = <&aoss_qmp>; - - qcom,smem-states = <&ipa_smp2p_out 0>, - <&ipa_smp2p_out 1>; - qcom,smem-state-names = "ipa-clock-enabled-valid", - "ipa-clock-enabled"; + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; }; + }; + + ipa@1e40000 { + compatible = "qcom,sc7180-ipa"; + + qcom,gsi-loader = "self"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sc7180-trogdor/modem/modem.mbn"; + + iommus = <&apps_smmu 0x440 0x0>, + <&apps_smmu 0x442 0x0>; + reg = <0x1e40000 0x7000>, + <0x1e47000 0x2000>, + <0x1e04000 0x2c000>; + reg-names = "ipa-reg", + "ipa-shared", + "gsi"; + + interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ipa", + "gsi", + "ipa-clock-query", + "ipa-setup-ready"; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + clock-names = "core"; + + interconnects = + <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, + <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; + interconnect-names = "memory", + "imem", + "config"; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&ipa_smp2p_out 0>, + <&ipa_smp2p_out 1>; + qcom,smem-state-names = "ipa-clock-enabled-valid", + "ipa-clock-enabled"; + }; diff --git a/Bindings/net/realtek,rtl9301-mdio.yaml b/Bindings/net/realtek,rtl9301-mdio.yaml new file mode 100644 index 00000000000..02e4e33e996 --- /dev/null +++ b/Bindings/net/realtek,rtl9301-mdio.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/realtek,rtl9301-mdio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek RTL9300 MDIO Controller + +maintainers: + - Chris Packham + +properties: + compatible: + oneOf: + - items: + - enum: + - realtek,rtl9302b-mdio + - realtek,rtl9302c-mdio + - realtek,rtl9303-mdio + - const: realtek,rtl9301-mdio + - const: realtek,rtl9301-mdio + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + reg: + maxItems: 1 + +patternProperties: + '^mdio-bus@[0-3]$': + $ref: mdio.yaml# + + properties: + reg: + maxItems: 1 + + required: + - reg + + patternProperties: + '^ethernet-phy@[a-f0-9]+$': + type: object + $ref: ethernet-phy.yaml# + unevaluatedProperties: false + + unevaluatedProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + mdio-controller@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + + mdio-bus@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + }; + }; + + mdio-bus@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + }; + }; + }; diff --git a/Bindings/net/realtek,rtl9301-switch.yaml b/Bindings/net/realtek,rtl9301-switch.yaml new file mode 100644 index 00000000000..80eabc17066 --- /dev/null +++ b/Bindings/net/realtek,rtl9301-switch.yaml @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/realtek,rtl9301-switch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Realtek Switch with Internal CPU + +maintainers: + - Chris Packham + +description: + The RTL9300 is a series of is an Ethernet switches with an integrated CPU. A + number of different peripherals are accessed through a common register block, + represented here as a syscon node. + +$ref: ethernet-switch.yaml#/$defs/ethernet-ports + +properties: + compatible: + items: + - enum: + - realtek,rtl9301-switch + - realtek,rtl9302b-switch + - realtek,rtl9302c-switch + - realtek,rtl9303-switch + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: switch + - const: nic + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ethernet-ports: + type: object + +patternProperties: + 'reboot@[0-9a-f]+$': + $ref: /schemas/power/reset/syscon-reboot.yaml# + + 'i2c@[0-9a-f]+$': + $ref: /schemas/i2c/realtek,rtl9301-i2c.yaml# + + 'mdio-controller@[0-9a-f]+$': + $ref: realtek,rtl9301-mdio.yaml# + +required: + - compatible + - reg + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + ethernet-switch@1b000000 { + compatible = "realtek,rtl9301-switch", "syscon", "simple-mfd"; + reg = <0x1b000000 0x10000>; + interrupt-parent = <&intc>; + interrupts = <23>, <24>; + interrupt-names = "switch", "nic"; + #address-cells = <1>; + #size-cells = <1>; + + reboot@c { + compatible = "syscon-reboot"; + reg = <0x0c 0x4>; + value = <0x01>; + }; + + i2c@36c { + compatible = "realtek,rtl9301-i2c"; + reg = <0x36c 0x14>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + gpio@20 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + gpio@20 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; + }; + }; + + i2c@388 { + compatible = "realtek,rtl9301-i2c"; + reg = <0x388 0x14>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + gpio@20 { + compatible = "nxp,pca9555"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x20>; + }; + }; + }; + + mdio-controller@ca00 { + compatible = "realtek,rtl9301-mdio"; + reg = <0xca00 0x200>; + #address-cells = <1>; + #size-cells = <0>; + + mdio-bus@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + phy1: ethernet-phy@0 { + reg = <0>; + }; + }; + mdio-bus@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + phy2: ethernet-phy@0 { + reg = <0>; + }; + }; + }; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + phy-handle = <&phy1>; + }; + port@1 { + reg = <1>; + phy-handle = <&phy2>; + }; + }; + }; + diff --git a/Bindings/net/rfkill-gpio.yaml b/Bindings/net/rfkill-gpio.yaml index 9630c8466fa..4a706a41ab3 100644 --- a/Bindings/net/rfkill-gpio.yaml +++ b/Bindings/net/rfkill-gpio.yaml @@ -32,6 +32,10 @@ properties: shutdown-gpios: maxItems: 1 + default-blocked: + $ref: /schemas/types.yaml#/definitions/flag + description: configure rfkill state as blocked at boot + required: - compatible - radio-type @@ -48,4 +52,5 @@ examples: label = "rfkill-pcie-wlan"; radio-type = "wlan"; shutdown-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; + default-blocked; }; diff --git a/Bindings/net/rockchip-dwmac.yaml b/Bindings/net/rockchip-dwmac.yaml index f8a576611d6..0ac7c4b47d6 100644 --- a/Bindings/net/rockchip-dwmac.yaml +++ b/Bindings/net/rockchip-dwmac.yaml @@ -24,6 +24,7 @@ select: - rockchip,rk3366-gmac - rockchip,rk3368-gmac - rockchip,rk3399-gmac + - rockchip,rk3528-gmac - rockchip,rk3568-gmac - rockchip,rk3576-gmac - rockchip,rk3588-gmac @@ -32,9 +33,6 @@ select: required: - compatible -allOf: - - $ref: snps,dwmac.yaml# - properties: compatible: oneOf: @@ -52,14 +50,25 @@ properties: - rockchip,rv1108-gmac - items: - enum: + - rockchip,rk3528-gmac - rockchip,rk3568-gmac - rockchip,rk3576-gmac - rockchip,rk3588-gmac - rockchip,rv1126-gmac - const: snps,dwmac-4.20a + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - const: macirq + - const: eth_wake_irq + clocks: - minItems: 5 + minItems: 4 maxItems: 8 clock-names: @@ -114,6 +123,36 @@ required: - compatible - clocks - clock-names + - rockchip,grf + +allOf: + - $ref: snps,dwmac.yaml# + + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3576-gmac + - rockchip,rk3588-gmac + then: + required: + - rockchip,php-grf + else: + properties: + rockchip,php-grf: false + + - if: + not: + properties: + compatible: + contains: + enum: + - rockchip,rk3528-gmac + then: + properties: + clocks: + minItems: 5 unevaluatedProperties: false diff --git a/Bindings/net/smsc,lan9115.yaml b/Bindings/net/smsc,lan9115.yaml index f86667cbcca..42279ae8c2b 100644 --- a/Bindings/net/smsc,lan9115.yaml +++ b/Bindings/net/smsc,lan9115.yaml @@ -11,6 +11,7 @@ maintainers: allOf: - $ref: ethernet-controller.yaml# + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# properties: compatible: @@ -89,10 +90,7 @@ required: - reg - interrupts -# There are lots of bus-specific properties ("qcom,*", "samsung,*", "fsl,*", -# "gpmc,*", ...) to be found, that actually depend on the compatible value of -# the parent node. -additionalProperties: true +unevaluatedProperties: false examples: - | diff --git a/Bindings/net/snps,dwmac.yaml b/Bindings/net/snps,dwmac.yaml index 91e75eb3f32..78b3030dc56 100644 --- a/Bindings/net/snps,dwmac.yaml +++ b/Bindings/net/snps,dwmac.yaml @@ -32,6 +32,7 @@ select: - snps,dwmac-4.20a - snps,dwmac-5.10a - snps,dwmac-5.20 + - snps,dwmac-5.30a - snps,dwxgmac - snps,dwxgmac-2.10 @@ -98,10 +99,13 @@ properties: - snps,dwmac-4.20a - snps,dwmac-5.10a - snps,dwmac-5.20 + - snps,dwmac-5.30a - snps,dwxgmac - snps,dwxgmac-2.10 + - sophgo,sg2044-dwmac - starfive,jh7100-dwmac - starfive,jh7110-dwmac + - tesla,fsd-ethqos - thead,th1520-gmac reg: @@ -126,7 +130,7 @@ properties: clocks: minItems: 1 - maxItems: 8 + maxItems: 10 additionalItems: true items: - description: GMAC main clock @@ -138,7 +142,7 @@ properties: clock-names: minItems: 1 - maxItems: 8 + maxItems: 10 additionalItems: true contains: enum: @@ -490,6 +494,7 @@ properties: snps,en-tx-lpi-clockgating: $ref: /schemas/types.yaml#/definitions/flag + deprecated: true description: Enable gating of the MAC TX clock during TX low-power mode @@ -631,6 +636,7 @@ allOf: - snps,dwmac-4.20a - snps,dwmac-5.10a - snps,dwmac-5.20 + - snps,dwmac-5.30a - snps,dwxgmac - snps,dwxgmac-2.10 - st,spear600-gmac diff --git a/Bindings/net/sophgo,sg2044-dwmac.yaml b/Bindings/net/sophgo,sg2044-dwmac.yaml new file mode 100644 index 00000000000..4dd2dc9c678 --- /dev/null +++ b/Bindings/net/sophgo,sg2044-dwmac.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/sophgo,sg2044-dwmac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2044 DWMAC glue layer + +maintainers: + - Inochi Amaoto + +select: + properties: + compatible: + contains: + enum: + - sophgo,sg2044-dwmac + required: + - compatible + +properties: + compatible: + items: + - const: sophgo,sg2044-dwmac + - const: snps,dwmac-5.30a + + reg: + maxItems: 1 + + clocks: + items: + - description: GMAC main clock + - description: PTP clock + - description: TX clock + + clock-names: + items: + - const: stmmaceth + - const: ptp_ref + - const: tx + + dma-noncoherent: true + + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: stmmaceth + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - resets + - reset-names + +allOf: + - $ref: snps,dwmac.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + ethernet@30006000 { + compatible = "sophgo,sg2044-dwmac", "snps,dwmac-5.30a"; + reg = <0x30006000 0x4000>; + clocks = <&clk 151>, <&clk 152>, <&clk 154>; + clock-names = "stmmaceth", "ptp_ref", "tx"; + interrupt-parent = <&intc>; + interrupts = <296 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + resets = <&rst 30>; + reset-names = "stmmaceth"; + snps,multicast-filter-bins = <0>; + snps,perfect-filter-entries = <1>; + snps,aal; + snps,tso; + snps,txpbl = <32>; + snps,rxpbl = <32>; + snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; + snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; + snps,axi-config = <&gmac0_stmmac_axi_setup>; + status = "disabled"; + + gmac0_mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <8>; + snps,rx-sched-wsp; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + queue4 {}; + queue5 {}; + queue6 {}; + queue7 {}; + }; + + gmac0_mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <8>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + queue4 {}; + queue5 {}; + queue6 {}; + queue7 {}; + }; + + gmac0_stmmac_axi_setup: stmmac-axi-config { + snps,blen = <16 8 4 0 0 0 0>; + snps,wr_osr_lmt = <1>; + snps,rd_osr_lmt = <2>; + }; + }; diff --git a/Bindings/net/stm32-dwmac.yaml b/Bindings/net/stm32-dwmac.yaml index 85cea9966a2..987254900d0 100644 --- a/Bindings/net/stm32-dwmac.yaml +++ b/Bindings/net/stm32-dwmac.yaml @@ -54,6 +54,16 @@ properties: items: - const: stmmaceth + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + items: + - const: macirq + - const: eth_wake_irq + clocks: minItems: 3 items: diff --git a/Bindings/net/tesla,fsd-ethqos.yaml b/Bindings/net/tesla,fsd-ethqos.yaml new file mode 100644 index 00000000000..dd7481bb16e --- /dev/null +++ b/Bindings/net/tesla,fsd-ethqos.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/tesla,fsd-ethqos.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FSD Ethernet Quality of Service + +maintainers: + - Swathi K S + +description: + Tesla ethernet devices based on dwmmac support Gigabit ethernet. + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + const: tesla,fsd-ethqos + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: macirq + + clocks: + minItems: 5 + items: + - description: PTP clock + - description: Master bus clock + - description: Slave bus clock + - description: MAC TX clock + - description: MAC RX clock + - description: Master2 bus clock + - description: Slave2 bus clock + - description: RX MUX clock + - description: PHY RX clock + - description: PERIC RGMII clock + + clock-names: + minItems: 5 + items: + - const: ptp_ref + - const: master_bus + - const: slave_bus + - const: tx + - const: rx + - const: master2_bus + - const: slave2_bus + - const: eqos_rxclk_mux + - const: eqos_phyrxclk + - const: dout_peric_rgmii_clk + + iommus: + maxItems: 1 + + phy-mode: + enum: + - rgmii + - rgmii-id + - rgmii-rxid + - rgmii-txid + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - iommus + - phy-mode + +unevaluatedProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + ethernet1: ethernet@14300000 { + compatible = "tesla,fsd-ethqos"; + reg = <0x0 0x14300000 0x0 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I>, + <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_ACLK_I>, + <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_HCLK_I>, + <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I>, + <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I>, + <&clock_peric PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK>, + <&clock_peric PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK>, + <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>, + <&clock_peric PERIC_EQOS_PHYRXCLK>, + <&clock_peric PERIC_DOUT_RGMII_CLK>; + clock-names = "ptp_ref", "master_bus", "slave_bus","tx", + "rx", "master2_bus", "slave2_bus", "eqos_rxclk_mux", + "eqos_phyrxclk","dout_peric_rgmii_clk"; + assigned-clocks = <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>, + <&clock_peric PERIC_EQOS_PHYRXCLK>; + assigned-clock-parents = <&clock_peric PERIC_EQOS_PHYRXCLK>; + pinctrl-names = "default"; + pinctrl-0 = <ð1_tx_clk>, <ð1_tx_data>, <ð1_tx_ctrl>, + <ð1_phy_intr>, <ð1_rx_clk>, <ð1_rx_data>, + <ð1_rx_ctrl>, <ð1_mdio>; + iommus = <&smmu_peric 0x0 0x1>; + phy-mode = "rgmii-id"; + }; + }; + +... diff --git a/Bindings/net/toshiba,visconti-dwmac.yaml b/Bindings/net/toshiba,visconti-dwmac.yaml index 052f636158b..f0f32e18fc8 100644 --- a/Bindings/net/toshiba,visconti-dwmac.yaml +++ b/Bindings/net/toshiba,visconti-dwmac.yaml @@ -42,6 +42,12 @@ properties: - const: stmmaceth - const: phy_ref_clk + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + required: - compatible - reg diff --git a/Bindings/net/wireless/qcom,ath10k.yaml b/Bindings/net/wireless/qcom,ath10k.yaml index aace072e2d5..f2440d39b7e 100644 --- a/Bindings/net/wireless/qcom,ath10k.yaml +++ b/Bindings/net/wireless/qcom,ath10k.yaml @@ -92,20 +92,41 @@ properties: ieee80211-freq-limit: true + qcom,calibration-data: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: + Calibration data + board-specific data as a byte array. The length + can vary between hardware versions. + qcom,ath10k-calibration-data: $ref: /schemas/types.yaml#/definitions/uint8-array + deprecated: true description: Calibration data + board-specific data as a byte array. The length can vary between hardware versions. + qcom,calibration-variant: + $ref: /schemas/types.yaml#/definitions/string + description: + Unique variant identifier of the calibration data in board-2.bin + for designs with colliding bus and device specific ids + qcom,ath10k-calibration-variant: $ref: /schemas/types.yaml#/definitions/string + deprecated: true description: Unique variant identifier of the calibration data in board-2.bin for designs with colliding bus and device specific ids + qcom,pre-calibration-data: + $ref: /schemas/types.yaml#/definitions/uint8-array + description: + Pre-calibration data as a byte array. The length can vary between + hardware versions. + qcom,ath10k-pre-calibration-data: $ref: /schemas/types.yaml#/definitions/uint8-array + deprecated: true description: Pre-calibration data as a byte array. The length can vary between hardware versions. diff --git a/Bindings/net/wireless/qcom,ath11k-pci.yaml b/Bindings/net/wireless/qcom,ath11k-pci.yaml index a4425cf196a..653b319fee8 100644 --- a/Bindings/net/wireless/qcom,ath11k-pci.yaml +++ b/Bindings/net/wireless/qcom,ath11k-pci.yaml @@ -22,8 +22,15 @@ properties: reg: maxItems: 1 + qcom,calibration-variant: + $ref: /schemas/types.yaml#/definitions/string + description: | + string to uniquely identify variant of the calibration data for designs + with colliding bus and device ids + qcom,ath11k-calibration-variant: $ref: /schemas/types.yaml#/definitions/string + deprecated: true description: | string to uniquely identify variant of the calibration data for designs with colliding bus and device ids @@ -127,7 +134,7 @@ examples: vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; - qcom,ath11k-calibration-variant = "LE_X13S"; + qcom,calibration-variant = "LE_X13S"; }; }; }; diff --git a/Bindings/net/wireless/qcom,ath11k.yaml b/Bindings/net/wireless/qcom,ath11k.yaml index a69ffb7b3cb..c089677702c 100644 --- a/Bindings/net/wireless/qcom,ath11k.yaml +++ b/Bindings/net/wireless/qcom,ath11k.yaml @@ -41,8 +41,15 @@ properties: * reg * reg-names + qcom,calibration-variant: + $ref: /schemas/types.yaml#/definitions/string + description: + string to uniquely identify variant of the calibration data in the + board-2.bin for designs with colliding bus and device specific ids + qcom,ath11k-calibration-variant: $ref: /schemas/types.yaml#/definitions/string + deprecated: true description: string to uniquely identify variant of the calibration data in the board-2.bin for designs with colliding bus and device specific ids diff --git a/Bindings/net/wireless/qcom,ath12k-wsi.yaml b/Bindings/net/wireless/qcom,ath12k-wsi.yaml index 318f305405e..589960144fe 100644 --- a/Bindings/net/wireless/qcom,ath12k-wsi.yaml +++ b/Bindings/net/wireless/qcom,ath12k-wsi.yaml @@ -52,8 +52,15 @@ properties: reg: maxItems: 1 + qcom,calibration-variant: + $ref: /schemas/types.yaml#/definitions/string + description: + String to uniquely identify variant of the calibration data for designs + with colliding bus and device ids + qcom,ath12k-calibration-variant: $ref: /schemas/types.yaml#/definitions/string + deprecated: true description: String to uniquely identify variant of the calibration data for designs with colliding bus and device ids @@ -103,7 +110,7 @@ examples: compatible = "pci17cb,1109"; reg = <0x0 0x0 0x0 0x0 0x0>; - qcom,ath12k-calibration-variant = "RDP433_1"; + qcom,calibration-variant = "RDP433_1"; ports { #address-cells = <1>; @@ -139,7 +146,7 @@ examples: compatible = "pci17cb,1109"; reg = <0x0 0x0 0x0 0x0 0x0>; - qcom,ath12k-calibration-variant = "RDP433_2"; + qcom,calibration-variant = "RDP433_2"; qcom,wsi-controller; ports { @@ -176,7 +183,7 @@ examples: compatible = "pci17cb,1109"; reg = <0x0 0x0 0x0 0x0 0x0>; - qcom,ath12k-calibration-variant = "RDP433_3"; + qcom,calibration-variant = "RDP433_3"; ports { #address-cells = <1>; diff --git a/Bindings/nvmem/layouts/fixed-cell.yaml b/Bindings/nvmem/layouts/fixed-cell.yaml index 8b3826243dd..38e3ad50ff4 100644 --- a/Bindings/nvmem/layouts/fixed-cell.yaml +++ b/Bindings/nvmem/layouts/fixed-cell.yaml @@ -27,7 +27,7 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32-array items: - minimum: 0 - maximum: 7 + maximum: 31 description: Offset in bit within the address range specified by reg. - minimum: 1 diff --git a/Bindings/nvmem/qcom,qfprom.yaml b/Bindings/nvmem/qcom,qfprom.yaml index 39c209249c9..3f6dc6a3a9f 100644 --- a/Bindings/nvmem/qcom,qfprom.yaml +++ b/Bindings/nvmem/qcom,qfprom.yaml @@ -19,6 +19,7 @@ properties: - enum: - qcom,apq8064-qfprom - qcom,apq8084-qfprom + - qcom,ipq5018-qfprom - qcom,ipq5332-qfprom - qcom,ipq5424-qfprom - qcom,ipq6018-qfprom @@ -28,6 +29,8 @@ properties: - qcom,msm8226-qfprom - qcom,msm8916-qfprom - qcom,msm8917-qfprom + - qcom,msm8937-qfprom + - qcom,msm8960-qfprom - qcom,msm8974-qfprom - qcom,msm8976-qfprom - qcom,msm8996-qfprom @@ -51,6 +54,7 @@ properties: - qcom,sm8450-qfprom - qcom,sm8550-qfprom - qcom,sm8650-qfprom + - qcom,x1e80100-qfprom - const: qcom,qfprom reg: diff --git a/Bindings/nvmem/rockchip,otp.yaml b/Bindings/nvmem/rockchip,otp.yaml index a44d44b3280..dc89020b095 100644 --- a/Bindings/nvmem/rockchip,otp.yaml +++ b/Bindings/nvmem/rockchip,otp.yaml @@ -14,6 +14,7 @@ properties: enum: - rockchip,px30-otp - rockchip,rk3308-otp + - rockchip,rk3576-otp - rockchip,rk3588-otp reg: @@ -62,12 +63,34 @@ allOf: properties: clocks: maxItems: 3 + clock-names: + maxItems: 3 resets: maxItems: 1 reset-names: items: - const: phy + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3576-otp + then: + properties: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 + resets: + minItems: 2 + maxItems: 2 + reset-names: + items: + - const: otp + - const: apb + - if: properties: compatible: @@ -78,6 +101,8 @@ allOf: properties: clocks: minItems: 4 + clock-names: + minItems: 4 resets: minItems: 3 reset-names: diff --git a/Bindings/pci/altr,pcie-root-port.yaml b/Bindings/pci/altr,pcie-root-port.yaml index 52533fccc13..5d3f48a001b 100644 --- a/Bindings/pci/altr,pcie-root-port.yaml +++ b/Bindings/pci/altr,pcie-root-port.yaml @@ -12,9 +12,19 @@ maintainers: properties: compatible: + description: Each family of socfpga has its own implementation of the + PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5 + family of chips. The Stratix10 family of chips is supported by the + altr,pcie-root-port-2.0. The Agilex family of chips has three, + non-register compatible, variants of PCIe Hard IP referred to as the + F-Tile, P-Tile, and R-Tile, depending on the specific chip instance. + enum: - altr,pcie-root-port-1.0 - altr,pcie-root-port-2.0 + - altr,pcie-root-port-3.0-f-tile + - altr,pcie-root-port-3.0-p-tile + - altr,pcie-root-port-3.0-r-tile reg: items: diff --git a/Bindings/pci/amd,versal2-mdb-host.yaml b/Bindings/pci/amd,versal2-mdb-host.yaml new file mode 100644 index 00000000000..43dc2585c23 --- /dev/null +++ b/Bindings/pci/amd,versal2-mdb-host.yaml @@ -0,0 +1,121 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/amd,versal2-mdb-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Versal2 MDB(Multimedia DMA Bridge) Host Controller + +maintainers: + - Thippeswamy Havalige + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: amd,versal2-mdb-host + + reg: + items: + - description: MDB System Level Control and Status Register (SLCR) Base + - description: configuration region + - description: data bus interface + - description: address translation unit register + + reg-names: + items: + - const: slcr + - const: config + - const: dbi + - const: atu + + ranges: + maxItems: 2 + + msi-map: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-map-mask: + items: + - const: 0 + - const: 0 + - const: 0 + - const: 7 + + interrupt-map: + maxItems: 4 + + "#interrupt-cells": + const: 1 + + interrupt-controller: + description: identifies the node as an interrupt controller + type: object + additionalProperties: false + properties: + interrupt-controller: true + + "#address-cells": + const: 0 + + "#interrupt-cells": + const: 1 + + required: + - interrupt-controller + - "#address-cells" + - "#interrupt-cells" + +required: + - reg + - reg-names + - interrupts + - interrupt-map + - interrupt-map-mask + - msi-map + - "#interrupt-cells" + - interrupt-controller + +unevaluatedProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie@ed931000 { + compatible = "amd,versal2-mdb-host"; + reg = <0x0 0xed931000 0x0 0x2000>, + <0x1000 0x100000 0x0 0xff00000>, + <0x1000 0x0 0x0 0x1000>, + <0x0 0xed860000 0x0 0x2000>; + reg-names = "slcr", "config", "dbi", "atu"; + ranges = <0x2000000 0x00 0xa0000000 0x00 0xa0000000 0x00 0x10000000>, + <0x43000000 0x1100 0x00 0x1100 0x00 0x00 0x1000000>; + interrupts = ; + interrupt-parent = <&gic>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc_0 0>, + <0 0 0 2 &pcie_intc_0 1>, + <0 0 0 3 &pcie_intc_0 2>, + <0 0 0 4 &pcie_intc_0 3>; + msi-map = <0x0 &gic_its 0x00 0x10000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + pcie_intc_0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; diff --git a/Bindings/pci/brcm,stb-pcie.yaml b/Bindings/pci/brcm,stb-pcie.yaml index 2ad1652c258..29f0e1eb509 100644 --- a/Bindings/pci/brcm,stb-pcie.yaml +++ b/Bindings/pci/brcm,stb-pcie.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - brcm,bcm2711-pcie # The Raspberry Pi 4 + - brcm,bcm2712-pcie # Raspberry Pi 5 - brcm,bcm4908-pcie - brcm,bcm7211-pcie # Broadcom STB version of RPi4 - brcm,bcm7216-pcie # Broadcom 7216 Arm @@ -101,7 +102,10 @@ properties: reset-names: minItems: 1 - maxItems: 3 + items: + - enum: [perst, rescal] + - const: bridge + - const: swinit required: - compatible diff --git a/Bindings/pci/fsl,imx6q-pcie.yaml b/Bindings/pci/fsl,imx6q-pcie.yaml index 4c76cd3f98a..ca5f2970f21 100644 --- a/Bindings/pci/fsl,imx6q-pcie.yaml +++ b/Bindings/pci/fsl,imx6q-pcie.yaml @@ -47,12 +47,16 @@ properties: maxItems: 5 interrupts: + minItems: 1 items: - description: builtin MSI controller. + - description: builtin DMA controller. interrupt-names: + minItems: 1 items: - const: msi + - const: dma reset-gpio: description: Should specify the GPIO for controlling the PCI bus device diff --git a/Bindings/pci/fsl,layerscape-pcie-ep.yaml b/Bindings/pci/fsl,layerscape-pcie-ep.yaml index 399efa7364c..d78a6d1f719 100644 --- a/Bindings/pci/fsl,layerscape-pcie-ep.yaml +++ b/Bindings/pci/fsl,layerscape-pcie-ep.yaml @@ -94,9 +94,6 @@ examples: reg-names = "regs", "addr_space"; interrupts = ; /* PME interrupt */ interrupt-names = "pme"; - num-ib-windows = <6>; - num-ob-windows = <8>; - status = "disabled"; }; }; ... diff --git a/Bindings/pci/fsl,mpc8xxx-pci.yaml b/Bindings/pci/fsl,mpc8xxx-pci.yaml new file mode 100644 index 00000000000..28759ab1caa --- /dev/null +++ b/Bindings/pci/fsl,mpc8xxx-pci.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- + +$id: http://devicetree.org/schemas/pci/fsl,mpc8xxx-pci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MPC83xx PCI/PCI-X/PCIe controllers + +description: + Binding for the PCI/PCI-X/PCIe host bridges on MPC8xxx SoCs + +maintainers: + - J. Neuschäfer + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +properties: + compatible: + oneOf: + - enum: + - fsl,mpc8314-pcie + - fsl,mpc8349-pci + - fsl,mpc8540-pci + - fsl,mpc8548-pcie + - fsl,mpc8641-pcie + - items: + - enum: + - fsl,mpc8308-pcie + - fsl,mpc8315-pcie + - fsl,mpc8377-pcie + - fsl,mpc8378-pcie + - const: fsl,mpc8314-pcie + - items: + - const: fsl,mpc8360-pci + - const: fsl,mpc8349-pci + - items: + - const: fsl,mpc8540-pcix + - const: fsl,mpc8540-pci + + reg: + minItems: 1 + items: + - description: internal registers + - description: config space access registers + + clock-frequency: true + + interrupts: + items: + - description: Consolidated PCI interrupt + + fsl,pci-agent-force-enum: + type: boolean + description: + Typically any Freescale PCI-X bridge hardware strapped into Agent mode is + prevented from enumerating the bus. The PrPMC form-factor requires all + mezzanines to be PCI-X Agents, but one per system may still enumerate the + bus. + + This property allows a PCI-X bridge to be used for bus enumeration + despite being strapped into Agent mode. + +required: + - reg + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + + pcie@e0009000 { + compatible = "fsl,mpc8315-pcie", "fsl,mpc8314-pcie"; + reg = <0xe0009000 0x00001000>; + ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 + 0x01000000 0 0x00000000 0xb1000000 0 0x00800000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + bus-range = <0 255>; + interrupt-map-mask = <0xf800 0 0 7>; + interrupt-map = <0 0 0 1 &ipic 1 IRQ_TYPE_LEVEL_LOW + 0 0 0 2 &ipic 1 IRQ_TYPE_LEVEL_LOW + 0 0 0 3 &ipic 1 IRQ_TYPE_LEVEL_LOW + 0 0 0 4 &ipic 1 IRQ_TYPE_LEVEL_LOW>; + clock-frequency = <0>; + }; + + - | + pci@ef008000 { + compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; + reg = <0xef008000 0x1000>; + ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000 + 0x01000000 0 0x00000000 0xd0000000 0 0x01000000>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + device_type = "pci"; + clock-frequency = <33333333>; + interrupt-map-mask = <0xf800 0x0 0x0 0x7>; + interrupt-map = ; + interrupts-extended = <&mpic 24 2>; + bus-range = <0 0>; + fsl,pci-agent-force-enum; + }; + +... diff --git a/Bindings/pci/fsl,pci.txt b/Bindings/pci/fsl,pci.txt deleted file mode 100644 index d8ac4a768e7..00000000000 --- a/Bindings/pci/fsl,pci.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Bus Enumeration by Freescale PCI-X Agent - -Typically any Freescale PCI-X bridge hardware strapped into Agent mode -is prevented from enumerating the bus. The PrPMC form-factor requires -all mezzanines to be PCI-X Agents, but one per system may still -enumerate the bus. - -The property defined below will allow a PCI-X bridge to be used for bus -enumeration despite being strapped into Agent mode. - -Required properties: -- fsl,pci-agent-force-enum : There is no value associated with this - property. The property itself is treated as a boolean. - -Example: - - /* PCI-X bridge known to be PrPMC Monarch */ - pci0: pci@ef008000 { - fsl,pci-agent-force-enum; - #interrupt-cells = <1>; - #size-cells = <2>; - #address-cells = <3>; - compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; - device_type = "pci"; - ... - ... - }; diff --git a/Bindings/pci/mediatek-pcie-gen3.yaml b/Bindings/pci/mediatek-pcie-gen3.yaml index f05aab2b1ad..162406e0691 100644 --- a/Bindings/pci/mediatek-pcie-gen3.yaml +++ b/Bindings/pci/mediatek-pcie-gen3.yaml @@ -109,6 +109,17 @@ properties: power-domains: maxItems: 1 + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + '#interrupt-cells': const: 1 @@ -168,6 +179,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: @@ -197,6 +210,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: @@ -224,6 +239,8 @@ allOf: minItems: 1 maxItems: 2 + mediatek,pbus-csr: false + - if: properties: compatible: diff --git a/Bindings/pci/pci-ep-bus.yaml b/Bindings/pci/pci-ep-bus.yaml new file mode 100644 index 00000000000..a2cd7905f5b --- /dev/null +++ b/Bindings/pci/pci-ep-bus.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/pci-ep-bus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common Properties for PCI MFD EP with Peripherals Addressable from BARs + +maintainers: + - A. della Porta + +description: + Define a generic node representing a PCI endpoint which contains several sub- + peripherals. The peripherals can be accessed through one or more BARs. + This common schema is intended to be referenced from device tree bindings and + does not represent a device tree binding by itself. + +properties: + '#address-cells': + const: 3 + + '#size-cells': + const: 2 + + ranges: + minItems: 1 + maxItems: 6 + items: + maxItems: 8 + additionalItems: true + items: + - maximum: 5 # The BAR number + - const: 0 + - const: 0 + +patternProperties: + '^pci-ep-bus@[0-5]$': + type: object + description: + One node for each BAR used by peripherals contained in the PCI endpoint. + Each node represents a bus on which peripherals are connected. + This allows for some segmentation, e.g., one peripheral is accessible + through BAR0 and another through BAR1, and you don't want the two + peripherals to be able to act on the other BAR. Alternatively, when + different peripherals need to share BARs, you can define only one node + and use a 'ranges' property to map all the used BARs. + + additionalProperties: true + + properties: + compatible: + const: simple-bus + + required: + - compatible + +additionalProperties: true +... diff --git a/Bindings/pci/qcom,pcie-ep.yaml b/Bindings/pci/qcom,pcie-ep.yaml index 1226ee5d08d..ac3414203d3 100644 --- a/Bindings/pci/qcom,pcie-ep.yaml +++ b/Bindings/pci/qcom,pcie-ep.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - qcom,sa8775p-pcie-ep + - qcom,sar2130p-pcie-ep - qcom,sdx55-pcie-ep - qcom,sm8450-pcie-ep - items: @@ -44,11 +45,11 @@ properties: clocks: minItems: 5 - maxItems: 8 + maxItems: 9 clock-names: minItems: 5 - maxItems: 8 + maxItems: 9 qcom,perst-regs: description: Reference to a syscon representing TCSR followed by the two @@ -75,6 +76,9 @@ properties: - const: doorbell - const: dma + iommus: + maxItems: 1 + reset-gpios: description: GPIO used as PERST# input signal maxItems: 1 @@ -91,6 +95,8 @@ properties: - const: pcie-mem - const: cpu-pcie + dma-coherent: true + resets: maxItems: 1 @@ -126,6 +132,38 @@ required: allOf: - $ref: pci-ep.yaml# + + - if: + properties: + compatible: + contains: + enum: + - qcom,sar2130p-pcie-ep + then: + properties: + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + - description: PCIe DDRSS SF TBU clock + - description: PCIe AGGRE NOC AXI clock + - description: PCIe CFG NOC AXI clock + - description: PCIe QMIP AHB clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + - const: ddrss_sf_tbu + - const: aggre_noc_axi + - const: cnoc_sf_axi + - const: qmip_pcie_ahb + - if: properties: compatible: @@ -135,9 +173,43 @@ allOf: then: properties: reg: + minItems: 6 maxItems: 6 reg-names: + minItems: 6 maxItems: 6 + interrupts: + minItems: 2 + maxItems: 2 + interrupt-names: + minItems: 2 + maxItems: 2 + iommus: false + else: + properties: + reg: + minItems: 7 + maxItems: 7 + reg-names: + minItems: 7 + maxItems: 7 + interrupts: + minItems: 3 + maxItems: 3 + interrupt-names: + minItems: 3 + maxItems: 3 + required: + - iommus + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdx55-pcie-ep + then: + properties: clocks: items: - description: PCIe Auxiliary clock @@ -156,10 +228,6 @@ allOf: - const: slave_q2a - const: sleep - const: ref - interrupts: - maxItems: 2 - interrupt-names: - maxItems: 2 - if: properties: @@ -169,10 +237,6 @@ allOf: - qcom,sm8450-pcie-ep then: properties: - reg: - maxItems: 6 - reg-names: - maxItems: 6 clocks: items: - description: PCIe Auxiliary clock @@ -193,10 +257,6 @@ allOf: - const: ref - const: ddrss_sf_tbu - const: aggre_noc_axi - interrupts: - maxItems: 2 - interrupt-names: - maxItems: 2 - if: properties: @@ -206,12 +266,6 @@ allOf: - qcom,sa8775p-pcie-ep then: properties: - reg: - minItems: 7 - maxItems: 7 - reg-names: - minItems: 7 - maxItems: 7 clocks: items: - description: PCIe Auxiliary clock @@ -226,12 +280,6 @@ allOf: - const: bus_master - const: bus_slave - const: slave_q2a - interrupts: - minItems: 3 - maxItems: 3 - interrupt-names: - minItems: 3 - maxItems: 3 unevaluatedProperties: false diff --git a/Bindings/pci/qcom,pcie.yaml b/Bindings/pci/qcom,pcie.yaml index 7235d6554cf..8f628939209 100644 --- a/Bindings/pci/qcom,pcie.yaml +++ b/Bindings/pci/qcom,pcie.yaml @@ -33,6 +33,7 @@ properties: - qcom,pcie-sdx55 - items: - enum: + - qcom,pcie-ipq5332 - qcom,pcie-ipq5424 - const: qcom,pcie-ipq9574 - items: @@ -49,11 +50,11 @@ properties: interrupts: minItems: 1 - maxItems: 8 + maxItems: 9 interrupt-names: minItems: 1 - maxItems: 8 + maxItems: 9 iommu-map: minItems: 1 @@ -443,6 +444,7 @@ allOf: interrupts: minItems: 8 interrupt-names: + minItems: 8 items: - const: msi0 - const: msi1 @@ -452,6 +454,7 @@ allOf: - const: msi5 - const: msi6 - const: msi7 + - const: global - if: properties: @@ -599,6 +602,7 @@ allOf: - properties: interrupts: minItems: 8 + maxItems: 8 interrupt-names: items: - const: msi0 diff --git a/Bindings/pci/snps,dw-pcie.yaml b/Bindings/pci/snps,dw-pcie.yaml index 205326fb2d7..1117a86fb6f 100644 --- a/Bindings/pci/snps,dw-pcie.yaml +++ b/Bindings/pci/snps,dw-pcie.yaml @@ -113,6 +113,8 @@ properties: enum: [ smu, mpu ] - description: Tegra234 aperture enum: [ ecam ] + - description: AMD MDB PCIe SLCR region + const: slcr allOf: - contains: const: dbi diff --git a/Bindings/pci/xilinx-versal-cpm.yaml b/Bindings/pci/xilinx-versal-cpm.yaml index b63a759ec2d..d674a24c8cc 100644 --- a/Bindings/pci/xilinx-versal-cpm.yaml +++ b/Bindings/pci/xilinx-versal-cpm.yaml @@ -18,6 +18,7 @@ properties: - xlnx,versal-cpm-host-1.00 - xlnx,versal-cpm5-host - xlnx,versal-cpm5-host1 + - xlnx,versal-cpm5nc-host reg: items: diff --git a/Bindings/phy/allwinner,sun50i-a64-usb-phy.yaml b/Bindings/phy/allwinner,sun50i-a64-usb-phy.yaml index 21209126ed0..580c3296a18 100644 --- a/Bindings/phy/allwinner,sun50i-a64-usb-phy.yaml +++ b/Bindings/phy/allwinner,sun50i-a64-usb-phy.yaml @@ -20,7 +20,9 @@ properties: - allwinner,sun20i-d1-usb-phy - allwinner,sun50i-a64-usb-phy - items: - - const: allwinner,sun50i-a100-usb-phy + - enum: + - allwinner,sun50i-a100-usb-phy + - allwinner,sun55i-a523-usb-phy - const: allwinner,sun20i-d1-usb-phy reg: diff --git a/Bindings/phy/phy-rockchip-naneng-combphy.yaml b/Bindings/phy/phy-rockchip-naneng-combphy.yaml index 1b3de6678c0..888e6b2aac5 100644 --- a/Bindings/phy/phy-rockchip-naneng-combphy.yaml +++ b/Bindings/phy/phy-rockchip-naneng-combphy.yaml @@ -12,6 +12,7 @@ maintainers: properties: compatible: enum: + - rockchip,rk3562-naneng-combphy - rockchip,rk3568-naneng-combphy - rockchip,rk3576-naneng-combphy - rockchip,rk3588-naneng-combphy diff --git a/Bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml b/Bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml new file mode 100644 index 00000000000..e39168d55d2 --- /dev/null +++ b/Bindings/phy/qcom,ipq5332-uniphy-pcie-phy.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-uniphy-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm UNIPHY PCIe 28LP PHY + +maintainers: + - Nitheesh Sekar + - Varadarajan Narayanan + +description: + PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC + +properties: + compatible: + enum: + - qcom,ipq5332-uniphy-pcie-phy + + reg: + maxItems: 1 + + clocks: + items: + - description: pcie pipe clock + - description: pcie ahb clock + + resets: + items: + - description: phy reset + - description: ahb reset + - description: cfg reset + + "#phy-cells": + const: 0 + + "#clock-cells": + const: 0 + + num-lanes: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + +required: + - compatible + - reg + - clocks + - resets + - "#phy-cells" + - "#clock-cells" + - num-lanes + +additionalProperties: false + +examples: + - | + #include + + pcie0_phy: phy@4b0000 { + compatible = "qcom,ipq5332-uniphy-pcie-phy"; + reg = <0x004b0000 0x800>; + + clocks = <&gcc GCC_PCIE3X1_0_PIPE_CLK>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK>; + + resets = <&gcc GCC_PCIE3X1_0_PHY_BCR>, + <&gcc GCC_PCIE3X1_PHY_AHB_CLK_ARES>, + <&gcc GCC_PCIE3X1_0_PHY_PHY_BCR>; + + #clock-cells = <0>; + + #phy-cells = <0>; + + num-lanes = <1>; + }; diff --git a/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 89391649e0b..2c6c9296e4c 100644 --- a/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - qcom,qcs615-qmp-gen3x1-pcie-phy + - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy - qcom,sar2130p-qmp-gen3x2-pcie-phy @@ -45,6 +46,7 @@ properties: - qcom,x1e80100-qmp-gen4x2-pcie-phy - qcom,x1e80100-qmp-gen4x4-pcie-phy - qcom,x1e80100-qmp-gen4x8-pcie-phy + - qcom,x1p42100-qmp-gen4x4-pcie-phy reg: minItems: 1 @@ -124,6 +126,7 @@ allOf: enum: - qcom,sc8280xp-qmp-gen3x4-pcie-phy - qcom,x1e80100-qmp-gen4x4-pcie-phy + - qcom,x1p42100-qmp-gen4x4-pcie-phy then: properties: reg: @@ -180,6 +183,7 @@ allOf: - qcom,x1e80100-qmp-gen4x2-pcie-phy - qcom,x1e80100-qmp-gen4x4-pcie-phy - qcom,x1e80100-qmp-gen4x8-pcie-phy + - qcom,x1p42100-qmp-gen4x4-pcie-phy then: properties: clocks: @@ -192,6 +196,7 @@ allOf: compatible: contains: enum: + - qcom,qcs8300-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x2-pcie-phy - qcom,sa8775p-qmp-gen4x4-pcie-phy then: @@ -217,12 +222,6 @@ allOf: minItems: 2 reset-names: minItems: 2 - else: - properties: - resets: - maxItems: 1 - reset-names: - maxItems: 1 - if: properties: diff --git a/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index 72bed2933b0..a58370a6a5d 100644 --- a/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -44,6 +44,7 @@ properties: - qcom,sm8475-qmp-ufs-phy - qcom,sm8550-qmp-ufs-phy - qcom,sm8650-qmp-ufs-phy + - qcom,sm8750-qmp-ufs-phy reg: maxItems: 1 @@ -111,6 +112,7 @@ allOf: - qcom,sm8475-qmp-ufs-phy - qcom,sm8550-qmp-ufs-phy - qcom,sm8650-qmp-ufs-phy + - qcom,sm8750-qmp-ufs-phy then: properties: clocks: diff --git a/Bindings/phy/rockchip,rk3588-hdptx-phy.yaml b/Bindings/phy/rockchip,rk3588-hdptx-phy.yaml index 84fe59dbcf4..7a307f45cde 100644 --- a/Bindings/phy/rockchip,rk3588-hdptx-phy.yaml +++ b/Bindings/phy/rockchip,rk3588-hdptx-phy.yaml @@ -11,8 +11,13 @@ maintainers: properties: compatible: - enum: - - rockchip,rk3588-hdptx-phy + oneOf: + - enum: + - rockchip,rk3588-hdptx-phy + - items: + - enum: + - rockchip,rk3576-hdptx-phy + - const: rockchip,rk3588-hdptx-phy reg: maxItems: 1 @@ -34,24 +39,12 @@ properties: const: 0 resets: - items: - - description: PHY reset line - - description: APB reset line - - description: INIT reset line - - description: CMN reset line - - description: LANE reset line - - description: ROPLL reset line - - description: LCPLL reset line + minItems: 4 + maxItems: 7 reset-names: - items: - - const: phy - - const: apb - - const: init - - const: cmn - - const: lane - - const: ropll - - const: lcpll + minItems: 4 + maxItems: 7 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle @@ -67,6 +60,39 @@ required: - reset-names - rockchip,grf +allOf: + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3576-hdptx-phy + then: + properties: + resets: + minItems: 4 + maxItems: 4 + reset-names: + items: + - const: apb + - const: init + - const: cmn + - const: lane + else: + properties: + resets: + minItems: 7 + maxItems: 7 + reset-names: + items: + - const: phy + - const: apb + - const: init + - const: cmn + - const: lane + - const: ropll + - const: lcpll + additionalProperties: false examples: diff --git a/Bindings/phy/rockchip,rk3588-mipi-dcphy.yaml b/Bindings/phy/rockchip,rk3588-mipi-dcphy.yaml new file mode 100644 index 00000000000..c8ff5ba22a8 --- /dev/null +++ b/Bindings/phy/rockchip,rk3588-mipi-dcphy.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3588-mipi-dcphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip MIPI D-/C-PHY with Samsung IP block + +maintainers: + - Guochun Huang + - Heiko Stuebner + +properties: + compatible: + enum: + - rockchip,rk3576-mipi-dcphy + - rockchip,rk3588-mipi-dcphy + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + description: | + Argument is mode to operate in. Supported modes are: + - PHY_TYPE_DPHY + - PHY_TYPE_CPHY + See include/dt-bindings/phy/phy.h for constants. + + clocks: + maxItems: 2 + + clock-names: + items: + - const: pclk + - const: ref + + resets: + maxItems: 4 + + reset-names: + items: + - const: m_phy + - const: apb + - const: grf + - const: s_phy + + rockchip,grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon managing the 'mipi dcphy general register files'. + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + phy@feda0000 { + compatible = "rockchip,rk3588-mipi-dcphy"; + reg = <0x0 0xfeda0000 0x0 0x10000>; + clocks = <&cru PCLK_MIPI_DCPHY0>, + <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; + clock-names = "pclk", "ref"; + resets = <&cru SRST_M_MIPI_DCPHY0>, + <&cru SRST_P_MIPI_DCPHY0>, + <&cru SRST_P_MIPI_DCPHY0_GRF>, + <&cru SRST_S_MIPI_DCPHY0>; + reset-names = "m_phy", "apb", "grf", "s_phy"; + rockchip,grf = <&mipidcphy0_grf>; + #phy-cells = <1>; + }; + }; diff --git a/Bindings/phy/samsung,ufs-phy.yaml b/Bindings/phy/samsung,ufs-phy.yaml index f402e31bf58..d70ffeb6e82 100644 --- a/Bindings/phy/samsung,ufs-phy.yaml +++ b/Bindings/phy/samsung,ufs-phy.yaml @@ -18,6 +18,7 @@ properties: - google,gs101-ufs-phy - samsung,exynos7-ufs-phy - samsung,exynosautov9-ufs-phy + - samsung,exynosautov920-ufs-phy - tesla,fsd-ufs-phy reg: diff --git a/Bindings/phy/samsung,usb3-drd-phy.yaml b/Bindings/phy/samsung,usb3-drd-phy.yaml index 16321cdd491..27295acbba7 100644 --- a/Bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Bindings/phy/samsung,usb3-drd-phy.yaml @@ -83,14 +83,19 @@ properties: pll-supply: description: Power supply for the USB PLL. + dvdd-usb20-supply: description: DVDD power supply for the USB 2.0 phy. + vddh-usb20-supply: description: VDDh power supply for the USB 2.0 phy. + vdd33-usb20-supply: description: 3.3V power supply for the USB 2.0 phy. + vdda-usbdp-supply: description: VDDa power supply for the USB DP phy. + vddh-usbdp-supply: description: VDDh power supply for the USB DP phy. @@ -109,6 +114,8 @@ allOf: contains: const: google,gs101-usb31drd-phy then: + $ref: /schemas/usb/usb-switch.yaml# + properties: clocks: items: @@ -117,6 +124,7 @@ allOf: - description: Gate of control interface AXI clock - description: Gate of control interface APB clock - description: Gate of SCL APB clock + clock-names: items: - const: phy @@ -124,12 +132,17 @@ allOf: - const: ctrl_aclk - const: ctrl_pclk - const: scl_pclk + reg: minItems: 3 + reg-names: minItems: 3 + required: - reg-names + - orientation-switch + - port - pll-supply - dvdd-usb20-supply - vddh-usb20-supply @@ -149,6 +162,7 @@ allOf: clocks: minItems: 5 maxItems: 5 + clock-names: items: - const: phy @@ -156,8 +170,10 @@ allOf: - const: phy_utmi - const: phy_pipe - const: itp + reg: maxItems: 1 + reg-names: maxItems: 1 @@ -174,16 +190,19 @@ allOf: clocks: minItems: 2 maxItems: 2 + clock-names: items: - const: phy - const: ref + reg: maxItems: 1 + reg-names: maxItems: 1 -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Bindings/pinctrl/airoha,en7581-pinctrl.yaml b/Bindings/pinctrl/airoha,en7581-pinctrl.yaml index b2601d698dc..21fd4f1ba78 100644 --- a/Bindings/pinctrl/airoha,en7581-pinctrl.yaml +++ b/Bindings/pinctrl/airoha,en7581-pinctrl.yaml @@ -24,6 +24,9 @@ properties: '#gpio-cells': const: 2 + gpio-ranges: + maxItems: 1 + interrupt-controller: true '#interrupt-cells': diff --git a/Bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml b/Bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml new file mode 100644 index 00000000000..154e03da8ce --- /dev/null +++ b/Bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml @@ -0,0 +1,175 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/allwinner,sun55i-a523-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A523 Pin Controller + +maintainers: + - Andre Przywara + +properties: + "#gpio-cells": + const: 3 + description: + GPIO consumers must use three arguments, first the number of the + bank, then the pin number inside that bank, and finally the GPIO + flags. + + "#interrupt-cells": + const: 3 + description: + Interrupts consumers must use three arguments, first the number + of the bank, then the pin number inside that bank, and finally + the interrupts flags. + + compatible: + enum: + - allwinner,sun55i-a523-pinctrl + - allwinner,sun55i-a523-r-pinctrl + + reg: + maxItems: 1 + + interrupts: + minItems: 2 + maxItems: 10 + description: + One interrupt per external interrupt bank supported on the + controller, sorted by bank number ascending order. + + clocks: + items: + - description: Bus Clock + - description: High Frequency Oscillator + - description: Low Frequency Oscillator + + clock-names: + items: + - const: apb + - const: hosc + - const: losc + + gpio-controller: true + interrupt-controller: true + gpio-line-names: true + + input-debounce: + description: + Debouncing periods in microseconds, one period per interrupt + bank found in the controller + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 10 + +patternProperties: + # It's pretty scary, but the basic idea is that: + # - One node name can start with either s- or r- for PRCM nodes, + # - Then, the name itself can be any repetition of - (to + # accommodate with nodes like uart4-rts-cts-pins), where each + # string can be either starting with 'p' but in a string longer + # than 3, or something that doesn't start with 'p', + # - Then, the bank name is optional and will be between pa and pm. + # Some pins groups that have several options will have the pin + # numbers then, + # - Finally, the name will end with either -pin or pins. + + "^([rs]-)?(([a-z0-9]{3,}|[a-oq-z][a-z0-9]*?)?-)+?(p[a-m][0-9]*?-)??pins?$": + type: object + + properties: + pins: true + function: true + bias-disable: true + bias-pull-up: true + bias-pull-down: true + + drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [10, 20, 30, 40] + + allwinner,pinmux: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Pinmux selector value, for each pin. Almost every time this value + is the same for all pins, so any array shorter than the number of + pins will repeat the last value, to allow just specifying a single + cell, for all cells. + + required: + - pins + - allwinner,pinmux + - function + + additionalProperties: false + + "^vcc-p[a-m]-supply$": + description: + Power supplies for pin banks. + +required: + - "#gpio-cells" + - compatible + - reg + - clocks + - clock-names + - gpio-controller + - "#interrupt-cells" + - interrupts + - interrupt-controller + +allOf: + - $ref: pinctrl.yaml# + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-pinctrl + + then: + properties: + interrupts: + minItems: 10 + maxItems: 10 + + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-r-pinctrl + + then: + properties: + interrupts: + minItems: 2 + maxItems: 2 + +additionalProperties: false + +examples: + - | + r_pio: pinctrl@7022000 { + compatible = "allwinner,sun55i-a523-r-pinctrl"; + reg = <0x7022000 0x800>; + interrupts = <0 159 4>, <0 161 4>; + clocks = <&r_ccu 1>, <&osc24M>, <&osc32k>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + + r_i2c_pins: r-i2c-pins { + pins = "PL0", "PL1"; + allwinner,pinmux = <2>; + function = "r_i2c0"; + bias-pull-up; + }; + + r_spi_pins: r-spi-pins { + pins = "PL11" ,"PL12", "PL13"; + allwinner,pinmux = <6>; + function = "r_spi"; + }; + }; diff --git a/Bindings/pinctrl/amlogic,pinctrl-a4.yaml b/Bindings/pinctrl/amlogic,pinctrl-a4.yaml new file mode 100644 index 00000000000..8eb50cad61d --- /dev/null +++ b/Bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -0,0 +1,126 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/amlogic,pinctrl-a4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic pinmux controller + +maintainers: + - Xianwei Zhao + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + const: amlogic,pinctrl-a4 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + +patternProperties: + "^gpio@[0-9a-f]+$": + type: object + + additionalProperties: false + properties: + reg: + minItems: 1 + items: + - description: pin config register + - description: pin mux setting register (some special pin fixed function) + - description: pin drive strength register (optional) + + reg-names: + minItems: 1 + items: + - const: gpio + - const: mux + - const: ds + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + maxItems: 1 + + required: + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + + "^func-[0-9a-z-]+$": + type: object + additionalProperties: false + patternProperties: + "^group-[0-9a-z-]+$": + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml + - $ref: /schemas/pinctrl/pinmux-node.yaml + + required: + - pinmux + +required: + - compatible + - "#address-cells" + - "#size-cells" + - ranges + +additionalProperties: false + +examples: + - | + #include + apb { + #address-cells = <2>; + #size-cells = <2>; + periphs_pinctrl: pinctrl { + compatible = "amlogic,pinctrl-a4"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio@4240 { + reg = <0 0x4240 0 0x40>, <0 0x4000 0 0x8>; + reg-names = "gpio", "mux"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 8 10>; + }; + + func-uart-b { + group-default { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + + group-pins1 { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + + func-uart-c { + group-default { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <4000>; + }; + }; + }; + }; diff --git a/Bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/Bindings/pinctrl/atmel,at91-pio4-pinctrl.txt index 774c3c269c4..81a05a09f19 100644 --- a/Bindings/pinctrl/atmel,at91-pio4-pinctrl.txt +++ b/Bindings/pinctrl/atmel,at91-pio4-pinctrl.txt @@ -6,6 +6,7 @@ configure it. Required properties: - compatible: "atmel,sama5d2-pinctrl" + "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl" "microchip,sama7g5-pinctrl" - reg: base address and length of the PIO controller. - interrupts: interrupt outputs from the controller, one for each bank. diff --git a/Bindings/pinctrl/brcm,bcm21664-pinctrl.yaml b/Bindings/pinctrl/brcm,bcm21664-pinctrl.yaml new file mode 100644 index 00000000000..1283a588416 --- /dev/null +++ b/Bindings/pinctrl/brcm,bcm21664-pinctrl.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm21664-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM21664 pin controller + +maintainers: + - Florian Fainelli + - Ray Jui + - Scott Branden + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + const: brcm,bcm21664-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-pins$': + type: object + additionalProperties: false + + patternProperties: + '-grp[0-9]$': + type: object + + properties: + pins: + description: + Specifies the name(s) of one or more pins to be configured by + this node. + items: + enum: [ adcsyn, batrm, bsc1clk, bsc1dat, camcs0, camcs1, clk32k, + clk_cx8, dclk1, dclk4, dclkreq1, dclkreq4, dmic0clk, + dmic0dq, dsi0te, gpio00, gpio01, gpio02, gpio03, gpio04, + gpio05, gpio06, gpio07, gpio08, gpio09, gpio10, gpio11, + gpio12, gpio13, gpio14, gpio15, gpio16, gpio17, gpio18, + gpio19, gpio20, gpio21, gpio22, gpio23, gpio24, gpio25, + gpio26, gpio27, gpio28, gpio32, gpio33, gpio34, gpio93, + gpio94, gps_calreq, gps_hostreq, gps_pablank, gps_tmark, + icusbdm, icusbdp, lcdcs0, lcdres, lcdscl, lcdsda, lcdte, + mdmgpio00, mdmgpio01, mdmgpio02, mdmgpio03, mdmgpio04, + mdmgpio05, mdmgpio06, mdmgpio07, mdmgpio08, mmc0ck, + mmc0cmd, mmc0dat0, mmc0dat1, mmc0dat2, mmc0dat3, mmc0dat4, + mmc0dat5, mmc0dat6, mmc0dat7, mmc0rst, mmc1ck, mmc1cmd, + mmc1dat0, mmc1dat1, mmc1dat2, mmc1dat3, mmc1dat4, + mmc1dat5, mmc1dat6, mmc1dat7, mmc1rst, pc1, pc2, pmbscclk, + pmbscdat, pmuint, resetn, rfst2g_mtsloten3g, + rtxdata2g_txdata3g1, rtxen2g_txdata3g2, rxdata3g0, + rxdata3g1, rxdata3g2, sdck, sdcmd, sddat0, sddat1, sddat2, + sddat3, simclk, simdat, simdet, simrst, spi0clk, spi0fss, + spi0rxd, spi0txd, sri_c, sri_d, sri_e, sspck, sspdi, + sspdo, sspsyn, stat1, stat2, swclktck, swdiotms, sysclken, + tdi, tdo, testmode, traceclk, tracedt00, tracedt01, + tracedt02, tracedt03, tracedt04, tracedt05, tracedt06, + tracedt07, tracedt08, tracedt09, tracedt10, tracedt11, + tracedt12, tracedt13, tracedt14, tracedt15, trstb, + txdata3g0, ubctsn, ubrtsn, ubrx, ubtx ] + + function: + description: + Specifies the pin mux selection. + enum: [ alt1, alt2, alt3, alt4, alt5, alt6 ] + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + slew-rate: + description: | + Meaning depends on configured pin mux: + bsc*clk/pmbscclk or bsc*dat/pmbscdat or gpio16/gpio17: + 0: Standard (100 kbps) & Fast (400 kbps) mode + 1: Highspeed (3.4 Mbps) mode + Otherwise: + 0: fast slew rate + 1: normal slew rate + + drive-strength: + enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ] + + input-enable: true + input-disable: true + + input-schmitt-enable: true + input-schmitt-disable: true + + required: + - pins + + additionalProperties: false + + allOf: + - $ref: pincfg-node.yaml# + # Limitations for I2C pins + - if: + properties: + pins: + contains: + enum: [ bsc1clk, bsc1dat, gpio16, gpio17, pmbscclk, + pmbscdat ] + then: + properties: + drive-strength: false + bias-pull-down: false + input-schmitt-enable: false + input-schmitt-disable: false + + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pinctrl@35004800 { + compatible = "brcm,bcm21664-pinctrl"; + reg = <0x35004800 0x7f0>; + + dev-a-active-pins { + /* group node defining 1 standard pin */ + std-grp0 { + pins = "gpio00"; + function = "alt1"; + input-schmitt-enable; + bias-disable; + slew-rate = <1>; + drive-strength = <4>; + }; + + /* group node defining 2 I2C pins */ + i2c-grp0 { + pins = "bsc1clk", "bsc1dat"; + function = "alt2"; + bias-pull-up; + input-enable; + }; + }; + }; +... diff --git a/Bindings/pinctrl/ingenic,pinctrl.yaml b/Bindings/pinctrl/ingenic,pinctrl.yaml index 890961826c6..84e960255a3 100644 --- a/Bindings/pinctrl/ingenic,pinctrl.yaml +++ b/Bindings/pinctrl/ingenic,pinctrl.yaml @@ -42,6 +42,7 @@ properties: - ingenic,jz4780-pinctrl - ingenic,x1000-pinctrl - ingenic,x1500-pinctrl + - ingenic,x1600-pinctrl - ingenic,x1830-pinctrl - ingenic,x2000-pinctrl - ingenic,x2100-pinctrl @@ -81,6 +82,7 @@ patternProperties: - ingenic,jz4780-gpio - ingenic,x1000-gpio - ingenic,x1500-gpio + - ingenic,x1600-gpio - ingenic,x1830-gpio - ingenic,x2000-gpio - ingenic,x2100-gpio diff --git a/Bindings/pinctrl/qcom,sa8775p-tlmm.yaml b/Bindings/pinctrl/qcom,sa8775p-tlmm.yaml index 749dbc563ac..7a156b9bfaf 100644 --- a/Bindings/pinctrl/qcom,sa8775p-tlmm.yaml +++ b/Bindings/pinctrl/qcom,sa8775p-tlmm.yaml @@ -79,7 +79,7 @@ $defs: cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot, - edp3_lcd, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3, + edp3_lcd, egpio, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3, emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0, emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio, emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3, diff --git a/Bindings/pinctrl/rockchip,pinctrl.yaml b/Bindings/pinctrl/rockchip,pinctrl.yaml index 80a2b193484..960758dc417 100644 --- a/Bindings/pinctrl/rockchip,pinctrl.yaml +++ b/Bindings/pinctrl/rockchip,pinctrl.yaml @@ -44,6 +44,7 @@ properties: - rockchip,rk3328-pinctrl - rockchip,rk3368-pinctrl - rockchip,rk3399-pinctrl + - rockchip,rk3528-pinctrl - rockchip,rk3562-pinctrl - rockchip,rk3568-pinctrl - rockchip,rk3576-pinctrl diff --git a/Bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 68ed714eb0a..0da6d69f599 100644 --- a/Bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -40,6 +40,7 @@ properties: - items: - enum: - samsung,exynos5433-wakeup-eint + - samsung,exynos7870-wakeup-eint - samsung,exynos7885-wakeup-eint - samsung,exynos850-wakeup-eint - samsung,exynos8895-wakeup-eint @@ -47,6 +48,7 @@ properties: - items: - enum: - google,gs101-wakeup-eint + - samsung,exynos2200-wakeup-eint - samsung,exynos9810-wakeup-eint - samsung,exynos990-wakeup-eint - samsung,exynosautov9-wakeup-eint @@ -104,6 +106,7 @@ allOf: - contains: enum: - samsung,exynos5433-wakeup-eint + - samsung,exynos7870-wakeup-eint - samsung,exynos7885-wakeup-eint - samsung,exynos8895-wakeup-eint then: diff --git a/Bindings/pinctrl/samsung,pinctrl.yaml b/Bindings/pinctrl/samsung,pinctrl.yaml index 5296a9e4faa..de846085614 100644 --- a/Bindings/pinctrl/samsung,pinctrl.yaml +++ b/Bindings/pinctrl/samsung,pinctrl.yaml @@ -42,6 +42,7 @@ properties: - samsung,s3c2450-pinctrl - samsung,s3c64xx-pinctrl - samsung,s5pv210-pinctrl + - samsung,exynos2200-pinctrl - samsung,exynos3250-pinctrl - samsung,exynos4210-pinctrl - samsung,exynos4x12-pinctrl @@ -51,6 +52,7 @@ properties: - samsung,exynos5420-pinctrl - samsung,exynos5433-pinctrl - samsung,exynos7-pinctrl + - samsung,exynos7870-pinctrl - samsung,exynos7885-pinctrl - samsung,exynos850-pinctrl - samsung,exynos8895-pinctrl diff --git a/Bindings/pinctrl/sophgo,sg2042-pinctrl.yaml b/Bindings/pinctrl/sophgo,sg2042-pinctrl.yaml new file mode 100644 index 00000000000..924dfe1404a --- /dev/null +++ b/Bindings/pinctrl/sophgo,sg2042-pinctrl.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/sophgo,sg2042-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 Pin Controller + +maintainers: + - Inochi Amaoto + +properties: + compatible: + enum: + - sophgo,sg2042-pinctrl + - sophgo,sg2044-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-cfg$': + type: object + description: + A pinctrl node should contain at least one subnode representing the + pinctrl groups available on the machine. + + additionalProperties: false + + patternProperties: + '-pins$': + type: object + description: | + Each subnode will list the pins it needs, and how they should + be configured, with regard to muxer configuration, bias input + enable/disable, input schmitt trigger enable, drive strength + output enable/disable state. For configuration detail, + refer to https://github.com/sophgo/sophgo-doc/. + + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + properties: + pinmux: + description: | + The list of GPIOs and their mux settings that properties in the + node apply to. This should be set using the PINMUX macro. + + bias-disable: true + + bias-pull-up: + type: boolean + + bias-pull-down: + type: boolean + + drive-strength-microamp: + description: typical current when output low level. + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: sophgo,sg2042-pinctrl + then: + patternProperties: + '-cfg$': + patternProperties: + '-pins$': + properties: + drive-strength-microamp: + enum: [ 5400, 8100, 10700, 13400, + 16100, 18800, 21400, 24100, + 26800, 29400, 32100, 34800, + 37400, 40100, 42800, 45400 ] + + - if: + properties: + compatible: + contains: + const: sophgo,sg2044-pinctrl + then: + patternProperties: + '-cfg$': + patternProperties: + '-pins$': + properties: + drive-strength-microamp: + enum: [ 3200, 6400, 9600, 12700, + 15900, 19100, 22200, 25300, + 29500, 32700, 35900, 39000, + 42000, 45200, 48300, 51400] + +additionalProperties: false + +examples: + - | + #include + + pinctrl@30011000 { + compatible = "sophgo,sg2042-pinctrl"; + reg = <30011000 0x1000>; + + uart0_cfg: uart0-cfg { + uart0-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <13400>; + }; + }; + }; + +... diff --git a/Bindings/platform/huawei,gaokun-ec.yaml b/Bindings/platform/huawei,gaokun-ec.yaml new file mode 100644 index 00000000000..4a03b0ee314 --- /dev/null +++ b/Bindings/platform/huawei,gaokun-ec.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/platform/huawei,gaokun-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Huawei Matebook E Go Embedded Controller + +maintainers: + - Pengyu Luo + +description: + Different from other Qualcomm Snapdragon sc8180x and sc8280xp-based + machines, the Huawei Matebook E Go tablets use embedded controllers + while others use a system called PMIC GLink which handles battery, + UCSI, USB Type-C DP Alt Mode. In addition, Huawei's implementation + also handles additional features, such as charging thresholds, FN + lock, smart charging, tablet lid status, thermal sensors, and more. + +properties: + compatible: + enum: + - huawei,gaokun3-ec + + reg: + const: 0x38 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + interrupts: + maxItems: 1 + +patternProperties: + '^connector@[01]$': + $ref: /schemas/connector/usb-connector.yaml# + + properties: + reg: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@38 { + compatible = "huawei,gaokun3-ec"; + reg = <0x38>; + + interrupts-extended = <&tlmm 107 IRQ_TYPE_LEVEL_LOW>; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ucsi0_ss_in: endpoint { + remote-endpoint = <&usb_0_qmpphy_out>; + }; + }; + + port@1 { + reg = <1>; + + ucsi0_sbu: endpoint { + remote-endpoint = <&usb0_sbu_mux>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ucsi1_ss_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + + port@1 { + reg = <1>; + + ucsi1_sbu: endpoint { + remote-endpoint = <&usb1_sbu_mux>; + }; + }; + }; + }; + }; + }; diff --git a/Bindings/power/allwinner,sun20i-d1-ppu.yaml b/Bindings/power/allwinner,sun20i-d1-ppu.yaml index 46e2647a5d7..f578be6a3bc 100644 --- a/Bindings/power/allwinner,sun20i-d1-ppu.yaml +++ b/Bindings/power/allwinner,sun20i-d1-ppu.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - allwinner,sun20i-d1-ppu + - allwinner,sun8i-v853-ppu reg: maxItems: 1 diff --git a/Bindings/power/apple,pmgr-pwrstate.yaml b/Bindings/power/apple,pmgr-pwrstate.yaml index 59a6af735a2..6e9a670eaf5 100644 --- a/Bindings/power/apple,pmgr-pwrstate.yaml +++ b/Bindings/power/apple,pmgr-pwrstate.yaml @@ -31,6 +31,11 @@ properties: compatible: items: - enum: + - apple,s5l8960x-pmgr-pwrstate + - apple,t7000-pmgr-pwrstate + - apple,s8000-pmgr-pwrstate + - apple,t8010-pmgr-pwrstate + - apple,t8015-pmgr-pwrstate - apple,t8103-pmgr-pwrstate - apple,t8112-pmgr-pwrstate - apple,t6000-pmgr-pwrstate diff --git a/Bindings/power/qcom,kpss-acc-v2.yaml b/Bindings/power/qcom,kpss-acc-v2.yaml index 202a5d51ee8..3fa77fe14c8 100644 --- a/Bindings/power/qcom,kpss-acc-v2.yaml +++ b/Bindings/power/qcom,kpss-acc-v2.yaml @@ -18,7 +18,9 @@ description: properties: compatible: - const: qcom,kpss-acc-v2 + enum: + - qcom,kpss-acc-v2 + - qcom,msm8916-acc reg: items: diff --git a/Bindings/power/reset/atmel,sama5d2-shdwc.yaml b/Bindings/power/reset/atmel,sama5d2-shdwc.yaml index 0735ceb7c10..9c34249b2d6 100644 --- a/Bindings/power/reset/atmel,sama5d2-shdwc.yaml +++ b/Bindings/power/reset/atmel,sama5d2-shdwc.yaml @@ -16,6 +16,11 @@ description: | properties: compatible: oneOf: + - items: + - enum: + - microchip,sama7d65-shdwc + - const: microchip,sama7g5-shdwc + - const: syscon - items: - const: microchip,sama7g5-shdwc - const: syscon diff --git a/Bindings/power/reset/xlnx,zynqmp-power.yaml b/Bindings/power/reset/xlnx,zynqmp-power.yaml index 79983163619..079ad977b90 100644 --- a/Bindings/power/reset/xlnx,zynqmp-power.yaml +++ b/Bindings/power/reset/xlnx,zynqmp-power.yaml @@ -46,7 +46,6 @@ properties: required: - compatible - - interrupts additionalProperties: false diff --git a/Bindings/power/rockchip,power-controller.yaml b/Bindings/power/rockchip,power-controller.yaml index 650dc0aae6f..ebab98987e4 100644 --- a/Bindings/power/rockchip,power-controller.yaml +++ b/Bindings/power/rockchip,power-controller.yaml @@ -132,6 +132,9 @@ $defs: A number of phandles to clocks that need to be enabled while power domain switches state. + domain-supply: + description: domain regulator supply. + pm_qos: $ref: /schemas/types.yaml#/definitions/phandle-array items: diff --git a/Bindings/power/supply/maxim,max77705.yaml b/Bindings/power/supply/maxim,max77705.yaml new file mode 100644 index 00000000000..bce7fabbd9d --- /dev/null +++ b/Bindings/power/supply/maxim,max77705.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/supply/maxim,max77705.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX777705 charger + +maintainers: + - Dzmitry Sankouski + +description: | + This is a device tree bindings for charger found in Maxim MAX77705 chip. + +allOf: + - $ref: power-supply.yaml# + +properties: + compatible: + const: maxim,max77705-charger + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - monitored-battery + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + charger@69 { + compatible = "maxim,max77705-charger"; + reg = <0x69>; + monitored-battery = <&battery>; + interrupt-parent = <&pm8998_gpios>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; + }; diff --git a/Bindings/power/supply/x-powers,axp20x-battery-power-supply.yaml b/Bindings/power/supply/x-powers,axp20x-battery-power-supply.yaml index 5ccd375eb29..3504c76a01d 100644 --- a/Bindings/power/supply/x-powers,axp20x-battery-power-supply.yaml +++ b/Bindings/power/supply/x-powers,axp20x-battery-power-supply.yaml @@ -14,9 +14,6 @@ maintainers: - Chen-Yu Tsai - Sebastian Reichel -allOf: - - $ref: power-supply.yaml# - properties: compatible: oneOf: @@ -35,7 +32,24 @@ properties: this gauge. $ref: /schemas/types.yaml#/definitions/phandle + x-powers,no-thermistor: + type: boolean + description: Indicates that no thermistor is connected to the TS pin + required: - compatible +allOf: + - $ref: power-supply.yaml# + - if: + not: + properties: + compatible: + contains: + enum: + - x-powers,axp717-battery-power-supply + then: + properties: + x-powers,no-thermistor: false + additionalProperties: false diff --git a/Bindings/power/wakeup-source.txt b/Bindings/power/wakeup-source.txt index 27f1797be96..66bb016305f 100644 --- a/Bindings/power/wakeup-source.txt +++ b/Bindings/power/wakeup-source.txt @@ -23,7 +23,7 @@ List of legacy properties and respective binding document 1. "gpio-key,wakeup" Documentation/devicetree/bindings/input/gpio-keys{,-polled}.txt 2. "has-tpo" Documentation/devicetree/bindings/rtc/rtc-opal.txt -3. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.txt +3. "linux,wakeup" Documentation/devicetree/bindings/input/gpio-matrix-keypad.yaml Documentation/devicetree/bindings/mfd/tc3589x.txt Documentation/devicetree/bindings/input/touchscreen/ti,ads7843.yaml 4. "linux,keypad-wakeup" Documentation/devicetree/bindings/input/qcom,pm8921-keypad.yaml diff --git a/Bindings/powerpc/fsl/dma.txt b/Bindings/powerpc/fsl/dma.txt deleted file mode 100644 index c11ad5c6db2..00000000000 --- a/Bindings/powerpc/fsl/dma.txt +++ /dev/null @@ -1,204 +0,0 @@ -* Freescale DMA Controllers - -** Freescale Elo DMA Controller - This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx - series chips such as mpc8315, mpc8349, mpc8379 etc. - -Required properties: - -- compatible : must include "fsl,elo-dma" -- reg : DMA General Status Register, i.e. DGSR which contains - status for all the 4 DMA channels -- ranges : describes the mapping between the address space of the - DMA channels and the address space of the DMA controller -- cell-index : controller index. 0 for controller @ 0x8100 -- interrupts : interrupt specifier for DMA IRQ - -- DMA channel nodes: - - compatible : must include "fsl,elo-dma-channel" - However, see note below. - - reg : DMA channel specific registers - - cell-index : DMA channel index starts at 0. - -Optional properties: - - interrupts : interrupt specifier for DMA channel IRQ - (on 83xx this is expected to be identical to - the interrupts property of the parent node) - -Example: - dma@82a8 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc8349-dma", "fsl,elo-dma"; - reg = <0x82a8 4>; - ranges = <0 0x8100 0x1a4>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - cell-index = <0>; - dma-channel@0 { - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; - cell-index = <0>; - reg = <0 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@80 { - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; - cell-index = <1>; - reg = <0x80 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@100 { - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; - cell-index = <2>; - reg = <0x100 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - dma-channel@180 { - compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel"; - cell-index = <3>; - reg = <0x180 0x80>; - interrupt-parent = <&ipic>; - interrupts = <71 8>; - }; - }; - -** Freescale EloPlus DMA Controller - This is a 4-channel DMA controller with extended addresses and chaining, - mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as - mpc8540, mpc8641 p4080, bsc9131 etc. - -Required properties: - -- compatible : must include "fsl,eloplus-dma" -- reg : DMA General Status Register, i.e. DGSR which contains - status for all the 4 DMA channels -- cell-index : controller index. 0 for controller @ 0x21000, - 1 for controller @ 0xc000 -- ranges : describes the mapping between the address space of the - DMA channels and the address space of the DMA controller - -- DMA channel nodes: - - compatible : must include "fsl,eloplus-dma-channel" - However, see note below. - - cell-index : DMA channel index starts at 0. - - reg : DMA channel specific registers - - interrupts : interrupt specifier for DMA channel IRQ - -Example: - dma@21300 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma"; - reg = <0x21300 4>; - ranges = <0 0x21100 0x200>; - cell-index = <0>; - dma-channel@0 { - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; - reg = <0 0x80>; - cell-index = <0>; - interrupt-parent = <&mpic>; - interrupts = <20 2>; - }; - dma-channel@80 { - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; - reg = <0x80 0x80>; - cell-index = <1>; - interrupt-parent = <&mpic>; - interrupts = <21 2>; - }; - dma-channel@100 { - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; - reg = <0x100 0x80>; - cell-index = <2>; - interrupt-parent = <&mpic>; - interrupts = <22 2>; - }; - dma-channel@180 { - compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel"; - reg = <0x180 0x80>; - cell-index = <3>; - interrupt-parent = <&mpic>; - interrupts = <23 2>; - }; - }; - -** Freescale Elo3 DMA Controller - DMA controller which has same function as EloPlus except that Elo3 has 8 - channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx - series chips, such as t1040, t4240, b4860. - -Required properties: - -- compatible : must include "fsl,elo3-dma" -- reg : contains two entries for DMA General Status Registers, - i.e. DGSR0 which includes status for channel 1~4, and - DGSR1 for channel 5~8 -- ranges : describes the mapping between the address space of the - DMA channels and the address space of the DMA controller - -- DMA channel nodes: - - compatible : must include "fsl,eloplus-dma-channel" - - reg : DMA channel specific registers - - interrupts : interrupt specifier for DMA channel IRQ - -Example: -dma@100300 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,elo3-dma"; - reg = <0x100300 0x4>, - <0x100600 0x4>; - ranges = <0x0 0x100100 0x500>; - dma-channel@0 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x0 0x80>; - interrupts = <28 2 0 0>; - }; - dma-channel@80 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x80 0x80>; - interrupts = <29 2 0 0>; - }; - dma-channel@100 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x100 0x80>; - interrupts = <30 2 0 0>; - }; - dma-channel@180 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x180 0x80>; - interrupts = <31 2 0 0>; - }; - dma-channel@300 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x300 0x80>; - interrupts = <76 2 0 0>; - }; - dma-channel@380 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x380 0x80>; - interrupts = <77 2 0 0>; - }; - dma-channel@400 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x400 0x80>; - interrupts = <78 2 0 0>; - }; - dma-channel@480 { - compatible = "fsl,eloplus-dma-channel"; - reg = <0x480 0x80>; - interrupts = <79 2 0 0>; - }; -}; - -Note on DMA channel compatible properties: The compatible property must say -"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA -driver (fsldma). Any DMA channel used by fsldma cannot be used by another -DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA -channel that should be used for another driver should not use -"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for -example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt -for more information. diff --git a/Bindings/powerpc/fsl/mcu-mpc8349emitx.txt b/Bindings/powerpc/fsl/mcu-mpc8349emitx.txt deleted file mode 100644 index 37f91fa5765..00000000000 --- a/Bindings/powerpc/fsl/mcu-mpc8349emitx.txt +++ /dev/null @@ -1,17 +0,0 @@ -Freescale MPC8349E-mITX-compatible Power Management Micro Controller Unit (MCU) - -Required properties: -- compatible : "fsl,-", "fsl,mcu-mpc8349emitx". -- reg : should specify I2C address (0x0a). -- #gpio-cells : should be 2. -- gpio-controller : should be present. - -Example: - -mcu@a { - #gpio-cells = <2>; - compatible = "fsl,mc9s08qg8-mpc8349emitx", - "fsl,mcu-mpc8349emitx"; - reg = <0x0a>; - gpio-controller; -}; diff --git a/Bindings/pps/pps-gpio.yaml b/Bindings/pps/pps-gpio.yaml index fd4adfa8d2d..383a838744e 100644 --- a/Bindings/pps/pps-gpio.yaml +++ b/Bindings/pps/pps-gpio.yaml @@ -36,14 +36,14 @@ additionalProperties: false examples: - | - #include - - pps { - compatible = "pps-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pps>; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - assert-falling-edge; - echo-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; - echo-active-ms = <100>; - }; + #include + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + assert-falling-edge; + echo-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + echo-active-ms = <100>; + }; diff --git a/Bindings/pwm/imx-tpm-pwm.yaml b/Bindings/pwm/imx-tpm-pwm.yaml index ac0a35bf864..d5a9340ff92 100644 --- a/Bindings/pwm/imx-tpm-pwm.yaml +++ b/Bindings/pwm/imx-tpm-pwm.yaml @@ -23,8 +23,15 @@ properties: const: 3 compatible: - enum: - - fsl,imx7ulp-pwm + oneOf: + - enum: + - fsl,imx7ulp-pwm + - items: + - enum: + - fsl,imx93-pwm + - fsl,imx94-pwm + - fsl,imx95-pwm + - const: fsl,imx7ulp-pwm reg: maxItems: 1 diff --git a/Bindings/pwm/pwm-nexus-node.yaml b/Bindings/pwm/pwm-nexus-node.yaml new file mode 100644 index 00000000000..3b40e271fe8 --- /dev/null +++ b/Bindings/pwm/pwm-nexus-node.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/pwm-nexus-node.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: PWM Nexus node properties + +description: > + Platforms can have a standardized connector/expansion slot that exposes PWMs + signals to expansion boards. + + A nexus node allows to remap a phandle list in a consumer node through a + connector node in a generic way. With this remapping, the consumer node needs + to know only about the nexus node. Resources behind the nexus node are + decoupled by the nexus node itself. + +maintainers: + - Herve Codina + +select: true + +properties: + '#pwm-cells': true + + pwm-map: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + + pwm-map-mask: + $ref: /schemas/types.yaml#/definitions/uint32-array + + pwm-map-pass-thru: + $ref: /schemas/types.yaml#/definitions/uint32-array + +dependentRequired: + pwm-map: ['#pwm-cells'] + pwm-map-mask: [ pwm-map ] + pwm-map-pass-thru: [ pwm-map ] + +additionalProperties: true + +examples: + - | + pwm1: pwm@100 { + reg = <0x100 0x10>; + #pwm-cells = <3>; + }; + + pwm2: pwm@200 { + reg = <0x200 0x10>; + #pwm-cells = <3>; + }; + + connector: connector { + #pwm-cells = <3>; + pwm-map = <0 0 0 &pwm1 1 0 0>, + <1 0 0 &pwm2 4 0 0>, + <2 0 0 &pwm1 3 0 0>; + pwm-map-mask = <0xffffffff 0x0 0x0>; + pwm-map-pass-thru = <0x0 0xffffffff 0xffffffff>; + }; + + device { + pwms = <&connector 1 57000 0>; + }; diff --git a/Bindings/pwm/pwm-rockchip.yaml b/Bindings/pwm/pwm-rockchip.yaml index 65bfb492b3a..c8cdfb72333 100644 --- a/Bindings/pwm/pwm-rockchip.yaml +++ b/Bindings/pwm/pwm-rockchip.yaml @@ -30,6 +30,8 @@ properties: - enum: - rockchip,px30-pwm - rockchip,rk3308-pwm + - rockchip,rk3528-pwm + - rockchip,rk3562-pwm - rockchip,rk3568-pwm - rockchip,rk3588-pwm - rockchip,rv1126-pwm diff --git a/Bindings/pwm/renesas,tpu-pwm.yaml b/Bindings/pwm/renesas,tpu-pwm.yaml index a4dfa09344d..f85ee5d20cc 100644 --- a/Bindings/pwm/renesas,tpu-pwm.yaml +++ b/Bindings/pwm/renesas,tpu-pwm.yaml @@ -9,15 +9,6 @@ title: Renesas R-Car Timer Pulse Unit PWM Controller maintainers: - Laurent Pinchart -select: - properties: - compatible: - contains: - const: renesas,tpu - required: - - compatible - - '#pwm-cells' - properties: compatible: items: diff --git a/Bindings/pwm/sophgo,sg2042-pwm.yaml b/Bindings/pwm/sophgo,sg2042-pwm.yaml new file mode 100644 index 00000000000..bbb6326d47d --- /dev/null +++ b/Bindings/pwm/sophgo,sg2042-pwm.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/sophgo,sg2042-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Sophgo SG2042 PWM controller + +maintainers: + - Chen Wang + +description: + This controller contains 4 channels which can generate PWM waveforms. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + const: sophgo,sg2042-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + +unevaluatedProperties: false + +examples: + - | + #include + + pwm@7f006000 { + compatible = "sophgo,sg2042-pwm"; + reg = <0x7f006000 0x1000>; + #pwm-cells = <3>; + clocks = <&clock 67>; + clock-names = "apb"; + resets = <&rstgen RST_PWM>; + }; diff --git a/Bindings/regulator/nxp,pca9450-regulator.yaml b/Bindings/regulator/nxp,pca9450-regulator.yaml index 68709a7dc43..4ffe5c3faea 100644 --- a/Bindings/regulator/nxp,pca9450-regulator.yaml +++ b/Bindings/regulator/nxp,pca9450-regulator.yaml @@ -17,6 +17,9 @@ description: | Datasheet is available at https://www.nxp.com/docs/en/data-sheet/PCA9450DS.pdf + Support PF9453, Datasheet is available at + https://www.nxp.com/docs/en/data-sheet/PF9453_SDS.pdf + # The valid names for PCA9450 regulator nodes are: # BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, BUCK6, # LDO1, LDO2, LDO3, LDO4, LDO5 @@ -30,6 +33,7 @@ properties: - nxp,pca9450c - nxp,pca9451a - nxp,pca9452 + - nxp,pf9453 reg: maxItems: 1 @@ -42,8 +46,30 @@ properties: description: | list of regulators provided by this controller + properties: + LDO5: + type: object + $ref: regulator.yaml# + description: + Properties for single LDO5 regulator. + + properties: + nxp,sd-vsel-fixed-low: + type: boolean + description: + Let the driver know that SD_VSEL is hardwired to low level and + there is no GPIO to get the actual value from. + + sd-vsel-gpios: + description: + GPIO that can be used to read the current status of the SD_VSEL + signal in order for the driver to know if LDO5CTRL_L or LDO5CTRL_H + is used by the hardware. + + unevaluatedProperties: false + patternProperties: - "^LDO[1-5]$": + "^LDO([1-4]|-SNVS)$": type: object $ref: regulator.yaml# description: @@ -78,11 +104,6 @@ properties: additionalProperties: false - sd-vsel-gpios: - description: GPIO that is used to switch LDO5 between being configured by - LDO5CTRL_L or LDO5CTRL_H register. Use this if the SD_VSEL signal is - connected to a host GPIO. - nxp,i2c-lt-enable: type: boolean description: @@ -101,6 +122,24 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: nxp,pf9453 + then: + properties: + regulators: + patternProperties: + "^LDO[3-4]$": false + "^BUCK[5-6]$": false + else: + properties: + regulators: + properties: + LDO-SNVS: false + examples: - | #include diff --git a/Bindings/regulator/richtek,rtq2208.yaml b/Bindings/regulator/richtek,rtq2208.yaml index 87accc6f13b..022c1f19736 100644 --- a/Bindings/regulator/richtek,rtq2208.yaml +++ b/Bindings/regulator/richtek,rtq2208.yaml @@ -39,7 +39,7 @@ properties: interrupts: maxItems: 1 - + richtek,mtp-sel-high: type: boolean description: @@ -77,6 +77,7 @@ properties: properties: richtek,fixed-microvolt: + deprecated: true description: | This property can be used to set a fixed operating voltage that lies outside the range of the regulator's adjustable mode. diff --git a/Bindings/regulator/samsung,s2mpu05.yaml b/Bindings/regulator/samsung,s2mpu05.yaml new file mode 100644 index 00000000000..378518a5a7f --- /dev/null +++ b/Bindings/regulator/samsung,s2mpu05.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/samsung,s2mpu05.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPU05 Power Management IC regulators + +maintainers: + - Kaustabh Chakraborty + +description: | + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + The S2MPU05 provides buck and LDO regulators. + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +patternProperties: + # 21 LDOs + "^ldo([1-9]|10|2[5-9]|3[0-5])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + LDOs 11-24 are used for CP, and they're left unimplemented due to lack + of documentation on these regulators. + + required: + - regulator-name + + # 5 bucks + "^buck[1-5]$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single buck regulator. + + required: + - regulator-name + +additionalProperties: false diff --git a/Bindings/regulator/ti,tps65219.yaml b/Bindings/regulator/ti,tps65219.yaml index 78e64521d40..7c64e588a8b 100644 --- a/Bindings/regulator/ti,tps65219.yaml +++ b/Bindings/regulator/ti,tps65219.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/regulator/ti,tps65219.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: TI tps65219 Power Management Integrated Circuit regulators +title: TI TPS65214/TPS65215/TPS65219 Power Management Integrated Circuit maintainers: - Jerome Neanne @@ -12,9 +12,20 @@ maintainers: description: | Regulator nodes should be named to buck and ldo. + TI TPS65219 is a Power Management IC with 3 Buck regulators, 4 Low + Drop-out Regulators (LDOs), 1 GPIO, 2 GPOs, and power-button. + + TI TPS65215 is a derivative of TPS65219 with 3 Buck regulators, 2 Low + Drop-out Regulators (LDOs), 1 GPIO, 1 GPO, and power-button. + + TI TPS65214 is a derivative of TPS65219 with 3 Buck regulators, 2 Low + Drop-out Regulators (LDOs), 1 GPIO, 1 GPO, and power-button. + properties: compatible: enum: + - ti,tps65214 + - ti,tps65215 - ti,tps65219 reg: @@ -90,6 +101,20 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - ti,tps65214 + - ti,tps65215 + then: + properties: + regulators: + patternProperties: + "^ldo[3-4]$": false + examples: - | #include diff --git a/Bindings/remoteproc/qcom,msm8916-mss-pil.yaml b/Bindings/remoteproc/qcom,msm8916-mss-pil.yaml index 588b010b2a9..c179b560572 100644 --- a/Bindings/remoteproc/qcom,msm8916-mss-pil.yaml +++ b/Bindings/remoteproc/qcom,msm8916-mss-pil.yaml @@ -17,8 +17,10 @@ properties: compatible: oneOf: - enum: + - qcom,msm8226-mss-pil - qcom,msm8909-mss-pil - qcom,msm8916-mss-pil + - qcom,msm8926-mss-pil - qcom,msm8953-mss-pil - qcom,msm8974-mss-pil @@ -70,16 +72,18 @@ properties: items: - description: CX proxy power domain (control handed over after startup) - description: MX proxy power domain (control handed over after startup) + (not valid for qcom,msm8226-mss-pil, qcom,msm8926-mss-pil + and qcom,msm8974-mss-pil) - description: MSS proxy power domain (control handed over after startup) (only valid for qcom,msm8953-mss-pil) - minItems: 2 + minItems: 1 power-domain-names: items: - const: cx - - const: mx + - const: mx # not valid for qcom,msm8226-mss-pil, qcom-msm8926-mss-pil and qcom,msm8974-mss-pil - const: mss # only valid for qcom,msm8953-mss-pil - minItems: 2 + minItems: 1 pll-supply: description: PLL proxy supply (control handed over after startup) @@ -106,6 +110,15 @@ properties: items: - const: stop + qcom,ext-bhs-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: External power block headswitch (BHS) register + (only valid for qcom,msm8226-mss-pil) + items: + - items: + - description: phandle to external BHS syscon region + - description: offset to the external BHS register + qcom,halt-regs: $ref: /schemas/types.yaml#/definitions/phandle-array description: @@ -207,17 +220,58 @@ allOf: required: - power-domains - power-domain-names - else: + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8909-mss-pil + - qcom,msm8916-mss-pil + then: properties: power-domains: + minItems: 2 maxItems: 2 power-domain-names: + minItems: 2 maxItems: 2 - if: properties: compatible: - const: qcom,msm8974-mss-pil + contains: + enum: + - qcom,msm8226-mss-pil + - qcom,msm8926-mss-pil + - qcom,msm8974-mss-pil + then: + properties: + power-domains: + maxItems: 1 + power-domain-names: + maxItems: 1 + required: + - mx-supply + + - if: + properties: + compatible: + const: qcom,msm8226-mss-pil + then: + required: + - qcom,ext-bhs-reg + else: + properties: + qcom,ext-bhs-reg: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8926-mss-pil + - qcom,msm8974-mss-pil then: required: - mss-supply diff --git a/Bindings/remoteproc/qcom,sc8180x-pas.yaml b/Bindings/remoteproc/qcom,sc8180x-pas.yaml deleted file mode 100644 index 45ee9fbe096..00000000000 --- a/Bindings/remoteproc/qcom,sc8180x-pas.yaml +++ /dev/null @@ -1,96 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/remoteproc/qcom,sc8180x-pas.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SC8180X Peripheral Authentication Service - -maintainers: - - Manivannan Sadhasivam - -description: - Qualcomm SC8180X SoC Peripheral Authentication Service loads and boots - firmware on the Qualcomm DSP Hexagon cores. - -properties: - compatible: - enum: - - qcom,sc8180x-adsp-pas - - qcom,sc8180x-cdsp-pas - - qcom,sc8180x-mpss-pas - - reg: - maxItems: 1 - - clocks: - items: - - description: XO clock - - clock-names: - items: - - const: xo - - qcom,qmp: - $ref: /schemas/types.yaml#/definitions/phandle - description: Reference to the AOSS side-channel message RAM. - - smd-edge: false - - memory-region: - maxItems: 1 - description: Reference to the reserved-memory for the Hexagon core - - firmware-name: - maxItems: 1 - description: Firmware name for the Hexagon core - -required: - - compatible - - reg - - memory-region - -allOf: - - $ref: /schemas/remoteproc/qcom,pas-common.yaml# - - if: - properties: - compatible: - enum: - - qcom,sc8180x-adsp-pas - - qcom,sc8180x-cdsp-pas - then: - properties: - interrupts: - maxItems: 5 - interrupt-names: - maxItems: 5 - else: - properties: - interrupts: - minItems: 6 - interrupt-names: - minItems: 6 - - - if: - properties: - compatible: - enum: - - qcom,sc8180x-adsp-pas - - qcom,sc8180x-cdsp-pas - then: - properties: - power-domains: - items: - - description: LCX power domain - - description: LMX power domain - power-domain-names: - items: - - const: lcx - - const: lmx - else: - properties: - # TODO: incomplete - power-domains: false - power-domain-names: false - -unevaluatedProperties: false diff --git a/Bindings/remoteproc/qcom,sm6115-pas.yaml b/Bindings/remoteproc/qcom,sm6115-pas.yaml index 059cb87b4d6..eeb6a8aafeb 100644 --- a/Bindings/remoteproc/qcom,sm6115-pas.yaml +++ b/Bindings/remoteproc/qcom,sm6115-pas.yaml @@ -127,7 +127,7 @@ examples: clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; clock-names = "xo"; - firmware-name = "qcom/sm6115/adsp.mdt"; + firmware-name = "qcom/sm6115/adsp.mbn"; interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, diff --git a/Bindings/remoteproc/qcom,sm8150-pas.yaml b/Bindings/remoteproc/qcom,sm8150-pas.yaml index d67386c50fa..56ff6386534 100644 --- a/Bindings/remoteproc/qcom,sm8150-pas.yaml +++ b/Bindings/remoteproc/qcom,sm8150-pas.yaml @@ -60,6 +60,9 @@ allOf: properties: compatible: enum: + - qcom,sc8180x-adsp-pas + - qcom,sc8180x-cdsp-pas + - qcom,sc8180x-slpi-pas - qcom,sm8150-adsp-pas - qcom,sm8150-cdsp-pas - qcom,sm8150-slpi-pas @@ -83,6 +86,8 @@ allOf: properties: compatible: enum: + - qcom,sc8180x-adsp-pas + - qcom,sc8180x-cdsp-pas - qcom,sm8150-adsp-pas - qcom,sm8150-cdsp-pas - qcom,sm8250-cdsp-pas @@ -99,6 +104,7 @@ allOf: properties: compatible: enum: + - qcom,sc8180x-mpss-pas - qcom,sm8150-mpss-pas then: properties: @@ -115,6 +121,7 @@ allOf: properties: compatible: enum: + - qcom,sc8180x-slpi-pas - qcom,sm8150-slpi-pas - qcom,sm8250-adsp-pas - qcom,sm8250-slpi-pas diff --git a/Bindings/remoteproc/qcom,sm8550-pas.yaml b/Bindings/remoteproc/qcom,sm8550-pas.yaml index a24cbb61bda..2dd479cf482 100644 --- a/Bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Bindings/remoteproc/qcom,sm8550-pas.yaml @@ -24,11 +24,15 @@ properties: - qcom,sm8650-adsp-pas - qcom,sm8650-cdsp-pas - qcom,sm8650-mpss-pas + - qcom,sm8750-mpss-pas - qcom,x1e80100-adsp-pas - qcom,x1e80100-cdsp-pas - items: - const: qcom,sm8750-adsp-pas - const: qcom,sm8550-adsp-pas + - items: + - const: qcom,sm8750-cdsp-pas + - const: qcom,sm8650-cdsp-pas reg: maxItems: 1 @@ -114,6 +118,23 @@ allOf: memory-region: minItems: 3 maxItems: 3 + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8750-cdsp-pas + then: + properties: + interrupts: + maxItems: 6 + interrupt-names: + maxItems: 6 + memory-region: + minItems: 3 + maxItems: 3 + - if: properties: compatible: @@ -144,6 +165,21 @@ allOf: minItems: 5 maxItems: 5 + - if: + properties: + compatible: + enum: + - qcom,sm8750-mpss-pas + then: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + memory-region: + minItems: 4 + maxItems: 4 + - if: properties: compatible: @@ -171,6 +207,7 @@ allOf: - qcom,sdx75-mpss-pas - qcom,sm8550-mpss-pas - qcom,sm8650-mpss-pas + - qcom,sm8750-mpss-pas then: properties: power-domains: @@ -184,10 +221,11 @@ allOf: - if: properties: compatible: - enum: - - qcom,sm8550-cdsp-pas - - qcom,sm8650-cdsp-pas - - qcom,x1e80100-cdsp-pas + contains: + enum: + - qcom,sm8550-cdsp-pas + - qcom,sm8650-cdsp-pas + - qcom,x1e80100-cdsp-pas then: properties: power-domains: diff --git a/Bindings/remoteproc/qcom,wcnss-pil.yaml b/Bindings/remoteproc/qcom,wcnss-pil.yaml index 8e033b22d28..117fb4d0c4a 100644 --- a/Bindings/remoteproc/qcom,wcnss-pil.yaml +++ b/Bindings/remoteproc/qcom,wcnss-pil.yaml @@ -69,9 +69,11 @@ properties: CX regulator to be held on behalf of the booting of the WCNSS core. power-domains: + minItems: 1 maxItems: 2 power-domain-names: + minItems: 1 items: - const: cx - const: mx @@ -187,22 +189,43 @@ allOf: - qcom,pronto-v1-pil - qcom,pronto-v2-pil then: - properties: - vddmx-supply: - deprecated: true - description: Deprecated for qcom,pronto-v1/2-pil - - vddcx-supply: - deprecated: true - description: Deprecated for qcom,pronto-v1/2-pil - + # CX and MX must be present either as power domains or regulators oneOf: + # Both CX and MX represented as power domains - required: - power-domains - power-domain-names + properties: + power-domains: + minItems: 2 + power-domain-names: + minItems: 2 + vddmx-supply: false + vddcx-supply: false + # CX represented as power domain, MX as regulator + - required: + - power-domains + - power-domain-names + - vddmx-supply + properties: + power-domains: + maxItems: 1 + power-domain-names: + maxItems: 1 + vddcx-supply: false + # Both CX and MX represented as regulators - required: - vddmx-supply - vddcx-supply + properties: + power-domains: false + power-domain-names: false + vddmx-supply: + deprecated: true + description: Deprecated for qcom,pronto-v1/2-pil + vddcx-supply: + deprecated: true + description: Deprecated for qcom,pronto-v1/2-pil - if: properties: @@ -212,6 +235,10 @@ allOf: - qcom,pronto-v3-pil then: properties: + power-domains: + minItems: 2 + power-domain-names: + minItems: 2 vddmx-supply: false vddcx-supply: false diff --git a/Bindings/reset/atmel,at91sam9260-reset.yaml b/Bindings/reset/atmel,at91sam9260-reset.yaml index 98465d26949..c3b33bbc731 100644 --- a/Bindings/reset/atmel,at91sam9260-reset.yaml +++ b/Bindings/reset/atmel,at91sam9260-reset.yaml @@ -26,6 +26,10 @@ properties: - items: - const: atmel,sama5d3-rstc - const: atmel,at91sam9g45-rstc + - items: + - enum: + - microchip,sam9x7-rstc + - const: microchip,sam9x60-rstc reg: minItems: 1 diff --git a/Bindings/reset/xlnx,zynqmp-reset.yaml b/Bindings/reset/xlnx,zynqmp-reset.yaml index 1f1b42dde94..1db85fc9966 100644 --- a/Bindings/reset/xlnx,zynqmp-reset.yaml +++ b/Bindings/reset/xlnx,zynqmp-reset.yaml @@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Zynq UltraScale+ MPSoC and Versal reset maintainers: - - Mubin Sayyed - Radhey Shyam Pandey description: | diff --git a/Bindings/riscv/extensions.yaml b/Bindings/riscv/extensions.yaml index a63b994e076..bcab59e0cc2 100644 --- a/Bindings/riscv/extensions.yaml +++ b/Bindings/riscv/extensions.yaml @@ -224,6 +224,12 @@ properties: as ratified at commit 4a69197e5617 ("Update to ratified state") of riscv-svvptc. + - const: zaamo + description: | + The standard Zaamo extension for atomic memory operations as + ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text + (#1304)") of the unprivileged ISA specification. + - const: zabha description: | The Zabha extension for Byte and Halfword Atomic Memory Operations @@ -236,6 +242,12 @@ properties: is supported as ratified at commit 5059e0ca641c ("update to ratified") of the riscv-zacas. + - const: zalrsc + description: | + The standard Zalrsc extension for load-reserved/store-conditional as + ratified at commit e87412e621f1 ("integrate Zaamo and Zalrsc text + (#1304)") of the unprivileged ISA specification. + - const: zawrs description: | The Zawrs extension for entering a low-power state or for trapping @@ -329,6 +341,12 @@ properties: instructions, as ratified in commit 056b6ff ("Zfa is ratified") of riscv-isa-manual. + - const: zfbfmin + description: + The standard Zfbfmin extension which provides minimal support for + 16-bit half-precision brain floating-point instructions, as ratified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. + - const: zfh description: The standard Zfh extension for 16-bit half-precision binary @@ -525,6 +543,18 @@ properties: in commit 6f702a2 ("Vector extensions are now ratified") of riscv-v-spec. + - const: zvfbfmin + description: + The standard Zvfbfmin extension for minimal support for vectored + 16-bit half-precision brain floating-point instructions, as ratified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. + + - const: zvfbfwma + description: + The standard Zvfbfwma extension for vectored half-precision brain + floating-point widening multiply-accumulate instructions, as ratified + in commit 4dc23d62 ("Added Chapter title to BF16") of riscv-isa-manual. + - const: zvfh description: The standard Zvfh extension for vectored half-precision @@ -639,6 +669,12 @@ properties: https://github.com/T-head-Semi/thead-extension-spec/blob/95358cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. allOf: + - if: + contains: + const: d + then: + contains: + const: f # Zcb depends on Zca - if: contains: @@ -673,6 +709,119 @@ properties: then: contains: const: zca + # Zfbfmin depends on F + - if: + contains: + const: zfbfmin + then: + contains: + const: f + # Zvfbfmin depends on V or Zve32f + - if: + contains: + const: zvfbfmin + then: + oneOf: + - contains: + const: v + - contains: + const: zve32f + # Zvfbfwma depends on Zfbfmin and Zvfbfmin + - if: + contains: + const: zvfbfwma + then: + allOf: + - contains: + const: zfbfmin + - contains: + const: zvfbfmin + # Zacas depends on Zaamo + - if: + contains: + const: zacas + then: + contains: + const: zaamo + + - if: + contains: + const: zve32x + then: + contains: + const: zicsr + + - if: + contains: + const: zve32f + then: + allOf: + - contains: + const: f + - contains: + const: zve32x + + - if: + contains: + const: zve64x + then: + contains: + const: zve32x + + - if: + contains: + const: zve64f + then: + allOf: + - contains: + const: f + - contains: + const: zve32f + - contains: + const: zve64x + + - if: + contains: + const: zve64d + then: + allOf: + - contains: + const: d + - contains: + const: zve64f + + - if: + contains: + anyOf: + - const: zvbc + - const: zvkn + - const: zvknc + - const: zvkng + - const: zvknhb + - const: zvksc + then: + contains: + anyOf: + - const: v + - const: zve64x + + - if: + contains: + anyOf: + - const: zvbb + - const: zvkb + - const: zvkg + - const: zvkned + - const: zvknha + - const: zvksed + - const: zvksh + - const: zvks + - const: zvkt + then: + contains: + anyOf: + - const: v + - const: zve32x allOf: # Zcf extension does not exist on rv64 diff --git a/Bindings/riscv/spacemit.yaml b/Bindings/riscv/spacemit.yaml index 52e55077af1..077b94f10dc 100644 --- a/Bindings/riscv/spacemit.yaml +++ b/Bindings/riscv/spacemit.yaml @@ -21,6 +21,7 @@ properties: - items: - enum: - bananapi,bpi-f3 + - milkv,jupiter - const: spacemit,k1 additionalProperties: true diff --git a/Bindings/rng/rockchip,rk3588-rng.yaml b/Bindings/rng/rockchip,rk3588-rng.yaml new file mode 100644 index 00000000000..ca71b400bca --- /dev/null +++ b/Bindings/rng/rockchip,rk3588-rng.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/rockchip,rk3588-rng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3588 TRNG + +description: True Random Number Generator on Rockchip RK3588 SoC + +maintainers: + - Nicolas Frattaroli + +properties: + compatible: + enum: + - rockchip,rk3588-rng + + reg: + maxItems: 1 + + clocks: + items: + - description: TRNG AHB clock + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + bus { + #address-cells = <2>; + #size-cells = <2>; + + rng@fe378000 { + compatible = "rockchip,rk3588-rng"; + reg = <0x0 0xfe378000 0x0 0x200>; + interrupts = ; + clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; + resets = <&scmi_reset SCMI_SRST_H_TRNG_NS>; + }; + }; + +... diff --git a/Bindings/rtc/adi,max31335.yaml b/Bindings/rtc/adi,max31335.yaml index 0125cf6727c..bce7558d0d8 100644 --- a/Bindings/rtc/adi,max31335.yaml +++ b/Bindings/rtc/adi,max31335.yaml @@ -18,7 +18,9 @@ allOf: properties: compatible: - const: adi,max31335 + enum: + - adi,max31331 + - adi,max31335 reg: maxItems: 1 diff --git a/Bindings/rtc/nxp,pcf2127.yaml b/Bindings/rtc/nxp,pcf2127.yaml index 2d9fe5a75b0..11fcf0ca1ae 100644 --- a/Bindings/rtc/nxp,pcf2127.yaml +++ b/Bindings/rtc/nxp,pcf2127.yaml @@ -8,6 +8,7 @@ title: NXP PCF2127 Real Time Clock allOf: - $ref: rtc.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# maintainers: - Alexandre Belloni @@ -34,7 +35,7 @@ required: - compatible - reg -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Bindings/rtc/qcom-pm8xxx-rtc.yaml b/Bindings/rtc/qcom-pm8xxx-rtc.yaml index d274bb7a534..68ef3208c88 100644 --- a/Bindings/rtc/qcom-pm8xxx-rtc.yaml +++ b/Bindings/rtc/qcom-pm8xxx-rtc.yaml @@ -50,6 +50,11 @@ properties: items: - const: offset + qcom,no-alarm: + type: boolean + description: + RTC alarm is not owned by the OS + wakeup-source: true required: diff --git a/Bindings/serial/8250.yaml b/Bindings/serial/8250.yaml index 0bde2379e86..dc0d5292057 100644 --- a/Bindings/serial/8250.yaml +++ b/Bindings/serial/8250.yaml @@ -77,7 +77,6 @@ properties: - altr,16550-FIFO64 - altr,16550-FIFO128 - fsl,16550-FIFO64 - - fsl,ns16550 - andestech,uart16550 - nxp,lpc1850-uart - opencores,uart16550-rtlsvn105 @@ -86,6 +85,7 @@ properties: - items: - enum: - ns16750 + - fsl,ns16550 - cavium,octeon-3860-uart - xlnx,xps-uart16550-2.00.b - ralink,rt2880-uart diff --git a/Bindings/serial/fsl-lpuart.yaml b/Bindings/serial/fsl-lpuart.yaml index 3f9ace89dee..c42261b5a80 100644 --- a/Bindings/serial/fsl-lpuart.yaml +++ b/Bindings/serial/fsl-lpuart.yaml @@ -30,6 +30,7 @@ properties: - items: - enum: - fsl,imx93-lpuart + - fsl,imx94-lpuart - fsl,imx95-lpuart - const: fsl,imx8ulp-lpuart - const: fsl,imx7ulp-lpuart diff --git a/Bindings/serial/nvidia,tegra264-utc.yaml b/Bindings/serial/nvidia,tegra264-utc.yaml new file mode 100644 index 00000000000..572cc574da6 --- /dev/null +++ b/Bindings/serial/nvidia,tegra264-utc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nvidia,tegra264-utc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra UTC (UART Trace Controller) client + +maintainers: + - Kartik Rajput + - Thierry Reding + - Jonathan Hunter + +description: + Represents a client interface of the Tegra UTC (UART Trace Controller). The + Tegra UTC allows multiple clients within the Tegra SoC to share a physical + UART interface. It supports up to 16 clients. Each client operates as an + independent UART endpoint with a dedicated interrupt and 128-character TX/RX + FIFOs. + + The Tegra UTC clients use 8-N-1 configuration and operates on a baudrate + configured by the bootloader at the controller level. + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: nvidia,tegra264-utc + + reg: + items: + - description: TX region. + - description: RX region. + + reg-names: + items: + - const: tx + - const: rx + + interrupts: + maxItems: 1 + + tx-threshold: + minimum: 1 + maximum: 128 + + rx-threshold: + minimum: 1 + maximum: 128 + +required: + - compatible + - reg + - reg-names + - interrupts + - tx-threshold + - rx-threshold + +additionalProperties: false + +examples: + - | + #include + + tegra_utc: serial@c4e0000 { + compatible = "nvidia,tegra264-utc"; + reg = <0xc4e0000 0x8000>, <0xc4e8000 0x8000>; + reg-names = "tx", "rx"; + interrupts = ; + tx-threshold = <4>; + rx-threshold = <4>; + }; diff --git a/Bindings/serial/pl011.yaml b/Bindings/serial/pl011.yaml index 9571041030b..3fcf2d04237 100644 --- a/Bindings/serial/pl011.yaml +++ b/Bindings/serial/pl011.yaml @@ -92,6 +92,9 @@ properties: 3000ms. default: 3000 + power-domains: + maxItems: 1 + resets: maxItems: 1 diff --git a/Bindings/serial/samsung_uart.yaml b/Bindings/serial/samsung_uart.yaml index 070eba9f19d..83d9986d8e9 100644 --- a/Bindings/serial/samsung_uart.yaml +++ b/Bindings/serial/samsung_uart.yaml @@ -42,6 +42,10 @@ properties: - samsung,exynosautov9-uart - samsung,exynosautov920-uart - const: samsung,exynos850-uart + - items: + - enum: + - samsung,exynos7870-uart + - const: samsung,exynos8895-uart reg: maxItems: 1 diff --git a/Bindings/serial/snps-dw-apb-uart.yaml b/Bindings/serial/snps-dw-apb-uart.yaml index 1c163cb5dff..1aa3480d8d8 100644 --- a/Bindings/serial/snps-dw-apb-uart.yaml +++ b/Bindings/serial/snps-dw-apb-uart.yaml @@ -13,6 +13,20 @@ allOf: - $ref: serial.yaml# - $ref: rs485.yaml# + - if: + properties: + compatible: + items: + - enum: + - renesas,r9a06g032-uart + - renesas,r9a06g033-uart + - const: renesas,rzn1-uart + - const: snps,dw-apb-uart + then: + properties: + dmas: false + dma-names: false + - if: properties: compatible: @@ -30,6 +44,12 @@ allOf: properties: compatible: oneOf: + - items: + - enum: + - renesas,r9a06g032-uart + - renesas,r9a06g033-uart + - const: renesas,rzn1-uart + - const: snps,dw-apb-uart - items: - enum: - renesas,r9a06g032-uart @@ -51,6 +71,7 @@ properties: - rockchip,rk3368-uart - rockchip,rk3399-uart - rockchip,rk3528-uart + - rockchip,rk3562-uart - rockchip,rk3568-uart - rockchip,rk3576-uart - rockchip,rk3588-uart diff --git a/Bindings/serial/sprd-uart.yaml b/Bindings/serial/sprd-uart.yaml index a2a5056eba0..5bf2656afcf 100644 --- a/Bindings/serial/sprd-uart.yaml +++ b/Bindings/serial/sprd-uart.yaml @@ -17,13 +17,18 @@ properties: oneOf: - items: - enum: - - sprd,sc9632-uart + - sprd,ums9632-uart + - const: sprd,sc9632-uart + - items: + - enum: - sprd,sc9860-uart - sprd,sc9863a-uart - sprd,ums512-uart - sprd,ums9620-uart - const: sprd,sc9836-uart - - const: sprd,sc9836-uart + - enum: + - sprd,sc9632-uart + - sprd,sc9836-uart reg: maxItems: 1 diff --git a/Bindings/soc/fsl/fsl,ls1028a-reset.yaml b/Bindings/soc/fsl/fsl,ls1028a-reset.yaml index 31295be9101..234089b5954 100644 --- a/Bindings/soc/fsl/fsl,ls1028a-reset.yaml +++ b/Bindings/soc/fsl/fsl,ls1028a-reset.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Freescale Layerscape Reset Registers Module maintainers: - - Frank Li + - Frank Li description: Reset Module includes chip reset, service processor control and Reset Control diff --git a/Bindings/soc/imx/fsl,aips-bus.yaml b/Bindings/soc/imx/fsl,aips-bus.yaml index 80d99861fec..70a4af65011 100644 --- a/Bindings/soc/imx/fsl,aips-bus.yaml +++ b/Bindings/soc/imx/fsl,aips-bus.yaml @@ -22,6 +22,9 @@ select: required: - compatible +allOf: + - $ref: /schemas/simple-bus.yaml# + properties: compatible: items: @@ -35,7 +38,7 @@ required: - compatible - reg -additionalProperties: true +unevaluatedProperties: false examples: - | diff --git a/Bindings/soc/qcom/qcom,geni-se.yaml b/Bindings/soc/qcom/qcom,geni-se.yaml index 7b031ef0966..54cd585f19e 100644 --- a/Bindings/soc/qcom/qcom,geni-se.yaml +++ b/Bindings/soc/qcom/qcom,geni-se.yaml @@ -54,6 +54,10 @@ properties: dma-coherent: true + firmware-name: + maxItems: 1 + description: Specify the name of the QUP firmware to load. + required: - compatible - reg @@ -135,6 +139,7 @@ examples: #address-cells = <2>; #size-cells = <2>; ranges; + firmware-name = "qcom/sa8775p/qupv3fw.elf"; i2c0: i2c@a94000 { compatible = "qcom,geni-i2c"; diff --git a/Bindings/soc/qcom/qcom,pmic-glink.yaml b/Bindings/soc/qcom/qcom,pmic-glink.yaml index 2d3fe0b5424..4c9e78f2952 100644 --- a/Bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Bindings/soc/qcom/qcom,pmic-glink.yaml @@ -38,6 +38,7 @@ properties: - items: - enum: - qcom,sm8650-pmic-glink + - qcom,sm8750-pmic-glink - qcom,x1e80100-pmic-glink - const: qcom,sm8550-pmic-glink - const: qcom,pmic-glink diff --git a/Bindings/soc/renesas/renesas,r9a09g057-sys.yaml b/Bindings/soc/renesas/renesas,r9a09g057-sys.yaml index ebbf0c9109c..e0f7503a9f3 100644 --- a/Bindings/soc/renesas/renesas,r9a09g057-sys.yaml +++ b/Bindings/soc/renesas/renesas,r9a09g057-sys.yaml @@ -22,7 +22,10 @@ description: | properties: compatible: - const: renesas,r9a09g057-sys + items: + - enum: + - renesas,r9a09g047-sys # RZ/G3E + - renesas,r9a09g057-sys # RZ/V2H reg: maxItems: 1 diff --git a/Bindings/soc/renesas/renesas.yaml b/Bindings/soc/renesas/renesas.yaml index 225c0f07ae9..51a4c48eea6 100644 --- a/Bindings/soc/renesas/renesas.yaml +++ b/Bindings/soc/renesas/renesas.yaml @@ -493,6 +493,13 @@ properties: - renesas,r9a07g044l2 # Dual Cortex-A55 RZ/G2L - const: renesas,r9a07g044 + - items: + - enum: + # MYIR Remi Pi SBC (MYB-YG2LX-REMI) + - myir,remi-pi + - const: renesas,r9a07g044l2 + - const: renesas,r9a07g044 + - description: RZ/V2L (R9A07G054) items: - enum: @@ -552,6 +559,15 @@ properties: - renesas,r9a09g057h41 # RZ/V2H - renesas,r9a09g057h42 # RZ/V2H with Mali-G31 support - renesas,r9a09g057h44 # RZ/V2HP with Mali-G31 + Mali-C55 support + - renesas,r9a09g057h45 # RZ/V2H with cryptographic extension support + - renesas,r9a09g057h46 # RZ/V2H with Mali-G31 + cryptographic extension support + - renesas,r9a09g057h48 # RZ/V2HP with Mali-G31 + Mali-C55 + cryptographic extension support + - const: renesas,r9a09g057 + + - description: Yuridenki-Shokai RZ/V2H Kakip + items: + - const: yuridenki,kakip + - const: renesas,r9a09g057h48 - const: renesas,r9a09g057 additionalProperties: true diff --git a/Bindings/soc/rockchip/grf.yaml b/Bindings/soc/rockchip/grf.yaml index 61f38b68a4a..2f61c1b95fe 100644 --- a/Bindings/soc/rockchip/grf.yaml +++ b/Bindings/soc/rockchip/grf.yaml @@ -15,6 +15,9 @@ properties: - items: - enum: - rockchip,rk3288-sgrf + - rockchip,rk3528-ioc-grf + - rockchip,rk3528-vo-grf + - rockchip,rk3528-vpu-grf - rockchip,rk3566-pipe-grf - rockchip,rk3568-pcie3-phy-grf - rockchip,rk3568-pipe-grf diff --git a/Bindings/soc/samsung/exynos-pmu.yaml b/Bindings/soc/samsung/exynos-pmu.yaml index 8e6d051d8c9..204da6fe458 100644 --- a/Bindings/soc/samsung/exynos-pmu.yaml +++ b/Bindings/soc/samsung/exynos-pmu.yaml @@ -52,6 +52,8 @@ properties: - const: syscon - items: - enum: + - samsung,exynos2200-pmu + - samsung,exynos7870-pmu - samsung,exynos7885-pmu - samsung,exynos8895-pmu - samsung,exynos9810-pmu diff --git a/Bindings/soc/samsung/exynos-usi.yaml b/Bindings/soc/samsung/exynos-usi.yaml index 5b046932fbc..cb22637091e 100644 --- a/Bindings/soc/samsung/exynos-usi.yaml +++ b/Bindings/soc/samsung/exynos-usi.yaml @@ -11,11 +11,21 @@ maintainers: - Krzysztof Kozlowski description: | - USI IP-core provides selectable serial protocol (UART, SPI or High-Speed I2C). - USI shares almost all internal circuits within each protocol, so only one - protocol can be chosen at a time. USI is modeled as a node with zero or more - child nodes, each representing a serial sub-node device. The mode setting - selects which particular function will be used. + The USI IP-core provides configurable support for serial protocols, enabling + different serial communication modes depending on the version. + + In USIv1, configurations are available to enable either one or two protocols + simultaneously in select combinations - High-Speed I2C0, High-Speed + I2C1, SPI, UART, High-Speed I2C0 and I2C1 or both High-Speed + I2C1 and UART. + + In USIv2, only one protocol can be active at a time, either UART, SPI, or + High-Speed I2C. + + The USI core shares internal circuits across protocols, meaning only the + selected configuration is active at any given time. USI is modeled as a node + with zero or more child nodes, each representing a serial sub-node device. The + mode setting selects which particular function will be used. properties: $nodename: @@ -31,6 +41,7 @@ properties: - const: samsung,exynos850-usi - enum: - samsung,exynos850-usi + - samsung,exynos8895-usi reg: maxItems: 1 @@ -64,7 +75,7 @@ properties: samsung,mode: $ref: /schemas/types.yaml#/definitions/uint32 - enum: [0, 1, 2, 3] + enum: [0, 1, 2, 3, 4, 5, 6] description: Selects USI function (which serial protocol to use). Refer to for valid USI mode values. @@ -101,37 +112,59 @@ required: - samsung,sysreg - samsung,mode -if: - properties: - compatible: - contains: - enum: - - samsung,exynos850-usi +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos850-usi + + then: + properties: + reg: + maxItems: 1 + + clocks: + items: + - description: Bus (APB) clock + - description: Operating clock for UART/SPI/I2C protocol -then: - properties: - reg: - maxItems: 1 + clock-names: + maxItems: 2 - clocks: - items: - - description: Bus (APB) clock - - description: Operating clock for UART/SPI/I2C protocol + samsung,mode: + enum: [0, 1, 2, 3] - clock-names: - maxItems: 2 + required: + - reg + - clocks + - clock-names - required: - - reg - - clocks - - clock-names + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos8895-usi -else: - properties: - reg: false - clocks: false - clock-names: false - samsung,clkreq-on: false + then: + properties: + reg: false + + clocks: + items: + - description: Bus (APB) clock + - description: Operating clock for UART/SPI protocol + + clock-names: + maxItems: 2 + + samsung,clkreq-on: false + + required: + - clocks + - clock-names additionalProperties: false @@ -144,7 +177,7 @@ examples: compatible = "samsung,exynos850-usi"; reg = <0x138200c0 0x20>; samsung,sysreg = <&sysreg_peri 0x1010>; - samsung,mode = ; + samsung,mode = ; samsung,clkreq-on; /* needed for UART mode */ #address-cells = <1>; #size-cells = <1>; @@ -158,7 +191,6 @@ examples: interrupts = ; clocks = <&cmu_peri 32>, <&cmu_peri 31>; clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; }; hsi2c_0: i2c@13820000 { diff --git a/Bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Bindings/soc/samsung/samsung,exynos-sysreg.yaml index a75aef24062..d27ed6c9d61 100644 --- a/Bindings/soc/samsung/samsung,exynos-sysreg.yaml +++ b/Bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -18,6 +18,11 @@ properties: - google,gs101-hsi2-sysreg - google,gs101-peric0-sysreg - google,gs101-peric1-sysreg + - samsung,exynos2200-cmgp-sysreg + - samsung,exynos2200-peric0-sysreg + - samsung,exynos2200-peric1-sysreg + - samsung,exynos2200-peric2-sysreg + - samsung,exynos2200-ufs-sysreg - samsung,exynos3-sysreg - samsung,exynos4-sysreg - samsung,exynos5-sysreg diff --git a/Bindings/soc/xilinx/xilinx.yaml b/Bindings/soc/xilinx/xilinx.yaml index 131aba5ed9f..fb5c39c79d2 100644 --- a/Bindings/soc/xilinx/xilinx.yaml +++ b/Bindings/soc/xilinx/xilinx.yaml @@ -9,8 +9,8 @@ title: Xilinx Zynq Platforms maintainers: - Michal Simek -description: | - Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC +description: + AMD/Xilinx boards with ARM 32/64bits cores properties: $nodename: @@ -187,6 +187,13 @@ properties: - const: qemu,mbv - const: amd,mbv + - description: Xilinx Versal NET VN-X revA platform + items: + enum: + - xlnx,versal-net-vnx-revA + - xlnx,versal-net-vnx + - xlnx,versal-net + additionalProperties: true ... diff --git a/Bindings/sound/allwinner,sun4i-a10-codec.yaml b/Bindings/sound/allwinner,sun4i-a10-codec.yaml index ccae64ce307..b4eca702feb 100644 --- a/Bindings/sound/allwinner,sun4i-a10-codec.yaml +++ b/Bindings/sound/allwinner,sun4i-a10-codec.yaml @@ -102,6 +102,10 @@ properties: maxItems: 1 description: GPIO to enable the external amplifier + hp-det-gpios: + maxItems: 1 + description: GPIO for headphone/line-out detection + required: - "#sound-dai-cells" - compatible @@ -251,8 +255,10 @@ allOf: allwinner,audio-routing: items: enum: + - Headphone - LINEOUT - Line Out + - Speaker dmas: items: diff --git a/Bindings/sound/atmel,at91-ssc.yaml b/Bindings/sound/atmel,at91-ssc.yaml new file mode 100644 index 00000000000..a05e6143182 --- /dev/null +++ b/Bindings/sound/atmel,at91-ssc.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/atmel,at91-ssc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Serial Synchronous Serial (SSC) + +maintainers: + - Andrei Simion + +description: + The Atmel Synchronous Serial Controller (SSC) provides a versatile + synchronous communication link for audio and telecom applications, + supporting protocols like I2S, Short Frame Sync, and Long Frame Sync. + +properties: + compatible: + enum: + - atmel,at91rm9200-ssc + - atmel,at91sam9g45-ssc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pclk + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + + atmel,clk-from-rk-pin: + description: + Specify the clock source for the SSC (Synchronous Serial Controller) + when operating in slave mode. By default, the clock is sourced from + the TK pin. + type: boolean + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +allOf: + - $ref: dai-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - atmel,at91sam9g45-ssc + then: + required: + - dmas + - dma-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + ssc@100000 { + compatible = "atmel,at91sam9g45-ssc"; + reg = <0x100000 0x4000>; + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(38))>, + <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(39))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; + clock-names = "pclk"; + #sound-dai-cells = <0>; + }; + + ssc@c00000 { + compatible = "atmel,at91rm9200-ssc"; + reg = <0xc00000 0x4000>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "pclk"; + }; diff --git a/Bindings/sound/atmel,at91sam9g20ek-wm8731.yaml b/Bindings/sound/atmel,at91sam9g20ek-wm8731.yaml new file mode 100644 index 00000000000..627da2d890b --- /dev/null +++ b/Bindings/sound/atmel,at91sam9g20ek-wm8731.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/atmel,at91sam9g20ek-wm8731.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel at91sam9g20ek wm8731 audio complex + +maintainers: + - Balakrishnan Sambath + +description: + The audio complex configuration for Atmel at91sam9g20ek with WM8731 audio codec. + +properties: + compatible: + const: atmel,at91sam9g20ek-wm8731-audio + + atmel,model: + $ref: /schemas/types.yaml#/definitions/string + description: The user-visible name of this sound complex. + + atmel,audio-routing: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: A list of the connections between audio components. + minItems: 2 + maxItems: 4 + items: + enum: + # Board Connectors + - Ext Spk + - Int Mic + + # CODEC Pins + - LOUT + - ROUT + - LHPOUT + - RHPOUT + - LLINEIN + - RLINEIN + - MICIN + + atmel,ssc-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the SSC controller. + + atmel,audio-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of WM8731 audio codec. + +required: + - compatible + - atmel,model + - atmel,audio-routing + - atmel,ssc-controller + - atmel,audio-codec + +additionalProperties: false + +examples: + - | + sound { + compatible = "atmel,at91sam9g20ek-wm8731-audio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pck0_as_mck>; + atmel,model = "wm8731 @ AT91SAMG20EK"; + atmel,audio-routing = + "Ext Spk", "LHPOUT", + "Int Mic", "MICIN"; + atmel,ssc-controller = <&ssc0>; + atmel,audio-codec = <&wm8731>; + }; diff --git a/Bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt b/Bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt deleted file mode 100644 index 9c5a9947b64..00000000000 --- a/Bindings/sound/atmel-at91sam9g20ek-wm8731-audio.txt +++ /dev/null @@ -1,26 +0,0 @@ -* Atmel at91sam9g20ek wm8731 audio complex - -Required properties: - - compatible: "atmel,at91sam9g20ek-wm8731-audio" - - atmel,model: The user-visible name of this sound complex. - - atmel,audio-routing: A list of the connections between audio components. - - atmel,ssc-controller: The phandle of the SSC controller - - atmel,audio-codec: The phandle of the WM8731 audio codec -Optional properties: - - pinctrl-names, pinctrl-0: Please refer to pinctrl-bindings.txt - -Example: -sound { - compatible = "atmel,at91sam9g20ek-wm8731-audio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pck0_as_mck>; - - atmel,model = "wm8731 @ AT91SAMG20EK"; - - atmel,audio-routing = - "Ext Spk", "LHPOUT", - "Int MIC", "MICIN"; - - atmel,ssc-controller = <&ssc0>; - atmel,audio-codec = <&wm8731>; -}; diff --git a/Bindings/sound/audio-graph-card2.yaml b/Bindings/sound/audio-graph-card2.yaml index f943f90d8b1..94588353f85 100644 --- a/Bindings/sound/audio-graph-card2.yaml +++ b/Bindings/sound/audio-graph-card2.yaml @@ -37,6 +37,10 @@ properties: codec2codec: type: object description: Codec to Codec node + hp-det-gpios: + $ref: audio-graph.yaml#/properties/hp-det-gpios + widgets: + $ref: audio-graph.yaml#/properties/widgets required: - compatible diff --git a/Bindings/sound/awinic,aw88395.yaml b/Bindings/sound/awinic,aw88395.yaml index 6676406bf2d..bb92d6ca314 100644 --- a/Bindings/sound/awinic,aw88395.yaml +++ b/Bindings/sound/awinic,aw88395.yaml @@ -19,6 +19,7 @@ properties: enum: - awinic,aw88081 - awinic,aw88083 + - awinic,aw88166 - awinic,aw88261 - awinic,aw88395 - awinic,aw88399 diff --git a/Bindings/sound/dmic-codec.yaml b/Bindings/sound/dmic-codec.yaml index 59ef0cf6b6e..cc3c84dd4c2 100644 --- a/Bindings/sound/dmic-codec.yaml +++ b/Bindings/sound/dmic-codec.yaml @@ -19,6 +19,9 @@ properties: '#sound-dai-cells': const: 0 + vref-supply: + description: Phandle to the digital microphone reference supply + dmicen-gpios: description: GPIO specifier for DMIC to control start and stop maxItems: 1 diff --git a/Bindings/sound/everest,es8328.yaml b/Bindings/sound/everest,es8328.yaml index ed18e40dcaa..ddddd7b143a 100644 --- a/Bindings/sound/everest,es8328.yaml +++ b/Bindings/sound/everest,es8328.yaml @@ -24,9 +24,13 @@ maintainers: properties: compatible: - enum: - - everest,es8328 - - everest,es8388 + oneOf: + - enum: + - everest,es8328 + - items: + - enum: + - everest,es8388 + - const: everest,es8328 reg: maxItems: 1 @@ -56,6 +60,7 @@ properties: required: - compatible + - reg - clocks - DVDD-supply - AVDD-supply diff --git a/Bindings/sound/fsl,audmix.yaml b/Bindings/sound/fsl,audmix.yaml index 9413b901cf7..3ad197b3c82 100644 --- a/Bindings/sound/fsl,audmix.yaml +++ b/Bindings/sound/fsl,audmix.yaml @@ -61,13 +61,26 @@ properties: - description: serial audio input 2 maxItems: 1 + ports: + $ref: /schemas/graph.yaml#/properties/ports + patternProperties: + '^port@[0-1]': + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: Input port from SAI TX + + properties: + port@2: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: Output port to SAI RX + required: - compatible - reg - clocks - clock-names - power-domains - - dais unevaluatedProperties: false @@ -80,4 +93,50 @@ examples: clock-names = "ipg"; power-domains = <&pd_audmix>; dais = <&sai4>, <&sai5>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + playback-only; + + amix_endpoint0: endpoint { + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + dai-tdm-slot-width-map = <32 8 32>; + dai-format = "dsp_a"; + remote-endpoint = <&be00_ep>; + }; + }; + + port@1 { + reg = <1>; + playback-only; + + amix_endpoint1: endpoint { + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + dai-tdm-slot-width-map = <32 8 32>; + dai-format = "dsp_a"; + remote-endpoint = <&be01_ep>; + }; + }; + + port@2 { + reg = <2>; + capture-only; + + amix_endpoint2: endpoint { + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + dai-tdm-slot-width-map = <32 8 32>; + dai-format = "dsp_a"; + bitclock-master; + frame-master; + remote-endpoint = <&be02_ep>; + }; + }; + }; }; diff --git a/Bindings/sound/fsl,easrc.yaml b/Bindings/sound/fsl,easrc.yaml index c454110f428..8f1108e7e14 100644 --- a/Bindings/sound/fsl,easrc.yaml +++ b/Bindings/sound/fsl,easrc.yaml @@ -80,7 +80,10 @@ required: - fsl,asrc-rate - fsl,asrc-format -additionalProperties: false +allOf: + - $ref: dai-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Bindings/sound/fsl,imx-asrc.yaml b/Bindings/sound/fsl,imx-asrc.yaml index 76aa1f24848..85799f83e65 100644 --- a/Bindings/sound/fsl,imx-asrc.yaml +++ b/Bindings/sound/fsl,imx-asrc.yaml @@ -77,6 +77,10 @@ properties: power-domains: maxItems: 1 + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + fsl,asrc-rate: $ref: /schemas/types.yaml#/definitions/uint32 description: The mutual sample rate used by DPCM Back Ends @@ -120,6 +124,7 @@ required: - fsl,asrc-width allOf: + - $ref: dai-common.yaml# - if: properties: compatible: @@ -145,7 +150,7 @@ allOf: required: - power-domains -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -173,4 +178,12 @@ examples: "txa", "txb", "txc"; fsl,asrc-rate = <48000>; fsl,asrc-width = <16>; + + port { + playback-only; + + asrc_endpoint: endpoint { + remote-endpoint = <&fe00_ep>; + }; + }; }; diff --git a/Bindings/sound/fsl,imx95-cm7-sof.yaml b/Bindings/sound/fsl,imx95-cm7-sof.yaml new file mode 100644 index 00000000000..f00ae3219e1 --- /dev/null +++ b/Bindings/sound/fsl,imx95-cm7-sof.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/fsl,imx95-cm7-sof.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP imx95 CM7 core + +maintainers: + - Daniel Baluta + +description: NXP imx95 CM7 core used for audio processing + +properties: + compatible: + const: fsl,imx95-cm7-sof + + reg: + maxItems: 1 + + reg-names: + const: sram + + memory-region: + maxItems: 1 + + memory-region-names: + const: dma + + port: + description: SAI3 port + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - reg-names + - memory-region + - memory-region-names + - port + +allOf: + - $ref: fsl,sof-cpu.yaml# + +unevaluatedProperties: false + +examples: + - | + cm7-cpu@80000000 { + compatible = "fsl,imx95-cm7-sof"; + reg = <0x80000000 0x6100000>; + reg-names = "sram"; + mboxes = <&mu7 2 0>, <&mu7 2 1>, <&mu7 3 0>, <&mu7 3 1>; + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; + memory-region = <&adma_res>; + memory-region-names = "dma"; + port { + /* SAI3-WM8962 link */ + endpoint { + remote-endpoint = <&wm8962_ep>; + }; + }; + }; diff --git a/Bindings/sound/fsl,sai.yaml b/Bindings/sound/fsl,sai.yaml index a5d9c246cc4..0d733e5b08a 100644 --- a/Bindings/sound/fsl,sai.yaml +++ b/Bindings/sound/fsl,sai.yaml @@ -41,6 +41,10 @@ properties: - fsl,imx93-sai - fsl,imx95-sai - fsl,vf610-sai + - items: + - enum: + - fsl,imx94-sai + - const: fsl,imx95-sai reg: maxItems: 1 @@ -93,6 +97,24 @@ properties: items: - description: receive and transmit interrupt + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: port for TX and RX + + port@1: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: port for TX only + + port@2: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + description: port for RX only + big-endian: description: | required if all the SAI registers are big-endian rather than little-endian. @@ -204,4 +226,37 @@ examples: dma-names = "rx", "tx"; fsl,dataline = <1 0xff 0xff 2 0xff 0x11>; #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + playback-only; + + sai1_endpoint0: endpoint { + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + dai-tdm-slot-width-map = <32 8 32>; + dai-format = "dsp_a"; + bitclock-master; + frame-master; + remote-endpoint = <&mcodec01_ep>; + }; + }; + + port@2 { + reg = <2>; + capture-only; + + sai1_endpoint1: endpoint { + dai-tdm-slot-num = <8>; + dai-tdm-slot-width = <32>; + dai-tdm-slot-width-map = <32 8 32>; + dai-format = "dsp_a"; + remote-endpoint = <&fe02_ep>; + }; + }; + }; }; diff --git a/Bindings/sound/fsl,sof-cpu.yaml b/Bindings/sound/fsl,sof-cpu.yaml new file mode 100644 index 00000000000..31863932dbc --- /dev/null +++ b/Bindings/sound/fsl,sof-cpu.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/fsl,sof-cpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP audio processor common properties + +maintainers: + - Daniel Baluta + +properties: + mboxes: + maxItems: 4 + + mbox-names: + items: + - const: txdb0 + - const: txdb1 + - const: rxdb0 + - const: rxdb1 + +required: + - mboxes + - mbox-names + +additionalProperties: true diff --git a/Bindings/sound/ics43432.txt b/Bindings/sound/ics43432.txt deleted file mode 100644 index e6f05f2f6c4..00000000000 --- a/Bindings/sound/ics43432.txt +++ /dev/null @@ -1,19 +0,0 @@ -Invensense ICS-43432-compatible MEMS microphone with I2S output. - -There are no software configuration options for this device, indeed, the only -host connection is the I2S interface. Apart from requirements on clock -frequency (460 kHz to 3.379 MHz according to the data sheet) there must be -64 clock cycles in each stereo output frame; 24 of the 32 available bits -contain audio data. A hardware pin determines if the device outputs data -on the left or right channel of the I2S frame. - -Required properties: - - compatible: should be one of the following. - "invensense,ics43432": For the Invensense ICS43432 - "cui,cmm-4030d-261": For the CUI CMM-4030D-261-I2S-TR - -Example: - - ics43432: ics43432 { - compatible = "invensense,ics43432"; - }; diff --git a/Bindings/sound/imx-audio-card.yaml b/Bindings/sound/imx-audio-card.yaml index f7ad5ea2491..3c75c8c7898 100644 --- a/Bindings/sound/imx-audio-card.yaml +++ b/Bindings/sound/imx-audio-card.yaml @@ -46,6 +46,14 @@ patternProperties: description: see tdm-slot.txt. $ref: /schemas/types.yaml#/definitions/uint32 + playback-only: + description: link is used only for playback + $ref: /schemas/types.yaml#/definitions/flag + + capture-only: + description: link is used only for capture + $ref: /schemas/types.yaml#/definitions/flag + cpu: description: Holds subnode which indicates cpu dai. type: object @@ -71,6 +79,12 @@ patternProperties: - link-name - cpu + allOf: + - not: + required: + - playback-only + - capture-only + additionalProperties: false required: diff --git a/Bindings/sound/invensense,ics43432.yaml b/Bindings/sound/invensense,ics43432.yaml new file mode 100644 index 00000000000..7bd984817aa --- /dev/null +++ b/Bindings/sound/invensense,ics43432.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/invensense,ics43432.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Invensense ICS-43432-compatible MEMS Microphone with I2S Output + +maintainers: + - Oleksij Rempel + +description: + The ICS-43432 and compatible MEMS microphones output audio over an I2S + interface and require no software configuration. The only host connection + is the I2S bus. The microphone requires an I2S clock frequency between + 460 kHz and 3.379 MHz and 64 clock cycles per stereo frame. Each frame + contains 32-bit slots per channel, with 24 bits carrying audio data. + A hardware pin determines whether the microphone outputs audio on the + left or right channel of the I2S frame. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - invensense,ics43432 + - cui,cmm-4030d-261 + + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + ics43432: ics43432 { + compatible = "invensense,ics43432"; + + port { + endpoint { + remote-endpoint = <&i2s1_endpoint>; + dai-format = "i2s"; + }; + }; + + }; diff --git a/Bindings/sound/mediatek,mt8188-mt6359.yaml b/Bindings/sound/mediatek,mt8188-mt6359.yaml index 362e729b51b..76d5a437dc8 100644 --- a/Bindings/sound/mediatek,mt8188-mt6359.yaml +++ b/Bindings/sound/mediatek,mt8188-mt6359.yaml @@ -40,6 +40,14 @@ properties: hardware that provides additional audio functionalities if present. The AFE will link to ADSP when the phandle is provided. + mediatek,accdet: + $ref: /schemas/types.yaml#/definitions/phandle + description: + The phandle to the MT6359 accessory detection block, which detects audio + jack insertion and removal. This property should only be present if the + accdet block is actually wired to the audio jack pins and to be used for + jack detection. + patternProperties: "^dai-link-[0-9]+$": type: object @@ -62,6 +70,7 @@ patternProperties: - PCM1_BE - DL_SRC_BE - UL_SRC_BE + - DMIC_BE codec: description: Holds subnode which indicates codec dai. diff --git a/Bindings/sound/nvidia,tegra30-hda.yaml b/Bindings/sound/nvidia,tegra30-hda.yaml index 12c31b4b99e..3ca9affb79a 100644 --- a/Bindings/sound/nvidia,tegra30-hda.yaml +++ b/Bindings/sound/nvidia,tegra30-hda.yaml @@ -28,6 +28,7 @@ properties: - nvidia,tegra186-hda - nvidia,tegra210-hda - nvidia,tegra124-hda + - nvidia,tegra114-hda - const: nvidia,tegra30-hda - items: - const: nvidia,tegra132-hda diff --git a/Bindings/sound/qcom,wcd937x-sdw.yaml b/Bindings/sound/qcom,wcd937x-sdw.yaml index d3cf8f59cb2..c8543f969eb 100644 --- a/Bindings/sound/qcom,wcd937x-sdw.yaml +++ b/Bindings/sound/qcom,wcd937x-sdw.yaml @@ -58,6 +58,40 @@ properties: items: enum: [1, 2, 3, 4, 5] + qcom,tx-channel-mapping: + description: | + Specifies static channel mapping between slave and master tx port + channels. + In the order of slave port channels which is adc1, adc2, adc3, + dmic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7. + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 12 + maxItems: 12 + additionalItems: false + items: + enum: + - 1 # WCD9370_SWRM_CH1 + - 2 # WCD9370_SWRM_CH2 + - 3 # WCD9370_SWRM_CH3 + - 4 # WCD9370_SWRM_CH4 + + qcom,rx-channel-mapping: + description: | + Specifies static channels mapping between slave and master rx port + channels. + In the order of slave port channels, which is + hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l. + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 8 + maxItems: 8 + additionalItems: false + items: + enum: + - 1 # WCD9370_SWRM_CH1 + - 2 # WCD9370_SWRM_CH2 + - 3 # WCD9370_SWRM_CH3 + - 4 # WCD9370_SWRM_CH4 + required: - compatible - reg @@ -74,6 +108,7 @@ examples: compatible = "sdw20217010a00"; reg = <0 4>; qcom,rx-port-mapping = <1 2 3 4 5>; + qcom,rx-channel-mapping = /bits/ 8 <1 2 1 1 2 1 1 2>; }; }; @@ -85,6 +120,7 @@ examples: compatible = "sdw20217010a00"; reg = <0 3>; qcom,tx-port-mapping = <2 2 3 4>; + qcom,tx-channel-mapping = /bits/ 8 <1 2 1 1 2 3 3 4 1 2 3 4>; }; }; diff --git a/Bindings/sound/rockchip-spdif.yaml b/Bindings/sound/rockchip-spdif.yaml index c3c989ef2a2..32dea7392e8 100644 --- a/Bindings/sound/rockchip-spdif.yaml +++ b/Bindings/sound/rockchip-spdif.yaml @@ -31,6 +31,10 @@ properties: - rockchip,rk3288-spdif - rockchip,rk3308-spdif - const: rockchip,rk3066-spdif + - items: + - enum: + - rockchip,rk3588-spdif + - const: rockchip,rk3568-spdif reg: maxItems: 1 diff --git a/Bindings/sound/ti,tas2770.yaml b/Bindings/sound/ti,tas2770.yaml index 5e7aea43ace..8eab98a0f7a 100644 --- a/Bindings/sound/ti,tas2770.yaml +++ b/Bindings/sound/ti,tas2770.yaml @@ -23,6 +23,7 @@ properties: compatible: enum: - ti,tas2770 + - ti,tas5770l # Apple variant reg: maxItems: 1 diff --git a/Bindings/sound/ti,tas27xx.yaml b/Bindings/sound/ti,tas27xx.yaml index 5447482179c..fcaae848e78 100644 --- a/Bindings/sound/ti,tas27xx.yaml +++ b/Bindings/sound/ti,tas27xx.yaml @@ -24,6 +24,7 @@ properties: enum: - ti,tas2764 - ti,tas2780 + - ti,sn012776 # Apple variant of TAS2764 reg: maxItems: 1 diff --git a/Bindings/sound/wlf,wm8904.yaml b/Bindings/sound/wlf,wm8904.yaml index 329260cf0fa..3029a868e5e 100644 --- a/Bindings/sound/wlf,wm8904.yaml +++ b/Bindings/sound/wlf,wm8904.yaml @@ -38,6 +38,82 @@ properties: DCVDD-supply: true MICVDD-supply: true + wlf,in1l-as-dmicdat1: + type: boolean + description: + Use IN1L/DMICDAT1 as DMICDAT1, enabling the DMIC input path. + Can be used separately or together with wlf,in1r-as-dmicdat2. + + wlf,in1r-as-dmicdat2: + type: boolean + description: + Use IN1R/DMICDAT2 as DMICDAT2, enabling the DMIC input path. + Can be used separately or together with wlf,in1l-as-dmicdat1. + + wlf,gpio-cfg: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 4 + maxItems: 4 + description: + Default register values for R121/122/123/124 (GPIO Control). + If any entry has the value 0xFFFF, the related register won't be set. + default: [0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF] + + wlf,micbias-cfg: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + description: + Default register values for R6/R7 (Mic Bias Control). + default: [0, 0] + + wlf,drc-cfg-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: + List of strings for the available DRC modes. + If absent, DRC is disabled. + + wlf,drc-cfg-regs: + $ref: /schemas/types.yaml#/definitions/uint16-matrix + description: + Sets of default register values for R40/41/42/43 (DRC). + Each set corresponds to a DRC mode, so the number of sets should equal + the length of wlf,drc-cfg-names. + If absent, DRC is disabled. + items: + minItems: 4 + maxItems: 4 + + wlf,retune-mobile-cfg-names: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + description: + List of strings for the available retune modes. + If absent, retune is disabled. + + wlf,retune-mobile-cfg-hz: + description: + The list must be the same length as wlf,retune-mobile-cfg-names. + If absent, retune is disabled. + + wlf,retune-mobile-cfg-regs: + $ref: /schemas/types.yaml#/definitions/uint16-matrix + description: + Sets of default register values for R134/.../157 (EQ). + Each set corresponds to a retune mode, so the number of sets should equal + the length of wlf,retune-mobile-cfg-names. + If absent, retune is disabled. + items: + minItems: 24 + maxItems: 24 + +dependencies: + wlf,drc-cfg-names: [ 'wlf,drc-cfg-regs' ] + wlf,drc-cfg-regs: [ 'wlf,drc-cfg-names' ] + + wlf,retune-mobile-cfg-names: [ 'wlf,retune-mobile-cfg-hz', 'wlf,retune-mobile-cfg-regs' ] + wlf,retune-mobile-cfg-regs: [ 'wlf,retune-mobile-cfg-names', 'wlf,retune-mobile-cfg-hz' ] + wlf,retune-mobile-cfg-hz: [ 'wlf,retune-mobile-cfg-names', 'wlf,retune-mobile-cfg-regs' ] + required: - compatible - reg @@ -70,5 +146,58 @@ examples: DBVDD-supply = <®_1p8v>; DCVDD-supply = <®_1p8v>; MICVDD-supply = <®_1p8v>; + + wlf,drc-cfg-names = "default", "peaklimiter", "tradition", "soft", + "music"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1 + * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1 + * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>, + /bits/ 16 <0x04af 0x324b 0x0028 0x0704>, + /bits/ 16 <0x04af 0x324b 0x0018 0x078c>, + /bits/ 16 <0x04af 0x324b 0x0010 0x050e>; + + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + + /* Use IN1R as DMICDAT2, leave IN1L as an analog input path */ + wlf,in1r-as-dmicdat2; + + wlf,retune-mobile-cfg-names = "bassboost", "bassboost", "treble"; + wlf,retune-mobile-cfg-hz = <48000>, <44100>, <48000>; + /* + * Config registers per name, respectively: + * EQ_ENA, 100 Hz, 300 Hz, 875 Hz, 2400 Hz, 6900 Hz + * 1, +6 dB, +3 dB, 0 dB, 0 dB, 0 dB + * 1, +6 dB, +3 dB, 0 dB, 0 dB, 0 dB + * 1, -2 dB, -2 dB, 0 dB, 0 dB, +3 dB + * Each one uses the defaults for ReTune Mobile registers 140-157 + */ + wlf,retune-mobile-cfg-regs = /bits/ 16 <0x1 0x12 0xf 0xc 0xc 0xc + 0x0fca 0x0400 0x00d8 0x1eb5 + 0xf145 0x0bd5 0x0075 0x1c58 + 0xf3d3 0x0a54 0x0568 0x168e + 0xf829 0x07ad 0x1103 0x0564 + 0x0559 0x4000>, + + /bits/ 16 <0x1 0x12 0xf 0xc 0xc 0xc + 0x0fca 0x0400 0x00d8 0x1eb5 + 0xf145 0x0bd5 0x0075 0x1c58 + 0xf3d3 0x0a54 0x0568 0x168e + 0xf829 0x07ad 0x1103 0x0564 + 0x0559 0x4000>, + + /bits/ 16 <0x1 0xa 0xa 0xc 0xc 0xf + 0x0fca 0x0400 0x00d8 0x1eb5 + 0xf145 0x0bd5 0x0075 0x1c58 + 0xf3d3 0x0a54 0x0568 0x168e + 0xf829 0x07ad 0x1103 0x0564 + 0x0559 0x4000>; }; }; diff --git a/Bindings/sound/wlf,wm8960.yaml b/Bindings/sound/wlf,wm8960.yaml index 62e62c335d0..3c2b9790ffc 100644 --- a/Bindings/sound/wlf,wm8960.yaml +++ b/Bindings/sound/wlf,wm8960.yaml @@ -75,6 +75,10 @@ properties: enable DACLRC pin. If shared-lrclk is present, no need to enable DAC for captrue. + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible - reg diff --git a/Bindings/sound/xlnx,audio-formatter.txt b/Bindings/sound/xlnx,audio-formatter.txt deleted file mode 100644 index cbc93c8f496..00000000000 --- a/Bindings/sound/xlnx,audio-formatter.txt +++ /dev/null @@ -1,29 +0,0 @@ -Device-Tree bindings for Xilinx PL audio formatter - -The IP core supports DMA, data formatting(AES<->PCM conversion) -of audio samples. - -Required properties: - - compatible: "xlnx,audio-formatter-1.0" - - interrupt-names: Names specified to list of interrupts in same - order mentioned under "interrupts". - List of supported interrupt names are: - "irq_mm2s" : interrupt from MM2S block - "irq_s2mm" : interrupt from S2MM block - - interrupts-parent: Phandle for interrupt controller. - - interrupts: List of Interrupt numbers. - - reg: Base address and size of the IP core instance. - - clock-names: List of input clocks. - Required elements: "s_axi_lite_aclk", "aud_mclk" - - clocks: Input clock specifier. Refer to common clock bindings. - -Example: - audio_ss_0_audio_formatter_0: audio_formatter@80010000 { - compatible = "xlnx,audio-formatter-1.0"; - interrupt-names = "irq_mm2s", "irq_s2mm"; - interrupt-parent = <&gic>; - interrupts = <0 104 4>, <0 105 4>; - reg = <0x0 0x80010000 0x0 0x1000>; - clock-names = "s_axi_lite_aclk", "aud_mclk"; - clocks = <&clk 71>, <&clk_wiz_1 0>; - }; diff --git a/Bindings/sound/xlnx,audio-formatter.yaml b/Bindings/sound/xlnx,audio-formatter.yaml new file mode 100644 index 00000000000..82fa448bd2e --- /dev/null +++ b/Bindings/sound/xlnx,audio-formatter.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/xlnx,audio-formatter.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx PL audio formatter + +description: + The IP core supports DMA, data formatting(AES<->PCM conversion) + of audio samples. + +maintainers: + - Vincenzo Frascino + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - xlnx,audio-formatter-1.0 + + reg: + maxItems: 1 + + interrupt-names: + minItems: 1 + items: + - const: irq_mm2s + - const: irq_s2mm + + interrupts: + minItems: 1 + items: + - description: interrupt from MM2S block + - description: interrupt from S2MM block + + clock-names: + minItems: 1 + items: + - const: s_axi_lite_aclk + - const: aud_mclk + + clocks: + minItems: 1 + items: + - description: clock for the axi data stream + - description: clock for the MEMS microphone data stream + +required: + - compatible + - reg + - interrupt-names + - interrupts + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + audio_formatter@80010000 { + compatible = "xlnx,audio-formatter-1.0"; + reg = <0x80010000 0x1000>; + interrupt-names = "irq_mm2s", "irq_s2mm"; + interrupt-parent = <&gic>; + interrupts = <0 104 4>, <0 105 4>; + clock-names = "s_axi_lite_aclk", "aud_mclk"; + clocks = <&clk 71>, <&clk_wiz_1 0>; + }; +... diff --git a/Bindings/sound/xlnx,i2s.txt b/Bindings/sound/xlnx,i2s.txt deleted file mode 100644 index 5e7c7d5bb60..00000000000 --- a/Bindings/sound/xlnx,i2s.txt +++ /dev/null @@ -1,28 +0,0 @@ -Device-Tree bindings for Xilinx I2S PL block - -The IP supports I2S based playback/capture audio - -Required property: - - compatible: "xlnx,i2s-transmitter-1.0" for playback and - "xlnx,i2s-receiver-1.0" for capture - -Required property common to both I2S playback and capture: - - reg: Base address and size of the IP core instance. - - xlnx,dwidth: sample data width. Can be any of 16, 24. - - xlnx,num-channels: Number of I2S streams. Can be any of 1, 2, 3, 4. - supported channels = 2 * xlnx,num-channels - -Example: - - i2s_receiver@a0080000 { - compatible = "xlnx,i2s-receiver-1.0"; - reg = <0x0 0xa0080000 0x0 0x10000>; - xlnx,dwidth = <0x18>; - xlnx,num-channels = <1>; - }; - i2s_transmitter@a0090000 { - compatible = "xlnx,i2s-transmitter-1.0"; - reg = <0x0 0xa0090000 0x0 0x10000>; - xlnx,dwidth = <0x18>; - xlnx,num-channels = <1>; - }; diff --git a/Bindings/sound/xlnx,i2s.yaml b/Bindings/sound/xlnx,i2s.yaml new file mode 100644 index 00000000000..3c2b0be07c5 --- /dev/null +++ b/Bindings/sound/xlnx,i2s.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/xlnx,i2s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx I2S PL block + +description: + The IP supports I2S based playback/capture audio. + +maintainers: + - Vincenzo Frascino + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - xlnx,i2s-receiver-1.0 + - xlnx,i2s-transmitter-1.0 + + reg: + maxItems: 1 + + xlnx,dwidth: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 16 + - 24 + description: | + Sample data width. + + xlnx,num-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 4 + description: | + Number of I2S streams. + +required: + - compatible + - reg + - xlnx,dwidth + - xlnx,num-channels + +additionalProperties: false + +examples: + - | + i2s@a0080000 { + compatible = "xlnx,i2s-receiver-1.0"; + reg = <0xa0080000 0x10000>; + xlnx,dwidth = <0x18>; + xlnx,num-channels = <1>; + }; + i2s@a0090000 { + compatible = "xlnx,i2s-transmitter-1.0"; + reg = <0xa0090000 0x10000>; + xlnx,dwidth = <0x18>; + xlnx,num-channels = <1>; + }; + +... diff --git a/Bindings/sound/xlnx,spdif.txt b/Bindings/sound/xlnx,spdif.txt deleted file mode 100644 index 15c2d64d247..00000000000 --- a/Bindings/sound/xlnx,spdif.txt +++ /dev/null @@ -1,28 +0,0 @@ -Device-Tree bindings for Xilinx SPDIF IP - -The IP supports playback and capture of SPDIF audio - -Required properties: - - compatible: "xlnx,spdif-2.0" - - clock-names: List of input clocks. - Required elements: "s_axi_aclk", "aud_clk_i" - - clocks: Input clock specifier. Refer to common clock bindings. - - reg: Base address and address length of the IP core instance. - - interrupts-parent: Phandle for interrupt controller. - - interrupts: List of Interrupt numbers. - - xlnx,spdif-mode: 0 :- receiver mode - 1 :- transmitter mode - - xlnx,aud_clk_i: input audio clock value. - -Example: - spdif_0: spdif@80010000 { - clock-names = "aud_clk_i", "s_axi_aclk"; - clocks = <&misc_clk_0>, <&clk 71>; - compatible = "xlnx,spdif-2.0"; - interrupt-names = "spdif_interrupt"; - interrupt-parent = <&gic>; - interrupts = <0 91 4>; - reg = <0x0 0x80010000 0x0 0x10000>; - xlnx,spdif-mode = <1>; - xlnx,aud_clk_i = <49152913>; - }; diff --git a/Bindings/sound/xlnx,spdif.yaml b/Bindings/sound/xlnx,spdif.yaml new file mode 100644 index 00000000000..a45d8a0755f --- /dev/null +++ b/Bindings/sound/xlnx,spdif.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/xlnx,spdif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx SPDIF IP + +description: + The IP supports playback and capture of SPDIF audio. + +maintainers: + - Vincenzo Frascino + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - xlnx,spdif-2.0 + + reg: + maxItems: 1 + + interrupts: + items: + - description: SPDIF audio interrupt + + clock-names: + items: + - const: aud_clk_i + - const: s_axi_aclk + + clocks: + minItems: 1 + items: + - description: input audio clock + - description: clock for the AXI data stream + + xlnx,spdif-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 + - 1 + description: | + 0 - receiver + 1 - transmitter + + xlnx,aud_clk_i: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Input audio clock frequency. It affects the sampling rate. + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + +additionalProperties: false + +examples: + - | + spdif@80010000 { + compatible = "xlnx,spdif-2.0"; + reg = <0x80010000 0x10000>; + clock-names = "aud_clk_i", "s_axi_aclk"; + clocks = <&misc_clk_0>, <&clk 71>; + interrupt-parent = <&gic>; + interrupts = <0 91 4>; + xlnx,spdif-mode = <1>; + xlnx,aud_clk_i = <49152913>; + }; + +... diff --git a/Bindings/spi/adi,axi-spi-engine.yaml b/Bindings/spi/adi,axi-spi-engine.yaml index d48faa42d02..4b3828eda6c 100644 --- a/Bindings/spi/adi,axi-spi-engine.yaml +++ b/Bindings/spi/adi,axi-spi-engine.yaml @@ -41,6 +41,26 @@ properties: - const: s_axi_aclk - const: spi_clk + trigger-sources: + description: + An array of trigger source phandles for offload instances. The index in + the array corresponds to the offload instance number. + minItems: 1 + maxItems: 32 + + dmas: + description: + DMA channels connected to the input or output stream interface of an + offload instance. + minItems: 1 + maxItems: 32 + + dma-names: + items: + pattern: "^offload(?:[12]?[0-9]|3[01])-[tr]x$" + minItems: 1 + maxItems: 32 + required: - compatible - reg @@ -59,6 +79,10 @@ examples: clocks = <&clkc 15>, <&clkc 15>; clock-names = "s_axi_aclk", "spi_clk"; + trigger-sources = <&trigger_clock>; + dmas = <&dma 0>; + dma-names = "offload0-rx"; + #address-cells = <1>; #size-cells = <0>; diff --git a/Bindings/spi/cdns,qspi-nor.yaml b/Bindings/spi/cdns,qspi-nor.yaml index b6bc71d1928..53a52fb8b81 100644 --- a/Bindings/spi/cdns,qspi-nor.yaml +++ b/Bindings/spi/cdns,qspi-nor.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Cadence Quad SPI controller +title: Cadence Quad/Octal SPI controller maintainers: - Vaishnav Achath @@ -76,8 +76,12 @@ properties: - ti,am654-ospi - ti,k2g-qspi - xlnx,versal-ospi-1.0 + # The compatible is qspi-nor for historical reasons but such + # controllers are meant to be used with flashes of all kinds, + # ie. also NAND flashes, not only NOR flashes. - const: cdns,qspi-nor - const: cdns,qspi-nor + deprecated: true reg: items: @@ -142,6 +146,18 @@ properties: items: enum: [ qspi, qspi-ocp, rstc_ref ] +patternProperties: + "^flash@[0-9a-f]+$": + type: object + $ref: cdns,qspi-nor-peripheral-props.yaml + additionalProperties: true + required: + - cdns,read-delay + - cdns,tshsl-ns + - cdns,tsd2d-ns + - cdns,tchsh-ns + - cdns,tslch-ns + required: - compatible - reg @@ -157,7 +173,7 @@ unevaluatedProperties: false examples: - | qspi: spi@ff705000 { - compatible = "cdns,qspi-nor"; + compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; #address-cells = <1>; #size-cells = <0>; reg = <0xff705000 0x1000>, @@ -173,5 +189,10 @@ examples: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; + cdns,read-delay = <4>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; }; }; diff --git a/Bindings/spi/fsl,espi.yaml b/Bindings/spi/fsl,espi.yaml new file mode 100644 index 00000000000..d267bbfaf02 --- /dev/null +++ b/Bindings/spi/fsl,espi.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/fsl,espi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale eSPI (Enhanced Serial Peripheral Interface) controller + +maintainers: + - J. Neuschäfer + +properties: + compatible: + const: fsl,mpc8536-espi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + fsl,espi-num-chipselects: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 1, 4 ] + description: The number of the chipselect signals. + + fsl,csbef: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: Chip select assertion time in bits before frame starts + + fsl,csaft: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + description: Chip select negation time in bits after frame ends + +required: + - compatible + - reg + - interrupts + - fsl,espi-num-chipselects + +allOf: + - $ref: spi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi@110000 { + compatible = "fsl,mpc8536-espi"; + reg = <0x110000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <53 IRQ_TYPE_EDGE_FALLING>; + fsl,espi-num-chipselects = <4>; + fsl,csbef = <1>; + fsl,csaft = <1>; + }; + +... diff --git a/Bindings/spi/fsl,spi.yaml b/Bindings/spi/fsl,spi.yaml new file mode 100644 index 00000000000..d74792fc9bf --- /dev/null +++ b/Bindings/spi/fsl,spi.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/fsl,spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale SPI (Serial Peripheral Interface) controller + +maintainers: + - J. Neuschäfer + +properties: + compatible: + enum: + - fsl,spi + - aeroflexgaisler,spictrl + + reg: + maxItems: 1 + + cell-index: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + QE SPI subblock index. + 0: QE subblock SPI1 + 1: QE subblock SPI2 + + mode: + description: SPI operation mode + enum: + - cpu + - cpu-qe + + interrupts: + maxItems: 1 + + clock-frequency: + description: input clock frequency to non FSL_SOC cores + + cs-gpios: true + + fsl,spisel_boot: + $ref: /schemas/types.yaml#/definitions/flag + description: + For the MPC8306 and MPC8309, specifies that the SPISEL_BOOT signal is used + as chip select for a slave device. Use reg = in the + corresponding child node, i.e. 0 if the cs-gpios property is not present. + +required: + - compatible + - reg + - mode + - interrupts + +allOf: + - $ref: spi-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi@4c0 { + compatible = "fsl,spi"; + reg = <0x4c0 0x40>; + cell-index = <0>; + interrupts = <82 0>; + mode = "cpu"; + cs-gpios = <&gpio 18 IRQ_TYPE_EDGE_RISING // device reg=<0> + &gpio 19 IRQ_TYPE_EDGE_RISING>; // device reg=<1> + }; + +... diff --git a/Bindings/spi/fsl-spi.txt b/Bindings/spi/fsl-spi.txt deleted file mode 100644 index 0654380eb75..00000000000 --- a/Bindings/spi/fsl-spi.txt +++ /dev/null @@ -1,62 +0,0 @@ -* SPI (Serial Peripheral Interface) - -Required properties: -- cell-index : QE SPI subblock index. - 0: QE subblock SPI1 - 1: QE subblock SPI2 -- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl". -- mode : the SPI operation mode, it can be "cpu" or "cpu-qe". -- reg : Offset and length of the register set for the device -- interrupts : where a is the interrupt number and b is a - field that represents an encoding of the sense and level - information for the interrupt. This should be encoded based on - the information in section 2) depending on the type of interrupt - controller you have. -- clock-frequency : input clock frequency to non FSL_SOC cores - -Optional properties: -- cs-gpios : specifies the gpio pins to be used for chipselects. - The gpios will be referred to as reg = in the SPI child nodes. - If unspecified, a single SPI device without a chip select can be used. -- fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the - SPISEL_BOOT signal is used as chip select for a slave device. Use - reg = in the corresponding child node, i.e. 0 if - the cs-gpios property is not present. - -Example: - spi@4c0 { - cell-index = <0>; - compatible = "fsl,spi"; - reg = <4c0 40>; - interrupts = <82 0>; - interrupt-parent = <700>; - mode = "cpu"; - cs-gpios = <&gpio 18 1 // device reg=<0> - &gpio 19 1>; // device reg=<1> - }; - - -* eSPI (Enhanced Serial Peripheral Interface) - -Required properties: -- compatible : should be "fsl,mpc8536-espi". -- reg : Offset and length of the register set for the device. -- interrupts : should contain eSPI interrupt, the device has one interrupt. -- fsl,espi-num-chipselects : the number of the chipselect signals. - -Optional properties: -- fsl,csbef: chip select assertion time in bits before frame starts -- fsl,csaft: chip select negation time in bits after frame ends - -Example: - spi@110000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mpc8536-espi"; - reg = <0x110000 0x1000>; - interrupts = <53 0x2>; - interrupt-parent = <&mpic>; - fsl,espi-num-chipselects = <4>; - fsl,csbef = <1>; - fsl,csaft = <1>; - }; diff --git a/Bindings/spi/mediatek,spi-mt65xx.yaml b/Bindings/spi/mediatek,spi-mt65xx.yaml index e1f5bfa4433..ed17815263a 100644 --- a/Bindings/spi/mediatek,spi-mt65xx.yaml +++ b/Bindings/spi/mediatek,spi-mt65xx.yaml @@ -35,6 +35,8 @@ properties: - enum: - mediatek,mt7981-spi-ipm - mediatek,mt7986-spi-ipm + - mediatek,mt7988-spi-quad + - mediatek,mt7988-spi-single - mediatek,mt8188-spi-ipm - const: mediatek,spi-ipm - items: diff --git a/Bindings/spi/qcom,spi-qpic-snand.yaml b/Bindings/spi/qcom,spi-qpic-snand.yaml new file mode 100644 index 00000000000..aa3f9331920 --- /dev/null +++ b/Bindings/spi/qcom,spi-qpic-snand.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QPIC NAND controller + +maintainers: + - Md sadre Alam + +description: + The QCOM QPIC-SPI-NAND flash controller is an extended version of + the QCOM QPIC NAND flash controller. It can work both in serial + and parallel mode. It supports typical SPI-NAND page cache + operations in single, dual or quad IO mode with pipelined ECC + encoding/decoding using the QPIC ECC HW engine. + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + enum: + - qcom,ipq9574-snand + + reg: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: core + - const: aon + - const: iom + + dmas: + items: + - description: tx DMA channel + - description: rx DMA channel + - description: cmd DMA channel + + dma-names: + items: + - const: tx + - const: rx + - const: cmd + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + spi@79b0000 { + compatible = "qcom,ipq9574-snand"; + reg = <0x1ac00000 0x800>; + + clocks = <&gcc GCC_QPIC_CLK>, + <&gcc GCC_QPIC_AHB_CLK>, + <&gcc GCC_QPIC_IO_MACRO_CLK>; + clock-names = "core", "aon", "iom"; + + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-engine = <&qpic_nand>; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + }; + }; diff --git a/Bindings/spi/snps,dw-apb-ssi.yaml b/Bindings/spi/snps,dw-apb-ssi.yaml index bccd00a1ddd..53d00ca643b 100644 --- a/Bindings/spi/snps,dw-apb-ssi.yaml +++ b/Bindings/spi/snps,dw-apb-ssi.yaml @@ -56,19 +56,18 @@ properties: enum: - snps,dw-apb-ssi - snps,dwc-ssi-1.01a - - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller - items: - - enum: - - mscc,ocelot-spi - - mscc,jaguar2-spi - - const: snps,dw-apb-ssi - description: Microchip Sparx5 SoC SPI Controller const: microchip,sparx5-spi - description: Amazon Alpine SPI Controller const: amazon,alpine-dw-apb-ssi - - description: Renesas RZ/N1 SPI Controller + - description: Vendor controllers which use snps,dw-apb-ssi as fallback items: - - const: renesas,rzn1-spi + - enum: + - mscc,ocelot-spi + - mscc,jaguar2-spi + - renesas,rzn1-spi + - sophgo,sg2042-spi + - thead,th1520-spi - const: snps,dw-apb-ssi - description: Intel Keem Bay SPI Controller const: intel,keembay-ssi @@ -88,10 +87,6 @@ properties: - renesas,r9a06g032-spi # RZ/N1D - renesas,r9a06g033-spi # RZ/N1S - const: renesas,rzn1-spi # RZ/N1 - - description: T-HEAD TH1520 SoC SPI Controller - items: - - const: thead,th1520-spi - - const: snps,dw-apb-ssi reg: minItems: 1 diff --git a/Bindings/spi/spi-fsl-lpspi.yaml b/Bindings/spi/spi-fsl-lpspi.yaml index ed1d4aa41b8..a65a42ccaaf 100644 --- a/Bindings/spi/spi-fsl-lpspi.yaml +++ b/Bindings/spi/spi-fsl-lpspi.yaml @@ -24,6 +24,7 @@ properties: - enum: - fsl,imx8ulp-spi - fsl,imx93-spi + - fsl,imx94-spi - fsl,imx95-spi - const: fsl,imx7ulp-spi reg: diff --git a/Bindings/spi/spi-rockchip.yaml b/Bindings/spi/spi-rockchip.yaml index 46d9d6ee092..104f5ffdd04 100644 --- a/Bindings/spi/spi-rockchip.yaml +++ b/Bindings/spi/spi-rockchip.yaml @@ -34,6 +34,7 @@ properties: - rockchip,rk3328-spi - rockchip,rk3368-spi - rockchip,rk3399-spi + - rockchip,rk3562-spi - rockchip,rk3568-spi - rockchip,rk3576-spi - rockchip,rk3588-spi diff --git a/Bindings/spi/spi-sg2044-nor.yaml b/Bindings/spi/spi-sg2044-nor.yaml new file mode 100644 index 00000000000..948ff7a0964 --- /dev/null +++ b/Bindings/spi/spi-sg2044-nor.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/spi-sg2044-nor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SG2044 SPI NOR controller + +maintainers: + - Longbin Li + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + const: sophgo,sg2044-spifmc-nor + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + - resets + +unevaluatedProperties: false + +examples: + - | + #include + + spi@1000000 { + compatible = "sophgo,sg2044-spifmc-nor"; + reg = <0x1000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk 0>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rst 0>; + }; diff --git a/Bindings/spi/spi-zynqmp-qspi.yaml b/Bindings/spi/spi-zynqmp-qspi.yaml index 04d4d3b4916..02cf1314367 100644 --- a/Bindings/spi/spi-zynqmp-qspi.yaml +++ b/Bindings/spi/spi-zynqmp-qspi.yaml @@ -65,14 +65,13 @@ allOf: examples: - | - #include soc { #address-cells = <2>; #size-cells = <2>; qspi: spi@ff0f0000 { compatible = "xlnx,zynqmp-qspi-1.0"; - clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; + clocks = <&zynqmp_clk 53>, <&zynqmp_clk 82>; clock-names = "ref_clk", "pclk"; interrupts = <0 15 4>; interrupt-parent = <&gic>; diff --git a/Bindings/spi/st,stm32mp25-ospi.yaml b/Bindings/spi/st,stm32mp25-ospi.yaml new file mode 100644 index 00000000000..5f276f27dc4 --- /dev/null +++ b/Bindings/spi/st,stm32mp25-ospi.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/st,stm32mp25-ospi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32 Octal Serial Peripheral Interface (OSPI) + +maintainers: + - Patrice Chotard + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + const: st,stm32mp25-ospi + + reg: + maxItems: 1 + + memory-region: + description: + Memory region to be used for memory-map read access. + In memory-mapped mode, read access are performed from the memory + device using the direct mapping. + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + resets: + items: + - description: phandle to OSPI block reset + - description: phandle to delay block reset + + dmas: + maxItems: 2 + + dma-names: + items: + - const: tx + - const: rx + + st,syscfg-dlyb: + description: configure OCTOSPI delay block. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - description: phandle to syscfg + - description: register offset within syscfg + + access-controllers: + description: phandle to the rifsc device to check access right + and in some cases, an additional phandle to the rcc device for + secure clock control. + items: + - description: phandle to bus controller + - description: phandle to clock controller + minItems: 1 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - interrupts + - st,syscfg-dlyb + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + spi@40430000 { + compatible = "st,stm32mp25-ospi"; + reg = <0x40430000 0x400>; + memory-region = <&mm_ospi1>; + interrupts = ; + dmas = <&hpdma 2 0x62 0x00003121 0x0>, + <&hpdma 2 0x42 0x00003112 0x0>; + dma-names = "tx", "rx"; + clocks = <&scmi_clk CK_SCMI_OSPI1>; + resets = <&scmi_reset RST_SCMI_OSPI1>, <&scmi_reset RST_SCMI_OSPI1DLL>; + access-controllers = <&rifsc 74>; + power-domains = <&CLUSTER_PD>; + st,syscfg-dlyb = <&syscfg 0x1000>; + + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + }; + }; diff --git a/Bindings/submitting-patches.rst b/Bindings/submitting-patches.rst index a64f21a5f29..f3e23e69a63 100644 --- a/Bindings/submitting-patches.rst +++ b/Bindings/submitting-patches.rst @@ -54,11 +54,22 @@ I. For patch submitters followed as of commit bff5da4335256513497cc8c79f9a9d1665e09864 ("checkpatch: add DT compatible string documentation checks"). ] - 7) If a documented compatible string is not yet matched by the + 7) DTS is treated in general as driver-independent hardware description, thus + any DTS patches, regardless whether using existing or new bindings, should + be placed at the end of patchset to indicate no dependency of drivers on + the DTS. DTS will be anyway applied through separate tree or branch, so + different order would indicate the serie is non-bisectable. + + If a driver subsystem maintainer prefers to apply entire set, instead of + their relevant portion of patchset, please split the DTS patches into + separate patchset with a reference in changelog or cover letter to the + bindings submission on the mailing list. + + 8) If a documented compatible string is not yet matched by the driver, the documentation should also include a compatible string that is matched by the driver. - 8) Bindings are actively used by multiple projects other than the Linux + 9) Bindings are actively used by multiple projects other than the Linux Kernel, extra care and consideration may need to be taken when making changes to existing bindings. @@ -79,6 +90,10 @@ II. For kernel maintainers 3) For a series going though multiple trees, the binding patch should be kept with the driver using the binding. + 4) The DTS files should however never be applied via driver subsystem tree, + but always via platform SoC trees on dedicated branches (see also + Documentation/process/maintainer-soc.rst). + III. Notes ========== diff --git a/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml index dad8de90049..3e61689f6dd 100644 --- a/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml +++ b/Bindings/thermal/allwinner,sun8i-a83t-ths.yaml @@ -142,38 +142,38 @@ unevaluatedProperties: false examples: - | thermal-sensor@1f04000 { - compatible = "allwinner,sun8i-a83t-ths"; - reg = <0x01f04000 0x100>; - interrupts = <0 31 0>; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <1>; + compatible = "allwinner,sun8i-a83t-ths"; + reg = <0x01f04000 0x100>; + interrupts = <0 31 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; }; - | thermal-sensor@1c25000 { - compatible = "allwinner,sun8i-h3-ths"; - reg = <0x01c25000 0x400>; - clocks = <&ccu 0>, <&ccu 1>; - clock-names = "bus", "mod"; - resets = <&ccu 2>; - interrupts = <0 31 0>; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <0>; + compatible = "allwinner,sun8i-h3-ths"; + reg = <0x01c25000 0x400>; + clocks = <&ccu 0>, <&ccu 1>; + clock-names = "bus", "mod"; + resets = <&ccu 2>; + interrupts = <0 31 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <0>; }; - | thermal-sensor@5070400 { - compatible = "allwinner,sun50i-h6-ths"; - reg = <0x05070400 0x100>; - clocks = <&ccu 0>; - clock-names = "bus"; - resets = <&ccu 2>; - interrupts = <0 15 0>; - nvmem-cells = <&ths_calibration>; - nvmem-cell-names = "calibration"; - #thermal-sensor-cells = <1>; + compatible = "allwinner,sun50i-h6-ths"; + reg = <0x05070400 0x100>; + clocks = <&ccu 0>; + clock-names = "bus"; + resets = <&ccu 2>; + interrupts = <0 15 0>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + #thermal-sensor-cells = <1>; }; ... diff --git a/Bindings/thermal/brcm,avs-tmon.yaml b/Bindings/thermal/brcm,avs-tmon.yaml index 081486b4438..2f62551a49c 100644 --- a/Bindings/thermal/brcm,avs-tmon.yaml +++ b/Bindings/thermal/brcm,avs-tmon.yaml @@ -18,6 +18,7 @@ properties: compatible: items: - enum: + - brcm,avs-tmon-bcm74110 - brcm,avs-tmon-bcm7216 - brcm,avs-tmon-bcm7445 - const: brcm,avs-tmon diff --git a/Bindings/thermal/imx-thermal.yaml b/Bindings/thermal/imx-thermal.yaml index 33756056233..949b154856c 100644 --- a/Bindings/thermal/imx-thermal.yaml +++ b/Bindings/thermal/imx-thermal.yaml @@ -80,19 +80,19 @@ examples: #include efuse@21bc000 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "fsl,imx6sx-ocotp", "syscon"; - reg = <0x021bc000 0x4000>; - clocks = <&clks IMX6SX_CLK_OCOTP>; - - tempmon_calib: calib@38 { - reg = <0x38 4>; - }; - - tempmon_temp_grade: temp-grade@20 { - reg = <0x20 4>; - }; + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,imx6sx-ocotp", "syscon"; + reg = <0x021bc000 0x4000>; + clocks = <&clks IMX6SX_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; anatop@20c8000 { @@ -103,12 +103,12 @@ examples: <0 127 IRQ_TYPE_LEVEL_HIGH>; tempmon { - compatible = "fsl,imx6sx-tempmon"; - interrupts = ; - fsl,tempmon = <&anatop>; - nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; - nvmem-cell-names = "calib", "temp_grade"; - clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; - #thermal-sensor-cells = <0>; + compatible = "fsl,imx6sx-tempmon"; + interrupts = ; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; + #thermal-sensor-cells = <0>; }; }; diff --git a/Bindings/thermal/imx8mm-thermal.yaml b/Bindings/thermal/imx8mm-thermal.yaml index bef0e95e741..df6c7c5d519 100644 --- a/Bindings/thermal/imx8mm-thermal.yaml +++ b/Bindings/thermal/imx8mm-thermal.yaml @@ -63,10 +63,10 @@ examples: #include thermal-sensor@30260000 { - compatible = "fsl,imx8mm-tmu"; - reg = <0x30260000 0x10000>; - clocks = <&clk IMX8MM_CLK_TMU_ROOT>; - #thermal-sensor-cells = <0>; + compatible = "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; }; ... diff --git a/Bindings/thermal/qcom-tsens.yaml b/Bindings/thermal/qcom-tsens.yaml index b9829bb22cc..f9d8012c8cf 100644 --- a/Bindings/thermal/qcom-tsens.yaml +++ b/Bindings/thermal/qcom-tsens.yaml @@ -75,6 +75,8 @@ properties: - description: v2 of TSENS with combined interrupt enum: + - qcom,ipq5332-tsens + - qcom,ipq5424-tsens - qcom,ipq8074-tsens - description: v2 of TSENS with combined interrupt @@ -212,6 +214,18 @@ properties: - const: s9_p2_backup - const: s10_p1_backup - const: s10_p2_backup + - minItems: 8 + items: + - const: mode + - const: base0 + - const: base1 + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' + - pattern: '^tsens_sens[0-9]+_off$' "#qcom,sensors": description: @@ -271,6 +285,8 @@ allOf: compatible: contains: enum: + - qcom,ipq5332-tsens + - qcom,ipq5424-tsens - qcom,ipq8074-tsens then: properties: @@ -286,6 +302,8 @@ allOf: compatible: contains: enum: + - qcom,ipq5332-tsens + - qcom,ipq5424-tsens - qcom,ipq8074-tsens - qcom,tsens-v0_1 - qcom,tsens-v1 diff --git a/Bindings/thermal/thermal-zones.yaml b/Bindings/thermal/thermal-zones.yaml index 0f435be1dbd..0de0a9757cc 100644 --- a/Bindings/thermal/thermal-zones.yaml +++ b/Bindings/thermal/thermal-zones.yaml @@ -82,9 +82,8 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/string description: | The action the OS should perform after the critical temperature is reached. - By default the system will shutdown as a safe action to prevent damage - to the hardware, if the property is not set. - The shutdown action should be always the default and preferred one. + If the property is not set, it is up to the system to select the correct + action. The recommended and preferred default is shutdown. Choose 'reboot' with care, as the hardware may be in thermal stress, thus leading to infinite reboots that may cause damage to the hardware. Make sure the firmware/bootloader will act as the last resort and take diff --git a/Bindings/timer/arm,twd-timer.yaml b/Bindings/timer/arm,twd-timer.yaml index 5684df6448e..eb1127352c7 100644 --- a/Bindings/timer/arm,twd-timer.yaml +++ b/Bindings/timer/arm,twd-timer.yaml @@ -50,7 +50,7 @@ examples: #include timer@2c000600 { - compatible = "arm,arm11mp-twd-timer"; - reg = <0x2c000600 0x20>; - interrupts = ; + compatible = "arm,arm11mp-twd-timer"; + reg = <0x2c000600 0x20>; + interrupts = ; }; diff --git a/Bindings/timer/nxp,sysctr-timer.yaml b/Bindings/timer/nxp,sysctr-timer.yaml index 891cca00952..6b80b060672 100644 --- a/Bindings/timer/nxp,sysctr-timer.yaml +++ b/Bindings/timer/nxp,sysctr-timer.yaml @@ -18,9 +18,14 @@ description: | properties: compatible: - enum: - - nxp,imx95-sysctr-timer - - nxp,sysctr-timer + oneOf: + - enum: + - nxp,imx95-sysctr-timer + - nxp,sysctr-timer + - items: + - enum: + - nxp,imx94-sysctr-timer + - const: nxp,imx95-sysctr-timer reg: maxItems: 1 diff --git a/Bindings/timer/renesas,cmt.yaml b/Bindings/timer/renesas,cmt.yaml index 5e09c04da30..260b05f213e 100644 --- a/Bindings/timer/renesas,cmt.yaml +++ b/Bindings/timer/renesas,cmt.yaml @@ -178,29 +178,29 @@ examples: #include #include cmt0: timer@ffca0000 { - compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0"; - reg = <0xffca0000 0x1004>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 124>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 124>; + compatible = "renesas,r8a7790-cmt0", "renesas,rcar-gen2-cmt0"; + reg = <0xffca0000 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 124>; }; cmt1: timer@e6130000 { - compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1"; - reg = <0xe6130000 0x1004>; - interrupts = , - , - , - , - , - , - , - ; - clocks = <&cpg CPG_MOD 329>; - clock-names = "fck"; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 329>; + compatible = "renesas,r8a7790-cmt1", "renesas,rcar-gen2-cmt1"; + reg = <0xe6130000 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 329>; + clock-names = "fck"; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 329>; }; diff --git a/Bindings/timer/renesas,em-sti.yaml b/Bindings/timer/renesas,em-sti.yaml index 233d74d5402..a7385d865bc 100644 --- a/Bindings/timer/renesas,em-sti.yaml +++ b/Bindings/timer/renesas,em-sti.yaml @@ -38,9 +38,9 @@ examples: - | #include timer@e0180000 { - compatible = "renesas,em-sti"; - reg = <0xe0180000 0x54>; - interrupts = ; - clocks = <&sti_sclk>; - clock-names = "sclk"; + compatible = "renesas,em-sti"; + reg = <0xe0180000 0x54>; + interrupts = ; + clocks = <&sti_sclk>; + clock-names = "sclk"; }; diff --git a/Bindings/timer/renesas,mtu2.yaml b/Bindings/timer/renesas,mtu2.yaml index 15d8dddf4ae..e56c12f03f7 100644 --- a/Bindings/timer/renesas,mtu2.yaml +++ b/Bindings/timer/renesas,mtu2.yaml @@ -66,11 +66,11 @@ examples: #include #include mtu2: timer@fcff0000 { - compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; - reg = <0xfcff0000 0x400>; - interrupts = ; - interrupt-names = "tgi0a"; - clocks = <&mstp3_clks R7S72100_CLK_MTU2>; - clock-names = "fck"; - power-domains = <&cpg_clocks>; + compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; + reg = <0xfcff0000 0x400>; + interrupts = ; + interrupt-names = "tgi0a"; + clocks = <&mstp3_clks R7S72100_CLK_MTU2>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; }; diff --git a/Bindings/timer/renesas,ostm.yaml b/Bindings/timer/renesas,ostm.yaml index e8c64216646..9ba858f094a 100644 --- a/Bindings/timer/renesas,ostm.yaml +++ b/Bindings/timer/renesas,ostm.yaml @@ -71,9 +71,9 @@ examples: #include #include ostm0: timer@fcfec000 { - compatible = "renesas,r7s72100-ostm", "renesas,ostm"; - reg = <0xfcfec000 0x30>; - interrupts = ; - clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; - power-domains = <&cpg_clocks>; + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec000 0x30>; + interrupts = ; + clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; + power-domains = <&cpg_clocks>; }; diff --git a/Bindings/timer/renesas,tmu.yaml b/Bindings/timer/renesas,tmu.yaml index 75b0e7c70b6..b1229595acf 100644 --- a/Bindings/timer/renesas,tmu.yaml +++ b/Bindings/timer/renesas,tmu.yaml @@ -122,15 +122,15 @@ examples: #include #include tmu0: timer@ffd80000 { - compatible = "renesas,tmu-r8a7779", "renesas,tmu"; - reg = <0xffd80000 0x30>; - interrupts = , - , - , - ; - interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; - clocks = <&mstp0_clks R8A7779_CLK_TMU0>; - clock-names = "fck"; - power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; - #renesas,channels = <3>; + compatible = "renesas,tmu-r8a7779", "renesas,tmu"; + reg = <0xffd80000 0x30>; + interrupts = , + , + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; + clocks = <&mstp0_clks R8A7779_CLK_TMU0>; + clock-names = "fck"; + power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; + #renesas,channels = <3>; }; diff --git a/Bindings/timer/renesas,tpu.yaml b/Bindings/timer/renesas,tpu.yaml deleted file mode 100644 index 01554dff23d..00000000000 --- a/Bindings/timer/renesas,tpu.yaml +++ /dev/null @@ -1,56 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/timer/renesas,tpu.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Renesas H8/300 Timer Pulse Unit - -maintainers: - - Yoshinori Sato - -description: - The TPU is a 16bit timer/counter with configurable clock inputs and - programmable compare match. - This implementation supports only cascade mode. - -select: - properties: - compatible: - contains: - const: renesas,tpu - '#pwm-cells': false - required: - - compatible - -properties: - compatible: - const: renesas,tpu - - reg: - items: - - description: First channel - - description: Second channel - - clocks: - maxItems: 1 - - clock-names: - const: fck - -required: - - compatible - - reg - - clocks - - clock-names - -additionalProperties: false - -examples: - - | - tpu: tpu@ffffe0 { - compatible = "renesas,tpu"; - reg = <0xffffe0 16>, <0xfffff0 12>; - clocks = <&pclk>; - clock-names = "fck"; - }; diff --git a/Bindings/timer/samsung,exynos4210-mct.yaml b/Bindings/timer/samsung,exynos4210-mct.yaml index 02d1c355808..10578f54458 100644 --- a/Bindings/timer/samsung,exynos4210-mct.yaml +++ b/Bindings/timer/samsung,exynos4210-mct.yaml @@ -27,6 +27,7 @@ properties: - enum: - axis,artpec8-mct - google,gs101-mct + - samsung,exynos2200-mct-peris - samsung,exynos3250-mct - samsung,exynos5250-mct - samsung,exynos5260-mct @@ -34,6 +35,7 @@ properties: - samsung,exynos5433-mct - samsung,exynos850-mct - samsung,exynos8895-mct + - samsung,exynos990-mct - tesla,fsd-mct - const: samsung,exynos4210-mct @@ -130,11 +132,13 @@ allOf: enum: - axis,artpec8-mct - google,gs101-mct + - samsung,exynos2200-mct-peris - samsung,exynos5260-mct - samsung,exynos5420-mct - samsung,exynos5433-mct - samsung,exynos850-mct - samsung,exynos8895-mct + - samsung,exynos990-mct then: properties: interrupts: diff --git a/Bindings/timer/sifive,clint.yaml b/Bindings/timer/sifive,clint.yaml index 76d83aea4e2..653e2e0ca87 100644 --- a/Bindings/timer/sifive,clint.yaml +++ b/Bindings/timer/sifive,clint.yaml @@ -36,6 +36,12 @@ properties: - starfive,jh7110-clint # StarFive JH7110 - starfive,jh8100-clint # StarFive JH8100 - const: sifive,clint0 # SiFive CLINT v0 IP block + - items: + - {} + - const: sifive,clint2 # SiFive CLINT v2 IP block + description: + SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2 + differs from that of sifive,clint0, making them incompatible. - items: - enum: - allwinner,sun20i-d1-clint @@ -62,6 +68,22 @@ properties: minItems: 1 maxItems: 4095 + sifive,fine-ctr-bits: + maximum: 15 + description: The width in bits of the fine counter. + +if: + properties: + compatible: + contains: + const: sifive,clint2 +then: + required: + - sifive,fine-ctr-bits +else: + properties: + sifive,fine-ctr-bits: false + additionalProperties: false required: @@ -77,6 +99,6 @@ examples: <&cpu2intc 3>, <&cpu2intc 7>, <&cpu3intc 3>, <&cpu3intc 7>, <&cpu4intc 3>, <&cpu4intc 7>; - reg = <0x2000000 0x10000>; + reg = <0x2000000 0x10000>; }; ... diff --git a/Bindings/trigger-source/pwm-trigger.yaml b/Bindings/trigger-source/pwm-trigger.yaml new file mode 100644 index 00000000000..1eac20031dc --- /dev/null +++ b/Bindings/trigger-source/pwm-trigger.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/trigger-source/pwm-trigger.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic trigger source using PWM + +description: Remaps a PWM channel as a trigger source. + +maintainers: + - David Lechner + +properties: + compatible: + const: pwm-trigger + + '#trigger-source-cells': + const: 0 + + pwms: + maxItems: 1 + +required: + - compatible + - '#trigger-source-cells' + - pwms + +additionalProperties: false + +examples: + - | + trigger { + compatible = "pwm-trigger"; + #trigger-source-cells = <0>; + pwms = <&pwm 0 1000000 0>; + }; diff --git a/Bindings/trivial-devices.yaml b/Bindings/trivial-devices.yaml index fadbd3c041c..8da408107e5 100644 --- a/Bindings/trivial-devices.yaml +++ b/Bindings/trivial-devices.yaml @@ -185,10 +185,20 @@ properties: - maxim,max5484 # PECI-to-I2C translator for PECI-to-SMBus/I2C protocol conversion - maxim,max6621 + # InTune Automatically Compensated Digital PoL Controller with Driver and PMBus Telemetry + - maxim,max15301 + # 6A InTune Automatically Compensated Converter with PMBus Telemetry + - maxim,max15303 + # Multiphase Master with PMBus Interface and Internal Buck Converter + - maxim,max20751 # mCube 3-axis 8-bit digital accelerometer - mcube,mc3230 + # mCube 3-axis 8-bit digital accelerometer + - mcube,mc3510c # Measurement Specialities I2C temperature and humidity sensor - meas,htu21 + # Measurement Specialities I2C temperature and humidity sensor + - meas,htu31 # Measurement Specialities I2C pressure and temperature sensor - meas,ms5637 # Measurement Specialities I2C pressure and temperature sensor @@ -380,6 +390,8 @@ properties: - ti,tps53676 # TI Dual channel DCAP+ multiphase controller TPS53679 - ti,tps53679 + # TI Dual channel DCAP+ multiphase controller TPS53681 + - ti,tps53681 # TI Dual channel DCAP+ multiphase controller TPS53688 - ti,tps53688 # TI DC-DC converters on PMBus @@ -387,6 +399,7 @@ properties: - ti,tps544b25 - ti,tps544c20 - ti,tps544c25 + - ti,tps546b24 - ti,tps546d24 # I2C Touch-Screen Controller - ti,tsc2003 diff --git a/Bindings/ufs/renesas,ufs.yaml b/Bindings/ufs/renesas,ufs.yaml index 1949a15e73d..ac11ac7d1d1 100644 --- a/Bindings/ufs/renesas,ufs.yaml +++ b/Bindings/ufs/renesas,ufs.yaml @@ -33,6 +33,16 @@ properties: resets: maxItems: 1 + nvmem-cells: + maxItems: 1 + + nvmem-cell-names: + items: + - const: calibration + +dependencies: + nvmem-cells: [ nvmem-cell-names ] + required: - compatible - reg @@ -58,4 +68,6 @@ examples: freq-table-hz = <200000000 200000000>, <38400000 38400000>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 1514>; + nvmem-cells = <&ufs_tune>; + nvmem-cell-names = "calibration"; }; diff --git a/Bindings/ufs/rockchip,rk3576-ufshc.yaml b/Bindings/ufs/rockchip,rk3576-ufshc.yaml new file mode 100644 index 00000000000..c7d17cf4dc4 --- /dev/null +++ b/Bindings/ufs/rockchip,rk3576-ufshc.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/rockchip,rk3576-ufshc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip UFS Host Controller + +maintainers: + - Shawn Lin + +allOf: + - $ref: ufs-common.yaml + +properties: + compatible: + const: rockchip,rk3576-ufshc + + reg: + maxItems: 5 + + reg-names: + items: + - const: hci + - const: mphy + - const: hci_grf + - const: mphy_grf + - const: hci_apb + + clocks: + maxItems: 4 + + clock-names: + items: + - const: core + - const: pclk + - const: pclk_mphy + - const: ref_out + + power-domains: + maxItems: 1 + + resets: + maxItems: 4 + + reset-names: + items: + - const: biu + - const: sys + - const: ufs + - const: grf + + reset-gpios: + maxItems: 1 + description: | + GPIO specifiers for host to reset the whole UFS device including PHY and + memory. This gpio is active low and should choose the one whose high output + voltage is lower than 1.5V based on the UFS spec. + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - power-domains + - resets + - reset-names + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + ufshc: ufshc@2a2d0000 { + compatible = "rockchip,rk3576-ufshc"; + reg = <0x0 0x2a2d0000 0x0 0x10000>, + <0x0 0x2b040000 0x0 0x10000>, + <0x0 0x2601f000 0x0 0x1000>, + <0x0 0x2603c000 0x0 0x1000>, + <0x0 0x2a2e0000 0x0 0x10000>; + reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; + clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, + <&cru CLK_REF_UFS_CLKOUT>; + clock-names = "core", "pclk", "pclk_mphy", "ref_out"; + interrupts = ; + power-domains = <&power RK3576_PD_USB>; + resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, <&cru SRST_A_UFS>, + <&cru SRST_P_UFS_GRF>; + reset-names = "biu", "sys", "ufs", "grf"; + reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Bindings/usb/dwc3-xilinx.yaml b/Bindings/usb/dwc3-xilinx.yaml index 00f87a558c7..379dacacb52 100644 --- a/Bindings/usb/dwc3-xilinx.yaml +++ b/Bindings/usb/dwc3-xilinx.yaml @@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx SuperSpeed DWC3 USB SoC controller maintainers: - - Mubin Sayyed - Radhey Shyam Pandey properties: @@ -101,7 +100,6 @@ examples: #include #include #include - #include #include #include axi { @@ -113,7 +111,7 @@ examples: #size-cells = <0x2>; compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; - clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>; + clocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>; clock-names = "bus_clk", "ref_clk"; power-domains = <&zynqmp_firmware PD_USB_0>; resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, diff --git a/Bindings/usb/generic-xhci.yaml b/Bindings/usb/generic-xhci.yaml index 6ceafa4af29..a2b94a13899 100644 --- a/Bindings/usb/generic-xhci.yaml +++ b/Bindings/usb/generic-xhci.yaml @@ -51,6 +51,8 @@ properties: - const: core - const: reg + dma-coherent: true + power-domains: maxItems: 1 diff --git a/Bindings/usb/mediatek,mtk-xhci.yaml b/Bindings/usb/mediatek,mtk-xhci.yaml index ef3143f4b79..004d3ebec09 100644 --- a/Bindings/usb/mediatek,mtk-xhci.yaml +++ b/Bindings/usb/mediatek,mtk-xhci.yaml @@ -106,6 +106,10 @@ properties: - description: USB3/SS(P) PHY - description: USB2/HS PHY + port: + $ref: /schemas/graph.yaml#/properties/port + description: Super Speed (SS) Output endpoint to a Type-C connector + vusb33-supply: description: Regulator of USB AVDD3.3v diff --git a/Bindings/usb/mediatek,mtu3.yaml b/Bindings/usb/mediatek,mtu3.yaml index d4e187c78a0..21fc6bbe954 100644 --- a/Bindings/usb/mediatek,mtu3.yaml +++ b/Bindings/usb/mediatek,mtu3.yaml @@ -155,6 +155,18 @@ properties: property is used. See graph.txt $ref: /schemas/graph.yaml#/properties/port + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: High Speed (HS) data bus. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Super Speed (SS) data bus. + enable-manual-drd: $ref: /schemas/types.yaml#/definitions/flag description: diff --git a/Bindings/usb/microchip,usb2514.yaml b/Bindings/usb/microchip,usb2514.yaml index b14e6f37b29..4e3901efed3 100644 --- a/Bindings/usb/microchip,usb2514.yaml +++ b/Bindings/usb/microchip,usb2514.yaml @@ -9,16 +9,19 @@ title: Microchip USB2514 Hub Controller maintainers: - Fabio Estevam -allOf: - - $ref: usb-device.yaml# - properties: compatible: - enum: - - usb424,2412 - - usb424,2417 - - usb424,2514 - - usb424,2517 + oneOf: + - enum: + - usb424,2412 + - usb424,2417 + - usb424,2514 + - usb424,2517 + - items: + - enum: + - usb424,2512 + - usb424,2513 + - const: usb424,2514 reg: true @@ -28,6 +31,9 @@ properties: vdd-supply: description: 3.3V power supply. + vdda-supply: + description: 3.3V analog power supply. + clocks: description: External 24MHz clock connected to the CLKIN pin. maxItems: 1 @@ -43,6 +49,18 @@ patternProperties: $ref: /schemas/usb/usb-device.yaml additionalProperties: true +allOf: + - $ref: usb-device.yaml# + - if: + not: + properties: + compatible: + contains: + const: usb424,2514 + then: + properties: + vdda-supply: false + unevaluatedProperties: false examples: @@ -60,6 +78,7 @@ examples: clocks = <&clks IMX6QDL_CLK_CKO>; reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; vdd-supply = <®_3v3_hub>; + vdda-supply = <®_3v3a_hub>; #address-cells = <1>; #size-cells = <0>; diff --git a/Bindings/usb/microchip,usb5744.yaml b/Bindings/usb/microchip,usb5744.yaml index e2a72deae77..c68c04da339 100644 --- a/Bindings/usb/microchip,usb5744.yaml +++ b/Bindings/usb/microchip,usb5744.yaml @@ -17,7 +17,6 @@ description: maintainers: - Michal Simek - - Mubin Sayyed - Radhey Shyam Pandey properties: diff --git a/Bindings/usb/parade,ps8830.yaml b/Bindings/usb/parade,ps8830.yaml new file mode 100644 index 00000000000..935d57f5d26 --- /dev/null +++ b/Bindings/usb/parade,ps8830.yaml @@ -0,0 +1,140 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/parade,ps8830.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Parade PS883x USB and DisplayPort Retimer + +maintainers: + - Abel Vesa + +properties: + compatible: + enum: + - parade,ps8830 + + reg: + maxItems: 1 + + clocks: + items: + - description: XO Clock + + reset-gpios: + maxItems: 1 + + vdd-supply: + description: power supply (1.07V) + + vdd33-supply: + description: power supply (3.3V) + + vdd33-cap-supply: + description: power supply (3.3V) + + vddar-supply: + description: power supply (1.07V) + + vddat-supply: + description: power supply (1.07V) + + vddio-supply: + description: power supply (1.2V or 1.8V) + + orientation-switch: true + retimer-switch: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Super Speed (SS) Output endpoint to the Type-C connector + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + description: Super Speed (SS) Input endpoint from the Super-Speed PHY + unevaluatedProperties: false + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: + Sideband Use (SBU) AUX lines endpoint to the Type-C connector for the purpose of + handling altmode muxing and orientation switching. + +required: + - compatible + - reg + - clocks + - reset-gpios + - vdd-supply + - vdd33-supply + - vdd33-cap-supply + - vddat-supply + - vddio-supply + - orientation-switch + - retimer-switch + +allOf: + - $ref: usb-switch.yaml# + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + typec-mux@8 { + compatible = "parade,ps8830"; + reg = <0x8>; + + clocks = <&clk_rtmr_xo>; + + vdd-supply = <&vreg_rtmr_1p15>; + vdd33-supply = <&vreg_rtmr_3p3>; + vdd33-cap-supply = <&vreg_rtmr_3p3>; + vddar-supply = <&vreg_rtmr_1p15>; + vddat-supply = <&vreg_rtmr_1p15>; + vddio-supply = <&vreg_rtmr_1p8>; + + reset-gpios = <&tlmm 10 GPIO_ACTIVE_LOW>; + + retimer-switch; + orientation-switch; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&usb_phy_ss>; + }; + }; + + port@2 { + reg = <2>; + + endpoint { + remote-endpoint = <&typec_dp_aux>; + }; + }; + }; + }; + }; +... diff --git a/Bindings/usb/qcom,dwc3.yaml b/Bindings/usb/qcom,dwc3.yaml index a2b3cf625e5..64137c1619a 100644 --- a/Bindings/usb/qcom,dwc3.yaml +++ b/Bindings/usb/qcom,dwc3.yaml @@ -404,6 +404,7 @@ allOf: minItems: 2 maxItems: 3 interrupt-names: + minItems: 2 items: - const: pwr_event - const: qusb2_phy @@ -425,6 +426,7 @@ allOf: minItems: 3 maxItems: 4 interrupt-names: + minItems: 3 items: - const: pwr_event - const: qusb2_phy diff --git a/Bindings/usb/richtek,rt1711h.yaml b/Bindings/usb/richtek,rt1711h.yaml index 8da4d2ad1a9..ae611f7e57c 100644 --- a/Bindings/usb/richtek,rt1711h.yaml +++ b/Bindings/usb/richtek,rt1711h.yaml @@ -30,6 +30,9 @@ properties: interrupts: maxItems: 1 + vbus-supply: + description: VBUS power supply + wakeup-source: type: boolean diff --git a/Bindings/usb/rockchip,dwc3.yaml b/Bindings/usb/rockchip,dwc3.yaml index a21cc098542..fba2cb05ecb 100644 --- a/Bindings/usb/rockchip,dwc3.yaml +++ b/Bindings/usb/rockchip,dwc3.yaml @@ -26,6 +26,7 @@ select: contains: enum: - rockchip,rk3328-dwc3 + - rockchip,rk3562-dwc3 - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 - rockchip,rk3588-dwc3 @@ -37,6 +38,7 @@ properties: items: - enum: - rockchip,rk3328-dwc3 + - rockchip,rk3562-dwc3 - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 - rockchip,rk3588-dwc3 @@ -72,6 +74,7 @@ properties: - enum: - grf_clk - utmi + - pipe - const: pipe power-domains: @@ -111,6 +114,22 @@ allOf: - const: suspend_clk - const: bus_clk - const: grf_clk + - if: + properties: + compatible: + contains: + const: rockchip,rk3562-dwc3 + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + clock-names: + items: + - const: ref_clk + - const: suspend_clk + - const: bus_clk + - const: pipe - if: properties: compatible: diff --git a/Bindings/usb/samsung,exynos-dwc3.yaml b/Bindings/usb/samsung,exynos-dwc3.yaml index 2b3430cebe9..256bee2a03c 100644 --- a/Bindings/usb/samsung,exynos-dwc3.yaml +++ b/Bindings/usb/samsung,exynos-dwc3.yaml @@ -11,12 +11,17 @@ maintainers: properties: compatible: - enum: - - google,gs101-dwusb3 - - samsung,exynos5250-dwusb3 - - samsung,exynos5433-dwusb3 - - samsung,exynos7-dwusb3 - - samsung,exynos850-dwusb3 + oneOf: + - enum: + - google,gs101-dwusb3 + - samsung,exynos5250-dwusb3 + - samsung,exynos5433-dwusb3 + - samsung,exynos7-dwusb3 + - samsung,exynos7870-dwusb3 + - samsung,exynos850-dwusb3 + - items: + - const: samsung,exynos990-dwusb3 + - const: samsung,exynos850-dwusb3 '#address-cells': const: 1 @@ -52,7 +57,6 @@ required: - clock-names - ranges - '#size-cells' - - vdd10-supply - vdd33-supply allOf: @@ -72,6 +76,8 @@ allOf: - const: susp_clk - const: link_aclk - const: link_pclk + required: + - vdd10-supply - if: properties: @@ -86,6 +92,8 @@ allOf: clock-names: items: - const: usbdrd30 + required: + - vdd10-supply - if: properties: @@ -103,6 +111,8 @@ allOf: - const: susp_clk - const: phyclk - const: pipe_pclk + required: + - vdd10-supply - if: properties: @@ -119,6 +129,24 @@ allOf: - const: usbdrd30 - const: usbdrd30_susp_clk - const: usbdrd30_axius_clk + required: + - vdd10-supply + + - if: + properties: + compatible: + contains: + const: samsung,exynos7870-dwusb3 + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: bus_early + - const: ref + - const: ctrl - if: properties: @@ -134,6 +162,8 @@ allOf: items: - const: bus_early - const: ref + required: + - vdd10-supply additionalProperties: false diff --git a/Bindings/usb/snps,dwc3-common.yaml b/Bindings/usb/snps,dwc3-common.yaml index c956053fd03..71249b6ba61 100644 --- a/Bindings/usb/snps,dwc3-common.yaml +++ b/Bindings/usb/snps,dwc3-common.yaml @@ -65,6 +65,17 @@ properties: mode. type: boolean + snps,reserved-endpoints: + description: + Reserve endpoints for other needs, e.g, for tracing control and output. + When set, the driver will avoid using them for the regular USB transfers. + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 1 + maxItems: 30 + items: + minimum: 2 + maximum: 31 + snps,dis-start-transfer-quirk: description: When set, disable isoc START TRANSFER command failure SW work-around diff --git a/Bindings/usb/usb-device.yaml b/Bindings/usb/usb-device.yaml index da890ee60ce..c6769568103 100644 --- a/Bindings/usb/usb-device.yaml +++ b/Bindings/usb/usb-device.yaml @@ -39,8 +39,10 @@ properties: reg: description: the number of the USB hub port or the USB host-controller - port to which this device is attached. The range is 1-255. - maxItems: 1 + port to which this device is attached. + items: + - minimum: 1 + maximum: 255 "#address-cells": description: should be 1 for hub nodes with device nodes, diff --git a/Bindings/usb/xlnx,usb2.yaml b/Bindings/usb/xlnx,usb2.yaml index a7f75fe3666..f295aa9d9ee 100644 --- a/Bindings/usb/xlnx,usb2.yaml +++ b/Bindings/usb/xlnx,usb2.yaml @@ -7,7 +7,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Xilinx udc controller maintainers: - - Mubin Sayyed - Radhey Shyam Pandey properties: diff --git a/Bindings/vendor-prefixes.yaml b/Bindings/vendor-prefixes.yaml index 5079ca6ce1d..86f6a19b28a 100644 --- a/Bindings/vendor-prefixes.yaml +++ b/Bindings/vendor-prefixes.yaml @@ -18,7 +18,7 @@ patternProperties: # DO NOT ADD NEW PROPERTIES TO THIS LIST "^(at25|bm|devbus|dmacap|dsa|exynos|fsi[ab]|gpio-fan|gpio-key|gpio|gpmc|hdmi|i2c-gpio),.*": true "^(keypad|m25p|max8952|max8997|max8998|mpmc),.*": true - "^(pinctrl-single|#pinctrl-single|PowerPC),.*": true + "^(pciclass|pinctrl-single|#pinctrl-single|PowerPC),.*": true "^(pl022|pxa-mmc|rcar_sound|rotary-encoder|s5m8767|sdhci),.*": true "^(simple-audio-card|st-plgpio|st-spics|ts),.*": true @@ -147,6 +147,8 @@ patternProperties: description: Arctic Sand "^arcx,.*": description: arcx Inc. / Archronix Inc. + "^ariaboard,.*": + description: Shanghai Novotech Co., Ltd. (Ariaboard) "^aries,.*": description: Aries Embedded GmbH "^arm,.*": @@ -338,6 +340,8 @@ patternProperties: description: Crystalfontz America, Inc. "^csky,.*": description: Hangzhou C-SKY Microsystems Co., Ltd + "^csot,.*": + description: Guangzhou China Star Optoelectronics Technology Co., Ltd "^csq,.*": description: Shenzen Chuangsiqi Technology Co.,Ltd. "^ctera,.*": @@ -593,6 +597,8 @@ patternProperties: description: GlobalTop Technology, Inc. "^gmt,.*": description: Global Mixed-mode Technology, Inc. + "^gocontroll,.*": + description: GOcontroll Modular Embedded Electronics B.V. "^goldelico,.*": description: Golden Delicious Computers GmbH & Co. KG "^goodix,.*": @@ -1031,6 +1037,8 @@ patternProperties: description: Neofidelity Inc. "^neonode,.*": description: Neonode Inc. + "^netcube,.*": + description: NetCube Systems Austria "^netgear,.*": description: NETGEAR "^netlogic,.*": @@ -1202,6 +1210,8 @@ patternProperties: description: Primux Trading, S.L. "^probox2,.*": description: PROBOX2 (by W2COMP Co., Ltd.) + "^pri,.*": + description: Priva "^prt,.*": description: Protonic Holland "^pulsedlight,.*": @@ -1267,7 +1277,7 @@ patternProperties: "^riscv,.*": description: RISC-V Foundation "^rockchip,.*": - description: Fuzhou Rockchip Electronics Co., Ltd + description: Rockchip Electronics Co., Ltd. "^rocktech,.*": description: ROCKTECH DISPLAYS LIMITED "^rohm,.*": @@ -1737,6 +1747,8 @@ patternProperties: description: Shenzhen Yashi Changhua Intelligent Technology Co., Ltd. "^ysoft,.*": description: Y Soft Corporation a.s. + "^yuridenki,.*": + description: Yuridenki-Shokai Co. Ltd. "^zarlink,.*": description: Zarlink Semiconductor "^zealz,.*": diff --git a/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml b/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml index 64c8f739380..b35ac03d517 100644 --- a/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml +++ b/Bindings/watchdog/allwinner,sun4i-a10-wdt.yaml @@ -32,6 +32,7 @@ properties: - items: - const: allwinner,sun20i-d1-wdt-reset - const: allwinner,sun20i-d1-wdt + - const: allwinner,sun55i-a523-wdt reg: maxItems: 1 @@ -60,6 +61,7 @@ if: - allwinner,sun20i-d1-wdt-reset - allwinner,sun50i-r329-wdt - allwinner,sun50i-r329-wdt-reset + - allwinner,sun55i-a523-wdt then: properties: diff --git a/Bindings/watchdog/fsl-imx7ulp-wdt.yaml b/Bindings/watchdog/fsl-imx7ulp-wdt.yaml index a09686b3030..6ec391b9723 100644 --- a/Bindings/watchdog/fsl-imx7ulp-wdt.yaml +++ b/Bindings/watchdog/fsl-imx7ulp-wdt.yaml @@ -22,6 +22,10 @@ properties: - const: fsl,imx8ulp-wdt - const: fsl,imx7ulp-wdt - const: fsl,imx93-wdt + - items: + - enum: + - fsl,imx94-wdt + - const: fsl,imx93-wdt reg: maxItems: 1 diff --git a/Bindings/watchdog/renesas,wdt.yaml b/Bindings/watchdog/renesas,wdt.yaml index 29ada89fdcd..3e0a8747a35 100644 --- a/Bindings/watchdog/renesas,wdt.yaml +++ b/Bindings/watchdog/renesas,wdt.yaml @@ -75,6 +75,10 @@ properties: - renesas,r8a779h0-wdt # R-Car V4M - const: renesas,rcar-gen4-wdt # R-Car Gen4 + - items: + - const: renesas,r9a09g047-wdt # RZ/G3E + - const: renesas,r9a09g057-wdt # RZ/V2H(P) + - const: renesas,r9a09g057-wdt # RZ/V2H(P) reg: diff --git a/Bindings/xilinx.txt b/Bindings/xilinx.txt index 28199b31fe5..0ee9de99b3a 100644 --- a/Bindings/xilinx.txt +++ b/Bindings/xilinx.txt @@ -102,15 +102,6 @@ Default is . - rotate-display (empty) : rotate display 180 degrees. - ii) Xilinx SystemACE - - The Xilinx SystemACE device is used to program FPGAs from an FPGA - bitstream stored on a CF card. It can also be used as a generic CF - interface device. - - Optional properties: - - 8-bit (empty) : Set this property for SystemACE in 8 bit mode - iii) Xilinx EMAC and Xilinx TEMAC Xilinx Ethernet devices. In addition to general xilinx properties @@ -118,13 +109,6 @@ property, and may include other common network device properties like local-mac-address. - iv) Xilinx Uartlite - - Xilinx uartlite devices are simple fixed speed serial ports. - - Required properties: - - current-speed : Baud rate of uartlite - v) Xilinx hwicap Xilinx hwicap devices provide access to the configuration logic @@ -141,16 +125,6 @@ - compatible : should contain "xlnx,xps-hwicap-1.00.a" or "xlnx,opb-hwicap-1.00.b". - vi) Xilinx Uart 16550 - - Xilinx UART 16550 devices are very similar to the NS16550 but with - different register spacing and an offset from the base address. - - Required properties: - - clock-frequency : Frequency of the clock input - - reg-offset : A value of 3 is required - - reg-shift : A value of 2 is required - vii) Xilinx USB Host controller The Xilinx USB host controller is EHCI compatible but with a different diff --git a/include/dt-bindings/clock/mediatek,mt8188-clk.h b/include/dt-bindings/clock/mediatek,mt8188-clk.h index bd5cd100b79..0e87f61c90f 100644 --- a/include/dt-bindings/clock/mediatek,mt8188-clk.h +++ b/include/dt-bindings/clock/mediatek,mt8188-clk.h @@ -721,6 +721,6 @@ #define CLK_VDO1_DPINTF 58 #define CLK_VDO1_DISP_MONITOR_DPINTF 59 #define CLK_VDO1_26M_SLOW 60 -#define CLK_VDO1_NR_CLK 61 +#define CLK_VDO1_DPI1_HDMI 61 #endif /* _DT_BINDINGS_CLK_MT8188_H */ diff --git a/include/dt-bindings/clock/mediatek,mtmips-sysc.h b/include/dt-bindings/clock/mediatek,mtmips-sysc.h new file mode 100644 index 00000000000..a03335b0e07 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mtmips-sysc.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Author: Sergio Paracuellos + */ + +#ifndef _DT_BINDINGS_CLK_MTMIPS_H +#define _DT_BINDINGS_CLK_MTMIPS_H + +/* Ralink RT-2880 clocks */ + +#define RT2880_CLK_XTAL 0 +#define RT2880_CLK_CPU 1 +#define RT2880_CLK_BUS 2 +#define RT2880_CLK_TIMER 3 +#define RT2880_CLK_WATCHDOG 4 +#define RT2880_CLK_UART 5 +#define RT2880_CLK_I2C 6 +#define RT2880_CLK_UARTLITE 7 +#define RT2880_CLK_ETHERNET 8 +#define RT2880_CLK_WMAC 9 + +/* Ralink RT-305X clocks */ + +#define RT305X_CLK_XTAL 0 +#define RT305X_CLK_CPU 1 +#define RT305X_CLK_BUS 2 +#define RT305X_CLK_TIMER 3 +#define RT305X_CLK_WATCHDOG 4 +#define RT305X_CLK_UART 5 +#define RT305X_CLK_I2C 6 +#define RT305X_CLK_I2S 7 +#define RT305X_CLK_SPI1 8 +#define RT305X_CLK_SPI2 9 +#define RT305X_CLK_UARTLITE 10 +#define RT305X_CLK_ETHERNET 11 +#define RT305X_CLK_WMAC 12 + +/* Ralink RT-3352 clocks */ + +#define RT3352_CLK_XTAL 0 +#define RT3352_CLK_CPU 1 +#define RT3352_CLK_PERIPH 2 +#define RT3352_CLK_BUS 3 +#define RT3352_CLK_TIMER 4 +#define RT3352_CLK_WATCHDOG 5 +#define RT3352_CLK_UART 6 +#define RT3352_CLK_I2C 7 +#define RT3352_CLK_I2S 8 +#define RT3352_CLK_SPI1 9 +#define RT3352_CLK_SPI2 10 +#define RT3352_CLK_UARTLITE 11 +#define RT3352_CLK_ETHERNET 12 +#define RT3352_CLK_WMAC 13 + +/* Ralink RT-3883 clocks */ + +#define RT3883_CLK_XTAL 0 +#define RT3883_CLK_CPU 1 +#define RT3883_CLK_BUS 2 +#define RT3883_CLK_PERIPH 3 +#define RT3883_CLK_TIMER 4 +#define RT3883_CLK_WATCHDOG 5 +#define RT3883_CLK_UART 6 +#define RT3883_CLK_I2C 7 +#define RT3883_CLK_I2S 8 +#define RT3883_CLK_SPI1 9 +#define RT3883_CLK_SPI2 10 +#define RT3883_CLK_UARTLITE 11 +#define RT3883_CLK_ETHERNET 12 +#define RT3883_CLK_WMAC 13 + +/* Ralink RT-5350 clocks */ + +#define RT5350_CLK_XTAL 0 +#define RT5350_CLK_CPU 1 +#define RT5350_CLK_BUS 2 +#define RT5350_CLK_PERIPH 3 +#define RT5350_CLK_TIMER 4 +#define RT5350_CLK_WATCHDOG 5 +#define RT5350_CLK_UART 6 +#define RT5350_CLK_I2C 7 +#define RT5350_CLK_I2S 8 +#define RT5350_CLK_SPI1 9 +#define RT5350_CLK_SPI2 10 +#define RT5350_CLK_UARTLITE 11 +#define RT5350_CLK_ETHERNET 12 +#define RT5350_CLK_WMAC 13 + +/* Ralink MT-7620 clocks */ + +#define MT7620_CLK_XTAL 0 +#define MT7620_CLK_PLL 1 +#define MT7620_CLK_CPU 2 +#define MT7620_CLK_PERIPH 3 +#define MT7620_CLK_BUS 4 +#define MT7620_CLK_BBPPLL 5 +#define MT7620_CLK_SDHC 6 +#define MT7620_CLK_TIMER 7 +#define MT7620_CLK_WATCHDOG 8 +#define MT7620_CLK_UART 9 +#define MT7620_CLK_I2C 10 +#define MT7620_CLK_I2S 11 +#define MT7620_CLK_SPI1 12 +#define MT7620_CLK_SPI2 13 +#define MT7620_CLK_UARTLITE 14 +#define MT7620_CLK_MMC 15 +#define MT7620_CLK_WMAC 16 + +/* Ralink MT-76X8 clocks */ + +#define MT76X8_CLK_XTAL 0 +#define MT76X8_CLK_CPU 1 +#define MT76X8_CLK_BBPPLL 2 +#define MT76X8_CLK_PCMI2S 3 +#define MT76X8_CLK_PERIPH 4 +#define MT76X8_CLK_BUS 5 +#define MT76X8_CLK_SDHC 6 +#define MT76X8_CLK_TIMER 7 +#define MT76X8_CLK_WATCHDOG 8 +#define MT76X8_CLK_I2C 9 +#define MT76X8_CLK_I2S 10 +#define MT76X8_CLK_SPI1 11 +#define MT76X8_CLK_SPI2 12 +#define MT76X8_CLK_UART0 13 +#define MT76X8_CLK_UART1 14 +#define MT76X8_CLK_UART2 15 +#define MT76X8_CLK_MMC 16 +#define MT76X8_CLK_WMAC 17 + +#endif /* _DT_BINDINGS_CLK_MTMIPS_H */ diff --git a/include/dt-bindings/clock/qcom,dsi-phy-28nm.h b/include/dt-bindings/clock/qcom,dsi-phy-28nm.h new file mode 100644 index 00000000000..ab94d58377a --- /dev/null +++ b/include/dt-bindings/clock/qcom,dsi-phy-28nm.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DSI_PHY_28NM_H +#define _DT_BINDINGS_CLK_QCOM_DSI_PHY_28NM_H + +#define DSI_BYTE_PLL_CLK 0 +#define DSI_PIXEL_PLL_CLK 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-sdm660.h b/include/dt-bindings/clock/qcom,gcc-sdm660.h index df8a6f3d367..74c22f67da2 100644 --- a/include/dt-bindings/clock/qcom,gcc-sdm660.h +++ b/include/dt-bindings/clock/qcom,gcc-sdm660.h @@ -153,5 +153,7 @@ #define GCC_USB_30_BCR 7 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 8 #define GCC_MSS_RESTART 9 +#define GCC_SDCC1_BCR 10 +#define GCC_SDCC2_BCR 11 #endif diff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h index f238aa4794a..0e7c319897f 100644 --- a/include/dt-bindings/clock/qcom,ipq9574-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h @@ -202,4 +202,5 @@ #define GCC_PCIE1_PIPE_CLK 211 #define GCC_PCIE2_PIPE_CLK 212 #define GCC_PCIE3_PIPE_CLK 213 +#define GPLL0_OUT_AUX 214 #endif diff --git a/include/dt-bindings/clock/qcom,ipq9574-nsscc.h b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h new file mode 100644 index 00000000000..21a16dc0e64 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq9574-nsscc.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H +#define _DT_BINDINGS_CLOCK_IPQ_NSSCC_9574_H + +#define NSS_CC_CE_APB_CLK 0 +#define NSS_CC_CE_AXI_CLK 1 +#define NSS_CC_CE_CLK_SRC 2 +#define NSS_CC_CFG_CLK_SRC 3 +#define NSS_CC_CLC_AXI_CLK 4 +#define NSS_CC_CLC_CLK_SRC 5 +#define NSS_CC_CRYPTO_CLK 6 +#define NSS_CC_CRYPTO_CLK_SRC 7 +#define NSS_CC_CRYPTO_PPE_CLK 8 +#define NSS_CC_HAQ_AHB_CLK 9 +#define NSS_CC_HAQ_AXI_CLK 10 +#define NSS_CC_HAQ_CLK_SRC 11 +#define NSS_CC_IMEM_AHB_CLK 12 +#define NSS_CC_IMEM_CLK_SRC 13 +#define NSS_CC_IMEM_QSB_CLK 14 +#define NSS_CC_INT_CFG_CLK_SRC 15 +#define NSS_CC_NSS_CSR_CLK 16 +#define NSS_CC_NSSNOC_CE_APB_CLK 17 +#define NSS_CC_NSSNOC_CE_AXI_CLK 18 +#define NSS_CC_NSSNOC_CLC_AXI_CLK 19 +#define NSS_CC_NSSNOC_CRYPTO_CLK 20 +#define NSS_CC_NSSNOC_HAQ_AHB_CLK 21 +#define NSS_CC_NSSNOC_HAQ_AXI_CLK 22 +#define NSS_CC_NSSNOC_IMEM_AHB_CLK 23 +#define NSS_CC_NSSNOC_IMEM_QSB_CLK 24 +#define NSS_CC_NSSNOC_NSS_CSR_CLK 25 +#define NSS_CC_NSSNOC_PPE_CFG_CLK 26 +#define NSS_CC_NSSNOC_PPE_CLK 27 +#define NSS_CC_NSSNOC_UBI32_AHB0_CLK 28 +#define NSS_CC_NSSNOC_UBI32_AXI0_CLK 29 +#define NSS_CC_NSSNOC_UBI32_INT0_AHB_CLK 30 +#define NSS_CC_NSSNOC_UBI32_NC_AXI0_1_CLK 31 +#define NSS_CC_NSSNOC_UBI32_NC_AXI0_CLK 32 +#define NSS_CC_PORT1_MAC_CLK 33 +#define NSS_CC_PORT1_RX_CLK 34 +#define NSS_CC_PORT1_RX_CLK_SRC 35 +#define NSS_CC_PORT1_RX_DIV_CLK_SRC 36 +#define NSS_CC_PORT1_TX_CLK 37 +#define NSS_CC_PORT1_TX_CLK_SRC 38 +#define NSS_CC_PORT1_TX_DIV_CLK_SRC 39 +#define NSS_CC_PORT2_MAC_CLK 40 +#define NSS_CC_PORT2_RX_CLK 41 +#define NSS_CC_PORT2_RX_CLK_SRC 42 +#define NSS_CC_PORT2_RX_DIV_CLK_SRC 43 +#define NSS_CC_PORT2_TX_CLK 44 +#define NSS_CC_PORT2_TX_CLK_SRC 45 +#define NSS_CC_PORT2_TX_DIV_CLK_SRC 46 +#define NSS_CC_PORT3_MAC_CLK 47 +#define NSS_CC_PORT3_RX_CLK 48 +#define NSS_CC_PORT3_RX_CLK_SRC 49 +#define NSS_CC_PORT3_RX_DIV_CLK_SRC 50 +#define NSS_CC_PORT3_TX_CLK 51 +#define NSS_CC_PORT3_TX_CLK_SRC 52 +#define NSS_CC_PORT3_TX_DIV_CLK_SRC 53 +#define NSS_CC_PORT4_MAC_CLK 54 +#define NSS_CC_PORT4_RX_CLK 55 +#define NSS_CC_PORT4_RX_CLK_SRC 56 +#define NSS_CC_PORT4_RX_DIV_CLK_SRC 57 +#define NSS_CC_PORT4_TX_CLK 58 +#define NSS_CC_PORT4_TX_CLK_SRC 59 +#define NSS_CC_PORT4_TX_DIV_CLK_SRC 60 +#define NSS_CC_PORT5_MAC_CLK 61 +#define NSS_CC_PORT5_RX_CLK 62 +#define NSS_CC_PORT5_RX_CLK_SRC 63 +#define NSS_CC_PORT5_RX_DIV_CLK_SRC 64 +#define NSS_CC_PORT5_TX_CLK 65 +#define NSS_CC_PORT5_TX_CLK_SRC 66 +#define NSS_CC_PORT5_TX_DIV_CLK_SRC 67 +#define NSS_CC_PORT6_MAC_CLK 68 +#define NSS_CC_PORT6_RX_CLK 69 +#define NSS_CC_PORT6_RX_CLK_SRC 70 +#define NSS_CC_PORT6_RX_DIV_CLK_SRC 71 +#define NSS_CC_PORT6_TX_CLK 72 +#define NSS_CC_PORT6_TX_CLK_SRC 73 +#define NSS_CC_PORT6_TX_DIV_CLK_SRC 74 +#define NSS_CC_PPE_CLK_SRC 75 +#define NSS_CC_PPE_EDMA_CFG_CLK 76 +#define NSS_CC_PPE_EDMA_CLK 77 +#define NSS_CC_PPE_SWITCH_BTQ_CLK 78 +#define NSS_CC_PPE_SWITCH_CFG_CLK 79 +#define NSS_CC_PPE_SWITCH_CLK 80 +#define NSS_CC_PPE_SWITCH_IPE_CLK 81 +#define NSS_CC_UBI0_CLK_SRC 82 +#define NSS_CC_UBI0_DIV_CLK_SRC 83 +#define NSS_CC_UBI1_CLK_SRC 84 +#define NSS_CC_UBI1_DIV_CLK_SRC 85 +#define NSS_CC_UBI2_CLK_SRC 86 +#define NSS_CC_UBI2_DIV_CLK_SRC 87 +#define NSS_CC_UBI32_AHB0_CLK 88 +#define NSS_CC_UBI32_AHB1_CLK 89 +#define NSS_CC_UBI32_AHB2_CLK 90 +#define NSS_CC_UBI32_AHB3_CLK 91 +#define NSS_CC_UBI32_AXI0_CLK 92 +#define NSS_CC_UBI32_AXI1_CLK 93 +#define NSS_CC_UBI32_AXI2_CLK 94 +#define NSS_CC_UBI32_AXI3_CLK 95 +#define NSS_CC_UBI32_CORE0_CLK 96 +#define NSS_CC_UBI32_CORE1_CLK 97 +#define NSS_CC_UBI32_CORE2_CLK 98 +#define NSS_CC_UBI32_CORE3_CLK 99 +#define NSS_CC_UBI32_INTR0_AHB_CLK 100 +#define NSS_CC_UBI32_INTR1_AHB_CLK 101 +#define NSS_CC_UBI32_INTR2_AHB_CLK 102 +#define NSS_CC_UBI32_INTR3_AHB_CLK 103 +#define NSS_CC_UBI32_NC_AXI0_CLK 104 +#define NSS_CC_UBI32_NC_AXI1_CLK 105 +#define NSS_CC_UBI32_NC_AXI2_CLK 106 +#define NSS_CC_UBI32_NC_AXI3_CLK 107 +#define NSS_CC_UBI32_UTCM0_CLK 108 +#define NSS_CC_UBI32_UTCM1_CLK 109 +#define NSS_CC_UBI32_UTCM2_CLK 110 +#define NSS_CC_UBI32_UTCM3_CLK 111 +#define NSS_CC_UBI3_CLK_SRC 112 +#define NSS_CC_UBI3_DIV_CLK_SRC 113 +#define NSS_CC_UBI_AXI_CLK_SRC 114 +#define NSS_CC_UBI_NC_AXI_BFDCD_CLK_SRC 115 +#define NSS_CC_UNIPHY_PORT1_RX_CLK 116 +#define NSS_CC_UNIPHY_PORT1_TX_CLK 117 +#define NSS_CC_UNIPHY_PORT2_RX_CLK 118 +#define NSS_CC_UNIPHY_PORT2_TX_CLK 119 +#define NSS_CC_UNIPHY_PORT3_RX_CLK 120 +#define NSS_CC_UNIPHY_PORT3_TX_CLK 121 +#define NSS_CC_UNIPHY_PORT4_RX_CLK 122 +#define NSS_CC_UNIPHY_PORT4_TX_CLK 123 +#define NSS_CC_UNIPHY_PORT5_RX_CLK 124 +#define NSS_CC_UNIPHY_PORT5_TX_CLK 125 +#define NSS_CC_UNIPHY_PORT6_RX_CLK 126 +#define NSS_CC_UNIPHY_PORT6_TX_CLK 127 +#define NSS_CC_XGMAC0_PTP_REF_CLK 128 +#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 129 +#define NSS_CC_XGMAC1_PTP_REF_CLK 130 +#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 131 +#define NSS_CC_XGMAC2_PTP_REF_CLK 132 +#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 133 +#define NSS_CC_XGMAC3_PTP_REF_CLK 134 +#define NSS_CC_XGMAC3_PTP_REF_DIV_CLK_SRC 135 +#define NSS_CC_XGMAC4_PTP_REF_CLK 136 +#define NSS_CC_XGMAC4_PTP_REF_DIV_CLK_SRC 137 +#define NSS_CC_XGMAC5_PTP_REF_CLK 138 +#define NSS_CC_XGMAC5_PTP_REF_DIV_CLK_SRC 139 +#define UBI32_PLL 140 +#define UBI32_PLL_MAIN 141 + +#endif diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h index 46309c9953b..1477a75e7f6 100644 --- a/include/dt-bindings/clock/qcom,rpmcc.h +++ b/include/dt-bindings/clock/qcom,rpmcc.h @@ -170,5 +170,9 @@ #define RPM_SMD_BIMC_FREQ_LOG 124 #define RPM_SMD_LN_BB_CLK_PIN 125 #define RPM_SMD_LN_BB_A_CLK_PIN 126 +#define RPM_SMD_BB_CLK3 127 +#define RPM_SMD_BB_CLK3_A 128 +#define RPM_SMD_BB_CLK3_PIN 129 +#define RPM_SMD_BB_CLK3_A_PIN 130 #endif diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h index 01e14ab252a..dd988cc9d58 100644 --- a/include/dt-bindings/clock/rk3188-cru-common.h +++ b/include/dt-bindings/clock/rk3188-cru-common.h @@ -103,6 +103,8 @@ #define PCLK_PERI 351 #define PCLK_DDRUPCTL 352 #define PCLK_PUBL 353 +#define PCLK_CIF0 354 +#define PCLK_CIF1 355 /* hclk gates */ #define HCLK_SDMMC 448 diff --git a/include/dt-bindings/clock/rockchip,rk3528-cru.h b/include/dt-bindings/clock/rockchip,rk3528-cru.h new file mode 100644 index 00000000000..55a448f5ed6 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3528-cru.h @@ -0,0 +1,453 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi + * Author: Joseph Chen + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H + +/* cru-clocks indices */ +#define PLL_APLL 0 +#define PLL_CPLL 1 +#define PLL_GPLL 2 +#define PLL_PPLL 3 +#define PLL_DPLL 4 +#define ARMCLK 5 +#define XIN_OSC0_HALF 6 +#define CLK_MATRIX_50M_SRC 7 +#define CLK_MATRIX_100M_SRC 8 +#define CLK_MATRIX_150M_SRC 9 +#define CLK_MATRIX_200M_SRC 10 +#define CLK_MATRIX_250M_SRC 11 +#define CLK_MATRIX_300M_SRC 12 +#define CLK_MATRIX_339M_SRC 13 +#define CLK_MATRIX_400M_SRC 14 +#define CLK_MATRIX_500M_SRC 15 +#define CLK_MATRIX_600M_SRC 16 +#define CLK_UART0_SRC 17 +#define CLK_UART0_FRAC 18 +#define SCLK_UART0 19 +#define CLK_UART1_SRC 20 +#define CLK_UART1_FRAC 21 +#define SCLK_UART1 22 +#define CLK_UART2_SRC 23 +#define CLK_UART2_FRAC 24 +#define SCLK_UART2 25 +#define CLK_UART3_SRC 26 +#define CLK_UART3_FRAC 27 +#define SCLK_UART3 28 +#define CLK_UART4_SRC 29 +#define CLK_UART4_FRAC 30 +#define SCLK_UART4 31 +#define CLK_UART5_SRC 32 +#define CLK_UART5_FRAC 33 +#define SCLK_UART5 34 +#define CLK_UART6_SRC 35 +#define CLK_UART6_FRAC 36 +#define SCLK_UART6 37 +#define CLK_UART7_SRC 38 +#define CLK_UART7_FRAC 39 +#define SCLK_UART7 40 +#define CLK_I2S0_2CH_SRC 41 +#define CLK_I2S0_2CH_FRAC 42 +#define MCLK_I2S0_2CH_SAI_SRC 43 +#define CLK_I2S3_8CH_SRC 44 +#define CLK_I2S3_8CH_FRAC 45 +#define MCLK_I2S3_8CH_SAI_SRC 46 +#define CLK_I2S1_8CH_SRC 47 +#define CLK_I2S1_8CH_FRAC 48 +#define MCLK_I2S1_8CH_SAI_SRC 49 +#define CLK_I2S2_2CH_SRC 50 +#define CLK_I2S2_2CH_FRAC 51 +#define MCLK_I2S2_2CH_SAI_SRC 52 +#define CLK_SPDIF_SRC 53 +#define CLK_SPDIF_FRAC 54 +#define MCLK_SPDIF_SRC 55 +#define DCLK_VOP_SRC0 56 +#define DCLK_VOP_SRC1 57 +#define CLK_HSM 58 +#define CLK_CORE_SRC_ACS 59 +#define CLK_CORE_SRC_PVTMUX 60 +#define CLK_CORE_SRC 61 +#define CLK_CORE 62 +#define ACLK_M_CORE_BIU 63 +#define CLK_CORE_PVTPLL_SRC 64 +#define PCLK_DBG 65 +#define SWCLKTCK 66 +#define CLK_SCANHS_CORE 67 +#define CLK_SCANHS_ACLKM_CORE 68 +#define CLK_SCANHS_PCLK_DBG 69 +#define CLK_SCANHS_PCLK_CPU_BIU 70 +#define PCLK_CPU_ROOT 71 +#define PCLK_CORE_GRF 72 +#define PCLK_DAPLITE_BIU 73 +#define PCLK_CPU_BIU 74 +#define CLK_REF_PVTPLL_CORE 75 +#define ACLK_BUS_VOPGL_ROOT 76 +#define ACLK_BUS_VOPGL_BIU 77 +#define ACLK_BUS_H_ROOT 78 +#define ACLK_BUS_H_BIU 79 +#define ACLK_BUS_ROOT 80 +#define HCLK_BUS_ROOT 81 +#define PCLK_BUS_ROOT 82 +#define ACLK_BUS_M_ROOT 83 +#define ACLK_SYSMEM_BIU 84 +#define CLK_TIMER_ROOT 85 +#define ACLK_BUS_BIU 86 +#define HCLK_BUS_BIU 87 +#define PCLK_BUS_BIU 88 +#define PCLK_DFT2APB 89 +#define PCLK_BUS_GRF 90 +#define ACLK_BUS_M_BIU 91 +#define ACLK_GIC 92 +#define ACLK_SPINLOCK 93 +#define ACLK_DMAC 94 +#define PCLK_TIMER 95 +#define CLK_TIMER0 96 +#define CLK_TIMER1 97 +#define CLK_TIMER2 98 +#define CLK_TIMER3 99 +#define CLK_TIMER4 100 +#define CLK_TIMER5 101 +#define PCLK_JDBCK_DAP 102 +#define CLK_JDBCK_DAP 103 +#define PCLK_WDT_NS 104 +#define TCLK_WDT_NS 105 +#define HCLK_TRNG_NS 106 +#define PCLK_UART0 107 +#define PCLK_DMA2DDR 108 +#define ACLK_DMA2DDR 109 +#define PCLK_PWM0 110 +#define CLK_PWM0 111 +#define CLK_CAPTURE_PWM0 112 +#define PCLK_PWM1 113 +#define CLK_PWM1 114 +#define CLK_CAPTURE_PWM1 115 +#define PCLK_SCR 116 +#define ACLK_DCF 117 +#define PCLK_INTMUX 118 +#define CLK_PPLL_I 119 +#define CLK_PPLL_MUX 120 +#define CLK_PPLL_100M_MATRIX 121 +#define CLK_PPLL_50M_MATRIX 122 +#define CLK_REF_PCIE_INNER_PHY 123 +#define CLK_REF_PCIE_100M_PHY 124 +#define ACLK_VPU_L_ROOT 125 +#define CLK_GMAC1_VPU_25M 126 +#define CLK_PPLL_125M_MATRIX 127 +#define ACLK_VPU_ROOT 128 +#define HCLK_VPU_ROOT 129 +#define PCLK_VPU_ROOT 130 +#define ACLK_VPU_BIU 131 +#define HCLK_VPU_BIU 132 +#define PCLK_VPU_BIU 133 +#define ACLK_VPU 134 +#define HCLK_VPU 135 +#define PCLK_CRU_PCIE 136 +#define PCLK_VPU_GRF 137 +#define HCLK_SFC 138 +#define SCLK_SFC 139 +#define CCLK_SRC_EMMC 140 +#define HCLK_EMMC 141 +#define ACLK_EMMC 142 +#define BCLK_EMMC 143 +#define TCLK_EMMC 144 +#define PCLK_GPIO1 145 +#define DBCLK_GPIO1 146 +#define ACLK_VPU_L_BIU 147 +#define PCLK_VPU_IOC 148 +#define HCLK_SAI_I2S0 149 +#define MCLK_SAI_I2S0 150 +#define HCLK_SAI_I2S2 151 +#define MCLK_SAI_I2S2 152 +#define PCLK_ACODEC 153 +#define MCLK_ACODEC_TX 154 +#define PCLK_GPIO3 155 +#define DBCLK_GPIO3 156 +#define PCLK_SPI1 157 +#define CLK_SPI1 158 +#define SCLK_IN_SPI1 159 +#define PCLK_UART2 160 +#define PCLK_UART5 161 +#define PCLK_UART6 162 +#define PCLK_UART7 163 +#define PCLK_I2C3 164 +#define CLK_I2C3 165 +#define PCLK_I2C5 166 +#define CLK_I2C5 167 +#define PCLK_I2C6 168 +#define CLK_I2C6 169 +#define ACLK_MAC_VPU 170 +#define PCLK_MAC_VPU 171 +#define CLK_GMAC1_RMII_VPU 172 +#define CLK_GMAC1_SRC_VPU 173 +#define PCLK_PCIE 174 +#define CLK_PCIE_AUX 175 +#define ACLK_PCIE 176 +#define HCLK_PCIE_SLV 177 +#define HCLK_PCIE_DBI 178 +#define PCLK_PCIE_PHY 179 +#define PCLK_PIPE_GRF 180 +#define CLK_PIPE_USB3OTG_COMBO 181 +#define CLK_UTMI_USB3OTG 182 +#define CLK_PCIE_PIPE_PHY 183 +#define CCLK_SRC_SDIO0 184 +#define HCLK_SDIO0 185 +#define CCLK_SRC_SDIO1 186 +#define HCLK_SDIO1 187 +#define CLK_TS_0 188 +#define CLK_TS_1 189 +#define PCLK_CAN2 190 +#define CLK_CAN2 191 +#define PCLK_CAN3 192 +#define CLK_CAN3 193 +#define PCLK_SARADC 194 +#define CLK_SARADC 195 +#define PCLK_TSADC 196 +#define CLK_TSADC 197 +#define CLK_TSADC_TSEN 198 +#define ACLK_USB3OTG 199 +#define CLK_REF_USB3OTG 200 +#define CLK_SUSPEND_USB3OTG 201 +#define ACLK_GPU_ROOT 202 +#define PCLK_GPU_ROOT 203 +#define ACLK_GPU_BIU 204 +#define PCLK_GPU_BIU 205 +#define ACLK_GPU 206 +#define CLK_GPU_PVTPLL_SRC 207 +#define ACLK_GPU_MALI 208 +#define HCLK_RKVENC_ROOT 209 +#define ACLK_RKVENC_ROOT 210 +#define PCLK_RKVENC_ROOT 211 +#define HCLK_RKVENC_BIU 212 +#define ACLK_RKVENC_BIU 213 +#define PCLK_RKVENC_BIU 214 +#define HCLK_RKVENC 215 +#define ACLK_RKVENC 216 +#define CLK_CORE_RKVENC 217 +#define HCLK_SAI_I2S1 218 +#define MCLK_SAI_I2S1 219 +#define PCLK_I2C1 220 +#define CLK_I2C1 221 +#define PCLK_I2C0 222 +#define CLK_I2C0 223 +#define CLK_UART_JTAG 224 +#define PCLK_SPI0 225 +#define CLK_SPI0 226 +#define SCLK_IN_SPI0 227 +#define PCLK_GPIO4 228 +#define DBCLK_GPIO4 229 +#define PCLK_RKVENC_IOC 230 +#define HCLK_SPDIF 231 +#define MCLK_SPDIF 232 +#define HCLK_PDM 233 +#define MCLK_PDM 234 +#define PCLK_UART1 235 +#define PCLK_UART3 236 +#define PCLK_RKVENC_GRF 237 +#define PCLK_CAN0 238 +#define CLK_CAN0 239 +#define PCLK_CAN1 240 +#define CLK_CAN1 241 +#define ACLK_VO_ROOT 242 +#define HCLK_VO_ROOT 243 +#define PCLK_VO_ROOT 244 +#define ACLK_VO_BIU 245 +#define HCLK_VO_BIU 246 +#define PCLK_VO_BIU 247 +#define HCLK_RGA2E 248 +#define ACLK_RGA2E 249 +#define CLK_CORE_RGA2E 250 +#define HCLK_VDPP 251 +#define ACLK_VDPP 252 +#define CLK_CORE_VDPP 253 +#define PCLK_VO_GRF 254 +#define PCLK_CRU 255 +#define ACLK_VOP_ROOT 256 +#define ACLK_VOP_BIU 257 +#define HCLK_VOP 258 +#define DCLK_VOP0 259 +#define DCLK_VOP1 260 +#define ACLK_VOP 261 +#define PCLK_HDMI 262 +#define CLK_SFR_HDMI 263 +#define CLK_CEC_HDMI 264 +#define CLK_SPDIF_HDMI 265 +#define CLK_HDMIPHY_TMDSSRC 266 +#define CLK_HDMIPHY_PREP 267 +#define PCLK_HDMIPHY 268 +#define HCLK_HDCP_KEY 269 +#define ACLK_HDCP 270 +#define HCLK_HDCP 271 +#define PCLK_HDCP 272 +#define HCLK_CVBS 273 +#define DCLK_CVBS 274 +#define DCLK_4X_CVBS 275 +#define ACLK_JPEG_DECODER 276 +#define HCLK_JPEG_DECODER 277 +#define ACLK_VO_L_ROOT 278 +#define ACLK_VO_L_BIU 279 +#define ACLK_MAC_VO 280 +#define PCLK_MAC_VO 281 +#define CLK_GMAC0_SRC 282 +#define CLK_GMAC0_RMII_50M 283 +#define CLK_GMAC0_TX 284 +#define CLK_GMAC0_RX 285 +#define ACLK_JPEG_ROOT 286 +#define ACLK_JPEG_BIU 287 +#define HCLK_SAI_I2S3 288 +#define MCLK_SAI_I2S3 289 +#define CLK_MACPHY 290 +#define PCLK_VCDCPHY 291 +#define PCLK_GPIO2 292 +#define DBCLK_GPIO2 293 +#define PCLK_VO_IOC 294 +#define CCLK_SRC_SDMMC0 295 +#define HCLK_SDMMC0 296 +#define PCLK_OTPC_NS 297 +#define CLK_SBPI_OTPC_NS 298 +#define CLK_USER_OTPC_NS 299 +#define CLK_HDMIHDP0 300 +#define HCLK_USBHOST 301 +#define HCLK_USBHOST_ARB 302 +#define CLK_USBHOST_OHCI 303 +#define CLK_USBHOST_UTMI 304 +#define PCLK_UART4 305 +#define PCLK_I2C4 306 +#define CLK_I2C4 307 +#define PCLK_I2C7 308 +#define CLK_I2C7 309 +#define PCLK_USBPHY 310 +#define CLK_REF_USBPHY 311 +#define HCLK_RKVDEC_ROOT 312 +#define ACLK_RKVDEC_ROOT_NDFT 313 +#define PCLK_DDRPHY_CRU 314 +#define HCLK_RKVDEC_BIU 315 +#define ACLK_RKVDEC_BIU 316 +#define ACLK_RKVDEC 317 +#define HCLK_RKVDEC 318 +#define CLK_HEVC_CA_RKVDEC 319 +#define ACLK_RKVDEC_PVTMUX_ROOT 320 +#define CLK_RKVDEC_PVTPLL_SRC 321 +#define PCLK_DDR_ROOT 322 +#define PCLK_DDR_BIU 323 +#define PCLK_DDRC 324 +#define PCLK_DDRMON 325 +#define CLK_TIMER_DDRMON 326 +#define PCLK_MSCH_BIU 327 +#define PCLK_DDR_GRF 328 +#define PCLK_DDR_HWLP 329 +#define PCLK_DDRPHY 330 +#define CLK_MSCH_BIU 331 +#define ACLK_DDR_UPCTL 332 +#define CLK_DDR_UPCTL 333 +#define CLK_DDRMON 334 +#define ACLK_DDR_SCRAMBLE 335 +#define ACLK_SPLIT 336 +#define CLK_DDRC_SRC 337 +#define CLK_DDR_PHY 338 +#define PCLK_OTPC_S 339 +#define CLK_SBPI_OTPC_S 340 +#define CLK_USER_OTPC_S 341 +#define PCLK_KEYREADER 342 +#define PCLK_BUS_SGRF 343 +#define PCLK_STIMER 344 +#define CLK_STIMER0 345 +#define CLK_STIMER1 346 +#define PCLK_WDT_S 347 +#define TCLK_WDT_S 348 +#define HCLK_TRNG_S 349 +#define HCLK_BOOTROM 350 +#define PCLK_DCF 351 +#define ACLK_SYSMEM 352 +#define HCLK_TSP 353 +#define ACLK_TSP 354 +#define CLK_CORE_TSP 355 +#define CLK_OTPC_ARB 356 +#define PCLK_OTP_MASK 357 +#define CLK_PMC_OTP 358 +#define PCLK_PMU_ROOT 359 +#define HCLK_PMU_ROOT 360 +#define PCLK_I2C2 361 +#define CLK_I2C2 362 +#define HCLK_PMU_BIU 363 +#define PCLK_PMU_BIU 364 +#define FCLK_MCU 365 +#define RTC_CLK_MCU 366 +#define PCLK_OSCCHK 367 +#define CLK_PMU_MCU_JTAG 368 +#define PCLK_PMU 369 +#define PCLK_GPIO0 370 +#define DBCLK_GPIO0 371 +#define XIN_OSC0_DIV 372 +#define CLK_DEEPSLOW 373 +#define CLK_DDR_FAIL_SAFE 374 +#define PCLK_PMU_HP_TIMER 375 +#define CLK_PMU_HP_TIMER 376 +#define CLK_PMU_32K_HP_TIMER 377 +#define PCLK_PMU_IOC 378 +#define PCLK_PMU_CRU 379 +#define PCLK_PMU_GRF 380 +#define PCLK_PMU_WDT 381 +#define TCLK_PMU_WDT 382 +#define PCLK_PMU_MAILBOX 383 +#define PCLK_SCRKEYGEN 384 +#define CLK_SCRKEYGEN 385 +#define CLK_PVTM_OSCCHK 386 +#define CLK_REFOUT 387 +#define CLK_PVTM_PMU 388 +#define PCLK_PVTM_PMU 389 +#define PCLK_PMU_SGRF 390 +#define HCLK_PMU_SRAM 391 +#define CLK_UART0 392 +#define CLK_UART1 393 +#define CLK_UART2 394 +#define CLK_UART3 395 +#define CLK_UART4 396 +#define CLK_UART5 397 +#define CLK_UART6 398 +#define CLK_UART7 399 +#define MCLK_I2S0_2CH_SAI_SRC_PRE 400 +#define MCLK_I2S1_8CH_SAI_SRC_PRE 401 +#define MCLK_I2S2_2CH_SAI_SRC_PRE 402 +#define MCLK_I2S3_8CH_SAI_SRC_PRE 403 +#define MCLK_SDPDIF_SRC_PRE 404 + +/* scmi-clocks indices */ +#define SCMI_PCLK_KEYREADER 0 +#define SCMI_HCLK_KLAD 1 +#define SCMI_PCLK_KLAD 2 +#define SCMI_HCLK_TRNG_S 3 +#define SCMI_HCLK_CRYPTO_S 4 +#define SCMI_PCLK_WDT_S 5 +#define SCMI_TCLK_WDT_S 6 +#define SCMI_PCLK_STIMER 7 +#define SCMI_CLK_STIMER0 8 +#define SCMI_CLK_STIMER1 9 +#define SCMI_PCLK_OTP_MASK 10 +#define SCMI_PCLK_OTPC_S 11 +#define SCMI_CLK_SBPI_OTPC_S 12 +#define SCMI_CLK_USER_OTPC_S 13 +#define SCMI_CLK_PMC_OTP 14 +#define SCMI_CLK_OTPC_ARB 15 +#define SCMI_CLK_CORE_TSP 16 +#define SCMI_ACLK_TSP 17 +#define SCMI_HCLK_TSP 18 +#define SCMI_PCLK_DCF 19 +#define SCMI_CLK_DDR 20 +#define SCMI_CLK_CPU 21 +#define SCMI_CLK_GPU 22 +#define SCMI_CORE_CRYPTO 23 +#define SCMI_ACLK_CRYPTO 24 +#define SCMI_PKA_CRYPTO 25 +#define SCMI_HCLK_CRYPTO 26 +#define SCMI_CORE_CRYPTO_S 27 +#define SCMI_ACLK_CRYPTO_S 28 +#define SCMI_PKA_CRYPTO_S 29 +#define SCMI_CORE_KLAD 30 +#define SCMI_ACLK_KLAD 31 +#define SCMI_HCLK_TRNG 32 + +#endif // _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H diff --git a/include/dt-bindings/clock/rockchip,rk3562-cru.h b/include/dt-bindings/clock/rockchip,rk3562-cru.h new file mode 100644 index 00000000000..a5b0b153209 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3562-cru.h @@ -0,0 +1,379 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2022-2025 Rockchip Electronics Co., Ltd. + * Author: Finley Xiao + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_DMPLL0 0 +#define PLL_APLL 1 +#define PLL_GPLL 2 +#define PLL_VPLL 3 +#define PLL_HPLL 4 +#define PLL_CPLL 5 +#define PLL_DPLL 6 +#define PLL_DMPLL1 7 + +/* cru clocks */ +#define ARMCLK 8 +#define CLK_GPU 9 +#define ACLK_RKNN 10 +#define CLK_DDR 11 +#define CLK_MATRIX_50M_SRC 12 +#define CLK_MATRIX_100M_SRC 13 +#define CLK_MATRIX_125M_SRC 14 +#define CLK_MATRIX_200M_SRC 15 +#define CLK_MATRIX_300M_SRC 16 +#define ACLK_TOP 17 +#define ACLK_TOP_VIO 18 +#define CLK_CAM0_OUT2IO 19 +#define CLK_CAM1_OUT2IO 20 +#define CLK_CAM2_OUT2IO 21 +#define CLK_CAM3_OUT2IO 22 +#define ACLK_BUS 23 +#define HCLK_BUS 24 +#define PCLK_BUS 25 +#define PCLK_I2C1 26 +#define PCLK_I2C2 27 +#define PCLK_I2C3 28 +#define PCLK_I2C4 29 +#define PCLK_I2C5 30 +#define CLK_I2C 31 +#define CLK_I2C1 32 +#define CLK_I2C2 33 +#define CLK_I2C3 34 +#define CLK_I2C4 35 +#define CLK_I2C5 36 +#define DCLK_BUS_GPIO 37 +#define DCLK_BUS_GPIO3 38 +#define DCLK_BUS_GPIO4 39 +#define PCLK_TIMER 40 +#define CLK_TIMER0 41 +#define CLK_TIMER1 42 +#define CLK_TIMER2 43 +#define CLK_TIMER3 44 +#define CLK_TIMER4 45 +#define CLK_TIMER5 46 +#define PCLK_STIMER 47 +#define CLK_STIMER0 48 +#define CLK_STIMER1 49 +#define PCLK_WDTNS 50 +#define CLK_WDTNS 51 +#define PCLK_GRF 52 +#define PCLK_SGRF 53 +#define PCLK_MAILBOX 54 +#define PCLK_INTC 55 +#define ACLK_BUS_GIC400 56 +#define ACLK_BUS_SPINLOCK 57 +#define ACLK_DCF 58 +#define PCLK_DCF 59 +#define FCLK_BUS_CM0_CORE 60 +#define CLK_BUS_CM0_RTC 61 +#define HCLK_ICACHE 62 +#define HCLK_DCACHE 63 +#define PCLK_TSADC 64 +#define CLK_TSADC 65 +#define CLK_TSADC_TSEN 66 +#define PCLK_DFT2APB 67 +#define CLK_SARADC_VCCIO156 68 +#define PCLK_GMAC 69 +#define ACLK_GMAC 70 +#define CLK_GMAC_125M_CRU_I 71 +#define CLK_GMAC_50M_CRU_I 72 +#define CLK_GMAC_50M_O 73 +#define CLK_GMAC_ETH_OUT2IO 74 +#define PCLK_APB2ASB_VCCIO156 75 +#define PCLK_TO_VCCIO156 76 +#define PCLK_DSIPHY 77 +#define PCLK_DSITX 78 +#define PCLK_CPU_EMA_DET 79 +#define PCLK_HASH 80 +#define PCLK_TOPCRU 81 +#define PCLK_ASB2APB_VCCIO156 82 +#define PCLK_IOC_VCCIO156 83 +#define PCLK_GPIO3_VCCIO156 84 +#define PCLK_GPIO4_VCCIO156 85 +#define PCLK_SARADC_VCCIO156 86 +#define PCLK_MAC100 87 +#define ACLK_MAC100 89 +#define CLK_MAC100_50M_MATRIX 90 +#define HCLK_CORE 91 +#define PCLK_DDR 92 +#define CLK_MSCH_BRG_BIU 93 +#define PCLK_DDR_HWLP 94 +#define PCLK_DDR_UPCTL 95 +#define PCLK_DDR_PHY 96 +#define PCLK_DDR_DFICTL 97 +#define PCLK_DDR_DMA2DDR 98 +#define PCLK_DDR_MON 99 +#define TMCLK_DDR_MON 100 +#define PCLK_DDR_GRF 101 +#define PCLK_DDR_CRU 102 +#define PCLK_SUBDDR_CRU 103 +#define CLK_GPU_PRE 104 +#define ACLK_GPU_PRE 105 +#define CLK_GPU_BRG 107 +#define CLK_NPU_PRE 108 +#define HCLK_NPU_PRE 109 +#define HCLK_RKNN 111 +#define ACLK_PERI 112 +#define HCLK_PERI 113 +#define PCLK_PERI 114 +#define PCLK_PERICRU 115 +#define HCLK_SAI0 116 +#define CLK_SAI0_SRC 117 +#define CLK_SAI0_FRAC 118 +#define CLK_SAI0 119 +#define MCLK_SAI0 120 +#define MCLK_SAI0_OUT2IO 121 +#define HCLK_SAI1 122 +#define CLK_SAI1_SRC 123 +#define CLK_SAI1_FRAC 124 +#define CLK_SAI1 125 +#define MCLK_SAI1 126 +#define MCLK_SAI1_OUT2IO 127 +#define HCLK_SAI2 128 +#define CLK_SAI2_SRC 129 +#define CLK_SAI2_FRAC 130 +#define CLK_SAI2 131 +#define MCLK_SAI2 132 +#define MCLK_SAI2_OUT2IO 133 +#define HCLK_DSM 134 +#define CLK_DSM 135 +#define HCLK_PDM 136 +#define MCLK_PDM 137 +#define HCLK_SPDIF 138 +#define CLK_SPDIF_SRC 139 +#define CLK_SPDIF_FRAC 140 +#define CLK_SPDIF 141 +#define MCLK_SPDIF 142 +#define HCLK_SDMMC0 143 +#define CCLK_SDMMC0 144 +#define HCLK_SDMMC1 145 +#define CCLK_SDMMC1 146 +#define SCLK_SDMMC0_DRV 147 +#define SCLK_SDMMC0_SAMPLE 148 +#define SCLK_SDMMC1_DRV 149 +#define SCLK_SDMMC1_SAMPLE 150 +#define HCLK_EMMC 151 +#define ACLK_EMMC 152 +#define CCLK_EMMC 153 +#define BCLK_EMMC 154 +#define TMCLK_EMMC 155 +#define SCLK_SFC 156 +#define HCLK_SFC 157 +#define HCLK_USB2HOST 158 +#define HCLK_USB2HOST_ARB 159 +#define PCLK_SPI1 160 +#define CLK_SPI1 161 +#define SCLK_IN_SPI1 162 +#define PCLK_SPI2 163 +#define CLK_SPI2 164 +#define SCLK_IN_SPI2 165 +#define PCLK_UART1 166 +#define PCLK_UART2 167 +#define PCLK_UART3 168 +#define PCLK_UART4 169 +#define PCLK_UART5 170 +#define PCLK_UART6 171 +#define PCLK_UART7 172 +#define PCLK_UART8 173 +#define PCLK_UART9 174 +#define CLK_UART1_SRC 175 +#define CLK_UART1_FRAC 176 +#define CLK_UART1 177 +#define SCLK_UART1 178 +#define CLK_UART2_SRC 179 +#define CLK_UART2_FRAC 180 +#define CLK_UART2 181 +#define SCLK_UART2 182 +#define CLK_UART3_SRC 183 +#define CLK_UART3_FRAC 184 +#define CLK_UART3 185 +#define SCLK_UART3 186 +#define CLK_UART4_SRC 187 +#define CLK_UART4_FRAC 188 +#define CLK_UART4 189 +#define SCLK_UART4 190 +#define CLK_UART5_SRC 191 +#define CLK_UART5_FRAC 192 +#define CLK_UART5 193 +#define SCLK_UART5 194 +#define CLK_UART6_SRC 195 +#define CLK_UART6_FRAC 196 +#define CLK_UART6 197 +#define SCLK_UART6 198 +#define CLK_UART7_SRC 199 +#define CLK_UART7_FRAC 200 +#define CLK_UART7 201 +#define SCLK_UART7 202 +#define CLK_UART8_SRC 203 +#define CLK_UART8_FRAC 204 +#define CLK_UART8 205 +#define SCLK_UART8 206 +#define CLK_UART9_SRC 207 +#define CLK_UART9_FRAC 208 +#define CLK_UART9 209 +#define SCLK_UART9 210 +#define PCLK_PWM1_PERI 211 +#define CLK_PWM1_PERI 212 +#define CLK_CAPTURE_PWM1_PERI 213 +#define PCLK_PWM2_PERI 214 +#define CLK_PWM2_PERI 215 +#define CLK_CAPTURE_PWM2_PERI 216 +#define PCLK_PWM3_PERI 217 +#define CLK_PWM3_PERI 218 +#define CLK_CAPTURE_PWM3_PERI 219 +#define PCLK_CAN0 220 +#define CLK_CAN0 221 +#define PCLK_CAN1 222 +#define CLK_CAN1 223 +#define ACLK_CRYPTO 224 +#define HCLK_CRYPTO 225 +#define PCLK_CRYPTO 226 +#define CLK_CORE_CRYPTO 227 +#define CLK_PKA_CRYPTO 228 +#define HCLK_KLAD 229 +#define PCLK_KEY_READER 230 +#define HCLK_RK_RNG_NS 231 +#define HCLK_RK_RNG_S 232 +#define HCLK_TRNG_NS 233 +#define HCLK_TRNG_S 234 +#define HCLK_CRYPTO_S 235 +#define PCLK_PERI_WDT 236 +#define TCLK_PERI_WDT 237 +#define ACLK_SYSMEM 238 +#define HCLK_BOOTROM 239 +#define PCLK_PERI_GRF 240 +#define ACLK_DMAC 241 +#define ACLK_RKDMAC 242 +#define PCLK_OTPC_NS 243 +#define CLK_SBPI_OTPC_NS 244 +#define CLK_USER_OTPC_NS 245 +#define PCLK_OTPC_S 246 +#define CLK_SBPI_OTPC_S 247 +#define CLK_USER_OTPC_S 248 +#define CLK_OTPC_ARB 249 +#define PCLK_OTPPHY 250 +#define PCLK_USB2PHY 251 +#define PCLK_PIPEPHY 252 +#define PCLK_SARADC 253 +#define CLK_SARADC 254 +#define PCLK_IOC_VCCIO234 255 +#define PCLK_PERI_GPIO1 256 +#define PCLK_PERI_GPIO2 257 +#define DCLK_PERI_GPIO 258 +#define DCLK_PERI_GPIO1 259 +#define DCLK_PERI_GPIO2 260 +#define ACLK_PHP 261 +#define PCLK_PHP 262 +#define ACLK_PCIE20_MST 263 +#define ACLK_PCIE20_SLV 264 +#define ACLK_PCIE20_DBI 265 +#define PCLK_PCIE20 266 +#define CLK_PCIE20_AUX 267 +#define ACLK_USB3OTG 268 +#define CLK_USB3OTG_SUSPEND 269 +#define CLK_USB3OTG_REF 270 +#define CLK_PIPEPHY_REF_FUNC 271 +#define CLK_200M_PMU 272 +#define CLK_RTC_32K 273 +#define CLK_RTC32K_FRAC 274 +#define BUSCLK_PDPMU0 275 +#define PCLK_PMU0_CRU 276 +#define PCLK_PMU0_PMU 277 +#define CLK_PMU0_PMU 278 +#define PCLK_PMU0_HP_TIMER 279 +#define CLK_PMU0_HP_TIMER 280 +#define CLK_PMU0_32K_HP_TIMER 281 +#define PCLK_PMU0_PVTM 282 +#define CLK_PMU0_PVTM 283 +#define PCLK_IOC_PMUIO 284 +#define PCLK_PMU0_GPIO0 285 +#define DBCLK_PMU0_GPIO0 286 +#define PCLK_PMU0_GRF 287 +#define PCLK_PMU0_SGRF 288 +#define CLK_DDR_FAIL_SAFE 289 +#define PCLK_PMU0_SCRKEYGEN 290 +#define PCLK_PMU1_CRU 291 +#define HCLK_PMU1_MEM 292 +#define PCLK_PMU0_I2C0 293 +#define CLK_PMU0_I2C0 294 +#define PCLK_PMU1_UART0 295 +#define CLK_PMU1_UART0_SRC 296 +#define CLK_PMU1_UART0_FRAC 297 +#define CLK_PMU1_UART0 298 +#define SCLK_PMU1_UART0 299 +#define PCLK_PMU1_SPI0 300 +#define CLK_PMU1_SPI0 301 +#define SCLK_IN_PMU1_SPI0 302 +#define PCLK_PMU1_PWM0 303 +#define CLK_PMU1_PWM0 304 +#define CLK_CAPTURE_PMU1_PWM0 305 +#define CLK_PMU1_WIFI 306 +#define FCLK_PMU1_CM0_CORE 307 +#define CLK_PMU1_CM0_RTC 308 +#define PCLK_PMU1_WDTNS 309 +#define CLK_PMU1_WDTNS 310 +#define PCLK_PMU1_MAILBOX 311 +#define CLK_PIPEPHY_DIV 312 +#define CLK_PIPEPHY_XIN24M 313 +#define CLK_PIPEPHY_REF 314 +#define CLK_24M_SSCSRC 315 +#define CLK_USB2PHY_XIN24M 316 +#define CLK_USB2PHY_REF 317 +#define CLK_MIPIDSIPHY_XIN24M 318 +#define CLK_MIPIDSIPHY_REF 319 +#define ACLK_RGA_PRE 320 +#define HCLK_RGA_PRE 321 +#define ACLK_RGA 322 +#define HCLK_RGA 323 +#define CLK_RGA_CORE 324 +#define ACLK_JDEC 325 +#define HCLK_JDEC 326 +#define ACLK_VDPU_PRE 327 +#define CLK_RKVDEC_HEVC_CA 328 +#define HCLK_VDPU_PRE 329 +#define ACLK_RKVDEC 330 +#define HCLK_RKVDEC 331 +#define CLK_RKVENC_CORE 332 +#define ACLK_VEPU_PRE 333 +#define HCLK_VEPU_PRE 334 +#define ACLK_RKVENC 335 +#define HCLK_RKVENC 336 +#define ACLK_VI 337 +#define HCLK_VI 338 +#define PCLK_VI 339 +#define ACLK_ISP 340 +#define HCLK_ISP 341 +#define CLK_ISP 342 +#define ACLK_VICAP 343 +#define HCLK_VICAP 344 +#define DCLK_VICAP 345 +#define CSIRX0_CLK_DATA 346 +#define CSIRX1_CLK_DATA 347 +#define CSIRX2_CLK_DATA 348 +#define CSIRX3_CLK_DATA 349 +#define PCLK_CSIHOST0 350 +#define PCLK_CSIHOST1 351 +#define PCLK_CSIHOST2 352 +#define PCLK_CSIHOST3 353 +#define PCLK_CSIPHY0 354 +#define PCLK_CSIPHY1 355 +#define ACLK_VO_PRE 356 +#define HCLK_VO_PRE 357 +#define ACLK_VOP 358 +#define HCLK_VOP 359 +#define DCLK_VOP 360 +#define DCLK_VOP1 361 +#define ACLK_CRYPTO_S 362 +#define PCLK_CRYPTO_S 363 +#define CLK_CORE_CRYPTO_S 364 +#define CLK_PKA_CRYPTO_S 365 + +#endif diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-bindings/clock/rockchip,rk3576-cru.h index 25aed298ac2..f576e61bec7 100644 --- a/include/dt-bindings/clock/rockchip,rk3576-cru.h +++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h @@ -589,4 +589,9 @@ #define PCLK_EDP_S 569 #define ACLK_KLAD 570 +/* SCMI clocks, use these when changing clocks through SCMI */ +#define SCMI_ARMCLK_L 10 +#define SCMI_ARMCLK_B 11 +#define SCMI_CLK_GPU 456 + #endif diff --git a/include/dt-bindings/clock/samsung,exynos2200-cmu.h b/include/dt-bindings/clock/samsung,exynos2200-cmu.h new file mode 100644 index 00000000000..310552be0c8 --- /dev/null +++ b/include/dt-bindings/clock/samsung,exynos2200-cmu.h @@ -0,0 +1,431 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 Ivaylo Ivanov + * Author: Ivaylo Ivanov + * + * Device Tree binding constants for Exynos2200 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS2200_H +#define _DT_BINDINGS_CLOCK_EXYNOS2200_H + +/* CMU_TOP */ +#define CLK_FOUT_SHARED0_PLL 1 +#define CLK_FOUT_SHARED1_PLL 2 +#define CLK_FOUT_SHARED2_PLL 3 +#define CLK_FOUT_SHARED3_PLL 4 +#define CLK_FOUT_SHARED4_PLL 5 +#define CLK_FOUT_MMC_PLL 6 +#define CLK_FOUT_SHARED_MIF_PLL 7 + +#define CLK_MOUT_CMU_CP_MPLL_CLK_D2_USER 8 +#define CLK_MOUT_CMU_CP_MPLL_CLK_USER 9 +#define CLK_MOUT_CMU_AUD_AUDIF0 10 +#define CLK_MOUT_CMU_AUD_AUDIF1 11 +#define CLK_MOUT_CMU_AUD_CPU 12 +#define CLK_MOUT_CMU_CPUCL0_DBG_NOC 13 +#define CLK_MOUT_CMU_CPUCL0_SWITCH 14 +#define CLK_MOUT_CMU_CPUCL1_SWITCH 15 +#define CLK_MOUT_CMU_CPUCL2_SWITCH 16 +#define CLK_MOUT_CMU_DNC_NOC 17 +#define CLK_MOUT_CMU_DPUB_NOC 18 +#define CLK_MOUT_CMU_DPUF_NOC 19 +#define CLK_MOUT_CMU_DSP_NOC 20 +#define CLK_MOUT_CMU_DSU_SWITCH 21 +#define CLK_MOUT_CMU_G3D_SWITCH 22 +#define CLK_MOUT_CMU_GNPU_NOC 23 +#define CLK_MOUT_CMU_UFS_MMC_CARD 24 +#define CLK_MOUT_CMU_M2M_NOC 25 +#define CLK_MOUT_CMU_NOCL0_NOC 26 +#define CLK_MOUT_CMU_NOCL1A_NOC 27 +#define CLK_MOUT_CMU_NOCL1B_NOC0 28 +#define CLK_MOUT_CMU_NOCL1C_NOC 29 +#define CLK_MOUT_CMU_SDMA_NOC 30 +#define CLK_MOUT_CMU_CP_HISPEEDY_CLK 31 +#define CLK_MOUT_CMU_CP_SHARED0_CLK 32 +#define CLK_MOUT_CMU_CP_SHARED2_CLK 33 +#define CLK_MOUT_CMU_MUX_ALIVE_NOC 34 +#define CLK_MOUT_CMU_MUX_AUD_AUDIF0 35 +#define CLK_MOUT_CMU_MUX_AUD_AUDIF1 36 +#define CLK_MOUT_CMU_MUX_AUD_CPU 37 +#define CLK_MOUT_CMU_MUX_AUD_NOC 38 +#define CLK_MOUT_CMU_MUX_BRP_NOC 39 +#define CLK_MOUT_CMU_MUX_CIS_CLK0 40 +#define CLK_MOUT_CMU_MUX_CIS_CLK1 41 +#define CLK_MOUT_CMU_MUX_CIS_CLK2 42 +#define CLK_MOUT_CMU_MUX_CIS_CLK3 43 +#define CLK_MOUT_CMU_MUX_CIS_CLK4 44 +#define CLK_MOUT_CMU_MUX_CIS_CLK5 45 +#define CLK_MOUT_CMU_MUX_CIS_CLK6 46 +#define CLK_MOUT_CMU_MUX_CIS_CLK7 47 +#define CLK_MOUT_CMU_MUX_CMU_BOOST 48 +#define CLK_MOUT_CMU_MUX_CMU_BOOST_CAM 49 +#define CLK_MOUT_CMU_MUX_CMU_BOOST_CPU 50 +#define CLK_MOUT_CMU_MUX_CMU_BOOST_MIF 51 +#define CLK_MOUT_CMU_MUX_CPUCL0_DBG_NOC 52 +#define CLK_MOUT_CMU_MUX_CPUCL0_NOCP 53 +#define CLK_MOUT_CMU_MUX_CPUCL0_SWITCH 54 +#define CLK_MOUT_CMU_MUX_CPUCL1_SWITCH 55 +#define CLK_MOUT_CMU_MUX_CPUCL2_SWITCH 56 +#define CLK_MOUT_CMU_MUX_CSIS_DCPHY 57 +#define CLK_MOUT_CMU_MUX_CSIS_NOC 58 +#define CLK_MOUT_CMU_MUX_CSIS_OIS_MCU 59 +#define CLK_MOUT_CMU_MUX_CSTAT_NOC 60 +#define CLK_MOUT_CMU_MUX_DNC_NOC 61 +#define CLK_MOUT_CMU_MUX_DPUB 62 +#define CLK_MOUT_CMU_MUX_DPUB_ALT 63 +#define CLK_MOUT_CMU_MUX_DPUB_DSIM 64 +#define CLK_MOUT_CMU_MUX_DPUF 65 +#define CLK_MOUT_CMU_MUX_DPUF_ALT 66 +#define CLK_MOUT_CMU_MUX_DSP_NOC 67 +#define CLK_MOUT_CMU_MUX_DSU_SWITCH 68 +#define CLK_MOUT_CMU_MUX_G3D_NOCP 69 +#define CLK_MOUT_CMU_MUX_G3D_SWITCH 70 +#define CLK_MOUT_CMU_MUX_GNPU_NOC 71 +#define CLK_MOUT_CMU_MUX_HSI0_DPGTC 72 +#define CLK_MOUT_CMU_MUX_HSI0_DPOSC 73 +#define CLK_MOUT_CMU_MUX_HSI0_NOC 74 +#define CLK_MOUT_CMU_MUX_HSI0_USB32DRD 75 +#define CLK_MOUT_CMU_MUX_UFS_MMC_CARD 76 +#define CLK_MOUT_CMU_MUX_HSI1_NOC 77 +#define CLK_MOUT_CMU_MUX_HSI1_PCIE 78 +#define CLK_MOUT_CMU_MUX_UFS_UFS_EMBD 79 +#define CLK_MOUT_CMU_MUX_LME_LME 80 +#define CLK_MOUT_CMU_MUX_LME_NOC 81 +#define CLK_MOUT_CMU_MUX_M2M_NOC 82 +#define CLK_MOUT_CMU_MUX_MCSC_MCSC 83 +#define CLK_MOUT_CMU_MUX_MCSC_NOC 84 +#define CLK_MOUT_CMU_MUX_MFC0_MFC0 85 +#define CLK_MOUT_CMU_MUX_MFC0_WFD 86 +#define CLK_MOUT_CMU_MUX_MFC1_MFC1 87 +#define CLK_MOUT_CMU_MUX_MIF_NOCP 88 +#define CLK_MOUT_CMU_MUX_MIF_SWITCH 89 +#define CLK_MOUT_CMU_MUX_NOCL0_NOC 90 +#define CLK_MOUT_CMU_MUX_NOCL1A_NOC 91 +#define CLK_MOUT_CMU_MUX_NOCL1B_NOC0 92 +#define CLK_MOUT_CMU_MUX_NOCL1B_NOC1 93 +#define CLK_MOUT_CMU_MUX_NOCL1C_NOC 94 +#define CLK_MOUT_CMU_MUX_PERIC0_IP0 95 +#define CLK_MOUT_CMU_MUX_PERIC0_IP1 96 +#define CLK_MOUT_CMU_MUX_PERIC0_NOC 97 +#define CLK_MOUT_CMU_MUX_PERIC1_IP0 98 +#define CLK_MOUT_CMU_MUX_PERIC1_IP1 99 +#define CLK_MOUT_CMU_MUX_PERIC1_NOC 100 +#define CLK_MOUT_CMU_MUX_PERIC2_IP0 101 +#define CLK_MOUT_CMU_MUX_PERIC2_IP1 102 +#define CLK_MOUT_CMU_MUX_PERIC2_NOC 103 +#define CLK_MOUT_CMU_MUX_PERIS_GIC 104 +#define CLK_MOUT_CMU_MUX_PERIS_NOC 105 +#define CLK_MOUT_CMU_MUX_SDMA_NOC 106 +#define CLK_MOUT_CMU_MUX_SSP_NOC 107 +#define CLK_MOUT_CMU_MUX_VTS_DMIC 108 +#define CLK_MOUT_CMU_MUX_YUVP_NOC 109 +#define CLK_MOUT_CMU_MUX_CMU_CMUREF 110 +#define CLK_MOUT_CMU_MUX_CP_HISPEEDY_CLK 111 +#define CLK_MOUT_CMU_MUX_CP_SHARED0_CLK 112 +#define CLK_MOUT_CMU_MUX_CP_SHARED1_CLK 113 +#define CLK_MOUT_CMU_MUX_CP_SHARED2_CLK 114 +#define CLK_MOUT_CMU_M2M_FRC 115 +#define CLK_MOUT_CMU_MCSC_MCSC 116 +#define CLK_MOUT_CMU_MCSC_NOC 117 +#define CLK_MOUT_CMU_MUX_M2M_FRC 118 +#define CLK_MOUT_CMU_MUX_UFS_NOC 119 + +#define CLK_DOUT_CMU_ALIVE_NOC 120 +#define CLK_DOUT_CMU_AUD_NOC 121 +#define CLK_DOUT_CMU_BRP_NOC 122 +#define CLK_DOUT_CMU_CMU_BOOST 123 +#define CLK_DOUT_CMU_CMU_BOOST_CAM 124 +#define CLK_DOUT_CMU_CMU_BOOST_CPU 125 +#define CLK_DOUT_CMU_CMU_BOOST_MIF 126 +#define CLK_DOUT_CMU_CPUCL0_NOCP 127 +#define CLK_DOUT_CMU_CSIS_DCPHY 128 +#define CLK_DOUT_CMU_CSIS_NOC 129 +#define CLK_DOUT_CMU_CSIS_OIS_MCU 130 +#define CLK_DOUT_CMU_CSTAT_NOC 131 +#define CLK_DOUT_CMU_DPUB_DSIM 132 +#define CLK_DOUT_CMU_LME_LME 133 +#define CLK_DOUT_CMU_G3D_NOCP 134 +#define CLK_DOUT_CMU_HSI0_DPGTC 135 +#define CLK_DOUT_CMU_HSI0_DPOSC 136 +#define CLK_DOUT_CMU_HSI0_NOC 137 +#define CLK_DOUT_CMU_HSI0_USB32DRD 138 +#define CLK_DOUT_CMU_HSI1_NOC 139 +#define CLK_DOUT_CMU_HSI1_PCIE 140 +#define CLK_DOUT_CMU_UFS_UFS_EMBD 141 +#define CLK_DOUT_CMU_LME_NOC 142 +#define CLK_DOUT_CMU_MFC0_MFC0 143 +#define CLK_DOUT_CMU_MFC0_WFD 144 +#define CLK_DOUT_CMU_MFC1_MFC1 145 +#define CLK_DOUT_CMU_MIF_NOCP 146 +#define CLK_DOUT_CMU_NOCL1B_NOC1 147 +#define CLK_DOUT_CMU_PERIC0_IP0 148 +#define CLK_DOUT_CMU_PERIC0_IP1 149 +#define CLK_DOUT_CMU_PERIC0_NOC 150 +#define CLK_DOUT_CMU_PERIC1_IP0 151 +#define CLK_DOUT_CMU_PERIC1_IP1 152 +#define CLK_DOUT_CMU_PERIC1_NOC 153 +#define CLK_DOUT_CMU_PERIC2_IP0 154 +#define CLK_DOUT_CMU_PERIC2_IP1 155 +#define CLK_DOUT_CMU_PERIC2_NOC 156 +#define CLK_DOUT_CMU_PERIS_GIC 157 +#define CLK_DOUT_CMU_PERIS_NOC 158 +#define CLK_DOUT_CMU_SSP_NOC 159 +#define CLK_DOUT_CMU_VTS_DMIC 160 +#define CLK_DOUT_CMU_YUVP_NOC 161 +#define CLK_DOUT_CMU_CP_SHARED1_CLK 162 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF0 163 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF0_SM 164 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF1 165 +#define CLK_DOUT_CMU_DIV_AUD_AUDIF1_SM 166 +#define CLK_DOUT_CMU_DIV_AUD_CPU 167 +#define CLK_DOUT_CMU_DIV_AUD_CPU_SM 168 +#define CLK_DOUT_CMU_DIV_CIS_CLK0 169 +#define CLK_DOUT_CMU_DIV_CIS_CLK1 170 +#define CLK_DOUT_CMU_DIV_CIS_CLK2 171 +#define CLK_DOUT_CMU_DIV_CIS_CLK3 172 +#define CLK_DOUT_CMU_DIV_CIS_CLK4 173 +#define CLK_DOUT_CMU_DIV_CIS_CLK5 174 +#define CLK_DOUT_CMU_DIV_CIS_CLK6 175 +#define CLK_DOUT_CMU_DIV_CIS_CLK7 176 +#define CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC 177 +#define CLK_DOUT_CMU_DIV_CPUCL0_DBG_NOC_SM 178 +#define CLK_DOUT_CMU_DIV_CPUCL0_SWITCH 179 +#define CLK_DOUT_CMU_DIV_CPUCL0_SWITCH_SM 180 +#define CLK_DOUT_CMU_DIV_CPUCL1_SWITCH 181 +#define CLK_DOUT_CMU_DIV_CPUCL1_SWITCH_SM 182 +#define CLK_DOUT_CMU_DIV_CPUCL2_SWITCH 183 +#define CLK_DOUT_CMU_DIV_CPUCL2_SWITCH_SM 184 +#define CLK_DOUT_CMU_DIV_DNC_NOC 185 +#define CLK_DOUT_CMU_DIV_DNC_NOC_SM 186 +#define CLK_DOUT_CMU_DIV_DPUB 187 +#define CLK_DOUT_CMU_DIV_DPUB_ALT 188 +#define CLK_DOUT_CMU_DIV_DPUF 189 +#define CLK_DOUT_CMU_DIV_DPUF_ALT 190 +#define CLK_DOUT_CMU_DIV_DSP_NOC 191 +#define CLK_DOUT_CMU_DIV_DSP_NOC_SM 192 +#define CLK_DOUT_CMU_DIV_DSU_SWITCH 193 +#define CLK_DOUT_CMU_DIV_DSU_SWITCH_SM 194 +#define CLK_DOUT_CMU_DIV_G3D_SWITCH 195 +#define CLK_DOUT_CMU_DIV_G3D_SWITCH_SM 196 +#define CLK_DOUT_CMU_DIV_GNPU_NOC 197 +#define CLK_DOUT_CMU_DIV_GNPU_NOC_SM 198 +#define CLK_DOUT_CMU_DIV_UFS_MMC_CARD 199 +#define CLK_DOUT_CMU_DIV_UFS_MMC_CARD_SM 200 +#define CLK_DOUT_CMU_DIV_M2M_NOC 201 +#define CLK_DOUT_CMU_DIV_M2M_NOC_SM 202 +#define CLK_DOUT_CMU_DIV_NOCL0_NOC 203 +#define CLK_DOUT_CMU_DIV_NOCL0_NOC_SM 204 +#define CLK_DOUT_CMU_DIV_NOCL1A_NOC 205 +#define CLK_DOUT_CMU_DIV_NOCL1A_NOC_SM 206 +#define CLK_DOUT_CMU_DIV_NOCL1B_NOC0 207 +#define CLK_DOUT_CMU_DIV_NOCL1B_NOC0_SM 208 +#define CLK_DOUT_CMU_DIV_NOCL1C_NOC 209 +#define CLK_DOUT_CMU_DIV_NOCL1C_NOC_SM 210 +#define CLK_DOUT_CMU_DIV_SDMA_NOC 211 +#define CLK_DOUT_CMU_DIV_SDMA_NOC_SM 212 +#define CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK 213 +#define CLK_DOUT_CMU_DIV_CP_HISPEEDY_CLK_SM 214 +#define CLK_DOUT_CMU_DIV_CP_SHARED0_CLK 215 +#define CLK_DOUT_CMU_DIV_CP_SHARED0_CLK_SM 216 +#define CLK_DOUT_CMU_DIV_CP_SHARED2_CLK 217 +#define CLK_DOUT_CMU_DIV_CP_SHARED2_CLK_SM 218 +#define CLK_DOUT_CMU_UFS_NOC 219 +#define CLK_DOUT_CMU_DIV_M2M_FRC 220 +#define CLK_DOUT_CMU_DIV_M2M_FRC_SM 221 +#define CLK_DOUT_CMU_DIV_MCSC_MCSC 222 +#define CLK_DOUT_CMU_DIV_MCSC_MCSC_SM 223 +#define CLK_DOUT_CMU_DIV_MCSC_NOC 224 +#define CLK_DOUT_CMU_DIV_MCSC_NOC_SM 225 +#define CLK_DOUT_SHARED0_DIV1 226 +#define CLK_DOUT_SHARED0_DIV2 227 +#define CLK_DOUT_SHARED0_DIV4 228 +#define CLK_DOUT_SHARED1_DIV1 229 +#define CLK_DOUT_SHARED1_DIV2 230 +#define CLK_DOUT_SHARED1_DIV4 231 +#define CLK_DOUT_SHARED2_DIV1 232 +#define CLK_DOUT_SHARED2_DIV2 233 +#define CLK_DOUT_SHARED2_DIV4 234 +#define CLK_DOUT_SHARED3_DIV1 235 +#define CLK_DOUT_SHARED3_DIV2 236 +#define CLK_DOUT_SHARED3_DIV4 237 +#define CLK_DOUT_SHARED4_DIV1 238 +#define CLK_DOUT_SHARED4_DIV2 239 +#define CLK_DOUT_SHARED4_DIV4 240 +#define CLK_DOUT_SHARED_MIF_DIV1 241 +#define CLK_DOUT_SHARED_MIF_DIV2 242 +#define CLK_DOUT_SHARED_MIF_DIV4 243 +#define CLK_DOUT_TCXO_DIV3 244 +#define CLK_DOUT_TCXO_DIV4 245 + +/* CMU_ALIVE */ +#define CLK_MOUT_ALIVE_NOC_USER 1 +#define CLK_MOUT_ALIVE_RCO_SPMI_USER 2 +#define CLK_MOUT_RCO_ALIVE_USER 3 +#define CLK_MOUT_ALIVE_CHUB_PERI 4 +#define CLK_MOUT_ALIVE_CMGP_NOC 5 +#define CLK_MOUT_ALIVE_CMGP_PERI 6 +#define CLK_MOUT_ALIVE_DBGCORE_NOC 7 +#define CLK_MOUT_ALIVE_DNC_NOC 8 +#define CLK_MOUT_ALIVE_CHUBVTS_NOC 9 +#define CLK_MOUT_ALIVE_GNPU_NOC 10 +#define CLK_MOUT_ALIVE_GNSS_NOC 11 +#define CLK_MOUT_ALIVE_SDMA_NOC 12 +#define CLK_MOUT_ALIVE_UFD_NOC 13 +#define CLK_MOUT_ALIVE_DBGCORE_UART 14 +#define CLK_MOUT_ALIVE_NOC 15 +#define CLK_MOUT_ALIVE_PMU_SUB 16 +#define CLK_MOUT_ALIVE_SPMI 17 +#define CLK_MOUT_ALIVE_TIMER 18 +#define CLK_MOUT_ALIVE_CSIS_NOC 19 +#define CLK_MOUT_ALIVE_DSP_NOC 20 + +#define CLK_DOUT_ALIVE_CHUB_PERI 21 +#define CLK_DOUT_ALIVE_CMGP_NOC 22 +#define CLK_DOUT_ALIVE_CMGP_PERI 23 +#define CLK_DOUT_ALIVE_DBGCORE_NOC 24 +#define CLK_DOUT_ALIVE_DNC_NOC 25 +#define CLK_DOUT_ALIVE_CHUBVTS_NOC 26 +#define CLK_DOUT_ALIVE_GNPU_NOC 27 +#define CLK_DOUT_ALIVE_SDMA_NOC 28 +#define CLK_DOUT_ALIVE_UFD_NOC 29 +#define CLK_DOUT_ALIVE_DBGCORE_UART 30 +#define CLK_DOUT_ALIVE_NOC 31 +#define CLK_DOUT_ALIVE_PMU_SUB 32 +#define CLK_DOUT_ALIVE_SPMI 33 +#define CLK_DOUT_ALIVE_CSIS_NOC 34 +#define CLK_DOUT_ALIVE_DSP_NOC 35 + +/* CMU_PERIS */ +#define CLK_MOUT_PERIS_GIC_USER 1 +#define CLK_MOUT_PERIS_NOC_USER 2 +#define CLK_MOUT_PERIS_GIC 3 + +#define CLK_DOUT_PERIS_OTP 4 +#define CLK_DOUT_PERIS_DDD_CTRL 5 + +/* CMU_CMGP */ +#define CLK_MOUT_CMGP_CLKALIVE_NOC_USER 1 +#define CLK_MOUT_CMGP_CLKALIVE_PERI_USER 2 +#define CLK_MOUT_CMGP_I2C 3 +#define CLK_MOUT_CMGP_SPI_I2C0 4 +#define CLK_MOUT_CMGP_SPI_I2C1 5 +#define CLK_MOUT_CMGP_SPI_MS_CTRL 6 +#define CLK_MOUT_CMGP_USI0 7 +#define CLK_MOUT_CMGP_USI1 8 +#define CLK_MOUT_CMGP_USI2 9 +#define CLK_MOUT_CMGP_USI3 10 +#define CLK_MOUT_CMGP_USI4 11 +#define CLK_MOUT_CMGP_USI5 12 +#define CLK_MOUT_CMGP_USI6 13 + +#define CLK_DOUT_CMGP_I2C 14 +#define CLK_DOUT_CMGP_SPI_I2C0 15 +#define CLK_DOUT_CMGP_SPI_I2C1 16 +#define CLK_DOUT_CMGP_SPI_MS_CTRL 17 +#define CLK_DOUT_CMGP_USI0 18 +#define CLK_DOUT_CMGP_USI1 19 +#define CLK_DOUT_CMGP_USI2 20 +#define CLK_DOUT_CMGP_USI3 21 +#define CLK_DOUT_CMGP_USI4 22 +#define CLK_DOUT_CMGP_USI5 23 +#define CLK_DOUT_CMGP_USI6 24 + +/* CMU_HSI0 */ +#define CLK_MOUT_CLKCMU_HSI0_DPGTC_USER 1 +#define CLK_MOUT_CLKCMU_HSI0_DPOSC_USER 2 +#define CLK_MOUT_CLKCMU_HSI0_NOC_USER 3 +#define CLK_MOUT_CLKCMU_HSI0_USB32DRD_USER 4 +#define CLK_MOUT_HSI0_NOC 5 +#define CLK_MOUT_HSI0_RTCCLK 6 +#define CLK_MOUT_HSI0_USB32DRD 7 + +#define CLK_DOUT_DIV_CLK_HSI0_EUSB 8 + +/* CMU_PERIC0 */ +#define CLK_MOUT_PERIC0_IP0_USER 1 +#define CLK_MOUT_PERIC0_IP1_USER 2 +#define CLK_MOUT_PERIC0_NOC_USER 3 +#define CLK_MOUT_PERIC0_I2C 4 +#define CLK_MOUT_PERIC0_USI04 5 + +#define CLK_DOUT_PERIC0_I2C 6 +#define CLK_DOUT_PERIC0_USI04 7 + +/* CMU_PERIC1 */ +#define CLK_MOUT_PERIC1_IP0_USER 1 +#define CLK_MOUT_PERIC1_IP1_USER 2 +#define CLK_MOUT_PERIC1_NOC_USER 3 +#define CLK_MOUT_PERIC1_I2C 4 +#define CLK_MOUT_PERIC1_SPI_MS_CTRL 5 +#define CLK_MOUT_PERIC1_UART_BT 6 +#define CLK_MOUT_PERIC1_USI07 7 +#define CLK_MOUT_PERIC1_USI07_SPI_I2C 8 +#define CLK_MOUT_PERIC1_USI08 9 +#define CLK_MOUT_PERIC1_USI08_SPI_I2C 10 +#define CLK_MOUT_PERIC1_USI09 11 +#define CLK_MOUT_PERIC1_USI10 12 + +#define CLK_DOUT_PERIC1_I2C 13 +#define CLK_DOUT_PERIC1_SPI_MS_CTRL 14 +#define CLK_DOUT_PERIC1_UART_BT 15 +#define CLK_DOUT_PERIC1_USI07 16 +#define CLK_DOUT_PERIC1_USI07_SPI_I2C 17 +#define CLK_DOUT_PERIC1_USI08 18 +#define CLK_DOUT_PERIC1_USI08_SPI_I2C 19 +#define CLK_DOUT_PERIC1_USI09 20 +#define CLK_DOUT_PERIC1_USI10 21 + +/* CMU_PERIC2 */ +#define CLK_MOUT_PERIC2_IP0_USER 1 +#define CLK_MOUT_PERIC2_IP1_USER 2 +#define CLK_MOUT_PERIC2_NOC_USER 3 +#define CLK_MOUT_PERIC2_I2C 4 +#define CLK_MOUT_PERIC2_SPI_MS_CTRL 5 +#define CLK_MOUT_PERIC2_UART_DBG 6 +#define CLK_MOUT_PERIC2_USI00 7 +#define CLK_MOUT_PERIC2_USI00_SPI_I2C 8 +#define CLK_MOUT_PERIC2_USI01 9 +#define CLK_MOUT_PERIC2_USI01_SPI_I2C 10 +#define CLK_MOUT_PERIC2_USI02 11 +#define CLK_MOUT_PERIC2_USI03 12 +#define CLK_MOUT_PERIC2_USI05 13 +#define CLK_MOUT_PERIC2_USI06 14 +#define CLK_MOUT_PERIC2_USI11 15 + +#define CLK_DOUT_PERIC2_I2C 16 +#define CLK_DOUT_PERIC2_SPI_MS_CTRL 17 +#define CLK_DOUT_PERIC2_UART_DBG 18 +#define CLK_DOUT_PERIC2_USI00 19 +#define CLK_DOUT_PERIC2_USI00_SPI_I2C 20 +#define CLK_DOUT_PERIC2_USI01 21 +#define CLK_DOUT_PERIC2_USI01_SPI_I2C 22 +#define CLK_DOUT_PERIC2_USI02 23 +#define CLK_DOUT_PERIC2_USI03 24 +#define CLK_DOUT_PERIC2_USI05 25 +#define CLK_DOUT_PERIC2_USI06 26 +#define CLK_DOUT_PERIC2_USI11 27 + +/* CMU_UFS */ +#define CLK_MOUT_UFS_MMC_CARD_USER 1 +#define CLK_MOUT_UFS_NOC_USER 2 +#define CLK_MOUT_UFS_UFS_EMBD_USER 3 + +/* CMU_VTS */ +#define CLK_MOUT_CLKALIVE_VTS_NOC_USER 1 +#define CLK_MOUT_CLKALIVE_VTS_RCO_USER 2 +#define CLK_MOUT_CLKCMU_VTS_DMIC_USER 3 +#define CLK_MOUT_CLKVTS_AUD_DMIC1 4 +#define CLK_MOUT_CLKVTS_NOC 5 +#define CLK_MOUT_CLKVTS_DMIC_PAD 6 + +#define CLK_DOUT_CLKVTS_AUD_DMIC0 7 +#define CLK_DOUT_CLKVTS_AUD_DMIC1 8 +#define CLK_DOUT_CLKVTS_CPU 9 +#define CLK_DOUT_CLKVTS_DMIC_IF 10 +#define CLK_DOUT_CLKVTS_DMIC_IF_DIV2 11 +#define CLK_DOUT_CLKVTS_NOC 12 +#define CLK_DOUT_CLKVTS_SERIAL_LIF 13 +#define CLK_DOUT_CLKVTS_SERIAL_LIF_CORE 14 + +#endif diff --git a/include/dt-bindings/clock/samsung,exynos7870-cmu.h b/include/dt-bindings/clock/samsung,exynos7870-cmu.h new file mode 100644 index 00000000000..57d04bbe342 --- /dev/null +++ b/include/dt-bindings/clock/samsung,exynos7870-cmu.h @@ -0,0 +1,324 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2015 Samsung Electronics Co., Ltd. + * Author: Kaustabh Chakraborty + * + * Device Tree binding constants for Exynos7870 clock controller. + */ + +#ifndef _DT_BINDINGS_CLOCK_EXYNOS7870_H +#define _DT_BINDINGS_CLOCK_EXYNOS7870_H + +/* CMU_MIF */ +#define CLK_DOUT_MIF_APB 1 +#define CLK_DOUT_MIF_BUSD 2 +#define CLK_DOUT_MIF_CMU_DISPAUD_BUS 3 +#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_ECLK 4 +#define CLK_DOUT_MIF_CMU_DISPAUD_DECON_VCLK 5 +#define CLK_DOUT_MIF_CMU_FSYS_BUS 6 +#define CLK_DOUT_MIF_CMU_FSYS_MMC0 7 +#define CLK_DOUT_MIF_CMU_FSYS_MMC1 8 +#define CLK_DOUT_MIF_CMU_FSYS_MMC2 9 +#define CLK_DOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 10 +#define CLK_DOUT_MIF_CMU_G3D_SWITCH 11 +#define CLK_DOUT_MIF_CMU_ISP_CAM 12 +#define CLK_DOUT_MIF_CMU_ISP_ISP 13 +#define CLK_DOUT_MIF_CMU_ISP_SENSOR0 14 +#define CLK_DOUT_MIF_CMU_ISP_SENSOR1 15 +#define CLK_DOUT_MIF_CMU_ISP_SENSOR2 16 +#define CLK_DOUT_MIF_CMU_ISP_VRA 17 +#define CLK_DOUT_MIF_CMU_MFCMSCL_MFC 18 +#define CLK_DOUT_MIF_CMU_MFCMSCL_MSCL 19 +#define CLK_DOUT_MIF_CMU_PERI_BUS 20 +#define CLK_DOUT_MIF_CMU_PERI_SPI0 21 +#define CLK_DOUT_MIF_CMU_PERI_SPI1 22 +#define CLK_DOUT_MIF_CMU_PERI_SPI2 23 +#define CLK_DOUT_MIF_CMU_PERI_SPI3 24 +#define CLK_DOUT_MIF_CMU_PERI_SPI4 25 +#define CLK_DOUT_MIF_CMU_PERI_UART0 26 +#define CLK_DOUT_MIF_CMU_PERI_UART1 27 +#define CLK_DOUT_MIF_CMU_PERI_UART2 28 +#define CLK_DOUT_MIF_HSI2C 29 +#define CLK_FOUT_MIF_BUS_PLL 30 +#define CLK_FOUT_MIF_MEDIA_PLL 31 +#define CLK_FOUT_MIF_MEM_PLL 32 +#define CLK_GOUT_MIF_CMU_DISPAUD_BUS 33 +#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_ECLK 34 +#define CLK_GOUT_MIF_CMU_DISPAUD_DECON_VCLK 35 +#define CLK_GOUT_MIF_CMU_FSYS_BUS 36 +#define CLK_GOUT_MIF_CMU_FSYS_MMC0 37 +#define CLK_GOUT_MIF_CMU_FSYS_MMC1 38 +#define CLK_GOUT_MIF_CMU_FSYS_MMC2 39 +#define CLK_GOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 40 +#define CLK_GOUT_MIF_CMU_G3D_SWITCH 41 +#define CLK_GOUT_MIF_CMU_ISP_CAM 42 +#define CLK_GOUT_MIF_CMU_ISP_ISP 43 +#define CLK_GOUT_MIF_CMU_ISP_SENSOR0 44 +#define CLK_GOUT_MIF_CMU_ISP_SENSOR1 45 +#define CLK_GOUT_MIF_CMU_ISP_SENSOR2 46 +#define CLK_GOUT_MIF_CMU_ISP_VRA 47 +#define CLK_GOUT_MIF_CMU_MFCMSCL_MFC 48 +#define CLK_GOUT_MIF_CMU_MFCMSCL_MSCL 49 +#define CLK_GOUT_MIF_CMU_PERI_BUS 50 +#define CLK_GOUT_MIF_CMU_PERI_SPI0 51 +#define CLK_GOUT_MIF_CMU_PERI_SPI1 52 +#define CLK_GOUT_MIF_CMU_PERI_SPI2 53 +#define CLK_GOUT_MIF_CMU_PERI_SPI3 54 +#define CLK_GOUT_MIF_CMU_PERI_SPI4 55 +#define CLK_GOUT_MIF_CMU_PERI_UART0 56 +#define CLK_GOUT_MIF_CMU_PERI_UART1 57 +#define CLK_GOUT_MIF_CMU_PERI_UART2 58 +#define CLK_GOUT_MIF_CP_PCLK_HSI2C 59 +#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_0 60 +#define CLK_GOUT_MIF_CP_PCLK_HSI2C_BAT_1 61 +#define CLK_GOUT_MIF_HSI2C_AP_PCLKM 62 +#define CLK_GOUT_MIF_HSI2C_AP_PCLKS 63 +#define CLK_GOUT_MIF_HSI2C_CP_PCLKM 64 +#define CLK_GOUT_MIF_HSI2C_CP_PCLKS 65 +#define CLK_GOUT_MIF_HSI2C_IPCLK 66 +#define CLK_GOUT_MIF_HSI2C_ITCLK 67 +#define CLK_GOUT_MIF_MUX_BUSD 68 +#define CLK_GOUT_MIF_MUX_BUS_PLL 69 +#define CLK_GOUT_MIF_MUX_BUS_PLL_CON 70 +#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_BUS 71 +#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_ECLK 72 +#define CLK_GOUT_MIF_MUX_CMU_DISPAUD_DECON_VCLK 73 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_BUS 74 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC0 75 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC1 76 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_MMC2 77 +#define CLK_GOUT_MIF_MUX_CMU_FSYS_USB20DRD_REFCLK 78 +#define CLK_GOUT_MIF_MUX_CMU_ISP_CAM 79 +#define CLK_GOUT_MIF_MUX_CMU_ISP_ISP 80 +#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR0 81 +#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR1 82 +#define CLK_GOUT_MIF_MUX_CMU_ISP_SENSOR2 83 +#define CLK_GOUT_MIF_MUX_CMU_ISP_VRA 84 +#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MFC 85 +#define CLK_GOUT_MIF_MUX_CMU_MFCMSCL_MSCL 86 +#define CLK_GOUT_MIF_MUX_CMU_PERI_BUS 87 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI0 88 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI1 89 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI2 90 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI3 91 +#define CLK_GOUT_MIF_MUX_CMU_PERI_SPI4 92 +#define CLK_GOUT_MIF_MUX_CMU_PERI_UART0 93 +#define CLK_GOUT_MIF_MUX_CMU_PERI_UART1 94 +#define CLK_GOUT_MIF_MUX_CMU_PERI_UART2 95 +#define CLK_GOUT_MIF_MUX_MEDIA_PLL 96 +#define CLK_GOUT_MIF_MUX_MEDIA_PLL_CON 97 +#define CLK_GOUT_MIF_MUX_MEM_PLL 98 +#define CLK_GOUT_MIF_MUX_MEM_PLL_CON 99 +#define CLK_GOUT_MIF_WRAP_ADC_IF_OSC_SYS 100 +#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S0 101 +#define CLK_GOUT_MIF_WRAP_ADC_IF_PCLK_S1 102 +#define CLK_MOUT_MIF_BUSD 103 +#define CLK_MOUT_MIF_CMU_DISPAUD_BUS 104 +#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_ECLK 105 +#define CLK_MOUT_MIF_CMU_DISPAUD_DECON_VCLK 106 +#define CLK_MOUT_MIF_CMU_FSYS_BUS 107 +#define CLK_MOUT_MIF_CMU_FSYS_MMC0 108 +#define CLK_MOUT_MIF_CMU_FSYS_MMC1 109 +#define CLK_MOUT_MIF_CMU_FSYS_MMC2 110 +#define CLK_MOUT_MIF_CMU_FSYS_USB20DRD_REFCLK 111 +#define CLK_MOUT_MIF_CMU_ISP_CAM 112 +#define CLK_MOUT_MIF_CMU_ISP_ISP 113 +#define CLK_MOUT_MIF_CMU_ISP_SENSOR0 114 +#define CLK_MOUT_MIF_CMU_ISP_SENSOR1 115 +#define CLK_MOUT_MIF_CMU_ISP_SENSOR2 116 +#define CLK_MOUT_MIF_CMU_ISP_VRA 117 +#define CLK_MOUT_MIF_CMU_MFCMSCL_MFC 118 +#define CLK_MOUT_MIF_CMU_MFCMSCL_MSCL 119 +#define CLK_MOUT_MIF_CMU_PERI_BUS 120 +#define CLK_MOUT_MIF_CMU_PERI_SPI0 121 +#define CLK_MOUT_MIF_CMU_PERI_SPI1 122 +#define CLK_MOUT_MIF_CMU_PERI_SPI2 123 +#define CLK_MOUT_MIF_CMU_PERI_SPI3 124 +#define CLK_MOUT_MIF_CMU_PERI_SPI4 125 +#define CLK_MOUT_MIF_CMU_PERI_UART0 126 +#define CLK_MOUT_MIF_CMU_PERI_UART1 127 +#define CLK_MOUT_MIF_CMU_PERI_UART2 128 +#define MIF_NR_CLK 129 + +/* CMU_DISPAUD */ +#define CLK_DOUT_DISPAUD_APB 1 +#define CLK_DOUT_DISPAUD_DECON_ECLK 2 +#define CLK_DOUT_DISPAUD_DECON_VCLK 3 +#define CLK_DOUT_DISPAUD_MI2S 4 +#define CLK_DOUT_DISPAUD_MIXER 5 +#define CLK_FOUT_DISPAUD_AUD_PLL 6 +#define CLK_FOUT_DISPAUD_PLL 7 +#define CLK_GOUT_DISPAUD_APB_AUD 8 +#define CLK_GOUT_DISPAUD_APB_AUD_AMP 9 +#define CLK_GOUT_DISPAUD_APB_DISP 10 +#define CLK_GOUT_DISPAUD_BUS 11 +#define CLK_GOUT_DISPAUD_BUS_DISP 12 +#define CLK_GOUT_DISPAUD_BUS_PPMU 13 +#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_BT_IN 14 +#define CLK_GOUT_DISPAUD_CON_AUD_I2S_BCLK_FM_IN 15 +#define CLK_GOUT_DISPAUD_CON_CP2AUD_BCK 16 +#define CLK_GOUT_DISPAUD_CON_EXT2AUD_BCK_GPIO_I2S 17 +#define CLK_GOUT_DISPAUD_DECON_ECLK 18 +#define CLK_GOUT_DISPAUD_DECON_VCLK 19 +#define CLK_GOUT_DISPAUD_MI2S_AMP_I2SCODCLKI 20 +#define CLK_GOUT_DISPAUD_MI2S_AUD_I2SCODCLKI 21 +#define CLK_GOUT_DISPAUD_MIXER_AUD_SYSCLK 22 +#define CLK_GOUT_DISPAUD_MUX_AUD_PLL 23 +#define CLK_GOUT_DISPAUD_MUX_AUD_PLL_CON 24 +#define CLK_GOUT_DISPAUD_MUX_BUS_USER 25 +#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK 26 +#define CLK_GOUT_DISPAUD_MUX_DECON_ECLK_USER 27 +#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK 28 +#define CLK_GOUT_DISPAUD_MUX_DECON_VCLK_USER 29 +#define CLK_GOUT_DISPAUD_MUX_MI2S 30 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER 31 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_RXCLKESC0_USER_CON 32 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER 33 +#define CLK_GOUT_DISPAUD_MUX_MIPIPHY_TXBYTECLKHS_USER_CON 34 +#define CLK_GOUT_DISPAUD_MUX_PLL 35 +#define CLK_GOUT_DISPAUD_MUX_PLL_CON 36 +#define CLK_MOUT_DISPAUD_BUS_USER 37 +#define CLK_MOUT_DISPAUD_DECON_ECLK 38 +#define CLK_MOUT_DISPAUD_DECON_ECLK_USER 39 +#define CLK_MOUT_DISPAUD_DECON_VCLK 40 +#define CLK_MOUT_DISPAUD_DECON_VCLK_USER 41 +#define CLK_MOUT_DISPAUD_MI2S 42 +#define DISPAUD_NR_CLK 43 + +/* CMU_FSYS */ +#define CLK_FOUT_FSYS_USB_PLL 1 +#define CLK_GOUT_FSYS_BUSP3_HCLK 2 +#define CLK_GOUT_FSYS_MMC0_ACLK 3 +#define CLK_GOUT_FSYS_MMC1_ACLK 4 +#define CLK_GOUT_FSYS_MMC2_ACLK 5 +#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER 6 +#define CLK_GOUT_FSYS_MUX_USB20DRD_PHYCLOCK_USER_CON 7 +#define CLK_GOUT_FSYS_MUX_USB_PLL 8 +#define CLK_GOUT_FSYS_MUX_USB_PLL_CON 9 +#define CLK_GOUT_FSYS_PDMA0_ACLK_PDMA0 10 +#define CLK_GOUT_FSYS_PPMU_ACLK 11 +#define CLK_GOUT_FSYS_PPMU_PCLK 12 +#define CLK_GOUT_FSYS_SROMC_HCLK 13 +#define CLK_GOUT_FSYS_UPSIZER_BUS1_ACLK 14 +#define CLK_GOUT_FSYS_USB20DRD_ACLK_HSDRD 15 +#define CLK_GOUT_FSYS_USB20DRD_HCLK_USB20_CTRL 16 +#define CLK_GOUT_FSYS_USB20DRD_HSDRD_REF_CLK 17 +#define FSYS_NR_CLK 18 + +/* CMU_G3D */ +#define CLK_DOUT_G3D_APB 1 +#define CLK_DOUT_G3D_BUS 2 +#define CLK_FOUT_G3D_PLL 3 +#define CLK_GOUT_G3D_ASYNCS_D0_CLK 4 +#define CLK_GOUT_G3D_ASYNC_PCLKM 5 +#define CLK_GOUT_G3D_CLK 6 +#define CLK_GOUT_G3D_MUX 7 +#define CLK_GOUT_G3D_MUX_PLL 8 +#define CLK_GOUT_G3D_MUX_PLL_CON 9 +#define CLK_GOUT_G3D_MUX_SWITCH_USER 10 +#define CLK_GOUT_G3D_PPMU_ACLK 11 +#define CLK_GOUT_G3D_PPMU_PCLK 12 +#define CLK_GOUT_G3D_QE_ACLK 13 +#define CLK_GOUT_G3D_QE_PCLK 14 +#define CLK_GOUT_G3D_SYSREG_PCLK 15 +#define CLK_MOUT_G3D 16 +#define CLK_MOUT_G3D_SWITCH_USER 17 +#define G3D_NR_CLK 18 + +/* CMU_ISP */ +#define CLK_DOUT_ISP_APB 1 +#define CLK_DOUT_ISP_CAM_HALF 2 +#define CLK_FOUT_ISP_PLL 3 +#define CLK_GOUT_ISP_CAM 4 +#define CLK_GOUT_ISP_CAM_HALF 5 +#define CLK_GOUT_ISP_ISPD 6 +#define CLK_GOUT_ISP_ISPD_PPMU 7 +#define CLK_GOUT_ISP_MUX_CAM 8 +#define CLK_GOUT_ISP_MUX_CAM_USER 9 +#define CLK_GOUT_ISP_MUX_ISP 10 +#define CLK_GOUT_ISP_MUX_ISPD 11 +#define CLK_GOUT_ISP_MUX_PLL 12 +#define CLK_GOUT_ISP_MUX_PLL_CON 13 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER 14 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR0_USER_CON 15 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER 16 +#define CLK_GOUT_ISP_MUX_RXBYTECLKHS0_SENSOR1_USER_CON 17 +#define CLK_GOUT_ISP_MUX_USER 18 +#define CLK_GOUT_ISP_MUX_VRA 19 +#define CLK_GOUT_ISP_MUX_VRA_USER 20 +#define CLK_GOUT_ISP_VRA 21 +#define CLK_MOUT_ISP_CAM 22 +#define CLK_MOUT_ISP_CAM_USER 23 +#define CLK_MOUT_ISP_ISP 24 +#define CLK_MOUT_ISP_ISPD 25 +#define CLK_MOUT_ISP_USER 26 +#define CLK_MOUT_ISP_VRA 27 +#define CLK_MOUT_ISP_VRA_USER 28 +#define ISP_NR_CLK 29 + +/* CMU_MFCMSCL */ +#define CLK_DOUT_MFCMSCL_APB 1 +#define CLK_GOUT_MFCMSCL_MFC 2 +#define CLK_GOUT_MFCMSCL_MSCL 3 +#define CLK_GOUT_MFCMSCL_MSCL_BI 4 +#define CLK_GOUT_MFCMSCL_MSCL_D 5 +#define CLK_GOUT_MFCMSCL_MSCL_JPEG 6 +#define CLK_GOUT_MFCMSCL_MSCL_POLY 7 +#define CLK_GOUT_MFCMSCL_MSCL_PPMU 8 +#define CLK_GOUT_MFCMSCL_MUX_MFC_USER 9 +#define CLK_GOUT_MFCMSCL_MUX_MSCL_USER 10 +#define CLK_MOUT_MFCMSCL_MFC_USER 11 +#define CLK_MOUT_MFCMSCL_MSCL_USER 12 +#define MFCMSCL_NR_CLK 13 + +/* CMU_PERI */ +#define CLK_GOUT_PERI_BUSP1_PERIC0_HCLK 1 +#define CLK_GOUT_PERI_GPIO2_PCLK 2 +#define CLK_GOUT_PERI_GPIO5_PCLK 3 +#define CLK_GOUT_PERI_GPIO6_PCLK 4 +#define CLK_GOUT_PERI_GPIO7_PCLK 5 +#define CLK_GOUT_PERI_HSI2C1_IPCLK 6 +#define CLK_GOUT_PERI_HSI2C2_IPCLK 7 +#define CLK_GOUT_PERI_HSI2C3_IPCLK 8 +#define CLK_GOUT_PERI_HSI2C4_IPCLK 9 +#define CLK_GOUT_PERI_HSI2C5_IPCLK 10 +#define CLK_GOUT_PERI_HSI2C6_IPCLK 11 +#define CLK_GOUT_PERI_I2C0_PCLK 12 +#define CLK_GOUT_PERI_I2C1_PCLK 13 +#define CLK_GOUT_PERI_I2C2_PCLK 14 +#define CLK_GOUT_PERI_I2C3_PCLK 15 +#define CLK_GOUT_PERI_I2C4_PCLK 16 +#define CLK_GOUT_PERI_I2C5_PCLK 17 +#define CLK_GOUT_PERI_I2C6_PCLK 18 +#define CLK_GOUT_PERI_I2C7_PCLK 19 +#define CLK_GOUT_PERI_I2C8_PCLK 20 +#define CLK_GOUT_PERI_MCT_PCLK 21 +#define CLK_GOUT_PERI_PWM_MOTOR_OSCCLK 22 +#define CLK_GOUT_PERI_PWM_MOTOR_PCLK_S0 23 +#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL0_PCLK 24 +#define CLK_GOUT_PERI_SFRIF_TMU_CPUCL1_PCLK 25 +#define CLK_GOUT_PERI_SFRIF_TMU_PCLK 26 +#define CLK_GOUT_PERI_SPI0_PCLK 27 +#define CLK_GOUT_PERI_SPI0_SPI_EXT_CLK 28 +#define CLK_GOUT_PERI_SPI1_PCLK 29 +#define CLK_GOUT_PERI_SPI1_SPI_EXT_CLK 30 +#define CLK_GOUT_PERI_SPI2_PCLK 31 +#define CLK_GOUT_PERI_SPI2_SPI_EXT_CLK 32 +#define CLK_GOUT_PERI_SPI3_PCLK 33 +#define CLK_GOUT_PERI_SPI3_SPI_EXT_CLK 34 +#define CLK_GOUT_PERI_SPI4_PCLK 35 +#define CLK_GOUT_PERI_SPI4_SPI_EXT_CLK 36 +#define CLK_GOUT_PERI_TMU_CLK 37 +#define CLK_GOUT_PERI_TMU_CPUCL0_CLK 38 +#define CLK_GOUT_PERI_TMU_CPUCL1_CLK 39 +#define CLK_GOUT_PERI_UART0_EXT_UCLK 40 +#define CLK_GOUT_PERI_UART0_PCLK 41 +#define CLK_GOUT_PERI_UART1_EXT_UCLK 42 +#define CLK_GOUT_PERI_UART1_PCLK 43 +#define CLK_GOUT_PERI_UART2_EXT_UCLK 44 +#define CLK_GOUT_PERI_UART2_PCLK 45 +#define CLK_GOUT_PERI_WDT_CPUCL0_PCLK 46 +#define CLK_GOUT_PERI_WDT_CPUCL1_PCLK 47 +#define PERI_NR_CLK 48 + +#endif /* _DT_BINDINGS_CLOCK_EXYNOS7870_H */ diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bindings/clock/samsung,exynos990.h index 307215a3f3e..6b9df09d282 100644 --- a/include/dt-bindings/clock/samsung,exynos990.h +++ b/include/dt-bindings/clock/samsung,exynos990.h @@ -233,4 +233,25 @@ #define CLK_GOUT_HSI0_CMU_HSI0_PCLK 21 #define CLK_GOUT_HSI0_XIU_D_HSI0_ACLK 22 +/* CMU_PERIS */ +#define CLK_MOUT_PERIS_BUS_USER 1 +#define CLK_MOUT_PERIS_CLK_PERIS_GIC 2 +#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 3 +#define CLK_GOUT_PERIS_WDT_CLUSTER2_PCLK 4 +#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 5 +#define CLK_CLK_PERIS_PERIS_CMU_PERIS_PCLK 6 +#define CLK_GOUT_PERIS_CLK_PERIS_BUSP_CLK 7 +#define CLK_GOUT_PERIS_CLK_PERIS_OSCCLK_CLK 8 +#define CLK_GOUT_PERIS_CLK_PERIS_GIC_CLK 9 +#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 10 +#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 11 +#define CLK_GOUT_PERIS_GIC_CLK 12 +#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_CLK 13 +#define CLK_GOUT_PERIS_MCT_PCLK 14 +#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 15 +#define CLK_GOUT_PERIS_D_TZPC_PERIS_PCLK 16 +#define CLK_GOUT_PERIS_TMU_TOP_PCLK 17 +#define CLK_GOUT_PERIS_OTP_CON_BIRA_OSCCLK 18 +#define CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK 19 + #endif diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h index ebb146ab7f8..6889405f9fe 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -113,5 +113,9 @@ #define CLK_BUS_HDCP 127 #define CLK_PLL_SYSTEM_32K 128 #define CLK_BUS_GPADC 129 +#define CLK_TCON_LCD0 130 +#define CLK_BUS_TCON_LCD0 131 +#define CLK_TCON_LCD1 132 +#define CLK_BUS_TCON_LCD1 133 #endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/clock/sun55i-a523-ccu.h b/include/dt-bindings/clock/sun55i-a523-ccu.h new file mode 100644 index 00000000000..c8259ac5ada --- /dev/null +++ b/include/dt-bindings/clock/sun55i-a523-ccu.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ +#define _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ + +#define CLK_PLL_DDR0 0 +#define CLK_PLL_PERIPH0_4X 1 +#define CLK_PLL_PERIPH0_2X 2 +#define CLK_PLL_PERIPH0_800M 3 +#define CLK_PLL_PERIPH0_480M 4 +#define CLK_PLL_PERIPH0_600M 5 +#define CLK_PLL_PERIPH0_400M 6 +#define CLK_PLL_PERIPH0_300M 7 +#define CLK_PLL_PERIPH0_200M 8 +#define CLK_PLL_PERIPH0_160M 9 +#define CLK_PLL_PERIPH0_150M 10 +#define CLK_PLL_PERIPH1_4X 11 +#define CLK_PLL_PERIPH1_2X 12 +#define CLK_PLL_PERIPH1_800M 13 +#define CLK_PLL_PERIPH1_480M 14 +#define CLK_PLL_PERIPH1_600M 15 +#define CLK_PLL_PERIPH1_400M 16 +#define CLK_PLL_PERIPH1_300M 17 +#define CLK_PLL_PERIPH1_200M 18 +#define CLK_PLL_PERIPH1_160M 19 +#define CLK_PLL_PERIPH1_150M 20 +#define CLK_PLL_GPU 21 +#define CLK_PLL_VIDEO0_8X 22 +#define CLK_PLL_VIDEO0_4X 23 +#define CLK_PLL_VIDEO0_3X 24 +#define CLK_PLL_VIDEO1_8X 25 +#define CLK_PLL_VIDEO1_4X 26 +#define CLK_PLL_VIDEO1_3X 27 +#define CLK_PLL_VIDEO2_8X 28 +#define CLK_PLL_VIDEO2_4X 29 +#define CLK_PLL_VIDEO2_3X 30 +#define CLK_PLL_VIDEO3_8X 31 +#define CLK_PLL_VIDEO3_4X 32 +#define CLK_PLL_VIDEO3_3X 33 +#define CLK_PLL_VE 34 +#define CLK_PLL_AUDIO0_4X 35 +#define CLK_PLL_AUDIO0_2X 36 +#define CLK_PLL_AUDIO0 37 +#define CLK_PLL_NPU_4X 38 +#define CLK_PLL_NPU_2X 39 +#define CLK_PLL_NPU 40 +#define CLK_AHB 41 +#define CLK_APB0 42 +#define CLK_APB1 43 +#define CLK_MBUS 44 +#define CLK_DE 45 +#define CLK_BUS_DE 46 +#define CLK_DI 47 +#define CLK_BUS_DI 48 +#define CLK_G2D 49 +#define CLK_BUS_G2D 50 +#define CLK_GPU 51 +#define CLK_BUS_GPU 52 +#define CLK_CE 53 +#define CLK_BUS_CE 54 +#define CLK_BUS_CE_SYS 55 +#define CLK_VE 56 +#define CLK_BUS_VE 57 +#define CLK_BUS_DMA 58 +#define CLK_BUS_MSGBOX 59 +#define CLK_BUS_SPINLOCK 60 +#define CLK_HSTIMER0 61 +#define CLK_HSTIMER1 62 +#define CLK_HSTIMER2 63 +#define CLK_HSTIMER3 64 +#define CLK_HSTIMER4 65 +#define CLK_HSTIMER5 66 +#define CLK_BUS_HSTIMER 67 +#define CLK_BUS_DBG 68 +#define CLK_BUS_PWM0 69 +#define CLK_BUS_PWM1 70 +#define CLK_IOMMU 71 +#define CLK_BUS_IOMMU 72 +#define CLK_DRAM 73 +#define CLK_MBUS_DMA 74 +#define CLK_MBUS_VE 75 +#define CLK_MBUS_CE 76 +#define CLK_MBUS_CSI 77 +#define CLK_MBUS_ISP 78 +#define CLK_MBUS_EMAC1 79 +#define CLK_BUS_DRAM 80 +#define CLK_NAND0 81 +#define CLK_NAND1 82 +#define CLK_BUS_NAND 83 +#define CLK_MMC0 84 +#define CLK_MMC1 85 +#define CLK_MMC2 86 +#define CLK_BUS_SYSDAP 87 +#define CLK_BUS_MMC0 88 +#define CLK_BUS_MMC1 89 +#define CLK_BUS_MMC2 90 +#define CLK_BUS_UART0 91 +#define CLK_BUS_UART1 92 +#define CLK_BUS_UART2 93 +#define CLK_BUS_UART3 94 +#define CLK_BUS_UART4 95 +#define CLK_BUS_UART5 96 +#define CLK_BUS_UART6 97 +#define CLK_BUS_UART7 98 +#define CLK_BUS_I2C0 99 +#define CLK_BUS_I2C1 100 +#define CLK_BUS_I2C2 101 +#define CLK_BUS_I2C3 102 +#define CLK_BUS_I2C4 103 +#define CLK_BUS_I2C5 104 +#define CLK_BUS_CAN 105 +#define CLK_SPI0 106 +#define CLK_SPI1 107 +#define CLK_SPI2 108 +#define CLK_SPIFC 109 +#define CLK_BUS_SPI0 110 +#define CLK_BUS_SPI1 111 +#define CLK_BUS_SPI2 112 +#define CLK_BUS_SPIFC 113 +#define CLK_EMAC0_25M 114 +#define CLK_EMAC1_25M 115 +#define CLK_BUS_EMAC0 116 +#define CLK_BUS_EMAC1 117 +#define CLK_IR_RX 118 +#define CLK_BUS_IR_RX 119 +#define CLK_IR_TX 120 +#define CLK_BUS_IR_TX 121 +#define CLK_GPADC0 122 +#define CLK_GPADC1 123 +#define CLK_BUS_GPADC0 124 +#define CLK_BUS_GPADC1 125 +#define CLK_BUS_THS 126 +#define CLK_USB_OHCI0 127 +#define CLK_USB_OHCI1 128 +#define CLK_BUS_OHCI0 129 +#define CLK_BUS_OHCI1 130 +#define CLK_BUS_EHCI0 131 +#define CLK_BUS_EHCI1 132 +#define CLK_BUS_OTG 133 +#define CLK_BUS_LRADC 134 +#define CLK_PCIE_AUX 135 +#define CLK_BUS_DISPLAY0_TOP 136 +#define CLK_BUS_DISPLAY1_TOP 137 +#define CLK_HDMI_24M 138 +#define CLK_HDMI_CEC_32K 139 +#define CLK_HDMI_CEC 140 +#define CLK_BUS_HDMI 141 +#define CLK_MIPI_DSI0 142 +#define CLK_MIPI_DSI1 143 +#define CLK_BUS_MIPI_DSI0 144 +#define CLK_BUS_MIPI_DSI1 145 +#define CLK_TCON_LCD0 146 +#define CLK_TCON_LCD1 147 +#define CLK_TCON_LCD2 148 +#define CLK_COMBOPHY_DSI0 149 +#define CLK_COMBOPHY_DSI1 150 +#define CLK_BUS_TCON_LCD0 151 +#define CLK_BUS_TCON_LCD1 152 +#define CLK_BUS_TCON_LCD2 153 +#define CLK_TCON_TV0 154 +#define CLK_TCON_TV1 155 +#define CLK_BUS_TCON_TV0 156 +#define CLK_BUS_TCON_TV1 157 +#define CLK_EDP 158 +#define CLK_BUS_EDP 159 +#define CLK_LEDC 160 +#define CLK_BUS_LEDC 161 +#define CLK_CSI_TOP 162 +#define CLK_CSI_MCLK0 163 +#define CLK_CSI_MCLK1 164 +#define CLK_CSI_MCLK2 165 +#define CLK_CSI_MCLK3 166 +#define CLK_BUS_CSI 167 +#define CLK_ISP 168 +#define CLK_DSP 169 +#define CLK_FANOUT_24M 170 +#define CLK_FANOUT_12M 171 +#define CLK_FANOUT_16M 172 +#define CLK_FANOUT_25M 173 +#define CLK_FANOUT_27M 174 +#define CLK_FANOUT_PCLK 175 +#define CLK_FANOUT0 176 +#define CLK_FANOUT1 177 +#define CLK_FANOUT2 178 + +#endif /* _DT_BINDINGS_CLK_SUN55I_A523_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun55i-a523-r-ccu.h b/include/dt-bindings/clock/sun55i-a523-r-ccu.h new file mode 100644 index 00000000000..365647499b9 --- /dev/null +++ b/include/dt-bindings/clock/sun55i-a523-r-ccu.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_ + +#define CLK_R_AHB 0 +#define CLK_R_APB0 1 +#define CLK_R_APB1 2 +#define CLK_R_TIMER0 3 +#define CLK_R_TIMER1 4 +#define CLK_R_TIMER2 5 +#define CLK_BUS_R_TIMER 6 +#define CLK_BUS_R_TWD 7 +#define CLK_R_PWMCTRL 8 +#define CLK_BUS_R_PWMCTRL 9 +#define CLK_R_SPI 10 +#define CLK_BUS_R_SPI 11 +#define CLK_BUS_R_SPINLOCK 12 +#define CLK_BUS_R_MSGBOX 13 +#define CLK_BUS_R_UART0 14 +#define CLK_BUS_R_UART1 15 +#define CLK_BUS_R_I2C0 16 +#define CLK_BUS_R_I2C1 17 +#define CLK_BUS_R_I2C2 18 +#define CLK_BUS_R_PPU0 19 +#define CLK_BUS_R_PPU1 20 +#define CLK_BUS_R_CPU_BIST 21 +#define CLK_R_IR_RX 22 +#define CLK_BUS_R_IR_RX 23 +#define CLK_BUS_R_DMA 24 +#define CLK_BUS_R_RTC 25 +#define CLK_BUS_R_CPUCFG 26 + +#endif /* _DT_BINDINGS_CLK_SUN55I_A523_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/xlnx-zynqmp-clk.h b/include/dt-bindings/clock/xlnx-zynqmp-clk.h index cdc4c0b9a37..f0f7ddd3dcb 100644 --- a/include/dt-bindings/clock/xlnx-zynqmp-clk.h +++ b/include/dt-bindings/clock/xlnx-zynqmp-clk.h @@ -9,6 +9,13 @@ #ifndef _DT_BINDINGS_CLK_ZYNQMP_H #define _DT_BINDINGS_CLK_ZYNQMP_H +/* + * These bindings are deprecated, because they do not match the actual + * concept of bindings but rather contain pure firmware values. + * Instead include the header in the DTS source directory. + */ +#warning "These bindings are deprecated. Instead use the header in the DTS source directory." + #define IOPLL 0 #define RPLL 1 #define APLL 2 diff --git a/include/dt-bindings/iio/adc/adi,ad4695.h b/include/dt-bindings/iio/adc/adi,ad4695.h index 9fbef542bf6..fea4525d271 100644 --- a/include/dt-bindings/iio/adc/adi,ad4695.h +++ b/include/dt-bindings/iio/adc/adi,ad4695.h @@ -6,4 +6,11 @@ #define AD4695_COMMON_MODE_REFGND 0xFF #define AD4695_COMMON_MODE_COM 0xFE +#define AD4695_TRIGGER_EVENT_BUSY 0 +#define AD4695_TRIGGER_EVENT_ALERT 1 + +#define AD4695_TRIGGER_PIN_GP0 0 +#define AD4695_TRIGGER_PIN_GP2 2 +#define AD4695_TRIGGER_PIN_GP3 3 + #endif /* _DT_BINDINGS_ADI_AD4695_H */ diff --git a/include/dt-bindings/pinctrl/amlogic,pinctrl.h b/include/dt-bindings/pinctrl/amlogic,pinctrl.h new file mode 100644 index 00000000000..7d40aecc714 --- /dev/null +++ b/include/dt-bindings/pinctrl/amlogic,pinctrl.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Amlogic, Inc. All rights reserved. + * Author: Xianwei Zhao + */ + +#ifndef _DT_BINDINGS_AMLOGIC_PINCTRL_H +#define _DT_BINDINGS_AMLOGIC_PINCTRL_H +/* Normal PIN bank */ +#define AMLOGIC_GPIO_A 0 +#define AMLOGIC_GPIO_B 1 +#define AMLOGIC_GPIO_C 2 +#define AMLOGIC_GPIO_D 3 +#define AMLOGIC_GPIO_E 4 +#define AMLOGIC_GPIO_F 5 +#define AMLOGIC_GPIO_G 6 +#define AMLOGIC_GPIO_H 7 +#define AMLOGIC_GPIO_I 8 +#define AMLOGIC_GPIO_J 9 +#define AMLOGIC_GPIO_K 10 +#define AMLOGIC_GPIO_L 11 +#define AMLOGIC_GPIO_M 12 +#define AMLOGIC_GPIO_N 13 +#define AMLOGIC_GPIO_O 14 +#define AMLOGIC_GPIO_P 15 +#define AMLOGIC_GPIO_Q 16 +#define AMLOGIC_GPIO_R 17 +#define AMLOGIC_GPIO_S 18 +#define AMLOGIC_GPIO_T 19 +#define AMLOGIC_GPIO_U 20 +#define AMLOGIC_GPIO_V 21 +#define AMLOGIC_GPIO_W 22 +#define AMLOGIC_GPIO_X 23 +#define AMLOGIC_GPIO_Y 24 +#define AMLOGIC_GPIO_Z 25 + +/* Special PIN bank */ +#define AMLOGIC_GPIO_DV 26 +#define AMLOGIC_GPIO_AO 27 +#define AMLOGIC_GPIO_CC 28 +#define AMLOGIC_GPIO_TEST_N 29 +#define AMLOGIC_GPIO_ANALOG 30 + +#define AML_PINMUX(bank, offset, mode) (((((bank) << 8) + (offset)) << 8) | (mode)) + +#endif /* _DT_BINDINGS_AMLOGIC_PINCTRL_H */ diff --git a/include/dt-bindings/pinctrl/pinctrl-sg2042.h b/include/dt-bindings/pinctrl/pinctrl-sg2042.h new file mode 100644 index 00000000000..79d5bb8e04f --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-sg2042.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2024 Inochi Amaoto + * + */ + +#ifndef _DT_BINDINGS_PINCTRL_SG2042_H +#define _DT_BINDINGS_PINCTRL_SG2042_H + +#define PINMUX(pin, mux) \ + (((pin) & 0xffff) | (((mux) & 0xff) << 16)) + +#define PIN_LPC_LCLK 0 +#define PIN_LPC_LFRAME 1 +#define PIN_LPC_LAD0 2 +#define PIN_LPC_LAD1 3 +#define PIN_LPC_LAD2 4 +#define PIN_LPC_LAD3 5 +#define PIN_LPC_LDRQ0 6 +#define PIN_LPC_LDRQ1 7 +#define PIN_LPC_SERIRQ 8 +#define PIN_LPC_CLKRUN 9 +#define PIN_LPC_LPME 10 +#define PIN_LPC_LPCPD 11 +#define PIN_LPC_LSMI 12 +#define PIN_PCIE0_L0_RESET 13 +#define PIN_PCIE0_L1_RESET 14 +#define PIN_PCIE0_L0_WAKEUP 15 +#define PIN_PCIE0_L1_WAKEUP 16 +#define PIN_PCIE0_L0_CLKREQ_IN 17 +#define PIN_PCIE0_L1_CLKREQ_IN 18 +#define PIN_PCIE1_L0_RESET 19 +#define PIN_PCIE1_L1_RESET 20 +#define PIN_PCIE1_L0_WAKEUP 21 +#define PIN_PCIE1_L1_WAKEUP 22 +#define PIN_PCIE1_L0_CLKREQ_IN 23 +#define PIN_PCIE1_L1_CLKREQ_IN 24 +#define PIN_SPIF0_CLK_SEL1 25 +#define PIN_SPIF0_CLK_SEL0 26 +#define PIN_SPIF0_WP 27 +#define PIN_SPIF0_HOLD 28 +#define PIN_SPIF0_SDI 29 +#define PIN_SPIF0_CS 30 +#define PIN_SPIF0_SCK 31 +#define PIN_SPIF0_SDO 32 +#define PIN_SPIF1_CLK_SEL1 33 +#define PIN_SPIF1_CLK_SEL0 34 +#define PIN_SPIF1_WP 35 +#define PIN_SPIF1_HOLD 36 +#define PIN_SPIF1_SDI 37 +#define PIN_SPIF1_CS 38 +#define PIN_SPIF1_SCK 39 +#define PIN_SPIF1_SDO 40 +#define PIN_EMMC_WP 41 +#define PIN_EMMC_CD 42 +#define PIN_EMMC_RST 43 +#define PIN_EMMC_PWR_EN 44 +#define PIN_SDIO_CD 45 +#define PIN_SDIO_WP 46 +#define PIN_SDIO_RST 47 +#define PIN_SDIO_PWR_EN 48 +#define PIN_RGMII0_TXD0 49 +#define PIN_RGMII0_TXD1 50 +#define PIN_RGMII0_TXD2 51 +#define PIN_RGMII0_TXD3 52 +#define PIN_RGMII0_TXCTRL 53 +#define PIN_RGMII0_RXD0 54 +#define PIN_RGMII0_RXD1 55 +#define PIN_RGMII0_RXD2 56 +#define PIN_RGMII0_RXD3 57 +#define PIN_RGMII0_RXCTRL 58 +#define PIN_RGMII0_TXC 59 +#define PIN_RGMII0_RXC 60 +#define PIN_RGMII0_REFCLKO 61 +#define PIN_RGMII0_IRQ 62 +#define PIN_RGMII0_MDC 63 +#define PIN_RGMII0_MDIO 64 +#define PIN_PWM0 65 +#define PIN_PWM1 66 +#define PIN_PWM2 67 +#define PIN_PWM3 68 +#define PIN_FAN0 69 +#define PIN_FAN1 70 +#define PIN_FAN2 71 +#define PIN_FAN3 72 +#define PIN_IIC0_SDA 73 +#define PIN_IIC0_SCL 74 +#define PIN_IIC1_SDA 75 +#define PIN_IIC1_SCL 76 +#define PIN_IIC2_SDA 77 +#define PIN_IIC2_SCL 78 +#define PIN_IIC3_SDA 79 +#define PIN_IIC3_SCL 80 +#define PIN_UART0_TX 81 +#define PIN_UART0_RX 82 +#define PIN_UART0_RTS 83 +#define PIN_UART0_CTS 84 +#define PIN_UART1_TX 85 +#define PIN_UART1_RX 86 +#define PIN_UART1_RTS 87 +#define PIN_UART1_CTS 88 +#define PIN_UART2_TX 89 +#define PIN_UART2_RX 90 +#define PIN_UART2_RTS 91 +#define PIN_UART2_CTS 92 +#define PIN_UART3_TX 93 +#define PIN_UART3_RX 94 +#define PIN_UART3_RTS 95 +#define PIN_UART3_CTS 96 +#define PIN_SPI0_CS0 97 +#define PIN_SPI0_CS1 98 +#define PIN_SPI0_SDI 99 +#define PIN_SPI0_SDO 100 +#define PIN_SPI0_SCK 101 +#define PIN_SPI1_CS0 102 +#define PIN_SPI1_CS1 103 +#define PIN_SPI1_SDI 104 +#define PIN_SPI1_SDO 105 +#define PIN_SPI1_SCK 106 +#define PIN_JTAG0_TDO 107 +#define PIN_JTAG0_TCK 108 +#define PIN_JTAG0_TDI 109 +#define PIN_JTAG0_TMS 110 +#define PIN_JTAG0_TRST 111 +#define PIN_JTAG0_SRST 112 +#define PIN_JTAG1_TDO 113 +#define PIN_JTAG1_TCK 114 +#define PIN_JTAG1_TDI 115 +#define PIN_JTAG1_TMS 116 +#define PIN_JTAG1_TRST 117 +#define PIN_JTAG1_SRST 118 +#define PIN_JTAG2_TDO 119 +#define PIN_JTAG2_TCK 120 +#define PIN_JTAG2_TDI 121 +#define PIN_JTAG2_TMS 122 +#define PIN_JTAG2_TRST 123 +#define PIN_JTAG2_SRST 124 +#define PIN_GPIO0 125 +#define PIN_GPIO1 126 +#define PIN_GPIO2 127 +#define PIN_GPIO3 128 +#define PIN_GPIO4 129 +#define PIN_GPIO5 130 +#define PIN_GPIO6 131 +#define PIN_GPIO7 132 +#define PIN_GPIO8 133 +#define PIN_GPIO9 134 +#define PIN_GPIO10 135 +#define PIN_GPIO11 136 +#define PIN_GPIO12 137 +#define PIN_GPIO13 138 +#define PIN_GPIO14 139 +#define PIN_GPIO15 140 +#define PIN_GPIO16 141 +#define PIN_GPIO17 142 +#define PIN_GPIO18 143 +#define PIN_GPIO19 144 +#define PIN_GPIO20 145 +#define PIN_GPIO21 146 +#define PIN_GPIO22 147 +#define PIN_GPIO23 148 +#define PIN_GPIO24 149 +#define PIN_GPIO25 150 +#define PIN_GPIO26 151 +#define PIN_GPIO27 152 +#define PIN_GPIO28 153 +#define PIN_GPIO29 154 +#define PIN_GPIO30 155 +#define PIN_GPIO31 156 +#define PIN_MODE_SEL0 157 +#define PIN_MODE_SEL1 158 +#define PIN_MODE_SEL2 159 +#define PIN_BOOT_SEL0 160 +#define PIN_BOOT_SEL1 161 +#define PIN_BOOT_SEL2 162 +#define PIN_BOOT_SEL3 163 +#define PIN_BOOT_SEL4 164 +#define PIN_BOOT_SEL5 165 +#define PIN_BOOT_SEL6 166 +#define PIN_BOOT_SEL7 167 +#define PIN_MULTI_SCKT 168 +#define PIN_SCKT_ID0 169 +#define PIN_SCKT_ID1 170 +#define PIN_PLL_CLK_IN_MAIN 171 +#define PIN_PLL_CLK_IN_DDR_L 172 +#define PIN_PLL_CLK_IN_DDR_R 173 +#define PIN_XTAL_32K 174 +#define PIN_SYS_RST 175 +#define PIN_PWR_BUTTON 176 +#define PIN_TEST_EN 177 +#define PIN_TEST_MODE_MBIST 178 +#define PIN_TEST_MODE_SCAN 179 +#define PIN_TEST_MODE_BSD 180 +#define PIN_BISR_BYP 181 + +#endif /* _DT_BINDINGS_PINCTRL_SG2042_H */ diff --git a/include/dt-bindings/pinctrl/pinctrl-sg2044.h b/include/dt-bindings/pinctrl/pinctrl-sg2044.h new file mode 100644 index 00000000000..2a619f681c3 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-sg2044.h @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (C) 2024 Inochi Amaoto + * + */ + +#ifndef _DT_BINDINGS_PINCTRL_SG2044_H +#define _DT_BINDINGS_PINCTRL_SG2044_H + +#define PINMUX(pin, mux) \ + (((pin) & 0xffff) | (((mux) & 0xff) << 16)) + +#define PIN_IIC0_SMBSUS_IN 0 +#define PIN_IIC0_SMBSUS_OUT 1 +#define PIN_IIC0_SMBALERT 2 +#define PIN_IIC1_SMBSUS_IN 3 +#define PIN_IIC1_SMBSUS_OUT 4 +#define PIN_IIC1_SMBALERT 5 +#define PIN_IIC2_SMBSUS_IN 6 +#define PIN_IIC2_SMBSUS_OUT 7 +#define PIN_IIC2_SMBALERT 8 +#define PIN_IIC3_SMBSUS_IN 9 +#define PIN_IIC3_SMBSUS_OUT 10 +#define PIN_IIC3_SMBALERT 11 +#define PIN_PCIE0_L0_RESET 12 +#define PIN_PCIE0_L1_RESET 13 +#define PIN_PCIE0_L0_WAKEUP 14 +#define PIN_PCIE0_L1_WAKEUP 15 +#define PIN_PCIE0_L0_CLKREQ_IN 16 +#define PIN_PCIE0_L1_CLKREQ_IN 17 +#define PIN_PCIE1_L0_RESET 18 +#define PIN_PCIE1_L1_RESET 19 +#define PIN_PCIE1_L0_WAKEUP 20 +#define PIN_PCIE1_L1_WAKEUP 21 +#define PIN_PCIE1_L0_CLKREQ_IN 22 +#define PIN_PCIE1_L1_CLKREQ_IN 23 +#define PIN_PCIE2_L0_RESET 24 +#define PIN_PCIE2_L1_RESET 25 +#define PIN_PCIE2_L0_WAKEUP 26 +#define PIN_PCIE2_L1_WAKEUP 27 +#define PIN_PCIE2_L0_CLKREQ_IN 28 +#define PIN_PCIE2_L1_CLKREQ_IN 29 +#define PIN_PCIE3_L0_RESET 30 +#define PIN_PCIE3_L1_RESET 31 +#define PIN_PCIE3_L0_WAKEUP 32 +#define PIN_PCIE3_L1_WAKEUP 33 +#define PIN_PCIE3_L0_CLKREQ_IN 34 +#define PIN_PCIE3_L1_CLKREQ_IN 35 +#define PIN_PCIE4_L0_RESET 36 +#define PIN_PCIE4_L1_RESET 37 +#define PIN_PCIE4_L0_WAKEUP 38 +#define PIN_PCIE4_L1_WAKEUP 39 +#define PIN_PCIE4_L0_CLKREQ_IN 40 +#define PIN_PCIE4_L1_CLKREQ_IN 41 +#define PIN_SPIF0_CLK_SEL1 42 +#define PIN_SPIF0_CLK_SEL0 43 +#define PIN_SPIF0_WP 44 +#define PIN_SPIF0_HOLD 45 +#define PIN_SPIF0_SDI 46 +#define PIN_SPIF0_CS 47 +#define PIN_SPIF0_SCK 48 +#define PIN_SPIF0_SDO 49 +#define PIN_SPIF1_CLK_SEL1 50 +#define PIN_SPIF1_CLK_SEL0 51 +#define PIN_SPIF1_WP 52 +#define PIN_SPIF1_HOLD 53 +#define PIN_SPIF1_SDI 54 +#define PIN_SPIF1_CS 55 +#define PIN_SPIF1_SCK 56 +#define PIN_SPIF1_SDO 57 +#define PIN_EMMC_WP 58 +#define PIN_EMMC_CD 59 +#define PIN_EMMC_RST 60 +#define PIN_EMMC_PWR_EN 61 +#define PIN_SDIO_CD 62 +#define PIN_SDIO_WP 63 +#define PIN_SDIO_RST 64 +#define PIN_SDIO_PWR_EN 65 +#define PIN_RGMII0_TXD0 66 +#define PIN_RGMII0_TXD1 67 +#define PIN_RGMII0_TXD2 68 +#define PIN_RGMII0_TXD3 69 +#define PIN_RGMII0_TXCTRL 70 +#define PIN_RGMII0_RXD0 71 +#define PIN_RGMII0_RXD1 72 +#define PIN_RGMII0_RXD2 73 +#define PIN_RGMII0_RXD3 74 +#define PIN_RGMII0_RXCTRL 75 +#define PIN_RGMII0_TXC 76 +#define PIN_RGMII0_RXC 77 +#define PIN_RGMII0_REFCLKO 78 +#define PIN_RGMII0_IRQ 79 +#define PIN_RGMII0_MDC 80 +#define PIN_RGMII0_MDIO 81 +#define PIN_PWM0 82 +#define PIN_PWM1 83 +#define PIN_PWM2 84 +#define PIN_PWM3 85 +#define PIN_FAN0 86 +#define PIN_FAN1 87 +#define PIN_FAN2 88 +#define PIN_FAN3 89 +#define PIN_IIC0_SDA 90 +#define PIN_IIC0_SCL 91 +#define PIN_IIC1_SDA 92 +#define PIN_IIC1_SCL 93 +#define PIN_IIC2_SDA 94 +#define PIN_IIC2_SCL 95 +#define PIN_IIC3_SDA 96 +#define PIN_IIC3_SCL 97 +#define PIN_UART0_TX 98 +#define PIN_UART0_RX 99 +#define PIN_UART0_RTS 100 +#define PIN_UART0_CTS 101 +#define PIN_UART1_TX 102 +#define PIN_UART1_RX 103 +#define PIN_UART1_RTS 104 +#define PIN_UART1_CTS 105 +#define PIN_UART2_TX 106 +#define PIN_UART2_RX 107 +#define PIN_UART2_RTS 108 +#define PIN_UART2_CTS 109 +#define PIN_UART3_TX 110 +#define PIN_UART3_RX 111 +#define PIN_UART3_RTS 112 +#define PIN_UART3_CTS 113 +#define PIN_SPI0_CS0 114 +#define PIN_SPI0_CS1 115 +#define PIN_SPI0_SDI 116 +#define PIN_SPI0_SDO 117 +#define PIN_SPI0_SCK 118 +#define PIN_SPI1_CS0 119 +#define PIN_SPI1_CS1 120 +#define PIN_SPI1_SDI 121 +#define PIN_SPI1_SDO 122 +#define PIN_SPI1_SCK 123 +#define PIN_JTAG0_TDO 124 +#define PIN_JTAG0_TCK 125 +#define PIN_JTAG0_TDI 126 +#define PIN_JTAG0_TMS 127 +#define PIN_JTAG0_TRST 128 +#define PIN_JTAG0_SRST 129 +#define PIN_JTAG1_TDO 130 +#define PIN_JTAG1_TCK 131 +#define PIN_JTAG1_TDI 132 +#define PIN_JTAG1_TMS 133 +#define PIN_JTAG1_TRST 134 +#define PIN_JTAG1_SRST 135 +#define PIN_JTAG2_TDO 136 +#define PIN_JTAG2_TCK 137 +#define PIN_JTAG2_TDI 138 +#define PIN_JTAG2_TMS 139 +#define PIN_JTAG2_TRST 140 +#define PIN_JTAG2_SRST 141 +#define PIN_JTAG3_TDO 142 +#define PIN_JTAG3_TCK 143 +#define PIN_JTAG3_TDI 144 +#define PIN_JTAG3_TMS 145 +#define PIN_JTAG3_TRST 146 +#define PIN_JTAG3_SRST 147 +#define PIN_GPIO0 148 +#define PIN_GPIO1 149 +#define PIN_GPIO2 150 +#define PIN_GPIO3 151 +#define PIN_GPIO4 152 +#define PIN_GPIO5 153 +#define PIN_GPIO6 154 +#define PIN_GPIO7 155 +#define PIN_GPIO8 156 +#define PIN_GPIO9 157 +#define PIN_GPIO10 158 +#define PIN_GPIO11 159 +#define PIN_GPIO12 160 +#define PIN_GPIO13 161 +#define PIN_GPIO14 162 +#define PIN_GPIO15 163 +#define PIN_GPIO16 164 +#define PIN_GPIO17 165 +#define PIN_GPIO18 166 +#define PIN_GPIO19 167 +#define PIN_GPIO20 168 +#define PIN_GPIO21 169 +#define PIN_GPIO22 170 +#define PIN_GPIO23 171 +#define PIN_GPIO24 172 +#define PIN_GPIO25 173 +#define PIN_GPIO26 174 +#define PIN_GPIO27 175 +#define PIN_GPIO28 176 +#define PIN_GPIO29 177 +#define PIN_GPIO30 178 +#define PIN_GPIO31 179 +#define PIN_MODE_SEL0 180 +#define PIN_MODE_SEL1 181 +#define PIN_MODE_SEL2 182 +#define PIN_BOOT_SEL0 183 +#define PIN_BOOT_SEL1 184 +#define PIN_BOOT_SEL2 185 +#define PIN_BOOT_SEL3 186 +#define PIN_BOOT_SEL4 187 +#define PIN_BOOT_SEL5 188 +#define PIN_BOOT_SEL6 189 +#define PIN_BOOT_SEL7 190 +#define PIN_MULTI_SCKT 191 +#define PIN_SCKT_ID0 192 +#define PIN_SCKT_ID1 193 +#define PIN_PLL_CLK_IN_MAIN 194 +#define PIN_PLL_CLK_IN_DDR_0 195 +#define PIN_PLL_CLK_IN_DDR_1 196 +#define PIN_PLL_CLK_IN_DDR_2 197 +#define PIN_PLL_CLK_IN_DDR_3 198 +#define PIN_XTAL_32K 199 +#define PIN_SYS_RST 200 +#define PIN_PWR_BUTTON 201 +#define PIN_TEST_EN 202 +#define PIN_TEST_MODE_MBIST 203 +#define PIN_TEST_MODE_SCAN 204 +#define PIN_TEST_MODE_BSD 205 +#define PIN_BISR_BYP 206 + +#endif /* _DT_BINDINGS_PINCTRL_SG2044_H */ diff --git a/include/dt-bindings/power/allwinner,sun8i-v853-ppu.h b/include/dt-bindings/power/allwinner,sun8i-v853-ppu.h new file mode 100644 index 00000000000..b1c18a49061 --- /dev/null +++ b/include/dt-bindings/power/allwinner,sun8i-v853-ppu.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef _DT_BINDINGS_POWER_SUN8I_V853_PPU_H_ +#define _DT_BINDINGS_POWER_SUN8I_V853_PPU_H_ + +#define PD_RISCV 0 +#define PD_NPU 1 +#define PD_VE 2 + +#endif diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index df599bf4622..d9b7bac3095 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -65,7 +65,7 @@ #define SM6350_MSS 4 #define SM6350_MX 5 -/* SM6350 Power Domain Indexes */ +/* SM6375 Power Domain Indexes */ #define SM6375_VDDCX 0 #define SM6375_VDDCX_AO 1 #define SM6375_VDDCX_VFL 2 diff --git a/include/dt-bindings/power/thead,th1520-power.h b/include/dt-bindings/power/thead,th1520-power.h new file mode 100644 index 00000000000..8395bd1459f --- /dev/null +++ b/include/dt-bindings/power/thead,th1520-power.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2022 Alibaba Group Holding Limited. + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#ifndef __DT_BINDINGS_POWER_TH1520_H +#define __DT_BINDINGS_POWER_TH1520_H + +#define TH1520_AUDIO_PD 0 +#define TH1520_VDEC_PD 1 +#define TH1520_NPU_PD 2 +#define TH1520_VENC_PD 3 +#define TH1520_GPU_PD 4 +#define TH1520_DSP0_PD 5 +#define TH1520_DSP1_PD 6 + +#endif diff --git a/include/dt-bindings/reset/imx8mp-reset-audiomix.h b/include/dt-bindings/reset/imx8mp-reset-audiomix.h new file mode 100644 index 00000000000..746c1337ed9 --- /dev/null +++ b/include/dt-bindings/reset/imx8mp-reset-audiomix.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Copyright 2025 NXP + */ + +#ifndef DT_BINDING_RESET_IMX8MP_AUDIOMIX_H +#define DT_BINDING_RESET_IMX8MP_AUDIOMIX_H + +#define IMX8MP_AUDIOMIX_EARC_RESET 0 +#define IMX8MP_AUDIOMIX_EARC_PHY_RESET 1 +#define IMX8MP_AUDIOMIX_DSP_RUNSTALL 2 + +#endif /* DT_BINDING_RESET_IMX8MP_AUDIOMIX_H */ diff --git a/include/dt-bindings/reset/qcom,ipq9574-nsscc.h b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h new file mode 100644 index 00000000000..7f152e98b99 --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq9574-nsscc.h @@ -0,0 +1,134 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H +#define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H + +#define EDMA_HW_RESET 0 +#define NSS_CC_CE_BCR 1 +#define NSS_CC_CLC_BCR 2 +#define NSS_CC_EIP197_BCR 3 +#define NSS_CC_HAQ_BCR 4 +#define NSS_CC_IMEM_BCR 5 +#define NSS_CC_MAC_BCR 6 +#define NSS_CC_PPE_BCR 7 +#define NSS_CC_UBI_BCR 8 +#define NSS_CC_UNIPHY_BCR 9 +#define UBI3_CLKRST_CLAMP_ENABLE 10 +#define UBI3_CORE_CLAMP_ENABLE 11 +#define UBI2_CLKRST_CLAMP_ENABLE 12 +#define UBI2_CORE_CLAMP_ENABLE 13 +#define UBI1_CLKRST_CLAMP_ENABLE 14 +#define UBI1_CORE_CLAMP_ENABLE 15 +#define UBI0_CLKRST_CLAMP_ENABLE 16 +#define UBI0_CORE_CLAMP_ENABLE 17 +#define NSSNOC_NSS_CSR_ARES 18 +#define NSS_CSR_ARES 19 +#define PPE_BTQ_ARES 20 +#define PPE_IPE_ARES 21 +#define PPE_ARES 22 +#define PPE_CFG_ARES 23 +#define PPE_EDMA_ARES 24 +#define PPE_EDMA_CFG_ARES 25 +#define CRY_PPE_ARES 26 +#define NSSNOC_PPE_ARES 27 +#define NSSNOC_PPE_CFG_ARES 28 +#define PORT1_MAC_ARES 29 +#define PORT2_MAC_ARES 30 +#define PORT3_MAC_ARES 31 +#define PORT4_MAC_ARES 32 +#define PORT5_MAC_ARES 33 +#define PORT6_MAC_ARES 34 +#define XGMAC0_PTP_REF_ARES 35 +#define XGMAC1_PTP_REF_ARES 36 +#define XGMAC2_PTP_REF_ARES 37 +#define XGMAC3_PTP_REF_ARES 38 +#define XGMAC4_PTP_REF_ARES 39 +#define XGMAC5_PTP_REF_ARES 40 +#define HAQ_AHB_ARES 41 +#define HAQ_AXI_ARES 42 +#define NSSNOC_HAQ_AHB_ARES 43 +#define NSSNOC_HAQ_AXI_ARES 44 +#define CE_APB_ARES 45 +#define CE_AXI_ARES 46 +#define NSSNOC_CE_APB_ARES 47 +#define NSSNOC_CE_AXI_ARES 48 +#define CRYPTO_ARES 49 +#define NSSNOC_CRYPTO_ARES 50 +#define NSSNOC_NC_AXI0_1_ARES 51 +#define UBI0_CORE_ARES 52 +#define UBI1_CORE_ARES 53 +#define UBI2_CORE_ARES 54 +#define UBI3_CORE_ARES 55 +#define NC_AXI0_ARES 56 +#define UTCM0_ARES 57 +#define NC_AXI1_ARES 58 +#define UTCM1_ARES 59 +#define NC_AXI2_ARES 60 +#define UTCM2_ARES 61 +#define NC_AXI3_ARES 62 +#define UTCM3_ARES 63 +#define NSSNOC_NC_AXI0_ARES 64 +#define AHB0_ARES 65 +#define INTR0_AHB_ARES 66 +#define AHB1_ARES 67 +#define INTR1_AHB_ARES 68 +#define AHB2_ARES 69 +#define INTR2_AHB_ARES 70 +#define AHB3_ARES 71 +#define INTR3_AHB_ARES 72 +#define NSSNOC_AHB0_ARES 73 +#define NSSNOC_INT0_AHB_ARES 74 +#define AXI0_ARES 75 +#define AXI1_ARES 76 +#define AXI2_ARES 77 +#define AXI3_ARES 78 +#define NSSNOC_AXI0_ARES 79 +#define IMEM_QSB_ARES 80 +#define NSSNOC_IMEM_QSB_ARES 81 +#define IMEM_AHB_ARES 82 +#define NSSNOC_IMEM_AHB_ARES 83 +#define UNIPHY_PORT1_RX_ARES 84 +#define UNIPHY_PORT1_TX_ARES 85 +#define UNIPHY_PORT2_RX_ARES 86 +#define UNIPHY_PORT2_TX_ARES 87 +#define UNIPHY_PORT3_RX_ARES 88 +#define UNIPHY_PORT3_TX_ARES 89 +#define UNIPHY_PORT4_RX_ARES 90 +#define UNIPHY_PORT4_TX_ARES 91 +#define UNIPHY_PORT5_RX_ARES 92 +#define UNIPHY_PORT5_TX_ARES 93 +#define UNIPHY_PORT6_RX_ARES 94 +#define UNIPHY_PORT6_TX_ARES 95 +#define PORT1_RX_ARES 96 +#define PORT1_TX_ARES 97 +#define PORT2_RX_ARES 98 +#define PORT2_TX_ARES 99 +#define PORT3_RX_ARES 100 +#define PORT3_TX_ARES 101 +#define PORT4_RX_ARES 102 +#define PORT4_TX_ARES 103 +#define PORT5_RX_ARES 104 +#define PORT5_TX_ARES 105 +#define PORT6_RX_ARES 106 +#define PORT6_TX_ARES 107 +#define PPE_FULL_RESET 108 +#define UNIPHY0_SOFT_RESET 109 +#define UNIPHY1_SOFT_RESET 110 +#define UNIPHY2_SOFT_RESET 111 +#define UNIPHY_PORT1_ARES 112 +#define UNIPHY_PORT2_ARES 113 +#define UNIPHY_PORT3_ARES 114 +#define UNIPHY_PORT4_ARES 115 +#define UNIPHY_PORT5_ARES 116 +#define UNIPHY_PORT6_ARES 117 +#define NSSPORT1_RESET 118 +#define NSSPORT2_RESET 119 +#define NSSPORT3_RESET 120 +#define NSSPORT4_RESET 121 +#define NSSPORT5_RESET 122 +#define NSSPORT6_RESET 123 + +#endif diff --git a/include/dt-bindings/reset/rockchip,rk3528-cru.h b/include/dt-bindings/reset/rockchip,rk3528-cru.h new file mode 100644 index 00000000000..6b024c5f2e1 --- /dev/null +++ b/include/dt-bindings/reset/rockchip,rk3528-cru.h @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2022 Rockchip Electronics Co. Ltd. + * Copyright (c) 2024 Yao Zi + * Author: Joseph Chen + */ + +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H + +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_NL2 8 +#define SRST_CORE_BIU 9 +#define SRST_CORE_CRYPTO 10 +#define SRST_P_DBG 11 +#define SRST_POT_DBG 12 +#define SRST_NT_DBG 13 +#define SRST_P_CORE_GRF 14 +#define SRST_P_DAPLITE_BIU 15 +#define SRST_P_CPU_BIU 16 +#define SRST_REF_PVTPLL_CORE 17 +#define SRST_A_BUS_VOPGL_BIU 18 +#define SRST_A_BUS_H_BIU 19 +#define SRST_A_SYSMEM_BIU 20 +#define SRST_A_BUS_BIU 21 +#define SRST_H_BUS_BIU 22 +#define SRST_P_BUS_BIU 23 +#define SRST_P_DFT2APB 24 +#define SRST_P_BUS_GRF 25 +#define SRST_A_BUS_M_BIU 26 +#define SRST_A_GIC 27 +#define SRST_A_SPINLOCK 28 +#define SRST_A_DMAC 29 +#define SRST_P_TIMER 30 +#define SRST_TIMER0 31 +#define SRST_TIMER1 32 +#define SRST_TIMER2 33 +#define SRST_TIMER3 34 +#define SRST_TIMER4 35 +#define SRST_TIMER5 36 +#define SRST_P_JDBCK_DAP 37 +#define SRST_JDBCK_DAP 38 +#define SRST_P_WDT_NS 39 +#define SRST_T_WDT_NS 40 +#define SRST_H_TRNG_NS 41 +#define SRST_P_UART0 42 +#define SRST_S_UART0 43 +#define SRST_PKA_CRYPTO 44 +#define SRST_A_CRYPTO 45 +#define SRST_H_CRYPTO 46 +#define SRST_P_DMA2DDR 47 +#define SRST_A_DMA2DDR 48 +#define SRST_P_PWM0 49 +#define SRST_PWM0 50 +#define SRST_P_PWM1 51 +#define SRST_PWM1 52 +#define SRST_P_SCR 53 +#define SRST_A_DCF 54 +#define SRST_P_INTMUX 55 +#define SRST_A_VPU_BIU 56 +#define SRST_H_VPU_BIU 57 +#define SRST_P_VPU_BIU 58 +#define SRST_A_VPU 59 +#define SRST_H_VPU 60 +#define SRST_P_CRU_PCIE 61 +#define SRST_P_VPU_GRF 62 +#define SRST_H_SFC 63 +#define SRST_S_SFC 64 +#define SRST_C_EMMC 65 +#define SRST_H_EMMC 66 +#define SRST_A_EMMC 67 +#define SRST_B_EMMC 68 +#define SRST_T_EMMC 69 +#define SRST_P_GPIO1 70 +#define SRST_DB_GPIO1 71 +#define SRST_A_VPU_L_BIU 72 +#define SRST_P_VPU_IOC 73 +#define SRST_H_SAI_I2S0 74 +#define SRST_M_SAI_I2S0 75 +#define SRST_H_SAI_I2S2 76 +#define SRST_M_SAI_I2S2 77 +#define SRST_P_ACODEC 78 +#define SRST_P_GPIO3 79 +#define SRST_DB_GPIO3 80 +#define SRST_P_SPI1 81 +#define SRST_SPI1 82 +#define SRST_P_UART2 83 +#define SRST_S_UART2 84 +#define SRST_P_UART5 85 +#define SRST_S_UART5 86 +#define SRST_P_UART6 87 +#define SRST_S_UART6 88 +#define SRST_P_UART7 89 +#define SRST_S_UART7 90 +#define SRST_P_I2C3 91 +#define SRST_I2C3 92 +#define SRST_P_I2C5 93 +#define SRST_I2C5 94 +#define SRST_P_I2C6 95 +#define SRST_I2C6 96 +#define SRST_A_MAC 97 +#define SRST_P_PCIE 98 +#define SRST_PCIE_PIPE_PHY 99 +#define SRST_PCIE_POWER_UP 100 +#define SRST_P_PCIE_PHY 101 +#define SRST_P_PIPE_GRF 102 +#define SRST_H_SDIO0 103 +#define SRST_H_SDIO1 104 +#define SRST_TS_0 105 +#define SRST_TS_1 106 +#define SRST_P_CAN2 107 +#define SRST_CAN2 108 +#define SRST_P_CAN3 109 +#define SRST_CAN3 110 +#define SRST_P_SARADC 111 +#define SRST_SARADC 112 +#define SRST_SARADC_PHY 113 +#define SRST_P_TSADC 114 +#define SRST_TSADC 115 +#define SRST_A_USB3OTG 116 +#define SRST_A_GPU_BIU 117 +#define SRST_P_GPU_BIU 118 +#define SRST_A_GPU 119 +#define SRST_REF_PVTPLL_GPU 120 +#define SRST_H_RKVENC_BIU 121 +#define SRST_A_RKVENC_BIU 122 +#define SRST_P_RKVENC_BIU 123 +#define SRST_H_RKVENC 124 +#define SRST_A_RKVENC 125 +#define SRST_CORE_RKVENC 126 +#define SRST_H_SAI_I2S1 127 +#define SRST_M_SAI_I2S1 128 +#define SRST_P_I2C1 129 +#define SRST_I2C1 130 +#define SRST_P_I2C0 131 +#define SRST_I2C0 132 +#define SRST_P_SPI0 133 +#define SRST_SPI0 134 +#define SRST_P_GPIO4 135 +#define SRST_DB_GPIO4 136 +#define SRST_P_RKVENC_IOC 137 +#define SRST_H_SPDIF 138 +#define SRST_M_SPDIF 139 +#define SRST_H_PDM 140 +#define SRST_M_PDM 141 +#define SRST_P_UART1 142 +#define SRST_S_UART1 143 +#define SRST_P_UART3 144 +#define SRST_S_UART3 145 +#define SRST_P_RKVENC_GRF 146 +#define SRST_P_CAN0 147 +#define SRST_CAN0 148 +#define SRST_P_CAN1 149 +#define SRST_CAN1 150 +#define SRST_A_VO_BIU 151 +#define SRST_H_VO_BIU 152 +#define SRST_P_VO_BIU 153 +#define SRST_H_RGA2E 154 +#define SRST_A_RGA2E 155 +#define SRST_CORE_RGA2E 156 +#define SRST_H_VDPP 157 +#define SRST_A_VDPP 158 +#define SRST_CORE_VDPP 159 +#define SRST_P_VO_GRF 160 +#define SRST_P_CRU 161 +#define SRST_A_VOP_BIU 162 +#define SRST_H_VOP 163 +#define SRST_D_VOP0 164 +#define SRST_D_VOP1 165 +#define SRST_A_VOP 166 +#define SRST_P_HDMI 167 +#define SRST_HDMI 168 +#define SRST_P_HDMIPHY 169 +#define SRST_H_HDCP_KEY 170 +#define SRST_A_HDCP 171 +#define SRST_H_HDCP 172 +#define SRST_P_HDCP 173 +#define SRST_H_CVBS 174 +#define SRST_D_CVBS_VOP 175 +#define SRST_D_4X_CVBS_VOP 176 +#define SRST_A_JPEG_DECODER 177 +#define SRST_H_JPEG_DECODER 178 +#define SRST_A_VO_L_BIU 179 +#define SRST_A_MAC_VO 180 +#define SRST_A_JPEG_BIU 181 +#define SRST_H_SAI_I2S3 182 +#define SRST_M_SAI_I2S3 183 +#define SRST_MACPHY 184 +#define SRST_P_VCDCPHY 185 +#define SRST_P_GPIO2 186 +#define SRST_DB_GPIO2 187 +#define SRST_P_VO_IOC 188 +#define SRST_H_SDMMC0 189 +#define SRST_P_OTPC_NS 190 +#define SRST_SBPI_OTPC_NS 191 +#define SRST_USER_OTPC_NS 192 +#define SRST_HDMIHDP0 193 +#define SRST_H_USBHOST 194 +#define SRST_H_USBHOST_ARB 195 +#define SRST_HOST_UTMI 196 +#define SRST_P_UART4 197 +#define SRST_S_UART4 198 +#define SRST_P_I2C4 199 +#define SRST_I2C4 200 +#define SRST_P_I2C7 201 +#define SRST_I2C7 202 +#define SRST_P_USBPHY 203 +#define SRST_USBPHY_POR 204 +#define SRST_USBPHY_OTG 205 +#define SRST_USBPHY_HOST 206 +#define SRST_P_DDRPHY_CRU 207 +#define SRST_H_RKVDEC_BIU 208 +#define SRST_A_RKVDEC_BIU 209 +#define SRST_A_RKVDEC 210 +#define SRST_H_RKVDEC 211 +#define SRST_HEVC_CA_RKVDEC 212 +#define SRST_REF_PVTPLL_RKVDEC 213 +#define SRST_P_DDR_BIU 214 +#define SRST_P_DDRC 215 +#define SRST_P_DDRMON 216 +#define SRST_TIMER_DDRMON 217 +#define SRST_P_MSCH_BIU 218 +#define SRST_P_DDR_GRF 219 +#define SRST_P_DDR_HWLP 220 +#define SRST_P_DDRPHY 221 +#define SRST_MSCH_BIU 222 +#define SRST_A_DDR_UPCTL 223 +#define SRST_DDR_UPCTL 224 +#define SRST_DDRMON 225 +#define SRST_A_DDR_SCRAMBLE 226 +#define SRST_A_SPLIT 227 +#define SRST_DDR_PHY 228 + +#endif // _DT_BINDINGS_RESET_ROCKCHIP_RK3528_H diff --git a/include/dt-bindings/reset/rockchip,rk3562-cru.h b/include/dt-bindings/reset/rockchip,rk3562-cru.h new file mode 100644 index 00000000000..8df95113056 --- /dev/null +++ b/include/dt-bindings/reset/rockchip,rk3562-cru.h @@ -0,0 +1,358 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2024-2025 Rockchip Electronics Co. Ltd. + * + * Author: Elaine Zhang + */ + +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3562_H + +/********Name=SOFTRST_CON01,Offset=0x404********/ +#define SRST_A_TOP_BIU 0 +#define SRST_A_TOP_VIO_BIU 1 +#define SRST_REF_PVTPLL_LOGIC 2 +/********Name=SOFTRST_CON03,Offset=0x40C********/ +#define SRST_NCOREPORESET0 3 +#define SRST_NCOREPORESET1 4 +#define SRST_NCOREPORESET2 5 +#define SRST_NCOREPORESET3 6 +#define SRST_NCORESET0 7 +#define SRST_NCORESET1 8 +#define SRST_NCORESET2 9 +#define SRST_NCORESET3 10 +#define SRST_NL2RESET 11 +/********Name=SOFTRST_CON04,Offset=0x410********/ +#define SRST_DAP 12 +#define SRST_P_DBG_DAPLITE 13 +#define SRST_REF_PVTPLL_CORE 14 +/********Name=SOFTRST_CON05,Offset=0x414********/ +#define SRST_A_CORE_BIU 15 +#define SRST_P_CORE_BIU 16 +#define SRST_H_CORE_BIU 17 +/********Name=SOFTRST_CON06,Offset=0x418********/ +#define SRST_A_NPU_BIU 18 +#define SRST_H_NPU_BIU 19 +#define SRST_A_RKNN 20 +#define SRST_H_RKNN 21 +#define SRST_REF_PVTPLL_NPU 22 +/********Name=SOFTRST_CON08,Offset=0x420********/ +#define SRST_A_GPU_BIU 23 +#define SRST_GPU 24 +#define SRST_REF_PVTPLL_GPU 25 +#define SRST_GPU_BRG_BIU 26 +/********Name=SOFTRST_CON09,Offset=0x424********/ +#define SRST_RKVENC_CORE 27 +#define SRST_A_VEPU_BIU 28 +#define SRST_H_VEPU_BIU 29 +#define SRST_A_RKVENC 30 +#define SRST_H_RKVENC 31 +/********Name=SOFTRST_CON10,Offset=0x428********/ +#define SRST_RKVDEC_HEVC_CA 32 +#define SRST_A_VDPU_BIU 33 +#define SRST_H_VDPU_BIU 34 +#define SRST_A_RKVDEC 35 +#define SRST_H_RKVDEC 36 +/********Name=SOFTRST_CON11,Offset=0x42C********/ +#define SRST_A_VI_BIU 37 +#define SRST_H_VI_BIU 38 +#define SRST_P_VI_BIU 39 +#define SRST_ISP 40 +#define SRST_A_VICAP 41 +#define SRST_H_VICAP 42 +#define SRST_D_VICAP 43 +#define SRST_I0_VICAP 44 +#define SRST_I1_VICAP 45 +#define SRST_I2_VICAP 46 +#define SRST_I3_VICAP 47 +/********Name=SOFTRST_CON12,Offset=0x430********/ +#define SRST_P_CSIHOST0 48 +#define SRST_P_CSIHOST1 49 +#define SRST_P_CSIHOST2 50 +#define SRST_P_CSIHOST3 51 +#define SRST_P_CSIPHY0 52 +#define SRST_P_CSIPHY1 53 +/********Name=SOFTRST_CON13,Offset=0x434********/ +#define SRST_A_VO_BIU 54 +#define SRST_H_VO_BIU 55 +#define SRST_A_VOP 56 +#define SRST_H_VOP 57 +#define SRST_D_VOP 58 +#define SRST_D_VOP1 59 +/********Name=SOFTRST_CON14,Offset=0x438********/ +#define SRST_A_RGA_BIU 60 +#define SRST_H_RGA_BIU 61 +#define SRST_A_RGA 62 +#define SRST_H_RGA 63 +#define SRST_RGA_CORE 64 +#define SRST_A_JDEC 65 +#define SRST_H_JDEC 66 +/********Name=SOFTRST_CON15,Offset=0x43C********/ +#define SRST_B_EBK_BIU 67 +#define SRST_P_EBK_BIU 68 +#define SRST_AHB2AXI_EBC 69 +#define SRST_H_EBC 70 +#define SRST_D_EBC 71 +#define SRST_H_EINK 72 +#define SRST_P_EINK 73 +/********Name=SOFTRST_CON16,Offset=0x440********/ +#define SRST_P_PHP_BIU 74 +#define SRST_A_PHP_BIU 75 +#define SRST_P_PCIE20 76 +#define SRST_PCIE20_POWERUP 77 +#define SRST_USB3OTG 78 +/********Name=SOFTRST_CON17,Offset=0x444********/ +#define SRST_PIPEPHY 79 +/********Name=SOFTRST_CON18,Offset=0x448********/ +#define SRST_A_BUS_BIU 80 +#define SRST_H_BUS_BIU 81 +#define SRST_P_BUS_BIU 82 +/********Name=SOFTRST_CON19,Offset=0x44C********/ +#define SRST_P_I2C1 83 +#define SRST_P_I2C2 84 +#define SRST_P_I2C3 85 +#define SRST_P_I2C4 86 +#define SRST_P_I2C5 87 +#define SRST_I2C1 88 +#define SRST_I2C2 89 +#define SRST_I2C3 90 +#define SRST_I2C4 91 +#define SRST_I2C5 92 +/********Name=SOFTRST_CON20,Offset=0x450********/ +#define SRST_BUS_GPIO3 93 +#define SRST_BUS_GPIO4 94 +/********Name=SOFTRST_CON21,Offset=0x454********/ +#define SRST_P_TIMER 95 +#define SRST_TIMER0 96 +#define SRST_TIMER1 97 +#define SRST_TIMER2 98 +#define SRST_TIMER3 99 +#define SRST_TIMER4 100 +#define SRST_TIMER5 101 +#define SRST_P_STIMER 102 +#define SRST_STIMER0 103 +#define SRST_STIMER1 104 +/********Name=SOFTRST_CON22,Offset=0x458********/ +#define SRST_P_WDTNS 105 +#define SRST_WDTNS 106 +#define SRST_P_GRF 107 +#define SRST_P_SGRF 108 +#define SRST_P_MAILBOX 109 +#define SRST_P_INTC 110 +#define SRST_A_BUS_GIC400 111 +#define SRST_A_BUS_GIC400_DEBUG 112 +/********Name=SOFTRST_CON23,Offset=0x45C********/ +#define SRST_A_BUS_SPINLOCK 113 +#define SRST_A_DCF 114 +#define SRST_P_DCF 115 +#define SRST_F_BUS_CM0_CORE 116 +#define SRST_T_BUS_CM0_JTAG 117 +#define SRST_H_ICACHE 118 +#define SRST_H_DCACHE 119 +/********Name=SOFTRST_CON24,Offset=0x460********/ +#define SRST_P_TSADC 120 +#define SRST_TSADC 121 +#define SRST_TSADCPHY 122 +#define SRST_P_DFT2APB 123 +/********Name=SOFTRST_CON25,Offset=0x464********/ +#define SRST_A_GMAC 124 +#define SRST_P_APB2ASB_VCCIO156 125 +#define SRST_P_DSIPHY 126 +#define SRST_P_DSITX 127 +#define SRST_P_CPU_EMA_DET 128 +#define SRST_P_HASH 129 +#define SRST_P_TOPCRU 130 +/********Name=SOFTRST_CON26,Offset=0x468********/ +#define SRST_P_ASB2APB_VCCIO156 131 +#define SRST_P_IOC_VCCIO156 132 +#define SRST_P_GPIO3_VCCIO156 133 +#define SRST_P_GPIO4_VCCIO156 134 +#define SRST_P_SARADC_VCCIO156 135 +#define SRST_SARADC_VCCIO156 136 +#define SRST_SARADC_VCCIO156_PHY 137 +/********Name=SOFTRST_CON27,Offset=0x46c********/ +#define SRST_A_MAC100 138 + +/********Name=PMU0SOFTRST_CON00,Offset=0x10200********/ +#define SRST_P_PMU0_CRU 139 +#define SRST_P_PMU0_PMU 140 +#define SRST_PMU0_PMU 141 +#define SRST_P_PMU0_HP_TIMER 142 +#define SRST_PMU0_HP_TIMER 143 +#define SRST_PMU0_32K_HP_TIMER 144 +#define SRST_P_PMU0_PVTM 145 +#define SRST_PMU0_PVTM 146 +#define SRST_P_IOC_PMUIO 147 +#define SRST_P_PMU0_GPIO0 148 +#define SRST_PMU0_GPIO0 149 +#define SRST_P_PMU0_GRF 150 +#define SRST_P_PMU0_SGRF 151 +/********Name=PMU0SOFTRST_CON01,Offset=0x10204********/ +#define SRST_DDR_FAIL_SAFE 152 +#define SRST_P_PMU0_SCRKEYGEN 153 +/********Name=PMU0SOFTRST_CON02,Offset=0x10208********/ +#define SRST_P_PMU0_I2C0 154 +#define SRST_PMU0_I2C0 155 + +/********Name=PMU1SOFTRST_CON00,Offset=0x18200********/ +#define SRST_P_PMU1_CRU 156 +#define SRST_H_PMU1_MEM 157 +#define SRST_H_PMU1_BIU 158 +#define SRST_P_PMU1_BIU 159 +#define SRST_P_PMU1_UART0 160 +#define SRST_S_PMU1_UART0 161 +/********Name=PMU1SOFTRST_CON01,Offset=0x18204********/ +#define SRST_P_PMU1_SPI0 162 +#define SRST_PMU1_SPI0 163 +#define SRST_P_PMU1_PWM0 164 +#define SRST_PMU1_PWM0 165 +/********Name=PMU1SOFTRST_CON02,Offset=0x18208********/ +#define SRST_F_PMU1_CM0_CORE 166 +#define SRST_T_PMU1_CM0_JTAG 167 +#define SRST_P_PMU1_WDTNS 168 +#define SRST_PMU1_WDTNS 169 +#define SRST_PMU1_MAILBOX 170 + +/********Name=DDRSOFTRST_CON00,Offset=0x20200********/ +#define SRST_MSCH_BRG_BIU 171 +#define SRST_P_MSCH_BIU 172 +#define SRST_P_DDR_HWLP 173 +#define SRST_P_DDR_PHY 290 +#define SRST_P_DDR_DFICTL 174 +#define SRST_P_DDR_DMA2DDR 175 +/********Name=DDRSOFTRST_CON01,Offset=0x20204********/ +#define SRST_P_DDR_MON 176 +#define SRST_TM_DDR_MON 177 +#define SRST_P_DDR_GRF 178 +#define SRST_P_DDR_CRU 179 +#define SRST_P_SUBDDR_CRU 180 + +/********Name=SUBDDRSOFTRST_CON00,Offset=0x28200********/ +#define SRST_MSCH_BIU 181 +#define SRST_DDR_PHY 182 +#define SRST_DDR_DFICTL 183 +#define SRST_DDR_SCRAMBLE 184 +#define SRST_DDR_MON 185 +#define SRST_A_DDR_SPLIT 186 +#define SRST_DDR_DMA2DDR 187 + +/********Name=PERISOFTRST_CON01,Offset=0x30404********/ +#define SRST_A_PERI_BIU 188 +#define SRST_H_PERI_BIU 189 +#define SRST_P_PERI_BIU 190 +#define SRST_P_PERICRU 191 +/********Name=PERISOFTRST_CON02,Offset=0x30408********/ +#define SRST_H_SAI0_8CH 192 +#define SRST_M_SAI0_8CH 193 +#define SRST_H_SAI1_8CH 194 +#define SRST_M_SAI1_8CH 195 +#define SRST_H_SAI2_2CH 196 +#define SRST_M_SAI2_2CH 197 +/********Name=PERISOFTRST_CON03,Offset=0x3040C********/ +#define SRST_H_DSM 198 +#define SRST_DSM 199 +#define SRST_H_PDM 200 +#define SRST_M_PDM 201 +#define SRST_H_SPDIF 202 +#define SRST_M_SPDIF 203 +/********Name=PERISOFTRST_CON04,Offset=0x30410********/ +#define SRST_H_SDMMC0 204 +#define SRST_H_SDMMC1 205 +#define SRST_H_EMMC 206 +#define SRST_A_EMMC 207 +#define SRST_C_EMMC 208 +#define SRST_B_EMMC 209 +#define SRST_T_EMMC 210 +#define SRST_S_SFC 211 +#define SRST_H_SFC 212 +/********Name=PERISOFTRST_CON05,Offset=0x30414********/ +#define SRST_H_USB2HOST 213 +#define SRST_H_USB2HOST_ARB 214 +#define SRST_USB2HOST_UTMI 215 +/********Name=PERISOFTRST_CON06,Offset=0x30418********/ +#define SRST_P_SPI1 216 +#define SRST_SPI1 217 +#define SRST_P_SPI2 218 +#define SRST_SPI2 219 +/********Name=PERISOFTRST_CON07,Offset=0x3041C********/ +#define SRST_P_UART1 220 +#define SRST_P_UART2 221 +#define SRST_P_UART3 222 +#define SRST_P_UART4 223 +#define SRST_P_UART5 224 +#define SRST_P_UART6 225 +#define SRST_P_UART7 226 +#define SRST_P_UART8 227 +#define SRST_P_UART9 228 +#define SRST_S_UART1 229 +#define SRST_S_UART2 230 +/********Name=PERISOFTRST_CON08,Offset=0x30420********/ +#define SRST_S_UART3 231 +#define SRST_S_UART4 232 +#define SRST_S_UART5 233 +#define SRST_S_UART6 234 +#define SRST_S_UART7 235 +/********Name=PERISOFTRST_CON09,Offset=0x30424********/ +#define SRST_S_UART8 236 +#define SRST_S_UART9 237 +/********Name=PERISOFTRST_CON10,Offset=0x30428********/ +#define SRST_P_PWM1_PERI 238 +#define SRST_PWM1_PERI 239 +#define SRST_P_PWM2_PERI 240 +#define SRST_PWM2_PERI 241 +#define SRST_P_PWM3_PERI 242 +#define SRST_PWM3_PERI 243 +/********Name=PERISOFTRST_CON11,Offset=0x3042C********/ +#define SRST_P_CAN0 244 +#define SRST_CAN0 245 +#define SRST_P_CAN1 246 +#define SRST_CAN1 247 +/********Name=PERISOFTRST_CON12,Offset=0x30430********/ +#define SRST_A_CRYPTO 248 +#define SRST_H_CRYPTO 249 +#define SRST_P_CRYPTO 250 +#define SRST_CORE_CRYPTO 251 +#define SRST_PKA_CRYPTO 252 +#define SRST_H_KLAD 253 +#define SRST_P_KEY_READER 254 +#define SRST_H_RK_RNG_NS 255 +#define SRST_H_RK_RNG_S 256 +#define SRST_H_TRNG_NS 257 +#define SRST_H_TRNG_S 258 +#define SRST_H_CRYPTO_S 259 +/********Name=PERISOFTRST_CON13,Offset=0x30434********/ +#define SRST_P_PERI_WDT 260 +#define SRST_T_PERI_WDT 261 +#define SRST_A_SYSMEM 262 +#define SRST_H_BOOTROM 263 +#define SRST_P_PERI_GRF 264 +#define SRST_A_DMAC 265 +#define SRST_A_RKDMAC 267 +/********Name=PERISOFTRST_CON14,Offset=0x30438********/ +#define SRST_P_OTPC_NS 268 +#define SRST_SBPI_OTPC_NS 269 +#define SRST_USER_OTPC_NS 270 +#define SRST_P_OTPC_S 271 +#define SRST_SBPI_OTPC_S 272 +#define SRST_USER_OTPC_S 273 +#define SRST_OTPC_ARB 274 +#define SRST_P_OTPPHY 275 +#define SRST_OTP_NPOR 276 +/********Name=PERISOFTRST_CON15,Offset=0x3043C********/ +#define SRST_P_USB2PHY 277 +#define SRST_USB2PHY_POR 278 +#define SRST_USB2PHY_OTG 279 +#define SRST_USB2PHY_HOST 280 +#define SRST_P_PIPEPHY 281 +/********Name=PERISOFTRST_CON16,Offset=0x30440********/ +#define SRST_P_SARADC 282 +#define SRST_SARADC 283 +#define SRST_SARADC_PHY 284 +#define SRST_P_IOC_VCCIO234 285 +/********Name=PERISOFTRST_CON17,Offset=0x30444********/ +#define SRST_P_PERI_GPIO1 286 +#define SRST_P_PERI_GPIO2 287 +#define SRST_PERI_GPIO1 288 +#define SRST_PERI_GPIO2 289 + +#endif diff --git a/include/dt-bindings/reset/rockchip,rk3588-cru.h b/include/dt-bindings/reset/rockchip,rk3588-cru.h index e2fe4bd5f7f..878beae6dc3 100644 --- a/include/dt-bindings/reset/rockchip,rk3588-cru.h +++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* - * Copyright (c) 2021 Rockchip Electronics Co. Ltd. + * Copyright (c) 2021, 2024 Rockchip Electronics Co. Ltd. * Copyright (c) 2022 Collabora Ltd. * * Author: Elaine Zhang @@ -753,4 +753,43 @@ #define SRST_A_HDMIRX_BIU 660 +/* SCMI Secure Resets */ + +/* Name=SECURE_SOFTRST_CON00,Offset=0xA00 */ +#define SCMI_SRST_A_SECURE_NS_BIU 10 +#define SCMI_SRST_H_SECURE_NS_BIU 11 +#define SCMI_SRST_A_SECURE_S_BIU 12 +#define SCMI_SRST_H_SECURE_S_BIU 13 +#define SCMI_SRST_P_SECURE_S_BIU 14 +#define SCMI_SRST_CRYPTO_CORE 15 +/* Name=SECURE_SOFTRST_CON01,Offset=0xA04 */ +#define SCMI_SRST_CRYPTO_PKA 16 +#define SCMI_SRST_CRYPTO_RNG 17 +#define SCMI_SRST_A_CRYPTO 18 +#define SCMI_SRST_H_CRYPTO 19 +#define SCMI_SRST_KEYLADDER_CORE 25 +#define SCMI_SRST_KEYLADDER_RNG 26 +#define SCMI_SRST_A_KEYLADDER 27 +#define SCMI_SRST_H_KEYLADDER 28 +#define SCMI_SRST_P_OTPC_S 29 +#define SCMI_SRST_OTPC_S 30 +#define SCMI_SRST_WDT_S 31 +/* Name=SECURE_SOFTRST_CON02,Offset=0xA08 */ +#define SCMI_SRST_T_WDT_S 32 +#define SCMI_SRST_H_BOOTROM 33 +#define SCMI_SRST_A_DCF 34 +#define SCMI_SRST_P_DCF 35 +#define SCMI_SRST_H_BOOTROM_NS 37 +#define SCMI_SRST_P_KEYLADDER 46 +#define SCMI_SRST_H_TRNG_S 47 +/* Name=SECURE_SOFTRST_CON03,Offset=0xA0C */ +#define SCMI_SRST_H_TRNG_NS 48 +#define SCMI_SRST_D_SDMMC_BUFFER 49 +#define SCMI_SRST_H_SDMMC 50 +#define SCMI_SRST_H_SDMMC_BUFFER 51 +#define SCMI_SRST_SDMMC 52 +#define SCMI_SRST_P_TRNG_CHK 53 +#define SCMI_SRST_TRNG_S 54 + + #endif diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h index ed177c04afd..81b1eba2a7f 100644 --- a/include/dt-bindings/reset/sun50i-h616-ccu.h +++ b/include/dt-bindings/reset/sun50i-h616-ccu.h @@ -67,5 +67,7 @@ #define RST_BUS_HDCP 58 #define RST_BUS_KEYADC 59 #define RST_BUS_GPADC 60 +#define RST_BUS_TCON_LCD0 61 +#define RST_BUS_TCON_LCD1 62 #endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */ diff --git a/include/dt-bindings/reset/sun55i-a523-ccu.h b/include/dt-bindings/reset/sun55i-a523-ccu.h new file mode 100644 index 00000000000..70df503f34f --- /dev/null +++ b/include/dt-bindings/reset/sun55i-a523-ccu.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (c) 2024 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ +#define _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ + +#define RST_MBUS 0 +#define RST_BUS_NSI 1 +#define RST_BUS_DE 2 +#define RST_BUS_DI 3 +#define RST_BUS_G2D 4 +#define RST_BUS_SYS 5 +#define RST_BUS_GPU 6 +#define RST_BUS_CE 7 +#define RST_BUS_SYS_CE 8 +#define RST_BUS_VE 9 +#define RST_BUS_DMA 10 +#define RST_BUS_MSGBOX 11 +#define RST_BUS_SPINLOCK 12 +#define RST_BUS_CPUXTIMER 13 +#define RST_BUS_DBG 14 +#define RST_BUS_PWM0 15 +#define RST_BUS_PWM1 16 +#define RST_BUS_DRAM 17 +#define RST_BUS_NAND 18 +#define RST_BUS_MMC0 19 +#define RST_BUS_MMC1 20 +#define RST_BUS_MMC2 21 +#define RST_BUS_SYSDAP 22 +#define RST_BUS_UART0 23 +#define RST_BUS_UART1 24 +#define RST_BUS_UART2 25 +#define RST_BUS_UART3 26 +#define RST_BUS_UART4 27 +#define RST_BUS_UART5 28 +#define RST_BUS_UART6 29 +#define RST_BUS_UART7 30 +#define RST_BUS_I2C0 31 +#define RST_BUS_I2C1 32 +#define RST_BUS_I2C2 33 +#define RST_BUS_I2C3 34 +#define RST_BUS_I2C4 35 +#define RST_BUS_I2C5 36 +#define RST_BUS_CAN 37 +#define RST_BUS_SPI0 38 +#define RST_BUS_SPI1 39 +#define RST_BUS_SPI2 40 +#define RST_BUS_SPIFC 41 +#define RST_BUS_EMAC0 42 +#define RST_BUS_EMAC1 43 +#define RST_BUS_IR_RX 44 +#define RST_BUS_IR_TX 45 +#define RST_BUS_GPADC0 46 +#define RST_BUS_GPADC1 47 +#define RST_BUS_THS 48 +#define RST_USB_PHY0 49 +#define RST_USB_PHY1 50 +#define RST_BUS_OHCI0 51 +#define RST_BUS_OHCI1 52 +#define RST_BUS_EHCI0 53 +#define RST_BUS_EHCI1 54 +#define RST_BUS_OTG 55 +#define RST_BUS_3 56 +#define RST_BUS_LRADC 57 +#define RST_BUS_PCIE_USB3 58 +#define RST_BUS_DISPLAY0_TOP 59 +#define RST_BUS_DISPLAY1_TOP 60 +#define RST_BUS_HDMI_MAIN 61 +#define RST_BUS_HDMI_SUB 62 +#define RST_BUS_MIPI_DSI0 63 +#define RST_BUS_MIPI_DSI1 64 +#define RST_BUS_TCON_LCD0 65 +#define RST_BUS_TCON_LCD1 66 +#define RST_BUS_TCON_LCD2 67 +#define RST_BUS_TCON_TV0 68 +#define RST_BUS_TCON_TV1 69 +#define RST_BUS_LVDS0 70 +#define RST_BUS_LVDS1 71 +#define RST_BUS_EDP 72 +#define RST_BUS_VIDEO_OUT0 73 +#define RST_BUS_VIDEO_OUT1 74 +#define RST_BUS_LEDC 75 +#define RST_BUS_CSI 76 +#define RST_BUS_ISP 77 + +#endif /* _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun55i-a523-r-ccu.h b/include/dt-bindings/reset/sun55i-a523-r-ccu.h new file mode 100644 index 00000000000..dd6fbb372e1 --- /dev/null +++ b/include/dt-bindings/reset/sun55i-a523-r-ccu.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2024 Arm Ltd. + */ + +#ifndef _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ + +#define RST_BUS_R_TIMER 0 +#define RST_BUS_R_TWD 1 +#define RST_BUS_R_PWMCTRL 2 +#define RST_BUS_R_SPI 3 +#define RST_BUS_R_SPINLOCK 4 +#define RST_BUS_R_MSGBOX 5 +#define RST_BUS_R_UART0 6 +#define RST_BUS_R_UART1 7 +#define RST_BUS_R_I2C0 8 +#define RST_BUS_R_I2C1 9 +#define RST_BUS_R_I2C2 10 +#define RST_BUS_R_PPU1 11 +#define RST_BUS_R_IR_RX 12 +#define RST_BUS_R_RTC 13 +#define RST_BUS_R_CPUCFG 14 + +#endif /* _DT_BINDINGS_RST_SUN55I_A523_R_CCU_H_ */ diff --git a/include/dt-bindings/soc/samsung,exynos-usi.h b/include/dt-bindings/soc/samsung,exynos-usi.h index a01af169d24..b46de214dd0 100644 --- a/include/dt-bindings/soc/samsung,exynos-usi.h +++ b/include/dt-bindings/soc/samsung,exynos-usi.h @@ -9,9 +9,18 @@ #ifndef __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H #define __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H -#define USI_V2_NONE 0 -#define USI_V2_UART 1 -#define USI_V2_SPI 2 -#define USI_V2_I2C 3 +#define USI_MODE_NONE 0 +#define USI_MODE_UART 1 +#define USI_MODE_SPI 2 +#define USI_MODE_I2C 3 +#define USI_MODE_I2C1 4 +#define USI_MODE_I2C0_1 5 +#define USI_MODE_UART_I2C1 6 + +/* Deprecated */ +#define USI_V2_NONE USI_MODE_NONE +#define USI_V2_UART USI_MODE_UART +#define USI_V2_SPI USI_MODE_SPI +#define USI_V2_I2C USI_MODE_I2C #endif /* __DT_BINDINGS_SAMSUNG_EXYNOS_USI_H */ diff --git a/include/dt-bindings/sound/qcom,wcd934x.h b/include/dt-bindings/sound/qcom,wcd934x.h new file mode 100644 index 00000000000..8b30d34fcc8 --- /dev/null +++ b/include/dt-bindings/sound/qcom,wcd934x.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ + +#ifndef __DT_SOUND_QCOM_WCD934x_H +#define __DT_SOUND_QCOM_WCD934x_H + +#define AIF1_PB 0 +#define AIF1_CAP 1 +#define AIF2_PB 2 +#define AIF2_CAP 3 +#define AIF3_PB 4 +#define AIF3_CAP 5 +#define AIF4_PB 6 +#define AIF4_VIFEED 7 +#define AIF4_MAD_TX 8 + +#endif diff --git a/src/arm/allwinner/sun8i-v3s-netcube-kumquat.dts b/src/arm/allwinner/sun8i-v3s-netcube-kumquat.dts new file mode 100644 index 00000000000..5143cb4e7b7 --- /dev/null +++ b/src/arm/allwinner/sun8i-v3s-netcube-kumquat.dts @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2025 Lukas Schmid + */ + +/dts-v1/; +#include "sun8i-v3s.dtsi" + +#include +#include +#include + +/{ + model = "NetCube Systems Kumquat"; + compatible = "netcube,kumquat", "allwinner,sun8i-v3s"; + + aliases { + serial0 = &uart0; + ethernet0 = &emac; + rtc0 = &ds3232; + rtc1 = &rtc; /* not battery backed */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* 40 MHz Crystal Oscillator on PCB */ + clk_can0: clock-can0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + key-user { + label = "GPIO Key User"; + linux,code = ; + gpios = <&pio 1 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; /* PB2 */ + }; + }; + + leds { + compatible = "gpio-leds"; + + led-heartbeat { + gpios = <&pio 4 4 GPIO_ACTIVE_HIGH>; /* PE4 */ + linux,default-trigger = "heartbeat"; + color = ; + function = LED_FUNCTION_HEARTBEAT; + }; + + led-mmc0-act { + gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + linux,default-trigger = "mmc0"; + color = ; + function = LED_FUNCTION_DISK; + }; + }; + + /* EA3036C Switching 3 Channel Regulator - Channel 2 */ + reg_vcc3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v0>; + }; + + /* K7805-1000R3 Switching Regulator supplied from main 12/24V terminal block */ + reg_vcc5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&codec { + allwinner,audio-routing = + "Headphone", "HP", + "Headphone", "HPCOM", + "MIC1", "Mic", + "Mic", "HBIAS"; + status = "okay"; +}; + +&ehci { + status = "okay"; +}; + +&emac { + allwinner,leds-active-low; + nvmem-cells = <ð0_macaddress>; + nvmem-cell-names = "mac-address"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom0: eeprom@50 { + compatible = "atmel,24c02"; /* actually it's a 24AA02E48 */ + reg = <0x50>; + pagesize = <16>; + read-only; + vcc-supply = <®_vcc3v3>; + + #address-cells = <1>; + #size-cells = <1>; + + eth0_macaddress: macaddress@fa { + reg = <0xfa 0x06>; + }; + }; + + tusb320: typec@60 { + compatible = "ti,tusb320"; + reg = <0x60>; + interrupts-extended = <&pio 1 5 IRQ_TYPE_LEVEL_LOW>; /* PB5 */ + }; + + ds3232: rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + }; +}; + +/* Exposed as the Flash/SD Header on the board */ +&mmc0 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + broken-cd; + status = "okay"; +}; + +/* Connected to the on-board ESP32 */ +&mmc1 { + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + broken-cd; + status = "okay"; +}; + +&ohci { + status = "okay"; +}; + +/* Disable external 32k osc as it is broken on current revision */ +&osc32k { + status = "disabled"; +}; + +&pio { + vcc-pb-supply = <®_vcc3v3>; + vcc-pc-supply = <®_vcc3v3>; + vcc-pe-supply = <®_vcc3v3>; + vcc-pf-supply = <®_vcc3v3>; + vcc-pg-supply = <®_vcc3v3>; + + gpio-line-names = "", "", "", "", // PA + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "CAN_nCS", "CAN_nINT", "USER_SW", "PB3", // PB + "USB_ID", "USBC_nINT", "I2C0_SCL", "I2C0_SDA", + "UART0_TX", "UART0_RX", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "SPI_MISO", "SPI_SCK", "FLASH_nCS", "SPI_MOSI", // PC + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", // PD + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "Q12", "Q11", "Q10", "Q9", // PE + "LED_SYS0", "I1", "Q1", "Q2", + "I2", "I3", "Q3", "Q4", + "I4", "I5", "Q5", "Q6", + "I6", "I7", "Q7", "Q8", + "I8", "UART1_TXD", "UART1_RXD", "ESP_nRST", + "ESP_nBOOT", "", "", "", + "", "", "", "", + "SD_D1", "SD_D0", "SD_CLK", "SD_CMD", // PF + "SD_D3", "SD_D2", "LED_SYS1", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "ESP_CLK", "ESP_CMD", "ESP_D0", "ESP_D1", // PG + "ESP_D2", "ESP_D3", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* Disable external 32k osc as it is broken on current revision */ +&rtc { + /delete-property/ clocks; +}; + +/* Exposed as a USB-C connector with USB-Serial converter */ +&uart0 { + pinctrl-0 = <&uart0_pb_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* Connected to the Bootloader/Console of the ESP32 */ +&uart1 { + pinctrl-0 = <&uart1_pe_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb_otg { + extcon = <&tusb320 0>; + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + status = "okay"; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <0>, <&pio 1 0 GPIO_ACTIVE_LOW>; /* PB0 */ + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + label = "firmware"; + spi-max-frequency = <40000000>; + }; + + can@1 { + compatible = "microchip,mcp2518fd"; + reg = <1>; + clocks = <&clk_can0>; + interrupts-extended = <&pio 1 1 IRQ_TYPE_LEVEL_LOW>; /* PB1 */ + spi-max-frequency = <20000000>; + vdd-supply = <®_vcc3v3>; + xceiver-supply = <®_vcc3v3>; + }; +}; diff --git a/src/arm/allwinner/sun8i-v3s.dtsi b/src/arm/allwinner/sun8i-v3s.dtsi index 9e13c2aa891..f909b1d4dbc 100644 --- a/src/arm/allwinner/sun8i-v3s.dtsi +++ b/src/arm/allwinner/sun8i-v3s.dtsi @@ -416,6 +416,12 @@ function = "uart0"; }; + /omit-if-no-ref/ + uart1_pe_pins: uart1-pe-pins { + pins = "PE21", "PE22"; + function = "uart1"; + }; + uart2_pins: uart2-pins { pins = "PB0", "PB1"; function = "uart2"; diff --git a/src/arm/amlogic/meson8.dtsi b/src/arm/amlogic/meson8.dtsi index 9ff142d9fe3..f785e0de084 100644 --- a/src/arm/amlogic/meson8.dtsi +++ b/src/arm/amlogic/meson8.dtsi @@ -449,7 +449,11 @@ }; pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; reg = <0x86c0 0x10>; #pwm-cells = <3>; status = "disabled"; @@ -699,11 +703,19 @@ }; &pwm_ab { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &pwm_cd { - compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &rtc { diff --git a/src/arm/amlogic/meson8b-ec100.dts b/src/arm/amlogic/meson8b-ec100.dts index 18ea6592b7d..23699954809 100644 --- a/src/arm/amlogic/meson8b-ec100.dts +++ b/src/arm/amlogic/meson8b-ec100.dts @@ -443,8 +443,6 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &rtc { diff --git a/src/arm/amlogic/meson8b-mxq.dts b/src/arm/amlogic/meson8b-mxq.dts index fb28cb330f1..0bca0b33eea 100644 --- a/src/arm/amlogic/meson8b-mxq.dts +++ b/src/arm/amlogic/meson8b-mxq.dts @@ -162,8 +162,6 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &uart_AO { diff --git a/src/arm/amlogic/meson8b-odroidc1.dts b/src/arm/amlogic/meson8b-odroidc1.dts index 2aa012f38a3..1cd2093202c 100644 --- a/src/arm/amlogic/meson8b-odroidc1.dts +++ b/src/arm/amlogic/meson8b-odroidc1.dts @@ -347,8 +347,6 @@ status = "okay"; pinctrl-0 = <&pwm_c1_pins>, <&pwm_d_pins>; pinctrl-names = "default"; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; &rtc { diff --git a/src/arm/amlogic/meson8b.dtsi b/src/arm/amlogic/meson8b.dtsi index 9e02a97f86a..fdb0abe23a0 100644 --- a/src/arm/amlogic/meson8b.dtsi +++ b/src/arm/amlogic/meson8b.dtsi @@ -403,8 +403,12 @@ }; pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x86c0 0x10>; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; @@ -674,11 +678,19 @@ }; &pwm_ab { - compatible = "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &pwm_cd { - compatible = "amlogic,meson8b-pwm"; + compatible = "amlogic,meson8b-pwm-v2", "amlogic,meson8-pwm-v2"; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "Video PLL" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; }; &rtc { diff --git a/src/arm/cirrus/ep7211-edb7211.dts b/src/arm/cirrus/ep7211-edb7211.dts index 808cd5778e2..adc74243ed1 100644 --- a/src/arm/cirrus/ep7211-edb7211.dts +++ b/src/arm/cirrus/ep7211-edb7211.dts @@ -88,7 +88,7 @@ }; &portd { - lcden { + lcden-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; output-high; diff --git a/src/arm/intel/ixp/intel-ixp42x-netgear-wg302v1.dts b/src/arm/intel/ixp/intel-ixp42x-netgear-wg302v1.dts index 19d56e9aec9..a351a97d257 100644 --- a/src/arm/intel/ixp/intel-ixp42x-netgear-wg302v1.dts +++ b/src/arm/intel/ixp/intel-ixp42x-netgear-wg302v1.dts @@ -8,6 +8,7 @@ #include "intel-ixp42x.dtsi" #include +#include / { model = "Netgear WG302 v1"; @@ -32,6 +33,35 @@ serial0 = &uart1; }; + leds { + compatible = "gpio-leds"; + test_led: led-test { + color = ; + function = "test"; + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + wlan_led: led-wlan { + color = ; + function = LED_FUNCTION_WLAN; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + linux,default-trigger = "phy0tx"; + }; + }; + + gpio_keys { + /* RESET is on GPIO13 which can't fire interrupts */ + compatible = "gpio-keys-polled"; + poll-interval = <100>; + + button-reset { + linux,code = ; + label = "reset"; + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + }; + }; + soc { bus@c4000000 { flash@0,0 { @@ -57,7 +87,7 @@ status = "okay"; /* - * Taken from WG302 v2 PCI boardfile (wg302v2-pci.c) + * Taken from WG302 v1 PCI boardfile (wg302v1-pci.c) * We have slots (IDSEL) 1 and 2 with one assigned IRQ * each handling all IRQs. */ @@ -70,10 +100,10 @@ <0x0800 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 8 */ <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ /* IDSEL 2 */ - <0x1000 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 9 */ - <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ - <0x1000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 9 */ - <0x1000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 9 */ + <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ + <0x1000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 10 */ + <0x1000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 10 */ + <0x1000 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 10 */ }; ethernet@c8009000 { diff --git a/src/arm/intel/ixp/intel-ixp4xx.dtsi b/src/arm/intel/ixp/intel-ixp4xx.dtsi index 51a716c5966..0adeccabd4f 100644 --- a/src/arm/intel/ixp/intel-ixp4xx.dtsi +++ b/src/arm/intel/ixp/intel-ixp4xx.dtsi @@ -193,10 +193,10 @@ compatible = "intel,ixp4xx-ethernet"; reg = <0xc800c000 0x1000>; status = "disabled"; - intel,npe = <0>; /* Dummy values that depend on firmware */ queue-rx = <&qmgr 0>; queue-txready = <&qmgr 0>; + intel,npe-handle = <&npe 0>; }; }; }; diff --git a/src/arm/marvell/armada-385-clearfog-gtr.dtsi b/src/arm/marvell/armada-385-clearfog-gtr.dtsi index 8208c6a9627..7aa71a9aa1b 100644 --- a/src/arm/marvell/armada-385-clearfog-gtr.dtsi +++ b/src/arm/marvell/armada-385-clearfog-gtr.dtsi @@ -453,7 +453,7 @@ pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>; pinctrl-names = "default"; - wifi-disable { + wifi-disable-hog { gpio-hog; gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>; output-low; @@ -465,7 +465,7 @@ pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>; pinctrl-names = "default"; - lte-disable { + lte-disable-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_LOW>; output-low; @@ -476,14 +476,14 @@ * This signal, when asserted, isolates Armada 38x sample at reset pins * from control of external devices. Should be de-asserted after reset. */ - sar-isolation { + sar-isolation-hog { gpio-hog; gpios = <15 GPIO_ACTIVE_LOW>; output-low; line-name = "sar-isolation"; }; - poe-reset { + poe-reset-hog { gpio-hog; gpios = <16 GPIO_ACTIVE_LOW>; output-low; diff --git a/src/arm/marvell/armada-388-clearfog-base.dts b/src/arm/marvell/armada-388-clearfog-base.dts index f7daa3bc707..cf32ba9b4e8 100644 --- a/src/arm/marvell/armada-388-clearfog-base.dts +++ b/src/arm/marvell/armada-388-clearfog-base.dts @@ -34,7 +34,7 @@ }; &gpio0 { - phy1_reset { + phy1-reset-hog { gpio-hog; gpios = <19 GPIO_ACTIVE_LOW>; output-low; diff --git a/src/arm/marvell/kirkwood-openrd.dtsi b/src/arm/marvell/kirkwood-openrd.dtsi index 47f03c69c55..9d7cff4fead 100644 --- a/src/arm/marvell/kirkwood-openrd.dtsi +++ b/src/arm/marvell/kirkwood-openrd.dtsi @@ -53,7 +53,7 @@ cd-gpios = <&gpio0 29 9>; }; gpio@10100 { - p28 { + p28-hog { gpio-hog; gpios = <28 GPIO_ACTIVE_HIGH>; /* @@ -71,7 +71,7 @@ }; }; gpio@10140 { - p2 { + p2-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; /* diff --git a/src/arm/microchip/aks-cdu.dts b/src/arm/microchip/aks-cdu.dts index b65f80e1ef0..302cb872efa 100644 --- a/src/arm/microchip/aks-cdu.dts +++ b/src/arm/microchip/aks-cdu.dts @@ -56,7 +56,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/src/arm/microchip/animeo_ip.dts b/src/arm/microchip/animeo_ip.dts index 7f527622d3f..c11f4f7dac9 100644 --- a/src/arm/microchip/animeo_ip.dts +++ b/src/arm/microchip/animeo_ip.dts @@ -136,7 +136,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>; status = "okay"; diff --git a/src/arm/microchip/at91-foxg20.dts b/src/arm/microchip/at91-foxg20.dts index 9dfd5de808d..8e9e8766504 100644 --- a/src/arm/microchip/at91-foxg20.dts +++ b/src/arm/microchip/at91-foxg20.dts @@ -131,7 +131,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/src/arm/microchip/at91-qil_a9260.dts b/src/arm/microchip/at91-qil_a9260.dts index 5ccb3c13959..892dbd8dbbe 100644 --- a/src/arm/microchip/at91-qil_a9260.dts +++ b/src/arm/microchip/at91-qil_a9260.dts @@ -114,7 +114,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/src/arm/microchip/at91-sam9_l9260.dts b/src/arm/microchip/at91-sam9_l9260.dts index 2fb51b9aca2..49dc1a4ccb3 100644 --- a/src/arm/microchip/at91-sam9_l9260.dts +++ b/src/arm/microchip/at91-sam9_l9260.dts @@ -105,7 +105,7 @@ status = "okay"; }; - usb0: ohci@500000 { + usb0: usb@500000 { status = "okay"; }; diff --git a/src/arm/microchip/at91-sama5d27_som1_ek.dts b/src/arm/microchip/at91-sama5d27_som1_ek.dts index f3ffb8f01d8..45edf6214cf 100644 --- a/src/arm/microchip/at91-sama5d27_som1_ek.dts +++ b/src/arm/microchip/at91-sama5d27_som1_ek.dts @@ -37,7 +37,7 @@ status = "okay"; }; - usb1: ohci@400000 { + usb1: usb@400000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioA PIN_PD20 GPIO_ACTIVE_HIGH */ &pioA PIN_PA27 GPIO_ACTIVE_HIGH @@ -48,7 +48,7 @@ status = "okay"; }; - usb2: ehci@500000 { + usb2: usb@500000 { status = "okay"; }; diff --git a/src/arm/microchip/at91-sama5d2_ptc_ek.dts b/src/arm/microchip/at91-sama5d2_ptc_ek.dts index e4ae60ef5f8..10d69f6957c 100644 --- a/src/arm/microchip/at91-sama5d2_ptc_ek.dts +++ b/src/arm/microchip/at91-sama5d2_ptc_ek.dts @@ -47,7 +47,7 @@ status = "okay"; }; - usb1: ohci@400000 { + usb1: usb@400000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioA PIN_PB12 GPIO_ACTIVE_HIGH @@ -58,7 +58,7 @@ status = "okay"; }; - usb2: ehci@500000 { + usb2: usb@500000 { status = "okay"; }; diff --git a/src/arm/microchip/at91-sama5d2_xplained.dts b/src/arm/microchip/at91-sama5d2_xplained.dts index 4bab3f25b85..7e77a55ed41 100644 --- a/src/arm/microchip/at91-sama5d2_xplained.dts +++ b/src/arm/microchip/at91-sama5d2_xplained.dts @@ -46,7 +46,7 @@ status = "okay"; }; - usb1: ohci@400000 { + usb1: usb@400000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioA PIN_PB9 GPIO_ACTIVE_HIGH */ &pioA PIN_PB10 GPIO_ACTIVE_HIGH @@ -57,7 +57,7 @@ status = "okay"; }; - usb2: ehci@500000 { + usb2: usb@500000 { status = "okay"; }; diff --git a/src/arm/microchip/at91-sama5d3_xplained.dts b/src/arm/microchip/at91-sama5d3_xplained.dts index 5662992cf21..d2c43957497 100644 --- a/src/arm/microchip/at91-sama5d3_xplained.dts +++ b/src/arm/microchip/at91-sama5d3_xplained.dts @@ -283,7 +283,7 @@ status = "okay"; }; - usb1: ohci@600000 { + usb1: usb@600000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 3 GPIO_ACTIVE_LOW @@ -294,7 +294,7 @@ status = "okay"; }; - usb2: ehci@700000 { + usb2: usb@700000 { status = "okay"; }; diff --git a/src/arm/microchip/at91-sama5d4_ma5d4evk.dts b/src/arm/microchip/at91-sama5d4_ma5d4evk.dts index 8adf567f2f0..b9725e40050 100644 --- a/src/arm/microchip/at91-sama5d4_ma5d4evk.dts +++ b/src/arm/microchip/at91-sama5d4_ma5d4evk.dts @@ -22,7 +22,7 @@ status = "okay"; }; - usb1: ohci@500000 { + usb1: usb@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_LOW @@ -31,7 +31,7 @@ status = "okay"; }; - usb2: ehci@600000 { + usb2: usb@600000 { status = "okay"; }; diff --git a/src/arm/microchip/at91-sama5d4_xplained.dts b/src/arm/microchip/at91-sama5d4_xplained.dts index 95d701d13fe..0ecccb9a809 100644 --- a/src/arm/microchip/at91-sama5d4_xplained.dts +++ b/src/arm/microchip/at91-sama5d4_xplained.dts @@ -164,7 +164,7 @@ status = "okay"; }; - usb1: ohci@500000 { + usb1: usb@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_HIGH @@ -175,7 +175,7 @@ status = "okay"; }; - usb2: ehci@600000 { + usb2: usb@600000 { status = "okay"; }; diff --git a/src/arm/microchip/at91-sama5d4ek.dts b/src/arm/microchip/at91-sama5d4ek.dts index 20ac775059c..69107d6cd26 100644 --- a/src/arm/microchip/at91-sama5d4ek.dts +++ b/src/arm/microchip/at91-sama5d4ek.dts @@ -198,7 +198,7 @@ status = "okay"; }; - usb1: ohci@500000 { + usb1: usb@500000 { num-ports = <3>; atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */ &pioE 11 GPIO_ACTIVE_LOW @@ -207,7 +207,7 @@ status = "okay"; }; - usb2: ehci@600000 { + usb2: usb@600000 { status = "okay"; }; diff --git a/src/arm/microchip/at91-sama7d65_curiosity.dts b/src/arm/microchip/at91-sama7d65_curiosity.dts index 0f86360fb73..30fdc4f55a3 100644 --- a/src/arm/microchip/at91-sama7d65_curiosity.dts +++ b/src/arm/microchip/at91-sama7d65_curiosity.dts @@ -32,6 +32,18 @@ }; }; +&dma0 { + status = "okay"; +}; + +&dma1 { + status = "okay"; +}; + +&dma2 { + status = "okay"; +}; + &flx6 { atmel,flexcom-mode = ; status = "okay"; @@ -43,11 +55,63 @@ status = "okay"; }; +&flx10 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&i2c10 { + dmas = <0>, <0>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c10_default>; + status = "okay"; + + power-monitor@10 { + compatible = "microchip,pac1934"; + reg = <0x10>; + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <0x1>; + shunt-resistor-micro-ohms = <47000>; + label = "VDD3V3"; + }; + + channel@2 { + reg = <0x2>; + shunt-resistor-micro-ohms = <47000>; + label = "VDDIODDR"; + }; + + channel@3 { + reg = <0x3>; + shunt-resistor-micro-ohms = <47000>; + label = "VDDCORE"; + }; + + channel@4 { + reg = <0x4>; + shunt-resistor-micro-ohms = <47000>; + label = "VDDCPU"; + }; + }; +}; + &main_xtal { clock-frequency = <24000000>; }; &pioa { + pinctrl_i2c10_default: i2c10-default{ + pinmux = , + ; + bias-pull-up; + }; + pinctrl_sdmmc1_default: sdmmc1-default { cmd-data { pinmux = , @@ -84,6 +148,15 @@ status = "okay"; }; +&shdwc { + debounce-delay-us = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + &slow_xtal { clock-frequency = <32768>; }; diff --git a/src/arm/microchip/at91-sama7g5ek.dts b/src/arm/microchip/at91-sama7g5ek.dts index 0f5e6ad438d..2543599013b 100644 --- a/src/arm/microchip/at91-sama7g5ek.dts +++ b/src/arm/microchip/at91-sama7g5ek.dts @@ -137,6 +137,7 @@ vref-supply = <&vddout25>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mikrobus1_an_default &pinctrl_mikrobus2_an_default>; + atmel,trigger-edge-type = ; status = "okay"; }; diff --git a/src/arm/microchip/at91-vinco.dts b/src/arm/microchip/at91-vinco.dts index ecbdacf4870..c5fc5166706 100644 --- a/src/arm/microchip/at91-vinco.dts +++ b/src/arm/microchip/at91-vinco.dts @@ -162,7 +162,7 @@ status = "disabled"; }; - usb1: ohci@500000 { + usb1: usb@500000 { num-ports = <3>; atmel,vbus-gpio = <0 &pioE 11 GPIO_ACTIVE_LOW @@ -171,7 +171,7 @@ status = "disabled"; }; - usb2: ehci@600000 { + usb2: usb@600000 { /* 4G Modem */ status = "okay"; }; diff --git a/src/arm/microchip/at91rm9200.dtsi b/src/arm/microchip/at91rm9200.dtsi index 02a838541dc..2a4c83d8873 100644 --- a/src/arm/microchip/at91rm9200.dtsi +++ b/src/arm/microchip/at91rm9200.dtsi @@ -702,7 +702,7 @@ status = "disabled"; }; - usb0: ohci@300000 { + usb0: usb@300000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00300000 0x100000>; interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/src/arm/microchip/at91rm9200ek.dts b/src/arm/microchip/at91rm9200ek.dts index 0bf472b157a..ce691c4692b 100644 --- a/src/arm/microchip/at91rm9200ek.dts +++ b/src/arm/microchip/at91rm9200ek.dts @@ -89,7 +89,7 @@ }; }; - usb0: ohci@300000 { + usb0: usb@300000 { num-ports = <2>; status = "okay"; }; diff --git a/src/arm/microchip/at91sam9260.dtsi b/src/arm/microchip/at91sam9260.dtsi index 0038183e9a5..ec973f07a96 100644 --- a/src/arm/microchip/at91sam9260.dtsi +++ b/src/arm/microchip/at91sam9260.dtsi @@ -742,7 +742,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/src/arm/microchip/at91sam9260ek.dts b/src/arm/microchip/at91sam9260ek.dts index e8e65e60564..8522a210b48 100644 --- a/src/arm/microchip/at91sam9260ek.dts +++ b/src/arm/microchip/at91sam9260ek.dts @@ -131,7 +131,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/src/arm/microchip/at91sam9261.dtsi b/src/arm/microchip/at91sam9261.dtsi index b57a7fd6719..0b556c23455 100644 --- a/src/arm/microchip/at91sam9261.dtsi +++ b/src/arm/microchip/at91sam9261.dtsi @@ -77,7 +77,7 @@ #size-cells = <1>; ranges; - usb0: ohci@500000 { + usb0: usb@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/src/arm/microchip/at91sam9261ek.dts b/src/arm/microchip/at91sam9261ek.dts index a8f523131cd..313bc2797fd 100644 --- a/src/arm/microchip/at91sam9261ek.dts +++ b/src/arm/microchip/at91sam9261ek.dts @@ -31,7 +31,7 @@ }; ahb { - usb0: ohci@500000 { + usb0: usb@500000 { status = "okay"; }; diff --git a/src/arm/microchip/at91sam9263.dtsi b/src/arm/microchip/at91sam9263.dtsi index b95d4016ae9..3e9e5ce7c6c 100644 --- a/src/arm/microchip/at91sam9263.dtsi +++ b/src/arm/microchip/at91sam9263.dtsi @@ -768,7 +768,7 @@ status = "disabled"; }; - usb0: ohci@a00000 { + usb0: usb@a00000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00a00000 0x100000>; interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/src/arm/microchip/at91sam9263ek.dts b/src/arm/microchip/at91sam9263ek.dts index f25692543d7..471ea25296a 100644 --- a/src/arm/microchip/at91sam9263ek.dts +++ b/src/arm/microchip/at91sam9263ek.dts @@ -207,7 +207,7 @@ }; }; - usb0: ohci@a00000 { + usb0: usb@a00000 { num-ports = <2>; status = "okay"; atmel,vbus-gpio = <&pioA 24 GPIO_ACTIVE_HIGH diff --git a/src/arm/microchip/at91sam9g20ek_common.dtsi b/src/arm/microchip/at91sam9g20ek_common.dtsi index 4e7cfbbd424..84a7287107f 100644 --- a/src/arm/microchip/at91sam9g20ek_common.dtsi +++ b/src/arm/microchip/at91sam9g20ek_common.dtsi @@ -211,7 +211,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/src/arm/microchip/at91sam9g45.dtsi b/src/arm/microchip/at91sam9g45.dtsi index 157d306ef5c..535e26e05e9 100644 --- a/src/arm/microchip/at91sam9g45.dtsi +++ b/src/arm/microchip/at91sam9g45.dtsi @@ -964,7 +964,7 @@ status = "disabled"; }; - usb0: ohci@700000 { + usb0: usb@700000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; @@ -973,7 +973,7 @@ status = "disabled"; }; - usb1: ehci@800000 { + usb1: usb@800000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00800000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/src/arm/microchip/at91sam9m10g45ek.dts b/src/arm/microchip/at91sam9m10g45ek.dts index 071db4f1631..2a31b2f1489 100644 --- a/src/arm/microchip/at91sam9m10g45ek.dts +++ b/src/arm/microchip/at91sam9m10g45ek.dts @@ -303,14 +303,14 @@ }; }; - usb0: ohci@700000 { + usb0: usb@700000 { status = "okay"; num-ports = <2>; atmel,vbus-gpio = <&pioD 1 GPIO_ACTIVE_LOW &pioD 3 GPIO_ACTIVE_LOW>; }; - usb1: ehci@800000 { + usb1: usb@800000 { status = "okay"; }; }; diff --git a/src/arm/microchip/at91sam9n12.dtsi b/src/arm/microchip/at91sam9n12.dtsi index 844bd50943f..2f930c39ce4 100644 --- a/src/arm/microchip/at91sam9n12.dtsi +++ b/src/arm/microchip/at91sam9n12.dtsi @@ -748,7 +748,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x00100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/src/arm/microchip/at91sam9n12ek.dts b/src/arm/microchip/at91sam9n12ek.dts index 643c3b2ab97..b06a54e8e23 100644 --- a/src/arm/microchip/at91sam9n12ek.dts +++ b/src/arm/microchip/at91sam9n12ek.dts @@ -180,7 +180,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <1>; atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>; status = "okay"; diff --git a/src/arm/microchip/at91sam9x5.dtsi b/src/arm/microchip/at91sam9x5.dtsi index 27c1f2861cc..17bdf1e4db0 100644 --- a/src/arm/microchip/at91sam9x5.dtsi +++ b/src/arm/microchip/at91sam9x5.dtsi @@ -886,7 +886,7 @@ }; }; - usb0: ohci@600000 { + usb0: usb@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; @@ -895,7 +895,7 @@ status = "disabled"; }; - usb1: ehci@700000 { + usb1: usb@700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/src/arm/microchip/ethernut5.dts b/src/arm/microchip/ethernut5.dts index ad7a0850252..52ccef31b39 100644 --- a/src/arm/microchip/ethernut5.dts +++ b/src/arm/microchip/ethernut5.dts @@ -101,7 +101,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/src/arm/microchip/evk-pro3.dts b/src/arm/microchip/evk-pro3.dts index 6d519d02d19..40c5111c2f0 100644 --- a/src/arm/microchip/evk-pro3.dts +++ b/src/arm/microchip/evk-pro3.dts @@ -45,7 +45,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; diff --git a/src/arm/microchip/mpa1600.dts b/src/arm/microchip/mpa1600.dts index 005c2758e22..2a97e2c0b89 100644 --- a/src/arm/microchip/mpa1600.dts +++ b/src/arm/microchip/mpa1600.dts @@ -57,7 +57,7 @@ }; }; - usb0: ohci@300000 { + usb0: usb@300000 { num-ports = <1>; status = "okay"; }; diff --git a/src/arm/microchip/pm9g45.dts b/src/arm/microchip/pm9g45.dts index c349fd3758a..2258e62f586 100644 --- a/src/arm/microchip/pm9g45.dts +++ b/src/arm/microchip/pm9g45.dts @@ -139,12 +139,12 @@ }; }; - usb0: ohci@700000 { + usb0: usb@700000 { status = "okay"; num-ports = <2>; }; - usb1: ehci@800000 { + usb1: usb@800000 { status = "okay"; }; }; diff --git a/src/arm/microchip/sam9x60.dtsi b/src/arm/microchip/sam9x60.dtsi index b8b2c1ddf3f..b075865e6a7 100644 --- a/src/arm/microchip/sam9x60.dtsi +++ b/src/arm/microchip/sam9x60.dtsi @@ -88,7 +88,7 @@ status = "disabled"; }; - usb1: ohci@600000 { + usb1: usb@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; @@ -97,7 +97,7 @@ status = "disabled"; }; - usb2: ehci@700000 { + usb2: usb@700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/src/arm/microchip/sama5d2.dtsi b/src/arm/microchip/sama5d2.dtsi index 3f99451aef8..dc22fb67933 100644 --- a/src/arm/microchip/sama5d2.dtsi +++ b/src/arm/microchip/sama5d2.dtsi @@ -136,7 +136,7 @@ status = "disabled"; }; - usb1: ohci@400000 { + usb1: usb@400000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00400000 0x100000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; @@ -145,7 +145,7 @@ status = "disabled"; }; - usb2: ehci@500000 { + usb2: usb@500000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00500000 0x100000>; interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/src/arm/microchip/sama5d3.dtsi b/src/arm/microchip/sama5d3.dtsi index 70f380c399c..e95799c17fd 100644 --- a/src/arm/microchip/sama5d3.dtsi +++ b/src/arm/microchip/sama5d3.dtsi @@ -1074,7 +1074,7 @@ status = "disabled"; }; - usb1: ohci@600000 { + usb1: usb@600000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; @@ -1083,7 +1083,7 @@ status = "disabled"; }; - usb2: ehci@700000 { + usb2: usb@700000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/src/arm/microchip/sama5d3xmb.dtsi b/src/arm/microchip/sama5d3xmb.dtsi index 3652c9e2412..90da04b84b3 100644 --- a/src/arm/microchip/sama5d3xmb.dtsi +++ b/src/arm/microchip/sama5d3xmb.dtsi @@ -172,7 +172,7 @@ status = "okay"; }; - usb1: ohci@600000 { + usb1: usb@600000 { num-ports = <3>; atmel,vbus-gpio = <&pioD 25 GPIO_ACTIVE_HIGH &pioD 26 GPIO_ACTIVE_LOW @@ -181,7 +181,7 @@ status = "okay"; }; - usb2: ehci@700000 { + usb2: usb@700000 { status = "okay"; }; }; diff --git a/src/arm/microchip/sama5d4.dtsi b/src/arm/microchip/sama5d4.dtsi index 35513262860..59a7d557c7c 100644 --- a/src/arm/microchip/sama5d4.dtsi +++ b/src/arm/microchip/sama5d4.dtsi @@ -119,7 +119,7 @@ status = "disabled"; }; - usb1: ohci@500000 { + usb1: usb@500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00500000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; @@ -128,7 +128,7 @@ status = "disabled"; }; - usb2: ehci@600000 { + usb2: usb@600000 { compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00600000 0x100000>; interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; diff --git a/src/arm/microchip/sama7d65.dtsi b/src/arm/microchip/sama7d65.dtsi index 854b30d15dc..b6710ccd4c3 100644 --- a/src/arm/microchip/sama7d65.dtsi +++ b/src/arm/microchip/sama7d65.dtsi @@ -9,6 +9,7 @@ */ #include +#include #include #include #include @@ -52,6 +53,11 @@ #address-cells = <1>; #size-cells = <1>; + sfrbu: sfr@e0008000 { + compatible ="microchip,sama7d65-sfrbu", "atmel,sama5d2-sfrbu", "syscon"; + reg = <0xe0008000 0x20>; + }; + pioa: pinctrl@e0014000 { compatible = "microchip,sama7d65-pinctrl", "microchip,sama7g5-pinctrl"; reg = <0xe0014000 0x800>; @@ -76,6 +82,31 @@ clock-names = "td_slck", "md_slck", "main_xtal"; }; + ps_wdt: watchdog@e001d000 { + compatible = "microchip,sama7d65-wdt", "microchip,sama7g5-wdt"; + reg = <0xe001d000 0x30>; + interrupts = ; + clocks = <&clk32k 0>; + }; + + reset_controller: reset-controller@e001d100 { + compatible = "microchip,sama7d65-rstc", "microchip,sama7g5-rstc"; + reg = <0xe001d100 0xc>, <0xe001d1e4 0x4>; + #reset-cells = <1>; + clocks = <&clk32k 0>; + }; + + shdwc: poweroff@e001d200 { + compatible = "microchip,sama7d65-shdwc", "microchip,sama7g5-shdwc", "syscon"; + reg = <0xe001d200 0x20>; + clocks = <&clk32k 0>; + #address-cells = <1>; + #size-cells = <0>; + atmel,wakeup-rtc-timer; + atmel,wakeup-rtt-timer; + status = "disabled"; + }; + clk32k: clock-controller@e001d500 { compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; reg = <0xe001d500 0x4>; @@ -83,6 +114,29 @@ #clock-cells = <1>; }; + rtc: rtc@e001d800 { + compatible = "microchip,sama7d65-rtc", "microchip,sam9x60-rtc"; + reg = <0xe001d800 0x30>; + interrupts = ; + clocks = <&clk32k 1>; + }; + + chipid@e0020000 { + compatible = "microchip,sama7d65-chipid"; + reg = <0xe0020000 0x8>; + }; + + dma2: dma-controller@e1200000 { + compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; + reg = <0xe1200000 0x1000>; + interrupts = ; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; + clock-names = "dma_clk"; + dma-requests = <0>; + status = "disabled"; + }; + sdmmc1: mmc@e1208000 { compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; reg = <0xe1208000 0x400>; @@ -95,6 +149,26 @@ status = "disabled"; }; + dma0: dma-controller@e1610000 { + compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; + reg = <0xe1610000 0x1000>; + interrupts = ; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 21>; + clock-names = "dma_clk"; + status = "disabled"; + }; + + dma1: dma-controller@e1614000 { + compatible = "microchip,sama7d65-dma", "microchip,sama7g5-dma"; + reg = <0xe1614000 0x1000>; + interrupts = ; + #dma-cells = <1>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; + clock-names = "dma_clk"; + status = "disabled"; + }; + pit64b0: timer@e1800000 { compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; reg = <0xe1800000 0x100>; @@ -132,6 +206,27 @@ }; }; + flx10: flexcom@e2824000 { + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; + reg = <0xe2824000 0x200>; + ranges = <0x0 0xe2824000 0x800>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + i2c10: i2c@600 { + compatible = "microchip,sama7d65-i2c", "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; + #address-cells = <1>; + #size-cells = <0>; + atmel,fifo-size = <32>; + status = "disabled"; + }; + }; + gic: interrupt-controller@e8c11000 { compatible = "arm,cortex-a7-gic"; reg = <0xe8c11000 0x1000>, diff --git a/src/arm/microchip/tny_a9260.dts b/src/arm/microchip/tny_a9260.dts index ef6d586ce88..f0f2a787d66 100644 --- a/src/arm/microchip/tny_a9260.dts +++ b/src/arm/microchip/tny_a9260.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * tny_a9260.dts - Device Tree file for Caloa TNY A9260 board + * tny_a9260.dts - Device Tree file for Calao TNY A9260 board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD */ diff --git a/src/arm/microchip/tny_a9260_common.dtsi b/src/arm/microchip/tny_a9260_common.dtsi index 70e5635c78e..4d4377f51be 100644 --- a/src/arm/microchip/tny_a9260_common.dtsi +++ b/src/arm/microchip/tny_a9260_common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * tny_a9260_common.dtsi - Device Tree file for Caloa TNY A926x board + * tny_a9260_common.dtsi - Device Tree file for Calao TNY A926x board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD */ diff --git a/src/arm/microchip/tny_a9263.dts b/src/arm/microchip/tny_a9263.dts index 62b7d9f9a92..3dd48b3e06d 100644 --- a/src/arm/microchip/tny_a9263.dts +++ b/src/arm/microchip/tny_a9263.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * usb_a9263.dts - Device Tree file for Caloa USB A9293 board + * usb_a9263.dts - Device Tree file for Calao USB A9293 board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD */ diff --git a/src/arm/microchip/tny_a9g20.dts b/src/arm/microchip/tny_a9g20.dts index 118d766a126..cebd5696a2c 100644 --- a/src/arm/microchip/tny_a9g20.dts +++ b/src/arm/microchip/tny_a9g20.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * tny_a9g20.dts - Device Tree file for Caloa TNY A9G20 board + * tny_a9g20.dts - Device Tree file for Calao TNY A9G20 board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD */ diff --git a/src/arm/microchip/usb_a9260.dts b/src/arm/microchip/usb_a9260.dts index 66f8da89007..e7f7b259ccf 100644 --- a/src/arm/microchip/usb_a9260.dts +++ b/src/arm/microchip/usb_a9260.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * usb_a9260.dts - Device Tree file for Caloa USB A9260 board + * usb_a9260.dts - Device Tree file for Calao USB A9260 board * * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD */ diff --git a/src/arm/microchip/usb_a9260_common.dtsi b/src/arm/microchip/usb_a9260_common.dtsi index 8744b5f6f79..8c3530638c6 100644 --- a/src/arm/microchip/usb_a9260_common.dtsi +++ b/src/arm/microchip/usb_a9260_common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * usb_a926x.dts - Device Tree file for Caloa USB A926x board + * usb_a926x.dts - Device Tree file for Calao USB A926x board * * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD */ @@ -111,7 +111,7 @@ }; }; - usb0: ohci@500000 { + usb0: usb@500000 { num-ports = <2>; status = "okay"; }; @@ -122,17 +122,14 @@ user_led { label = "user_led"; - gpios = <&pioB 21 GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; + gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; }; }; gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - user_pb { + button-user-pb { label = "user_pb"; gpios = <&pioB 10 GPIO_ACTIVE_LOW>; linux,code = <28>; diff --git a/src/arm/microchip/usb_a9263.dts b/src/arm/microchip/usb_a9263.dts index 45745915b2e..60d7936dc56 100644 --- a/src/arm/microchip/usb_a9263.dts +++ b/src/arm/microchip/usb_a9263.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * usb_a9263.dts - Device Tree file for Caloa USB A9293 board + * usb_a9263.dts - Device Tree file for Calao USB A9293 board * * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD */ @@ -9,7 +9,7 @@ / { model = "Calao USB A9263"; - compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9"; + compatible = "calao,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9"; chosen { bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; @@ -139,7 +139,7 @@ }; }; - usb0: ohci@a00000 { + usb0: usb@a00000 { num-ports = <2>; status = "okay"; }; @@ -151,16 +151,13 @@ user_led { label = "user_led"; gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; }; }; gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - user_pb { + button-user-pb { label = "user_pb"; gpios = <&pioB 10 GPIO_ACTIVE_LOW>; linux,code = <28>; diff --git a/src/arm/microchip/usb_a9g20-dab-mmx.dtsi b/src/arm/microchip/usb_a9g20-dab-mmx.dtsi index 08d58081201..5b1d80c0ab2 100644 --- a/src/arm/microchip/usb_a9g20-dab-mmx.dtsi +++ b/src/arm/microchip/usb_a9g20-dab-mmx.dtsi @@ -65,28 +65,26 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - user_pb1 { + button-user-pb1 { label = "user_pb1"; gpios = <&pioB 25 GPIO_ACTIVE_LOW>; linux,code = <0x100>; }; - user_pb2 { + button-user-pb2 { label = "user_pb2"; gpios = <&pioB 13 GPIO_ACTIVE_LOW>; linux,code = <0x101>; }; - user_pb3 { + button-user-pb3 { label = "user_pb3"; gpios = <&pioA 26 GPIO_ACTIVE_LOW>; linux,code = <0x102>; }; - user_pb4 { + button-user-pb4 { label = "user_pb4"; gpios = <&pioC 9 GPIO_ACTIVE_LOW>; linux,code = <0x103>; diff --git a/src/arm/microchip/usb_a9g20.dts b/src/arm/microchip/usb_a9g20.dts index 2f667b083e8..a2f748141d4 100644 --- a/src/arm/microchip/usb_a9g20.dts +++ b/src/arm/microchip/usb_a9g20.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board + * usb_a9g20.dts - Device Tree file for Calao USB A9G20 board * * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD */ diff --git a/src/arm/microchip/usb_a9g20_common.dtsi b/src/arm/microchip/usb_a9g20_common.dtsi index 7d10b36db1e..f1946e0996b 100644 --- a/src/arm/microchip/usb_a9g20_common.dtsi +++ b/src/arm/microchip/usb_a9g20_common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board + * usb_a9g20.dts - Device Tree file for Calao USB A9G20 board * * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD */ diff --git a/src/arm/microchip/usb_a9g20_lpw.dts b/src/arm/microchip/usb_a9g20_lpw.dts index f65712015d4..4d104797176 100644 --- a/src/arm/microchip/usb_a9g20_lpw.dts +++ b/src/arm/microchip/usb_a9g20_lpw.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later /* - * usb_a9g20_lpw.dts - Device Tree file for Caloa USB A9G20 Low Power board + * usb_a9g20_lpw.dts - Device Tree file for Calao USB A9G20 Low Power board * * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD */ @@ -16,7 +16,7 @@ spi1: spi@fffcc000 { cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; status = "okay"; - mmc-slot@0 { + mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; voltage-ranges = <3200 3400>; diff --git a/src/arm/nvidia/tegra114.dtsi b/src/arm/nvidia/tegra114.dtsi index 86f14e2fd29..4caf2073c55 100644 --- a/src/arm/nvidia/tegra114.dtsi +++ b/src/arm/nvidia/tegra114.dtsi @@ -139,7 +139,7 @@ reg = <0x54400000 0x00040000>; clocks = <&tegra_car TEGRA114_CLK_DSIB>, <&tegra_car TEGRA114_CLK_DSIBLP>, - <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; + <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; clock-names = "dsi", "lp", "parent"; resets = <&tegra_car 82>; reset-names = "dsi"; @@ -577,6 +577,21 @@ #iommu-cells = <1>; }; + hda@70030000 { + compatible = "nvidia,tegra114-hda", "nvidia,tegra30-hda"; + reg = <0x70030000 0x10000>; + interrupts = ; + clocks = <&tegra_car TEGRA114_CLK_HDA>, + <&tegra_car TEGRA114_CLK_HDA2HDMI>, + <&tegra_car TEGRA114_CLK_HDA2CODEC_2X>; + clock-names = "hda", "hda2hdmi", "hda2codec_2x"; + resets = <&tegra_car 125>, /* hda */ + <&tegra_car 128>, /* hda2hdmi */ + <&tegra_car 111>; /* hda2codec_2x */ + reset-names = "hda", "hda2hdmi", "hda2codec_2x"; + status = "disabled"; + }; + ahub@70080000 { compatible = "nvidia,tegra114-ahub"; reg = <0x70080000 0x200>, @@ -805,31 +820,40 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <2>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <3>; }; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = diff --git a/src/arm/nvidia/tegra124.dtsi b/src/arm/nvidia/tegra124.dtsi index 8f1fff37346..ec4f0e346b2 100644 --- a/src/arm/nvidia/tegra124.dtsi +++ b/src/arm/nvidia/tegra124.dtsi @@ -165,6 +165,22 @@ status = "disabled"; }; + dsia: dsi@54300000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x0 0x54300000 0x0 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIA>, + <&tegra_car TEGRA124_CLK_DSIALP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 48>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + vic@54340000 { compatible = "nvidia,tegra124-vic"; reg = <0x0 0x54340000 0x0 0x00040000>; @@ -177,6 +193,22 @@ iommus = <&mc TEGRA_SWGROUP_VIC>; }; + dsib: dsi@54400000 { + compatible = "nvidia,tegra124-dsi"; + reg = <0x0 0x54400000 0x0 0x00040000>; + clocks = <&tegra_car TEGRA124_CLK_DSIB>, + <&tegra_car TEGRA124_CLK_DSIBLP>, + <&tegra_car TEGRA124_CLK_PLL_D_OUT0>; + clock-names = "dsi", "lp", "parent"; + resets = <&tegra_car 82>; + reset-names = "dsi"; + nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + sor@54540000 { compatible = "nvidia,tegra124-sor"; reg = <0x0 0x54540000 0x0 0x00040000>; @@ -938,6 +970,14 @@ }; }; + mipi: mipi@700e3000 { + compatible = "nvidia,tegra124-mipi"; + reg = <0x0 0x700e3000 0x0 0x100>; + clocks = <&tegra_car TEGRA124_CLK_MIPI_CAL>; + clock-names = "mipi-cal"; + #nvidia,mipi-calibrate-cells = <1>; + }; + dfll: clock@70110000 { compatible = "nvidia,tegra124-dfll"; reg = <0 0x70110000 0 0x100>, /* DFLL control */ diff --git a/src/arm/nvidia/tegra20-asus-tf101.dts b/src/arm/nvidia/tegra20-asus-tf101.dts index e118809dc6d..67764afeb01 100644 --- a/src/arm/nvidia/tegra20-asus-tf101.dts +++ b/src/arm/nvidia/tegra20-asus-tf101.dts @@ -1085,6 +1085,17 @@ sbs,poll-retry-count = <10>; power-supplies = <&mains>; }; + + /* Dynaimage ambient light sensor */ + light-sensor@1c { + compatible = "dynaimage,al3000a"; + reg = <0x1c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vdd-supply = <&vdd_1v8_sys>; + }; }; }; diff --git a/src/arm/nxp/imx/imx31.dtsi b/src/arm/nxp/imx/imx31.dtsi index 00006c90d9a..813a81558c4 100644 --- a/src/arm/nxp/imx/imx31.dtsi +++ b/src/arm/nxp/imx/imx31.dtsi @@ -340,7 +340,7 @@ #address-cells = <1>; #size-cells = <1>; - nfc: nand@b8000000 { + nfc: nand-controller@b8000000 { compatible = "fsl,imx31-nand", "fsl,imx27-nand"; reg = <0xb8000000 0x1000>; interrupts = <33>; diff --git a/src/arm/nxp/imx/imx50.dtsi b/src/arm/nxp/imx/imx50.dtsi index 1b6f444443d..d76c496b3f7 100644 --- a/src/arm/nxp/imx/imx50.dtsi +++ b/src/arm/nxp/imx/imx50.dtsi @@ -338,7 +338,7 @@ clks: ccm@53fd4000 { compatible = "fsl,imx50-ccm"; reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; + interrupts = <71>, <72>; #clock-cells = <1>; }; diff --git a/src/arm/nxp/imx/imx51.dtsi b/src/arm/nxp/imx/imx51.dtsi index cc88da4d778..8323e3a56a1 100644 --- a/src/arm/nxp/imx/imx51.dtsi +++ b/src/arm/nxp/imx/imx51.dtsi @@ -458,7 +458,7 @@ clks: ccm@73fd4000 { compatible = "fsl,imx51-ccm"; reg = <0x73fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; + interrupts = <71>, <72>; #clock-cells = <1>; }; }; diff --git a/src/arm/nxp/imx/imx53-mba53.dts b/src/arm/nxp/imx/imx53-mba53.dts index c14eb7280f0..3cdb87ac1d7 100644 --- a/src/arm/nxp/imx/imx53-mba53.dts +++ b/src/arm/nxp/imx/imx53-mba53.dts @@ -162,7 +162,7 @@ }; expander: pca9554@20 { - compatible = "pca9554"; + compatible = "nxp,pca9554"; reg = <0x20>; interrupts = <109>; #gpio-cells = <2>; diff --git a/src/arm/nxp/imx/imx53-ppd.dts b/src/arm/nxp/imx/imx53-ppd.dts index e939acc1c88..2892e457fea 100644 --- a/src/arm/nxp/imx/imx53-ppd.dts +++ b/src/arm/nxp/imx/imx53-ppd.dts @@ -593,7 +593,7 @@ touchscreen@4b { compatible = "atmel,maxtouch"; - reset-gpio = <&gpio5 19 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; reg = <0x4b>; interrupt-parent = <&gpio5>; interrupts = <4 IRQ_TYPE_LEVEL_LOW>; diff --git a/src/arm/nxp/imx/imx53.dtsi b/src/arm/nxp/imx/imx53.dtsi index 845e2bf8460..faac7cc249d 100644 --- a/src/arm/nxp/imx/imx53.dtsi +++ b/src/arm/nxp/imx/imx53.dtsi @@ -598,7 +598,7 @@ clks: ccm@53fd4000 { compatible = "fsl,imx53-ccm"; reg = <0x53fd4000 0x4000>; - interrupts = <0 71 0x04 0 72 0x04>; + interrupts = <71>, <72>; #clock-cells = <1>; }; diff --git a/src/arm/nxp/imx/imx6dl-colibri-v1.2-aster.dts b/src/arm/nxp/imx/imx6dl-colibri-v1.2-aster.dts new file mode 100644 index 00000000000..44c78c07f43 --- /dev/null +++ b/src/arm/nxp/imx/imx6dl-colibri-v1.2-aster.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6dl-colibri-aster.dts" +#include "imx6qdl-colibri-v1.2.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Aster Board"; +}; diff --git a/src/arm/nxp/imx/imx6dl-colibri-v1.2-eval-v3.dts b/src/arm/nxp/imx/imx6dl-colibri-v1.2-eval-v3.dts new file mode 100644 index 00000000000..93fd0af53a3 --- /dev/null +++ b/src/arm/nxp/imx/imx6dl-colibri-v1.2-eval-v3.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6dl-colibri-eval-v3.dts" +#include "imx6qdl-colibri-v1.2.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Evaluation Board V3"; +}; diff --git a/src/arm/nxp/imx/imx6dl-colibri-v1.2-iris-v2.dts b/src/arm/nxp/imx/imx6dl-colibri-v1.2-iris-v2.dts new file mode 100644 index 00000000000..92d41fc9a13 --- /dev/null +++ b/src/arm/nxp/imx/imx6dl-colibri-v1.2-iris-v2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6dl-colibri-iris-v2.dts" +#include "imx6qdl-colibri-v1.2.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Iris V2 Board"; +}; diff --git a/src/arm/nxp/imx/imx6dl-colibri-v1.2-iris.dts b/src/arm/nxp/imx/imx6dl-colibri-v1.2-iris.dts new file mode 100644 index 00000000000..c8957948c88 --- /dev/null +++ b/src/arm/nxp/imx/imx6dl-colibri-v1.2-iris.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6dl-colibri-iris.dts" +#include "imx6qdl-colibri-v1.2.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S V1.2+ on Colibri Iris Board"; +}; diff --git a/src/arm/nxp/imx/imx6q-apalis-v1.2-eval-v1.2.dts b/src/arm/nxp/imx/imx6q-apalis-v1.2-eval-v1.2.dts new file mode 100644 index 00000000000..908dab57fd8 --- /dev/null +++ b/src/arm/nxp/imx/imx6q-apalis-v1.2-eval-v1.2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-eval-v1.2.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Apalis Evaluation Board v1.2"; +}; diff --git a/src/arm/nxp/imx/imx6q-apalis-v1.2-eval.dts b/src/arm/nxp/imx/imx6q-apalis-v1.2-eval.dts new file mode 100644 index 00000000000..5463d412738 --- /dev/null +++ b/src/arm/nxp/imx/imx6q-apalis-v1.2-eval.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-eval.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Apalis Evaluation Board"; +}; diff --git a/src/arm/nxp/imx/imx6q-apalis-v1.2-ixora-v1.1.dts b/src/arm/nxp/imx/imx6q-apalis-v1.2-ixora-v1.1.dts new file mode 100644 index 00000000000..84eabf81ba8 --- /dev/null +++ b/src/arm/nxp/imx/imx6q-apalis-v1.2-ixora-v1.1.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-ixora-v1.1.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Ixora Carrier Board V1.1"; +}; diff --git a/src/arm/nxp/imx/imx6q-apalis-v1.2-ixora-v1.2.dts b/src/arm/nxp/imx/imx6q-apalis-v1.2-ixora-v1.2.dts new file mode 100644 index 00000000000..d7cfab4de45 --- /dev/null +++ b/src/arm/nxp/imx/imx6q-apalis-v1.2-ixora-v1.2.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-ixora-v1.2.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Ixora Carrier Board V1.2"; +}; diff --git a/src/arm/nxp/imx/imx6q-apalis-v1.2-ixora.dts b/src/arm/nxp/imx/imx6q-apalis-v1.2-ixora.dts new file mode 100644 index 00000000000..189b074e31c --- /dev/null +++ b/src/arm/nxp/imx/imx6q-apalis-v1.2-ixora.dts @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +/dts-v1/; + +#include "imx6q-apalis-ixora.dts" +#include "imx6qdl-apalis-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module V1.2+ on Ixora Carrier Board"; +}; diff --git a/src/arm/nxp/imx/imx6qdl-apalis-v1.2.dtsi b/src/arm/nxp/imx/imx6qdl-apalis-v1.2.dtsi new file mode 100644 index 00000000000..83fa04fc9f1 --- /dev/null +++ b/src/arm/nxp/imx/imx6qdl-apalis-v1.2.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +&i2c2 { + /delete-node/ stmpe811@41; + + ad7879_ts: touchscreen@2c { + compatible = "adi,ad7879-1"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio4>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; + + tla2024_adc: adc@49 { + compatible = "ti,tla2024"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* Apalis AN1_ADC0 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Apalis AN1_ADC1 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Apalis AN1_ADC2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Apalis AN1_TSWIP_ADC3 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <1>; + }; + }; +}; diff --git a/src/arm/nxp/imx/imx6qdl-apalis.dtsi b/src/arm/nxp/imx/imx6qdl-apalis.dtsi index 88be29166c1..b13000a62a7 100644 --- a/src/arm/nxp/imx/imx6qdl-apalis.dtsi +++ b/src/arm/nxp/imx/imx6qdl-apalis.dtsi @@ -10,7 +10,6 @@ / { model = "Toradex Apalis iMX6Q/D Module"; - compatible = "toradex,apalis_imx6q", "fsl,imx6q"; aliases { mmc0 = &usdhc3; /* eMMC */ @@ -664,7 +663,6 @@ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; - status = "disabled"; }; stmpe_adc: stmpe_adc { diff --git a/src/arm/nxp/imx/imx6qdl-colibri-v1.2.dtsi b/src/arm/nxp/imx/imx6qdl-colibri-v1.2.dtsi new file mode 100644 index 00000000000..d11bf911b72 --- /dev/null +++ b/src/arm/nxp/imx/imx6qdl-colibri-v1.2.dtsi @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) 2025 Toradex */ + +&i2c2 { + /delete-node/ stmpe811@41; + + ad7879_ts: touchscreen@2c { + compatible = "adi,ad7879-1"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio6>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; + + tla2024_adc: adc@49 { + compatible = "ti,tla2024"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* Colibri AIN0 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Colibri AIN1 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Colibri AIN2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <1>; + }; + + /* Colibri AIN3 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <1>; + }; + }; +}; diff --git a/src/arm/nxp/imx/imx6qdl-colibri.dtsi b/src/arm/nxp/imx/imx6qdl-colibri.dtsi index 9f33419c260..3525cbcda57 100644 --- a/src/arm/nxp/imx/imx6qdl-colibri.dtsi +++ b/src/arm/nxp/imx/imx6qdl-colibri.dtsi @@ -10,7 +10,6 @@ / { model = "Toradex Colibri iMX6DL/S Module"; - compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; aliases { mmc0 = &usdhc3; /* eMMC */ @@ -588,7 +587,6 @@ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; - status = "disabled"; }; stmpe_adc: stmpe_adc { diff --git a/src/arm/nxp/imx/imx6qdl-mba6.dtsi b/src/arm/nxp/imx/imx6qdl-mba6.dtsi index 8cefda70db6..ee2c6bec92e 100644 --- a/src/arm/nxp/imx/imx6qdl-mba6.dtsi +++ b/src/arm/nxp/imx/imx6qdl-mba6.dtsi @@ -124,7 +124,7 @@ compatible = "fsl,imx-audio-tlv320aic32x4"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; - model = "imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; ssi-controller = <&ssi1>; audio-codec = <&tlv320aic32x4>; audio-asrc = <&asrc>; diff --git a/src/arm/nxp/imx/imx6qdl-tqma6.dtsi b/src/arm/nxp/imx/imx6qdl-tqma6.dtsi index 6152a9ed476..07492f63a1f 100644 --- a/src/arm/nxp/imx/imx6qdl-tqma6.dtsi +++ b/src/arm/nxp/imx/imx6qdl-tqma6.dtsi @@ -7,16 +7,6 @@ #include #include -/ { - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "supply-3p3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; @@ -25,11 +15,16 @@ m25p80: flash@0 { compatible = "jedec,spi-nor"; - spi-max-frequency = <50000000>; reg = <0>; - #address-cells = <1>; - #size-cells = <1>; + spi-max-frequency = <50000000>; + vcc-supply = <&sw4_reg>; m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; @@ -119,7 +114,7 @@ }; sw4_reg: sw4 { - regulator-min-microvolt = <800000>; + regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; @@ -183,7 +178,7 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - vmmc-supply = <®_3p3v>; + vmmc-supply = <&sw4_reg>; non-removable; disable-wp; no-sd; diff --git a/src/arm/nxp/imx/imx6qdl-tqma6a.dtsi b/src/arm/nxp/imx/imx6qdl-tqma6a.dtsi index 828996382f2..e8fd37dd883 100644 --- a/src/arm/nxp/imx/imx6qdl-tqma6a.dtsi +++ b/src/arm/nxp/imx/imx6qdl-tqma6a.dtsi @@ -30,14 +30,14 @@ temperature-sensor@48 { compatible = "national,lm75a"; reg = <0x48>; - vs-supply = <®_3p3v>; + vs-supply = <&sw4_reg>; }; eeprom@50 { compatible = "st,24c64", "atmel,24c64"; reg = <0x50>; pagesize = <32>; - vcc-supply = <®_3p3v>; + vcc-supply = <&sw4_reg>; }; }; diff --git a/src/arm/nxp/imx/imx6qdl-tqma6b.dtsi b/src/arm/nxp/imx/imx6qdl-tqma6b.dtsi index 1d0966b8d99..0e404c1f62f 100644 --- a/src/arm/nxp/imx/imx6qdl-tqma6b.dtsi +++ b/src/arm/nxp/imx/imx6qdl-tqma6b.dtsi @@ -23,14 +23,14 @@ temperature-sensor@48 { compatible = "national,lm75a"; reg = <0x48>; - vs-supply = <®_3p3v>; + vs-supply = <&sw4_reg>; }; eeprom@50 { compatible = "st,24c64", "atmel,24c64"; reg = <0x50>; pagesize = <32>; - vcc-supply = <®_3p3v>; + vcc-supply = <&sw4_reg>; }; }; diff --git a/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi b/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi index 0e839bbfea0..911ccbd132c 100644 --- a/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/src/arm/nxp/imx/imx6ul-14x14-evk.dtsi @@ -62,6 +62,33 @@ gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + sound-wm8960 { compatible = "fsl,imx-audio-wm8960"; model = "wm8960-audio"; @@ -139,6 +166,11 @@ wlf,gpio-cfg = <1 3>; clocks = <&clks IMX6UL_CLK_SAI2>; clock-names = "mclk"; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; camera@3c { diff --git a/src/arm/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi b/src/arm/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi index f2386dcb9ff..dda4fa91b2f 100644 --- a/src/arm/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi +++ b/src/arm/nxp/imx/imx6ul-imx6ull-opos6ul.dtsi @@ -40,6 +40,9 @@ reg = <1>; interrupt-parent = <&gpio4>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; status = "okay"; }; }; diff --git a/src/arm/nxp/imx/imx6ul-tqma6ul-common.dtsi b/src/arm/nxp/imx/imx6ul-tqma6ul-common.dtsi index c9c0794f01a..2dd635a615c 100644 --- a/src/arm/nxp/imx/imx6ul-tqma6ul-common.dtsi +++ b/src/arm/nxp/imx/imx6ul-tqma6ul-common.dtsi @@ -162,13 +162,18 @@ status = "okay"; flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "jedec,spi-nor"; + reg = <0>; spi-max-frequency = <33000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <1>; - reg = <0>; + vcc-supply = <®_vldo4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; diff --git a/src/arm/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts b/src/arm/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts index f2a5f17f312..2e7b96e7b79 100644 --- a/src/arm/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts +++ b/src/arm/nxp/imx/imx6ul-tqma6ul1-mba6ulx.dts @@ -6,8 +6,9 @@ /dts-v1/; -#include "imx6ul-tqma6ul1.dtsi" +#include "imx6ul-tqma6ul2.dtsi" #include "mba6ulx.dtsi" +#include "imx6ul-tqma6ul1.dtsi" / { model = "TQ-Systems TQMa6UL1 SoM on MBa6ULx board"; diff --git a/src/arm/nxp/imx/imx6ul-tqma6ul1.dtsi b/src/arm/nxp/imx/imx6ul-tqma6ul1.dtsi index 24192d012ef..79c8c552913 100644 --- a/src/arm/nxp/imx/imx6ul-tqma6ul1.dtsi +++ b/src/arm/nxp/imx/imx6ul-tqma6ul1.dtsi @@ -4,8 +4,6 @@ * Author: Markus Niebel */ -#include "imx6ul-tqma6ul2.dtsi" - / { model = "TQ-Systems TQMa6UL1 SoM"; compatible = "tq,imx6ul-tqma6ul1", "fsl,imx6ul"; diff --git a/src/arm/nxp/imx/imx6ul-var-som-concerto.dts b/src/arm/nxp/imx/imx6ul-var-som-concerto.dts new file mode 100644 index 00000000000..9ff3b374a2b --- /dev/null +++ b/src/arm/nxp/imx/imx6ul-var-som-concerto.dts @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-MX6UL + * Variscite SoM mounted on it + * + * Copyright 2019 Variscite Ltd. + * Copyright 2025 Bootlin + */ + +#include "imx6ul-var-som.dtsi" +#include + +/ { + model = "Variscite VAR-SOM-MX6UL Concerto Board"; + compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul"; + + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>; + + key-back { + gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-wakeup { + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + label = "gpled2"; + gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&fec1 { + status = "disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <0>; + micrel,rmii-reference-clock-select-25-mhz = <1>; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + rtc@68 { + /* + * To actually use this interrupt + * connect pins J14.8 & J14.10 on the Concerto-Board. + */ + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iomuxc { + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_enet2_gpio: enet2-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ + >; + }; + + pinctrl_enet2_mdio: enet2-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_gpio_key_back: gpio-key-backgrp { + fsl,pins = < + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059 + >; + }; + + pinctrl_gpio_leds: gpio-ledsgrp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ + >; + }; + + pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1-gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 + >; + }; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&tsc { + /* + * Conflics with wdog1 ext-reset-output & SD CD pins, + * so we keep it disabled by default. + */ + status = "disabled"; +}; + +/* Console UART */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* ttymxc4 UART */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + /* + * To actually use ext-reset-output + * connect pins J17.3 & J17.8 on the Concerto-Board + */ + fsl,ext-reset-output; +}; diff --git a/src/arm/nxp/imx/imx6ul-var-som.dtsi b/src/arm/nxp/imx/imx6ul-var-som.dtsi new file mode 100644 index 00000000000..4e536e0252d --- /dev/null +++ b/src/arm/nxp/imx/imx6ul-var-som.dtsi @@ -0,0 +1,233 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite VAR-SOM-MX6UL Module + * + * Copyright 2019 Variscite Ltd. + * Copyright 2025 Bootlin + */ + +/dts-v1/; + +#include "imx6ul.dtsi" +#include +#include + +/ { + model = "Variscite VAR-SOM-MX6UL module"; + compatible = "variscite,var-som-imx6ul", "fsl,imx6ul"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_gpio_dvfs: reg-gpio-dvfs { + compatible = "regulator-gpio"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 + 1400000 0x0>; + }; + + rmii_ref_clk: rmii-ref-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "rmii-ref"; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&cpu0 { + dc-supply = <®_gpio_dvfs>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <1>; + micrel,rmii-reference-clock-select-25-mhz = <1>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet1_gpio: enet1-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ + >; + }; + + pinctrl_enet1_mdio: enet1-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */ + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; +}; + +&pxp { + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/src/arm/nxp/imx/imx7-mba7.dtsi b/src/arm/nxp/imx/imx7-mba7.dtsi index 576a7df505d..4d948a9757f 100644 --- a/src/arm/nxp/imx/imx7-mba7.dtsi +++ b/src/arm/nxp/imx/imx7-mba7.dtsi @@ -170,7 +170,7 @@ sound { compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; ssi-controller = <&sai1>; audio-codec = <&tlv320aic32x4>; audio-routing = diff --git a/src/arm/nxp/imx/imx7-tqma7.dtsi b/src/arm/nxp/imx/imx7-tqma7.dtsi index aa8f65cd4ad..2966a33bc52 100644 --- a/src/arm/nxp/imx/imx7-tqma7.dtsi +++ b/src/arm/nxp/imx/imx7-tqma7.dtsi @@ -265,6 +265,13 @@ spi-max-frequency = <29000000>; spi-rx-bus-width = <4>; spi-tx-bus-width = <4>; + vcc-supply = <&vgen4_reg>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; diff --git a/src/arm/nxp/imx/imx7d-sdb.dts b/src/arm/nxp/imx/imx7d-sdb.dts index 6cde8463690..17236f90ab3 100644 --- a/src/arm/nxp/imx/imx7d-sdb.dts +++ b/src/arm/nxp/imx/imx7d-sdb.dts @@ -143,6 +143,33 @@ gpio = <&gpio1 4 GPIO_ACTIVE_LOW>; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000 0>; @@ -406,6 +433,11 @@ <&clks IMX7D_AUDIO_MCLK_ROOT_DIV>; assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; assigned-clock-rates = <0>, <884736000>, <12288000>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; diff --git a/src/arm/nxp/imx/imx7s.dtsi b/src/arm/nxp/imx/imx7s.dtsi index 22dd72499ef..2629968001a 100644 --- a/src/arm/nxp/imx/imx7s.dtsi +++ b/src/arm/nxp/imx/imx7s.dtsi @@ -176,6 +176,34 @@ ; }; + video_mux: csi-mux { + compatible = "video-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + csi_mux_from_mipi_vc0: endpoint { + remote-endpoint = <&mipi_vc0_to_csi_mux>; + }; + }; + + port@2 { + reg = <2>; + + csi_mux_to_csi: endpoint { + remote-endpoint = <&csi_from_csi_mux>; + }; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; @@ -529,34 +557,6 @@ #mux-control-cells = <1>; mux-reg-masks = <0x14 0x00000010>; }; - - video_mux: csi-mux { - compatible = "video-mux"; - mux-controls = <&mux 0>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - - csi_mux_from_mipi_vc0: endpoint { - remote-endpoint = <&mipi_vc0_to_csi_mux>; - }; - }; - - port@2 { - reg = <2>; - - csi_mux_to_csi: endpoint { - remote-endpoint = <&csi_from_csi_mux>; - }; - }; - }; }; ocotp: efuse@30350000 { diff --git a/src/arm/nxp/imx/mba6ulx.dtsi b/src/arm/nxp/imx/mba6ulx.dtsi index 941d9860218..67a3d484bc9 100644 --- a/src/arm/nxp/imx/mba6ulx.dtsi +++ b/src/arm/nxp/imx/mba6ulx.dtsi @@ -142,7 +142,7 @@ sound { compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; ssi-controller = <&sai1>; audio-codec = <&tlv320aic32x4>; audio-asrc = <&asrc>; diff --git a/src/arm/nxp/mxs/imx28-btt3-0.dts b/src/arm/nxp/mxs/imx28-btt3-0.dts new file mode 100644 index 00000000000..6ac46e4b21b --- /dev/null +++ b/src/arm/nxp/mxs/imx28-btt3-0.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28-btt3.dtsi" + +&hog_pins_rev { + fsl,pull-up = ; +}; diff --git a/src/arm/nxp/mxs/imx28-btt3-1.dts b/src/arm/nxp/mxs/imx28-btt3-1.dts new file mode 100644 index 00000000000..213fe931c58 --- /dev/null +++ b/src/arm/nxp/mxs/imx28-btt3-1.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28-btt3.dtsi" diff --git a/src/arm/nxp/mxs/imx28-btt3-2.dts b/src/arm/nxp/mxs/imx28-btt3-2.dts new file mode 100644 index 00000000000..4bccd784d06 --- /dev/null +++ b/src/arm/nxp/mxs/imx28-btt3-2.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/dts-v1/; +#include "imx28-btt3.dtsi" + +/ { + panel { + compatible = "powertip,st7272", "panel-dpi"; + power-supply = <®_3v3>; + width-mm = <70>; + height-mm = <52>; + + panel-timing { + clock-frequency = <6500000>; + hactive = <320>; + vactive = <240>; + hfront-porch = <20>; + hback-porch = <68>; + hsync-len = <30>; + vfront-porch = <4>; + vback-porch = <14>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; diff --git a/src/arm/nxp/mxs/imx28-btt3.dtsi b/src/arm/nxp/mxs/imx28-btt3.dtsi new file mode 100644 index 00000000000..2c52e67e5c1 --- /dev/null +++ b/src/arm/nxp/mxs/imx28-btt3.dtsi @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ +/dts-v1/; +#include "imx28-lwe.dtsi" + +/ { + model = "BTT3"; + + compatible = "lwn,imx28-btt3", "fsl,imx28"; + + chosen { + bootargs = "root=/dev/mmcblk0p2 rootfstype=ext4 ro rootwait console=ttyAMA0,115200 panic=1 quiet"; + }; + + memory@40000000 { + reg = <0x40000000 0x10000000>; + device_type = "memory"; + }; + + panel { + compatible = "powertip,hx8238a", "panel-dpi"; + power-supply = <®_3v3>; + width-mm = <70>; + height-mm = <52>; + + panel-timing { + clock-frequency = <6500000>; + hactive = <320>; + vactive = <240>; + hfront-porch = <20>; + hback-porch = <38>; + hsync-len = <30>; + vfront-porch = <4>; + vback-porch = <14>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <1>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; + + poweroff { + compatible = "gpio-poweroff"; + gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "BTTC Audio"; + simple-audio-card,widgets = "Speaker", "BTTC Speaker"; + simple-audio-card,routing = "BTTC Speaker", "SPKOUTN", "BTTC Speaker", "SPKOUTP"; + + simple-audio-card,dai-link@0 { + format = "left_j"; + bitclock-master = <&dai0_master>; + frame-master = <&dai0_master>; + mclk-fs = <256>; + + dai0_master: cpu { + sound-dai = <&saif0>; + }; + + codec { + sound-dai = <&wm89xx>; + clocks = <&saif0>; + }; + }; + }; + + wifi_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_en_pin_bttc>; + reset-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; + /* W1-163 needs 60us for WL_EN to be low and */ + /* 150ms after high before downloading FW is possible */ + post-power-on-delay-ms = <200>; + power-off-delay-us = <100>; + }; +}; + +&auart0 { + pinctrl-names = "default"; + pinctrl-0 = <&auart0_2pins_a>; + status = "okay"; +}; + +&auart3 { + pinctrl-names = "default"; + pinctrl-0 = <&auart3_pins_a>; + uart-has-rtscts; + status = "okay"; +}; + +&i2c0 { + wm89xx: audio-codec@1a { + compatible = "wlf,wm8940"; + reg = <0x1a>; + #sound-dai-cells = <0>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a>, <&lcdif_sync_pins_bttc>, + <&lcdif_reset_pins_bttc>; + status = "okay"; + + port { + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; +}; + +&mac0 { + clocks = <&clks 57>, <&clks 57>, <&clks 64>; + clock-names = "ipg", "ahb", "enet_out"; + phy-handle = <&mac0_phy>; + phy-mode = "rmii"; + phy-supply = <®_3v3>; + /* + * This MAC address is adjusted during production. + * Value specified below is used as a fallback during recovery. + */ + local-mac-address = [ 00 11 B8 00 BF 8A ]; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mac0_phy: ethernet-phy@0 { + /* LAN8720Ai - PHY ID */ + compatible = "ethernet-phy-id0007.c0f0","ethernet-phy-ieee802.3-c22"; + reg = <0>; + smsc,disable-energy-detect; + max-speed = <100>; + reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + reset-assert-us = <1000>; + reset-deassert-us = <1000>; + }; + }; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>, <&hog_pins_rev>; + + hog_pins_a: hog@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY2__GPIO_0_22 + MX28_PAD_GPMI_RDY3__GPIO_0_23 + MX28_PAD_GPMI_RDN__GPIO_0_24 + MX28_PAD_LCD_VSYNC__GPIO_1_28 + MX28_PAD_SSP2_SS1__GPIO_2_20 + MX28_PAD_SSP2_SS2__GPIO_2_21 + MX28_PAD_AUART2_CTS__GPIO_3_10 + MX28_PAD_AUART2_RTS__GPIO_3_11 + MX28_PAD_GPMI_WRN__GPIO_0_25 + MX28_PAD_ENET0_RXD2__GPIO_4_9 + MX28_PAD_ENET0_TXD2__GPIO_4_11 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + hog_pins_rev: hog@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_ENET0_RXD3__GPIO_4_10 + MX28_PAD_ENET0_TX_CLK__GPIO_4_5 + MX28_PAD_ENET0_COL__GPIO_4_14 + MX28_PAD_ENET0_CRS__GPIO_4_15 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + keypad_pins_bttc: keypad-bttc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__GPIO_0_0 + MX28_PAD_AUART0_CTS__GPIO_3_2 + MX28_PAD_AUART0_RTS__GPIO_3_3 + MX28_PAD_GPMI_D03__GPIO_0_3 + MX28_PAD_GPMI_D04__GPIO_0_4 + MX28_PAD_GPMI_D05__GPIO_0_5 + MX28_PAD_GPMI_D06__GPIO_0_6 + MX28_PAD_GPMI_D07__GPIO_0_7 + MX28_PAD_GPMI_CE1N__GPIO_0_17 + MX28_PAD_GPMI_CE2N__GPIO_0_18 + MX28_PAD_GPMI_CE3N__GPIO_0_19 + MX28_PAD_GPMI_RDY0__GPIO_0_20 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_sync_pins_bttc: lcdif-bttc@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK + MX28_PAD_LCD_ENABLE__LCD_ENABLE + MX28_PAD_LCD_HSYNC__LCD_HSYNC + MX28_PAD_LCD_RD_E__LCD_VSYNC + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + lcdif_reset_pins_bttc: lcdif-bttc@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_LCD_RESET__GPIO_3_30 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + ssp1_sdio_pins_a: ssp1-sdio@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_SSP1_DATA0__SSP1_D0 + MX28_PAD_GPMI_D01__SSP1_D1 + MX28_PAD_GPMI_D02__SSP1_D2 + MX28_PAD_SSP1_DATA3__SSP1_D3 + MX28_PAD_SSP1_CMD__SSP1_CMD + MX28_PAD_SSP1_SCK__SSP1_SCK + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; + + wifi_en_pin_bttc: wifi-en-pin@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_CLE__GPIO_0_27 + >; + fsl,drive-strength = ; + fsl,voltage = ; + fsl,pull-up = ; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pins_a>; + status = "okay"; +}; + +®_usb_5v { + gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; +}; + +&saif0 { + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + #sound-dai-cells = <0>; + assigned-clocks = <&clks 53>; + assigned-clock-rates = <12000000>; + status = "okay"; +}; + +&saif1 { + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + #sound-dai-cells = <0>; + fsl,saif-master = <&saif0>; + status = "okay"; +}; + +&ssp1 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&ssp1_sdio_pins_a>; + bus-width = <4>; + no-1-8-v; /* force 3.3V VIO */ + non-removable; + vmmc-supply = <®_3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + keep-power-in-suspend; + status = "okay"; + + wlan@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&ssp2 { + compatible = "fsl,imx28-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_a>; + status = "okay"; +}; diff --git a/src/arm/nxp/mxs/imx28-sps1.dts b/src/arm/nxp/mxs/imx28-sps1.dts index 0f01dded4e3..ca62e793311 100644 --- a/src/arm/nxp/mxs/imx28-sps1.dts +++ b/src/arm/nxp/mxs/imx28-sps1.dts @@ -24,30 +24,25 @@ }; leds { - #address-cells = <1>; - #size-cells = <0>; compatible = "gpio-leds"; status = "okay"; - led@1 { + led-1 { label = "sps1-1:yellow:user"; gpios = <&gpio0 6 0>; linux,default-trigger = "heartbeat"; - reg = <0>; }; - led@2 { + led-2 { label = "sps1-2:red:user"; gpios = <&gpio0 3 0>; linux,default-trigger = "heartbeat"; - reg = <1>; }; - led@3 { + led-3 { label = "sps1-3:red:user"; gpios = <&gpio0 0 0>; - default-trigger = "heartbeat"; - reg = <2>; + linux,default-trigger = "heartbeat"; }; }; diff --git a/src/arm/nxp/vf/vf610-bk4.dts b/src/arm/nxp/vf/vf610-bk4.dts index 722182f5fd1..2492fb99956 100644 --- a/src/arm/nxp/vf/vf610-bk4.dts +++ b/src/arm/nxp/vf/vf610-bk4.dts @@ -119,7 +119,7 @@ status = "okay"; spidev0@0 { - compatible = "lwn,bk4"; + compatible = "lwn,bk4-spi"; spi-max-frequency = <30000000>; reg = <0>; fsl,spi-cs-sck-delay = <200>; @@ -136,7 +136,7 @@ #address-cells = <0>; slave { - compatible = "lwn,bk4"; + compatible = "lwn,bk4-spi"; spi-max-frequency = <30000000>; }; }; diff --git a/src/arm/nxp/vf/vf610-colibri.dtsi b/src/arm/nxp/vf/vf610-colibri.dtsi index 607cec2df86..20aed394621 100644 --- a/src/arm/nxp/vf/vf610-colibri.dtsi +++ b/src/arm/nxp/vf/vf610-colibri.dtsi @@ -8,7 +8,6 @@ / { model = "Toradex Colibri VF61 COM"; - compatible = "toradex,vf610-colibri_vf61", "fsl,vf610"; memory@80000000 { device_type = "memory"; diff --git a/src/arm/nxp/vf/vf610-zii-dev-rev-c.dts b/src/arm/nxp/vf/vf610-zii-dev-rev-c.dts index 6f9878f124c..4f99044837f 100644 --- a/src/arm/nxp/vf/vf610-zii-dev-rev-c.dts +++ b/src/arm/nxp/vf/vf610-zii-dev-rev-c.dts @@ -392,7 +392,7 @@ }; &gpio0 { - eth0_intrp { + eth0-intrp-hog { gpio-hog; gpios = <23 GPIO_ACTIVE_HIGH>; input; @@ -401,7 +401,7 @@ }; &gpio3 { - eth0_intrp { + eth0-intrp-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; input; diff --git a/src/arm/nxp/vf/vfxxx.dtsi b/src/arm/nxp/vf/vfxxx.dtsi index acccf9a3c89..597f20be82f 100644 --- a/src/arm/nxp/vf/vfxxx.dtsi +++ b/src/arm/nxp/vf/vfxxx.dtsi @@ -158,8 +158,8 @@ clocks = <&clks VF610_CLK_DSPI0>; clock-names = "dspi"; spi-num-chipselects = <6>; - dmas = <&edma1 1 12>, <&edma1 1 13>; - dma-names = "rx", "tx"; + dmas = <&edma1 1 13>, <&edma1 1 12>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -172,8 +172,8 @@ clocks = <&clks VF610_CLK_DSPI1>; clock-names = "dspi"; spi-num-chipselects = <4>; - dmas = <&edma1 1 14>, <&edma1 1 15>; - dma-names = "rx", "tx"; + dmas = <&edma1 1 15>, <&edma1 1 14>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -529,9 +529,8 @@ clocks = <&clks VF610_CLK_DSPI2>; clock-names = "dspi"; spi-num-chipselects = <2>; - dmas = <&edma1 0 10>, - <&edma1 0 11>; - dma-names = "rx", "tx"; + dmas = <&edma1 0 11>, <&edma1 0 10>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -544,8 +543,8 @@ clocks = <&clks VF610_CLK_DSPI3>; clock-names = "dspi"; spi-num-chipselects = <2>; - dmas = <&edma1 0 12>, <&edma1 0 13>; - dma-names = "rx", "tx"; + dmas = <&edma1 0 13>, <&edma1 0 12>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -725,13 +724,13 @@ clocks = <&clks VF610_CLK_CAAM>; clock-names = "ipg"; - sec_jr0: jr0@1000 { + sec_jr0: jr@1000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x1000 0x1000>; interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; }; - sec_jr1: jr1@2000 { + sec_jr1: jr@2000 { compatible = "fsl,sec-v4.0-job-ring"; reg = <0x2000 0x1000>; interrupts = <102 IRQ_TYPE_LEVEL_HIGH>; diff --git a/src/arm/renesas/r8a7790-lager.dts b/src/arm/renesas/r8a7790-lager.dts index 3bce5876a9d..4f002aa7fba 100644 --- a/src/arm/renesas/r8a7790-lager.dts +++ b/src/arm/renesas/r8a7790-lager.dts @@ -754,6 +754,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm/renesas/r8a7790-stout.dts b/src/arm/renesas/r8a7790-stout.dts index d7c0a9574ce..b1e20579e07 100644 --- a/src/arm/renesas/r8a7790-stout.dts +++ b/src/arm/renesas/r8a7790-stout.dts @@ -268,6 +268,7 @@ &scifa0 { pinctrl-0 = <&scifa0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm/renesas/r8a7790.dtsi b/src/arm/renesas/r8a7790.dtsi index f746f0b9e68..4f97c09dbc9 100644 --- a/src/arm/renesas/r8a7790.dtsi +++ b/src/arm/renesas/r8a7790.dtsi @@ -227,6 +227,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -265,6 +266,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -374,6 +376,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7790"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; tpu: pwm@e60f0000 { @@ -395,6 +398,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6151000 { @@ -412,6 +416,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7790-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1948,6 +1953,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -2018,5 +2024,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/src/arm/renesas/r8a7791-koelsch.dts b/src/arm/renesas/r8a7791-koelsch.dts index e4e1d9c98c6..e9f90fa44d5 100644 --- a/src/arm/renesas/r8a7791-koelsch.dts +++ b/src/arm/renesas/r8a7791-koelsch.dts @@ -679,6 +679,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm/renesas/r8a7791-porter.dts b/src/arm/renesas/r8a7791-porter.dts index 08381498350..f518eadd8b9 100644 --- a/src/arm/renesas/r8a7791-porter.dts +++ b/src/arm/renesas/r8a7791-porter.dts @@ -312,6 +312,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm/renesas/r8a7791.dtsi b/src/arm/renesas/r8a7791.dtsi index e57567adff5..5023b41c28b 100644 --- a/src/arm/renesas/r8a7791.dtsi +++ b/src/arm/renesas/r8a7791.dtsi @@ -125,6 +125,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -152,6 +153,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -291,6 +293,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7791"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; tpu: pwm@e60f0000 { @@ -312,6 +315,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -323,6 +327,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7791-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1875,6 +1880,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1945,5 +1951,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/src/arm/renesas/r8a7792-blanche.dts b/src/arm/renesas/r8a7792-blanche.dts index a3986076d8e..23ec0f8a665 100644 --- a/src/arm/renesas/r8a7792-blanche.dts +++ b/src/arm/renesas/r8a7792-blanche.dts @@ -301,6 +301,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm/renesas/r8a7792-wheat.dts b/src/arm/renesas/r8a7792-wheat.dts index bfc780f7e39..93bd81723c8 100644 --- a/src/arm/renesas/r8a7792-wheat.dts +++ b/src/arm/renesas/r8a7792-wheat.dts @@ -183,6 +183,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm/renesas/r8a7792.dtsi b/src/arm/renesas/r8a7792.dtsi index 08cbe6c13ce..7513afc1c95 100644 --- a/src/arm/renesas/r8a7792.dtsi +++ b/src/arm/renesas/r8a7792.dtsi @@ -82,6 +82,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; lbsc: bus { @@ -109,6 +110,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -308,6 +310,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7792"; reg = <0 0xe6060000 0 0x144>; + bootph-all; }; cpg: clock-controller@e6150000 { @@ -318,6 +321,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -329,6 +333,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7792-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -947,6 +952,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { diff --git a/src/arm/renesas/r8a7793-gose.dts b/src/arm/renesas/r8a7793-gose.dts index 2c05d7c2b37..45b267ec267 100644 --- a/src/arm/renesas/r8a7793-gose.dts +++ b/src/arm/renesas/r8a7793-gose.dts @@ -642,6 +642,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm/renesas/r8a7793.dtsi b/src/arm/renesas/r8a7793.dtsi index e48e43cc6b0..fc6d3bcca29 100644 --- a/src/arm/renesas/r8a7793.dtsi +++ b/src/arm/renesas/r8a7793.dtsi @@ -117,6 +117,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; pmu { @@ -137,6 +138,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -276,6 +278,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7793"; reg = <0 0xe6060000 0 0x250>; + bootph-all; }; /* Special CPG clocks */ @@ -287,6 +290,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6152000 { @@ -298,6 +302,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7793-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1454,6 +1459,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1524,5 +1530,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/src/arm/renesas/r8a7794-alt.dts b/src/arm/renesas/r8a7794-alt.dts index f70e26aa83a..3f06a7f67d6 100644 --- a/src/arm/renesas/r8a7794-alt.dts +++ b/src/arm/renesas/r8a7794-alt.dts @@ -479,6 +479,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm/renesas/r8a7794-silk.dts b/src/arm/renesas/r8a7794-silk.dts index 2a0819311a3..34282560576 100644 --- a/src/arm/renesas/r8a7794-silk.dts +++ b/src/arm/renesas/r8a7794-silk.dts @@ -394,6 +394,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm/renesas/r8a7794.dtsi b/src/arm/renesas/r8a7794.dtsi index bc16c896c0f..92010d09f6c 100644 --- a/src/arm/renesas/r8a7794.dtsi +++ b/src/arm/renesas/r8a7794.dtsi @@ -99,6 +99,7 @@ #clock-cells = <0>; /* This value must be overridden by the board. */ clock-frequency = <0>; + bootph-all; }; pmu { @@ -119,6 +120,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -243,6 +245,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7794"; reg = <0 0xe6060000 0 0x11c>; + bootph-all; }; cpg: clock-controller@e6150000 { @@ -253,6 +256,7 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; apmu@e6151000 { @@ -264,6 +268,7 @@ rst: reset-controller@e6160000 { compatible = "renesas,r8a7794-rst"; reg = <0 0xe6160000 0 0x0100>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1440,6 +1445,7 @@ prr: chipid@ff000044 { compatible = "renesas,prr"; reg = <0 0xff000044 0 4>; + bootph-all; }; cmt0: timer@ffca0000 { @@ -1491,5 +1497,6 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <48000000>; + bootph-all; }; }; diff --git a/src/arm/renesas/r9a06g032.dtsi b/src/arm/renesas/r9a06g032.dtsi index 7548291c8d7..87e03446fb4 100644 --- a/src/arm/renesas/r9a06g032.dtsi +++ b/src/arm/renesas/r9a06g032.dtsi @@ -211,8 +211,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 1 0 0 0 1 1>, <&dmamux 0 0 0 0 0 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -224,8 +224,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 3 0 0 0 3 1>, <&dmamux 2 0 0 0 2 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -237,8 +237,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 5 0 0 0 5 1>, <&dmamux 4 0 0 0 4 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -250,8 +250,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 7 0 0 0 7 1>, <&dmamux 6 0 0 0 6 1>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -263,8 +263,8 @@ reg-io-width = <4>; clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; clock-names = "baudclk", "apb_pclk"; - dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>; - dma-names = "rx", "tx"; + dmas = <&dmamux 5 0 0 0 21 1>, <&dmamux 4 0 0 0 20 1>; + dma-names = "tx", "rx"; status = "disabled"; }; diff --git a/src/arm/st/stm32f746-disco.dts b/src/arm/st/stm32f746-disco.dts index 087de6f0962..b57dbdce2f4 100644 --- a/src/arm/st/stm32f746-disco.dts +++ b/src/arm/st/stm32f746-disco.dts @@ -78,6 +78,24 @@ serial0 = &usart1; }; + leds { + compatible = "gpio-leds"; + led-usr { + gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + button-0 { + label = "User"; + linux,code = ; + gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>; + }; + }; + usbotg_hs_phy: usb-phy { #phy-cells = <0>; compatible = "usb-nop-xceiv"; diff --git a/src/arm/st/stm32f769-disco.dts b/src/arm/st/stm32f769-disco.dts index 52c5baf58ab..535cfdc4681 100644 --- a/src/arm/st/stm32f769-disco.dts +++ b/src/arm/st/stm32f769-disco.dts @@ -79,13 +79,16 @@ leds { compatible = "gpio-leds"; - led-green { + led-usr2 { gpios = <&gpioj 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - led-red { + led-usr1 { gpios = <&gpioj 13 GPIO_ACTIVE_HIGH>; }; + led-usr3 { + gpios = <&gpioa 12 GPIO_ACTIVE_HIGH>; + }; }; gpio-keys { diff --git a/src/arm/st/stm32mp131.dtsi b/src/arm/st/stm32mp131.dtsi index 0019d12c3d3..8512a6e46b3 100644 --- a/src/arm/st/stm32mp131.dtsi +++ b/src/arm/st/stm32mp131.dtsi @@ -100,6 +100,31 @@ always-on; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&dts>; + + trips { + cpu_alert1: cpu-alert1 { + temperature = <85000>; + hysteresis = <0>; + type = "passive"; + }; + + cpu-crit { + temperature = <120000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + }; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -919,6 +944,16 @@ }; }; + dts: thermal@50028000 { + compatible = "st,stm32-thermal"; + reg = <0x50028000 0x100>; + interrupts = ; + clocks = <&rcc DTS>; + clock-names = "pclk"; + #thermal-sensor-cells = <0>; + status = "disabled"; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; diff --git a/src/arm/st/stm32mp133c-prihmb.dts b/src/arm/st/stm32mp133c-prihmb.dts new file mode 100644 index 00000000000..663b6de1b81 --- /dev/null +++ b/src/arm/st/stm32mp133c-prihmb.dts @@ -0,0 +1,496 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/dts-v1/; + +#include +#include +#include +#include +#include "stm32mp133.dtsi" +#include "stm32mp13xc.dtsi" +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "Priva E-Measuringbox board"; + compatible = "pri,prihmb", "st,stm32mp133"; + + aliases { + ethernet0 = ðernet1; + mdio-gpio0 = &mdio0; + mmc0 = &sdmmc1; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &usart6; + serial2 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + counter-0 { + compatible = "interrupt-counter"; + gpios = <&gpioa 11 GPIO_ACTIVE_HIGH>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + button-reset { + label = "reset-button"; + linux,code = ; + gpios = <&gpioi 7 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + led-controller-0 { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + max-brightness = <255>; + + led-red { + active-low; + color = ; + pwms = <&pwm2 2 1000000 1>; + }; + + led-green { + active-low; + color = ; + pwms = <&pwm1 1 1000000 1>; + }; + + led-blue { + active-low; + color = ; + pwms = <&pwm1 2 1000000 1>; + }; + }; + }; + + led-controller-1 { + compatible = "pwm-leds-multicolor"; + + multi-led { + color = ; + function = LED_FUNCTION_STATUS; + max-brightness = <255>; + + led-red { + active-low; + color = ; + pwms = <&pwm1 0 1000000 1>; + }; + + led-green { + active-low; + color = ; + pwms = <&pwm2 0 1000000 1>; + }; + + led-blue { + active-low; + color = ; + pwms = <&pwm2 1 1000000 1>; + }; + }; + }; + + /* DP83TD510E PHYs have max MDC rate of 1.75MHz. Since we can't reduce + * stmmac MDC clock without reducing system bus rate, we need to use + * gpio based MDIO bus. + */ + mdio0: mdio { + compatible = "virtual,mdio-gpio"; + #address-cells = <1>; + #size-cells = <0>; + gpios = <&gpiog 2 GPIO_ACTIVE_HIGH + &gpioa 2 GPIO_ACTIVE_HIGH>; + + /* TI DP83TD510E */ + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id2000.0181"; + reg = <0>; + interrupts-extended = <&gpioa 4 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioa 3 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x10000000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@ce000000 { + reg = <0xce000000 0x02000000>; + no-map; + }; + }; +}; + +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc_1_pins_a>; + vdda-supply = <®_3v3>; + vref-supply = <®_3v3>; + status = "okay"; +}; + +&adc1 { + status = "okay"; + + channel@0 { /* Fan current PC0*/ + reg = <0>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; + channel@11 { /* Fan voltage */ + reg = <11>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; + channel@15 { /* Supply voltage */ + reg = <15>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; +}; + +&dts { + status = "okay"; +}; + +ðernet1 { + status = "okay"; + pinctrl-0 = <ðernet1_rmii_pins_a>; + pinctrl-1 = <ðernet1_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + phy-handle = <&phy0>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + clock-frequency = <100000>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + board-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + vs-supply = <®_3v3>; + }; +}; + +&{i2c1_pins_a/pins} { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; +}; + +&{i2c1_sleep_pins_a/pins} { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +/* SD card without Card-detect */ +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +/* EMMC */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + non-removable; + no-sd; + no-sdio; + no-1-8-v; + st,neg-edge; + mmc-ddr-3_3v; + bus-width = <8>; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&timers1 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pwm1: pwm { + pinctrl-0 = <&pwm1_pins_a>; + pinctrl-1 = <&pwm1_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +&timers4 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pwm2: pwm { + pinctrl-0 = <&pwm4_pins_a>; + pinctrl-1 = <&pwm4_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +/* Fan PWM */ +&timers5 { + status = "okay"; + + pwm3: pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +&timers2 { + status = "okay"; + + timer@1 { + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_pins_a>; + pinctrl-1 = <&uart7_sleep_pins_a>; + pinctrl-2 = <&uart7_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart6 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart6_pins_a>; + pinctrl-1 = <&usart6_sleep_pins_a>; + pinctrl-2 = <&usart6_idle_pins_a>; + linux,rs485-enabled-at-boot-time; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&pinctrl { + adc_1_pins_a: adc1-0 { + pins { + pinmux = , /* ADC1 in0 */ + , /* ADC1 in15 */ + ; /* ADC1 in11 */ + }; + }; + + ethernet1_rmii_pins_a: rmii-0 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + ; /* ETH1_RMII_REF_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + ; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet1_rmii_sleep_pins_a: rmii-sleep-0 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; + }; + + pwm1_pins_a: pwm1-0 { + pins { + pinmux = , /* TIM1_CH1 */ + , /* TIM1_CH2 */ + ; /* TIM1_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_a: pwm1-sleep-0 { + pins { + pinmux = , /* TIM1_CH1 */ + , /* TIM1_CH2 */ + ; /* TIM1_CH3 */ + }; + }; + + pwm4_pins_a: pwm4-0 { + pins { + pinmux = , /* TIM4_CH1 */ + , /* TIM4_CH2 */ + ; /* TIM4_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux = , /* TIM4_CH1 */ + , /* TIM4_CH2 */ + ; /* TIM4_CH3 */ + }; + }; + pwm5_pins_a: pwm5-0 { + pins { + pinmux = ; /* TIM5_CH1 */ + }; + }; + + pwm5_sleep_pins_a: pwm5-sleep-0 { + pins { + pinmux = ; /* TIM5_CH1 */ + }; + }; + + uart7_pins_a: uart7-0 { + pins1 { + pinmux = ; /* UART_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART7_RX */ + bias-pull-up; + }; + }; + + uart7_idle_pins_a: uart7-idle-0 { + pins1 { + pinmux = ; /* UART7_TX */ + }; + pins2 { + pinmux = ; /* UART7_RX */ + bias-pull-up; + }; + }; + + uart7_sleep_pins_a: uart7-sleep-0 { + pins { + pinmux = , /* UART7_TX */ + ; /* UART7_RX */ + }; + }; + + usart6_pins_a: usart6-0 { + pins1 { + pinmux = , /* USART6_TX */ + ; /* USART6_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART6_RX */ + bias-disable; + }; + }; + + usart6_idle_pins_a: usart6-idle-0 { + pins1 { + pinmux = ; /* USART6_TX */ + }; + pins2 { + pinmux = ; /* USART6_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART6_RX */ + bias-disable; + }; + }; + + usart6_sleep_pins_a: usart6-sleep-0 { + pins { + pinmux = , /* USART6_TX */ + , /* USART6_DE */ + ; /* USART6_RX */ + }; + }; +}; diff --git a/src/arm/st/stm32mp135f-dhcor-dhsbc.dts b/src/arm/st/stm32mp135f-dhcor-dhsbc.dts index 853dc21449d..9902849ed04 100644 --- a/src/arm/st/stm32mp135f-dhcor-dhsbc.dts +++ b/src/arm/st/stm32mp135f-dhcor-dhsbc.dts @@ -176,7 +176,7 @@ gpio-line-names = "", "", "", "", "", "DHSBC_USB_PWR_CC1", "", "", "", "", "", "DHSBC_nETH1_RST", - "", "DHCOR_HW-CODING_0", "", ""; + "", "DHCOR_HW-CODING_0", "", "DHSBC_HW-CODE_2"; }; &gpiob { @@ -197,7 +197,7 @@ gpio-line-names = "", "", "", "", "", "DHCOR_RAM-CODING_0", "", "", "", "DHCOR_RAM-CODING_1", "", "", - "", "", "", ""; + "", "DHSBC_HW-CODE_1", "", ""; }; &gpioe { @@ -221,6 +221,13 @@ "DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB"; }; +&gpioh { + gpio-line-names = "", "", "", "DHSBC_HW-CODE_0", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + &gpioi { gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1", "DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT", @@ -296,6 +303,9 @@ st33htph: tpm@0 { compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; reg = <0>; + interrupt-parent = <&gpioe>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioe 12 GPIO_ACTIVE_LOW>; spi-max-frequency = <24000000>; }; }; @@ -419,3 +429,19 @@ type = "micro"; }; }; + +/* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ +&vdd_ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; + +/* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */ +&vdd_sd { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; +}; diff --git a/src/arm/st/stm32mp15-pinctrl.dtsi b/src/arm/st/stm32mp15-pinctrl.dtsi index 95fafc51a1c..40605ea85ee 100644 --- a/src/arm/st/stm32mp15-pinctrl.dtsi +++ b/src/arm/st/stm32mp15-pinctrl.dtsi @@ -25,6 +25,13 @@ }; }; + /omit-if-no-ref/ + adc1_in10_pins_a: adc1-in10-0 { + pins { + pinmux = ; + }; + }; + /omit-if-no-ref/ adc12_ain_pins_a: adc12-ain-0 { pins { @@ -584,6 +591,43 @@ }; }; + /omit-if-no-ref/ + ethernet0_rmii_pins_d: rmii-3 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_REF_CLK */ + , /* ETH1_MDIO */ + ; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + ; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + ethernet0_rmii_sleep_pins_d: rmii-sleep-3 { + pins1 { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_MDIO */ + , /* ETH1_MDC */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; + }; + /omit-if-no-ref/ fmc_pins_a: fmc-0 { pins1 { @@ -725,6 +769,25 @@ }; }; + /omit-if-no-ref/ + i2c1_pins_c: i2c1-2 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + i2c1_sleep_pins_c: i2c1-sleep-2 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { pins { @@ -819,6 +882,27 @@ }; }; + /omit-if-no-ref/ + i2s1_pins_a: i2s1-0 { + pins { + pinmux = , /* I2S2_SDI */ + , /* I2S2_WS */ + ; /* I2S2_CK */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + /omit-if-no-ref/ + i2s1_sleep_pins_a: i2s1-sleep-0 { + pins { + pinmux = , /* I2S2_SDI */ + , /* I2S2_WS */ + ; /* I2S2_CK */ + }; + }; + /omit-if-no-ref/ i2s2_pins_a: i2s2-0 { pins { @@ -1418,6 +1502,23 @@ }; }; + /omit-if-no-ref/ + pwm1_pins_d: pwm1-3 { + pins { + pinmux = ; /* TIM5_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + pwm1_sleep_pins_d: pwm1-sleep-3 { + pins { + pinmux = ; + }; + }; + /omit-if-no-ref/ pwm2_pins_a: pwm2-0 { pins { @@ -2160,6 +2261,66 @@ }; }; + /omit-if-no-ref/ + sdmmc2_b4_pins_c: sdmmc2-b4-2 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_od_pins_c: sdmmc2-b4-od-2 { + pins1 { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = ; /* SDMMC2_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + + pins3 { + pinmux = ; /* SDMMC2_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_sleep_pins_c: sdmmc2-b4-sleep-2 { + pins { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + /omit-if-no-ref/ sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { @@ -2389,6 +2550,66 @@ }; }; + /omit-if-no-ref/ + sdmmc3_b4_pins_c: sdmmc3-b4-2 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_od_pins_c: sdmmc3-b4-od-2 { + pins1 { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + ; /* SDMMC3_D3 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux = ; /* SDMMC3_CK */ + slew-rate = <2>; + drive-push-pull; + bias-pull-up; + }; + + pins3 { + pinmux = ; /* SDMMC3_CMD */ + slew-rate = <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_sleep_pins_c: sdmmc3-b4-sleep-2 { + pins { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CK */ + ; /* SDMMC3_CMD */ + }; + }; + /omit-if-no-ref/ spdifrx_pins_a: spdifrx-0 { pins { @@ -2600,6 +2821,41 @@ }; }; + /omit-if-no-ref/ + uart4_pins_e: uart4-4 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_idle_pins_e: uart4-idle-4 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_sleep_pins_e: uart4-sleep-4 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + /omit-if-no-ref/ uart5_pins_a: uart5-0 { pins1 { @@ -2677,6 +2933,23 @@ }; }; + /omit-if-no-ref/ + uart7_pins_d: uart7-3 { + pins1 { + pinmux = , /* UART7_TX */ + ; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + + pins2 { + pinmux = , /* UART7_RX */ + ; /* UART7_CTS */ + bias-disable; + }; + }; + /omit-if-no-ref/ uart8_pins_a: uart8-0 { pins1 { @@ -3118,6 +3391,25 @@ }; }; + /omit-if-no-ref/ + i2c6_pins_b: i2c6-1 { + pins { + pinmux = , /* I2C6_SCL */ + ; /* I2C6_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + i2c6_sleep_pins_b: i2c6-sleep-1 { + pins { + pinmux = , /* I2C6_SCL */ + ; /* I2C6_SDA */ + }; + }; + /omit-if-no-ref/ spi1_pins_a: spi1-0 { pins1 { diff --git a/src/arm/st/stm32mp151.dtsi b/src/arm/st/stm32mp151.dtsi index b9a87fbe971..0daa8ffe2ff 100644 --- a/src/arm/st/stm32mp151.dtsi +++ b/src/arm/st/stm32mp151.dtsi @@ -1781,7 +1781,6 @@ st,syscon = <&syscfg 0x4>; snps,mixed-burst; snps,pbl = <2>; - snps,en-tx-lpi-clockgating; snps,axi-config = <&stmmac_axi_config_0>; snps,tso; access-controllers = <&etzpc 94>; diff --git a/src/arm/st/stm32mp151c-plyaqm.dts b/src/arm/st/stm32mp151c-plyaqm.dts new file mode 100644 index 00000000000..39a3211c613 --- /dev/null +++ b/src/arm/st/stm32mp151c-plyaqm.dts @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "Plymovent AQM board"; + compatible = "ply,plyaqm", "st,stm32mp151"; + + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + serial1 = &uart7; + }; + + codec { + compatible = "invensense,ics43432"; + + port { + codec_endpoint: endpoint { + remote-endpoint = <&i2s1_endpoint>; + dai-format = "i2s"; + }; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + gpios = <&gpioa 3 GPIO_ACTIVE_HIGH>; /* WHITE_EN */ + color = ; + default-state = "on"; + }; + }; + + v3v3: fixed-regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + v5v_sw: fixed-regulator-v5sw { + compatible = "regulator-fixed"; + regulator-name = "5v-switched"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpioe 10 GPIO_ACTIVE_HIGH>; /* 5V_SWITCHED_EN */ + startup-delay-us = <100000>; + enable-active-high; + regulator-boot-on; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@cfd00000 { + reg = <0xcfd00000 0x300000>; + no-map; + }; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP15"; + dais = <&i2s1_port>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpioe 12 GPIO_ACTIVE_LOW>; /* WLAN_REG_ON */ + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_in10_pins_a>; + vdda-supply = <&v3v3>; + vref-supply = <&v3v3>; + status = "okay"; + + adc@0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + channel@10 { /* NTC */ + reg = <10>; + st,min-sample-time-ns = <10000>; /* 10µs sampling time */ + }; + }; +}; + +&cpu0 { + clocks = <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks = <&scmi_clk CK_SCMI_CRYP1>; + resets = <&scmi_reset RST_SCMI_CRYP1>; + status = "okay"; +}; + +ðernet0 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rmii_pins_d>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_d>; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + /* KSZ8081RNA PHY */ + ethphy0: ethernet-phy@0 { + reg = <0>; + interrupts-extended = <&gpiob 0 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiob 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&gpioa { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "HWID_PL_N", "HWID_CP", ""; +}; + +&gpiob { + gpio-line-names = + "", "", "", "", "", "", "LED_LATCH", "", + "", "RELAY1_EN", "", "", "", "", "", ""; +}; + +&gpioc { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "HWID_Q7", "", ""; +}; + +&gpioe { + gpio-line-names = + "", "", "", "", "RELAY2_EN", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpiog { + gpio-line-names = + "", "", "", "", "", "", "", "SW1", + "", "", "", "", "", "", "", ""; +}; + +&gpioz { + clocks = <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks = <&scmi_clk CK_SCMI_HASH1>; + resets = <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_c>; + pinctrl-1 = <&i2c1_sleep_pins_c>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + clocks = <&scmi_clk CK_SCMI_I2C4>; + resets = <&scmi_reset RST_SCMI_I2C4>; +}; + +&i2c6 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c6_pins_b>; + pinctrl-1 = <&i2c6_sleep_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + clocks = <&scmi_clk CK_SCMI_I2C6>; + resets = <&scmi_reset RST_SCMI_I2C6>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pressure-sensor@47 { + compatible = "bosch,bmp580"; + reg = <0x47>; + vdda-supply = <&v5v_sw>; + vddd-supply = <&v5v_sw>; + }; + + co2-sensor@62 { + compatible = "sensirion,scd41"; + reg = <0x62>; + vdd-supply = <&v5v_sw>; + }; + + pm-sensor@69 { + compatible = "sensirion,sps30"; + reg = <0x69>; + }; +}; + +&i2s1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2s1_pins_a>; + pinctrl-1 = <&i2s1_sleep_pins_a>; + clocks = <&rcc SPI1>, <&rcc SPI1_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "i2sclk", "x8k", "x11k"; + #clock-cells = <0>; /* Set I2S2 as master clock provider */ + status = "okay"; + + i2s1_port: port { + i2s1_endpoint: endpoint { + format = "i2s"; + mclk-fs = <256>; + remote-endpoint = <&codec_endpoint>; + }; + }; +}; + +&iwdg2 { + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; + status = "okay"; +}; + +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets = <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; +}; + +&mdma1 { + resets = <&scmi_reset RST_SCMI_MDMA>; +}; + +&rcc { + compatible = "st,stm32mp1-rcc-secure", "syscon"; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks = <&scmi_clk CK_SCMI_RNG1>; + resets = <&scmi_reset RST_SCMI_RNG1>; + status = "okay"; +}; + +&rtc { + clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +/* SD card without Card-detect */ +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +/* EMMC */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_c &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_c &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_c &sdmmc2_d47_sleep_pins_b>; + non-removable; + no-sd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +/* Wifi */ +&sdmmc3 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_c>; + pinctrl-1 = <&sdmmc3_b4_od_pins_c>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_c>; + non-removable; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + mmc-pwrseq = <&wifi_pwrseq>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + }; +}; + +&timers5 { + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pwm { + pinctrl-0 = <&pwm1_pins_d>; + pinctrl-1 = <&pwm1_sleep_pins_d>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_e>; + pinctrl-1 = <&uart4_idle_pins_e>; + pinctrl-2 = <&uart4_sleep_pins_e>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_d>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + shutdown-gpios = <&gpioe 11 GPIO_ACTIVE_HIGH>; /* BT_REG_ON */ + max-speed = <4000000>; + vbat-supply = <&v3v3>; + vddio-supply = <&v3v3>; + interrupt-parent = <&gpiog>; + interrupts = <12 IRQ_TYPE_EDGE_RISING>; /* BT_HOST_WAKE */ + interrupt-names = "host-wakeup"; + }; +}; diff --git a/src/arm/st/stm32mp153c-lxa-fairytux2-gen1.dts b/src/arm/st/stm32mp153c-lxa-fairytux2-gen1.dts new file mode 100644 index 00000000000..3a0e8426242 --- /dev/null +++ b/src/arm/st/stm32mp153c-lxa-fairytux2-gen1.dts @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2024 Leonard Göhrs, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp153c-lxa-fairytux2.dtsi" + +/ { + model = "Linux Automation GmbH FairyTux 2 Gen 1"; + compatible = "lxa,stm32mp153c-fairytux2-gen1", "oct,stm32mp153x-osd32", "st,stm32mp153"; + + gpio-keys { + compatible = "gpio-keys"; + + button-left { + label = "USER_BTN1"; + linux,code = ; + gpios = <&gpioi 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-right { + label = "USER_BTN2"; + linux,code = ; + gpios = <&gpioe 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; +}; + +&gpiof { + gpio-line-names = "GPIO1", "GPIO2", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioh { + gpio-line-names = "", "", "", "", "LCD_RESET", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "GPIO3", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioi { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "ETH_", "", /* 5 */ + "", "USER_BTN1"; /* 10 */ +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + status = "okay"; + + io_board_gpio: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <&v3v3_hdmi>; + gpio-line-names = "LED1_GA_YK", "LED2_GA_YK", "LED1_GK_YA", "LED2_GK_YA", + "RS485_EN", "RS485_120R", "", "CAN_120R"; + }; +}; + +&led_controller_io { + /* + * led-2 and led-3 are internally connected antiparallel to one + * another inside the ethernet jack like this: + * GPIO1 ---+---|led-2|>--+--- GPIO3 + * +--<|led-3|---+ + * E.g. only one of the LEDs can be illuminated at a time while + * the other output must be driven low. + * This should likely be implemented using a multi color LED + * driver for antiparallel LEDs. + */ + led-2 { + color = ; + function = LED_FUNCTION_ACTIVITY; + gpios = <&io_board_gpio 1 GPIO_ACTIVE_HIGH>; + }; + + led-3 { + color = ; + function = LED_FUNCTION_ACTIVITY; + gpios = <&io_board_gpio 3 GPIO_ACTIVE_HIGH>; + }; +}; + +&usart3 { + /* + * On Gen 1 FairyTux 2 only RTS can be used and not CTS as well, + * Because pins PD11 (CTS) and PI11 (USER_BTN1) share the same + * interrupt and only one of them can be used at a time. + */ + rts-gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; +}; + +&usbotg_hs { + dr_mode = "peripheral"; +}; diff --git a/src/arm/st/stm32mp153c-lxa-fairytux2-gen2.dts b/src/arm/st/stm32mp153c-lxa-fairytux2-gen2.dts new file mode 100644 index 00000000000..66e6da91250 --- /dev/null +++ b/src/arm/st/stm32mp153c-lxa-fairytux2-gen2.dts @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2024 Leonard Göhrs, Pengutronix + */ + +/dts-v1/; + +#include "stm32mp153c-lxa-fairytux2.dtsi" + +/ { + model = "Linux Automation GmbH FairyTux 2 Gen 2"; + compatible = "lxa,stm32mp153c-fairytux2-gen2", "oct,stm32mp153x-osd32", "st,stm32mp153"; + + gpio-keys { + compatible = "gpio-keys"; + + button-left { + label = "USER_BTN1"; + linux,code = ; + gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + + button-right { + label = "USER_BTN2"; + linux,code = ; + gpios = <&gpioe 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; + }; +}; + +&gpiof { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioh { + gpio-line-names = "", "", "", "", "LCD_RESET", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "GPIO1", "GPIO_INT", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioi { + gpio-line-names = "GPIO2", "", "", "", "", /* 0 */ + "", "", "", "ETH_", "", /* 5 */ + "", "USER_BTN1"; /* 10 */ +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_b>; + pinctrl-1 = <&i2c1_sleep_pins_b>; + status = "okay"; + + io_board_gpio: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpioh>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + pinctrl-names = "default"; + pinctrl-0 = <&board_tca6408_pins>; + #interrupt-cells = <2>; + vcc-supply = <&v3v3_hdmi>; + gpio-line-names = "LED1_GA_YK", "LED2_GA_YK", "LED1_GK_YA", "USB_CC_ALERT", + "RS485_EN", "RS485_120R", "USB_CC_RESET", "CAN_120R"; + }; + + usb_c: typec@28 { + compatible = "st,stusb1600"; + reg = <0x28>; + interrupt-parent = <&io_board_gpio>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <®_5v>; + vsys-supply = <&v3v3_hdmi>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + typec-power-opmode = "default"; + + port { + con_usbotg_hs_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; + + temperature-sensor@48 { + compatible = "national,lm75a"; + reg = <0x48>; + /* + * The sensor itself is powered by a voltage divider from the + * always-on 5V supply. + * The required pull-up resistors however are on v3v3_hdmi. + */ + vs-supply = <&v3v3_hdmi>; + }; + + io_board_eeprom: eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + vcc-supply = <&v3v3_hdmi>; + }; +}; + +&rtc { + status = "okay"; +}; + +&led_controller_io { + led-2 { + color = ; + function = LED_FUNCTION_ACTIVITY; + gpios = <&io_board_gpio 1 GPIO_ACTIVE_LOW>; + }; +}; + +&usart3 { + rts-gpios = <&gpiod 12 GPIO_ACTIVE_LOW>; + cts-gpios = <&gpiod 11 GPIO_ACTIVE_LOW>; +}; + +&usbotg_hs { + usb-role-switch; + + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usbotg_hs_ep>; + }; + }; +}; + +&pinctrl { + board_tca6408_pins: stusb1600-0 { + pins { + pinmux = ; + bias-pull-up; + }; + }; +}; diff --git a/src/arm/st/stm32mp153c-lxa-fairytux2.dtsi b/src/arm/st/stm32mp153c-lxa-fairytux2.dtsi new file mode 100644 index 00000000000..9eeb9d6b5eb --- /dev/null +++ b/src/arm/st/stm32mp153c-lxa-fairytux2.dtsi @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) 2020 STMicroelectronics - All Rights Reserved + * Copyright (C) 2021 Rouven Czerwinski, Pengutronix + * Copyright (C) 2023, 2024 Leonard Göhrs, Pengutronix + */ + +#include "stm32mp153.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-osd32.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" + +#include +#include +#include +#include + +/ { + aliases { + can0 = &m_can1; + ethernet0 = ðernet0; + i2c0 = &i2c1; + i2c1 = &i2c4; + mmc1 = &sdmmc2; + serial0 = &uart4; + serial1 = &usart3; + spi0 = &spi4; + }; + + chosen { + stdout-path = &uart4; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&v3v3>; + + brightness-levels = <0 31 63 95 127 159 191 223 255>; + default-brightness-level = <7>; + pwms = <&led_pwm 3 1000000 0>; + }; + + led-controller-cpu { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + led_controller_io: led-controller-io { + compatible = "gpio-leds"; + + /* + * led-0 and led-1 are internally connected antiparallel to one + * another inside the ethernet jack like this: + * GPIO0 ---+---|led-0|>--+--- GPIO2 + * +--<|led-1|---+ + * E.g. only one of the LEDs can be illuminated at a time while + * the other output must be driven low. + * This should likely be implemented using a multi color LED + * driver for antiparallel LEDs. + */ + led-0 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&io_board_gpio 0 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&io_board_gpio 2 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_1v2: regulator-1v2 { + compatible = "regulator-fixed"; + regulator-name = "1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + vin-supply = <®_5v>; + }; +}; + +baseboard_eeprom: &sip_eeprom { +}; + +&crc1 { + status = "okay"; +}; + +&cryp1 { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +ðernet0 { + assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF */ + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ðernet0_rgmii_pins_b>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_b>; + + st,eth-clk-sel; + phy-mode = "rgmii-id"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@3 { /* KSZ9031RN */ + reg = <3>; + reset-gpios = <&gpioe 11 GPIO_ACTIVE_LOW>; /* ETH_RST# */ + interrupt-parent = <&gpioa>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */ + reset-assert-us = <10000>; + reset-deassert-us = <300>; + micrel,force-master; + }; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "ETH_INT", "", "", "", /* 5 */ + "", "", "", "BOOTROM_LED", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiob { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioc { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", ""; /* 10 */ +}; + +&gpiod { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "LCD_TE", "", "", /* 5 */ + "LCD_DC", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioe { + gpio-line-names = "LCD_CS", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiof { + gpio-line-names = "GPIO1", "GPIO2", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpiog { + gpio-line-names = "", "", "", "", "", /* 0 */ + "", "", "", "", "", /* 5 */ + "", "", "", "", "", /* 10 */ + ""; /* 15 */ +}; + +&gpioz { + gpio-line-names = "HWID0", "HWID1", "HWID2", "HWID3", "", /* 0 */ + "", "HWID4", "HWID5"; /* 5 */ +}; + +&hash1 { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <8>; + status = "okay"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_b>; + pinctrl-1 = <&m_can1_sleep_pins_b>; + status = "okay"; + termination-gpios = <&io_board_gpio 7 GPIO_ACTIVE_HIGH>; + termination-ohms = <120>; +}; + +&pmic { + regulators { + buck1-supply = <®_5v>; /* VIN */ + buck2-supply = <®_5v>; /* VIN */ + buck3-supply = <®_5v>; /* VIN */ + buck4-supply = <®_5v>; /* VIN */ + ldo2-supply = <®_5v>; /* PMIC_LDO25IN */ + ldo4-supply = <®_5v>; /* VIN */ + ldo5-supply = <®_5v>; /* PMIC_LDO25IN */ + vref_ddr-supply = <®_5v>; /* VIN */ + boost-supply = <®_5v>; /* PMIC_BSTIN */ + pwr_sw2-supply = <&bst_out>; /* PMIC_SWIN */ + }; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + vmmc-supply = <&v3v3>; + + bus-width = <8>; + mmc-ddr-3_3v; + no-1-8-v; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + + status = "okay"; +}; + +&spi4 { + pinctrl-names = "default"; + pinctrl-0 = <&spi4_pins_a>; + cs-gpios = <&gpioe 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + lcd: display@0 { + compatible = "shineworld,lh133k", "panel-mipi-dbi-spi"; + reg = <0>; + power-supply = <&v3v3>; + io-supply = <&v3v3>; + backlight = <&backlight>; + dc-gpios = <&gpiod 10 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpioh 4 GPIO_ACTIVE_HIGH>; + spi-3wire; + spi-max-frequency = <32000000>; + + width-mm = <23>; + height-mm = <23>; + rotation = <180>; + + panel-timing { + hactive = <240>; + vactive = <240>; + hback-porch = <0>; + vback-porch = <0>; + + clock-frequency = <0>; + hfront-porch = <0>; + hsync-len = <0>; + vfront-porch = <0>; + vsync-len = <0>; + }; + }; +}; + +&timers2 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@1 { + status = "okay"; + }; +}; + +&timers3 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@2 { + status = "okay"; + }; +}; + +&timers4 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + timer@3 { + status = "okay"; + }; +}; + +&timers8 { + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; + + led_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm8_pins_b>; + pinctrl-1 = <&pwm8_sleep_pins_b>; + status = "okay"; + }; +}; + +&uart4 { + label = "debug"; + + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; +}; + +&usart3 { + label = "external"; + + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + phy-names = "usb"; + + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + + vusb_d-supply = <&vdd_usb>; + vusb_a-supply = <®18>; + + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; + +&v3v3_hdmi { + regulator-enable-ramp-delay = <1000>; +}; diff --git a/src/arm/st/stm32mp157c-dk2.dts b/src/arm/st/stm32mp157c-dk2.dts index 5f9c0160a9c..324f7bb988d 100644 --- a/src/arm/st/stm32mp157c-dk2.dts +++ b/src/arm/st/stm32mp157c-dk2.dts @@ -67,7 +67,7 @@ touchscreen@38 { compatible = "focaltech,ft6236"; reg = <0x38>; - interrupts = <2 2>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; interrupt-parent = <&gpiof>; touchscreen-size-x = <480>; touchscreen-size-y = <800>; diff --git a/src/arm/ti/davinci/da850-lego-ev3.dts b/src/arm/ti/davinci/da850-lego-ev3.dts index 4df10379ff2..173401c58d5 100644 --- a/src/arm/ti/davinci/da850-lego-ev3.dts +++ b/src/arm/ti/davinci/da850-lego-ev3.dts @@ -412,14 +412,14 @@ status = "okay"; /* Don't pull down battery voltage adc io channel */ - batt_volt_en { + batt-volt-en-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; output-high; }; /* Don't impede Bluetooth clock signal */ - bt_clock_en { + bt-clock-en-hog { gpio-hog; gpios = <5 GPIO_ACTIVE_HIGH>; input; @@ -433,19 +433,19 @@ * anything, but they are present in the source code from LEGO. */ - bt_pic_en { + bt-pic-en-hog { gpio-hog; gpios = <51 GPIO_ACTIVE_HIGH>; output-low; }; - bt_pic_rst { + bt-pic-rst-hog { gpio-hog; gpios = <78 GPIO_ACTIVE_HIGH>; output-high; }; - bt_pic_cts { + bt-pic-cts-hog { gpio-hog; gpios = <87 GPIO_ACTIVE_HIGH>; input; diff --git a/src/arm/ti/omap/omap3-evm-processor-common.dtsi b/src/arm/ti/omap/omap3-evm-processor-common.dtsi index e27837093e4..70e33cdd519 100644 --- a/src/arm/ti/omap/omap3-evm-processor-common.dtsi +++ b/src/arm/ti/omap/omap3-evm-processor-common.dtsi @@ -205,7 +205,7 @@ /* T2_GPIO_2 low to route GPIO_61 to on-board devices */ &twl_gpio { - en_on_board_gpio_61 { + en-on-board-gpio-61-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_HIGH>; output-low; diff --git a/src/arm/ti/omap/omap4-l4.dtsi b/src/arm/ti/omap/omap4-l4.dtsi index 3fcef3080ea..150dd84c9e0 100644 --- a/src/arm/ti/omap/omap4-l4.dtsi +++ b/src/arm/ti/omap/omap4-l4.dtsi @@ -1414,7 +1414,7 @@ uart3: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; - interrupts = ; + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; }; }; @@ -1765,7 +1765,7 @@ uart1: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; - interrupts = ; + interrupts-extended = <&wakeupgen GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; }; }; @@ -1794,7 +1794,7 @@ uart2: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; - interrupts = ; + interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; }; }; @@ -1823,7 +1823,7 @@ uart4: serial@0 { compatible = "ti,omap4-uart"; reg = <0x0 0x100>; - interrupts = ; + interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <48000000>; }; }; diff --git a/src/arm/ti/omap/omap4-panda-a4.dts b/src/arm/ti/omap/omap4-panda-a4.dts index 8fd076e5d1b..4b8bfd0188a 100644 --- a/src/arm/ti/omap/omap4-panda-a4.dts +++ b/src/arm/ti/omap/omap4-panda-a4.dts @@ -7,6 +7,11 @@ #include "omap443x.dtsi" #include "omap4-panda-common.dtsi" +/ { + model = "TI OMAP4 PandaBoard (A4)"; + compatible = "ti,omap4-panda-a4", "ti,omap4-panda", "ti,omap4430", "ti,omap4"; +}; + /* Pandaboard Rev A4+ have external pullups on SCL & SDA */ &dss_hdmi_pins { pinctrl-single,pins = < diff --git a/src/arm/xilinx/zynq-7000.dtsi b/src/arm/xilinx/zynq-7000.dtsi index a7db3f3009f..153b8d93cbe 100644 --- a/src/arm/xilinx/zynq-7000.dtsi +++ b/src/arm/xilinx/zynq-7000.dtsi @@ -8,6 +8,13 @@ #size-cells = <1>; compatible = "xlnx,zynq-7000"; + options { + u-boot { + compatible = "u-boot,config"; + bootscr-address = /bits/ 64 <0x3000000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -34,7 +41,7 @@ }; }; - fpga_full: fpga-full { + fpga_full: fpga-region { compatible = "fpga-region"; fpga-mgr = <&devcfg>; #address-cells = <1>; @@ -93,6 +100,7 @@ }; amba: axi { + bootph-all; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; @@ -190,6 +198,17 @@ reg = <0xf8006000 0x1000>; }; + ocm: sram@fffc0000 { + compatible = "mmio-sram"; + reg = <0xfffc0000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffc0000 0x10000>; + ocm-sram@0 { + reg = <0x0 0x10000>; + }; + }; + uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; @@ -277,13 +296,18 @@ 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ #address-cells = <2>; #size-cells = <1>; + interrupt-parent = <&intc>; + interrupts = <0 18 4>; nfc0: nand-controller@0,0 { compatible = "arm,pl353-nand-r2p1"; reg = <0 0 0x1000000>; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; + }; + nor0: flash@1,0 { + status = "disabled"; + compatible = "cfi-flash"; + reg = <1 0 0x2000000>; }; }; @@ -308,12 +332,14 @@ }; slcr: slcr@f8000000 { + bootph-all; #address-cells = <1>; #size-cells = <1>; compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; reg = <0xF8000000 0x1000>; ranges; clkc: clkc@100 { + bootph-all; #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; fclk-enable = <0>; @@ -398,6 +424,7 @@ }; scutimer: timer@f8f00600 { + bootph-all; interrupt-parent = <&intc>; interrupts = <1 13 0x301>; compatible = "arm,cortex-a9-twd-timer"; diff --git a/src/arm/xilinx/zynq-cc108.dts b/src/arm/xilinx/zynq-cc108.dts index 8b9ab9bba23..f5525c04842 100644 --- a/src/arm/xilinx/zynq-cc108.dts +++ b/src/arm/xilinx/zynq-cc108.dts @@ -18,6 +18,7 @@ aliases { ethernet0 = &gem0; serial0 = &uart0; + spi0 = &qspi; }; chosen { @@ -48,7 +49,44 @@ ethernet_phy: ethernet-phy@1 { reg = <1>; - device_type = "ethernet-phy"; + }; +}; + +&qspi { + status = "okay"; + num-cs = <1>; + flash@0 { /* 16 MB */ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot-bs"; + reg = <0x0 0x400000>; /* 4MB */ + }; + partition@400000 { + label = "qspi-linux"; + reg = <0x400000 0x400000>; /* 4MB */ + }; + partition@800000 { + label = "qspi-rootfs"; + reg = <0x800000 0x400000>; /* 4MB */ + }; + partition@c00000 { + label = "qspi-devicetree"; + reg = <0xc00000 0x100000>; /* 1MB */ + }; + partition@d00000 { + label = "qspi-scratch"; + reg = <0xd00000 0x200000>; /* 2MB */ + }; + partition@f00000 { + label = "qspi-uboot-env"; + reg = <0xf00000 0x100000>; /* 1MB */ + }; }; }; @@ -59,6 +97,7 @@ }; &uart0 { + bootph-all; status = "okay"; }; diff --git a/src/arm/xilinx/zynq-ebaz4205.dts b/src/arm/xilinx/zynq-ebaz4205.dts index 53fa6dbfd8f..14f644156a6 100644 --- a/src/arm/xilinx/zynq-ebaz4205.dts +++ b/src/arm/xilinx/zynq-ebaz4205.dts @@ -51,6 +51,8 @@ &nfc0 { status = "okay"; + #address-cells = <1>; + #size-cells = <0>; nand@0 { reg = <0>; }; diff --git a/src/arm/xilinx/zynq-microzed.dts b/src/arm/xilinx/zynq-microzed.dts index 6ed84fb1590..68b867e8369 100644 --- a/src/arm/xilinx/zynq-microzed.dts +++ b/src/arm/xilinx/zynq-microzed.dts @@ -11,8 +11,9 @@ compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; aliases { - ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; + mmc0 = &sdhci0; }; memory@0 { @@ -35,6 +36,11 @@ ps-clk-frequency = <33333333>; }; +&qspi { + bootph-all; + status = "okay"; +}; + &gem0 { status = "okay"; phy-mode = "rgmii-id"; @@ -46,10 +52,12 @@ }; &sdhci0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/src/arm/xilinx/zynq-parallella.dts b/src/arm/xilinx/zynq-parallella.dts index 54592aeb92b..366af4fcf8d 100644 --- a/src/arm/xilinx/zynq-parallella.dts +++ b/src/arm/xilinx/zynq-parallella.dts @@ -46,7 +46,6 @@ compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c22"; reg = <0>; - device_type = "ethernet-phy"; marvell,reg-init = <0x3 0x10 0xff00 0x1e>, <0x3 0x11 0xfff0 0xa>; }; diff --git a/src/arm/xilinx/zynq-zc702.dts b/src/arm/xilinx/zynq-zc702.dts index 6efdbca9d3e..6955637c5b1 100644 --- a/src/arm/xilinx/zynq-zc702.dts +++ b/src/arm/xilinx/zynq-zc702.dts @@ -15,7 +15,10 @@ ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; mmc0 = &sdhci0; + nvmem0 = &eeprom; + rtc0 = &rtc; }; memory@0 { @@ -63,19 +66,6 @@ }; }; -&amba { - ocm: sram@fffc0000 { - compatible = "mmio-sram"; - reg = <0xfffc0000 0x10000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xfffc0000 0x10000>; - ocm-sram@0 { - reg = <0x0 0x10000>; - }; - }; -}; - &can0 { status = "okay"; pinctrl-names = "default"; @@ -95,7 +85,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; @@ -152,7 +141,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - eeprom@54 { + eeprom: eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; @@ -174,7 +163,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - rtc@51 { + rtc: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; @@ -210,7 +199,7 @@ conf { groups = "can0_9_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -233,7 +222,7 @@ conf { groups = "ethernet0_0_grp"; slew-rate = <0>; - io-standard = <4>; + power-source = <4>; }; conf-rx { @@ -256,7 +245,7 @@ conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; bias-disable; }; }; @@ -274,7 +263,7 @@ "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp", "gpio0_13_grp", "gpio0_14_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-pull-up { @@ -298,11 +287,11 @@ groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; - pinctrl_i2c0_gpio: i2c0-gpio { + pinctrl_i2c0_gpio: i2c0-gpio-grp { mux { groups = "gpio0_50_grp", "gpio0_51_grp"; function = "gpio0"; @@ -311,7 +300,7 @@ conf { groups = "gpio0_50_grp", "gpio0_51_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; @@ -324,7 +313,7 @@ conf { groups = "sdio0_2_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; bias-disable; }; @@ -338,7 +327,7 @@ bias-high-impedance; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; mux-wp { @@ -351,7 +340,7 @@ bias-high-impedance; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; @@ -364,7 +353,7 @@ conf { groups = "uart1_10_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -387,7 +376,7 @@ conf { groups = "usb0_0_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -403,13 +392,53 @@ }; }; +&qspi { + bootph-all; + status = "okay"; + num-cs = <1>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; + }; +}; + &sdhci0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; diff --git a/src/arm/xilinx/zynq-zc706.dts b/src/arm/xilinx/zynq-zc706.dts index 77943c16d33..3b803c69847 100644 --- a/src/arm/xilinx/zynq-zc706.dts +++ b/src/arm/xilinx/zynq-zc706.dts @@ -14,7 +14,10 @@ ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; mmc0 = &sdhci0; + nvmem0 = &eeprom; + rtc0 = &rtc; }; memory@0 { @@ -46,7 +49,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; @@ -100,7 +102,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <2>; - eeprom@54 { + eeprom: eeprom@54 { compatible = "atmel,24c08"; reg = <0x54>; }; @@ -122,7 +124,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - rtc@51 { + rtc: rtc@51 { compatible = "nxp,pcf8563"; reg = <0x51>; }; @@ -150,7 +152,7 @@ conf { groups = "ethernet0_0_grp"; slew-rate = <0>; - io-standard = <4>; + power-source = <4>; }; conf-rx { @@ -173,7 +175,7 @@ conf-mdio { groups = "mdio0_0_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; bias-disable; }; }; @@ -187,7 +189,7 @@ conf { groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-pull-up { @@ -211,7 +213,7 @@ groups = "i2c0_10_grp"; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; @@ -224,7 +226,7 @@ conf { groups = "sdio0_2_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; bias-disable; }; @@ -238,7 +240,7 @@ bias-high-impedance; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; mux-wp { @@ -251,7 +253,7 @@ bias-high-impedance; bias-pull-up; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; }; @@ -264,7 +266,7 @@ conf { groups = "uart1_10_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -287,7 +289,7 @@ conf { groups = "usb0_0_grp"; slew-rate = <0>; - io-standard = <1>; + power-source = <1>; }; conf-rx { @@ -303,13 +305,54 @@ }; }; +&qspi { + bootph-all; + status = "okay"; + num-cs = <2>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; + }; +}; + &sdhci0 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sdhci0_default>; }; &uart1 { + bootph-all; status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1_default>; diff --git a/src/arm/xilinx/zynq-zc770-xm010.dts b/src/arm/xilinx/zynq-zc770-xm010.dts index 0dd352289a4..5fe799c3c7c 100644 --- a/src/arm/xilinx/zynq-zc770-xm010.dts +++ b/src/arm/xilinx/zynq-zc770-xm010.dts @@ -15,6 +15,7 @@ ethernet0 = &gem0; i2c0 = &i2c0; serial0 = &uart1; + spi0 = &qspi; spi1 = &spi1; }; @@ -45,7 +46,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; @@ -57,7 +57,43 @@ compatible = "atmel,24c02"; reg = <0x52>; }; +}; +&qspi { + status = "okay"; + num-cs = <1>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; + }; }; &sdhci0 { @@ -85,6 +121,7 @@ }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/src/arm/xilinx/zynq-zc770-xm011.dts b/src/arm/xilinx/zynq-zc770-xm011.dts index 56732e8f6ca..f9a086fe66d 100644 --- a/src/arm/xilinx/zynq-zc770-xm011.dts +++ b/src/arm/xilinx/zynq-zc770-xm011.dts @@ -47,6 +47,36 @@ }; }; +&nfc0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + nand@0 { + reg = <0>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "nand-fsbl-uboot"; + reg = <0x0 0x1000000>; + }; + partition@1000000 { + label = "nand-linux"; + reg = <0x1000000 0x2000000>; + }; + partition@3000000 { + label = "nand-rootfs"; + reg = <0x3000000 0x200000>; + }; + }; + }; +}; + +&smcc { + status = "okay"; +}; + &spi0 { status = "okay"; num-cs = <4>; @@ -54,6 +84,7 @@ }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/src/arm/xilinx/zynq-zc770-xm012.dts b/src/arm/xilinx/zynq-zc770-xm012.dts index d2359b789eb..24520e7d396 100644 --- a/src/arm/xilinx/zynq-zc770-xm012.dts +++ b/src/arm/xilinx/zynq-zc770-xm012.dts @@ -53,6 +53,40 @@ }; }; +&nor0 { + status = "okay"; + bank-width = <1>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "nor-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "nor-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "nor-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "nor-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "nor-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; +}; + +&smcc { + status = "okay"; +}; + &spi1 { status = "okay"; num-cs = <4>; @@ -60,5 +94,6 @@ }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/src/arm/xilinx/zynq-zc770-xm013.dts b/src/arm/xilinx/zynq-zc770-xm013.dts index 38d96adc870..103e87ea725 100644 --- a/src/arm/xilinx/zynq-zc770-xm013.dts +++ b/src/arm/xilinx/zynq-zc770-xm013.dts @@ -15,6 +15,7 @@ ethernet0 = &gem1; i2c0 = &i2c1; serial0 = &uart0; + spi0 = &qspi; spi1 = &spi0; }; @@ -40,7 +41,6 @@ ethernet_phy: ethernet-phy@7 { reg = <7>; - device_type = "ethernet-phy"; }; }; @@ -58,6 +58,44 @@ }; }; +&qspi { + status = "okay"; + num-cs = <2>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>, <1>; + parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 16MB */ + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; + }; +}; + &spi0 { status = "okay"; num-cs = <4>; @@ -73,5 +111,6 @@ }; &uart0 { + bootph-all; status = "okay"; }; diff --git a/src/arm/xilinx/zynq-zed.dts b/src/arm/xilinx/zynq-zed.dts index 6a5a93aa655..52ba569b2b9 100644 --- a/src/arm/xilinx/zynq-zed.dts +++ b/src/arm/xilinx/zynq-zed.dts @@ -13,6 +13,7 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; mmc0 = &sdhci0; }; @@ -43,15 +44,55 @@ ethernet_phy: ethernet-phy@0 { reg = <0>; - device_type = "ethernet-phy"; + }; +}; + +&qspi { + bootph-all; + status = "okay"; + num-cs = <1>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + m25p,fast-read; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; + partition@c00000 { + label = "qspi-bitstream"; + reg = <0xc00000 0x400000>; + }; + }; }; }; &sdhci0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/src/arm/xilinx/zynq-zturn-common.dtsi b/src/arm/xilinx/zynq-zturn-common.dtsi index 33b02e05ce8..defef9c8da1 100644 --- a/src/arm/xilinx/zynq-zturn-common.dtsi +++ b/src/arm/xilinx/zynq-zturn-common.dtsi @@ -63,6 +63,11 @@ ps-clk-frequency = <33333333>; }; +&qspi { + bootph-all; + status = "okay"; +}; + &gem0 { status = "okay"; phy-mode = "rgmii-id"; @@ -73,14 +78,17 @@ }; &sdhci0 { + bootph-all; status = "okay"; }; &uart0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/src/arm/xilinx/zynq-zybo-z7.dts b/src/arm/xilinx/zynq-zybo-z7.dts index 7b87e10d395..56b917eec78 100644 --- a/src/arm/xilinx/zynq-zybo-z7.dts +++ b/src/arm/xilinx/zynq-zybo-z7.dts @@ -10,6 +10,8 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; + mmc0 = &sdhci0; }; memory@0 { @@ -49,15 +51,21 @@ ethernet_phy: ethernet-phy@0 { reg = <0>; - device_type = "ethernet-phy"; }; }; +&qspi { + bootph-all; + status = "okay"; +}; + &sdhci0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/src/arm/xilinx/zynq-zybo.dts b/src/arm/xilinx/zynq-zybo.dts index 755f6f109d5..fbc7d1b12e9 100644 --- a/src/arm/xilinx/zynq-zybo.dts +++ b/src/arm/xilinx/zynq-zybo.dts @@ -13,6 +13,7 @@ aliases { ethernet0 = &gem0; serial0 = &uart1; + spi0 = &qspi; mmc0 = &sdhci0; }; @@ -44,15 +45,21 @@ ethernet_phy: ethernet-phy@0 { reg = <0>; - device_type = "ethernet-phy"; }; }; +&qspi { + bootph-all; + status = "okay"; +}; + &sdhci0 { + bootph-all; status = "okay"; }; &uart1 { + bootph-all; status = "okay"; }; diff --git a/src/arm64/airoha/en7581-evb.dts b/src/arm64/airoha/en7581-evb.dts index cf58e43dd5b..d53b72d1824 100644 --- a/src/arm64/airoha/en7581-evb.dts +++ b/src/arm64/airoha/en7581-evb.dts @@ -24,3 +24,47 @@ reg = <0x0 0x80000000 0x2 0x00000000>; }; }; + +&spi_nand { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootloader@0 { + label = "bootloader"; + reg = <0x00000000 0x00080000>; + read-only; + }; + + art@200000 { + label = "art"; + reg = <0x00200000 0x00400000>; + }; + + tclinux@600000 { + label = "tclinux"; + reg = <0x00600000 0x03200000>; + }; + + tclinux_slave@3800000 { + label = "tclinux_alt"; + reg = <0x03800000 0x03200000>; + }; + + rootfs_data@6a00000 { + label = "rootfs_data"; + reg = <0x06a00000 0x01400000>; + }; + + reserved_bmt@7e00000 { + label = "reserved_bmt"; + reg = <0x07e00000 0x00200000>; + read-only; + }; + }; +}; + +&i2c0 { + status = "okay"; +}; diff --git a/src/arm64/airoha/en7581.dtsi b/src/arm64/airoha/en7581.dtsi index 55eb1762fb1..26b13694091 100644 --- a/src/arm64/airoha/en7581.dtsi +++ b/src/arm64/airoha/en7581.dtsi @@ -2,6 +2,8 @@ #include #include +#include +#include / { interrupt-parent = <&gic>; @@ -122,6 +124,12 @@ ; }; + clk20m: clock-20000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -142,6 +150,36 @@ interrupts = ; }; + spi@1fa10000 { + compatible = "airoha,en7581-snand"; + reg = <0x0 0x1fa10000 0x0 0x140>, + <0x0 0x1fa11000 0x0 0x160>; + + clocks = <&scuclk EN7523_CLK_SPI>; + clock-names = "spi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + spi_nand: nand@0 { + compatible = "spi-nand"; + reg = <0>; + + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <2>; + }; + }; + + scuclk: clock-controller@1fb00000 { + compatible = "airoha,en7581-scu"; + reg = <0x0 0x1fb00000 0x0 0x970>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + uart1: serial@1fbf0000 { compatible = "ns16550"; reg = <0x0 0x1fbf0000 0x0 0x30>; @@ -150,5 +188,58 @@ interrupts = ; clock-frequency = <1843200>; }; + + rng@1faa1000 { + compatible = "airoha,en7581-trng"; + reg = <0x0 0x1faa1000 0x0 0xc04>; + interrupts = ; + }; + + system-controller@1fbf0200 { + compatible = "airoha,en7581-gpio-sysctl", "syscon", + "simple-mfd"; + reg = <0x0 0x1fbf0200 0x0 0xc0>; + + en7581_pinctrl: pinctrl { + compatible = "airoha,en7581-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + i2c0: i2c@1fbf8000 { + compatible = "mediatek,mt7621-i2c"; + reg = <0x0 0x1fbf8000 0x0 0x100>; + + resets = <&scuclk EN7581_I2C2_RST>; + + clocks = <&clk20m>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@1fbf8100 { + compatible = "mediatek,mt7621-i2c"; + reg = <0x0 0x1fbf8100 0x0 0x100>; + + resets = <&scuclk EN7581_I2C_MASTER_RST>; + + clocks = <&clk20m>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; }; }; diff --git a/src/arm64/allwinner/sun50i-a100-allwinner-perf1.dts b/src/arm64/allwinner/sun50i-a100-allwinner-perf1.dts index a387bccdcef..a7e3be0155a 100644 --- a/src/arm64/allwinner/sun50i-a100-allwinner-perf1.dts +++ b/src/arm64/allwinner/sun50i-a100-allwinner-perf1.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "sun50i-a100.dtsi" +#include "sun50i-a100-cpu-opp.dtsi" #include @@ -38,6 +39,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &pio { vcc-pb-supply = <®_dcdc1>; vcc-pc-supply = <®_eldo1>; diff --git a/src/arm64/allwinner/sun50i-a100-cpu-opp.dtsi b/src/arm64/allwinner/sun50i-a100-cpu-opp.dtsi new file mode 100644 index 00000000000..c6a2efa037d --- /dev/null +++ b/src/arm64/allwinner/sun50i-a100-cpu-opp.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2020 Yangtao Li +// Copyright (c) 2020 ShuoSheng Huang + +/ { + cpu_opp_table: opp-table-cpu { + compatible = "allwinner,sun50i-a100-operating-points"; + nvmem-cells = <&cpu_speed_grade>; + opp-shared; + + opp-408000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <408000000>; + + opp-microvolt-speed0 = <900000>; + opp-microvolt-speed1 = <900000>; + opp-microvolt-speed2 = <900000>; + }; + + opp-600000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <600000000>; + + opp-microvolt-speed0 = <900000>; + opp-microvolt-speed1 = <900000>; + opp-microvolt-speed2 = <900000>; + }; + + opp-816000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <816000000>; + + opp-microvolt-speed0 = <940000>; + opp-microvolt-speed1 = <900000>; + opp-microvolt-speed2 = <900000>; + }; + + opp-1080000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1080000000>; + + opp-microvolt-speed0 = <1020000>; + opp-microvolt-speed1 = <980000>; + opp-microvolt-speed2 = <950000>; + }; + + opp-1200000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1200000000>; + + opp-microvolt-speed0 = <1100000>; + opp-microvolt-speed1 = <1020000>; + opp-microvolt-speed2 = <1000000>; + }; + + opp-1320000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1320000000>; + + opp-microvolt-speed0 = <1160000>; + opp-microvolt-speed1 = <1060000>; + opp-microvolt-speed2 = <1030000>; + }; + + opp-1464000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1464000000>; + + opp-microvolt-speed0 = <1180000>; + opp-microvolt-speed1 = <1180000>; + opp-microvolt-speed2 = <1130000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opp_table>; +}; diff --git a/src/arm64/allwinner/sun50i-a100.dtsi b/src/arm64/allwinner/sun50i-a100.dtsi index a24adba201a..f9f6fea03b7 100644 --- a/src/arm64/allwinner/sun50i-a100.dtsi +++ b/src/arm64/allwinner/sun50i-a100.dtsi @@ -23,6 +23,7 @@ device_type = "cpu"; reg = <0x0>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; cpu1: cpu@1 { @@ -30,6 +31,7 @@ device_type = "cpu"; reg = <0x1>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; cpu2: cpu@2 { @@ -37,6 +39,7 @@ device_type = "cpu"; reg = <0x2>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; cpu3: cpu@3 { @@ -44,6 +47,7 @@ device_type = "cpu"; reg = <0x3>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; }; @@ -175,6 +179,10 @@ ths_calibration: calib@14 { reg = <0x14 8>; }; + + cpu_speed_grade: cpu-speed-grade@1c { + reg = <0x1c 0x2>; + }; }; watchdog@30090a0 { diff --git a/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts b/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts index 13a0e63afea..2c64d834a2c 100644 --- a/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts +++ b/src/arm64/allwinner/sun50i-h6-beelink-gs1.dts @@ -152,28 +152,12 @@ vcc-pg-supply = <®_aldo1>; }; -&r_ir { - linux,rc-map-name = "rc-beelink-gs1"; - status = "okay"; -}; - -&r_pio { - /* - * FIXME: We can't add that supply for now since it would - * create a circular dependency between pinctrl, the regulator - * and the RSB Bus. - * - * vcc-pl-supply = <®_aldo1>; - */ - vcc-pm-supply = <®_aldo1>; -}; - -&r_rsb { +&r_i2c { status = "okay"; - axp805: pmic@745 { + axp805: pmic@36 { compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x745>; + reg = <0x36>; interrupt-parent = <&r_intc>; interrupts = ; interrupt-controller; @@ -291,6 +275,22 @@ }; }; +&r_ir { + linux,rc-map-name = "rc-beelink-gs1"; + status = "okay"; +}; + +&r_pio { + /* + * PL0 and PL1 are used for PMIC I2C + * don't enable the pl-supply else + * it will fail at boot + * + * vcc-pl-supply = <®_aldo1>; + */ + vcc-pm-supply = <®_aldo1>; +}; + &spdif { pinctrl-names = "default"; pinctrl-0 = <&spdif_tx_pin>; diff --git a/src/arm64/allwinner/sun50i-h6-orangepi-3.dts b/src/arm64/allwinner/sun50i-h6-orangepi-3.dts index ab87c3447cd..f005072c68a 100644 --- a/src/arm64/allwinner/sun50i-h6-orangepi-3.dts +++ b/src/arm64/allwinner/sun50i-h6-orangepi-3.dts @@ -176,16 +176,12 @@ vcc-pg-supply = <®_vcc_wifi_io>; }; -&r_ir { - status = "okay"; -}; - -&r_rsb { +&r_i2c { status = "okay"; - axp805: pmic@745 { + axp805: pmic@36 { compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x745>; + reg = <0x36>; interrupt-parent = <&r_intc>; interrupts = ; interrupt-controller; @@ -296,6 +292,10 @@ }; }; +&r_ir { + status = "okay"; +}; + &rtc { clocks = <&ext_osc32k>; }; diff --git a/src/arm64/allwinner/sun50i-h6-orangepi.dtsi b/src/arm64/allwinner/sun50i-h6-orangepi.dtsi index d05dc5d6e6b..e34dbb99202 100644 --- a/src/arm64/allwinner/sun50i-h6-orangepi.dtsi +++ b/src/arm64/allwinner/sun50i-h6-orangepi.dtsi @@ -113,20 +113,12 @@ vcc-pg-supply = <®_aldo1>; }; -&r_ir { - status = "okay"; -}; - -&r_pio { - vcc-pm-supply = <®_bldo3>; -}; - -&r_rsb { +&r_i2c { status = "okay"; - axp805: pmic@745 { + axp805: pmic@36 { compatible = "x-powers,axp805", "x-powers,axp806"; - reg = <0x745>; + reg = <0x36>; interrupt-parent = <&r_intc>; interrupts = ; interrupt-controller; @@ -241,6 +233,14 @@ }; }; +&r_ir { + status = "okay"; +}; + +&r_pio { + vcc-pm-supply = <®_bldo3>; +}; + &rtc { clocks = <&ext_osc32k>; }; diff --git a/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts b/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts index a231abf1684..7e17ca07892 100644 --- a/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts +++ b/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-2024.dts @@ -167,6 +167,12 @@ gpios = <&pio 8 12 GPIO_ACTIVE_HIGH>; /* PI12 */ default-state = "on"; }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 8 11 GPIO_ACTIVE_HIGH>; /* PI11 */ + }; }; reg_vcc5v: regulator-vcc5v { /* USB-C power input */ @@ -237,6 +243,7 @@ battery_power: battery-power { compatible = "x-powers,axp717-battery-power-supply"; monitored-battery = <&battery>; + x-powers,no-thermistor; }; regulators { @@ -328,8 +335,17 @@ regulator-name = "boost"; }; + /* + * Regulator function is unknown, but reading + * GPIO values in bootloader is inconsistent + * on reboot if this is disabled. Setting to + * default value from regulator OTP mem. + */ reg_cpusldo: cpusldo { - /* unused */ + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; }; }; diff --git a/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-h.dts b/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-h.dts index ff453336eab..bef4d107482 100644 --- a/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-h.dts +++ b/src/arm64/allwinner/sun50i-h700-anbernic-rg35xx-h.dts @@ -71,6 +71,25 @@ <&pio 8 2 GPIO_ACTIVE_LOW>; #mux-control-cells = <0>; }; + + reg_vcc3v8_usb: regulator-vcc3v8-usb { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pio 4 5 GPIO_ACTIVE_HIGH>; /* PE5 */ + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + regulator-name = "vcc3v8-usb"; + }; + + reg_vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pio 8 7 GPIO_ACTIVE_HIGH>; /* PI7 */ + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0-usb"; + vin-supply = <®_vcc3v8_usb>; + }; }; &gpadc { @@ -113,3 +132,7 @@ function = "gpio_out"; }; }; + +&usbphy { + usb1_vbus-supply = <®_vcc5v0_usb>; +}; diff --git a/src/arm64/amazon/alpine-v2.dtsi b/src/arm64/amazon/alpine-v2.dtsi index da9de498666..5a72f0b6424 100644 --- a/src/arm64/amazon/alpine-v2.dtsi +++ b/src/arm64/amazon/alpine-v2.dtsi @@ -151,7 +151,7 @@ al,msi-num-spis = <160>; }; - io-fabric@fc000000 { + io-bus@fc000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/src/arm64/amazon/alpine-v3.dtsi b/src/arm64/amazon/alpine-v3.dtsi index 8b6156b5af6..dea60d136c2 100644 --- a/src/arm64/amazon/alpine-v3.dtsi +++ b/src/arm64/amazon/alpine-v3.dtsi @@ -361,7 +361,7 @@ interrupt-parent = <&gic>; }; - io-fabric@fc000000 { + io-bus@fc000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/src/arm64/amd/amd-overdrive-rev-b0.dts b/src/arm64/amd/amd-overdrive-rev-b0.dts index 7c82d90e940..8862adae44e 100644 --- a/src/arm64/amd/amd-overdrive-rev-b0.dts +++ b/src/arm64/amd/amd-overdrive-rev-b0.dts @@ -58,7 +58,7 @@ &spi1 { status = "okay"; - sdcard0: sdcard@0 { + sdcard0: mmc@0 { compatible = "mmc-spi-slot"; reg = <0>; spi-max-frequency = <20000000>; diff --git a/src/arm64/amd/amd-overdrive-rev-b1.dts b/src/arm64/amd/amd-overdrive-rev-b1.dts index 58e2b0a6f84..b34dd8d5d1b 100644 --- a/src/arm64/amd/amd-overdrive-rev-b1.dts +++ b/src/arm64/amd/amd-overdrive-rev-b1.dts @@ -8,32 +8,10 @@ /dts-v1/; -/include/ "amd-seattle-soc.dtsi" -/include/ "amd-seattle-cpus.dtsi" +/include/ "amd-overdrive-rev-b0.dts" / { model = "AMD Seattle (Rev.B1) Development Board (Overdrive)"; - compatible = "amd,seattle-overdrive", "amd,seattle"; - - chosen { - stdout-path = &serial0; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; -}; - -&ccp0 { - status = "okay"; -}; - -/** - * NOTE: In Rev.B, gpio0 is reserved. - */ -&gpio1 { - status = "okay"; }; &gpio2 { @@ -44,48 +22,11 @@ status = "okay"; }; -&gpio4 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&i2c1 { - status = "okay"; -}; - -&pcie0 { - status = "okay"; -}; - &sata1 { status = "okay"; }; -&spi0 { - status = "okay"; -}; - -&spi1 { - status = "okay"; - sdcard0: sdcard@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3200 3400>; - pl022,interface = <0>; - pl022,com-mode = <0x0>; - pl022,rx-level-trig = <0>; - pl022,tx-level-trig = <0>; - }; -}; - &ipmi_kcs { status = "okay"; }; -&smb0 { - /include/ "amd-seattle-xgbe-b.dtsi" -}; diff --git a/src/arm64/amd/amd-seattle-clks.dtsi b/src/arm64/amd/amd-seattle-clks.dtsi index 2dd2c28171e..73f687773ce 100644 --- a/src/arm64/amd/amd-seattle-clks.dtsi +++ b/src/arm64/amd/amd-seattle-clks.dtsi @@ -5,51 +5,39 @@ * Copyright (C) 2014 Advanced Micro Devices, Inc. */ - adl3clk_100mhz: clk100mhz_0 { + adl3clk_100mhz: uartspiclk_100mhz: clock-100000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; clock-output-names = "adl3clk_100mhz"; }; - ccpclk_375mhz: clk375mhz { + ccpclk_375mhz: clock-375000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <375000000>; clock-output-names = "ccpclk_375mhz"; }; - sataclk_333mhz: clk333mhz { + sataclk_333mhz: clock-333000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <333000000>; clock-output-names = "sataclk_333mhz"; }; - pcieclk_500mhz: clk500mhz_0 { + dmaclk_500mhz: pcieclk_500mhz: clock-500000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <500000000>; clock-output-names = "pcieclk_500mhz"; }; - dmaclk_500mhz: clk500mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <500000000>; - clock-output-names = "dmaclk_500mhz"; - }; - - miscclk_250mhz: clk250mhz_4 { + xgmacclk0_dma_250mhz: xgmacclk0_ptp_250mhz: xgmacclk1_dma_250mhz: xgmacclk1_ptp_250mhz: + miscclk_250mhz: clock-250000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <250000000>; clock-output-names = "miscclk_250mhz"; }; - uartspiclk_100mhz: clk100mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "uartspiclk_100mhz"; - }; diff --git a/src/arm64/amd/amd-seattle-soc.dtsi b/src/arm64/amd/amd-seattle-soc.dtsi index d3d931eb767..a611f8288b3 100644 --- a/src/arm64/amd/amd-seattle-soc.dtsi +++ b/src/arm64/amd/amd-seattle-soc.dtsi @@ -11,6 +11,8 @@ #address-cells = <2>; #size-cells = <2>; + /include/ "amd-seattle-clks.dtsi" + gic0: interrupt-controller@e1101000 { compatible = "arm,gic-400", "arm,cortex-a15-gic"; interrupt-controller; @@ -38,7 +40,7 @@ <1 10 0xff04>; }; - smb0: smb { + smb0: bus { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <2>; @@ -51,8 +53,6 @@ */ dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; - /include/ "amd-seattle-clks.dtsi" - sata0: sata@e0300000 { compatible = "snps,dwc-ahci"; reg = <0 0xe0300000 0 0xf0000>; @@ -121,7 +121,6 @@ status = "disabled"; compatible = "arm,pl022", "arm,primecell"; reg = <0 0xe1020000 0 0x1000>; - spi-controller; interrupts = <0 330 4>; clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>; clock-names = "sspclk", "apb_pclk"; @@ -131,7 +130,6 @@ status = "disabled"; compatible = "arm,pl022", "arm,primecell"; reg = <0 0xe1030000 0 0x1000>; - spi-controller; interrupts = <0 329 4>; clocks = <&uartspiclk_100mhz>, <&uartspiclk_100mhz>; clock-names = "sspclk", "apb_pclk"; diff --git a/src/arm64/amd/amd-seattle-xgbe-b.dtsi b/src/arm64/amd/amd-seattle-xgbe-b.dtsi index 9259e547e2e..18b0c2dd1b2 100644 --- a/src/arm64/amd/amd-seattle-xgbe-b.dtsi +++ b/src/arm64/amd/amd-seattle-xgbe-b.dtsi @@ -5,35 +5,7 @@ * Copyright (C) 2015 Advanced Micro Devices, Inc. */ - xgmacclk0_dma_250mhz: clk250mhz_0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk0_dma_250mhz"; - }; - - xgmacclk0_ptp_250mhz: clk250mhz_1 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk0_ptp_250mhz"; - }; - - xgmacclk1_dma_250mhz: clk250mhz_2 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk1_dma_250mhz"; - }; - - xgmacclk1_ptp_250mhz: clk250mhz_3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <250000000>; - clock-output-names = "xgmacclk1_ptp_250mhz"; - }; - - xgmac0: xgmac@e0700000 { + xgmac0: ethernet@e0700000 { compatible = "amd,xgbe-seattle-v1a"; reg = <0 0xe0700000 0 0x80000>, <0 0xe0780000 0 0x80000>, @@ -59,7 +31,7 @@ dma-coherent; }; - xgmac1: xgmac@e0900000 { + xgmac1: ethernet@e0900000 { compatible = "amd,xgbe-seattle-v1a"; reg = <0 0xe0900000 0 0x80000>, <0 0xe0980000 0 0x80000>, diff --git a/src/arm64/amlogic/amlogic-a4.dtsi b/src/arm64/amlogic/amlogic-a4.dtsi index de10e7aebf2..a06838552f2 100644 --- a/src/arm64/amlogic/amlogic-a4.dtsi +++ b/src/arm64/amlogic/amlogic-a4.dtsi @@ -48,3 +48,24 @@ }; }; }; + +&apb { + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,a4-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; + + gpio_ao_intc: interrupt-controller@8e72c { + compatible = "amlogic,a4-gpio-ao-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x8e72c 0x0 0x0c>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = <140 141>; + }; +}; diff --git a/src/arm64/amlogic/amlogic-a5.dtsi b/src/arm64/amlogic/amlogic-a5.dtsi index 17a6316de89..32ed1776891 100644 --- a/src/arm64/amlogic/amlogic-a5.dtsi +++ b/src/arm64/amlogic/amlogic-a5.dtsi @@ -48,3 +48,15 @@ }; }; }; + +&apb { + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,a5-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; +}; diff --git a/src/arm64/amlogic/meson-axg.dtsi b/src/arm64/amlogic/meson-axg.dtsi index e9b22868983..a6924d246bb 100644 --- a/src/arm64/amlogic/meson-axg.dtsi +++ b/src/arm64/amlogic/meson-axg.dtsi @@ -1693,8 +1693,12 @@ }; pwm_AO_cd: pwm@2000 { - compatible = "amlogic,meson-axg-ao-pwm"; + compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x02000 0x0 0x20>; + clocks = <&xtal>, + <&clkc_AO CLKID_AO_CLK81>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV5>; #pwm-cells = <3>; status = "disabled"; }; @@ -1728,8 +1732,12 @@ }; pwm_AO_ab: pwm@7000 { - compatible = "amlogic,meson-axg-ao-pwm"; + compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x07000 0x0 0x20>; + clocks = <&xtal>, + <&clkc_AO CLKID_AO_CLK81>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV5>; #pwm-cells = <3>; status = "disabled"; }; @@ -1806,15 +1814,23 @@ }; pwm_ab: pwm@1b000 { - compatible = "amlogic,meson-axg-ee-pwm"; + compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x1b000 0x0 0x20>; + clocks = <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; pwm_cd: pwm@1a000 { - compatible = "amlogic,meson-axg-ee-pwm"; + compatible = "amlogic,meson-axg-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x1a000 0x0 0x20>; + clocks = <&xtal>, + <&clkc CLKID_FCLK_DIV5>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; diff --git a/src/arm64/amlogic/meson-g12-common.dtsi b/src/arm64/amlogic/meson-g12-common.dtsi index 49b51c54013..69834b49673 100644 --- a/src/arm64/amlogic/meson-g12-common.dtsi +++ b/src/arm64/amlogic/meson-g12-common.dtsi @@ -2060,8 +2060,11 @@ }; pwm_AO_cd: pwm@2000 { - compatible = "amlogic,meson-g12a-ao-pwm-cd"; + compatible = "amlogic,meson-g12-pwm-v2", + "amlogic,meson8-pwm-v2"; reg = <0x0 0x2000 0x0 0x20>; + clocks = <&xtal>, + <&clkc_AO CLKID_AO_CLK81>; #pwm-cells = <3>; status = "disabled"; }; @@ -2099,8 +2102,13 @@ }; pwm_AO_ab: pwm@7000 { - compatible = "amlogic,meson-g12a-ao-pwm-ab"; + compatible = "amlogic,meson-g12-pwm-v2", + "amlogic,meson8-pwm-v2"; reg = <0x0 0x7000 0x0 0x20>; + clocks = <&xtal>, + <&clkc_AO CLKID_AO_CLK81>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV5>; #pwm-cells = <3>; status = "disabled"; }; @@ -2301,22 +2309,37 @@ }; pwm_ef: pwm@19000 { - compatible = "amlogic,meson-g12a-ee-pwm"; + compatible = "amlogic,meson-g12-pwm-v2", + "amlogic,meson8-pwm-v2"; reg = <0x0 0x19000 0x0 0x20>; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; pwm_cd: pwm@1a000 { - compatible = "amlogic,meson-g12a-ee-pwm"; + compatible = "amlogic,meson-g12-pwm-v2", + "amlogic,meson8-pwm-v2"; reg = <0x0 0x1a000 0x0 0x20>; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; pwm_ab: pwm@1b000 { - compatible = "amlogic,meson-g12a-ee-pwm"; + compatible = "amlogic,meson-g12-pwm-v2", + "amlogic,meson8-pwm-v2"; reg = <0x0 0x1b000 0x0 0x20>; + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; #pwm-cells = <3>; status = "disabled"; }; diff --git a/src/arm64/amlogic/meson-g12a-fbx8am.dts b/src/arm64/amlogic/meson-g12a-fbx8am.dts index a457b3f4397..9aa36f17ffa 100644 --- a/src/arm64/amlogic/meson-g12a-fbx8am.dts +++ b/src/arm64/amlogic/meson-g12a-fbx8am.dts @@ -346,8 +346,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; @@ -355,8 +353,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &pdm { diff --git a/src/arm64/amlogic/meson-g12a-radxa-zero.dts b/src/arm64/amlogic/meson-g12a-radxa-zero.dts index c779a5da7d1..952b8d02e5c 100644 --- a/src/arm64/amlogic/meson-g12a-radxa-zero.dts +++ b/src/arm64/amlogic/meson-g12a-radxa-zero.dts @@ -284,8 +284,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; @@ -293,8 +291,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &saradc { diff --git a/src/arm64/amlogic/meson-g12a-sei510.dts b/src/arm64/amlogic/meson-g12a-sei510.dts index ea51341f031..52fbc5103e4 100644 --- a/src/arm64/amlogic/meson-g12a-sei510.dts +++ b/src/arm64/amlogic/meson-g12a-sei510.dts @@ -389,8 +389,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; @@ -398,8 +396,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &pdm { diff --git a/src/arm64/amlogic/meson-g12a-u200.dts b/src/arm64/amlogic/meson-g12a-u200.dts index f70a46967e2..5407049d264 100644 --- a/src/arm64/amlogic/meson-g12a-u200.dts +++ b/src/arm64/amlogic/meson-g12a-u200.dts @@ -502,8 +502,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/src/arm64/amlogic/meson-g12a-x96-max.dts b/src/arm64/amlogic/meson-g12a-x96-max.dts index 32f98a19249..01da83658ae 100644 --- a/src/arm64/amlogic/meson-g12a-x96-max.dts +++ b/src/arm64/amlogic/meson-g12a-x96-max.dts @@ -328,8 +328,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; @@ -363,8 +361,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &uart_A { diff --git a/src/arm64/amlogic/meson-g12b-a311d-libretech-cc.dts b/src/arm64/amlogic/meson-g12b-a311d-libretech-cc.dts index 65b963d794c..adedc1340c7 100644 --- a/src/arm64/amlogic/meson-g12b-a311d-libretech-cc.dts +++ b/src/arm64/amlogic/meson-g12b-a311d-libretech-cc.dts @@ -116,6 +116,4 @@ &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>, <&pwm_b_x7_pins>; - clocks = <&xtal>, <&xtal>; - clock-names = "clkin0", "clkin1"; }; diff --git a/src/arm64/amlogic/meson-g12b-bananapi-cm4.dtsi b/src/arm64/amlogic/meson-g12b-bananapi-cm4.dtsi index 08c33ec7e9f..92e8b26eccc 100644 --- a/src/arm64/amlogic/meson-g12b-bananapi-cm4.dtsi +++ b/src/arm64/amlogic/meson-g12b-bananapi-cm4.dtsi @@ -257,8 +257,6 @@ &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; @@ -273,8 +271,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/src/arm64/amlogic/meson-g12b-bananapi.dtsi b/src/arm64/amlogic/meson-g12b-bananapi.dtsi index d4e1990b5f2..54663c55a20 100644 --- a/src/arm64/amlogic/meson-g12b-bananapi.dtsi +++ b/src/arm64/amlogic/meson-g12b-bananapi.dtsi @@ -367,8 +367,6 @@ status = "okay"; pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &pwm_ef { @@ -380,8 +378,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/src/arm64/amlogic/meson-g12b-dreambox.dtsi b/src/arm64/amlogic/meson-g12b-dreambox.dtsi index de35fa2d7a6..8e3e3354ed6 100644 --- a/src/arm64/amlogic/meson-g12b-dreambox.dtsi +++ b/src/arm64/amlogic/meson-g12b-dreambox.dtsi @@ -116,6 +116,10 @@ status = "okay"; }; +&clkc_audio { + status = "okay"; +}; + &frddr_a { status = "okay"; }; diff --git a/src/arm64/amlogic/meson-g12b-khadas-vim3.dtsi b/src/arm64/amlogic/meson-g12b-khadas-vim3.dtsi index 16dd409051b..48650bad230 100644 --- a/src/arm64/amlogic/meson-g12b-khadas-vim3.dtsi +++ b/src/arm64/amlogic/meson-g12b-khadas-vim3.dtsi @@ -92,16 +92,12 @@ &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/src/arm64/amlogic/meson-g12b-odroid.dtsi b/src/arm64/amlogic/meson-g12b-odroid.dtsi index 09d959aefb1..7e8964bacfc 100644 --- a/src/arm64/amlogic/meson-g12b-odroid.dtsi +++ b/src/arm64/amlogic/meson-g12b-odroid.dtsi @@ -327,16 +327,12 @@ &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/src/arm64/amlogic/meson-g12b-radxa-zero2.dts b/src/arm64/amlogic/meson-g12b-radxa-zero2.dts index 39feba7f2d0..fc05ecf9071 100644 --- a/src/arm64/amlogic/meson-g12b-radxa-zero2.dts +++ b/src/arm64/amlogic/meson-g12b-radxa-zero2.dts @@ -379,32 +379,24 @@ &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; &pwm_ef { pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; &pwm_AO_ab { pinctrl-0 = <&pwm_ao_a_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/src/arm64/amlogic/meson-g12b-w400.dtsi b/src/arm64/amlogic/meson-g12b-w400.dtsi index 4cb6930ffb1..a7a0fc264cd 100644 --- a/src/arm64/amlogic/meson-g12b-w400.dtsi +++ b/src/arm64/amlogic/meson-g12b-w400.dtsi @@ -304,24 +304,18 @@ &pwm_ab { pinctrl-0 = <&pwm_a_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; &pwm_ef { pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; status = "okay"; }; diff --git a/src/arm64/amlogic/meson-gx-libretech-pc.dtsi b/src/arm64/amlogic/meson-gx-libretech-pc.dtsi index d38c3a224fb..2da49cfbde7 100644 --- a/src/arm64/amlogic/meson-gx-libretech-pc.dtsi +++ b/src/arm64/amlogic/meson-gx-libretech-pc.dtsi @@ -345,24 +345,18 @@ &pwm_AO_ab { pinctrl-0 = <&pwm_ao_a_3_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; status = "okay"; }; &pwm_ab { pinctrl-0 = <&pwm_b_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; status = "okay"; }; &pwm_ef { pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; status = "okay"; }; diff --git a/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi b/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi index 45ccddd1aaf..6da1316d97c 100644 --- a/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi +++ b/src/arm64/amlogic/meson-gx-p23x-q20x.dtsi @@ -240,8 +240,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &saradc { diff --git a/src/arm64/amlogic/meson-gx.dtsi b/src/arm64/amlogic/meson-gx.dtsi index 2673f0dbafe..7d99ca44e66 100644 --- a/src/arm64/amlogic/meson-gx.dtsi +++ b/src/arm64/amlogic/meson-gx.dtsi @@ -329,14 +329,14 @@ }; pwm_ab: pwm@8550 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; + compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x08550 0x0 0x10>; #pwm-cells = <3>; status = "disabled"; }; pwm_cd: pwm@8650 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; + compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x08650 0x0 0x10>; #pwm-cells = <3>; status = "disabled"; @@ -351,7 +351,7 @@ }; pwm_ef: pwm@86c0 { - compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; + compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x086c0 0x0 0x10>; #pwm-cells = <3>; status = "disabled"; @@ -498,7 +498,7 @@ }; pwm_AO_ab: pwm@550 { - compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; + compatible = "amlogic,meson-gxbb-pwm-v2", "amlogic,meson8-pwm-v2"; reg = <0x0 0x00550 0x0 0x10>; #pwm-cells = <3>; status = "disabled"; diff --git a/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts b/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts index cf2e2ef8168..2ecc6ebd5a4 100644 --- a/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts +++ b/src/arm64/amlogic/meson-gxbb-nanopi-k2.dts @@ -298,8 +298,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &saradc { diff --git a/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts b/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts index 7d7dde93fff..c09da40ff7b 100644 --- a/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts +++ b/src/arm64/amlogic/meson-gxbb-nexbox-a95x.dts @@ -241,8 +241,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; /* Wireless SDIO Module */ diff --git a/src/arm64/amlogic/meson-gxbb-p20x.dtsi b/src/arm64/amlogic/meson-gxbb-p20x.dtsi index 1736bd2e96e..6f67364fd63 100644 --- a/src/arm64/amlogic/meson-gxbb-p20x.dtsi +++ b/src/arm64/amlogic/meson-gxbb-p20x.dtsi @@ -150,8 +150,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; /* Wireless SDIO Module */ diff --git a/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi b/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi index 3807a184810..6ff567225fe 100644 --- a/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi +++ b/src/arm64/amlogic/meson-gxbb-vega-s95.dtsi @@ -222,8 +222,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &saradc { diff --git a/src/arm64/amlogic/meson-gxbb-wetek.dtsi b/src/arm64/amlogic/meson-gxbb-wetek.dtsi index deb29522718..bfedfc1472e 100644 --- a/src/arm64/amlogic/meson-gxbb-wetek.dtsi +++ b/src/arm64/amlogic/meson-gxbb-wetek.dtsi @@ -185,8 +185,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &saradc { diff --git a/src/arm64/amlogic/meson-gxbb.dtsi b/src/arm64/amlogic/meson-gxbb.dtsi index ed00e67e692..6c134592c7b 100644 --- a/src/arm64/amlogic/meson-gxbb.dtsi +++ b/src/arm64/amlogic/meson-gxbb.dtsi @@ -739,6 +739,31 @@ }; }; +&pwm_ab { + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + +&pwm_AO_ab { + clocks = <&xtal>, <&clkc CLKID_CLK81>; +}; + +&pwm_cd { + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + +&pwm_ef { + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + &pwrc { resets = <&reset RESET_VIU>, <&reset RESET_VENC>, diff --git a/src/arm64/amlogic/meson-gxl-s805x-p241.dts b/src/arm64/amlogic/meson-gxl-s805x-p241.dts index c5e2306ad7a..ca7c4e8e7ca 100644 --- a/src/arm64/amlogic/meson-gxl-s805x-p241.dts +++ b/src/arm64/amlogic/meson-gxl-s805x-p241.dts @@ -280,8 +280,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; /* This is connected to the Bluetooth module: */ diff --git a/src/arm64/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts b/src/arm64/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts index 2b94b6e5285..4ca90ac947b 100644 --- a/src/arm64/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts +++ b/src/arm64/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts @@ -116,8 +116,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &saradc { diff --git a/src/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts b/src/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts index 89fe5110f7a..62a2da766a0 100644 --- a/src/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts +++ b/src/arm64/amlogic/meson-gxl-s905x-hwacom-amazetv.dts @@ -115,8 +115,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; /* SD card */ diff --git a/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts b/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts index a80f0ea2773..4e89d6f6bb5 100644 --- a/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts +++ b/src/arm64/amlogic/meson-gxl-s905x-khadas-vim.dts @@ -211,8 +211,6 @@ status = "okay"; pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; pinctrl-names = "default"; - clocks = <&xtal> , <&xtal>; - clock-names = "clkin0", "clkin1" ; }; &pwm_ef { diff --git a/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts b/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts index c79f9f2099b..236cedec9f1 100644 --- a/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts +++ b/src/arm64/amlogic/meson-gxl-s905x-nexbox-a95x.dts @@ -145,8 +145,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; /* Wireless SDIO Module */ diff --git a/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi b/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi index b52a830efcc..05a0d4de3ad 100644 --- a/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi +++ b/src/arm64/amlogic/meson-gxl-s905x-p212.dtsi @@ -101,8 +101,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &saradc { diff --git a/src/arm64/amlogic/meson-gxl.dtsi b/src/arm64/amlogic/meson-gxl.dtsi index f58d1790de1..19b8a39de6a 100644 --- a/src/arm64/amlogic/meson-gxl.dtsi +++ b/src/arm64/amlogic/meson-gxl.dtsi @@ -809,6 +809,31 @@ }; }; +&pwm_ab { + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + +&pwm_AO_ab { + clocks = <&xtal>, <&clkc CLKID_CLK81>; +}; + +&pwm_cd { + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + +&pwm_ef { + clocks = <&xtal>, + <0>, /* unknown/untested, the datasheet calls it "vid_pll" */ + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_FCLK_DIV3>; +}; + &pwrc { resets = <&reset RESET_VIU>, <&reset RESET_VENC>, diff --git a/src/arm64/amlogic/meson-gxm-khadas-vim2.dts b/src/arm64/amlogic/meson-gxm-khadas-vim2.dts index 96a3dd2d8a9..2a09b3d550e 100644 --- a/src/arm64/amlogic/meson-gxm-khadas-vim2.dts +++ b/src/arm64/amlogic/meson-gxm-khadas-vim2.dts @@ -289,16 +289,12 @@ status = "okay"; pinctrl-0 = <&pwm_ao_a_3_pins>, <&pwm_ao_b_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &pwm_ef { status = "okay"; pinctrl-0 = <&pwm_e_pins>, <&pwm_f_clk_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; &sd_emmc_a { diff --git a/src/arm64/amlogic/meson-gxm-rbox-pro.dts b/src/arm64/amlogic/meson-gxm-rbox-pro.dts index 7356d3b628b..ecaf678b23d 100644 --- a/src/arm64/amlogic/meson-gxm-rbox-pro.dts +++ b/src/arm64/amlogic/meson-gxm-rbox-pro.dts @@ -192,8 +192,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&clkc CLKID_FCLK_DIV4>; - clock-names = "clkin0"; }; /* Wireless SDIO Module */ diff --git a/src/arm64/amlogic/meson-libretech-cottonwood.dtsi b/src/arm64/amlogic/meson-libretech-cottonwood.dtsi index 929e4720ae7..ac9c4c2673b 100644 --- a/src/arm64/amlogic/meson-libretech-cottonwood.dtsi +++ b/src/arm64/amlogic/meson-libretech-cottonwood.dtsi @@ -458,24 +458,18 @@ status = "okay"; pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; }; &pwm_ab { status = "okay"; pinctrl-0 = <&pwm_b_x7_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; }; &pwm_cd { status = "okay"; pinctrl-0 = <&pwm_d_x3_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; }; &saradc { diff --git a/src/arm64/amlogic/meson-sm1-ac2xx.dtsi b/src/arm64/amlogic/meson-sm1-ac2xx.dtsi index d1fa8b8bf79..a3463149db3 100644 --- a/src/arm64/amlogic/meson-sm1-ac2xx.dtsi +++ b/src/arm64/amlogic/meson-sm1-ac2xx.dtsi @@ -199,15 +199,11 @@ status = "okay"; pinctrl-0 = <&pwm_ao_a_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; @@ -215,8 +211,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &saradc { diff --git a/src/arm64/amlogic/meson-sm1-bananapi.dtsi b/src/arm64/amlogic/meson-sm1-bananapi.dtsi index 81dce862902..40db95f6463 100644 --- a/src/arm64/amlogic/meson-sm1-bananapi.dtsi +++ b/src/arm64/amlogic/meson-sm1-bananapi.dtsi @@ -367,8 +367,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts b/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts index 9c0b544e220..5d75ad3f3e4 100644 --- a/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts +++ b/src/arm64/amlogic/meson-sm1-khadas-vim3l.dts @@ -78,8 +78,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/src/arm64/amlogic/meson-sm1-odroid.dtsi b/src/arm64/amlogic/meson-sm1-odroid.dtsi index 7b0e9817a61..ad8d0788376 100644 --- a/src/arm64/amlogic/meson-sm1-odroid.dtsi +++ b/src/arm64/amlogic/meson-sm1-odroid.dtsi @@ -392,8 +392,6 @@ &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; diff --git a/src/arm64/amlogic/meson-sm1-sei610.dts b/src/arm64/amlogic/meson-sm1-sei610.dts index 2e3397e55da..37d7f64b6d5 100644 --- a/src/arm64/amlogic/meson-sm1-sei610.dts +++ b/src/arm64/amlogic/meson-sm1-sei610.dts @@ -435,15 +435,11 @@ status = "okay"; pinctrl-0 = <&pwm_ao_a_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &pwm_AO_cd { pinctrl-0 = <&pwm_ao_d_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin1"; status = "okay"; }; @@ -451,8 +447,6 @@ status = "okay"; pinctrl-0 = <&pwm_e_pins>; pinctrl-names = "default"; - clocks = <&xtal>; - clock-names = "clkin0"; }; &saradc { diff --git a/src/arm64/apple/s5l8960x-5s.dtsi b/src/arm64/apple/s5l8960x-5s.dtsi index 0b16adf07f7..8868df1538d 100644 --- a/src/arm64/apple/s5l8960x-5s.dtsi +++ b/src/arm64/apple/s5l8960x-5s.dtsi @@ -8,6 +8,7 @@ #include "s5l8960x.dtsi" #include "s5l8960x-common.dtsi" +#include "s5l8960x-opp.dtsi" #include / { @@ -49,3 +50,11 @@ }; }; }; + +&dwi_bl { + status = "okay"; +}; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_mipi_dsi>; +}; diff --git a/src/arm64/apple/s5l8960x-air1.dtsi b/src/arm64/apple/s5l8960x-air1.dtsi index 741c5a9f21d..dd57eb1d34c 100644 --- a/src/arm64/apple/s5l8960x-air1.dtsi +++ b/src/arm64/apple/s5l8960x-air1.dtsi @@ -8,6 +8,7 @@ #include "s5l8960x.dtsi" #include "s5l8960x-common.dtsi" +#include "s5l8965x-opp.dtsi" #include / { @@ -49,3 +50,7 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_dp>; +}; diff --git a/src/arm64/apple/s5l8960x-mini2.dtsi b/src/arm64/apple/s5l8960x-mini2.dtsi index b27ef568062..f3696d22e71 100644 --- a/src/arm64/apple/s5l8960x-mini2.dtsi +++ b/src/arm64/apple/s5l8960x-mini2.dtsi @@ -8,6 +8,7 @@ #include "s5l8960x.dtsi" #include "s5l8960x-common.dtsi" +#include "s5l8960x-opp.dtsi" #include / { @@ -49,3 +50,7 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_dp>; +}; diff --git a/src/arm64/apple/s5l8960x-opp.dtsi b/src/arm64/apple/s5l8960x-opp.dtsi new file mode 100644 index 00000000000..e4d568c4a11 --- /dev/null +++ b/src/arm64/apple/s5l8960x-opp.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Operating points for Apple S5L8960X "A7" SoC, Up to 1296 MHz + * + * target-type: N51, N53, J85, J86. J87, J85m, J86m, J87m + * + * Copyright (c) 2024, Nick Chan + */ + +/ { + cyclone_opp: opp-table { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <15500>; + }; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <43000>; + }; + opp03 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <3>; + clock-latency-ns = <26000>; + }; + opp04 { + opp-hz = /bits/ 64 <840000000>; + opp-level = <4>; + clock-latency-ns = <30000>; + }; + opp05 { + opp-hz = /bits/ 64 <1128000000>; + opp-level = <5>; + clock-latency-ns = <39500>; + }; + opp06 { + opp-hz = /bits/ 64 <1296000000>; + opp-level = <6>; + clock-latency-ns = <45500>; + }; + }; +}; diff --git a/src/arm64/apple/s5l8960x-pmgr.dtsi b/src/arm64/apple/s5l8960x-pmgr.dtsi new file mode 100644 index 00000000000..da265f48430 --- /dev/null +++ b/src/arm64/apple/s5l8960x-pmgr.dtsi @@ -0,0 +1,610 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple S5L8960X "A7" SoC + * + * Copyright (c) 2024 Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@20000 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@20008 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_secuart0: power-controller@200f0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "secuart0"; + power-domains = <&ps_sio_p>; + }; + + ps_secuart1: power-controller@200f8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "secuart1"; + power-domains = <&ps_sio_p>; + }; + + ps_cpm: power-controller@20010 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_lio: power-controller@20018 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "lio"; + apple,always-on; /* Core device */ + }; + + ps_iomux: power-controller@20020 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "iomux"; + apple,always-on; /* Core device */ + }; + + ps_aic: power-controller@20028 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_debug: power-controller@20030 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20030 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_dwi: power-controller@20038 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20038 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@20040 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_mca0: power-controller@20048 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20048 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@20050 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@20058 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20058 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@20060 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20060 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@20068 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20068 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@20070 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20070 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@20078 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20078 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@20080 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20080 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@20088 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20088 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@20090 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20090 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@20098 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20098 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@200a0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@200a8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@200b0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@200b8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@200c0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@200c8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_uart3: power-controller@200d0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@200d8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_uart5: power-controller@200e0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_uart6: power-controller@200e8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x200e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_sio_p: power-controller@20110 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + }; + + ps_usb: power-controller@20158 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@20160 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@20170 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@20180 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctrl>; + }; + + ps_disp_busmux: power-controller@201a8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp_busmux"; + }; + + ps_media: power-controller@201d8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp: power-controller@201d0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp"; + }; + + ps_msr: power-controller@201e0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@201e8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0: power-controller@201b0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0"; + power-domains = <&ps_disp_busmux>; + }; + + ps_aes0: power-controller@20100 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes0"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@20108 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@20118 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic0_phy"; + power-domains = <&ps_usb2host0>; + }; + + ps_hsic1_phy: power-controller@20120 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic1_phy"; + power-domains = <&ps_usb2host0>; + }; + + ps_hsic2_phy: power-controller@20128 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic2_phy"; + power-domains = <&ps_usb2host1>; + }; + + ps_ispsens0: power-controller@20130 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens0"; + }; + + ps_ispsens1: power-controller@20138 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens1"; + }; + + ps_mcc: power-controller@20140 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Core device */ + }; + + ps_mcu: power-controller@20148 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcu"; + apple,always-on; /* Core device */ + }; + + ps_amp: power-controller@20150 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "amp"; + apple,always-on; /* Core device */ + }; + + ps_usb2host0_ohci: power-controller@20168 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usb2host1_ohci: power-controller@20178 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1_ohci"; + power-domains = <&ps_usb2host1>; + }; + + ps_usbotg: power-controller@20188 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbotg"; + power-domains = <&ps_usbctrl>; + }; + + ps_smx: power-controller@20190 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@20198 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_cp: power-controller@201a0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cp"; + apple,always-on; /* Core device */ + }; + + ps_mipi_dsi: power-controller@201b8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_disp_busmux>; + }; + + ps_dp: power-controller@201c0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp"; + power-domains = <&ps_disp0>; + }; + + ps_disp1: power-controller@201c8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp1"; + power-domains = <&ps_disp_busmux>; + }; + + ps_vdec: power-controller@201f0 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec"; + power-domains = <&ps_media>; + }; + + ps_venc: power-controller@201f8 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc"; + power-domains = <&ps_media>; + }; + + ps_ans: power-controller@20200 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans"; + }; + + ps_ans_dll: power-controller@20208 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans_dll"; + power-domains = <&ps_ans>; + }; + + ps_gfx: power-controller@20218 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_sep: power-controller@20268 { + compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + power-domains = <&ps_secuart1>, <&ps_secuart0>; + apple,always-on; /* Locked on */ + }; +}; diff --git a/src/arm64/apple/s5l8960x.dtsi b/src/arm64/apple/s5l8960x.dtsi index 0218ecac1d8..d820b0e4305 100644 --- a/src/arm64/apple/s5l8960x.dtsi +++ b/src/arm64/apple/s5l8960x.dtsi @@ -33,6 +33,8 @@ compatible = "apple,cyclone"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&cyclone_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -41,6 +43,8 @@ compatible = "apple,cyclone"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&cyclone_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -53,6 +57,12 @@ nonposted-mmio; ranges; + cpufreq: performance-controller@202220000 { + compatible = "apple,s5l8960x-cluster-cpufreq"; + reg = <0x2 0x02220000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@20a0a0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0a0000 0x0 0x4000>; @@ -62,9 +72,18 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; + pmgr: power-management@20e000000 { + compatible = "apple,s5l8960x-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x24000>; + }; + wdt: watchdog@20e027000 { compatible = "apple,s5l8960x-wdt", "apple,wdt"; reg = <0x2 0x0e027000 0x0 0x1000>; @@ -78,11 +97,20 @@ reg = <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; + power-domains = <&ps_aic>; + }; + + dwi_bl: backlight@20e200010 { + compatible = "apple,s5l8960x-dwi-bl", "apple,dwi-bl"; + reg = <0x2 0x0e200010 0x0 0x8>; + power-domains = <&ps_dwi>; + status = "disabled"; }; pinctrl: pinctrl@20e300000 { compatible = "apple,s5l8960x-pinctrl", "apple,pinctrl"; reg = <0x2 0x0e300000 0x0 0x100000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -111,3 +139,5 @@ ; }; }; + +#include "s5l8960x-pmgr.dtsi" diff --git a/src/arm64/apple/s5l8965x-opp.dtsi b/src/arm64/apple/s5l8965x-opp.dtsi new file mode 100644 index 00000000000..d34dae74a90 --- /dev/null +++ b/src/arm64/apple/s5l8965x-opp.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Operating points for Apple S5L8965X "A7" Rev A SoC, Up to 1392 MHz + * + * target-type: J71, J72, J73 + * + * Copyright (c) 2024, Nick Chan + */ + +/ { + cyclone_opp: opp-table { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <10000>; + }; + opp02 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <2>; + clock-latency-ns = <49000>; + }; + opp03 { + opp-hz = /bits/ 64 <840000000>; + opp-level = <3>; + clock-latency-ns = <30000>; + }; + opp04 { + opp-hz = /bits/ 64 <1128000000>; + opp-level = <4>; + clock-latency-ns = <39500>; + }; + opp05 { + opp-hz = /bits/ 64 <1296000000>; + opp-level = <5>; + clock-latency-ns = <45500>; + }; + opp06 { + opp-hz = /bits/ 64 <1392000000>; + opp-level = <6>; + clock-latency-ns = <46500>; + }; + }; +}; diff --git a/src/arm64/apple/s800-0-3-common.dtsi b/src/arm64/apple/s800-0-3-common.dtsi index 4276bd890e8..cb42c5f2c1b 100644 --- a/src/arm64/apple/s800-0-3-common.dtsi +++ b/src/arm64/apple/s800-0-3-common.dtsi @@ -43,6 +43,10 @@ }; }; +&dwi_bl { + status = "okay"; +}; + &serial0 { status = "okay"; }; diff --git a/src/arm64/apple/s800-0-3-pmgr.dtsi b/src/arm64/apple/s800-0-3-pmgr.dtsi new file mode 100644 index 00000000000..196b8e745a9 --- /dev/null +++ b/src/arm64/apple/s800-0-3-pmgr.dtsi @@ -0,0 +1,757 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple S8000/3 "A9" SoC + * + * Copyright (c) 2024 Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80150 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio_p: power-controller@80158 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + power-domains = <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pms: power-controller@80120 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_pcie_ref: power-controller@80148 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_mca0: power-controller@80168 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@80170 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@80178 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@80180 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@80188 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@80190 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@80198 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801a0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801a8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801b0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@801b8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@801c0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@801c8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@801d0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@801d8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@801e0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@801e8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_uart3: power-controller@801f0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@801f8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@80160 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@80128 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic0_phy"; + power-domains = <&ps_usb2host1>; + }; + + ps_hsic1_phy: power-controller@80130 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic1_phy"; + power-domains = <&ps_usb2host2>; + }; + + ps_isp_sens0: power-controller@80138 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80140 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens1"; + }; + + ps_usb: power-controller@80250 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@80258 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@80260 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@80270 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host2: power-controller@80280 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host2"; + power-domains = <&ps_usbctrl>; + }; + + ps_rtmux: power-controller@802a8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "rtmux"; + }; + + ps_media: power-controller@802d0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp: power-controller@802c8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp"; + power-domains = <&ps_rtmux>; + }; + + ps_msr: power-controller@802e0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@802d8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0: power-controller@802b0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0"; + power-domains = <&ps_rtmux>; + }; + + ps_pmp: power-controller@802e8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pms_sram: power-controller@802f0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_uart5: power-controller@80200 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_uart6: power-controller@80208 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_uart7: power-controller@80210 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_sio_p>; + }; + + ps_uart8: power-controller@80218 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_sio_p>; + }; + + ps_aes0: power-controller@80220 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes0"; + power-domains = <&ps_sio_p>; + }; + + ps_mcc: power-controller@80228 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80230 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80238 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80240 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80248 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_usb2host0_ohci: power-controller@80268 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usb2host1_ohci: power-controller@80278 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1_ohci"; + power-domains = <&ps_usb2host1>; + }; + + ps_usb2host2_ohci: power-controller@80288 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host2_ohci"; + power-domains = <&ps_usb2host2>; + }; + + ps_usbotg: power-controller@80290 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbotg"; + power-domains = <&ps_usbctrl>; + }; + + ps_smx: power-controller@80298 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802a0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mipi_dsi: power-controller@802b8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_rtmux>; + }; + + ps_dp: power-controller@802c0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp"; + power-domains = <&ps_disp0>; + }; + + ps_vdec: power-controller@802f8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec"; + power-domains = <&ps_media>; + }; + + ps_venc: power-controller@80308 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc"; + power-domains = <&ps_media>; + }; + + ps_pcie: power-controller@80310 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie"; + }; + + ps_pcie_aux: power-controller@80318 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_aux"; + }; + + ps_pcie_link0: power-controller@80320 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link0"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link1: power-controller@80328 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link1"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link2: power-controller@80330 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link2"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link3: power-controller@80338 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link3"; + power-domains = <&ps_pcie>; + }; + + ps_gfx: power-controller@80340 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_sep: power-controller@80400 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_venc_pipe: power-controller@88000 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe"; + power-domains = <&ps_venc>; + }; + + ps_venc_me0: power-controller@88008 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + }; + + ps_venc_me1: power-controller@88010 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop: power-controller@80000 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop"; + power-domains = <&ps_aop_busif &ps_aop_cpu &ps_aop_filter>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80008 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_aop_gpio: power-controller@80010 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_gpio"; + power-domains = <&ps_aop>; + }; + + ps_aop_cpu: power-controller@80040 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_cpu"; + }; + + ps_aop_filter: power-controller@80048 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80048 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_filter"; + }; + + ps_aop_busif: power-controller@80050 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_busif"; + }; +}; diff --git a/src/arm64/apple/s800-0-3.dtsi b/src/arm64/apple/s800-0-3.dtsi new file mode 100644 index 00000000000..c0e9ae45627 --- /dev/null +++ b/src/arm64/apple/s800-0-3.dtsi @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple S8000/S8003 "A9" SoC + * + * This file contains parts common to both variants of A9 + * + * Copyright (c) 2022, Konrad Dybcio + */ + +#include +#include +#include +#include + +/ { + interrupt-parent = <&aic>; + #address-cells = <2>; + #size-cells = <2>; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "apple,twister"; + reg = <0x0 0x0>; + cpu-release-addr = <0 0>; /* To be filled in by loader */ + operating-points-v2 = <&twister_opp>; + performance-domains = <&cpufreq>; + enable-method = "spin-table"; + device_type = "cpu"; + }; + + cpu1: cpu@1 { + compatible = "apple,twister"; + reg = <0x0 0x1>; + cpu-release-addr = <0 0>; /* To be filled in by loader */ + operating-points-v2 = <&twister_opp>; + performance-domains = <&cpufreq>; + enable-method = "spin-table"; + device_type = "cpu"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + nonposted-mmio; + ranges; + + cpufreq: performance-controller@202220000 { + compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x02220000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + serial0: serial@20a0c0000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x0a0c0000 0x0 0x4000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = ; + /* Use the bootloader-enabled clocks for now. */ + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; + status = "disabled"; + }; + + pmgr: power-management@20e000000 { + compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x8c000>; + }; + + aic: interrupt-controller@20e100000 { + compatible = "apple,s8000-aic", "apple,aic"; + reg = <0x2 0x0e100000 0x0 0x100000>; + #interrupt-cells = <3>; + interrupt-controller; + power-domains = <&ps_aic>; + }; + + dwi_bl: backlight@20e200080 { + compatible = "apple,s8000-dwi-bl", "apple,dwi-bl"; + reg = <0x2 0x0e200080 0x0 0x8>; + power-domains = <&ps_dwi>; + status = "disabled"; + }; + + pinctrl_ap: pinctrl@20f100000 { + compatible = "apple,s8000-pinctrl", "apple,pinctrl"; + reg = <0x2 0x0f100000 0x0 0x100000>; + power-domains = <&ps_gpio>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_ap 0 0 208>; + apple,npins = <208>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + pinctrl_aop: pinctrl@2100f0000 { + compatible = "apple,s8000-pinctrl", "apple,pinctrl"; + reg = <0x2 0x100f0000 0x0 0x100000>; + power-domains = <&ps_aop_gpio>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aop 0 0 42>; + apple,npins = <42>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + pmgr_mini: power-management@210200000 { + compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x10200000 0 0x84000>; + }; + + wdt: watchdog@2102b0000 { + compatible = "apple,s8000-wdt", "apple,wdt"; + reg = <0x2 0x102b0000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt"; + /* Note that A9 doesn't actually have a hypervisor (EL2 is not implemented). */ + interrupts = , + ; + }; +}; + +#include "s800-0-3-pmgr.dtsi" + +/* + * The A9 was made by two separate fabs on two different process + * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made + * the S8003 (APL1022) on 16nm. There are some minor differences + * such as timing in cpufreq state transistions. + */ diff --git a/src/arm64/apple/s8000.dtsi b/src/arm64/apple/s8000.dtsi index 6e9046ea106..72322f5677a 100644 --- a/src/arm64/apple/s8000.dtsi +++ b/src/arm64/apple/s8000.dtsi @@ -4,141 +4,65 @@ * * Other names: H8P, "Maui" * - * Copyright (c) 2022, Konrad Dybcio + * Copyright (c) 2024, Nick Chan */ -#include -#include -#include -#include +#include "s800-0-3.dtsi" / { - interrupt-parent = <&aic>; - #address-cells = <2>; - #size-cells = <2>; + twister_opp: opp-table { + compatible = "operating-points-v2"; - clkref: clock-ref { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - clock-output-names = "clkref"; - }; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "apple,twister"; - reg = <0x0 0x0>; - cpu-release-addr = <0 0>; /* To be filled in by loader */ - enable-method = "spin-table"; - device_type = "cpu"; + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <650>; }; - - cpu1: cpu@1 { - compatible = "apple,twister"; - reg = <0x0 0x1>; - cpu-release-addr = <0 0>; /* To be filled in by loader */ - enable-method = "spin-table"; - device_type = "cpu"; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <75000>; }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - nonposted-mmio; - ranges; - - serial0: serial@20a0c0000 { - compatible = "apple,s5l-uart"; - reg = <0x2 0x0a0c0000 0x0 0x4000>; - reg-io-width = <4>; - interrupt-parent = <&aic>; - interrupts = ; - /* Use the bootloader-enabled clocks for now. */ - clocks = <&clkref>, <&clkref>; - clock-names = "uart", "clk_uart_baud0"; - status = "disabled"; + opp03 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <3>; + clock-latency-ns = <27000>; }; - - aic: interrupt-controller@20e100000 { - compatible = "apple,s8000-aic", "apple,aic"; - reg = <0x2 0x0e100000 0x0 0x100000>; - #interrupt-cells = <3>; - interrupt-controller; + opp04 { + opp-hz = /bits/ 64 <912000000>; + opp-level = <4>; + clock-latency-ns = <32000>; }; - - pinctrl_ap: pinctrl@20f100000 { - compatible = "apple,s8000-pinctrl", "apple,pinctrl"; - reg = <0x2 0x0f100000 0x0 0x100000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_ap 0 0 208>; - apple,npins = <208>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = , - , - , - , - , - , - ; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-level = <5>; + clock-latency-ns = <35000>; }; - - pinctrl_aop: pinctrl@2100f0000 { - compatible = "apple,s8000-pinctrl", "apple,pinctrl"; - reg = <0x2 0x100f0000 0x0 0x100000>; - - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aop 0 0 42>; - apple,npins = <42>; - - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&aic>; - interrupts = , - , - , - , - , - , - ; + opp06 { + opp-hz = /bits/ 64 <1512000000>; + opp-level = <6>; + clock-latency-ns = <45000>; }; - - wdt: watchdog@2102b0000 { - compatible = "apple,s8000-wdt", "apple,wdt"; - reg = <0x2 0x102b0000 0x0 0x4000>; - clocks = <&clkref>; - interrupt-parent = <&aic>; - interrupts = ; + opp07 { + opp-hz = /bits/ 64 <1800000000>; + opp-level = <7>; + clock-latency-ns = <58000>; }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupt-parent = <&aic>; - interrupt-names = "phys", "virt"; - /* Note that A9 doesn't actually have a hypervisor (EL2 is not implemented). */ - interrupts = , - ; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp08 { + opp-hz = /bits/ 64 <1844000000>; + opp-level = <8>; + clock-latency-ns = <58000>; + turbo-mode; + }; +#endif }; }; /* * The A9 was made by two separate fabs on two different process * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made - * the S8003 (APL1022) on 16nm. While they are seemingly the same, - * they do have distinct part numbers and devices using them have - * distinct model names. There are currently no known differences - * between these as far as Linux is concerned, but let's keep things - * structured properly to make it easier to alter the behaviour of - * one of the chips if need be. + * the S8003 (APL1022) on 16nm. There are some minor differences + * such as timing in cpufreq state transistions. */ diff --git a/src/arm64/apple/s8001-common.dtsi b/src/arm64/apple/s8001-common.dtsi index e94d0e77653..91b06e11389 100644 --- a/src/arm64/apple/s8001-common.dtsi +++ b/src/arm64/apple/s8001-common.dtsi @@ -24,6 +24,7 @@ framebuffer0: framebuffer@0 { compatible = "apple,simple-framebuffer", "simple-framebuffer"; reg = <0 0 0 0>; /* To be filled by loader */ + power-domains = <&ps_disp0 &ps_dp0>; /* Format properties will be added by loader */ status = "disabled"; }; diff --git a/src/arm64/apple/s8001-j98a-j99a.dtsi b/src/arm64/apple/s8001-j98a-j99a.dtsi new file mode 100644 index 00000000000..e66a4c1c138 --- /dev/null +++ b/src/arm64/apple/s8001-j98a-j99a.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple iPad Pro (12.9-inch) + * + * This file contains parts common to iPad Pro (12.9-inch). + * + * target-type: J98a, J99a + * + * Copyright (c) 2024, Nick Chan + */ + +&ps_dcs4 { + apple,always-on; /* LPDDR4 interface */ +}; + +&ps_dcs5 { + apple,always-on; /* LPDDR4 interface */ +}; + +&ps_dcs6 { + apple,always-on; /* LPDDR4 interface */ +}; + +&ps_dcs7 { + apple,always-on; /* LPDDR4 interface */ +}; diff --git a/src/arm64/apple/s8001-j98a.dts b/src/arm64/apple/s8001-j98a.dts index 6d6b841e7ab..162eca05c2d 100644 --- a/src/arm64/apple/s8001-j98a.dts +++ b/src/arm64/apple/s8001-j98a.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "s8001-pro.dtsi" +#include "s8001-j98a-j99a.dtsi" / { compatible = "apple,j98a", "apple,s8001", "apple,arm-platform"; diff --git a/src/arm64/apple/s8001-j99a.dts b/src/arm64/apple/s8001-j99a.dts index d20194b1cae..7b765820c69 100644 --- a/src/arm64/apple/s8001-j99a.dts +++ b/src/arm64/apple/s8001-j99a.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "s8001-pro.dtsi" +#include "s8001-j98a-j99a.dtsi" / { compatible = "apple,j99a", "apple,s8001", "apple,arm-platform"; diff --git a/src/arm64/apple/s8001-pmgr.dtsi b/src/arm64/apple/s8001-pmgr.dtsi new file mode 100644 index 00000000000..859ab77ae92 --- /dev/null +++ b/src/arm64/apple/s8001-pmgr.dtsi @@ -0,0 +1,822 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple S8001 "A9X" SoC + * + * Copyright (c) 2024 Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80148 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio_p: power-controller@80150 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + power-domains = <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pcie_ref: power-controller@80140 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_mca0: power-controller@80160 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@80168 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@80170 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@80178 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@80180 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@80188 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@80190 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@80198 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801a0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801a8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@801b0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@801b8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@801c0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@801c8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@801d0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@801d8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@801e0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_uart3: power-controller@801e8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@801f0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_uart5: power-controller@801f8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@80158 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@80128 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic0_phy"; + power-domains = <&ps_usb2host1>; + }; + + ps_isp_sens0: power-controller@80130 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80138 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens1"; + }; + + ps_pms: power-controller@80120 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_usb: power-controller@80278 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@80280 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@80288 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@80298 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host2: power-controller@802a8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host2"; + power-domains = <&ps_usbctrl>; + }; + + ps_rtmux: power-controller@802d0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "rtmux"; + apple,always-on; /* Core device */ + }; + + ps_disp1mux: power-controller@802e8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp1mux"; + }; + + ps_disp0: power-controller@802d8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0"; + power-domains = <&ps_rtmux>; + }; + + ps_disp1: power-controller@802f0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp1"; + power-domains = <&ps_disp1mux>; + }; + + ps_uart6: power-controller@80200 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_uart7: power-controller@80208 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_sio_p>; + }; + + ps_uart8: power-controller@80210 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_sio_p>; + }; + + ps_aes0: power-controller@80218 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes0"; + power-domains = <&ps_sio_p>; + }; + + ps_mcc: power-controller@80230 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80238 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80240 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80248 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80250 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs4: power-controller@80258 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs4"; + }; + + ps_dcs5: power-controller@80260 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs5"; + }; + + ps_dcs6: power-controller@80268 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs6"; + }; + + ps_dcs7: power-controller@80270 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs7"; + }; + + ps_usb2host0_ohci: power-controller@80290 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@802b8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbotg"; + power-domains = <&ps_usbctrl>; + }; + + ps_smx: power-controller@802c0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802c8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_dp0: power-controller@802e0 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp0"; + power-domains = <&ps_disp0>; + }; + + ps_dp1: power-controller@802f8 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp1"; + power-domains = <&ps_disp1>; + }; + + ps_dpa0: power-controller@80220 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa0"; + }; + + ps_dpa1: power-controller@80228 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa1"; + }; + + ps_media: power-controller@80308 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp: power-controller@80300 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp"; + power-domains = <&ps_rtmux>; + }; + + ps_msr: power-controller@80318 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@80310 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_venc: power-controller@80340 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc"; + power-domains = <&ps_media>; + }; + + ps_pcie: power-controller@80348 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80348 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie"; + }; + + ps_srs: power-controller@80390 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80390 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "srs"; + power-domains = <&ps_media>; + }; + + ps_pcie_aux: power-controller@80350 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_aux"; + }; + + ps_pcie_link0: power-controller@80358 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80358 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link0"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link1: power-controller@80360 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80360 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link1"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link2: power-controller@80368 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80368 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link2"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link3: power-controller@80370 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80370 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link3"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link4: power-controller@80378 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80378 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link4"; + power-domains = <&ps_pcie>; + }; + + ps_pcie_link5: power-controller@80380 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80380 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_link5"; + power-domains = <&ps_pcie>; + }; + + ps_vdec: power-controller@80330 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec"; + power-domains = <&ps_media>; + }; + + ps_gfx: power-controller@80388 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80388 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_pmp: power-controller@80320 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pms_sram: power-controller@80328 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_sep: power-controller@80400 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on*/ + }; + + ps_venc_pipe: power-controller@88000 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe"; + power-domains = <&ps_venc>; + }; + + ps_venc_me0: power-controller@88008 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + }; + + ps_venc_me1: power-controller@88010 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop: power-controller@80000 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop"; + power-domains = <&ps_aop_cpu &ps_aop_filter &ps_aop_busif>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80008 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_aop_gpio: power-controller@80010 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_gpio"; + }; + + ps_aop_cpu: power-controller@80040 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_cpu"; + }; + + ps_aop_filter: power-controller@80048 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80048 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_filter"; + }; + + ps_aop_busif: power-controller@80050 { + compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_busif"; + }; +}; diff --git a/src/arm64/apple/s8001.dtsi b/src/arm64/apple/s8001.dtsi index 23ee3238844..d56d49c048b 100644 --- a/src/arm64/apple/s8001.dtsi +++ b/src/arm64/apple/s8001.dtsi @@ -32,6 +32,8 @@ compatible = "apple,twister"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled in by loader */ + operating-points-v2 = <&twister_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -40,11 +42,62 @@ compatible = "apple,twister"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled in by loader */ + operating-points-v2 = <&twister_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; }; + twister_opp: opp-table { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <800>; + }; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <53000>; + }; + opp03 { + opp-hz = /bits/ 64 <792000000>; + opp-level = <3>; + clock-latency-ns = <18000>; + }; + opp04 { + opp-hz = /bits/ 64 <1080000000>; + opp-level = <4>; + clock-latency-ns = <21000>; + }; + opp05 { + opp-hz = /bits/ 64 <1440000000>; + opp-level = <5>; + clock-latency-ns = <25000>; + }; + opp06 { + opp-hz = /bits/ 64 <1800000000>; + opp-level = <6>; + clock-latency-ns = <33000>; + }; + opp07 { + opp-hz = /bits/ 64 <2160000000>; + opp-level = <7>; + clock-latency-ns = <45000>; + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp08 { + opp-hz = /bits/ 64 <2160000000>; + opp-level = <8>; + clock-latency-ns = <45000>; + turbo-mode; + }; +#endif + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -52,6 +105,12 @@ nonposted-mmio; ranges; + cpufreq: performance-controller@202220000 { + compatible = "apple,s8000-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x02220000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@20a0c0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0c0000 0x0 0x4000>; @@ -61,19 +120,30 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; + pmgr: power-management@20e000000 { + compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x8c000>; + }; + aic: interrupt-controller@20e100000 { compatible = "apple,s8000-aic", "apple,aic"; reg = <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; + power-domains = <&ps_aic>; }; pinctrl_ap: pinctrl@20f100000 { compatible = "apple,s8000-pinctrl", "apple,pinctrl"; reg = <0x2 0x0f100000 0x0 0x100000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -95,6 +165,7 @@ pinctrl_aop: pinctrl@2100f0000 { compatible = "apple,s8000-pinctrl", "apple,pinctrl"; reg = <0x2 0x100f0000 0x0 0x100000>; + power-domains = <&ps_aop_gpio>; gpio-controller; #gpio-cells = <2>; @@ -113,6 +184,14 @@ ; }; + pmgr_mini: power-management@210200000 { + compatible = "apple,s8000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x10200000 0 0x84000>; + }; + wdt: watchdog@2102b0000 { compatible = "apple,s8000-wdt", "apple,wdt"; reg = <0x2 0x102b0000 0x0 0x4000>; @@ -131,3 +210,5 @@ ; }; }; + +#include "s8001-pmgr.dtsi" diff --git a/src/arm64/apple/s8003.dtsi b/src/arm64/apple/s8003.dtsi index 7e4ad4f7e49..79df5c78326 100644 --- a/src/arm64/apple/s8003.dtsi +++ b/src/arm64/apple/s8003.dtsi @@ -4,18 +4,65 @@ * * Other names: H8P, "Malta" * - * Copyright (c) 2022, Konrad Dybcio + * Copyright (c) 2024, Nick Chan */ -#include "s8000.dtsi" +#include "s800-0-3.dtsi" + +/ { + twister_opp: opp-table { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <500>; + }; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <45000>; + }; + opp03 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <3>; + clock-latency-ns = <22000>; + }; + opp04 { + opp-hz = /bits/ 64 <912000000>; + opp-level = <4>; + clock-latency-ns = <25000>; + }; + opp05 { + opp-hz = /bits/ 64 <1200000000>; + opp-level = <5>; + clock-latency-ns = <28000>; + }; + opp06 { + opp-hz = /bits/ 64 <1512000000>; + opp-level = <6>; + clock-latency-ns = <35000>; + }; + opp07 { + opp-hz = /bits/ 64 <1800000000>; + opp-level = <7>; + clock-latency-ns = <38000>; + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp08 { + opp-hz = /bits/ 64 <1844000000>; + opp-level = <8>; + clock-latency-ns = <38000>; + turbo-mode; + }; +#endif + }; +}; /* * The A9 was made by two separate fabs on two different process * nodes: Samsung made the S8000 (APL0898) on 14nm and TSMC made - * the S8003 (APL1022) on 16nm. While they are seemingly the same, - * they do have distinct part numbers and devices using them have - * distinct model names. There are currently no known differences - * between these as far as Linux is concerned, but let's keep things - * structured properly to make it easier to alter the behaviour of - * one of the chips if need be. + * the S8003 (APL1022) on 16nm. There are some minor differences + * such as timing in cpufreq state transistions. */ diff --git a/src/arm64/apple/s800x-6s.dtsi b/src/arm64/apple/s800x-6s.dtsi index 49b04db310c..1dcf80cc292 100644 --- a/src/arm64/apple/s800x-6s.dtsi +++ b/src/arm64/apple/s800x-6s.dtsi @@ -47,3 +47,7 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_mipi_dsi>; +}; diff --git a/src/arm64/apple/s800x-ipad5.dtsi b/src/arm64/apple/s800x-ipad5.dtsi index 32570ed3cdf..c1701e81f0c 100644 --- a/src/arm64/apple/s800x-ipad5.dtsi +++ b/src/arm64/apple/s800x-ipad5.dtsi @@ -41,3 +41,7 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_dp>; +}; diff --git a/src/arm64/apple/s800x-se.dtsi b/src/arm64/apple/s800x-se.dtsi index a1a5690e837..deb7c7cc90f 100644 --- a/src/arm64/apple/s800x-se.dtsi +++ b/src/arm64/apple/s800x-se.dtsi @@ -47,3 +47,7 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_mipi_dsi>; +}; diff --git a/src/arm64/apple/spi1-nvram.dtsi b/src/arm64/apple/spi1-nvram.dtsi new file mode 100644 index 00000000000..3df2fd3993b --- /dev/null +++ b/src/arm64/apple/spi1-nvram.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +// +// Devicetree include for common spi-nor nvram flash. +// +// Apple uses a consistent configiguration for the nvram on all known M1* and +// M2* devices. +// +// Copyright The Asahi Linux Contributors + +/ { + aliases { + nvram = &nvram; + }; +}; + +&spi1 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <25000000>; + #address-cells = <1>; + #size-cells = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + nvram: partition@700000 { + label = "nvram"; + /* To be filled by the loader */ + reg = <0x0 0x0>; + status = "disabled"; + }; + }; + }; +}; diff --git a/src/arm64/apple/t600x-common.dtsi b/src/arm64/apple/t600x-common.dtsi index fa8ead69936..87dfc13d741 100644 --- a/src/arm64/apple/t600x-common.dtsi +++ b/src/arm64/apple/t600x-common.dtsi @@ -362,6 +362,13 @@ clock-output-names = "clkref"; }; + clk_200m: clock-200m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. diff --git a/src/arm64/apple/t600x-die0.dtsi b/src/arm64/apple/t600x-die0.dtsi index b1c875e692c..e9b3140ba1a 100644 --- a/src/arm64/apple/t600x-die0.dtsi +++ b/src/arm64/apple/t600x-die0.dtsi @@ -163,6 +163,34 @@ status = "disabled"; }; + spi1: spi@39b104000 { + compatible = "apple,t6000-spi", "apple,spi"; + reg = <0x3 0x9b104000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_200m>; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi1>; + status = "disabled"; + }; + + spi3: spi@39b10c000 { + compatible = "apple,t6000-spi", "apple,spi"; + reg = <0x3 0x9b10c000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkref>; + pinctrl-0 = <&spi3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi3>; + status = "disabled"; + }; + serial0: serial@39b200000 { compatible = "apple,s5l-uart"; reg = <0x3 0x9b200000 0x0 0x1000>; diff --git a/src/arm64/apple/t600x-gpio-pins.dtsi b/src/arm64/apple/t600x-gpio-pins.dtsi index b31f1a7a2b3..1a994c3c1b7 100644 --- a/src/arm64/apple/t600x-gpio-pins.dtsi +++ b/src/arm64/apple/t600x-gpio-pins.dtsi @@ -36,6 +36,20 @@ ; }; + spi1_pins: spi1-pins { + pinmux = , + , + , + ; + }; + + spi3_pins: spi3-pins { + pinmux = , + , + , + ; + }; + pcie_pins: pcie-pins { pinmux = , , diff --git a/src/arm64/apple/t600x-j314-j316.dtsi b/src/arm64/apple/t600x-j314-j316.dtsi index 2e471dfe43c..22ebc78e120 100644 --- a/src/arm64/apple/t600x-j314-j316.dtsi +++ b/src/arm64/apple/t600x-j314-j316.dtsi @@ -119,3 +119,5 @@ &fpwm0 { status = "okay"; }; + +#include "spi1-nvram.dtsi" diff --git a/src/arm64/apple/t600x-j375.dtsi b/src/arm64/apple/t600x-j375.dtsi index 1e5a19e49b0..d5b985ad567 100644 --- a/src/arm64/apple/t600x-j375.dtsi +++ b/src/arm64/apple/t600x-j375.dtsi @@ -126,3 +126,5 @@ &pcie0_dart_3 { status = "okay"; }; + +#include "spi1-nvram.dtsi" diff --git a/src/arm64/apple/t7000-6.dtsi b/src/arm64/apple/t7000-6.dtsi index f60ea4a4a38..7048d738398 100644 --- a/src/arm64/apple/t7000-6.dtsi +++ b/src/arm64/apple/t7000-6.dtsi @@ -48,3 +48,11 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_mipi_dsi>; +}; + +&typhoon_opp06 { + status = "okay"; +}; diff --git a/src/arm64/apple/t7000-handheld.dtsi b/src/arm64/apple/t7000-handheld.dtsi index 8984c9ec6cc..7b58aa648b5 100644 --- a/src/arm64/apple/t7000-handheld.dtsi +++ b/src/arm64/apple/t7000-handheld.dtsi @@ -22,6 +22,10 @@ }; }; +&dwi_bl { + status = "okay"; +}; + &serial0 { status = "okay"; }; diff --git a/src/arm64/apple/t7000-j42d.dts b/src/arm64/apple/t7000-j42d.dts index 2231db6a739..2ec9e06cc63 100644 --- a/src/arm64/apple/t7000-j42d.dts +++ b/src/arm64/apple/t7000-j42d.dts @@ -20,6 +20,7 @@ framebuffer0: framebuffer@0 { compatible = "apple,simple-framebuffer", "simple-framebuffer"; reg = <0 0 0 0>; /* To be filled by loader */ + power-domains = <&ps_disp0 &ps_dp>; /* Format properties will be added by loader */ status = "disabled"; }; @@ -29,3 +30,7 @@ &serial6 { status = "okay"; }; + +&typhoon_opp06 { + status = "okay"; +}; diff --git a/src/arm64/apple/t7000-mini4.dtsi b/src/arm64/apple/t7000-mini4.dtsi index c64ddc402fd..cc235c5a0c4 100644 --- a/src/arm64/apple/t7000-mini4.dtsi +++ b/src/arm64/apple/t7000-mini4.dtsi @@ -49,3 +49,15 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_dp>; +}; + +&typhoon_opp06 { + status = "okay"; +}; + +&typhoon_opp07 { + status = "okay"; +}; diff --git a/src/arm64/apple/t7000-n102.dts b/src/arm64/apple/t7000-n102.dts index 9c55d339ba4..99eb8a2b8c7 100644 --- a/src/arm64/apple/t7000-n102.dts +++ b/src/arm64/apple/t7000-n102.dts @@ -46,3 +46,7 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0 &ps_mipi_dsi>; +}; diff --git a/src/arm64/apple/t7000-pmgr.dtsi b/src/arm64/apple/t7000-pmgr.dtsi new file mode 100644 index 00000000000..5948fa7afff --- /dev/null +++ b/src/arm64/apple/t7000-pmgr.dtsi @@ -0,0 +1,641 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T7000 "A8" SoC + * + * Copyright (c) 2024, Nick Chan + */ +&pmgr { + ps_cpu0: power-controller@20000 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@20008 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@20040 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_p: power-controller@201f8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + }; + + ps_lio: power-controller@20100 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "lio"; + apple,always-on; /* Core device */ + }; + + ps_iomux: power-controller@20108 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "iomux"; + apple,always-on; /* Core device */ + }; + + ps_aic: power-controller@20110 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_debug: power-controller@20118 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_dwi: power-controller@20120 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@20128 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_mca0: power-controller@20130 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@20138 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@20140 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@20148 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@20150 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@20158 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@20160 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@20168 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@20170 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@20178 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@20180 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@20188 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@20190 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@20198 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@201a0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@201a8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@201b0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_uart3: power-controller@201b8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@201c0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_uart5: power-controller@201c8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_uart6: power-controller@201d0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_uart7: power-controller@201d8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_sio_p>; + }; + + ps_uart8: power-controller@201e0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_sio_p>; + }; + + ps_aes0: power-controller@201e8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes0"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@201f0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_usb: power-controller@20248 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@20250 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@20258 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@20268 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host2: power-controller@20278 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host2"; + power-domains = <&ps_usbctrl>; + }; + + ps_disp_busmux: power-controller@202a8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp_busmux"; + }; + + ps_media: power-controller@202d8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp: power-controller@202d0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp"; + }; + + ps_msr: power-controller@202e0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@202e8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0: power-controller@202b0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0"; + power-domains = <&ps_disp_busmux>; + }; + + ps_disp1: power-controller@202c8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp1"; + power-domains = <&ps_disp_busmux>; + }; + + ps_pcie_ref: power-controller@20220 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_hsic0_phy: power-controller@20200 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic0_phy"; + power-domains = <&ps_usb2host1>; + }; + + ps_hsic1_phy: power-controller@20208 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic1_phy"; + power-domains = <&ps_usb2host2>; + }; + + ps_ispsens0: power-controller@20210 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens0"; + }; + + ps_ispsens1: power-controller@20218 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens1"; + }; + + ps_mcc: power-controller@20230 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_mcu: power-controller@20238 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcu"; + apple,always-on; /* Core device */ + }; + + ps_amp: power-controller@20240 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "amp"; + apple,always-on; /* Core device */ + }; + + ps_usb2host0_ohci: power-controller@20260 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@20288 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbotg"; + power-domains = <&ps_usbctrl>; + }; + + ps_smx: power-controller@20290 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple Fabric, critical block */ + }; + + ps_sf: power-controller@20298 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple Fabric, critical block */ + }; + + ps_cp: power-controller@202a0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cp"; + apple,always-on; /* Core device */ + }; + + ps_mipi_dsi: power-controller@202b8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_disp_busmux>; + }; + + ps_dp: power-controller@202c0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp"; + power-domains = <&ps_disp0>; + }; + + ps_vdec: power-controller@202f0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec"; + power-domains = <&ps_media>; + }; + + ps_ans: power-controller@20318 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans"; + }; + + ps_venc: power-controller@20300 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc"; + power-domains = <&ps_media>; + }; + + ps_pcie: power-controller@20308 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie"; + }; + + ps_pcie_aux: power-controller@20310 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_aux"; + }; + + ps_gfx: power-controller@20320 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_sep: power-controller@20400 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_venc_pipe: power-controller@21000 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x21000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe"; + power-domains = <&ps_venc>; + }; + + ps_venc_me0: power-controller@21008 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x21008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + power-domains = <&ps_venc>; + }; + + ps_venc_me1: power-controller@21010 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x21010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + power-domains = <&ps_venc>; + }; +}; diff --git a/src/arm64/apple/t7000.dtsi b/src/arm64/apple/t7000.dtsi index a7cc29e84c8..85a34dc7bc0 100644 --- a/src/arm64/apple/t7000.dtsi +++ b/src/arm64/apple/t7000.dtsi @@ -33,6 +33,8 @@ compatible = "apple,typhoon"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled in by loader */ + performance-domains = <&cpufreq>; + operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -41,11 +43,55 @@ compatible = "apple,typhoon"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled in by loader */ + performance-domains = <&cpufreq>; + operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; }; }; + typhoon_opp: opp-table { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <300>; + }; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <50000>; + }; + opp03 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <3>; + clock-latency-ns = <29000>; + }; + opp04 { + opp-hz = /bits/ 64 <840000000>; + opp-level = <4>; + clock-latency-ns = <29000>; + }; + opp05 { + opp-hz = /bits/ 64 <1128000000>; + opp-level = <5>; + clock-latency-ns = <36000>; + }; + typhoon_opp06: opp06 { + opp-hz = /bits/ 64 <1392000000>; + opp-level = <6>; + clock-latency-ns = <42000>; + status = "disabled"; /* Not available on N102 */ + }; + typhoon_opp07: opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-level = <7>; + clock-latency-ns = <49000>; + status = "disabled"; /* J96 and J97 only */ + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -53,6 +99,12 @@ nonposted-mmio; ranges; + cpufreq: performance-controller@202220000 { + compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq"; + reg = <0x2 0x02220000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@20a0c0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0c0000 0x0 0x4000>; @@ -62,6 +114,7 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; @@ -74,9 +127,18 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart6>; status = "disabled"; }; + pmgr: power-management@20e000000 { + compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x24000>; + }; + wdt: watchdog@20e027000 { compatible = "apple,t7000-wdt", "apple,wdt"; reg = <0x2 0x0e027000 0x0 0x1000>; @@ -90,11 +152,20 @@ reg = <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; + power-domains = <&ps_aic>; + }; + + dwi_bl: backlight@20e200010 { + compatible = "apple,t7000-dwi-bl", "apple,dwi-bl"; + reg = <0x2 0x0e200010 0x0 0x8>; + power-domains = <&ps_dwi>; + status = "disabled"; }; pinctrl: pinctrl@20e300000 { compatible = "apple,t7000-pinctrl", "apple,pinctrl"; reg = <0x2 0x0e300000 0x0 0x100000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -123,3 +194,5 @@ ; }; }; + +#include "t7000-pmgr.dtsi" diff --git a/src/arm64/apple/t7001-air2.dtsi b/src/arm64/apple/t7001-air2.dtsi index 19fabd425c5..e4ec8c1977d 100644 --- a/src/arm64/apple/t7001-air2.dtsi +++ b/src/arm64/apple/t7001-air2.dtsi @@ -20,6 +20,7 @@ framebuffer0: framebuffer@0 { compatible = "apple,simple-framebuffer", "simple-framebuffer"; reg = <0 0 0 0>; /* To be filled by loader */ + power-domains = <&ps_disp0 &ps_dp>; /* Format properties will be added by loader */ status = "disabled"; }; diff --git a/src/arm64/apple/t7001-pmgr.dtsi b/src/arm64/apple/t7001-pmgr.dtsi new file mode 100644 index 00000000000..7321cfdcd18 --- /dev/null +++ b/src/arm64/apple/t7001-pmgr.dtsi @@ -0,0 +1,650 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T7001 "A8X" SoC + * + * Copyright (c) 2024, Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@20000 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@20008 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpu2: power-controller@20010 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu2"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@20040 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_p: power-controller@201f8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + }; + + ps_lio: power-controller@20100 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "lio"; + apple,always-on; /* Core device */ + }; + + ps_iomux: power-controller@20108 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "iomux"; + apple,always-on; /* Core device */ + }; + + ps_aic: power-controller@20110 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_debug: power-controller@20118 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_dwi: power-controller@20120 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@20128 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_mca0: power-controller@20130 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@20138 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@20140 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@20148 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@20150 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@20158 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@20160 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@20168 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@20170 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@20178 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@20180 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@20188 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@20190 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@20198 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@201a0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@201a8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@201b0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_uart3: power-controller@201b8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@201c0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_uart5: power-controller@201c8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_uart6: power-controller@201d0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_uart7: power-controller@201d8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_sio_p>; + }; + + ps_uart8: power-controller@201e0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_sio_p>; + }; + + ps_aes0: power-controller@201e8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aes0"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@201f0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x201f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_usb: power-controller@20248 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@20250 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@20258 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@20268 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host2: power-controller@20278 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host2"; + power-domains = <&ps_usbctrl>; + }; + + ps_disp_busmux: power-controller@202a8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp_busmux"; + }; + + ps_disp1_busmux: power-controller@202c0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp1_busmux"; + }; + + ps_media: power-controller@202d8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp: power-controller@202d0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp"; + }; + + ps_msr: power-controller@202e0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@202e8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0: power-controller@202b0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0"; + power-domains = <&ps_disp_busmux>; + }; + + ps_disp1: power-controller@202c8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp1"; + power-domains = <&ps_disp1_busmux>; + }; + + ps_pcie_ref: power-controller@20220 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_hsic0_phy: power-controller@20200 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic0_phy"; + power-domains = <&ps_usb2host1>; + }; + + ps_hsic1_phy: power-controller@20208 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic1_phy"; + power-domains = <&ps_usb2host2>; + }; + + ps_ispsens0: power-controller@20210 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens0"; + }; + + ps_ispsens1: power-controller@20218 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens1"; + }; + + ps_mcc: power-controller@20230 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_mcu: power-controller@20238 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcu"; + apple,always-on; /* Core device */ + }; + + ps_amp: power-controller@20240 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "amp"; + apple,always-on; /* Core device */ + }; + + ps_usb2host0_ohci: power-controller@20260 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@20288 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbotg"; + power-domains = <&ps_usbctrl>; + }; + + ps_smx: power-controller@20290 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@20298 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_cp: power-controller@202a0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cp"; + apple,always-on; /* Core device */ + }; + + ps_dp: power-controller@202b8 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp"; + power-domains = <&ps_disp0>; + }; + + ps_vdec: power-controller@202f0 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x202f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec"; + power-domains = <&ps_media>; + }; + + ps_ans: power-controller@20318 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans"; + }; + + ps_venc: power-controller@20300 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc"; + power-domains = <&ps_media>; + }; + + ps_pcie: power-controller@20308 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie"; + }; + + ps_pcie_aux: power-controller@20310 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_aux"; + }; + + ps_gfx: power-controller@20320 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_sep: power-controller@20400 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x20400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_venc_pipe: power-controller@21000 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x21000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe"; + power-domains = <&ps_venc>; + }; + + ps_venc_me0: power-controller@21008 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x21008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + power-domains = <&ps_venc>; + }; + + ps_venc_me1: power-controller@21010 { + compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x21010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + power-domains = <&ps_venc>; + }; +}; diff --git a/src/arm64/apple/t7001.dtsi b/src/arm64/apple/t7001.dtsi index a76e034c85e..8e2c67e19c4 100644 --- a/src/arm64/apple/t7001.dtsi +++ b/src/arm64/apple/t7001.dtsi @@ -35,6 +35,8 @@ compatible = "apple,typhoon"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled in by loader */ + performance-domains = <&cpufreq>; + operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -43,6 +45,8 @@ compatible = "apple,typhoon"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled in by loader */ + performance-domains = <&cpufreq>; + operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -51,11 +55,53 @@ compatible = "apple,typhoon"; reg = <0x0 0x2>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq>; + operating-points-v2 = <&typhoon_opp>; enable-method = "spin-table"; device_type = "cpu"; }; }; + typhoon_opp: opp-table { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <300>; + }; + opp02 { + opp-hz = /bits/ 64 <396000000>; + opp-level = <2>; + clock-latency-ns = <49000>; + }; + opp03 { + opp-hz = /bits/ 64 <600000000>; + opp-level = <3>; + clock-latency-ns = <31000>; + }; + opp04 { + opp-hz = /bits/ 64 <840000000>; + opp-level = <4>; + clock-latency-ns = <32000>; + }; + opp05 { + opp-hz = /bits/ 64 <1128000000>; + opp-level = <5>; + clock-latency-ns = <32000>; + }; + opp06 { + opp-hz = /bits/ 64 <1392000000>; + opp-level = <6>; + clock-latency-ns = <37000>; + }; + opp07 { + opp-hz = /bits/ 64 <1512000000>; + opp-level = <7>; + clock-latency-ns = <41000>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -63,6 +109,12 @@ nonposted-mmio; ranges; + cpufreq: performance-controller@202220000 { + compatible = "apple,t7000-cluster-cpufreq", "apple,s5l8960x-cluster-cpufreq"; + reg = <0x2 0x02220000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@20a0c0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0c0000 0x0 0x4000>; @@ -72,9 +124,18 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; + pmgr: power-management@20e000000 { + compatible = "apple,t7000-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x24000>; + }; + wdt: watchdog@20e027000 { compatible = "apple,t7000-wdt", "apple,wdt"; reg = <0x2 0x0e027000 0x0 0x1000>; @@ -88,11 +149,13 @@ reg = <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; + power-domains = <&ps_aic>; }; pinctrl: pinctrl@20e300000 { compatible = "apple,t7000-pinctrl", "apple,pinctrl"; reg = <0x2 0x0e300000 0x0 0x100000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -121,3 +184,5 @@ ; }; }; + +#include "t7001-pmgr.dtsi" diff --git a/src/arm64/apple/t8010-7.dtsi b/src/arm64/apple/t8010-7.dtsi index 1332fd73f50..1913b7b2c1f 100644 --- a/src/arm64/apple/t8010-7.dtsi +++ b/src/arm64/apple/t8010-7.dtsi @@ -41,3 +41,15 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0_fe &ps_disp0_be &ps_mipi_dsi>; +}; + +&hurricane_opp09 { + status = "okay"; +}; + +&hurricane_opp10 { + status = "okay"; +}; diff --git a/src/arm64/apple/t8010-common.dtsi b/src/arm64/apple/t8010-common.dtsi index 6613fb57c92..44dc968638b 100644 --- a/src/arm64/apple/t8010-common.dtsi +++ b/src/arm64/apple/t8010-common.dtsi @@ -43,6 +43,10 @@ }; }; +&dwi_bl { + status = "okay"; +}; + &serial0 { status = "okay"; }; diff --git a/src/arm64/apple/t8010-ipad6.dtsi b/src/arm64/apple/t8010-ipad6.dtsi index 81696c6e302..1e46e4a3a7f 100644 --- a/src/arm64/apple/t8010-ipad6.dtsi +++ b/src/arm64/apple/t8010-ipad6.dtsi @@ -42,3 +42,15 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0_fe &ps_disp0_be &ps_dp>; +}; + +&hurricane_opp09 { + status = "okay"; +}; + +&hurricane_opp10 { + status = "okay"; +}; diff --git a/src/arm64/apple/t8010-n112.dts b/src/arm64/apple/t8010-n112.dts index 6e71c3cb5d9..48fdbedf74d 100644 --- a/src/arm64/apple/t8010-n112.dts +++ b/src/arm64/apple/t8010-n112.dts @@ -45,3 +45,7 @@ }; }; }; + +&framebuffer0 { + power-domains = <&ps_disp0_fe &ps_disp0_be &ps_mipi_dsi>; +}; diff --git a/src/arm64/apple/t8010-pmgr.dtsi b/src/arm64/apple/t8010-pmgr.dtsi new file mode 100644 index 00000000000..6d451088616 --- /dev/null +++ b/src/arm64/apple/t8010-pmgr.dtsi @@ -0,0 +1,772 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8010 "A10" SoC + * + * Copyright (c) 2024 Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80160 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio_p: power-controller@80168 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + power-domains = <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pms: power-controller@80120 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_pcie_ref: power-controller@80148 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_socuvd: power-controller@80150 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "socuvd"; + }; + + ps_mca0: power-controller@80178 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@80180 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@80188 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@80190 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@80198 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@801a0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@801a8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801b0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801b8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801c0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@801c8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@801d0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@801d8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@801e0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@801e8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@801f0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@801f8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@80170 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@80128 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic0_phy"; + power-domains = <&ps_usb2host1>; + }; + + ps_isp_sens0: power-controller@80130 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80138 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens1"; + }; + + ps_isp_sens2: power-controller@80140 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens2"; + }; + + ps_usb: power-controller@80268 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@80270 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@80278 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@80288 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctrl>; + }; + + ps_rtmux: power-controller@802a8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "rtmux"; + }; + + ps_media: power-controller@802d8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp_sys: power-controller@802d0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sys"; + power-domains = <&ps_rtmux>; + }; + + ps_msr: power-controller@802e8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@802e0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0_fe: power-controller@802b0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_fe"; + power-domains = <&ps_rtmux>; + }; + + ps_disp0_be: power-controller@802b8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_be"; + power-domains = <&ps_disp0_fe>; + }; + + ps_pmp: power-controller@802f0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pms_sram: power-controller@802f8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_uart3: power-controller@80200 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@80208 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_uart5: power-controller@80210 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_uart6: power-controller@80218 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_uart7: power-controller@80220 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_sio_p>; + }; + + ps_uart8: power-controller@80228 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_sio_p>; + }; + + ps_hfd0: power-controller@80238 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hfd0"; + power-domains = <&ps_sio_p>; + }; + + ps_mcc: power-controller@80240 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80248 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80250 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80258 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80260 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_usb2host0_ohci: power-controller@80280 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@80290 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbotg"; + power-domains = <&ps_usbctrl>; + }; + + ps_smx: power-controller@80298 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802a0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mipi_dsi: power-controller@802c0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_disp0_be>; + }; + + ps_dp: power-controller@802c8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp"; + power-domains = <&ps_disp0_be>; + }; + + ps_venc_sys: power-controller@80310 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_sys"; + power-domains = <&ps_media>; + }; + + ps_pcie: power-controller@80318 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie"; + }; + + ps_pcie_aux: power-controller@80320 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_aux"; + }; + + ps_vdec0: power-controller@80300 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec0"; + power-domains = <&ps_media>; + }; + + ps_gfx: power-controller@80328 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_sep: power-controller@80400 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_isp_rsts0: power-controller@84000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts0"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_rsts1: power-controller@84008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts1"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_vis: power-controller@84010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_vis"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_be: power-controller@84018 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_be"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_pearl: power-controller@84020 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_pearl"; + power-domains = <&ps_isp_sys>; + }; + + ps_dprx: power-controller@84028 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dprx"; + power-domains = <&ps_isp_sys>; + }; + + ps_venc_pipe4: power-controller@88000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe4"; + power-domains = <&ps_venc_sys>; + }; + + ps_venc_pipe5: power-controller@88008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe5"; + power-domains = <&ps_venc_sys>; + }; + + ps_venc_me0: power-controller@88010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + }; + + ps_venc_me1: power-controller@88018 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop: power-controller@80000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop"; + power-domains = <&ps_aop_cpu &ps_aop_busif &ps_aop_filter>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_aop_gpio: power-controller@80010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_gpio"; + }; + + ps_aop_cpu: power-controller@80048 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80048 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_cpu"; + }; + + ps_aop_filter: power-controller@80050 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_filter"; + }; + + ps_aop_busif: power-controller@80058 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80058 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_busif"; + }; +}; diff --git a/src/arm64/apple/t8010.dtsi b/src/arm64/apple/t8010.dtsi index e3d6a835410..17e294bd7c4 100644 --- a/src/arm64/apple/t8010.dtsi +++ b/src/arm64/apple/t8010.dtsi @@ -32,6 +32,8 @@ compatible = "apple,hurricane-zephyr"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&fusion_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -40,11 +42,89 @@ compatible = "apple,hurricane-zephyr"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&fusion_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; }; + fusion_opp: opp-table { + compatible = "operating-points-v2"; + + /* + * Apple Fusion Architecture: Hardware big.LITTLE switcher + * that use p-state transitions to switch between cores. + * Only one type of core can be active at a given time. + * + * The E-core frequencies are adjusted so performance scales + * linearly with reported clock speed. + */ + + opp01 { + opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */ + opp-level = <1>; + clock-latency-ns = <11000>; + }; + opp02 { + opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */ + opp-level = <2>; + clock-latency-ns = <49000>; + }; + opp03 { + opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */ + opp-level = <3>; + clock-latency-ns = <13000>; + }; + opp04 { + opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */ + opp-level = <4>; + clock-latency-ns = <18000>; + }; + opp05 { + opp-hz = /bits/ 64 <756000000>; + opp-level = <5>; + clock-latency-ns = <35000>; + }; + opp06 { + opp-hz = /bits/ 64 <1056000000>; + opp-level = <6>; + clock-latency-ns = <31000>; + }; + opp07 { + opp-hz = /bits/ 64 <1356000000>; + opp-level = <7>; + clock-latency-ns = <37000>; + }; + opp08 { + opp-hz = /bits/ 64 <1644000000>; + opp-level = <8>; + clock-latency-ns = <39500>; + }; + hurricane_opp09: opp09 { + opp-hz = /bits/ 64 <1944000000>; + opp-level = <9>; + clock-latency-ns = <46000>; + status = "disabled"; /* Not available on N112 */ + }; + hurricane_opp10: opp10 { + opp-hz = /bits/ 64 <2244000000>; + opp-level = <10>; + clock-latency-ns = <56000>; + status = "disabled"; /* Not available on N112 */ + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + hurricane_opp11: opp11 { + opp-hz = /bits/ 64 <2340000000>; + opp-level = <11>; + clock-latency-ns = <56000>; + turbo-mode; + status = "disabled"; /* Not available on N112 */ + }; +#endif + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -52,6 +132,12 @@ nonposted-mmio; ranges; + cpufreq: performance-controller@202f20000 { + compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x02f20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@20a0c0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0c0000 0x0 0x4000>; @@ -61,19 +147,37 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; + pmgr: power-management@20e000000 { + compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x8c000>; + }; + aic: interrupt-controller@20e100000 { compatible = "apple,t8010-aic", "apple,aic"; reg = <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; + power-domains = <&ps_aic>; + }; + + dwi_bl: backlight@20e200080 { + compatible = "apple,t8010-dwi-bl", "apple,dwi-bl"; + reg = <0x2 0x0e200080 0x0 0x8>; + power-domains = <&ps_dwi>; + status = "disabled"; }; pinctrl_ap: pinctrl@20f100000 { compatible = "apple,t8010-pinctrl", "apple,pinctrl"; reg = <0x2 0x0f100000 0x0 0x100000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -95,6 +199,7 @@ pinctrl_aop: pinctrl@2100f0000 { compatible = "apple,t8010-pinctrl", "apple,pinctrl"; reg = <0x2 0x100f0000 0x0 0x100000>; + power-domains = <&ps_aop_gpio>; gpio-controller; #gpio-cells = <2>; @@ -113,6 +218,14 @@ ; }; + pmgr_mini: power-management@210200000 { + compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x10200000 0 0x84000>; + }; + wdt: watchdog@2102b0000 { compatible = "apple,t8010-wdt", "apple,wdt"; reg = <0x2 0x102b0000 0x0 0x4000>; @@ -131,3 +244,5 @@ ; }; }; + +#include "t8010-pmgr.dtsi" diff --git a/src/arm64/apple/t8011-common.dtsi b/src/arm64/apple/t8011-common.dtsi index 44a0d0ea2ee..2010b56246f 100644 --- a/src/arm64/apple/t8011-common.dtsi +++ b/src/arm64/apple/t8011-common.dtsi @@ -22,6 +22,7 @@ framebuffer0: framebuffer@0 { compatible = "apple,simple-framebuffer", "simple-framebuffer"; reg = <0 0 0 0>; /* To be filled by loader */ + power-domains = <&ps_disp0_fe &ps_disp0_be &ps_dp>; /* Format properties will be added by loader */ status = "disabled"; }; diff --git a/src/arm64/apple/t8011-pmgr.dtsi b/src/arm64/apple/t8011-pmgr.dtsi new file mode 100644 index 00000000000..c44e3f9d708 --- /dev/null +++ b/src/arm64/apple/t8011-pmgr.dtsi @@ -0,0 +1,806 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8011 "A10X" SoC + * + * Copyright (c) 2024 Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpu2: power-controller@80010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu2"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80158 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio_p: power-controller@80160 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + power-domains = <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pms: power-controller@80120 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_pcie_ref: power-controller@80148 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_mca0: power-controller@80170 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@80178 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@80180 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@80188 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@80190 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@80198 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@801a0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801a8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801b0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801b8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@801c0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@801c8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@801d0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@801d8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@801e0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@801e8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@801f0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_uart3: power-controller@801f8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@80168 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsic0_phy: power-controller@80128 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsic0_phy"; + power-domains = <&ps_usb3host>; + }; + + ps_isp_sens0: power-controller@80130 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80138 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens1"; + }; + + ps_isp_sens2: power-controller@80140 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens2"; + }; + + ps_usb: power-controller@80288 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@80290 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host: power-controller@80298 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2dev: power-controller@802a0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2dev"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb3host: power-controller@802a8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb3host"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb3dev: power-controller@802b0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb3dev"; + power-domains = <&ps_usbctrl>; + }; + + ps_media: power-controller@802e8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp_sys: power-controller@802e0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sys"; + }; + + ps_msr: power-controller@802f8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@802f0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0_fe: power-controller@802c8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_fe"; + }; + + ps_disp0_be: power-controller@802d0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_be"; + power-domains = <&ps_disp0_fe>; + }; + + ps_dpa: power-controller@80230 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@80200 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_uart5: power-controller@80208 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_uart6: power-controller@80210 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_uart7: power-controller@80218 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_sio_p>; + }; + + ps_uart8: power-controller@80220 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_sio_p>; + }; + + ps_hfd0: power-controller@80238 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hfd0"; + power-domains = <&ps_sio_p>; + }; + + ps_mcc: power-controller@80240 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80248 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80250 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80258 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80260 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs4: power-controller@80268 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs4"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs5: power-controller@80270 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs5"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs6: power-controller@80278 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs6"; + }; + + ps_dcs7: power-controller@80280 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs7"; + }; + + ps_smx: power-controller@802b8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802c0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_dp: power-controller@802d8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp"; + power-domains = <&ps_disp0_be>; + }; + + ps_venc_sys: power-controller@80320 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_sys"; + power-domains = <&ps_media>; + }; + + ps_srs: power-controller@80390 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80390 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "srs"; + power-domains = <&ps_media>; + }; + + ps_pms_sram: power-controller@80308 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_pmp: power-controller@80300 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pcie: power-controller@80328 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie"; + }; + + ps_pcie_aux: power-controller@80330 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_aux"; + }; + + ps_vdec0: power-controller@80310 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec0"; + power-domains = <&ps_media>; + }; + + ps_gfx: power-controller@80338 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_sep: power-controller@80400 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_isp_rsts0: power-controller@84000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts0"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_rsts1: power-controller@84008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts1"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_vis: power-controller@84010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_vis"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_be: power-controller@84018 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_be"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_pearl: power-controller@84020 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_pearl"; + power-domains = <&ps_isp_sys>; + }; + + ps_dprx: power-controller@84028 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dprx"; + power-domains = <&ps_isp_sys>; + }; + + ps_venc_pipe4: power-controller@88000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe4"; + power-domains = <&ps_venc_sys>; + }; + + ps_venc_pipe5: power-controller@88008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe5"; + power-domains = <&ps_venc_sys>; + }; + + ps_venc_me0: power-controller@88010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + }; + + ps_venc_me1: power-controller@88018 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop: power-controller@80000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop"; + power-domains = <&ps_aop_cpu &ps_aop_filter &ps_aop_busif>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_aop_gpio: power-controller@80010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_gpio"; + }; + + ps_aop_cpu: power-controller@80048 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80048 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_cpu"; + }; + + ps_aop_filter: power-controller@80050 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_filter"; + }; + + ps_aop_busif: power-controller@80058 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80058 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_busif"; + }; +}; diff --git a/src/arm64/apple/t8011-pro2.dtsi b/src/arm64/apple/t8011-pro2.dtsi index f4e70741500..5eaa0a73350 100644 --- a/src/arm64/apple/t8011-pro2.dtsi +++ b/src/arm64/apple/t8011-pro2.dtsi @@ -40,3 +40,11 @@ }; }; }; + +&ps_dcs6 { + apple,always-on; /* LPDDR4 interface */ +}; + +&ps_dcs7 { + apple,always-on; /* LPDDR4 interface */ +}; diff --git a/src/arm64/apple/t8011.dtsi b/src/arm64/apple/t8011.dtsi index 6c4ed9dc4a5..5b280c896b7 100644 --- a/src/arm64/apple/t8011.dtsi +++ b/src/arm64/apple/t8011.dtsi @@ -32,6 +32,8 @@ compatible = "apple,hurricane-zephyr"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&fusion_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -40,6 +42,8 @@ compatible = "apple,hurricane-zephyr"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&fusion_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -48,11 +52,80 @@ compatible = "apple,hurricane-zephyr"; reg = <0x0 0x2>; cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&fusion_opp>; + performance-domains = <&cpufreq>; enable-method = "spin-table"; device_type = "cpu"; }; }; + fusion_opp: opp-table { + compatible = "operating-points-v2"; + + /* + * Apple Fusion Architecture: Hardwired big.LITTLE switcher + * that use p-state transitions to switch between cores. + * + * The E-core frequencies are adjusted so performance scales + * linearly with reported clock speed. + */ + + opp01 { + opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */ + opp-level = <1>; + clock-latency-ns = <12000>; + }; + opp02 { + opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */ + opp-level = <2>; + clock-latency-ns = <135000>; + }; + opp03 { + opp-hz = /bits/ 64 <448000000>; /* 768 MHz, E-core */ + opp-level = <3>; + clock-latency-ns = <105000>; + }; + opp04 { + opp-hz = /bits/ 64 <662000000>; /* 1152 MHz, E-core */ + opp-level = <4>; + clock-latency-ns = <115000>; + }; + opp05 { + opp-hz = /bits/ 64 <804000000>; + opp-level = <5>; + clock-latency-ns = <122000>; + }; + opp06 { + opp-hz = /bits/ 64 <1140000000>; + opp-level = <6>; + clock-latency-ns = <120000>; + }; + opp07 { + opp-hz = /bits/ 64 <1548000000>; + opp-level = <7>; + clock-latency-ns = <125000>; + }; + opp08 { + opp-hz = /bits/ 64 <1956000000>; + opp-level = <8>; + clock-latency-ns = <135000>; + }; + opp09 { + opp-hz = /bits/ 64 <2316000000>; + opp-level = <9>; + clock-latency-ns = <140000>; + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp10 { + opp-hz = /bits/ 64 <2400000000>; + opp-level = <10>; + clock-latency-ns = <140000>; + turbo-mode; + }; +#endif + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -60,6 +133,12 @@ nonposted-mmio; ranges; + cpufreq: performance-controller@202f20000 { + compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x02f20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@20a0c0000 { compatible = "apple,s5l-uart"; reg = <0x2 0x0a0c0000 0x0 0x4000>; @@ -69,19 +148,30 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; + pmgr: power-management@20e000000 { + compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x8c000>; + }; + aic: interrupt-controller@20e100000 { compatible = "apple,t8010-aic", "apple,aic"; reg = <0x2 0x0e100000 0x0 0x100000>; #interrupt-cells = <3>; interrupt-controller; + power-domains = <&ps_aic>; }; pinctrl_ap: pinctrl@20f100000 { compatible = "apple,t8010-pinctrl", "apple,pinctrl"; reg = <0x2 0x0f100000 0x0 0x100000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -103,6 +193,7 @@ pinctrl_aop: pinctrl@2100f0000 { compatible = "apple,t8010-pinctrl", "apple,pinctrl"; reg = <0x2 0x100f0000 0x0 0x100000>; + power-domains = <&ps_aop_gpio>; gpio-controller; #gpio-cells = <2>; @@ -121,6 +212,14 @@ ; }; + pmgr_mini: power-management@210200000 { + compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x10200000 0 0x84000>; + }; + wdt: watchdog@2102b0000 { compatible = "apple,t8010-wdt", "apple,wdt"; reg = <0x2 0x102b0000 0x0 0x4000>; @@ -139,3 +238,5 @@ ; }; }; + +#include "t8011-pmgr.dtsi" diff --git a/src/arm64/apple/t8012-j132.dts b/src/arm64/apple/t8012-j132.dts new file mode 100644 index 00000000000..778a69be18d --- /dev/null +++ b/src/arm64/apple/t8012-j132.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro15,2 (j132), J132, iBridge2,4 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 MacBookPro15,2 (j132)"; + compatible = "apple,j132", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j137.dts b/src/arm64/apple/t8012-j137.dts new file mode 100644 index 00000000000..dbde1ad7ce1 --- /dev/null +++ b/src/arm64/apple/t8012-j137.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 iMacPro1,1 (j137), J137, iBridge2,1 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 iMacPro1,1 (j137)"; + compatible = "apple,j137", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j140a.dts b/src/arm64/apple/t8012-j140a.dts new file mode 100644 index 00000000000..5df1ff74d2d --- /dev/null +++ b/src/arm64/apple/t8012-j140a.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookAir8,2 (j140a), J140a, iBridge2,12 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 MacBookAir8,2 (j140a)"; + compatible = "apple,j140a", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j140k.dts b/src/arm64/apple/t8012-j140k.dts new file mode 100644 index 00000000000..a0ef1585e5c --- /dev/null +++ b/src/arm64/apple/t8012-j140k.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookAir8,1 (j140k), J140k, iBridge2,8 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 MacBookAir8,1 (j140k)"; + compatible = "apple,j140k", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j152f.dts b/src/arm64/apple/t8012-j152f.dts new file mode 100644 index 00000000000..261416eaf97 --- /dev/null +++ b/src/arm64/apple/t8012-j152f.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro16,1 (j152f), J152f, iBridge2,14 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model = "Apple T2 MacBookPro16,1 (j152f)"; + compatible = "apple,j152f", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j160.dts b/src/arm64/apple/t8012-j160.dts new file mode 100644 index 00000000000..fbcc0604f4a --- /dev/null +++ b/src/arm64/apple/t8012-j160.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacPro7,1 (j160), J160, iBridge2,6 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 MacPro7,1 (j160)"; + compatible = "apple,j160", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j174.dts b/src/arm64/apple/t8012-j174.dts new file mode 100644 index 00000000000..d11c70f84a7 --- /dev/null +++ b/src/arm64/apple/t8012-j174.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 Macmini8,1 (j174), J174, iBridge2,5 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 Macmini8,1 (j174)"; + compatible = "apple,j174", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j185.dts b/src/arm64/apple/t8012-j185.dts new file mode 100644 index 00000000000..33492f5db46 --- /dev/null +++ b/src/arm64/apple/t8012-j185.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 iMac20,1 (j185), J185, iBridge2,19 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 iMac20,1 (j185)"; + compatible = "apple,j185", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j185f.dts b/src/arm64/apple/t8012-j185f.dts new file mode 100644 index 00000000000..3a4abdd8f7d --- /dev/null +++ b/src/arm64/apple/t8012-j185f.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 iMac20,2 (j185f), J185f, iBridge2,20 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 iMac20,2 (j185f)"; + compatible = "apple,j185f", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j213.dts b/src/arm64/apple/t8012-j213.dts new file mode 100644 index 00000000000..8270812b9a6 --- /dev/null +++ b/src/arm64/apple/t8012-j213.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro15,4 (j213), J213, iBridge2,10 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model = "Apple T2 MacBookPro15,4 (j213)"; + compatible = "apple,j213", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j214k.dts b/src/arm64/apple/t8012-j214k.dts new file mode 100644 index 00000000000..5b8e4251206 --- /dev/null +++ b/src/arm64/apple/t8012-j214k.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro16,2 (j214k), J214k, iBridge2,16 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model = "Apple T2 MacBookPro16,2 (j214k)"; + compatible = "apple,j214k", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j215.dts b/src/arm64/apple/t8012-j215.dts new file mode 100644 index 00000000000..ad574fbf7f9 --- /dev/null +++ b/src/arm64/apple/t8012-j215.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro16,4 (j215), J215, iBridge2,22 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model = "Apple T2 MacBookPro16,4 (j215)"; + compatible = "apple,j215", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j223.dts b/src/arm64/apple/t8012-j223.dts new file mode 100644 index 00000000000..de75d775aac --- /dev/null +++ b/src/arm64/apple/t8012-j223.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro16,3 (j223), J223, iBridge2,21 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model = "Apple T2 MacBookPro16,3 (j223)"; + compatible = "apple,j223", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j230k.dts b/src/arm64/apple/t8012-j230k.dts new file mode 100644 index 00000000000..4b19bc70ab0 --- /dev/null +++ b/src/arm64/apple/t8012-j230k.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookAir9,1 (j230k), J230k, iBridge2,15 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" + +/ { + model = "Apple T2 MacBookAir9,1 (j230k)"; + compatible = "apple,j230k", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j680.dts b/src/arm64/apple/t8012-j680.dts new file mode 100644 index 00000000000..aa5a72e07d3 --- /dev/null +++ b/src/arm64/apple/t8012-j680.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro15,1 (j680), J680, iBridge2,3 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model = "Apple T2 MacBookPro15,1 (j680)"; + compatible = "apple,j680", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-j780.dts b/src/arm64/apple/t8012-j780.dts new file mode 100644 index 00000000000..9cee891cb16 --- /dev/null +++ b/src/arm64/apple/t8012-j780.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T2 MacBookPro15,3 (j780), J780, iBridge2,7 + * Copyright (c) 2024, Nick Chan + */ + +/dts-v1/; + +#include "t8012-jxxx.dtsi" +#include "t8012-touchbar.dtsi" + +/ { + model = "Apple T2 MacBookPro15,3 (j780)"; + compatible = "apple,j780", "apple,t8012", "apple,arm-platform"; +}; diff --git a/src/arm64/apple/t8012-jxxx.dtsi b/src/arm64/apple/t8012-jxxx.dtsi new file mode 100644 index 00000000000..36e82633bc5 --- /dev/null +++ b/src/arm64/apple/t8012-jxxx.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Common Device Tree for all T2 devices + * + * target-type: J132, J137, J140a, J140k, J152f, J160, J174, J185, J185f + * J213, J214k, J215, J223, J230k, J680, J780 + * + * Copyright (c) 2024, Nick Chan + */ + +#include "t8012.dtsi" + +/ { + chassis-type = "embedded"; + + aliases { + serial0 = &serial0; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + stdout-path = "serial0"; + }; + + memory@800000000 { + device_type = "memory"; + reg = <0x8 0 0 0>; /* To be filled by loader */ + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* To be filled by loader */ + }; +}; + +&serial0 { + status = "okay"; +}; diff --git a/src/arm64/apple/t8012-pmgr.dtsi b/src/arm64/apple/t8012-pmgr.dtsi new file mode 100644 index 00000000000..35a462edd4a --- /dev/null +++ b/src/arm64/apple/t8012-pmgr.dtsi @@ -0,0 +1,837 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8012 "T2" SoC + * + * Copyright (c) 2024 Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80158 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio_p: power-controller@80160 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + power-domains = <&ps_sio_busif>; + }; + + ps_iomux: power-controller@80150 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80150 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "iomux"; + }; + + ps_sbr: power-controller@80100 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_gpio: power-controller@80110 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pcie_down_ref: power-controller@80138 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_down_ref"; + }; + + ps_pcie_stg0_ref: power-controller@80140 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_stg0_ref"; + }; + + ps_pcie_stg1_ref: power-controller@80148 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_stg1_ref"; + }; + + ps_mca0: power-controller@80170 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@80178 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@80180 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@80188 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@80190 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_mca5: power-controller@80198 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca5"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@801a8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801b0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801b8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801c0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@801e0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@801e8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@801f0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@801f8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@801a0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@80168 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_isp_sens0: power-controller@80120 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens0"; + }; + + ps_isp_sens1: power-controller@80128 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens1"; + }; + + ps_isp_sens2: power-controller@80130 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sens2"; + }; + + ps_pms: power-controller@80118 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_i2c4: power-controller@801c8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c4"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c5: power-controller@801d0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c5"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c6: power-controller@801d8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c6"; + power-domains = <&ps_sio_p>; + }; + + ps_usb: power-controller@80268 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctrl: power-controller@80270 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctrl"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@80278 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctrl>; + }; + + ps_usb2host1: power-controller@80288 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctrl>; + }; + + ps_rtmux: power-controller@802a8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "rtmux"; + }; + + ps_media: power-controller@802d8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_isp_sys: power-controller@802d0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sys"; + power-domains = <&ps_rtmux>; + }; + + ps_msr: power-controller@802e8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_jpg: power-controller@802e0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0_fe: power-controller@802b0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_fe"; + power-domains = <&ps_rtmux>; + }; + + ps_disp0_be: power-controller@802b8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_be"; + power-domains = <&ps_disp0_fe>; + }; + + ps_uart0: power-controller@80200 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@80208 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@80210 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_uart3: power-controller@80218 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@80220 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_dpa: power-controller@80228 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa"; + power-domains = <&ps_sio_p>; + }; + + ps_hfd0: power-controller@80230 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hfd0"; + power-domains = <&ps_sio_p>; + }; + + ps_mcc: power-controller@80240 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80240 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80248 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs1: power-controller@80250 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs2: power-controller@80258 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + /* Not used on some devicecs, to be disabled by loader */ + apple,always-on; /* LPDDR4 interface */ + }; + + ps_dcs3: power-controller@80260 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + /* Not used on some devicecs, to be disabled by loader */ + apple,always-on; /* LPDDR4 interface */ + }; + + ps_usb2host0_ohci: power-controller@80280 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usbotg: power-controller@80290 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbotg"; + power-domains = <&ps_usbctrl>; + }; + + ps_smx: power-controller@80298 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802a0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mipi_dsi: power-controller@802c8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_disp0_be>; + }; + + ps_pmp: power-controller@802f0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pms_sram: power-controller@802f8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_pcie_up_af: power-controller@80320 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_up_af"; + power-domains = <&ps_iomux>; + }; + + ps_pcie_up: power-controller@80328 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_up"; + power-domains = <&ps_pcie_up_af>; + }; + + ps_venc_sys: power-controller@80300 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_sys"; + power-domains = <&ps_media>; + }; + + ps_ans2: power-controller@80308 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans2"; + power-domains = <&ps_iomux>; + }; + + ps_pcie_down: power-controller@80310 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_down"; + power-domains = <&ps_iomux>; + }; + + ps_pcie_down_aux: power-controller@80318 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_down_aux"; + }; + + ps_pcie_up_aux: power-controller@80330 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_up_aux"; + power-domains = <&ps_pcie_up>; + }; + + ps_pcie_stg0: power-controller@80338 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_stg0"; + power-domains = <&ps_ans2>; + }; + + ps_pcie_stg0_aux: power-controller@80340 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80340 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_stg0_aux"; + }; + + ps_pcie_stg1: power-controller@80348 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80348 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_stg1"; + power-domains = <&ps_ans2>; + }; + + ps_pcie_stg1_aux: power-controller@80350 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_stg1_aux"; + }; + + ps_sep: power-controller@80400 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_isp_rsts0: power-controller@84000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts0"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_rsts1: power-controller@84008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts1"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_vis: power-controller@84010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_vis"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_be: power-controller@84018 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_be"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_pearl: power-controller@84020 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_pearl"; + power-domains = <&ps_isp_sys>; + }; + + ps_venc_pipe4: power-controller@88000 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe4"; + }; + + ps_venc_pipe5: power-controller@88008 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe5"; + }; + + ps_venc_me0: power-controller@88010 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + }; + + ps_venc_me1: power-controller@88018 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + }; +}; + +&pmgr_mini { + ps_spmi: power-controller@80058 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80058 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spmi"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_aon: power-controller@80060 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80060 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_aon"; + apple,always-on; /* Core AON device */ + }; + + ps_smc_fabric: power-controller@80030 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80030 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smc_fabric"; + apple,always-on; /* Core AON device */ + }; + + ps_smc_aon: power-controller@80088 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80088 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smc_aon"; + apple,always-on; /* Core AON device */ + }; + + ps_debug: power-controller@80050 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_nub_sram: power-controller@801a0 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_sram"; + apple,always-on; /* Core AON device */ + }; + + ps_nub_fabric: power-controller@80198 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "nub_fabric"; + apple,always-on; /* Core AON device */ + }; + + ps_smc_cpu: power-controller@801a8 { + compatible = "apple,t8010-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smc_cpu"; + power-domains = <&ps_smc_fabric &ps_smc_aon>; + }; +}; diff --git a/src/arm64/apple/t8012-touchbar.dtsi b/src/arm64/apple/t8012-touchbar.dtsi new file mode 100644 index 00000000000..fc4a80d0c78 --- /dev/null +++ b/src/arm64/apple/t8012-touchbar.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Common Device Tree for T2 devices with a Touch Bar + * + * target-type: J152f, J213, J214k, J215, J223, J680, J780 + * + * Copyright (c) 2024, Nick Chan + */ + +/ { + chosen { + framebuffer0: framebuffer@0 { + compatible = "apple,simple-framebuffer", "simple-framebuffer"; + reg = <0 0 0 0>; /* To be filled by loader */ + power-domains = <&ps_disp0_fe &ps_disp0_be &ps_mipi_dsi>; + /* Format properties will be added by loader */ + status = "disabled"; + }; + }; +}; diff --git a/src/arm64/apple/t8012.dtsi b/src/arm64/apple/t8012.dtsi new file mode 100644 index 00000000000..42df2f51ad7 --- /dev/null +++ b/src/arm64/apple/t8012.dtsi @@ -0,0 +1,281 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Apple T8012 "T2" SoC + * + * Other names: H9M, "Gibraltar" + * + * Copyright (c) 2024, Nick Chan + */ + +#include +#include +#include +#include + +/ { + interrupt-parent = <&aic>; + #address-cells = <2>; + #size-cells = <2>; + + clkref: clock-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "clkref"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@10000 { + compatible = "apple,hurricane-zephyr"; + reg = <0x0 0x10000>; + cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&fusion_opp>; + performance-domains = <&cpufreq>; + enable-method = "spin-table"; + device_type = "cpu"; + }; + + cpu1: cpu@10001 { + compatible = "apple,hurricane-zephyr"; + reg = <0x0 0x10001>; + cpu-release-addr = <0 0>; /* To be filled by loader */ + operating-points-v2 = <&fusion_opp>; + performance-domains = <&cpufreq>; + enable-method = "spin-table"; + device_type = "cpu"; + }; + }; + + fusion_opp: opp-table { + compatible = "operating-points-v2"; + + /* + * Apple Fusion Architecture: Hardware big.LITTLE switcher + * that use p-state transitions to switch between cores. + * Only one type of core can be active at a given time. + * + * The E-core frequencies are adjusted so performance scales + * linearly with reported clock speed. + */ + + opp01 { + opp-hz = /bits/ 64 <172000000>; /* 300 MHz, E-core */ + opp-level = <1>; + clock-latency-ns = <11000>; + }; + opp02 { + opp-hz = /bits/ 64 <230000000>; /* 396 MHz, E-core */ + opp-level = <2>; + clock-latency-ns = <140000>; + }; + opp03 { + opp-hz = /bits/ 64 <425000000>; /* 732 MHz, E-core */ + opp-level = <3>; + clock-latency-ns = <110000>; + }; + opp04 { + opp-hz = /bits/ 64 <637000000>; /* 1092 MHz, E-core */ + opp-level = <4>; + clock-latency-ns = <130000>; + }; + opp05 { + opp-hz = /bits/ 64 <756000000>; + opp-level = <5>; + clock-latency-ns = <130000>; + }; + opp06 { + opp-hz = /bits/ 64 <1056000000>; + opp-level = <6>; + clock-latency-ns = <130000>; + }; + opp07 { + opp-hz = /bits/ 64 <1356000000>; + opp-level = <7>; + clock-latency-ns = <130000>; + }; + opp08 { + opp-hz = /bits/ 64 <1644000000>; + opp-level = <8>; + clock-latency-ns = <135000>; + }; + opp09 { + opp-hz = /bits/ 64 <1944000000>; + opp-level = <9>; + clock-latency-ns = <140000>; + }; + opp10 { + opp-hz = /bits/ 64 <2244000000>; + opp-level = <10>; + clock-latency-ns = <150000>; + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp11 { + opp-hz = /bits/ 64 <2340000000>; + opp-level = <11>; + clock-latency-ns = <150000>; + turbo-mode; + }; +#endif + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + nonposted-mmio; + ranges; + + cpufreq: performance-controller@202f20000 { + compatible = "apple,t8010-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x02f20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + serial0: serial@20a600000 { + compatible = "apple,s5l-uart"; + reg = <0x2 0x0a600000 0x0 0x4000>; + reg-io-width = <4>; + interrupt-parent = <&aic>; + interrupts = ; + /* Use the bootloader-enabled clocks for now. */ + clocks = <&clkref>, <&clkref>; + clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; + status = "disabled"; + }; + + pmgr: power-management@20e000000 { + compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0xe000000 0 0x8c000>; + }; + + aic: interrupt-controller@20e100000 { + compatible = "apple,t8010-aic", "apple,aic"; + reg = <0x2 0x0e100000 0x0 0x100000>; + #interrupt-cells = <3>; + interrupt-controller; + power-domains = <&ps_aic>; + }; + + pinctrl_ap: pinctrl@20f100000 { + compatible = "apple,t8010-pinctrl", "apple,pinctrl"; + reg = <0x2 0x0f100000 0x0 0x100000>; + power-domains = <&ps_gpio>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_ap 0 0 221>; + apple,npins = <221>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + pinctrl_aop: pinctrl@2100f0000 { + compatible = "apple,t8010-pinctrl", "apple,pinctrl"; + reg = <0x2 0x0100f0000 0x0 0x10000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aop 0 0 41>; + apple,npins = <41>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + }; + + pinctrl_nub: pinctrl@2111f0000 { + compatible = "apple,t8010-pinctrl", "apple,pinctrl"; + reg = <0x2 0x111f0000 0x0 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_nub 0 0 19>; + apple,npins = <19>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + ; + }; + + pmgr_mini: power-management@211200000 { + compatible = "apple,t8010-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x11200000 0 0x84000>; + }; + + wdt: watchdog@2112b0000 { + compatible = "apple,t8010-wdt", "apple,wdt"; + reg = <0x2 0x112b0000 0x0 0x4000>; + clocks = <&clkref>; + interrupt-parent = <&aic>; + interrupts = ; + }; + + pinctrl_smc: pinctrl@212024000 { + compatible = "apple,t8010-pinctrl", "apple,pinctrl"; + reg = <0x2 0x12024000 0x0 0x1000>; + power-domains = <&ps_smc_cpu>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_smc 0 0 81>; + apple,npins = <81>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&aic>; + interrupts = , + , + , + , + , + , + ; + /* + * SMC is not yet supported and accessing this pinctrl while SMC is + * suspended results in a hang. + */ + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&aic>; + interrupt-names = "phys", "virt"; + /* Note that T2 doesn't actually have a hypervisor (EL2 is not implemented). */ + interrupts = , + ; + }; +}; + +#include "t8012-pmgr.dtsi" diff --git a/src/arm64/apple/t8015-8.dtsi b/src/arm64/apple/t8015-8.dtsi index b6505b5185b..0300ee1a2ff 100644 --- a/src/arm64/apple/t8015-8.dtsi +++ b/src/arm64/apple/t8015-8.dtsi @@ -11,3 +11,7 @@ / { chassis-type = "handset"; }; + +&dwi_bl { + status = "okay"; +}; diff --git a/src/arm64/apple/t8015-common.dtsi b/src/arm64/apple/t8015-common.dtsi index 69258a33ea5..498f58fb971 100644 --- a/src/arm64/apple/t8015-common.dtsi +++ b/src/arm64/apple/t8015-common.dtsi @@ -24,6 +24,7 @@ framebuffer0: framebuffer@0 { compatible = "apple,simple-framebuffer", "simple-framebuffer"; reg = <0 0 0 0>; /* To be filled by loader */ + power-domains = <&ps_disp0_be &ps_mipi_dsi &ps_disp0_hilo &ps_disp0_ppp>; /* Format properties will be added by loader */ status = "disabled"; }; diff --git a/src/arm64/apple/t8015-pmgr.dtsi b/src/arm64/apple/t8015-pmgr.dtsi new file mode 100644 index 00000000000..e238c2d2732 --- /dev/null +++ b/src/arm64/apple/t8015-pmgr.dtsi @@ -0,0 +1,931 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * PMGR Power domains for the Apple T8015 "A11" SoC + * + * Copyright (c) 2024, Nick Chan + */ + +&pmgr { + ps_cpu0: power-controller@80000 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu0"; + apple,always-on; /* Core device */ + }; + + ps_cpu1: power-controller@80008 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu1"; + apple,always-on; /* Core device */ + }; + + ps_cpu2: power-controller@80010 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu2"; + apple,always-on; /* Core device */ + }; + + ps_cpu3: power-controller@80018 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu3"; + apple,always-on; /* Core device */ + }; + + ps_cpu4: power-controller@80020 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu4"; + apple,always-on; /* Core device */ + }; + + ps_cpu5: power-controller@80028 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpu5"; + apple,always-on; /* Core device */ + }; + + ps_cpm: power-controller@80040 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80040 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "cpm"; + apple,always-on; /* Core device */ + }; + + ps_sio_busif: power-controller@80158 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80158 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_busif"; + }; + + ps_sio_p: power-controller@80160 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80160 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio_p"; + power-domains = <&ps_sio_busif>; + }; + + ps_sbr: power-controller@80100 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80100 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sbr"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_aic: power-controller@80108 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80108 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aic"; + apple,always-on; /* Core device */ + }; + + ps_dwi: power-controller@80110 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80110 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dwi"; + }; + + ps_gpio: power-controller@80118 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80118 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gpio"; + }; + + ps_pms: power-controller@80120 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80120 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms"; + apple,always-on; /* Core device */ + }; + + ps_pcie_ref: power-controller@80148 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80148 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_ref"; + }; + + ps_mca0: power-controller@80170 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80170 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca0"; + power-domains = <&ps_sio_p>; + }; + + ps_mca1: power-controller@80178 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80178 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca1"; + power-domains = <&ps_sio_p>; + }; + + ps_mca2: power-controller@80180 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80180 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca2"; + power-domains = <&ps_sio_p>; + }; + + ps_mca3: power-controller@80188 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80188 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca3"; + power-domains = <&ps_sio_p>; + }; + + ps_mca4: power-controller@80190 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80190 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca4"; + power-domains = <&ps_sio_p>; + }; + + ps_pwm0: power-controller@801a0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pwm0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c0: power-controller@801a8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c0"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c1: power-controller@801b0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c1"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c2: power-controller@801b8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c2"; + power-domains = <&ps_sio_p>; + }; + + ps_i2c3: power-controller@801c0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "i2c3"; + power-domains = <&ps_sio_p>; + }; + + ps_spi0: power-controller@801c8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi0"; + power-domains = <&ps_sio_p>; + }; + + ps_spi1: power-controller@801d0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi1"; + power-domains = <&ps_sio_p>; + }; + + ps_spi2: power-controller@801d8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi2"; + power-domains = <&ps_sio_p>; + }; + + ps_spi3: power-controller@801e0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart0: power-controller@801e8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801e8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart0"; + power-domains = <&ps_sio_p>; + }; + + ps_uart1: power-controller@801f0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart1"; + power-domains = <&ps_sio_p>; + }; + + ps_uart2: power-controller@801f8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x801f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart2"; + power-domains = <&ps_sio_p>; + }; + + ps_sio: power-controller@80168 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80168 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sio"; + power-domains = <&ps_sio_p>; + apple,always-on; /* Core device */ + }; + + ps_hsicphy: power-controller@80128 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80128 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hsicphy"; + power-domains = <&ps_usb2host1>; + }; + + ps_ispsens0: power-controller@80130 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80130 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens0"; + }; + + ps_ispsens1: power-controller@80138 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80138 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens1"; + }; + + ps_ispsens2: power-controller@80140 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ispsens2"; + }; + + ps_mca5: power-controller@80198 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80198 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mca5"; + power-domains = <&ps_sio_p>; + }; + + ps_usb: power-controller@80270 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80270 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb"; + }; + + ps_usbctlreg: power-controller@80278 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80278 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usbctlreg"; + power-domains = <&ps_usb>; + }; + + ps_usb2host0: power-controller@80280 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80280 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0"; + power-domains = <&ps_usbctlreg>; + }; + + ps_usb2host1: power-controller@80290 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80290 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host1"; + power-domains = <&ps_usbctlreg>; + }; + + ps_rtmux: power-controller@802b0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "rtmux"; + }; + + ps_media: power-controller@802f0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "media"; + }; + + ps_jpg: power-controller@802f8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802f8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "jpg"; + power-domains = <&ps_media>; + }; + + ps_disp0_fe: power-controller@802b8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802b8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_fe"; + power-domains = <&ps_rtmux>; + }; + + ps_disp0_be: power-controller@802c0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_be"; + power-domains = <&ps_disp0_fe>; + }; + + ps_disp0_gp: power-controller@802c8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802c8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_gp"; + power-domains = <&ps_disp0_be>; + status = "disabled"; + }; + + ps_uart3: power-controller@80200 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80200 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart3"; + power-domains = <&ps_sio_p>; + }; + + ps_uart4: power-controller@80208 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80208 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart4"; + power-domains = <&ps_sio_p>; + }; + + ps_uart5: power-controller@80210 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80210 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart5"; + power-domains = <&ps_sio_p>; + }; + + ps_uart6: power-controller@80218 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80218 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart6"; + power-domains = <&ps_sio_p>; + }; + + ps_uart7: power-controller@80220 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80220 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart7"; + power-domains = <&ps_sio_p>; + }; + + ps_uart8: power-controller@80228 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80228 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "uart8"; + power-domains = <&ps_sio_p>; + }; + + ps_hfd0: power-controller@80238 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80238 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "hfd0"; + power-domains = <&ps_sio_p>; + }; + + ps_mcc: power-controller@80248 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80248 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mcc"; + apple,always-on; /* Memory cache controller */ + }; + + ps_dcs0: power-controller@80250 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80250 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs0"; + apple,always-on; /* LPDDR4X interface */ + }; + + ps_dcs1: power-controller@80258 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80258 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs1"; + apple,always-on; /* LPDDR4X interface */ + }; + + ps_dcs2: power-controller@80260 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs2"; + apple,always-on; /* LPDDR4X interface */ + }; + + ps_dcs3: power-controller@80268 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80268 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dcs3"; + apple,always-on; /* LPDDR4X interface */ + }; + + ps_usb2host0_ohci: power-controller@80288 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80288 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2host0_ohci"; + power-domains = <&ps_usb2host0>; + }; + + ps_usb2dev: power-controller@80298 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80298 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "usb2dev"; + power-domains = <&ps_usbctlreg>; + }; + + ps_smx: power-controller@802a0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smx"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_sf: power-controller@802a8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sf"; + apple,always-on; /* Apple fabric, critical block */ + }; + + ps_mipi_dsi: power-controller@802d8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "mipi_dsi"; + power-domains = <&ps_rtmux>; + }; + + ps_dp: power-controller@802e0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802e0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dp"; + power-domains = <&ps_disp0_be>; + }; + + ps_dpa: power-controller@80230 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80230 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dpa"; + }; + + ps_disp0_be_2x: power-controller@802d0 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x802d0 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_be_2x"; + power-domains = <&ps_disp0_be>; + }; + + ps_isp_sys: power-controller@80350 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80350 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_sys"; + power-domains = <&ps_rtmux>; + }; + + ps_msr: power-controller@80300 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80300 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "msr"; + power-domains = <&ps_media>; + }; + + ps_venc_sys: power-controller@80398 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80398 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_sys"; + power-domains = <&ps_media>; + }; + + ps_pmp: power-controller@80308 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80308 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pmp"; + }; + + ps_pms_sram: power-controller@80310 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80310 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pms_sram"; + }; + + ps_pcie: power-controller@80318 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80318 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie"; + }; + + ps_pcie_aux: power-controller@80320 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80320 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_aux"; + }; + + ps_vdec0: power-controller@80388 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80388 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "vdec0"; + power-domains = <&ps_media>; + }; + + ps_gfx: power-controller@80338 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80338 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "gfx"; + }; + + ps_ans2: power-controller@80328 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80328 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "ans2"; + apple,always-on; + }; + + ps_pcie_direct: power-controller@80330 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80330 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "pcie_direct"; + apple,always-on; + }; + + ps_avd_sys: power-controller@803a8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x803a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "avd_sys"; + power-domains = <&ps_media>; + }; + + ps_sep: power-controller@80400 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80400 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "sep"; + apple,always-on; /* Locked on */ + }; + + ps_disp0_gp0: power-controller@80830 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80830 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_gp0"; + power-domains = <&ps_disp0_gp>; + status = "disabled"; + }; + + ps_disp0_gp1: power-controller@80838 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80838 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_gp1"; + status = "disabled"; + }; + + ps_disp0_ppp: power-controller@80840 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80840 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_ppp"; + }; + + ps_disp0_hilo: power-controller@80848 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80848 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "disp0_hilo"; + }; + + ps_isp_rsts0: power-controller@84000 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts0"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_rsts1: power-controller@84008 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_rsts1"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_vis: power-controller@84010 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_vis"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_be: power-controller@84018 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_be"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_pearl: power-controller@84020 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_pearl"; + power-domains = <&ps_isp_sys>; + }; + + ps_dprx: power-controller@84028 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "dprx"; + power-domains = <&ps_isp_sys>; + }; + + ps_isp_cnv: power-controller@84030 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x84030 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "isp_cnv"; + power-domains = <&ps_isp_sys>; + }; + + ps_venc_dma: power-controller@88000 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_dma"; + }; + + ps_venc_pipe4: power-controller@88010 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88010 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe4"; + }; + + ps_venc_pipe5: power-controller@88018 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88018 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_pipe5"; + }; + + ps_venc_me0: power-controller@88020 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me0"; + }; + + ps_venc_me1: power-controller@88028 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x88028 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "venc_me1"; + }; +}; + +&pmgr_mini { + ps_aop_base: power-controller@80008 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80008 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_base"; + power-domains = <&ps_aop_cpu &ps_aop_filter>; + apple,always-on; /* Always on processor */ + }; + + ps_debug: power-controller@80050 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80050 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "debug"; + }; + + ps_aop_cpu: power-controller@80020 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80020 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_cpu"; + }; + + ps_aop_filter: power-controller@80000 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80000 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "aop_filter"; + }; + + ps_spmi: power-controller@80058 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80058 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spmi"; + apple,always-on; /* System Power Management Interface */ + }; + + ps_smc_i2cm1: power-controller@800a8 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x800a8 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smc_i2cm1"; + }; + + ps_smc_fabric: power-controller@80030 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80030 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smc_fabric"; + }; + + ps_smc_cpu: power-controller@80140 { + compatible = "apple,t8015-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x80140 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "smc_cpu"; + power-domains = <&ps_smc_fabric &ps_smc_i2cm1>; + }; +}; diff --git a/src/arm64/apple/t8015.dtsi b/src/arm64/apple/t8015.dtsi index 8828d830e5b..4d54afcecd5 100644 --- a/src/arm64/apple/t8015.dtsi +++ b/src/arm64/apple/t8015.dtsi @@ -58,6 +58,9 @@ compatible = "apple,mistral"; reg = <0x0 0x0>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq_e>; + operating-points-v2 = <&mistral_opp>; + capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -66,6 +69,9 @@ compatible = "apple,mistral"; reg = <0x0 0x1>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq_e>; + operating-points-v2 = <&mistral_opp>; + capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -74,6 +80,9 @@ compatible = "apple,mistral"; reg = <0x0 0x2>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq_e>; + operating-points-v2 = <&mistral_opp>; + capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -82,6 +91,9 @@ compatible = "apple,mistral"; reg = <0x0 0x3>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq_e>; + operating-points-v2 = <&mistral_opp>; + capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -90,6 +102,9 @@ compatible = "apple,monsoon"; reg = <0x0 0x10004>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq_p>; + operating-points-v2 = <&monsoon_opp>; + capacity-dmips-mhz = <1024>; enable-method = "spin-table"; device_type = "cpu"; }; @@ -98,11 +113,107 @@ compatible = "apple,monsoon"; reg = <0x0 0x10005>; cpu-release-addr = <0 0>; /* To be filled by loader */ + performance-domains = <&cpufreq_p>; + operating-points-v2 = <&monsoon_opp>; + capacity-dmips-mhz = <1024>; enable-method = "spin-table"; device_type = "cpu"; }; }; + mistral_opp: opp-table-0 { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <1800>; + }; + opp02 { + opp-hz = /bits/ 64 <453000000>; + opp-level = <2>; + clock-latency-ns = <140000>; + }; + opp03 { + opp-hz = /bits/ 64 <672000000>; + opp-level = <3>; + clock-latency-ns = <105000>; + }; + opp04 { + opp-hz = /bits/ 64 <972000000>; + opp-level = <4>; + clock-latency-ns = <115000>; + }; + opp05 { + opp-hz = /bits/ 64 <1272000000>; + opp-level = <5>; + clock-latency-ns = <125000>; + }; + opp06 { + opp-hz = /bits/ 64 <1572000000>; + opp-level = <6>; + clock-latency-ns = <135000>; + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp07 { + opp-hz = /bits/ 64 <1680000000>; + opp-level = <7>; + clock-latency-ns = <135000>; + turbo-mode; + }; +#endif + }; + + monsoon_opp: opp-table-1 { + compatible = "operating-points-v2"; + + opp01 { + opp-hz = /bits/ 64 <300000000>; + opp-level = <1>; + clock-latency-ns = <1400>; + }; + opp02 { + opp-hz = /bits/ 64 <453000000>; + opp-level = <2>; + clock-latency-ns = <140000>; + }; + opp03 { + opp-hz = /bits/ 64 <853000000>; + opp-level = <3>; + clock-latency-ns = <110000>; + }; + opp04 { + opp-hz = /bits/ 64 <1332000000>; + opp-level = <4>; + clock-latency-ns = <110000>; + }; + opp05 { + opp-hz = /bits/ 64 <1812000000>; + opp-level = <5>; + clock-latency-ns = <125000>; + }; + opp06 { + opp-hz = /bits/ 64 <2064000000>; + opp-level = <6>; + clock-latency-ns = <130000>; + }; + opp07 { + opp-hz = /bits/ 64 <2304000000>; + opp-level = <7>; + clock-latency-ns = <140000>; + }; +#if 0 + /* Not available until CPU deep sleep is implemented */ + opp08 { + opp-hz = /bits/ 64 <2376000000>; + opp-level = <8>; + clock-latency-ns = <140000>; + turbo-mode; + }; +#endif + }; + soc { compatible = "simple-bus"; #address-cells = <2>; @@ -110,6 +221,18 @@ nonposted-mmio; ranges; + cpufreq_e: performance-controller@208e20000 { + compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x08e20000 0 0x1000>; + #performance-domain-cells = <0>; + }; + + cpufreq_p: performance-controller@208ea0000 { + compatible = "apple,t8015-cluster-cpufreq", "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq"; + reg = <0x2 0x08ea0000 0 0x1000>; + #performance-domain-cells = <0>; + }; + serial0: serial@22e600000 { compatible = "apple,s5l-uart"; reg = <0x2 0x2e600000 0x0 0x4000>; @@ -119,6 +242,7 @@ /* Use the bootloader-enabled clocks for now. */ clocks = <&clkref>, <&clkref>; clock-names = "uart", "clk_uart_baud0"; + power-domains = <&ps_uart0>; status = "disabled"; }; @@ -127,11 +251,28 @@ reg = <0x2 0x32100000 0x0 0x8000>; #interrupt-cells = <3>; interrupt-controller; + power-domains = <&ps_aic>; + }; + + pmgr: power-management@232000000 { + compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x32000000 0 0x8c000>; + }; + + dwi_bl: backlight@232200080 { + compatible = "apple,t8015-dwi-bl", "apple,dwi-bl"; + reg = <0x2 0x32200080 0x0 0x8>; + power-domains = <&ps_dwi>; + status = "disabled"; }; pinctrl_ap: pinctrl@233100000 { compatible = "apple,t8015-pinctrl", "apple,pinctrl"; reg = <0x2 0x33100000 0x0 0x1000>; + power-domains = <&ps_gpio>; gpio-controller; #gpio-cells = <2>; @@ -188,6 +329,14 @@ ; }; + pmgr_mini: power-management@235200000 { + compatible = "apple,t8015-pmgr", "apple,pmgr", "syscon", "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + + reg = <0x2 0x35200000 0 0x84000>; + }; + wdt: watchdog@2352b0000 { compatible = "apple,t8015-wdt", "apple,wdt"; reg = <0x2 0x352b0000 0x0 0x4000>; @@ -232,3 +381,5 @@ ; }; }; + +#include "t8015-pmgr.dtsi" diff --git a/src/arm64/apple/t8103-j293.dts b/src/arm64/apple/t8103-j293.dts index 56b0c67bfcd..e2d9439397f 100644 --- a/src/arm64/apple/t8103-j293.dts +++ b/src/arm64/apple/t8103-j293.dts @@ -17,6 +17,14 @@ compatible = "apple,j293", "apple,t8103", "apple,arm-platform"; model = "Apple MacBook Pro (13-inch, M1, 2020)"; + /* + * All of those are used by the bootloader to pass calibration + * blobs and other device-specific properties + */ + aliases { + touchbar0 = &touchbar0; + }; + led-controller { compatible = "pwm-leds"; led-0 { @@ -49,3 +57,63 @@ &fpwm1 { status = "okay"; }; + +&spi0 { + cs-gpios = <&pinctrl_ap 109 GPIO_ACTIVE_LOW>; + status = "okay"; + + touchbar0: touchbar@0 { + compatible = "apple,j293-touchbar"; + reg = <0>; + spi-max-frequency = <11500000>; + spi-cs-setup-delay-ns = <2000>; + spi-cs-hold-delay-ns = <2000>; + reset-gpios = <&pinctrl_ap 139 GPIO_ACTIVE_LOW>; + interrupts-extended = <&pinctrl_ap 194 IRQ_TYPE_EDGE_FALLING>; + firmware-name = "apple/dfrmtfw-j293.bin"; + touchscreen-size-x = <23045>; + touchscreen-size-y = <640>; + touchscreen-inverted-y; + }; +}; + +/* + * The driver depends on boot loader initialized state which resets when this + * power-domain is powered off. This happens on suspend or when the driver is + * missing during boot. Mark the domain as always on until the driver can + * handle this. + */ +&ps_dispdfr_be { + apple,always-on; +}; + +&display_dfr { + status = "okay"; +}; + +&dfr_mipi_out { + dfr_mipi_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&dfr_panel_in>; + }; +}; + +&displaydfr_mipi { + status = "okay"; + + dfr_panel: panel@0 { + compatible = "apple,j293-summit", "apple,summit"; + reg = <0>; + max-brightness = <255>; + + port { + dfr_panel_in: endpoint { + remote-endpoint = <&dfr_mipi_out_panel>; + }; + }; + }; +}; + +&displaydfr_dart { + status = "okay"; +}; diff --git a/src/arm64/apple/t8103-jxxx.dtsi b/src/arm64/apple/t8103-jxxx.dtsi index 5988a4eb6ef..8e82231acab 100644 --- a/src/arm64/apple/t8103-jxxx.dtsi +++ b/src/arm64/apple/t8103-jxxx.dtsi @@ -90,3 +90,5 @@ &nco_clkref { clock-frequency = <900000000>; }; + +#include "spi1-nvram.dtsi" diff --git a/src/arm64/apple/t8103-pmgr.dtsi b/src/arm64/apple/t8103-pmgr.dtsi index 9645861a858..c41c57d6399 100644 --- a/src/arm64/apple/t8103-pmgr.dtsi +++ b/src/arm64/apple/t8103-pmgr.dtsi @@ -387,6 +387,15 @@ power-domains = <&ps_sio>, <&ps_spi_p>; }; + ps_spi4: power-controller@260 { + compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; + reg = <0x260 4>; + #power-domain-cells = <0>; + #reset-cells = <0>; + label = "spi4"; + power-domains = <&ps_sio>, <&ps_spi_p>; + }; + ps_uart_n: power-controller@268 { compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; reg = <0x268 4>; @@ -558,15 +567,6 @@ apple,always-on; /* Memory controller */ }; - ps_spi4: power-controller@260 { - compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; - reg = <0x260 4>; - #power-domain-cells = <0>; - #reset-cells = <0>; - label = "spi4"; - power-domains = <&ps_sio>, <&ps_spi_p>; - }; - ps_dcs0: power-controller@300 { compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate"; reg = <0x300 4>; diff --git a/src/arm64/apple/t8103.dtsi b/src/arm64/apple/t8103.dtsi index 9b0dad6b618..97b6a067394 100644 --- a/src/arm64/apple/t8103.dtsi +++ b/src/arm64/apple/t8103.dtsi @@ -326,6 +326,20 @@ clock-output-names = "clkref"; }; + clk_120m: clock-120m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "clk_120m"; + }; + + clk_200m: clock-200m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. @@ -356,6 +370,67 @@ #performance-domain-cells = <0>; }; + display_dfr: display-pipe@228200000 { + compatible = "apple,t8103-display-pipe", "apple,h7-display-pipe"; + reg = <0x2 0x28200000 0x0 0xc000>, + <0x2 0x28400000 0x0 0x4000>; + reg-names = "be", "fe"; + power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>; + interrupt-parent = <&aic>; + interrupts = , + ; + interrupt-names = "be", "fe"; + iommus = <&displaydfr_dart 0>; + status = "disabled"; + + port { + dfr_adp_out_mipi: endpoint { + remote-endpoint = <&dfr_mipi_in_adp>; + }; + }; + }; + + displaydfr_dart: iommu@228304000 { + compatible = "apple,t8103-dart"; + reg = <0x2 0x28304000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_dispdfr_fe>; + status = "disabled"; + }; + + displaydfr_mipi: dsi@228600000 { + compatible = "apple,t8103-display-pipe-mipi", "apple,h7-display-pipe-mipi"; + reg = <0x2 0x28600000 0x0 0x100000>; + power-domains = <&ps_mipi_dsi>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dfr_mipi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dfr_mipi_in_adp: endpoint@0 { + reg = <0>; + remote-endpoint = <&dfr_adp_out_mipi>; + }; + }; + + dfr_mipi_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + sio_dart: iommu@235004000 { compatible = "apple,t8103-dart"; reg = <0x2 0x35004000 0x0 0x4000>; @@ -441,6 +516,48 @@ status = "disabled"; }; + spi0: spi@235100000 { + compatible = "apple,t8103-spi", "apple,spi"; + reg = <0x2 0x35100000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + clocks = <&clk_200m>; + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@235104000 { + compatible = "apple,t8103-spi", "apple,spi"; + reg = <0x2 0x35104000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + clocks = <&clk_200m>; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@23510c000 { + compatible = "apple,t8103-spi", "apple,spi"; + reg = <0x2 0x3510c000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + clocks = <&clk_120m>; + pinctrl-0 = <&spi3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + serial0: serial@235200000 { compatible = "apple,s5l-uart"; reg = <0x2 0x35200000 0x0 0x1000>; @@ -597,6 +714,26 @@ ; }; + spi0_pins: spi0-pins { + pinmux = , /* CLK */ + , /* MOSI */ + ; /* MISO */ + }; + + spi1_pins: spi1-pins { + pinmux = , + , + , + ; + }; + + spi3_pins: spi3-pins { + pinmux = , + , + , + ; + }; + pcie_pins: pcie-pins { pinmux = , , diff --git a/src/arm64/apple/t8112-j493.dts b/src/arm64/apple/t8112-j493.dts index 0ad908349f5..be86d34c669 100644 --- a/src/arm64/apple/t8112-j493.dts +++ b/src/arm64/apple/t8112-j493.dts @@ -17,8 +17,13 @@ compatible = "apple,j493", "apple,t8112", "apple,arm-platform"; model = "Apple MacBook Pro (13-inch, M2, 2022)"; + /* + * All of those are used by the bootloader to pass calibration + * blobs and other device-specific properties + */ aliases { bluetooth0 = &bluetooth0; + touchbar0 = &touchbar0; wifi0 = &wifi0; }; @@ -35,6 +40,47 @@ }; }; +/* + * The driver depends on boot loader initialized state which resets when this + * power-domain is powered off. This happens on suspend or when the driver is + * missing during boot. Mark the domain as always on until the driver can + * handle this. + */ +&ps_dispdfr_be { + apple,always-on; +}; + +&display_dfr { + status = "okay"; +}; + +&dfr_mipi_out { + dfr_mipi_out_panel: endpoint@0 { + reg = <0>; + remote-endpoint = <&dfr_panel_in>; + }; +}; + +&displaydfr_mipi { + status = "okay"; + + dfr_panel: panel@0 { + compatible = "apple,j493-summit", "apple,summit"; + reg = <0>; + max-brightness = <255>; + + port { + dfr_panel_in: endpoint { + remote-endpoint = <&dfr_mipi_out_panel>; + }; + }; + }; +}; + +&displaydfr_dart { + status = "okay"; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader @@ -67,3 +113,21 @@ &fpwm1 { status = "okay"; }; + +&spi3 { + status = "okay"; + + touchbar0: touchbar@0 { + compatible = "apple,j493-touchbar"; + reg = <0>; + spi-max-frequency = <8000000>; + spi-cs-setup-delay-ns = <2000>; + spi-cs-hold-delay-ns = <2000>; + reset-gpios = <&pinctrl_ap 170 GPIO_ACTIVE_LOW>; + interrupts-extended = <&pinctrl_ap 174 IRQ_TYPE_EDGE_FALLING>; + firmware-name = "apple/dfrmtfw-j493.bin"; + touchscreen-size-x = <23045>; + touchscreen-size-y = <640>; + touchscreen-inverted-y; + }; +}; diff --git a/src/arm64/apple/t8112-jxxx.dtsi b/src/arm64/apple/t8112-jxxx.dtsi index f5edf61113e..6da35496a4c 100644 --- a/src/arm64/apple/t8112-jxxx.dtsi +++ b/src/arm64/apple/t8112-jxxx.dtsi @@ -79,3 +79,5 @@ &nco_clkref { clock-frequency = <900000000>; }; + +#include "spi1-nvram.dtsi" diff --git a/src/arm64/apple/t8112.dtsi b/src/arm64/apple/t8112.dtsi index 1666e6ab250..d9b966d68e4 100644 --- a/src/arm64/apple/t8112.dtsi +++ b/src/arm64/apple/t8112.dtsi @@ -349,6 +349,13 @@ clock-output-names = "clkref"; }; + clk_200m: clock-200m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "clk_200m"; + }; + /* * This is a fabulated representation of the input clock * to NCO since we don't know the true clock tree. @@ -379,6 +386,67 @@ #performance-domain-cells = <0>; }; + display_dfr: display-pipe@228200000 { + compatible = "apple,t8112-display-pipe", "apple,h7-display-pipe"; + reg = <0x2 0x28200000 0x0 0xc000>, + <0x2 0x28400000 0x0 0x4000>; + reg-names = "be", "fe"; + power-domains = <&ps_dispdfr_fe>, <&ps_dispdfr_be>; + interrupt-parent = <&aic>; + interrupts = , + ; + interrupt-names = "be", "fe"; + iommus = <&displaydfr_dart 0>; + status = "disabled"; + + port { + dfr_adp_out_mipi: endpoint { + remote-endpoint = <&dfr_mipi_in_adp>; + }; + }; + }; + + displaydfr_dart: iommu@228304000 { + compatible = "apple,t8110-dart"; + reg = <0x2 0x28304000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + #iommu-cells = <1>; + power-domains = <&ps_dispdfr_fe>; + status = "disabled"; + }; + + displaydfr_mipi: dsi@228600000 { + compatible = "apple,t8112-display-pipe-mipi", "apple,h7-display-pipe-mipi"; + reg = <0x2 0x28600000 0x0 0x100000>; + power-domains = <&ps_mipi_dsi>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dfr_mipi_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + dfr_mipi_in_adp: endpoint@0 { + reg = <0>; + remote-endpoint = <&dfr_adp_out_mipi>; + }; + }; + + dfr_mipi_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + sio_dart: iommu@235004000 { compatible = "apple,t8110-dart"; reg = <0x2 0x35004000 0x0 0x4000>; @@ -467,6 +535,34 @@ status = "disabled"; }; + spi1: spi@235104000 { + compatible = "apple,t8112-spi", "apple,spi"; + reg = <0x2 0x35104000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + clocks = <&clk_200m>; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@23510c000 { + compatible = "apple,t8112-spi", "apple,spi"; + reg = <0x2 0x3510c000 0x0 0x4000>; + interrupt-parent = <&aic>; + interrupts = ; + clocks = <&clkref>; + pinctrl-0 = <&spi3_pins>; + pinctrl-names = "default"; + power-domains = <&ps_spi3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; /* only used in J493 */ + }; + serial0: serial@235200000 { compatible = "apple,s5l-uart"; reg = <0x2 0x35200000 0x0 0x1000>; @@ -626,13 +722,20 @@ ; }; - spi3_pins: spi3-pins { + spi1_pins: spi1-pins { pinmux = , , , ; }; + spi3_pins: spi3-pins { + pinmux = , + , + , + ; + }; + pcie_pins: pcie-pins { pinmux = , , diff --git a/src/arm64/arm/corstone1000-fvp.dts b/src/arm64/arm/corstone1000-fvp.dts index abd01356299..66ba6b02719 100644 --- a/src/arm64/arm/corstone1000-fvp.dts +++ b/src/arm64/arm/corstone1000-fvp.dts @@ -49,3 +49,29 @@ clock-names = "smclk", "apb_pclk"; }; }; + +&cpus { + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x2>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x3>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; +}; diff --git a/src/arm64/arm/corstone1000.dtsi b/src/arm64/arm/corstone1000.dtsi index bb9b96fb531..56ada8728b6 100644 --- a/src/arm64/arm/corstone1000.dtsi +++ b/src/arm64/arm/corstone1000.dtsi @@ -21,7 +21,7 @@ stdout-path = "serial0:115200n8"; }; - cpus { + cpus: cpus { #address-cells = <1>; #size-cells = <0>; @@ -29,6 +29,7 @@ device_type = "cpu"; compatible = "arm,cortex-a35"; reg = <0>; + enable-method = "psci"; next-level-cache = <&L2_0>; }; }; diff --git a/src/arm64/arm/morello-fvp.dts b/src/arm64/arm/morello-fvp.dts new file mode 100644 index 00000000000..2072c0b7232 --- /dev/null +++ b/src/arm64/arm/morello-fvp.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model = "Arm Morello Fixed Virtual Platform"; + compatible = "arm,morello-fvp", "arm,morello"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + bp_refclock24mhz: clock-24000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "bp:clock24mhz"; + }; + + block_0: virtio_block@1c170000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c170000 0x0 0x200>; + interrupts = ; + }; + + net_0: virtio_net@1c180000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c180000 0x0 0x200>; + interrupts = ; + }; + + rng_0: virtio_rng@1c190000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c190000 0x0 0x200>; + interrupts = ; + }; + + p9_0: virtio_p9@1c1a0000 { + compatible = "virtio,mmio"; + reg = <0x0 0x1c1a0000 0x0 0x200>; + interrupts = ; + }; + + kmi_0: kmi@1c150000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x0 0x1c150000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi_1: kmi@1c160000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x0 0x1c160000 0x0 0x1000>; + interrupts = ; + clocks = <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + eth_0: ethernet@1d100000 { + compatible = "smsc,lan91c111"; + reg = <0x0 0x1d100000 0x0 0x10000>; + interrupts = ; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/src/arm64/arm/morello-sdp.dts b/src/arm64/arm/morello-sdp.dts new file mode 100644 index 00000000000..cee49dee757 --- /dev/null +++ b/src/arm64/arm/morello-sdp.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model = "Arm Morello System Development Platform"; + compatible = "arm,morello-sdp", "arm,morello"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dpu_aclk: clock-350000000 { + /* 77.1 MHz derived from 24 MHz reference clock */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <350000000>; + clock-output-names = "aclk"; + }; + + dpu_pixel_clk: clock-148500000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + clock-output-names = "pxclk"; + }; + + i2c0: i2c@1c0f0000 { + compatible = "cdns,i2c-r1p14"; + reg = <0x0 0x1c0f0000 0x0 0x1000>; + interrupts = ; + clocks = <&dpu_aclk>; + + #address-cells = <1>; + #size-cells = <0>; + + clock-frequency = <100000>; + + hdmi_tx: hdmi-transmitter@70 { + compatible = "nxp,tda998x"; + reg = <0x70>; + video-ports = <0x234501>; + port { + tda998x_0_input: endpoint { + remote-endpoint = <&dp_pl0_out0>; + }; + }; + }; + }; + + dp0: display@2cc00000 { + compatible = "arm,mali-d32", "arm,mali-d71"; + reg = <0x0 0x2cc00000 0x0 0x20000>; + interrupts = <0 69 4>; + clocks = <&dpu_aclk>; + clock-names = "aclk"; + iommus = <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>, + <&smmu_dp 8>; + + #address-cells = <1>; + #size-cells = <0>; + + pl0: pipeline@0 { + reg = <0>; + clocks = <&dpu_pixel_clk>; + clock-names = "pxclk"; + port { + dp_pl0_out0: endpoint { + remote-endpoint = <&tda998x_0_input>; + }; + }; + }; + }; + + smmu_ccix: iommu@4f000000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x4f000000 0x0 0x40000>; + + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent = <&its1 0>; + #iommu-cells = <1>; + dma-coherent; + }; + + smmu_pcie: iommu@4f400000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x4f400000 0x0 0x40000>; + + interrupts = , + , + , + ; + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent = <&its2 0>; + #iommu-cells = <1>; + dma-coherent; + }; + + pcie_ctlr: pcie@28c0000000 { + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + reg = <0x28 0xC0000000 0 0x10000000>; + ranges = <0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000>, + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000>, + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000>; + bus-range = <0 255>; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; + msi-map = <0 &its_pcie 0 0x10000>; + iommu-map = <0 &smmu_pcie 0 0x10000>; + }; + + ccix_pcie_ctlr: pcie@4fc0000000 { + device_type = "pci"; + compatible = "pci-host-ecam-generic"; + reg = <0x4f 0xC0000000 0 0x10000000>; + ranges = <0x01000000 0x00 0x00000000 0x00 0x7f000000 0x00 0x00800000>, + <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0f000000>, + <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1f 0xc0000000>; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; + msi-map = <0 &its_ccix 0 0x10000>; + iommu-map = <0 &smmu_ccix 0 0x10000>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/src/arm64/arm/morello.dtsi b/src/arm64/arm/morello.dtsi new file mode 100644 index 00000000000..5bc1c725dc8 --- /dev/null +++ b/src/arm64/arm/morello.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + */ + +#include + +/ { + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + + soc_refclk50mhz: clock-50000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "apb_pclk"; + }; + + soc_refclk85mhz: clock-85000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <85000000>; + clock-output-names = "iofpga:aclk"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,rainier"; + reg = <0x0 0x0>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_0>; + clocks = <&scmi_dvfs 0>; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu1: cpu@100 { + compatible = "arm,rainier"; + reg = <0x0 0x100>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_1>; + clocks = <&scmi_dvfs 0>; + + l2_1: l2-cache { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu2: cpu@10000 { + compatible = "arm,rainier"; + reg = <0x0 0x10000>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_2>; + clocks = <&scmi_dvfs 1>; + + l2_2: l2-cache { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + cpu3: cpu@10100 { + compatible = "arm,rainier"; + reg = <0x0 0x10100>; + device_type = "cpu"; + enable-method = "psci"; + /* 4 ways set associative */ + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <512>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <512>; + next-level-cache = <&l2_3>; + clocks = <&scmi_dvfs 1>; + + l2_3: l2-cache { + compatible = "cache"; + cache-level = <2>; + /* 8 ways set associative */ + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <2048>; + cache-unified; + next-level-cache = <&l3_0>; + }; + }; + + l3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-size = <0x100000>; + cache-unified; + }; + }; + + firmware { + interrupt-parent = <&gic>; + + scmi { + compatible = "arm,scmi"; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 1 0>, <&mailbox 1 1>; + shmem = <&cpu_scp_hpri0>, <&cpu_scp_hpri1>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_dvfs: protocol@13 { + reg = <0x13>; + #clock-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + + /* The first bank of memory, memory map is actually provided by UEFI. */ + memory@80000000 { + device_type = "memory"; + /* [0x80000000-0xffffffff] */ + reg = <0x00000000 0x80000000 0x0 0x7f000000>; + }; + + memory@8080000000 { + device_type = "memory"; + /* [0x8080000000-0x83f7ffffff] */ + reg = <0x00000080 0x80000000 0x3 0x78000000>; + }; + + pmu { + compatible = "arm,rainier-pmu"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure-firmware@ff000000 { + reg = <0x0 0xff000000 0x0 0x01000000>; + no-map; + }; + }; + + spe-pmu { + compatible = "arm,statistical-profiling-extension-v1"; + interrupts = ; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + ranges; + + uart0: serial@2a400000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0 0x2a400000 0x0 0x1000>; + interrupts = ; + clocks = <&soc_refclk50mhz>, <&soc_refclk50mhz>; + clock-names = "uartclk", "apb_pclk"; + + status = "disabled"; + }; + + gic: interrupt-controller@30000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x30000000 0x0 0x10000>, /* GICD */ + <0x0 0x300c0000 0x0 0x80000>; /* GICR */ + + interrupts = ; + + #interrupt-cells = <3>; + interrupt-controller; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + its1: msi-controller@30040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30040000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + + its2: msi-controller@30060000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30060000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + + its_ccix: msi-controller@30080000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x30080000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + + its_pcie: msi-controller@300a0000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x300a0000 0x0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + smmu_dp: iommu@2ce00000 { + compatible = "arm,smmu-v3"; + reg = <0x0 0x2ce00000 0x0 0x40000>; + + interrupts = , + , + ; + interrupt-names = "eventq", "gerror", "cmdq-sync"; + #iommu-cells = <1>; + }; + + mailbox: mhu@45000000 { + compatible = "arm,mhu-doorbell", "arm,primecell"; + reg = <0x0 0x45000000 0x0 0x1000>; + + interrupts = , + ; + #mbox-cells = <2>; + clocks = <&soc_refclk50mhz>; + clock-names = "apb_pclk"; + }; + + sram: sram@6000000 { + compatible = "mmio-sram"; + reg = <0x0 0x06000000 0x0 0x8000>; + ranges = <0 0x0 0x06000000 0x8000>; + + #address-cells = <1>; + #size-cells = <1>; + + cpu_scp_hpri0: scp-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x80>; + }; + + cpu_scp_hpri1: scp-sram@80 { + compatible = "arm,scmi-shmem"; + reg = <0x80 0x80>; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; +}; diff --git a/src/arm64/exynos/exynos8895-dreamlte.dts b/src/arm64/exynos/exynos8895-dreamlte.dts index 3a376ab2bb9..61e064af333 100644 --- a/src/arm64/exynos/exynos8895-dreamlte.dts +++ b/src/arm64/exynos/exynos8895-dreamlte.dts @@ -10,12 +10,17 @@ #include #include #include +#include / { model = "Samsung Galaxy S8 (SM-G950F)"; compatible = "samsung,dreamlte", "samsung,exynos8895"; chassis-type = "handset"; + aliases { + mmc0 = &mmc; + }; + chosen { #address-cells = <2>; #size-cells = <1>; @@ -89,12 +94,60 @@ wakeup-source; }; }; + + /* TODO: Remove once PMIC is implemented */ + reg_placeholder: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "reg-placeholder"; + }; +}; + +&hsi2c_23 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + touchscreen@48 { + compatible = "samsung,s6sy761"; + reg = <0x48>; + + /* TODO: Update once PMIC is implemented */ + avdd-supply = <®_placeholder>; + vdd-supply = <®_placeholder>; + + interrupt-parent = <&gpa1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-0 = <&ts_int>; + pinctrl-names = "default"; + }; }; &oscclk { clock-frequency = <26000000>; }; +&mmc { + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4 &sd2_cd>; + pinctrl-names = "default"; + + bus-width = <4>; + card-detect-delay = <200>; + cd-gpios = <&gpa1 5 GPIO_ACTIVE_LOW>; + clock-frequency = <800000000>; + disable-wp; + sd-uhs-sdr50; + sd-uhs-sdr104; + + /* TODO: Add regulators once PMIC is implemented */ + + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-ddr-timing = <1 2>; + samsung,dw-mshc-sdr-timing = <0 3>; + + status = "okay"; +}; + &pinctrl_alive { key_power: key-power-pins { samsung,pins = "gpa2-4"; @@ -123,4 +176,23 @@ samsung,pin-pud = ; samsung,pin-drv = ; }; + + sd2_cd: sd2-cd-pins { + samsung,pins = "gpa1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + ts_int: ts-int-pins { + samsung,pins = "gpa1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&usi9 { + samsung,mode = ; + status = "okay"; }; diff --git a/src/arm64/exynos/exynos8895.dtsi b/src/arm64/exynos/exynos8895.dtsi index 36657abfc61..f92d2a8a20a 100644 --- a/src/arm64/exynos/exynos8895.dtsi +++ b/src/arm64/exynos/exynos8895.dtsi @@ -26,30 +26,6 @@ pinctrl7 = &pinctrl_peric1; }; - arm-a53-pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - mongoose-m2-pmu { - compatible = "samsung,mongoose-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu4>, - <&cpu5>, - <&cpu6>, - <&cpu7>; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -149,6 +125,30 @@ clock-output-names = "oscclk"; }; + pmu-a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + pmu-mongoose-m2 { + compatible = "samsung,mongoose-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu4>, + <&cpu5>, + <&cpu6>, + <&cpu7>; + }; + psci { compatible = "arm,psci"; method = "smc"; @@ -228,6 +228,12 @@ "usi1", "usi2", "usi3"; }; + syscon_peric0: syscon@10420000 { + compatible = "samsung,exynos8895-peric0-sysreg", "syscon"; + reg = <0x10420000 0x2000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK>; + }; + serial_0: serial@10430000 { compatible = "samsung,exynos8895-uart"; reg = <0x10430000 0x100>; @@ -241,6 +247,254 @@ status = "disabled"; }; + usi0: usi@10440000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10440000 0x11000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric0 0x1000>; + status = "disabled"; + + hsi2c_5: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c5_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_2: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart2_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_2: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi2_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_6: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI00_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c6_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi1: usi@10460000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10460000 0x11000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric0 0x1004>; + status = "disabled"; + + hsi2c_7: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c5_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_3: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart3_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_3: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi3_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_8: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI01_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c8_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi2: usi@10480000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10480000 0x11000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric0 0x1008>; + status = "disabled"; + + hsi2c_9: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c9_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_4: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart4_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_4: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi4_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_10: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI02_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c10_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi3: usi@104a0000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x104a0000 0x11000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric0 0x100c>; + status = "disabled"; + + hsi2c_11: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c11_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_5: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart5_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_5: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>, + <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi5_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_12: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_USI03_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c12_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + pinctrl_peric0: pinctrl@104d0000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x104d0000 0x1000>; @@ -273,6 +527,12 @@ "usi10", "usi11", "usi12", "usi13"; }; + syscon_peric1: syscon@10820000 { + compatible = "samsung,exynos8895-peric1-sysreg", "syscon"; + reg = <0x10820000 0x2000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>; + }; + serial_1: serial@10830000 { compatible = "samsung,exynos8895-uart"; reg = <0x10830000 0x100>; @@ -286,6 +546,626 @@ status = "disabled"; }; + usi4: usi@10840000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10840000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x1008>; + status = "disabled"; + + hsi2c_13: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c13_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_6: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart6_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_6: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi6_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_14: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI04_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c14_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi5: usi@10860000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10860000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x100c>; + status = "disabled"; + + hsi2c_15: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c15_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_7: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart7_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_7: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi7_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_16: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI05_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c16_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi6: usi@10880000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10880000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x1010>; + status = "disabled"; + + hsi2c_17: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c17_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_8: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart8_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_8: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi8_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_18: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI06_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c18_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi7: usi@108a0000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x108a0000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x1014>; + status = "disabled"; + + hsi2c_19: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c19_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_9: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart9_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_9: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi9_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_20: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI07_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c20_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi8: usi@108c0000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x108c0000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x1018>; + status = "disabled"; + + hsi2c_21: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c21_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_10: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart10_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_10: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0x0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi10_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_22: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI08_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c22_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi9: usi@108e0000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x108e0000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x101c>; + status = "disabled"; + + hsi2c_23: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c23_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_11: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart11_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_11: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi11_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_24: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI09_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c24_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi10: usi@10900000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10900000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x1020>; + status = "disabled"; + + hsi2c_25: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c25_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_12: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart12_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_12: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi12_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_26: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI10_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c26_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi11: usi@10920000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10920000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x1024>; + status = "disabled"; + + hsi2c_27: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c27_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_13: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart13_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_13: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi13_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_28: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI11_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c28_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi12: usi@10940000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10940000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x1028>; + status = "disabled"; + + hsi2c_29: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c29_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_14: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart14_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_14: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi14_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_30: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI12_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c30_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + + usi13: usi@10960000 { + compatible = "samsung,exynos8895-usi"; + ranges = <0x0 0x10960000 0x11000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_SCLK_USI>; + clock-names = "pclk", "ipclk"; + #address-cells = <1>; + #size-cells = <1>; + samsung,sysreg = <&syscon_peric1 0x102c>; + status = "disabled"; + + hsi2c_31: i2c@0 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x0 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c31_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + + serial_15: serial@0 { + compatible = "samsung,exynos8895-uart"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_SCLK_USI>; + clock-names = "uart", "clk_uart_baud0"; + interrupts = ; + pinctrl-0 = <&uart15_bus>; + pinctrl-names = "default"; + samsung,uart-fifosize = <64>; + status = "disabled"; + }; + + spi_15: spi@0 { + compatible = "samsung,exynos8895-spi", + "samsung,exynos850-spi"; + reg = <0 0x100>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>, + <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_SCLK_USI>; + clock-names = "spi", "spi_busclk0"; + interrupts = ; + pinctrl-0 = <&spi15_bus>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hsi2c_32: i2c@10000 { + compatible = "samsung,exynos8895-hsi2c"; + reg = <0x10000 0x1000>; + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_USI13_I_PCLK>; + clock-names = "hsi2c"; + interrupts = ; + pinctrl-0 = <&hsi2c32_bus>; + pinctrl-names = "default"; + status = "disabled"; + }; + }; + pinctrl_peric1: pinctrl@10980000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x10980000 0x1000>; @@ -380,6 +1260,12 @@ "ufs", "usbdrd30"; }; + syscon_fsys0: syscon@11020000 { + compatible = "samsung,exynos8895-fsys0-sysreg", "syscon"; + reg = <0x11020000 0x2000>; + clocks = <&cmu_fsys0 CLK_GOUT_FSYS0_SYSREG_FSYS0_PCLK>; + }; + pinctrl_fsys0: pinctrl@11050000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x11050000 0x1000>; @@ -398,12 +1284,34 @@ clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; }; + syscon_fsys1: syscon@11420000 { + compatible = "samsung,exynos8895-fsys1-sysreg", "syscon"; + reg = <0x11420000 0x2000>; + clocks = <&cmu_fsys1 CLK_GOUT_FSYS1_SYSREG_FSYS1_PCLK>; + }; + pinctrl_fsys1: pinctrl@11430000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x11430000 0x1000>; interrupts = ; }; + mmc: mmc@11500000 { + compatible = "samsung,exynos8895-dw-mshc-smu", + "samsung,exynos7-dw-mshc-smu"; + reg = <0x11500000 0x2000>; + assigned-clocks = <&cmu_top CLK_MOUT_CMU_FSYS1_MMC_CARD>; + assigned-clock-parents = <&cmu_top CLK_FOUT_SHARED4_PLL>; + clocks = <&cmu_fsys1 CLK_GOUT_FSYS1_MMC_CARD_I_ACLK>, + <&cmu_fsys1 CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN>; + clock-names = "biu", "ciu"; + fifo-depth = <64>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pinctrl_abox: pinctrl@13e60000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x13e60000 0x1000>; diff --git a/src/arm64/exynos/exynos990.dtsi b/src/arm64/exynos/exynos990.dtsi index 9d017dbed95..dd7f99f51a7 100644 --- a/src/arm64/exynos/exynos990.dtsi +++ b/src/arm64/exynos/exynos990.dtsi @@ -25,37 +25,6 @@ pinctrl6 = &pinctrl_vts; }; - arm-a55-pmu { - compatible = "arm,cortex-a55-pmu"; - interrupts = , - , - , - ; - - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - arm-a76-pmu { - compatible = "arm,cortex-a76-pmu"; - interrupts = , - ; - - interrupt-affinity = <&cpu4>, - <&cpu5>; - }; - - mongoose-m5-pmu { - compatible = "samsung,mongoose-pmu"; - interrupts = , - ; - - interrupt-affinity = <&cpu6>, - <&cpu7>; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -163,6 +132,37 @@ clock-output-names = "oscclk"; }; + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupts = , + , + , + ; + + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts = , + ; + + interrupt-affinity = <&cpu4>, + <&cpu5>; + }; + + pmu-mongoose-m5 { + compatible = "samsung,mongoose-pmu"; + interrupts = , + ; + + interrupt-affinity = <&cpu6>, + <&cpu7>; + }; + psci { compatible = "arm,psci-0.2"; method = "hvc"; @@ -181,6 +181,36 @@ reg = <0x10000000 0x100>; }; + cmu_peris: clock-controller@10020000 { + compatible = "samsung,exynos990-cmu-peris"; + reg = <0x10020000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIS_BUS>; + clock-names = "oscclk", "bus"; + }; + + timer@10040000 { + compatible = "samsung,exynos990-mct", + "samsung,exynos4210-mct"; + reg = <0x10040000 0x800>; + clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>; + clock-names = "fin_pll", "mct"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + }; + gic: interrupt-controller@10101000 { compatible = "arm,gic-400"; reg = <0x10101000 0x1000>, diff --git a/src/arm64/exynos/exynosautov920.dtsi b/src/arm64/exynos/exynosautov920.dtsi index eb446cdc4ab..fc6ac531d59 100644 --- a/src/arm64/exynos/exynosautov920.dtsi +++ b/src/arm64/exynos/exynosautov920.dtsi @@ -89,6 +89,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x0>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl0>; }; cpu1: cpu@100 { @@ -96,6 +103,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x100>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl0>; }; cpu2: cpu@200 { @@ -103,6 +117,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x200>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl0>; }; cpu3: cpu@300 { @@ -110,6 +131,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x300>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl0>; }; cpu4: cpu@10000 { @@ -117,6 +145,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x10000>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl1>; }; cpu5: cpu@10100 { @@ -124,6 +159,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x10100>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl1>; }; cpu6: cpu@10200 { @@ -131,6 +173,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x10200>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl1>; }; cpu7: cpu@10300 { @@ -138,6 +187,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x10300>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl1>; }; cpu8: cpu@20000 { @@ -145,6 +201,13 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x20000>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl2>; }; cpu9: cpu@20100 { @@ -152,6 +215,70 @@ compatible = "arm,cortex-a78ae"; reg = <0x0 0x20100>; enable-method = "psci"; + i-cache-size = <0x10000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x10000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; + next-level-cache = <&l2_cache_cl2>; + }; + + l2_cache_cl0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache_cl0>; + }; + + l2_cache_cl1: l2-cache1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache_cl1>; + }; + + l2_cache_cl2: l2-cache2 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x40000>; + cache-line-size = <64>; + cache-sets = <512>; + next-level-cache = <&l3_cache_cl2>; + }; + + l3_cache_cl0: l3-cache0 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-0 */ + cache-line-size = <64>; + cache-sets = <2048>; + }; + + l3_cache_cl1: l3-cache1 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-1 */ + cache-line-size = <64>; + cache-sets = <2048>; + }; + + l3_cache_cl2: l3-cache2 { + compatible = "cache"; + cache-level = <3>; + cache-unified; + cache-size = <0x100000>;/* 1MB L3 cache for cpu cluster-2 */ + cache-line-size = <64>; + cache-sets = <1365>; }; }; @@ -440,6 +567,17 @@ interrupts = ; }; + ufs_0_phy: phy@16e04000 { + compatible = "samsung,exynosautov920-ufs-phy"; + reg = <0x16e04000 0x4000>; + reg-names = "phy-pma"; + clocks = <&xtcxo>; + clock-names = "ref_clk"; + samsung,pmu-syscon = <&pmu_system_controller>; + #phy-cells = <0>; + status = "disabled"; + }; + pinctrl_aud: pinctrl@1a460000 { compatible = "samsung,exynosautov920-pinctrl"; reg = <0x1a460000 0x10000>; diff --git a/src/arm64/exynos/google/gs101-oriole.dts b/src/arm64/exynos/google/gs101-oriole.dts index e58881c61d5..8df42bedbc0 100644 --- a/src/arm64/exynos/google/gs101-oriole.dts +++ b/src/arm64/exynos/google/gs101-oriole.dts @@ -8,273 +8,22 @@ /dts-v1/; -#include -#include -#include -#include "gs101-pinctrl.h" -#include "gs101.dtsi" +#include "gs101-pixel-common.dtsi" / { model = "Oriole"; compatible = "google,gs101-oriole", "google,gs101"; - - aliases { - serial0 = &serial_0; - }; - - chosen { - /* Bootloader expects bootargs specified otherwise it crashes */ - bootargs = ""; - stdout-path = &serial_0; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-0 = <&key_voldown>, <&key_volup>, <&key_power>; - pinctrl-names = "default"; - - button-vol-down { - label = "KEY_VOLUMEDOWN"; - linux,code = ; - gpios = <&gpa7 3 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button-vol-up { - label = "KEY_VOLUMEUP"; - linux,code = ; - gpios = <&gpa8 1 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - - button-power { - label = "KEY_POWER"; - linux,code = ; - gpios = <&gpa10 1 GPIO_ACTIVE_LOW>; - wakeup-source; - }; - }; - - /* TODO: Remove this once PMIC is implemented */ - reg_placeholder: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "placeholder_reg"; - }; - - /* TODO: Remove this once S2MPG11 slave PMIC is implemented */ - ufs_0_fixed_vcc_reg: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "ufs-vcc"; - gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - enable-active-high; - }; -}; - -&ext_24_5m { - clock-frequency = <24576000>; -}; - -&ext_200m { - clock-frequency = <200000000>; -}; - -&hsi2c_8 { - status = "okay"; - - eeprom: eeprom@50 { - compatible = "atmel,24c08"; - reg = <0x50>; - }; -}; - -&hsi2c_12 { - status = "okay"; - /* TODO: add the devices once drivers exist */ - - usb-typec@25 { - compatible = "maxim,max77759-tcpci", "maxim,max33359"; - reg = <0x25>; - interrupts-extended = <&gpa8 2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&typec_int>; - pinctrl-names = "default"; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - self-powered; - try-power-role = "sink"; - op-sink-microwatt = <2600000>; - slow-charger-loop; - /* - * max77759 operating in reverse boost mode (0xA) can - * source up to 1.5A while extboost can only do ~1A. - * Since extboost is the primary path, advertise 900mA. - */ - source-pdos = ; - sink-pdos = ; - sink-vdos = ; - sink-vdos-v1 = ; - /* - * Until bootloader is updated to set those two when - * console is enabled, we disable PD here. - */ - pd-disable; - typec-power-opmode = "default"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usbc0_orien_sw: endpoint { - remote-endpoint = <&usbdrd31_phy_orien_switch>; - }; - }; - - port@1 { - reg = <1>; - - usbc0_role_sw: endpoint { - remote-endpoint = <&usbdrd31_dwc3_role_switch>; - }; - }; - }; - }; - }; -}; - -&pinctrl_far_alive { - key_voldown: key-voldown-pins { - samsung,pins = "gpa7-3"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - key_volup: key-volup-pins { - samsung,pins = "gpa8-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; - - typec_int: typec-int-pins { - samsung,pins = "gpa8-2"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&pinctrl_gpio_alive { - key_power: key-power-pins { - samsung,pins = "gpa10-1"; - samsung,pin-function = ; - samsung,pin-pud = ; - samsung,pin-drv = ; - }; -}; - -&serial_0 { - status = "okay"; -}; - -&ufs_0 { - status = "okay"; - vcc-supply = <&ufs_0_fixed_vcc_reg>; -}; - -&ufs_0_phy { - status = "okay"; -}; - -&usbdrd31 { - vdd10-supply = <®_placeholder>; - vdd33-supply = <®_placeholder>; - status = "okay"; -}; - -&usbdrd31_dwc3 { - dr_mode = "otg"; - usb-role-switch; - role-switch-default-mode = "peripheral"; - maximum-speed = "super-speed-plus"; - status = "okay"; - - port { - usbdrd31_dwc3_role_switch: endpoint { - remote-endpoint = <&usbc0_role_sw>; - }; - }; -}; - -&usbdrd31_phy { - orientation-switch; - /* TODO: Update these once PMIC is implemented */ - pll-supply = <®_placeholder>; - dvdd-usb20-supply = <®_placeholder>; - vddh-usb20-supply = <®_placeholder>; - vdd33-usb20-supply = <®_placeholder>; - vdda-usbdp-supply = <®_placeholder>; - vddh-usbdp-supply = <®_placeholder>; - status = "okay"; - - port { - usbdrd31_phy_orien_switch: endpoint { - remote-endpoint = <&usbc0_orien_sw>; - }; - }; -}; - -&usi_uart { - samsung,clkreq-on; /* needed for UART mode */ - status = "okay"; -}; - -&usi8 { - samsung,mode = ; - status = "okay"; }; -&usi12 { - samsung,mode = ; +&cont_splash_mem { + reg = <0x0 0xfac00000 (1080 * 2400 * 4)>; status = "okay"; }; -&watchdog_cl0 { - timeout-sec = <30>; +&framebuffer0 { + width = <1080>; + height = <2400>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; status = "okay"; }; diff --git a/src/arm64/exynos/google/gs101-pixel-common.dtsi b/src/arm64/exynos/google/gs101-pixel-common.dtsi new file mode 100644 index 00000000000..b25230495c6 --- /dev/null +++ b/src/arm64/exynos/google/gs101-pixel-common.dtsi @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Device Tree nodes common for all GS101-based Pixel + * + * Copyright 2021-2023 Google LLC + * Copyright 2023 Linaro Ltd - + */ + +/dts-v1/; + +#include +#include +#include +#include "gs101-pinctrl.h" +#include "gs101.dtsi" + +/ { + aliases { + serial0 = &serial_0; + }; + + chosen { + /* Bootloader expects bootargs specified otherwise it crashes */ + bootargs = ""; + stdout-path = &serial_0; + + /* Use display framebuffer as setup by bootloader */ + framebuffer0: framebuffer-0 { + compatible = "simple-framebuffer"; + memory-region = <&cont_splash_mem>; + /* format properties to be added by actual board */ + status = "disabled"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&key_voldown>, <&key_volup>, <&key_power>; + pinctrl-names = "default"; + + button-vol-down { + label = "KEY_VOLUMEDOWN"; + linux,code = ; + gpios = <&gpa7 3 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-vol-up { + label = "KEY_VOLUMEUP"; + linux,code = ; + gpios = <&gpa8 1 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-power { + label = "KEY_POWER"; + linux,code = ; + gpios = <&gpa10 1 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + /* TODO: Remove this once PMIC is implemented */ + reg_placeholder: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "placeholder_reg"; + }; + + /* TODO: Remove this once S2MPG11 slave PMIC is implemented */ + ufs_0_fixed_vcc_reg: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "ufs-vcc"; + gpio = <&gpp0 1 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + enable-active-high; + }; + + reserved-memory { + cont_splash_mem: splash@fac00000 { + /* size to be updated by actual board */ + reg = <0x0 0xfac00000 0x0>; + no-map; + status = "disabled"; + }; + }; +}; + +&ext_24_5m { + clock-frequency = <24576000>; +}; + +&ext_200m { + clock-frequency = <200000000>; +}; + +&hsi2c_8 { + status = "okay"; + + eeprom: eeprom@50 { + compatible = "atmel,24c08"; + reg = <0x50>; + }; +}; + +&hsi2c_12 { + status = "okay"; + /* TODO: add the devices once drivers exist */ + + usb-typec@25 { + compatible = "maxim,max77759-tcpci", "maxim,max33359"; + reg = <0x25>; + interrupts-extended = <&gpa8 2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&typec_int>; + pinctrl-names = "default"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + self-powered; + try-power-role = "sink"; + op-sink-microwatt = <2600000>; + slow-charger-loop; + /* + * max77759 operating in reverse boost mode (0xA) can + * source up to 1.5A while extboost can only do ~1A. + * Since extboost is the primary path, advertise 900mA. + */ + source-pdos = ; + sink-pdos = ; + sink-vdos = ; + sink-vdos-v1 = ; + /* + * Until bootloader is updated to set those two when + * console is enabled, we disable PD here. + */ + pd-disable; + typec-power-opmode = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_orien_sw: endpoint { + remote-endpoint = <&usbdrd31_phy_orien_switch>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_role_sw: endpoint { + remote-endpoint = <&usbdrd31_dwc3_role_switch>; + }; + }; + }; + }; + }; +}; + +&pinctrl_far_alive { + key_voldown: key-voldown-pins { + samsung,pins = "gpa7-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + key_volup: key-volup-pins { + samsung,pins = "gpa8-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + typec_int: typec-int-pins { + samsung,pins = "gpa8-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&pinctrl_gpio_alive { + key_power: key-power-pins { + samsung,pins = "gpa10-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; +}; + +&serial_0 { + status = "okay"; +}; + +&ufs_0 { + status = "okay"; + vcc-supply = <&ufs_0_fixed_vcc_reg>; +}; + +&ufs_0_phy { + status = "okay"; +}; + +&usbdrd31 { + vdd10-supply = <®_placeholder>; + vdd33-supply = <®_placeholder>; + status = "okay"; +}; + +&usbdrd31_dwc3 { + dr_mode = "otg"; + usb-role-switch; + role-switch-default-mode = "peripheral"; + maximum-speed = "super-speed-plus"; + status = "okay"; + + port { + usbdrd31_dwc3_role_switch: endpoint { + remote-endpoint = <&usbc0_role_sw>; + }; + }; +}; + +&usbdrd31_phy { + orientation-switch; + /* TODO: Update these once PMIC is implemented */ + pll-supply = <®_placeholder>; + dvdd-usb20-supply = <®_placeholder>; + vddh-usb20-supply = <®_placeholder>; + vdd33-usb20-supply = <®_placeholder>; + vdda-usbdp-supply = <®_placeholder>; + vddh-usbdp-supply = <®_placeholder>; + status = "okay"; + + port { + usbdrd31_phy_orien_switch: endpoint { + remote-endpoint = <&usbc0_orien_sw>; + }; + }; +}; + +&usi_uart { + samsung,clkreq-on; /* needed for UART mode */ + status = "okay"; +}; + +&usi8 { + samsung,mode = ; + status = "okay"; +}; + +&usi12 { + samsung,mode = ; + status = "okay"; +}; + +&watchdog_cl0 { + timeout-sec = <30>; + status = "okay"; +}; diff --git a/src/arm64/exynos/google/gs101-raven.dts b/src/arm64/exynos/google/gs101-raven.dts new file mode 100644 index 00000000000..1e7e6b34b86 --- /dev/null +++ b/src/arm64/exynos/google/gs101-raven.dts @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Raven Device Tree + * + * Copyright 2021-2023 Google LLC + * Copyright 2023-2025 Linaro Ltd + */ + +/dts-v1/; + +#include "gs101-pixel-common.dtsi" + +/ { + model = "Raven"; + compatible = "google,gs101-raven", "google,gs101"; +}; + +&cont_splash_mem { + reg = <0x0 0xfac00000 (1440 * 3120 * 4)>; + status = "okay"; +}; + +&framebuffer0 { + width = <1440>; + height = <3120>; + stride = <(1440 * 4)>; + format = "a8r8g8b8"; + status = "okay"; +}; diff --git a/src/arm64/exynos/google/gs101.dtsi b/src/arm64/exynos/google/gs101.dtsi index c5335dd59df..3de3a758f11 100644 --- a/src/arm64/exynos/google/gs101.dtsi +++ b/src/arm64/exynos/google/gs101.dtsi @@ -73,7 +73,7 @@ compatible = "arm,cortex-a55"; reg = <0x0000>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -83,7 +83,7 @@ compatible = "arm,cortex-a55"; reg = <0x0100>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -93,7 +93,7 @@ compatible = "arm,cortex-a55"; reg = <0x0200>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -103,7 +103,7 @@ compatible = "arm,cortex-a55"; reg = <0x0300>; enable-method = "psci"; - cpu-idle-states = <&ANANKE_CPU_SLEEP>; + cpu-idle-states = <&ananke_cpu_sleep>; capacity-dmips-mhz = <250>; dynamic-power-coefficient = <70>; }; @@ -113,7 +113,7 @@ compatible = "arm,cortex-a76"; reg = <0x0400>; enable-method = "psci"; - cpu-idle-states = <&ENYO_CPU_SLEEP>; + cpu-idle-states = <&enyo_cpu_sleep>; capacity-dmips-mhz = <620>; dynamic-power-coefficient = <284>; }; @@ -123,7 +123,7 @@ compatible = "arm,cortex-a76"; reg = <0x0500>; enable-method = "psci"; - cpu-idle-states = <&ENYO_CPU_SLEEP>; + cpu-idle-states = <&enyo_cpu_sleep>; capacity-dmips-mhz = <620>; dynamic-power-coefficient = <284>; }; @@ -133,7 +133,7 @@ compatible = "arm,cortex-x1"; reg = <0x0600>; enable-method = "psci"; - cpu-idle-states = <&HERA_CPU_SLEEP>; + cpu-idle-states = <&hera_cpu_sleep>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <650>; }; @@ -143,7 +143,7 @@ compatible = "arm,cortex-x1"; reg = <0x0700>; enable-method = "psci"; - cpu-idle-states = <&HERA_CPU_SLEEP>; + cpu-idle-states = <&hera_cpu_sleep>; capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <650>; }; @@ -151,7 +151,7 @@ idle-states { entry-method = "psci"; - ANANKE_CPU_SLEEP: cpu-ananke-sleep { + ananke_cpu_sleep: cpu-ananke-sleep { idle-state-name = "c2"; compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0010000>; @@ -160,7 +160,7 @@ min-residency-us = <2000>; }; - ENYO_CPU_SLEEP: cpu-enyo-sleep { + enyo_cpu_sleep: cpu-enyo-sleep { idle-state-name = "c2"; compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0010000>; @@ -169,7 +169,7 @@ min-residency-us = <2500>; }; - HERA_CPU_SLEEP: cpu-hera-sleep { + hera_cpu_sleep: cpu-hera-sleep { idle-state-name = "c2"; compatible = "arm,idle-state"; arm,psci-suspend-param = <0x0010000>; @@ -196,6 +196,14 @@ clock-output-names = "ext-200m"; }; + firmware { + acpm_ipc: power-management { + compatible = "google,gs101-acpm-ipc"; + mboxes = <&ap2apm_mailbox>; + shmem = <&apm_sram>; + }; + }; + pmu-0 { compatible = "arm,cortex-a55-pmu"; interrupts = ; @@ -1400,18 +1408,30 @@ poweroff: syscon-poweroff { compatible = "syscon-poweroff"; - regmap = <&pmu_system_controller>; offset = <0x3e9c>; /* PAD_CTRL_PWR_HOLD */ - mask = <0x100>; /* reset value */ + mask = <0x00000100>; + value = <0x0>; }; reboot: syscon-reboot { compatible = "syscon-reboot"; - regmap = <&pmu_system_controller>; offset = <0x3a00>; /* SYSTEM_CONFIGURATION */ mask = <0x2>; /* SWRESET_SYSTEM */ value = <0x2>; /* reset value */ }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x0810>; /* EXYNOS_PMU_SYSIP_DAT0 */ + mode-bootloader = <0xfc>; + mode-charge = <0x0a>; + mode-fastboot = <0xfa>; + mode-reboot-ab-update = <0x52>; + mode-recovery = <0xff>; + mode-rescue = <0xf9>; + mode-shutdown-thermal = <0x51>; + mode-shutdown-thermal-battery = <0x51>; + }; }; pinctrl_gpio_alive: pinctrl@174d0000 { @@ -1440,6 +1460,15 @@ }; }; + ap2apm_mailbox: mailbox@17610000 { + compatible = "google,gs101-mbox"; + reg = <0x17610000 0x1000>; + clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>; + clock-names = "pclk"; + interrupts = ; + #mbox-cells = <0>; + }; + pinctrl_gsactrl: pinctrl@17940000 { compatible = "google,gs101-pinctrl"; reg = <0x17940000 0x00001000>; @@ -1454,6 +1483,7 @@ /* TODO: update once support for this CMU exists */ clocks = <0>; clock-names = "pclk"; + status = "disabled"; }; cmu_top: clock-controller@1e080000 { @@ -1466,6 +1496,14 @@ }; }; + apm_sram: sram@2039000 { + compatible = "mmio-sram"; + reg = <0x0 0x2039000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x2039000 0x40000>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = diff --git a/src/arm64/freescale/fsl-ls1088a-ten64.dts b/src/arm64/freescale/fsl-ls1088a-ten64.dts index bc0d89427fb..3a11068f221 100644 --- a/src/arm64/freescale/fsl-ls1088a-ten64.dts +++ b/src/arm64/freescale/fsl-ls1088a-ten64.dts @@ -87,6 +87,22 @@ los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>; maximum-power-milliwatt = <2000>; }; + + usb1v2_supply: regulator-usbhub-1v2 { + compatible = "regulator-fixed"; + regulator-name = "usbhub_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + system3v3_supply: regulator-system-3v3 { + compatible = "regulator-fixed"; + regulator-name = "system_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; /* XG1 - Upper SFP */ @@ -231,6 +247,12 @@ compatible = "atmel,at97sc3204t"; reg = <0x29>; }; + + usbhub: usb-hub@2d { + compatible = "microchip,usb5744"; + reg = <0x2d>; + }; + }; &i2c2 { @@ -378,10 +400,32 @@ }; }; +/* LS1088A USB Port 0 - direct to bottom USB-A port */ &usb0 { status = "okay"; }; +/* LS1088A USB Port 1 - to Microchip USB5744 USB Hub */ &usb1 { + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb424,2744"; + reg = <1>; + peer-hub = <&hub_3_0>; + i2c-bus = <&usbhub>; + vdd-supply = <&system3v3_supply>; + vdd2-supply = <&usb1v2_supply>; + }; + + hub_3_0: hub@2 { + compatible = "usb424,5744"; + reg = <2>; + peer-hub = <&hub_2_0>; + i2c-bus = <&usbhub>; + vdd-supply = <&system3v3_supply>; + vdd2-supply = <&usb1v2_supply>; + }; }; diff --git a/src/arm64/freescale/imx8-apalis-v1.1.dtsi b/src/arm64/freescale/imx8-apalis-v1.1.dtsi index a3fc945aea1..dbea1eefdee 100644 --- a/src/arm64/freescale/imx8-apalis-v1.1.dtsi +++ b/src/arm64/freescale/imx8-apalis-v1.1.dtsi @@ -790,6 +790,22 @@ status = "okay"; }; +/* Apalis HDMI Audio */ +&sai5 { + assigned-clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, + <&sai5_lpcg 0>; + assigned-clock-parents = <&aud_pll_div0_lpcg 0>, <&aud_rec1_lpcg 0>; + assigned-clock-rates = <0>, <0>, <786432000>, <49152000>, <12288000>, + <722534400>, <45158400>, <11289600>, <49152000>; +}; + /* TODO: Apalis SATA1 */ /* Apalis SPDIF1 */ diff --git a/src/arm64/freescale/imx8-ss-hsio.dtsi b/src/arm64/freescale/imx8-ss-hsio.dtsi index 70a8aa1a679..9b8b1380c4c 100644 --- a/src/arm64/freescale/imx8-ss-hsio.dtsi +++ b/src/arm64/freescale/imx8-ss-hsio.dtsi @@ -57,8 +57,9 @@ hsio_subsys: bus@5f000000 { ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; #interrupt-cells = <1>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + ; + interrupt-names = "msi", "dma"; #address-cells = <3>; #size-cells = <2>; clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, @@ -68,9 +69,9 @@ hsio_subsys: bus@5f000000 { bus-range = <0x00 0xff>; device_type = "pci"; interrupt-map = <0 0 0 1 &gic 0 105 4>, - <0 0 0 2 &gic 0 106 4>, - <0 0 0 3 &gic 0 107 4>, - <0 0 0 4 &gic 0 108 4>; + <0 0 0 2 &gic 0 106 4>, + <0 0 0 3 &gic 0 107 4>, + <0 0 0 4 &gic 0 108 4>; interrupt-map-mask = <0 0 0 0x7>; num-lanes = <1>; num-viewport = <4>; @@ -79,6 +80,25 @@ hsio_subsys: bus@5f000000 { status = "disabled"; }; + pcieb_ep: pcie-ep@5f010000 { + compatible = "fsl,imx8q-pcie-ep"; + reg = <0x5f010000 0x00010000>, + <0x80000000 0x10000000>; + reg-names = "dbi", "addr_space"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, + <&pcieb_lpcg IMX_LPCG_CLK_4>, + <&pcieb_lpcg IMX_LPCG_CLK_5>; + clock-names = "dbi", "mstr", "slv"; + power-domains = <&pd IMX_SC_R_PCIE_B>; + fsl,max-link-speed = <3>; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; + pcieb_lpcg: clock-controller@5f060000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5f060000 0x10000>; diff --git a/src/arm64/freescale/imx8dxl-evk.dts b/src/arm64/freescale/imx8dxl-evk.dts index 6259186cd4d..5f3b4014e15 100644 --- a/src/arm64/freescale/imx8dxl-evk.dts +++ b/src/arm64/freescale/imx8dxl-evk.dts @@ -191,6 +191,33 @@ enable-active-high; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + bt_sco_codec: audio-codec-bt { compatible = "linux,bt-sco"; #sound-dai-cells = <1>; @@ -420,6 +447,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; @@ -444,6 +476,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; @@ -468,6 +505,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; diff --git a/src/arm64/freescale/imx8mm-kontron-bl.dts b/src/arm64/freescale/imx8mm-kontron-bl.dts index a8ef4fba16a..d16490d8768 100644 --- a/src/arm64/freescale/imx8mm-kontron-bl.dts +++ b/src/arm64/freescale/imx8mm-kontron-bl.dts @@ -254,6 +254,10 @@ status = "okay"; }; +®_nvcc_sd { + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -454,7 +458,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 >; }; @@ -467,7 +471,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 >; }; @@ -480,7 +484,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xd0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000d0 >; }; }; diff --git a/src/arm64/freescale/imx8mm-kontron-osm-s.dtsi b/src/arm64/freescale/imx8mm-kontron-osm-s.dtsi index 663ae52b485..d4554296523 100644 --- a/src/arm64/freescale/imx8mm-kontron-osm-s.dtsi +++ b/src/arm64/freescale/imx8mm-kontron-osm-s.dtsi @@ -342,6 +342,7 @@ regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; }; }; @@ -794,7 +795,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 >; }; @@ -807,7 +808,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 >; }; @@ -820,7 +821,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 /* SDIO_A_WP */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x90 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x40000090 >; }; diff --git a/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10.dtso b/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10.dtso new file mode 100644 index 00000000000..840f8329345 --- /dev/null +++ b/src/arm64/freescale/imx8mm-phyboard-polis-peb-av-10.dtso @@ -0,0 +1,237 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "imx8mm-pinfunc.h" + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + default-brightness-level = <6>; + pwms = <&pwm4 0 50000 0>; + power-supply = <®_vdd_3v3_s>; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + brightness-levels= <0 4 8 16 32 64 128 255>; + }; + + panel { + compatible = "edt,etml1010g3dra"; + backlight = <&backlight>; + power-supply = <®_vcc_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&bridge_out>; + }; + }; + }; + + reg_sound_1v8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC_1V8_Audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_sound_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC_3V3_Analog"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + sound-peb-av-10 { + compatible = "simple-audio-card"; + simple-audio-card,name = "snd-peb-av-10"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,mclk-fs = <32>; + simple-audio-card,widgets = + "Line", "Line In", + "Speaker", "Speaker", + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Speaker", "SPOP", + "Speaker", "SPOM", + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "LINE1L", "Line In", + "LINE1R", "Line In", + "MIC3R", "Microphone Jack", + "Microphone Jack", "Mic Bias"; + + simple-audio-card,cpu { + sound-dai = <&sai5>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clk IMX8MM_CLK_SAI5>; + }; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + codec: codec@18 { + compatible = "ti,tlv320aic3007"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tlv320>; + #sound-dai-cells = <0>; + reg = <0x18>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + ai3x-gpio-func = <0xd 0x0>; + ai3x-micbias-vg = <2>; + AVDD-supply = <®_sound_3v3>; + IOVDD-supply = <®_sound_3v3>; + DRVDD-supply = <®_sound_3v3>; + DVDD-supply = <®_sound_1v8>; + }; + + eeprom@57 { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x57>; + vcc-supply = <®_vdd_3v3_s>; + }; + + eeprom@5f { + compatible = "atmel,24c32"; + pagesize = <32>; + reg = <0x5f>; + size = <32>; + vcc-supply = <®_vdd_3v3_s>; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + dsi_out: endpoint { + remote-endpoint = <&bridge_in>; + }; + }; + }; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&sai5 { + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; + assigned-clock-rates = <11289600>; + clocks = <&clk IMX8MM_CLK_SAI5_IPG>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_SAI5_ROOT>, <&clk IMX8MM_CLK_DUMMY>, + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, + <&clk IMX8MM_AUDIO_PLL2_OUT>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", + "pll11k"; + fsl,sai-mclk-direction-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +&sn65dsi83 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + bridge_in: endpoint { + remote-endpoint = <&dsi_out>; + data-lanes = <1 2 3 4>; + }; + }; + + port@2 { + reg = <2>; + bridge_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&iomuxc { + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e2 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e2 + >; + }; + pinctrl_lcd: lcd0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x12 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x12 + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 + >; + }; + + pinctrl_tlv320: tlv320grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x16 + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16 + >; + }; +}; diff --git a/src/arm64/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso b/src/arm64/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso new file mode 100644 index 00000000000..a28f51ece93 --- /dev/null +++ b/src/arm64/freescale/imx8mm-phyboard-polis-peb-eval-01.dtso @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Janine Hagemann + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include "imx8mm-pinfunc.h" + +&{/} { + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + button-0 { + label = "home"; + linux,code = ; + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + button-1 { + label = "menu"; + linux,code = ; + gpios = <&gpio5 29 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + user-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_user_leds>; + + user-led1 { + gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led2 { + gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user-led3 { + gpios = <&gpio5 28 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; +}; + +&iomuxc { + pinctrl_gpio_keys: gpio_keysgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x16 + MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 + >; + }; + + pinctrl_user_leds: user_ledsgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x16 + MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x16 + >; + }; +}; diff --git a/src/arm64/freescale/imx8mm-phyboard-polis-rdk.dts b/src/arm64/freescale/imx8mm-phyboard-polis-rdk.dts index 5eacbd9611e..be470cfb03d 100644 --- a/src/arm64/freescale/imx8mm-phyboard-polis-rdk.dts +++ b/src/arm64/freescale/imx8mm-phyboard-polis-rdk.dts @@ -219,9 +219,15 @@ status = "okay"; }; +/* RTC */ &rv3028 { + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_rtc>; + pinctrl-names = "default"; aux-voltage-chargeable = <1>; trickle-resistor-ohms = <3000>; + wakeup-source; }; &snvs_pwrkey { @@ -255,11 +261,12 @@ device-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; interrupt-names = "host-wakeup"; interrupt-parent = <&gpio2>; - interrupts = <9 IRQ_TYPE_EDGE_BOTH>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; max-speed = <2000000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_bt>; shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_vcc_3v3>; vddio-supply = <®_vcc_3v3>; }; }; @@ -332,7 +339,7 @@ fsl,pins = < MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x00 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x00 - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x00 + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x140 >; }; @@ -408,6 +415,12 @@ >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + pinctrl_tpm: tpmgrp { fsl,pins = < MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 diff --git a/src/arm64/freescale/imx8mm-phycore-no-eth.dtso b/src/arm64/freescale/imx8mm-phycore-no-eth.dtso new file mode 100644 index 00000000000..0fb4b6da6c1 --- /dev/null +++ b/src/arm64/freescale/imx8mm-phycore-no-eth.dtso @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +/dts-v1/; +/plugin/; + +ðphy0 { + status = "disabled"; +}; diff --git a/src/arm64/freescale/imx8mm-phycore-no-spiflash.dtso b/src/arm64/freescale/imx8mm-phycore-no-spiflash.dtso new file mode 100644 index 00000000000..7bfc366c168 --- /dev/null +++ b/src/arm64/freescale/imx8mm-phycore-no-spiflash.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Teresa Remmet + */ + +/dts-v1/; +/plugin/; + +&flexspi { + status = "disabled"; +}; + +&som_flash { + status = "disabled"; +}; diff --git a/src/arm64/freescale/imx8mm-phycore-rpmsg.dtso b/src/arm64/freescale/imx8mm-phycore-rpmsg.dtso new file mode 100644 index 00000000000..43d5905f3d7 --- /dev/null +++ b/src/arm64/freescale/imx8mm-phycore-rpmsg.dtso @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Dominik Haller + */ + +/dts-v1/; +/plugin/; + +#include + +&{/} { + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + m4_reserved: m4@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + vdev0vring0: vdev0vring0@b8000000 { + reg = <0 0xb8000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@b8008000 { + reg = <0 0xb8008000 0 0x8000>; + no-map; + }; + + rsc_table: rsc_table@b80ff000 { + reg = <0 0xb80ff000 0 0x1000>; + no-map; + }; + + vdevbuffer: vdevbuffer@b8400000 { + compatible = "shared-dma-pool"; + reg = <0 0xb8400000 0 0x100000>; + no-map; + }; + }; + + core-m4 { + compatible = "fsl,imx8mm-cm4"; + clocks = <&clk IMX8MM_CLK_M4_DIV>; + mboxes = <&mu 0 1 + &mu 1 1 + &mu 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, <&rsc_table>; + syscon = <&src>; + }; +}; diff --git a/src/arm64/freescale/imx8mm-phycore-som.dtsi b/src/arm64/freescale/imx8mm-phycore-som.dtsi index 6069678244f..672baba4c8d 100644 --- a/src/arm64/freescale/imx8mm-phycore-som.dtsi +++ b/src/arm64/freescale/imx8mm-phycore-som.dtsi @@ -69,7 +69,6 @@ /* Ethernet */ &fec1 { - fsl,magic-packet; phy-mode = "rgmii-id"; phy-handle = <ðphy0>; pinctrl-names = "default"; @@ -161,11 +160,13 @@ regulator-always-on; regulator-boot-on; regulator-max-microvolt = <2500000>; - regulator-min-microvolt = <1500000>; + regulator-min-microvolt = <2500000>; regulator-name = "VCC_ENET_2V5 (LDO3)"; regulator-state-mem { - regulator-off-in-suspend; + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <2500000>; + regulator-suspend-min-microvolt = <2500000>; }; }; @@ -285,9 +286,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sn65dsi83>; reg = <0x2d>; + vcc-supply = <®_vdd_1v8>; status = "disabled"; }; + /* EEPROM */ eeprom@51 { compatible = "atmel,24c32"; pagesize = <32>; @@ -295,17 +298,14 @@ vcc-supply = <®_vdd_3v3_s>; }; + /* RTC */ rv3028: rtc@52 { compatible = "microcrystal,rv3028"; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-parent = <&gpio1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; reg = <0x52>; }; }; -/* EMMC */ +/* eMMC */ &usdhc3 { assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; assigned-clock-rates = <400000000>; @@ -373,12 +373,6 @@ >; }; - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 - >; - }; - pinctrl_sn65dsi83: sn65dsi83grp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x0 diff --git a/src/arm64/freescale/imx8mm-phygate-tauri-l.dts b/src/arm64/freescale/imx8mm-phygate-tauri-l.dts index c3835b2d860..755cf9cacd2 100644 --- a/src/arm64/freescale/imx8mm-phygate-tauri-l.dts +++ b/src/arm64/freescale/imx8mm-phygate-tauri-l.dts @@ -215,8 +215,13 @@ /* RTC */ &rv3028 { + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_rtc>; + pinctrl-names = "default"; aux-voltage-chargeable = <1>; trickle-resistor-ohms = <3000>; + wakeup-source; }; &uart1 { @@ -394,6 +399,12 @@ >; }; + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0 + >; + }; + pinctrl_tempsense: tempsensegrp { fsl,pins = < MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00 diff --git a/src/arm64/freescale/imx8mm-tqma8mqml.dtsi b/src/arm64/freescale/imx8mm-tqma8mqml.dtsi index 8f58c84e14c..b82e9790ea2 100644 --- a/src/arm64/freescale/imx8mm-tqma8mqml.dtsi +++ b/src/arm64/freescale/imx8mm-tqma8mqml.dtsi @@ -65,6 +65,7 @@ spi-max-frequency = <84000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <&buck5_reg>; partitions { compatible = "fixed-partitions"; diff --git a/src/arm64/freescale/imx8mm-verdin.dtsi b/src/arm64/freescale/imx8mm-verdin.dtsi index c528594ac44..b46566f3ce2 100644 --- a/src/arm64/freescale/imx8mm-verdin.dtsi +++ b/src/arm64/freescale/imx8mm-verdin.dtsi @@ -18,20 +18,6 @@ rtc1 = &snvs_rtc; }; - backlight: backlight { - compatible = "pwm-backlight"; - brightness-levels = <0 45 63 88 119 158 203 255>; - default-brightness-level = <4>; - /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ - enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; - power-supply = <®_3p3v>; - /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ - pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; - status = "disabled"; - }; - /* Fixed clock dedicated to SPI CAN controller */ clk40m: oscillator { compatible = "fixed-clock"; @@ -66,13 +52,6 @@ status = "disabled"; }; - panel_lvds: panel-lvds { - compatible = "panel-lvds"; - backlight = <&backlight>; - data-mapping = "vesa-24"; - status = "disabled"; - }; - /* Carrier Board Supplies */ reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; @@ -165,6 +144,19 @@ startup-delay-us = <20000>; }; + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vsel>; + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + states = <1800000 0x1>, + <3300000 0x0>; + regulator-name = "PMIC_USDHC_VSELECT"; + vin-supply = <®_nvcc_sd>; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -290,7 +282,7 @@ "SODIMM_19", "", "", - "", + "PMIC_USDHC_VSELECT", "", "", "", @@ -806,6 +798,7 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; }; &wdog1 { @@ -1227,13 +1220,17 @@ ; /* SODIMM 76 */ }; + pinctrl_usdhc2_vsel: usdhc2vselgrp { + fsl,pins = + ; /* PMIC_USDHC_VSELECT */ + }; + /* * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. */ pinctrl_usdhc2: usdhc2grp { fsl,pins = - , , /* SODIMM 78 */ , /* SODIMM 74 */ , /* SODIMM 80 */ @@ -1244,7 +1241,6 @@ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = - , , , , @@ -1255,7 +1251,6 @@ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = - , , , , @@ -1267,7 +1262,6 @@ /* Avoid backfeeding with removed card power */ pinctrl_usdhc2_sleep: usdhc2slpgrp { fsl,pins = - , , , , diff --git a/src/arm64/freescale/imx8mn-bsh-smm-s2pro.dts b/src/arm64/freescale/imx8mn-bsh-smm-s2pro.dts index c6ad65becc9..475cbf9e0d1 100644 --- a/src/arm64/freescale/imx8mn-bsh-smm-s2pro.dts +++ b/src/arm64/freescale/imx8mn-bsh-smm-s2pro.dts @@ -64,7 +64,6 @@ DVDD-supply = <&buck5_reg>; reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; ai31xx-micbias-vg = ; - clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; }; }; diff --git a/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi b/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi index e68a3fd73e1..640c41b51af 100644 --- a/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi +++ b/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi @@ -63,6 +63,7 @@ spi-max-frequency = <84000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <&buck5_reg>; partitions { compatible = "fixed-partitions"; diff --git a/src/arm64/freescale/imx8mp-evk.dts b/src/arm64/freescale/imx8mp-evk.dts index 68e12a752ed..c26954e5a60 100644 --- a/src/arm64/freescale/imx8mp-evk.dts +++ b/src/arm64/freescale/imx8mp-evk.dts @@ -74,6 +74,24 @@ clock-frequency = <100000000>; }; + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + reg_audio_pwr: regulator-audio-pwr { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -586,7 +604,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <3 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; }; pca6416: gpio@20 { diff --git a/src/arm64/freescale/imx8mp-kontron-osm-s.dtsi b/src/arm64/freescale/imx8mp-kontron-osm-s.dtsi index e0e9f6f7616..b97bfeb1c30 100644 --- a/src/arm64/freescale/imx8mp-kontron-osm-s.dtsi +++ b/src/arm64/freescale/imx8mp-kontron-osm-s.dtsi @@ -311,6 +311,7 @@ regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; }; }; @@ -808,7 +809,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 >; }; @@ -820,7 +821,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 >; }; @@ -832,7 +833,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */ MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */ MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */ - MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x400001d0 >; }; diff --git a/src/arm64/freescale/imx8mp-nominal.dtsi b/src/arm64/freescale/imx8mp-nominal.dtsi new file mode 100644 index 00000000000..2ce1860b244 --- /dev/null +++ b/src/arm64/freescale/imx8mp-nominal.dtsi @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2024 Pengutronix, Ahmad Fatoum + */ + +&clk { + assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, + <&clk IMX8MP_CLK_A53_CORE>, + <&clk IMX8MP_SYS_PLL3>, + <&clk IMX8MP_CLK_NOC>, + <&clk IMX8MP_CLK_NOC_IO>, + <&clk IMX8MP_CLK_GIC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_ARM_PLL_OUT>, + <0>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL3_OUT>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <0>, <0>, + <600000000>, + <800000000>, + <600000000>, + <400000000>; + fsl,operating-mode = "nominal"; +}; + +&gpu2d { + assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>; +}; + +&gpu3d { + assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <800000000>; +}; + +&pgc_hdmimix { + assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, + <&clk IMX8MP_CLK_HDMI_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_133M>; + assigned-clock-rates = <400000000>, <133000000>; +}; + +&pgc_hsiomix { + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>; +}; + +&pgc_gpumix { + assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL3_OUT>, + <&clk IMX8MP_SYS_PLL3_OUT>; + assigned-clock-rates = <600000000>, <300000000>; +}; + +&pgc_mlmix { + assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, + <800000000>, + <300000000>; +}; + +&media_blk_ctrl { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, + <&clk IMX8MP_CLK_MEDIA_ISP>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_VIDEO_PLL1_OUT>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>, <200000000>, + <0>, <0>, <400000000>, + <1039500000>; +}; + +/delete-node/ &{noc_opp_table/opp-1000000000}; diff --git a/src/arm64/freescale/imx8mp-skov-basic.dts b/src/arm64/freescale/imx8mp-skov-basic.dts new file mode 100644 index 00000000000..5a2629f3567 --- /dev/null +++ b/src/arm64/freescale/imx8mp-skov-basic.dts @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-skov-reva.dtsi" + +/ { + model = "SKOV IMX8MP CPU basic/fallback"; + compatible = "skov,imx8mp-skov-basic", "fsl,imx8mp"; +}; diff --git a/src/arm64/freescale/imx8mp-skov-reva.dtsi b/src/arm64/freescale/imx8mp-skov-reva.dtsi index 59813ef8e2b..020f20c8ce6 100644 --- a/src/arm64/freescale/imx8mp-skov-reva.dtsi +++ b/src/arm64/freescale/imx8mp-skov-reva.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) #include "imx8mp.dtsi" +#include "imx8mp-nominal.dtsi" #include @@ -116,6 +117,11 @@ regulator-name = "24V"; regulator-min-microvolt = <24000000>; regulator-max-microvolt = <24000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg24v>; + interrupts-extended = <&gpio4 23 IRQ_TYPE_EDGE_FALLING>; + system-critical-regulator; + regulator-uv-less-critical-window-ms = <50>; }; reg_can2rs: regulator-can2rs { @@ -163,6 +169,19 @@ }; }; +/* + * Board is passively cooled and heatsink is specced for continuous operation + * at 1.2 GHz only. Short bouts of 1.6 GHz are ok, but these should be done + * intentionally, not as part of suspend/resume cycles. + */ +&{/opp-table/opp-1600000000} { + /delete-property/ opp-suspend; +}; + +&{/opp-table/opp-1800000000} { + /delete-property/ opp-suspend; +}; + &A53_0 { cpu-supply = <®_vdd_arm>; }; @@ -197,7 +216,7 @@ &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; - phy-mode = "rgmii-txid"; + phy-mode = "rgmii-rxid"; status = "okay"; fixed-link { @@ -222,8 +241,11 @@ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic@25 { @@ -232,13 +254,12 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; interrupts-extended = <&gpio1 3 IRQ_TYPE_EDGE_RISING>; - sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; regulators { reg_vdd_soc: BUCK1 { regulator-name = "VDD_SOC"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -247,20 +268,20 @@ reg_vdd_arm: BUCK2 { regulator-name = "VDD_ARM"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; - nxp,dvs-run-voltage = <950000>; + nxp,dvs-run-voltage = <850000>; nxp,dvs-standby-voltage = <850000>; }; reg_vdd_3v3: BUCK4 { regulator-name = "VDD_3V3"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -268,8 +289,8 @@ reg_vdd_1v8: BUCK5 { regulator-name = "VDD_1V8"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -277,8 +298,8 @@ reg_nvcc_dram_1v1: BUCK6 { regulator-name = "NVCC_DRAM_1V1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -286,8 +307,8 @@ reg_nvcc_snvs_1v8: LDO1 { regulator-name = "NVCC_SNVS_1V8"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -295,8 +316,8 @@ reg_vdda_1v8: LDO3 { regulator-name = "VDDA_1V8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; vin-supply = <®_5v_p>; regulator-boot-on; regulator-always-on; @@ -314,10 +335,21 @@ }; }; +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + &i2c3 { - clock-frequency = <100000>; - pinctrl-names = "default"; + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; i2c_rtc: rtc@51 { @@ -332,8 +364,11 @@ &i2c4 { clock-frequency = <380000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; switch: switch@5f { @@ -391,6 +426,13 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; + /* + * While there is no CTS line, the property "uart-has-rtscts" is still + * the right thing to do to enable the UART to do RS485. In RS485-Mode + * CTS isn't used anyhow and there is no dedicated property + * "uart-has-rts-but-no-cts". + */ + uart-has-rtscts; }; &uart2 { @@ -538,6 +580,27 @@ >; }; + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c2 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 @@ -545,6 +608,13 @@ >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c2 + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 @@ -552,10 +622,16 @@ >; }; + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3 + >; + }; + pinctrl_pmic: pmicirqgrp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 - MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x41 >; }; @@ -571,6 +647,12 @@ >; }; + pinctrl_reg24v: reg24vgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x154 + >; + }; + pinctrl_reg_vsd_3v3: regvsd3v3grp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 @@ -605,6 +687,8 @@ MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x140 + /* CTS pin is not connected, but needed as workaround */ + MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x140 >; }; @@ -623,6 +707,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; }; @@ -634,6 +719,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; }; @@ -645,6 +731,7 @@ MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 >; }; diff --git a/src/arm64/freescale/imx8mp-skov-revb-hdmi.dts b/src/arm64/freescale/imx8mp-skov-revb-hdmi.dts index c1ca69da3cb..32a429437cb 100644 --- a/src/arm64/freescale/imx8mp-skov-revb-hdmi.dts +++ b/src/arm64/freescale/imx8mp-skov-revb-hdmi.dts @@ -9,12 +9,53 @@ compatible = "skov,imx8mp-skov-revb-hdmi", "fsl,imx8mp"; }; +&hdmi_pvi { + status = "okay"; +}; + +&hdmi_tx { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&hdmi_tx_phy { + status = "okay"; +}; + +&i2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c5>; + pinctrl-1 = <&pinctrl_i2c5_gpio>; + scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + clock-frequency = <100000>; + status = "okay"; +}; + +&lcdif3 { + status = "okay"; +}; + &iomuxc { pinctrl_hdmi: hdmigrp { fsl,pins = < - MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3 - MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19 >; }; + + pinctrl_i2c5: i2c5grp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x400001c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x400001c2 + >; + }; + + pinctrl_i2c5_gpio: i2c5gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x400001c2 + MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x400001c2 + >; + }; }; diff --git a/src/arm64/freescale/imx8mp-skov-revb-lt6.dts b/src/arm64/freescale/imx8mp-skov-revb-lt6.dts index ccbd3abedd6..baecf768a2e 100644 --- a/src/arm64/freescale/imx8mp-skov-revb-lt6.dts +++ b/src/arm64/freescale/imx8mp-skov-revb-lt6.dts @@ -8,6 +8,45 @@ model = "SKOV IMX8MP CPU revB - LT6"; compatible = "skov,imx8mp-skov-revb-lt6", "fsl,imx8mp"; + lvds-decoder { + compatible = "ti,sn65lvds822", "lvds-decoder"; + power-supply = <®_3v3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + in_lvds1: endpoint { + data-mapping = "vesa-24"; + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + + port@1 { + reg = <1>; + + lvds_decoder_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; + + panel { + compatible = "logictechno,lttd800480070-l6wh-rt"; + backlight = <&backlight>; + power-supply = <®_tft_vcom>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds_decoder_out>; + }; + }; + }; + touchscreen { compatible = "resistive-adc-touch"; io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, <&adc_ts 5>; @@ -78,6 +117,27 @@ }; }; +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */ + assigned-clock-rates = <0>, <462000000>; + status = "okay"; + + ports { + port@2 { + ldb_lvds_ch1: endpoint { + remote-endpoint = <&in_lvds1>; + }; + }; + }; +}; + &pwm1 { status = "okay"; }; diff --git a/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts b/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts index 2c75da5f064..45c9a6d55bc 100644 --- a/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts +++ b/src/arm64/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts @@ -27,8 +27,6 @@ &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; touchscreen@38 { @@ -51,8 +49,11 @@ }; &lvds_bridge { - /* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */ - assigned-clock-rates = <490000000>; + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */ + assigned-clock-rates = <0>, <980000000>; status = "okay"; ports { @@ -64,18 +65,6 @@ }; }; -&media_blk_ctrl { - /* currently it is not possible to let display clocks confugure - * automatically, so we need to set them manually - */ - assigned-clock-rates = <500000000>, <200000000>, <0>, - /* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */ - <70000000>, - <500000000>, - /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB */ - <490000000>; -}; - &pwm4 { status = "okay"; }; @@ -90,12 +79,3 @@ voltage-table = <3160000 73>; status = "okay"; }; - -&iomuxc { - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 - MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 - >; - }; -}; diff --git a/src/arm64/freescale/imx8mp-skov-revc-bd500.dts b/src/arm64/freescale/imx8mp-skov-revc-bd500.dts new file mode 100644 index 00000000000..b816c6cd3bc --- /dev/null +++ b/src/arm64/freescale/imx8mp-skov-revc-bd500.dts @@ -0,0 +1,91 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-skov-reva.dtsi" + +/ { + model = "SKOV IMX8MP CPU revC - bd500"; + compatible = "skov,imx8mp-skov-revc-bd500", "fsl,imx8mp"; + + leds { + led_system_red: led-3 { + label = "bd500:system:red"; + color = ; + /* Inverted compared to others due to NMOS inverter */ + gpios = <&gpioexp 3 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led_system_green: led-4 { + label = "bd500:system:green"; + color = ; + gpios = <&gpioexp 2 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + led_lan1_red: led-5 { + label = "bd500:lan1:act"; + color = ; + linux,default-trigger = "netdev"; + gpios = <&gpioexp 1 GPIO_ACTIVE_LOW>; + }; + + led_lan1_green: led-6 { + label = "bd500:lan1:link"; + color = ; + linux,default-trigger = "netdev"; + gpios = <&gpioexp 0 GPIO_ACTIVE_LOW>; + }; + + led_lan2_red: led-7 { + label = "bd500:lan2:act"; + color = ; + linux,default-trigger = "netdev"; + gpios = <&gpioexp 6 GPIO_ACTIVE_LOW>; + }; + + led_lan2_green: led-8 { + label = "bd500:lan2:link"; + color = ; + linux,default-trigger = "netdev"; + gpios = <&gpioexp 7 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-1 { + label = "S1"; + linux,code = ; + gpios = <&gpioexp 5 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + + gpioexp: gpio@20 { + compatible = "nxp,pca6408"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_exp>; + interrupts-extended = <&gpio4 28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + vcc-supply = <®_vdd_3v3>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&iomuxc { + pinctrl_gpio_exp: gpioexpgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x0 + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x0 + >; + }; +}; diff --git a/src/arm64/freescale/imx8mp-skov-revc-tian-g07017.dts b/src/arm64/freescale/imx8mp-skov-revc-tian-g07017.dts new file mode 100644 index 00000000000..9a562c011f2 --- /dev/null +++ b/src/arm64/freescale/imx8mp-skov-revc-tian-g07017.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-skov-reva.dtsi" + +/ { + model = "SKOV IMX8MP CPU revC - TIAN G07017"; + compatible = "skov,imx8mp-skov-revc-tian-g07017", "fsl,imx8mp"; + + panel { + compatible = "topland,tian-g07017-01"; + backlight = <&backlight>; + power-supply = <®_tft_vcom>; + + port { + in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&backlight { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5506"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupts-extended = <&gpio4 28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1024>; + touchscreen-size-y = <600>; + vcc-supply = <®_vdd_3v3>; + iovcc-supply = <®_vdd_3v3>; + wakeup-source; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_DISP2_PIX * 2 * 7 */ + assigned-clock-rates = <0>, <358400000>; + status = "okay"; + + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint = <&in_lvds0>; + }; + }; + }; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +®_tft_vcom { + regulator-min-microvolt = <3160000>; + regulator-max-microvolt = <3160000>; + voltage-table = <3160000 73>; + status = "okay"; +}; diff --git a/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index ae64731266f..23c612e80dd 100644 --- a/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/src/arm64/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -234,7 +234,7 @@ sound { compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "tq-tlv320aic32x"; + model = "tqm-tlv320aic32"; audio-cpu = <&sai3>; audio-codec = <&tlv320aic3x04>; }; diff --git a/src/arm64/freescale/imx8mp-tqma8mpql.dtsi b/src/arm64/freescale/imx8mp-tqma8mpql.dtsi index 3ddc5aaa7c5..6067ca3be81 100644 --- a/src/arm64/freescale/imx8mp-tqma8mpql.dtsi +++ b/src/arm64/freescale/imx8mp-tqma8mpql.dtsi @@ -41,6 +41,7 @@ spi-max-frequency = <80000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <&buck5_reg>; partitions { compatible = "fixed-partitions"; diff --git a/src/arm64/freescale/imx8mp-var-som.dtsi b/src/arm64/freescale/imx8mp-var-som.dtsi index b2ac2583a59..b59da91fdd0 100644 --- a/src/arm64/freescale/imx8mp-var-som.dtsi +++ b/src/arm64/freescale/imx8mp-var-som.dtsi @@ -35,7 +35,6 @@ <0x1 0x00000000 0 0xc0000000>; }; - reg_usdhc2_vmmc: regulator-usdhc2-vmmc { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -46,6 +45,16 @@ startup-delay-us = <100>; off-on-delay-us = <12000>; }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + regulator-name = "VSD_VSEL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + states = <3300000 0x0 1800000 0x1>; + vin-supply = <&ldo5>; + }; }; &A53_0 { @@ -205,6 +214,7 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; cd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; bus-width = <4>; status = "okay"; }; diff --git a/src/arm64/freescale/imx8mp.dtsi b/src/arm64/freescale/imx8mp.dtsi index e0d3b8cba22..7c1c87eab54 100644 --- a/src/arm64/freescale/imx8mp.dtsi +++ b/src/arm64/freescale/imx8mp.dtsi @@ -816,12 +816,12 @@ assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, <&clk IMX8MP_CLK_ML_AXI>, <&clk IMX8MP_CLK_ML_AHB>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>, + assigned-clock-rates = <1000000000>, <800000000>, - <300000000>; + <400000000>; }; pgc_audio: power-domain@5 { @@ -834,7 +834,7 @@ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, <&clk IMX8MP_SYS_PLL1_800M>; assigned-clock-rates = <400000000>, - <600000000>; + <800000000>; }; pgc_gpu2d: power-domain@6 { @@ -1619,10 +1619,11 @@ <&clk IMX8MP_CLK_SAI3>, <&clk IMX8MP_CLK_SAI5>, <&clk IMX8MP_CLK_SAI6>, - <&clk IMX8MP_CLK_SAI7>; + <&clk IMX8MP_CLK_SAI7>, + <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; clock-names = "ahb", "sai1", "sai2", "sai3", - "sai5", "sai6", "sai7"; + "sai5", "sai6", "sai7", "axi"; power-domains = <&pgc_audio>; assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; @@ -1644,6 +1645,12 @@ opp-hz = /bits/ 64 <200000000>; }; + /* Nominal drive mode maximum */ + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + }; + + /* Overdrive mode maximum */ opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; }; @@ -2232,9 +2239,9 @@ clock-names = "core", "shader", "bus", "reg"; assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, - <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>, <800000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <1000000000>, <1000000000>; power-domains = <&pgc_gpu3d>; }; @@ -2247,8 +2254,8 @@ <&clk IMX8MP_CLK_GPU_AHB>; clock-names = "core", "bus", "reg"; assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; - assigned-clock-rates = <800000000>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; + assigned-clock-rates = <1000000000>; power-domains = <&pgc_gpu2d>; }; diff --git a/src/arm64/freescale/imx8mq-librem5-devkit.dts b/src/arm64/freescale/imx8mq-librem5-devkit.dts index 9d8e7231b7c..d9f203c7951 100644 --- a/src/arm64/freescale/imx8mq-librem5-devkit.dts +++ b/src/arm64/freescale/imx8mq-librem5-devkit.dts @@ -979,24 +979,27 @@ }; &usb_dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; dr_mode = "otg"; status = "okay"; - port@0 { - reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - typec_hs: endpoint { - remote-endpoint = <&usb_con_hs>; + port@0 { + reg = <0>; + + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; }; - }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - typec_ss: endpoint { - remote-endpoint = <&usb_con_ss>; + typec_ss: endpoint { + remote-endpoint = <&usb_con_ss>; + }; }; }; }; diff --git a/src/arm64/freescale/imx8mq-librem5.dtsi b/src/arm64/freescale/imx8mq-librem5.dtsi index bb37a32ce46..9e0e2d7271e 100644 --- a/src/arm64/freescale/imx8mq-librem5.dtsi +++ b/src/arm64/freescale/imx8mq-librem5.dtsi @@ -794,7 +794,6 @@ interrupt-parent = <&gpio1>; interrupts = <10 IRQ_TYPE_LEVEL_LOW>; interrupt-names = "irq"; - extcon = <&usb3_phy0>; wakeup-source; connector { @@ -1322,25 +1321,28 @@ }; &usb_dwc3_0 { - #address-cells = <1>; - #size-cells = <0>; dr_mode = "otg"; usb-role-switch; status = "okay"; - port@0 { - reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - typec_hs: endpoint { - remote-endpoint = <&usb_con_hs>; + port@0 { + reg = <0>; + + typec_hs: endpoint { + remote-endpoint = <&usb_con_hs>; + }; }; - }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - typec_ss: endpoint { - remote-endpoint = <&usb_con_ss>; + typec_ss: endpoint { + remote-endpoint = <&usb_con_ss>; + }; }; }; }; diff --git a/src/arm64/freescale/imx8mq-tqma8mq.dtsi b/src/arm64/freescale/imx8mq-tqma8mq.dtsi index 01e5092e4c4..c92001c80f1 100644 --- a/src/arm64/freescale/imx8mq-tqma8mq.dtsi +++ b/src/arm64/freescale/imx8mq-tqma8mq.dtsi @@ -254,6 +254,7 @@ spi-max-frequency = <84000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <&nvcc_1v8_reg>; partitions { compatible = "fixed-partitions"; diff --git a/src/arm64/freescale/imx8qm-apalis-v1.1.dtsi b/src/arm64/freescale/imx8qm-apalis-v1.1.dtsi index 81ba8b2831a..b1c3f331c4e 100644 --- a/src/arm64/freescale/imx8qm-apalis-v1.1.dtsi +++ b/src/arm64/freescale/imx8qm-apalis-v1.1.dtsi @@ -9,8 +9,6 @@ / { model = "Toradex Apalis iMX8QM V1.1"; - compatible = "toradex,apalis-imx8-v1.1", - "fsl,imx8qm"; }; /* TODO: Cooling Maps */ diff --git a/src/arm64/freescale/imx8qm-apalis.dtsi b/src/arm64/freescale/imx8qm-apalis.dtsi index 4d6427fbe87..c18f57039f6 100644 --- a/src/arm64/freescale/imx8qm-apalis.dtsi +++ b/src/arm64/freescale/imx8qm-apalis.dtsi @@ -7,8 +7,6 @@ / { model = "Toradex Apalis iMX8QM"; - compatible = "toradex,apalis-imx8", - "fsl,imx8qm"; }; ðphy0 { diff --git a/src/arm64/freescale/imx8qm-mek.dts b/src/arm64/freescale/imx8qm-mek.dts index 50fd3370f7d..353f825a8ac 100644 --- a/src/arm64/freescale/imx8qm-mek.dts +++ b/src/arm64/freescale/imx8qm-mek.dts @@ -155,6 +155,13 @@ enable-active-high; }; + reg_audio: regulator-audio { + compatible = "regulator-fixed"; + regulator-name = "cs42888_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_fec2_supply: regulator-fec2-nvcc { compatible = "regulator-fixed"; regulator-name = "fec2_nvcc"; @@ -220,6 +227,33 @@ regulator-max-microvolt = <1800000>; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + bt_sco_codec: audio-codec-bt { compatible = "linux,bt-sco"; #sound-dai-cells = <1>; @@ -244,6 +278,26 @@ }; }; + sound-cs42888 { + compatible = "fsl,imx-audio-cs42888"; + model = "imx-cs42888"; + audio-cpu = <&esai0>; + audio-codec = <&cs42888>; + audio-asrc = <&asrc0>; + audio-routing = "Line Out Jack", "AOUT1L", + "Line Out Jack", "AOUT1R", + "Line Out Jack", "AOUT2L", + "Line Out Jack", "AOUT2R", + "Line Out Jack", "AOUT3L", + "Line Out Jack", "AOUT3R", + "Line Out Jack", "AOUT4L", + "Line Out Jack", "AOUT4R", + "AIN1L", "Line In Jack", + "AIN1R", "Line In Jack", + "AIN2L", "Line In Jack", + "AIN2R", "Line In Jack"; + }; + sound-wm8960 { compatible = "fsl,imx-audio-wm8960"; model = "wm8960-audio"; @@ -322,12 +376,44 @@ gpio-controller; #gpio-cells = <2>; }; + + cs42888: audio-codec@48 { + compatible = "cirrus,cs42888"; + reg = <0x48>; + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; + clock-names = "mclk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cs42888_reset>; + VA-supply = <®_audio>; + VD-supply = <®_audio>; + VLS-supply = <®_audio>; + VLC-supply = <®_audio>; + reset-gpios = <&lsio_gpio4 25 GPIO_ACTIVE_LOW>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + }; }; &cm41_intmux { status = "okay"; }; +&esai0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esai0>; + assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&esai0_lpcg IMX_LPCG_CLK_4>; + assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + status = "okay"; +}; + &hsio_phy { fsl,hsio-cfg = "pciea-pcieb-sata"; fsl,refclk-pad-mode = "input"; @@ -439,6 +525,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; }; @@ -718,6 +809,12 @@ >; }; + pinctrl_cs42888_reset: cs42888_resetgrp { + fsl,pins = < + IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c + >; + }; + pinctrl_i2c0: i2c0grp { fsl,pins = < IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 @@ -752,6 +849,21 @@ >; }; + pinctrl_esai0: esai0grp { + fsl,pins = < + IMX8QM_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 + IMX8QM_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 + IMX8QM_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 + IMX8QM_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 + IMX8QM_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 + IMX8QM_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 + IMX8QM_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 + IMX8QM_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 + IMX8QM_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 + IMX8QM_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020 diff --git a/src/arm64/freescale/imx8qm-ss-hsio.dtsi b/src/arm64/freescale/imx8qm-ss-hsio.dtsi index b1d0189a172..e80f722dbe6 100644 --- a/src/arm64/freescale/imx8qm-ss-hsio.dtsi +++ b/src/arm64/freescale/imx8qm-ss-hsio.dtsi @@ -42,6 +42,25 @@ status = "disabled"; }; + pciea_ep: pcie-ep@5f000000 { + compatible = "fsl,imx8q-pcie-ep"; + reg = <0x5f000000 0x00010000>, + <0x40000000 0x10000000>; + reg-names = "dbi", "addr_space"; + num-lanes = <1>; + interrupts = ; + interrupt-names = "dma"; + clocks = <&pciea_lpcg IMX_LPCG_CLK_6>, + <&pciea_lpcg IMX_LPCG_CLK_4>, + <&pciea_lpcg IMX_LPCG_CLK_5>; + clock-names = "dbi", "mstr", "slv"; + power-domains = <&pd IMX_SC_R_PCIE_A>; + fsl,max-link-speed = <3>; + num-ib-windows = <6>; + num-ob-windows = <6>; + status = "disabled"; + }; + pcieb: pcie@5f010000 { compatible = "fsl,imx8q-pcie"; reg = <0x5f010000 0x10000>, @@ -50,8 +69,9 @@ ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>, <0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>; #interrupt-cells = <1>; - interrupts = ; - interrupt-names = "msi"; + interrupts = , + ; + interrupt-names = "msi", "dma"; #address-cells = <3>; #size-cells = <2>; clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>, diff --git a/src/arm64/freescale/imx8qxp-mek-pcie-ep.dtso b/src/arm64/freescale/imx8qxp-mek-pcie-ep.dtso new file mode 100644 index 00000000000..4f562eb5c5b --- /dev/null +++ b/src/arm64/freescale/imx8qxp-mek-pcie-ep.dtso @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +#include + +/dts-v1/; +/plugin/; + +&pcieb { + status = "disabled"; +}; + +&pcieb_ep { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + vpcie-supply = <®_pcieb>; + status = "okay"; +}; diff --git a/src/arm64/freescale/imx8qxp-mek.dts b/src/arm64/freescale/imx8qxp-mek.dts index be79c793213..a669a5d500d 100644 --- a/src/arm64/freescale/imx8qxp-mek.dts +++ b/src/arm64/freescale/imx8qxp-mek.dts @@ -98,6 +98,33 @@ regulator-name = "cs42888_supply"; }; + reg_audio_5v: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-name = "audio-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_audio_1v8: regulator-audio-1v8 { + compatible = "regulator-fixed"; + regulator-name = "audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + reg_can_en: regulator-can-en { compatible = "regulator-fixed"; regulator-max-microvolt = <3300000>; @@ -418,6 +445,11 @@ wlf,shared-lrclk; wlf,hp-cfg = <2 2 3>; wlf,gpio-cfg = <1 3>; + AVDD-supply = <®_audio_3v3>; + DBVDD-supply = <®_audio_1v8>; + DCVDD-supply = <®_audio_1v8>; + SPKVDD1-supply = <®_audio_5v>; + SPKVDD2-supply = <®_audio_5v>; }; pca6416: gpio@20 { diff --git a/src/arm64/freescale/imx8x-colibri.dtsi b/src/arm64/freescale/imx8x-colibri.dtsi index d5abfdb8ede..ecb35c6b67f 100644 --- a/src/arm64/freescale/imx8x-colibri.dtsi +++ b/src/arm64/freescale/imx8x-colibri.dtsi @@ -295,8 +295,8 @@ "", "SODIMM_61", "SODIMM_103", - "", - "", + "SODIMM_79", + "SODIMM_97", "", "SODIMM_25", "SODIMM_27", diff --git a/src/arm64/freescale/imx93-kontron-osm-s.dtsi b/src/arm64/freescale/imx93-kontron-osm-s.dtsi index 47c1363a2f9..119a1620705 100644 --- a/src/arm64/freescale/imx93-kontron-osm-s.dtsi +++ b/src/arm64/freescale/imx93-kontron-osm-s.dtsi @@ -189,6 +189,7 @@ regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; + nxp,sd-vsel-fixed-low; }; }; }; @@ -282,6 +283,7 @@ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; vmmc-supply = <®_usdhc2_vcc>; + vqmmc-supply = <®_nvcc_sd>; cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; }; @@ -553,7 +555,6 @@ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 /* SDIO_A_D1 */ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 /* SDIO_A_D2 */ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 /* SDIO_A_D3 */ - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0 >; }; @@ -565,7 +566,6 @@ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e /* SDIO_A_D1 */ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e /* SDIO_A_D2 */ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e /* SDIO_A_D3 */ - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0 >; }; @@ -577,7 +577,6 @@ MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe /* SDIO_A_D1 */ MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe /* SDIO_A_D2 */ MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe /* SDIO_A_D3 */ - MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x1d0 >; }; diff --git a/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts b/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts index 8e939d716aa..ebbac5f8d2b 100644 --- a/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts +++ b/src/arm64/freescale/imx93-tqma9352-mba93xxca.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2022-2023 TQ-Systems GmbH , + * Copyright (c) 2022-2024 TQ-Systems GmbH , * D-82229 Seefeld, Germany. * Author: Markus Niebel * Author: Alexander Stein @@ -26,8 +26,8 @@ aliases { eeprom0 = &eeprom0; - ethernet0 = &fec; - ethernet1 = &eqos; + ethernet0 = &eqos; + ethernet1 = &fec; rtc0 = &pcf85063; rtc1 = &bbnsm_rtc; }; @@ -448,38 +448,38 @@ "WLAN_PERST#", "12V_EN"; /* - * Controls the WiFi card PD pin which is low active - * as power down signal. The output-high states, the signal - * is active, e.g. card is powered down + * Controls the WiFi card's low-active power down pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin */ wlan-pd-hog { gpio-hog; gpios = <4 GPIO_ACTIVE_LOW>; - output-high; + output-low; line-name = "WLAN_PD#"; }; /* - * Controls the WiFi card disable pin which is low active - * as disable signal. The output-high states, the signal - * is active, e.g. card is disabled + * Controls the WiFi card's low-active disable pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin */ wlan-wdisable-hog { gpio-hog; gpios = <5 GPIO_ACTIVE_LOW>; - output-high; + output-low; line-name = "WLAN_W_DISABLE#"; }; /* - * Controls the WiFi card reset pin which is low active - * as reset signal. The output-high states, the signal - * is active, e.g. card in reset + * Controls the WiFi card's reset pin. + * The output-low states, the signal is inactive, + * resulting in high signal at power-down pin */ wlan-perst-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_LOW>; - output-high; + output-low; line-name = "WLAN_PERST#"; }; }; @@ -755,12 +755,6 @@ >; }; - pinctrl_pcf85063: pcf85063grp { - fsl,pins = < - MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1000 - >; - }; - pinctrl_mipi_csi: mipicsigrp { fsl,pins = < MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x051e /* MCLK */ @@ -769,6 +763,12 @@ >; }; + pinctrl_pcf85063: pcf85063grp { + fsl,pins = < + MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1000 + >; + }; + pinctrl_pexp_irq: pexpirqgrp { fsl,pins = < /* HYS | FSEL_0 | No DSE */ @@ -783,17 +783,17 @@ >; }; - pinctrl_temp_sensor_som: tempsensorsomgrp { + pinctrl_tc9595: tc9595-grp { fsl,pins = < - /* HYS | FSEL_0 | no DSE */ - MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x1000 + /* HYS | PD | FSEL_0 | no DSE */ + MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1400 >; }; - pinctrl_tc9595: tc9595-grp { + pinctrl_temp_sensor_som: tempsensorsomgrp { fsl,pins = < - /* HYS | PD | FSEL_0 | no DSE */ - MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x1400 + /* HYS | FSEL_0 | no DSE */ + MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x1000 >; }; diff --git a/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts b/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts index 2e953a05c59..9e88c42c3d1 100644 --- a/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts +++ b/src/arm64/freescale/imx93-tqma9352-mba93xxla.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) /* - * Copyright (c) 2022-2023 TQ-Systems GmbH , + * Copyright (c) 2022-2024 TQ-Systems GmbH , * D-82229 Seefeld, Germany. * Author: Markus Niebel * Author: Alexander Stein @@ -26,8 +26,8 @@ aliases { eeprom0 = &eeprom0; - ethernet0 = &fec; - ethernet1 = &eqos; + ethernet0 = &eqos; + ethernet1 = &fec; rtc0 = &pcf85063; rtc1 = &bbnsm_rtc; }; diff --git a/src/arm64/freescale/imx93.dtsi b/src/arm64/freescale/imx93.dtsi index 56766fdb0b1..64cd0776b43 100644 --- a/src/arm64/freescale/imx93.dtsi +++ b/src/arm64/freescale/imx93.dtsi @@ -1334,6 +1334,14 @@ #index-cells = <1>; }; + memory-controller@4e300000 { + compatible = "nxp,imx9-memory-controller"; + reg = <0x4e300000 0x800>, <0x4e301000 0x1000>; + reg-names = "ctrl", "inject"; + interrupts = ; + little-endian; + }; + ddr-pmu@4e300dc0 { compatible = "fsl,imx93-ddr-pmu"; reg = <0x4e300dc0 0x200>; diff --git a/src/arm64/freescale/imx95-15x15-evk.dts b/src/arm64/freescale/imx95-15x15-evk.dts new file mode 100644 index 00000000000..514f2429dcb --- /dev/null +++ b/src/arm64/freescale/imx95-15x15-evk.dts @@ -0,0 +1,1130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "imx95.dtsi" + +#define FALLING_EDGE BIT(0) +#define RISING_EDGE BIT(1) + +#define BRD_SM_CTRL_SD3_WAKE 0x8000 +#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 +#define BRD_SM_CTRL_BT_WAKE 0x8002 +#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 +#define BRD_SM_CTRL_BUTTON 0x8004 + +/ { + compatible = "fsl,imx95-15x15-evk", "fsl,imx95"; + model = "NXP i.MX95 15X15 board"; + + aliases { + ethernet0 = &enetc_port0; + ethernet1 = &enetc_port1; + serial0 = &lpuart1; + }; + + bt_sco_codec: bt-sco-codec { + compatible = "linux,bt-sco"; + #sound-dai-cells = <1>; + }; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + stdout-path = &lpuart1; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + cooling-levels = <64 128 192 255>; + pwms = <&tpm6 0 4000000 PWM_POLARITY_INVERTED>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_vref_1v8: regulator-adc-vref { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vref_1v8"; + }; + + reg_audio_pwr: regulator-audio-pwr { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "audio-pwr"; + gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_audio_switch1: regulator-audio-switch1 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "audio-switch1"; + gpio = <&pcal6524 0 GPIO_ACTIVE_LOW>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can2-stby"; + gpio = <&pcal6524 14 GPIO_ACTIVE_LOW>; + }; + + reg_m2_pwr: regulator-m2-pwr { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "M.2-power"; + gpio = <&pcal6524 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + off-on-delay-us = <12000>; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + pinctrl-names = "default"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD_SD2_3V3"; + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usdhc3_vmmc: regulator-usdhc3 { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "WLAN_EN"; + vin-supply = <®_m2_pwr>; + gpio = <&pcal6524 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + /* + * IW612 wifi chip needs more delay than other wifi chips to complete + * the host interface initialization after power up, otherwise the + * internal state of IW612 may be unstable, resulting in the failure of + * the SDIO3.0 switch voltage. + */ + startup-delay-us = <20000>; + }; + + reg_vcc_12v: regulator-vcc-12v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <12000000>; + regulator-min-microvolt = <12000000>; + regulator-name = "VCC_12V"; + gpio = <&pcal6524 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + ranges; + #address-cells = <2>; + #size-cells = <2>; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x80000000 0 0x7F000000>; + reusable; + size = <0 0x3c000000>; + linux,cma-default; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vpu_boot: vpu_boot@a0000000 { + reg = <0 0xa0000000 0 0x100000>; + no-map; + }; + }; + + sound-bt-sco { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-inversion; + simple-audio-card,bitclock-master = <&btcpu>; + simple-audio-card,format = "dsp_a"; + simple-audio-card,frame-master = <&btcpu>; + simple-audio-card,name = "bt-sco-audio"; + + simple-audio-card,codec { + sound-dai = <&bt_sco_codec 1>; + }; + + btcpu: simple-audio-card,cpu { + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <16>; + sound-dai = <&sai1>; + }; + }; + + sound-micfil { + compatible = "fsl,imx-audio-card"; + model = "micfil-audio"; + + pri-dai-link { + format = "i2s"; + link-name = "micfil hifi"; + + cpu { + sound-dai = <&micfil>; + }; + }; + }; + + sound-wm8962 { + compatible = "fsl,imx-audio-wm8962"; + audio-codec = <&wm8962>; + audio-cpu = <&sai3>; + audio-routing = "Headphone Jack", "HPOUTL", "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", "Ext Spk", "SPKOUTR", "AMIC", "MICBIAS", + "IN3R", "AMIC", "IN1R", "AMIC"; + hp-det-gpio = <&gpio2 21 GPIO_ACTIVE_HIGH>; + model = "wm8962-audio"; + pinctrl-0 = <&pinctrl_hp>; + pinctrl-names = "default"; + }; + + sound-xcvr { + compatible = "fsl,imx-audio-card"; + model = "imx-audio-xcvr"; + + pri-dai-link { + link-name = "XCVR PCM"; + + cpu { + sound-dai = <&xcvr>; + }; + }; + }; + + usdhc3_pwrseq: usdhc3-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-0 = <&pinctrl_usdhc3_pwrseq>; + pinctrl-names = "default"; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + }; + + memory@80000000 { + reg = <0x0 0x80000000 0 0x80000000>; + device_type = "memory"; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&enetc_port0 { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc0>; + pinctrl-names = "default"; + status = "okay"; +}; + +&enetc_port1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <&pinctrl_enetc1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flexcan2 { + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&i3c2 { + i2c-scl-hz = <400000>; + pinctrl-0 = <&pinctrl_i3c2>; + pinctrl-names = "default"; + status = "okay"; + + pca9570: gpio@24 { + compatible = "nxp,pca9570"; + reg = <0x24 0 (I2C_FILTER)>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "OUT1", "OUT2", "OUT3", "OUT4"; + }; +}; + +&lpi2c2 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-names = "default"; + status = "okay"; + + wm8962: codec@1a { + compatible = "wlf,wm8962"; + reg = <0x1a>; + clocks = <&scmi_clk IMX95_CLK_SAI3>; + AVDD-supply = <®_audio_pwr>; + CPVDD-supply = <®_audio_pwr>; + DBVDD-supply = <®_audio_pwr>; + DCVDD-supply = <®_audio_pwr>; + gpio-cfg = < + 0x0000 + 0x0000 + 0x0000 + 0x0000 + 0x0000 + 0x0000 + >; + MICVDD-supply = <®_audio_pwr>; + PLLVDD-supply = <®_audio_pwr>; + SPKVDD1-supply = <®_audio_pwr>; + SPKVDD2-supply = <®_audio_pwr>; + }; + + pcal6524: gpio@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + pinctrl-0 = <&pinctrl_pcal6524>; + pinctrl-names = "default"; + }; +}; + +&lpi2c3 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-names = "default"; + status = "okay"; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio5>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_ptn5110>; + pinctrl-names = "default"; + + typec_con: connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USB-C"; + op-sink-microwatt = <15000000>; + power-role = "dual"; + self-powered; + sink-pdos = ; + source-pdos = ; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; + + pca9632: led-controller@62 { + compatible = "nxp,pca9632"; + reg = <0x62>; + #address-cells = <1>; + #size-cells = <0>; + nxp,inverted-out; + + led_backlight0: led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_BACKLIGHT; + function-enumerator = <0>; + }; + + led_backlight1: led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_BACKLIGHT; + function-enumerator = <1>; + }; + }; +}; + +&lpi2c4 { + clock-frequency = <400000>; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpi2c6 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_lpi2c6>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpuart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&lpuart5 { + pinctrl-0 = <&pinctrl_uart5>; + pinctrl-names = "default"; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + }; +}; + +&micfil { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_PDM>; + assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <49152000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_pdm>; + pinctrl-names = "default"; + status = "okay"; +}; + +&mu7 { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_bus0 { + msi-map = <0x00 &its 0x60 0x1>, //ENETC0 PF + <0x10 &its 0x61 0x1>, //ENETC0 VF0 + <0x20 &its 0x62 0x1>, //ENETC0 VF1 + <0x40 &its 0x63 0x1>, //ENETC1 PF + <0x50 &its 0x65 0x1>, //ENETC1 VF0 + <0x60 &its 0x66 0x1>, //ENETC1 VF1 + <0x80 &its 0x64 0x1>, //ENETC2 PF + <0xc0 &its 0x67 0x1>; +}; + +&netc_emdio { + pinctrl-0 = <&pinctrl_emdio>; + pinctrl-names = "default"; + status = "okay"; + + ethphy0: ethernet-phy@1 { + reg = <1>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 4 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; + + ethphy1: ethernet-phy@2 { + reg = <2>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pcal6524 5 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; +}; + +&netc_timer { + status = "okay"; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&pcie0 { + pinctrl-0 = <&pinctrl_pcie0>; + pinctrl-names = "default"; + reset-gpio = <&gpio5 13 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_m2_pwr>; + status = "okay"; +}; + +&sai1 { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI1>; + assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <12288000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_sai1>; + pinctrl-names = "default"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai3 { + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI3>; + assigned-clock-parents = <0>, <0>, <0>, <0>, <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, <3612672000>, <393216000>, <361267200>, <12288000>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_sai3>; + pinctrl-names = "default"; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&scmi_iomuxc { + pinctrl_emdio: emdiogrp { + fsl,pins = < + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x57e + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e + >; + }; + + pinctrl_enetc0: enetc0grp { + fsl,pins = < + IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x57e + IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x57e + IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x57e + IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x57e + IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e + IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e + IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e + IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e + >; + }; + + pinctrl_enetc1: enetc1grp { + fsl,pins = < + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x57e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x57e + IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x57e + IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x57e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e + IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e + IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e + >; + }; + + pinctrl_hp: hpgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21 0x31e + >; + }; + + pinctrl_i3c2: i3c2grp { + fsl,pins = < + IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40000186 + IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40000186 + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x40000b9e + IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e + IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = < + IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40000b9e + IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c6: lpi2c6grp { + fsl,pins = < + IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x40000b9e + IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x40000b9e + >; + }; + + pinctrl_mipi_dsi_csi: mipidsigrp { + fsl,pins = < + IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x31e + >; + }; + + pinctrl_pcal6524: pcal6524grp { + fsl,pins = < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40000b1e + IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e + >; + }; + + pinctrl_pdm: pdmgrp { + fsl,pins = < + IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e + IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x31e + >; + }; + + pinctrl_ptn5110: ptn5110grp { + fsl,pins = < + IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x31e + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x31e + IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e + IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e + IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x31e + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x31e + IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x31e + IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x31e + IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x31e + IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x31e + IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x31e + IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x31e + IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x31e + IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x31e + IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x31e + IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e + IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e + IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e + IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x31e + IMX95_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0 0x31e + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO22__SPDIF_IN 0x3fe + IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x3fe + >; + }; + + pinctrl_tpm3: tpm3grp { + fsl,pins = < + IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x51e + >; + }; + + pinctrl_tpm6: tpm6grp { + fsl,pins = < + IMX95_PAD_GPIO_IO08__TPM6_CH0 0x51e + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + IMX95_PAD_DAP_TDI__LPUART5_RX 0x31e + IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_pwrseq: usdhc3pwrseqgrp { + fsl,pins = < + IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x31e + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe + IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe + IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe + IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe + IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe + IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe + >; + }; +}; + +&scmi_misc { + nxp,ctrl-ids = , + , + , + , + ; +}; + +&thermal_zones { + a55-thermal { + cooling-maps { + map1 { + cooling-device = <&fan0 0 1>; + trip = <&atrip2>; + }; + + map2 { + cooling-device = <&fan0 1 2>; + trip = <&atrip3>; + }; + + map3 { + cooling-device = <&fan0 2 3>; + trip = <&atrip4>; + }; + }; + + trips { + atrip2: trip2 { + hysteresis = <2000>; + temperature = <55000>; + type = "active"; + }; + + atrip3: trip3 { + hysteresis = <2000>; + temperature = <65000>; + type = "active"; + }; + + atrip4: trip4 { + hysteresis = <2000>; + temperature = <75000>; + type = "active"; + }; + }; + }; + + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + pf09_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf09_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + cooling-maps { + map0 { + cooling-device = <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&pf5301_alert>; + }; + }; + + trips { + pf5301_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5301_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + pf53soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + pf5302_alert: trip0 { + hysteresis = <2000>; + temperature = <140000>; + type = "passive"; + }; + + pf5302_crit: trip1 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +&tpm3 { + pinctrl-0 = <&pinctrl_tpm3>; + pinctrl-names = "default"; + status = "okay"; +}; + +&tpm6 { + pinctrl-0 = <&pinctrl_tpm6>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + role-switch-default-mode = "peripheral"; + srp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +&usdhc1 { + bus-width = <8>; + non-removable; + no-sd; + no-sdio; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc2_vmmc>; + fsl,tuning-step = <1>; + status = "okay"; +}; + +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + mmc-pwrseq = <&usdhc3_pwrseq>; + non-removable; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + vmmc-supply = <®_usdhc3_vmmc>; + wakeup-source; + status = "okay"; +}; + +&wdog3 { + status = "okay"; +}; + +&xcvr { + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, + <&scmi_clk IMX95_CLK_SPDIF>, + <&dummy>, + <&scmi_clk IMX95_CLK_AUDIOXCVR>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>; + clock-names = "ipg", "phy", "spba", "pll_ipg", "pll8k", "pll11k"; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SPDIF>, + <&scmi_clk IMX95_CLK_AUDIOXCVR>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; + assigned-clock-rates = <3932160000>, <3612672000>, + <393216000>, <361267200>, + <12288000>, <0>; + #sound-dai-cells = <0>; + pinctrl-0 = <&pinctrl_spdif>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/src/arm64/freescale/imx95-19x19-evk.dts b/src/arm64/freescale/imx95-19x19-evk.dts index 8bc066c3760..25ac331f031 100644 --- a/src/arm64/freescale/imx95-19x19-evk.dts +++ b/src/arm64/freescale/imx95-19x19-evk.dts @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include "imx95.dtsi" #define FALLING_EDGE 1 @@ -317,6 +318,48 @@ interrupt-parent = <&gpio5>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; }; + + ptn5110: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_typec>; + interrupt-parent = <&gpio5>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + + typec_con: connector { + compatible = "usb-c-connector"; + label = "USB-C"; + power-role = "dual"; + data-role = "dual"; + try-power-role = "sink"; + source-pdos = ; + sink-pdos = ; + op-sink-microwatt = <0>; + self-powered; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; }; &lpuart1 { @@ -418,6 +461,40 @@ status = "okay"; }; +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + dr_mode = "otg"; + hnp-disable; + srp-disable; + adp-disable; + usb-role-switch; + role-switch-default-mode = "peripheral"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + orientation-switch; + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -676,6 +753,12 @@ >; }; + pinctrl_typec: typecgrp { + fsl,pins = < + IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e + >; + }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e diff --git a/src/arm64/freescale/imx95.dtsi b/src/arm64/freescale/imx95.dtsi index 6b8470cb346..59f057ba6fa 100644 --- a/src/arm64/freescale/imx95.dtsi +++ b/src/arm64/freescale/imx95.dtsi @@ -291,6 +291,13 @@ clock-output-names = "sai5_mclk"; }; + clk_sys100m: clock-sys100m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "clk_sys100m"; + }; + osc_24m: clock-24m { compatible = "fixed-clock"; #clock-cells = <0>; @@ -673,6 +680,19 @@ status = "disabled"; }; + i3c2: i3c@42520000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x42520000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX95_CLK_BUSAON>, + <&scmi_clk IMX95_CLK_I3C2>, + <&scmi_clk IMX95_CLK_I3C2SLOW>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + lpi2c3: i2c@42530000 { compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x42530000 0x10000>; @@ -1245,6 +1265,19 @@ status = "disabled"; }; + i3c1: i3c@44330000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x44330000 0x10000>; + interrupts = ; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&scmi_clk IMX95_CLK_BUSAON>, + <&scmi_clk IMX95_CLK_I3C1>, + <&scmi_clk IMX95_CLK_I3C1SLOW>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + lpi2c1: i2c@44340000 { compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x44340000 0x10000>; @@ -1379,6 +1412,7 @@ ; clocks = <&scmi_clk IMX95_CLK_ADC>; clock-names = "ipg"; + #io-channel-cells = <1>; status = "disabled"; }; @@ -1537,12 +1571,62 @@ }; }; + usb3: usb@4c010010 { + compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; + reg = <0x0 0x4c010010 0x0 0x04>, + <0x0 0x4c1f0000 0x0 0x20>; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_32K>; + clock-names = "hsio", "suspend"; + interrupts = ; + #address-cells = <2>; + #size-cells = <2>; + ranges; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; + status = "disabled"; + + usb3_dwc3: usb@4c100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x4c100000 0x0 0x10000>; + clocks = <&scmi_clk IMX95_CLK_HSIO>, + <&scmi_clk IMX95_CLK_24M>, + <&scmi_clk IMX95_CLK_32K>; + clock-names = "bus_early", "ref", "suspend"; + interrupts = ; + phys = <&usb3_phy>, <&usb3_phy>; + phy-names = "usb2-phy", "usb3-phy"; + snps,gfladj-refclk-lpm-sel-quirk; + snps,parkmode-disable-ss-quirk; + iommus = <&smmu 0xe>; + }; + }; + + hsio_blk_ctl: syscon@4c0100c0 { + compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; + reg = <0x0 0x4c0100c0 0x0 0x1>; + #clock-cells = <1>; + clocks = <&clk_sys100m>; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + }; + + usb3_phy: phy@4c1f0040 { + compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; + reg = <0x0 0x4c1f0040 0x0 0x40>, + <0x0 0x4c1fc000 0x0 0x100>; + clocks = <&scmi_clk IMX95_CLK_HSIO>; + clock-names = "phy"; + #phy-cells = <0>; + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + status = "disabled"; + }; + pcie0: pcie@4c300000 { compatible = "fsl,imx95-pcie"; reg = <0 0x4c300000 0 0x10000>, <0 0x60100000 0 0xfe00000>, <0 0x4c360000 0 0x10000>, - <0 0x4c340000 0 0x2000>; + <0 0x4c340000 0 0x4000>; reg-names = "dbi", "config", "atu", "app"; ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; @@ -1564,8 +1648,9 @@ clocks = <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; @@ -1573,6 +1658,12 @@ assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + /* pcie0's Devid(BIT[7:6]) is 0x00, stream id(BIT[5:0]) is 0x10~0x17 */ + msi-map = <0x0 &its 0x10 0x1>, + <0x100 &its 0x11 0x7>; + iommu-map = <0x000 &smmu 0x10 0x1>, + <0x100 &smmu 0x11 0x7>; + iommu-map-mask = <0x1ff>; fsl,max-link-speed = <3>; status = "disabled"; }; @@ -1582,7 +1673,7 @@ reg = <0 0x4c300000 0 0x10000>, <0 0x4c360000 0 0x1000>, <0 0x4c320000 0 0x1000>, - <0 0x4c340000 0 0x2000>, + <0 0x4c340000 0 0x4000>, <0 0x4c370000 0 0x10000>, <0x9 0 1 0>; reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; @@ -1609,7 +1700,7 @@ reg = <0 0x4c380000 0 0x10000>, <8 0x80100000 0 0xfe00000>, <0 0x4c3e0000 0 0x10000>, - <0 0x4c3c0000 0 0x2000>; + <0 0x4c3c0000 0 0x4000>; reg-names = "dbi", "config", "atu", "app"; ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>; @@ -1631,8 +1722,9 @@ clocks = <&scmi_clk IMX95_CLK_HSIO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, - <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, + <&hsio_blk_ctl 0>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, <&scmi_clk IMX95_CLK_HSIOPLL>, <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; @@ -1640,6 +1732,14 @@ assigned-clock-parents = <0>, <0>, <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; + /* pcie1's Devid(BIT[7:6]) is 0x10, stream id(BIT[5:0]) is 0x18~0x1f */ + msi-map = <0x0 &its 0x98 0x1>, + <0x100 &its 0x99 0x7>; + msi-map-mask = <0x1ff>; + /* smmu have not Devid(BIT[7:6]) */ + iommu-map = <0x000 &smmu 0x18 0x1>, + <0x100 &smmu 0x19 0x7>; + iommu-map-mask = <0x1ff>; fsl,max-link-speed = <3>; status = "disabled"; }; @@ -1649,7 +1749,7 @@ reg = <0 0x4c380000 0 0x10000>, <0 0x4c3e0000 0 0x1000>, <0 0x4c3a0000 0 0x1000>, - <0 0x4c3c0000 0 0x2000>, + <0 0x4c3c0000 0 0x4000>, <0 0x4c3f0000 0 0x10000>, <0xa 0 1 0>; reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; diff --git a/src/arm64/freescale/mba8mx.dtsi b/src/arm64/freescale/mba8mx.dtsi index 58e3865c288..7ee1228a50f 100644 --- a/src/arm64/freescale/mba8mx.dtsi +++ b/src/arm64/freescale/mba8mx.dtsi @@ -138,7 +138,7 @@ sound { compatible = "fsl,imx-audio-tlv320aic32x4"; - model = "imx-audio-tlv320aic32x4"; + model = "tqm-tlv320aic32"; ssi-controller = <&sai3>; audio-codec = <&tlv320aic3x04>; }; diff --git a/src/arm64/freescale/mba8xx.dtsi b/src/arm64/freescale/mba8xx.dtsi index 276d1683b03..c4b5663949a 100644 --- a/src/arm64/freescale/mba8xx.dtsi +++ b/src/arm64/freescale/mba8xx.dtsi @@ -36,6 +36,13 @@ stdout-path = &lpuart1; }; + /* Non-controllable PCIe reference clock generator */ + pcie_refclk: clock-pcie-ref { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -208,6 +215,12 @@ status = "okay"; }; +&hsio_phy { + fsl,hsio-cfg = "pciea-x2-pcieb"; + fsl,refclk-pad-mode = "input"; + status = "okay"; +}; + &i2c1 { tlv320aic3x04: audio-codec@18 { compatible = "ti,tlv320aic32x4"; @@ -309,7 +322,15 @@ "", "", "", ""; }; -/* TODO: Mini-PCIe */ +&pcieb { + phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy"; + pinctrl-0 = <&pinctrl_pcieb>; + pinctrl-names = "default"; + reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie_1v5>; + status = "okay"; +}; &sai1 { assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, @@ -467,10 +488,10 @@ fsl,pins = ; }; - pinctrl_pcieb: pcieagrp { - fsl,pins = , - , - ; + pinctrl_pcieb: pciebgrp { + fsl,pins = , + , + ; }; pinctrl_reg_pcie_1v5: regpcie1v5grp { diff --git a/src/arm64/freescale/s32g2.dtsi b/src/arm64/freescale/s32g2.dtsi index 7be430b78c8..ea1456d361a 100644 --- a/src/arm64/freescale/s32g2.dtsi +++ b/src/arm64/freescale/s32g2.dtsi @@ -317,6 +317,49 @@ }; }; + edma0: dma-controller@40144000 { + compatible = "nxp,s32g2-edma"; + reg = <0x40144000 0x24000>, + <0x4012c000 0x3000>, + <0x40130000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = , + , + ; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + + can0: can@401b4000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x401b4000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@401be000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x401be000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart0: serial@401c8000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; @@ -333,6 +376,82 @@ status = "disabled"; }; + i2c0: i2c@401e4000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401e4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c1: i2c@401e8000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401e8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c2: i2c@401ec000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x401ec000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + edma1: dma-controller@40244000 { + compatible = "nxp,s32g2-edma"; + reg = <0x40244000 0x24000>, + <0x4022c000 0x3000>, + <0x40230000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = , + , + ; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + + can2: can@402a8000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x402a8000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can3: can@402b2000 { + compatible = "nxp,s32g2-flexcan"; + reg = <0x402b2000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g2-linflexuart", "fsl,s32v234-linflexuart"; @@ -341,6 +460,28 @@ status = "disabled"; }; + i2c3: i2c@402d8000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x402d8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c4: i2c@402dc000 { + compatible = "nxp,s32g2-i2c"; + reg = <0x402dc000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + usdhc0: mmc@402f0000 { compatible = "nxp,s32g2-usdhc"; reg = <0x402f0000 0x1000>; diff --git a/src/arm64/freescale/s32g274a-evb.dts b/src/arm64/freescale/s32g274a-evb.dts index b9a119eea2b..c4a195dd67b 100644 --- a/src/arm64/freescale/s32g274a-evb.dts +++ b/src/arm64/freescale/s32g274a-evb.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "s32g2.dtsi" +#include "s32gxxxa-evb.dtsi" / { model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)"; diff --git a/src/arm64/freescale/s32g274a-rdb2.dts b/src/arm64/freescale/s32g274a-rdb2.dts index aaa61a8ad0d..b5ba51696f4 100644 --- a/src/arm64/freescale/s32g274a-rdb2.dts +++ b/src/arm64/freescale/s32g274a-rdb2.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "s32g2.dtsi" +#include "s32gxxxa-rdb.dtsi" / { model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)"; diff --git a/src/arm64/freescale/s32g3.dtsi b/src/arm64/freescale/s32g3.dtsi index 6c572ffe37c..991dbfbfa20 100644 --- a/src/arm64/freescale/s32g3.dtsi +++ b/src/arm64/freescale/s32g3.dtsi @@ -374,6 +374,51 @@ }; }; + edma0: dma-controller@40144000 { + compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; + reg = <0x40144000 0x24000>, + <0x4012c000 0x3000>, + <0x40130000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = , + , + ; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + + can0: can@401b4000 { + compatible = "nxp,s32g3-flexcan", + "nxp,s32g2-flexcan"; + reg = <0x401b4000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@401be000 { + compatible = "nxp,s32g3-flexcan", + "nxp,s32g2-flexcan"; + reg = <0x401be000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart0: serial@401c8000 { compatible = "nxp,s32g3-linflexuart", "fsl,s32v234-linflexuart"; @@ -390,6 +435,87 @@ status = "disabled"; }; + i2c0: i2c@401e4000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x401e4000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c1: i2c@401e8000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x401e8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c2: i2c@401ec000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x401ec000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + edma1: dma-controller@40244000 { + compatible = "nxp,s32g3-edma", "nxp,s32g2-edma"; + reg = <0x40244000 0x24000>, + <0x4022c000 0x3000>, + <0x40230000 0x3000>; + #dma-cells = <2>; + dma-channels = <32>; + interrupts = , + , + ; + interrupt-names = "tx-0-15", + "tx-16-31", + "err"; + clocks = <&clks 63>, <&clks 64>; + clock-names = "dmamux0", "dmamux1"; + }; + + can2: can@402a8000 { + compatible = "nxp,s32g3-flexcan", + "nxp,s32g2-flexcan"; + reg = <0x402a8000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can3: can@402b2000 { + compatible = "nxp,s32g3-flexcan", + "nxp,s32g2-flexcan"; + reg = <0x402b2000 0xa000>; + interrupts = , + , + , + ; + interrupt-names = "mb-0", "state", "berr", "mb-1"; + clocks = <&clks 9>, <&clks 11>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart2: serial@402bc000 { compatible = "nxp,s32g3-linflexuart", "fsl,s32v234-linflexuart"; @@ -398,6 +524,30 @@ status = "disabled"; }; + i2c3: i2c@402d8000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x402d8000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + + i2c4: i2c@402dc000 { + compatible = "nxp,s32g3-i2c", + "nxp,s32g2-i2c"; + reg = <0x402dc000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks 40>; + clock-names = "ipg"; + status = "disabled"; + }; + usdhc0: mmc@402f0000 { compatible = "nxp,s32g3-usdhc", "nxp,s32g2-usdhc"; diff --git a/src/arm64/freescale/s32g399a-rdb3.dts b/src/arm64/freescale/s32g399a-rdb3.dts index 828e353455b..802f543cae4 100644 --- a/src/arm64/freescale/s32g399a-rdb3.dts +++ b/src/arm64/freescale/s32g399a-rdb3.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "s32g3.dtsi" +#include "s32gxxxa-rdb.dtsi" / { model = "NXP S32G3 Reference Design Board 3 (S32G-VNP-RDB3)"; @@ -39,6 +40,14 @@ status = "okay"; }; +&i2c4 { + current-sensor@40 { + compatible = "ti,ina231"; + reg = <0x40>; + shunt-resistor = <1000>; + }; +}; + &usdhc0 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc0>; diff --git a/src/arm64/freescale/s32gxxxa-evb.dtsi b/src/arm64/freescale/s32gxxxa-evb.dtsi new file mode 100644 index 00000000000..d26af0fb8be --- /dev/null +++ b/src/arm64/freescale/s32gxxxa-evb.dtsi @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2024 NXP + * + * Authors: Ciprian Marian Costea + * Ghennadi Procopciuc + * Larisa Grigore + */ + +&pinctrl { + can0_pins: can0-pins { + can0-grp0 { + pinmux = <0x2c1>; + output-enable; + slew-rate = <133>; + }; + + can0-grp1 { + pinmux = <0x2b0>; + input-enable; + slew-rate = <133>; + }; + + can0-grp2 { + pinmux = <0x2012>; + }; + }; + + can2_pins: can2-pins { + can2-grp0 { + pinmux = <0x1b2>; + output-enable; + slew-rate = <133>; + }; + + can2-grp1 { + pinmux = <0x1c0>; + input-enable; + slew-rate = <133>; + }; + + can2-grp2 { + pinmux = <0x2782>; + }; + }; + + can3_pins: can3-pins { + can3-grp0 { + pinmux = <0x192>; + output-enable; + slew-rate = <133>; + }; + + can3-grp1 { + pinmux = <0x1a0>; + input-enable; + slew-rate = <133>; + }; + + can3-grp2 { + pinmux = <0x2792>; + }; + }; + + i2c0_pins: i2c0-pins { + i2c0-grp0 { + pinmux = <0x101>, <0x111>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c0-grp1 { + pinmux = <0x2352>, <0x2362>; + }; + }; + + i2c0_gpio_pins: i2c0-gpio-pins { + i2c0-gpio-grp0 { + pinmux = <0x100>, <0x110>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c0-gpio-grp1 { + pinmux = <0x2350>, <0x2360>; + }; + }; + + i2c1_pins: i2c1-pins { + i2c1-grp0 { + pinmux = <0x131>, <0x141>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c1-grp1 { + pinmux = <0x2cd2>, <0x2ce2>; + }; + }; + + i2c1_gpio_pins: i2c1-gpio-pins { + i2c1-gpio-grp0 { + pinmux = <0x130>, <0x140>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c1-gpio-grp1 { + pinmux = <0x2cd0>, <0x2ce0>; + }; + }; + + i2c2_pins: i2c2-pins { + i2c2-grp0 { + pinmux = <0x151>, <0x161>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c2-grp1 { + pinmux = <0x2cf2>, <0x2d02>; + }; + }; + + i2c2_gpio_pins: i2c2-gpio-pins { + i2c2-gpio-grp0 { + pinmux = <0x150>, <0x160>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c2-gpio-grp1 { + pinmux = <0x2cf0>, <0x2d00>; + }; + }; + + i2c4_pins: i2c4-pins { + i2c4-grp0 { + pinmux = <0x211>, <0x222>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c4-grp1 { + pinmux = <0x2d43>, <0x2d33>; + }; + }; + + i2c4_gpio_pins: i2c4-gpio-pins { + i2c4-gpio-grp0 { + pinmux = <0x210>, <0x220>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c4-gpio-grp1 { + pinmux = <0x2d40>, <0x2d30>; + }; + }; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&can2_pins>; + status = "okay"; +}; + +&can3 { + pinctrl-names = "default"; + pinctrl-0 = <&can3_pins>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-1 = <&i2c0_gpio_pins>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_pins>; + pinctrl-1 = <&i2c1_gpio_pins>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&i2c2_gpio_pins>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&i2c4_gpio_pins>; + status = "okay"; +}; diff --git a/src/arm64/freescale/s32gxxxa-rdb.dtsi b/src/arm64/freescale/s32gxxxa-rdb.dtsi new file mode 100644 index 00000000000..ba53ec622f0 --- /dev/null +++ b/src/arm64/freescale/s32gxxxa-rdb.dtsi @@ -0,0 +1,170 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright 2024 NXP + * + * Authors: Ciprian Marian Costea + * Ghennadi Procopciuc + * Larisa Grigore + */ + +&pinctrl { + can0_pins: can0-pins { + can0-grp0 { + pinmux = <0x112>; + output-enable; + slew-rate = <133>; + }; + + can0-grp1 { + pinmux = <0x120>; + input-enable; + slew-rate = <133>; + }; + + can0-grp2 { + pinmux = <0x2013>; + }; + }; + + can1_pins: can1-pins { + can1-grp0 { + pinmux = <0x132>; + output-enable; + slew-rate = <133>; + }; + + can1-grp1 { + pinmux = <0x140>; + input-enable; + slew-rate = <133>; + }; + + can1-grp2 { + pinmux = <0x2772>; + }; + }; + + i2c0_pins: i2c0-pins { + i2c0-grp0 { + pinmux = <0x1f2>, <0x201>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c0-grp1 { + pinmux = <0x2353>, <0x2363>; + }; + }; + + i2c0_gpio_pins: i2c0-gpio-pins { + i2c0-gpio-grp0 { + pinmux = <0x1f0>, <0x200>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c0-gpio-grp1 { + pinmux = <0x2350>, <0x2360>; + }; + }; + + i2c2_pins: i2c2-pins { + i2c2-grp0 { + pinmux = <0x151>, <0x161>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c2-grp1 { + pinmux = <0x2cf2>, <0x2d02>; + }; + }; + + i2c2_gpio_pins: i2c2-gpio-pins { + i2c2-gpio-grp0 { + pinmux = <0x2cf0>, <0x2d00>; + }; + + i2c2-gpio-grp1 { + pinmux = <0x150>, <0x160>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + }; + + i2c4_pins: i2c4-pins { + i2c4-grp0 { + pinmux = <0x211>, <0x222>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c4-grp1 { + pinmux = <0x2d43>, <0x2d33>; + }; + }; + + i2c4_gpio_pins: i2c4-gpio-pins { + i2c4-gpio-grp0 { + pinmux = <0x210>, <0x220>; + drive-open-drain; + output-enable; + input-enable; + slew-rate = <133>; + }; + + i2c4-gpio-grp1 { + pinmux = <0x2d40>, <0x2d30>; + }; + }; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-1 = <&i2c0_gpio_pins>; + status = "okay"; + + pcal6524: gpio-expander@22 { + compatible = "nxp,pcal6524"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-1 = <&i2c2_gpio_pins>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&i2c4_gpio_pins>; + status = "okay"; +}; diff --git a/src/arm64/freescale/tqma8xx.dtsi b/src/arm64/freescale/tqma8xx.dtsi index 366912bf3d5..58693b774d4 100644 --- a/src/arm64/freescale/tqma8xx.dtsi +++ b/src/arm64/freescale/tqma8xx.dtsi @@ -65,6 +65,7 @@ spi-max-frequency = <66000000>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; + vcc-supply = <®_1v8>; partitions { compatible = "fixed-partitions"; @@ -74,8 +75,6 @@ }; }; -/* TODO GPU */ - &i2c1 { #address-cells = <1>; #size-cells = <0>; @@ -114,6 +113,15 @@ }; }; +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + + &mu_m0 { status = "okay"; }; diff --git a/src/arm64/hisilicon/hi3660-coresight.dtsi b/src/arm64/hisilicon/hi3660-coresight.dtsi index 79a55a0fa2f..4c6a075908d 100644 --- a/src/arm64/hisilicon/hi3660-coresight.dtsi +++ b/src/arm64/hisilicon/hi3660-coresight.dtsi @@ -17,6 +17,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu0>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -34,6 +35,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu1>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -51,6 +53,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu2>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -68,6 +71,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu3>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -160,6 +164,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu4>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -177,6 +182,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu5>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -194,6 +200,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu6>; + arm,coresight-loses-context-with-cpu; out-ports { port { @@ -211,6 +218,7 @@ clocks = <&crg_ctrl HI3660_PCLK>; clock-names = "apb_pclk"; cpu = <&cpu7>; + arm,coresight-loses-context-with-cpu; out-ports { port { diff --git a/src/arm64/marvell/ac5-98dx25xx.dtsi b/src/arm64/marvell/ac5-98dx25xx.dtsi index 75377c292bc..605f5be1538 100644 --- a/src/arm64/marvell/ac5-98dx25xx.dtsi +++ b/src/arm64/marvell/ac5-98dx25xx.dtsi @@ -78,7 +78,7 @@ #size-cells = <2>; ranges; - internal-regs@7f000000 { + bus@7f000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; diff --git a/src/arm64/marvell/armada-371x.dtsi b/src/arm64/marvell/armada-371x.dtsi deleted file mode 100644 index dc1182ec9fa..00000000000 --- a/src/arm64/marvell/armada-371x.dtsi +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 371x family of SoCs - * (also named 88F3710) - * - * Copyright (C) 2016 Marvell - * - * Gregory CLEMENT - * - */ - -#include "armada-37xx.dtsi" - -/ { - model = "Marvell Armada 3710 SoC"; - compatible = "marvell,armada3710", "marvell,armada3700"; -}; diff --git a/src/arm64/marvell/armada-3720-db.dts b/src/arm64/marvell/armada-3720-db.dts index 0cfb3849202..bd4e61d5448 100644 --- a/src/arm64/marvell/armada-3720-db.dts +++ b/src/arm64/marvell/armada-3720-db.dts @@ -18,7 +18,7 @@ / { model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3"; - compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3700"; + compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710"; chosen { stdout-path = "serial0:115200n8"; diff --git a/src/arm64/marvell/armada-3720-espressobin-emmc.dts b/src/arm64/marvell/armada-3720-espressobin-emmc.dts index 6715a19c148..5c4d8f37970 100644 --- a/src/arm64/marvell/armada-3720-espressobin-emmc.dts +++ b/src/arm64/marvell/armada-3720-espressobin-emmc.dts @@ -18,7 +18,7 @@ / { model = "Globalscale Marvell ESPRESSOBin Board (eMMC)"; compatible = "globalscale,espressobin-emmc", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3700"; + "marvell,armada3720", "marvell,armada3710"; }; &sdhci0 { diff --git a/src/arm64/marvell/armada-3720-espressobin-ultra.dts b/src/arm64/marvell/armada-3720-espressobin-ultra.dts index b3cc2b7b5d1..97a180c8dcd 100644 --- a/src/arm64/marvell/armada-3720-espressobin-ultra.dts +++ b/src/arm64/marvell/armada-3720-espressobin-ultra.dts @@ -13,7 +13,7 @@ / { model = "Globalscale Marvell ESPRESSOBin Ultra Board"; compatible = "globalscale,espressobin-ultra", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3700"; + "marvell,armada3720", "marvell,armada3710"; aliases { /* ethernet1 is WAN port */ diff --git a/src/arm64/marvell/armada-3720-espressobin-v7-emmc.dts b/src/arm64/marvell/armada-3720-espressobin-v7-emmc.dts index 2a8aa3901a9..75401eab4d4 100644 --- a/src/arm64/marvell/armada-3720-espressobin-v7-emmc.dts +++ b/src/arm64/marvell/armada-3720-espressobin-v7-emmc.dts @@ -19,7 +19,7 @@ model = "Globalscale Marvell ESPRESSOBin Board V7 (eMMC)"; compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7", "globalscale,espressobin", "marvell,armada3720", - "marvell,armada3700"; + "marvell,armada3710"; aliases { /* ethernet1 is wan port */ diff --git a/src/arm64/marvell/armada-3720-espressobin-v7.dts b/src/arm64/marvell/armada-3720-espressobin-v7.dts index b03af87611a..48a7f50fb42 100644 --- a/src/arm64/marvell/armada-3720-espressobin-v7.dts +++ b/src/arm64/marvell/armada-3720-espressobin-v7.dts @@ -18,7 +18,7 @@ / { model = "Globalscale Marvell ESPRESSOBin Board V7"; compatible = "globalscale,espressobin-v7", "globalscale,espressobin", - "marvell,armada3720", "marvell,armada3700"; + "marvell,armada3720", "marvell,armada3710"; aliases { /* ethernet1 is wan port */ diff --git a/src/arm64/marvell/armada-3720-espressobin.dts b/src/arm64/marvell/armada-3720-espressobin.dts index c5a834b33b7..1542d836c09 100644 --- a/src/arm64/marvell/armada-3720-espressobin.dts +++ b/src/arm64/marvell/armada-3720-espressobin.dts @@ -16,5 +16,5 @@ / { model = "Globalscale Marvell ESPRESSOBin Board"; - compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3700"; + compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710"; }; diff --git a/src/arm64/marvell/armada-3720-gl-mv1000.dts b/src/arm64/marvell/armada-3720-gl-mv1000.dts index 56930f2ce48..9f4bafeddd8 100644 --- a/src/arm64/marvell/armada-3720-gl-mv1000.dts +++ b/src/arm64/marvell/armada-3720-gl-mv1000.dts @@ -7,7 +7,7 @@ / { model = "GL.iNet GL-MV1000"; - compatible = "glinet,gl-mv1000", "marvell,armada3720"; + compatible = "glinet,gl-mv1000", "marvell,armada3720", "marvell,armada3710"; aliases { led-boot = &led_power; diff --git a/src/arm64/marvell/armada-3720-turris-mox.dts b/src/arm64/marvell/armada-3720-turris-mox.dts index 54453b0a91f..f4d73c8b1a6 100644 --- a/src/arm64/marvell/armada-3720-turris-mox.dts +++ b/src/arm64/marvell/armada-3720-turris-mox.dts @@ -14,7 +14,7 @@ / { model = "CZ.NIC Turris Mox Board"; compatible = "cznic,turris-mox", "marvell,armada3720", - "marvell,armada3700"; + "marvell,armada3710"; aliases { spi0 = &spi0; diff --git a/src/arm64/marvell/armada-3720-uDPU.dtsi b/src/arm64/marvell/armada-3720-uDPU.dtsi index 3a9b6907185..24282084570 100644 --- a/src/arm64/marvell/armada-3720-uDPU.dtsi +++ b/src/arm64/marvell/armada-3720-uDPU.dtsi @@ -26,6 +26,8 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&spi_quad_pins>; led-power1 { label = "udpu:green:power"; @@ -82,8 +84,6 @@ &spi0 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&spi_quad_pins>; flash@0 { compatible = "jedec,spi-nor"; @@ -108,6 +108,10 @@ }; }; +&spi_quad_pins { + function = "gpio"; +}; + &pinctrl_nb { i2c2_recovery_pins: i2c2-recovery-pins { groups = "i2c2"; diff --git a/src/arm64/marvell/armada-372x.dtsi b/src/arm64/marvell/armada-372x.dtsi index 02ae1e15328..b99ac4c03a4 100644 --- a/src/arm64/marvell/armada-372x.dtsi +++ b/src/arm64/marvell/armada-372x.dtsi @@ -12,9 +12,6 @@ #include "armada-37xx.dtsi" / { - model = "Marvell Armada 3720 SoC"; - compatible = "marvell,armada3720", "marvell,armada3700"; - cpus { cpu1: cpu@1 { device_type = "cpu"; diff --git a/src/arm64/marvell/armada-37xx.dtsi b/src/arm64/marvell/armada-37xx.dtsi index 9603223dd76..75b0fdc3efb 100644 --- a/src/arm64/marvell/armada-37xx.dtsi +++ b/src/arm64/marvell/armada-37xx.dtsi @@ -11,8 +11,6 @@ #include / { - model = "Marvell Armada 37xx SoC"; - compatible = "marvell,armada3700"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; @@ -78,7 +76,7 @@ #size-cells = <2>; ranges; - internal-regs@d0000000 { + bus@d0000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; diff --git a/src/arm64/marvell/armada-7020.dtsi b/src/arm64/marvell/armada-7020.dtsi index 4e46326dd12..570f901b4f4 100644 --- a/src/arm64/marvell/armada-7020.dtsi +++ b/src/arm64/marvell/armada-7020.dtsi @@ -8,9 +8,3 @@ #include "armada-ap806-dual.dtsi" #include "armada-70x0.dtsi" - -/ { - model = "Marvell Armada 7020"; - compatible = "marvell,armada7020", "marvell,armada-ap806-dual", - "marvell,armada-ap806"; -}; diff --git a/src/arm64/marvell/armada-7040.dtsi b/src/arm64/marvell/armada-7040.dtsi index 2f440711d21..710ac44870b 100644 --- a/src/arm64/marvell/armada-7040.dtsi +++ b/src/arm64/marvell/armada-7040.dtsi @@ -9,12 +9,6 @@ #include "armada-ap806-quad.dtsi" #include "armada-70x0.dtsi" -/ { - model = "Marvell Armada 7040"; - compatible = "marvell,armada7040", "marvell,armada-ap806-quad", - "marvell,armada-ap806"; -}; - &cp0_pcie0 { iommu-map = <0x0 &smmu 0x480 0x20>, diff --git a/src/arm64/marvell/armada-8020.dtsi b/src/arm64/marvell/armada-8020.dtsi index ba1307c0fad..b6fc1887609 100644 --- a/src/arm64/marvell/armada-8020.dtsi +++ b/src/arm64/marvell/armada-8020.dtsi @@ -9,12 +9,6 @@ #include "armada-ap806-dual.dtsi" #include "armada-80x0.dtsi" -/ { - model = "Marvell Armada 8020"; - compatible = "marvell,armada8020", "marvell,armada-ap806-dual", - "marvell,armada-ap806"; -}; - /* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock * in CP master is not connected (by package) to the oscillator. So * disable it. However, the RTC clock in CP slave is connected to the diff --git a/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts b/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts index 225a54ab688..90ae93274a1 100644 --- a/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts +++ b/src/arm64/marvell/armada-8040-clearfog-gt-8k.dts @@ -371,25 +371,25 @@ }; &cp0_gpio2 { - sata_reset { + sata-reset-hog { gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; output-high; }; - lte_reset { + lte-reset-hog { gpio-hog; gpios = <2 GPIO_ACTIVE_LOW>; output-low; }; - wlan_disable { + wlan_disable-hog { gpio-hog; gpios = <19 GPIO_ACTIVE_LOW>; output-low; }; - lte_disable { + lte-disable-hog { gpio-hog; gpios = <21 GPIO_ACTIVE_LOW>; output-low; diff --git a/src/arm64/marvell/armada-8040-puzzle-m801.dts b/src/arm64/marvell/armada-8040-puzzle-m801.dts index 9c25a88581e..def25d51c4b 100644 --- a/src/arm64/marvell/armada-8040-puzzle-m801.dts +++ b/src/arm64/marvell/armada-8040-puzzle-m801.dts @@ -13,7 +13,7 @@ / { model = "IEI-Puzzle-M801"; - compatible = "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; + compatible = "iei,puzzle-m801", "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; aliases { ethernet0 = &cp0_eth0; diff --git a/src/arm64/marvell/armada-8040.dtsi b/src/arm64/marvell/armada-8040.dtsi index 22c2d6ebf38..3efd9b9e689 100644 --- a/src/arm64/marvell/armada-8040.dtsi +++ b/src/arm64/marvell/armada-8040.dtsi @@ -9,12 +9,6 @@ #include "armada-ap806-quad.dtsi" #include "armada-80x0.dtsi" -/ { - model = "Marvell Armada 8040"; - compatible = "marvell,armada8040", "marvell,armada-ap806-quad", - "marvell,armada-ap806"; -}; - &cp0_pcie0 { iommu-map = <0x0 &smmu 0x480 0x20>, diff --git a/src/arm64/marvell/armada-8080.dtsi b/src/arm64/marvell/armada-8080.dtsi index 299e814d1de..32bb56f2fe3 100644 --- a/src/arm64/marvell/armada-8080.dtsi +++ b/src/arm64/marvell/armada-8080.dtsi @@ -6,9 +6,3 @@ */ #include "armada-ap810-ap0-octa-core.dtsi" - -/ { - model = "Marvell 8080 board"; - compatible = "marvell,armada-8080", "marvell,armada-ap810-octa", - "marvell,armada-ap810"; -}; diff --git a/src/arm64/marvell/armada-ap806-dual.dtsi b/src/arm64/marvell/armada-ap806-dual.dtsi index 3ed6fba1f43..82f4dedfc25 100644 --- a/src/arm64/marvell/armada-ap806-dual.dtsi +++ b/src/arm64/marvell/armada-ap806-dual.dtsi @@ -8,9 +8,6 @@ #include "armada-ap806.dtsi" / { - model = "Marvell Armada AP806 Dual"; - compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806"; - cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/src/arm64/marvell/armada-ap806-quad.dtsi b/src/arm64/marvell/armada-ap806-quad.dtsi index cf6a96ddcf4..f37f49c79a5 100644 --- a/src/arm64/marvell/armada-ap806-quad.dtsi +++ b/src/arm64/marvell/armada-ap806-quad.dtsi @@ -8,9 +8,6 @@ #include "armada-ap806.dtsi" / { - model = "Marvell Armada AP806 Quad"; - compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806"; - cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/src/arm64/marvell/armada-ap806.dtsi b/src/arm64/marvell/armada-ap806.dtsi index 866628679ac..73a570cf101 100644 --- a/src/arm64/marvell/armada-ap806.dtsi +++ b/src/arm64/marvell/armada-ap806.dtsi @@ -5,14 +5,8 @@ * Device Tree file for Marvell Armada AP806. */ -#define AP_NAME ap806 #include "armada-ap80x.dtsi" -/ { - model = "Marvell Armada AP806"; - compatible = "marvell,armada-ap806"; -}; - &ap_syscon0 { ap_clk: clock { compatible = "marvell,ap806-clock"; diff --git a/src/arm64/marvell/armada-ap807-quad.dtsi b/src/arm64/marvell/armada-ap807-quad.dtsi index 8848238f956..e8af7546e89 100644 --- a/src/arm64/marvell/armada-ap807-quad.dtsi +++ b/src/arm64/marvell/armada-ap807-quad.dtsi @@ -8,9 +8,6 @@ #include "armada-ap807.dtsi" / { - model = "Marvell Armada AP807 Quad"; - compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807"; - cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/src/arm64/marvell/armada-ap807.dtsi b/src/arm64/marvell/armada-ap807.dtsi index a3328d05fc9..196793d8715 100644 --- a/src/arm64/marvell/armada-ap807.dtsi +++ b/src/arm64/marvell/armada-ap807.dtsi @@ -5,14 +5,8 @@ * Copyright (C) 2019 Marvell Technology Group Ltd. */ -#define AP_NAME ap807 #include "armada-ap80x.dtsi" -/ { - model = "Marvell Armada AP807"; - compatible = "marvell,armada-ap807"; -}; - &ap_syscon0 { ap_clk: clock { compatible = "marvell,ap807-clock"; diff --git a/src/arm64/marvell/armada-ap80x.dtsi b/src/arm64/marvell/armada-ap80x.dtsi index fdf88cd0eb0..40e14698292 100644 --- a/src/arm64/marvell/armada-ap80x.dtsi +++ b/src/arm64/marvell/armada-ap80x.dtsi @@ -48,14 +48,29 @@ }; }; - AP_NAME { + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupt-parent = <&pic>; + interrupts = <17>; + }; + + soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; interrupt-parent = <&gic>; ranges; - config-space@f0000000 { + bus@f0000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -122,20 +137,6 @@ }; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - pmu { - compatible = "arm,cortex-a72-pmu"; - interrupt-parent = <&pic>; - interrupts = <17>; - }; - odmi: odmi@300000 { compatible = "marvell,odmi-controller"; msi-controller; diff --git a/src/arm64/marvell/armada-ap810-ap0-octa-core.dtsi b/src/arm64/marvell/armada-ap810-ap0-octa-core.dtsi index d1a7143ef3d..2e719ffc828 100644 --- a/src/arm64/marvell/armada-ap810-ap0-octa-core.dtsi +++ b/src/arm64/marvell/armada-ap810-ap0-octa-core.dtsi @@ -11,7 +11,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - compatible = "marvell,armada-ap810-octa"; cpu0: cpu@0 { device_type = "cpu"; diff --git a/src/arm64/marvell/armada-ap810-ap0.dtsi b/src/arm64/marvell/armada-ap810-ap0.dtsi index 2f9ab6b4a2c..abb37e5fc2c 100644 --- a/src/arm64/marvell/armada-ap810-ap0.dtsi +++ b/src/arm64/marvell/armada-ap810-ap0.dtsi @@ -10,10 +10,9 @@ /dts-v1/; / { - model = "Marvell Armada AP810"; - compatible = "marvell,armada-ap810"; #address-cells = <2>; #size-cells = <2>; + interrupt-parent = <&gic>; aliases { serial0 = &uart0_ap0; @@ -25,14 +24,21 @@ method = "smc"; }; - ap810-ap0 { + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + soc { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; - interrupt-parent = <&gic>; ranges; - config-space@e8000000 { + bus@e8000000 { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; @@ -62,14 +68,6 @@ }; }; - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - xor@400000 { compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; reg = <0x400000 0x1000>, diff --git a/src/arm64/marvell/armada-cp110.dtsi b/src/arm64/marvell/armada-cp110.dtsi index 4fd33b0fa56..e3cfd168bec 100644 --- a/src/arm64/marvell/armada-cp110.dtsi +++ b/src/arm64/marvell/armada-cp110.dtsi @@ -5,8 +5,4 @@ * Device Tree file for Marvell Armada CP110. */ -#define CP11X_TYPE cp110 - #include "armada-cp11x.dtsi" - -#undef CP11X_TYPE diff --git a/src/arm64/marvell/armada-cp115.dtsi b/src/arm64/marvell/armada-cp115.dtsi index 1d0a9653e68..ec6432c8db7 100644 --- a/src/arm64/marvell/armada-cp115.dtsi +++ b/src/arm64/marvell/armada-cp115.dtsi @@ -5,8 +5,4 @@ * Device Tree file for Marvell Armada CP115. */ -#define CP11X_TYPE cp115 - #include "armada-cp11x.dtsi" - -#undef CP11X_TYPE diff --git a/src/arm64/marvell/armada-cp11x.dtsi b/src/arm64/marvell/armada-cp11x.dtsi index 161beec0b6b..a057e119492 100644 --- a/src/arm64/marvell/armada-cp11x.dtsi +++ b/src/arm64/marvell/armada-cp11x.dtsi @@ -17,7 +17,7 @@ * The contents of the node are defined below, in order to * save one indentation level */ - CP11X_NAME: CP11X_NAME { }; + CP11X_NAME: CP11X_NODE_NAME(bus) { }; /* * CPs only have one sensor in the thermal IC. @@ -51,7 +51,7 @@ interrupt-parent = <&CP11X_LABEL(icu_nsr)>; ranges; - config-space@CP11X_BASE { + bus@CP11X_BASE { #address-cells = <1>; #size-cells = <1>; compatible = "simple-bus"; diff --git a/src/arm64/marvell/cn9130-sr-som.dtsi b/src/arm64/marvell/cn9130-sr-som.dtsi index cb8d54895a7..a997bbabedd 100644 --- a/src/arm64/marvell/cn9130-sr-som.dtsi +++ b/src/arm64/marvell/cn9130-sr-som.dtsi @@ -7,9 +7,6 @@ #include / { - model = "SolidRun CN9130 SoM"; - compatible = "solidrun,cn9130-sr-som", "marvell,cn9130"; - aliases { ethernet0 = &cp0_eth0; ethernet1 = &cp0_eth1; diff --git a/src/arm64/mediatek/mt6359.dtsi b/src/arm64/mediatek/mt6359.dtsi index 150ad84d5d2..7b10f9c5981 100644 --- a/src/arm64/mediatek/mt6359.dtsi +++ b/src/arm64/mediatek/mt6359.dtsi @@ -15,7 +15,8 @@ #io-channel-cells = <1>; }; - mt6359codec: mt6359codec { + mt6359codec: audio-codec { + compatible = "mediatek,mt6359-codec"; }; regulators { diff --git a/src/arm64/mediatek/mt8173-elm.dtsi b/src/arm64/mediatek/mt8173-elm.dtsi index b5d4b5baf47..0d995b342d4 100644 --- a/src/arm64/mediatek/mt8173-elm.dtsi +++ b/src/arm64/mediatek/mt8173-elm.dtsi @@ -925,8 +925,6 @@ &pwrap { pmic: pmic { compatible = "mediatek,mt6397"; - #address-cells = <1>; - #size-cells = <1>; interrupts-extended = <&pio 11 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; diff --git a/src/arm64/mediatek/mt8173.dtsi b/src/arm64/mediatek/mt8173.dtsi index 3458be7f7f6..6d1d8877b43 100644 --- a/src/arm64/mediatek/mt8173.dtsi +++ b/src/arm64/mediatek/mt8173.dtsi @@ -352,14 +352,14 @@ #clock-cells = <1>; }; - infracfg: power-controller@10001000 { + infracfg: clock-controller@10001000 { compatible = "mediatek,mt8173-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; - pericfg: power-controller@10003000 { + pericfg: clock-controller@10003000 { compatible = "mediatek,mt8173-pericfg", "syscon"; reg = <0 0x10003000 0 0x1000>; #clock-cells = <1>; @@ -564,7 +564,7 @@ memory-region = <&vpu_dma_reserved>; }; - sysirq: intpol-controller@10200620 { + sysirq: interrupt-controller@10200620 { compatible = "mediatek,mt8173-sysirq", "mediatek,mt6577-sysirq"; interrupt-controller; @@ -1255,8 +1255,7 @@ }; pwm0: pwm@1401e000 { - compatible = "mediatek,mt8173-disp-pwm", - "mediatek,mt6595-disp-pwm"; + compatible = "mediatek,mt8173-disp-pwm"; reg = <0 0x1401e000 0 0x1000>; #pwm-cells = <2>; clocks = <&mmsys CLK_MM_DISP_PWM026M>, @@ -1266,8 +1265,7 @@ }; pwm1: pwm@1401f000 { - compatible = "mediatek,mt8173-disp-pwm", - "mediatek,mt6595-disp-pwm"; + compatible = "mediatek,mt8173-disp-pwm"; reg = <0 0x1401f000 0 0x1000>; #pwm-cells = <2>; clocks = <&mmsys CLK_MM_DISP_PWM126M>, diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts b/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts index 3935d83a047..7bc7c2687d6 100644 --- a/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts +++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-damu.dts @@ -14,16 +14,13 @@ }; &touchscreen { - status = "okay"; + compatible = "elan,ekth6a12nay"; - compatible = "hid-over-i2c"; - reg = <0x10>; - interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&touchscreen_pins>; - post-power-on-delay-ms = <10>; - hid-descr-addr = <0x0001>; + vcc33-supply = <&pp3300_alw>; + vccio-supply = <&pp1800_alw>; }; &mt6358codec { diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts index 72852b76003..863f3e403de 100644 --- a/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -27,16 +27,12 @@ }; &touchscreen { - status = "okay"; + compatible = "elan,ekth6a12nay"; - compatible = "hid-over-i2c"; - reg = <0x10>; - interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&touchscreen_pins>; - post-power-on-delay-ms = <10>; - hid-descr-addr = <0x0001>; + vcc33-supply = <&pp3300_alw>; }; &qca_wifi { diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts index 757d0afd14f..e0a583ce4a0 100644 --- a/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts +++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts @@ -14,16 +14,12 @@ }; &touchscreen { - status = "okay"; + compatible = "elan,ekth6a12nay"; - compatible = "hid-over-i2c"; - reg = <0x10>; - interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&touchscreen_pins>; - post-power-on-delay-ms = <10>; - hid-descr-addr = <0x0001>; + vcc33-supply = <&pp3300_alw>; }; diff --git a/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts b/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts index 6641b087e7c..7874c9a20e1 100644 --- a/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts +++ b/src/arm64/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts @@ -14,16 +14,12 @@ }; &touchscreen { - status = "okay"; + compatible = "elan,ekth6a12nay"; - compatible = "hid-over-i2c"; - reg = <0x10>; - interrupts-extended = <&pio 155 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; pinctrl-0 = <&touchscreen_pins>; - post-power-on-delay-ms = <10>; - hid-descr-addr = <0x0001>; + vcc33-supply = <&pp3300_alw>; }; diff --git a/src/arm64/mediatek/mt8188-geralt.dtsi b/src/arm64/mediatek/mt8188-geralt.dtsi index b6abecbcfa8..c5254ae0bb9 100644 --- a/src/arm64/mediatek/mt8188-geralt.dtsi +++ b/src/arm64/mediatek/mt8188-geralt.dtsi @@ -9,6 +9,7 @@ / { aliases { + dsi0 = &disp_dsi0; i2c0 = &i2c0; i2c1 = &i2c1; i2c2 = &i2c2; @@ -273,14 +274,27 @@ port { dsi_panel_in: endpoint { - remote-endpoint = <&dsi_out>; + remote-endpoint = <&dsi0_out>; }; }; }; - port { - dsi_out: endpoint { - remote-endpoint = <&dsi_panel_in>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + remote-endpoint = <&dsi_panel_in>; + }; }; }; }; @@ -296,12 +310,74 @@ pinctrl-0 = <&disp_pwm1_pins>; }; +&dither0_in { + remote-endpoint = <&postmask0_out>; +}; + +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + +&gamma0_out { + remote-endpoint = <&postmask0_in>; +}; + &dp_intf1 { status = "okay"; - port { - dp_intf1_out: endpoint { - remote-endpoint = <&dptx_in>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dp_intf1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dp_intf1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dptx_in>; + }; }; }; }; @@ -394,6 +470,35 @@ status = "okay"; }; +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_intf1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6359_vproc2_buck_reg>; }; @@ -513,6 +618,10 @@ }; }; +&ovl0_in { + remote-endpoint = <&vdosys0_ep_main>; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pcie_pins>; @@ -1029,6 +1138,14 @@ interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; +&postmask0_in { + remote-endpoint = <&gamma0_out>; +}; + +&postmask0_out { + remote-endpoint = <&dither0_in>; +}; + &sound { pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off", "aud_etdm_spk_on", "aud_etdm_spk_off", @@ -1103,6 +1220,12 @@ }; /* USB detachable base */ +&ssusb0 { + dr_mode = "host"; + vusb33-supply = <&pp3300_s3>; + status = "okay"; +}; + &xhci0 { /* controlled by EC */ vbus-supply = <&pp3300_z1>; @@ -1110,6 +1233,12 @@ }; /* USB3 hub */ +&ssusb1 { + dr_mode = "host"; + vusb33-supply = <&pp3300_s3>; + status = "okay"; +}; + &xhci1 { vusb33-supply = <&pp3300_s3>; vbus-supply = <&pp5000_usb_vbus>; @@ -1117,6 +1246,36 @@ }; /* USB BT */ +&ssusb2 { + dr_mode = "host"; + vusb33-supply = <&pp3300_s3>; + status = "okay"; +}; + +&vdosys0 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys0_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + }; +}; + +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &xhci2 { /* no power supply since MT7921's power is controlled by PCIe */ /* MT7921's USB BT has issues with USB2 LPM */ diff --git a/src/arm64/mediatek/mt8188.dtsi b/src/arm64/mediatek/mt8188.dtsi index 338120930b8..69a8423d385 100644 --- a/src/arm64/mediatek/mt8188.dtsi +++ b/src/arm64/mediatek/mt8188.dtsi @@ -26,9 +26,11 @@ aliases { dp-intf0 = &dp_intf0; dp-intf1 = &dp_intf1; + dsc0 = &dsc0; ethdr0 = ðdr0; gce0 = &gce0; gce1 = &gce1; + merge0 = &merge0; merge1 = &merge1; merge2 = &merge2; merge3 = &merge3; @@ -492,7 +494,7 @@ }; cooling-maps { - map0 { + cpu_little0_cooling_map0: map0 { trip = <&cpu_little0_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -530,7 +532,7 @@ }; cooling-maps { - map0 { + cpu_little1_cooling_map0: map0 { trip = <&cpu_little1_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -568,7 +570,7 @@ }; cooling-maps { - map0 { + cpu_little2_cooling_map0: map0 { trip = <&cpu_little2_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -606,7 +608,7 @@ }; cooling-maps { - map0 { + cpu_little3_cooling_map0: map0 { trip = <&cpu_little3_alert0>; cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, @@ -1392,7 +1394,7 @@ compatible = "mediatek,mt8188-afe"; reg = <0 0x10b10000 0 0x10000>; assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP>; - assigned-clock-parents = <&clk26m>; + assigned-clock-parents = <&topckgen CLK_TOP_APLL1_D4>; clocks = <&clk26m>, <&apmixedsys CLK_APMIXED_APLL1>, <&apmixedsys CLK_APMIXED_APLL2>, @@ -1647,6 +1649,38 @@ status = "disabled"; }; + ssusb1: usb@11201000 { + compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + ranges = <0 0 0 0x11200000 0 0x3f00>; + #address-cells = <2>; + #size-cells = <2>; + interrupts = ; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>, + <&topckgen CLK_TOP_SSUSB_TOP_REF>, + <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck"; + phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x468 2>; + status = "disabled"; + + xhci1: usb@0 { + compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; + reg = <0 0 0 0x1000>; + reg-names = "mac"; + interrupts = ; + assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; + clock-names = "sys_ck"; + status = "disabled"; + }; + }; + eth: ethernet@11021000 { compatible = "mediatek,mt8188-gmac", "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; @@ -1744,27 +1778,6 @@ }; }; - xhci1: usb@11200000 { - compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; - reg = <0 0x11200000 0 0x1000>, - <0 0x11203e00 0 0x0100>; - reg-names = "mac", "ippc"; - interrupts = ; - phys = <&u2port1 PHY_TYPE_USB2>, - <&u3port1 PHY_TYPE_USB3>; - assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, - <&topckgen CLK_TOP_SSUSB_XHCI>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, - <&topckgen CLK_TOP_UNIVPLL_D5_D4>; - clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_BUS>, - <&topckgen CLK_TOP_SSUSB_TOP_REF>, - <&pericfg_ao CLK_PERI_AO_SSUSB_XHCI>; - clock-names = "sys_ck", "ref_ck", "mcu_ck"; - mediatek,syscon-wakeup = <&pericfg 0x468 2>; - wakeup-source; - status = "disabled"; - }; - mmc0: mmc@11230000 { compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; reg = <0 0x11230000 0 0x10000>, @@ -1792,6 +1805,20 @@ status = "disabled"; }; + mmc2: mmc@11250000 { + compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11250000 0 0x1000>, + <0 0x11e60000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC30_2>, + <&infracfg_ao CLK_INFRA_AO_MSDC2>, + <&infracfg_ao CLK_INFRA_AO_MSDC30_2>; + clock-names = "source", "hclk", "source_cg"; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + status = "disabled"; + }; + lvts_mcu: thermal-sensor@11278000 { compatible = "mediatek,mt8188-lvts-mcu"; reg = <0 0x11278000 0 0x1000>; @@ -1851,42 +1878,68 @@ #clock-cells = <1>; }; - xhci2: usb@112a0000 { - compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; - reg = <0 0x112a0000 0 0x1000>, - <0 0x112a3e00 0 0x0100>; + ssusb2: usb@112a1000 { + compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; + reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>; reg-names = "mac", "ippc"; - interrupts = ; - phys = <&u2port2 PHY_TYPE_USB2>; - assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>, - <&topckgen CLK_TOP_USB_TOP_3P>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, - <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + ranges = <0 0 0 0x112a0000 0 0x3f00>; + #address-cells = <2>; + #size-cells = <2>; + interrupts = ; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, <&topckgen CLK_TOP_SSUSB_TOP_P3_REF>, <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck"; + phys = <&u2port2 PHY_TYPE_USB2>; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x470 2>; status = "disabled"; + + xhci2: usb@0 { + compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; + reg = <0 0 0 0x1000>; + reg-names = "mac"; + interrupts = ; + assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; + clock-names = "sys_ck"; + status = "disabled"; + }; }; - xhci0: usb@112b0000 { - compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; - reg = <0 0x112b0000 0 0x1000>, - <0 0x112b3e00 0 0x0100>; + ssusb0: usb@112b1000 { + compatible = "mediatek,mt8188-mtu3", "mediatek,mtu3"; + reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>; reg-names = "mac", "ippc"; - interrupts = ; - phys = <&u2port0 PHY_TYPE_USB2>; - assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>, - <&topckgen CLK_TOP_USB_TOP_2P>; - assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, - <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + ranges = <0 0 0 0x112b0000 0 0x3f00>; + #address-cells = <2>; + #size-cells = <2>; + interrupts = ; + assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, <&topckgen CLK_TOP_SSUSB_TOP_P2_REF>, <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; clock-names = "sys_ck", "ref_ck", "mcu_ck"; - mediatek,syscon-wakeup = <&pericfg 0x460 2>; + phys = <&u2port0 PHY_TYPE_USB2>; wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x460 2>; status = "disabled"; + + xhci0: usb@0 { + compatible = "mediatek,mt8188-xhci", "mediatek,mtk-xhci"; + reg = <0 0 0 0x1000>; + reg-names = "mac"; + interrupts = ; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; + clock-names = "sys_ck"; + status = "disabled"; + }; }; pcie: pcie@112f0000 { @@ -2502,6 +2555,23 @@ iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; }; rdma0: rdma@1c002000 { @@ -2512,6 +2582,25 @@ iommus = <&vdo_iommu M4U_PORT_L1_DISP_RDMA0>; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { + remote-endpoint = <&color0_in>; + }; + }; + }; }; color0: color@1c003000 { @@ -2521,6 +2610,25 @@ interrupts = ; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color0_in: endpoint { + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + reg = <1>; + color0_out: endpoint { + remote-endpoint = <&ccorr0_in>; + }; + }; + }; }; ccorr0: ccorr@1c004000 { @@ -2530,6 +2638,25 @@ interrupts = ; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr0_in: endpoint { + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr0_out: endpoint { + remote-endpoint = <&aal0_in>; + }; + }; + }; }; aal0: aal@1c005000 { @@ -2539,6 +2666,25 @@ interrupts = ; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal0_in: endpoint { + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + reg = <1>; + aal0_out: endpoint { + remote-endpoint = <&gamma0_in>; + }; + }; + }; }; gamma0: gamma@1c006000 { @@ -2548,6 +2694,23 @@ interrupts = ; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma0_in: endpoint { + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + reg = <1>; + gamma0_out: endpoint { }; + }; + }; }; dither0: dither@1c007000 { @@ -2557,6 +2720,21 @@ interrupts = ; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + dither0_out: endpoint { }; + }; + }; }; disp_dsi0: dsi@1c008000 { @@ -2574,6 +2752,15 @@ status = "disabled"; }; + dsc0: dsc@1c009000 { + compatible = "mediatek,mt8188-disp-dsc", "mediatek,mt8195-disp-dsc"; + reg = <0 0x1c009000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; + interrupts = ; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; + }; + disp_dsi1: dsi@1c012000 { compatible = "mediatek,mt8188-dsi"; reg = <0 0x1c012000 0 0x1000>; @@ -2589,6 +2776,17 @@ status = "disabled"; }; + merge0: merge0@1c014000 { + compatible = "mediatek,mt8188-disp-merge", "mediatek,mt8195-disp-merge"; + reg = <0 0x1c014000 0 0x1000>; + clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>, + <&vdosys1 CLK_VDO1_MERGE_VDO1_DL_ASYNC>; + clock-names = "merge", "merge_async"; + interrupts = ; + power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; + }; + dp_intf0: dp-intf@1c015000 { compatible = "mediatek,mt8188-dp-intf"; reg = <0 0x1c015000 0 0x1000>; @@ -2619,6 +2817,21 @@ interrupts = ; power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + postmask0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + postmask0_out: endpoint { }; + }; + }; }; vdosys0: syscon@1c01d000 { diff --git a/src/arm64/mediatek/mt8195-cherry.dtsi b/src/arm64/mediatek/mt8195-cherry.dtsi index 5056e07399e..e70599807bb 100644 --- a/src/arm64/mediatek/mt8195-cherry.dtsi +++ b/src/arm64/mediatek/mt8195-cherry.dtsi @@ -297,12 +297,29 @@ cpu-supply = <&mt6315_6_vbuck1>; }; +&dither0_out { + remote-endpoint = <&dsc0_in>; +}; + &dp_intf0 { status = "okay"; - port { - dp_intf0_out: endpoint { - remote-endpoint = <&edp_in>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp_intf0_in: endpoint { + remote-endpoint = <&merge0_out>; + }; + }; + + port@1 { + reg = <1>; + dp_intf0_out: endpoint { + remote-endpoint = <&edp_in>; + }; }; }; }; @@ -310,9 +327,51 @@ &dp_intf1 { status = "okay"; - port { - dp_intf1_out: endpoint { - remote-endpoint = <&dptx_in>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dp_intf1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dp_intf1_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dptx_in>; + }; + }; + }; +}; + +&dsc0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsc0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsc0_out: endpoint { + remote-endpoint = <&merge0_in>; + }; }; }; }; @@ -357,6 +416,35 @@ }; }; +ðdr0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethdr0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + ethdr0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&merge5_in>; + }; + }; + }; +}; + &disp_pwm0 { status = "okay"; @@ -376,8 +464,12 @@ #size-cells = <0>; port@0 { + #address-cells = <1>; + #size-cells = <0>; reg = <0>; - dptx_in: endpoint { + + dptx_in: endpoint@1 { + reg = <1>; remote-endpoint = <&dp_intf1_out>; }; }; @@ -511,6 +603,56 @@ }; }; +&merge0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge0_in: endpoint { + remote-endpoint = <&dsc0_out>; + }; + }; + + port@1 { + reg = <1>; + merge0_out: endpoint { + remote-endpoint = <&dp_intf0_in>; + }; + }; + }; +}; + +&merge5 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + merge5_in: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + merge5_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&dp_intf1_in>; + }; + }; + }; +}; + &mfg0 { domain-supply = <&mt6315_7_vbuck1>; }; @@ -612,6 +754,10 @@ }; }; +&ovl0_in { + remote-endpoint = <&vdosys0_ep_main>; +}; + &pcie1 { status = "okay"; @@ -1363,6 +1509,18 @@ status = "okay"; }; +&vdosys0 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys0_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + }; +}; + /* * For the USB Type-C ports the role and alternate modes switching is * done by the EC so we set dr_mode to host to avoid interfering. @@ -1385,6 +1543,18 @@ status = "okay"; }; +&vdosys1 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys1_ep_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <ðdr0_in>; + }; + }; +}; + &xhci0 { status = "okay"; diff --git a/src/arm64/mediatek/mt8195.dtsi b/src/arm64/mediatek/mt8195.dtsi index f013dbad9dc..4f2dc0a7556 100644 --- a/src/arm64/mediatek/mt8195.dtsi +++ b/src/arm64/mediatek/mt8195.dtsi @@ -3142,6 +3142,23 @@ clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ovl0_in: endpoint { }; + }; + + port@1 { + reg = <1>; + ovl0_out: endpoint { + remote-endpoint = <&rdma0_in>; + }; + }; + }; }; rdma0: rdma@1c002000 { @@ -3152,6 +3169,25 @@ clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + rdma0_in: endpoint { + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + reg = <1>; + rdma0_out: endpoint { + remote-endpoint = <&color0_in>; + }; + }; + }; }; color0: color@1c003000 { @@ -3161,6 +3197,25 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + color0_in: endpoint { + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + reg = <1>; + color0_out: endpoint { + remote-endpoint = <&ccorr0_in>; + }; + }; + }; }; ccorr0: ccorr@1c004000 { @@ -3170,6 +3225,25 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + ccorr0_in: endpoint { + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + reg = <1>; + ccorr0_out: endpoint { + remote-endpoint = <&aal0_in>; + }; + }; + }; }; aal0: aal@1c005000 { @@ -3179,6 +3253,25 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + aal0_in: endpoint { + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + reg = <1>; + aal0_out: endpoint { + remote-endpoint = <&gamma0_in>; + }; + }; + }; }; gamma0: gamma@1c006000 { @@ -3188,6 +3281,25 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + gamma0_in: endpoint { + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + reg = <1>; + gamma0_out: endpoint { + remote-endpoint = <&dither0_in>; + }; + }; + }; }; dither0: dither@1c007000 { @@ -3197,6 +3309,23 @@ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dither0_in: endpoint { + remote-endpoint = <&gamma0_out>; + }; + }; + + port@1 { + reg = <1>; + dither0_out: endpoint { }; + }; + }; }; dsi0: dsi@1c008000 { diff --git a/src/arm64/mediatek/mt8365-evk.dts b/src/arm64/mediatek/mt8365-evk.dts index 44c61094c4d..1f8584bd66c 100644 --- a/src/arm64/mediatek/mt8365-evk.dts +++ b/src/arm64/mediatek/mt8365-evk.dts @@ -28,6 +28,21 @@ stdout-path = "serial0:921600n8"; }; + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "d"; + + port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_connector_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + firmware { optee { compatible = "linaro,optee-tz"; @@ -105,6 +120,16 @@ pinctrl-5 = <&aud_mosi_on_pins>; mediatek,platform = <&afe>; }; + + vsys_lcm_reg: regulator-vsys-lcm { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pio 129 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "vsys_lcm"; + }; + }; &afe { @@ -132,13 +157,102 @@ sram-supply = <&mt6357_vsram_proc_reg>; }; +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +&dpi0 { + pinctrl-0 = <&dpi_default_pins>; + pinctrl-1 = <&dpi_idle_pins>; + pinctrl-names = "default", "sleep"; + /* + * Ethernet and HDMI (DPI0) are sharing pins. + * Only one can be enabled at a time and require the physical switch + * SW2101 to be set on LAN position + */ + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dpi0_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&rdma1_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + dpi0_out: endpoint@1 { + reg = <1>; + remote-endpoint = <&it66121_in>; + }; + }; + }; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "startek,kd070fhfid015"; + reg = <0>; + enable-gpios = <&pio 67 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + iovcc-supply = <&mt6357_vsim1_reg>; + power-supply = <&vsys_lcm_reg>; + + port { + #address-cells = <1>; + #size-cells = <0>; + panel_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dsi0_out>; + }; + }; + }; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dsi0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + dsi0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + ðernet { pinctrl-0 = <ðernet_pins>; pinctrl-names = "default"; phy-handle = <ð_phy>; phy-mode = "rmii"; /* - * Ethernet and HDMI (DSI0) are sharing pins. + * Ethernet and HDMI (DPI0) are sharing pins. * Only one can be enabled at a time and require the physical switch * SW2101 to be set on LAN position * mt6357_vibr_reg and mt6357_vsim2_reg are needed to supply ethernet @@ -162,6 +276,56 @@ status = "okay"; }; +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-div = <2>; + clock-frequency = <100000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + + it66121_hdmi: hdmi@4c { + compatible = "ite,it66121"; + reg = <0x4c>; + #sound-dai-cells = <0>; + interrupt-parent = <&pio>; + interrupts = <68 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&ite_pins>; + pinctrl-names = "default"; + reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>; + vcn18-supply = <&mt6357_vsim2_reg>; + vcn33-supply = <&mt6357_vibr_reg>; + vrf12-supply = <&mt6357_vrf12_reg>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + it66121_in: endpoint@0 { + reg = <0>; + bus-width = <12>; + remote-endpoint = <&dpi0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + hdmi_connector_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; +}; + &mmc0 { assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>; assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; @@ -206,6 +370,11 @@ mediatek,micbias1-microvolt = <1700000>; }; +&mt6357_vsim1_reg { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; +}; + &pio { aud_default_pins: audiodefault-pins { clk-dat-pins { @@ -268,6 +437,49 @@ }; }; + dpi_default_pins: dpi-default-pins { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = <4>; + }; + }; + + dpi_idle_pins: dpi-idle-pins { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + ethernet_pins: ethernet-pins { phy_reset_pins { pinmux = ; @@ -309,6 +521,33 @@ }; }; + i2c1_pins: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + ite_pins: ite-pins { + irq_ite_pins { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pwr_pins { + pinmux = , + ; + output-high; + }; + + rst_ite_pins { + pinmux = ; + output-high; + }; + }; + mmc0_default_pins: mmc0-default-pins { clk-pins { pinmux = ; @@ -464,6 +703,10 @@ status = "okay"; }; +&rdma1_out { + remote-endpoint = <&dpi0_in>; +}; + &ssusb { dr_mode = "otg"; maximum-speed = "high-speed"; diff --git a/src/arm64/mediatek/mt8365.dtsi b/src/arm64/mediatek/mt8365.dtsi index 2bf8c9d02b6..e6d2b3221a3 100644 --- a/src/arm64/mediatek/mt8365.dtsi +++ b/src/arm64/mediatek/mt8365.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include @@ -19,6 +20,19 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + aal0 = &aal0; + ccorr0 = &ccorr0; + color0 = &color0; + dither0 = &dither0; + dpi0 = &dpi0; + dsi0 = &dsi0; + gamma0 = &gamma0; + ovl0 = &ovl0; + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -609,6 +623,15 @@ status = "disabled"; }; + disp_pwm: pwm@1100e000 { + compatible = "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + clock-names = "main", "mm"; + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PWM>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + #pwm-cells = <2>; + }; + i2c3: i2c@1100f000 { compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; @@ -705,6 +728,15 @@ status = "disabled"; }; + mipi_tx0: dsi-phy@11c00000 { + compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c00000 0 0x800>; + clock-output-names = "mipi_tx0_pll"; + clocks = <&clk26m>; + #clock-cells = <0>; + #phy-cells = <0>; + }; + u3phy: t-phy@11cc0000 { compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>; @@ -732,6 +764,26 @@ compatible = "mediatek,mt8365-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>; + port { + #address-cells = <1>; + #size-cells = <0>; + + mmsys_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + mmsys_ext: endpoint@1 { + reg = <1>; + remote-endpoint = <&rdma1_in>; + }; + }; + }; + + mutex: mutex@14001000 { + compatible = "mediatek,mt8365-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; }; smi_common: smi@14002000 { @@ -757,6 +809,290 @@ mediatek,larb-id = <0>; }; + ovl0: ovl@1400b000 { + compatible = "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_OVL0>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + ovl0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&mmsys_main>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + ovl0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&rdma0_in>; + }; + }; + }; + }; + + rdma0: rdma@1400d000 { + compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size = <5120>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + rdma0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + rdma0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&color0_in>; + }; + }; + }; + }; + + color0: color@1400f000 { + compatible = "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-color"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + color0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&rdma0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + color0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&ccorr0_in>; + }; + }; + }; + }; + + ccorr0: ccorr@14010000 { + compatible = "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccorr"; + reg = <0 0x14010000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + ccorr0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&color0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + ccorr0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&aal0_in>; + }; + }; + }; + }; + + aal0: aal@14011000 { + compatible = "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal"; + reg = <0 0x14011000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + aal0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&ccorr0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + aal0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&gamma0_in>; + }; + }; + }; + }; + + gamma0: gamma@14012000 { + compatible = "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamma"; + reg = <0 0x14012000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + gamma0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&aal0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + gamma0_out: endpoint@0 { + reg = <0>; + remote-endpoint = <&dither0_in>; + }; + }; + }; + }; + + dither0: dither@14013000 { + compatible = "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dither"; + reg = <0 0x14013000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dither0_in: endpoint@0 { + reg = <0>; + remote-endpoint = <&gamma0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + dither0_out: endpoint@0 { + reg = <0>; + }; + }; + }; + }; + + dsi0: dsi@14014000 { + compatible = "mediatek,mt8365-dsi", "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + clock-names = "engine", "digital", "hs"; + clocks = <&mmsys CLK_MM_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DIG_DSI>, + <&mipi_tx0>; + interrupts = ; + phy-names = "dphy"; + phys = <&mipi_tx0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma1: rdma@14016000 { + compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; + reg = <0 0x14016000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,rdma-fifo-size = <2048>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + rdma1_in: endpoint@1 { + reg = <1>; + remote-endpoint = <&mmsys_ext>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + rdma1_out: endpoint@1 { + reg = <1>; + }; + }; + }; + }; + + dpi0: dpi@14018000 { + compatible = "mediatek,mt8365-dpi", "mediatek,mt8192-dpi"; + reg = <0 0x14018000 0 0x1000>; + clocks = <&mmsys CLK_MM_DPI0_DPI0>, + <&mmsys CLK_MM_MM_DPI0>, + <&apmixedsys CLK_APMIXED_LVDSPLL>; + clock-names = "pixel", "engine", "pll"; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + status = "disabled"; + }; + camsys: syscon@15000000 { compatible = "mediatek,mt8365-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>; diff --git a/src/arm64/mediatek/mt8370-genio-510-evk.dts b/src/arm64/mediatek/mt8370-genio-510-evk.dts new file mode 100644 index 00000000000..71a8cbed1df --- /dev/null +++ b/src/arm64/mediatek/mt8370-genio-510-evk.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 Collabora Ltd. + * Author: Louis-Alexis Eyraud + */ +/dts-v1/; + +#include "mt8370.dtsi" +#include "mt8390-genio-common.dtsi" + +/ { + model = "MediaTek Genio-510 EVK"; + compatible = "mediatek,mt8370-evk", "mediatek,mt8370", "mediatek,mt8188"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x1 0x00000000>; + }; +}; diff --git a/src/arm64/mediatek/mt8370.dtsi b/src/arm64/mediatek/mt8370.dtsi new file mode 100644 index 00000000000..cf1a3759451 --- /dev/null +++ b/src/arm64/mediatek/mt8370.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2025 Collabora Ltd. + * Author: Louis-Alexis Eyraud + */ + +/dts-v1/; +#include "mt8188.dtsi" + +/ { + compatible = "mediatek,mt8370"; + + cpus { + /delete-node/ cpu@400; + /delete-node/ cpu@500; + + cpu-map { + cluster0 { + /delete-node/ core4; + /delete-node/ core5; + }; + }; + }; +}; + +&cpu6 { + clock-frequency = <2200000000>; +}; + +&cpu7 { + clock-frequency = <2200000000>; +}; + +&cpu_little0_cooling_map0 { + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; + +&cpu_little1_cooling_map0 { + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; + +&cpu_little2_cooling_map0 { + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; + +&cpu_little3_cooling_map0 { + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; +}; + +&ppi_cluster0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; +}; diff --git a/src/arm64/mediatek/mt8390-genio-700-evk.dts b/src/arm64/mediatek/mt8390-genio-700-evk.dts index 04e4a2f7379..612336713a6 100644 --- a/src/arm64/mediatek/mt8390-genio-700-evk.dts +++ b/src/arm64/mediatek/mt8390-genio-700-evk.dts @@ -8,1047 +8,16 @@ /dts-v1/; #include "mt8188.dtsi" -#include "mt6359.dtsi" -#include -#include -#include -#include -#include -#include -#include +#include "mt8390-genio-common.dtsi" / { model = "MediaTek Genio-700 EVK"; compatible = "mediatek,mt8390-evk", "mediatek,mt8390", "mediatek,mt8188"; - aliases { - ethernet0 = ð - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - mmc0 = &mmc0; - mmc1 = &mmc1; - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:921600n8"; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; - memory@40000000 { device_type = "memory"; reg = <0 0x40000000 0x2 0x00000000>; }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * 12 MiB reserved for OP-TEE (BL32) - * +-----------------------+ 0x43e0_0000 - * | SHMEM 2MiB | - * +-----------------------+ 0x43c0_0000 - * | | TA_RAM 8MiB | - * + TZDRAM +--------------+ 0x4340_0000 - * | | TEE_RAM 2MiB | - * +-----------------------+ 0x4320_0000 - */ - optee_reserved: optee@43200000 { - no-map; - reg = <0 0x43200000 0 0x00c00000>; - }; - - scp_mem: memory@50000000 { - compatible = "shared-dma-pool"; - reg = <0 0x50000000 0 0x2900000>; - no-map; - }; - - /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ - bl31_secmon_reserved: memory@54600000 { - no-map; - reg = <0 0x54600000 0x0 0x200000>; - }; - - apu_mem: memory@55000000 { - compatible = "shared-dma-pool"; - reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ - }; - - vpu_mem: memory@57000000 { - compatible = "shared-dma-pool"; - reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ - }; - - adsp_mem: memory@60000000 { - compatible = "shared-dma-pool"; - reg = <0 0x60000000 0 0xf00000>; - no-map; - }; - - afe_dma_mem: memory@60f00000 { - compatible = "shared-dma-pool"; - reg = <0 0x60f00000 0 0x100000>; - no-map; - }; - - adsp_dma_mem: memory@61000000 { - compatible = "shared-dma-pool"; - reg = <0 0x61000000 0 0x100000>; - no-map; - }; - }; - - common_fixed_5v: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 10 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - vin-supply = <®_vsys>; - }; - - edp_panel_fixed_3v3: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "vedp_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&pio 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&edp_panel_3v3_en_pins>; - vin-supply = <®_vsys>; - }; - - gpio_fixed_3v3: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "ext_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 9 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - vin-supply = <®_vsys>; - }; - - /* system wide 4.2V power rail from charger */ - reg_vsys: regulator-vsys { - compatible = "regulator-fixed"; - regulator-name = "vsys"; - regulator-always-on; - regulator-boot-on; - }; - - /* used by mmc2 */ - sdio_fixed_1v8: regulator-3 { - compatible = "regulator-fixed"; - regulator-name = "vio18_conn"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - enable-active-high; - regulator-always-on; - }; - - /* used by mmc2 */ - sdio_fixed_3v3: regulator-4 { - compatible = "regulator-fixed"; - regulator-name = "wifi_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 74 GPIO_ACTIVE_HIGH>; - enable-active-high; - regulator-always-on; - vin-supply = <®_vsys>; - }; - - touch0_fixed_3v3: regulator-5 { - compatible = "regulator-fixed"; - regulator-name = "vio33_tp1"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 119 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_vsys>; - }; - - usb_hub_fixed_3v3: regulator-6 { - compatible = "regulator-fixed"; - regulator-name = "vhub_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&pio 112 GPIO_ACTIVE_HIGH>; /* HUB_3V3_EN */ - startup-delay-us = <10000>; - enable-active-high; - vin-supply = <®_vsys>; - }; - - usb_p0_vbus: regulator-7 { - compatible = "regulator-fixed"; - regulator-name = "vbus_p0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 84 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_vsys>; - }; - - usb_p1_vbus: regulator-8 { - compatible = "regulator-fixed"; - regulator-name = "vbus_p1"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&pio 87 GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <®_vsys>; - }; - - /* used by ssusb2 */ - usb_p2_vbus: regulator-9 { - compatible = "regulator-fixed"; - regulator-name = "wifi_3v3"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - }; -}; - -&adsp { - memory-region = <&adsp_dma_mem>, <&adsp_mem>; - status = "okay"; -}; - -&afe { - memory-region = <&afe_dma_mem>; - status = "okay"; -}; - -&gpu { - mali-supply = <&mt6359_vproc2_buck_reg>; - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins>; - clock-frequency = <400000>; - status = "okay"; - - touchscreen@5d { - compatible = "goodix,gt9271"; - reg = <0x5d>; - interrupt-parent = <&pio>; - interrupts-extended = <&pio 6 IRQ_TYPE_EDGE_RISING>; - irq-gpios = <&pio 6 GPIO_ACTIVE_HIGH>; - reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; - AVDD28-supply = <&touch0_fixed_3v3>; - VDDIO-supply = <&mt6359_vio18_ldo_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&touch_pins>; - }; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins>; - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins>; - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c4_pins>; - clock-frequency = <1000000>; - status = "okay"; -}; - -&i2c5 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c5_pins>; - clock-frequency = <400000>; - status = "okay"; -}; - -&i2c6 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c6_pins>; - clock-frequency = <400000>; - status = "okay"; -}; - -&mfg0 { - domain-supply = <&mt6359_vproc2_buck_reg>; -}; - -&mfg1 { - domain-supply = <&mt6359_vsram_others_ldo_reg>; -}; - -&mmc0 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc0_default_pins>; - pinctrl-1 = <&mmc0_uhs_pins>; - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - supports-cqe; - cap-mmc-hw-reset; - no-sdio; - no-sd; - hs400-ds-delay = <0x1481b>; - vmmc-supply = <&mt6359_vemc_1_ldo_reg>; - vqmmc-supply = <&mt6359_vufs_ldo_reg>; - non-removable; -}; - -&mmc1 { - status = "okay"; - pinctrl-names = "default", "state_uhs"; - pinctrl-0 = <&mmc1_default_pins>; - pinctrl-1 = <&mmc1_uhs_pins>; - bus-width = <4>; - max-frequency = <200000000>; - cap-sd-highspeed; - sd-uhs-sdr50; - sd-uhs-sdr104; - no-mmc; - no-sdio; - cd-gpios = <&pio 2 GPIO_ACTIVE_LOW>; - vmmc-supply = <&mt6359_vpa_buck_reg>; - vqmmc-supply = <&mt6359_vsim1_ldo_reg>; -}; - -&mt6359_vbbck_ldo_reg { - regulator-always-on; -}; - -&mt6359_vcn18_ldo_reg { - regulator-name = "vcn18_pmu"; - regulator-always-on; -}; - -&mt6359_vcn33_2_bt_ldo_reg { - regulator-name = "vcn33_2_pmu"; - regulator-always-on; -}; - -&mt6359_vcore_buck_reg { - regulator-name = "dvdd_proc_l"; - regulator-always-on; -}; - -&mt6359_vgpu11_buck_reg { - regulator-name = "dvdd_core"; - regulator-always-on; -}; - -&mt6359_vpa_buck_reg { - regulator-name = "vpa_pmu"; - regulator-max-microvolt = <3100000>; -}; - -&mt6359_vproc2_buck_reg { - /* The name "vgpu" is required by mtk-regulator-coupler */ - regulator-name = "vgpu"; - regulator-min-microvolt = <550000>; - regulator-max-microvolt = <800000>; - regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; - regulator-coupled-max-spread = <6250>; -}; - -&mt6359_vpu_buck_reg { - regulator-name = "dvdd_adsp"; - regulator-always-on; -}; - -&mt6359_vrf12_ldo_reg { - regulator-name = "va12_abb2_pmu"; - regulator-always-on; -}; - -&mt6359_vsim1_ldo_reg { - regulator-name = "vsim1_pmu"; - regulator-enable-ramp-delay = <480>; -}; - -&mt6359_vsram_others_ldo_reg { - /* The name "vsram_gpu" is required by mtk-regulator-coupler */ - regulator-name = "vsram_gpu"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <800000>; - regulator-coupled-with = <&mt6359_vproc2_buck_reg>; - regulator-coupled-max-spread = <6250>; -}; - -&mt6359_vufs_ldo_reg { - regulator-name = "vufs18_pmu"; - regulator-always-on; -}; - -&mt6359codec { - mediatek,mic-type-0 = <1>; /* ACC */ - mediatek,mic-type-1 = <3>; /* DCC */ -}; - -&pcie { - pinctrl-names = "default"; - pinctrl-0 = <&pcie_pins_default>; - status = "okay"; -}; - -&pciephy { - status = "okay"; -}; - -&pio { - audio_default_pins: audio-default-pins { - pins-cmd-dat { - pinmux = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - }; - }; - - dptx_pins: dptx-pins { - pins-cmd-dat { - pinmux = ; - bias-pull-up; - }; - }; - - edp_panel_3v3_en_pins: edp-panel-3v3-en-pins { - pins1 { - pinmux = ; - output-high; - }; - }; - - eth_default_pins: eth-default-pins { - pins-cc { - pinmux = , - , - , - ; - drive-strength = <8>; - }; - - pins-mdio { - pinmux = , - ; - drive-strength = <8>; - input-enable; - }; - - pins-power { - pinmux = , - ; - output-high; - }; - - pins-rxd { - pinmux = , - , - , - ; - drive-strength = <8>; - }; - - pins-txd { - pinmux = , - , - , - ; - drive-strength = <8>; - }; - }; - - eth_sleep_pins: eth-sleep-pins { - pins-cc { - pinmux = , - , - , - ; - }; - - pins-mdio { - pinmux = , - ; - input-disable; - bias-disable; - }; - - pins-rxd { - pinmux = , - , - , - ; - }; - - pins-txd { - pinmux = , - , - , - ; - }; - }; - - i2c0_pins: i2c0-pins { - pins { - pinmux = , - ; - bias-pull-up = ; - drive-strength-microamp = <1000>; - }; - }; - - i2c1_pins: i2c1-pins { - pins { - pinmux = , - ; - bias-pull-up = ; - drive-strength-microamp = <1000>; - }; - }; - - i2c2_pins: i2c2-pins { - pins { - pinmux = , - ; - bias-pull-up = ; - drive-strength-microamp = <1000>; - }; - }; - - i2c3_pins: i2c3-pins { - pins { - pinmux = , - ; - bias-pull-up = ; - drive-strength-microamp = <1000>; - }; - }; - - i2c4_pins: i2c4-pins { - pins { - pinmux = , - ; - bias-pull-up = ; - drive-strength-microamp = <1000>; - }; - }; - - i2c5_pins: i2c5-pins { - pins { - pinmux = , - ; - bias-pull-up = ; - drive-strength-microamp = <1000>; - }; - }; - - i2c6_pins: i2c6-pins { - pins { - pinmux = , - ; - bias-pull-up = ; - drive-strength-microamp = <1000>; - }; - }; - - gpio_key_pins: gpio-key-pins { - pins { - pinmux = , - , - ; - }; - }; - - mmc0_default_pins: mmc0-default-pins { - pins-clk { - pinmux = ; - drive-strength = <6>; - bias-pull-down = ; - }; - - pins-cmd-dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = <6>; - bias-pull-up = ; - }; - - pins-rst { - pinmux = ; - drive-strength = <6>; - bias-pull-up = ; - }; - }; - - mmc0_uhs_pins: mmc0-uhs-pins { - pins-clk { - pinmux = ; - drive-strength = <8>; - bias-pull-down = ; - }; - - pins-cmd-dat { - pinmux = , - , - , - , - , - , - , - , - ; - input-enable; - drive-strength = <8>; - bias-pull-up = ; - }; - - pins-ds { - pinmux = ; - drive-strength = <8>; - bias-pull-down = ; - }; - - pins-rst { - pinmux = ; - drive-strength = <8>; - bias-pull-up = ; - }; - }; - - mmc1_default_pins: mmc1-default-pins { - pins-clk { - pinmux = ; - drive-strength = <6>; - bias-pull-down = ; - }; - - pins-cmd-dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = <6>; - bias-pull-up = ; - }; - - pins-insert { - pinmux = ; - bias-pull-up; - }; - }; - - mmc1_uhs_pins: mmc1-uhs-pins { - pins-clk { - pinmux = ; - drive-strength = <6>; - bias-pull-down = ; - }; - - pins-cmd-dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = <6>; - bias-pull-up = ; - }; - }; - - mmc2_default_pins: mmc2-default-pins { - pins-clk { - pinmux = ; - drive-strength = <4>; - bias-pull-down = ; - }; - - pins-cmd-dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = <6>; - bias-pull-up = ; - }; - - pins-pcm { - pinmux = ; - }; - }; - - mmc2_uhs_pins: mmc2-uhs-pins { - pins-clk { - pinmux = ; - drive-strength = <4>; - bias-pull-down = ; - }; - - pins-cmd-dat { - pinmux = , - , - , - , - ; - input-enable; - drive-strength = <6>; - bias-pull-up = ; - }; - }; - - mmc2_eint_pins: mmc2-eint-pins { - pins-dat1 { - pinmux = ; - input-enable; - bias-pull-up = ; - }; - }; - - mmc2_dat1_pins: mmc2-dat1-pins { - pins-dat1 { - pinmux = ; - input-enable; - drive-strength = <6>; - bias-pull-up = ; - }; - }; - - panel_default_pins: panel-default-pins { - pins-dcdc { - pinmux = ; - output-low; - }; - - pins-en { - pinmux = ; - output-low; - }; - - pins-rst { - pinmux = ; - output-high; - }; - }; - - pcie_pins_default: pcie-default { - mux { - pinmux = , - , - ; - bias-pull-up; - }; - }; - - rt1715_int_pins: rt1715-int-pins { - pins_cmd0_dat { - pinmux = ; - bias-pull-up; - input-enable; - }; - }; - - spi0_pins: spi0-pins { - pins-spi { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi1_pins: spi1-pins { - pins-spi { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - spi2_pins: spi2-pins { - pins-spi { - pinmux = , - , - , - ; - bias-disable; - }; - }; - - touch_pins: touch-pins { - pins-irq { - pinmux = ; - input-enable; - bias-disable; - }; - - pins-reset { - pinmux = ; - output-high; - }; - }; - - uart0_pins: uart0-pins { - pins { - pinmux = , - ; - bias-pull-up; - }; - }; - - uart1_pins: uart1-pins { - pins { - pinmux = , - ; - bias-pull-up; - }; - }; - - uart2_pins: uart2-pins { - pins { - pinmux = , - ; - bias-pull-up; - }; - }; - - usb_default_pins: usb-default-pins { - pins-iddig { - pinmux = ; - input-enable; - bias-pull-up; - }; - - pins-valid { - pinmux = ; - input-enable; - }; - - pins-vbus { - pinmux = ; - output-high; - }; - - }; - - usb1_default_pins: usb1-default-pins { - pins-valid { - pinmux = ; - input-enable; - }; - - pins-usb-hub-3v3-en { - pinmux = ; - output-high; - }; - }; - - wifi_pwrseq_pins: wifi-pwrseq-pins { - pins-wifi-enable { - pinmux = ; - output-low; - }; - }; -}; - -ð { - phy-mode ="rgmii-id"; - phy-handle = <ðernet_phy0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <ð_default_pins>; - pinctrl-1 = <ð_sleep_pins>; - mediatek,mac-wol; - snps,reset-gpio = <&pio 147 GPIO_ACTIVE_HIGH>; - snps,reset-delays-us = <0 10000 10000>; - status = "okay"; -}; - -ð_mdio { - ethernet_phy0: ethernet-phy@1 { - compatible = "ethernet-phy-id001c.c916"; - reg = <0x1>; - }; -}; - -&pmic { - interrupt-parent = <&pio>; - interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; - - mt6359keys: keys { - compatible = "mediatek,mt6359-keys"; - mediatek,long-press-mode = <1>; - power-off-time-sec = <0>; - - power-key { - linux,keycodes = ; - wakeup-source; - }; - }; -}; - -&scp { - memory-region = <&scp_mem>; - status = "okay"; -}; - -&sound { - compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb"; - model = "mt8390-evk"; - pinctrl-names = "default"; - pinctrl-0 = <&audio_default_pins>; - audio-routing = - "Headphone", "Headphone L", - "Headphone", "Headphone R"; - mediatek,adsp = <&adsp>; - status = "okay"; - - dai-link-0 { - link-name = "DL_SRC_BE"; - - codec { - sound-dai = <&pmic 0>; - }; - }; -}; - -&spi2 { - pinctrl-0 = <&spi2_pins>; - pinctrl-names = "default"; - mediatek,pad-select = <0>; - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; }; -&uart0 { - pinctrl-0 = <&uart0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart1 { - pinctrl-0 = <&uart1_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart2 { - pinctrl-0 = <&uart2_pins>; - pinctrl-names = "default"; - status = "okay"; -}; - -&u3phy0 { - status = "okay"; -}; - -&u3phy1 { - status = "okay"; -}; - -&u3phy2 { - status = "okay"; -}; - -&xhci0 { - status = "okay"; - vusb33-supply = <&mt6359_vusb_ldo_reg>; -}; - -&xhci1 { - status = "okay"; - vusb33-supply = <&mt6359_vusb_ldo_reg>; - #address-cells = <1>; - #size-cells = <0>; - - hub_2_0: hub@1 { - compatible = "usb451,8025"; - reg = <1>; - peer-hub = <&hub_3_0>; - reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; - vdd-supply = <&usb_hub_fixed_3v3>; - }; - - hub_3_0: hub@2 { - compatible = "usb451,8027"; - reg = <2>; - peer-hub = <&hub_2_0>; - reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; - vdd-supply = <&usb_hub_fixed_3v3>; - }; -}; - -&xhci2 { - status = "okay"; - vusb33-supply = <&mt6359_vusb_ldo_reg>; - vbus-supply = <&sdio_fixed_3v3>; /* wifi_3v3 */ -}; diff --git a/src/arm64/mediatek/mt8390-genio-common.dtsi b/src/arm64/mediatek/mt8390-genio-common.dtsi new file mode 100644 index 00000000000..60139e6dffd --- /dev/null +++ b/src/arm64/mediatek/mt8390-genio-common.dtsi @@ -0,0 +1,1223 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Chris Chen + * Pablo Sun + * Macpaul Lin + * + * Copyright (C) 2025 Collabora Ltd. + * Louis-Alexis Eyraud + * AngeloGioacchino Del Regno + */ + +#include "mt6359.dtsi" +#include +#include +#include +#include +#include +#include +#include + +/ { + aliases { + ethernet0 = ð + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + dmic_codec: dmic-codec { + #sound-dai-cells = <0>; + compatible = "dmic-codec"; + num-channels = <2>; + wakeup-delay-ms = <30>; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + apu_mem: memory@55000000 { + compatible = "shared-dma-pool"; + reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ + }; + + vpu_mem: memory@57000000 { + compatible = "shared-dma-pool"; + reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ + }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xf00000>; + no-map; + }; + + afe_dma_mem: memory@60f00000 { + compatible = "shared-dma-pool"; + reg = <0 0x60f00000 0 0x100000>; + no-map; + }; + + adsp_dma_mem: memory@61000000 { + compatible = "shared-dma-pool"; + reg = <0 0x61000000 0 0x100000>; + no-map; + }; + }; + + common_fixed_5v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_vsys>; + }; + + edp_panel_fixed_3v3: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "vedp_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_panel_3v3_en_pins>; + vin-supply = <®_vsys>; + }; + + gpio_fixed_3v3: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "ext_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_vsys>; + }; + + /* system wide 4.2V power rail from charger */ + reg_vsys: regulator-vsys { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-always-on; + regulator-boot-on; + }; + + /* used by mmc2 */ + sdio_fixed_1v8: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "vio18_conn"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-always-on; + }; + + /* used by mmc2 */ + sdio_fixed_3v3: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "wifi_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 74 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + vin-supply = <®_vsys>; + }; + + touch0_fixed_3v3: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "vio33_tp1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 119 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vsys>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_vreg_pins>; + }; + + usb_hub_fixed_3v3: regulator-6 { + compatible = "regulator-fixed"; + regulator-name = "vhub_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 112 GPIO_ACTIVE_HIGH>; /* HUB_3V3_EN */ + startup-delay-us = <10000>; + enable-active-high; + vin-supply = <®_vsys>; + }; + + usb_p0_vbus: regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "vbus_p0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 84 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vsys>; + }; + + usb_p1_vbus: regulator-8 { + compatible = "regulator-fixed"; + regulator-name = "vbus_p1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 87 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vsys>; + }; + + /* used by ssusb2 */ + usb_p2_vbus: regulator-9 { + compatible = "regulator-fixed"; + regulator-name = "vbus_p2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; +}; + +&adsp { + memory-region = <&adsp_dma_mem>, <&adsp_mem>; + status = "okay"; +}; + +&afe { + memory-region = <&afe_dma_mem>; + status = "okay"; +}; + +&gpu { + mali-supply = <&mt6359_vproc2_buck_reg>; + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt9271"; + reg = <0x5d>; + interrupt-parent = <&pio>; + interrupts-extended = <&pio 6 IRQ_TYPE_EDGE_RISING>; + irq-gpios = <&pio 6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&touch0_fixed_3v3>; + VDDIO-supply = <&mt6359_vio18_ldo_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pins>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + status = "okay"; + + typec-mux@48 { + compatible = "ite,it5205"; + reg = <0x48>; + + mode-switch; + orientation-switch; + + vcc-supply = <&mt6359_vcn33_1_bt_ldo_reg>; + + port { + it5205_sbu_mux: endpoint { + remote-endpoint = <&typec_sbu_out>; + }; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + clock-frequency = <1000000>; + status = "okay"; + + rt1715@4e { + compatible = "richtek,rt1715"; + reg = <0x4e>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&tcpci_int_pins>; + vbus-supply = <&usb_p1_vbus>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + op-sink-microwatt = <10000000>; + power-role = "dual"; + try-power-role = "sink"; + pd-revision = /bits/ 8 <0x03 0x00 0x01 0x08>; + + sink-pdos = ; + source-pdos = ; + + altmodes { + displayport { + svid = /bits/ 16 <0xff01>; + vdo = <0x001c1c47>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + typec_con_hs: endpoint { + remote-endpoint = <&mtu3_hs1_role_sw>; + }; + }; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&xhci_ss_ep>; + }; + }; + + port@2 { + reg = <2>; + typec_sbu_out: endpoint { + remote-endpoint = <&it5205_sbu_mux>; + }; + + }; + }; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&mfg0 { + domain-supply = <&mt6359_vproc2_buck_reg>; +}; + +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x1481b>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-mmc; + no-sdio; + cd-gpios = <&pio 2 GPIO_ACTIVE_LOW>; + vmmc-supply = <&mt6359_vpa_buck_reg>; + vqmmc-supply = <&mt6359_vsim1_ldo_reg>; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn18_ldo_reg { + regulator-name = "vcn18_pmu"; + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-name = "vcn33_2_pmu"; + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-name = "dvdd_proc_l"; + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-name = "dvdd_core"; + regulator-always-on; +}; + +&mt6359_vpa_buck_reg { + regulator-name = "vpa_pmu"; + regulator-max-microvolt = <3100000>; +}; + +&mt6359_vproc2_buck_reg { + /* The name "vgpu" is required by mtk-regulator-coupler */ + regulator-name = "vgpu"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; + regulator-coupled-max-spread = <6250>; +}; + +&mt6359_vpu_buck_reg { + regulator-name = "dvdd_adsp"; + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-name = "va12_abb2_pmu"; + regulator-always-on; +}; + +&mt6359_vsim1_ldo_reg { + regulator-name = "vsim1_pmu"; + regulator-enable-ramp-delay = <480>; +}; + +&mt6359_vsram_others_ldo_reg { + /* The name "vsram_gpu" is required by mtk-regulator-coupler */ + regulator-name = "vsram_gpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vproc2_buck_reg>; + regulator-coupled-max-spread = <6250>; +}; + +&mt6359_vufs_ldo_reg { + regulator-name = "vufs18_pmu"; + regulator-always-on; +}; + +&mt6359codec { + mediatek,mic-type-0 = <1>; /* ACC */ + mediatek,mic-type-1 = <3>; /* DCC */ +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins_default>; + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&pio { + audio_default_pins: audio-default-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + dptx_pins: dptx-pins { + pins-cmd-dat { + pinmux = ; + bias-pull-up; + }; + }; + + edp_panel_3v3_en_pins: edp-panel-3v3-en-pins { + pins1 { + pinmux = ; + output-high; + }; + }; + + eth_default_pins: eth-default-pins { + pins-cc { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + + pins-mdio { + pinmux = , + ; + drive-strength = <8>; + input-enable; + }; + + pins-power { + pinmux = , + ; + output-high; + }; + + pins-rxd { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + + pins-txd { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-cc { + pinmux = , + , + , + ; + }; + + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-txd { + pinmux = , + , + , + ; + }; + }; + + i2c0_pins: i2c0-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c5_pins: i2c5-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + gpio_key_pins: gpio-key-pins { + pins { + pinmux = , + , + ; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <8>; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <8>; + bias-pull-up = ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc2_default_pins: mmc2-default-pins { + pins-clk { + pinmux = ; + drive-strength = <4>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-pcm { + pinmux = ; + }; + }; + + mmc2_uhs_pins: mmc2-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = <4>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc2_eint_pins: mmc2-eint-pins { + pins-dat1 { + pinmux = ; + input-enable; + bias-pull-up = ; + }; + }; + + mmc2_dat1_pins: mmc2-dat1-pins { + pins-dat1 { + pinmux = ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + panel_default_pins: panel-default-pins { + pins-dcdc { + pinmux = ; + output-low; + }; + + pins-en { + pinmux = ; + output-low; + }; + + pins-rst { + pinmux = ; + output-high; + }; + }; + + pcie_pins_default: pcie-default { + mux { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + rt1715_int_pins: rt1715-int-pins { + pins_cmd0_dat { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + + spi0_pins: spi0-pins { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi1_pins: spi1-pins { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi2_pins: spi2-pins { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + touch_vreg_pins: touch-avdd-pins { + pins-power { + pinmux = ; + output-high; + }; + }; + + touch_pins: touch-pins { + pins-irq { + pinmux = ; + input-enable; + bias-disable; + }; + + pins-reset { + pinmux = ; + output-high; + }; + }; + + tcpci_int_pins: tcpci-int-pins { + pins-int-n { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + usb_default_pins: usb-default-pins { + pins-iddig { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-valid { + pinmux = ; + input-enable; + }; + + pins-vbus { + pinmux = ; + output-high; + }; + + }; + + usb1_default_pins: usb1-default-pins { + pins-valid { + pinmux = ; + input-enable; + }; + + pins-usb-hub-3v3-en { + pinmux = ; + output-high; + }; + }; + + usb2_default_pins: usb2-default-pins { + pins-iddig { + pinmux = ; + input-enable; + bias-pull-up; + }; + }; + + wifi_pwrseq_pins: wifi-pwrseq-pins { + pins-wifi-enable { + pinmux = ; + output-low; + }; + }; +}; + +ð { + phy-mode ="rgmii-id"; + phy-handle = <ðernet_phy0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + mediatek,mac-wol; + snps,reset-gpio = <&pio 147 GPIO_ACTIVE_HIGH>; + snps,reset-delays-us = <0 10000 10000>; + status = "okay"; +}; + +ð_mdio { + ethernet_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + }; +}; + +&pmic { + interrupt-parent = <&pio>; + interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; + + mt6359keys: keys { + compatible = "mediatek,mt6359-keys"; + mediatek,long-press-mode = <1>; + power-off-time-sec = <0>; + + power-key { + linux,keycodes = ; + wakeup-source; + }; + }; +}; + +&scp { + memory-region = <&scp_mem>; + status = "okay"; +}; + +&sound { + compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb"; + model = "mt8390-evk"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_default_pins>; + audio-routing = + "Headphone", "Headphone L", + "Headphone", "Headphone R", + "DMIC_INPUT", "AP DMIC", + "AP DMIC", "AUDGLB", + "AP DMIC", "MIC_BIAS_0", + "AP DMIC", "MIC_BIAS_2"; + mediatek,adsp = <&adsp>; + status = "okay"; + + dai-link-0 { + link-name = "DL_SRC_BE"; + + codec { + sound-dai = <&pmic 0>; + }; + }; + + dai-link-1 { + link-name = "DMIC_BE"; + + codec { + sound-dai = <&dmic_codec>; + }; + }; +}; + +&spi2 { + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&ssusb0 { + dr_mode = "otg"; + maximum-speed = "high-speed"; + usb-role-switch; + wakeup-source; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + pinctrl-0 = <&usb_default_pins>; + pinctrl-names = "default"; + status = "okay"; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + id-gpios = <&pio 83 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb_p0_vbus>; + }; +}; + +&xhci0 { + status = "okay"; +}; + +&ssusb1 { + dr_mode = "otg"; + usb-role-switch; + wakeup-source; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + pinctrl-0 = <&usb1_default_pins>; + pinctrl-names = "default"; + status = "okay"; + + port { + mtu3_hs1_role_sw: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&xhci1 { + status = "okay"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + #address-cells = <1>; + #size-cells = <0>; + + hub_2_0: hub@1 { + compatible = "usb451,8025"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <&usb_hub_fixed_3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8027"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <&usb_hub_fixed_3v3>; + }; + + port { + xhci_ss_ep: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +&ssusb2 { + dr_mode = "otg"; + maximum-speed = "high-speed"; + usb-role-switch; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_default_pins>; + status = "okay"; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + id-gpios = <&pio 89 GPIO_ACTIVE_HIGH>; + vbus-supply = <&usb_p2_vbus>; + }; +}; + +&xhci2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&sdio_fixed_3v3>; /* wifi_3v3 */ + status = "okay"; +}; diff --git a/src/arm64/mediatek/mt8395-genio-1200-evk.dts b/src/arm64/mediatek/mt8395-genio-1200-evk.dts index 5950194c9cc..f02c32def59 100644 --- a/src/arm64/mediatek/mt8395-genio-1200-evk.dts +++ b/src/arm64/mediatek/mt8395-genio-1200-evk.dts @@ -229,6 +229,21 @@ pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; status = "okay"; + + typec-mux@48 { + compatible = "ite,it5205"; + reg = <0x48>; + vcc-supply = <&mt6359_vibr_ldo_reg>; + mode-switch; + orientation-switch; + status = "okay"; + + port { + it5205_sbu_ep: endpoint { + remote-endpoint = <&mt6360_ssusb_sbu_ep>; + }; + }; + }; }; &i2c6 { @@ -335,6 +350,63 @@ regulator-always-on; }; }; + + tcpc { + compatible = "mediatek,mt6360-tcpc"; + interrupts-extended = <&pio 17 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "PD_IRQB"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + op-sink-microwatt = <10000000>; + power-role = "dual"; + try-power-role = "sink"; + + source-pdos = ; + sink-pdos = ; + + pd-revision = /bits/ 8 <0x03 0x01 0x01 0x06>; + + altmodes { + displayport { + svid = /bits/ 16 <0xff01>; + vdo = <0x00001c46>; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + typec_con_hs: endpoint { + remote-endpoint = <&mtu3_hs0_role_sw>; + }; + }; + + port@1 { + reg = <1>; + typec_con_ss: endpoint { + remote-endpoint = <&mtu3_ss0_role_sw>; + }; + }; + + port@2 { + reg = <2>; + mt6360_ssusb_sbu_ep: endpoint { + remote-endpoint = <&it5205_sbu_ep>; + }; + }; + }; + }; + }; }; }; @@ -770,6 +842,13 @@ }; }; + u3_p0_vbus: u3-p0-vbus-default-pins { + pins-vbus { + pinmux = ; + input-enable; + }; + }; + uart0_pins: uart0-pins { pins { pinmux = , @@ -898,8 +977,31 @@ }; &ssusb0 { + dr_mode = "otg"; + pinctrl-names = "default"; + pinctrl-0 = <&u3_p0_vbus>; + usb-role-switch; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mtu3_hs0_role_sw: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; + + port@1 { + reg = <1>; + mtu3_ss0_role_sw: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; + }; }; &ssusb2 { diff --git a/src/arm64/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso b/src/arm64/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso new file mode 100644 index 00000000000..0389c9cb858 --- /dev/null +++ b/src/arm64/mediatek/mt8395-radxa-nio-12l-8-hd-panel.dtso @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Radxa Display 8 HD touchscreen module + * Copyright (C) 2025 Collabora Ltd. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&backlight { + status = "okay"; +}; + +&disp_pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_default_pins>; + status = "okay"; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "radxa,display-8hd-ad002", "jadard,jd9365da-h3"; + reg = <0>; + backlight = <&backlight>; + vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + vccio-supply = <&mt6360_ldo2>; + reset-gpios = <&pio 108 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&panel_default_pins>; + + port { + dsi_panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; +}; + +&dsi0_out { + remote-endpoint = <&dsi_panel_in>; +}; + +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupts-extended = <&pio 132 IRQ_TYPE_EDGE_RISING>; + irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>; + VDDIO-supply = <&mt6359_vcn33_2_bt_ldo_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pins>; + }; +}; + +&mipi_tx0 { + status = "okay"; +}; + +&ovl0_in { + remote-endpoint = <&vdosys0_ep_main>; +}; + +&vdosys0 { + port { + #address-cells = <1>; + #size-cells = <0>; + + vdosys0_ep_main: endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_in>; + }; + }; +}; diff --git a/src/arm64/mediatek/mt8395-radxa-nio-12l.dts b/src/arm64/mediatek/mt8395-radxa-nio-12l.dts index 41dc34837b0..1c922e98441 100644 --- a/src/arm64/mediatek/mt8395-radxa-nio-12l.dts +++ b/src/arm64/mediatek/mt8395-radxa-nio-12l.dts @@ -48,6 +48,18 @@ reg = <0 0x40000000 0x1 0x0>; }; + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 1023>; + default-brightness-level = <576>; + enable-gpios = <&pio 107 GPIO_ACTIVE_HIGH>; + num-interpolated-steps = <1023>; + pinctrl-names = "default"; + pinctrl-0 = <&dsi0_backlight_pins>; + pwms = <&disp_pwm0 0 500000>; + status = "disabled"; + }; + wifi_vreg: regulator-wifi-3v3-en { compatible = "regulator-fixed"; regulator-name = "wifi_3v3_en"; @@ -172,6 +184,32 @@ cpu-supply = <&mt6315_6_vbuck1>; }; +&dither0_out { + remote-endpoint = <&dsi0_in>; +}; + +&dsi0 { + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dither0_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { }; + }; + }; +}; + ð { phy-mode = "rgmii-rxid"; phy-handle = <&rgmii_phy>; @@ -476,6 +514,13 @@ &pio { mediatek,rsel-resistance-in-si-unit; + dsi0_backlight_pins: dsi0-backlight-pins { + pins-backlight-en { + pinmux = ; + output-high; + }; + }; + eth_default_pins: eth-default-pins { pins-cc { pinmux = , @@ -673,6 +718,13 @@ }; }; + panel_default_pins: panel-pins { + pins-rst { + pinmux = ; + bias-pull-up; + }; + }; + pcie0_default_pins: pcie0-default-pins { pins-bus { pinmux = , @@ -691,6 +743,12 @@ }; }; + pwm0_default_pins: pwm0-pins { + pins-disp-pwm { + pinmux = ; + }; + }; + spi1_pins: spi1-default-pins { pins-bus { pinmux = , @@ -711,6 +769,19 @@ }; }; + touch_pins: touch-pins { + pins-touch-int { + pinmux = ; + input-enable; + bias-disable; + }; + + pins-touch-rst { + pinmux = ; + output-high; + }; + }; + uart0_pins: uart0-pins { pins-bus { pinmux = , diff --git a/src/arm64/nvidia/tegra210-p2180.dtsi b/src/arm64/nvidia/tegra210-p2180.dtsi index 1c53ccc5e3c..9b9d1d15b0c 100644 --- a/src/arm64/nvidia/tegra210-p2180.dtsi +++ b/src/arm64/nvidia/tegra210-p2180.dtsi @@ -49,6 +49,19 @@ }; }; + i2c@7000c000 { + status = "okay"; + + tmp451: temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = ; + vcc-supply = <&vdd_1v8>; + #thermal-sensor-cells = <1>; + }; + }; + i2c@7000c400 { status = "okay"; diff --git a/src/arm64/nvidia/tegra210-p2597.dtsi b/src/arm64/nvidia/tegra210-p2597.dtsi index 63b94a04308..83ed6ac2a8d 100644 --- a/src/arm64/nvidia/tegra210-p2597.dtsi +++ b/src/arm64/nvidia/tegra210-p2597.dtsi @@ -1375,6 +1375,15 @@ #gpio-cells = <2>; gpio-controller; + + interrupt-parent = <&gpio>; + interrupts = ; + + #interrupt-cells = <2>; + interrupt-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_1v8>; }; exp2: gpio@77 { @@ -1383,6 +1392,15 @@ #gpio-cells = <2>; gpio-controller; + + interrupt-parent = <&gpio>; + interrupts = ; + + #interrupt-cells = <2>; + interrupt-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_1v8>; }; }; @@ -1686,7 +1704,7 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-always-on; - gpio = <&exp1 14 GPIO_ACTIVE_HIGH>; + gpio = <&exp1 9 GPIO_ACTIVE_HIGH>; enable-active-high; vin-supply = <&vdd_1v8>; }; diff --git a/src/arm64/nvidia/tegra210-p3450-0000.dts b/src/arm64/nvidia/tegra210-p3450-0000.dts index c56824d7f4d..0ecdd7243b2 100644 --- a/src/arm64/nvidia/tegra210-p3450-0000.dts +++ b/src/arm64/nvidia/tegra210-p3450-0000.dts @@ -266,7 +266,6 @@ regulator-max-microvolt = <1170000>; regulator-enable-ramp-delay = <146>; regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <300>; regulator-always-on; regulator-boot-on; @@ -281,7 +280,6 @@ regulator-max-microvolt = <1150000>; regulator-enable-ramp-delay = <176>; regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <300>; regulator-always-on; regulator-boot-on; @@ -296,7 +294,6 @@ regulator-max-microvolt = <1350000>; regulator-enable-ramp-delay = <176>; regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <350>; regulator-always-on; regulator-boot-on; @@ -311,7 +308,6 @@ regulator-max-microvolt = <1800000>; regulator-enable-ramp-delay = <242>; regulator-ramp-delay = <27500>; - regulator-ramp-delay-scale = <360>; regulator-always-on; regulator-boot-on; @@ -326,7 +322,6 @@ regulator-max-microvolt = <1200000>; regulator-enable-ramp-delay = <26>; regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; regulator-always-on; regulator-boot-on; @@ -341,7 +336,6 @@ regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <22>; regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; maxim,active-fps-source = ; maxim,active-fps-power-up-slot = <0>; @@ -354,7 +348,6 @@ regulator-max-microvolt = <3300000>; regulator-enable-ramp-delay = <62>; regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; maxim,active-fps-source = ; maxim,active-fps-power-up-slot = <0>; @@ -371,7 +364,6 @@ regulator-max-microvolt = <1100000>; regulator-enable-ramp-delay = <22>; regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; regulator-disable-active-discharge; regulator-always-on; regulator-boot-on; @@ -395,7 +387,6 @@ regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <24>; regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; maxim,active-fps-source = ; maxim,active-fps-power-up-slot = <3>; @@ -408,7 +399,6 @@ regulator-max-microvolt = <1050000>; regulator-enable-ramp-delay = <22>; regulator-ramp-delay = <100000>; - regulator-ramp-delay-scale = <200>; maxim,active-fps-source = ; maxim,active-fps-power-up-slot = <6>; diff --git a/src/arm64/nvidia/tegra210.dtsi b/src/arm64/nvidia/tegra210.dtsi index 942e3a0f81e..b6c84d195c0 100644 --- a/src/arm64/nvidia/tegra210.dtsi +++ b/src/arm64/nvidia/tegra210.dtsi @@ -874,6 +874,16 @@ pins = "sdmmc3"; power-source = ; }; + + gpio_1v8: gpio-1v8 { + pins = "gpio"; + power-source = ; + }; + + gpio_3v3: gpio-3v3 { + pins = "gpio"; + power-source = ; + }; }; powergates { diff --git a/src/arm64/nvidia/tegra234-p3740-0002+p3701-0008.dts b/src/arm64/nvidia/tegra234-p3740-0002+p3701-0008.dts index 36e88805374..9ce55b4d2de 100644 --- a/src/arm64/nvidia/tegra234-p3740-0002+p3701-0008.dts +++ b/src/arm64/nvidia/tegra234-p3740-0002+p3701-0008.dts @@ -302,6 +302,16 @@ }; pcie@141a0000 { + reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ + 0x00 0x3a000000 0x0 0x00040000 /* configuration space (256K) */ + 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ + 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */ + 0x2e 0x20000000 0x0 0x10000000>; /* ECAM (256MB) */ + + ranges = <0x81000000 0x00 0x3a100000 0x00 0x3a100000 0x0 0x00100000 /* downstream I/O (1MB) */ + 0x82000000 0x00 0x40000000 0x2e 0x30000000 0x0 0x08000000 /* non-prefetchable memory (128MB) */ + 0xc3000000 0x28 0x00000000 0x28 0x00000000 0x6 0x20000000>; /* prefetchable memory (25088MB) */ + status = "okay"; vddio-pex-ctl-supply = <&vdd_1v8_ls>; phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, diff --git a/src/arm64/nvidia/tegra234-p3768-0000+p3767.dtsi b/src/arm64/nvidia/tegra234-p3768-0000+p3767.dtsi index 19340d13f78..41821354bbd 100644 --- a/src/arm64/nvidia/tegra234-p3768-0000+p3767.dtsi +++ b/src/arm64/nvidia/tegra234-p3768-0000+p3767.dtsi @@ -227,13 +227,6 @@ wakeup-event-action = ; wakeup-source; }; - - key-suspend { - label = "Suspend"; - gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - }; }; fan: pwm-fan { diff --git a/src/arm64/qcom/sc8280xp-huawei-gaokun3.dts b/src/arm64/qcom/sc8280xp-huawei-gaokun3.dts index 09b95f89ee5..1667c715705 100644 --- a/src/arm64/qcom/sc8280xp-huawei-gaokun3.dts +++ b/src/arm64/qcom/sc8280xp-huawei-gaokun3.dts @@ -28,6 +28,7 @@ aliases { i2c4 = &i2c4; + i2c15 = &i2c15; serial1 = &uart2; }; @@ -216,6 +217,40 @@ }; }; + usb0-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + select-gpios = <&tlmm 164 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb0_sbu_default>; + pinctrl-names = "default"; + + orientation-switch; + + port { + usb0_sbu_mux: endpoint { + remote-endpoint = <&ucsi0_sbu>; + }; + }; + }; + + usb1-sbu-mux { + compatible = "pericom,pi3usb102", "gpio-sbu-mux"; + + select-gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&usb1_sbu_default>; + pinctrl-names = "default"; + + orientation-switch; + + port { + usb1_sbu_mux: endpoint { + remote-endpoint = <&ucsi1_sbu>; + }; + }; + }; + wcn6855-pmu { compatible = "qcom,wcn6855-pmu"; @@ -584,6 +619,97 @@ }; +&i2c15 { + clock-frequency = <400000>; + + pinctrl-0 = <&i2c15_default>; + pinctrl-names = "default"; + + status = "okay"; + + embedded-controller@38 { + compatible = "huawei,gaokun3-ec"; + reg = <0x38>; + + interrupts-extended = <&tlmm 107 IRQ_TYPE_LEVEL_LOW>; + + #address-cells = <1>; + #size-cells = <0>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ucsi0_hs_in: endpoint { + remote-endpoint = <&usb_0_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + ucsi0_ss_in: endpoint { + remote-endpoint = <&usb_0_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + ucsi0_sbu: endpoint { + remote-endpoint = <&usb0_sbu_mux>; + }; + }; + }; + }; + + connector@1 { + compatible = "usb-c-connector"; + reg = <1>; + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ucsi1_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + ucsi1_ss_in: endpoint { + remote-endpoint = <&usb_1_qmpphy_out>; + }; + }; + + port@2 { + reg = <2>; + + ucsi1_sbu: endpoint { + remote-endpoint = <&usb1_sbu_mux>; + }; + }; + }; + }; + }; +}; + &mdss0 { status = "okay"; }; @@ -1004,6 +1130,10 @@ dr_mode = "host"; }; +&usb_0_dwc3_hs { + remote-endpoint = <&ucsi0_hs_in>; +}; + &usb_0_hsphy { vdda-pll-supply = <&vreg_l9d>; vdda18-supply = <&vreg_l1c>; @@ -1025,6 +1155,10 @@ remote-endpoint = <&mdss0_dp0_out>; }; +&usb_0_qmpphy_out { + remote-endpoint = <&ucsi0_ss_in>; +}; + &usb_1 { status = "okay"; }; @@ -1033,6 +1167,10 @@ dr_mode = "host"; }; +&usb_1_dwc3_hs { + remote-endpoint = <&ucsi1_hs_in>; +}; + &usb_1_hsphy { vdda-pll-supply = <&vreg_l4b>; vdda18-supply = <&vreg_l1c>; @@ -1054,6 +1192,10 @@ remote-endpoint = <&mdss0_dp1_out>; }; +&usb_1_qmpphy_out { + remote-endpoint = <&ucsi1_ss_in>; +}; + &usb_2 { status = "okay"; }; @@ -1177,6 +1319,13 @@ bias-disable; }; + i2c15_default: i2c15-default-state { + pins = "gpio36", "gpio37"; + function = "qup15"; + drive-strength = <2>; + bias-pull-up; + }; + mode_pin_active: mode-pin-state { pins = "gpio26"; function = "gpio"; @@ -1301,6 +1450,20 @@ }; }; + usb0_sbu_default: usb0-sbu-state { + pins = "gpio164"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + usb1_sbu_default: usb1-sbu-state { + pins = "gpio47"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + wcd_default: wcd-default-state { reset-pins { pins = "gpio106"; diff --git a/src/arm64/renesas/beacon-renesom-som.dtsi b/src/arm64/renesas/beacon-renesom-som.dtsi index 43f88c199b7..1489bc8d2f4 100644 --- a/src/arm64/renesas/beacon-renesom-som.dtsi +++ b/src/arm64/renesas/beacon-renesom-som.dtsi @@ -282,6 +282,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm64/renesas/condor-common.dtsi b/src/arm64/renesas/condor-common.dtsi index 375a56b20f2..a1058415057 100644 --- a/src/arm64/renesas/condor-common.dtsi +++ b/src/arm64/renesas/condor-common.dtsi @@ -544,6 +544,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm64/renesas/draak.dtsi b/src/arm64/renesas/draak.dtsi index 05712cd96d2..380b857fd27 100644 --- a/src/arm64/renesas/draak.dtsi +++ b/src/arm64/renesas/draak.dtsi @@ -695,6 +695,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm64/renesas/ebisu.dtsi b/src/arm64/renesas/ebisu.dtsi index ab828365666..4f38b01ae18 100644 --- a/src/arm64/renesas/ebisu.dtsi +++ b/src/arm64/renesas/ebisu.dtsi @@ -786,6 +786,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm64/renesas/hihope-common.dtsi b/src/arm64/renesas/hihope-common.dtsi index 659ae1fed2f..4e78139d52f 100644 --- a/src/arm64/renesas/hihope-common.dtsi +++ b/src/arm64/renesas/hihope-common.dtsi @@ -289,6 +289,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm64/renesas/r8a774a1.dtsi b/src/arm64/renesas/r8a774a1.dtsi index f065ee90649..c8b87aed92a 100644 --- a/src/arm64/renesas/r8a774a1.dtsi +++ b/src/arm64/renesas/r8a774a1.dtsi @@ -215,6 +215,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -222,6 +223,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -262,6 +264,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -400,6 +404,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774a1"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -480,11 +485,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774a1-rst"; reg = <0 0xe6160000 0 0x018c>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2785,6 +2792,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a774b1.dtsi b/src/arm64/renesas/r8a774b1.dtsi index 117cb6950f9..f2fc2a2035a 100644 --- a/src/arm64/renesas/r8a774b1.dtsi +++ b/src/arm64/renesas/r8a774b1.dtsi @@ -108,6 +108,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -115,6 +116,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -146,6 +148,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -284,6 +288,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774b1"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -364,11 +369,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774b1-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2661,6 +2668,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a774c0-cat874.dts b/src/arm64/renesas/r8a774c0-cat874.dts index b78dbd807d1..57a281fc497 100644 --- a/src/arm64/renesas/r8a774c0-cat874.dts +++ b/src/arm64/renesas/r8a774c0-cat874.dts @@ -378,6 +378,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm64/renesas/r8a774c0.dtsi b/src/arm64/renesas/r8a774c0.dtsi index 7655d5e3a03..530ffd29cf1 100644 --- a/src/arm64/renesas/r8a774c0.dtsi +++ b/src/arm64/renesas/r8a774c0.dtsi @@ -47,16 +47,20 @@ cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; + opp-800000000 { opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; opp-suspend; }; @@ -103,6 +107,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -134,6 +139,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -257,6 +264,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774c0"; reg = <0 0xe6060000 0 0x508>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -337,11 +345,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774c0-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1953,6 +1963,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a774e1.dtsi b/src/arm64/renesas/r8a774e1.dtsi index f845ca604de..e4dbda8c34d 100644 --- a/src/arm64/renesas/r8a774e1.dtsi +++ b/src/arm64/renesas/r8a774e1.dtsi @@ -277,6 +277,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -284,6 +285,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -326,6 +328,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -464,6 +468,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a774e1"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -544,11 +549,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a774e1-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2917,6 +2924,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a77951.dtsi b/src/arm64/renesas/r8a77951.dtsi index 96f3b5fe7e9..6ee9cdeb5a3 100644 --- a/src/arm64/renesas/r8a77951.dtsi +++ b/src/arm64/renesas/r8a77951.dtsi @@ -292,6 +292,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -299,6 +300,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -347,6 +349,7 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -485,6 +488,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7795"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -565,11 +569,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a7795-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -3398,6 +3404,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a77960.dtsi b/src/arm64/renesas/r8a77960.dtsi index ee80f52dc7c..a323ac47ca7 100644 --- a/src/arm64/renesas/r8a77960.dtsi +++ b/src/arm64/renesas/r8a77960.dtsi @@ -264,6 +264,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -271,6 +272,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -311,6 +313,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -449,6 +453,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a7796"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -529,11 +534,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a7796-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2996,6 +3003,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a77961.dtsi b/src/arm64/renesas/r8a77961.dtsi index 3b9066043a7..49f6d31c590 100644 --- a/src/arm64/renesas/r8a77961.dtsi +++ b/src/arm64/renesas/r8a77961.dtsi @@ -264,6 +264,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -271,6 +272,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -311,6 +313,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -449,6 +453,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77961"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -529,11 +534,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77961-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2817,6 +2824,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a77965.dtsi b/src/arm64/renesas/r8a77965.dtsi index 557bdf8fab1..136a22ca50b 100644 --- a/src/arm64/renesas/r8a77965.dtsi +++ b/src/arm64/renesas/r8a77965.dtsi @@ -143,6 +143,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -150,6 +151,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -182,6 +184,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -320,6 +324,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77965"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -400,11 +405,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77965-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2828,6 +2835,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a77970-eagle-function-expansion.dtso b/src/arm64/renesas/r8a77970-eagle-function-expansion.dtso index 9450d8ac94c..0c005660d8d 100644 --- a/src/arm64/renesas/r8a77970-eagle-function-expansion.dtso +++ b/src/arm64/renesas/r8a77970-eagle-function-expansion.dtso @@ -70,7 +70,7 @@ gpio-controller; #gpio-cells = <2>; - vin0_adv7612_en { + vin0-adv7612-en-hog { gpio-hog; gpios = <3 GPIO_ACTIVE_LOW>; output-high; diff --git a/src/arm64/renesas/r8a77970-eagle.dts b/src/arm64/renesas/r8a77970-eagle.dts index 32f07aa2731..8b594e9e9dc 100644 --- a/src/arm64/renesas/r8a77970-eagle.dts +++ b/src/arm64/renesas/r8a77970-eagle.dts @@ -409,6 +409,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm64/renesas/r8a77970-v3msk.dts b/src/arm64/renesas/r8a77970-v3msk.dts index 118e77f4477..445f5dd7c98 100644 --- a/src/arm64/renesas/r8a77970-v3msk.dts +++ b/src/arm64/renesas/r8a77970-v3msk.dts @@ -296,6 +296,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm64/renesas/r8a77970.dtsi b/src/arm64/renesas/r8a77970.dtsi index 38145fd6acf..01744496805 100644 --- a/src/arm64/renesas/r8a77970.dtsi +++ b/src/arm64/renesas/r8a77970.dtsi @@ -60,6 +60,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -67,6 +68,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a53 { @@ -91,6 +93,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -200,6 +203,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77970"; reg = <0 0xe6060000 0 0x504>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -280,11 +284,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77970-rst"; reg = <0 0xe6160000 0 0x200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1196,6 +1202,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a77980-v3hsk.dts b/src/arm64/renesas/r8a77980-v3hsk.dts index b409a8d1737..c2692d6fd00 100644 --- a/src/arm64/renesas/r8a77980-v3hsk.dts +++ b/src/arm64/renesas/r8a77980-v3hsk.dts @@ -282,6 +282,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm64/renesas/r8a77980.dtsi b/src/arm64/renesas/r8a77980.dtsi index 55a6c622f87..f7e506ad7a2 100644 --- a/src/arm64/renesas/r8a77980.dtsi +++ b/src/arm64/renesas/r8a77980.dtsi @@ -80,6 +80,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -87,6 +88,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -120,6 +122,7 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; #address-cells = <2>; #size-cells = <2>; @@ -229,6 +232,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77980"; reg = <0 0xe6060000 0 0x50c>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -309,11 +313,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77980-rst"; reg = <0 0xe6160000 0 0x200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1579,6 +1585,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a77990.dtsi b/src/arm64/renesas/r8a77990.dtsi index 233af3081e8..6b874204583 100644 --- a/src/arm64/renesas/r8a77990.dtsi +++ b/src/arm64/renesas/r8a77990.dtsi @@ -47,16 +47,20 @@ cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; + opp-800000000 { opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; }; opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; }; opp-1200000000 { opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1030000>; clock-latency-ns = <300000>; opp-suspend; }; @@ -118,6 +122,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; /* External PCIe clock - can be overridden by the board */ @@ -149,6 +154,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -272,6 +279,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77990"; reg = <0 0xe6060000 0 0x508>; + bootph-all; }; i2c_dvfs: i2c@e60b0000 { @@ -368,11 +376,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77990-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2117,6 +2127,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a77995.dtsi b/src/arm64/renesas/r8a77995.dtsi index 5f0828a4675..b66cd7c90d5 100644 --- a/src/arm64/renesas/r8a77995.dtsi +++ b/src/arm64/renesas/r8a77995.dtsi @@ -65,6 +65,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a53 { @@ -86,6 +87,8 @@ soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -209,6 +212,7 @@ pfc: pinctrl@e6060000 { compatible = "renesas,pfc-r8a77995"; reg = <0 0xe6060000 0 0x508>; + bootph-all; }; cmt0: timer@e60f0000 { @@ -289,11 +293,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77995-rst"; reg = <0 0xe6160000 0 0x0200>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -1448,6 +1454,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a779a0-falcon-cpu.dtsi b/src/arm64/renesas/r8a779a0-falcon-cpu.dtsi index e8c8fca48b6..0916fd57d1f 100644 --- a/src/arm64/renesas/r8a779a0-falcon-cpu.dtsi +++ b/src/arm64/renesas/r8a779a0-falcon-cpu.dtsi @@ -348,6 +348,7 @@ &scif0 { pinctrl-0 = <&scif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/src/arm64/renesas/r8a779a0.dtsi b/src/arm64/renesas/r8a779a0.dtsi index fe6d97859e4..f1613bfd163 100644 --- a/src/arm64/renesas/r8a779a0.dtsi +++ b/src/arm64/renesas/r8a779a0.dtsi @@ -47,6 +47,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -54,6 +55,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pmu_a76 { @@ -71,6 +73,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -93,6 +97,7 @@ <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>, <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6058180 { @@ -331,11 +336,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779a0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2338,6 +2345,42 @@ iommus = <&ipmmu_vi1 7>; }; + fcpvx0: fcp@fedb0000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb0000 0 0x200>; + clocks = <&cpg CPG_MOD 1100>; + power-domains = <&sysc R8A779A0_PD_A3ISP01>; + resets = <&cpg 1100>; + iommus = <&ipmmu_vi1 24>; + }; + + fcpvx1: fcp@fedb8000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb8000 0 0x200>; + clocks = <&cpg CPG_MOD 1101>; + power-domains = <&sysc R8A779A0_PD_A3ISP01>; + resets = <&cpg 1101>; + iommus = <&ipmmu_vi1 25>; + }; + + fcpvx2: fcp@fedc0000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedc0000 0 0x200>; + clocks = <&cpg CPG_MOD 1102>; + power-domains = <&sysc R8A779A0_PD_A3ISP23>; + resets = <&cpg 1102>; + iommus = <&ipmmu_vi1 26>; + }; + + fcpvx3: fcp@fedc8000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedc8000 0 0x200>; + clocks = <&cpg CPG_MOD 1103>; + power-domains = <&sysc R8A779A0_PD_A3ISP23>; + resets = <&cpg 1103>; + iommus = <&ipmmu_vi1 27>; + }; + vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x5000>; @@ -2360,6 +2403,50 @@ renesas,fcp = <&fcpvd1>; }; + vspx0: vsp@fedd0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 1028>; + power-domains = <&sysc R8A779A0_PD_A3ISP01>; + resets = <&cpg 1028>; + + renesas,fcp = <&fcpvx0>; + }; + + vspx1: vsp@fedd8000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd8000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 1029>; + power-domains = <&sysc R8A779A0_PD_A3ISP01>; + resets = <&cpg 1029>; + + renesas,fcp = <&fcpvx1>; + }; + + vspx2: vsp@fede0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfede0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 1030>; + power-domains = <&sysc R8A779A0_PD_A3ISP23>; + resets = <&cpg 1030>; + + renesas,fcp = <&fcpvx2>; + }; + + vspx3: vsp@fede8000 { + compatible = "renesas,vsp2"; + reg = <0 0xfede8000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 1031>; + power-domains = <&sysc R8A779A0_PD_A3ISP23>; + resets = <&cpg 1031>; + + renesas,fcp = <&fcpvx3>; + }; + csi40: csi2@feaa0000 { compatible = "renesas,r8a779a0-csi2"; reg = <0 0xfeaa0000 0 0x10000>; @@ -2893,6 +2980,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a779f0-spider-cpu.dtsi b/src/arm64/renesas/r8a779f0-spider-cpu.dtsi index e03baefb6a9..1781bb79a61 100644 --- a/src/arm64/renesas/r8a779f0-spider-cpu.dtsi +++ b/src/arm64/renesas/r8a779f0-spider-cpu.dtsi @@ -101,6 +101,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; diff --git a/src/arm64/renesas/r8a779f0-spider-ethernet.dtsi b/src/arm64/renesas/r8a779f0-spider-ethernet.dtsi index 5d38669ed1e..ad2b0398d35 100644 --- a/src/arm64/renesas/r8a779f0-spider-ethernet.dtsi +++ b/src/arm64/renesas/r8a779f0-spider-ethernet.dtsi @@ -5,6 +5,14 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ +/ { + aliases { + ethernet0 = &rswitch_port0; + ethernet1 = &rswitch_port1; + ethernet2 = &rswitch_port2; + }; +}; + ð_serdes { status = "okay"; }; @@ -42,61 +50,61 @@ pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>; pinctrl-names = "default"; status = "okay"; +}; + +&rswitch_port0 { + reg = <0>; + phy-handle = <&u101>; + phy-mode = "sgmii"; + phys = <ð_serdes 0>; + status = "okay"; - ethernet-ports { + mdio { #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; - phy-handle = <&u101>; - phy-mode = "sgmii"; - phys = <ð_serdes 0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - u101: ethernet-phy@1 { - reg = <1>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>; - }; - }; - }; - port@1 { + u101: ethernet-phy@1 { reg = <1>; - phy-handle = <&u201>; - phy-mode = "sgmii"; - phys = <ð_serdes 1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - u201: ethernet-phy@2 { - reg = <2>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>; - }; - }; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>; }; - port@2 { + }; +}; + +&rswitch_port1 { + reg = <1>; + phy-handle = <&u201>; + phy-mode = "sgmii"; + phys = <ð_serdes 1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + u201: ethernet-phy@2 { reg = <2>; - phy-handle = <&u301>; - phy-mode = "sgmii"; - phys = <ð_serdes 2>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - u301: ethernet-phy@3 { - reg = <3>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 9 IRQ_TYPE_LEVEL_LOW>; - }; - }; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&rswitch_port2 { + reg = <2>; + phy-handle = <&u301>; + phy-mode = "sgmii"; + phys = <ð_serdes 2>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + u301: ethernet-phy@3 { + reg = <3>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 9 IRQ_TYPE_LEVEL_LOW>; }; }; }; diff --git a/src/arm64/renesas/r8a779f0.dtsi b/src/arm64/renesas/r8a779f0.dtsi index 054498e5473..b496495c59a 100644 --- a/src/arm64/renesas/r8a779f0.dtsi +++ b/src/arm64/renesas/r8a779f0.dtsi @@ -253,6 +253,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -260,6 +261,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -296,6 +298,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -315,6 +319,7 @@ compatible = "renesas,pfc-r8a779f0"; reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -463,11 +468,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779f0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -974,17 +981,20 @@ #address-cells = <1>; #size-cells = <0>; - port@0 { + rswitch_port0: port@0 { reg = <0>; phys = <ð_serdes 0>; + status = "disabled"; }; - port@1 { + rswitch_port1: port@1 { reg = <1>; phys = <ð_serdes 1>; + status = "disabled"; }; - port@2 { + rswitch_port2: port@2 { reg = <2>; phys = <ð_serdes 2>; + status = "disabled"; }; }; }; @@ -1280,6 +1290,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a779f4-s4sk.dts b/src/arm64/renesas/r8a779f4-s4sk.dts index 5d71d52f9c6..67b18f2bffb 100644 --- a/src/arm64/renesas/r8a779f4-s4sk.dts +++ b/src/arm64/renesas/r8a779f4-s4sk.dts @@ -22,7 +22,8 @@ i2c5 = &i2c5; serial0 = &hscif0; serial1 = &hscif1; - ethernet0 = &rswitch; + ethernet0 = &rswitch_port0; + ethernet1 = &rswitch_port1; }; chosen { @@ -67,6 +68,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; @@ -179,49 +181,42 @@ pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>; pinctrl-names = "default"; status = "okay"; +}; + +&rswitch_port0 { + reg = <0>; + phy-handle = <&ic99>; + phy-mode = "sgmii"; + phys = <ð_serdes 0>; + status = "okay"; - ethernet-ports { + mdio { #address-cells = <1>; #size-cells = <0>; - port@0 { - reg = <0>; - phy-handle = <&ic99>; - phy-mode = "sgmii"; - phys = <ð_serdes 0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ic99: ethernet-phy@1 { - reg = <1>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>; - }; - }; - }; - - port@1 { + ic99: ethernet-phy@1 { reg = <1>; - phy-handle = <&ic102>; - phy-mode = "sgmii"; - phys = <ð_serdes 1>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ic102: ethernet-phy@2 { - reg = <2>; - compatible = "ethernet-phy-ieee802.3-c45"; - interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>; - }; - }; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 10 IRQ_TYPE_LEVEL_LOW>; }; + }; +}; + +&rswitch_port1 { + reg = <1>; + phy-handle = <&ic102>; + phy-mode = "sgmii"; + phys = <ð_serdes 1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; - port@2 { - status = "disabled"; + ic102: ethernet-phy@2 { + reg = <2>; + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts-extended = <&gpio3 11 IRQ_TYPE_LEVEL_LOW>; }; }; }; diff --git a/src/arm64/renesas/r8a779g0.dtsi b/src/arm64/renesas/r8a779g0.dtsi index 104f740d20d..1760720b712 100644 --- a/src/arm64/renesas/r8a779g0.dtsi +++ b/src/arm64/renesas/r8a779g0.dtsi @@ -166,6 +166,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr { @@ -173,6 +174,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -215,6 +217,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -237,6 +241,7 @@ <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>, <0 0xe6068000 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -452,11 +457,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779g0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -2171,6 +2178,24 @@ iommus = <&ipmmu_vi1 7>; }; + fcpvx0: fcp@fedb0000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb0000 0 0x200>; + clocks = <&cpg CPG_MOD 1100>; + power-domains = <&sysc R8A779G0_PD_A3ISP0>; + resets = <&cpg 1100>; + iommus = <&ipmmu_vi1 24>; + }; + + fcpvx1: fcp@fedb8000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb8000 0 0x200>; + clocks = <&cpg CPG_MOD 1101>; + power-domains = <&sysc R8A779G0_PD_A3ISP1>; + resets = <&cpg 1101>; + iommus = <&ipmmu_vi1 25>; + }; + vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x7000>; @@ -2193,6 +2218,28 @@ renesas,fcp = <&fcpvd1>; }; + vspx0: vsp@fedd0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 1028>; + power-domains = <&sysc R8A779G0_PD_A3ISP0>; + resets = <&cpg 1028>; + + renesas,fcp = <&fcpvx0>; + }; + + vspx1: vsp@fedd8000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd8000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 1029>; + power-domains = <&sysc R8A779G0_PD_A3ISP1>; + resets = <&cpg 1029>; + + renesas,fcp = <&fcpvx1>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a779g0"; reg = <0 0xfeb00000 0 0x40000>; @@ -2453,49 +2500,10 @@ }; }; - fcpvx0: fcp@fedb0000 { - compatible = "renesas,fcpv"; - reg = <0 0xfedb0000 0 0x200>; - clocks = <&cpg CPG_MOD 1100>; - power-domains = <&sysc R8A779G0_PD_A3ISP0>; - resets = <&cpg 1100>; - iommus = <&ipmmu_vi1 24>; - }; - - fcpvx1: fcp@fedb8000 { - compatible = "renesas,fcpv"; - reg = <0 0xfedb8000 0 0x200>; - clocks = <&cpg CPG_MOD 1101>; - power-domains = <&sysc R8A779G0_PD_A3ISP1>; - resets = <&cpg 1101>; - iommus = <&ipmmu_vi1 25>; - }; - - vspx0: vsp@fedd0000 { - compatible = "renesas,vsp2"; - reg = <0 0xfedd0000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 1028>; - power-domains = <&sysc R8A779G0_PD_A3ISP0>; - resets = <&cpg 1028>; - - renesas,fcp = <&fcpvx0>; - }; - - vspx1: vsp@fedd8000 { - compatible = "renesas,vsp2"; - reg = <0 0xfedd8000 0 0x8000>; - interrupts = ; - clocks = <&cpg CPG_MOD 1029>; - power-domains = <&sysc R8A779G0_PD_A3ISP1>; - resets = <&cpg 1029>; - - renesas,fcp = <&fcpvx1>; - }; - prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r8a779h0-gray-hawk-single.dts b/src/arm64/renesas/r8a779h0-gray-hawk-single.dts index 18fd52f55de..4d890e0617a 100644 --- a/src/arm64/renesas/r8a779h0-gray-hawk-single.dts +++ b/src/arm64/renesas/r8a779h0-gray-hawk-single.dts @@ -46,6 +46,8 @@ serial0 = &hscif0; serial1 = &hscif2; ethernet0 = &avb0; + ethernet1 = &avb1; + ethernet2 = &avb2; }; can_transceiver0: can-phy0 { @@ -200,17 +202,64 @@ &avb0 { pinctrl-0 = <&avb0_pins>; pinctrl-names = "default"; - phy-handle = <&phy0>; + phy-handle = <&avb0_phy>; tx-internal-delay-ps = <2000>; status = "okay"; - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + mdio { + #address-cells = <1>; + #size-cells = <0>; + + avb0_phy: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupts-extended = <&gpio7 5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&avb1 { + pinctrl-0 = <&avb1_pins>; + pinctrl-names = "default"; + phy-handle = <&avb1_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio6 1 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb1_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + interrupts-extended = <&gpio6 3 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&avb2 { + pinctrl-0 = <&avb2_pins>; + pinctrl-names = "default"; + phy-handle = <&avb2_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + avb2_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0>; + interrupts-extended = <&gpio5 4 IRQ_TYPE_LEVEL_LOW>; + }; }; }; @@ -233,25 +282,6 @@ }; }; -&dsi0 { - status = "okay"; - - ports { - port@1 { - reg = <1>; - - dsi0_out: endpoint { - remote-endpoint = <&sn65dsi86_in0>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&du { - status = "okay"; -}; - &csi40 { status = "okay"; @@ -292,6 +322,25 @@ }; }; +&dsi0 { + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi86_in0>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + &extal_clk { clock-frequency = <16666666>; }; @@ -312,6 +361,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; uart-has-rtscts; status = "okay"; @@ -558,6 +608,56 @@ }; }; + avb1_pins: avb1 { + mux { + groups = "avb1_link", "avb1_mdio", "avb1_rgmii", + "avb1_txcrefclk"; + function = "avb1"; + }; + + link { + groups = "avb1_link"; + bias-disable; + }; + + mdio { + groups = "avb1_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb1_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + + avb2_pins: avb2 { + mux { + groups = "avb2_link", "avb2_mdio", "avb2_rgmii", + "avb2_txcrefclk"; + function = "avb2"; + }; + + link { + groups = "avb2_link"; + bias-disable; + }; + + mdio { + groups = "avb2_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "avb2_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; + can_clk_pins: can-clk { groups = "can_clk"; function = "can_clk"; diff --git a/src/arm64/renesas/r8a779h0.dtsi b/src/arm64/renesas/r8a779h0.dtsi index d0c01c0fdda..8524a1e7205 100644 --- a/src/arm64/renesas/r8a779h0.dtsi +++ b/src/arm64/renesas/r8a779h0.dtsi @@ -138,6 +138,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; extalr_clk: extalr-clk { @@ -145,6 +146,7 @@ #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; + bootph-all; }; pcie0_clkref: pcie0-clkref { @@ -180,6 +182,8 @@ soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; + bootph-all; + #address-cells = <2>; #size-cells = <2>; ranges; @@ -201,6 +205,7 @@ <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>; + bootph-all; }; gpio0: gpio@e6050180 { @@ -401,11 +406,13 @@ #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; + bootph-all; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a779h0-rst"; reg = <0 0xe6160000 0 0x4000>; + bootph-all; }; sysc: system-controller@e6180000 { @@ -793,8 +800,6 @@ rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_hc 0>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -842,8 +847,6 @@ rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_hc 1>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -891,8 +894,6 @@ rx-internal-delay-ps = <0>; tx-internal-delay-ps = <0>; iommus = <&ipmmu_hc 2>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; @@ -1908,6 +1909,15 @@ resets = <&cpg 508>; }; + fcpvx0: fcp@fedb0000 { + compatible = "renesas,fcpv"; + reg = <0 0xfedb0000 0 0x200>; + clocks = <&cpg CPG_MOD 1100>; + power-domains = <&sysc R8A779H0_PD_A3ISP0>; + resets = <&cpg 1100>; + iommus = <&ipmmu_vi1 24>; + }; + vspd0: vsp@fea20000 { compatible = "renesas,vsp2"; reg = <0 0xfea20000 0 0x8000>; @@ -1918,6 +1928,17 @@ renesas,fcp = <&fcpvd0>; }; + vspx0: vsp@fedd0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfedd0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 1028>; + power-domains = <&sysc R8A779H0_PD_A3ISP0>; + resets = <&cpg 1028>; + + renesas,fcp = <&fcpvx0>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a779h0"; reg = <0 0xfeb00000 0 0x40000>; @@ -2144,6 +2165,7 @@ prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; + bootph-all; }; }; diff --git a/src/arm64/renesas/r9a07g044l2-remi-pi.dts b/src/arm64/renesas/r9a07g044l2-remi-pi.dts new file mode 100644 index 00000000000..3267e7b75b5 --- /dev/null +++ b/src/arm64/renesas/r9a07g044l2-remi-pi.dts @@ -0,0 +1,339 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the MYIR Remi Pi + * + * Copyright (C) 2022 MYIR Electronics Corp. + * Copyright (C) 2025 Collabora Ltd. + */ + +/dts-v1/; + +#include +#include + +#include "r9a07g044l2.dtsi" + +/ { + model = "MYIR Tech Limited Remi Pi MYB-YG2LX-REMI"; + compatible = "myir,remi-pi", "renesas,r9a07g044l2", "renesas,r9a07g044"; + + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + + mmc0 = &sdhi0; + + serial0 = &scif0; + serial4 = &scif4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + ddc-i2c-bus = <&i2c1>; + + port { + hdmi_con: endpoint { + remote-endpoint = <<8912_out>; + }; + }; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + vin-supply = <®_5p0v>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + vin-supply = <®_5p0v>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5.0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_1p1v: regulator-vdd-core { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; +}; + +&dsi { + status = "okay"; + + ports { + port@1 { + dsi_out: endpoint { + remote-endpoint = <<8912_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupts-extended = <&pinctrl RZG2L_GPIO(44, 2) IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&pinctrl RZG2L_GPIO(44, 3) GPIO_ACTIVE_LOW>; + }; +}; + +ð1 { + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy1: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <6>; + interrupts-extended = <&pinctrl RZG2L_GPIO(43, 2) IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&pinctrl RZG2L_GPIO(43, 3) GPIO_ACTIVE_LOW>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +&gpu { + mali-supply = <®_1p1v>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + clock-frequency = <400000>; + status = "okay"; + + hdmi-bridge@48 { + compatible = "lontium,lt8912b"; + reg = <0x48> ; + reset-gpios = <&pinctrl RZG2L_GPIO(42, 2) GPIO_ACTIVE_LOW>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt8912_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + lt8912_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; +}; + +&mtu3 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + +&phyrst { + status = "okay"; +}; + +&pinctrl { + eth0_pins: eth0 { + pinmux = , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TXC */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + ; /* ET0_RXD3 */ + }; + + eth1_pins: eth1 { + pinmux = , /* ET1_MDC */ + , /* ET1_MDIO */ + , /* ET1_TXC */ + , /* ET1_TX_CTL */ + , /* ET1_TXD0 */ + , /* ET1_TXD1 */ + , /* ET1_TXD2 */ + , /* ET1_TXD3 */ + , /* ET1_RXC */ + , /* ET1_RX_CTL */ + , /* ET1_RXD0 */ + , /* ET1_RXD1 */ + , /* ET1_RXD2 */ + ; /* ET1_RXD3 */ + }; + + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + i2c2_pins: i2c2 { + pinmux = , /* SDA */ + ; /* SCL */ + }; + + i2c3_pins: i2c3 { + pinmux = , /* SDA */ + ; /* SCL */ + }; + + scif0_pins: scif0 { + pinmux = , /* TxD */ + ; /* RxD */ + }; + + scif4_pins: scif4 { + pinmux = , /* TxD */ + ; /* RxD */ + }; + + sdhi0_pins: sd0 { + sd0-ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0-data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source = <1800>; + }; + + sd0-rst { + pins = "SD0_RST#"; + power-source = <1800>; + }; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scif4 { + pinctrl-0 = <&scif4_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; + +&usb2_phy1 { + status = "okay"; +}; diff --git a/src/arm64/renesas/r9a08g045.dtsi b/src/arm64/renesas/r9a08g045.dtsi index a9b98db9ef9..0364f89776e 100644 --- a/src/arm64/renesas/r9a08g045.dtsi +++ b/src/arm64/renesas/r9a08g045.dtsi @@ -28,6 +28,33 @@ clock-frequency = <0>; }; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-137500000 { + opp-hz = /bits/ 64 <137500000>; + opp-microvolt = <940000>; + clock-latency-ns = <300000>; + }; + opp-275000000 { + opp-hz = /bits/ 64 <275000000>; + opp-microvolt = <940000>; + clock-latency-ns = <300000>; + }; + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-microvolt = <940000>; + clock-latency-ns = <300000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <940000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -40,6 +67,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { @@ -443,7 +471,6 @@ ; interrupt-names = "lpm_int", "ca55stbydone_int", "cm33stbyr_int", "ca55_deny"; - status = "disabled"; }; pinctrl: pinctrl@11030000 { diff --git a/src/arm64/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso b/src/arm64/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso new file mode 100644 index 00000000000..4a81e3a3c8b --- /dev/null +++ b/src/arm64/renesas/r9a08g045s33-smarc-pmod1-type-3a.dtso @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G3S SMARC Carrier II EVK PMOD parts + * + * Copyright (C) 2024 Renesas Electronics Corp. + * + * + * [Connection] + * + * SMARC Carrier II EVK + * +--------------------------------------------+ + * |PMOD1_3A (PMOD1 PIN HEADER) | + * | SCIF1_CTS# (pin1) (pin7) PMOD1_GPIO10 | + * | SCIF1_TXD (pin2) (pin8) PMOD1_GPIO11 | + * | SCIF1_RXD (pin3) (pin9) PMOD1_GPIO12 | + * | SCIF1_RTS# (pin4) (pin10) PMOD1_GPIO13 | + * | GND (pin5) (pin11) GND | + * | PWR_PMOD1 (pin6) (pin12) GND | + * +--------------------------------------------+ + * + * The following switches should be set as follows for SCIF1: + * - SW_CONFIG2: ON + * - SW_OPT_MUX4: ON + */ + +/dts-v1/; +/plugin/; + +#include +#include "rzg3s-smarc-switches.h" + +&pinctrl { + scif1_pins: scif1-pins { + pinmux = , /* TXD */ + , /* RXD */ + , /* CTS# */ + ; /* RTS# */ + }; +}; + +#if SW_CONFIG3 == SW_ON && SW_OPT_MUX4 == SW_ON +&scif1 { + pinctrl-names = "default"; + pinctrl-0 = <&scif1_pins>; + uart-has-rtscts; + status = "okay"; +}; +#endif diff --git a/src/arm64/renesas/r9a09g047.dtsi b/src/arm64/renesas/r9a09g047.dtsi index 200e9ea8919..c93aa16d0a6 100644 --- a/src/arm64/renesas/r9a09g047.dtsi +++ b/src/arm64/renesas/r9a09g047.dtsi @@ -154,6 +154,13 @@ #power-domain-cells = <0>; }; + sys: system-controller@10430000 { + compatible = "renesas,r9a09g047-sys"; + reg = <0 0x10430000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; + resets = <&cpg 0x30>; + }; + scif0: serial@11c01400 { compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; reg = <0 0x11c01400 0 0x400>; @@ -175,6 +182,36 @@ status = "disabled"; }; + wdt1: watchdog@14400000 { + compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; + reg = <0 0x14400000 0 0x400>; + clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x76>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt2: watchdog@13000000 { + compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; + reg = <0 0x13000000 0 0x400>; + clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x77>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt3: watchdog@13000400 { + compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; + reg = <0 0x13000400 0 0x400>; + clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x78>; + power-domains = <&cpg>; + status = "disabled"; + }; + i2c0: i2c@14400400 { compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; reg = <0 0x14400400 0 0x400>; diff --git a/src/arm64/renesas/r9a09g057.dtsi b/src/arm64/renesas/r9a09g057.dtsi index 1c550b22b16..0cd00bb0519 100644 --- a/src/arm64/renesas/r9a09g057.dtsi +++ b/src/arm64/renesas/r9a09g057.dtsi @@ -105,6 +105,35 @@ }; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000>; + opp-microvolt = <800000>; + }; + + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-microvolt = <800000>; + }; + + opp-157500000 { + opp-hz = /bits/ 64 <157500000>; + opp-microvolt = <800000>; + }; + + opp-78750000 { + opp-hz = /bits/ 64 <78750000>; + opp-microvolt = <800000>; + }; + + opp-19687500 { + opp-hz = /bits/ 64 <19687500>; + opp-microvolt = <800000>; + }; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -249,7 +278,6 @@ reg = <0 0x10430000 0 0x10000>; clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; resets = <&cpg 0x30>; - status = "disabled"; }; ostm0: timer@11800000 { @@ -582,6 +610,28 @@ status = "disabled"; }; + gpu: gpu@14850000 { + compatible = "renesas,r9a09g057-mali", + "arm,mali-bifrost"; + reg = <0x0 0x14850000 0x0 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "job", "mmu", "gpu", "event"; + clocks = <&cpg CPG_MOD 0xf0>, + <&cpg CPG_MOD 0xf1>, + <&cpg CPG_MOD 0xf2>; + clock-names = "gpu", "bus", "bus_ace"; + power-domains = <&cpg>; + resets = <&cpg 0xdd>, + <&cpg 0xde>, + <&cpg 0xdf>; + reset-names = "rst", "axi_rst", "ace_rst"; + operating-points-v2 = <&gpu_opp_table>; + status = "disabled"; + }; + gic: interrupt-controller@14900000 { compatible = "arm,gic-v3"; reg = <0x0 0x14900000 0 0x20000>, diff --git a/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts b/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts index 0b705c987b6..063eca0ba3e 100644 --- a/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/src/arm64/renesas/r9a09g057h44-rzv2h-evk.dts @@ -43,6 +43,16 @@ reg = <0x2 0x40000000 0x2 0x00000000>; }; + reg_0p8v: regulator0 { + compatible = "regulator-fixed"; + + regulator-name = "fixed-0.8V"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + reg_3p3v: regulator1 { compatible = "regulator-fixed"; @@ -68,6 +78,11 @@ clock-frequency = <22579200>; }; +&gpu { + status = "okay"; + mali-supply = <®_0p8v>; +}; + &i2c0 { pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; diff --git a/src/arm64/renesas/r9a09g057h48-kakip.dts b/src/arm64/renesas/r9a09g057h48-kakip.dts new file mode 100644 index 00000000000..d2586d27876 --- /dev/null +++ b/src/arm64/renesas/r9a09g057h48-kakip.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for Yuridenki-Shokai the Kakip board + * + * Copyright (C) 2024 Nobuhiro Iwamatsu + */ + +/dts-v1/; + +#include +#include +#include "r9a09g057.dtsi" + +/ { + model = "Yuridenki-Shokai Kakip Board based on r9a09g057h48"; + compatible = "yuridenki,kakip", "renesas,r9a09g057h48", "renesas,r9a09g057"; + + aliases { + serial0 = &scif; + mmc0 = &sdhi0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x1 0xF8000000>; + }; + + reg_3p3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vqmmc_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + regulator-name = "SDHI0 VccQ"; + gpios = <&pinctrl RZV2H_GPIO(A, 0) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios-states = <0>; + states = <3300000 0>, <1800000 1>; + }; +}; + +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + +&ostm3 { + status = "okay"; +}; + +&ostm4 { + status = "okay"; +}; + +&ostm5 { + status = "okay"; +}; + +&ostm6 { + status = "okay"; +}; + +&ostm7 { + status = "okay"; +}; + +&pinctrl { + scif_pins: scif { + pins = "SCIF_RXD", "SCIF_TXD"; + }; + + sd0-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd0_pwr_en"; + }; + + sdhi0_pins: sd0 { + sd0-clk { + pins = "SD0CLK"; + renesas,output-impedance = <3>; + slew-rate = <0>; + }; + + sd0-data { + pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3", "SD0CMD"; + input-enable; + renesas,output-impedance = <3>; + slew-rate = <0>; + }; + + sd0-mux { + pinmux = ; /* SD0_CD */ + }; + }; +}; + +&qextal_clk { + clock-frequency = <24000000>; +}; + +&scif { + pinctrl-0 = <&scif_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vqmmc_sdhi0>; + bus-width = <4>; + + status = "okay"; +}; diff --git a/src/arm64/renesas/rzg3e-smarc-som.dtsi b/src/arm64/renesas/rzg3e-smarc-som.dtsi index 6b583ae2ac5..f4ba050beb0 100644 --- a/src/arm64/renesas/rzg3e-smarc-som.dtsi +++ b/src/arm64/renesas/rzg3e-smarc-som.dtsi @@ -26,3 +26,7 @@ &rtxin_clk { clock-frequency = <32768>; }; + +&wdt1 { + status = "okay"; +}; diff --git a/src/arm64/renesas/rzg3s-smarc-som.dtsi b/src/arm64/renesas/rzg3s-smarc-som.dtsi index ef12c1c462a..39845faec89 100644 --- a/src/arm64/renesas/rzg3s-smarc-som.dtsi +++ b/src/arm64/renesas/rzg3s-smarc-som.dtsi @@ -9,25 +9,7 @@ #include #include -/* - * On-board switches' states: - * @SW_OFF: switch's state is OFF - * @SW_ON: switch's state is ON - */ -#define SW_OFF 0 -#define SW_ON 1 - -/* - * SW_CONFIG[x] switches' states: - * @SW_CONFIG2: - * SW_OFF - SD0 is connected to eMMC - * SW_ON - SD0 is connected to uSD0 card - * @SW_CONFIG3: - * SW_OFF - SD2 is connected to SoC - * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC - */ -#define SW_CONFIG2 SW_OFF -#define SW_CONFIG3 SW_ON +#include "rzg3s-smarc-switches.h" / { compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; diff --git a/src/arm64/renesas/rzg3s-smarc-switches.h b/src/arm64/renesas/rzg3s-smarc-switches.h new file mode 100644 index 00000000000..bbf908a5322 --- /dev/null +++ b/src/arm64/renesas/rzg3s-smarc-switches.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * On-board switches for the Renesas RZ/G3S SMARC Module and RZ SMARC Carrier II + * boards. + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#ifndef __RZG3S_SMARC_SWITCHES_H__ +#define __RZG3S_SMARC_SWITCHES_H__ + +/* + * On-board switches' states: + * @SW_OFF: switch's state is OFF + * @SW_ON: switch's state is ON + */ +#define SW_OFF 0 +#define SW_ON 1 + +/* + * SW_CONFIG[x] switches' states: + * @SW_CONFIG2: + * SW_OFF - SD0 is connected to eMMC + * SW_ON - SD0 is connected to uSD0 card + * @SW_CONFIG3: + * SW_OFF - SD2 is connected to SoC + * SW_ON - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC + */ +#define SW_CONFIG2 SW_OFF +#define SW_CONFIG3 SW_ON + +/* + * SW_OPT_MUX[x] switches' states: + * @SW_OPT_MUX4: + * SW_OFF - The SMARC SER0 signals are routed to M.2 Key E UART + * SW_ON - The SMARC SER0 signals are routed to PMOD1 + */ +#define SW_OPT_MUX4 SW_ON + +#endif /* __RZG3S_SMARC_SWITCHES_H__ */ diff --git a/src/arm64/renesas/rzg3s-smarc.dtsi b/src/arm64/renesas/rzg3s-smarc.dtsi index 81b4ffd1417..5e044a4d023 100644 --- a/src/arm64/renesas/rzg3s-smarc.dtsi +++ b/src/arm64/renesas/rzg3s-smarc.dtsi @@ -12,6 +12,8 @@ / { aliases { i2c0 = &i2c0; + serial0 = &scif1; + serial1 = &scif3; serial3 = &scif0; mmc1 = &sdhi1; }; @@ -162,6 +164,11 @@ ; /* TXD */ }; + scif3_pins: scif3 { + pinmux = , /* RXD */ + ; /* TXD */ + }; + sdhi1_pins: sd1 { data { pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; @@ -208,6 +215,12 @@ status = "okay"; }; +&scif3 { + pinctrl-names = "default"; + pinctrl-0 = <&scif3_pins>; + status = "okay"; +}; + &sdhi1 { pinctrl-0 = <&sdhi1_pins>; pinctrl-1 = <&sdhi1_pins_uhs>; diff --git a/src/arm64/renesas/salvator-common.dtsi b/src/arm64/renesas/salvator-common.dtsi index 06c7e974630..68971c870d1 100644 --- a/src/arm64/renesas/salvator-common.dtsi +++ b/src/arm64/renesas/salvator-common.dtsi @@ -940,6 +940,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm64/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi b/src/arm64/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi index 8ae6af1af09..4caa0281a68 100644 --- a/src/arm64/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi +++ b/src/arm64/renesas/ulcb-kf-audio-graph-card-mix+split.dtsi @@ -15,7 +15,9 @@ * (D) CPU3 (2ch) --/ (TDM-1 : 2,3ch) * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) - * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * (G) CPU6 (2ch) <---- (6ch) (Z) PCM3168A-c (TDM-a: 0,1ch) + * (H) CPU7 (2ch) <--/ (TDM-b: 2,3ch) + * (I) CPU8 (2ch) <--/ (TDM-c: 4,5ch) * * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) @@ -25,7 +27,9 @@ * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) * * (A) arecord -D plughw:0,0 xxx.wav - * (G) arecord -D plughw:1,4 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav (TDM-a) + * (H) arecord -D plughw:1,5 xxx.wav (TDM-b) + * (I) arecord -D plughw:1,6 xxx.wav (TDM-c) */ / { sound_card_kf: expand-sound { @@ -35,13 +39,18 @@ routing = "pcm3168a Playback", "DAI2 Playback", "pcm3168a Playback", "DAI3 Playback", "pcm3168a Playback", "DAI4 Playback", - "pcm3168a Playback", "DAI5 Playback"; + "pcm3168a Playback", "DAI5 Playback", + "DAI6 Capture", "pcm3168a Capture", + "DAI7 Capture", "pcm3168a Capture", + "DAI8 Capture", "pcm3168a Capture"; dais = <&snd_kf1 /* (C) CPU2 */ &snd_kf2 /* (D) CPU3 */ &snd_kf3 /* (E) CPU4 */ &snd_kf4 /* (F) CPU5 */ - &snd_kf5 /* (G) GPU6 */ + &snd_kf5 /* (G) CPU6 */ + &snd_kf6 /* (H) CPU7 */ + &snd_kf7 /* (I) CPU8 */ >; }; }; @@ -50,7 +59,9 @@ ports { #address-cells = <1>; #size-cells = <0>; + mclk-fs = <512>; + prefix = "pcm3168a"; /* * (Y) PCM3168A-p @@ -59,7 +70,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; - prefix = "pcm3168a"; convert-channels = <8>; /* to 8ch TDM */ /* (C) CPU2 -> (Y) PCM3168A-p */ @@ -91,10 +101,28 @@ * (Z) PCM3168A-c */ port@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; + + convert-channels = <6>; /* to 6ch TDM */ + /* (G) CPU6 <- PCM3168A-c */ - pcm3168a_endpoint_c: endpoint { - remote-endpoint = <&rsnd_for_pcm3168a_capture>; + pcm3168a_endpoint_c1: endpoint@0 { + reg = <0>; + remote-endpoint = <&rsnd_for_pcm3168a_capture1>; + clocks = <&clksndsel>; + }; + /* (H) CPU7 <- PCM3168A-c */ + pcm3168a_endpoint_c2: endpoint@1 { + reg = <1>; + remote-endpoint = <&rsnd_for_pcm3168a_capture2>; + clocks = <&clksndsel>; + }; + /* (I) CPU8 <- PCM3168A-c */ + pcm3168a_endpoint_c3: endpoint@2 { + reg = <2>; + remote-endpoint = <&rsnd_for_pcm3168a_capture3>; clocks = <&clksndsel>; }; }; @@ -160,12 +188,35 @@ */ snd_kf5: port@6 { reg = <6>; - rsnd_for_pcm3168a_capture: endpoint { - remote-endpoint = <&pcm3168a_endpoint_c>; + rsnd_for_pcm3168a_capture1: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c1>; + bitclock-master; + frame-master; + capture = <&ssiu40 &ssi4>; + }; + }; + /* + * (H) CPU7 + */ + snd_kf6: port@7 { + reg = <7>; + rsnd_for_pcm3168a_capture2: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c2>; + bitclock-master; + frame-master; + capture = <&ssiu41 &ssi4>; + }; + }; + /* + * (I) CPU8 + */ + snd_kf7: port@8 { + reg = <8>; + rsnd_for_pcm3168a_capture3: endpoint { + remote-endpoint = <&pcm3168a_endpoint_c3>; bitclock-master; frame-master; - dai-tdm-slot-num = <6>; - capture = <&ssi4>; + capture = <&ssiu42 &ssi4>; }; }; }; diff --git a/src/arm64/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi b/src/arm64/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi index 4cf632bc462..67a0057a338 100644 --- a/src/arm64/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi +++ b/src/arm64/renesas/ulcb-kf-audio-graph-card2-mix+split.dtsi @@ -15,7 +15,9 @@ * (D) CPU2 (2ch) --/ (TDM-1 : 2,3ch) * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) - * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * (G) CPU6 (2ch) <---- (6ch) (Z) PCM3168A-c (TDM-a: 0,1ch) + * (H) CPU7 (2ch) <--/ (TDM-b: 2,3ch) + * (I) CPU8 (2ch) <--/ (TDM-c: 4,5ch) * * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) @@ -25,7 +27,9 @@ * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) * * (A) arecord -D plughw:0,0 xxx.wav - * (G) arecord -D plughw:1,4 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav (TDM-a) + * (H) arecord -D plughw:1,5 xxx.wav (TDM-b) + * (I) arecord -D plughw:1,6 xxx.wav (TDM-c) */ / { sound_card_kf: expand-sound { @@ -36,19 +40,25 @@ "pcm3168a Playback", "DAI3 Playback", "pcm3168a Playback", "DAI4 Playback", "pcm3168a Playback", "DAI5 Playback", - "DAI6 Capture", "pcm3168a Capture"; + "DAI6 Capture", "pcm3168a Capture", + "DAI7 Capture", "pcm3168a Capture", + "DAI8 Capture", "pcm3168a Capture"; links = <&fe_c /* (C) CPU2 */ &fe_d /* (D) CPU3 */ &fe_e /* (E) CPU4 */ &fe_f /* (F) CPU5 */ - &rsnd_g /* (G) CPU6 */ + &fe_g /* (G) CPU6 */ + &fe_h /* (H) CPU7 */ + &fe_i /* (I) CPU8 */ &be_y /* (Y) PCM3168A-p */ + &be_z /* (Z) PCM3168A-c */ >; - dpcm { + dpcm: dpcm { #address-cells = <1>; #size-cells = <0>; + non-supplier; ports@0 { #address-cells = <1>; @@ -62,21 +72,32 @@ * (D) CPU3 * (E) CPU4 * (F) CPU5 + * (G) CPU6 + * (H) CPU7 + * (I) CPU8 */ fe_c: port@2 { reg = <2>; fe_c_ep: endpoint { remote-endpoint = <&rsnd_c_ep>; }; }; fe_d: port@3 { reg = <3>; fe_d_ep: endpoint { remote-endpoint = <&rsnd_d_ep>; }; }; fe_e: port@4 { reg = <4>; fe_e_ep: endpoint { remote-endpoint = <&rsnd_e_ep>; }; }; fe_f: port@5 { reg = <5>; fe_f_ep: endpoint { remote-endpoint = <&rsnd_f_ep>; }; }; + + fe_g: port@6 { reg = <6>; fe_g_ep: endpoint { remote-endpoint = <&rsnd_g_ep>; }; }; + fe_h: port@7 { reg = <7>; fe_h_ep: endpoint { remote-endpoint = <&rsnd_h_ep>; }; }; + fe_i: port@8 { reg = <8>; fe_i_ep: endpoint { remote-endpoint = <&rsnd_i_ep>; }; }; }; ports@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; /* * BE * * (Y) PCM3168A-p + * (Z) PCM3168A-c */ - be_y: port { be_y_ep: endpoint { remote-endpoint = <&pcm3168a_y_ep>; }; }; + be_y: port@0 { reg = <0>; be_y_ep: endpoint { remote-endpoint = <&pcm3168a_y_ep>; }; }; + be_z: port@1 { reg = <1>; be_z_ep: endpoint { remote-endpoint = <&pcm3168a_z_ep>; }; }; }; }; }; @@ -106,8 +127,9 @@ */ port@1 { reg = <1>; + convert-channels = <6>; /* to 6ch TDM */ pcm3168a_z_ep: endpoint { - remote-endpoint = <&rsnd_g_ep>; + remote-endpoint = <&be_z_ep>; clocks = <&clksndsel>; }; }; @@ -171,13 +193,37 @@ /* * (G) CPU6 */ - rsnd_g: port@6 { + port@6 { reg = <6>; rsnd_g_ep: endpoint { - remote-endpoint = <&pcm3168a_z_ep>; + remote-endpoint = <&fe_g_ep>; + bitclock-master; + frame-master; + capture = <&ssiu40 &ssi4>; + }; + }; + /* + * (H) CPU7 + */ + port@7 { + reg = <7>; + rsnd_h_ep: endpoint { + remote-endpoint = <&fe_h_ep>; + bitclock-master; + frame-master; + capture = <&ssiu41 &ssi4>; + }; + }; + /* + * (I) CPU8 + */ + port@8 { + reg = <8>; + rsnd_i_ep: endpoint { + remote-endpoint = <&fe_i_ep>; bitclock-master; frame-master; - capture = <&ssi4>; + capture = <&ssiu42 &ssi4>; }; }; }; diff --git a/src/arm64/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi b/src/arm64/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi index f01d91aaadf..fd75801c329 100644 --- a/src/arm64/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi +++ b/src/arm64/renesas/ulcb-kf-simple-audio-card-mix+split.dtsi @@ -15,7 +15,9 @@ * (D) CPU2 (2ch) --/ (TDM-1 : 2,3ch) * (E) CPU4 (2ch) --/ (TDM-2 : 4,5ch) * (F) CPU5 (2ch) --/ (TDM-3 : 6,7ch) - * (G) CPU6 (6ch) <---- (6ch) (Z) PCM3168A-c + * (G) CPU6 (2ch) <---- (6ch) (Z) PCM3168A-c (TDM-a: 0,1ch) + * (H) CPU7 (2ch) <--/ (TDM-b: 2,3ch) + * (I) CPU8 (2ch) <--/ (TDM-c: 4,5ch) * * (A) aplay -D plughw:0,0 xxx.wav (MIX-0) * (B) aplay -D plughw:0,1 xxx.wav (MIX-1) @@ -25,7 +27,9 @@ * (F) aplay -D plughw:1,3 xxx.wav (TDM-3) * * (A) arecord -D plughw:0,0 xxx.wav - * (G) arecord -D plughw:1,4 xxx.wav + * (G) arecord -D plughw:1,4 xxx.wav (TDM-a) + * (H) arecord -D plughw:1,5 xxx.wav (TDM-b) + * (I) arecord -D plughw:1,6 xxx.wav (TDM-c) */ / { @@ -39,7 +43,10 @@ simple-audio-card,routing = "pcm3168a Playback", "DAI2 Playback", "pcm3168a Playback", "DAI3 Playback", "pcm3168a Playback", "DAI4 Playback", - "pcm3168a Playback", "DAI5 Playback"; + "pcm3168a Playback", "DAI5 Playback", + "DAI6 Capture", "pcm3168a Capture", + "DAI7 Capture", "pcm3168a Capture", + "DAI8 Capture", "pcm3168a Capture"; simple-audio-card,dai-link@0 { #address-cells = <1>; @@ -88,15 +95,39 @@ }; simple-audio-card,dai-link@1 { + #address-cells = <1>; + #size-cells = <0>; reg = <1>; + convert-channels = <6>; /* to 6ch TDM */ + /* * (G) CPU6 */ - cpu { + cpu@0 { + reg = <0>; bitclock-master; frame-master; sound-dai = <&rcar_sound 6>; }; + /* + * (H) CPU7 + */ + cpu@1 { + reg = <1>; + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 7>; + }; + /* + * (I) CPU8 + */ + cpu@2 { + reg = <2>; + bitclock-master; + frame-master; + sound-dai = <&rcar_sound 8>; + }; + /* * (Z) PCM3168A-c */ @@ -151,7 +182,19 @@ * (G) CPU6 */ dai6 { - capture = <&ssi4>; + capture = <&ssiu40 &ssi4>; + }; + /* + * (H) CPU7 + */ + dai7 { + capture = <&ssiu41 &ssi4>; + }; + /* + * (I) CPU8 + */ + dai8 { + capture = <&ssiu42 &ssi4>; }; }; }; diff --git a/src/arm64/renesas/ulcb.dtsi b/src/arm64/renesas/ulcb.dtsi index 0c58d816c37..fcab957b54f 100644 --- a/src/arm64/renesas/ulcb.dtsi +++ b/src/arm64/renesas/ulcb.dtsi @@ -448,6 +448,7 @@ &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm64/renesas/white-hawk-cpu-common.dtsi b/src/arm64/renesas/white-hawk-cpu-common.dtsi index f24814d7c92..b4024e85ae5 100644 --- a/src/arm64/renesas/white-hawk-cpu-common.dtsi +++ b/src/arm64/renesas/white-hawk-cpu-common.dtsi @@ -201,6 +201,7 @@ &hscif0 { pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; + bootph-all; status = "okay"; }; diff --git a/src/arm64/renesas/white-hawk-csi-dsi.dtsi b/src/arm64/renesas/white-hawk-csi-dsi.dtsi index 9017c4475a7..a5d1c1008e7 100644 --- a/src/arm64/renesas/white-hawk-csi-dsi.dtsi +++ b/src/arm64/renesas/white-hawk-csi-dsi.dtsi @@ -21,7 +21,9 @@ bus-type = ; clock-lanes = <0>; data-lanes = <1 2 3>; - line-orders = <0 3 0>; + line-orders = ; remote-endpoint = <&max96712_out0>; }; }; @@ -42,7 +44,9 @@ bus-type = ; clock-lanes = <0>; data-lanes = <1 2 3>; - line-orders = <0 3 0>; + line-orders = ; remote-endpoint = <&max96712_out1>; }; }; diff --git a/src/arm64/rockchip/px30-engicam-common.dtsi b/src/arm64/rockchip/px30-engicam-common.dtsi index 1edfd643b25..a334ef0629d 100644 --- a/src/arm64/rockchip/px30-engicam-common.dtsi +++ b/src/arm64/rockchip/px30-engicam-common.dtsi @@ -31,7 +31,7 @@ }; vcc3v3_btreg: vcc3v3-btreg { - compatible = "regulator-gpio"; + compatible = "regulator-fixed"; enable-active-high; pinctrl-names = "default"; pinctrl-0 = <&bt_enable_h>; @@ -39,7 +39,6 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; - states = <3300000 0x0>; }; vcc3v3_rf_aux_mod: regulator-vcc3v3-rf-aux-mod { diff --git a/src/arm64/rockchip/px30-engicam-ctouch2.dtsi b/src/arm64/rockchip/px30-engicam-ctouch2.dtsi index 80db778c968..b60e68faa83 100644 --- a/src/arm64/rockchip/px30-engicam-ctouch2.dtsi +++ b/src/arm64/rockchip/px30-engicam-ctouch2.dtsi @@ -26,5 +26,5 @@ }; &vcc3v3_btreg { - enable-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; }; diff --git a/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts b/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts index 165d09ccb94..5886b802c52 100644 --- a/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts +++ b/src/arm64/rockchip/px30-engicam-px30-core-edimm2.2.dts @@ -39,5 +39,5 @@ }; &vcc3v3_btreg { - enable-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; + gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>; }; diff --git a/src/arm64/rockchip/px30-ringneck-haikou-lvds-9904379.dtso b/src/arm64/rockchip/px30-ringneck-haikou-lvds-9904379.dtso new file mode 100644 index 00000000000..3fc088a5636 --- /dev/null +++ b/src/arm64/rockchip/px30-ringneck-haikou-lvds-9904379.dtso @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * HAIKOU-LVDS-9904379 adapter for PX30 Ringneck and Haikou carrierboard. + * + * This adapter needs to be plugged in the fake PCIe connector called Video + * Connector on Haikou carrierboard. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +&{/} { + backlight_lvds: backlight-lvds { + compatible = "pwm-backlight"; + brightness-levels = <0 255>; + default-brightness-level = <255>; + num-interpolated-steps = <255>; + power-supply = <&vcc3v3_baseboard>; + pwms = <&pwm0 0 25000 0>; + }; + + panel { + compatible = "admatec,9904379", "panel-lvds"; + backlight = <&backlight_lvds>; + data-mapping = "vesa-24"; + height-mm = <126>; + power-supply = <&vcc3v3_baseboard>; + width-mm = <224>; + + panel-timing { + clock-frequency = <49500000>; + hactive = <1024>; + hback-porch = <90>; + hfront-porch = <90>; + hsync-len = <90>; + vactive = <600>; + vback-porch = <10>; + vfront-porch = <10>; + vsync-len = <10>; + }; + + port { + panel_in_lvds: endpoint { + remote-endpoint = <&lvds_out_panel>; + }; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi_dphy { + status = "okay"; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + /* EEPROM and GT928 are limited to 400KHz */ + clock-frequency = <400000>; + + touchscreen@14 { + compatible = "goodix,gt928"; + reg = <0x14>; + interrupt-parent = <&gpio0>; + interrupts = ; + irq-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int &touch_rst>; + pinctrl-names = "default"; + touchscreen-inverted-x; + touchscreen-inverted-y; + AVDD28-supply = <&vcc3v3_baseboard>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + eeprom@54 { + reg = <0x54>; + compatible = "st,24c04", "atmel,24c04"; + pagesize = <16>; + size = <512>; + vcc-supply = <&vcc3v3_baseboard>; + }; +}; + +&lvds { + status = "okay"; +}; + +&lvds_out { + lvds_out_panel: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; +}; + +&pinctrl { + touch { + touch_int: touch-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + touch_rst: touch-rst { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/src/arm64/rockchip/px30-ringneck-haikou-video-demo.dtso b/src/arm64/rockchip/px30-ringneck-haikou-video-demo.dtso new file mode 100644 index 00000000000..7d9ea5aa598 --- /dev/null +++ b/src/arm64/rockchip/px30-ringneck-haikou-video-demo.dtso @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Ringneck system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&dc_12v>; + pwms = <&pwm0 0 25000 0>; + }; + + cam_afvdd_2v8: regulator-cam-afvdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 2 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-afvdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_avdd_2v8: regulator-cam-avdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 4 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-avdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_dovdd_1v8: regulator-cam-dovdd-1v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "cam-dovdd-1v8"; + vin-supply = <&vcc1v8_video>; + }; + + cam_dvdd_1v2: regulator-cam-dvdd-1v2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pca9670 5 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "cam-dvdd-1v2"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc1v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "vcc2v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible = "gpio-leds"; + + video-adapter-led { + color = ; + gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>; + label = "video-adapter-led"; + linux,default-trigger = "none"; + }; + }; +}; + +&display_subsystem { + status = "okay"; +}; + +&dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3148w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc1v8_video>; + reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc2v8_video>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&dsi_dphy { + status = "okay"; +}; + +&dsi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency = <400000>; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio0>; + interrupts = ; + irq-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int>; + pinctrl-names = "default"; + reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vcc2v8_video>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible = "nxp,pca9670"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pca9670_resetn>; + pinctrl-names = "default"; + reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; diff --git a/src/arm64/rockchip/px30-ringneck-haikou.dts b/src/arm64/rockchip/px30-ringneck-haikou.dts index 1a59e8b1dc4..91cf4cd3fae 100644 --- a/src/arm64/rockchip/px30-ringneck-haikou.dts +++ b/src/arm64/rockchip/px30-ringneck-haikou.dts @@ -154,6 +154,8 @@ }; &i2c3 { + status = "okay"; + eeprom@50 { reg = <0x50>; compatible = "atmel,24c01"; diff --git a/src/arm64/rockchip/px30-ringneck.dtsi b/src/arm64/rockchip/px30-ringneck.dtsi index e80412abec0..142244d5270 100644 --- a/src/arm64/rockchip/px30-ringneck.dtsi +++ b/src/arm64/rockchip/px30-ringneck.dtsi @@ -325,10 +325,6 @@ }; }; -&i2c3 { - status = "okay"; -}; - &i2s0_8ch { rockchip,trcm-sync-tx-only; diff --git a/src/arm64/rockchip/rk3308-roc-cc.dts b/src/arm64/rockchip/rk3308-roc-cc.dts index 629121de5a1..5e718194899 100644 --- a/src/arm64/rockchip/rk3308-roc-cc.dts +++ b/src/arm64/rockchip/rk3308-roc-cc.dts @@ -147,7 +147,7 @@ &pwm5 { status = "okay"; - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm5_pin_pull_down>; }; diff --git a/src/arm64/rockchip/rk3318-a95x-z2.dts b/src/arm64/rockchip/rk3318-a95x-z2.dts index a94114fb7cc..96c27fc5005 100644 --- a/src/arm64/rockchip/rk3318-a95x-z2.dts +++ b/src/arm64/rockchip/rk3318-a95x-z2.dts @@ -274,13 +274,13 @@ &pwm0 { pinctrl-0 = <&pwm0_pin_pull_up>; - pinctrl-names = "active"; + pinctrl-names = "default"; status = "okay"; }; &pwm1 { pinctrl-0 = <&pwm1_pin_pull_up>; - pinctrl-names = "active"; + pinctrl-names = "default"; status = "okay"; }; diff --git a/src/arm64/rockchip/rk3328-rock-pi-e.dts b/src/arm64/rockchip/rk3328-rock-pi-e.dts index 6310b58de77..a4bdd87d072 100644 --- a/src/arm64/rockchip/rk3328-rock-pi-e.dts +++ b/src/arm64/rockchip/rk3328-rock-pi-e.dts @@ -428,10 +428,18 @@ status = "okay"; }; +&u2phy_otg { + status = "okay"; +}; + &uart2 { status = "okay"; }; +&usb20_otg { + status = "okay"; +}; + &usbdrd3 { dr_mode = "host"; status = "okay"; diff --git a/src/arm64/rockchip/rk3399-nanopi4.dtsi b/src/arm64/rockchip/rk3399-nanopi4.dtsi index b169be06d4d..c8eb5481f43 100644 --- a/src/arm64/rockchip/rk3399-nanopi4.dtsi +++ b/src/arm64/rockchip/rk3399-nanopi4.dtsi @@ -603,7 +603,7 @@ }; &pwm2 { - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm2_pin_pull_down>; status = "okay"; }; diff --git a/src/arm64/rockchip/rk3399-puma-haikou-video-demo.dtso b/src/arm64/rockchip/rk3399-puma-haikou-video-demo.dtso new file mode 100644 index 00000000000..0377ec860d3 --- /dev/null +++ b/src/arm64/rockchip/rk3399-puma-haikou-video-demo.dtso @@ -0,0 +1,166 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Cherry Embedded Solutions GmbH + * + * DEVKIT ADDON CAM-TS-A01 + * https://embedded.cherry.de/product/development-kit/ + * + * DT-overlay for the camera / DSI demo appliance for Haikou boards. + * In the flavour for use with a Puma system-on-module. + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include +#include +#include + +&{/} { + backlight: backlight { + compatible = "pwm-backlight"; + power-supply = <&dc_12v>; + pwms = <&pwm0 0 25000 0>; + }; + + cam_afvdd_2v8: regulator-cam-afvdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 2 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-afvdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_avdd_2v8: regulator-cam-avdd-2v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 4 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "cam-avdd-2v8"; + vin-supply = <&vcc2v8_video>; + }; + + cam_dovdd_1v8: regulator-cam-dovdd-1v8 { + compatible = "regulator-fixed"; + gpio = <&pca9670 3 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "cam-dovdd-1v8"; + vin-supply = <&vcc1v8_video>; + }; + + cam_dvdd_1v2: regulator-cam-dvdd-1v2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pca9670 5 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "cam-dvdd-1v2"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc1v8_video: regulator-vcc1v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc1v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + vcc2v8_video: regulator-vcc2v8-video { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2800000>; + regulator-min-microvolt = <2800000>; + regulator-name = "vcc2v8-video"; + vin-supply = <&vcc3v3_baseboard>; + }; + + video-adapter-leds { + compatible = "gpio-leds"; + + video-adapter-led { + color = ; + gpios = <&pca9670 7 GPIO_ACTIVE_HIGH>; + label = "video-adapter-led"; + linux,default-trigger = "none"; + }; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + /* OV5675, GT911, DW9714 are limited to 400KHz */ + clock-frequency = <400000>; + + touchscreen@14 { + compatible = "goodix,gt911"; + reg = <0x14>; + interrupt-parent = <&gpio1>; + interrupts = ; + irq-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&touch_int>; + pinctrl-names = "default"; + reset-gpios = <&pca9670 1 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vcc2v8_video>; + VDDIO-supply = <&vcc3v3_baseboard>; + }; + + pca9670: gpio@27 { + compatible = "nxp,pca9670"; + reg = <0x27>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-0 = <&pca9670_resetn>; + pinctrl-names = "default"; + reset-gpios = <&gpio4 RK_PD6 GPIO_ACTIVE_LOW>; + }; +}; + +&mipi_out { + mipi_out_panel: endpoint { + remote-endpoint = <&mipi_in_panel>; + }; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + panel@0 { + compatible = "leadtek,ltk050h3148w"; + reg = <0>; + backlight = <&backlight>; + iovcc-supply = <&vcc1v8_video>; + reset-gpios = <&pca9670 0 GPIO_ACTIVE_LOW>; + vci-supply = <&vcc2v8_video>; + + port { + mipi_in_panel: endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; +}; + +&pinctrl { + pca9670 { + pca9670_resetn: pca9670-resetn { + rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + touch { + touch_int: touch-int { + rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/src/arm64/rockchip/rk3399-puma-haikou.dts b/src/arm64/rockchip/rk3399-puma-haikou.dts index 947bbd62a6b..f2234dabd66 100644 --- a/src/arm64/rockchip/rk3399-puma-haikou.dts +++ b/src/arm64/rockchip/rk3399-puma-haikou.dts @@ -149,8 +149,15 @@ }; }; +&gmac { + status = "okay"; +}; + &hdmi { - ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&hdmi_sound { status = "okay"; }; @@ -186,9 +193,22 @@ }; }; -&i2c6 { +&i2c7 { + eeprom@50 { + reg = <0x50>; + compatible = "atmel,24c01"; + pagesize = <8>; + size = <128>; + vcc-supply = <&vcc3v3_baseboard>; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&i2s2 { status = "okay"; - clock-frequency = <400000>; }; &pcie_phy { diff --git a/src/arm64/rockchip/rk3399-puma.dtsi b/src/arm64/rockchip/rk3399-puma.dtsi index 995b30a7aae..e00fbaa8acc 100644 --- a/src/arm64/rockchip/rk3399-puma.dtsi +++ b/src/arm64/rockchip/rk3399-puma.dtsi @@ -183,7 +183,6 @@ snps,reset-delays-us = <0 10000 50000>; tx_delay = <0x10>; rx_delay = <0x23>; - status = "okay"; }; &gpu { @@ -389,6 +388,14 @@ }; }; +&hdmi { + ddc-i2c-bus = <&i2c3>; +}; + +&i2c6 { + clock-frequency = <400000>; +}; + &i2c7 { status = "okay"; clock-frequency = <400000>; @@ -439,7 +446,6 @@ pinctrl-1 = <&i2s0_2ch_bus_bclk_off>; rockchip,playback-channels = <2>; rockchip,capture-channels = <2>; - status = "okay"; }; /* diff --git a/src/arm64/rockchip/rk3399-roc-pc-plus.dts b/src/arm64/rockchip/rk3399-roc-pc-plus.dts index e2e9279fa26..8e3858cf988 100644 --- a/src/arm64/rockchip/rk3399-roc-pc-plus.dts +++ b/src/arm64/rockchip/rk3399-roc-pc-plus.dts @@ -112,7 +112,7 @@ &i2c1 { es8388: es8388@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru SCLK_I2S_8CH_OUT>; #sound-dai-cells = <0>; diff --git a/src/arm64/rockchip/rk3399-rock-pi-4.dtsi b/src/arm64/rockchip/rk3399-rock-pi-4.dtsi index 541dca12bf1..046dbe32901 100644 --- a/src/arm64/rockchip/rk3399-rock-pi-4.dtsi +++ b/src/arm64/rockchip/rk3399-rock-pi-4.dtsi @@ -43,7 +43,7 @@ sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; clocks = <&rk808 1>; - clock-names = "lpo"; + clock-names = "ext_clock"; pinctrl-names = "default"; pinctrl-0 = <&wifi_enable_h>; reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>; diff --git a/src/arm64/rockchip/rk3528-pinctrl.dtsi b/src/arm64/rockchip/rk3528-pinctrl.dtsi new file mode 100644 index 00000000000..ea051362fb2 --- /dev/null +++ b/src/arm64/rockchip/rk3528-pinctrl.dtsi @@ -0,0 +1,1397 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2022 Rockchip Electronics Co., Ltd. + */ + +#include +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + arm { + /omit-if-no-ref/ + arm_pins: arm-pins { + rockchip,pins = + /* arm_avs */ + <4 RK_PC4 3 &pcfg_pull_none>; + }; + }; + + clk { + /omit-if-no-ref/ + clkm0_32k_out: clkm0-32k-out { + rockchip,pins = + /* clkm0_32k_out */ + <3 RK_PC3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + clkm1_32k_out: clkm1-32k-out { + rockchip,pins = + /* clkm1_32k_out */ + <1 RK_PC3 1 &pcfg_pull_none>; + }; + }; + + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PD6 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <1 RK_PC7 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <1 RK_PD0 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <1 RK_PD1 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <1 RK_PD2 1 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <1 RK_PD3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clk */ + <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <1 RK_PD4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + emmc_strb: emmc-strb { + rockchip,pins = + /* emmc_strb */ + <1 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + eth { + /omit-if-no-ref/ + eth_pins: eth-pins { + rockchip,pins = + /* eth_clk_25m_out */ + <3 RK_PB5 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + fephy { + /omit-if-no-ref/ + fephym0_led_dpx: fephym0-led_dpx { + rockchip,pins = + /* fephy_led_dpx_m0 */ + <4 RK_PB5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym0_led_link: fephym0-led_link { + rockchip,pins = + /* fephy_led_link_m0 */ + <4 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym0_led_spd: fephym0-led_spd { + rockchip,pins = + /* fephy_led_spd_m0 */ + <4 RK_PB7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_dpx: fephym1-led_dpx { + rockchip,pins = + /* fephy_led_dpx_m1 */ + <2 RK_PA4 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_link: fephym1-led_link { + rockchip,pins = + /* fephy_led_link_m1 */ + <2 RK_PA6 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fephym1_led_spd: fephym1-led_spd { + rockchip,pins = + /* fephy_led_spd_m1 */ + <2 RK_PA5 5 &pcfg_pull_none>; + }; + }; + + fspi { + /omit-if-no-ref/ + fspi_pins: fspi-pins { + rockchip,pins = + /* fspi_clk */ + <1 RK_PD5 2 &pcfg_pull_none>, + /* fspi_d0 */ + <1 RK_PC4 2 &pcfg_pull_none>, + /* fspi_d1 */ + <1 RK_PC5 2 &pcfg_pull_none>, + /* fspi_d2 */ + <1 RK_PC6 2 &pcfg_pull_none>, + /* fspi_d3 */ + <1 RK_PC7 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + fspi_csn0: fspi-csn0 { + rockchip,pins = + /* fspi_csn0 */ + <1 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + fspi_csn1: fspi-csn1 { + rockchip,pins = + /* fspi_csn1 */ + <1 RK_PD1 2 &pcfg_pull_none>; + }; + }; + + gpu { + /omit-if-no-ref/ + gpu_pins: gpu-pins { + rockchip,pins = + /* gpu_avs */ + <4 RK_PC3 3 &pcfg_pull_none>; + }; + }; + + hdmi { + /omit-if-no-ref/ + hdmi_pins: hdmi-pins { + rockchip,pins = + /* hdmi_tx_cec */ + <0 RK_PA3 1 &pcfg_pull_none>, + /* hdmi_tx_hpd */ + <0 RK_PA2 1 &pcfg_pull_none>, + /* hdmi_tx_scl */ + <0 RK_PA4 1 &pcfg_pull_none>, + /* hdmi_tx_sda */ + <0 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + hsm { + /omit-if-no-ref/ + hsmm0_pins: hsmm0-pins { + rockchip,pins = + /* hsm_clk_out_m0 */ + <2 RK_PA2 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + hsmm1_pins: hsmm1-pins { + rockchip,pins = + /* hsm_clk_out_m1 */ + <1 RK_PA4 3 &pcfg_pull_none>; + }; + }; + + i2c0 { + /omit-if-no-ref/ + i2c0m0_xfer: i2c0m0-xfer { + rockchip,pins = + /* i2c0_scl_m0 */ + <4 RK_PC4 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m0 */ + <4 RK_PC3 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c0m1_xfer: i2c0m1-xfer { + rockchip,pins = + /* i2c0_scl_m1 */ + <4 RK_PA1 2 &pcfg_pull_none_smt>, + /* i2c0_sda_m1 */ + <4 RK_PA0 2 &pcfg_pull_none_smt>; + }; + }; + + i2c1 { + /omit-if-no-ref/ + i2c1m0_xfer: i2c1m0-xfer { + rockchip,pins = + /* i2c1_scl_m0 */ + <4 RK_PA3 2 &pcfg_pull_none_smt>, + /* i2c1_sda_m0 */ + <4 RK_PA2 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c1m1_xfer: i2c1m1-xfer { + rockchip,pins = + /* i2c1_scl_m1 */ + <4 RK_PC5 4 &pcfg_pull_none_smt>, + /* i2c1_sda_m1 */ + <4 RK_PC6 4 &pcfg_pull_none_smt>; + }; + }; + + i2c2 { + /omit-if-no-ref/ + i2c2m0_xfer: i2c2m0-xfer { + rockchip,pins = + /* i2c2_scl_m0 */ + <0 RK_PA4 2 &pcfg_pull_none_smt>, + /* i2c2_sda_m0 */ + <0 RK_PA5 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c2m1_xfer: i2c2m1-xfer { + rockchip,pins = + /* i2c2_scl_m1 */ + <1 RK_PA5 3 &pcfg_pull_none_smt>, + /* i2c2_sda_m1 */ + <1 RK_PA6 3 &pcfg_pull_none_smt>; + }; + }; + + i2c3 { + /omit-if-no-ref/ + i2c3m0_xfer: i2c3m0-xfer { + rockchip,pins = + /* i2c3_scl_m0 */ + <1 RK_PA0 2 &pcfg_pull_none_smt>, + /* i2c3_sda_m0 */ + <1 RK_PA1 2 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c3m1_xfer: i2c3m1-xfer { + rockchip,pins = + /* i2c3_scl_m1 */ + <3 RK_PC1 5 &pcfg_pull_none_smt>, + /* i2c3_sda_m1 */ + <3 RK_PC3 5 &pcfg_pull_none_smt>; + }; + }; + + i2c4 { + /omit-if-no-ref/ + i2c4_xfer: i2c4-xfer { + rockchip,pins = + /* i2c4_scl */ + <2 RK_PA0 4 &pcfg_pull_none_smt>, + /* i2c4_sda */ + <2 RK_PA1 4 &pcfg_pull_none_smt>; + }; + }; + + i2c5 { + /omit-if-no-ref/ + i2c5m0_xfer: i2c5m0-xfer { + rockchip,pins = + /* i2c5_scl_m0 */ + <1 RK_PB2 3 &pcfg_pull_none_smt>, + /* i2c5_sda_m0 */ + <1 RK_PB3 3 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c5m1_xfer: i2c5m1-xfer { + rockchip,pins = + /* i2c5_scl_m1 */ + <1 RK_PD2 3 &pcfg_pull_none_smt>, + /* i2c5_sda_m1 */ + <1 RK_PD3 3 &pcfg_pull_none_smt>; + }; + }; + + i2c6 { + /omit-if-no-ref/ + i2c6m0_xfer: i2c6m0-xfer { + rockchip,pins = + /* i2c6_scl_m0 */ + <3 RK_PB2 5 &pcfg_pull_none_smt>, + /* i2c6_sda_m0 */ + <3 RK_PB3 5 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2c6m1_xfer: i2c6m1-xfer { + rockchip,pins = + /* i2c6_scl_m1 */ + <1 RK_PD4 3 &pcfg_pull_none_smt>, + /* i2c6_sda_m1 */ + <1 RK_PD7 3 &pcfg_pull_none_smt>; + }; + }; + + i2c7 { + /omit-if-no-ref/ + i2c7_xfer: i2c7-xfer { + rockchip,pins = + /* i2c7_scl */ + <2 RK_PA5 4 &pcfg_pull_none_smt>, + /* i2c7_sda */ + <2 RK_PA6 4 &pcfg_pull_none_smt>; + }; + }; + + i2s0 { + /omit-if-no-ref/ + i2s0m0_lrck: i2s0m0-lrck { + rockchip,pins = + /* i2s0_lrck_m0 */ + <3 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_mclk: i2s0m0-mclk { + rockchip,pins = + /* i2s0_mclk_m0 */ + <3 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sclk: i2s0m0-sclk { + rockchip,pins = + /* i2s0_sclk_m0 */ + <3 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m0_sdi: i2s0m0-sdi { + rockchip,pins = + /* i2s0m0_sdi */ + <3 RK_PB7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s0m0_sdo: i2s0m0-sdo { + rockchip,pins = + /* i2s0m0_sdo */ + <3 RK_PC0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s0m1_lrck: i2s0m1-lrck { + rockchip,pins = + /* i2s0_lrck_m1 */ + <1 RK_PB6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_mclk: i2s0m1-mclk { + rockchip,pins = + /* i2s0_mclk_m1 */ + <1 RK_PB4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sclk: i2s0m1-sclk { + rockchip,pins = + /* i2s0_sclk_m1 */ + <1 RK_PB5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s0m1_sdi: i2s0m1-sdi { + rockchip,pins = + /* i2s0m1_sdi */ + <1 RK_PB7 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + i2s0m1_sdo: i2s0m1-sdo { + rockchip,pins = + /* i2s0m1_sdo */ + <1 RK_PC0 1 &pcfg_pull_none>; + }; + }; + + i2s1 { + /omit-if-no-ref/ + i2s1_lrck: i2s1-lrck { + rockchip,pins = + /* i2s1_lrck */ + <4 RK_PA6 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_mclk: i2s1-mclk { + rockchip,pins = + /* i2s1_mclk */ + <4 RK_PA4 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_sclk: i2s1-sclk { + rockchip,pins = + /* i2s1_sclk */ + <4 RK_PA5 1 &pcfg_pull_none_smt>; + }; + + /omit-if-no-ref/ + i2s1_sdi0: i2s1-sdi0 { + rockchip,pins = + /* i2s1_sdi0 */ + <4 RK_PB4 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi1: i2s1-sdi1 { + rockchip,pins = + /* i2s1_sdi1 */ + <4 RK_PB3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi2: i2s1-sdi2 { + rockchip,pins = + /* i2s1_sdi2 */ + <4 RK_PA3 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdi3: i2s1-sdi3 { + rockchip,pins = + /* i2s1_sdi3 */ + <4 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo0: i2s1-sdo0 { + rockchip,pins = + /* i2s1_sdo0 */ + <4 RK_PA7 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo1: i2s1-sdo1 { + rockchip,pins = + /* i2s1_sdo1 */ + <4 RK_PB0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo2: i2s1-sdo2 { + rockchip,pins = + /* i2s1_sdo2 */ + <4 RK_PB1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + i2s1_sdo3: i2s1-sdo3 { + rockchip,pins = + /* i2s1_sdo3 */ + <4 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + jtag { + /omit-if-no-ref/ + jtagm0_pins: jtagm0-pins { + rockchip,pins = + /* jtag_cpu_tck_m0 */ + <2 RK_PA2 2 &pcfg_pull_none>, + /* jtag_cpu_tms_m0 */ + <2 RK_PA3 2 &pcfg_pull_none>, + /* jtag_mcu_tck_m0 */ + <2 RK_PA4 2 &pcfg_pull_none>, + /* jtag_mcu_tms_m0 */ + <2 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + jtagm1_pins: jtagm1-pins { + rockchip,pins = + /* jtag_cpu_tck_m1 */ + <4 RK_PD0 2 &pcfg_pull_none>, + /* jtag_cpu_tms_m1 */ + <4 RK_PC7 2 &pcfg_pull_none>, + /* jtag_mcu_tck_m1 */ + <4 RK_PD0 3 &pcfg_pull_none>, + /* jtag_mcu_tms_m1 */ + <4 RK_PC7 3 &pcfg_pull_none>; + }; + }; + + pcie { + /omit-if-no-ref/ + pciem0_pins: pciem0-pins { + rockchip,pins = + /* pcie_clkreqn_m0 */ + <3 RK_PA6 5 &pcfg_pull_none>, + /* pcie_perstn_m0 */ + <3 RK_PB0 5 &pcfg_pull_none>, + /* pcie_waken_m0 */ + <3 RK_PA7 5 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pciem1_pins: pciem1-pins { + rockchip,pins = + /* pcie_clkreqn_m1 */ + <1 RK_PA0 4 &pcfg_pull_none>, + /* pcie_perstn_m1 */ + <1 RK_PA2 4 &pcfg_pull_none>, + /* pcie_waken_m1 */ + <1 RK_PA1 4 &pcfg_pull_none>; + }; + }; + + pdm { + /omit-if-no-ref/ + pdm_clk0: pdm-clk0 { + rockchip,pins = + /* pdm_clk0 */ + <4 RK_PB5 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_clk1: pdm-clk1 { + rockchip,pins = + /* pdm_clk1 */ + <4 RK_PA4 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi0: pdm-sdi0 { + rockchip,pins = + /* pdm_sdi0 */ + <4 RK_PB2 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi1: pdm-sdi1 { + rockchip,pins = + /* pdm_sdi1 */ + <4 RK_PB1 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi2: pdm-sdi2 { + rockchip,pins = + /* pdm_sdi2 */ + <4 RK_PB3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + pdm_sdi3: pdm-sdi3 { + rockchip,pins = + /* pdm_sdi3 */ + <4 RK_PC1 3 &pcfg_pull_none>; + }; + }; + + pmu { + /omit-if-no-ref/ + pmu_pins: pmu-pins { + rockchip,pins = + /* pmu_debug */ + <4 RK_PA0 4 &pcfg_pull_none>; + }; + }; + + pwm0 { + /omit-if-no-ref/ + pwm0m0_pins: pwm0m0-pins { + rockchip,pins = + /* pwm0_m0 */ + <4 RK_PC3 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm0m1_pins: pwm0m1-pins { + rockchip,pins = + /* pwm0_m1 */ + <1 RK_PA2 5 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm1 { + /omit-if-no-ref/ + pwm1m0_pins: pwm1m0-pins { + rockchip,pins = + /* pwm1_m0 */ + <4 RK_PC4 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm1m1_pins: pwm1m1-pins { + rockchip,pins = + /* pwm1_m1 */ + <1 RK_PA3 4 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm2 { + /omit-if-no-ref/ + pwm2m0_pins: pwm2m0-pins { + rockchip,pins = + /* pwm2_m0 */ + <4 RK_PC5 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm2m1_pins: pwm2m1-pins { + rockchip,pins = + /* pwm2_m1 */ + <1 RK_PA7 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm3 { + /omit-if-no-ref/ + pwm3m0_pins: pwm3m0-pins { + rockchip,pins = + /* pwm3_m0 */ + <4 RK_PC6 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm3m1_pins: pwm3m1-pins { + rockchip,pins = + /* pwm3_m1 */ + <2 RK_PA4 3 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm4 { + /omit-if-no-ref/ + pwm4m0_pins: pwm4m0-pins { + rockchip,pins = + /* pwm4_m0 */ + <4 RK_PB7 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm4m1_pins: pwm4m1-pins { + rockchip,pins = + /* pwm4_m1 */ + <1 RK_PA4 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm5 { + /omit-if-no-ref/ + pwm5m0_pins: pwm5m0-pins { + rockchip,pins = + /* pwm5_m0 */ + <4 RK_PC0 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm5m1_pins: pwm5m1-pins { + rockchip,pins = + /* pwm5_m1 */ + <3 RK_PC3 1 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm6 { + /omit-if-no-ref/ + pwm6m0_pins: pwm6m0-pins { + rockchip,pins = + /* pwm6_m0 */ + <4 RK_PC1 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm6m1_pins: pwm6m1-pins { + rockchip,pins = + /* pwm6_m1 */ + <1 RK_PC3 3 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm6m2_pins: pwm6m2-pins { + rockchip,pins = + /* pwm6_m2 */ + <3 RK_PC1 1 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwm7 { + /omit-if-no-ref/ + pwm7m0_pins: pwm7m0-pins { + rockchip,pins = + /* pwm7_m0 */ + <4 RK_PC2 1 &pcfg_pull_none_drv_level_0>; + }; + + /omit-if-no-ref/ + pwm7m1_pins: pwm7m1-pins { + rockchip,pins = + /* pwm7_m1 */ + <1 RK_PC2 2 &pcfg_pull_none_drv_level_0>; + }; + }; + + pwr { + /omit-if-no-ref/ + pwr_pins: pwr-pins { + rockchip,pins = + /* pwr_ctrl0 */ + <4 RK_PC2 2 &pcfg_pull_none>, + /* pwr_ctrl1 */ + <4 RK_PB6 1 &pcfg_pull_none>; + }; + }; + + ref { + /omit-if-no-ref/ + refm0_pins: refm0-pins { + rockchip,pins = + /* ref_clk_out_m0 */ + <0 RK_PA1 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + refm1_pins: refm1-pins { + rockchip,pins = + /* ref_clk_out_m1 */ + <3 RK_PC3 6 &pcfg_pull_none>; + }; + }; + + rgmii { + /omit-if-no-ref/ + rgmii_miim: rgmii-miim { + rockchip,pins = + /* rgmii_mdc */ + <3 RK_PB6 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_mdio */ + <3 RK_PB7 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_rx_bus2: rgmii-rx_bus2 { + rockchip,pins = + /* rgmii_rxd0 */ + <3 RK_PA3 2 &pcfg_pull_none>, + /* rgmii_rxd1 */ + <3 RK_PA2 2 &pcfg_pull_none>, + /* rgmii_rxdv_crs */ + <3 RK_PC2 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmii_tx_bus2: rgmii-tx_bus2 { + rockchip,pins = + /* rgmii_txd0 */ + <3 RK_PA1 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txd1 */ + <3 RK_PA0 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txen */ + <3 RK_PC0 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + rgmii_rgmii_clk: rgmii-rgmii_clk { + rockchip,pins = + /* rgmii_rxclk */ + <3 RK_PA5 2 &pcfg_pull_none>, + /* rgmii_txclk */ + <3 RK_PA4 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_rgmii_bus: rgmii-rgmii_bus { + rockchip,pins = + /* rgmii_rxd2 */ + <3 RK_PA7 2 &pcfg_pull_none>, + /* rgmii_rxd3 */ + <3 RK_PA6 2 &pcfg_pull_none>, + /* rgmii_txd2 */ + <3 RK_PB1 2 &pcfg_pull_none_drv_level_2>, + /* rgmii_txd3 */ + <3 RK_PB0 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + rgmii_clk: rgmii-clk { + rockchip,pins = + /* rgmii_clk */ + <3 RK_PB4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + rgmii_txer: rgmii-txer { + rockchip,pins = + /* rgmii_txer */ + <3 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + scr { + /omit-if-no-ref/ + scrm0_pins: scrm0-pins { + rockchip,pins = + /* scr_clk_m0 */ + <1 RK_PA2 3 &pcfg_pull_none>, + /* scr_data_m0 */ + <1 RK_PA1 3 &pcfg_pull_none>, + /* scr_detn_m0 */ + <1 RK_PA0 3 &pcfg_pull_none>, + /* scr_rstn_m0 */ + <1 RK_PA3 3 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + scrm1_pins: scrm1-pins { + rockchip,pins = + /* scr_clk_m1 */ + <2 RK_PA5 3 &pcfg_pull_none>, + /* scr_data_m1 */ + <2 RK_PA3 4 &pcfg_pull_none>, + /* scr_detn_m1 */ + <2 RK_PA6 3 &pcfg_pull_none>, + /* scr_rstn_m1 */ + <2 RK_PA4 4 &pcfg_pull_none>; + }; + }; + + sdio0 { + /omit-if-no-ref/ + sdio0_bus4: sdio0-bus4 { + rockchip,pins = + /* sdio0_d0 */ + <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d1 */ + <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d2 */ + <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* sdio0_d3 */ + <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_clk: sdio0-clk { + rockchip,pins = + /* sdio0_clk */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_cmd: sdio0-cmd { + rockchip,pins = + /* sdio0_cmd */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio0_det: sdio0-det { + rockchip,pins = + /* sdio0_det */ + <1 RK_PA6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdio0_pwren: sdio0-pwren { + rockchip,pins = + /* sdio0_pwren */ + <1 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + sdio1 { + /omit-if-no-ref/ + sdio1_bus4: sdio1-bus4 { + rockchip,pins = + /* sdio1_d0 */ + <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d1 */ + <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d2 */ + <3 RK_PB0 1 &pcfg_pull_up_drv_level_2>, + /* sdio1_d3 */ + <3 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_clk: sdio1-clk { + rockchip,pins = + /* sdio1_clk */ + <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_cmd: sdio1-cmd { + rockchip,pins = + /* sdio1_cmd */ + <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdio1_det: sdio1-det { + rockchip,pins = + /* sdio1_det */ + <3 RK_PB3 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdio1_pwren: sdio1-pwren { + rockchip,pins = + /* sdio1_pwren */ + <3 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + sdmmc { + /omit-if-no-ref/ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = + /* sdmmc_d0 */ + <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d1 */ + <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d2 */ + <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc_d3 */ + <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_clk: sdmmc-clk { + rockchip,pins = + /* sdmmc_clk */ + <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = + /* sdmmc_cmd */ + <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>; + }; + + /omit-if-no-ref/ + sdmmc_det: sdmmc-det { + rockchip,pins = + /* sdmmc_detn */ + <2 RK_PA6 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = + /* sdmmc_pwren */ + <4 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + spdif { + /omit-if-no-ref/ + spdifm0_pins: spdifm0-pins { + rockchip,pins = + /* spdif_tx_m0 */ + <4 RK_PA0 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm1_pins: spdifm1-pins { + rockchip,pins = + /* spdif_tx_m1 */ + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + spdifm2_pins: spdifm2-pins { + rockchip,pins = + /* spdif_tx_m2 */ + <3 RK_PC3 2 &pcfg_pull_none>; + }; + }; + + spi0 { + /omit-if-no-ref/ + spi0_pins: spi0-pins { + rockchip,pins = + /* spi0_clk */ + <4 RK_PB4 2 &pcfg_pull_none_drv_level_2>, + /* spi0_miso */ + <4 RK_PB3 2 &pcfg_pull_none_drv_level_2>, + /* spi0_mosi */ + <4 RK_PB2 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + spi0_csn0: spi0-csn0 { + rockchip,pins = + /* spi0_csn0 */ + <4 RK_PB6 2 &pcfg_pull_none_drv_level_2>; + }; + /omit-if-no-ref/ + spi0_csn1: spi0-csn1 { + rockchip,pins = + /* spi0_csn1 */ + <4 RK_PC1 2 &pcfg_pull_none_drv_level_2>; + }; + }; + + spi1 { + /omit-if-no-ref/ + spi1_pins: spi1-pins { + rockchip,pins = + /* spi1_clk */ + <1 RK_PB6 2 &pcfg_pull_none_drv_level_2>, + /* spi1_miso */ + <1 RK_PC0 2 &pcfg_pull_none_drv_level_2>, + /* spi1_mosi */ + <1 RK_PB7 2 &pcfg_pull_none_drv_level_2>; + }; + + /omit-if-no-ref/ + spi1_csn0: spi1-csn0 { + rockchip,pins = + /* spi1_csn0 */ + <1 RK_PC1 1 &pcfg_pull_none_drv_level_2>; + }; + /omit-if-no-ref/ + spi1_csn1: spi1-csn1 { + rockchip,pins = + /* spi1_csn1 */ + <1 RK_PC2 1 &pcfg_pull_none_drv_level_2>; + }; + }; + + tsi0 { + /omit-if-no-ref/ + tsi0_pins: tsi0-pins { + rockchip,pins = + /* tsi0_clkin */ + <3 RK_PB2 3 &pcfg_pull_none>, + /* tsi0_d0 */ + <3 RK_PB1 3 &pcfg_pull_none>, + /* tsi0_d1 */ + <3 RK_PB5 3 &pcfg_pull_none>, + /* tsi0_d2 */ + <3 RK_PB6 3 &pcfg_pull_none>, + /* tsi0_d3 */ + <3 RK_PB7 3 &pcfg_pull_none>, + /* tsi0_d4 */ + <3 RK_PA3 3 &pcfg_pull_none>, + /* tsi0_d5 */ + <3 RK_PA2 3 &pcfg_pull_none>, + /* tsi0_d6 */ + <3 RK_PA1 3 &pcfg_pull_none>, + /* tsi0_d7 */ + <3 RK_PA0 3 &pcfg_pull_none>, + /* tsi0_fail */ + <3 RK_PC0 3 &pcfg_pull_none>, + /* tsi0_sync */ + <3 RK_PB4 3 &pcfg_pull_none>, + /* tsi0_valid */ + <3 RK_PB3 3 &pcfg_pull_none>; + }; + }; + + tsi1 { + /omit-if-no-ref/ + tsi1_pins: tsi1-pins { + rockchip,pins = + /* tsi1_clkin */ + <3 RK_PA5 3 &pcfg_pull_none>, + /* tsi1_d0 */ + <3 RK_PA4 3 &pcfg_pull_none>, + /* tsi1_sync */ + <3 RK_PA7 3 &pcfg_pull_none>, + /* tsi1_valid */ + <3 RK_PA6 3 &pcfg_pull_none>; + }; + }; + + uart0 { + /omit-if-no-ref/ + uart0m0_xfer: uart0m0-xfer { + rockchip,pins = + /* uart0_rx_m0 */ + <4 RK_PC7 1 &pcfg_pull_up>, + /* uart0_tx_m0 */ + <4 RK_PD0 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart0m1_xfer: uart0m1-xfer { + rockchip,pins = + /* uart0_rx_m1 */ + <2 RK_PA0 2 &pcfg_pull_up>, + /* uart0_tx_m1 */ + <2 RK_PA1 2 &pcfg_pull_up>; + }; + }; + + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <4 RK_PA7 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <4 RK_PA6 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1m1_xfer: uart1m1-xfer { + rockchip,pins = + /* uart1_rx_m1 */ + <4 RK_PC6 2 &pcfg_pull_up>, + /* uart1_tx_m1 */ + <4 RK_PC5 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart1_ctsn: uart1-ctsn { + rockchip,pins = + /* uart1_ctsn */ + <4 RK_PA4 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart1_rtsn: uart1-rtsn { + rockchip,pins = + /* uart1_rtsn */ + <4 RK_PA5 2 &pcfg_pull_none>; + }; + }; + + uart2 { + /omit-if-no-ref/ + uart2m0_xfer: uart2m0-xfer { + rockchip,pins = + /* uart2_rx_m0 */ + <3 RK_PA0 1 &pcfg_pull_up>, + /* uart2_tx_m0 */ + <3 RK_PA1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m0_ctsn: uart2m0-ctsn { + rockchip,pins = + /* uart2m0_ctsn */ + <3 RK_PA3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m0_rtsn: uart2m0-rtsn { + rockchip,pins = + /* uart2m0_rtsn */ + <3 RK_PA2 1 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <1 RK_PB0 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <1 RK_PB1 1 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart2m1_ctsn: uart2m1-ctsn { + rockchip,pins = + /* uart2m1_ctsn */ + <1 RK_PB3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart2m1_rtsn: uart2m1-rtsn { + rockchip,pins = + /* uart2m1_rtsn */ + <1 RK_PB2 1 &pcfg_pull_none>; + }; + }; + + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <4 RK_PB0 2 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <4 RK_PB1 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3m1_xfer: uart3m1-xfer { + rockchip,pins = + /* uart3_rx_m1 */ + <4 RK_PB7 3 &pcfg_pull_up>, + /* uart3_tx_m1 */ + <4 RK_PC0 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart3_ctsn: uart3-ctsn { + rockchip,pins = + /* uart3_ctsn */ + <4 RK_PA3 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart3_rtsn: uart3-rtsn { + rockchip,pins = + /* uart3_rtsn */ + <4 RK_PA2 3 &pcfg_pull_none>; + }; + }; + + uart4 { + /omit-if-no-ref/ + uart4_xfer: uart4-xfer { + rockchip,pins = + /* uart4_rx */ + <2 RK_PA2 3 &pcfg_pull_up>, + /* uart4_tx */ + <2 RK_PA3 3 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart4_ctsn: uart4-ctsn { + rockchip,pins = + /* uart4_ctsn */ + <2 RK_PA1 3 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart4_rtsn: uart4-rtsn { + rockchip,pins = + /* uart4_rtsn */ + <2 RK_PA0 3 &pcfg_pull_none>; + }; + }; + + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <1 RK_PA2 2 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <1 RK_PA3 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m0_ctsn: uart5m0-ctsn { + rockchip,pins = + /* uart5m0_ctsn */ + <1 RK_PA6 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m0_rtsn: uart5m0-rtsn { + rockchip,pins = + /* uart5m0_rtsn */ + <1 RK_PA5 2 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart5m1_xfer: uart5m1-xfer { + rockchip,pins = + /* uart5_rx_m1 */ + <1 RK_PD4 2 &pcfg_pull_up>, + /* uart5_tx_m1 */ + <1 RK_PD7 2 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart5m1_ctsn: uart5m1-ctsn { + rockchip,pins = + /* uart5m1_ctsn */ + <1 RK_PD3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart5m1_rtsn: uart5m1-rtsn { + rockchip,pins = + /* uart5m1_rtsn */ + <1 RK_PD2 2 &pcfg_pull_none>; + }; + }; + + uart6 { + /omit-if-no-ref/ + uart6m0_xfer: uart6m0-xfer { + rockchip,pins = + /* uart6_rx_m0 */ + <3 RK_PA7 4 &pcfg_pull_up>, + /* uart6_tx_m0 */ + <3 RK_PA6 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6m1_xfer: uart6m1-xfer { + rockchip,pins = + /* uart6_rx_m1 */ + <3 RK_PC3 4 &pcfg_pull_up>, + /* uart6_tx_m1 */ + <3 RK_PC1 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart6_ctsn: uart6-ctsn { + rockchip,pins = + /* uart6_ctsn */ + <3 RK_PA4 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart6_rtsn: uart6-rtsn { + rockchip,pins = + /* uart6_rtsn */ + <3 RK_PA5 4 &pcfg_pull_none>; + }; + }; + + uart7 { + /omit-if-no-ref/ + uart7m0_xfer: uart7m0-xfer { + rockchip,pins = + /* uart7_rx_m0 */ + <3 RK_PB3 4 &pcfg_pull_up>, + /* uart7_tx_m0 */ + <3 RK_PB2 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m0_ctsn: uart7m0-ctsn { + rockchip,pins = + /* uart7m0_ctsn */ + <3 RK_PB0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m0_rtsn: uart7m0-rtsn { + rockchip,pins = + /* uart7m0_rtsn */ + <3 RK_PB1 4 &pcfg_pull_none>; + }; + + /omit-if-no-ref/ + uart7m1_xfer: uart7m1-xfer { + rockchip,pins = + /* uart7_rx_m1 */ + <1 RK_PB3 4 &pcfg_pull_up>, + /* uart7_tx_m1 */ + <1 RK_PB2 4 &pcfg_pull_up>; + }; + + /omit-if-no-ref/ + uart7m1_ctsn: uart7m1-ctsn { + rockchip,pins = + /* uart7m1_ctsn */ + <1 RK_PB0 4 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart7m1_rtsn: uart7m1-rtsn { + rockchip,pins = + /* uart7m1_rtsn */ + <1 RK_PB1 4 &pcfg_pull_none>; + }; + }; +}; diff --git a/src/arm64/rockchip/rk3528-radxa-e20c.dts b/src/arm64/rockchip/rk3528-radxa-e20c.dts index d2cdb63d4a9..57a446b5cbd 100644 --- a/src/arm64/rockchip/rk3528-radxa-e20c.dts +++ b/src/arm64/rockchip/rk3528-radxa-e20c.dts @@ -6,17 +6,150 @@ */ /dts-v1/; + +#include +#include #include "rk3528.dtsi" / { model = "Radxa E20C"; compatible = "radxa,e20c", "rockchip,rk3528"; + aliases { + mmc0 = &sdhci; + }; + chosen { stdout-path = "serial0:1500000n8"; }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "MASKROM"; + linux,code = ; + press-threshold-microvolt = <0>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&user_key>; + + button-user { + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; + label = "USER"; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&lan_led_g>, <&sys_led_g>, <&wan_led_g>; + + led-lan { + color = ; + default-state = "off"; + function = LED_FUNCTION_LAN; + gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + }; + + led-sys { + color = ; + default-state = "on"; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led-wan { + color = ; + default-state = "off"; + function = LED_FUNCTION_WAN; + gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "netdev"; + }; + }; + + vcc_1v8: regulator-1v8-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + vcc_3v3: regulator-3v3-vcc { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_sys: regulator-5v0-vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&pinctrl { + gpio-keys { + user_key: user-key { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + lan_led_g: lan-led-g { + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + sys_led_g: sys-led-g { + rockchip,pins = <4 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + wan_led_g: wan-led-g { + rockchip,pins = <4 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + cap-mmc-highspeed; + no-sd; + no-sdio; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; }; &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; diff --git a/src/arm64/rockchip/rk3528.dtsi b/src/arm64/rockchip/rk3528.dtsi index e58faa985aa..26c3559d6a6 100644 --- a/src/arm64/rockchip/rk3528.dtsi +++ b/src/arm64/rockchip/rk3528.dtsi @@ -4,8 +4,12 @@ * Copyright (c) 2024 Yao Zi */ +#include #include #include +#include +#include +#include / { compatible = "rockchip,rk3528"; @@ -15,6 +19,11 @@ #size-cells = <2>; aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -51,6 +60,7 @@ reg = <0x0>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; }; cpu1: cpu@1 { @@ -58,6 +68,7 @@ reg = <0x1>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; }; cpu2: cpu@2 { @@ -65,6 +76,7 @@ reg = <0x2>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; }; cpu3: cpu@3 { @@ -72,6 +84,22 @@ reg = <0x3>; device_type = "cpu"; enable-method = "psci"; + clocks = <&scmi_clk SCMI_CLK_CPU>; + }; + }; + + firmware { + scmi: scmi { + compatible = "arm,scmi-smc"; + arm,smc-id = <0x82000010>; + shmem = <&scmi_shmem>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; }; }; @@ -80,6 +108,18 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_shmem: shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + no-map; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -95,6 +135,13 @@ #clock-cells = <0>; }; + gmac0_clk: clock-gmac50m { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "gmac0"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; ranges = <0x0 0xfe000000 0x0 0xfe000000 0x0 0x2000000>; @@ -114,10 +161,219 @@ #interrupt-cells = <3>; }; + qos_crypto_a: qos@ff200000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200000 0x0 0x20>; + }; + + qos_crypto_p: qos@ff200080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200080 0x0 0x20>; + }; + + qos_dcf: qos@ff200100 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200100 0x0 0x20>; + }; + + qos_dft2apb: qos@ff200200 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200200 0x0 0x20>; + }; + + qos_dma2ddr: qos@ff200280 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200280 0x0 0x20>; + }; + + qos_dmac: qos@ff200300 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200300 0x0 0x20>; + }; + + qos_keyreader: qos@ff200380 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff200380 0x0 0x20>; + }; + + qos_cpu: qos@ff210000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff210000 0x0 0x20>; + }; + + qos_debug: qos@ff210080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff210080 0x0 0x20>; + }; + + qos_gpu_m0: qos@ff220000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff220000 0x0 0x20>; + }; + + qos_gpu_m1: qos@ff220080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff220080 0x0 0x20>; + }; + + qos_pmu_mcu: qos@ff240000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff240000 0x0 0x20>; + }; + + qos_rkvdec: qos@ff250000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff250000 0x0 0x20>; + }; + + qos_rkvenc: qos@ff260000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff260000 0x0 0x20>; + }; + + qos_gmac0: qos@ff270000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270000 0x0 0x20>; + }; + + qos_hdcp: qos@ff270080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270080 0x0 0x20>; + }; + + qos_jpegdec: qos@ff270100 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270100 0x0 0x20>; + }; + + qos_rga2_m0ro: qos@ff270200 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270200 0x0 0x20>; + }; + + qos_rga2_m0wo: qos@ff270280 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270280 0x0 0x20>; + }; + + qos_sdmmc0: qos@ff270300 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270300 0x0 0x20>; + }; + + qos_usb2host: qos@ff270380 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270380 0x0 0x20>; + }; + + qos_vdpp: qos@ff270480 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270480 0x0 0x20>; + }; + + qos_vop: qos@ff270500 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff270500 0x0 0x20>; + }; + + qos_emmc: qos@ff280000 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280000 0x0 0x20>; + }; + + qos_fspi: qos@ff280080 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280080 0x0 0x20>; + }; + + qos_gmac1: qos@ff280100 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280100 0x0 0x20>; + }; + + qos_pcie: qos@ff280180 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280180 0x0 0x20>; + }; + + qos_sdio0: qos@ff280200 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280200 0x0 0x20>; + }; + + qos_sdio1: qos@ff280280 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280280 0x0 0x20>; + }; + + qos_tsp: qos@ff280300 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280300 0x0 0x20>; + }; + + qos_usb3otg: qos@ff280380 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280380 0x0 0x20>; + }; + + qos_vpu: qos@ff280400 { + compatible = "rockchip,rk3528-qos", "syscon"; + reg = <0x0 0xff280400 0x0 0x20>; + }; + + cru: clock-controller@ff4a0000 { + compatible = "rockchip,rk3528-cru"; + reg = <0x0 0xff4a0000 0x0 0x30000>; + assigned-clocks = + <&cru XIN_OSC0_DIV>, <&cru PLL_GPLL>, + <&cru PLL_PPLL>, <&cru PLL_CPLL>, + <&cru ARMCLK>, <&cru CLK_MATRIX_250M_SRC>, + <&cru CLK_MATRIX_500M_SRC>, + <&cru CLK_MATRIX_50M_SRC>, + <&cru CLK_MATRIX_100M_SRC>, + <&cru CLK_MATRIX_150M_SRC>, + <&cru CLK_MATRIX_200M_SRC>, + <&cru CLK_MATRIX_300M_SRC>, + <&cru CLK_MATRIX_339M_SRC>, + <&cru CLK_MATRIX_400M_SRC>, + <&cru CLK_MATRIX_600M_SRC>, + <&cru CLK_PPLL_50M_MATRIX>, + <&cru CLK_PPLL_100M_MATRIX>, + <&cru CLK_PPLL_125M_MATRIX>, + <&cru ACLK_BUS_VOPGL_ROOT>; + assigned-clock-rates = + <32768>, <1188000000>, + <1000000000>, <996000000>, + <408000000>, <250000000>, + <500000000>, + <50000000>, + <100000000>, + <150000000>, + <200000000>, + <300000000>, + <340000000>, + <400000000>, + <600000000>, + <50000000>, + <100000000>, + <125000000>, + <500000000>; + clocks = <&xin24m>, <&gmac0_clk>; + clock-names = "xin24m", "gmac0"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + ioc_grf: syscon@ff540000 { + compatible = "rockchip,rk3528-ioc-grf", "syscon"; + reg = <0x0 0xff540000 0x0 0x40000>; + }; + uart0: serial@ff9f0000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xff9f0000 0x0 0x100>; - clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-io-width = <4>; reg-shift = <2>; @@ -127,6 +383,8 @@ uart1: serial@ff9f8000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xff9f8000 0x0 0x100>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-io-width = <4>; reg-shift = <2>; @@ -136,6 +394,8 @@ uart2: serial@ffa00000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa00000 0x0 0x100>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-io-width = <4>; reg-shift = <2>; @@ -144,6 +404,8 @@ uart3: serial@ffa08000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; reg = <0x0 0xffa08000 0x0 0x100>; reg-io-width = <4>; reg-shift = <2>; @@ -153,6 +415,8 @@ uart4: serial@ffa10000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa10000 0x0 0x100>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-io-width = <4>; reg-shift = <2>; @@ -162,6 +426,8 @@ uart5: serial@ffa18000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa18000 0x0 0x100>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-io-width = <4>; reg-shift = <2>; @@ -171,6 +437,8 @@ uart6: serial@ffa20000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa20000 0x0 0x100>; + clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-io-width = <4>; reg-shift = <2>; @@ -180,10 +448,118 @@ uart7: serial@ffa28000 { compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; reg = <0x0 0xffa28000 0x0 0x100>; + clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; + clock-names = "baudclk", "apb_pclk"; interrupts = ; reg-io-width = <4>; reg-shift = <2>; status = "disabled"; }; + + saradc: adc@ffae0000 { + compatible = "rockchip,rk3528-saradc"; + reg = <0x0 0xffae0000 0x0 0x10000>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + interrupts = ; + resets = <&cru SRST_P_SARADC>; + reset-names = "saradc-apb"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + sdhci: mmc@ffbf0000 { + compatible = "rockchip,rk3528-dwcmshc", + "rockchip,rk3588-dwcmshc"; + reg = <0x0 0xffbf0000 0x0 0x10000>; + assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, + <&cru CCLK_SRC_EMMC>; + assigned-clock-rates = <200000000>, <24000000>, + <200000000>; + clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, + <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, + <&cru TCLK_EMMC>; + clock-names = "core", "bus", "axi", "block", "timer"; + interrupts = ; + max-frequency = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, + <&emmc_strb>; + resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, + <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, + <&cru SRST_T_EMMC>; + reset-names = "core", "bus", "axi", "block", "timer"; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3528-pinctrl"; + rockchip,grf = <&ioc_grf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio@ff610000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff610000 0x0 0x200>; + clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ffaf0000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffaf0000 0x0 0x200>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 32 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ffb00000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb00000 0x0 0x200>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 64 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ffb10000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb10000 0x0 0x200>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 96 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ffb20000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xffb20000 0x0 0x200>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 128 32>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; }; }; + +#include "rk3528-pinctrl.dtsi" diff --git a/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi b/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi index a4835147176..e7ba477e75f 100644 --- a/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi +++ b/src/arm64/rockchip/rk3566-bigtreetech-cb2.dtsi @@ -775,7 +775,7 @@ rockchip,default-sample-phase = <90>; status = "okay"; - sdio-wifi@1 { + wifi@1 { compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio2>; diff --git a/src/arm64/rockchip/rk3566-pinenote.dtsi b/src/arm64/rockchip/rk3566-pinenote.dtsi index 2d3ae154482..3613661417b 100644 --- a/src/arm64/rockchip/rk3566-pinenote.dtsi +++ b/src/arm64/rockchip/rk3566-pinenote.dtsi @@ -9,6 +9,8 @@ #include "rk3566.dtsi" / { + chassis-type = "tablet"; + aliases { mmc0 = &sdhci; }; diff --git a/src/arm64/rockchip/rk3566-quartz64-a.dts b/src/arm64/rockchip/rk3566-quartz64-a.dts index 98e75df8b15..3c127c5c260 100644 --- a/src/arm64/rockchip/rk3566-quartz64-a.dts +++ b/src/arm64/rockchip/rk3566-quartz64-a.dts @@ -265,8 +265,12 @@ }; &gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>, + <&gmac1_clkin>; clock_in_out = "input"; phy-supply = <&vcc_3v3>; phy-mode = "rgmii"; diff --git a/src/arm64/rockchip/rk3566-quartz64-b.dts b/src/arm64/rockchip/rk3566-quartz64-b.dts index 24928a12944..5707321a114 100644 --- a/src/arm64/rockchip/rk3566-quartz64-b.dts +++ b/src/arm64/rockchip/rk3566-quartz64-b.dts @@ -173,8 +173,12 @@ }; &gmac1 { - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, + <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, + <&cru SCLK_GMAC1>, + <&gmac1_clkin>; clock_in_out = "input"; phy-mode = "rgmii"; phy-supply = <&vcc_3v3>; diff --git a/src/arm64/rockchip/rk3568-photonicat.dts b/src/arm64/rockchip/rk3568-photonicat.dts new file mode 100644 index 00000000000..58c1052ba8e --- /dev/null +++ b/src/arm64/rockchip/rk3568-photonicat.dts @@ -0,0 +1,588 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Ariaboard Photonicat"; + compatible = "ariaboard,photonicat", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + mmc0 = &sdhci; + mmc1 = &sdmmc0; + mmc2 = &sdmmc1; + }; + + battery: battery { + compatible = "simple-battery"; + device-chemistry = "lithium-ion"; + charge-full-design-microamp-hours = <6800000>; + energy-full-design-microwatt-hours = <25000000>; + voltage-max-design-microvolt = <4200000>; + voltage-min-design-microvolt = <3400000>; + + ocv-capacity-celsius = <25>; + ocv-capacity-table-0 = <4100000 100>, <4040000 90>, + <3980000 80>, <3920000 70>, + <3870000 60>, <3820000 50>, + <3790000 40>, <3770000 30>, + <3740000 20>, <3680000 10>, + <3450000 0>; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + hdmi_con: hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + vcc_1v8: regulator-vcc-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vcc_3v3: regulator-vcc-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_sys>; + }; + + /* actually fed by vcc_syson, dependent + * on pi6c clock generator + */ + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_pi6c>; + }; + + /* pi6c pcie clock generator */ + vcc3v3_pi6c: regulator-vcc3v3-pi6c { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_pi6c"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_syson>; + }; + + vcc3v3_sd: regulator-vcc3v3-sd { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_pwren>; + regulator-boot-on; + regulator-name = "vcc3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3>; + }; + + vcc3v3_sys: regulator-vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_syson>; + }; + + vcc3v4_rf: regulator-vcc3v4-rf { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&rf_pwr_en>; + regulator-name = "vcc3v4_rf"; + regulator-min-microvolt = <3400000>; + regulator-max-microvolt = <3400000>; + vin-supply = <&vccin_5v>; + }; + + vcc5v0_usb30_otg0: regulator-vcc5v0-usb30-otg0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren_h>; + regulator-name = "vcc5v0_usb30_otg0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vccin_5v>; + }; + + vccin_5v: regulator-vccin-5v { + compatible = "regulator-fixed"; + regulator-name = "vccin_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc_sysin: regulator-vcc-sysin { + compatible = "regulator-fixed"; + regulator-name = "vcc_sysin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vccin_5v>; + }; + + vcc_syson: regulator-vcc-syson { + compatible = "regulator-fixed"; + regulator-name = "vcc_syson"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc_sysin>; + }; + + vcca_1v8: regulator-vcca-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdda_0v9: regulator-vdda-0v9 { + compatible = "regulator-fixed"; + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + vin-supply = <&vcc3v3_sys>; + }; + + vdd_gpu: regulator-vdd-gpu { + compatible = "pwm-regulator"; + pwms = <&pwm2 0 5000 1>; + pwm-supply = <&vcc_syson>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-settling-time-up-us = <250>; + }; + + vdd_logic: regulator-vdd-logic { + compatible = "pwm-regulator"; + pwms = <&pwm1 0 5000 1>; + pwm-supply = <&vcc_syson>; + regulator-name = "vdd_logic"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-settling-time-up-us = <250>; + }; + + rfkill-modem { + compatible = "rfkill-gpio"; + label = "M.2 USB Modem"; + radio-type = "wwan"; + shutdown-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&pmucru CLK_RTC_32K>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_reg_on_h &clk32k_out1>; + post-power-on-delay-ms = <200>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + +&combphy2 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +/* Motorcomm YT8521SC LAN port (require SGMII) */ +&gmac0 { + status = "disabled"; +}; + +/* Motorcomm YT8521SC WAN port */ +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + avdd-0v9-supply = <&vdda_0v9>; + avdd-1v8-supply = <&vcca_1v8>; + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdmi_sound { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc_syson>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + +&i2s0_8ch { + status = "okay"; +}; + +&mdio1 { + rgmii_phy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>; + rx-internal-delay-ps = <1500>; + tx-internal-delay-ps = <1500>; + }; +}; + +&pcie30phy { + status = "okay"; +}; + +/* M.2 E-Key for PCIe WLAN */ +&pcie3x2 { + max-link-speed = <1>; + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie30x1m0_pins>; + reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie>; + status = "okay"; +}; + +&pinctrl { + bt { + bt_reg_on_h: bt-reg-on-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc0 { + sdmmc0_pwren: sdmmc0-pwren { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + rf_pwr_en: rf-pwr-en { + rockchip,pins = <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_host_pwren_h: usb-host-pwren-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + wifi { + wifi_reg_on_h: wifi-reg-on-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc_3v3>; + pmuio2-supply = <&vcc_3v3>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vcc_3v3>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +/* eMMC */ +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +/* Micro SD card slot */ +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; + disable-wp; + no-1-8-v; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +/* Qualcomm Atheros QCA9377 WiFi */ +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + wifi: wifi@1 { + reg = <1>; + interrupt-parent = <&gpio2>; + interrupts = ; + interrupt-names = "host-wake"; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +/* Qualcomm Atheros QCA9377 Bluetooth */ +&uart1 { + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "qcom,qca9377-bt"; + clocks = <&pmucru CLK_RTC_32K>; + enable-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_reg_on_h>; + vddio-supply = <&vcc_1v8>; + }; +}; + +/* Debug UART */ +&uart2 { + status = "okay"; +}; + +&uart3 { + dma-names = "tx", "rx"; + status = "okay"; +}; + +/* Onboard power management MCU */ +&uart4 { + dma-names = "tx", "rx"; + status = "okay"; +}; + +/* M.2 E-Key for USB Bluetooth */ +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +/* USB Type-A Port */ +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +/* M.2 B-Key for USB Modem WWAN */ +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc3v4_rf>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb30_otg0>; + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb30_otg0>; + status = "okay"; +}; + +&vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; + +&xin32k { + pinctrl-names = "default"; + pinctrl-0 = <&clk32k_out1>; +}; diff --git a/src/arm64/rockchip/rk3568-qnap-ts433.dts b/src/arm64/rockchip/rk3568-qnap-ts433.dts index 7bd32d230ad..b80d628c426 100644 --- a/src/arm64/rockchip/rk3568-qnap-ts433.dts +++ b/src/arm64/rockchip/rk3568-qnap-ts433.dts @@ -619,6 +619,8 @@ bus-width = <8>; max-frequency = <200000000>; non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; status = "okay"; }; diff --git a/src/arm64/rockchip/rk3568-rock-3a.dts b/src/arm64/rockchip/rk3568-rock-3a.dts index ac79140a9ec..44cfdfeed66 100644 --- a/src/arm64/rockchip/rk3568-rock-3a.dts +++ b/src/arm64/rockchip/rk3568-rock-3a.dts @@ -778,20 +778,6 @@ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; uart-has-rtscts; status = "okay"; - - bluetooth { - compatible = "brcm,bcm43438-bt"; - clocks = <&rk809 1>; - clock-names = "lpo"; - device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; - host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; - shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>; - vbat-supply = <&vcc3v3_sys>; - vddio-supply = <&vcc_1v8>; - /* vddio comes from regulator on module, use IO bank voltage instead */ - }; }; &uart2 { diff --git a/src/arm64/rockchip/rk356x-base.dtsi b/src/arm64/rockchip/rk356x-base.dtsi index e5539062911..fd2214b6fad 100644 --- a/src/arm64/rockchip/rk356x-base.dtsi +++ b/src/arm64/rockchip/rk356x-base.dtsi @@ -174,6 +174,18 @@ method = "smc"; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scmi_shmem: shmem@10f000 { + compatible = "arm,scmi-shmem"; + reg = <0x0 0x0010f000 0x0 0x100>; + no-map; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -199,19 +211,6 @@ #clock-cells = <0>; }; - sram@10f000 { - compatible = "mmio-sram"; - reg = <0x0 0x0010f000 0x0 0x100>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0x0010f000 0x100>; - - scmi_shmem: sram@0 { - compatible = "arm,scmi-shmem"; - reg = <0x0 0x100>; - }; - }; - sata1: sata@fc400000 { compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; reg = <0 0xfc400000 0 0x1000>; @@ -284,6 +283,18 @@ mbi-alias = <0x0 0xfd410000>; mbi-ranges = <296 24>; msi-controller; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dma-noncoherent; + + its: msi-controller@fd440000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0xfd440000 0 0x20000>; + dma-noncoherent; + msi-controller; + #msi-cells = <1>; + }; }; usb_host0_ehci: usb@fd800000 { @@ -957,7 +968,7 @@ num-ib-windows = <6>; num-ob-windows = <2>; max-link-speed = <2>; - msi-map = <0x0 &gic 0x0 0x1000>; + msi-map = <0x0 &its 0x0 0x1000>; num-lanes = <1>; phys = <&combphy2 PHY_TYPE_PCIE>; phy-names = "pcie-phy"; @@ -1032,6 +1043,11 @@ status = "disabled"; }; + /* + * Testing showed that the HWRNG found in RK3566 produces unacceptably + * low quality of random data, so the HWRNG isn't enabled for all RK356x + * SoC variants despite its presence. + */ rng: rng@fe388000 { compatible = "rockchip,rk3568-rng"; reg = <0x0 0xfe388000 0x0 0x4000>; diff --git a/src/arm64/rockchip/rk3576-armsom-sige5.dts b/src/arm64/rockchip/rk3576-armsom-sige5.dts index 7c7331936a7..314067ba6f3 100644 --- a/src/arm64/rockchip/rk3576-armsom-sige5.dts +++ b/src/arm64/rockchip/rk3576-armsom-sige5.dts @@ -10,6 +10,7 @@ #include #include #include +#include #include #include "rk3576.dtsi" @@ -26,6 +27,17 @@ stdout-path = "serial0:1500000n8"; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds: leds { compatible = "gpio-leds"; @@ -182,8 +194,7 @@ ð0m0_tx_bus2 ð0m0_rx_bus2 ð0m0_rgmii_clk - ð0m0_rgmii_bus - ðm0_clk0_25m_out>; + ð0m0_rgmii_bus>; phy-handle = <&rgmii_phy0>; status = "okay"; @@ -214,6 +225,26 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -579,7 +610,7 @@ reg = <0x51>; clock-output-names = "hym8563"; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&hym8563_int>; wakeup-source; @@ -656,3 +687,18 @@ pinctrl-0 = <&uart0m0_xfer>; status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/src/arm64/rockchip/rk3576-evb1-v10.dts b/src/arm64/rockchip/rk3576-evb1-v10.dts index 782ca000a64..e368691fd28 100644 --- a/src/arm64/rockchip/rk3576-evb1-v10.dts +++ b/src/arm64/rockchip/rk3576-evb1-v10.dts @@ -10,6 +10,7 @@ #include #include #include +#include #include "rk3576.dtsi" / { @@ -57,6 +58,17 @@ }; }; + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + leds: leds { compatible = "gpio-leds"; @@ -270,6 +282,26 @@ status = "okay"; }; +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + &i2c1 { status = "okay"; @@ -729,3 +761,18 @@ dr_mode = "host"; status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/src/arm64/rockchip/rk3576-roc-pc.dts b/src/arm64/rockchip/rk3576-roc-pc.dts new file mode 100644 index 00000000000..612b7bb0b74 --- /dev/null +++ b/src/arm64/rockchip/rk3576-roc-pc.dts @@ -0,0 +1,736 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Firefly Technology Co. Ltd + * Copyright (c) 2024 Heiko Stuebner + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "rk3576.dtsi" + +/ { + model = "Firefly ROC-RK3576-PC"; + compatible = "firefly,roc-rk3576-pc", "rockchip,rk3576"; + + aliases { + mmc0 = &sdhci; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + adc-keys-0 { + compatible = "adc-keys"; + io-channels = <&saradc 0>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-maskrom { + label = "Maskrom"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + adc-keys-1 { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + poll-interval = <100>; + + button-recovery { + label = "Recovery"; + linux,code = ; + press-threshold-microvolt = <17000>; + }; + }; + + vbus5v0_typec: regulator-vbus5v0-typec { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_otg0_pwren_h>; + regulator-name = "vbus5v0_typec"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_device_s0>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc1v2_ufs_vccq_s0: regulator-vcc1v2-ufs-vccq-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v2_ufs_vccq_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8_ufs_vccq2_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc3v3_pcie: regulator-vcc3v3-pcie { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren_h>; + regulator-name = "vcc3v3_pcie"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <5000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc3v3_rtc_s5: regulator-vcc3v3-rtc-s5 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_rtc_s5"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc5v0_device_s0: regulator-vcc5v0-device-s0 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5vd_en>; + regulator-name = "vcc5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys_s5: regulator-vcc5v0-sys-s5 { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb20_host1: regulator-vcc5v0-usb20-host1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb3_host_pwren_h>; + regulator-name = "vcc5v0_host1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_device_s0>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v8_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + vin-supply = <&vcc5v0_sys_s5>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_ufs_s0: regulator-vcc-ufs-s0 { + compatible = "regulator-fixed"; + regulator-name = "vcc_ufs_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys_s5>; + }; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&gmac0 { + clock_in_out = "output"; + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + /* Use rgmii-rxid mode to disable rx delay inside Soc */ + phy-mode = "rgmii-rxid"; + phy-handle = <&rgmii_phy0>; + tx_delay = <0x21>; + status = "okay"; +}; + +&mdio0 { + status = "okay"; + + rgmii_phy0: phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + /* Reset time is 20ms, 100ms for rtl8211f */ + reset-delay-us = <20000>; + reset-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <100000>; + }; +}; + +&i2c1 { + status = "okay"; + + pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys_s5>; + vcc2-supply = <&vcc5v0_sys_s5>; + vcc3-supply = <&vcc5v0_sys_s5>; + vcc4-supply = <&vcc5v0_sys_s5>; + vcc5-supply = <&vcc5v0_sys_s5>; + vcc6-supply = <&vcc5v0_sys_s5>; + vcc7-supply = <&vcc5v0_sys_s5>; + vcc8-supply = <&vcc5v0_sys_s5>; + vcc9-supply = <&vcc5v0_sys_s5>; + vcc10-supply = <&vcc5v0_sys_s5>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys_s5>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys_s5>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_big_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_npu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + /* pc9202 watchdog@3c with enable-gpio gpio0-c3 */ + + /* hnyetek,husb311 typec-portc@4e */ + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int_l>; + interrupt-parent = <&gpio0>; + interrupts = ; + wakeup-source; + }; +}; + +&saradc { + vref-supply = <&vcca_1v8_s0>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <200000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&sdmmc { + max-frequency = <200000000>; + no-sdio; + no-mmc; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + +&pinctrl { + hym8563 { + rtc_int_l: rtc-int-l { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + power { + vcc5vd_en: vcc5vd-en { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pcie_pwren_h: pcie-pwren-h { + rockchip,pins = <2 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + hub_reset_h: hub-reset-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb3_host_pwren_h: usb3-host-pwren-h { + rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usb_otg0_pwren_h: usb-otg0-pwren-h { + rockchip,pins = <0 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbc0_int_l: usbc0-int-l { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + watchdog { + wd_en: wd-en { + rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4m1_xfer &uart4m1_ctsn>; + status = "okay"; +}; + +/* On the extension pin header */ +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&uart6m3_xfer>; + status = "okay"; +}; diff --git a/src/arm64/rockchip/rk3576-rock-4d.dts b/src/arm64/rockchip/rk3576-rock-4d.dts new file mode 100644 index 00000000000..6756403111e --- /dev/null +++ b/src/arm64/rockchip/rk3576-rock-4d.dts @@ -0,0 +1,751 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "rk3576.dtsi" + +/ { + model = "Radxa ROCK 4D"; + compatible = "radxa,rock-4d", "rockchip,rk3576"; + + aliases { + ethernet0 = &gmac0; + mmc0 = &sdmmc; + }; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + hdmi-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con_in: endpoint { + remote-endpoint = <&hdmi_out_con>; + }; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_rgb_g &led_rgb_r>; + + power-led { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + user-led { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + vcc_12v0_dcin: regulator-vcc-12v0-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc_12v0_dcin"; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vcc_1v1_nldo_s3"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_1v2_ufs_vccq_s0: regulator-vcc-1v2-ufs-vccq-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc_1v2_ufs_vccq_s0"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_1v8_ufs_vccq2_s0: regulator-vcc-1v8-ufs-vccq2-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_ufs_vccq2_s0"; + vin-supply = <&vcc_1v8_s3>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vcc_2v0_pldo_s3"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_pcie: regulator-vcc-3v3-pcie { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pwren>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_pcie"; + startup-delay-us = <5000>; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_rtc_s5: regulator-vcc-3v3-rtc-s5 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_rtc_s5"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + vin-supply = <&vcc_3v3_s3>; + }; + + vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_ufs_s0"; + vin-supply = <&vcc_5v0_sys>; + }; + + vcc_5v0_device: regulator-vcc-5v0-device { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc_5v0_device"; + vin-supply = <&vcc_12v0_dcin>; + }; + + vcc_5v0_host: regulator-vcc-5v0-host { + compatible = "regulator-fixed"; + enable-active-high; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_host_pwren>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_host"; + vin-supply = <&vcc_5v0_device>; + }; + + vcc_5v0_sys: regulator-vcc-5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc_5v0_sys"; + vin-supply = <&vcc_12v0_dcin>; + }; +}; + +&combphy1_psu { + status = "okay"; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&hdmi_in { + hdmi_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi>; + }; +}; + +&hdmi_out { + hdmi_out_con: endpoint { + remote-endpoint = <&hdmi_con_in>; + }; +}; + +&hdptxphy { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + pmic@23 { + compatible = "rockchip,rk806"; + reg = <0x23>; + #gpio-cells = <2>; + gpio-controller; + interrupt-parent = <&gpio0>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins + &rk806_dvs1_null + &rk806_dvs2_null + &rk806_dvs3_null>; + system-power-controller; + vcc1-supply = <&vcc_5v0_sys>; + vcc2-supply = <&vcc_5v0_sys>; + vcc3-supply = <&vcc_5v0_sys>; + vcc4-supply = <&vcc_5v0_sys>; + vcc5-supply = <&vcc_5v0_sys>; + vcc6-supply = <&vcc_5v0_sys>; + vcc7-supply = <&vcc_5v0_sys>; + vcc8-supply = <&vcc_5v0_sys>; + vcc9-supply = <&vcc_5v0_sys>; + vcc10-supply = <&vcc_5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc_5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc_5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun3"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun1"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun5"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun1"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun5"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun3"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun1"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_big_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_cpu_lit_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-enable-ramp-delay = <400>; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd_gpu_s0"; + regulator-ramp-delay = <12500>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-name = "vdd_logic_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <837500>; + regulator-max-microvolt = <837500>; + regulator-name = "vdda0v75_hdmi_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdda_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "hym8563"; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&hym8563_int>; + wakeup-source; + }; +}; + +&mdio0 { + rgmii_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + clocks = <&cru REFCLKO25M_GMAC0_OUT>; + pinctrl-names = "default"; + pinctrl-0 = <&rtl8211f_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_rgb_g: led-green-en { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_rgb_r: led-red-en { + rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + rtl8211f { + rtl8211f_rst: rtl8211f-rst { + rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie { + pcie_pwren: pcie-pwren { + rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply = <&vcc_3v3_s3>; + vqmmc-supply = <&vccio_sd_s0>; + status = "okay"; +}; + + +&sfc0 { + pinctrl-names = "default"; + pinctrl-0 = <&fspi0_pins &fspi0_csn0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + vcc-supply = <&vcc_1v8_s3>; + }; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0m0_xfer>; + status = "okay"; +}; + +&usb_drd1_dwc3 { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi_in_vp0>; + }; +}; diff --git a/src/arm64/rockchip/rk3576.dtsi b/src/arm64/rockchip/rk3576.dtsi index 4dde954043e..ebb5fc8bb8b 100644 --- a/src/arm64/rockchip/rk3576.dtsi +++ b/src/arm64/rockchip/rk3576.dtsi @@ -111,7 +111,7 @@ reg = <0x0>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; #cooling-cells = <2>; dynamic-power-coefficient = <120>; @@ -124,7 +124,7 @@ reg = <0x1>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -135,7 +135,7 @@ reg = <0x2>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -146,7 +146,7 @@ reg = <0x3>; enable-method = "psci"; capacity-dmips-mhz = <485>; - clocks = <&scmi_clk ARMCLK_L>; + clocks = <&scmi_clk SCMI_ARMCLK_L>; operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -157,7 +157,7 @@ reg = <0x100>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; #cooling-cells = <2>; dynamic-power-coefficient = <320>; @@ -170,7 +170,7 @@ reg = <0x101>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -181,7 +181,7 @@ reg = <0x102>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -192,7 +192,7 @@ reg = <0x103>; enable-method = "psci"; capacity-dmips-mhz = <1024>; - clocks = <&scmi_clk ARMCLK_B>; + clocks = <&scmi_clk SCMI_ARMCLK_B>; operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; }; @@ -393,6 +393,11 @@ }; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + firmware { scmi: scmi { compatible = "arm,scmi-smc"; @@ -620,6 +625,11 @@ }; }; + hdptxphy_grf: syscon@26032000 { + compatible = "rockchip,rk3576-hdptxphy-grf", "syscon"; + reg = <0x0 0x26032000 0x0 0x100>; + }; + vo1_grf: syscon@26036000 { compatible = "rockchip,rk3576-vo1-grf", "syscon"; reg = <0x0 0x26036000 0x0 0x100>; @@ -922,7 +932,7 @@ gpu: gpu@27800000 { compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; reg = <0x0 0x27800000 0x0 0x200000>; - assigned-clocks = <&scmi_clk CLK_GPU>; + assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; assigned-clock-rates = <198000000>; clocks = <&cru CLK_GPU>; clock-names = "core"; @@ -937,6 +947,109 @@ status = "disabled"; }; + vop: vop@27d00000 { + compatible = "rockchip,rk3576-vop"; + reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>; + reg-names = "vop", "gamma-lut"; + interrupts = , + , + , + ; + interrupt-names = "sys", + "vp0", + "vp1", + "vp2"; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VP0>, + <&cru DCLK_VP1>, + <&cru DCLK_VP2>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2"; + iommus = <&vop_mmu>; + power-domains = <&power RK3576_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,pmu = <&pmu>; + status = "disabled"; + + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + }; + }; + + vop_mmu: iommu@27d07e00 { + compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0x27d07e00 0x0 0x100>, <0x0 0x27d07f00 0x0 0x100>; + interrupts = ; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3576_PD_VOP>; + status = "disabled"; + }; + + hdmi: hdmi@27da0000 { + compatible = "rockchip,rk3576-dw-hdmi-qp"; + reg = <0x0 0x27da0000 0x0 0x20000>; + clocks = <&cru PCLK_HDMITX0>, + <&cru CLK_HDMITX0_EARC>, + <&cru CLK_HDMITX0_REF>, + <&cru MCLK_SAI6_8CH>, + <&cru CLK_HDMITXHDP>, + <&cru HCLK_VO0_ROOT>; + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts = , + , + , + , + ; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; + phys = <&hdptxphy>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_txm0_pins &hdmi_tx_scl &hdmi_tx_sda>; + power-domains = <&power RK3576_PD_VO0>; + resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMITXHDP>; + reset-names = "ref", "hdp"; + rockchip,grf = <&ioc_grf>; + rockchip,vo-grf = <&vo0_grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi_in: port@0 { + reg = <0>; + }; + + hdmi_out: port@1 { + reg = <1>; + }; + }; + }; + qos_hdcp1: qos@27f02000 { compatible = "rockchip,rk3576-qos", "syscon"; reg = <0x0 0x27f02000 0x0 0x20>; @@ -1221,6 +1334,41 @@ }; }; + ufshc: ufshc@2a2d0000 { + compatible = "rockchip,rk3576-ufshc"; + reg = <0x0 0x2a2d0000 0x0 0x10000>, + <0x0 0x2b040000 0x0 0x10000>, + <0x0 0x2601f000 0x0 0x1000>, + <0x0 0x2603c000 0x0 0x1000>, + <0x0 0x2a2e0000 0x0 0x10000>; + reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; + clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, + <&cru CLK_REF_UFS_CLKOUT>; + clock-names = "core", "pclk", "pclk_mphy", "ref_out"; + assigned-clocks = <&cru CLK_REF_OSC_MPHY>; + assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; + interrupts = ; + power-domains = <&power RK3576_PD_USB>; + pinctrl-0 = <&ufs_refclk>; + pinctrl-names = "default"; + resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, + <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; + reset-names = "biu", "sys", "ufs", "grf"; + reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + sfc1: spi@2a300000 { + compatible = "rockchip,sfc"; + reg = <0x0 0x2a300000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sdmmc: mmc@2a310000 { compatible = "rockchip,rk3576-dw-mshc"; reg = <0x0 0x2a310000 0x0 0x4000>; @@ -1260,6 +1408,56 @@ status = "disabled"; }; + sfc0: spi@2a340000 { + compatible = "rockchip,sfc"; + reg = <0x0 0x2a340000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_FSPI_X2>, <&cru HCLK_FSPI>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + otp: otp@2a580000 { + compatible = "rockchip,rk3576-otp"; + reg = <0x0 0x2a580000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, + <&cru CLK_OTP_PHY_G>; + clock-names = "otp", "apb_pclk", "phy"; + resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>; + reset-names = "otp", "apb"; + + /* Data cells */ + cpu_code: cpu-code@2 { + reg = <0x02 0x2>; + }; + otp_cpu_version: cpu-version@5 { + reg = <0x05 0x1>; + bits = <3 3>; + }; + otp_id: id@a { + reg = <0x0a 0x10>; + }; + cpub_leakage: cpub-leakage@1e { + reg = <0x1e 0x1>; + }; + cpul_leakage: cpul-leakage@1f { + reg = <0x1f 0x1>; + }; + npu_leakage: npu-leakage@20 { + reg = <0x20 0x1>; + }; + gpu_leakage: gpu-leakage@21 { + reg = <0x21 0x1>; + }; + log_leakage: log-leakage@22 { + reg = <0x22 0x1>; + }; + }; + gic: interrupt-controller@2a701000 { compatible = "arm,gic-400"; reg = <0x0 0x2a701000 0 0x10000>, @@ -1756,6 +1954,19 @@ status = "disabled"; }; + hdptxphy: hdmiphy@2b000000 { + compatible = "rockchip,rk3576-hdptx-phy", "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0x2b000000 0x0 0x2000>; + clocks = <&cru CLK_PHY_REF_SRC>, <&cru PCLK_HDPTX_APB>; + clock-names = "ref", "apb"; + resets = <&cru SRST_P_HDPTX_APB>, <&cru SRST_HDPTX_INIT>, + <&cru SRST_HDPTX_CMN>, <&cru SRST_HDPTX_LANE>; + reset-names = "apb", "init", "cmn", "lane"; + rockchip,grf = <&hdptxphy_grf>; + #phy-cells = <0>; + status = "disabled"; + }; + sram: sram@3ff88000 { compatible = "mmio-sram"; reg = <0x0 0x3ff88000 0x0 0x78000>; diff --git a/src/arm64/rockchip/rk3588-armsom-lm7.dtsi b/src/arm64/rockchip/rk3588-armsom-lm7.dtsi index a3138d2d384..e44125e9a8f 100644 --- a/src/arm64/rockchip/rk3588-armsom-lm7.dtsi +++ b/src/arm64/rockchip/rk3588-armsom-lm7.dtsi @@ -114,6 +114,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &saradc { vref-supply = <&avcc_1v8_s0>; status = "okay"; diff --git a/src/arm64/rockchip/rk3588-armsom-sige7.dts b/src/arm64/rockchip/rk3588-armsom-sige7.dts index 08f09053a06..ae9274365be 100644 --- a/src/arm64/rockchip/rk3588-armsom-sige7.dts +++ b/src/arm64/rockchip/rk3588-armsom-sige7.dts @@ -4,6 +4,7 @@ #include #include +#include #include "rk3588.dtsi" / { @@ -33,6 +34,17 @@ "Headphone", "Headphones"; }; + hdmi0-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi0_con_in: endpoint { + remote-endpoint = <&hdmi0_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -164,6 +176,30 @@ status = "okay"; }; +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi0>; + }; +}; + +&hdmi0_out { + hdmi0_out_con: endpoint { + remote-endpoint = <&hdmi0_con_in>; + }; +}; + +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -258,6 +294,10 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + /* phy1 - right ethernet port */ &pcie2x1l0 { reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; @@ -268,6 +308,22 @@ &pcie2x1l1 { reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; status = "okay"; + + pcie@0,0 { + reg = <0x300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x30 0x3f>; + + wifi: wifi@0,0 { + compatible = "pci14e4,449d"; + reg = <0x310000 0 0 0 0>; + clocks = <&hym8563>; + clock-names = "lpo"; + }; + }; }; /* phy0 - left ethernet port */ @@ -286,6 +342,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -723,3 +783,18 @@ dr_mode = "host"; status = "okay"; }; + +&vop_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp0>; + }; +}; diff --git a/src/arm64/rockchip/rk3588-base.dtsi b/src/arm64/rockchip/rk3588-base.dtsi index c3abdfb04f8..1e18ad93ba0 100644 --- a/src/arm64/rockchip/rk3588-base.dtsi +++ b/src/arm64/rockchip/rk3588-base.dtsi @@ -358,11 +358,6 @@ }; firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - scmi: scmi { compatible = "arm,scmi-smc"; arm,smc-id = <0x82000010>; @@ -382,6 +377,22 @@ }; }; + hdmi0_sound: hdmi0-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "hdmi0"; + status = "disabled"; + + simple-audio-card,codec { + sound-dai = <&hdmi0>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s5_8ch>; + }; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupts = ; @@ -864,7 +875,7 @@ }; }; /* These power domains are grouped by VD_GPU */ - power-domain@RK3588_PD_GPU { + pd_gpu: power-domain@RK3588_PD_GPU { reg = ; clocks = <&cru CLK_GPU>, <&cru CLK_GPU_COREGROUP>, @@ -1261,14 +1272,16 @@ <&cru DCLK_VOP1>, <&cru DCLK_VOP2>, <&cru DCLK_VOP3>, - <&cru PCLK_VOP_ROOT>; + <&cru PCLK_VOP_ROOT>, + <&hdptxphy0>; clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2", "dclk_vp3", - "pclk_vop"; + "pclk_vop", + "pll_hdmiphy0"; iommus = <&vop_mmu>; power-domains = <&power RK3588_PD_VOP>; rockchip,grf = <&sys_grf>; @@ -1318,6 +1331,21 @@ status = "disabled"; }; + spdif_tx2: spdif-tx@fddb0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>; + dma-names = "tx"; + dmas = <&dmac1 6>; + interrupts = ; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s4_8ch: i2s@fddc0000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc0000 0x0 0x1000>; @@ -1335,6 +1363,21 @@ status = "disabled"; }; + spdif_tx3: spdif-tx@fdde0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF3_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; + dma-names = "tx"; + dmas = <&dmac1 7>; + interrupts = ; + power-domains = <&power RK3588_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s5_8ch: i2s@fddf0000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddf0000 0x0 0x1000>; @@ -1385,7 +1428,7 @@ , ; interrupt-names = "avp", "cec", "earc", "main", "hpd"; - phys = <&hdptxphy_hdmi0>; + phys = <&hdptxphy0>; pinctrl-names = "default"; pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; @@ -1394,6 +1437,7 @@ reset-names = "ref", "hdp"; rockchip,grf = <&sys_grf>; rockchip,vo-grf = <&vo1_grf>; + #sound-dai-cells = <0>; status = "disabled"; ports { @@ -1921,6 +1965,14 @@ status = "disabled"; }; + rng@fe378000 { + compatible = "rockchip,rk3588-rng"; + reg = <0x0 0xfe378000 0x0 0x200>; + interrupts = ; + clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; + resets = <&scmi_reset 48>; + }; + i2s0_8ch: i2s@fe470000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfe470000 0x0 0x1000>; @@ -2016,12 +2068,47 @@ status = "disabled"; }; + spdif_tx0: spdif-tx@fe4e0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4e0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF0_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; + dma-names = "tx"; + dmas = <&dmac0 5>; + interrupts = ; + pinctrl-0 = <&spdif0m0_tx>; + pinctrl-names = "default"; + power-domains = <&power RK3588_PD_AUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif_tx1: spdif-tx@fe4f0000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfe4f0000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF1_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; + dma-names = "tx"; + dmas = <&dmac1 5>; + interrupts = ; + pinctrl-0 = <&spdif1m0_tx>; + pinctrl-names = "default"; + power-domains = <&power RK3588_PD_AUDIO>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@fe600000 { compatible = "arm,gic-v3"; reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ <0x0 0xfe680000 0 0x100000>; /* GICR */ interrupts = ; interrupt-controller; + dma-noncoherent; mbi-alias = <0x0 0xfe610000>; mbi-ranges = <424 56>; msi-controller; @@ -2033,6 +2120,7 @@ its0: msi-controller@fe640000 { compatible = "arm,gic-v3-its"; reg = <0x0 0xfe640000 0x0 0x20000>; + dma-noncoherent; msi-controller; #msi-cells = <1>; }; @@ -2040,6 +2128,7 @@ its1: msi-controller@fe660000 { compatible = "arm,gic-v3-its"; reg = <0x0 0xfe660000 0x0 0x20000>; + dma-noncoherent; msi-controller; #msi-cells = <1>; }; @@ -2807,11 +2896,12 @@ #dma-cells = <1>; }; - hdptxphy_hdmi0: phy@fed60000 { + hdptxphy0: phy@fed60000 { compatible = "rockchip,rk3588-hdptx-phy"; reg = <0x0 0xfed60000 0x0 0x2000>; clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; clock-names = "ref", "apb"; + #clock-cells = <0>; #phy-cells = <0>; resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, diff --git a/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts b/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts index 9d525c8ff72..9eda6972266 100644 --- a/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts +++ b/src/arm64/rockchip/rk3588-coolpi-cm5-evb.dts @@ -129,7 +129,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts b/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts index bc6b43a7715..6dc10da5215 100644 --- a/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts +++ b/src/arm64/rockchip/rk3588-coolpi-cm5-genbook.dts @@ -166,7 +166,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi b/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi index 71ed680621b..cc37f082ade 100644 --- a/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi +++ b/src/arm64/rockchip/rk3588-coolpi-cm5.dtsi @@ -277,6 +277,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi b/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi index 5e72d0eff0e..8a783dc64c0 100644 --- a/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi +++ b/src/arm64/rockchip/rk3588-edgeble-neu6a-common.dtsi @@ -126,6 +126,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { led_user_en: led_user_en { diff --git a/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi b/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi index 7125790bbed..08920344a4b 100644 --- a/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi +++ b/src/arm64/rockchip/rk3588-edgeble-neu6a-io.dtsi @@ -4,12 +4,24 @@ */ #include +#include / { chosen { stdout-path = "serial2:1500000n8"; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { compatible = "gated-fixed-clock"; @@ -81,6 +93,26 @@ status = "okay"; }; +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdptxphy1 { + status = "okay"; +}; + &i2c6 { status = "okay"; @@ -275,3 +307,18 @@ &usb_host2_xhci { status = "okay"; }; + +&vop_mmu { + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vp0 { + vp0_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp0>; + }; +}; diff --git a/src/arm64/rockchip/rk3588-evb1-v10.dts b/src/arm64/rockchip/rk3588-evb1-v10.dts index ba49f0bbaac..8e912da299a 100644 --- a/src/arm64/rockchip/rk3588-evb1-v10.dts +++ b/src/arm64/rockchip/rk3588-evb1-v10.dts @@ -132,6 +132,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + pcie20_avdd0v85: regulator-pcie20-avdd0v85 { compatible = "regulator-fixed"; regulator-name = "pcie20_avdd0v85"; @@ -364,7 +375,27 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { status = "okay"; }; @@ -441,7 +472,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -519,6 +550,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { audio { hp_detect: headphone-detect { @@ -1371,11 +1406,11 @@ status = "okay"; }; -&vop_mmu { +&vop { status = "okay"; }; -&vop { +&vop_mmu { status = "okay"; }; @@ -1385,3 +1420,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/src/arm64/rockchip/rk3588-extra.dtsi b/src/arm64/rockchip/rk3588-extra.dtsi index 840b638af1c..099edb3fd0f 100644 --- a/src/arm64/rockchip/rk3588-extra.dtsi +++ b/src/arm64/rockchip/rk3588-extra.dtsi @@ -7,6 +7,46 @@ #include "rk3588-extra-pinctrl.dtsi" / { + hdmi1_sound: hdmi1-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <128>; + simple-audio-card,name = "hdmi1"; + status = "disabled"; + + simple-audio-card,codec { + sound-dai = <&hdmi1>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s6_8ch>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * The 4k HDMI capture controller works only with 32bit + * phys addresses and doesn't support IOMMU. HDMI RX CMA + * must be reserved below 4GB. + * The size of 160MB was determined as follows: + * (3840 * 2160 pixels) * (4 bytes/pixel) * (2 frames/buffer) / 10^6 = 66MB + * To ensure sufficient support for practical use-cases, + * we doubled the 66MB value. + */ + hdmi_receiver_cma: hdmi-receiver-cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x0 0x0 0xffffffff>; + size = <0x0 (160 * 0x100000)>; /* 160MiB */ + alignment = <0x0 0x40000>; /* 64K */ + no-map; + status = "disabled"; + }; + }; + usb_host1_xhci: usb@fc400000 { compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; reg = <0x0 0xfc400000 0x0 0x400000>; @@ -67,6 +107,26 @@ }; }; + hdptxphy1_grf: syscon@fd5e4000 { + compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; + reg = <0x0 0xfd5e4000 0x0 0x100>; + }; + + spdif_tx5: spdif-tx@fddb8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfddb8000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>; + dma-names = "tx"; + dmas = <&dmac1 22>; + interrupts = ; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s8_8ch: i2s@fddc8000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddc8000 0x0 0x1000>; @@ -84,6 +144,21 @@ status = "disabled"; }; + spdif_tx4: spdif-tx@fdde8000 { + compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; + reg = <0x0 0xfdde8000 0x0 0x1000>; + assigned-clock-parents = <&cru PLL_AUPLL>; + assigned-clocks = <&cru CLK_SPDIF4_SRC>; + clock-names = "mclk", "hclk"; + clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; + dma-names = "tx"; + dmas = <&dmac1 8>; + interrupts = ; + power-domains = <&power RK3588_PD_VO1>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + i2s6_8ch: i2s@fddf4000 { compatible = "rockchip,rk3588-i2s-tdm"; reg = <0x0 0xfddf4000 0x0 0x1000>; @@ -135,6 +210,79 @@ status = "disabled"; }; + hdmi1: hdmi@fdea0000 { + compatible = "rockchip,rk3588-dw-hdmi-qp"; + reg = <0x0 0xfdea0000 0x0 0x20000>; + clocks = <&cru PCLK_HDMITX1>, + <&cru CLK_HDMITX1_EARC>, + <&cru CLK_HDMITX1_REF>, + <&cru MCLK_I2S6_8CH_TX>, + <&cru CLK_HDMIHDP1>, + <&cru HCLK_VO1>; + clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1"; + interrupts = , + , + , + , + ; + interrupt-names = "avp", "cec", "earc", "main", "hpd"; + phys = <&hdptxphy1>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; + reset-names = "ref", "hdp"; + rockchip,grf = <&sys_grf>; + rockchip,vo-grf = <&vo1_grf>; + #sound-dai-cells = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + hdmi1_in: port@0 { + reg = <0>; + }; + + hdmi1_out: port@1 { + reg = <1>; + }; + }; + }; + + hdmi_receiver: hdmi_receiver@fdee0000 { + compatible = "rockchip,rk3588-hdmirx-ctrler", "snps,dw-hdmi-rx"; + reg = <0x0 0xfdee0000 0x0 0x6000>; + interrupts = , + , + ; + interrupt-names = "cec", "hdmi", "dma"; + clocks = <&cru ACLK_HDMIRX>, + <&cru CLK_HDMIRX_AUD>, + <&cru CLK_CR_PARA>, + <&cru PCLK_HDMIRX>, + <&cru CLK_HDMIRX_REF>, + <&cru PCLK_S_HDMIRX>, + <&cru HCLK_VO1>; + clock-names = "aclk", + "audio", + "cr_para", + "pclk", + "ref", + "hclk_s_hdmirx", + "hclk_vo1"; + memory-region = <&hdmi_receiver_cma>; + power-domains = <&power RK3588_PD_VO1>; + resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, + <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; + reset-names = "axi", "apb", "ref", "biu"; + rockchip,grf = <&sys_grf>; + rockchip,vo1-grf = <&vo1_grf>; + status = "disabled"; + }; + pcie3x4: pcie@fe150000 { compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie"; #address-cells = <3>; @@ -398,6 +546,23 @@ }; }; + hdptxphy1: phy@fed70000 { + compatible = "rockchip,rk3588-hdptx-phy"; + reg = <0x0 0xfed70000 0x0 0x2000>; + clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; + clock-names = "ref", "apb"; + #clock-cells = <0>; + #phy-cells = <0>; + resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, + <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, + <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, + <&cru SRST_HDPTX1_LCPLL>; + reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", + "lcpll"; + rockchip,grf = <&hdptxphy1_grf>; + status = "disabled"; + }; + usbdp_phy1: phy@fed90000 { compatible = "rockchip,rk3588-usbdp-phy"; reg = <0x0 0xfed90000 0x0 0x10000>; @@ -449,3 +614,24 @@ status = "disabled"; }; }; + +&vop { + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>, + <&hdptxphy0>, + <&hdptxphy1>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop", + "pll_hdmiphy0", + "pll_hdmiphy1"; +}; diff --git a/src/arm64/rockchip/rk3588-fet3588-c.dtsi b/src/arm64/rockchip/rk3588-fet3588-c.dtsi index 39005131738..4331cdc70f9 100644 --- a/src/arm64/rockchip/rk3588-fet3588-c.dtsi +++ b/src/arm64/rockchip/rk3588-fet3588-c.dtsi @@ -205,6 +205,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { led_rgb_b: led-rgb-b { diff --git a/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi b/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi index 42c523b553c..80e16ea4154 100644 --- a/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi +++ b/src/arm64/rockchip/rk3588-firefly-core-3588j.dtsi @@ -108,6 +108,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &sdhci { bus-width = <8>; no-sdio; diff --git a/src/arm64/rockchip/rk3588-firefly-icore-3588q.dtsi b/src/arm64/rockchip/rk3588-firefly-icore-3588q.dtsi new file mode 100644 index 00000000000..6726eeb4925 --- /dev/null +++ b/src/arm64/rockchip/rk3588-firefly-icore-3588q.dtsi @@ -0,0 +1,443 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +#include +#include + +#include "rk3588.dtsi" + +/ { + compatible = "firefly,icore-3588q", "rockchip,rk3588"; + + aliases { + mmc0 = &sdhci; + }; +}; + +&cpu_b0 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b1 { + cpu-supply = <&vdd_cpu_big0_s0>; +}; + +&cpu_b2 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_b3 { + cpu-supply = <&vdd_cpu_big1_s0>; +}; + +&cpu_l0 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l1 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l2 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&cpu_l3 { + cpu-supply = <&vdd_cpu_lit_s0>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0m2_xfer>; + status = "okay"; + + vdd_cpu_big0_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big0_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_big1_s0: regulator@43 { + compatible = "rockchip,rk8603", "rockchip,rk8602"; + reg = <0x43>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <1050000>; + regulator-name = "vdd_cpu_big1_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1m2_xfer>; + status = "okay"; + + vdd_npu_s0: vdd_npu_mem_s0: regulator@42 { + compatible = "rockchip,rk8602"; + reg = <0x42>; + fcs,suspend-voltage-selector = <1>; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd_npu_s0"; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; +}; + +&sdhci { + bus-width = <8>; + no-sdio; + no-sd; + non-removable; + max-frequency = <150000000>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + status = "okay"; +}; + +&spi2 { + assigned-clocks = <&cru CLK_SPI2>; + assigned-clock-rates = <200000000>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; + status = "okay"; + + pmic@0 { + compatible = "rockchip,rk806"; + reg = <0x0>; + interrupt-parent = <&gpio0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, + <&rk806_dvs2_null>, <&rk806_dvs3_null>; + spi-max-frequency = <1000000>; + system-power-controller; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc5v0_sys>; + vcc6-supply = <&vcc5v0_sys>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc5v0_sys>; + vcc9-supply = <&vcc5v0_sys>; + vcc10-supply = <&vcc5v0_sys>; + vcc11-supply = <&vcc_2v0_pldo_s3>; + vcc12-supply = <&vcc5v0_sys>; + vcc13-supply = <&vcc_1v1_nldo_s3>; + vcc14-supply = <&vcc_1v1_nldo_s3>; + vcca-supply = <&vcc5v0_sys>; + + rk806_dvs1_null: dvs1-null-pins { + pins = "gpio_pwrctrl1"; + function = "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins = "gpio_pwrctrl2"; + function = "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins = "gpio_pwrctrl3"; + function = "pin_fun0"; + }; + + regulators { + vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 { + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_gpu_s0"; + regulator-enable-ramp-delay = <400>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_cpu_lit_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_log_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <750000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_log_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_vdenc_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <12500>; + regulator-name = "vdd_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vdd2_ddr_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_2v0_pldo_s3: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-name = "vdd_2v0_pldo_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2000000>; + }; + }; + + vcc_3v3_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vddq_ddr_s0: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vddq_ddr_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avcc_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "avcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_1v8_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + avdd_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "avdd_1v2_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_3v3_s0"; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pldo6_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s3"; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <750000>; + }; + }; + + vdd_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_ddr_pll_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <850000>; + }; + }; + + avdd_0v75_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "avdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-name = "vdd_0v85_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "vdd_0v75_s0"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2m0_xfer>; + status = "okay"; +}; diff --git a/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts b/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts index 2be5251d3e3..e086114c763 100644 --- a/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts +++ b/src/arm64/rockchip/rk3588-firefly-itx-3588j.dts @@ -337,7 +337,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts b/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts index b3a04ca370b..8171fbfd819 100644 --- a/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts +++ b/src/arm64/rockchip/rk3588-friendlyelec-cm3588-nas.dts @@ -335,7 +335,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; diff --git a/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi b/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi index e3a9598b99f..af431fdcbea 100644 --- a/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi +++ b/src/arm64/rockchip/rk3588-friendlyelec-cm3588.dtsi @@ -222,6 +222,10 @@ compatible = "realtek,rt5616"; reg = <0x1b>; #sound-dai-cells = <0>; + assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; + assigned-clock-rates = <12288000>; + clocks = <&cru I2S0_8CH_MCLKOUT>; + clock-names = "mclk"; }; }; @@ -256,6 +260,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { gpio-leds { led_sys_pin: led-sys-pin { diff --git a/src/arm64/rockchip/rk3588-h96-max-v58.dts b/src/arm64/rockchip/rk3588-h96-max-v58.dts index 4791b77f357..73d8ce4fde2 100644 --- a/src/arm64/rockchip/rk3588-h96-max-v58.dts +++ b/src/arm64/rockchip/rk3588-h96-max-v58.dts @@ -140,6 +140,24 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + spdif_dit: spdif-dit { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + spdif_sound: spdif-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + + simple-audio-card,cpu { + sound-dai = <&spdif_tx0>; + }; + + simple-audio-card,codec { + sound-dai = <&spdif_dit>; + }; + }; }; &combphy0_ps { @@ -207,7 +225,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -316,6 +334,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -400,6 +422,12 @@ status = "okay"; }; +&spdif_tx0 { + pinctrl-names = "default"; + pinctrl-0 = <&spdif0m1_tx>; + status = "okay"; +}; + &spi2 { assigned-clocks = <&cru CLK_SPI2>; assigned-clock-rates = <200000000>; diff --git a/src/arm64/rockchip/rk3588-jaguar-pre-ict-tester.dtso b/src/arm64/rockchip/rk3588-jaguar-pre-ict-tester.dtso new file mode 100644 index 00000000000..9d44dfe2f30 --- /dev/null +++ b/src/arm64/rockchip/rk3588-jaguar-pre-ict-tester.dtso @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024 Cherry Embedded Solutions GmbH + * + * Device Tree Overlay for the Pre-ICT tester adapter for the Mezzanine + * connector on RK3588 Jaguar. + * + * This adapter has a PCIe Gen2 x1 M.2 M-Key connector and two proprietary + * camera connectors (each their own I2C bus, clock, reset and PWM lines as well + * as 2-lane CSI). + * + * This adapter routes some GPIOs to power rails and loops together some other + * GPIOs. + * + * This adapter is used during manufacturing for validating proper soldering of + * the mezzanine connector. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + pre_ict_tester_vcc_1v2: regulator-pre-ict-tester-vcc-1v2 { + compatible = "regulator-fixed"; + regulator-name = "pre_ict_tester_vcc_1v2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_3v3_s3>; + }; + + pre_ict_tester_vcc_2v8: regulator-pre-ict-tester-vcc-2v8 { + compatible = "regulator-fixed"; + regulator-name = "pre_ict_tester_vcc_2v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_3v3_s3>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&gpio3 { + pinctrl-0 = <&pre_ict_pwr2gpio>; + pinctrl-names = "default"; +}; + +&pcie2x1l2 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie2x1l2_perstn_m0>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; /* PCIE20X1_2_PERSTN_M0 */ + vpcie3v3-supply = <&vcc_3v3_s3>; + status = "okay"; +}; + +&pinctrl { + pcie2x1l2 { + pcie2x1l2_perstn_m0: pcie2x1l2-perstn-m0 { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pre-ict-tester { + pre_ict_pwr2gpio: pre-ict-pwr2gpio-pins { + rockchip,pins = + /* + * GPIO3_A3 requires two power rails to be properly + * routed to the mezzanine connector to report a proper + * value: VCC_1V8_S0_1 and VCC_IN_2. It may report an + * incorrect value if VCC_1V8_S0_1 isn't properly routed, + * but GPIO3_C6 would catch this HW soldering issue. + * If VCC_IN_2 is properly routed, GPIO3_A3 should be + * LOW. The signal shall not read HIGH in the event + * GPIO3_A3 isn't properly routed due to soldering + * issue. Therefore, let's enforce a pull-up (which is + * the SoC default for this pin). + */ + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + /* + * GPIO3_A4 is directly routed to VCC_1V8_S0_2 power + * rail. It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_B2 requires two power rails to be properly + * routed to the mezzanine connector to report a proper + * value: VCC_1V8_S0_1 and VCC_IN_1. It may report an + * incorrect value if VCC_1V8_S0_1 isn't properly routed, + * but GPIO3_C6 would catch this HW soldering issue. + * If VCC_IN_1 is properly routed, GPIO3_B2 should be + * LOW. This is an issue if GPIO3_B2 isn't properly + * routed due to soldering issue, because GPIO3_B2 + * default bias is pull-down therefore being LOW. So + * the worst case scenario and the pass scenario expect + * the same value. Make GPIO3_B2 a pull-up so that a + * soldering issue on GPIO3_B2 reports HIGH but proper + * soldering reports LOW. + */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + /* + * GPIO3_C6 is directly routed to VCC_1V8_S0_1 power + * rail. It should be HIGH if all is properly soldered. + * This is an issue if GPIO3_C6 or VCC_1V8_S0_1 isn't + * properly routed due to soldering issue, because + * GPIO3_C6 default bias is pull-up therefore being HIGH + * in all cases: + * - GPIO3_C6 is floating (so HIGH) if GPIO3_C6 is not + * routed properly, + * - GPIO3_C6 is floating (so HIGH) if VCC_1V8_S0_1 is + * not routed properly, + * - GPIO3_C6 is HIGH if everything is proper, + * Make GPIO3_C6 a pull-down so that a soldering issue + * on GPIO3_C6 or VCC_1V8_S0_1 reports LOW but proper + * soldering reports HIGH. + */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D2 is routed to VCC_5V0_1 power rail through a + * voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D3 is routed to VCC_5V0_2 power rail through a + * voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D4 is routed to VCC_3V3_S3_1 power rail through + * a voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D5 is routed to VCC_3V3_S3_2 power rail through + * a voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/src/arm64/rockchip/rk3588-jaguar.dts b/src/arm64/rockchip/rk3588-jaguar.dts index 7f457ab7801..9fceea6c139 100644 --- a/src/arm64/rockchip/rk3588-jaguar.dts +++ b/src/arm64/rockchip/rk3588-jaguar.dts @@ -303,7 +303,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -333,6 +333,56 @@ }; }; + typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio4>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&cc_int1>; + vbus-supply = <&vcc_5v0_usb_c1>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USBC-1 P11"; + power-role = "source"; + self-powered; + source-pdos = + ; + vbus-supply = <&vcc_5v0_usb_c1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc0_hs: endpoint { + remote-endpoint = <&usb_host0_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + + usbc0_ss: endpoint { + remote-endpoint = <&usbdp_phy0_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc0_sbu: endpoint { + remote-endpoint = <&usbdp_phy0_typec_sbu>; + }; + }; + }; + }; + }; + vdd_npu_s0: regulator@42 { compatible = "rockchip,rk8602"; reg = <0x42>; @@ -394,6 +444,56 @@ pinctrl-0 = <&i2c8m2_xfer>; status = "okay"; + typec-portc@22 { + compatible = "fcs,fusb302"; + reg = <0x22>; + interrupt-parent = <&gpio4>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&cc_int2>; + vbus-supply = <&vcc_5v0_usb_c2>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + label = "USBC-2 P12"; + power-role = "source"; + self-powered; + source-pdos = + ; + vbus-supply = <&vcc_5v0_usb_c2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usbc1_hs: endpoint { + remote-endpoint = <&usb_host1_xhci_drd_sw>; + }; + }; + + port@1 { + reg = <1>; + + usbc1_ss: endpoint { + remote-endpoint = <&usbdp_phy1_typec_ss>; + }; + }; + + port@2 { + reg = <2>; + + usbc1_sbu: endpoint { + remote-endpoint = <&usbdp_phy1_typec_sbu>; + }; + }; + }; + }; + }; + vdd_cpu_big0_s0: regulator@42 { compatible = "rockchip,rk8602"; reg = <0x42>; @@ -451,6 +551,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { @@ -483,6 +587,26 @@ rockchip,pins = <0 RK_PC7 12 &pcfg_pull_none>; }; }; + + usb3 { + cc_int1: cc-int1 { + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + cc_int2: cc-int2 { + rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + typec0_sbu_dc_pins: typec0-sbu-dc-pins { + rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + typec1_sbu_dc_pins: typec1-sbu-dc-pins { + rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>, + <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; }; &saradc { @@ -850,6 +974,24 @@ status = "okay"; }; +/* USB-C P11 connector */ +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +/* USB-C P12 connector */ +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -892,6 +1034,56 @@ status = "okay"; }; +/* Type-C on P11 */ +&usbdp_phy0 { + orientation-switch; + pinctrl-names = "default"; + pinctrl-0 = <&typec0_sbu_dc_pins>; + sbu1-dc-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU1_DC */ + sbu2-dc-gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>; /* Q7_USB_C0_SBU2_DC */ + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy0_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc0_ss>; + }; + + usbdp_phy0_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc0_sbu>; + }; + }; +}; + +/* Type-C on P12 */ +&usbdp_phy1 { + orientation-switch; + pinctrl-names = "default"; + pinctrl-0 = <&typec1_sbu_dc_pins>; + sbu1-dc-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU1_DC */ + sbu2-dc-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; /* Q7_USB_C1_SBU2_DC */ + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usbdp_phy1_typec_ss: endpoint@0 { + reg = <0>; + remote-endpoint = <&usbc1_ss>; + }; + + usbdp_phy1_typec_sbu: endpoint@1 { + reg = <1>; + remote-endpoint = <&usbc1_sbu>; + }; + }; +}; + /* host0 on P10 USB-A */ &usb_host0_ehci { status = "okay"; @@ -902,6 +1094,36 @@ status = "okay"; }; +/* host0 on P11 USB-C */ +&usb_host0_xhci { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usb_host0_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc0_hs>; + }; + }; +}; + +/* host1 on P12 USB-C */ +&usb_host1_xhci { + usb-role-switch; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + usb_host1_xhci_drd_sw: endpoint { + remote-endpoint = <&usbc1_hs>; + }; + }; +}; + /* host1 on M.2 E-key */ &usb_host1_ehci { status = "okay"; diff --git a/src/arm64/rockchip/rk3588-mnt-reform2.dts b/src/arm64/rockchip/rk3588-mnt-reform2.dts new file mode 100644 index 00000000000..78a4e896f66 --- /dev/null +++ b/src/arm64/rockchip/rk3588-mnt-reform2.dts @@ -0,0 +1,336 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 MNT Research GmbH + */ + +/dts-v1/; + +#include +#include +#include +#include +#include + +#include "rk3588-firefly-icore-3588q.dtsi" + +/ { + model = "MNT Reform 2 with RCORE RK3588 Module"; + compatible = "mntre,reform2-rcore", "firefly,icore-3588q", "rockchip,rk3588"; + chassis-type = "laptop"; + + aliases { + ethernet0 = &gmac0; + mmc1 = &sdmmc; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 8 16 32 64 128 160 200 255>; + default-brightness-level = <128>; + enable-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>; + pwms = <&pwm8 0 10000 0>; + }; + + gmac0_clkin: external-gmac0-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "gmac0_clkin"; + }; + + pcie30_avdd1v8: regulator-pcie30-avdd1v8 { + compatible = "regulator-fixed"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "pcie30_avdd1v8"; + vin-supply = <&avcc_1v8_s0>; + }; + + pcie30_avdd0v75: regulator-pcie30-avdd0v75 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <750000>; + regulator-name = "pcie30_avdd0v75"; + vin-supply = <&avdd_0v75_s0>; + }; + + vcc12v_dcin: regulator-vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-name = "vcc12v_dcin"; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible = "regulator-fixed"; + regulator-name = "vcc_1v1_nldo_s3"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: regulator-vcc3v3-pcie30 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pcie30"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_host: regulator-vcc5v0-host { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_host"; + }; + + vcc5v0_sys: regulator-vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_sys"; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: regulator-vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vcc5v0_usb"; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&combphy0_ps { + status = "okay"; +}; + +&gmac0 { + clock_in_out = "output"; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim + &gmac0_tx_bus2 + &gmac0_rx_bus2 + &gmac0_rgmii_clk + &gmac0_rgmii_bus + &gmac0_clkinout + ð_phy_reset>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu_s0>; + sram-supply = <&vdd_gpu_mem_s0>; + status = "okay"; +}; + +&hdmi0 { + status = "okay"; +}; + +&hdmi0_in { + hdmi0_in_vp2: endpoint { + remote-endpoint = <&vp2_out_hdmi0>; + }; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6m0_xfer>; + status = "okay"; + + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; +}; + +&mdio0 { + rgmii_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pcie2x1l2 { + pinctrl-0 = <&pcie2_0_rst>; + reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + status = "okay"; +}; + +&pcie3x4 { + num-lanes = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie3_reset>; + reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&pinctrl { + dp { + dp1_hpd: dp1-hpd { + rockchip,pins = <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie2 { + pcie2_0_rst: pcie2-0-rst { + rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pcie3 { + pcie3_reset: pcie3-reset { + rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + eth_phy { + eth_phy_reset: eth-phy-reset { + rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pwm8 { + pinctrl-0 = <&pwm8m2_pins>; + status = "okay"; +}; + +&saradc { + vref-supply = <&avcc_1v8_s0>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + max-frequency = <40000000>; + no-1-8-v; + no-mmc; + no-sdio; + vmmc-supply = <&vcc3v3_pcie30>; + vqmmc-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + +&u2phy1 { + status = "okay"; +}; + +&u2phy1_otg { + status = "okay"; +}; + +&u2phy2 { + status = "okay"; +}; + +&u2phy2_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&u2phy3 { + status = "okay"; +}; + +&u2phy3_host { + phy-supply = <&vcc5v0_host>; + status = "okay"; +}; + +&usbdp_phy0 { + status = "okay"; +}; + +&usbdp_phy1 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + dr_mode = "host"; + status = "okay"; +}; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp2 { + vp2_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { + reg = ; + remote-endpoint = <&hdmi0_in_vp2>; + }; +}; diff --git a/src/arm64/rockchip/rk3588-nanopc-t6.dtsi b/src/arm64/rockchip/rk3588-nanopc-t6.dtsi index cb350727d11..bbe500cc924 100644 --- a/src/arm64/rockchip/rk3588-nanopc-t6.dtsi +++ b/src/arm64/rockchip/rk3588-nanopc-t6.dtsi @@ -360,7 +360,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -565,6 +565,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { gpio-leds { sys_led_pin: sys-led-pin { diff --git a/src/arm64/rockchip/rk3588-ok3588-c.dts b/src/arm64/rockchip/rk3588-ok3588-c.dts index 1c0851b45eb..fbe1d5c06d9 100644 --- a/src/arm64/rockchip/rk3588-ok3588-c.dts +++ b/src/arm64/rockchip/rk3588-ok3588-c.dts @@ -312,6 +312,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { pcie2 { pcie2_0_rst: pcie2-0-rst { diff --git a/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi b/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi index 87090cb9802..f748c6f760d 100644 --- a/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi +++ b/src/arm64/rockchip/rk3588-orangepi-5-compact.dtsi @@ -7,9 +7,6 @@ #include "rk3588-orangepi-5.dtsi" / { - model = "Xunlong Orange Pi 5 Max"; - compatible = "xunlong,orangepi-5-max", "rockchip,rk3588"; - vcc5v0_usb30_otg: vcc5v0-usb30-otg-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -62,18 +59,12 @@ &led_blue_pwm { /* PWM_LED1 */ - pwms = <&pwm4 0 25000 0>; status = "okay"; }; -&led_green_pwm { - /* PWM_LED2 */ - pwms = <&pwm5 0 25000 0>; -}; - /* phy2 */ &pcie2x1l1 { - reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie_eth>; status = "okay"; }; diff --git a/src/arm64/rockchip/rk3588-orangepi-5-max.dts b/src/arm64/rockchip/rk3588-orangepi-5-max.dts index ce44549babf..8b1d35760c3 100644 --- a/src/arm64/rockchip/rk3588-orangepi-5-max.dts +++ b/src/arm64/rockchip/rk3588-orangepi-5-max.dts @@ -21,6 +21,17 @@ }; }; }; + + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; }; &hdmi0 { @@ -39,10 +50,57 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { status = "okay"; }; +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&led_blue_pwm { + pwms = <&pwm4 0 25000 0>; +}; + +&led_green_pwm { + pwms = <&pwm5 0 25000 0>; +}; + &pinctrl { usb { @@ -58,3 +116,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/src/arm64/rockchip/rk3588-orangepi-5-plus.dts b/src/arm64/rockchip/rk3588-orangepi-5-plus.dts index 255e33c5dbd..121e4d1c3fa 100644 --- a/src/arm64/rockchip/rk3588-orangepi-5-plus.dts +++ b/src/arm64/rockchip/rk3588-orangepi-5-plus.dts @@ -26,6 +26,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; @@ -113,6 +124,10 @@ status = "okay"; }; +&hdmi0_sound { + status = "okay"; +}; + &hdmi0_in { hdmi0_in_vp0: endpoint { remote-endpoint = <&vp0_out_hdmi0>; @@ -125,7 +140,31 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi1 { + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { status = "okay"; }; @@ -189,6 +228,14 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + &led_blue_gpio { gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; status = "okay"; @@ -342,3 +389,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/src/arm64/rockchip/rk3588-orangepi-5-ultra.dts b/src/arm64/rockchip/rk3588-orangepi-5-ultra.dts new file mode 100644 index 00000000000..f8c6c080e41 --- /dev/null +++ b/src/arm64/rockchip/rk3588-orangepi-5-ultra.dts @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include +#include +#include "rk3588-orangepi-5-compact.dtsi" + +/ { + model = "Xunlong Orange Pi 5 Ultra"; + compatible = "xunlong,orangepi-5-ultra", "rockchip,rk3588"; + + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; +}; + +&hdmi1 { + pinctrl-names = "default"; + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp0: endpoint { + remote-endpoint = <&vp0_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdptxphy1 { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + +&led_blue_pwm { + pwms = <&pwm4 0 25000 PWM_POLARITY_INVERTED>; +}; + +&led_green_pwm { + pwms = <&pwm5 0 25000 PWM_POLARITY_INVERTED>; +}; + +&pinctrl { + usb { + usb_otg_pwren: usb-otg-pwren { + rockchip,pins = <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&vcc5v0_usb30_otg { + gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; +}; + +&vp0 { + vp0_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp0>; + }; +}; diff --git a/src/arm64/rockchip/rk3588-orangepi-5.dtsi b/src/arm64/rockchip/rk3588-orangepi-5.dtsi index a98e804a094..91d56c34a1e 100644 --- a/src/arm64/rockchip/rk3588-orangepi-5.dtsi +++ b/src/arm64/rockchip/rk3588-orangepi-5.dtsi @@ -276,7 +276,7 @@ /* PLDO2 vcca 1.8V, BUCK8 gated by PLDO2 being enabled */ es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; AVDD-supply = <&vcc_3v3_s0>; @@ -348,6 +348,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &saradc { vref-supply = <&vcc_1v8_s0>; status = "okay"; diff --git a/src/arm64/rockchip/rk3588-quartzpro64.dts b/src/arm64/rockchip/rk3588-quartzpro64.dts index 088cfade6f6..78aaa6635b5 100644 --- a/src/arm64/rockchip/rk3588-quartzpro64.dts +++ b/src/arm64/rockchip/rk3588-quartzpro64.dts @@ -311,7 +311,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clock-rates = <12288000>; @@ -347,6 +347,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/src/arm64/rockchip/rk3588-rock-5-itx.dts b/src/arm64/rockchip/rk3588-rock-5-itx.dts index 2a059020946..7de17117df7 100644 --- a/src/arm64/rockchip/rk3588-rock-5-itx.dts +++ b/src/arm64/rockchip/rk3588-rock-5-itx.dts @@ -11,6 +11,7 @@ #include #include #include +#include #include "dt-bindings/usb/pd.h" #include "rk3588.dtsi" @@ -72,6 +73,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + /* Unnamed gated oscillator: 100MHz,3.3V,3225 */ pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator { compatible = "gated-fixed-clock"; @@ -261,6 +273,28 @@ status = "okay"; }; +&hdmi1 { + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdptxphy1 { + status = "okay"; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -564,6 +598,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { rtc_int: rtc-int { @@ -1208,3 +1246,18 @@ rockchip,dp-lane-mux = <2 3>; status = "okay"; }; + +&vop { + status = "okay"; +}; + +&vop_mmu { + status = "okay"; +}; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/src/arm64/rockchip/rk3588-rock-5b.dts b/src/arm64/rockchip/rk3588-rock-5b.dts index d597112f1d5..d22068475c5 100644 --- a/src/arm64/rockchip/rk3588-rock-5b.dts +++ b/src/arm64/rockchip/rk3588-rock-5b.dts @@ -49,6 +49,17 @@ }; }; + hdmi1-con { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint = <&hdmi1_out_con>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -220,7 +231,48 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdmi1 { + pinctrl-0 = <&hdmim0_tx1_cec &hdmim0_tx1_hpd + &hdmim1_tx1_scl &hdmim1_tx1_sda>; + status = "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint = <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint = <&hdmi1_con_in>; + }; +}; + +&hdmi1_sound { + status = "okay"; +}; + +&hdmi_receiver_cma { + status = "okay"; +}; + +&hdmi_receiver { + hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_hpd>; + pinctrl-names = "default"; + status = "okay"; +}; + +&hdptxphy0 { + status = "okay"; +}; + +&hdptxphy1 { status = "okay"; }; @@ -318,6 +370,14 @@ }; }; +&i2s5_8ch { + status = "okay"; +}; + +&i2s6_8ch { + status = "okay"; +}; + &package_thermal { polling-delay = <1000>; @@ -376,7 +436,17 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { + hdmirx { + hdmirx_hpd: hdmirx-5v-detection { + rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + hym8563 { hym8563_int: hym8563-int { rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -891,11 +961,11 @@ status = "okay"; }; -&vop_mmu { +&vop { status = "okay"; }; -&vop { +&vop_mmu { status = "okay"; }; @@ -905,3 +975,10 @@ remote-endpoint = <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg = ; + remote-endpoint = <&hdmi1_in_vp1>; + }; +}; diff --git a/src/arm64/rockchip/rk3588-tiger-haikou.dts b/src/arm64/rockchip/rk3588-tiger-haikou.dts index 3187b4918a3..a3d8ff64783 100644 --- a/src/arm64/rockchip/rk3588-tiger-haikou.dts +++ b/src/arm64/rockchip/rk3588-tiger-haikou.dts @@ -189,7 +189,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -310,8 +310,10 @@ status = "okay"; }; +/* DB9 RS232/RS485 when SW2 in "UART1" mode */ &uart5 { rts-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>; + status = "okay"; }; &usbdp_phy0 { diff --git a/src/arm64/rockchip/rk3588-tiger.dtsi b/src/arm64/rockchip/rk3588-tiger.dtsi index e8fa449517c..c4933a08dd1 100644 --- a/src/arm64/rockchip/rk3588-tiger.dtsi +++ b/src/arm64/rockchip/rk3588-tiger.dtsi @@ -173,7 +173,6 @@ &i2c2 { pinctrl-0 = <&i2c2m3_xfer>; - status = "okay"; }; &i2c2m3_xfer { @@ -336,6 +335,10 @@ reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { emmc { emmc_reset: emmc-reset { diff --git a/src/arm64/rockchip/rk3588-toybrick-x0.dts b/src/arm64/rockchip/rk3588-toybrick-x0.dts index 3cbee5b9747..5a428e00ab9 100644 --- a/src/arm64/rockchip/rk3588-toybrick-x0.dts +++ b/src/arm64/rockchip/rk3588-toybrick-x0.dts @@ -289,6 +289,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { rtl8211f { rtl8211f_rst: rtl8211f-rst { diff --git a/src/arm64/rockchip/rk3588-turing-rk1.dtsi b/src/arm64/rockchip/rk3588-turing-rk1.dtsi index 6bc46734cc1..60ad272982a 100644 --- a/src/arm64/rockchip/rk3588-turing-rk1.dtsi +++ b/src/arm64/rockchip/rk3588-turing-rk1.dtsi @@ -214,6 +214,8 @@ }; &package_thermal { + polling-delay = <1000>; + trips { package_active1: trip-active1 { temperature = <45000>; @@ -287,6 +289,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { fan { fan_int: fan-int { diff --git a/src/arm64/rockchip/rk3588j.dtsi b/src/arm64/rockchip/rk3588j.dtsi index bce72bac450..3045cb3bd68 100644 --- a/src/arm64/rockchip/rk3588j.dtsi +++ b/src/arm64/rockchip/rk3588j.dtsi @@ -11,20 +11,15 @@ compatible = "operating-points-v2"; opp-shared; - opp-1416000000 { - opp-hz = /bits/ 64 <1416000000>; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <750000 750000 950000>; clock-latency-ns = <40000>; opp-suspend; }; - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <887500 887500 950000>; - clock-latency-ns = <40000>; - }; - opp-1704000000 { - opp-hz = /bits/ 64 <1704000000>; - opp-microvolt = <937500 937500 950000>; + opp-1296000000 { + opp-hz = /bits/ 64 <1296000000>; + opp-microvolt = <775000 775000 950000>; clock-latency-ns = <40000>; }; }; @@ -33,9 +28,14 @@ compatible = "operating-points-v2"; opp-shared; + opp-1200000000{ + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; opp-1416000000 { opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <750000 750000 950000>; + opp-microvolt = <762500 762500 950000>; clock-latency-ns = <40000>; }; opp-1608000000 { @@ -43,25 +43,20 @@ opp-microvolt = <787500 787500 950000>; clock-latency-ns = <40000>; }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <875000 875000 950000>; - clock-latency-ns = <40000>; - }; - opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <950000 950000 950000>; - clock-latency-ns = <40000>; - }; }; cluster2_opp_table: opp-table-cluster2 { compatible = "operating-points-v2"; opp-shared; + opp-1200000000{ + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <750000 750000 950000>; + clock-latency-ns = <40000>; + }; opp-1416000000 { opp-hz = /bits/ 64 <1416000000>; - opp-microvolt = <750000 750000 950000>; + opp-microvolt = <762500 762500 950000>; clock-latency-ns = <40000>; }; opp-1608000000 { @@ -69,16 +64,6 @@ opp-microvolt = <787500 787500 950000>; clock-latency-ns = <40000>; }; - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <875000 875000 950000>; - clock-latency-ns = <40000>; - }; - opp-2016000000 { - opp-hz = /bits/ 64 <2016000000>; - opp-microvolt = <950000 950000 950000>; - clock-latency-ns = <40000>; - }; }; gpu_opp_table: opp-table { @@ -104,10 +89,6 @@ opp-hz = /bits/ 64 <700000000>; opp-microvolt = <750000 750000 850000>; }; - opp-850000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <787500 787500 850000>; - }; }; }; diff --git a/src/arm64/rockchip/rk3588s-coolpi-4b.dts b/src/arm64/rockchip/rk3588s-coolpi-4b.dts index 9c394f733bb..8b717c4017a 100644 --- a/src/arm64/rockchip/rk3588s-coolpi-4b.dts +++ b/src/arm64/rockchip/rk3588s-coolpi-4b.dts @@ -236,7 +236,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -361,6 +361,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { @@ -429,7 +433,7 @@ }; &pwm13 { - pinctrl-names = "active"; + pinctrl-names = "default"; pinctrl-0 = <&pwm13m2_pins>; status = "okay"; }; @@ -803,6 +807,14 @@ status = "okay"; }; +&u2phy0 { + status = "okay"; +}; + +&u2phy0_otg { + status = "okay"; +}; + &u2phy2 { status = "okay"; }; @@ -832,6 +844,16 @@ pinctrl-0 = <&uart9m2_xfer &uart9m2_ctsn>; }; +&usbdp_phy0 { + /* + * USBDP PHY0 is wired to a USB3 Type-A OTG connector. Additionally + * the differential pairs 0+1 and the aux channel are wired to a + * mini DP connector. + */ + rockchip,dp-lane-mux = <0 1>; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; @@ -840,6 +862,11 @@ status = "okay"; }; +&usb_host0_xhci { + extcon = <&u2phy0>; + status = "okay"; +}; + &usb_host1_ehci { status = "okay"; }; diff --git a/src/arm64/rockchip/rk3588s-evb1-v10.dts b/src/arm64/rockchip/rk3588s-evb1-v10.dts index bc4077575be..9f4aca9c2e3 100644 --- a/src/arm64/rockchip/rk3588s-evb1-v10.dts +++ b/src/arm64/rockchip/rk3588s-evb1-v10.dts @@ -242,7 +242,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; clocks = <&cru I2S0_8CH_MCLKOUT>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -340,6 +340,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { audio { hp_detect: headphone-detect { diff --git a/src/arm64/rockchip/rk3588s-gameforce-ace.dts b/src/arm64/rockchip/rk3588s-gameforce-ace.dts index 812bba0aef1..873a2bd6a6d 100644 --- a/src/arm64/rockchip/rk3588s-gameforce-ace.dts +++ b/src/arm64/rockchip/rk3588s-gameforce-ace.dts @@ -611,7 +611,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; assigned-clock-rates = <12288000>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -675,6 +675,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { audio-amplifier { headphone_amplifier_en: headphone-amplifier-en { diff --git a/src/arm64/rockchip/rk3588s-indiedroid-nova.dts b/src/arm64/rockchip/rk3588s-indiedroid-nova.dts index 4a3aa80f222..4189a88ecf4 100644 --- a/src/arm64/rockchip/rk3588s-indiedroid-nova.dts +++ b/src/arm64/rockchip/rk3588s-indiedroid-nova.dts @@ -278,7 +278,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -412,7 +412,7 @@ status = "okay"; es8388: audio-codec@11 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x11>; assigned-clock-rates = <12288000>; assigned-clocks = <&cru I2S0_8CH_MCLKOUT>; @@ -455,6 +455,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { bluetooth-pins { bt_reset: bt-reset { diff --git a/src/arm64/rockchip/rk3588s-khadas-edge2.dts b/src/arm64/rockchip/rk3588s-khadas-edge2.dts index ac48e7fd392..88a5e822ed1 100644 --- a/src/arm64/rockchip/rk3588s-khadas-edge2.dts +++ b/src/arm64/rockchip/rk3588s-khadas-edge2.dts @@ -233,6 +233,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { vdd_sd { vdd_sd_en: vdd-sd-en { diff --git a/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi b/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi index d2eddea1840..fbf062ec3bf 100644 --- a/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi +++ b/src/arm64/rockchip/rk3588s-nanopi-r6.dtsi @@ -251,7 +251,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -359,6 +359,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { gpio-key { key1_pin: key1-pin { diff --git a/src/arm64/rockchip/rk3588s-odroid-m2.dts b/src/arm64/rockchip/rk3588s-odroid-m2.dts index 8f034c6d494..a72063c5514 100644 --- a/src/arm64/rockchip/rk3588s-odroid-m2.dts +++ b/src/arm64/rockchip/rk3588s-odroid-m2.dts @@ -264,7 +264,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -433,6 +433,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { lcd { lcd_pwren: lcd-pwren { diff --git a/src/arm64/rockchip/rk3588s-orangepi-5.dtsi b/src/arm64/rockchip/rk3588s-orangepi-5.dtsi index d86aeacca23..4fedc50cce8 100644 --- a/src/arm64/rockchip/rk3588s-orangepi-5.dtsi +++ b/src/arm64/rockchip/rk3588s-orangepi-5.dtsi @@ -197,7 +197,11 @@ }; }; -&hdptxphy_hdmi0 { +&hdmi0_sound { + status = "okay"; +}; + +&hdptxphy0 { status = "okay"; }; @@ -268,7 +272,7 @@ status = "okay"; es8388: audio-codec@10 { - compatible = "everest,es8388"; + compatible = "everest,es8388", "everest,es8328"; reg = <0x10>; clocks = <&cru I2S1_8CH_MCLKOUT>; AVDD-supply = <&vcc_3v3_s0>; @@ -355,6 +359,10 @@ status = "okay"; }; +&i2s5_8ch { + status = "okay"; +}; + &mdio1 { rgmii_phy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -365,6 +373,10 @@ }; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { hym8563 { hym8563_int: hym8563-int { diff --git a/src/arm64/rockchip/rk3588s-rock-5a.dts b/src/arm64/rockchip/rk3588s-rock-5a.dts index 70a43432bdc..f894742b1eb 100644 --- a/src/arm64/rockchip/rk3588s-rock-5a.dts +++ b/src/arm64/rockchip/rk3588s-rock-5a.dts @@ -334,7 +334,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -359,6 +359,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { io_led: io-led { diff --git a/src/arm64/rockchip/rk3588s-rock-5c.dts b/src/arm64/rockchip/rk3588s-rock-5c.dts index 9b14d5383cd..dd7317bab61 100644 --- a/src/arm64/rockchip/rk3588s-rock-5c.dts +++ b/src/arm64/rockchip/rk3588s-rock-5c.dts @@ -68,10 +68,10 @@ }; }; - fan { + fan: fan { compatible = "pwm-fan"; #cooling-cells = <2>; - cooling-levels = <0 64 128 192 255>; + cooling-levels = <0 24 44 64 128 192 255>; fan-supply = <&vcc_5v0>; pwms = <&pwm3 0 10000 0>; }; @@ -278,7 +278,7 @@ }; }; -&hdptxphy_hdmi0 { +&hdptxphy0 { status = "okay"; }; @@ -417,6 +417,36 @@ }; }; +&package_thermal { + polling-delay = <1000>; + + trips { + package_fan0: package-fan0 { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + + package_fan1: package-fan1 { + temperature = <65000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map0 { + trip = <&package_fan0>; + cooling-device = <&fan THERMAL_NO_LIMIT 1>; + }; + + map1 { + trip = <&package_fan1>; + cooling-device = <&fan 2 THERMAL_NO_LIMIT>; + }; + }; +}; + &pcie2x1l2 { pinctrl-names = "default"; pinctrl-0 = <&pcie20x1_2_perstn_m0>; @@ -425,6 +455,10 @@ status = "okay"; }; +&pd_gpu { + domain-supply = <&vdd_gpu_s0>; +}; + &pinctrl { leds { led_pins: led-pins { @@ -843,6 +877,8 @@ }; &tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ status = "okay"; }; diff --git a/src/arm64/st/stm32mp211.dtsi b/src/arm64/st/stm32mp211.dtsi new file mode 100644 index 00000000000..bf888d60cd4 --- /dev/null +++ b/src/arm64/st/stm32mp211.dtsi @@ -0,0 +1,128 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + reg = <0>; + device_type = "cpu"; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xbc000000>; + status = "disabled"; + }; + + ck_flexgen_08: clock-64000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <64000000>; + }; + + ck_flexgen_51: clock-200000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + arm,no-tick-in-suspend; + }; + + soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x0 0x80000000>; + dma-ranges = <0x0 0x0 0x80000000 0x1 0x0>; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <2>; + + rifsc: bus@42080000 { + compatible = "simple-bus"; + reg = <0x42080000 0x0 0x1000>; + ranges; + dma-ranges; + #address-cells = <1>; + #size-cells = <2>; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x0 0x400>; + interrupts = ; + clocks = <&ck_flexgen_08>; + status = "disabled"; + }; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp21-syscfg", "syscon"; + reg = <0x44230000 0x0 0x10000>; + }; + + intc: interrupt-controller@4ac10000 { + compatible = "arm,gic-400"; + reg = <0x4ac10000 0x0 0x1000>, + <0x4ac20000 0x0 0x20000>, + <0x4ac40000 0x0 0x20000>, + <0x4ac60000 0x0 0x20000>; + #interrupt-cells = <3>; + interrupt-controller; + }; + }; +}; diff --git a/src/arm64/st/stm32mp213.dtsi b/src/arm64/st/stm32mp213.dtsi new file mode 100644 index 00000000000..fdd2dc432ed --- /dev/null +++ b/src/arm64/st/stm32mp213.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp211.dtsi" + +/ { +}; diff --git a/src/arm64/st/stm32mp215.dtsi b/src/arm64/st/stm32mp215.dtsi new file mode 100644 index 00000000000..a7df77f928c --- /dev/null +++ b/src/arm64/st/stm32mp215.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp213.dtsi" + +/ { +}; diff --git a/src/arm64/st/stm32mp215f-dk.dts b/src/arm64/st/stm32mp215f-dk.dts new file mode 100644 index 00000000000..7bdaeaa5ab0 --- /dev/null +++ b/src/arm64/st/stm32mp215f-dk.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Amelie Delaunay for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp215.dtsi" +#include "stm32mp21xf.dtsi" + +/ { + model = "STMicroelectronics STM32MP215F-DK Discovery Board"; + compatible = "st,stm32mp215f-dk", "st,stm32mp215"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&usart2 { + status = "okay"; +}; diff --git a/src/arm64/st/stm32mp21xc.dtsi b/src/arm64/st/stm32mp21xc.dtsi new file mode 100644 index 00000000000..e33b00b424e --- /dev/null +++ b/src/arm64/st/stm32mp21xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { +}; diff --git a/src/arm64/st/stm32mp21xf.dtsi b/src/arm64/st/stm32mp21xf.dtsi new file mode 100644 index 00000000000..e33b00b424e --- /dev/null +++ b/src/arm64/st/stm32mp21xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { +}; diff --git a/src/arm64/st/stm32mp231.dtsi b/src/arm64/st/stm32mp231.dtsi new file mode 100644 index 00000000000..75697acd134 --- /dev/null +++ b/src/arm64/st/stm32mp231.dtsi @@ -0,0 +1,1213 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include +#include +#include +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + reg = <0>; + device_type = "cpu"; + enable-method = "psci"; + power-domains = <&cpu0_pd>; + power-domain-names = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xb200005a>; + status = "disabled"; + }; + + clk_dsi_txbyte: clock-0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + clk_rcbsec: clk-64000000 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <64000000>; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + interrupt-parent = <&intc>; + interrupts = ; + }; + + scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + + scmi_voltd: protocol@17 { + reg = <0x17>; + + scmi_regu: regulators { + #address-cells = <1>; + #size-cells = <0>; + + scmi_vddio1: regulator@0 { + reg = ; + regulator-name = "vddio1"; + }; + scmi_vddio2: regulator@1 { + reg = ; + regulator-name = "vddio2"; + }; + scmi_vddio3: regulator@2 { + reg = ; + regulator-name = "vddio3"; + }; + scmi_vddio4: regulator@3 { + reg = ; + regulator-name = "vddio4"; + }; + scmi_vdd33ucpd: regulator@5 { + reg = ; + regulator-name = "vdd33ucpd"; + }; + scmi_vdda18adc: regulator@7 { + reg = ; + regulator-name = "vdda18adc"; + }; + }; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + cpu0_pd: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + }; + + cluster_pd: power-domain-cluster { + #power-domain-cells = <0>; + power-domains = <&ret_pd>; + }; + + ret_pd: power-domain-retention { + #power-domain-cells = <0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + always-on; + }; + + soc@0 { + compatible = "simple-bus"; + ranges = <0x0 0x0 0x0 0x80000000>; + interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; + + hpdma: dma-controller@40400000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40400000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&scmi_clk CK_SCMI_HPDMA1>; + #dma-cells = <3>; + }; + + hpdma2: dma-controller@40410000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40410000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&scmi_clk CK_SCMI_HPDMA2>; + #dma-cells = <3>; + }; + + hpdma3: dma-controller@40420000 { + compatible = "st,stm32mp25-dma3"; + reg = <0x40420000 0x1000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&scmi_clk CK_SCMI_HPDMA3>; + #dma-cells = <3>; + }; + + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc", "simple-bus"; + reg = <0x42080000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + #access-controller-cells = <1>; + + i2s2: audio-controller@400b0000 { + compatible = "st,stm32mp25-i2s"; + reg = <0x400b0000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + clocks = <&rcc CK_BUS_SPI2>, <&rcc CK_KER_SPI2>; + clock-names = "pclk", "i2sclk"; + resets = <&rcc SPI2_R>; + dmas = <&hpdma 51 0x43 0x12>, + <&hpdma 52 0x43 0x21>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 23>; + status = "disabled"; + }; + + spi2: spi@400b0000 { + compatible = "st,stm32mp25-spi"; + reg = <0x400b0000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&rcc CK_KER_SPI2>; + resets = <&rcc SPI2_R>; + dmas = <&hpdma 51 0x20 0x3012>, + <&hpdma 52 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 23>; + status = "disabled"; + }; + + i2s3: audio-controller@400c0000 { + compatible = "st,stm32mp25-i2s"; + reg = <0x400c0000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + clocks = <&rcc CK_BUS_SPI3>, <&rcc CK_KER_SPI3>; + clock-names = "pclk", "i2sclk"; + resets = <&rcc SPI3_R>; + dmas = <&hpdma 53 0x43 0x12>, + <&hpdma 54 0x43 0x21>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 24>; + status = "disabled"; + }; + + spi3: spi@400c0000 { + compatible = "st,stm32mp25-spi"; + reg = <0x400c0000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&rcc CK_KER_SPI3>; + resets = <&rcc SPI3_R>; + dmas = <&hpdma 53 0x20 0x3012>, + <&hpdma 54 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 24>; + status = "disabled"; + }; + + spdifrx: audio-controller@400d0000 { + compatible = "st,stm32h7-spdifrx"; + reg = <0x400d0000 0x400>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SPDIFRX>; + clock-names = "kclk"; + interrupts = ; + dmas = <&hpdma 71 0x43 0x212>, + <&hpdma 72 0x43 0x212>; + dma-names = "rx", "rx-ctrl"; + access-controllers = <&rifsc 30>; + status = "disabled"; + }; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_USART2>; + dmas = <&hpdma 11 0x20 0x10012>, + <&hpdma 12 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 32>; + status = "disabled"; + }; + + usart3: serial@400f0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400f0000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_USART3>; + dmas = <&hpdma 13 0x20 0x10012>, + <&hpdma 14 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 33>; + status = "disabled"; + }; + + uart4: serial@40100000 { + compatible = "st,stm32h7-uart"; + reg = <0x40100000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART4>; + dmas = <&hpdma 15 0x20 0x10012>, + <&hpdma 16 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 34>; + status = "disabled"; + }; + + uart5: serial@40110000 { + compatible = "st,stm32h7-uart"; + reg = <0x40110000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART5>; + dmas = <&hpdma 17 0x20 0x10012>, + <&hpdma 18 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 35>; + status = "disabled"; + }; + + i2c1: i2c@40120000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40120000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C1>; + resets = <&rcc I2C1_R>; + dmas = <&hpdma 27 0x20 0x3012>, + <&hpdma 28 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 41>; + status = "disabled"; + }; + + i2c2: i2c@40130000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40130000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C2>; + resets = <&rcc I2C2_R>; + dmas = <&hpdma 30 0x20 0x3012>, + <&hpdma 31 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 42>; + status = "disabled"; + }; + + i2c7: i2c@40180000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x40180000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C7>; + resets = <&rcc I2C7_R>; + dmas = <&hpdma 45 0x20 0x3012>, + <&hpdma 46 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 47>; + status = "disabled"; + }; + + usart6: serial@40220000 { + compatible = "st,stm32h7-uart"; + reg = <0x40220000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_USART6>; + dmas = <&hpdma 19 0x20 0x10012>, + <&hpdma 20 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 36>; + status = "disabled"; + }; + + i2s1: audio-controller@40230000 { + compatible = "st,stm32mp25-i2s"; + reg = <0x40230000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + clocks = <&rcc CK_BUS_SPI1>, <&rcc CK_KER_SPI1>; + clock-names = "pclk", "i2sclk"; + resets = <&rcc SPI1_R>; + dmas = <&hpdma 49 0x43 0x12>, + <&hpdma 50 0x43 0x21>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 22>; + status = "disabled"; + }; + + spi1: spi@40230000 { + compatible = "st,stm32mp25-spi"; + reg = <0x40230000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&rcc CK_KER_SPI1>; + resets = <&rcc SPI1_R>; + dmas = <&hpdma 49 0x20 0x3012>, + <&hpdma 50 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 22>; + status = "disabled"; + }; + + spi4: spi@40240000 { + compatible = "st,stm32mp25-spi"; + reg = <0x40240000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&rcc CK_KER_SPI4>; + resets = <&rcc SPI4_R>; + dmas = <&hpdma 55 0x20 0x3012>, + <&hpdma 56 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 25>; + status = "disabled"; + }; + + spi5: spi@40280000 { + compatible = "st,stm32mp25-spi"; + reg = <0x40280000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&rcc CK_KER_SPI5>; + resets = <&rcc SPI5_R>; + dmas = <&hpdma 57 0x20 0x3012>, + <&hpdma 58 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 26>; + status = "disabled"; + }; + + sai1: sai@40290000 { + compatible = "st,stm32mp25-sai"; + reg = <0x40290000 0x4>, <0x4029a3f0 0x10>; + ranges = <0 0x40290000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI1>; + clock-names = "pclk"; + interrupts = ; + resets = <&rcc SAI1_R>; + access-controllers = <&rifsc 49>; + status = "disabled"; + + sai1a: audio-controller@40290004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI1>; + clock-names = "sai_ck"; + dmas = <&hpdma 73 0x43 0x21>; + status = "disabled"; + }; + + sai1b: audio-controller@40290024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI1>; + clock-names = "sai_ck"; + dmas = <&hpdma 74 0x43 0x12>; + status = "disabled"; + }; + }; + + sai2: sai@402a0000 { + compatible = "st,stm32mp25-sai"; + reg = <0x402a0000 0x4>, <0x402aa3f0 0x10>; + ranges = <0 0x402a0000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI2>; + clock-names = "pclk"; + interrupts = ; + resets = <&rcc SAI2_R>; + access-controllers = <&rifsc 50>; + status = "disabled"; + + sai2a: audio-controller@402a0004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI2>; + clock-names = "sai_ck"; + dmas = <&hpdma 75 0x43 0x21>; + status = "disabled"; + }; + + sai2b: audio-controller@402a0024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI2>; + clock-names = "sai_ck"; + dmas = <&hpdma 76 0x43 0x12>; + status = "disabled"; + }; + }; + + sai3: sai@402b0000 { + compatible = "st,stm32mp25-sai"; + reg = <0x402b0000 0x4>, <0x402ba3f0 0x10>; + ranges = <0 0x402b0000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI3>; + clock-names = "pclk"; + interrupts = ; + resets = <&rcc SAI3_R>; + access-controllers = <&rifsc 51>; + status = "disabled"; + + sai3a: audio-controller@402b0004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI3>; + clock-names = "sai_ck"; + dmas = <&hpdma 77 0x43 0x21>; + status = "disabled"; + }; + + sai3b: audio-controller@502b0024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI3>; + clock-names = "sai_ck"; + dmas = <&hpdma 78 0x43 0x12>; + status = "disabled"; + }; + }; + + usart1: serial@40330000 { + compatible = "st,stm32h7-uart"; + reg = <0x40330000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_USART1>; + dmas = <&hpdma 9 0x20 0x10012>, + <&hpdma 10 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 31>; + status = "disabled"; + }; + + sai4: sai@40340000 { + compatible = "st,stm32mp25-sai"; + reg = <0x40340000 0x4>, <0x4034a3f0 0x10>; + ranges = <0 0x40340000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&rcc CK_BUS_SAI4>; + clock-names = "pclk"; + interrupts = ; + resets = <&rcc SAI4_R>; + access-controllers = <&rifsc 52>; + status = "disabled"; + + sai4a: audio-controller@40340004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI4>; + clock-names = "sai_ck"; + dmas = <&hpdma 79 0x63 0x21>; + status = "disabled"; + }; + + sai4b: audio-controller@40340024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc CK_KER_SAI4>; + clock-names = "sai_ck"; + dmas = <&hpdma 80 0x43 0x12>; + status = "disabled"; + }; + }; + + uart7: serial@40370000 { + compatible = "st,stm32h7-uart"; + reg = <0x40370000 0x400>; + interrupts = ; + clocks = <&rcc CK_KER_UART7>; + dmas = <&hpdma 21 0x20 0x10012>, + <&hpdma 22 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 37>; + status = "disabled"; + }; + + rng: rng@42020000 { + compatible = "st,stm32mp25-rng"; + reg = <0x42020000 0x400>; + clocks = <&clk_rcbsec>, <&rcc CK_BUS_RNG>; + clock-names = "core", "bus"; + resets = <&rcc RNG_R>; + access-controllers = <&rifsc 92>; + status = "disabled"; + }; + + spi8: spi@46020000 { + compatible = "st,stm32mp25-spi"; + reg = <0x46020000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&rcc CK_KER_SPI8>; + resets = <&rcc SPI8_R>; + dmas = <&hpdma 171 0x20 0x3012>, + <&hpdma 172 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 29>; + status = "disabled"; + }; + + i2c8: i2c@46040000 { + compatible = "st,stm32mp25-i2c"; + reg = <0x46040000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-names = "event"; + interrupts = ; + clocks = <&rcc CK_KER_I2C8>; + resets = <&rcc I2C8_R>; + dmas = <&hpdma 168 0x20 0x3012>, + <&hpdma 169 0x20 0x3021>; + dma-names = "rx", "tx"; + access-controllers = <&rifsc 48>; + status = "disabled"; + }; + + csi: csi@48020000 { + compatible = "st,stm32mp25-csi"; + reg = <0x48020000 0x2000>; + interrupts = ; + resets = <&rcc CSI_R>; + clocks = <&rcc CK_KER_CSI>, <&rcc CK_KER_CSITXESC>, + <&rcc CK_KER_CSIPHY>; + clock-names = "pclk", "txesc", "csi2phy"; + access-controllers = <&rifsc 86>; + status = "disabled"; + }; + + dcmipp: dcmipp@48030000 { + compatible = "st,stm32mp25-dcmipp"; + reg = <0x48030000 0x1000>; + interrupts = ; + resets = <&rcc DCMIPP_R>; + clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>; + clock-names = "kclk", "mclk"; + access-controllers = <&rifsc 87>; + status = "disabled"; + }; + + sdmmc1: mmc@48220000 { + compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; + reg = <0x48220000 0x400>, <0x44230400 0x8>; + arm,primecell-periphid = <0x00353180>; + interrupts = ; + clocks = <&rcc CK_KER_SDMMC1 >; + clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; + access-controllers = <&rifsc 76>; + status = "disabled"; + }; + + ethernet1: ethernet@482c0000 { + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; + reg = <0x482c0000 0x4000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ptp_ref", + "ethstp", + "eth-ck"; + clocks = <&rcc CK_ETH1_MAC>, + <&rcc CK_ETH1_TX>, + <&rcc CK_ETH1_RX>, + <&rcc CK_KER_ETH1PTP>, + <&rcc CK_ETH1_STP>, + <&rcc CK_KER_ETH1>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,mixed-burst; + snps,mtl-rx-config = <&mtl_rx_setup_1>; + snps,mtl-tx-config = <&mtl_tx_setup_1>; + snps,pbl = <2>; + snps,tso; + st,syscon = <&syscfg 0x3000>; + access-controllers = <&rifsc 60>; + status = "disabled"; + + mtl_rx_setup_1: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + mtl_tx_setup_1: tx-queues-config { + snps,tx-queues-to-use = <4>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + }; + + stmmac_axi_config_1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; + }; + + bsec: efuse@44000000 { + compatible = "st,stm32mp25-bsec"; + reg = <0x44000000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + part_number_otp@24 { + reg = <0x24 0x4>; + }; + + package_otp@1e8 { + reg = <0x1e8 0x1>; + bits = <0 3>; + }; + }; + + rcc: clock-controller@44200000 { + compatible = "st,stm32mp25-rcc"; + reg = <0x44200000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_MSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>, + <&scmi_clk CK_SCMI_HSE_DIV2>, + <&scmi_clk CK_SCMI_ICN_HS_MCU>, + <&scmi_clk CK_SCMI_ICN_LS_MCU>, + <&scmi_clk CK_SCMI_ICN_SDMMC>, + <&scmi_clk CK_SCMI_ICN_DDR>, + <&scmi_clk CK_SCMI_ICN_DISPLAY>, + <&scmi_clk CK_SCMI_ICN_HSL>, + <&scmi_clk CK_SCMI_ICN_NIC>, + <&scmi_clk CK_SCMI_ICN_VID>, + <&scmi_clk CK_SCMI_FLEXGEN_07>, + <&scmi_clk CK_SCMI_FLEXGEN_08>, + <&scmi_clk CK_SCMI_FLEXGEN_09>, + <&scmi_clk CK_SCMI_FLEXGEN_10>, + <&scmi_clk CK_SCMI_FLEXGEN_11>, + <&scmi_clk CK_SCMI_FLEXGEN_12>, + <&scmi_clk CK_SCMI_FLEXGEN_13>, + <&scmi_clk CK_SCMI_FLEXGEN_14>, + <&scmi_clk CK_SCMI_FLEXGEN_15>, + <&scmi_clk CK_SCMI_FLEXGEN_16>, + <&scmi_clk CK_SCMI_FLEXGEN_17>, + <&scmi_clk CK_SCMI_FLEXGEN_18>, + <&scmi_clk CK_SCMI_FLEXGEN_19>, + <&scmi_clk CK_SCMI_FLEXGEN_20>, + <&scmi_clk CK_SCMI_FLEXGEN_21>, + <&scmi_clk CK_SCMI_FLEXGEN_22>, + <&scmi_clk CK_SCMI_FLEXGEN_23>, + <&scmi_clk CK_SCMI_FLEXGEN_24>, + <&scmi_clk CK_SCMI_FLEXGEN_25>, + <&scmi_clk CK_SCMI_FLEXGEN_26>, + <&scmi_clk CK_SCMI_FLEXGEN_27>, + <&scmi_clk CK_SCMI_FLEXGEN_28>, + <&scmi_clk CK_SCMI_FLEXGEN_29>, + <&scmi_clk CK_SCMI_FLEXGEN_30>, + <&scmi_clk CK_SCMI_FLEXGEN_31>, + <&scmi_clk CK_SCMI_FLEXGEN_32>, + <&scmi_clk CK_SCMI_FLEXGEN_33>, + <&scmi_clk CK_SCMI_FLEXGEN_34>, + <&scmi_clk CK_SCMI_FLEXGEN_35>, + <&scmi_clk CK_SCMI_FLEXGEN_36>, + <&scmi_clk CK_SCMI_FLEXGEN_37>, + <&scmi_clk CK_SCMI_FLEXGEN_38>, + <&scmi_clk CK_SCMI_FLEXGEN_39>, + <&scmi_clk CK_SCMI_FLEXGEN_40>, + <&scmi_clk CK_SCMI_FLEXGEN_41>, + <&scmi_clk CK_SCMI_FLEXGEN_42>, + <&scmi_clk CK_SCMI_FLEXGEN_43>, + <&scmi_clk CK_SCMI_FLEXGEN_44>, + <&scmi_clk CK_SCMI_FLEXGEN_45>, + <&scmi_clk CK_SCMI_FLEXGEN_46>, + <&scmi_clk CK_SCMI_FLEXGEN_47>, + <&scmi_clk CK_SCMI_FLEXGEN_48>, + <&scmi_clk CK_SCMI_FLEXGEN_49>, + <&scmi_clk CK_SCMI_FLEXGEN_50>, + <&scmi_clk CK_SCMI_FLEXGEN_51>, + <&scmi_clk CK_SCMI_FLEXGEN_52>, + <&scmi_clk CK_SCMI_FLEXGEN_53>, + <&scmi_clk CK_SCMI_FLEXGEN_54>, + <&scmi_clk CK_SCMI_FLEXGEN_55>, + <&scmi_clk CK_SCMI_FLEXGEN_56>, + <&scmi_clk CK_SCMI_FLEXGEN_57>, + <&scmi_clk CK_SCMI_FLEXGEN_58>, + <&scmi_clk CK_SCMI_FLEXGEN_59>, + <&scmi_clk CK_SCMI_FLEXGEN_60>, + <&scmi_clk CK_SCMI_FLEXGEN_61>, + <&scmi_clk CK_SCMI_FLEXGEN_62>, + <&scmi_clk CK_SCMI_FLEXGEN_63>, + <&scmi_clk CK_SCMI_ICN_APB1>, + <&scmi_clk CK_SCMI_ICN_APB2>, + <&scmi_clk CK_SCMI_ICN_APB3>, + <&scmi_clk CK_SCMI_ICN_APB4>, + <&scmi_clk CK_SCMI_ICN_APBDBG>, + <&scmi_clk CK_SCMI_TIMG1>, + <&scmi_clk CK_SCMI_TIMG2>, + <&scmi_clk CK_SCMI_PLL3>, + <&clk_dsi_txbyte>; + access-controllers = <&rifsc 156>; + }; + + exti1: interrupt-controller@44220000 { + compatible = "st,stm32mp1-exti", "syscon"; + reg = <0x44220000 0x400>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = + <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ + <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ + <&intc GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_20 */ + <&intc GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ + <&intc GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ + <&intc GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <&intc GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_60 */ + <&intc GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_70 */ + <0>, + <&intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <0>, /* EXTI_80 */ + <0>, + <0>, + <&intc GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp23-syscfg", "syscon"; + reg = <0x44230000 0x10000>; + }; + + pinctrl: pinctrl@44240000 { + compatible = "st,stm32mp257-pinctrl"; + ranges = <0 0x44240000 0xa0400>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&exti1>; + st,syscfg = <&exti1 0x60 0xff>; + pins-are-numbered; + + gpioa: gpio@44240000 { + reg = <0x0 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOA>; + st,bank-name = "GPIOA"; + status = "disabled"; + }; + + gpiob: gpio@44250000 { + reg = <0x10000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOB>; + st,bank-name = "GPIOB"; + status = "disabled"; + }; + + gpioc: gpio@44260000 { + reg = <0x20000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOC>; + st,bank-name = "GPIOC"; + status = "disabled"; + }; + + gpiod: gpio@44270000 { + reg = <0x30000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOD>; + st,bank-name = "GPIOD"; + status = "disabled"; + }; + + gpioe: gpio@44280000 { + reg = <0x40000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOE>; + st,bank-name = "GPIOE"; + status = "disabled"; + }; + + gpiof: gpio@44290000 { + reg = <0x50000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOF>; + st,bank-name = "GPIOF"; + status = "disabled"; + }; + + gpiog: gpio@442a0000 { + reg = <0x60000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOG>; + st,bank-name = "GPIOG"; + status = "disabled"; + }; + + gpioh: gpio@442b0000 { + reg = <0x70000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOH>; + st,bank-name = "GPIOH"; + status = "disabled"; + }; + + gpioi: gpio@442c0000 { + reg = <0x80000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOI>; + st,bank-name = "GPIOI"; + status = "disabled"; + }; + + gpioj: gpio@442d0000 { + reg = <0x90000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOJ>; + st,bank-name = "GPIOJ"; + status = "disabled"; + }; + + gpiok: gpio@442e0000 { + reg = <0xa0000 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOK>; + st,bank-name = "GPIOK"; + status = "disabled"; + }; + }; + + rtc: rtc@46000000 { + compatible = "st,stm32mp25-rtc"; + reg = <0x46000000 0x400>; + clocks = <&scmi_clk CK_SCMI_RTC>, + <&scmi_clk CK_SCMI_RTCCK>; + clock-names = "pclk", "rtc_ck"; + interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pinctrl_z: pinctrl@46200000 { + compatible = "st,stm32mp257-z-pinctrl"; + ranges = <0 0x46200000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&exti1>; + st,syscfg = <&exti1 0x60 0xff>; + pins-are-numbered; + + gpioz: gpio@46200000 { + reg = <0 0x400>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&scmi_clk CK_SCMI_GPIOZ>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + status = "disabled"; + }; + + }; + + exti2: interrupt-controller@46230000 { + compatible = "st,stm32mp1-exti", "syscon"; + reg = <0x46230000 0x400>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts-extended = + <&intc GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */ + <&intc GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_10 */ + <&intc GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, /* EXTI_20 */ + <&intc GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_30 */ + <&intc GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_40 */ + <0>, + <0>, + <&intc GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_50 */ + <&intc GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, /* EXTI_60 */ + <&intc GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <&intc GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <0>, + <0>, + <&intc GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; /* EXTI_70 */ + }; + + intc: interrupt-controller@4ac10000 { + compatible = "arm,gic-400"; + reg = <0x4ac10000 0x1000>, + <0x4ac20000 0x20000>, + <0x4ac40000 0x20000>, + <0x4ac60000 0x20000>; + #interrupt-cells = <3>; + interrupt-controller; + }; + }; +}; diff --git a/src/arm64/st/stm32mp233.dtsi b/src/arm64/st/stm32mp233.dtsi new file mode 100644 index 00000000000..78f4059fca5 --- /dev/null +++ b/src/arm64/st/stm32mp233.dtsi @@ -0,0 +1,94 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp231.dtsi" + +/ { + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a35"; + reg = <1>; + device_type = "cpu"; + enable-method = "psci"; + power-domains = <&cpu1_pd>; + power-domain-names = "psci"; + }; + }; + + arm-pmu { + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + + psci { + cpu1_pd: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&cluster_pd>; + }; + }; + + timer { + interrupts = , + , + , + ; + }; +}; + +&optee { + interrupts = ; +}; + +&rifsc { + ethernet2: ethernet@482d0000 { + compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20"; + reg = <0x482d0000 0x4000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ptp_ref", + "ethstp", + "eth-ck"; + clocks = <&rcc CK_ETH2_MAC>, + <&rcc CK_ETH2_TX>, + <&rcc CK_ETH2_RX>, + <&rcc CK_KER_ETH2PTP>, + <&rcc CK_ETH2_STP>, + <&rcc CK_KER_ETH2>; + snps,axi-config = <&stmmac_axi_config_2>; + snps,mixed-burst; + snps,mtl-rx-config = <&mtl_rx_setup_2>; + snps,mtl-tx-config = <&mtl_tx_setup_2>; + snps,pbl = <2>; + snps,tso; + st,syscon = <&syscfg 0x3400>; + access-controllers = <&rifsc 61>; + status = "disabled"; + + mtl_rx_setup_2: rx-queues-config { + snps,rx-queues-to-use = <2>; + queue0 {}; + queue1 {}; + }; + + mtl_tx_setup_2: tx-queues-config { + snps,tx-queues-to-use = <4>; + queue0 {}; + queue1 {}; + queue2 {}; + queue3 {}; + }; + + stmmac_axi_config_2: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; +}; diff --git a/src/arm64/st/stm32mp235.dtsi b/src/arm64/st/stm32mp235.dtsi new file mode 100644 index 00000000000..2719c088dd5 --- /dev/null +++ b/src/arm64/st/stm32mp235.dtsi @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp233.dtsi" + +&rifsc { + vdec: vdec@480d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x480d0000 0x3c8>; + interrupts = ; + clocks = <&rcc CK_BUS_VDEC>; + access-controllers = <&rifsc 89>; + }; +}; diff --git a/src/arm64/st/stm32mp235f-dk.dts b/src/arm64/st/stm32mp235f-dk.dts new file mode 100644 index 00000000000..04d1b434c43 --- /dev/null +++ b/src/arm64/st/stm32mp235f-dk.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Amelie Delaunay for STMicroelectronics. + */ + +/dts-v1/; + +#include +#include +#include +#include "stm32mp235.dtsi" +#include "stm32mp23xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxak-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP235F-DK Discovery Board"; + compatible = "st,stm32mp235f-dk", "st,stm32mp235"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = ; + gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; + }; + + button-user-2 { + label = "User-2"; + linux,code = ; + gpios = <&gpioc 11 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + scmi_vdd_sdcard: regulator@23 { + reg = ; + regulator-name = "vdd_sdcard"; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiod 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_vdd_sdcard>; + vqmmc-supply = <&scmi_vddio1>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; diff --git a/src/arm64/st/stm32mp23xc.dtsi b/src/arm64/st/stm32mp23xc.dtsi new file mode 100644 index 00000000000..e33b00b424e --- /dev/null +++ b/src/arm64/st/stm32mp23xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { +}; diff --git a/src/arm64/st/stm32mp23xf.dtsi b/src/arm64/st/stm32mp23xf.dtsi new file mode 100644 index 00000000000..e33b00b424e --- /dev/null +++ b/src/arm64/st/stm32mp23xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { +}; diff --git a/src/arm64/st/stm32mp251.dtsi b/src/arm64/st/stm32mp251.dtsi index f3c6cdfd700..87110f91e48 100644 --- a/src/arm64/st/stm32mp251.dtsi +++ b/src/arm64/st/stm32mp251.dtsi @@ -115,14 +115,13 @@ }; intc: interrupt-controller@4ac00000 { - compatible = "arm,cortex-a7-gic"; + compatible = "arm,gic-400"; #interrupt-cells = <3>; - #address-cells = <1>; interrupt-controller; reg = <0x0 0x4ac10000 0x0 0x1000>, - <0x0 0x4ac20000 0x0 0x2000>, - <0x0 0x4ac40000 0x0 0x2000>, - <0x0 0x4ac60000 0x0 0x2000>; + <0x0 0x4ac20000 0x0 0x20000>, + <0x0 0x4ac40000 0x0 0x20000>, + <0x0 0x4ac60000 0x0 0x20000>; }; psci { diff --git a/src/arm64/st/stm32mp257f-dk.dts b/src/arm64/st/stm32mp257f-dk.dts new file mode 100644 index 00000000000..a278a1e3ce0 --- /dev/null +++ b/src/arm64/st/stm32mp257f-dk.dts @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include +#include +#include +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxak-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-DK Discovery Board"; + compatible = "st,stm32mp257f-dk", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user-1 { + label = "User-1"; + linux,code = ; + gpios = <&gpioc 5 GPIO_ACTIVE_HIGH>; + }; + + button-user-2 { + label = "User-2"; + linux,code = ; + gpios = <&gpioc 11 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-blue { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpioh 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&scmi_regu { + scmi_vddio1: regulator@0 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + scmi_vdd_sdcard: regulator@23 { + reg = ; + regulator-name = "vdd_sdcard"; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiod 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_vdd_sdcard>; + vqmmc-supply = <&scmi_vddio1>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; diff --git a/src/arm64/tesla/fsd.dtsi b/src/arm64/tesla/fsd.dtsi index 690b4ed9c29..9951eef9507 100644 --- a/src/arm64/tesla/fsd.dtsi +++ b/src/arm64/tesla/fsd.dtsi @@ -92,7 +92,7 @@ reg = <0x0 0x000>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -108,7 +108,7 @@ reg = <0x0 0x001>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -124,7 +124,7 @@ reg = <0x0 0x002>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -139,7 +139,7 @@ compatible = "arm,cortex-a72"; reg = <0x0 0x003>; enable-method = "psci"; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -156,7 +156,7 @@ reg = <0x0 0x100>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -172,7 +172,7 @@ reg = <0x0 0x101>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -188,7 +188,7 @@ reg = <0x0 0x102>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -204,7 +204,7 @@ reg = <0x0 0x103>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -221,7 +221,7 @@ reg = <0x0 0x200>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -237,7 +237,7 @@ reg = <0x0 0x201>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -253,7 +253,7 @@ reg = <0x0 0x202>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -269,7 +269,7 @@ reg = <0x0 0x203>; enable-method = "psci"; clock-frequency = <2400000000>; - cpu-idle-states = <&CPU_SLEEP>; + cpu-idle-states = <&cpu_sleep>; i-cache-size = <0xc000>; i-cache-line-size = <64>; i-cache-sets = <256>; @@ -291,7 +291,7 @@ idle-states { entry-method = "psci"; - CPU_SLEEP: cpu-sleep { + cpu_sleep: cpu-sleep { idle-state-name = "c2"; compatible = "arm,idle-state"; local-timer-stop; diff --git a/src/arm64/ti/k3-am62-phycore-som.dtsi b/src/arm64/ti/k3-am62-phycore-som.dtsi index 2ef4cbaec78..55ed418c023 100644 --- a/src/arm64/ti/k3-am62-phycore-som.dtsi +++ b/src/arm64/ti/k3-am62-phycore-som.dtsi @@ -29,6 +29,7 @@ memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + bootph-all; }; reserved_memory: reserved-memory { @@ -36,15 +37,21 @@ #size-cells = <2>; ranges; - ramoops@9ca00000 { + ramoops@9c700000 { compatible = "ramoops"; - reg = <0x00 0x9ca00000 0x00 0x00100000>; + reg = <0x00 0x9c700000 0x00 0x00100000>; record-size = <0x8000>; console-size = <0x8000>; ftrace-size = <0x00>; pmsg-size = <0x8000>; }; + rtos_ipc_memory_region: ipc-memories@9c800000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c800000 0x00 0x00300000>; + no-map; + }; + mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { compatible = "shared-dma-pool"; reg = <0x00 0x9cb00000 0x00 0x100000>; @@ -131,6 +138,7 @@ AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ >; + bootph-all; }; main_mdio1_pins_default: main-mdio1-default-pins { @@ -138,6 +146,7 @@ AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ >; + bootph-all; }; main_mmc0_pins_default: main-mmc0-default-pins { @@ -153,6 +162,7 @@ AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ >; + bootph-all; }; main_rgmii1_pins_default: main-rgmii1-default-pins { @@ -170,6 +180,7 @@ AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ >; + bootph-all; }; ospi0_pins_default: ospi0-default-pins { @@ -186,6 +197,7 @@ AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ >; + bootph-all; }; pmic_irq_pins_default: pmic-irq-default-pins { @@ -210,6 +222,7 @@ &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy1>; + bootph-all; }; &cpsw3g_mdio { @@ -220,6 +233,7 @@ cpsw3g_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; reg = <1>; + bootph-all; ti,rx-internal-delay = ; ti,fifo-depth = ; }; @@ -232,10 +246,15 @@ }; }; +&main_pktdma { + bootph-all; +}; + &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + bootph-all; status = "okay"; pmic@30 { @@ -355,6 +374,7 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + bootph-all; }; }; @@ -363,5 +383,6 @@ pinctrl-0 = <&main_mmc0_pins_default>; disable-wp; non-removable; + bootph-all; status = "okay"; }; diff --git a/src/arm64/ti/k3-am62-verdin-dahlia.dtsi b/src/arm64/ti/k3-am62-verdin-dahlia.dtsi index 9202181fbd6..fcc4cb2e938 100644 --- a/src/arm64/ti/k3-am62-verdin-dahlia.dtsi +++ b/src/arm64/ti/k3-am62-verdin-dahlia.dtsi @@ -28,10 +28,10 @@ "Headphone Jack", "HPOUTR", "IN2L", "Line In Jack", "IN2R", "Line In Jack", - "Headphone Jack", "MICBIAS", - "IN1L", "Headphone Jack"; + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack"; simple-audio-card,widgets = - "Microphone", "Headphone Jack", + "Microphone", "Microphone Jack", "Headphone", "Headphone Jack", "Line", "Line In Jack"; diff --git a/src/arm64/ti/k3-am625-beagleplay.dts b/src/arm64/ti/k3-am625-beagleplay.dts index 75c80290b12..a5469f2712f 100644 --- a/src/arm64/ti/k3-am625-beagleplay.dts +++ b/src/arm64/ti/k3-am625-beagleplay.dts @@ -65,6 +65,14 @@ pmsg-size = <0x8000>; }; + /* global cma region */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x00 0x8000000>; + linux,cma-default; + }; + secure_tfa_ddr: tfa@9e780000 { reg = <0x00 0x9e780000 0x00 0x80000>; no-map; diff --git a/src/arm64/ti/k3-am62a-mcu.dtsi b/src/arm64/ti/k3-am62a-mcu.dtsi index 0469c766b76..9ed9d703ff2 100644 --- a/src/arm64/ti/k3-am62a-mcu.dtsi +++ b/src/arm64/ti/k3-am62a-mcu.dtsi @@ -12,7 +12,6 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; - status = "disabled"; }; mcu_esm: esm@4100000 { diff --git a/src/arm64/ti/k3-am62a-phycore-som.dtsi b/src/arm64/ti/k3-am62a-phycore-som.dtsi index a5aceaa3967..147d56b8798 100644 --- a/src/arm64/ti/k3-am62a-phycore-som.dtsi +++ b/src/arm64/ti/k3-am62a-phycore-som.dtsi @@ -42,6 +42,7 @@ device_type = "memory"; /* 2G RAM */ reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + bootph-all; }; reserved-memory { @@ -99,6 +100,7 @@ AM62AX_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (D17) I2C0_SCL */ AM62AX_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (E16) I2C0_SDA */ >; + bootph-all; }; main_mdio1_pins_default: main-mdio1-default-pins { @@ -106,6 +108,7 @@ AM62AX_IOPAD(0x160, PIN_OUTPUT, 0) /* (V12) MDIO0_MDC */ AM62AX_IOPAD(0x15c, PIN_INPUT, 0) /* (V13) MDIO0_MDIO */ >; + bootph-all; }; main_mmc0_pins_default: main-mmc0-default-pins { @@ -121,6 +124,7 @@ AM62AX_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (W9) MMC0_DAT6 */ AM62AX_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AB8) MMC0_DAT7 */ >; + bootph-all; }; main_rgmii1_pins_default: main-rgmii1-default-pins { @@ -138,6 +142,7 @@ AM62AX_IOPAD(0x130, PIN_OUTPUT, 0) /* (AB17) RGMII1_TXC */ AM62AX_IOPAD(0x12c, PIN_OUTPUT, 0) /* (W16) RGMII1_TX_CTL */ >; + bootph-all; }; ospi0_pins_default: ospi0-default-pins { @@ -155,6 +160,7 @@ AM62AX_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ AM62AX_IOPAD(0x008, PIN_INPUT, 0) /* (L21) OSPI0_DQS */ >; + bootph-all; }; pmic_irq_pins_default: pmic-irq-default-pins { @@ -165,14 +171,15 @@ }; &cpsw3g { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_rgmii1_pins_default>; + status = "okay"; }; &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy1>; + bootph-all; }; &cpsw3g_mdio { @@ -182,6 +189,7 @@ cpsw3g_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; reg = <1>; + bootph-all; ti,clk-output-sel = ; ti,rx-internal-delay = ; ti,fifo-depth = ; @@ -196,6 +204,7 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + bootph-all; status = "okay"; pmic@30 { @@ -215,8 +224,8 @@ interrupts = ; interrupt-controller; #interrupt-cells = <1>; - ti,power-button; system-power-controller; + ti,power-button; regulators { vdd_3v3: buck1 { @@ -302,6 +311,10 @@ status = "okay"; }; +&main_pktdma { + bootph-all; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; @@ -318,6 +331,7 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + bootph-all; }; }; @@ -326,5 +340,6 @@ pinctrl-0 = <&main_mmc0_pins_default>; disable-wp; non-removable; + bootph-all; status = "okay"; }; diff --git a/src/arm64/ti/k3-am62a7-sk.dts b/src/arm64/ti/k3-am62a7-sk.dts index a6f0d87a50d..1c9d95696c8 100644 --- a/src/arm64/ti/k3-am62a7-sk.dts +++ b/src/arm64/ti/k3-am62a7-sk.dts @@ -18,10 +18,13 @@ aliases { serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart0; serial3 = &main_uart1; mmc0 = &sdhci0; mmc1 = &sdhci1; + rtc0 = &wkup_rtc0; + rtc1 = &tps659312; }; chosen { @@ -655,6 +658,7 @@ }; &usb0 { + bootph-all; usb-role-switch; port { diff --git a/src/arm64/ti/k3-am62p-j722s-common-mcu.dtsi b/src/arm64/ti/k3-am62p-j722s-common-mcu.dtsi index b33aff0d65c..bd6a00d13ae 100644 --- a/src/arm64/ti/k3-am62p-j722s-common-mcu.dtsi +++ b/src/arm64/ti/k3-am62p-j722s-common-mcu.dtsi @@ -12,15 +12,7 @@ #pinctrl-cells = <1>; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; - pinctrl-single,gpio-range = - <&mcu_pmx_range 0 21 PIN_GPIO_RANGE_IOPAD>, - <&mcu_pmx_range 23 1 PIN_GPIO_RANGE_IOPAD>, - <&mcu_pmx_range 32 2 PIN_GPIO_RANGE_IOPAD>; bootph-all; - - mcu_pmx_range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; }; mcu_esm: esm@4100000 { diff --git a/src/arm64/ti/k3-am62p-j722s-common-wakeup.dtsi b/src/arm64/ti/k3-am62p-j722s-common-wakeup.dtsi index 6f32135f00a..6757b37a9de 100644 --- a/src/arm64/ti/k3-am62p-j722s-common-wakeup.dtsi +++ b/src/arm64/ti/k3-am62p-j722s-common-wakeup.dtsi @@ -2,9 +2,11 @@ /* * Device Tree file for the WAKEUP domain peripherals shared by AM62P and J722S * - * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/ + * Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/ */ +#include + &cbass_wakeup { wkup_conf: bus@43000000 { compatible = "simple-bus"; @@ -41,14 +43,34 @@ }; }; - wkup_uart0: serial@2b300000 { - compatible = "ti,am64-uart", "ti,am654-uart"; - reg = <0x00 0x2b300000 0x00 0x100>; - interrupts = ; + target-module@2b300050 { + compatible = "ti,sysc-omap2", "ti,sysc"; + reg = <0 0x2b300050 0 0x4>, + <0 0x2b300054 0 0x4>, + <0 0x2b300058 0 0x4>; + reg-names = "rev", "sysc", "syss"; + ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP | + SYSC_OMAP2_SOFTRESET | + SYSC_OMAP2_AUTOIDLE)>; + ti,sysc-sidle = , + , + , + ; + ti,syss-mask = <1>; + ti,no-reset-on-init; power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 114 0>; - clock-names = "fclk"; - status = "disabled"; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x2b300000 0x100000>; + + wkup_uart0: serial@0 { + compatible = "ti,am64-uart", "ti,am654-uart"; + reg = <0 0x100>; + interrupts = ; + status = "disabled"; + }; }; wkup_i2c0: i2c@2b200000 { diff --git a/src/arm64/ti/k3-am62p-main.dtsi b/src/arm64/ti/k3-am62p-main.dtsi index 420c77c8e9e..6aea9d3f134 100644 --- a/src/arm64/ti/k3-am62p-main.dtsi +++ b/src/arm64/ti/k3-am62p-main.dtsi @@ -42,17 +42,23 @@ ti,interrupt-ranges = <5 69 35>; }; -&main_pmx0 { - pinctrl-single,gpio-range = - <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 72 22 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>; +&main_conf { + audio_refclk0: clock-controller@82e0 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e0 0x4>; + clocks = <&k3_clks 157 0>; + assigned-clocks = <&k3_clks 157 0>; + assigned-clock-parents = <&k3_clks 157 16>; + #clock-cells = <0>; + }; - main_pmx0_range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; + audio_refclk1: clock-controller@82e4 { + compatible = "ti,am62-audio-refclk"; + reg = <0x82e4 0x4>; + clocks = <&k3_clks 157 18>; + assigned-clocks = <&k3_clks 157 18>; + assigned-clock-parents = <&k3_clks 157 34>; + #clock-cells = <0>; }; }; diff --git a/src/arm64/ti/k3-am62p5-sk.dts b/src/arm64/ti/k3-am62p5-sk.dts index ad71d2f27f5..d29f524600a 100644 --- a/src/arm64/ti/k3-am62p5-sk.dts +++ b/src/arm64/ti/k3-am62p5-sk.dts @@ -19,6 +19,7 @@ aliases { serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart0; serial3 = &main_uart1; mmc0 = &sdhci0; @@ -310,7 +311,7 @@ main_usb1_pins_default: main-usb1-default-pins { pinctrl-single,pins = < - AM62PX_IOPAD(0x0258, PIN_INPUT, 0) /* (G21) USB1_DRVVBUS */ + AM62PX_IOPAD(0x0258, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (G21) USB1_DRVVBUS */ >; }; @@ -519,6 +520,7 @@ }; &usb0 { + bootph-all; usb-role-switch; port { diff --git a/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi b/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi index 922cad14c9f..aab74d6019b 100644 --- a/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi +++ b/src/arm64/ti/k3-am62x-phyboard-lyra.dtsi @@ -138,6 +138,7 @@ regulator-max-microvolt = <3300000>; regulator-always-on; regulator-boot-on; + bootph-all; }; vcc_3v3_sw: regulator-vcc-3v3-sw { @@ -233,6 +234,7 @@ AM62X_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (D22) MMC1_DAT3 */ AM62X_IOPAD(0x240, PIN_INPUT_PULLUP, 0) /* (D17) MMC1_SDCD */ >; + bootph-all; }; main_rgmii2_pins_default: main-rgmii2-default-pins { @@ -257,6 +259,7 @@ AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ >; + bootph-all; }; main_uart1_pins_default: main-uart1-default-pins { @@ -266,6 +269,7 @@ AM62X_IOPAD(0x1ac, PIN_INPUT, 2) /* (E19) MCASP0_AFSR.UART1_RXD */ AM62X_IOPAD(0x1b0, PIN_OUTPUT, 2) /* (A20) MCASP0_ACLKR.UART1_TXD */ >; + bootph-pre-ram; }; main_usb1_pins_default: main-usb1-default-pins { @@ -430,12 +434,14 @@ &main_uart0 { pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; status = "okay"; }; &main_uart1 { pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; + bootph-pre-ram; /* Main UART1 may be used by TIFS firmware */ status = "okay"; }; @@ -467,11 +473,13 @@ pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; no-1-8-v; + bootph-all; status = "okay"; }; &usbss0 { ti,vbus-divider; + bootph-all; status = "okay"; }; @@ -482,6 +490,7 @@ &usb0 { usb-role-switch; + bootph-all; port { typec_hs: endpoint { diff --git a/src/arm64/ti/k3-am62x-sk-common.dtsi b/src/arm64/ti/k3-am62x-sk-common.dtsi index 2f129e8cd5b..d52cb2a5a58 100644 --- a/src/arm64/ti/k3-am62x-sk-common.dtsi +++ b/src/arm64/ti/k3-am62x-sk-common.dtsi @@ -12,6 +12,8 @@ / { aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart0; mmc0 = &sdhci0; mmc1 = &sdhci1; diff --git a/src/arm64/ti/k3-am64-phycore-som.dtsi b/src/arm64/ti/k3-am64-phycore-som.dtsi index 99a6fdfaa7f..d9d491b12c3 100644 --- a/src/arm64/ti/k3-am64-phycore-som.dtsi +++ b/src/arm64/ti/k3-am64-phycore-som.dtsi @@ -27,6 +27,7 @@ memory@80000000 { device_type = "memory"; reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + bootph-all; }; reserved_memory: reserved-memory { @@ -99,6 +100,12 @@ reg = <0x00 0xa4100000 0x00 0xf00000>; no-map; }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; }; leds { @@ -132,6 +139,7 @@ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ AM64X_IOPAD(0x0100, PIN_OUTPUT, 7) /* (V7) PRG1_PRU0_GPO18.GPIO0_63 */ >; + bootph-all; }; cpsw_rgmii1_pins_default: cpsw-rgmii1-default-pins { @@ -150,6 +158,7 @@ AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ AM64X_IOPAD(0x0154, PIN_INPUT, 7) /* (V12) PRG1_PRU1_GPO19.GPIO0_84 */ >; + bootph-all; }; eeprom_wp_pins_default: eeprom-wp-default-pins { @@ -169,6 +178,7 @@ AM64X_IOPAD(0x0260, PIN_INPUT, 0) /* (A18) I2C0_SCL */ AM64X_IOPAD(0x0264, PIN_INPUT, 0) /* (B18) I2C0_SDA */ >; + bootph-all; }; ospi0_pins_default: ospi0-default-pins { @@ -185,6 +195,7 @@ AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ >; + bootph-all; }; rtc_pins_default: rtc-defaults-pins { @@ -201,26 +212,29 @@ }; &cpsw3g_mdio { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&cpsw_mdio_pins_default>; + bootph-all; + status = "okay"; cpsw3g_phy1: ethernet-phy@1 { compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; reg = <1>; interrupt-parent = <&main_gpio0>; interrupts = <84 IRQ_TYPE_EDGE_FALLING>; - ti,rx-internal-delay = ; - ti,fifo-depth = ; reset-gpios = <&main_gpio0 63 GPIO_ACTIVE_LOW>; reset-assert-us = <1000>; reset-deassert-us = <1000>; + bootph-all; + ti,rx-internal-delay = ; + ti,fifo-depth = ; }; }; &cpsw_port1 { phy-mode = "rgmii-rxid"; phy-handle = <&cpsw3g_phy1>; + bootph-all; status = "okay"; }; @@ -262,10 +276,11 @@ }; &main_i2c0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_pins_default>; clock-frequency = <400000>; + bootph-all; + status = "okay"; eeprom@50 { compatible = "atmel,24c32"; @@ -330,6 +345,10 @@ }; }; +&main_pktdma { + bootph-all; +}; + &main_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; memory-region = <&main_r5fss0_core0_dma_memory_region>, @@ -362,9 +381,9 @@ }; &ospi0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; + status = "okay"; serial_flash: flash@0 { compatible = "jedec,spi-nor"; @@ -377,15 +396,17 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <0>; + bootph-all; }; }; &sdhci0 { - status = "okay"; non-removable; ti,driver-strength-ohm = <50>; disable-wp; keep-power-in-suspend; + bootph-all; + status = "okay"; }; &tscadc0 { diff --git a/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts b/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts index bc8e1ce1104..f63c101b7d6 100644 --- a/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts +++ b/src/arm64/ti/k3-am642-phyboard-electra-rdk.dts @@ -171,6 +171,7 @@ regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; + bootph-all; }; }; @@ -275,6 +276,7 @@ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ >; + bootph-all; }; main_spi0_pins_default: main-spi0-default-pins { @@ -291,6 +293,7 @@ AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ >; + bootph-all; }; main_uart1_pins_default: main-uart1-default-pins { @@ -349,10 +352,10 @@ }; &main_i2c1 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; + status = "okay"; eeprom@51 { compatible = "atmel,24c02"; @@ -382,25 +385,25 @@ }; &main_mcan0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan0_pins_default>; phys = <&can_tc1>; + status = "okay"; }; &main_mcan1 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mcan1_pins_default>; phys = <&can_tc2>; + status = "okay"; }; &main_spi0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_spi0_pins_default>; cs-gpios = <0>, <&main_gpio1 43 GPIO_ACTIVE_LOW>; ti,pindir-d0-out-d1-in; + status = "okay"; tpm@1 { compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; @@ -410,25 +413,27 @@ }; &main_uart0 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; + bootph-all; + status = "okay"; }; &main_uart1 { - status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; uart-has-rtscts; + status = "okay"; }; &sdhci1 { - status = "okay"; vmmc-supply = <&vcc_3v3_mmc>; pinctrl-names = "default"; pinctrl-0 = <&main_mmc1_pins_default>; disable-wp; no-1-8-v; + bootph-all; + status = "okay"; }; &serdes0 { diff --git a/src/arm64/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso b/src/arm64/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso new file mode 100644 index 00000000000..996c42ec425 --- /dev/null +++ b/src/arm64/ti/k3-am642-phyboard-electra-x27-gpio1-spi1-uart3.dtso @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Authors: + * Wadim Egorov + * Daniel Schultz + * + * GPIO, SPI and UART examples for the X27 expansion connector. + */ + +/dts-v1/; +/plugin/; + +#include "k3-pinctrl.h" + +&{/} { + aliases { + serial5 = "/bus@f4000/serial@2830000"; + }; +}; + +&main_pmx0 { + main_gpio1_exp_header_gpio_pins_default: main-gpio1-exp-header-gpio-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0220, PIN_INPUT, 7) /* (D14) SPI1_CS1.GPIO1_48 */ + >; + }; + + main_spi1_pins_default: main-spi1-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0224, PIN_INPUT, 0) /* (C14) SPI1_CLK */ + AM64X_IOPAD(0x021C, PIN_OUTPUT, 0) /* (B14) SPI1_CS0 */ + AM64X_IOPAD(0x0228, PIN_OUTPUT, 0) /* (B15) SPI1_D0 */ + AM64X_IOPAD(0x022C, PIN_INPUT, 0) /* (A15) SPI1_D1 */ + >; + }; + + main_uart3_pins_default: main-uart3-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x0048, PIN_INPUT, 2) /* (U20) GPMC0_AD3.UART3_RXD */ + AM64X_IOPAD(0x004c, PIN_OUTPUT, 2) /* (U18) GPMC0_AD4.UART3_TXD */ + >; + }; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_exp_header_gpio_pins_default>; + status = "okay"; +}; + +&main_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_spi1_pins_default>; + ti,pindir-d0-out-d1-in = <1>; + status = "okay"; +}; + +&main_uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&main_uart3_pins_default>; + status = "okay"; +}; diff --git a/src/arm64/ti/k3-j721e-common-proc-board.dts b/src/arm64/ti/k3-j721e-common-proc-board.dts index 4c1e02a4e7a..4421852161d 100644 --- a/src/arm64/ti/k3-j721e-common-proc-board.dts +++ b/src/arm64/ti/k3-j721e-common-proc-board.dts @@ -540,6 +540,7 @@ #phy-cells = <0>; cdns,phy-type = ; resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; + bootph-all; }; }; diff --git a/src/arm64/ti/k3-j721e-sk.dts b/src/arm64/ti/k3-j721e-sk.dts index 69b3d1ed8a2..440ef57be29 100644 --- a/src/arm64/ti/k3-j721e-sk.dts +++ b/src/arm64/ti/k3-j721e-sk.dts @@ -1040,6 +1040,7 @@ #phy-cells = <0>; cdns,phy-type = ; resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; + bootph-all; }; }; diff --git a/src/arm64/ti/k3-j721s2-som-p0.dtsi b/src/arm64/ti/k3-j721s2-som-p0.dtsi index b3a0385ed3d..54fc5c4f8c3 100644 --- a/src/arm64/ti/k3-j721s2-som-p0.dtsi +++ b/src/arm64/ti/k3-j721s2-som-p0.dtsi @@ -448,6 +448,47 @@ cdns,tchsh-ns = <60>; cdns,tslch-ns = <60>; cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; }; }; diff --git a/src/arm64/ti/k3-j722s-evm.dts b/src/arm64/ti/k3-j722s-evm.dts index d184e9c1a0a..2127316f36a 100644 --- a/src/arm64/ti/k3-j722s-evm.dts +++ b/src/arm64/ti/k3-j722s-evm.dts @@ -263,6 +263,13 @@ bootph-all; }; + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins = < + J722S_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ + J722S_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ + >; + }; + main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J722S_IOPAD(0x01c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ @@ -590,7 +597,7 @@ p05-hog { /* P05 - USB2.0_MUX_SEL */ gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; + gpios = <5 GPIO_ACTIVE_LOW>; output-high; }; @@ -631,6 +638,27 @@ }; }; +&main_i2c2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c2_pins_default>; + clock-frequency = <400000>; + + pca9543_0: i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + }; + + pca9543_1: i2c-mux@71 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + }; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&ospi0_pins_default>; diff --git a/src/arm64/ti/k3-j722s-main.dtsi b/src/arm64/ti/k3-j722s-main.dtsi index 3ac2d45a055..6850f50530f 100644 --- a/src/arm64/ti/k3-j722s-main.dtsi +++ b/src/arm64/ti/k3-j722s-main.dtsi @@ -154,6 +154,189 @@ }; }; + ti_csi2rx1: ticsi2rx@30122000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30122000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x5100 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@30121000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30121000 0x00 0x1000>; + clocks = <&k3_clks 247 0>, <&k3_clks 247 3>, <&k3_clks 247 0>, + <&k3_clks 247 0>, <&k3_clks 247 4>, <&k3_clks 247 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@30142000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30142000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; + dmas = <&main_bcdma_csi 0 0x5200 0>; + dma-names = "rx0"; + status = "disabled"; + + cdns_csi2rx2: csi-bridge@30141000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30141000 0x00 0x1000>; + clocks = <&k3_clks 248 0>, <&k3_clks 248 3>, <&k3_clks 248 0>, + <&k3_clks 248 0>, <&k3_clks 248 4>, <&k3_clks 248 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy2>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi2_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi2_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi2_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi2_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx3: ticsi2rx@30162000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x30162000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x5300 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx3: csi-bridge@30161000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x30161000 0x00 0x1000>; + clocks = <&k3_clks 249 0>, <&k3_clks 249 3>, <&k3_clks 249 0>, + <&k3_clks 249 0>, <&k3_clks 249 4>, <&k3_clks 249 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy3>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi3_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi3_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi3_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi3_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi3_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy1: phy@30130000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30130000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy2: phy@30150000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30150000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy3: phy@30170000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x30170000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + main_r5fss0: r5fss@78400000 { compatible = "ti,am62-r5fss"; #address-cells = <1>; @@ -204,6 +387,16 @@ }; }; +&main_bcdma_csi { + compatible = "ti,j722s-dmss-bcdma-csi"; + reg = <0x00 0x4e230000 0x00 0x100>, + <0x00 0x4e180000 0x00 0x20000>, + <0x00 0x4e300000 0x00 0x10000>, + <0x00 0x4e100000 0x00 0x80000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + ti,sci-rm-range-tchan = <0x22>; +}; + /* MCU domain overrides */ &mcu_r5fss0_core0 { @@ -251,21 +444,6 @@ ti,interrupt-ranges = <7 71 21>; }; -&main_pmx0 { - pinctrl-single,gpio-range = - <&main_pmx0_range 0 32 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 33 38 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 72 17 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 101 25 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 137 5 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 143 3 PIN_GPIO_RANGE_IOPAD>, - <&main_pmx0_range 149 2 PIN_GPIO_RANGE_IOPAD>; - - main_pmx0_range: gpio-range { - #pinctrl-single,gpio-range-cells = <3>; - }; -}; - &main_gpio0 { gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>, <&main_pmx0 70 72 17>; diff --git a/src/arm64/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso b/src/arm64/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso index dcd2c7c39ec..c1f9573557d 100644 --- a/src/arm64/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso +++ b/src/arm64/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso @@ -102,13 +102,6 @@ gpios = <16 GPIO_ACTIVE_HIGH>; output-low; }; - - /* Toggle MUX2 for MDIO lines */ - mux-sel-hog { - gpio-hog; - gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>; - output-high; - }; }; &main_pmx0 { diff --git a/src/arm64/ti/k3-j784s4-j742s2-main-common.dtsi b/src/arm64/ti/k3-j784s4-j742s2-main-common.dtsi index 83bbf94b58d..1944616ab35 100644 --- a/src/arm64/ti/k3-j784s4-j742s2-main-common.dtsi +++ b/src/arm64/ti/k3-j784s4-j742s2-main-common.dtsi @@ -84,7 +84,9 @@ <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ - <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */ + <0x28 0x3>, <0x2c 0x3>, /* SERDES2 lane2/3 select */ + <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */ + <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */ idle-states = , , , @@ -193,7 +195,7 @@ ranges; #interrupt-cells = <3>; interrupt-controller; - reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ + reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ <0x00 0x01900000 0x00 0x100000>, /* GICR */ <0x00 0x6f000000 0x00 0x2000>, /* GICC */ <0x00 0x6f010000 0x00 0x1000>, /* GICH */ diff --git a/src/arm64/xilinx/versal-net-clk.dtsi b/src/arm64/xilinx/versal-net-clk.dtsi new file mode 100644 index 00000000000..b7a8a1a512c --- /dev/null +++ b/src/arm64/xilinx/versal-net-clk.dtsi @@ -0,0 +1,231 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET fixed clock + * + * (C) Copyright 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +/ { + clk60: clk60 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <60000000>; + }; + + clk100: clk100 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + clk125: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk150: clk150 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <150000000>; + }; + + clk160: clk160 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <160000000>; + }; + + clk200: clk200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + clk250: clk250 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + + clk300: clk300 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <300000000>; + }; + + clk450: clk450 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <450000000>; + }; + + clk1200: clk1200 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1200000000>; + }; + + firmware { + versal_net_firmware: versal-net-firmware { + compatible = "xlnx,versal-net-firmware", "xlnx,versal-firmware"; + bootph-all; + method = "smc"; + }; + }; +}; + +&adma0 { + clocks = <&clk450>, <&clk450>; +}; + +&adma1 { + clocks = <&clk450>, <&clk450>; +}; + +&adma2 { + clocks = <&clk450>, <&clk450>; +}; + +&adma3 { + clocks = <&clk450>, <&clk450>; +}; + +&adma4 { + clocks = <&clk450>, <&clk450>; +}; + +&adma5 { + clocks = <&clk450>, <&clk450>; +}; + +&adma6 { + clocks = <&clk450>, <&clk450>; +}; + +&adma7 { + clocks = <&clk450>, <&clk450>; +}; + +&can0 { + clocks = <&clk160>, <&clk160>; +}; + +&can1 { + clocks = <&clk160>, <&clk160>; +}; + +&gem0 { + clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; +}; + +&gem1 { + clocks = <&clk125>, <&clk125>, <&clk125>, <&clk125>, <&clk250>; +}; + +&gpio0 { + clocks = <&clk100>; +}; + +&gpio1 { + clocks = <&clk100>; +}; + +&i2c0 { + clocks = <&clk100>; +}; + +&i2c1 { + clocks = <&clk100>; +}; + +&i3c0 { + clocks = <&clk100>; +}; + +&i3c1 { + clocks = <&clk100>; +}; + +&ospi { + clocks = <&clk200>; +}; + +&qspi { + clocks = <&clk300>, <&clk300>; +}; + +&rtc { + /* Nothing */ +}; + +&sdhci0 { + clocks = <&clk200>, <&clk200>, <&clk1200>; +}; + +&sdhci1 { + clocks = <&clk200>, <&clk200>, <&clk1200>; +}; + +&serial0 { + clocks = <&clk100>, <&clk100>; +}; + +&serial1 { + clocks = <&clk100>, <&clk100>; +}; + +&spi0 { + clocks = <&clk200>, <&clk200>; +}; + +&spi1 { + clocks = <&clk200>, <&clk200>; +}; + +&ttc0 { + clocks = <&clk150>; +}; + +&usb0 { + clocks = <&clk60>, <&clk60>; +}; + +&dwc3_0 { + clocks = <&clk60>; +}; + +&usb1 { + clocks = <&clk60>, <&clk60>; +}; + +&dwc3_1 { + clocks = <&clk60>; +}; + +&wwdt0 { + clocks = <&clk150>; +}; + +&wwdt1 { + clocks = <&clk150>; +}; + +&wwdt2 { + clocks = <&clk150>; +}; + +&wwdt3 { + clocks = <&clk150>; +}; + +&lpd_wwdt0 { + clocks = <&clk150>; +}; + +&lpd_wwdt1 { + clocks = <&clk150>; +}; diff --git a/src/arm64/xilinx/versal-net-vn-x-b2197-01-revA.dts b/src/arm64/xilinx/versal-net-vn-x-b2197-01-revA.dts new file mode 100644 index 00000000000..06b2301f48a --- /dev/null +++ b/src/arm64/xilinx/versal-net-vn-x-b2197-01-revA.dts @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal Net VNX board revA + * + * (C) Copyright 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +#include "versal-net.dtsi" +#include "versal-net-clk.dtsi" +#include + +/ { + compatible = "xlnx,versal-net-vnx-revA", "xlnx,versal-net-vnx", "xlnx,versal-net"; + model = "Xilinx Versal NET VNX revA"; + dma-coherent; + + memory: memory@0 { + reg = <0 0 0 0x80000000>; + device_type = "memory"; + }; + + memory_hi: memory@800000000 { + reg = <8 0 3 0x80000000>; + device_type = "memory"; + }; + + memory_hi2: memory@50000000000 { + reg = <0x500 0 4 0>; + device_type = "memory"; + }; + + chosen { + bootargs = "console=ttyAMA1,115200n8"; + stdout-path = "serial1:115200n8"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + rsc_tbl_carveout: rproc@bbf14000 { + reg = <0 0xbbf14000 0 0x1000>; + no-map; + }; + rpu0vdev0vring0: rpu0vdev0vring0@bbf15000 { + reg = <0 0xbbf15000 0 0x1000>; + no-map; + }; + rpu0vdev0vring1: rpu0vdev0vring1@bbf16000 { + reg = <0 0xbbf16000 0 0x1000>; + no-map; + }; + rpu0vdev0buffer: rpu0vdev0buffer@bbf17000 { + reg = <0 0xbbf17000 0 0xD000>; + no-map; + }; + reserve_others: reserveothers@0 { + reg = <0 0x0 0 0x1c200000>; + no-map; + }; + pdi_update: pdiupdate@1c200000 { + reg = <0 0x1c200000 0 0x6000000>; + no-map; + }; + reserve_optee_atf: reserveopteeatf@22200000 { + reg = <0 0x22200000 0 0x4100000>; + no-map; + }; + }; +}; + +&gem1 { + status = "okay"; + iommus = <&smmu 0x235>; + phy-handle = <&phy>; + phy-mode = "rmii"; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy: ethernet-phy@4 { + reg = <4>; + }; + }; +}; + +&ospi { + num-cs = <2>; + iommus = <&smmu 0x245>; + #address-cells = <1>; + #size-cells = <0>; +}; + +&sdhci1 { + status = "okay"; + iommus = <&smmu 0x243>; + non-removable; + disable-wp; + no-sd; + no-sdio; + cap-mmc-hw-reset; + bus-width = <8>; + no-1-8-v; +}; + +&serial1 { + status = "okay"; +}; + +&smmu { + status = "okay"; +}; diff --git a/src/arm64/xilinx/versal-net.dtsi b/src/arm64/xilinx/versal-net.dtsi new file mode 100644 index 00000000000..fc9f49e5738 --- /dev/null +++ b/src/arm64/xilinx/versal-net.dtsi @@ -0,0 +1,752 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * dts file for Xilinx Versal NET + * + * (C) Copyright 2022, Xilinx, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. + * + * Michal Simek + */ + +/dts-v1/; + +/ { + compatible = "xlnx,versal-net"; + model = "Xilinx Versal NET"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&gic>; + + options { + u-boot { + compatible = "u-boot,config"; + bootscr-address = /bits/ 64 <0x20000000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu100>; + }; + core2 { + cpu = <&cpu200>; + }; + core3 { + cpu = <&cpu300>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu10000>; + }; + + core1 { + cpu = <&cpu10100>; + }; + + core2 { + cpu = <&cpu10200>; + }; + + core3 { + cpu = <&cpu10300>; + }; + }; + cluster2 { + core0 { + cpu = <&cpu20000>; + }; + + core1 { + cpu = <&cpu20100>; + }; + + core2 { + cpu = <&cpu20200>; + }; + + core3 { + cpu = <&cpu20300>; + }; + }; + cluster3 { + core0 { + cpu = <&cpu30000>; + }; + + core1 { + cpu = <&cpu30100>; + }; + + core2 { + cpu = <&cpu30200>; + }; + + core3 { + cpu = <&cpu30300>; + }; + }; + + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu100: cpu@100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x100>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu200: cpu@200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x200>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu300: cpu@300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x300>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu10000: cpu@10000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x10000>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu10100: cpu@10100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x10100>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu10200: cpu@10200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x10200>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu10300: cpu@10300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x10300>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu20000: cpu@20000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x20000>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu20100: cpu@20100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x20100>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu20200: cpu@20200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x20200>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu20300: cpu@20300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x20300>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu30000: cpu@30000 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x30000>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu30100: cpu@30100 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x30100>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu30200: cpu@30200 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x30200>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + cpu30300: cpu@30300 { + compatible = "arm,cortex-a78"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x30300>; + operating-points-v2 = <&cpu_opp_table>; + cpu-idle-states = <&CPU_SLEEP_0>; + }; + idle-states { + entry-method = "psci"; + + CPU_SLEEP_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x40000000>; + local-timer-stop; + entry-latency-us = <300>; + exit-latency-us = <600>; + min-residency-us = <10000>; + }; + }; + }; + + cpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-1066000000 { + opp-hz = /bits/ 64 <1066000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-1866000000 { + opp-hz = /bits/ 64 <1866000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-1900000000 { + opp-hz = /bits/ 64 <1900000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-1999000000 { + opp-hz = /bits/ 64 <1999000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-2050000000 { + opp-hz = /bits/ 64 <2050000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-2100000000 { + opp-hz = /bits/ 64 <2100000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-2200000000 { + opp-hz = /bits/ 64 <2200000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <500000>; + }; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &dcc; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + i2c0 = &i2c0; + i2c1 = &i2c1; + rtc = &rtc; + usb0 = &usb0; + usb1 = &usb1; + spi0 = &ospi; + spi1 = &qspi; + }; + + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; + bootph-all; + }; + + firmware { + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + fpga: fpga-region { + compatible = "fpga-region"; + fpga-mgr = <&versal_fpga>; + #address-cells = <2>; + #size-cells = <2>; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 4>, <1 14 4>, <1 11 4>, <1 10 4>; + }; + + versal_fpga: versal-fpga { + compatible = "xlnx,versal-fpga"; + }; + + amba: axi { + compatible = "simple-bus"; + bootph-all; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + adma0: dma-controller@ebd00000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd00000 0 0x1000>; + interrupts = <0 72 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma1: dma-controller@ebd10000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd10000 0 0x1000>; + interrupts = <0 73 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma2: dma-controller@ebd20000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd20000 0 0x1000>; + interrupts = <0 74 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma3: dma-controller@ebd30000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd30000 0 0x1000>; + interrupts = <0 75 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma4: dma-controller@ebd40000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd40000 0 0x1000>; + interrupts = <0 76 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma5: dma-controller@ebd50000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd50000 0 0x1000>; + interrupts = <0 77 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma6: dma-controller@ebd60000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd60000 0 0x1000>; + interrupts = <0 78 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + adma7: dma-controller@ebd70000 { + compatible = "xlnx,zynqmp-dma-1.0"; + status = "disabled"; + reg = <0 0xebd70000 0 0x1000>; + interrupts = <0 79 4>; + clock-names = "clk_main", "clk_apb"; + #dma-cells = <1>; + xlnx,bus-width = <64>; + }; + + can0: can@f1980000 { + compatible = "xlnx,canfd-2.0"; + status = "disabled"; + reg = <0 0xf1980000 0 0x6000>; + interrupts = <0 27 4>; + clock-names = "can_clk", "s_axi_aclk"; + rx-fifo-depth = <64>; + tx-mailbox-count = <32>; + }; + + can1: can@f1990000 { + compatible = "xlnx,canfd-2.0"; + status = "disabled"; + reg = <0 0xf1990000 0 0x6000>; + interrupts = <0 28 4>; + clock-names = "can_clk", "s_axi_aclk"; + rx-fifo-depth = <64>; + tx-mailbox-count = <32>; + }; + + gem0: ethernet@f19e0000 { + compatible = "xlnx,versal-gem", "cdns,gem"; + status = "disabled"; + reg = <0 0xf19e0000 0 0x1000>; + interrupts = <0 39 4>, <0 39 4>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", + "tsu_clk"; + }; + + gem1: ethernet@f19f0000 { + compatible = "xlnx,versal-gem", "cdns,gem"; + status = "disabled"; + reg = <0 0xf19f0000 0 0x1000>; + interrupts = <0 41 4>, <0 41 4>; + clock-names = "pclk", "hclk", "tx_clk", "rx_clk", + "tsu_clk"; + }; + + gic: interrupt-controller@e2000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + reg = <0 0xe2000000 0 0x10000>, + <0 0xe2060000 0 0x200000>; + interrupt-controller; + interrupts = <1 9 4>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + its: msi-controller@e2040000 { + compatible = "arm,gic-v3-its"; + msi-controller; + #msi-cells = <1>; + reg = <0 0xe2040000 0 0x20000>; + }; + }; + + gpio0: gpio@f19d0000 { + compatible = "xlnx,versal-gpio-1.0"; + status = "disabled"; + reg = <0 0xf19d0000 0 0x1000>; + interrupts = <0 20 4>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + gpio1: gpio@f1020000 { + compatible = "xlnx,pmc-gpio-1.0"; + status = "disabled"; + reg = <0 0xf1020000 0 0x1000>; + interrupts = <0 180 4>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; + + i2c0: i2c@f1940000 { + compatible = "cdns,i2c-r1p14"; + status = "disabled"; + reg = <0 0xf1940000 0 0x1000>; + interrupts = <0 21 4>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@f1950000 { + compatible = "cdns,i2c-r1p14"; + status = "disabled"; + reg = <0 0xf1950000 0 0x1000>; + interrupts = <0 22 4>; + clock-frequency = <400000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i3c0: i3c@f1948000 { + compatible = "snps,dw-i3c-master-1.00a"; + status = "disabled"; + reg = <0 0xf1948000 0 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + interrupts = <0 21 4>; + }; + + i3c1: i3c@f1958000 { + compatible = "snps,dw-i3c-master-1.00a"; + status = "disabled"; + reg = <0 0xf1958000 0 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + interrupts = <0 22 4>; + }; + + ospi: spi@f1010000 { + compatible = "xlnx,versal-ospi-1.0", "cdns,qspi-nor"; + status = "disabled"; + reg = <0 0xf1010000 0 0x10000>, + <0 0xc0000000 0 0x20000000>; + interrupts = <0 182 4>; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,is-dma = <1>; /* u-boot specific */ + cdns,trigger-address = <0xc0000000>; + }; + + qspi: spi@f1030000 { + compatible = "xlnx,versal-qspi-1.0"; + status = "disabled"; + reg = <0 0xf1030000 0 0x1000>; + interrupts = <0 183 4>; + clock-names = "ref_clk", "pclk"; + }; + + rtc: rtc@f12a0000 { + compatible = "xlnx,zynqmp-rtc"; + status = "disabled"; + reg = <0 0xf12a0000 0 0x100>; + interrupts = <0 200 4>, <0 201 4>; + interrupt-names = "alarm", "sec"; + calibration = <0x8000>; + }; + + sdhci0: mmc@f1040000 { + compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; + status = "disabled"; + reg = <0 0xf1040000 0 0x10000>; + interrupts = <0 184 4>; + clock-names = "clk_xin", "clk_ahb", "gate"; + #clock-cells = <1>; + clock-output-names = "clk_out_sd0", "clk_in_sd0"; + }; + + sdhci1: mmc@f1050000 { + compatible = "xlnx,versal-net-emmc"; + status = "disabled"; + reg = <0 0xf1050000 0 0x10000>; + interrupts = <0 186 4>; + clock-names = "clk_xin", "clk_ahb", "gate"; + #clock-cells = <1>; + clock-output-names = "clk_out_sd1", "clk_in_sd1"; + }; + + serial0: serial@f1920000 { + bootph-all; + compatible = "arm,pl011", "arm,primecell"; + status = "disabled"; + reg = <0 0xf1920000 0 0x1000>; + interrupts = <0 25 4>; + reg-io-width = <4>; + clock-names = "uartclk", "apb_pclk"; + }; + + serial1: serial@f1930000 { + bootph-all; + compatible = "arm,pl011", "arm,primecell"; + status = "disabled"; + reg = <0 0xf1930000 0 0x1000>; + interrupts = <0 26 4>; + reg-io-width = <4>; + clock-names = "uartclk", "apb_pclk"; + }; + + smmu: iommu@ec000000 { + compatible = "arm,smmu-v3"; + status = "disabled"; + reg = <0 0xec000000 0 0x40000>; + #iommu-cells = <1>; + interrupt-names = "combined"; + interrupts = <0 169 4>; + dma-coherent; + }; + + spi0: spi@f1960000 { + compatible = "cdns,spi-r1p6"; + status = "disabled"; + interrupts = <0 23 4>; + reg = <0 0xf1960000 0 0x1000>; + clock-names = "ref_clk", "pclk"; + }; + + spi1: spi@f1970000 { + compatible = "cdns,spi-r1p6"; + status = "disabled"; + interrupts = <0 24 4>; + reg = <0 0xf1970000 0 0x1000>; + clock-names = "ref_clk", "pclk"; + }; + + ttc0: timer@f1dc0000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <0 43 4>, <0 44 4>, <0 45 4>; + timer-width = <32>; + reg = <0x0 0xf1dc0000 0x0 0x1000>; + }; + + ttc1: timer@f1dd0000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <0 46 4>, <0 47 4>, <0 48 4>; + timer-width = <32>; + reg = <0x0 0xf1dd0000 0x0 0x1000>; + }; + + ttc2: timer@f1de0000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <0 49 4>, <0 50 4>, <0 51 4>; + timer-width = <32>; + reg = <0x0 0xf1de0000 0x0 0x1000>; + }; + + ttc3: timer@f1df0000 { + compatible = "cdns,ttc"; + status = "disabled"; + interrupts = <0 52 4>, <0 53 4>, <0 54 4>; + timer-width = <32>; + reg = <0x0 0xf1df0000 0x0 0x1000>; + }; + + usb0: usb@f1e00000 { + compatible = "xlnx,versal-dwc3"; + status = "disabled"; + reg = <0 0xf1e00000 0 0x100>; + clock-names = "bus_clk", "ref_clk"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + dwc3_0: usb@f1b00000 { + compatible = "snps,dwc3"; + status = "disabled"; + reg = <0 0xf1b00000 0 0x10000>; + interrupt-names = "host", "peripheral", "otg", "wakeup"; + interrupts = <0 29 4>, <0 29 4>, <0 33 4>, <0 98 4>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + dr_mode = "peripheral"; + maximum-speed = "high-speed"; + snps,usb3_lpm_capable; + clock-names = "ref"; + }; + }; + + usb1: usb@f1e10000 { + compatible = "xlnx,versal-dwc3"; + status = "disabled"; + reg = <0x0 0xf1e10000 0x0 0x100>; + clock-names = "bus_clk", "ref_clk"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + dwc3_1: usb@f1c00000 { + compatible = "snps,dwc3"; + status = "disabled"; + reg = <0x0 0xf1c00000 0x0 0x10000>; + interrupt-names = "host", "peripheral", "otg", "wakeup"; + interrupts = <0 34 4>, <0 34 4>, <0 38 4>, <0 99 4>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + dr_mode = "host"; + maximum-speed = "high-speed"; + snps,usb3_lpm_capable; + clock-names = "ref"; + }; + }; + + wwdt0: watchdog@ecc10000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xecc10000 0 0x10000>; + timeout-sec = <30>; + }; + + wwdt1: watchdog@ecd10000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xecd10000 0 0x10000>; + timeout-sec = <30>; + }; + + wwdt2: watchdog@ece10000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xece10000 0 0x10000>; + timeout-sec = <30>; + }; + + wwdt3: watchdog@ecf10000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xecf10000 0 0x10000>; + timeout-sec = <30>; + }; + + lpd_wwdt0: watchdog@ea420000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xea420000 0 0x10000>; + timeout-sec = <30>; + }; + + lpd_wwdt1: watchdog@ea430000 { + compatible = "xlnx,versal-wwdt"; + status = "disabled"; + reg = <0 0xea430000 0 0x10000>; + timeout-sec = <30>; + }; + }; +}; diff --git a/src/arm64/xilinx/xlnx-zynqmp-clk.h b/src/arm64/xilinx/xlnx-zynqmp-clk.h new file mode 100644 index 00000000000..0aa17f2a281 --- /dev/null +++ b/src/arm64/xilinx/xlnx-zynqmp-clk.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Xilinx Zynq MPSoC Firmware layer + * + * Copyright (C) 2014-2018 Xilinx, Inc. + * + */ + +#ifndef _XLNX_ZYNQMP_CLK_H +#define _XLNX_ZYNQMP_CLK_H + +#define IOPLL 0 +#define RPLL 1 +#define APLL 2 +#define DPLL 3 +#define VPLL 4 +#define IOPLL_TO_FPD 5 +#define RPLL_TO_FPD 6 +#define APLL_TO_LPD 7 +#define DPLL_TO_LPD 8 +#define VPLL_TO_LPD 9 +#define ACPU 10 +#define ACPU_HALF 11 +#define DBF_FPD 12 +#define DBF_LPD 13 +#define DBG_TRACE 14 +#define DBG_TSTMP 15 +#define DP_VIDEO_REF 16 +#define DP_AUDIO_REF 17 +#define DP_STC_REF 18 +#define GDMA_REF 19 +#define DPDMA_REF 20 +#define DDR_REF 21 +#define SATA_REF 22 +#define PCIE_REF 23 +#define GPU_REF 24 +#define GPU_PP0_REF 25 +#define GPU_PP1_REF 26 +#define TOPSW_MAIN 27 +#define TOPSW_LSBUS 28 +#define GTGREF0_REF 29 +#define LPD_SWITCH 30 +#define LPD_LSBUS 31 +#define USB0_BUS_REF 32 +#define USB1_BUS_REF 33 +#define USB3_DUAL_REF 34 +#define USB0 35 +#define USB1 36 +#define CPU_R5 37 +#define CPU_R5_CORE 38 +#define CSU_SPB 39 +#define CSU_PLL 40 +#define PCAP 41 +#define IOU_SWITCH 42 +#define GEM_TSU_REF 43 +#define GEM_TSU 44 +#define GEM0_TX 45 +#define GEM1_TX 46 +#define GEM2_TX 47 +#define GEM3_TX 48 +#define GEM0_RX 49 +#define GEM1_RX 50 +#define GEM2_RX 51 +#define GEM3_RX 52 +#define QSPI_REF 53 +#define SDIO0_REF 54 +#define SDIO1_REF 55 +#define UART0_REF 56 +#define UART1_REF 57 +#define SPI0_REF 58 +#define SPI1_REF 59 +#define NAND_REF 60 +#define I2C0_REF 61 +#define I2C1_REF 62 +#define CAN0_REF 63 +#define CAN1_REF 64 +#define CAN0 65 +#define CAN1 66 +#define DLL_REF 67 +#define ADMA_REF 68 +#define TIMESTAMP_REF 69 +#define AMS_REF 70 +#define PL0_REF 71 +#define PL1_REF 72 +#define PL2_REF 73 +#define PL3_REF 74 +#define WDT 75 +#define IOPLL_INT 76 +#define IOPLL_PRE_SRC 77 +#define IOPLL_HALF 78 +#define IOPLL_INT_MUX 79 +#define IOPLL_POST_SRC 80 +#define RPLL_INT 81 +#define RPLL_PRE_SRC 82 +#define RPLL_HALF 83 +#define RPLL_INT_MUX 84 +#define RPLL_POST_SRC 85 +#define APLL_INT 86 +#define APLL_PRE_SRC 87 +#define APLL_HALF 88 +#define APLL_INT_MUX 89 +#define APLL_POST_SRC 90 +#define DPLL_INT 91 +#define DPLL_PRE_SRC 92 +#define DPLL_HALF 93 +#define DPLL_INT_MUX 94 +#define DPLL_POST_SRC 95 +#define VPLL_INT 96 +#define VPLL_PRE_SRC 97 +#define VPLL_HALF 98 +#define VPLL_INT_MUX 99 +#define VPLL_POST_SRC 100 +#define CAN0_MIO 101 +#define CAN1_MIO 102 +#define ACPU_FULL 103 +#define GEM0_REF 104 +#define GEM1_REF 105 +#define GEM2_REF 106 +#define GEM3_REF 107 +#define GEM0_REF_UNG 108 +#define GEM1_REF_UNG 109 +#define GEM2_REF_UNG 110 +#define GEM3_REF_UNG 111 +#define LPD_WDT 112 + +#endif /* _XLNX_ZYNQMP_CLK_H */ diff --git a/src/arm64/xilinx/zynqmp-clk-ccf.dtsi b/src/arm64/xilinx/zynqmp-clk-ccf.dtsi index 60d1b1acf9a..52e122fc7c9 100644 --- a/src/arm64/xilinx/zynqmp-clk-ccf.dtsi +++ b/src/arm64/xilinx/zynqmp-clk-ccf.dtsi @@ -8,41 +8,46 @@ * Michal Simek */ -#include +#include "xlnx-zynqmp-clk.h" / { - pss_ref_clk: pss_ref_clk { + pss_ref_clk: pss-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <33333333>; + clock-output-names = "pss_ref_clk"; }; - video_clk: video_clk { + video_clk: video-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; + clock-output-names = "video_clk"; }; - pss_alt_ref_clk: pss_alt_ref_clk { + pss_alt_ref_clk: pss-alt-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; + clock-output-names = "pss_alt_ref_clk"; }; - gt_crx_ref_clk: gt_crx_ref_clk { + gt_crx_ref_clk: gt-crx-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <108000000>; + clock-output-names = "gt_crx_ref_clk"; }; - aux_ref_clk: aux_ref_clk { + aux_ref_clk: aux-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <27000000>; + clock-output-names = "aux_ref_clk"; }; }; diff --git a/src/loongarch/loongson-2k1000-ref.dts b/src/loongarch/loongson-2k1000-ref.dts index 23cf26cc3e5..3514ea78f52 100644 --- a/src/loongarch/loongson-2k1000-ref.dts +++ b/src/loongarch/loongson-2k1000-ref.dts @@ -90,11 +90,6 @@ #address-cells = <1>; #size-cells = <0>; - spidev@0 { - compatible = "rohm,dh2228fv"; - spi-max-frequency = <100000000>; - reg = <0>; - }; }; &ehci0 { diff --git a/src/mips/ingenic/gcw0.dts b/src/mips/ingenic/gcw0.dts index 5d33f26fd28..8455778928b 100644 --- a/src/mips/ingenic/gcw0.dts +++ b/src/mips/ingenic/gcw0.dts @@ -91,7 +91,7 @@ "MIC1N", "Built-in Mic"; simple-audio-card,pin-switches = "Speaker", "Headphones"; - simple-audio-card,hp-det-gpio = <&gpf 21 GPIO_ACTIVE_LOW>; + simple-audio-card,hp-det-gpios = <&gpf 21 GPIO_ACTIVE_LOW>; simple-audio-card,aux-devs = <&speaker_amp>, <&headphones_amp>; simple-audio-card,bitclock-master = <&dai_codec>; diff --git a/src/mips/ingenic/rs90.dts b/src/mips/ingenic/rs90.dts index e8df70dd42b..6d2c8aea5f4 100644 --- a/src/mips/ingenic/rs90.dts +++ b/src/mips/ingenic/rs90.dts @@ -148,7 +148,7 @@ "Speaker", "OUTR"; simple-audio-card,pin-switches = "Speaker"; - simple-audio-card,hp-det-gpio = <&gpd 16 GPIO_ACTIVE_LOW>; + simple-audio-card,hp-det-gpios = <&gpd 16 GPIO_ACTIVE_LOW>; simple-audio-card,aux-devs = <&>; simple-audio-card,bitclock-master = <&dai_codec>; diff --git a/src/mips/mobileye/eyeq6h.dtsi b/src/mips/mobileye/eyeq6h.dtsi index 4a1a43f351d..dabd5ed778b 100644 --- a/src/mips/mobileye/eyeq6h.dtsi +++ b/src/mips/mobileye/eyeq6h.dtsi @@ -32,6 +32,10 @@ #interrupt-cells = <1>; }; + coherency-manager { + compatible = "mobileye,eyeq6-cm"; + }; + xtal: clock-30000000 { compatible = "fixed-clock"; #clock-cells = <0>; diff --git a/src/mips/ralink/gardena_smart_gateway_mt7688.dts b/src/mips/ralink/gardena_smart_gateway_mt7688.dts index 18107ca0a06..7743d014631 100644 --- a/src/mips/ralink/gardena_smart_gateway_mt7688.dts +++ b/src/mips/ralink/gardena_smart_gateway_mt7688.dts @@ -5,7 +5,7 @@ /dts-v1/; -/include/ "mt7628a.dtsi" +#include "mt7628a.dtsi" #include #include diff --git a/src/mips/ralink/mt7620a.dtsi b/src/mips/ralink/mt7620a.dtsi index 1f6e5320f48..d66045948a8 100644 --- a/src/mips/ralink/mt7620a.dtsi +++ b/src/mips/ralink/mt7620a.dtsi @@ -1,4 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 +#include + / { #address-cells = <1>; #size-cells = <1>; @@ -25,9 +27,11 @@ #address-cells = <1>; #size-cells = <1>; - sysc@0 { - compatible = "ralink,mt7620a-sysc"; + sysc: syscon@0 { + compatible = "ralink,mt7620-sysc", "syscon"; reg = <0x0 0x100>; + #clock-cells = <1>; + #reset-cells = <1>; }; intc: intc@200 { @@ -50,6 +54,8 @@ compatible = "ralink,mt7620a-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; + clocks = <&sysc MT7620_CLK_UARTLITE>; + interrupt-parent = <&intc>; interrupts = <12>; diff --git a/src/mips/ralink/mt7620a_eval.dts b/src/mips/ralink/mt7620a_eval.dts index 8de8f89f31b..da483ee65b6 100644 --- a/src/mips/ralink/mt7620a_eval.dts +++ b/src/mips/ralink/mt7620a_eval.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -/include/ "mt7620a.dtsi" +#include "mt7620a.dtsi" / { compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc"; diff --git a/src/mips/ralink/mt7628a.dtsi b/src/mips/ralink/mt7628a.dtsi index 45a15e005cc..0212700c4fb 100644 --- a/src/mips/ralink/mt7628a.dtsi +++ b/src/mips/ralink/mt7628a.dtsi @@ -1,4 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 +#include / { #address-cells = <1>; @@ -16,11 +17,6 @@ }; }; - resetc: reset-controller { - compatible = "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - cpuintc: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; @@ -36,9 +32,11 @@ #address-cells = <1>; #size-cells = <1>; - sysc: system-controller@0 { - compatible = "ralink,mt7620a-sysc", "syscon"; + sysc: syscon@0 { + compatible = "ralink,mt7628-sysc", "syscon"; reg = <0x0 0x60>; + #clock-cells = <1>; + #reset-cells = <1>; }; pinmux: pinmux@60 { @@ -138,7 +136,7 @@ compatible = "mediatek,mt7621-wdt"; reg = <0x100 0x30>; - resets = <&resetc 8>; + resets = <&sysc 8>; reset-names = "wdt"; interrupt-parent = <&intc>; @@ -154,7 +152,7 @@ interrupt-controller; #interrupt-cells = <1>; - resets = <&resetc 9>; + resets = <&sysc 9>; reset-names = "intc"; interrupt-parent = <&cpuintc>; @@ -190,7 +188,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinmux_spi_spi>; - resets = <&resetc 18>; + clocks = <&sysc MT76X8_CLK_SPI1>; + + resets = <&sysc 18>; reset-names = "spi"; #address-cells = <1>; @@ -206,7 +206,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinmux_i2c_i2c>; - resets = <&resetc 16>; + clocks = <&sysc MT76X8_CLK_I2C>; + + resets = <&sysc 16>; reset-names = "i2c"; #address-cells = <1>; @@ -222,7 +224,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinmux_uart0_uart>; - resets = <&resetc 12>; + clocks = <&sysc MT76X8_CLK_UART0>; + + resets = <&sysc 12>; reset-names = "uart0"; interrupt-parent = <&intc>; @@ -238,7 +242,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinmux_uart1_uart>; - resets = <&resetc 19>; + clocks = <&sysc MT76X8_CLK_UART1>; + + resets = <&sysc 19>; reset-names = "uart1"; interrupt-parent = <&intc>; @@ -254,7 +260,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinmux_uart2_uart>; - resets = <&resetc 20>; + clocks = <&sysc MT76X8_CLK_UART2>; + + resets = <&sysc 20>; reset-names = "uart2"; interrupt-parent = <&intc>; @@ -271,7 +279,7 @@ #phy-cells = <0>; ralink,sysctl = <&sysc>; - resets = <&resetc 22 &resetc 25>; + resets = <&sysc 22 &sysc 25>; reset-names = "host", "device"; }; @@ -290,6 +298,8 @@ compatible = "mediatek,mt7628-wmac"; reg = <0x10300000 0x100000>; + clocks = <&sysc MT76X8_CLK_WMAC>; + interrupt-parent = <&cpuintc>; interrupts = <6>; diff --git a/src/mips/ralink/omega2p.dts b/src/mips/ralink/omega2p.dts index 5884fd48f59..51a40ab6df2 100644 --- a/src/mips/ralink/omega2p.dts +++ b/src/mips/ralink/omega2p.dts @@ -1,6 +1,6 @@ /dts-v1/; -/include/ "mt7628a.dtsi" +#include "mt7628a.dtsi" / { compatible = "onion,omega2+", "ralink,mt7688a-soc", "ralink,mt7628a-soc"; diff --git a/src/mips/ralink/rt2880.dtsi b/src/mips/ralink/rt2880.dtsi index 8fc1987d906..1f2ea343432 100644 --- a/src/mips/ralink/rt2880.dtsi +++ b/src/mips/ralink/rt2880.dtsi @@ -1,4 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 +#include + / { #address-cells = <1>; #size-cells = <1>; @@ -25,9 +27,11 @@ #address-cells = <1>; #size-cells = <1>; - sysc@0 { - compatible = "ralink,rt2880-sysc"; + sysc: syscon@0 { + compatible = "ralink,rt2880-sysc", "syscon"; reg = <0x0 0x100>; + #clock-cells = <1>; + #reset-cells = <1>; }; intc: intc@200 { @@ -50,6 +54,8 @@ compatible = "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; + clocks = <&sysc RT2880_CLK_UARTLITE>; + interrupt-parent = <&intc>; interrupts = <8>; diff --git a/src/mips/ralink/rt2880_eval.dts b/src/mips/ralink/rt2880_eval.dts index 759bc1dd5b8..9854a4b120e 100644 --- a/src/mips/ralink/rt2880_eval.dts +++ b/src/mips/ralink/rt2880_eval.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -/include/ "rt2880.dtsi" +#include "rt2880.dtsi" / { compatible = "ralink,rt2880-eval-board", "ralink,rt2880-soc"; diff --git a/src/mips/ralink/rt3050.dtsi b/src/mips/ralink/rt3050.dtsi index 23062333a76..a7d9bb9bc1a 100644 --- a/src/mips/ralink/rt3050.dtsi +++ b/src/mips/ralink/rt3050.dtsi @@ -1,4 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 +#include + / { #address-cells = <1>; #size-cells = <1>; @@ -25,9 +27,11 @@ #address-cells = <1>; #size-cells = <1>; - sysc@0 { - compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc"; + sysc: syscon@0 { + compatible = "ralink,rt3052-sysc", "ralink,rt3050-sysc", "syscon"; reg = <0x0 0x100>; + #clock-cells = <1>; + #reset-cells = <1>; }; intc: intc@200 { @@ -50,6 +54,8 @@ compatible = "ralink,rt3052-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; + clocks = <&sysc RT305X_CLK_UARTLITE>; + interrupt-parent = <&intc>; interrupts = <12>; diff --git a/src/mips/ralink/rt3883.dtsi b/src/mips/ralink/rt3883.dtsi index 61132cf157e..11d111a0603 100644 --- a/src/mips/ralink/rt3883.dtsi +++ b/src/mips/ralink/rt3883.dtsi @@ -1,4 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 +#include + / { #address-cells = <1>; #size-cells = <1>; @@ -25,9 +27,11 @@ #address-cells = <1>; #size-cells = <1>; - sysc@0 { - compatible = "ralink,rt3883-sysc", "ralink,rt3050-sysc"; + sysc: syscon@0 { + compatible = "ralink,rt3883-sysc", "syscon"; reg = <0x0 0x100>; + #clock-cells = <1>; + #reset-cells = <1>; }; intc: intc@200 { @@ -50,6 +54,8 @@ compatible = "ralink,rt3883-uart", "ralink,rt2880-uart", "ns16550a"; reg = <0xc00 0x100>; + clocks = <&sysc RT3883_CLK_UARTLITE>; + interrupt-parent = <&intc>; interrupts = <12>; diff --git a/src/mips/ralink/rt3883_eval.dts b/src/mips/ralink/rt3883_eval.dts index c22bc84df21..a095a1fe941 100644 --- a/src/mips/ralink/rt3883_eval.dts +++ b/src/mips/ralink/rt3883_eval.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 /dts-v1/; -/include/ "rt3883.dtsi" +#include "rt3883.dtsi" / { compatible = "ralink,rt3883-eval-board", "ralink,rt3883-soc"; diff --git a/src/mips/realtek/cisco_sg220-26.dts b/src/mips/realtek/cisco_sg220-26.dts index 1cdbb09297e..fab3d552404 100644 --- a/src/mips/realtek/cisco_sg220-26.dts +++ b/src/mips/realtek/cisco_sg220-26.dts @@ -2,9 +2,10 @@ /dts-v1/; -#include "rtl83xx.dtsi" #include "rtl838x.dtsi" +#include + / { model = "Cisco SG220-26"; compatible = "cisco,sg220-26", "realtek,rtl8382-soc"; @@ -18,6 +19,13 @@ device_type = "memory"; reg = <0x0 0x8000000>; }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + priority = <192>; + open-source; + }; }; &uart0 { diff --git a/src/mips/realtek/rtl838x.dtsi b/src/mips/realtek/rtl838x.dtsi index 722106e3919..ce522a6af26 100644 --- a/src/mips/realtek/rtl838x.dtsi +++ b/src/mips/realtek/rtl838x.dtsi @@ -1,6 +1,14 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause / { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -9,8 +17,7 @@ device_type = "cpu"; compatible = "mips,mips4KEc"; reg = <0>; - clocks = <&baseclk 0>; - clock-names = "cpu"; + clocks = <&baseclk>; }; }; @@ -19,4 +26,104 @@ #clock-cells = <0>; clock-frequency = <500000000>; }; + + cpuintc: cpuintc { + compatible = "mti,cpu-interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + + lx_clk: clock-lexra { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + soc@18000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000000 0x10000>; + + spi0: spi@1200 { + compatible = "realtek,rtl8380-spi"; + reg = <0x1200 0x100>; + + #address-cells = <1>; + #size-cells = <0>; + }; + + uart0: serial@2000 { + compatible = "ns16550a"; + reg = <0x2000 0x100>; + + clocks = <&lx_clk>; + + interrupt-parent = <&intc>; + interrupts = <31>; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + + status = "disabled"; + }; + + uart1: serial@2100 { + compatible = "ns16550a"; + reg = <0x2100 0x100>; + + clocks = <&lx_clk>; + + interrupt-parent = <&intc>; + interrupts = <30>; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + + status = "disabled"; + }; + + intc: interrupt-controller@3000 { + compatible = "realtek,rtl8380-intc", "realtek,rtl-intc"; + reg = <0x3000 0x20>; + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>, <4>, <5>, <6>; + }; + + watchdog: watchdog@3150 { + compatible = "realtek,rtl8380-wdt"; + reg = <0x3150 0xc>; + + realtek,reset-mode = "soc"; + + clocks = <&lx_clk>; + timeout-sec = <20>; + + interrupt-parent = <&intc>; + interrupt-names = "phase1", "phase2"; + interrupts = <19>, <18>; + }; + + gpio0: gpio@3500 { + compatible = "realtek,rtl8380-gpio", "realtek,otto-gpio"; + reg = <0x3500 0x1c>; + + gpio-controller; + #gpio-cells = <2>; + ngpios = <24>; + + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupts = <23>; + }; + }; }; diff --git a/src/mips/realtek/rtl83xx.dtsi b/src/mips/realtek/rtl83xx.dtsi deleted file mode 100644 index 03ddc61f7c9..00000000000 --- a/src/mips/realtek/rtl83xx.dtsi +++ /dev/null @@ -1,59 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause - -/ { - #address-cells = <1>; - #size-cells = <1>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - }; - - cpuintc: cpuintc { - compatible = "mti,cpu-interrupt-controller"; - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0x0 0x18000000 0x10000>; - - uart0: serial@2000 { - compatible = "ns16550a"; - reg = <0x2000 0x100>; - - clock-frequency = <200000000>; - - interrupt-parent = <&cpuintc>; - interrupts = <31>; - - reg-io-width = <1>; - reg-shift = <2>; - fifo-size = <1>; - no-loopback-test; - - status = "disabled"; - }; - - uart1: serial@2100 { - compatible = "ns16550a"; - reg = <0x2100 0x100>; - - clock-frequency = <200000000>; - - interrupt-parent = <&cpuintc>; - interrupts = <30>; - - reg-io-width = <1>; - reg-shift = <2>; - fifo-size = <1>; - no-loopback-test; - - status = "disabled"; - }; - }; -}; diff --git a/src/mips/realtek/rtl930x.dtsi b/src/mips/realtek/rtl930x.dtsi index 17577457d15..f2e57ea3a60 100644 --- a/src/mips/realtek/rtl930x.dtsi +++ b/src/mips/realtek/rtl930x.dtsi @@ -1,10 +1,23 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause -#include "rtl83xx.dtsi" - / { compatible = "realtek,rtl9302-soc"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + cpuintc: cpuintc { + compatible = "mti,cpu-interrupt-controller"; + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -13,8 +26,7 @@ device_type = "cpu"; compatible = "mips,mips34Kc"; reg = <0>; - clocks = <&baseclk 0>; - clock-names = "cpu"; + clocks = <&baseclk>; }; }; @@ -58,64 +70,84 @@ status = "disabled"; }; }; -}; -&soc { - ranges = <0x0 0x18000000 0x20000>; + soc: soc@18000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x18000000 0x20000>; - intc: interrupt-controller@3000 { - compatible = "realtek,rtl9300-intc", "realtek,rtl-intc"; - reg = <0x3000 0x18>, <0x3018 0x18>; - interrupt-controller; - #interrupt-cells = <1>; + intc: interrupt-controller@3000 { + compatible = "realtek,rtl9300-intc", "realtek,rtl-intc"; + reg = <0x3000 0x18>, <0x3018 0x18>; + interrupt-controller; + #interrupt-cells = <1>; - interrupt-parent = <&cpuintc>; - interrupts = <2>, <3>, <4>, <5>, <6>, <7>; - }; + interrupt-parent = <&cpuintc>; + interrupts = <2>, <3>, <4>, <5>, <6>, <7>; + }; - spi0: spi@1200 { - compatible = "realtek,rtl8380-spi"; - reg = <0x1200 0x100>; + spi0: spi@1200 { + compatible = "realtek,rtl8380-spi"; + reg = <0x1200 0x100>; - #address-cells = <1>; - #size-cells = <0>; - }; + #address-cells = <1>; + #size-cells = <0>; + }; - timer0: timer@3200 { - compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; - reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, - <0x3230 0x10>, <0x3240 0x10>; + timer0: timer@3200 { + compatible = "realtek,rtl9302-timer", "realtek,otto-timer"; + reg = <0x3200 0x10>, <0x3210 0x10>, <0x3220 0x10>, + <0x3230 0x10>, <0x3240 0x10>; - interrupt-parent = <&intc>; - interrupts = <7>, <8>, <9>, <10>, <11>; - clocks = <&lx_clk>; - }; + interrupt-parent = <&intc>; + interrupts = <7>, <8>, <9>, <10>, <11>; + clocks = <&lx_clk>; + }; - snand: spi@1a400 { - compatible = "realtek,rtl9301-snand"; - reg = <0x1a400 0x44>; - interrupt-parent = <&intc>; - interrupts = <19>; - clocks = <&lx_clk>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; + snand: spi@1a400 { + compatible = "realtek,rtl9301-snand"; + reg = <0x1a400 0x44>; + interrupt-parent = <&intc>; + interrupts = <19>; + clocks = <&lx_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; -&uart0 { - /delete-property/ clock-frequency; - clocks = <&lx_clk>; + uart0: serial@2000 { + compatible = "ns16550a"; + reg = <0x2000 0x100>; - interrupt-parent = <&intc>; - interrupts = <30>; -}; + clocks = <&lx_clk>; -&uart1 { - /delete-property/ clock-frequency; - clocks = <&lx_clk>; + interrupt-parent = <&intc>; + interrupts = <30>; - interrupt-parent = <&intc>; - interrupts = <31>; -}; + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + status = "disabled"; + }; + + uart1: serial@2100 { + compatible = "ns16550a"; + reg = <0x2100 0x100>; + + clocks = <&lx_clk>; + + interrupt-parent = <&intc>; + interrupts = <31>; + + reg-io-width = <1>; + reg-shift = <2>; + fifo-size = <1>; + no-loopback-test; + + status = "disabled"; + }; + }; +}; diff --git a/src/powerpc/microwatt.dts b/src/powerpc/microwatt.dts index 269e930b3b0..c4e4d2a9b46 100644 --- a/src/powerpc/microwatt.dts +++ b/src/powerpc/microwatt.dts @@ -1,4 +1,5 @@ /dts-v1/; +#include / { #size-cells = <0x02>; @@ -8,6 +9,7 @@ aliases { serial0 = &UART0; + ethernet = &enet0; }; reserved-memory { @@ -35,40 +37,79 @@ ibm,powerpc-cpu-features { display-name = "Microwatt"; - isa = <3000>; + isa = <3010>; device_type = "cpu-features"; compatible = "ibm,powerpc-cpu-features"; mmu-radix { isa = <3000>; - usable-privilege = <2>; + usable-privilege = <6>; + os-support = <0>; }; little-endian { - isa = <2050>; - usable-privilege = <3>; + isa = <0>; + usable-privilege = <7>; + os-support = <0>; hwcap-bit-nr = <1>; }; cache-inhibited-large-page { - isa = <2040>; - usable-privilege = <2>; + isa = <0>; + usable-privilege = <6>; + os-support = <0>; }; fixed-point-v3 { isa = <3000>; - usable-privilege = <3>; + usable-privilege = <7>; }; no-execute { - isa = <2010>; + isa = <0x00>; usable-privilege = <2>; + os-support = <0>; }; floating-point { + hfscr-bit-nr = <0>; hwcap-bit-nr = <27>; isa = <0>; - usable-privilege = <3>; + usable-privilege = <7>; + hv-support = <1>; + os-support = <0>; + }; + + prefixed-instructions { + hfscr-bit-nr = <13>; + fscr-bit-nr = <13>; + isa = <3010>; + usable-privilege = <7>; + os-support = <1>; + hv-support = <1>; + }; + + tar { + hfscr-bit-nr = <8>; + fscr-bit-nr = <8>; + isa = <2070>; + usable-privilege = <7>; + os-support = <1>; + hv-support = <1>; + hwcap-bit-nr = <58>; + }; + + control-register { + isa = <0>; + usable-privilege = <7>; + }; + + system-call-vectored { + isa = <3000>; + usable-privilege = <7>; + os-support = <1>; + fscr-bit-nr = <12>; + hwcap-bit-nr = <52>; }; }; @@ -101,6 +142,36 @@ ibm,mmu-lpid-bits = <12>; ibm,mmu-pid-bits = <20>; }; + + PowerPC,Microwatt@1 { + i-cache-sets = <2>; + ibm,dec-bits = <64>; + reservation-granule-size = <64>; + clock-frequency = <100000000>; + timebase-frequency = <100000000>; + i-tlb-sets = <1>; + ibm,ppc-interrupt-server#s = <1>; + i-cache-block-size = <64>; + d-cache-block-size = <64>; + d-cache-sets = <2>; + i-tlb-size = <64>; + cpu-version = <0x990000>; + status = "okay"; + i-cache-size = <0x1000>; + ibm,processor-radix-AP-encodings = <0x0c 0xa0000010 0x20000015 0x4000001e>; + tlb-size = <0>; + tlb-sets = <0>; + device_type = "cpu"; + d-tlb-size = <128>; + d-tlb-sets = <2>; + reg = <1>; + general-purpose; + 64-bit; + d-cache-size = <0x1000>; + ibm,chip-id = <0>; + ibm,mmu-lpid-bits = <12>; + ibm,mmu-pid-bits = <20>; + }; }; soc@c0000000 { @@ -113,8 +184,8 @@ interrupt-controller@4000 { compatible = "openpower,xics-presentation", "ibm,ppc-xicp"; - ibm,interrupt-server-ranges = <0x0 0x1>; - reg = <0x4000 0x100>; + ibm,interrupt-server-ranges = <0x0 0x2>; + reg = <0x4000 0x10 0x4010 0x10>; }; ICS: interrupt-controller@5000 { @@ -138,7 +209,18 @@ interrupts = <0x10 0x1>; }; - ethernet@8020000 { + gpio: gpio@7000 { + device_type = "gpio"; + compatible = "faraday,ftgpio010"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x7000 0x80>; + interrupts = <0x14 1>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + enet0: ethernet@8020000 { compatible = "litex,liteeth"; reg = <0x8021000 0x100 0x8020800 0x100 @@ -160,7 +242,6 @@ reg-names = "phy", "core", "reader", "writer", "irq"; bus-width = <4>; interrupts = <0x13 1>; - cap-sd-highspeed; clocks = <&sys_clk>; }; }; diff --git a/src/riscv/microchip/mpfs-icicle-kit-fabric.dtsi b/src/riscv/microchip/mpfs-icicle-kit-fabric.dtsi index 1069134f2e1..a6dda55a2d1 100644 --- a/src/riscv/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/src/riscv/microchip/mpfs-icicle-kit-fabric.dtsi @@ -32,8 +32,9 @@ #interrupt-cells = <0x1>; #size-cells = <0x2>; device_type = "pci"; - reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; + reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>, + <0x0 0x4300a000 0x0 0x2000>; + reg-names = "cfg", "bridge", "ctrl"; bus-range = <0x0 0x7f>; interrupt-parent = <&plic>; interrupts = <119>; diff --git a/src/riscv/microchip/mpfs-m100pfs-fabric.dtsi b/src/riscv/microchip/mpfs-m100pfs-fabric.dtsi index 8230f06ddf4..36a9860f31d 100644 --- a/src/riscv/microchip/mpfs-m100pfs-fabric.dtsi +++ b/src/riscv/microchip/mpfs-m100pfs-fabric.dtsi @@ -20,8 +20,9 @@ #interrupt-cells = <0x1>; #size-cells = <0x2>; device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>, + <0x0 0x4300a000 0x0 0x2000>; + reg-names = "cfg", "bridge", "ctrl"; bus-range = <0x0 0x7f>; interrupt-parent = <&plic>; interrupts = <119>; diff --git a/src/riscv/microchip/mpfs-polarberry-fabric.dtsi b/src/riscv/microchip/mpfs-polarberry-fabric.dtsi index 9a56de7b91d..a57dca89196 100644 --- a/src/riscv/microchip/mpfs-polarberry-fabric.dtsi +++ b/src/riscv/microchip/mpfs-polarberry-fabric.dtsi @@ -20,8 +20,9 @@ #interrupt-cells = <0x1>; #size-cells = <0x2>; device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43008000 0x0 0x2000>, + <0x0 0x4300a000 0x0 0x2000>; + reg-names = "cfg", "bridge", "ctrl"; bus-range = <0x0 0x7f>; interrupt-parent = <&plic>; interrupts = <119>; diff --git a/src/riscv/sophgo/cv18xx.dtsi b/src/riscv/sophgo/cv18xx.dtsi index c18822ec849..58cd546392e 100644 --- a/src/riscv/sophgo/cv18xx.dtsi +++ b/src/riscv/sophgo/cv18xx.dtsi @@ -341,7 +341,7 @@ 1024 1024 1024 1024>; snps,priority = <0 1 2 3 4 5 6 7>; snps,dma-masters = <2>; - snps,data-width = <4>; + snps,data-width = <2>; status = "disabled"; }; diff --git a/src/riscv/sophgo/sg2042-milkv-pioneer.dts b/src/riscv/sophgo/sg2042-milkv-pioneer.dts index be596d01ff8..34645a5f603 100644 --- a/src/riscv/sophgo/sg2042-milkv-pioneer.dts +++ b/src/riscv/sophgo/sg2042-milkv-pioneer.dts @@ -73,6 +73,13 @@ }; / { + pwmfan: pwm-fan { + compatible = "pwm-fan"; + cooling-levels = <103 128 179 230 255>; + pwms = <&pwm 0 40000 0>; + #cooling-cells = <2>; + }; + thermal-zones { soc-thermal { polling-delay-passive = <1000>; @@ -104,6 +111,28 @@ type = "hot"; }; }; + + cooling-maps { + map0 { + trip = <&soc_active1>; + cooling-device = <&pwmfan 0 1>; + }; + + map1 { + trip = <&soc_active2>; + cooling-device = <&pwmfan 1 2>; + }; + + map2 { + trip = <&soc_active3>; + cooling-device = <&pwmfan 2 3>; + }; + + map3 { + trip = <&soc_hot>; + cooling-device = <&pwmfan 3 4>; + }; + }; }; board-thermal { @@ -118,6 +147,13 @@ type = "active"; }; }; + + cooling-maps { + map4 { + trip = <&board_active>; + cooling-device = <&pwmfan 3 4>; + }; + }; }; }; }; diff --git a/src/riscv/sophgo/sg2042.dtsi b/src/riscv/sophgo/sg2042.dtsi index e62ac51ac55..aa8b7fcc125 100644 --- a/src/riscv/sophgo/sg2042.dtsi +++ b/src/riscv/sophgo/sg2042.dtsi @@ -165,6 +165,15 @@ }; }; + pwm: pwm@703000c000 { + compatible = "sophgo,sg2042-pwm"; + reg = <0x70 0x3000c000 0x0 0x20>; + #pwm-cells = <3>; + clocks = <&clkgen GATE_CLK_APB_PWM>; + clock-names = "apb"; + resets = <&rstgen RST_PWM>; + }; + pllclk: clock-controller@70300100c0 { compatible = "sophgo,sg2042-pll"; reg = <0x70 0x300100c0 0x0 0x40>; @@ -173,6 +182,16 @@ #clock-cells = <1>; }; + msi: msi-controller@7030010304 { + compatible = "sophgo,sg2042-msi"; + reg = <0x70 0x30010304 0x0 0x4>, + <0x70 0x30010300 0x0 0x4>; + reg-names = "clr", "doorbell"; + msi-controller; + #msi-cells = <0>; + msi-ranges = <&intc 64 IRQ_TYPE_LEVEL_HIGH 32>; + }; + rpgate: clock-controller@7030010368 { compatible = "sophgo,sg2042-rpgate"; reg = <0x70 0x30010368 0x0 0x98>; diff --git a/src/riscv/spacemit/k1-milkv-jupiter.dts b/src/riscv/spacemit/k1-milkv-jupiter.dts new file mode 100644 index 00000000000..44831921410 --- /dev/null +++ b/src/riscv/spacemit/k1-milkv-jupiter.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2024 Yangyu Chen + * Copyright (C) 2025 Javier Martinez Canillas + */ + +#include "k1.dtsi" +#include "k1-pinctrl.dtsi" + +/ { + model = "Milk-V Jupiter (K1)"; + compatible = "milkv,jupiter", "spacemit,k1"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0"; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; +}; diff --git a/src/riscv/starfive/jh7110-common.dtsi b/src/riscv/starfive/jh7110-common.dtsi index 48fb5091b81..c2f70f5e291 100644 --- a/src/riscv/starfive/jh7110-common.dtsi +++ b/src/riscv/starfive/jh7110-common.dtsi @@ -233,7 +233,7 @@ regulator-always-on; regulator-min-microvolt = <500000>; regulator-max-microvolt = <1540000>; - regulator-name = "vdd-cpu"; + regulator-name = "vdd_cpu"; }; emmc_vdd: aldo4 { @@ -350,12 +350,6 @@ &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; - - spi_dev0: spi@0 { - compatible = "rohm,dh2228fv"; - reg = <0>; - spi-max-frequency = <10000000>; - }; }; &syscrg { diff --git a/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts b/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts index 30b0715196b..8d9ce8b69a7 100644 --- a/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts +++ b/src/riscv/starfive/jh7110-deepcomputing-fml13v01.dts @@ -11,6 +11,40 @@ compatible = "deepcomputing,fml13v01", "starfive,jh7110"; }; +&pcie1 { + perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>; + phys = <&pciephy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + +&sysgpio { + pcie1_pins: pcie1-0 { + clkreq-pins { + pinmux = ; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = ; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; +}; + &usb0 { dr_mode = "host"; status = "okay"; diff --git a/src/riscv/starfive/jh7110-pine64-star64.dts b/src/riscv/starfive/jh7110-pine64-star64.dts index b764d4d92fd..31e825be206 100644 --- a/src/riscv/starfive/jh7110-pine64-star64.dts +++ b/src/riscv/starfive/jh7110-pine64-star64.dts @@ -100,3 +100,8 @@ pinctrl-0 = <&usb0_pins>; status = "okay"; }; + +&usb_cdns3 { + phys = <&usbphy0>, <&pciephy0>; + phy-names = "cdns3,usb2-phy", "cdns3,usb3-phy"; +}; diff --git a/src/riscv/starfive/jh7110.dtsi b/src/riscv/starfive/jh7110.dtsi index 0d8339357ba..0ba74ef0467 100644 --- a/src/riscv/starfive/jh7110.dtsi +++ b/src/riscv/starfive/jh7110.dtsi @@ -611,6 +611,8 @@ pciephy0: phy@10210000 { compatible = "starfive,jh7110-pcie-phy"; reg = <0x0 0x10210000 0x0 0x10000>; + starfive,sys-syscon = <&sys_syscon 0x18>; + starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>; #phy-cells = <0>; }; @@ -1022,7 +1024,6 @@ snps,force_thresh_dma_mode; snps,axi-config = <&stmmac_axi_setup>; snps,tso; - snps,en-tx-lpi-clockgating; snps,txpbl = <16>; snps,rxpbl = <16>; starfive,syscon = <&aon_syscon 0xc 0x12>; @@ -1053,7 +1054,6 @@ snps,force_thresh_dma_mode; snps,axi-config = <&stmmac_axi_setup>; snps,tso; - snps,en-tx-lpi-clockgating; snps,txpbl = <16>; snps,rxpbl = <16>; starfive,syscon = <&sys_syscon 0x90 0x2>; -- cgit v1.3.1 From 19b3e24083eb0b1b5299e689d0bc5f1a6c4ebdcd Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Tue, 13 May 2025 10:40:26 +0200 Subject: slre: drop wrong "anchored" optimization The regex '^a|b' means "does the string start with a, or does it have a b anywhere", not "does the string start with a or b" (the latter should be spelled '^[ab]' or '^(a|b)'). It should match exactly the same strings as 'b|^a'. But the current implementation hard-codes an assumption that when the regex starts with a ^, the whole regex must match from the beginning, i.e. it only attempts at offset 0. It really should be completely symmetrical to 'b|c$' ("does it have a b anywhere or end with c?"), which is treated correctly. Another quirk is that currently the regex 'x*$', which should match all strings (because it just means "does the string end with 0 or more x'es"), does not, because in the unanchored case we never attempt to match at ofs==len. In the anchored case, '^x*$', this works correctly and matches exactly strings (including the empty string) consisting entirely of x'es. Fix both of these issues by dropping all use of the slre->anchored member and always test at all possible offsets. If the regex does have a ^ somewhere (including after a | branch character), that is correctly handled by the match engine by only matching when *ofs is 0. Reviewed-by: Simon Glass Signed-off-by: Rasmus Villemoes --- include/slre.h | 1 - lib/slre.c | 13 +++---------- 2 files changed, 3 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/slre.h b/include/slre.h index 4b41a4b276f..af5b1302d9c 100644 --- a/include/slre.h +++ b/include/slre.h @@ -63,7 +63,6 @@ struct slre { int code_size; int data_size; int num_caps; /* Number of bracket pairs */ - int anchored; /* Must match from string start */ const char *err_str; /* Error string */ }; diff --git a/lib/slre.c b/lib/slre.c index 277a59a03a7..4f455400d3a 100644 --- a/lib/slre.c +++ b/lib/slre.c @@ -413,10 +413,7 @@ int slre_compile(struct slre *r, const char *re) { r->err_str = NULL; - r->code_size = r->data_size = r->num_caps = r->anchored = 0; - - if (*re == '^') - r->anchored++; + r->code_size = r->data_size = r->num_caps = 0; emit(r, OPEN); /* This will capture what matches full RE */ emit(r, 0); @@ -650,13 +647,9 @@ slre_match(const struct slre *r, const char *buf, int len, { int i, ofs = 0, res = 0; - if (r->anchored) { + for (i = 0; i <= len && res == 0; i++) { + ofs = i; res = match(r, 0, buf, len, &ofs, caps); - } else { - for (i = 0; i < len && res == 0; i++) { - ofs = i; - res = match(r, 0, buf, len, &ofs, caps); - } } return res; -- cgit v1.3.1 From 1e50f7457fcaaba2caf642132cf4f00f1eba29a9 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 14 May 2025 16:46:04 -0600 Subject: include/command.h: Drop Now that all of the cases of code that relied on to provide (or one of the headers that it includes, and so forth) have been fixed, we can drop the include from here. Signed-off-by: Tom Rini --- include/command.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/command.h b/include/command.h index 4158ca11b0e..5d225cd197f 100644 --- a/include/command.h +++ b/include/command.h @@ -10,7 +10,6 @@ #ifndef __COMMAND_H #define __COMMAND_H -#include #include #include -- cgit v1.3.1 From 05f6f6e8c76c68a36125ec7a6af911ee9418bc99 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 15 May 2025 17:31:30 -0600 Subject: net: Remove env_get_ip helper() function Currently, we have the function env_get_ip which takes an IP address in string form and returns a struct in_addr representation of that address. It is however little used and means that a number of places indirectly (and unclearly) get via . To clean this up start by replacing env_get_ip() calls with string_to_ip() calls. This is generally a no-op as env_get_ip(str) is an inline of string_to_ip(env_get(str)) but in a few cases we can or already have stored the result of env_get(str) and can save the additional call. Signed-off-by: Tom Rini --- cmd/elf.c | 2 +- cmd/net.c | 2 +- drivers/net/netconsole.c | 11 ++++++----- include/net-common.h | 13 ------------- net/link_local.c | 2 +- 5 files changed, 9 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/cmd/elf.c b/cmd/elf.c index 6b49c613703..5e0ee30a7c8 100644 --- a/cmd/elf.c +++ b/cmd/elf.c @@ -247,7 +247,7 @@ int do_bootvx(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ptr += sprintf(build_buf + ptr, "e=%s", tmp); tmp = env_get("netmask"); if (tmp) { - u32 mask = env_get_ip("netmask").s_addr; + u32 mask = string_to_ip(tmp).s_addr; ptr += sprintf(build_buf + ptr, ":%08x ", ntohl(mask)); } else { diff --git a/cmd/net.c b/cmd/net.c index eaa1de5295f..886735ea14f 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -564,7 +564,7 @@ int do_sntp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) char *toff; if (argc < 2) { - net_ntp_server = env_get_ip("ntpserverip"); + net_ntp_server = string_to_ip(env_get("ntpserverip")); if (net_ntp_server.s_addr == 0) { printf("ntpserverip not set\n"); return CMD_RET_FAILURE; diff --git a/drivers/net/netconsole.c b/drivers/net/netconsole.c index 1943de8ba73..c2ce4a80d12 100644 --- a/drivers/net/netconsole.c +++ b/drivers/net/netconsole.c @@ -61,8 +61,8 @@ static int is_broadcast(struct in_addr ip) /* update only when the environment has changed */ if (env_changed_id != env_id) { - netmask = env_get_ip("netmask"); - our_ip = env_get_ip("ipaddr"); + netmask = string_to_ip(env_get("netmask")); + our_ip = string_to_ip(env_get("ipaddr")); env_changed_id = env_id; } @@ -81,11 +81,12 @@ static int refresh_settings_from_env(void) /* update only when the environment has changed */ if (env_changed_id != env_id) { - if (env_get("ncip")) { - nc_ip = env_get_ip("ncip"); + char *tmp = env_get("ncip"); + if (tmp) { + nc_ip = string_to_ip(tmp); if (!nc_ip.s_addr) return -1; /* ncip is 0.0.0.0 */ - p = strchr(env_get("ncip"), ':'); + p = strchr(tmp, ':'); if (p != NULL) { nc_out_port = dectoul(p + 1, NULL); nc_in_port = nc_out_port; diff --git a/include/net-common.h b/include/net-common.h index e536968a92b..2ca565fe4ed 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -456,19 +456,6 @@ void net_process_received_packet(uchar *in_packet, int len); */ int update_tftp(ulong addr, char *interface, char *devstring); -/** - * env_get_ip() - Convert an environment value to an ip address - * - * @var: Environment variable to convert. The value of this variable must be - * in the format a.b.c.d, where each value is a decimal number from - * 0 to 255 - * Return: IP address, or 0 if invalid - */ -static inline struct in_addr env_get_ip(char *var) -{ - return string_to_ip(env_get(var)); -} - int net_init(void); /* Called when a network operation fails to know if it should be re-tried */ diff --git a/net/link_local.c b/net/link_local.c index 179721333ff..f6425ff3df2 100644 --- a/net/link_local.c +++ b/net/link_local.c @@ -106,7 +106,7 @@ static void configure_wait(void) void link_local_start(void) { - ip = env_get_ip("llipaddr"); + ip = string_to_ip(env_get("llipaddr")); if (ip.s_addr != 0 && (ntohl(ip.s_addr) & IN_CLASSB_NET) != LINKLOCAL_ADDR) { puts("invalid link address"); -- cgit v1.3.1 From 0b9450989c195430521b01d97ba79a9b644119a6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 15 May 2025 17:31:34 -0600 Subject: net: Include string.h in net-legacy.h This file uses memcpy() but does not include the header file. Update it. Reviewed-by: Jerome Forissier Signed-off-by: Simon Glass --- include/net-legacy.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/net-legacy.h b/include/net-legacy.h index 51780999a88..a7dbcec1506 100644 --- a/include/net-legacy.h +++ b/include/net-legacy.h @@ -17,6 +17,7 @@ #include #include #include +#include struct bd_info; struct cmd_tbl; -- cgit v1.3.1 From 22d4e22a3d2e8a95c37c0635701daaee8d5a5c6b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 15 May 2025 17:31:47 -0600 Subject: net: Include byteorder in net6.h This file uses byteorder but does not include the header file. Update it. Signed-off-by: Simon Glass --- include/net6.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/net6.h b/include/net6.h index 2ceeaba0639..39573e490a6 100644 --- a/include/net6.h +++ b/include/net6.h @@ -11,6 +11,7 @@ #define __NET6_H__ #include +#include #include #include -- cgit v1.3.1 From fe33175c073fe21945b39a4a8c27806cf0154bf3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 15 May 2025 17:31:51 -0600 Subject: include/net.h: Drop Now that all of the cases of code that relied on to provide (or one of the headers that it includes, and so forth) have been fixed, we can drop the include from here. Signed-off-by: Tom Rini --- include/net-common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/net-common.h b/include/net-common.h index 2ca565fe4ed..9e82b280df2 100644 --- a/include/net-common.h +++ b/include/net-common.h @@ -5,7 +5,6 @@ #include #include -#include #include #include #include -- cgit v1.3.1 From 43fd4bcefd4ea5e586e201a0908018d1e8395c82 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Tue, 13 May 2025 14:47:06 +0530 Subject: disk: part: implement generic function part_get_info_by_uuid() Add function to search for a partition by UUID as partition names may not be unique. Signed-off-by: Varadarajan Narayanan Acked-by: Casey Connolly --- disk/part.c | 39 +++++++++++++++++++++++++++++++++++++++ include/part.h | 20 ++++++++++++++++++++ 2 files changed, 59 insertions(+) (limited to 'include') diff --git a/disk/part.c b/disk/part.c index 303178161c0..8eefda39d7b 100644 --- a/disk/part.c +++ b/disk/part.c @@ -698,6 +698,45 @@ int part_get_info_by_name(struct blk_desc *desc, const char *name, return -ENOENT; } +int part_get_info_by_uuid(struct blk_desc *desc, const char *uuid, + struct disk_partition *info) +{ + struct part_driver *part_drv; + int ret; + int i; + + if (!CONFIG_IS_ENABLED(PARTITION_UUIDS)) + return -ENOENT; + + part_drv = part_driver_lookup_type(desc); + if (!part_drv) + return -1; + + if (!part_drv->get_info) { + log_debug("## Driver %s does not have the get_info() method\n", + part_drv->name); + return -ENOSYS; + } + + for (i = 1; i < part_drv->max_entries; i++) { + ret = part_drv->get_info(desc, i, info); + if (ret != 0) { + /* + * Partition with this index can't be obtained, but + * further partitions might be, so keep checking. + */ + continue; + } + + if (!strncasecmp(uuid, disk_partition_uuid(info), UUID_STR_LEN)) { + /* matched */ + return i; + } + } + + return -ENOENT; +} + /** * Get partition info from device number and partition name. * diff --git a/include/part.h b/include/part.h index fcb3c13dea4..3e6eb0ec33f 100644 --- a/include/part.h +++ b/include/part.h @@ -315,6 +315,20 @@ int blk_get_device_part_str(const char *ifname, const char *dev_part_str, int part_get_info_by_name(struct blk_desc *desc, const char *name, struct disk_partition *info); +/** + * part_get_info_by_uuid() - Search for a partition by uuid + * among all available registered partitions + * + * @desc: block device descriptor + * @uuid: the specified table entry uuid + * @info: the disk partition info + * + * Return: the partition number on match (starting on 1), -ENOENT on no match, + * otherwise error + */ +int part_get_info_by_uuid(struct blk_desc *desc, const char *uuid, + struct disk_partition *info); + /** * part_get_info_by_dev_and_name_or_num() - Get partition info from dev number * and part name, or dev number and @@ -386,6 +400,12 @@ static inline int part_get_info_by_name(struct blk_desc *desc, const char *name, return -ENOENT; } +static inline int part_get_info_by_uuid(struct blk_desc *desc, const char *uuid, + struct disk_partition *info) +{ + return -ENOENT; +} + static inline int part_get_info_by_dev_and_name_or_num(const char *dev_iface, const char *dev_part_str, -- cgit v1.3.1 From 9a2010941f56929cb28432cc3f4b37a944f55b8e Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Tue, 13 May 2025 14:47:07 +0530 Subject: scsi: Implement get_blk() function Add a function to obtain the block device for SCSI. Signed-off-by: Varadarajan Narayanan Acked-by: Casey Connolly --- drivers/scsi/scsi-uclass.c | 30 ++++++++++++++++++++++++++++++ include/scsi.h | 10 ++++++++++ 2 files changed, 40 insertions(+) (limited to 'include') diff --git a/drivers/scsi/scsi-uclass.c b/drivers/scsi/scsi-uclass.c index 1ee8236c05c..3eb6069649f 100644 --- a/drivers/scsi/scsi-uclass.c +++ b/drivers/scsi/scsi-uclass.c @@ -10,7 +10,9 @@ #define LOG_CATEGORY UCLASS_SCSI +#include #include +#include #include int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb) @@ -23,6 +25,34 @@ int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb) return ops->exec(dev, pccb); } +int scsi_get_blk_by_uuid(const char *uuid, + struct blk_desc **blk_desc_ptr, + struct disk_partition *part_info_ptr) +{ + static int is_scsi_scanned; + struct blk_desc *blk; + int i, ret; + + if (!is_scsi_scanned) { + scsi_scan(false /* no verbose */); + is_scsi_scanned = 1; + } + + for (i = 0; i < blk_find_max_devnum(UCLASS_SCSI) + 1; i++) { + ret = blk_get_desc(UCLASS_SCSI, i, &blk); + if (ret) + continue; + + ret = part_get_info_by_uuid(blk, uuid, part_info_ptr); + if (ret > 0) { + *blk_desc_ptr = blk; + return 0; + } + } + + return -1; +} + int scsi_bus_reset(struct udevice *dev) { struct scsi_ops *ops = scsi_get_ops(dev); diff --git a/include/scsi.h b/include/scsi.h index ab53b47b58f..8d6c5116419 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -351,6 +351,16 @@ int scsi_scan(bool verbose); */ int scsi_scan_dev(struct udevice *dev, bool verbose); +/** + * scsi_get_blk_by_uuid() - Provides SCSI partition information. + * + * @uuid: UUID of the partition for fetching its info + * @blk_desc_ptr: Provides the blk descriptor + * @part_info_ptr: Provides partition info + */ +int scsi_get_blk_by_uuid(const char *uuid, struct blk_desc **blk_desc_ptr, + struct disk_partition *part_info_ptr); + #define SCSI_IDENTIFY 0xC0 /* not used */ /* Hardware errors */ -- cgit v1.3.1 From 8bf3e967f6a999faa4782cf4a81f6aa82d31ead8 Mon Sep 17 00:00:00 2001 From: Varadarajan Narayanan Date: Tue, 13 May 2025 14:47:08 +0530 Subject: env: Add support for storing env variables in SCSI devices Allow SCSI to be able to store environment variables. Signed-off-by: Varadarajan Narayanan Acked-by: Casey Connolly --- env/Kconfig | 15 ++++++- env/Makefile | 1 + env/env.c | 3 ++ env/scsi.c | 115 +++++++++++++++++++++++++++++++++++++++++++++++++ include/env_internal.h | 1 + 5 files changed, 134 insertions(+), 1 deletion(-) create mode 100644 env/scsi.c (limited to 'include') diff --git a/env/Kconfig b/env/Kconfig index 9f5ec44601e..9081f7099b7 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -74,7 +74,7 @@ config ENV_IS_DEFAULT !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \ !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \ !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \ - !ENV_IS_IN_UBI && !ENV_IS_IN_MTD + !ENV_IS_IN_UBI && !ENV_IS_IN_MTD && !ENV_IS_IN_SCSI select ENV_IS_NOWHERE config ENV_IS_NOWHERE @@ -297,6 +297,13 @@ config ENV_IS_IN_NAND Currently, CONFIG_ENV_OFFSET_REDUND is not supported when using CONFIG_ENV_OFFSET_OOB. +config ENV_IS_IN_SCSI + bool "Environment in an SCSI device" + depends on SCSI + help + Define this if you have an SCSI device which you want to use for the + environment. + config ENV_RANGE hex "Length of the region in which the environment can be written" depends on ENV_IS_IN_NAND @@ -731,6 +738,12 @@ config ENV_MMC_USE_DT The 2 defines CONFIG_ENV_OFFSET, CONFIG_ENV_OFFSET_REDUND are not used as fallback. +config SCSI_ENV_PART_UUID + string "SCSI partition UUID for saving environment" + depends on ENV_IS_IN_SCSI + help + UUID of the SCSI partition that you want to store the environment in. + config USE_DEFAULT_ENV_FILE bool "Create default environment from file" help diff --git a/env/Makefile b/env/Makefile index 3b9c71d5681..d11b87702c1 100644 --- a/env/Makefile +++ b/env/Makefile @@ -28,5 +28,6 @@ obj-$(CONFIG_$(PHASE_)ENV_IS_IN_NAND) += nand.o obj-$(CONFIG_$(PHASE_)ENV_IS_IN_SPI_FLASH) += sf.o obj-$(CONFIG_$(PHASE_)ENV_IS_IN_MTD) += mtd.o obj-$(CONFIG_$(PHASE_)ENV_IS_IN_FLASH) += flash.o +obj-$(CONFIG_$(PHASE_)ENV_IS_IN_SCSI) += scsi.o CFLAGS_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null) diff --git a/env/env.c b/env/env.c index dbaeedc3c3b..7a9c96b4078 100644 --- a/env/env.c +++ b/env/env.c @@ -46,6 +46,9 @@ static enum env_location env_locations[] = { #ifdef CONFIG_ENV_IS_IN_MMC ENVL_MMC, #endif +#ifdef CONFIG_ENV_IS_IN_SCSI + ENVL_SCSI, +#endif #ifdef CONFIG_ENV_IS_IN_NAND ENVL_NAND, #endif diff --git a/env/scsi.c b/env/scsi.c new file mode 100644 index 00000000000..207717e17b1 --- /dev/null +++ b/env/scsi.c @@ -0,0 +1,115 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2008-2011 Freescale Semiconductor, Inc. + */ + +/* #define DEBUG */ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +static env_t envbuf; + +struct env_scsi_info { + struct blk_desc *blk; + struct disk_partition part; + int count; +}; + +static struct env_scsi_info env_part; + +static inline struct env_scsi_info *env_scsi_get_part(void) +{ + struct env_scsi_info *ep = &env_part; + + if (scsi_get_blk_by_uuid(CONFIG_SCSI_ENV_PART_UUID, &ep->blk, &ep->part)) + return NULL; + + ep->count = CONFIG_ENV_SIZE / ep->part.blksz; + + return ep; +} + +static int env_scsi_save(void) +{ + struct env_scsi_info *ep = env_scsi_get_part(); + int ret; + + if (!ep) + return -ENOENT; + + ret = env_export(&envbuf); + if (ret) + return ret; + + if (blk_dwrite(ep->blk, ep->part.start, ep->count, &envbuf) != ep->count) + return -EIO; + + return 0; +} + +static int env_scsi_erase(void) +{ + struct env_scsi_info *ep = env_scsi_get_part(); + + if (!ep) + return -ENOENT; + + return (int)blk_derase(ep->blk, ep->part.start, ep->count); +} + +#if defined(ENV_IS_EMBEDDED) +static int env_scsi_load(void) +{ + return 0; +} +#else +static int env_scsi_load(void) +{ + struct env_scsi_info *ep = env_scsi_get_part(); + int ret; + + if (!ep) { + env_set_default(CONFIG_SCSI_ENV_PART_UUID " partition not found", 0); + return -ENOENT; + } + + if (blk_dread(ep->blk, ep->part.start, ep->count, &envbuf) != ep->count) { + env_set_default(CONFIG_SCSI_ENV_PART_UUID " partition read failed", 0); + return -EIO; + } + + ret = env_import((char *)&envbuf, 1, H_EXTERNAL); + if (ret) { + debug("ENV import failed\n"); + env_set_default("Cannot load environment", 0); + } else { + gd->env_addr = (ulong)envbuf.data; + } + + return ret; +} +#endif + +U_BOOT_ENV_LOCATION(scsi) = { + .location = ENVL_SCSI, + ENV_NAME("SCSI") + .load = env_scsi_load, +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_XPL_BUILD) + .save = env_save_ptr(env_scsi_save), + .erase = ENV_ERASE_PTR(env_scsi_erase), +#endif +}; diff --git a/include/env_internal.h b/include/env_internal.h index ee939ba4293..75b46d0bcb0 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -115,6 +115,7 @@ enum env_location { ENVL_SPI_FLASH, ENVL_MTD, ENVL_UBI, + ENVL_SCSI, ENVL_NOWHERE, ENVL_COUNT, -- cgit v1.3.1 From 97b586695cd80821455ae06ee178c6c8cf759ce6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 1 May 2025 07:37:01 -0600 Subject: abuf: Add a helper for initing and allocating a buffer This construct appears in various places. Reduce code size by adding a function for it. It inits the abuf, then allocates it to the requested size. Signed-off-by: Simon Glass --- boot/cedit.c | 3 +-- boot/scene.c | 3 +-- boot/scene_textline.c | 3 +-- include/abuf.h | 11 +++++++++++ lib/abuf.c | 9 +++++++++ lib/of_live.c | 3 +-- test/lib/abuf.c | 21 +++++++++++++++++++++ 7 files changed, 45 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/boot/cedit.c b/boot/cedit.c index d69290c172e..4e80875828b 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -449,8 +449,7 @@ int cedit_write_settings(struct expo *exp, struct abuf *buf) void *fdt; int ret; - abuf_init(buf); - if (!abuf_realloc(buf, CEDIT_SIZE_INC)) + if (!abuf_init_size(buf, CEDIT_SIZE_INC)) return log_msg_ret("buf", -ENOMEM); fdt = abuf_data(buf); diff --git a/boot/scene.c b/boot/scene.c index fb82ffe768c..90b4ccf4766 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -31,8 +31,7 @@ int scene_new(struct expo *exp, const char *name, uint id, struct scene **scnp) return log_msg_ret("name", -ENOMEM); } - abuf_init(&scn->buf); - if (!abuf_realloc(&scn->buf, EXPO_MAX_CHARS + 1)) { + if (!abuf_init_size(&scn->buf, EXPO_MAX_CHARS + 1)) { free(scn->name); free(scn); return log_msg_ret("buf", -ENOMEM); diff --git a/boot/scene_textline.c b/boot/scene_textline.c index 6adef7cc173..90642a3f03d 100644 --- a/boot/scene_textline.c +++ b/boot/scene_textline.c @@ -31,8 +31,7 @@ int scene_textline(struct scene *scn, const char *name, uint id, uint max_chars, (struct scene_obj **)&tline); if (ret < 0) return log_msg_ret("obj", -ENOMEM); - abuf_init(&tline->buf); - if (!abuf_realloc(&tline->buf, max_chars + 1)) + if (!abuf_init_size(&tline->buf, max_chars + 1)) return log_msg_ret("buf", -ENOMEM); buf = abuf_data(&tline->buf); *buf = '\0'; diff --git a/include/abuf.h b/include/abuf.h index 62ff6499a0c..749bb188b0c 100644 --- a/include/abuf.h +++ b/include/abuf.h @@ -170,6 +170,17 @@ void abuf_init_set(struct abuf *abuf, void *data, size_t size); */ void abuf_init_const(struct abuf *abuf, const void *data, size_t size); +/** + * abuf_init_size() - Set up an allocated abuf + * + * Init a new abuf and allocate its size. + * + * @abuf: abuf to set up + * @data: New contents of abuf + * @size: New size of abuf + */ +bool abuf_init_size(struct abuf *buf, size_t size); + /** * abuf_uninit() - Free any memory used by an abuf * diff --git a/lib/abuf.c b/lib/abuf.c index 61adf7fc6b1..3cbe320fb08 100644 --- a/lib/abuf.c +++ b/lib/abuf.c @@ -119,6 +119,15 @@ void abuf_init_set(struct abuf *abuf, void *data, size_t size) abuf_set(abuf, data, size); } +bool abuf_init_size(struct abuf *buf, size_t size) +{ + abuf_init(buf); + if (!abuf_realloc(buf, size)) + return false; + + return true; +} + void abuf_init_const(struct abuf *abuf, const void *data, size_t size) { /* for now there is no flag indicating that the abuf data is constant */ diff --git a/lib/of_live.c b/lib/of_live.c index c1620616513..24200b948a6 100644 --- a/lib/of_live.c +++ b/lib/of_live.c @@ -448,8 +448,7 @@ int of_live_flatten(const struct device_node *root, struct abuf *buf) { int ret; - abuf_init(buf); - if (!abuf_realloc(buf, BUF_STEP)) + if (!abuf_init_size(buf, BUF_STEP)) return log_msg_ret("ini", -ENOMEM); ret = fdt_create(abuf_data(buf), abuf_size(buf)); diff --git a/test/lib/abuf.c b/test/lib/abuf.c index b38690fe1a9..cdc86aad988 100644 --- a/test/lib/abuf.c +++ b/test/lib/abuf.c @@ -419,3 +419,24 @@ static int lib_test_abuf_init(struct unit_test_state *uts) return 0; } LIB_TEST(lib_test_abuf_init, 0); + +/* Test abuf_init_size() */ +static int lib_test_abuf_init_size(struct unit_test_state *uts) +{ + struct abuf buf; + ulong start; + + start = ut_check_free(); + + ut_assert(abuf_init_size(&buf, TEST_DATA_LEN)); + ut_assertnonnull(buf.data); + ut_asserteq(TEST_DATA_LEN, buf.size); + ut_asserteq(true, buf.alloced); + abuf_uninit(&buf); + + /* Check for memory leaks */ + ut_assertok(ut_check_delta(start)); + + return 0; +} +LIB_TEST(lib_test_abuf_init_size, 0); -- cgit v1.3.1 From d58cebbbc7617fbc45e604c883e8501a58d25e62 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:03 -0600 Subject: abuf: Add a function to copy a buffer It is useful to be able to copy an abuf, to allow changes while preserving the original. Add a function for this. Signed-off-by: Simon Glass --- include/abuf.h | 11 +++++++++++ lib/abuf.c | 14 ++++++++++++++ test/lib/abuf.c | 23 +++++++++++++++++++++++ 3 files changed, 48 insertions(+) (limited to 'include') diff --git a/include/abuf.h b/include/abuf.h index 749bb188b0c..bbb3c51f334 100644 --- a/include/abuf.h +++ b/include/abuf.h @@ -111,6 +111,17 @@ bool abuf_realloc(struct abuf *abuf, size_t new_size); */ bool abuf_realloc_inc(struct abuf *abuf, size_t inc); +/** + * abuf_copy() - Make a copy of an abuf + * + * Creates an allocated copy of @old in @new + * + * @old: abuf to copy + * @new: new abuf to hold the copy (inited by this function) + * Return: true if OK, false if out of memory + */ +bool abuf_copy(const struct abuf *old, struct abuf *new); + /** * abuf_uninit_move() - Return the allocated contents and uninit the abuf * diff --git a/lib/abuf.c b/lib/abuf.c index 3cbe320fb08..28c748acb9f 100644 --- a/lib/abuf.c +++ b/lib/abuf.c @@ -128,6 +128,20 @@ bool abuf_init_size(struct abuf *buf, size_t size) return true; } +bool abuf_copy(const struct abuf *old, struct abuf *copy) +{ + char *data; + + data = malloc(old->size); + if (!data) + return false; + memcpy(data, old->data, old->size); + abuf_init_set(copy, data, old->size); + copy->alloced = true; + + return true; +} + void abuf_init_const(struct abuf *abuf, const void *data, size_t size) { /* for now there is no flag indicating that the abuf data is constant */ diff --git a/test/lib/abuf.c b/test/lib/abuf.c index cdc86aad988..96c77ed2379 100644 --- a/test/lib/abuf.c +++ b/test/lib/abuf.c @@ -420,6 +420,29 @@ static int lib_test_abuf_init(struct unit_test_state *uts) } LIB_TEST(lib_test_abuf_init, 0); +/* Test abuf_copy() */ +static int lib_test_abuf_copy(struct unit_test_state *uts) +{ + struct abuf buf, copy; + ulong start; + + start = ut_check_free(); + + abuf_init_set(&buf, test_data, TEST_DATA_LEN); + ut_assert(abuf_copy(&buf, ©)); + ut_asserteq(buf.size, copy.size); + ut_assert(buf.data != copy.data); + ut_assert(copy.alloced); + abuf_uninit(©); + abuf_uninit(&buf); + + /* Check for memory leaks */ + ut_assertok(ut_check_delta(start)); + + return 0; +} +LIB_TEST(lib_test_abuf_copy, 0); + /* Test abuf_init_size() */ static int lib_test_abuf_init_size(struct unit_test_state *uts) { -- cgit v1.3.1 From 4f4b9477f4476cd86ffd4219111065d610c5237a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:04 -0600 Subject: abuf: Add a way to printf() into a buffer It is useful to format a string into a buffer, with the sizing handled automatically. Add a function for this. Signed-off-by: Simon Glass --- include/abuf.h | 21 ++++++++++++++++++++ lib/abuf.c | 35 +++++++++++++++++++++++++++++++++ test/lib/abuf.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 117 insertions(+) (limited to 'include') diff --git a/include/abuf.h b/include/abuf.h index bbb3c51f334..7872e9c9b27 100644 --- a/include/abuf.h +++ b/include/abuf.h @@ -122,6 +122,27 @@ bool abuf_realloc_inc(struct abuf *abuf, size_t inc); */ bool abuf_copy(const struct abuf *old, struct abuf *new); +/** + * abuf_printf() - Format a string and place it in an abuf + * + * @buf: The buffer to place the result into + * @fmt: The format string to use + * @...: Arguments for the format string + * Return: the number of characters writtenwhich would be + * generated for the given input, excluding the trailing null, + * as per ISO C99. + * + * The abuf is expanded as necessary to fit the formated string + * + * See the vsprintf() documentation for format string extensions over C99. + * + * Returns: number of characters written (excluding trailing nul) on success, + * -E2BIG if the size exceeds 4K, -ENOMEM if out of memory, -EFAULT if there is + * an internal bug in the vsnprintf() implementation + */ +int abuf_printf(struct abuf *buf, const char *fmt, ...) + __attribute__ ((format (__printf__, 2, 3))); + /** * abuf_uninit_move() - Return the allocated contents and uninit the abuf * diff --git a/lib/abuf.c b/lib/abuf.c index 28c748acb9f..3a2fd1782e9 100644 --- a/lib/abuf.c +++ b/lib/abuf.c @@ -10,8 +10,11 @@ #include #include #include +#include #endif +#include +#include #include void abuf_set(struct abuf *abuf, void *data, size_t size) @@ -142,6 +145,38 @@ bool abuf_copy(const struct abuf *old, struct abuf *copy) return true; } +int abuf_printf(struct abuf *buf, const char *fmt, ...) +{ + int maxlen = buf->size; + va_list args; + int len; + + va_start(args, fmt); + len = vsnprintf(buf->data, buf->size, fmt, args); + va_end(args); + + /* add the terminator */ + len++; + + if (len > 4096) + return -E2BIG; + if (len > maxlen) { + /* make more space and try again */ + maxlen = len; + if (!abuf_realloc(buf, maxlen)) + return -ENOMEM; + va_start(args, fmt); + len = vsnprintf(buf->data, maxlen, fmt, args); + va_end(args); + + /* check there isn't anything strange going on */ + if (len > maxlen) + return -EFAULT; + } + + return len; +} + void abuf_init_const(struct abuf *abuf, const void *data, size_t size) { /* for now there is no flag indicating that the abuf data is constant */ diff --git a/test/lib/abuf.c b/test/lib/abuf.c index 96c77ed2379..97b128c01c0 100644 --- a/test/lib/abuf.c +++ b/test/lib/abuf.c @@ -463,3 +463,64 @@ static int lib_test_abuf_init_size(struct unit_test_state *uts) return 0; } LIB_TEST(lib_test_abuf_init_size, 0); + +/* Test abuf_printf() */ +static int lib_test_abuf_printf(struct unit_test_state *uts) +{ + struct abuf buf, fmt; + ulong start; + char *ptr; + + start = ut_check_free(); + + /* start with a fresh buffer */ + abuf_init(&buf); + + /* check handling of out-of-memory condition */ + malloc_enable_testing(0); + ut_asserteq(-ENOMEM, abuf_printf(&buf, "%s", "")); + malloc_enable_testing(1); + + ut_asserteq(0, abuf_printf(&buf, "%s", "")); + ut_asserteq(1, buf.size); + ut_asserteq(true, buf.alloced); + ut_asserteq_str("", buf.data); + + /* check expanding it, initially failing */ + ut_asserteq(-ENOMEM, abuf_printf(&buf, "%s", "testing")); + malloc_disable_testing(); + + ut_asserteq(7, abuf_printf(&buf, "%s", "testing")); + ut_asserteq(8, buf.size); + ut_asserteq_str("testing", buf.data); + + ut_asserteq(11, abuf_printf(&buf, "testing %d", 123)); + ut_asserteq(12, buf.size); + ut_asserteq_str("testing 123", buf.data); + + /* make it smaller; buffer should not shrink */ + ut_asserteq(9, abuf_printf(&buf, "test %d", 456)); + ut_asserteq(12, buf.size); + ut_asserteq_str("test 456", buf.data); + + /* test the maximum size */ + abuf_init(&fmt); + ut_assert(abuf_realloc(&fmt, 4100)); + memset(fmt.data, 'x', 4100); + ptr = fmt.data; + ptr[4096] = '\0'; + + /* we are allowed up to 4K including the terminator */ + ut_asserteq(-E2BIG, abuf_printf(&buf, "%s", ptr)); + ptr[4095] = '\0'; + ut_asserteq(4095, abuf_printf(&buf, "%s", ptr)); + + abuf_uninit(&fmt); + abuf_uninit(&buf); + + /* Check for memory leaks */ + ut_assertok(ut_check_delta(start)); + + return 0; +} +LIB_TEST(lib_test_abuf_printf, 0); -- cgit v1.3.1 From 5c365ecabcac6d3218cf7e560bda01629a46d88e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:15 -0600 Subject: expo: Add CLI context to the expo An expo generally needs to keep track of the keyboard state while it is running, so move the context into struct expo Signed-off-by: Simon Glass --- boot/bootflow_menu.c | 9 +++------ boot/cedit.c | 8 +++----- boot/expo.c | 1 + include/expo.h | 2 ++ 4 files changed, 9 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/boot/bootflow_menu.c b/boot/bootflow_menu.c index 9d0dc352f97..43125e15832 100644 --- a/boot/bootflow_menu.c +++ b/boot/bootflow_menu.c @@ -178,7 +178,6 @@ int bootflow_menu_apply_theme(struct expo *exp, ofnode node) int bootflow_menu_run(struct bootstd_priv *std, bool text_mode, struct bootflow **bflowp) { - struct cli_ch_state s_cch, *cch = &s_cch; struct bootflow *sel_bflow; struct udevice *dev; struct expo *exp; @@ -186,8 +185,6 @@ int bootflow_menu_run(struct bootstd_priv *std, bool text_mode, bool done; int ret; - cli_ch_init(cch); - sel_bflow = NULL; *bflowp = NULL; @@ -225,16 +222,16 @@ int bootflow_menu_run(struct bootstd_priv *std, bool text_mode, if (ret) break; - ichar = cli_ch_process(cch, 0); + ichar = cli_ch_process(&exp->cch, 0); if (!ichar) { while (!ichar && !tstc()) { schedule(); mdelay(2); - ichar = cli_ch_process(cch, -ETIMEDOUT); + ichar = cli_ch_process(&exp->cch, -ETIMEDOUT); } if (!ichar) { ichar = getchar(); - ichar = cli_ch_process(cch, ichar); + ichar = cli_ch_process(&exp->cch, ichar); } } diff --git a/boot/cedit.c b/boot/cedit.c index 4e80875828b..ed499f11140 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -151,14 +151,12 @@ int cedit_prepare(struct expo *exp, struct video_priv **vid_privp, int cedit_run(struct expo *exp) { - struct cli_ch_state s_cch, *cch = &s_cch; struct video_priv *vid_priv; uint scene_id; struct scene *scn; bool done, save; int ret; - cli_ch_init(cch); ret = cedit_prepare(exp, &vid_priv, &scn); if (ret < 0) return log_msg_ret("prep", ret); @@ -174,16 +172,16 @@ int cedit_run(struct expo *exp) if (ret) break; - ichar = cli_ch_process(cch, 0); + ichar = cli_ch_process(&exp->cch, 0); if (!ichar) { while (!ichar && !tstc()) { schedule(); mdelay(2); - ichar = cli_ch_process(cch, -ETIMEDOUT); + ichar = cli_ch_process(&exp->cch, -ETIMEDOUT); } if (!ichar) { ichar = getchar(); - ichar = cli_ch_process(cch, ichar); + ichar = cli_ch_process(&exp->cch, ichar); } } diff --git a/boot/expo.c b/boot/expo.c index 8ce645e5a8f..9c042f16fe7 100644 --- a/boot/expo.c +++ b/boot/expo.c @@ -30,6 +30,7 @@ int expo_new(const char *name, void *priv, struct expo **expp) INIT_LIST_HEAD(&exp->scene_head); INIT_LIST_HEAD(&exp->str_head); exp->next_id = EXPOID_BASE_ID; + cli_ch_init(&exp->cch); *expp = exp; diff --git a/include/expo.h b/include/expo.h index 3c383d2e2ee..b3b9c0b8872 100644 --- a/include/expo.h +++ b/include/expo.h @@ -108,6 +108,7 @@ struct expo_theme { * @theme: Information about fonts styles, etc. * @scene_head: List of scenes * @str_head: list of strings + * @cch: Keyboard context for input */ struct expo { char *name; @@ -122,6 +123,7 @@ struct expo { struct expo_theme theme; struct list_head scene_head; struct list_head str_head; + struct cli_ch_state cch; }; /** -- cgit v1.3.1 From bf9860459516d1837e92270340ca307211cd961a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:16 -0600 Subject: expo: Add a function to poll for input Both bootflow_menu and cedit use similar logic to poll an expo. Move this into the expo library so the code can be shared. Update bootflow_menu_run() to return -EPIPE when the user quits without choosing anything, since -EAGAIN is ambiguous and elsewhere means that there is no input yet. Signed-off-by: Simon Glass --- boot/bootflow_menu.c | 41 ++++------------------------------------- boot/cedit.c | 35 +++-------------------------------- boot/expo.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ cmd/bootflow.c | 2 +- include/bootflow.h | 2 +- include/expo.h | 13 +++++++++++++ 6 files changed, 66 insertions(+), 71 deletions(-) (limited to 'include') diff --git a/boot/bootflow_menu.c b/boot/bootflow_menu.c index 43125e15832..268c93ae8e3 100644 --- a/boot/bootflow_menu.c +++ b/boot/bootflow_menu.c @@ -216,39 +216,8 @@ int bootflow_menu_run(struct bootstd_priv *std, bool text_mode, done = false; do { struct expo_action act; - int ichar, key; - ret = expo_render(exp); - if (ret) - break; - - ichar = cli_ch_process(&exp->cch, 0); - if (!ichar) { - while (!ichar && !tstc()) { - schedule(); - mdelay(2); - ichar = cli_ch_process(&exp->cch, -ETIMEDOUT); - } - if (!ichar) { - ichar = getchar(); - ichar = cli_ch_process(&exp->cch, ichar); - } - } - - key = 0; - if (ichar) { - key = bootmenu_conv_key(ichar); - if (key == BKEY_NONE) - key = ichar; - } - if (!key) - continue; - - ret = expo_send_key(exp, key); - if (ret) - break; - - ret = expo_action_get(exp, &act); + ret = expo_poll(exp, &act); if (!ret) { switch (act.type) { case EXPOACT_SELECT: @@ -256,17 +225,15 @@ int bootflow_menu_run(struct bootstd_priv *std, bool text_mode, done = true; break; case EXPOACT_QUIT: - done = true; - break; + return -EPIPE; default: break; } + } else if (ret != -EPIPE && ret != -EAGAIN) { + return log_msg_ret("bmr", ret); } } while (!done); - if (ret) - return log_msg_ret("end", ret); - if (sel_id) { struct bootflow *bflow; int i; diff --git a/boot/cedit.c b/boot/cedit.c index ed499f11140..b7b9cc510e0 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -166,39 +166,8 @@ int cedit_run(struct expo *exp) save = false; do { struct expo_action act; - int ichar, key; - ret = expo_render(exp); - if (ret) - break; - - ichar = cli_ch_process(&exp->cch, 0); - if (!ichar) { - while (!ichar && !tstc()) { - schedule(); - mdelay(2); - ichar = cli_ch_process(&exp->cch, -ETIMEDOUT); - } - if (!ichar) { - ichar = getchar(); - ichar = cli_ch_process(&exp->cch, ichar); - } - } - - key = 0; - if (ichar) { - key = bootmenu_conv_key(ichar); - if (key == BKEY_NONE || key >= BKEY_FIRST_EXTRA) - key = ichar; - } - if (!key) - continue; - - ret = expo_send_key(exp, key); - if (ret) - break; - - ret = expo_action_get(exp, &act); + ret = expo_poll(exp, &act); if (!ret) { switch (act.type) { case EXPOACT_POINT_OBJ: @@ -233,6 +202,8 @@ int cedit_run(struct expo *exp) default: break; } + } else if (ret != -EAGAIN) { + return log_msg_ret("cep", ret); } } while (!done); diff --git a/boot/expo.c b/boot/expo.c index 9c042f16fe7..301bbfa5f9a 100644 --- a/boot/expo.c +++ b/boot/expo.c @@ -10,8 +10,12 @@ #include #include +#include #include +#include #include +#include +#include #include "scene_internal.h" int expo_new(const char *name, void *priv, struct expo **expp) @@ -286,3 +290,43 @@ int expo_iter_scene_objs(struct expo *exp, expo_scene_obj_iterator iter, return 0; } + +int expo_poll(struct expo *exp, struct expo_action *act) +{ + int ichar, key, ret; + + ret = expo_render(exp); + if (ret) + return log_msg_ret("ere", ret); + + ichar = cli_ch_process(&exp->cch, 0); + if (!ichar) { + while (!ichar && !tstc()) { + schedule(); + mdelay(2); + ichar = cli_ch_process(&exp->cch, -ETIMEDOUT); + } + if (!ichar) { + ichar = getchar(); + ichar = cli_ch_process(&exp->cch, ichar); + } + } + + key = 0; + if (ichar) { + key = bootmenu_conv_key(ichar); + if (key == BKEY_NONE || key >= BKEY_FIRST_EXTRA) + key = ichar; + } + if (!key) + return -EAGAIN; + + ret = expo_send_key(exp, key); + if (ret) + return log_msg_ret("epk", ret); + ret = expo_action_get(exp, act); + if (ret) + return log_msg_ret("eag", ret); + + return 0; +} diff --git a/cmd/bootflow.c b/cmd/bootflow.c index d4f7d336150..f2662239714 100644 --- a/cmd/bootflow.c +++ b/cmd/bootflow.c @@ -110,7 +110,7 @@ __maybe_unused static int bootflow_handle_menu(struct bootstd_priv *std, ret = bootflow_menu_run(std, text_mode, &bflow); if (ret) { - if (ret == -EAGAIN) { + if (ret == -EPIPE) { printf("Nothing chosen\n"); std->cur_bootflow = NULL; } else { diff --git a/include/bootflow.h b/include/bootflow.h index d408b8c85bd..fe090d39ffb 100644 --- a/include/bootflow.h +++ b/include/bootflow.h @@ -508,7 +508,7 @@ int bootflow_menu_apply_theme(struct expo *exp, ofnode node); * @std: Bootstd information * @text_mode: Uses a text-based menu suitable for a serial port * @bflowp: Returns chosen bootflow (set to NULL if nothing is chosen) - * @return 0 if an option was chosen, -EAGAIN if nothing was chosen, -ve on + * @return 0 if an option was chosen, -EPIPE if nothing was chosen, -ve on * error */ int bootflow_menu_run(struct bootstd_priv *std, bool text_mode, diff --git a/include/expo.h b/include/expo.h index b3b9c0b8872..63452bbdd6a 100644 --- a/include/expo.h +++ b/include/expo.h @@ -772,4 +772,17 @@ int expo_build(ofnode root, struct expo **expp); */ int cb_expo_build(struct expo **expp); +/** + * expo_poll() - render an expo and see if the user takes an action + * + * Thsi calls expo_render() and then checks for a keypress. If there is one, it + * is processed and the resulting action returned, if any + * + * @exp: Expo to poll + * @act: Returns action on success + * Return: 0 if an action was obtained, -EAGAIN if not, other error if something + * went wrong + */ +int expo_poll(struct expo *exp, struct expo_action *act); + #endif /*__EXPO_H */ -- cgit v1.3.1 From 932ea4a1044455e7bcb48fb1391ea7e06137fad5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:20 -0600 Subject: expo: Move cedit-state fields into expo Move the boolean flags into struct expo so that the state can be maintained over function calls. Signed-off-by: Simon Glass --- boot/cedit.c | 17 ++++++++--------- include/expo.h | 4 ++++ 2 files changed, 12 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/boot/cedit.c b/boot/cedit.c index b7b9cc510e0..8c6948d1d46 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -154,7 +154,6 @@ int cedit_run(struct expo *exp) struct video_priv *vid_priv; uint scene_id; struct scene *scn; - bool done, save; int ret; ret = cedit_prepare(exp, &vid_priv, &scn); @@ -162,8 +161,8 @@ int cedit_run(struct expo *exp) return log_msg_ret("prep", ret); scene_id = ret; - done = false; - save = false; + exp->done = false; + exp->save = false; do { struct expo_action act; @@ -179,11 +178,11 @@ int cedit_run(struct expo *exp) cedit_arange(exp, vid_priv, scene_id); switch (scn->highlight_id) { case EXPOID_SAVE: - done = true; - save = true; + exp->done = true; + exp->save = true; break; case EXPOID_DISCARD: - done = true; + exp->done = true; break; } break; @@ -197,7 +196,7 @@ int cedit_run(struct expo *exp) break; case EXPOACT_QUIT: log_debug("quitting\n"); - done = true; + exp->done = true; break; default: break; @@ -205,11 +204,11 @@ int cedit_run(struct expo *exp) } else if (ret != -EAGAIN) { return log_msg_ret("cep", ret); } - } while (!done); + } while (!exp->done); if (ret) return log_msg_ret("end", ret); - if (!save) + if (!exp->save) return -EACCES; return 0; diff --git a/include/expo.h b/include/expo.h index 63452bbdd6a..f8d44c0ea20 100644 --- a/include/expo.h +++ b/include/expo.h @@ -105,6 +105,8 @@ struct expo_theme { * @text_mode: true to use text mode for the menu (no vidconsole) * @popup: true to use popup menus, instead of showing all items * @priv: Private data for the controller + * @done: Indicates that a cedit session is complete and the user has quit + * @save: Indicates that cedit data should be saved, rather than discarded * @theme: Information about fonts styles, etc. * @scene_head: List of scenes * @str_head: list of strings @@ -120,6 +122,8 @@ struct expo { bool text_mode; bool popup; void *priv; + bool done; + bool save; struct expo_theme theme; struct list_head scene_head; struct list_head str_head; -- cgit v1.3.1 From 5f993342962de816044f4172234ca7ecfd2bcaf6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:21 -0600 Subject: expo: Test some cedit actions Refactor the action-processing code into a new cedit_do_action() function so we can call it from a test. Check moving to a new field and opening the menu, to ensure that rendering is correct. Signed-off-by: Simon Glass --- boot/cedit.c | 80 ++++++++++++++++++++++++++++++------------------------- include/cedit.h | 13 +++++++++ test/boot/cedit.c | 43 ++++++++++++++++++++++++++++++ 3 files changed, 100 insertions(+), 36 deletions(-) (limited to 'include') diff --git a/boot/cedit.c b/boot/cedit.c index 8c6948d1d46..f1a9ee7ce20 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -149,6 +149,47 @@ int cedit_prepare(struct expo *exp, struct video_priv **vid_privp, return scene_id; } +int cedit_do_action(struct expo *exp, struct scene *scn, + struct video_priv *vid_priv, struct expo_action *act) +{ + switch (act->type) { + case EXPOACT_NONE: + case EXPOACT_POINT_ITEM: + return -EAGAIN; + case EXPOACT_POINT_OBJ: + scene_set_highlight_id(scn, act->select.id); + cedit_arange(exp, vid_priv, scn->id); + break; + case EXPOACT_OPEN: + scene_set_open(scn, act->select.id, true); + cedit_arange(exp, vid_priv, scn->id); + switch (scn->highlight_id) { + case EXPOID_SAVE: + exp->done = true; + exp->save = true; + break; + case EXPOID_DISCARD: + exp->done = true; + break; + } + break; + case EXPOACT_CLOSE: + scene_set_open(scn, act->select.id, false); + cedit_arange(exp, vid_priv, scn->id); + break; + case EXPOACT_SELECT: + scene_set_open(scn, scn->highlight_id, false); + cedit_arange(exp, vid_priv, scn->id); + break; + case EXPOACT_QUIT: + log_debug("quitting\n"); + exp->done = true; + break; + } + + return 0; +} + int cedit_run(struct expo *exp) { struct video_priv *vid_priv; @@ -167,43 +208,10 @@ int cedit_run(struct expo *exp) struct expo_action act; ret = expo_poll(exp, &act); - if (!ret) { - switch (act.type) { - case EXPOACT_POINT_OBJ: - scene_set_highlight_id(scn, act.select.id); - cedit_arange(exp, vid_priv, scene_id); - break; - case EXPOACT_OPEN: - scene_set_open(scn, act.select.id, true); - cedit_arange(exp, vid_priv, scene_id); - switch (scn->highlight_id) { - case EXPOID_SAVE: - exp->done = true; - exp->save = true; - break; - case EXPOID_DISCARD: - exp->done = true; - break; - } - break; - case EXPOACT_CLOSE: - scene_set_open(scn, act.select.id, false); - cedit_arange(exp, vid_priv, scene_id); - break; - case EXPOACT_SELECT: - scene_set_open(scn, scn->highlight_id, false); - cedit_arange(exp, vid_priv, scene_id); - break; - case EXPOACT_QUIT: - log_debug("quitting\n"); - exp->done = true; - break; - default: - break; - } - } else if (ret != -EAGAIN) { + if (!ret) + cedit_do_action(exp, scn, vid_priv, &act); + else if (ret != -EAGAIN) return log_msg_ret("cep", ret); - } } while (!exp->done); if (ret) diff --git a/include/cedit.h b/include/cedit.h index 856509f0c7f..a9305ceebcb 100644 --- a/include/cedit.h +++ b/include/cedit.h @@ -13,6 +13,7 @@ struct abuf; struct expo; +struct expo_action; struct scene; struct udevice; struct video_priv; @@ -62,6 +63,18 @@ int cedit_run(struct expo *exp); int cedit_prepare(struct expo *exp, struct video_priv **vid_privp, struct scene **scnp); +/** + * cedit_do_action() - Process an action on a cedit + * + * @exp: Expo to use + * @scn: Current scene + * @vid_priv: Private data for the video device + * @act: Action to process + * Return: 0 on success, -EAGAIN if there was no action taken + */ +int cedit_do_action(struct expo *exp, struct scene *scn, + struct video_priv *vid_priv, struct expo_action *act); + /** * cedit_write_settings() - Write settings in FDT format * diff --git a/test/boot/cedit.c b/test/boot/cedit.c index df191a09f89..5b3e9b586a6 100644 --- a/test/boot/cedit.c +++ b/test/boot/cedit.c @@ -226,8 +226,10 @@ BOOTSTD_TEST(cedit_cmos, UTF_CONSOLE); /* Check the cedit displays correctely */ static int cedit_render(struct unit_test_state *uts) { + struct scene_obj_menu *menu; struct video_priv *vid_priv; extern struct expo *cur_exp; + struct expo_action act; struct udevice *dev; struct scene *scn; struct expo *exp; @@ -237,9 +239,50 @@ static int cedit_render(struct unit_test_state *uts) exp = cur_exp; ut_assertok(uclass_first_device_err(UCLASS_VIDEO, &dev)); ut_asserteq(ID_SCENE1, cedit_prepare(exp, &vid_priv, &scn)); + + menu = scene_obj_find(scn, ID_POWER_LOSS, SCENEOBJT_MENU); + ut_assertnonnull(menu); + ut_asserteq(ID_AC_OFF, menu->cur_item_id); + ut_assertok(expo_render(exp)); ut_asserteq(4929, video_compress_fb(uts, dev, false)); ut_assertok(video_check_copy_fb(uts, dev)); + + /* move to the second menu */ + act.type = EXPOACT_POINT_OBJ; + act.select.id = ID_POWER_LOSS; + ut_assertok(cedit_do_action(exp, scn, vid_priv, &act)); + ut_assertok(expo_render(exp)); + ut_asserteq(4986, video_compress_fb(uts, dev, false)); + + /* open the menu */ + act.type = EXPOACT_OPEN; + act.select.id = ID_POWER_LOSS; + ut_assertok(cedit_do_action(exp, scn, vid_priv, &act)); + ut_assertok(expo_render(exp)); + ut_asserteq(5393, video_compress_fb(uts, dev, false)); + + /* close the menu */ + act.type = EXPOACT_CLOSE; + act.select.id = ID_POWER_LOSS; + ut_assertok(cedit_do_action(exp, scn, vid_priv, &act)); + ut_assertok(expo_render(exp)); + ut_asserteq(4986, video_compress_fb(uts, dev, false)); + + /* open the menu again to check it looks the same */ + act.type = EXPOACT_OPEN; + act.select.id = ID_POWER_LOSS; + ut_assertok(cedit_do_action(exp, scn, vid_priv, &act)); + ut_assertok(expo_render(exp)); + ut_asserteq(5393, video_compress_fb(uts, dev, false)); + + /* close the menu */ + act.type = EXPOACT_CLOSE; + act.select.id = ID_POWER_LOSS; + ut_assertok(cedit_do_action(exp, scn, vid_priv, &act)); + ut_assertok(expo_render(exp)); + ut_asserteq(4986, video_compress_fb(uts, dev, false)); + expo_destroy(exp); cur_exp = NULL; -- cgit v1.3.1 From 23d2ddf1b4663c497ae6223174c96138df8b675a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:22 -0600 Subject: expo: Pass in the video device for cedit_prepare() At present this function locates it own video device. Pass it in to provide more flexibility. Signed-off-by: Simon Glass --- boot/cedit.c | 18 ++++++++++-------- include/cedit.h | 4 ++-- test/boot/cedit.c | 20 ++++++++++++++++---- 3 files changed, 28 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/boot/cedit.c b/boot/cedit.c index f1a9ee7ce20..eac851b395a 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -100,19 +100,16 @@ int cedit_arange(struct expo *exp, struct video_priv *vpriv, uint scene_id) return 0; } -int cedit_prepare(struct expo *exp, struct video_priv **vid_privp, +int cedit_prepare(struct expo *exp, struct udevice *vid_dev, struct scene **scnp) { + struct udevice *dev = vid_dev; struct video_priv *vid_priv; - struct udevice *dev; struct scene *scn; uint scene_id; int ret; /* For now we only support a video console */ - ret = uclass_first_device_err(UCLASS_VIDEO, &dev); - if (ret) - return log_msg_ret("vid", ret); ret = expo_set_display(exp, dev); if (ret) return log_msg_ret("dis", ret); @@ -143,7 +140,6 @@ int cedit_prepare(struct expo *exp, struct video_priv **vid_privp, if (ret) return log_msg_ret("dim", ret); - *vid_privp = vid_priv; *scnp = scn; return scene_id; @@ -193,11 +189,17 @@ int cedit_do_action(struct expo *exp, struct scene *scn, int cedit_run(struct expo *exp) { struct video_priv *vid_priv; - uint scene_id; + struct udevice *dev; struct scene *scn; + uint scene_id; int ret; - ret = cedit_prepare(exp, &vid_priv, &scn); + ret = uclass_first_device_err(UCLASS_VIDEO, &dev); + if (ret) + return log_msg_ret("vid", ret); + vid_priv = dev_get_uclass_priv(dev); + + ret = cedit_prepare(exp, dev, &scn); if (ret < 0) return log_msg_ret("prep", ret); scene_id = ret; diff --git a/include/cedit.h b/include/cedit.h index a9305ceebcb..319a61aecb8 100644 --- a/include/cedit.h +++ b/include/cedit.h @@ -56,11 +56,11 @@ int cedit_run(struct expo *exp); * This ensures that all menus have a selected item. * * @exp: Expo to use - * @vid_privp: Set to private data for the video device + * @dev: Video device to use * @scnp: Set to the first scene * Return: scene ID of first scene if OK, -ve on error */ -int cedit_prepare(struct expo *exp, struct video_priv **vid_privp, +int cedit_prepare(struct expo *exp, struct udevice *vid_dev, struct scene **scnp); /** diff --git a/test/boot/cedit.c b/test/boot/cedit.c index 5b3e9b586a6..746f60067fd 100644 --- a/test/boot/cedit.c +++ b/test/boot/cedit.c @@ -63,6 +63,7 @@ static int cedit_fdt(struct unit_test_state *uts) struct video_priv *vid_priv; extern struct expo *cur_exp; struct scene_obj_menu *menu; + struct udevice *dev; ulong addr = 0x1000; struct ofprop prop; struct scene *scn; @@ -72,9 +73,12 @@ static int cedit_fdt(struct unit_test_state *uts) void *fdt; int i; + ut_assertok(uclass_first_device_err(UCLASS_VIDEO, &dev)); + vid_priv = dev_get_uclass_priv(dev); + ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0)); - ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn)); + ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, dev, &scn)); /* get a menu to fiddle with */ menu = scene_obj_find(scn, ID_CPU_SPEED, SCENEOBJT_MENU); @@ -134,12 +138,16 @@ static int cedit_env(struct unit_test_state *uts) struct video_priv *vid_priv; extern struct expo *cur_exp; struct scene_obj_menu *menu; + struct udevice *dev; struct scene *scn; char *str; ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0)); - ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn)); + ut_assertok(uclass_first_device_err(UCLASS_VIDEO, &dev)); + vid_priv = dev_get_uclass_priv(dev); + + ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, dev, &scn)); /* get a menu to fiddle with */ menu = scene_obj_find(scn, ID_CPU_SPEED, SCENEOBJT_MENU); @@ -189,11 +197,14 @@ static int cedit_cmos(struct unit_test_state *uts) struct scene_obj_menu *menu, *menu2; struct video_priv *vid_priv; extern struct expo *cur_exp; + struct udevice *dev; struct scene *scn; ut_assertok(run_command("cedit load hostfs - cedit.dtb", 0)); - ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, &vid_priv, &scn)); + ut_assertok(uclass_first_device_err(UCLASS_VIDEO, &dev)); + vid_priv = dev_get_uclass_priv(dev); + ut_asserteq(ID_SCENE1, cedit_prepare(cur_exp, dev, &scn)); /* get the menus to fiddle with */ menu = scene_obj_find(scn, ID_CPU_SPEED, SCENEOBJT_MENU); @@ -238,7 +249,8 @@ static int cedit_render(struct unit_test_state *uts) exp = cur_exp; ut_assertok(uclass_first_device_err(UCLASS_VIDEO, &dev)); - ut_asserteq(ID_SCENE1, cedit_prepare(exp, &vid_priv, &scn)); + vid_priv = dev_get_uclass_priv(dev); + ut_asserteq(ID_SCENE1, cedit_prepare(exp, dev, &scn)); menu = scene_obj_find(scn, ID_POWER_LOSS, SCENEOBJT_MENU); ut_assertnonnull(menu); -- cgit v1.3.1 From 9f44b544e1d8b23dec51567c657e81488a289d6d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:24 -0600 Subject: expo: Provide access to the current menu item Add functions to allow a caller to find out the current menu item and to select a different one. Update the event handling so that an attempt to change the current item (e.g. by pressing the up-arrow key) is reported to the caller, since this may be used to cancel an autoboot timeout. Signed-off-by: Simon Glass --- boot/scene_menu.c | 44 ++++++++++++++++++++++++++++++++++++++++---- include/expo.h | 20 ++++++++++++++++++++ test/boot/expo.c | 4 ++++ 3 files changed, 64 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/boot/scene_menu.c b/boot/scene_menu.c index 17150af145d..06d7e9fc913 100644 --- a/boot/scene_menu.c +++ b/boot/scene_menu.c @@ -121,12 +121,21 @@ static int update_pointers(struct scene_obj_menu *menu, uint id, bool point) * * Sets the currently pointed-to / highlighted menu item */ -static void menu_point_to_item(struct scene_obj_menu *menu, uint item_id) +static int menu_point_to_item(struct scene_obj_menu *menu, uint item_id) { - if (menu->cur_item_id) - update_pointers(menu, menu->cur_item_id, false); + int ret; + + if (menu->cur_item_id) { + ret = update_pointers(menu, menu->cur_item_id, false); + if (ret) + return log_msg_ret("mpi", ret); + } menu->cur_item_id = item_id; - update_pointers(menu, item_id, true); + ret = update_pointers(menu, item_id, true); + if (ret) + return log_msg_ret("mpu", ret); + + return 0; } void scene_menu_calc_bbox(struct scene_obj_menu *menu, @@ -483,6 +492,33 @@ int scene_menu_set_pointer(struct scene *scn, uint id, uint pointer_id) return 0; } +int scene_menu_select_item(struct scene *scn, uint id, uint cur_item_id) +{ + struct scene_obj_menu *menu; + int ret; + + menu = scene_obj_find(scn, id, SCENEOBJT_MENU); + if (!menu) + return log_msg_ret("menu", -ENOENT); + + ret = menu_point_to_item(menu, cur_item_id); + if (ret) + return log_msg_ret("msi", ret); + + return 0; +} + +int scene_menu_get_cur_item(struct scene *scn, uint id) +{ + struct scene_obj_menu *menu; + + menu = scene_obj_find(scn, id, SCENEOBJT_MENU); + if (!menu) + return log_msg_ret("menu", -ENOENT); + + return menu->cur_item_id; +} + int scene_menu_display(struct scene_obj_menu *menu) { struct scene *scn = menu->obj.scene; diff --git a/include/expo.h b/include/expo.h index f8d44c0ea20..a2b093c521d 100644 --- a/include/expo.h +++ b/include/expo.h @@ -689,6 +689,26 @@ int scene_menu_set_title(struct scene *scn, uint id, uint title_id); */ int scene_menu_set_pointer(struct scene *scn, uint id, uint cur_item_id); +/** + * scene_menu_select_item() - move the pointer/highlight to an item + * + * @scn: Scene to update + * @id: ID of menu object to update + * @sel_id: ID of the menuitem to select + * Return 0 on success, -ENOENT if there was no such item + */ +int scene_menu_select_item(struct scene *scn, uint id, uint sel_id); + +/** + * scene_menu_get_cur_item() - get the currently pointed-to item + * + * @scn: Scene to update + * @id: ID of menu object to update + * Return ID of the current item the menu is pointing to, -ENOENT if @id is not + * valid, 0 if no item is pointed to + */ +int scene_menu_get_cur_item(struct scene *scn, uint id); + /** * scene_obj_get_hw() - Get width and height of an object in a scene * diff --git a/test/boot/expo.c b/test/boot/expo.c index 1d283a2ac95..616071ead48 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -588,6 +588,8 @@ static int expo_render_image(struct unit_test_state *uts) expo_set_scene_id(exp, SCENE1); ut_assertok(expo_render(exp)); + ut_asserteq(0, scn->highlight_id); + /* move down */ ut_assertok(expo_send_key(exp, BKEY_DOWN)); @@ -595,6 +597,8 @@ static int expo_render_image(struct unit_test_state *uts) ut_asserteq(EXPOACT_POINT_ITEM, act.type); ut_asserteq(ITEM2, act.select.id); + ut_assertok(scene_menu_select_item(scn, OBJ_MENU, act.select.id)); + ut_asserteq(ITEM2, scene_menu_get_cur_item(scn, OBJ_MENU)); ut_assertok(expo_render(exp)); /* make sure only the preview for the second item is shown */ -- cgit v1.3.1 From b991a0c8bf30095837b096acd691e0d2add07b8c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:27 -0600 Subject: expo: Split bootflow_menu_run() into two pieces Split the starting piece of this function into bootflow_menu_start() and the polling part into bootflow_menu_poll() so that it is possible for the caller to be in control of the event loop. Move the expo_destroy() call into the caller. Signed-off-by: Simon Glass --- boot/bootflow_menu.c | 89 ++++++++++++++++++++++++---------------------------- cmd/bootflow.c | 36 +++++++++++++-------- include/bootflow.h | 33 ++++++++++++------- 3 files changed, 85 insertions(+), 73 deletions(-) (limited to 'include') diff --git a/boot/bootflow_menu.c b/boot/bootflow_menu.c index f9ebc526200..ed7c0768c7b 100644 --- a/boot/bootflow_menu.c +++ b/boot/bootflow_menu.c @@ -175,20 +175,13 @@ int bootflow_menu_apply_theme(struct expo *exp, ofnode node) return 0; } -int bootflow_menu_run(struct bootstd_priv *std, bool text_mode, - struct bootflow **bflowp) +int bootflow_menu_start(struct bootstd_priv *std, bool text_mode, + struct expo **expp) { - struct bootflow *sel_bflow; struct udevice *dev; - struct scene *scn; struct expo *exp; - uint sel_id; - bool done; int ret; - sel_bflow = NULL; - *bflowp = NULL; - ret = bootflow_menu_new(&exp); if (ret) return log_msg_ret("exp", ret); @@ -210,58 +203,58 @@ int bootflow_menu_run(struct bootstd_priv *std, bool text_mode, ret = expo_set_scene_id(exp, MAIN); if (ret) return log_msg_ret("scn", ret); - scn = expo_lookup_scene_id(exp, MAIN); - if (!scn) - return log_msg_ret("scn", -ENOENT); if (text_mode) expo_set_text_mode(exp, text_mode); - done = false; - do { - struct expo_action act; - - ret = expo_poll(exp, &act); - if (!ret) { - switch (act.type) { - case EXPOACT_SELECT: - sel_id = act.select.id; - done = true; - break; - case EXPOACT_POINT_ITEM: - ret = scene_menu_select_item(scn, - OBJ_MENU, act.select.id); - if (ret) - return log_msg_ret("bmp", ret); - break; - case EXPOACT_QUIT: - return -EPIPE; - default: - break; - } - } else if (ret != -EPIPE && ret != -EAGAIN) { - return log_msg_ret("bmr", ret); - } - } while (!done); + *expp = exp; + + return 0; +} - if (sel_id) { +int bootflow_menu_poll(struct expo *exp, struct bootflow **bflowp) +{ + struct bootflow *sel_bflow; + struct expo_action act; + int ret; + + sel_bflow = NULL; + *bflowp = NULL; + + ret = expo_poll(exp, &act); + if (ret) + return log_msg_ret("bmp", ret); + + switch (act.type) { + case EXPOACT_SELECT: { struct bootflow *bflow; int i; for (ret = bootflow_first_glob(&bflow), i = 0; !ret && i < 36; ret = bootflow_next_glob(&bflow), i++) { - if (i == sel_id - ITEM) { - sel_bflow = bflow; - break; + if (i == act.select.id - ITEM) { + *bflowp = bflow; + // printf("found %p\n", bflow); + return 0; } } + break; } + case EXPOACT_POINT_ITEM: { + struct scene *scn = expo_lookup_scene_id(exp, MAIN); - expo_destroy(exp); - - if (!sel_bflow) - return -EAGAIN; - *bflowp = sel_bflow; + if (!scn) + return log_msg_ret("bms", -ENOENT); + ret = scene_menu_select_item(scn, OBJ_MENU, act.select.id); + if (ret) + return log_msg_ret("bmp", ret); + break; + } + case EXPOACT_QUIT: + return -EPIPE; + default: + break; + } - return 0; + return -EAGAIN; } diff --git a/cmd/bootflow.c b/cmd/bootflow.c index f2662239714..efac27a5d77 100644 --- a/cmd/bootflow.c +++ b/cmd/bootflow.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #include /** @@ -105,24 +107,32 @@ __maybe_unused static int bootflow_handle_menu(struct bootstd_priv *std, bool text_mode, struct bootflow **bflowp) { + struct expo *exp; struct bootflow *bflow; int ret; - ret = bootflow_menu_run(std, text_mode, &bflow); - if (ret) { - if (ret == -EPIPE) { - printf("Nothing chosen\n"); - std->cur_bootflow = NULL; - } else { - printf("Menu failed (err=%d)\n", ret); - } + ret = bootflow_menu_start(std, text_mode, &exp); + if (ret) + return log_msg_ret("bhs", ret); - return ret; - } + do { + ret = bootflow_menu_poll(exp, &bflow); + } while (ret == -EAGAIN); - printf("Selected: %s\n", bflow->os_name ? bflow->os_name : bflow->name); - std->cur_bootflow = bflow; - *bflowp = bflow; + if (ret == -EPIPE) { + printf("Nothing chosen\n"); + std->cur_bootflow = NULL; + } else if (ret) { + printf("Menu failed (err=%d)\n", ret); + } else { + printf("Selected: %s\n", bflow->os_name ? bflow->os_name : + bflow->name); + std->cur_bootflow = bflow; + *bflowp = bflow; + } + expo_destroy(exp); + if (ret) + return ret; return 0; } diff --git a/include/bootflow.h b/include/bootflow.h index fe090d39ffb..8244d4fca18 100644 --- a/include/bootflow.h +++ b/include/bootflow.h @@ -502,18 +502,6 @@ int bootflow_menu_new(struct expo **expp); */ int bootflow_menu_apply_theme(struct expo *exp, ofnode node); -/** - * bootflow_menu_run() - Create and run a menu of available bootflows - * - * @std: Bootstd information - * @text_mode: Uses a text-based menu suitable for a serial port - * @bflowp: Returns chosen bootflow (set to NULL if nothing is chosen) - * @return 0 if an option was chosen, -EPIPE if nothing was chosen, -ve on - * error - */ -int bootflow_menu_run(struct bootstd_priv *std, bool text_mode, - struct bootflow **bflowp); - #define BOOTFLOWCL_EMPTY ((void *)1) /** @@ -638,4 +626,25 @@ struct bootflow_img *bootflow_img_add(struct bootflow *bflow, const char *fname, */ int bootflow_get_seq(const struct bootflow *bflow); +/** + * bootflow_menu_start() - Start up a menu for bootflows + * + * @std: bootstd information + * @text_mode: true to show the menu in text mode, false to use video display + * @expp: Returns the expo created, on success + * Return: 0 if OK, -ve on error + */ +int bootflow_menu_start(struct bootstd_priv *std, bool text_mode, + struct expo **expp); + +/** + * bootflow_menu_poll() - Poll a menu for user action + * + * @exp: Expo to poll + * @bflowp: Returns chosen bootflow (set to NULL if nothing is chosen) + * Return 0 if a bootflow was chosen, -EAGAIN if nothing is chosen yet, -EPIPE + * if the user quit + */ +int bootflow_menu_poll(struct expo *exp, struct bootflow **bflowp); + #endif -- cgit v1.3.1 From da754e20c99a0e611b05c74f9e28daf9cdf1a199 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:28 -0600 Subject: expo: Split bootflow_menu_new() into two pieces Split the iteration piece of this function into bootflow_menu_add_all() so that it is possible for the caller to be in control of adding items to the menu. Move the expo_destroy() call into the caller. Signed-off-by: Simon Glass --- boot/bootflow_menu.c | 31 +++++++++++++++++++++++++------ include/bootflow.h | 13 +++++++++++++ test/boot/bootflow.c | 1 + 3 files changed, 39 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/boot/bootflow_menu.c b/boot/bootflow_menu.c index ed7c0768c7b..f731d7858b2 100644 --- a/boot/bootflow_menu.c +++ b/boot/bootflow_menu.c @@ -32,14 +32,12 @@ struct menu_priv { int bootflow_menu_new(struct expo **expp) { - struct udevice *last_bootdev; struct scene_obj_menu *menu; struct menu_priv *priv; - struct bootflow *bflow; struct scene *scn; struct expo *exp; void *logo; - int ret, i; + int ret; priv = calloc(1, sizeof(*priv)); if (!priv) @@ -74,6 +72,26 @@ int bootflow_menu_new(struct expo **expp) if (ret < 0) return log_msg_ret("new", -EINVAL); + *expp = exp; + + return 0; +} + +int bootflow_menu_add_all(struct expo *exp) +{ + struct menu_priv *priv = exp->priv; + struct udevice *last_bootdev; + struct bootflow *bflow; + struct scene *scn; + uint scene_id; + int ret, i; + + ret = expo_first_scene_id(exp); + if (ret < 0) + return log_msg_ret("scn", ret); + scene_id = ret; + scn = expo_lookup_scene_id(exp, scene_id); + last_bootdev = NULL; for (ret = bootflow_first_glob(&bflow), i = 0; !ret && i < 36; ret = bootflow_next_glob(&bflow), i++) { @@ -133,8 +151,6 @@ int bootflow_menu_new(struct expo **expp) if (ret) return log_msg_ret("arr", ret); - *expp = exp; - return 0; } @@ -184,7 +200,10 @@ int bootflow_menu_start(struct bootstd_priv *std, bool text_mode, ret = bootflow_menu_new(&exp); if (ret) - return log_msg_ret("exp", ret); + return log_msg_ret("bmn", ret); + ret = bootflow_menu_add_all(exp); + if (ret) + return log_msg_ret("bma", ret); if (ofnode_valid(std->theme)) { ret = bootflow_menu_apply_theme(exp, std->theme); diff --git a/include/bootflow.h b/include/bootflow.h index 8244d4fca18..994b38394e8 100644 --- a/include/bootflow.h +++ b/include/bootflow.h @@ -488,11 +488,24 @@ int bootflow_iter_check_system(const struct bootflow_iter *iter); /** * bootflow_menu_new() - Create a new bootflow menu * + * This is initially empty. Call bootflow_menu_add_all() to add all the + * bootflows to it. + * * @expp: Returns the expo created * Returns 0 on success, -ve on error */ int bootflow_menu_new(struct expo **expp); +/** + * bootflow_menu_add_all() - Add all bootflows to a menu + * + * Loops through all bootflows and adds them to the menu + * + * @exp: Menu to update + * Return 0 on success, -ve on error + */ +int bootflow_menu_add_all(struct expo *exp); + /** * bootflow_menu_apply_theme() - Apply a theme to a bootmenu * diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index a930d2cc309..58885b5d8bf 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -878,6 +878,7 @@ static int bootflow_menu_theme(struct unit_test_state *uts) ut_assertok(scan_mmc4_bootdev(uts)); ut_assertok(bootflow_menu_new(&exp)); + ut_assertok(bootflow_menu_add_all(exp)); node = ofnode_path("/bootstd/theme"); ut_assert(ofnode_valid(node)); ut_assertok(bootflow_menu_apply_theme(exp, node)); -- cgit v1.3.1 From a4ede5e0aced904efb17f3a3d5fb2c7f3c622133 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:29 -0600 Subject: expo: Allow adding a single bootflow to a menu Refactor bootflow_menu_add_all() to call a new bootflow_menu_add() to add each of its bootflows. Move the last_bootdev value into struct menu_priv to make this work. Signed-off-by: Simon Glass --- boot/bootflow_menu.c | 103 +++++++++++++++++++++++++++++---------------------- include/bootflow.h | 16 ++++++++ 2 files changed, 75 insertions(+), 44 deletions(-) (limited to 'include') diff --git a/boot/bootflow_menu.c b/boot/bootflow_menu.c index f731d7858b2..6a37fa8fa68 100644 --- a/boot/bootflow_menu.c +++ b/boot/bootflow_menu.c @@ -25,9 +25,11 @@ * struct menu_priv - information about the menu * * @num_bootflows: Number of bootflows in the menu + * @last_bootdev: bootdev of the last bootflow added to the menu, NULL if none */ struct menu_priv { int num_bootflows; + struct udevice *last_bootdev; }; int bootflow_menu_new(struct expo **expp) @@ -77,14 +79,16 @@ int bootflow_menu_new(struct expo **expp) return 0; } -int bootflow_menu_add_all(struct expo *exp) +int bootflow_menu_add(struct expo *exp, struct bootflow *bflow, int seq, + struct scene **scnp) { struct menu_priv *priv = exp->priv; - struct udevice *last_bootdev; - struct bootflow *bflow; + char str[2], *label, *key; struct scene *scn; + uint preview_id; uint scene_id; - int ret, i; + bool add_gap; + int ret; ret = expo_first_scene_id(exp); if (ret < 0) @@ -92,13 +96,57 @@ int bootflow_menu_add_all(struct expo *exp) scene_id = ret; scn = expo_lookup_scene_id(exp, scene_id); - last_bootdev = NULL; + *str = seq < 10 ? '0' + seq : 'A' + seq - 10; + str[1] = '\0'; + key = strdup(str); + if (!key) + return log_msg_ret("key", -ENOMEM); + label = strdup(dev_get_parent(bflow->dev)->name); + if (!label) { + free(key); + return log_msg_ret("nam", -ENOMEM); + } + + add_gap = priv->last_bootdev != bflow->dev; + priv->last_bootdev = bflow->dev; + + ret = expo_str(exp, "prompt", STR_POINTER, ">"); + ret |= scene_txt_str(scn, "label", ITEM_LABEL + seq, + STR_LABEL + seq, label, NULL); + ret |= scene_txt_str(scn, "desc", ITEM_DESC + seq, STR_DESC + seq, + bflow->os_name ? bflow->os_name : + bflow->name, NULL); + ret |= scene_txt_str(scn, "key", ITEM_KEY + seq, STR_KEY + seq, key, + NULL); + preview_id = 0; + if (bflow->logo) { + preview_id = ITEM_PREVIEW + seq; + ret |= scene_img(scn, "preview", preview_id, + bflow->logo, NULL); + } + ret |= scene_menuitem(scn, OBJ_MENU, "item", ITEM + seq, + ITEM_KEY + seq, ITEM_LABEL + seq, + ITEM_DESC + seq, preview_id, + add_gap ? SCENEMIF_GAP_BEFORE : 0, + NULL); + + if (ret < 0) + return log_msg_ret("itm", -EINVAL); + priv->num_bootflows++; + *scnp = scn; + + return 0; +} + +int bootflow_menu_add_all(struct expo *exp) +{ + struct bootflow *bflow; + struct scene *scn; + int ret, i; + for (ret = bootflow_first_glob(&bflow), i = 0; !ret && i < 36; ret = bootflow_next_glob(&bflow), i++) { struct bootmeth_uc_plat *ucp; - char str[2], *label, *key; - uint preview_id; - bool add_gap; if (bflow->state != BOOTFLOWST_READY) continue; @@ -108,43 +156,10 @@ int bootflow_menu_add_all(struct expo *exp) if (ucp->flags & BOOTMETHF_GLOBAL) continue; - *str = i < 10 ? '0' + i : 'A' + i - 10; - str[1] = '\0'; - key = strdup(str); - if (!key) - return log_msg_ret("key", -ENOMEM); - label = strdup(dev_get_parent(bflow->dev)->name); - if (!label) { - free(key); - return log_msg_ret("nam", -ENOMEM); - } + ret = bootflow_menu_add(exp, bflow, i, &scn); + if (ret) + return log_msg_ret("bao", ret); - add_gap = last_bootdev != bflow->dev; - last_bootdev = bflow->dev; - - ret = expo_str(exp, "prompt", STR_POINTER, ">"); - ret |= scene_txt_str(scn, "label", ITEM_LABEL + i, - STR_LABEL + i, label, NULL); - ret |= scene_txt_str(scn, "desc", ITEM_DESC + i, STR_DESC + i, - bflow->os_name ? bflow->os_name : - bflow->name, NULL); - ret |= scene_txt_str(scn, "key", ITEM_KEY + i, STR_KEY + i, key, - NULL); - preview_id = 0; - if (bflow->logo) { - preview_id = ITEM_PREVIEW + i; - ret |= scene_img(scn, "preview", preview_id, - bflow->logo, NULL); - } - ret |= scene_menuitem(scn, OBJ_MENU, "item", ITEM + i, - ITEM_KEY + i, ITEM_LABEL + i, - ITEM_DESC + i, preview_id, - add_gap ? SCENEMIF_GAP_BEFORE : 0, - NULL); - - if (ret < 0) - return log_msg_ret("itm", -EINVAL); - priv->num_bootflows++; } ret = scene_arrange(scn); diff --git a/include/bootflow.h b/include/bootflow.h index 994b38394e8..615fb97f4a4 100644 --- a/include/bootflow.h +++ b/include/bootflow.h @@ -15,6 +15,7 @@ struct bootstd_priv; struct expo; +struct scene; enum { BOOTFLOW_MAX_USED_DEVS = 16, @@ -506,6 +507,21 @@ int bootflow_menu_new(struct expo **expp); */ int bootflow_menu_add_all(struct expo *exp); +/** + * bootflow_menu_add() - Add a bootflow to a menu + * + * Adds a new bootflow to the end of a menu. The caller must be careful to pass + * seq=0 for the first bootflow added, 1 for the second, etc. + * + * @exp: Menu to update + * @bflow: Bootflow to add + * @seq: Sequence number of this bootflow (0 = first) + * @scnp: Returns a pointer to the scene + * Return 0 on success, -ve on error + */ +int bootflow_menu_add(struct expo *exp, struct bootflow *bflow, int seq, + struct scene **scnp); + /** * bootflow_menu_apply_theme() - Apply a theme to a bootmenu * -- cgit v1.3.1 From 85a2954c29cf8631ccd0fb2c2c348711f8b5260e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:30 -0600 Subject: expo: Rename scene_dim to scene_obj_bbox At present we assume that each object is a simple box and that it fills the whole box. This is quite limiting for text objects, which we may want to centre within the box. We need a position within the box where drawing starts. Rename the scene_dim struct to indicate that it is a bounding box. Signed-off-by: Simon Glass --- boot/scene.c | 36 +++++++++++++------------- boot/scene_menu.c | 12 ++++----- boot/scene_textline.c | 22 ++++++++-------- include/expo.h | 8 +++--- test/boot/expo.c | 72 +++++++++++++++++++++++++-------------------------- 5 files changed, 75 insertions(+), 75 deletions(-) (limited to 'include') diff --git a/boot/scene.c b/boot/scene.c index 90b4ccf4766..a0060c6a97d 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -210,8 +210,8 @@ int scene_obj_set_pos(struct scene *scn, uint id, int x, int y) obj = scene_obj_find(scn, id, SCENEOBJT_NONE); if (!obj) return log_msg_ret("find", -ENOENT); - obj->dim.x = x; - obj->dim.y = y; + obj->bbox.x = x; + obj->bbox.y = y; return 0; } @@ -223,8 +223,8 @@ int scene_obj_set_size(struct scene *scn, uint id, int w, int h) obj = scene_obj_find(scn, id, SCENEOBJT_NONE); if (!obj) return log_msg_ret("find", -ENOENT); - obj->dim.w = w; - obj->dim.h = h; + obj->bbox.w = w; + obj->bbox.h = h; return 0; } @@ -368,8 +368,8 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) struct udevice *cons = text_mode ? NULL : exp->cons; int x, y, ret; - x = obj->dim.x; - y = obj->dim.y; + x = obj->bbox.x; + y = obj->bbox.y; switch (obj->type) { case SCENEOBJT_NONE: @@ -419,8 +419,8 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) if (obj->flags & SCENEOF_POINT) { vidconsole_push_colour(cons, fore, back, &old); video_fill_part(dev, x - theme->menu_inset, y, - x + obj->dim.w, - y + obj->dim.h, + x + obj->bbox.w, + y + obj->bbox.h, vid_priv->colour_bg); } vidconsole_set_cursor_pos(cons, x, y); @@ -765,8 +765,8 @@ int scene_calc_dims(struct scene *scn, bool do_menus) ret = scene_obj_get_hw(scn, obj->id, &width); if (ret < 0) return log_msg_ret("get", ret); - obj->dim.w = width; - obj->dim.h = ret; + obj->bbox.w = width; + obj->bbox.h = ret; } break; } @@ -915,15 +915,15 @@ int scene_bbox_union(struct scene *scn, uint id, int inset, if (!obj) return log_msg_ret("obj", -ENOENT); if (bbox->valid) { - bbox->x0 = min(bbox->x0, obj->dim.x - inset); - bbox->y0 = min(bbox->y0, obj->dim.y); - bbox->x1 = max(bbox->x1, obj->dim.x + obj->dim.w + inset); - bbox->y1 = max(bbox->y1, obj->dim.y + obj->dim.h); + bbox->x0 = min(bbox->x0, obj->bbox.x - inset); + bbox->y0 = min(bbox->y0, obj->bbox.y); + bbox->x1 = max(bbox->x1, obj->bbox.x + obj->bbox.w + inset); + bbox->y1 = max(bbox->y1, obj->bbox.y + obj->bbox.h); } else { - bbox->x0 = obj->dim.x - inset; - bbox->y0 = obj->dim.y; - bbox->x1 = obj->dim.x + obj->dim.w + inset; - bbox->y1 = obj->dim.y + obj->dim.h; + bbox->x0 = obj->bbox.x - inset; + bbox->y0 = obj->bbox.y; + bbox->x1 = obj->bbox.x + obj->bbox.w + inset; + bbox->y1 = obj->bbox.y + obj->bbox.h; bbox->valid = true; } diff --git a/boot/scene_menu.c b/boot/scene_menu.c index 6a2f5b6b93f..20a6a6b6a01 100644 --- a/boot/scene_menu.c +++ b/boot/scene_menu.c @@ -102,7 +102,7 @@ static int update_pointers(struct scene_obj_menu *menu, uint id, bool point) label = scene_obj_find(scn, item->label_id, SCENEOBJT_NONE); ret = scene_obj_set_pos(scn, menu->pointer_id, - menu->obj.dim.x + 200, label->dim.y); + menu->obj.bbox.x + 200, label->bbox.y); if (ret < 0) return log_msg_ret("ptr", ret); } @@ -186,8 +186,8 @@ int scene_menu_calc_dims(struct scene_obj_menu *menu) } if (bbox.valid) { - menu->obj.dim.w = bbox.x1 - bbox.x0; - menu->obj.dim.h = bbox.y1 - bbox.y0; + menu->obj.bbox.w = bbox.x1 - bbox.x0; + menu->obj.bbox.h = bbox.y1 - bbox.y0; } return 0; @@ -205,12 +205,12 @@ int scene_menu_arrange(struct scene *scn, struct expo_arrange_info *arr, int x, y; int ret; - x = menu->obj.dim.x; - y = menu->obj.dim.y; + x = menu->obj.bbox.x; + y = menu->obj.bbox.y; if (menu->title_id) { int width; - ret = scene_obj_set_pos(scn, menu->title_id, menu->obj.dim.x, y); + ret = scene_obj_set_pos(scn, menu->title_id, menu->obj.bbox.x, y); if (ret < 0) return log_msg_ret("tit", ret); diff --git a/boot/scene_textline.c b/boot/scene_textline.c index 90642a3f03d..5b4e21e6360 100644 --- a/boot/scene_textline.c +++ b/boot/scene_textline.c @@ -76,11 +76,11 @@ int scene_textline_calc_dims(struct scene_obj_textline *tline) return log_msg_ret("nom", ret); if (bbox.valid) { - tline->obj.dim.w = bbox.x1 - bbox.x0; - tline->obj.dim.h = bbox.y1 - bbox.y0; + tline->obj.bbox.w = bbox.x1 - bbox.x0; + tline->obj.bbox.h = bbox.y1 - bbox.y0; - scene_obj_set_size(scn, tline->edit_id, tline->obj.dim.w, - tline->obj.dim.h); + scene_obj_set_size(scn, tline->edit_id, tline->obj.bbox.w, + tline->obj.bbox.h); } return 0; @@ -94,16 +94,16 @@ int scene_textline_arrange(struct scene *scn, struct expo_arrange_info *arr, int x, y; int ret; - x = tline->obj.dim.x; - y = tline->obj.dim.y; + x = tline->obj.bbox.x; + y = tline->obj.bbox.y; if (tline->label_id) { - ret = scene_obj_set_pos(scn, tline->label_id, tline->obj.dim.x, + ret = scene_obj_set_pos(scn, tline->label_id, tline->obj.bbox.x, y); if (ret < 0) return log_msg_ret("tit", ret); ret = scene_obj_set_pos(scn, tline->edit_id, - tline->obj.dim.x + 200, y); + tline->obj.bbox.x + 200, y); if (ret < 0) return log_msg_ret("tit", ret); @@ -197,8 +197,8 @@ int scene_textline_render_deps(struct scene *scn, if (ret) return log_msg_ret("sav", ret); - vidconsole_set_cursor_visible(cons, true, txt->obj.dim.x, - txt->obj.dim.y, scn->cls.num); + vidconsole_set_cursor_visible(cons, true, txt->obj.bbox.x, + txt->obj.bbox.y, scn->cls.num); } return 0; @@ -219,7 +219,7 @@ int scene_textline_open(struct scene *scn, struct scene_obj_textline *tline) if (!txt) return log_msg_ret("cur", -ENOENT); - vidconsole_set_cursor_pos(cons, txt->obj.dim.x, txt->obj.dim.y); + vidconsole_set_cursor_pos(cons, txt->obj.bbox.x, txt->obj.bbox.y); vidconsole_entry_start(cons); cli_cread_init(&scn->cls, abuf_data(&tline->buf), tline->max_chars); scn->cls.insert = true; diff --git a/include/expo.h b/include/expo.h index a2b093c521d..42e934e3ff2 100644 --- a/include/expo.h +++ b/include/expo.h @@ -192,14 +192,14 @@ enum scene_obj_t { }; /** - * struct scene_dim - Dimensions of an object + * struct scene_obj_bbox - Dimensions of an object * * @x: x position, in pixels from left side * @y: y position, in pixels from top * @w: width, in pixels * @h: height, in pixels */ -struct scene_dim { +struct scene_obj_bbox { int x; int y; int w; @@ -232,7 +232,7 @@ enum { * @name: Name of the object (allocated) * @id: ID number of the object * @type: Type of this object - * @dim: Dimensions for this object + * @bbox: Dimensions for this object * @flags: Flags for this object * @bit_length: Number of bits used for this object in CMOS RAM * @start_bit: Start bit to use for this object in CMOS RAM @@ -243,7 +243,7 @@ struct scene_obj { char *name; uint id; enum scene_obj_t type; - struct scene_dim dim; + struct scene_obj_bbox bbox; u8 flags; u8 bit_length; u16 start_bit; diff --git a/test/boot/expo.c b/test/boot/expo.c index b32a4596e85..77b956bdf06 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -270,8 +270,8 @@ static int expo_object_attr(struct unit_test_state *uts) ut_assert(id > 0); ut_assertok(scene_obj_set_pos(scn, OBJ_LOGO, 123, 456)); - ut_asserteq(123, img->obj.dim.x); - ut_asserteq(456, img->obj.dim.y); + ut_asserteq(123, img->obj.bbox.x); + ut_asserteq(456, img->obj.bbox.y); ut_asserteq(-ENOENT, scene_obj_set_pos(scn, OBJ_TEXT2, 0, 0)); @@ -360,8 +360,8 @@ static int expo_object_menu(struct unit_test_state *uts) ut_asserteq(0, menu->pointer_id); ut_assertok(scene_obj_set_pos(scn, OBJ_MENU, 50, 400)); - ut_asserteq(50, menu->obj.dim.x); - ut_asserteq(400, menu->obj.dim.y); + ut_asserteq(50, menu->obj.bbox.x); + ut_asserteq(400, menu->obj.bbox.y); id = scene_txt_str(scn, "title", OBJ_MENU_TITLE, STR_MENU_TITLE, "Main Menu", &tit); @@ -407,24 +407,24 @@ static int expo_object_menu(struct unit_test_state *uts) ut_asserteq(id, menu->cur_item_id); /* the title should be at the top */ - ut_asserteq(menu->obj.dim.x, tit->obj.dim.x); - ut_asserteq(menu->obj.dim.y, tit->obj.dim.y); + ut_asserteq(menu->obj.bbox.x, tit->obj.bbox.x); + ut_asserteq(menu->obj.bbox.y, tit->obj.bbox.y); /* the first item should be next */ - ut_asserteq(menu->obj.dim.x, name1->obj.dim.x); - ut_asserteq(menu->obj.dim.y + 32, name1->obj.dim.y); + ut_asserteq(menu->obj.bbox.x, name1->obj.bbox.x); + ut_asserteq(menu->obj.bbox.y + 32, name1->obj.bbox.y); - ut_asserteq(menu->obj.dim.x + 230, key1->obj.dim.x); - ut_asserteq(menu->obj.dim.y + 32, key1->obj.dim.y); + ut_asserteq(menu->obj.bbox.x + 230, key1->obj.bbox.x); + ut_asserteq(menu->obj.bbox.y + 32, key1->obj.bbox.y); - ut_asserteq(menu->obj.dim.x + 200, ptr->obj.dim.x); - ut_asserteq(menu->obj.dim.y + 32, ptr->obj.dim.y); + ut_asserteq(menu->obj.bbox.x + 200, ptr->obj.bbox.x); + ut_asserteq(menu->obj.bbox.y + 32, ptr->obj.bbox.y); - ut_asserteq(menu->obj.dim.x + 280, desc1->obj.dim.x); - ut_asserteq(menu->obj.dim.y + 32, desc1->obj.dim.y); + ut_asserteq(menu->obj.bbox.x + 280, desc1->obj.bbox.x); + ut_asserteq(menu->obj.bbox.y + 32, desc1->obj.bbox.y); - ut_asserteq(-4, prev1->obj.dim.x); - ut_asserteq(menu->obj.dim.y + 32, prev1->obj.dim.y); + ut_asserteq(-4, prev1->obj.bbox.x); + ut_asserteq(menu->obj.bbox.y + 32, prev1->obj.bbox.y); ut_asserteq(true, prev1->obj.flags & SCENEOF_HIDE); /* check iterating through scene items */ @@ -548,41 +548,41 @@ static int expo_render_image(struct unit_test_state *uts) /* check dimensions of text */ obj = scene_obj_find(scn, OBJ_TEXT, SCENEOBJT_NONE); ut_assertnonnull(obj); - ut_asserteq(400, obj->dim.x); - ut_asserteq(100, obj->dim.y); - ut_asserteq(126, obj->dim.w); - ut_asserteq(40, obj->dim.h); + ut_asserteq(400, obj->bbox.x); + ut_asserteq(100, obj->bbox.y); + ut_asserteq(126, obj->bbox.w); + ut_asserteq(40, obj->bbox.h); /* check dimensions of image */ obj = scene_obj_find(scn, OBJ_LOGO, SCENEOBJT_NONE); ut_assertnonnull(obj); - ut_asserteq(50, obj->dim.x); - ut_asserteq(20, obj->dim.y); - ut_asserteq(160, obj->dim.w); - ut_asserteq(160, obj->dim.h); + ut_asserteq(50, obj->bbox.x); + ut_asserteq(20, obj->bbox.y); + ut_asserteq(160, obj->bbox.w); + ut_asserteq(160, obj->bbox.h); /* check dimensions of menu labels - both should be the same width */ obj = scene_obj_find(scn, ITEM1_LABEL, SCENEOBJT_NONE); ut_assertnonnull(obj); - ut_asserteq(50, obj->dim.x); - ut_asserteq(436, obj->dim.y); - ut_asserteq(29, obj->dim.w); - ut_asserteq(18, obj->dim.h); + ut_asserteq(50, obj->bbox.x); + ut_asserteq(436, obj->bbox.y); + ut_asserteq(29, obj->bbox.w); + ut_asserteq(18, obj->bbox.h); obj = scene_obj_find(scn, ITEM2_LABEL, SCENEOBJT_NONE); ut_assertnonnull(obj); - ut_asserteq(50, obj->dim.x); - ut_asserteq(454, obj->dim.y); - ut_asserteq(29, obj->dim.w); - ut_asserteq(18, obj->dim.h); + ut_asserteq(50, obj->bbox.x); + ut_asserteq(454, obj->bbox.y); + ut_asserteq(29, obj->bbox.w); + ut_asserteq(18, obj->bbox.h); /* check dimensions of menu */ obj = scene_obj_find(scn, OBJ_MENU, SCENEOBJT_NONE); ut_assertnonnull(obj); - ut_asserteq(50, obj->dim.x); - ut_asserteq(400, obj->dim.y); - ut_asserteq(160, obj->dim.w); - ut_asserteq(160, obj->dim.h); + ut_asserteq(50, obj->bbox.x); + ut_asserteq(400, obj->bbox.y); + ut_asserteq(160, obj->bbox.w); + ut_asserteq(160, obj->bbox.h); /* render it */ expo_set_scene_id(exp, SCENE1); -- cgit v1.3.1 From 8aa384d01a079ec2d816f7051a7208a337727338 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:31 -0600 Subject: expo: Rename x and y in struct scene_obj_bbox These coordinates are the top left values, so rename them to x0 and y0 in preparation for changing the width and height to x1 and y1 Signed-off-by: Simon Glass --- boot/scene.c | 24 ++++++++++++------------ boot/scene_menu.c | 8 ++++---- boot/scene_textline.c | 16 ++++++++-------- include/expo.h | 8 ++++---- test/boot/expo.c | 52 +++++++++++++++++++++++++-------------------------- 5 files changed, 54 insertions(+), 54 deletions(-) (limited to 'include') diff --git a/boot/scene.c b/boot/scene.c index a0060c6a97d..49dac90ceed 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -210,8 +210,8 @@ int scene_obj_set_pos(struct scene *scn, uint id, int x, int y) obj = scene_obj_find(scn, id, SCENEOBJT_NONE); if (!obj) return log_msg_ret("find", -ENOENT); - obj->bbox.x = x; - obj->bbox.y = y; + obj->bbox.x0 = x; + obj->bbox.y0 = y; return 0; } @@ -368,8 +368,8 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) struct udevice *cons = text_mode ? NULL : exp->cons; int x, y, ret; - x = obj->bbox.x; - y = obj->bbox.y; + x = obj->bbox.x0; + y = obj->bbox.y0; switch (obj->type) { case SCENEOBJT_NONE: @@ -915,15 +915,15 @@ int scene_bbox_union(struct scene *scn, uint id, int inset, if (!obj) return log_msg_ret("obj", -ENOENT); if (bbox->valid) { - bbox->x0 = min(bbox->x0, obj->bbox.x - inset); - bbox->y0 = min(bbox->y0, obj->bbox.y); - bbox->x1 = max(bbox->x1, obj->bbox.x + obj->bbox.w + inset); - bbox->y1 = max(bbox->y1, obj->bbox.y + obj->bbox.h); + bbox->x0 = min(bbox->x0, obj->bbox.x0 - inset); + bbox->y0 = min(bbox->y0, obj->bbox.y0); + bbox->x1 = max(bbox->x1, obj->bbox.x0 + obj->bbox.w + inset); + bbox->y1 = max(bbox->y1, obj->bbox.y0 + obj->bbox.h); } else { - bbox->x0 = obj->bbox.x - inset; - bbox->y0 = obj->bbox.y; - bbox->x1 = obj->bbox.x + obj->bbox.w + inset; - bbox->y1 = obj->bbox.y + obj->bbox.h; + bbox->x0 = obj->bbox.x0 - inset; + bbox->y0 = obj->bbox.y0; + bbox->x1 = obj->bbox.x0 + obj->bbox.w + inset; + bbox->y1 = obj->bbox.y0 + obj->bbox.h; bbox->valid = true; } diff --git a/boot/scene_menu.c b/boot/scene_menu.c index 20a6a6b6a01..c47c2030527 100644 --- a/boot/scene_menu.c +++ b/boot/scene_menu.c @@ -102,7 +102,7 @@ static int update_pointers(struct scene_obj_menu *menu, uint id, bool point) label = scene_obj_find(scn, item->label_id, SCENEOBJT_NONE); ret = scene_obj_set_pos(scn, menu->pointer_id, - menu->obj.bbox.x + 200, label->bbox.y); + menu->obj.bbox.x0 + 200, label->bbox.y0); if (ret < 0) return log_msg_ret("ptr", ret); } @@ -205,12 +205,12 @@ int scene_menu_arrange(struct scene *scn, struct expo_arrange_info *arr, int x, y; int ret; - x = menu->obj.bbox.x; - y = menu->obj.bbox.y; + x = menu->obj.bbox.x0; + y = menu->obj.bbox.y0; if (menu->title_id) { int width; - ret = scene_obj_set_pos(scn, menu->title_id, menu->obj.bbox.x, y); + ret = scene_obj_set_pos(scn, menu->title_id, menu->obj.bbox.x0, y); if (ret < 0) return log_msg_ret("tit", ret); diff --git a/boot/scene_textline.c b/boot/scene_textline.c index 5b4e21e6360..a513d555ded 100644 --- a/boot/scene_textline.c +++ b/boot/scene_textline.c @@ -94,16 +94,16 @@ int scene_textline_arrange(struct scene *scn, struct expo_arrange_info *arr, int x, y; int ret; - x = tline->obj.bbox.x; - y = tline->obj.bbox.y; + x = tline->obj.bbox.x0; + y = tline->obj.bbox.y0; if (tline->label_id) { - ret = scene_obj_set_pos(scn, tline->label_id, tline->obj.bbox.x, - y); + ret = scene_obj_set_pos(scn, tline->label_id, + tline->obj.bbox.x0, y); if (ret < 0) return log_msg_ret("tit", ret); ret = scene_obj_set_pos(scn, tline->edit_id, - tline->obj.bbox.x + 200, y); + tline->obj.bbox.x0 + 200, y); if (ret < 0) return log_msg_ret("tit", ret); @@ -197,8 +197,8 @@ int scene_textline_render_deps(struct scene *scn, if (ret) return log_msg_ret("sav", ret); - vidconsole_set_cursor_visible(cons, true, txt->obj.bbox.x, - txt->obj.bbox.y, scn->cls.num); + vidconsole_set_cursor_visible(cons, true, txt->obj.bbox.x0, + txt->obj.bbox.y0, scn->cls.num); } return 0; @@ -219,7 +219,7 @@ int scene_textline_open(struct scene *scn, struct scene_obj_textline *tline) if (!txt) return log_msg_ret("cur", -ENOENT); - vidconsole_set_cursor_pos(cons, txt->obj.bbox.x, txt->obj.bbox.y); + vidconsole_set_cursor_pos(cons, txt->obj.bbox.x0, txt->obj.bbox.y0); vidconsole_entry_start(cons); cli_cread_init(&scn->cls, abuf_data(&tline->buf), tline->max_chars); scn->cls.insert = true; diff --git a/include/expo.h b/include/expo.h index 42e934e3ff2..84dc77f771e 100644 --- a/include/expo.h +++ b/include/expo.h @@ -194,14 +194,14 @@ enum scene_obj_t { /** * struct scene_obj_bbox - Dimensions of an object * - * @x: x position, in pixels from left side - * @y: y position, in pixels from top + * @x0: x position, in pixels from left side + * @y0: y position, in pixels from top * @w: width, in pixels * @h: height, in pixels */ struct scene_obj_bbox { - int x; - int y; + int x0; + int y0; int w; int h; }; diff --git a/test/boot/expo.c b/test/boot/expo.c index 77b956bdf06..9c940825278 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -270,8 +270,8 @@ static int expo_object_attr(struct unit_test_state *uts) ut_assert(id > 0); ut_assertok(scene_obj_set_pos(scn, OBJ_LOGO, 123, 456)); - ut_asserteq(123, img->obj.bbox.x); - ut_asserteq(456, img->obj.bbox.y); + ut_asserteq(123, img->obj.bbox.x0); + ut_asserteq(456, img->obj.bbox.y0); ut_asserteq(-ENOENT, scene_obj_set_pos(scn, OBJ_TEXT2, 0, 0)); @@ -360,8 +360,8 @@ static int expo_object_menu(struct unit_test_state *uts) ut_asserteq(0, menu->pointer_id); ut_assertok(scene_obj_set_pos(scn, OBJ_MENU, 50, 400)); - ut_asserteq(50, menu->obj.bbox.x); - ut_asserteq(400, menu->obj.bbox.y); + ut_asserteq(50, menu->obj.bbox.x0); + ut_asserteq(400, menu->obj.bbox.y0); id = scene_txt_str(scn, "title", OBJ_MENU_TITLE, STR_MENU_TITLE, "Main Menu", &tit); @@ -407,24 +407,24 @@ static int expo_object_menu(struct unit_test_state *uts) ut_asserteq(id, menu->cur_item_id); /* the title should be at the top */ - ut_asserteq(menu->obj.bbox.x, tit->obj.bbox.x); - ut_asserteq(menu->obj.bbox.y, tit->obj.bbox.y); + ut_asserteq(menu->obj.bbox.x0, tit->obj.bbox.x0); + ut_asserteq(menu->obj.bbox.y0, tit->obj.bbox.y0); /* the first item should be next */ - ut_asserteq(menu->obj.bbox.x, name1->obj.bbox.x); - ut_asserteq(menu->obj.bbox.y + 32, name1->obj.bbox.y); + ut_asserteq(menu->obj.bbox.x0, name1->obj.bbox.x0); + ut_asserteq(menu->obj.bbox.y0 + 32, name1->obj.bbox.y0); - ut_asserteq(menu->obj.bbox.x + 230, key1->obj.bbox.x); - ut_asserteq(menu->obj.bbox.y + 32, key1->obj.bbox.y); + ut_asserteq(menu->obj.bbox.x0 + 230, key1->obj.bbox.x0); + ut_asserteq(menu->obj.bbox.y0 + 32, key1->obj.bbox.y0); - ut_asserteq(menu->obj.bbox.x + 200, ptr->obj.bbox.x); - ut_asserteq(menu->obj.bbox.y + 32, ptr->obj.bbox.y); + ut_asserteq(menu->obj.bbox.x0 + 200, ptr->obj.bbox.x0); + ut_asserteq(menu->obj.bbox.y0 + 32, ptr->obj.bbox.y0); - ut_asserteq(menu->obj.bbox.x + 280, desc1->obj.bbox.x); - ut_asserteq(menu->obj.bbox.y + 32, desc1->obj.bbox.y); + ut_asserteq(menu->obj.bbox.x0 + 280, desc1->obj.bbox.x0); + ut_asserteq(menu->obj.bbox.y0 + 32, desc1->obj.bbox.y0); - ut_asserteq(-4, prev1->obj.bbox.x); - ut_asserteq(menu->obj.bbox.y + 32, prev1->obj.bbox.y); + ut_asserteq(-4, prev1->obj.bbox.x0); + ut_asserteq(menu->obj.bbox.y0 + 32, prev1->obj.bbox.y0); ut_asserteq(true, prev1->obj.flags & SCENEOF_HIDE); /* check iterating through scene items */ @@ -548,39 +548,39 @@ static int expo_render_image(struct unit_test_state *uts) /* check dimensions of text */ obj = scene_obj_find(scn, OBJ_TEXT, SCENEOBJT_NONE); ut_assertnonnull(obj); - ut_asserteq(400, obj->bbox.x); - ut_asserteq(100, obj->bbox.y); + ut_asserteq(400, obj->bbox.x0); + ut_asserteq(100, obj->bbox.y0); ut_asserteq(126, obj->bbox.w); ut_asserteq(40, obj->bbox.h); /* check dimensions of image */ obj = scene_obj_find(scn, OBJ_LOGO, SCENEOBJT_NONE); ut_assertnonnull(obj); - ut_asserteq(50, obj->bbox.x); - ut_asserteq(20, obj->bbox.y); + ut_asserteq(50, obj->bbox.x0); + ut_asserteq(20, obj->bbox.y0); ut_asserteq(160, obj->bbox.w); ut_asserteq(160, obj->bbox.h); /* check dimensions of menu labels - both should be the same width */ obj = scene_obj_find(scn, ITEM1_LABEL, SCENEOBJT_NONE); ut_assertnonnull(obj); - ut_asserteq(50, obj->bbox.x); - ut_asserteq(436, obj->bbox.y); + ut_asserteq(50, obj->bbox.x0); + ut_asserteq(436, obj->bbox.y0); ut_asserteq(29, obj->bbox.w); ut_asserteq(18, obj->bbox.h); obj = scene_obj_find(scn, ITEM2_LABEL, SCENEOBJT_NONE); ut_assertnonnull(obj); - ut_asserteq(50, obj->bbox.x); - ut_asserteq(454, obj->bbox.y); + ut_asserteq(50, obj->bbox.x0); + ut_asserteq(454, obj->bbox.y0); ut_asserteq(29, obj->bbox.w); ut_asserteq(18, obj->bbox.h); /* check dimensions of menu */ obj = scene_obj_find(scn, OBJ_MENU, SCENEOBJT_NONE); ut_assertnonnull(obj); - ut_asserteq(50, obj->bbox.x); - ut_asserteq(400, obj->bbox.y); + ut_asserteq(50, obj->bbox.x0); + ut_asserteq(400, obj->bbox.y0); ut_asserteq(160, obj->bbox.w); ut_asserteq(160, obj->bbox.h); -- cgit v1.3.1 From 8636da86a2fb5f5f1a571f6cb3f12c0e8c207698 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:32 -0600 Subject: expo: Use an abuf to hold strings It is more convenient to put strings in an abuf so they can easily be resized. Adjust the struct accordingly. Signed-off-by: Simon Glass --- boot/expo.c | 4 ++-- include/expo.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/boot/expo.c b/boot/expo.c index 301bbfa5f9a..debdb60022b 100644 --- a/boot/expo.c +++ b/boot/expo.c @@ -86,7 +86,7 @@ int expo_str(struct expo *exp, const char *name, uint id, const char *str) return log_msg_ret("obj", -ENOMEM); estr->id = resolve_id(exp, id); - estr->str = str; + abuf_init_const(&estr->buf, str, strlen(str) + 1); list_add_tail(&estr->sibling, &exp->str_head); return estr->id; @@ -98,7 +98,7 @@ const char *expo_get_str(struct expo *exp, uint id) list_for_each_entry(estr, &exp->str_head, sibling) { if (estr->id == id) - return estr->str; + return estr->buf.data; } return NULL; diff --git a/include/expo.h b/include/expo.h index 84dc77f771e..b6de0310071 100644 --- a/include/expo.h +++ b/include/expo.h @@ -134,12 +134,12 @@ struct expo { * struct expo_string - a string that can be used in an expo * * @id: ID number of the string - * @str: String + * @buf: String (contains nul terminator) * @sibling: Node to link this object to its siblings */ struct expo_string { uint id; - const char *str; + struct abuf buf; struct list_head sibling; }; -- cgit v1.3.1 From f04026a59f5384f32a452889fc199c06eaf1553e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:33 -0600 Subject: expo: Separate dimensions from the bounding box At present each object has a width and height and the bounding box is implicit in that. This is not flexible enough to handle objects which are larger than their contents might need. For example, when centring a text object we might want to have it stretch across the whole width of the display even if the text itself does not need that much space. Create a new 'dimensions' field and convert the existing width/height into x1/y1 coordinates. Signed-off-by: Simon Glass --- boot/scene.c | 31 +++++++++++++++++++++---------- boot/scene_menu.c | 7 +++++-- boot/scene_textline.c | 18 ++++++++++++------ include/expo.h | 31 ++++++++++++++++++++++++++----- test/boot/expo.c | 20 ++++++++++---------- 5 files changed, 74 insertions(+), 33 deletions(-) (limited to 'include') diff --git a/boot/scene.c b/boot/scene.c index 49dac90ceed..325dd23641f 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -206,12 +206,17 @@ int scene_txt_set_font(struct scene *scn, uint id, const char *font_name, int scene_obj_set_pos(struct scene *scn, uint id, int x, int y) { struct scene_obj *obj; + int w, h; obj = scene_obj_find(scn, id, SCENEOBJT_NONE); if (!obj) return log_msg_ret("find", -ENOENT); + w = obj->bbox.x1 - obj->bbox.x0; + h = obj->bbox.y1 - obj->bbox.y0; obj->bbox.x0 = x; obj->bbox.y0 = y; + obj->bbox.x1 = obj->bbox.x0 + w; + obj->bbox.y1 = obj->bbox.y0 + h; return 0; } @@ -223,8 +228,9 @@ int scene_obj_set_size(struct scene *scn, uint id, int w, int h) obj = scene_obj_find(scn, id, SCENEOBJT_NONE); if (!obj) return log_msg_ret("find", -ENOENT); - obj->bbox.w = w; - obj->bbox.h = h; + obj->bbox.x1 = obj->bbox.x0 + w; + obj->bbox.y1 = obj->bbox.y0 + h; + obj->flags |= SCENEOF_SIZE_VALID; return 0; } @@ -419,8 +425,8 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) if (obj->flags & SCENEOF_POINT) { vidconsole_push_colour(cons, fore, back, &old); video_fill_part(dev, x - theme->menu_inset, y, - x + obj->bbox.w, - y + obj->bbox.h, + obj->bbox.x1, + obj->bbox.y1, vid_priv->colour_bg); } vidconsole_set_cursor_pos(cons, x, y); @@ -765,8 +771,13 @@ int scene_calc_dims(struct scene *scn, bool do_menus) ret = scene_obj_get_hw(scn, obj->id, &width); if (ret < 0) return log_msg_ret("get", ret); - obj->bbox.w = width; - obj->bbox.h = ret; + obj->dims.x = width; + obj->dims.y = ret; + if (!(obj->flags & SCENEOF_SIZE_VALID)) { + obj->bbox.x1 = obj->bbox.x0 + width; + obj->bbox.y1 = obj->bbox.y0 + ret; + obj->flags |= SCENEOF_SIZE_VALID; + } } break; } @@ -917,13 +928,13 @@ int scene_bbox_union(struct scene *scn, uint id, int inset, if (bbox->valid) { bbox->x0 = min(bbox->x0, obj->bbox.x0 - inset); bbox->y0 = min(bbox->y0, obj->bbox.y0); - bbox->x1 = max(bbox->x1, obj->bbox.x0 + obj->bbox.w + inset); - bbox->y1 = max(bbox->y1, obj->bbox.y0 + obj->bbox.h); + bbox->x1 = max(bbox->x1, obj->bbox.x1 + inset); + bbox->y1 = max(bbox->y1, obj->bbox.y1); } else { bbox->x0 = obj->bbox.x0 - inset; bbox->y0 = obj->bbox.y0; - bbox->x1 = obj->bbox.x0 + obj->bbox.w + inset; - bbox->y1 = obj->bbox.y0 + obj->bbox.h; + bbox->x1 = obj->bbox.x1 + inset; + bbox->y1 = obj->bbox.y1; bbox->valid = true; } diff --git a/boot/scene_menu.c b/boot/scene_menu.c index c47c2030527..dbc6793e302 100644 --- a/boot/scene_menu.c +++ b/boot/scene_menu.c @@ -186,8 +186,8 @@ int scene_menu_calc_dims(struct scene_obj_menu *menu) } if (bbox.valid) { - menu->obj.bbox.w = bbox.x1 - bbox.x0; - menu->obj.bbox.h = bbox.y1 - bbox.y0; + menu->obj.dims.x = bbox.x1 - bbox.x0; + menu->obj.dims.y = bbox.y1 - bbox.y0; } return 0; @@ -295,6 +295,9 @@ int scene_menu_arrange(struct scene *scn, struct expo_arrange_info *arr, if (sel_id) menu_point_to_item(menu, sel_id); + menu->obj.bbox.x1 = menu->obj.bbox.x0 + menu->obj.dims.x; + menu->obj.bbox.y1 = menu->obj.bbox.y0 + menu->obj.dims.y; + menu->obj.flags |= SCENEOF_SIZE_VALID; return 0; } diff --git a/boot/scene_textline.c b/boot/scene_textline.c index a513d555ded..f1d6ff7607c 100644 --- a/boot/scene_textline.c +++ b/boot/scene_textline.c @@ -61,7 +61,8 @@ void scene_textline_calc_bbox(struct scene_obj_textline *tline, int scene_textline_calc_dims(struct scene_obj_textline *tline) { - struct scene *scn = tline->obj.scene; + struct scene_obj *obj = &tline->obj; + struct scene *scn = obj->scene; struct vidconsole_bbox bbox; struct scene_obj_txt *txt; int ret; @@ -76,11 +77,16 @@ int scene_textline_calc_dims(struct scene_obj_textline *tline) return log_msg_ret("nom", ret); if (bbox.valid) { - tline->obj.bbox.w = bbox.x1 - bbox.x0; - tline->obj.bbox.h = bbox.y1 - bbox.y0; - - scene_obj_set_size(scn, tline->edit_id, tline->obj.bbox.w, - tline->obj.bbox.h); + obj->dims.x = bbox.x1 - bbox.x0; + obj->dims.y = bbox.y1 - bbox.y0; + if (!(obj->flags & SCENEOF_SIZE_VALID)) { + obj->bbox.x1 = obj->bbox.x0 + obj->dims.x; + obj->bbox.y1 = obj->bbox.y0 + obj->dims.y; + obj->flags |= SCENEOF_SIZE_VALID; + } + scene_obj_set_size(scn, tline->edit_id, + obj->bbox.x1 - obj->bbox.x0, + obj->bbox.y1 - obj->bbox.y0); } return 0; diff --git a/include/expo.h b/include/expo.h index b6de0310071..6f0547a4b38 100644 --- a/include/expo.h +++ b/include/expo.h @@ -9,6 +9,7 @@ #include #include +#include #include struct udevice; @@ -196,14 +197,29 @@ enum scene_obj_t { * * @x0: x position, in pixels from left side * @y0: y position, in pixels from top - * @w: width, in pixels - * @h: height, in pixels + * @x1: x position of right size + * @y1: y position of bottom */ struct scene_obj_bbox { int x0; int y0; - int w; - int h; + int x1; + int y1; +}; + +/** + * struct scene_obj_dims - Dimensions of the object being drawn + * + * Image and text objects have a dimension which can change depending on what + * they contain. For images this stores the size. For text it stores the size as + * rendered on the display + * + * @x: x dimension + * @y: y dimension + */ +struct scene_obj_dims { + int x; + int y; }; /** @@ -213,11 +229,14 @@ struct scene_obj_bbox { * @SCENEOF_POINT: object should be highlighted * @SCENEOF_OPEN: object should be opened (e.g. menu is opened so that an option * can be selected) + * @SCENEOF_SIZE_VALID: object's size (width/height) is valid, so any adjustment + * to x0/y0 should maintain the width/height of the object */ enum scene_obj_flags_t { SCENEOF_HIDE = 1 << 0, SCENEOF_POINT = 1 << 1, SCENEOF_OPEN = 1 << 2, + SCENEOF_SIZE_VALID = BIT(3), }; enum { @@ -232,7 +251,8 @@ enum { * @name: Name of the object (allocated) * @id: ID number of the object * @type: Type of this object - * @bbox: Dimensions for this object + * @bbox: Bounding box for this object + * @dims: Dimensions of the text/image (may be smaller than bbox) * @flags: Flags for this object * @bit_length: Number of bits used for this object in CMOS RAM * @start_bit: Start bit to use for this object in CMOS RAM @@ -244,6 +264,7 @@ struct scene_obj { uint id; enum scene_obj_t type; struct scene_obj_bbox bbox; + struct scene_obj_dims dims; u8 flags; u8 bit_length; u16 start_bit; diff --git a/test/boot/expo.c b/test/boot/expo.c index 9c940825278..94c13e9b71f 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -550,39 +550,39 @@ static int expo_render_image(struct unit_test_state *uts) ut_assertnonnull(obj); ut_asserteq(400, obj->bbox.x0); ut_asserteq(100, obj->bbox.y0); - ut_asserteq(126, obj->bbox.w); - ut_asserteq(40, obj->bbox.h); + ut_asserteq(400 + 126, obj->bbox.x1); + ut_asserteq(100 + 40, obj->bbox.y1); /* check dimensions of image */ obj = scene_obj_find(scn, OBJ_LOGO, SCENEOBJT_NONE); ut_assertnonnull(obj); ut_asserteq(50, obj->bbox.x0); ut_asserteq(20, obj->bbox.y0); - ut_asserteq(160, obj->bbox.w); - ut_asserteq(160, obj->bbox.h); + ut_asserteq(50 + 160, obj->bbox.x1); + ut_asserteq(20 + 160, obj->bbox.y1); /* check dimensions of menu labels - both should be the same width */ obj = scene_obj_find(scn, ITEM1_LABEL, SCENEOBJT_NONE); ut_assertnonnull(obj); ut_asserteq(50, obj->bbox.x0); ut_asserteq(436, obj->bbox.y0); - ut_asserteq(29, obj->bbox.w); - ut_asserteq(18, obj->bbox.h); + ut_asserteq(50 + 29, obj->bbox.x1); + ut_asserteq(436 + 18, obj->bbox.y1); obj = scene_obj_find(scn, ITEM2_LABEL, SCENEOBJT_NONE); ut_assertnonnull(obj); ut_asserteq(50, obj->bbox.x0); ut_asserteq(454, obj->bbox.y0); - ut_asserteq(29, obj->bbox.w); - ut_asserteq(18, obj->bbox.h); + ut_asserteq(50 + 29, obj->bbox.x1); + ut_asserteq(454 + 18, obj->bbox.y1); /* check dimensions of menu */ obj = scene_obj_find(scn, OBJ_MENU, SCENEOBJT_NONE); ut_assertnonnull(obj); ut_asserteq(50, obj->bbox.x0); ut_asserteq(400, obj->bbox.y0); - ut_asserteq(160, obj->bbox.w); - ut_asserteq(160, obj->bbox.h); + ut_asserteq(50 + 160, obj->bbox.x1); + ut_asserteq(400 + 160, obj->bbox.y1); /* render it */ expo_set_scene_id(exp, SCENE1); -- cgit v1.3.1 From e3c3f83cb6ce85ef541359fa46fd802e1b53494b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:35 -0600 Subject: expo: Support setting the size and bounds of an object Add a function to allow the size of an object to be set independently of its position. Also add a function to permit the object's bounding box to be set independently of its dimensions. Signed-off-by: Simon Glass --- boot/scene.c | 29 +++++++++++++++++++++++++++++ include/expo.h | 24 ++++++++++++++++++++++++ test/boot/expo.c | 11 +++++++++++ 3 files changed, 64 insertions(+) (limited to 'include') diff --git a/boot/scene.c b/boot/scene.c index f1dc2d81922..ea329252d28 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -235,6 +235,35 @@ int scene_obj_set_size(struct scene *scn, uint id, int w, int h) return 0; } +int scene_obj_set_width(struct scene *scn, uint id, int w) +{ + struct scene_obj *obj; + + obj = scene_obj_find(scn, id, SCENEOBJT_NONE); + if (!obj) + return log_msg_ret("find", -ENOENT); + obj->bbox.x1 = obj->bbox.x0 + w; + + return 0; +} + +int scene_obj_set_bbox(struct scene *scn, uint id, int x0, int y0, int x1, + int y1) +{ + struct scene_obj *obj; + + obj = scene_obj_find(scn, id, SCENEOBJT_NONE); + if (!obj) + return log_msg_ret("find", -ENOENT); + obj->bbox.x0 = x0; + obj->bbox.y0 = y0; + obj->bbox.x1 = x1; + obj->bbox.y1 = y1; + obj->flags |= SCENEOF_SIZE_VALID; + + return 0; +} + int scene_obj_set_hide(struct scene *scn, uint id, bool hide) { int ret; diff --git a/include/expo.h b/include/expo.h index 6f0547a4b38..990cb3094ee 100644 --- a/include/expo.h +++ b/include/expo.h @@ -673,6 +673,30 @@ int scene_obj_set_pos(struct scene *scn, uint id, int x, int y); */ int scene_obj_set_size(struct scene *scn, uint id, int w, int h); +/** + * scene_obj_set_width() - Set the width of an object + * + * @scn: Scene to update + * @id: ID of object to update + * @w: width in pixels + * Returns: 0 if OK, -ENOENT if @id is invalid + */ +int scene_obj_set_width(struct scene *scn, uint id, int w); + +/** + * scene_obj_set_bbox() - Set the bounding box of an object + * + * @scn: Scene to update + * @id: ID of object to update + * @x0: x position, in pixels from left side + * @y0: y position, in pixels from top + * @x1: ending x position (right side) + * @y1: ending y position (botton side) + * Returns: 0 if OK, -ENOENT if @id is invalid + */ +int scene_obj_set_bbox(struct scene *scn, uint id, int x0, int y0, int x1, + int y1); + /** * scene_obj_set_hide() - Set whether an object is hidden * diff --git a/test/boot/expo.c b/test/boot/expo.c index 94c13e9b71f..2a430d3d482 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -584,6 +584,17 @@ static int expo_render_image(struct unit_test_state *uts) ut_asserteq(50 + 160, obj->bbox.x1); ut_asserteq(400 + 160, obj->bbox.y1); + scene_obj_set_width(scn, OBJ_MENU, 170); + ut_asserteq(50 + 170, obj->bbox.x1); + scene_obj_set_bbox(scn, OBJ_MENU, 60, 410, 50 + 160, 400 + 160); + ut_asserteq(60, obj->bbox.x0); + ut_asserteq(410, obj->bbox.y0); + ut_asserteq(50 + 160, obj->bbox.x1); + ut_asserteq(400 + 160, obj->bbox.y1); + + /* reset back to normal */ + scene_obj_set_bbox(scn, OBJ_MENU, 50, 400, 50 + 160, 400 + 160); + /* render it */ expo_set_scene_id(exp, SCENE1); ut_assertok(expo_render(exp)); -- cgit v1.3.1 From 5a80996cb6a285d09c03d687dc9ad793f12e7bf1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:37 -0600 Subject: expo: Create a struct for generic text attributes In preparation for adding more text types, refactor the common fields into a new structure. This will allow common code to be used. Signed-off-by: Simon Glass --- boot/cedit.c | 2 +- boot/scene.c | 65 ++++++++++++++++++++++++++++++++++----------------- boot/scene_menu.c | 12 +++++----- boot/scene_textline.c | 10 ++++---- include/expo.h | 21 ++++++++++++----- test/boot/bootflow.c | 2 +- test/boot/cedit.c | 2 +- test/boot/expo.c | 15 ++++++------ 8 files changed, 80 insertions(+), 49 deletions(-) (limited to 'include') diff --git a/boot/cedit.c b/boot/cedit.c index 792ab6d65bd..0f7a8657c58 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -271,7 +271,7 @@ static int get_cur_menuitem_text(const struct scene_obj_menu *menu, if (!txt) return log_msg_ret("txt", -ENOENT); - str = expo_get_str(scn->expo, txt->str_id); + str = expo_get_str(scn->expo, txt->gen.str_id); if (!str) return log_msg_ret("str", -ENOENT); *strp = str; diff --git a/boot/scene.c b/boot/scene.c index ea329252d28..99623d2d3a8 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -142,6 +142,31 @@ int scene_img(struct scene *scn, const char *name, uint id, char *data, return img->obj.id; } +int scene_txt_generic_init(struct expo *exp, struct scene_txt_generic *gen, + const char *name, uint str_id, const char *str) +{ + int ret; + + if (str) { + ret = expo_str(exp, name, str_id, str); + if (ret < 0) + return log_msg_ret("str", ret); + if (str_id && ret != str_id) + return log_msg_ret("id", -EEXIST); + str_id = ret; + } else { + ret = resolve_id(exp, str_id); + if (ret < 0) + return log_msg_ret("nst", ret); + if (str_id && ret != str_id) + return log_msg_ret("nid", -EEXIST); + } + + gen->str_id = str_id; + + return 0; +} + int scene_txt(struct scene *scn, const char *name, uint id, uint str_id, struct scene_obj_txt **txtp) { @@ -154,8 +179,9 @@ int scene_txt(struct scene *scn, const char *name, uint id, uint str_id, if (ret < 0) return log_msg_ret("obj", ret); - txt->str_id = str_id; - + ret = scene_txt_generic_init(scn->expo, &txt->gen, name, str_id, NULL); + if (ret) + return log_msg_ret("stg", ret); if (txtp) *txtp = txt; @@ -168,21 +194,15 @@ int scene_txt_str(struct scene *scn, const char *name, uint id, uint str_id, struct scene_obj_txt *txt; int ret; - ret = expo_str(scn->expo, name, str_id, str); - if (ret < 0) - return log_msg_ret("str", ret); - if (str_id && ret != str_id) - return log_msg_ret("id", -EEXIST); - str_id = ret; - ret = scene_obj_add(scn, name, id, SCENEOBJT_TEXT, sizeof(struct scene_obj_txt), (struct scene_obj **)&txt); if (ret < 0) return log_msg_ret("obj", ret); - txt->str_id = str_id; - + ret = scene_txt_generic_init(scn->expo, &txt->gen, name, str_id, str); + if (ret) + return log_msg_ret("tsg", ret); if (txtp) *txtp = txt; @@ -197,8 +217,8 @@ int scene_txt_set_font(struct scene *scn, uint id, const char *font_name, txt = scene_obj_find(scn, id, SCENEOBJT_TEXT); if (!txt) return log_msg_ret("find", -ENOENT); - txt->font_name = font_name; - txt->font_size = font_size; + txt->gen.font_name = font_name; + txt->gen.font_size = font_size; return 0; } @@ -313,13 +333,13 @@ int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) return height; } case SCENEOBJT_TEXT: { - struct scene_obj_txt *txt = (struct scene_obj_txt *)obj; + struct scene_txt_generic *gen = &((struct scene_obj_txt *)obj)->gen; struct expo *exp = scn->expo; struct vidconsole_bbox bbox; const char *str; int len, ret; - str = expo_get_str(exp, txt->str_id); + str = expo_get_str(exp, gen->str_id); if (!str) return log_msg_ret("str", -ENOENT); len = strlen(str); @@ -331,8 +351,8 @@ int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) return 16; } - ret = vidconsole_measure(scn->expo->cons, txt->font_name, - txt->font_size, str, -1, &bbox, NULL); + ret = vidconsole_measure(scn->expo->cons, gen->font_name, + gen->font_size, str, -1, &bbox, NULL); if (ret) return log_msg_ret("mea", ret); if (widthp) @@ -424,22 +444,23 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) break; } case SCENEOBJT_TEXT: { - struct scene_obj_txt *txt = (struct scene_obj_txt *)obj; + struct scene_txt_generic *gen = + &((struct scene_obj_txt *)obj)->gen; const char *str; if (!cons) return -ENOTSUPP; - if (txt->font_name || txt->font_size) { + if (gen->font_name || gen->font_size) { ret = vidconsole_select_font(cons, - txt->font_name, - txt->font_size); + gen->font_name, + gen->font_size); } else { ret = vidconsole_select_font(cons, NULL, 0); } if (ret && ret != -ENOSYS) return log_msg_ret("font", ret); - str = expo_get_str(exp, txt->str_id); + str = expo_get_str(exp, gen->str_id); if (str) { struct video_priv *vid_priv; struct vidconsole_colour old; diff --git a/boot/scene_menu.c b/boot/scene_menu.c index 96ac726ebcd..de433ece6ee 100644 --- a/boot/scene_menu.c +++ b/boot/scene_menu.c @@ -359,7 +359,7 @@ static struct scene_menitem *scene_menu_find_key(struct scene *scn, txt = scene_obj_find(scn, item->key_id, SCENEOBJT_TEXT); if (txt) { - str = expo_get_str(scn->expo, txt->str_id); + str = expo_get_str(scn->expo, txt->gen.str_id); if (str && *str == key) return item; } @@ -562,7 +562,7 @@ int scene_menu_display(struct scene_obj_menu *menu) if (!txt) return log_msg_ret("txt", -EINVAL); - str = expo_get_str(exp, txt->str_id); + str = expo_get_str(exp, txt->gen.str_id); printf("%s\n\n", str); } @@ -570,7 +570,7 @@ int scene_menu_display(struct scene_obj_menu *menu) return 0; pointer = scene_obj_find(scn, menu->pointer_id, SCENEOBJT_TEXT); - pstr = expo_get_str(scn->expo, pointer->str_id); + pstr = expo_get_str(scn->expo, pointer->gen.str_id); list_for_each_entry(item, &menu->item_head, sibling) { struct scene_obj_txt *key = NULL, *label = NULL; @@ -579,15 +579,15 @@ int scene_menu_display(struct scene_obj_menu *menu) key = scene_obj_find(scn, item->key_id, SCENEOBJT_TEXT); if (key) - kstr = expo_get_str(exp, key->str_id); + kstr = expo_get_str(exp, key->gen.str_id); label = scene_obj_find(scn, item->label_id, SCENEOBJT_TEXT); if (label) - lstr = expo_get_str(exp, label->str_id); + lstr = expo_get_str(exp, label->gen.str_id); desc = scene_obj_find(scn, item->desc_id, SCENEOBJT_TEXT); if (desc) - dstr = expo_get_str(exp, desc->str_id); + dstr = expo_get_str(exp, desc->gen.str_id); printf("%3s %3s %-10s %s\n", pointer && menu->cur_item_id == item->id ? pstr : "", diff --git a/boot/scene_textline.c b/boot/scene_textline.c index f1d6ff7607c..7bc35a997dc 100644 --- a/boot/scene_textline.c +++ b/boot/scene_textline.c @@ -71,8 +71,8 @@ int scene_textline_calc_dims(struct scene_obj_textline *tline) if (!txt) return log_msg_ret("dim", -ENOENT); - ret = vidconsole_nominal(scn->expo->cons, txt->font_name, - txt->font_size, tline->max_chars, &bbox); + ret = vidconsole_nominal(scn->expo->cons, txt->gen.font_name, + txt->gen.font_size, tline->max_chars, &bbox); if (ret) return log_msg_ret("nom", ret); @@ -191,10 +191,10 @@ int scene_textline_render_deps(struct scene *scn, if (!txt) return log_msg_ret("cur", -ENOENT); - if (txt->font_name || txt->font_size) { + if (txt->gen.font_name || txt->gen.font_size) { ret = vidconsole_select_font(cons, - txt->font_name, - txt->font_size); + txt->gen.font_name, + txt->gen.font_size); } else { ret = vidconsole_select_font(cons, NULL, 0); } diff --git a/include/expo.h b/include/expo.h index 990cb3094ee..32d69f269a7 100644 --- a/include/expo.h +++ b/include/expo.h @@ -291,22 +291,31 @@ struct scene_obj_img { }; /** - * struct scene_obj_txt - information about a text object in a scene - * - * This is a single-line text object + * struct scene_txt_generic - Generic information common to text objects * - * @obj: Basic object information * @str_id: ID of the text string to display * @font_name: Name of font (allocated by caller) * @font_size: Nominal size of font in pixels */ -struct scene_obj_txt { - struct scene_obj obj; +struct scene_txt_generic { uint str_id; const char *font_name; uint font_size; }; +/** + * struct scene_obj_txt - information about a text object in a scene + * + * This is a single-line text object + * + * @obj: Basic object information + * @gen: Generic information common to all objects which show text + */ +struct scene_obj_txt { + struct scene_obj obj; + struct scene_txt_generic gen; +}; + /** * struct scene_obj_menu - information about a menu object in a scene * diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index 58885b5d8bf..ea1a994fd3d 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -858,7 +858,7 @@ static int check_font(struct unit_test_state *uts, struct scene *scn, uint id, txt = scene_obj_find(scn, id, SCENEOBJT_TEXT); ut_assertnonnull(txt); - ut_asserteq(font_size, txt->font_size); + ut_asserteq(font_size, txt->gen.font_size); return 0; } diff --git a/test/boot/cedit.c b/test/boot/cedit.c index 0c34d4b3df0..dbf781902fb 100644 --- a/test/boot/cedit.c +++ b/test/boot/cedit.c @@ -48,7 +48,7 @@ static int cedit_base(struct unit_test_state *uts) txt = scene_obj_find(scn, menu->title_id, SCENEOBJT_NONE); ut_assertnonnull(txt); - ut_asserteq_str("AC Power", expo_get_str(exp, txt->str_id)); + ut_asserteq_str("AC Power", expo_get_str(exp, txt->gen.str_id)); ut_asserteq(ID_AC_ON, menu->cur_item_id); diff --git a/test/boot/expo.c b/test/boot/expo.c index 70db33d48b1..96c5943f394 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -280,8 +280,8 @@ static int expo_object_attr(struct unit_test_state *uts) strcpy(name, "font2"); ut_assertok(scene_txt_set_font(scn, OBJ_TEXT, name, 42)); - ut_asserteq_ptr(name, txt->font_name); - ut_asserteq(42, txt->font_size); + ut_asserteq_ptr(name, txt->gen.font_name); + ut_asserteq(42, txt->gen.font_size); ut_asserteq(-ENOENT, scene_txt_set_font(scn, OBJ_TEXT2, name, 42)); @@ -296,7 +296,7 @@ static int expo_object_attr(struct unit_test_state *uts) node = ofnode_path("/bootstd/theme"); ut_assert(ofnode_valid(node)); ut_assertok(expo_apply_theme(exp, node)); - ut_asserteq(30, txt->font_size); + ut_asserteq(30, txt->gen.font_size); expo_destroy(exp); @@ -727,7 +727,7 @@ static int expo_test_build(struct unit_test_state *uts) ut_assertnonnull(scn); ut_asserteq_str("main", scn->name); ut_asserteq(ID_SCENE1, scn->id); - ut_asserteq(ID_DYNAMIC_START + 1, scn->title_id); + ut_asserteq(ID_DYNAMIC_START, scn->title_id); ut_asserteq(0, scn->highlight_id); /* check the title */ @@ -739,7 +739,8 @@ static int expo_test_build(struct unit_test_state *uts) ut_asserteq(scn->title_id, obj->id); ut_asserteq(SCENEOBJT_TEXT, obj->type); ut_asserteq(0, obj->flags); - ut_asserteq_str("Test Configuration", expo_get_str(exp, txt->str_id)); + ut_asserteq_str("Test Configuration", + expo_get_str(exp, txt->gen.str_id)); /* check the menu */ menu = scene_obj_find(scn, ID_CPU_SPEED, SCENEOBJT_NONE); @@ -751,7 +752,7 @@ static int expo_test_build(struct unit_test_state *uts) ut_asserteq(0, obj->flags); txt = scene_obj_find(scn, menu->title_id, SCENEOBJT_NONE); - ut_asserteq_str("CPU speed", expo_get_str(exp, txt->str_id)); + ut_asserteq_str("CPU speed", expo_get_str(exp, txt->gen.str_id)); ut_asserteq(0, menu->cur_item_id); ut_asserteq(0, menu->pointer_id); @@ -768,7 +769,7 @@ static int expo_test_build(struct unit_test_state *uts) ut_asserteq(0, item->value); txt = scene_obj_find(scn, item->label_id, SCENEOBJT_NONE); - ut_asserteq_str("2 GHz", expo_get_str(exp, txt->str_id)); + ut_asserteq_str("2 GHz", expo_get_str(exp, txt->gen.str_id)); count = list_count_nodes(&menu->item_head); ut_asserteq(3, count); -- cgit v1.3.1 From 87750b027691cd67a20ae6c5b95df65c33e8294e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:40 -0600 Subject: expo: Allow strings to be editable In some cases dynamic text is needed, e.g. for a menu countdown. Add a function which handles this, allowing the caller to take control of the text that is shown on each render. Signed-off-by: Simon Glass --- boot/expo.c | 21 +++++++++++++++++++++ include/expo.h | 17 +++++++++++++++++ test/boot/expo.c | 11 +++++++++++ 3 files changed, 49 insertions(+) (limited to 'include') diff --git a/boot/expo.c b/boot/expo.c index debdb60022b..4404fcb67e9 100644 --- a/boot/expo.c +++ b/boot/expo.c @@ -104,6 +104,27 @@ const char *expo_get_str(struct expo *exp, uint id) return NULL; } +int expo_edit_str(struct expo *exp, uint id, struct abuf *orig, + struct abuf **copyp) +{ + struct expo_string *estr; + struct abuf old; + + list_for_each_entry(estr, &exp->str_head, sibling) { + if (estr->id == id) { + old = estr->buf; + if (!abuf_copy(&old, &estr->buf)) + return -ENOMEM; + *copyp = &estr->buf; + if (orig) + *orig = old; + return 0; + } + } + + return -ENOENT; +} + int expo_set_display(struct expo *exp, struct udevice *dev) { struct udevice *cons; diff --git a/include/expo.h b/include/expo.h index 32d69f269a7..7c6ab4bf630 100644 --- a/include/expo.h +++ b/include/expo.h @@ -469,6 +469,23 @@ int expo_str(struct expo *exp, const char *name, uint id, const char *str); */ const char *expo_get_str(struct expo *exp, uint id); +/** + * expo_edit_str() - Make a string writeable + * + * This allows a string to be updated under the control of the caller. The + * buffer must remain valid while the expo is active. + * + * @exp: Expo to use + * @id: String ID to look up + * @orig: If non-NULL, returns the original buffer, which can be used by the + * caller. It is no-longer used by expo so must be uninited by the caller. + * It contains a snapshot of the string contents + * @copyp: Returns a pointer to the new, writeable buffer + * Return: 0 if OK, -ENOENT if the id was not found, -ENOMEM if out of memory + */ +int expo_edit_str(struct expo *exp, uint id, struct abuf *orig, + struct abuf **copyp); + /** * expo_set_display() - set the display to use for a expo * diff --git a/test/boot/expo.c b/test/boot/expo.c index 96c5943f394..a50e9f721de 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -707,6 +707,7 @@ static int expo_test_build(struct unit_test_state *uts) struct scene_obj_menu *menu; struct scene_menitem *item; struct scene_obj_txt *txt; + struct abuf orig, *copy; struct scene_obj *obj; struct scene *scn; struct expo *exp; @@ -774,6 +775,16 @@ static int expo_test_build(struct unit_test_state *uts) count = list_count_nodes(&menu->item_head); ut_asserteq(3, count); + /* try editing some text */ + ut_assertok(expo_edit_str(exp, txt->gen.str_id, &orig, ©)); + ut_asserteq_str("2 GHz", orig.data); + ut_asserteq_str("2 GHz", copy->data); + + /* change it and check that things look right */ + abuf_printf(copy, "atlantic %d", 123); + ut_asserteq_str("2 GHz", orig.data); + ut_asserteq_str("atlantic 123", copy->data); + expo_destroy(exp); return 0; -- cgit v1.3.1 From 03f9ce815cbba660bb4c8e7cd28cfc19219631c8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:42 -0600 Subject: expo: Support rendering multiple lines of text Use the measurement info to write each line of text separately, thus respecting word-wrapping and newlines. Fix up the comment for scene_obj_render() while we are here. Since a lineedit does not support alignment, add a special case to just display the text if there is no measurement. This happens assuming the lineedit is initially empty. Signed-off-by: Simon Glass --- boot/bootflow_menu.c | 4 ++++ boot/scene.c | 26 ++++++++++++++++++++++---- include/expo.h | 4 ++++ test/boot/expo.c | 12 +++++++++++- 4 files changed, 41 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/boot/bootflow_menu.c b/boot/bootflow_menu.c index 6a37fa8fa68..ab21ed84ffd 100644 --- a/boot/bootflow_menu.c +++ b/boot/bootflow_menu.c @@ -241,6 +241,10 @@ int bootflow_menu_start(struct bootstd_priv *std, bool text_mode, if (text_mode) expo_set_text_mode(exp, text_mode); + ret = expo_calc_dims(exp); + if (ret) + return log_msg_ret("bmd", ret); + *expp = exp; return 0; diff --git a/boot/scene.c b/boot/scene.c index aacdccdce17..72a8e27a93d 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -8,6 +8,7 @@ #define LOG_CATEGORY LOGC_EXPO +#include #include #include #include @@ -163,6 +164,7 @@ int scene_txt_generic_init(struct expo *exp, struct scene_txt_generic *gen, } gen->str_id = str_id; + alist_init_struct(&gen->lines, struct vidconsole_mline); return 0; } @@ -336,8 +338,8 @@ int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) struct scene_txt_generic *gen = &((struct scene_obj_txt *)obj)->gen; struct expo *exp = scn->expo; struct vidconsole_bbox bbox; + int len, ret, limit; const char *str; - int len, ret; str = expo_get_str(exp, gen->str_id); if (!str) @@ -351,8 +353,12 @@ int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) return 16; } + limit = obj->flags & SCENEOF_SIZE_VALID ? + obj->bbox.x1 - obj->bbox.x0 : -1; + ret = vidconsole_measure(scn->expo->cons, gen->font_name, - gen->font_size, str, -1, &bbox, NULL); + gen->font_size, str, limit, &bbox, + &gen->lines); if (ret) return log_msg_ret("mea", ret); if (widthp) @@ -418,6 +424,7 @@ static int scene_txt_render(struct expo *exp, struct udevice *dev, struct scene_txt_generic *gen, int x, int y, int menu_inset) { + const struct vidconsole_mline *mline; struct video_priv *vid_priv; struct vidconsole_colour old; enum colour_idx fore, back; @@ -453,8 +460,16 @@ static int scene_txt_render(struct expo *exp, struct udevice *dev, video_fill_part(dev, x - menu_inset, y, obj->bbox.x1, obj->bbox.y1, vid_priv->colour_bg); } - vidconsole_set_cursor_pos(cons, x, y); - vidconsole_put_string(cons, str); + + if (!gen->lines.count) { + vidconsole_set_cursor_pos(cons, x, y); + vidconsole_put_string(cons, str); + } + alist_for_each(mline, &gen->lines) { + vidconsole_set_cursor_pos(cons, x + mline->bbox.x0, + y + mline->bbox.y0); + vidconsole_put_stringn(cons, str + mline->start, mline->len); + } if (obj->flags & SCENEOF_POINT) vidconsole_pop_colour(cons, &old); @@ -464,6 +479,9 @@ static int scene_txt_render(struct expo *exp, struct udevice *dev, /** * scene_obj_render() - Render an object * + * @obj: Object to render + * @text_mode: true to use text mode + * Return: 0 if OK, -ve on error */ static int scene_obj_render(struct scene_obj *obj, bool text_mode) { diff --git a/include/expo.h b/include/expo.h index 7c6ab4bf630..a79aa1da74f 100644 --- a/include/expo.h +++ b/include/expo.h @@ -8,6 +8,7 @@ #define __EXPO_H #include +#include #include #include #include @@ -296,11 +297,14 @@ struct scene_obj_img { * @str_id: ID of the text string to display * @font_name: Name of font (allocated by caller) * @font_size: Nominal size of font in pixels + * @lines: alist of struct vidconsole_mline with a separate record for each + * line of text */ struct scene_txt_generic { uint str_id; const char *font_name; uint font_size; + struct alist lines; }; /** diff --git a/test/boot/expo.c b/test/boot/expo.c index 6fb9f810885..c9ff5b8dd24 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -25,6 +25,7 @@ enum { OBJ_LOGO, OBJ_TEXT, OBJ_TEXT2, + OBJ_TEXT3, OBJ_MENU, OBJ_MENU_TITLE, @@ -33,6 +34,7 @@ enum { STR_TEXT, STR_TEXT2, + STR_TEXT3, STR_MENU_TITLE, STR_POINTER_TEXT, @@ -488,6 +490,14 @@ static int expo_render_image(struct unit_test_state *uts) 60)); ut_assertok(scene_obj_set_pos(scn, OBJ_TEXT2, 200, 600)); + id = scene_txt_str(scn, "text", OBJ_TEXT3, STR_TEXT3, + "this is yet\nanother string, with word-wrap", + NULL); + ut_assert(id > 0); + ut_assertok(scene_txt_set_font(scn, OBJ_TEXT3, "nimbus_sans_l_regular", + 60)); + ut_assertok(scene_obj_set_bbox(scn, OBJ_TEXT3, 500, 200, 1000, 700)); + id = scene_menu(scn, "main", OBJ_MENU, &menu); ut_assert(id > 0); @@ -646,7 +656,7 @@ static int expo_render_image(struct unit_test_state *uts) ut_assertok(scene_arrange(scn)); ut_assertok(expo_render(exp)); - ut_asserteq(10314, video_compress_fb(uts, dev, false)); + ut_asserteq(14848, video_compress_fb(uts, dev, false)); ut_assertok(video_check_copy_fb(uts, dev)); /* make sure only the preview for the second item is shown */ -- cgit v1.3.1 From 0635004e2228dea0aab023d7c56b0b74633e8a3c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:44 -0600 Subject: expo: Implement a box It is useful to be able to draw a box around elements in the menu. Add support for an unfilled box with a selectable thickness. Note that there is no support for selecting the colour for any expo objects yet. Signed-off-by: Simon Glass --- boot/cedit.c | 5 +++++ boot/scene.c | 40 +++++++++++++++++++++++++++++++++++++++- doc/develop/expo.rst | 2 ++ include/expo.h | 28 ++++++++++++++++++++++++++++ test/boot/expo.c | 13 +++++++++++-- 5 files changed, 85 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/boot/cedit.c b/boot/cedit.c index 0f7a8657c58..9153fe769c6 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -81,6 +81,7 @@ int cedit_arange(struct expo *exp, struct video_priv *vpriv, uint scene_id) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: break; case SCENEOBJT_MENU: scene_obj_set_pos(scn, obj->id, 50, y); @@ -381,6 +382,7 @@ static int h_write_settings(struct scene_obj *obj, void *vpriv) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: break; case SCENEOBJT_TEXTLINE: { const struct scene_obj_textline *tline; @@ -480,6 +482,7 @@ static int h_read_settings(struct scene_obj *obj, void *vpriv) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: break; case SCENEOBJT_TEXTLINE: { const struct scene_obj_textline *tline; @@ -551,6 +554,7 @@ static int h_write_settings_env(struct scene_obj *obj, void *vpriv) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: break; case SCENEOBJT_MENU: menu = (struct scene_obj_menu *)obj; @@ -634,6 +638,7 @@ static int h_read_settings_env(struct scene_obj *obj, void *vpriv) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: break; case SCENEOBJT_MENU: menu = (struct scene_obj_menu *)obj; diff --git a/boot/scene.c b/boot/scene.c index 72a8e27a93d..f971db9aab4 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -211,6 +211,26 @@ int scene_txt_str(struct scene *scn, const char *name, uint id, uint str_id, return txt->obj.id; } +int scene_box(struct scene *scn, const char *name, uint id, uint width, + struct scene_obj_box **boxp) +{ + struct scene_obj_box *box; + int ret; + + ret = scene_obj_add(scn, name, id, SCENEOBJT_BOX, + sizeof(struct scene_obj_box), + (struct scene_obj **)&box); + if (ret < 0) + return log_msg_ret("obj", ret); + + box->width = width; + + if (boxp) + *boxp = box; + + return box->obj.id; +} + int scene_txt_set_font(struct scene *scn, uint id, const char *font_name, uint font_size) { @@ -323,6 +343,7 @@ int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) case SCENEOBJT_NONE: case SCENEOBJT_MENU: case SCENEOBJT_TEXTLINE: + case SCENEOBJT_BOX: break; case SCENEOBJT_IMAGE: { struct scene_obj_img *img = (struct scene_obj_img *)obj; @@ -490,10 +511,12 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) const struct expo_theme *theme = &exp->theme; struct udevice *dev = exp->display; struct udevice *cons = text_mode ? NULL : exp->cons; + struct video_priv *vid_priv; int x, y, ret; - x = obj->bbox.x0; y = obj->bbox.y0; + x = obj->bbox.x0; + vid_priv = dev_get_uclass_priv(dev); switch (obj->type) { case SCENEOBJT_NONE: @@ -544,6 +567,13 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) if (obj->flags & SCENEOF_OPEN) scene_render_background(obj, true); break; + case SCENEOBJT_BOX: { + struct scene_obj_box *box = (struct scene_obj_box *)obj; + + video_draw_box(dev, obj->bbox.x0, obj->bbox.y0, obj->bbox.x1, + obj->bbox.y1, box->width, vid_priv->colour_fg); + break; + } } return 0; @@ -562,6 +592,7 @@ int scene_calc_arrange(struct scene *scn, struct expo_arrange_info *arr) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: break; case SCENEOBJT_MENU: { struct scene_obj_menu *menu; @@ -607,6 +638,7 @@ int scene_arrange(struct scene *scn) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: break; case SCENEOBJT_MENU: { struct scene_obj_menu *menu; @@ -652,6 +684,7 @@ int scene_render_deps(struct scene *scn, uint id) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: break; case SCENEOBJT_MENU: scene_menu_render_deps(scn, @@ -771,6 +804,7 @@ int scene_send_key(struct scene *scn, int key, struct expo_action *event) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: break; case SCENEOBJT_MENU: { struct scene_obj_menu *menu; @@ -815,6 +849,7 @@ int scene_obj_calc_bbox(struct scene_obj *obj, struct vidconsole_bbox bbox[]) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: return -ENOSYS; case SCENEOBJT_MENU: { struct scene_obj_menu *menu = (struct scene_obj_menu *)obj; @@ -844,6 +879,7 @@ int scene_calc_dims(struct scene *scn, bool do_menus) switch (obj->type) { case SCENEOBJT_NONE: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: case SCENEOBJT_IMAGE: { int width; @@ -902,6 +938,7 @@ int scene_apply_theme(struct scene *scn, struct expo_theme *theme) case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: case SCENEOBJT_MENU: + case SCENEOBJT_BOX: case SCENEOBJT_TEXTLINE: break; case SCENEOBJT_TEXT: @@ -944,6 +981,7 @@ static int scene_obj_open(struct scene *scn, struct scene_obj *obj) case SCENEOBJT_IMAGE: case SCENEOBJT_MENU: case SCENEOBJT_TEXT: + case SCENEOBJT_BOX: break; case SCENEOBJT_TEXTLINE: ret = scene_textline_open(scn, diff --git a/doc/develop/expo.rst b/doc/develop/expo.rst index cc7c36173db..8f63ccbe3ef 100644 --- a/doc/develop/expo.rst +++ b/doc/develop/expo.rst @@ -65,6 +65,8 @@ item is highlighted. A `textline object` contains a label and an editable string. +A `box object` is a rectangle with a given line width. It is not filled. + All components have a name. This is mostly for debugging, so it is easy to see what object is referred to, although the name is also used for saving values. Of course the ID numbers can help as well, but they are less easy to diff --git a/include/expo.h b/include/expo.h index a79aa1da74f..8833dcceb7e 100644 --- a/include/expo.h +++ b/include/expo.h @@ -179,6 +179,7 @@ struct scene { * * @SCENEOBJT_NONE: Used to indicate that the type does not matter * @SCENEOBJT_IMAGE: Image data to render + * @SCENEOBJT_BOX: Rectangular box * @SCENEOBJT_TEXT: Text line to render * @SCENEOBJT_MENU: Menu containing items the user can select * @SCENEOBJT_TEXTLINE: Line of text the user can edit @@ -187,6 +188,7 @@ enum scene_obj_t { SCENEOBJT_NONE = 0, SCENEOBJT_IMAGE, SCENEOBJT_TEXT, + SCENEOBJT_BOX, /* types from here on can be highlighted */ SCENEOBJT_MENU, @@ -406,6 +408,19 @@ struct scene_obj_textline { uint pos; }; +/** + * struct scene_obj_box - information about a box in a scene + * + * A box surrounds a part of the screen with a border + * + * @obj: Basic object information + * @width: Line-width in pixels + */ +struct scene_obj_box { + struct scene_obj obj; + uint width; +}; + /** * struct expo_arrange_info - Information used when arranging a scene * @@ -670,6 +685,19 @@ int scene_menu(struct scene *scn, const char *name, uint id, int scene_textline(struct scene *scn, const char *name, uint id, uint max_chars, struct scene_obj_textline **tlinep); +/** + * scene_box() - create a box + * + * @scn: Scene to update + * @name: Name to use (this is allocated by this call) + * @id: ID to use for the new object (0 to allocate one) + * @width: Line-width in pixels + * @boxp: If non-NULL, returns the new object + * Returns: ID number for the object (typically @id), or -ve on error + */ +int scene_box(struct scene *scn, const char *name, uint id, uint width, + struct scene_obj_box **boxp); + /** * scene_txt_set_font() - Set the font for an object * diff --git a/test/boot/expo.c b/test/boot/expo.c index c9ff5b8dd24..e4f3ffc01fb 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -28,6 +28,8 @@ enum { OBJ_TEXT3, OBJ_MENU, OBJ_MENU_TITLE, + OBJ_BOX, + OBJ_BOX2, /* strings */ STR_SCENE_TITLE, @@ -545,6 +547,14 @@ static int expo_render_image(struct unit_test_state *uts) ut_assertok(scene_obj_set_pos(scn, OBJ_MENU, 50, 400)); + id = scene_box(scn, "box", OBJ_BOX, 3, NULL); + ut_assert(id > 0); + ut_assertok(scene_obj_set_bbox(scn, OBJ_BOX, 40, 390, 1000, 510)); + + id = scene_box(scn, "box2", OBJ_BOX2, 1, NULL); + ut_assert(id > 0); + ut_assertok(scene_obj_set_bbox(scn, OBJ_BOX, 500, 200, 1000, 350)); + scn2 = expo_lookup_scene_id(exp, SCENE1); ut_asserteq_ptr(scn, scn2); scn2 = expo_lookup_scene_id(exp, SCENE2); @@ -655,8 +665,7 @@ static int expo_render_image(struct unit_test_state *uts) ut_asserteq(ITEM2, scene_menu_get_cur_item(scn, OBJ_MENU)); ut_assertok(scene_arrange(scn)); ut_assertok(expo_render(exp)); - - ut_asserteq(14848, video_compress_fb(uts, dev, false)); + ut_asserteq(14883, video_compress_fb(uts, dev, false)); ut_assertok(video_check_copy_fb(uts, dev)); /* make sure only the preview for the second item is shown */ -- cgit v1.3.1 From 09f6f915fea90ea21a1a7b6a0a6907f89034dae1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:45 -0600 Subject: expo: Support object alignment Add support for left, right and centred alignment for text, in the horizontal dimension. Also support top, bottom and centred in the vertical dimension, for the text object as a whole. Alignment is not yet implemented for images. It has no meaning for menus. A textline object uses a text object internally, so alignment is supported there. Provide some documentation to explain how objects are positioned. Signed-off-by: Simon Glass --- boot/scene.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++--- doc/develop/expo.rst | 31 +++++++++++++++ include/expo.h | 63 ++++++++++++++++++++++++++++++ test/boot/expo.c | 23 +++++++++-- 4 files changed, 216 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/boot/scene.c b/boot/scene.c index f971db9aab4..3091a9e0ab1 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -306,6 +306,30 @@ int scene_obj_set_bbox(struct scene *scn, uint id, int x0, int y0, int x1, return 0; } +int scene_obj_set_halign(struct scene *scn, uint id, enum scene_obj_align aln) +{ + struct scene_obj *obj; + + obj = scene_obj_find(scn, id, SCENEOBJT_NONE); + if (!obj) + return log_msg_ret("osh", -ENOENT); + obj->horiz = aln; + + return 0; +} + +int scene_obj_set_valign(struct scene *scn, uint id, enum scene_obj_align aln) +{ + struct scene_obj *obj; + + obj = scene_obj_find(scn, id, SCENEOBJT_NONE); + if (!obj) + return log_msg_ret("osv", -ENOENT); + obj->vert = aln; + + return 0; +} + int scene_obj_set_hide(struct scene *scn, uint id, bool hide) { int ret; @@ -331,6 +355,44 @@ int scene_obj_flag_clrset(struct scene *scn, uint id, uint clr, uint set) return 0; } +static void handle_alignment(enum scene_obj_align horiz, + enum scene_obj_align vert, + struct scene_obj_bbox *bbox, + struct scene_obj_dims *dims, + int xsize, int ysize, + struct scene_obj_offset *offset) +{ + int width, height; + + width = bbox->x1 - bbox->x0; + height = bbox->y1 - bbox->y0; + + switch (horiz) { + case SCENEOA_CENTRE: + offset->xofs = (width - dims->x) / 2; + break; + case SCENEOA_RIGHT: + offset->xofs = width - dims->x; + break; + case SCENEOA_LEFT: + offset->xofs = 0; + break; + } + + switch (vert) { + case SCENEOA_CENTRE: + offset->yofs = (height - dims->y) / 2; + break; + case SCENEOA_BOTTOM: + offset->yofs = height - dims->y; + break; + case SCENEOA_TOP: + default: + offset->yofs = 0; + break; + } +} + int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) { struct scene_obj *obj; @@ -445,10 +507,12 @@ static int scene_txt_render(struct expo *exp, struct udevice *dev, struct scene_txt_generic *gen, int x, int y, int menu_inset) { - const struct vidconsole_mline *mline; + const struct vidconsole_mline *mline, *last; struct video_priv *vid_priv; struct vidconsole_colour old; enum colour_idx fore, back; + struct scene_obj_dims dims; + struct scene_obj_bbox bbox; const char *str; int ret; @@ -482,13 +546,33 @@ static int scene_txt_render(struct expo *exp, struct udevice *dev, obj->bbox.y1, vid_priv->colour_bg); } - if (!gen->lines.count) { + mline = alist_get(&gen->lines, 0, typeof(*mline)); + last = alist_get(&gen->lines, gen->lines.count - 1, typeof(*mline)); + if (mline) + dims.y = last->bbox.y1 - mline->bbox.y0; + bbox.y0 = obj->bbox.y0; + bbox.y1 = obj->bbox.y1; + + if (!mline) { vidconsole_set_cursor_pos(cons, x, y); vidconsole_put_string(cons, str); } + alist_for_each(mline, &gen->lines) { - vidconsole_set_cursor_pos(cons, x + mline->bbox.x0, - y + mline->bbox.y0); + struct scene_obj_offset offset; + + bbox.x0 = obj->bbox.x0; + bbox.x1 = obj->bbox.x1; + dims.x = mline->bbox.x1 - mline->bbox.x0; + handle_alignment(obj->horiz, obj->vert, &bbox, &dims, + obj->bbox.x1 - obj->bbox.x0, + obj->bbox.y1 - obj->bbox.y0, &offset); + + x = obj->bbox.x0 + offset.xofs; + y = obj->bbox.y0 + offset.yofs + mline->bbox.y0; + if (y > bbox.y1) + break; /* clip this line and any following */ + vidconsole_set_cursor_pos(cons, x, y); vidconsole_put_stringn(cons, str + mline->start, mline->len); } if (obj->flags & SCENEOF_POINT) @@ -515,7 +599,7 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) int x, y, ret; y = obj->bbox.y0; - x = obj->bbox.x0; + x = obj->bbox.x0 + obj->ofs.xofs; vid_priv = dev_get_uclass_priv(dev); switch (obj->type) { @@ -626,14 +710,27 @@ int scene_calc_arrange(struct scene *scn, struct expo_arrange_info *arr) int scene_arrange(struct scene *scn) { struct expo_arrange_info arr; + int xsize = 0, ysize = 0; struct scene_obj *obj; + struct udevice *dev; int ret; + dev = scn->expo->display; + if (dev) { + struct video_priv *priv = dev_get_uclass_priv(dev); + + xsize = priv->xsize; + ysize = priv->ysize; + } + ret = scene_calc_arrange(scn, &arr); if (ret < 0) return log_msg_ret("arr", ret); list_for_each_entry(obj, &scn->obj_head, sibling) { + handle_alignment(obj->horiz, obj->vert, &obj->bbox, &obj->dims, + xsize, ysize, &obj->ofs); + switch (obj->type) { case SCENEOBJT_NONE: case SCENEOBJT_IMAGE: diff --git a/doc/develop/expo.rst b/doc/develop/expo.rst index 8f63ccbe3ef..d6fc487e030 100644 --- a/doc/develop/expo.rst +++ b/doc/develop/expo.rst @@ -107,6 +107,37 @@ refer to objects which have been created. So a menu item is just a collection of IDs of text and image objects. When adding a menu item you must create these objects first, then create the menu item, passing in the relevant IDs. +Position and alignment +~~~~~~~~~~~~~~~~~~~~~~ + +Objects are typically positioned automatically, when scene_arrange() is called. +However it is possible to position objects manually. The scene_obj_set_pos() +sets the coordinates of the top left of the object. + +All objects have a bounding box. Typically this is calculated by looking at the +object contents, in `scene_calc_arrange()`. The calculated dimensions of each +object are stored in the object's `dims` field. + +It is possible to adjust the size of an object with `scene_obj_set_size()` or +even set the bounding box, with `scene_obj_set_bbox()`. The `SCENEOF_SIZE_VALID` +flag tracks whether the width/height should be maintained when the position +changes. + +If the bounding box is larger than the object needs, the object can be aligned +to different edges within the box. Objects can be left- or right-aligned, +or centred. For text objects this applies to each line of text. Normally objects +are drawn starting at the top of their bounding box, but they can be aligned +vertically to the bottom, or centred vertically within the box. + +Where the width of a text object's bounding box is smaller than the space needed +to show the next, the text is word-wrapped onto multiple lines, assuming there +is enough vertical space. Newline characters in the next cause a new line to be +started. The measurement information is created by the Truetype console driver +and stored in an alist in `struct scene_txt_generic`. + +When the object is drawn the `ofs` field indicates the x and y offset to use, +from the top left of the bounding box. These values are affected by alignment. + Creating an expo ---------------- diff --git a/include/expo.h b/include/expo.h index 8833dcceb7e..001f7db2553 100644 --- a/include/expo.h +++ b/include/expo.h @@ -210,6 +210,19 @@ struct scene_obj_bbox { int y1; }; +/** + * struct scene_obj_offset - Offsets for drawing the object + * + * Stores the offset from x0, x1 at which objects are drawn + * + * @xofs: x offset + * @yofs: y offset + */ +struct scene_obj_offset { + int xofs; + int yofs; +}; + /** * struct scene_obj_dims - Dimensions of the object being drawn * @@ -225,6 +238,30 @@ struct scene_obj_dims { int y; }; +/** + * enum scene_obj_halign - Horizontal alignment of objects + * + * Objects are normally drawn on the left size of their bounding box. This + * properly allows aligning on the right or having the object centred. + * + * @SCENEOA_LEFT: Left of object is aligned with its x coordinate + * @SCENEOA_RIGHT: Right of object is aligned with x + w + * @SCENEOA_CENTRE: Centre of object is aligned with centre of bounding box + * @SCENEOA_TOP: Left of object is aligned with its x coordinate + * @SCENEOA_BOTTOM: Right of object is aligned with x + w + * + * Note: It would be nice to make this a char type but Sphinx riddles: + * ./include/expo.h:258: error: Cannot parse enum! + * enum scene_obj_align : char { + */ +enum scene_obj_align { + SCENEOA_LEFT, + SCENEOA_RIGHT, + SCENEOA_CENTRE, + SCENEOA_TOP = SCENEOA_LEFT, + SCENEOA_BOTTOM = SCENEOA_RIGHT, +}; + /** * enum scene_obj_flags_t - flags for objects * @@ -255,7 +292,10 @@ enum { * @id: ID number of the object * @type: Type of this object * @bbox: Bounding box for this object + * @ofs: Offset from x0, y0 where the object is drawn * @dims: Dimensions of the text/image (may be smaller than bbox) + * @horiz: Horizonal alignment + * @vert: Vertical alignment * @flags: Flags for this object * @bit_length: Number of bits used for this object in CMOS RAM * @start_bit: Start bit to use for this object in CMOS RAM @@ -267,7 +307,10 @@ struct scene_obj { uint id; enum scene_obj_t type; struct scene_obj_bbox bbox; + struct scene_obj_offset ofs; struct scene_obj_dims dims; + enum scene_obj_align horiz; + enum scene_obj_align vert; u8 flags; u8 bit_length; u16 start_bit; @@ -755,6 +798,26 @@ int scene_obj_set_width(struct scene *scn, uint id, int w); int scene_obj_set_bbox(struct scene *scn, uint id, int x0, int y0, int x1, int y1); +/** + * scene_obj_set_halign() - Set the horizontal alignment of an object + * + * @scn: Scene to update + * @id: ID of object to update + * @aln: Horizontal alignment to use + * Returns: 0 if OK, -ENOENT if @id is invalid + */ +int scene_obj_set_halign(struct scene *scn, uint id, enum scene_obj_align aln); + +/** + * scene_obj_set_valign() - Set the vertical alignment of an object + * + * @scn: Scene to update + * @id: ID of object to update + * @aln: Vertical alignment to use + * Returns: 0 if OK, -ENOENT if @id is invalid + */ +int scene_obj_set_valign(struct scene *scn, uint id, enum scene_obj_align aln); + /** * scene_obj_set_hide() - Set whether an object is hidden * diff --git a/test/boot/expo.c b/test/boot/expo.c index e4f3ffc01fb..b9093b5780b 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -492,13 +492,14 @@ static int expo_render_image(struct unit_test_state *uts) 60)); ut_assertok(scene_obj_set_pos(scn, OBJ_TEXT2, 200, 600)); + /* this string is clipped as it extends beyond its bottom bound */ id = scene_txt_str(scn, "text", OBJ_TEXT3, STR_TEXT3, - "this is yet\nanother string, with word-wrap", + "this is yet\nanother string, with word-wrap and it goes on for quite a while", NULL); ut_assert(id > 0); ut_assertok(scene_txt_set_font(scn, OBJ_TEXT3, "nimbus_sans_l_regular", 60)); - ut_assertok(scene_obj_set_bbox(scn, OBJ_TEXT3, 500, 200, 1000, 700)); + ut_assertok(scene_obj_set_bbox(scn, OBJ_TEXT3, 500, 200, 1000, 350)); id = scene_menu(scn, "main", OBJ_MENU, &menu); ut_assert(id > 0); @@ -665,9 +666,25 @@ static int expo_render_image(struct unit_test_state *uts) ut_asserteq(ITEM2, scene_menu_get_cur_item(scn, OBJ_MENU)); ut_assertok(scene_arrange(scn)); ut_assertok(expo_render(exp)); - ut_asserteq(14883, video_compress_fb(uts, dev, false)); + ut_asserteq(16304, video_compress_fb(uts, dev, false)); ut_assertok(video_check_copy_fb(uts, dev)); + /* do some alignment checks */ + ut_assertok(scene_obj_set_halign(scn, OBJ_TEXT3, SCENEOA_CENTRE)); + ut_assertok(expo_render(exp)); + ut_asserteq(16368, video_compress_fb(uts, dev, false)); + ut_assertok(scene_obj_set_halign(scn, OBJ_TEXT3, SCENEOA_RIGHT)); + ut_assertok(expo_render(exp)); + ut_asserteq(16321, video_compress_fb(uts, dev, false)); + + ut_assertok(scene_obj_set_halign(scn, OBJ_TEXT3, SCENEOA_LEFT)); + ut_assertok(scene_obj_set_valign(scn, OBJ_TEXT3, SCENEOA_CENTRE)); + ut_assertok(expo_render(exp)); + ut_asserteq(18763, video_compress_fb(uts, dev, false)); + ut_assertok(scene_obj_set_valign(scn, OBJ_TEXT3, SCENEOA_BOTTOM)); + ut_assertok(expo_render(exp)); + ut_asserteq(18714, video_compress_fb(uts, dev, false)); + /* make sure only the preview for the second item is shown */ obj = scene_obj_find(scn, ITEM1_PREVIEW, SCENEOBJT_NONE); ut_asserteq(true, obj->flags & SCENEOF_HIDE); -- cgit v1.3.1 From e005f18b933f3f4555fd08a4d66a1f9aee8f47e1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:46 -0600 Subject: expo: Begin implementation of a text editor It is useful to be able to edit text, e.g. to allow the user to edit the environment or the command-line arguments for the OS. Add the beginnings of an implementation. Future work is needed to finish this: keypress handling and scrolling. For now it just displays the text. Signed-off-by: Simon Glass --- boot/Makefile | 2 +- boot/cedit.c | 5 +++++ boot/scene.c | 30 +++++++++++++++++++++++-- boot/scene_internal.h | 12 ++++++++++ boot/scene_textedit.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++ doc/develop/expo.rst | 1 + include/expo.h | 41 ++++++++++++++++++++++++++++++++++ test/boot/expo.c | 16 +++++++++++++- 8 files changed, 164 insertions(+), 4 deletions(-) create mode 100644 boot/scene_textedit.c (limited to 'include') diff --git a/boot/Makefile b/boot/Makefile index 71dafaefa76..e0d1579827d 100644 --- a/boot/Makefile +++ b/boot/Makefile @@ -58,7 +58,7 @@ obj-$(CONFIG_CMD_ADTIMG) += image-android-dt.o obj-$(CONFIG_$(PHASE_)LOAD_FIT) += common_fit.o obj-$(CONFIG_$(PHASE_)EXPO) += expo.o scene.o expo_build.o -obj-$(CONFIG_$(PHASE_)EXPO) += scene_menu.o scene_textline.o +obj-$(CONFIG_$(PHASE_)EXPO) += scene_menu.o scene_textline.o scene_textedit.o ifdef CONFIG_COREBOOT_SYSINFO obj-$(CONFIG_$(PHASE_)EXPO) += expo_build_cb.o endif diff --git a/boot/cedit.c b/boot/cedit.c index 9153fe769c6..54810257fb9 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -82,6 +82,7 @@ int cedit_arange(struct expo *exp, struct video_priv *vpriv, uint scene_id) case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_MENU: scene_obj_set_pos(scn, obj->id, 50, y); @@ -383,6 +384,7 @@ static int h_write_settings(struct scene_obj *obj, void *vpriv) case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_TEXTLINE: { const struct scene_obj_textline *tline; @@ -483,6 +485,7 @@ static int h_read_settings(struct scene_obj *obj, void *vpriv) case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_TEXTLINE: { const struct scene_obj_textline *tline; @@ -555,6 +558,7 @@ static int h_write_settings_env(struct scene_obj *obj, void *vpriv) case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_MENU: menu = (struct scene_obj_menu *)obj; @@ -639,6 +643,7 @@ static int h_read_settings_env(struct scene_obj *obj, void *vpriv) case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_MENU: menu = (struct scene_obj_menu *)obj; diff --git a/boot/scene.c b/boot/scene.c index 3091a9e0ab1..c8dc1716f1d 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -417,13 +417,19 @@ int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) *widthp = width; return height; } - case SCENEOBJT_TEXT: { - struct scene_txt_generic *gen = &((struct scene_obj_txt *)obj)->gen; + case SCENEOBJT_TEXT: + case SCENEOBJT_TEXTEDIT: { + struct scene_txt_generic *gen; struct expo *exp = scn->expo; struct vidconsole_bbox bbox; int len, ret, limit; const char *str; + if (obj->type == SCENEOBJT_TEXT) + gen = &((struct scene_obj_txt *)obj)->gen; + else + gen = &((struct scene_obj_txtedit *)obj)->gen; + str = expo_get_str(exp, gen->str_id); if (!str) return log_msg_ret("str", -ENOENT); @@ -658,6 +664,13 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) obj->bbox.y1, box->width, vid_priv->colour_fg); break; } + case SCENEOBJT_TEXTEDIT: { + struct scene_obj_txtedit *ted = (struct scene_obj_txtedit *)obj; + + ret = scene_txt_render(exp, dev, cons, obj, &ted->gen, x, y, + theme->menu_inset); + break; + } } return 0; @@ -677,6 +690,7 @@ int scene_calc_arrange(struct scene *scn, struct expo_arrange_info *arr) case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_MENU: { struct scene_obj_menu *menu; @@ -736,6 +750,7 @@ int scene_arrange(struct scene *scn) case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_MENU: { struct scene_obj_menu *menu; @@ -782,6 +797,7 @@ int scene_render_deps(struct scene *scn, uint id) case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_MENU: scene_menu_render_deps(scn, @@ -921,6 +937,9 @@ int scene_send_key(struct scene *scn, int key, struct expo_action *event) return log_msg_ret("key", ret); break; } + case SCENEOBJT_TEXTEDIT: + /* TODO(sjg@chromium.org): Implement this */ + break; } return 0; } @@ -947,6 +966,7 @@ int scene_obj_calc_bbox(struct scene_obj *obj, struct vidconsole_bbox bbox[]) case SCENEOBJT_IMAGE: case SCENEOBJT_TEXT: case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: return -ENOSYS; case SCENEOBJT_MENU: { struct scene_obj_menu *menu = (struct scene_obj_menu *)obj; @@ -977,6 +997,7 @@ int scene_calc_dims(struct scene *scn, bool do_menus) case SCENEOBJT_NONE: case SCENEOBJT_TEXT: case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: case SCENEOBJT_IMAGE: { int width; @@ -1038,6 +1059,10 @@ int scene_apply_theme(struct scene *scn, struct expo_theme *theme) case SCENEOBJT_BOX: case SCENEOBJT_TEXTLINE: break; + case SCENEOBJT_TEXTEDIT: + scene_txted_set_font(scn, obj->id, NULL, + theme->font_size); + break; case SCENEOBJT_TEXT: scene_txt_set_font(scn, obj->id, NULL, theme->font_size); @@ -1079,6 +1104,7 @@ static int scene_obj_open(struct scene *scn, struct scene_obj *obj) case SCENEOBJT_MENU: case SCENEOBJT_TEXT: case SCENEOBJT_BOX: + case SCENEOBJT_TEXTEDIT: break; case SCENEOBJT_TEXTLINE: ret = scene_textline_open(scn, diff --git a/boot/scene_internal.h b/boot/scene_internal.h index ac2a36d6e4d..760cc629b86 100644 --- a/boot/scene_internal.h +++ b/boot/scene_internal.h @@ -414,4 +414,16 @@ int scene_textline_close(struct scene *scn, struct scene_obj_textline *tline); */ int scene_calc_arrange(struct scene *scn, struct expo_arrange_info *arr); +/** + * scene_txt_generic_init() - Set up the generic part of a text object + * + * @exp: Expo containing the object + * @gen: Generic text info + * @name: Object name + * @str_id: String ID for the text + * @str: Initial text string for the object, or NULL to just use str_id + */ +int scene_txt_generic_init(struct expo *exp, struct scene_txt_generic *gen, + const char *name, uint str_id, const char *str); + #endif /* __SCENE_INTERNAL_H */ diff --git a/boot/scene_textedit.c b/boot/scene_textedit.c new file mode 100644 index 00000000000..8242eb39806 --- /dev/null +++ b/boot/scene_textedit.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Implementation of a menu in a scene + * + * Copyright 2025 Google LLC + * Written by Simon Glass + */ + +#define LOG_CATEGORY LOGC_EXPO + +#include +#include +#include +#include +#include "scene_internal.h" + +enum { + INITIAL_SIZE = SZ_4K, +}; + +int scene_texted(struct scene *scn, const char *name, uint id, uint str_id, + struct scene_obj_txtedit **teditp) +{ + struct scene_obj_txtedit *ted; + char *buf; + int ret; + + ret = scene_obj_add(scn, name, id, SCENEOBJT_TEXTEDIT, + sizeof(struct scene_obj_txtedit), + (struct scene_obj **)&ted); + if (ret < 0) + return log_msg_ret("obj", ret); + + abuf_init(&ted->buf); + if (!abuf_realloc(&ted->buf, INITIAL_SIZE)) + return log_msg_ret("buf", -ENOMEM); + buf = abuf_data(&ted->buf); + *buf = '\0'; + + ret = scene_txt_generic_init(scn->expo, &ted->gen, name, str_id, buf); + if (ret) + return log_msg_ret("teg", ret); + if (teditp) + *teditp = ted; + + return ted->obj.id; +} + +int scene_txted_set_font(struct scene *scn, uint id, const char *font_name, + uint font_size) +{ + struct scene_obj_txtedit *ted; + + ted = scene_obj_find(scn, id, SCENEOBJT_TEXTEDIT); + if (!ted) + return log_msg_ret("find", -ENOENT); + ted->gen.font_name = font_name; + ted->gen.font_size = font_size; + + return 0; +} diff --git a/doc/develop/expo.rst b/doc/develop/expo.rst index d6fc487e030..b94340e9a8d 100644 --- a/doc/develop/expo.rst +++ b/doc/develop/expo.rst @@ -560,6 +560,7 @@ Future ideas Some ideas for future work: - Default menu item and a timeout +- Complete the text editor - Image formats other than BMP - Use of ANSI sequences to control a serial terminal - Colour selection diff --git a/include/expo.h b/include/expo.h index 001f7db2553..16f2f18c4fa 100644 --- a/include/expo.h +++ b/include/expo.h @@ -183,12 +183,14 @@ struct scene { * @SCENEOBJT_TEXT: Text line to render * @SCENEOBJT_MENU: Menu containing items the user can select * @SCENEOBJT_TEXTLINE: Line of text the user can edit + * @SCENEOBJT_TEXTEDIT: Simple text editor */ enum scene_obj_t { SCENEOBJT_NONE = 0, SCENEOBJT_IMAGE, SCENEOBJT_TEXT, SCENEOBJT_BOX, + SCENEOBJT_TEXTEDIT, /* types from here on can be highlighted */ SCENEOBJT_MENU, @@ -464,6 +466,21 @@ struct scene_obj_box { uint width; }; +/** + * struct scene_obj_txtedit - information about a box in a scene + * + * A text editor which allows users to edit a small text file + * + * @obj: Basic object information + * @gen: Generic information common to all objects which show text + * @buf: Text buffer containing current text + */ +struct scene_obj_txtedit { + struct scene_obj obj; + struct scene_txt_generic gen; + struct abuf buf; +}; + /** * struct expo_arrange_info - Information used when arranging a scene * @@ -741,6 +758,19 @@ int scene_textline(struct scene *scn, const char *name, uint id, uint max_chars, int scene_box(struct scene *scn, const char *name, uint id, uint width, struct scene_obj_box **boxp); +/** + * scene_texted() - create a text editor + * + * @scn: Scene to update + * @name: Name to use (this is allocated by this call) + * @id: ID to use for the new object (0 to allocate one) + * @strid: ID of the string to edit + * @teditp: If non-NULL, returns the new object + * Returns: ID number for the object (typically @id), or -ve on error + */ +int scene_texted(struct scene *scn, const char *name, uint id, uint strid, + struct scene_obj_txtedit **teditp); + /** * scene_txt_set_font() - Set the font for an object * @@ -752,6 +782,17 @@ int scene_box(struct scene *scn, const char *name, uint id, uint width, int scene_txt_set_font(struct scene *scn, uint id, const char *font_name, uint font_size); +/** + * scene_txted_set_font() - Set the font for an object + * + * @scn: Scene to update + * @id: ID of object to update + * @font_name: Font name to use (allocated by caller) + * @font_size: Font size to use (nominal height in pixels) + */ +int scene_txted_set_font(struct scene *scn, uint id, const char *font_name, + uint font_size); + /** * scene_obj_set_pos() - Set the postion of an object * diff --git a/test/boot/expo.c b/test/boot/expo.c index b9093b5780b..e624a00c2c0 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -30,6 +30,7 @@ enum { OBJ_MENU_TITLE, OBJ_BOX, OBJ_BOX2, + OBJ_TEXTED, /* strings */ STR_SCENE_TITLE, @@ -37,6 +38,7 @@ enum { STR_TEXT, STR_TEXT2, STR_TEXT3, + STR_TEXTED, STR_MENU_TITLE, STR_POINTER_TEXT, @@ -462,6 +464,7 @@ static int expo_render_image(struct unit_test_state *uts) { struct scene_obj_menu *menu; struct scene *scn, *scn2; + struct abuf orig, *text; struct expo_action act; struct scene_obj *obj; struct udevice *dev; @@ -556,6 +559,14 @@ static int expo_render_image(struct unit_test_state *uts) ut_assert(id > 0); ut_assertok(scene_obj_set_bbox(scn, OBJ_BOX, 500, 200, 1000, 350)); + id = scene_texted(scn, "editor", OBJ_TEXTED, STR_TEXTED, NULL); + ut_assert(id > 0); + ut_assertok(scene_obj_set_bbox(scn, OBJ_TEXTED, 100, 200, 400, 650)); + ut_assertok(expo_edit_str(exp, STR_TEXTED, &orig, &text)); + + abuf_printf(text, "This\nis the initial contents of the text editor " + "but it is quite likely that more will be added later"); + scn2 = expo_lookup_scene_id(exp, SCENE1); ut_asserteq_ptr(scn, scn2); scn2 = expo_lookup_scene_id(exp, SCENE2); @@ -666,9 +677,12 @@ static int expo_render_image(struct unit_test_state *uts) ut_asserteq(ITEM2, scene_menu_get_cur_item(scn, OBJ_MENU)); ut_assertok(scene_arrange(scn)); ut_assertok(expo_render(exp)); - ut_asserteq(16304, video_compress_fb(uts, dev, false)); + ut_asserteq(19673, video_compress_fb(uts, dev, false)); ut_assertok(video_check_copy_fb(uts, dev)); + /* hide the text editor since the following tets don't need it */ + scene_obj_set_hide(scn, OBJ_TEXTED, true); + /* do some alignment checks */ ut_assertok(scene_obj_set_halign(scn, OBJ_TEXT3, SCENEOA_CENTRE)); ut_assertok(expo_render(exp)); -- cgit v1.3.1 From 0dc8c7740c8f5a7155259f0e55618f8006c0d7af Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:50 -0600 Subject: expo: Support highlighting menu items Expo normally uses a pointer to show the current item. Add support for highlighting as well, since this makes it easier for the user to see the current item. Signed-off-by: Simon Glass --- boot/cedit.c | 1 + boot/scene.c | 31 +++++++++++++++++++++---------- boot/scene_menu.c | 14 +++++++++++--- include/expo.h | 2 ++ test/boot/expo.c | 13 +++++++++++++ 5 files changed, 48 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/boot/cedit.c b/boot/cedit.c index 54810257fb9..8faf230a9e2 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -126,6 +126,7 @@ int cedit_prepare(struct expo *exp, struct udevice *vid_dev, return log_msg_ret("sid", ret); exp->popup = true; + exp->show_highlight = true; /* This is not supported for now */ if (0) diff --git a/boot/scene.c b/boot/scene.c index c8dc1716f1d..237f2bccc00 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -466,8 +466,10 @@ int scene_obj_get_hw(struct scene *scn, uint id, int *widthp) * @obj: Object to render * @box_only: true to show a box around the object, but keep the normal * background colour inside + * @cur_item: true to render the background only for the current menu item */ -static void scene_render_background(struct scene_obj *obj, bool box_only) +static void scene_render_background(struct scene_obj *obj, bool box_only, + bool cur_item) { struct vidconsole_bbox bbox[SCENEBB_count], *sel; struct expo *exp = obj->scene->expo; @@ -493,7 +495,7 @@ static void scene_render_background(struct scene_obj *obj, bool box_only) if (scene_obj_calc_bbox(obj, bbox)) return; - sel = &bbox[SCENEBB_label]; + sel = cur_item ? &bbox[SCENEBB_curitem] : &bbox[SCENEBB_label]; if (!sel->valid) return; @@ -547,9 +549,13 @@ static int scene_txt_render(struct expo *exp, struct udevice *dev, } if (obj->flags & SCENEOF_POINT) { + int inset; + + inset = exp->popup ? menu_inset : 0; vidconsole_push_colour(cons, fore, back, &old); - video_fill_part(dev, x - menu_inset, y, obj->bbox.x1, - obj->bbox.y1, vid_priv->colour_bg); + video_fill_part(dev, x - inset, y, + obj->bbox.x1, obj->bbox.y1, + vid_priv->colour_bg); } mline = alist_get(&gen->lines, 0, typeof(*mline)); @@ -632,13 +638,18 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) case SCENEOBJT_MENU: { struct scene_obj_menu *menu = (struct scene_obj_menu *)obj; - if (exp->popup && (obj->flags & SCENEOF_OPEN)) { - if (!cons) - return -ENOTSUPP; + if (exp->popup) { + if (obj->flags & SCENEOF_OPEN) { + if (!cons) + return -ENOTSUPP; - /* draw a background behind the menu items */ - scene_render_background(obj, false); + /* draw a background behind the menu items */ + scene_render_background(obj, false, false); + } + } else if (exp->show_highlight) { + /* do nothing */ } + /* * With a vidconsole, the text and item pointer are rendered as * normal objects so we don't need to do anything here. The menu @@ -655,7 +666,7 @@ static int scene_obj_render(struct scene_obj *obj, bool text_mode) } case SCENEOBJT_TEXTLINE: if (obj->flags & SCENEOF_OPEN) - scene_render_background(obj, true); + scene_render_background(obj, true, false); break; case SCENEOBJT_BOX: { struct scene_obj_box *box = (struct scene_obj_box *)obj; diff --git a/boot/scene_menu.c b/boot/scene_menu.c index de433ece6ee..8db6a2b2f4d 100644 --- a/boot/scene_menu.c +++ b/boot/scene_menu.c @@ -87,7 +87,7 @@ struct scene_menitem *scene_menuitem_find_val(const struct scene_obj_menu *menu, static int update_pointers(struct scene_obj_menu *menu, uint id, bool point) { struct scene *scn = menu->obj.scene; - const bool stack = scn->expo->popup; + const bool stack = scn->expo->show_highlight; const struct scene_menitem *item; int ret; @@ -108,9 +108,17 @@ static int update_pointers(struct scene_obj_menu *menu, uint id, bool point) } if (stack) { + uint id; + int val; + point &= scn->highlight_id == menu->obj.id; - scene_obj_flag_clrset(scn, item->label_id, SCENEOF_POINT, - point ? SCENEOF_POINT : 0); + val = point ? SCENEOF_POINT : 0; + id = item->desc_id; + if (!id) + id = item->label_id; + if (!id) + id = item->key_id; + scene_obj_flag_clrset(scn, id, SCENEOF_POINT, val); } return 0; diff --git a/include/expo.h b/include/expo.h index 16f2f18c4fa..dfecd6ed239 100644 --- a/include/expo.h +++ b/include/expo.h @@ -106,6 +106,7 @@ struct expo_theme { * type set to EXPOACT_NONE if there is no action * @text_mode: true to use text mode for the menu (no vidconsole) * @popup: true to use popup menus, instead of showing all items + * @show_highlight: show a highlight bar on the selected menu item * @priv: Private data for the controller * @done: Indicates that a cedit session is complete and the user has quit * @save: Indicates that cedit data should be saved, rather than discarded @@ -123,6 +124,7 @@ struct expo { struct expo_action action; bool text_mode; bool popup; + bool show_highlight; void *priv; bool done; bool save; diff --git a/test/boot/expo.c b/test/boot/expo.c index e624a00c2c0..ddfb739f9cf 100644 --- a/test/boot/expo.c +++ b/test/boot/expo.c @@ -666,6 +666,13 @@ static int expo_render_image(struct unit_test_state *uts) ut_assertok(scene_arrange(scn)); ut_asserteq(0, scn->highlight_id); + scene_set_highlight_id(scn, OBJ_MENU); + ut_assertok(scene_arrange(scn)); + ut_asserteq(OBJ_MENU, scn->highlight_id); + ut_assertok(expo_render(exp)); + + ut_asserteq(19704, video_compress_fb(uts, dev, false)); + /* move down */ ut_assertok(expo_send_key(exp, BKEY_DOWN)); @@ -719,6 +726,12 @@ static int expo_render_image(struct unit_test_state *uts) /* make sure there was no console output */ ut_assert_console_end(); + /* now try with the highlight */ + exp->show_highlight = true; + ut_assertok(scene_arrange(scn)); + ut_assertok(expo_render(exp)); + ut_asserteq(18844, video_compress_fb(uts, dev, false)); + /* now try in text mode */ expo_set_text_mode(exp, true); ut_assertok(expo_render(exp)); -- cgit v1.3.1 From 8d7ae52d7735ffecf34fa8b2657ee2fcfaac51b6 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:52 -0600 Subject: expo: Drop the render from expo_poll() Within tests it is useful to be able to control rendering of the expo. Drop the automatic call to expo_render() within expo_poll() and adjust its callers to handle this instead. Signed-off-by: Simon Glass --- boot/cedit.c | 4 ++++ boot/expo.c | 4 ---- cmd/bootflow.c | 3 +++ include/expo.h | 9 ++++++--- 4 files changed, 13 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/boot/cedit.c b/boot/cedit.c index 8faf230a9e2..56dc7c6af15 100644 --- a/boot/cedit.c +++ b/boot/cedit.c @@ -219,6 +219,10 @@ int cedit_run(struct expo *exp) do { struct expo_action act; + ret = expo_render(exp); + if (ret) + return log_msg_ret("cer", ret); + ret = expo_poll(exp, &act); if (!ret) cedit_do_action(exp, scn, vid_priv, &act); diff --git a/boot/expo.c b/boot/expo.c index ee8ffaf8920..94413acd381 100644 --- a/boot/expo.c +++ b/boot/expo.c @@ -320,10 +320,6 @@ int expo_poll(struct expo *exp, struct expo_action *act) { int ichar, key, ret; - ret = expo_render(exp); - if (ret) - return log_msg_ret("ere", ret); - ichar = cli_ch_process(&exp->cch, 0); if (!ichar) { int i; diff --git a/cmd/bootflow.c b/cmd/bootflow.c index efac27a5d77..55643a6876f 100644 --- a/cmd/bootflow.c +++ b/cmd/bootflow.c @@ -116,6 +116,9 @@ __maybe_unused static int bootflow_handle_menu(struct bootstd_priv *std, return log_msg_ret("bhs", ret); do { + ret = expo_render(exp); + if (ret) + return log_msg_ret("bhr", ret); ret = bootflow_menu_poll(exp, &bflow); } while (ret == -EAGAIN); diff --git a/include/expo.h b/include/expo.h index dfecd6ed239..2addddd5012 100644 --- a/include/expo.h +++ b/include/expo.h @@ -1006,10 +1006,13 @@ int expo_build(ofnode root, struct expo **expp); int cb_expo_build(struct expo **expp); /** - * expo_poll() - render an expo and see if the user takes an action + * expo_poll() - see if the user takes an action * - * Thsi calls expo_render() and then checks for a keypress. If there is one, it - * is processed and the resulting action returned, if any + * This checks for a keypress. If there is one, it is processed and the + * resulting action returned, if any. + * + * Note that expo_render() should normally be called immediately before this + * function so that the user can see the latest state. * * @exp: Expo to poll * @act: Returns action on success -- cgit v1.3.1 From ddd1c97653560c6015f2c165de459ebfdc79f5d7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:53 -0600 Subject: expo: Provide a way to position things relative to display It is often necessary to centre objects within the display area. Add a special position value to indicate this. Signed-off-by: Simon Glass --- boot/scene.c | 5 +++++ include/expo.h | 6 ++++++ 2 files changed, 11 insertions(+) (limited to 'include') diff --git a/boot/scene.c b/boot/scene.c index 237f2bccc00..fa8f540bfb0 100644 --- a/boot/scene.c +++ b/boot/scene.c @@ -364,6 +364,11 @@ static void handle_alignment(enum scene_obj_align horiz, { int width, height; + if (bbox->x1 == SCENEOB_DISPLAY_MAX) + bbox->x1 = xsize ?: 1280; + if (bbox->y1 == SCENEOB_DISPLAY_MAX) + bbox->y1 = ysize ?: 1024; + width = bbox->x1 - bbox->x0; height = bbox->y1 - bbox->y0; diff --git a/include/expo.h b/include/expo.h index 2addddd5012..4dee479e9a0 100644 --- a/include/expo.h +++ b/include/expo.h @@ -242,6 +242,12 @@ struct scene_obj_dims { int y; }; +/* special values for dimensions */ +enum { + /* width/height of the display */ + SCENEOB_DISPLAY_MAX = 0x7f000000, +}; + /** * enum scene_obj_halign - Horizontal alignment of objects * -- cgit v1.3.1 From 06a9d88e4d887ea4c7395636d2cfb52948ab4112 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:55 -0600 Subject: expo: Update bootflow_menu_poll() to return a sequence ID Rather than returning a bootflow, return the index of the bootflow. This will allow callers to do their own translation to bootflows or some other data structure. Also return a special code when the user tries to move the pointer, so that the caller can cancel the boot-menu timeout, if this is in use. Signed-off-by: Simon Glass --- boot/bootflow_menu.c | 32 +++++++++++++------------------- cmd/bootflow.c | 16 ++++++++++------ include/bootflow.h | 8 ++++---- 3 files changed, 27 insertions(+), 29 deletions(-) (limited to 'include') diff --git a/boot/bootflow_menu.c b/boot/bootflow_menu.c index fb90e51e920..6bca17142ad 100644 --- a/boot/bootflow_menu.c +++ b/boot/bootflow_menu.c @@ -301,34 +301,28 @@ int bootflow_menu_start(struct bootstd_priv *std, bool text_mode, return 0; } -int bootflow_menu_poll(struct expo *exp, struct bootflow **bflowp) +int bootflow_menu_poll(struct expo *exp, int *seqp) { struct bootflow *sel_bflow; struct expo_action act; - int ret; + struct scene *scn; + int item, ret; sel_bflow = NULL; - *bflowp = NULL; + + scn = expo_lookup_scene_id(exp, exp->scene_id); + + item = scene_menu_get_cur_item(scn, OBJ_MENU); + *seqp = item > 0 ? item - ITEM : -1; ret = expo_poll(exp, &act); if (ret) return log_msg_ret("bmp", ret); switch (act.type) { - case EXPOACT_SELECT: { - struct bootflow *bflow; - int i; - - for (ret = bootflow_first_glob(&bflow), i = 0; !ret && i < 36; - ret = bootflow_next_glob(&bflow), i++) { - if (i == act.select.id - ITEM) { - *bflowp = bflow; - // printf("found %p\n", bflow); - return 0; - } - } + case EXPOACT_SELECT: + *seqp = act.select.id - ITEM; break; - } case EXPOACT_POINT_ITEM: { struct scene *scn = expo_lookup_scene_id(exp, MAIN); @@ -337,13 +331,13 @@ int bootflow_menu_poll(struct expo *exp, struct bootflow **bflowp) ret = scene_menu_select_item(scn, OBJ_MENU, act.select.id); if (ret) return log_msg_ret("bmp", ret); - break; + return -ERESTART; } case EXPOACT_QUIT: return -EPIPE; default: - break; + return -EAGAIN; } - return -EAGAIN; + return 0; } diff --git a/cmd/bootflow.c b/cmd/bootflow.c index 55643a6876f..551dffbb8b8 100644 --- a/cmd/bootflow.c +++ b/cmd/bootflow.c @@ -109,18 +109,21 @@ __maybe_unused static int bootflow_handle_menu(struct bootstd_priv *std, { struct expo *exp; struct bootflow *bflow; - int ret; + int ret, seq; ret = bootflow_menu_start(std, text_mode, &exp); if (ret) return log_msg_ret("bhs", ret); + ret = -ERESTART; do { - ret = expo_render(exp); - if (ret) - return log_msg_ret("bhr", ret); - ret = bootflow_menu_poll(exp, &bflow); - } while (ret == -EAGAIN); + if (ret == -ERESTART) { + ret = expo_render(exp); + if (ret) + return log_msg_ret("bhr", ret); + } + ret = bootflow_menu_poll(exp, &seq); + } while (ret == -EAGAIN || ret == -ERESTART); if (ret == -EPIPE) { printf("Nothing chosen\n"); @@ -128,6 +131,7 @@ __maybe_unused static int bootflow_handle_menu(struct bootstd_priv *std, } else if (ret) { printf("Menu failed (err=%d)\n", ret); } else { + bflow = alist_getw(&std->bootflows, seq, struct bootflow); printf("Selected: %s\n", bflow->os_name ? bflow->os_name : bflow->name); std->cur_bootflow = bflow; diff --git a/include/bootflow.h b/include/bootflow.h index 615fb97f4a4..75d88d47884 100644 --- a/include/bootflow.h +++ b/include/bootflow.h @@ -670,10 +670,10 @@ int bootflow_menu_start(struct bootstd_priv *std, bool text_mode, * bootflow_menu_poll() - Poll a menu for user action * * @exp: Expo to poll - * @bflowp: Returns chosen bootflow (set to NULL if nothing is chosen) - * Return 0 if a bootflow was chosen, -EAGAIN if nothing is chosen yet, -EPIPE - * if the user quit + * @seqp: Returns the bootflow chosen or currently pointed to (numbered from 0) + * Return: 0 if a bootflow was chosen, -EAGAIN if nothing is chosen yet, -EPIPE + * if the user quit, -ERESTART if the expo needs refreshing */ -int bootflow_menu_poll(struct expo *exp, struct bootflow **bflowp); +int bootflow_menu_poll(struct expo *exp, int *seqp); #endif -- cgit v1.3.1 From f769735f88fe8d864a895b275b4148616ffe2a29 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 2 May 2025 08:46:56 -0600 Subject: expo: Split setting up the menu from adding items Some callers may wish to add items later as they are discovered. Split the setup code into its own function, to permit this. Signed-off-by: Simon Glass --- boot/bootflow_menu.c | 31 ++++++++++++++++++++++++++----- include/bootflow.h | 15 +++++++++++++++ 2 files changed, 41 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/boot/bootflow_menu.c b/boot/bootflow_menu.c index 6bca17142ad..56a34ac8ed5 100644 --- a/boot/bootflow_menu.c +++ b/boot/bootflow_menu.c @@ -210,7 +210,6 @@ int bootflow_menu_add_all(struct expo *exp) ret = bootflow_menu_add(exp, bflow, i, &scn); if (ret) return log_msg_ret("bao", ret); - } ret = scene_arrange(scn); @@ -257,7 +256,7 @@ int bootflow_menu_apply_theme(struct expo *exp, ofnode node) return 0; } -int bootflow_menu_start(struct bootstd_priv *std, bool text_mode, +int bootflow_menu_setup(struct bootstd_priv *std, bool text_mode, struct expo **expp) { struct udevice *dev; @@ -267,9 +266,6 @@ int bootflow_menu_start(struct bootstd_priv *std, bool text_mode, ret = bootflow_menu_new(&exp); if (ret) return log_msg_ret("bmn", ret); - ret = bootflow_menu_add_all(exp); - if (ret) - return log_msg_ret("bma", ret); if (ofnode_valid(std->theme)) { ret = bootflow_menu_apply_theme(exp, std->theme); @@ -292,6 +288,31 @@ int bootflow_menu_start(struct bootstd_priv *std, bool text_mode, if (text_mode) expo_set_text_mode(exp, text_mode); + *expp = exp; + + return 0; +} + +int bootflow_menu_start(struct bootstd_priv *std, bool text_mode, + struct expo **expp) +{ + struct expo *exp; + int ret; + + ret = bootflow_menu_setup(std, text_mode, &exp); + if (ret) + return log_msg_ret("bmd", ret); + + ret = bootflow_menu_add_all(exp); + if (ret) + return log_msg_ret("bma", ret); + + if (ofnode_valid(std->theme)) { + ret = expo_apply_theme(exp, std->theme); + if (ret) + return log_msg_ret("thm", ret); + } + ret = expo_calc_dims(exp); if (ret) return log_msg_ret("bmd", ret); diff --git a/include/bootflow.h b/include/bootflow.h index 75d88d47884..8dcc8f96e11 100644 --- a/include/bootflow.h +++ b/include/bootflow.h @@ -655,9 +655,24 @@ struct bootflow_img *bootflow_img_add(struct bootflow *bflow, const char *fname, */ int bootflow_get_seq(const struct bootflow *bflow); +/** + * bootflow_menu_setup() - Set up a menu for bootflows + * + * Set up the expo, initially empty + * + * @std: bootstd information + * @text_mode: true to show the menu in text mode, false to use video display + * @expp: Returns the expo created, on success + * Return: 0 if OK, -ve on error + */ +int bootflow_menu_setup(struct bootstd_priv *std, bool text_mode, + struct expo **expp); + /** * bootflow_menu_start() - Start up a menu for bootflows * + * Set up the expo and add items + * * @std: bootstd information * @text_mode: true to show the menu in text mode, false to use video display * @expp: Returns the expo created, on success -- cgit v1.3.1 From 191b10ac70d7acfa9d5eda5bd5d3cb12f6c576fc Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 2 May 2025 14:07:39 -0600 Subject: PowerPC / Layerscape: Finish migration to DM_SERIAL Migrate the few ARM Layerscape platforms that had not been switched along with all remaining PowerPC platforms to DM_SERIAL. For PowerPC, this means that platforms which use SPL/TPL, keeping the non-DM serial driver enabled there as they do not use DM. We also rework the guards on how to define CFG_SYS_NS16550_CLK so that this is mostly in one place now. Signed-off-by: Tom Rini --- arch/powerpc/include/asm/config.h | 6 ++++-- configs/MPC8548CDS_36BIT_defconfig | 3 +-- configs/MPC8548CDS_defconfig | 3 +-- configs/MPC8548CDS_legacy_defconfig | 3 +-- configs/P1010RDB-PA_36BIT_NAND_defconfig | 3 ++- configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 +- configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 3 ++- configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 3 ++- configs/P1010RDB-PA_NAND_defconfig | 3 ++- configs/P1010RDB-PA_NOR_defconfig | 2 +- configs/P1010RDB-PA_SDCARD_defconfig | 3 ++- configs/P1010RDB-PA_SPIFLASH_defconfig | 3 ++- configs/P1010RDB-PB_36BIT_NAND_defconfig | 3 ++- configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 +- configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 3 ++- configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 3 ++- configs/P1010RDB-PB_NAND_defconfig | 3 ++- configs/P1010RDB-PB_NOR_defconfig | 2 +- configs/P1010RDB-PB_SDCARD_defconfig | 3 ++- configs/P1010RDB-PB_SPIFLASH_defconfig | 3 ++- configs/P1020RDB-PC_36BIT_NAND_defconfig | 3 ++- configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 3 ++- configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 3 ++- configs/P1020RDB-PC_36BIT_defconfig | 2 +- configs/P1020RDB-PC_NAND_defconfig | 3 ++- configs/P1020RDB-PC_SDCARD_defconfig | 3 ++- configs/P1020RDB-PC_SPIFLASH_defconfig | 3 ++- configs/P1020RDB-PC_defconfig | 2 +- configs/P1020RDB-PD_NAND_defconfig | 3 ++- configs/P1020RDB-PD_SDCARD_defconfig | 3 ++- configs/P1020RDB-PD_SPIFLASH_defconfig | 3 ++- configs/P1020RDB-PD_defconfig | 2 +- configs/P2020RDB-PC_36BIT_NAND_defconfig | 3 ++- configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 3 ++- configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 3 ++- configs/P2020RDB-PC_36BIT_defconfig | 2 +- configs/P2020RDB-PC_NAND_defconfig | 3 ++- configs/P2020RDB-PC_SDCARD_defconfig | 3 ++- configs/P2020RDB-PC_SPIFLASH_defconfig | 3 ++- configs/P2020RDB-PC_defconfig | 2 +- configs/P2041RDB_NAND_defconfig | 2 +- configs/P2041RDB_SDCARD_defconfig | 2 +- configs/P2041RDB_SPIFLASH_defconfig | 2 +- configs/P2041RDB_defconfig | 2 +- configs/T1024RDB_NAND_defconfig | 3 ++- configs/T1024RDB_SDCARD_defconfig | 3 ++- configs/T1024RDB_SPIFLASH_defconfig | 3 ++- configs/T1042D4RDB_NAND_defconfig | 3 ++- configs/T1042D4RDB_SDCARD_defconfig | 3 ++- configs/T1042D4RDB_SPIFLASH_defconfig | 3 ++- configs/T2080QDS_NAND_defconfig | 3 ++- configs/T2080QDS_SDCARD_defconfig | 3 ++- configs/T2080QDS_SECURE_BOOT_defconfig | 3 +-- configs/T2080QDS_SPIFLASH_defconfig | 3 ++- configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 +- configs/T2080QDS_defconfig | 2 +- configs/T2080RDB_NAND_defconfig | 3 ++- configs/T2080RDB_SDCARD_defconfig | 3 ++- configs/T2080RDB_SPIFLASH_defconfig | 3 ++- configs/T2080RDB_revD_NAND_defconfig | 3 ++- configs/T2080RDB_revD_SDCARD_defconfig | 3 ++- configs/T2080RDB_revD_SPIFLASH_defconfig | 3 ++- configs/T4240RDB_SDCARD_defconfig | 3 ++- configs/ls1012a2g5rdb_tfa_defconfig | 3 +-- configs/ls1012afrdm_tfa_defconfig | 3 +-- configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig | 3 +-- configs/ls1012afrwy_tfa_defconfig | 3 +-- configs/ls1012aqds_tfa_SECURE_BOOT_defconfig | 3 +-- configs/ls1012aqds_tfa_defconfig | 3 +-- configs/ls1012ardb_tfa_SECURE_BOOT_defconfig | 3 +-- configs/ls1012ardb_tfa_defconfig | 3 +-- configs/ls1021aiot_qspi_defconfig | 2 +- configs/ls1021aiot_sdcard_defconfig | 3 ++- configs/ls1021aqds_nand_defconfig | 3 ++- configs/ls1021aqds_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021aqds_qspi_defconfig | 2 +- configs/ls1021aqds_sdcard_ifc_defconfig | 3 ++- configs/ls1021aqds_sdcard_qspi_defconfig | 3 ++- configs/ls1021atsn_qspi_defconfig | 2 +- configs/ls1021atsn_sdcard_defconfig | 3 ++- configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_qspi_defconfig | 2 +- configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 +- configs/ls1021atwr_sdcard_ifc_defconfig | 3 ++- configs/ls1021atwr_sdcard_qspi_defconfig | 3 ++- configs/ls1043aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1043aqds_tfa_defconfig | 2 +- configs/ls1046aqds_tfa_SECURE_BOOT_defconfig | 2 +- configs/ls1046aqds_tfa_defconfig | 2 +- configs/ls2080aqds_nand_defconfig | 3 ++- configs/ls2080aqds_qspi_defconfig | 2 +- configs/ls2080ardb_nand_defconfig | 3 ++- include/configs/MPC837XERDB.h | 7 ------- include/configs/MPC8548CDS.h | 3 --- include/configs/P1010RDB.h | 2 -- include/configs/P2041RDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - 98 files changed, 147 insertions(+), 120 deletions(-) (limited to 'include') diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index f61f4e1ea6e..7e53dcf8af5 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -39,12 +39,14 @@ /* The FMAN driver uses the PHYLIB infrastructure */ -#if CONFIG_IS_ENABLED(DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX) +#if !defined(CONFIG_CLK_MPC83XX) /* * TODO: Convert this to a clock driver exists that can give us the UART * clock here. */ -#define CFG_SYS_NS16550_CLK get_serial_clock() +#ifndef CFG_SYS_NS16550_CLK +#define CFG_SYS_NS16550_CLK get_bus_freq(0) +#endif #endif #endif /* _ASM_CONFIG_H_ */ diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 37fe5134449..e9e4fe28f9a 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -103,6 +103,5 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_ADDR_MAP=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 4bc3ebe3d52..182b395462f 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -102,5 +102,4 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 6fcc7271d97..65ebb6c341c 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -102,5 +102,4 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y -CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 2a22b8ac9d8..779c7dacb90 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -132,7 +132,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index f21d79e9d7d..4797994a072 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -96,7 +96,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index d2ac0b47f53..d3184c96753 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -117,7 +117,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 49130342f12..09fb2661e88 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -119,7 +119,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 56e7357e550..56779fdcdf4 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -131,7 +131,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index e1dc33496ca..e5ccb437398 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -95,7 +95,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 1beb5bb1c0f..86349579f76 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -116,7 +116,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index a9275e5d22d..ae79576c30d 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -118,7 +118,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index d180f3476e6..93d99322c54 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -135,7 +135,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 6237f630866..60e1cea9f8a 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -98,7 +98,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index 4237dc960ff..aefc2d5114e 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -119,7 +119,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 3b5f6beed86..46cf0be1f62 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -121,7 +121,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 25c51c2f0c2..5979bcef3fe 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -134,7 +134,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index dc181151385..819d54b1b35 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -97,7 +97,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 5324e7bfaea..27ed09418aa 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -118,7 +118,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 7bfa4ebeb84..dc164c0f436 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -120,7 +120,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index c8897148fad..03683f0e1e5 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -147,7 +147,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index d1e097e4d6c..ea809a95670 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -129,7 +129,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index ad7d5b637fb..eaa892cbd76 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -131,7 +131,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 0391d36a83c..eb8e4e5d0c9 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -109,7 +109,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 2d5c83c84d4..3949c4d94d7 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -146,7 +146,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 679c6fe7ccd..ea7e58f3eb0 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -128,7 +128,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 2ccb202eb3d..6d7d9734604 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -130,7 +130,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 6b7e2b5a163..e7740064d2b 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -108,7 +108,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 118f510e388..3361d0db63c 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -149,7 +149,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 6b6b35a08f6..4c71c73d2f0 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -131,7 +131,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index e30b54144a5..85a5c917594 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -133,7 +133,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index f262fa74394..a24aae42103 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -111,7 +111,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index ec80871222d..8dfe52ccff5 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -152,7 +152,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 0a658738100..d283e16eb0a 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -134,7 +134,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index ce95ab8fb54..2ef218cb040 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -136,7 +136,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 8c0ce04b775..8be6d91e5fd 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -114,7 +114,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 618e8272614..0f79bfee5e6 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -151,7 +151,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPL_NS16550_MIN_FUNCTIONS=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index eb9ee653f3b..d19646dbd27 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -133,7 +133,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index f73ddc34b2a..1c5522b3421 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -135,7 +135,8 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 492888672d0..95e004b4b44 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -113,7 +113,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_FSL=y CONFIG_DM_RTC=y CONFIG_RTC_PT7C4338=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 76b42cb6a15..4f4d2d75cab 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -103,7 +103,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0x100000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 008c87b7219..3106ee8b7ce 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -98,7 +98,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0xD2000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index c01fc869322..2ef35896c7d 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -100,7 +100,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0x110000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index fef52a61a51..1511fd7710c 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -95,7 +95,7 @@ CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000 CONFIG_MII=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 37dfdb4c7b3..d78d89ee07f 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -131,7 +131,8 @@ CONFIG_SYS_QE_FW_ADDR=0x200000 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y CONFIG_RTC_DS1337=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 72630f12195..5e2a8739242 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -125,7 +125,8 @@ CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y CONFIG_RTC_DS1337=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 8d48b399fb4..86fb67c66c8 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -128,7 +128,8 @@ CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y CONFIG_RTC_DS1337=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 01a85947d87..e03fcb63d19 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -131,7 +131,8 @@ CONFIG_SYS_QE_FW_ADDR=0x380000 CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y CONFIG_RTC_DS1337=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 26de5bf8b3a..f3f5c27dd0b 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -125,7 +125,8 @@ CONFIG_SYS_QE_FW_ADDR=0x124000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y CONFIG_RTC_DS1337=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 674246aaa7d..36d855a1ac9 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -128,7 +128,8 @@ CONFIG_SYS_QE_FW_ADDR=0x130000 CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y CONFIG_RTC_DS1337=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index 8d7ca9bbbb0..67e606548a6 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -141,7 +141,8 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 3ba3022d77e..b9fd336a35a 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -135,7 +135,8 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index c1230f7e645..a05d7008e4f 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -30,7 +30,6 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set -# CONFIG_SYS_MALLOC_F is not set CONFIG_MP=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_FIT=y @@ -110,7 +109,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 1cdcd0d52f9..3e66d47a257 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -138,7 +138,8 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index a0dbbd0c54d..841f72ed73d 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -97,7 +97,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index b52112fcba5..1eadcce3ba7 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -110,7 +110,7 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 63db57b809f..c3589b19a7e 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -137,7 +137,8 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 04cc53d9392..becc99eff8f 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -131,7 +131,8 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 26c479f026a..51766dac9c0 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -134,7 +134,8 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index 995dc7e9ef2..e7f2b02a410 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -139,7 +139,8 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index a66dba3c115..92defbe55b5 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -133,7 +133,8 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index 8a87a1b3a3f..f37117d3c9d 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -136,7 +136,8 @@ CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 8d03c7d9171..cf0b7418fac 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -120,7 +120,8 @@ CONFIG_MII=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_FSL=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_ESPI=y diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig index 69abd098982..25927901797 100644 --- a/configs/ls1012a2g5rdb_tfa_defconfig +++ b/configs/ls1012a2g5rdb_tfa_defconfig @@ -17,7 +17,6 @@ CONFIG_AHCI=y CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -56,7 +55,7 @@ CONFIG_SPI_FLASH_SPANSION=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_FSL_PFE=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrdm_tfa_defconfig b/configs/ls1012afrdm_tfa_defconfig index 883a007c73e..7fdcc88fc1d 100644 --- a/configs/ls1012afrdm_tfa_defconfig +++ b/configs/ls1012afrdm_tfa_defconfig @@ -17,7 +17,6 @@ CONFIG_PCI=y CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -55,7 +54,7 @@ CONFIG_E1000=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig index 0e1452eb78c..c497cdd92a2 100644 --- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig @@ -17,7 +17,6 @@ CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -57,7 +56,7 @@ CONFIG_E1000=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig index 0ffae31dae5..ca691aee737 100644 --- a/configs/ls1012afrwy_tfa_defconfig +++ b/configs/ls1012afrwy_tfa_defconfig @@ -18,7 +18,6 @@ CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -60,7 +59,7 @@ CONFIG_E1000=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig index 8dc27474200..38112b4ee08 100644 --- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig @@ -20,7 +20,6 @@ CONFIG_PCIE1=y CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -73,7 +72,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig index 26cddb55e3d..7b7b7c2becd 100644 --- a/configs/ls1012aqds_tfa_defconfig +++ b/configs/ls1012aqds_tfa_defconfig @@ -22,7 +22,6 @@ CONFIG_PCIE1=y CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -82,7 +81,7 @@ CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y CONFIG_RTC_PCF8563=y CONFIG_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig index c63ed627305..15458f8bafb 100644 --- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig @@ -18,7 +18,6 @@ CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -61,7 +60,7 @@ CONFIG_E1000=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig index 15f30ebd387..d77cbe9c6bf 100644 --- a/configs/ls1012ardb_tfa_defconfig +++ b/configs/ls1012ardb_tfa_defconfig @@ -19,7 +19,6 @@ CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff -# CONFIG_SYS_MALLOC_F is not set CONFIG_FIT_VERBOSE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=10 @@ -62,7 +61,7 @@ CONFIG_E1000=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_DM_RTC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig index c91d8c76b3e..12aa937f94b 100644 --- a/configs/ls1021aiot_qspi_defconfig +++ b/configs/ls1021aiot_qspi_defconfig @@ -67,7 +67,7 @@ CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index c2763b4048a..9993bfc4c9c 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -98,7 +98,8 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0xf40000 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index f56395a5451..51d5888c2a7 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -128,7 +128,8 @@ CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig index 29141097b75..ad4b58e517b 100644 --- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig @@ -95,7 +95,7 @@ CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig index ec27ad3c7a7..a874cd8e917 100644 --- a/configs/ls1021aqds_qspi_defconfig +++ b/configs/ls1021aqds_qspi_defconfig @@ -83,7 +83,7 @@ CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 2f9d10dd6b5..d14b544dd23 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -127,7 +127,8 @@ CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index 58d1a68f595..2ab3cf2d008 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -112,7 +112,8 @@ CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig index 1c7f25ebc6d..99c2af79289 100644 --- a/configs/ls1021atsn_qspi_defconfig +++ b/configs/ls1021atsn_qspi_defconfig @@ -68,7 +68,7 @@ CONFIG_SJA1105=y CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index ee3d9569699..6e95bd6ba6d 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -96,7 +96,8 @@ CONFIG_SJA1105=y CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 89c02fe1fd3..38bb415bb81 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -79,7 +79,7 @@ CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index a3fd4ac9baa..935079cf338 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -76,7 +76,7 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index eb648f1e783..2a1a704c270 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -112,7 +112,7 @@ CONFIG_TSEC_ENET=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_U_QE=y CONFIG_SYS_QE_FW_ADDR=0x940000 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index f6edabaa76e..194e78ad266 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -111,7 +111,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index 24d20a262bb..df969dbe485 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -105,7 +105,8 @@ CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig index 1cbab056fd4..f3642594ff0 100644 --- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig @@ -96,7 +96,7 @@ CONFIG_E1000=y CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig index f124098b7bf..4be027c1ac5 100644 --- a/configs/ls1043aqds_tfa_defconfig +++ b/configs/ls1043aqds_tfa_defconfig @@ -105,7 +105,7 @@ CONFIG_E1000=y CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig index f7b44f64dd4..b657248f918 100644 --- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig @@ -97,7 +97,7 @@ CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig index 2efc17b9e43..c0529fd848b 100644 --- a/configs/ls1046aqds_tfa_defconfig +++ b/configs/ls1046aqds_tfa_defconfig @@ -107,7 +107,7 @@ CONFIG_NVME_PCI=y CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_DSPI=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 0685960f218..f028eec4589 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -111,7 +111,8 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_RTC_DS3231=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 44a1459749f..ea115f52432 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -90,7 +90,7 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_ENABLE_32KHZ_OUTPUT=y CONFIG_RTC_DS3231=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index 66276ec678e..d04385f36cd 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -115,7 +115,8 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_RTC_DS3231=y CONFIG_CONS_INDEX=2 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index a5176d176dc..b22c720d07f 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -136,13 +136,6 @@ #define CFG_SYS_VSC7385_BASE 0xF0000000 -/* - * Serial Port - */ -#if !CONFIG_IS_ENABLED(DM_SERIAL) && !CONFIG_IS_ENABLED(DM_CLK) -#define CFG_SYS_NS16550_CLK get_bus_freq(0) -#endif - #define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 6f3e298a249..71e81e09ddb 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -217,9 +217,6 @@ #define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* Serial Port */ -#define CFG_SYS_NS16550_CLK get_bus_freq(0) - #define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 20fded56b77..0d312643bc8 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -309,8 +309,6 @@ extern unsigned long get_sdram_size(void); #endif /* Serial Port */ -#define CFG_SYS_NS16550_CLK get_bus_freq(0) - #define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 7cf6514f148..f88fb9cdb9a 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -148,7 +148,6 @@ * open - index 2 * shorted - index 1 */ -#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 2023d7497f6..e81937cc332 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -250,7 +250,6 @@ /* * Serial Port */ -#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2) #define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} #define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 23d8917b718..2d9d5b27511 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -302,7 +302,6 @@ * open - index 2 * shorted - index 1 */ -#define CFG_SYS_NS16550_CLK get_bus_freq(0) #define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -- cgit v1.3.1 From e15282f943b42647478ec158011656df7cf12ec2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 12 May 2025 17:58:39 +0200 Subject: image: Fix FIT image loadable section custom processing The original commit always generated linker list entries with the same entry variable name, because _function passed to ll_entry_declare() is not a variable and therefore was interpreted as fixed string. Change it to _type which is a variable and which does allow generation of multiple unique linker list entries, one for each U_BOOT_FIT_LOADABLE_HANDLER(). Fixes: d7be50921ed3 ("image: Add FIT image loadable section custom processing") Signed-off-by: Marek Vasut --- include/image.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/image.h b/include/image.h index 4620782c069..1e1bded690b 100644 --- a/include/image.h +++ b/include/image.h @@ -2134,7 +2134,7 @@ struct fit_loadable_tbl { * _handler is the handler function to call after this image type is loaded */ #define U_BOOT_FIT_LOADABLE_HANDLER(_type, _handler) \ - ll_entry_declare(struct fit_loadable_tbl, _function, fit_loadable) = { \ + ll_entry_declare(struct fit_loadable_tbl, _type, fit_loadable) = { \ .type = _type, \ .handler = _handler, \ } -- cgit v1.3.1 From a510bc2c9a310a6204b4587c8c2c2e0962380e31 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:06 -0600 Subject: include/ahci.h: Audit include list This file does not need but does directly need . Signed-off-by: Tom Rini --- include/ahci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/ahci.h b/include/ahci.h index eb05cc687f6..470cda006de 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -7,7 +7,7 @@ #ifndef _AHCI_H_ #define _AHCI_H_ -#include +#include #define AHCI_PCI_BAR 0x24 #define AHCI_MAX_SG 56 /* hardware max is 64K */ -- cgit v1.3.1 From 6a891bb78cdc0f920bcae700af26f192421f93cd Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:07 -0600 Subject: include/arm_ffa.h: Audit include list This file does not need but does directly need . Signed-off-by: Tom Rini --- include/arm_ffa.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/arm_ffa.h b/include/arm_ffa.h index db9b1be995e..2994d8ee3ae 100644 --- a/include/arm_ffa.h +++ b/include/arm_ffa.h @@ -9,7 +9,7 @@ #ifndef __ARM_FFA_H #define __ARM_FFA_H -#include +#include /* * This header is public. It can be used by clients to access -- cgit v1.3.1 From 377c75f8c5588126259ff82bd33eaa3090853cb8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:08 -0600 Subject: include/bios_emul.h: Audit include list This file does not need but does directly need . Furthermore, arch/x86/lib/bios.c was getting via so add it there. Signed-off-by: Tom Rini --- arch/x86/lib/bios.c | 1 + include/bios_emul.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index de4578666fb..77a8117d158 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/include/bios_emul.h b/include/bios_emul.h index a7e6d73972c..47a45296cc3 100644 --- a/include/bios_emul.h +++ b/include/bios_emul.h @@ -8,7 +8,7 @@ /* Include the register header directly here */ #include "../drivers/bios_emulator/include/x86emu/regs.h" -#include +#include /**************************************************************************** REMARKS: -- cgit v1.3.1 From 48703b2d6b7c87a523e794a711fe5c0d86f15093 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:09 -0600 Subject: include/bootflow.h: Audit include list This file does not need but does directly need . Signed-off-by: Tom Rini --- include/bootflow.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/bootflow.h b/include/bootflow.h index d408b8c85bd..5a9ac5ed3b3 100644 --- a/include/bootflow.h +++ b/include/bootflow.h @@ -11,7 +11,7 @@ #include #include #include -#include +#include struct bootstd_priv; struct expo; -- cgit v1.3.1 From 5bbc8b5c55102145ba06bee4cfa7276f293d9c31 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:10 -0600 Subject: include/bootstd.h: Audit include list This file does not need so remove it. Signed-off-by: Tom Rini --- include/bootstd.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/bootstd.h b/include/bootstd.h index 2bc464756dd..f2fb5f55faa 100644 --- a/include/bootstd.h +++ b/include/bootstd.h @@ -11,7 +11,6 @@ #include #include -#include #include struct udevice; -- cgit v1.3.1 From 5d14fca77af7f2d4d950e0656329b03b9f5a2525 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:11 -0600 Subject: include/cadence-nand.h: Audit include list This file does not need but does directly need . Signed-off-by: Tom Rini --- include/cadence-nand.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/cadence-nand.h b/include/cadence-nand.h index 27ed217b1ed..f08dce19cb9 100644 --- a/include/cadence-nand.h +++ b/include/cadence-nand.h @@ -12,7 +12,7 @@ #define _CADENCE_NAND_H_ #include #include -#include +#include #include /* -- cgit v1.3.1 From ef560b42ec1f5db103ca8be8c4532c55ff0151f3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:12 -0600 Subject: include/cbfs.h: Audit include list This file does not need but does directly need . Signed-off-by: Tom Rini --- include/cbfs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/cbfs.h b/include/cbfs.h index 2bc5de2297e..1244dbdba0d 100644 --- a/include/cbfs.h +++ b/include/cbfs.h @@ -6,8 +6,8 @@ #ifndef __CBFS_H #define __CBFS_H -#include #include +#include struct cbfs_priv; -- cgit v1.3.1 From cad8e2033332c1693d03fbdcb1c07f788974c2ec Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:13 -0600 Subject: include/compiler.h: Audit include list This file does not need so remove it. Signed-off-by: Tom Rini --- include/compiler.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/compiler.h b/include/compiler.h index ef7b2cb1f7e..f2e1e09c598 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -60,8 +60,6 @@ # define __BIG_ENDIAN BIG_ENDIAN #endif -#include - typedef uint8_t __u8; typedef uint16_t __u16; typedef uint32_t __u32; -- cgit v1.3.1 From 1585d92a05517f5f0278dccb8d0a03012960d790 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:14 -0600 Subject: include/dfu.h: Audit include list This file does not need a forward declaration of 'struct list_head' as it includes so remove it. Reviewed-by: Mattijs Korpershoek Signed-off-by: Tom Rini --- include/dfu.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/dfu.h b/include/dfu.h index 12f9dfcdfcd..80593a906fd 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -173,7 +173,6 @@ struct dfu_entity { unsigned int inited:1; }; -struct list_head; extern struct list_head dfu_list; #ifdef CONFIG_SET_DFU_ALT_INFO -- cgit v1.3.1 From ddf050a5d6e86fc2c8c4ea9bd47915ed340e412f Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:15 -0600 Subject: include/dw_hdmi.h: Audit include list This file does not need so remove it. Signed-off-by: Tom Rini --- include/dw_hdmi.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/dw_hdmi.h b/include/dw_hdmi.h index b73518207ef..fab5aafea19 100644 --- a/include/dw_hdmi.h +++ b/include/dw_hdmi.h @@ -9,8 +9,6 @@ #ifndef _DW_HDMI_H #define _DW_HDMI_H -#include - #define HDMI_EDID_BLOCK_SIZE 128 /* Identification Registers */ -- cgit v1.3.1 From 8f3c64a53535b6bcc7b63a6cf9531a6dfddff5f3 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:16 -0600 Subject: include/dwmmc.h: Audit include list This file does not need so remove it. Signed-off-by: Tom Rini --- include/dwmmc.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/dwmmc.h b/include/dwmmc.h index 6edb9e1a59c..87ca127cd6c 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -7,7 +7,6 @@ #ifndef __DWMMC_HW_H #define __DWMMC_HW_H -#include #include #include #include -- cgit v1.3.1 From 40d5f553316eba90a893a58c12c098da74dca335 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:17 -0600 Subject: include/efi_loader.h, include/efi_tcg2.h: Audit include list In include/efi_loader.h we do not directly need , , nor so remove them. In include/efi_tcg2.h we make use of but did not include it, so add it directly. Reviewed-by: Ilias Apalodimas Tested-by: Ilias Apalodimas Signed-off-by: Tom Rini --- include/efi_loader.h | 4 ---- include/efi_tcg2.h | 1 + 2 files changed, 1 insertion(+), 4 deletions(-) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index 84e8cfe320e..f3c85ae8d66 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -10,15 +10,11 @@ #include #include -#include -#include #include #include -#include #include #include #include -#include struct blk_desc; struct bootflow; diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h index 7ed88809913..34a3d4a0434 100644 --- a/include/efi_tcg2.h +++ b/include/efi_tcg2.h @@ -17,6 +17,7 @@ #define _EFI_TCG2_PROTOCOL_H_ #include +#include #include #include -- cgit v1.3.1 From 43d76dc7df600b10cbf70753750bf87de098b210 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:18 -0600 Subject: include/fat.h: Audit include list This file does not need so remove it. However the file common/spl/spl_fat.c does need it, so add it there. Signed-off-by: Tom Rini --- common/spl/spl_fat.c | 1 + include/fat.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c index f426a068ff9..8b7cafa7291 100644 --- a/common/spl/spl_fat.c +++ b/common/spl/spl_fat.c @@ -16,6 +16,7 @@ #include #include #include +#include static int fat_registered; diff --git a/include/fat.h b/include/fat.h index ca97880de12..bdf430f7067 100644 --- a/include/fat.h +++ b/include/fat.h @@ -11,7 +11,6 @@ #include #include -#include struct disk_partition; -- cgit v1.3.1 From d81b57a3cc881569d18014c0a8806e163066fd77 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:19 -0600 Subject: include/ide.h: Cleanup usage At this point in time, provides the IDE_BUS macro and the function prototype for ide_set_reset, which is used with IDE_RESET. The only files which should include this header are the ones that either use that macro or that function. Remove from and remove from places which do not need it. Signed-off-by: Tom Rini --- board/freescale/m5253demo/m5253demo.c | 1 + board/imgtec/malta/malta.c | 1 - cmd/ide.c | 1 - common/board_r.c | 1 - disk/part.c | 1 - disk/part_amiga.c | 1 - disk/part_dos.c | 1 - disk/part_efi.c | 1 - disk/part_mac.c | 1 - include/ide.h | 2 -- include/part.h | 1 - lib/efi_loader/efi_device_path.c | 1 + 12 files changed, 2 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c index 446a79e6723..50c5320b55c 100644 --- a/board/freescale/m5253demo/m5253demo.c +++ b/board/freescale/m5253demo/m5253demo.c @@ -93,6 +93,7 @@ int testdram(void) #ifdef CONFIG_IDE #include +#include void ide_set_reset(int idereset) { atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR; diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 4a72ab5ceca..0ffa964178f 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include diff --git a/cmd/ide.c b/cmd/ide.c index 036489fda97..ed30f946866 100644 --- a/cmd/ide.c +++ b/cmd/ide.c @@ -19,7 +19,6 @@ #include #include -#include #include #ifdef CONFIG_LED_STATUS diff --git a/common/board_r.c b/common/board_r.c index b90a4d9ff69..a1183f0811d 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include #include diff --git a/disk/part.c b/disk/part.c index 303178161c0..9cbd03686f5 100644 --- a/disk/part.c +++ b/disk/part.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/disk/part_amiga.c b/disk/part_amiga.c index 5b8ae5762d3..22bf99f1b88 100644 --- a/disk/part_amiga.c +++ b/disk/part_amiga.c @@ -6,7 +6,6 @@ */ #include #include -#include #include "part_amiga.h" #include #include diff --git a/disk/part_dos.c b/disk/part_dos.c index 96f748702fd..5c77225cef9 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/disk/part_efi.c b/disk/part_efi.c index 932d058c184..68ba1d11e7b 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/disk/part_mac.c b/disk/part_mac.c index 21c85942fd8..dd3ce0be832 100644 --- a/disk/part_mac.c +++ b/disk/part_mac.c @@ -15,7 +15,6 @@ #include #include #include -#include #include "part_mac.h" #include diff --git a/include/ide.h b/include/ide.h index 2c25e74ede0..550b3305621 100644 --- a/include/ide.h +++ b/include/ide.h @@ -7,8 +7,6 @@ #ifndef _IDE_H #define _IDE_H -#include - #define IDE_BUS(dev) (dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS)) /** diff --git a/include/part.h b/include/part.h index fcb3c13dea4..3fa2d8424b7 100644 --- a/include/part.h +++ b/include/part.h @@ -7,7 +7,6 @@ #define _PART_H #include -#include #include #include #include diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c index c9bf2726fe2..66a951a8c1b 100644 --- a/lib/efi_loader/efi_device_path.c +++ b/lib/efi_loader/efi_device_path.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include -- cgit v1.3.1 From 2cf46de9b6b8463033ba4f9243643d004dc9ea5a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:20 -0600 Subject: include/mmc.h: Audit include list This file does not need nor so remove them. This exposes however that a number of other files had been relying on this implicit include for so add that where needed. Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc85xx/fdt.c | 1 + board/emulation/common/qemu_dfu.c | 1 + board/toradex/verdin-am62/verdin-am62.c | 1 + drivers/mmc/mmc.c | 1 + drivers/mmc/snps_sdhci.c | 1 + include/mmc.h | 2 -- 6 files changed, 5 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index b2c0c517e7a..143b7c624d2 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include diff --git a/board/emulation/common/qemu_dfu.c b/board/emulation/common/qemu_dfu.c index 393fcaeb742..8a59f5ade13 100644 --- a/board/emulation/common/qemu_dfu.c +++ b/board/emulation/common/qemu_dfu.c @@ -7,6 +7,7 @@ #include #include #include +#include #define DFU_ALT_BUF_LEN SZ_1K diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c index 7b2eecbf659..eca2cc8bc7f 100644 --- a/board/toradex/verdin-am62/verdin-am62.c +++ b/board/toradex/verdin-am62/verdin-am62.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include "../common/tdx-cfg-block.h" diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index cdcf2e0c8fe..9421a846e45 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/mmc/snps_sdhci.c b/drivers/mmc/snps_sdhci.c index f5ede38c3c1..fe834ec2969 100644 --- a/drivers/mmc/snps_sdhci.c +++ b/drivers/mmc/snps_sdhci.c @@ -6,6 +6,7 @@ #include #include #include +#include #include /* DWCMSHC specific Mode Select value */ diff --git a/include/mmc.h b/include/mmc.h index eead666ae44..87f7ef131b6 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -11,8 +11,6 @@ #include #include -#include -#include #include #include #include -- cgit v1.3.1 From 2266595bf893edb07331ca8464738e0d4c82c129 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 21 May 2025 16:51:21 -0600 Subject: include/mtd.h: Cleanup usage There are only a few things found in today. Go through and audit the C files which include and remove it when not required. Then, add it to the files which had either missed it or had an indirect inclusion of it. Signed-off-by: Tom Rini --- arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c | 1 + board/bosch/guardian/board.c | 1 - board/dhelectronics/dh_stm32mp1/board.c | 1 - board/isee/igep00x0/igep00x0.c | 1 + board/xilinx/zynqmp/zynqmp.c | 1 + cmd/legacy-mtd-utils.c | 1 - cmd/mtdparts.c | 1 + drivers/fwu-mdata/raw_mtd.c | 1 + drivers/mtd/altera_qspi.c | 2 +- drivers/mtd/renesas_rpc_hf.c | 1 - include/fwu.h | 1 - lib/fwu_updates/fwu_v1.c | 1 + lib/fwu_updates/fwu_v2.c | 1 + 13 files changed, 8 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 5b027fad048..9acbc0689a9 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/board/bosch/guardian/board.c b/board/bosch/guardian/board.c index 33ba7a7751c..ebbae27c0f9 100644 --- a/board/bosch/guardian/board.c +++ b/board/bosch/guardian/board.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index d30171f1fbe..f7347bbb826 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -27,7 +27,6 @@ #include #include #include -#include #include #include #include diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index a35a7cd3b1f..c21b083b62a 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 735ef3cd1be..789b945d462 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include diff --git a/cmd/legacy-mtd-utils.c b/cmd/legacy-mtd-utils.c index 1a5271000bf..34a6da01947 100644 --- a/cmd/legacy-mtd-utils.c +++ b/cmd/legacy-mtd-utils.c @@ -4,7 +4,6 @@ #include #include #include -#include static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size, loff_t *maxsize, int devtype) diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c index a021b2d198d..571b79f091d 100644 --- a/cmd/mtdparts.c +++ b/cmd/mtdparts.c @@ -74,6 +74,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/fwu-mdata/raw_mtd.c b/drivers/fwu-mdata/raw_mtd.c index 78a709f766c..41c153038ab 100644 --- a/drivers/fwu-mdata/raw_mtd.c +++ b/drivers/fwu-mdata/raw_mtd.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c index e5c8df750b7..46174aab349 100644 --- a/drivers/mtd/altera_qspi.c +++ b/drivers/mtd/altera_qspi.c @@ -9,10 +9,10 @@ #include #include #include -#include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c index 50a6191d9c2..9390c9e9ab3 100644 --- a/drivers/mtd/renesas_rpc_hf.c +++ b/drivers/mtd/renesas_rpc_hf.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/include/fwu.h b/include/fwu.h index 6441de370c9..77e60167fc7 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -9,7 +9,6 @@ #include #include #include -#include #include #include diff --git a/lib/fwu_updates/fwu_v1.c b/lib/fwu_updates/fwu_v1.c index c311a8857a6..974abf216f6 100644 --- a/lib/fwu_updates/fwu_v1.c +++ b/lib/fwu_updates/fwu_v1.c @@ -3,6 +3,7 @@ * Copyright (c) 2024, Linaro Limited */ +#include #include #include diff --git a/lib/fwu_updates/fwu_v2.c b/lib/fwu_updates/fwu_v2.c index ce46904ff2e..159315b45b9 100644 --- a/lib/fwu_updates/fwu_v2.c +++ b/lib/fwu_updates/fwu_v2.c @@ -3,6 +3,7 @@ * Copyright (c) 2024, Linaro Limited */ +#include #include #include #include -- cgit v1.3.1 From 422222f5170ac399f0e5fd39290f8508ad777fcc Mon Sep 17 00:00:00 2001 From: Emanuele Ghidoli Date: Tue, 20 May 2025 11:09:17 +0200 Subject: linux/sizes.h: sync from kernel The kernel added new size definitions and substituted the boilerplate/reference to the license with a SPDX identifier. Drop a local SZ_8G definition in MediaTek MT7988 SoC board file. Signed-off-by: Emanuele Ghidoli Reviewed-by: Tom Rini Reviewed-by: Weijie Gao --- arch/arm/mach-mediatek/mt7988/init.c | 3 +-- include/linux/sizes.h | 28 ++++++++++++++++++++++++---- 2 files changed, 25 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-mediatek/mt7988/init.c b/arch/arm/mach-mediatek/mt7988/init.c index 2efc8c6a88f..8bdd3848d26 100644 --- a/arch/arm/mach-mediatek/mt7988/init.c +++ b/arch/arm/mach-mediatek/mt7988/init.c @@ -6,14 +6,13 @@ #include #include +#include #include #include #include DECLARE_GLOBAL_DATA_PTR; -#define SZ_8G _AC(0x200000000, ULL) - int dram_init(void) { int ret; diff --git a/include/linux/sizes.h b/include/linux/sizes.h index fbde0bc7e88..49039494076 100644 --- a/include/linux/sizes.h +++ b/include/linux/sizes.h @@ -1,9 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * include/linux/sizes.h - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */ #ifndef __LINUX_SIZES_H__ #define __LINUX_SIZES_H__ @@ -26,17 +23,25 @@ #define SZ_4K 0x00001000 #define SZ_8K 0x00002000 #define SZ_16K 0x00004000 +#define SZ_24K 0x00006000 #define SZ_32K 0x00008000 #define SZ_64K 0x00010000 #define SZ_128K 0x00020000 +#define SZ_192K 0x00030000 #define SZ_256K 0x00040000 +#define SZ_384K 0x00060000 #define SZ_512K 0x00080000 #define SZ_1M 0x00100000 #define SZ_2M 0x00200000 +#define SZ_3M 0x00300000 #define SZ_4M 0x00400000 +#define SZ_6M 0x00600000 #define SZ_8M 0x00800000 +#define SZ_12M 0x00c00000 #define SZ_16M 0x01000000 +#define SZ_18M 0x01200000 +#define SZ_24M 0x01800000 #define SZ_32M 0x02000000 #define SZ_64M 0x04000000 #define SZ_128M 0x08000000 @@ -47,5 +52,20 @@ #define SZ_2G 0x80000000 #define SZ_4G _AC(0x100000000, ULL) +#define SZ_8G _AC(0x200000000, ULL) +#define SZ_16G _AC(0x400000000, ULL) +#define SZ_32G _AC(0x800000000, ULL) +#define SZ_64G _AC(0x1000000000, ULL) +#define SZ_128G _AC(0x2000000000, ULL) +#define SZ_256G _AC(0x4000000000, ULL) +#define SZ_512G _AC(0x8000000000, ULL) + +#define SZ_1T _AC(0x10000000000, ULL) +#define SZ_2T _AC(0x20000000000, ULL) +#define SZ_4T _AC(0x40000000000, ULL) +#define SZ_8T _AC(0x80000000000, ULL) +#define SZ_16T _AC(0x100000000000, ULL) +#define SZ_32T _AC(0x200000000000, ULL) +#define SZ_64T _AC(0x400000000000, ULL) #endif /* __LINUX_SIZES_H__ */ -- cgit v1.3.1 From b8c43968b801c568b66b1d2985e8542275d9d49a Mon Sep 17 00:00:00 2001 From: Parth Pancholi Date: Mon, 19 May 2025 16:47:45 +0100 Subject: board: toradex: add verdin am62p support This adds initial support for the Toradex Verdin AM62P module. The module consists of an TI AM62P family SoC, a TPS65219 PMIC, a Gigabit Ethernet PHY, up to 8GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC, an I2C EEPROM, an RX8130 RTC, plus an optional Bluetooth/Wi-Fi module. These specific changes adds support for Toradex Verdin AM62P Quad 2GB WB IT module. Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kit Signed-off-by: Parth Pancholi Signed-off-by: Vitor Soares --- arch/arm/dts/Makefile | 4 +- arch/arm/dts/k3-am62p-verdin-dev.dtsi | 243 ++ arch/arm/dts/k3-am62p-verdin-wifi.dtsi | 31 + arch/arm/dts/k3-am62p-verdin.dtsi | 1399 ++++++++++ arch/arm/dts/k3-am62p5-verdin-lpddr4-1600.dtsi | 2801 ++++++++++++++++++++ arch/arm/dts/k3-am62p5-verdin-r5.dts | 84 + arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi | 325 +++ arch/arm/dts/k3-am62p5-verdin-wifi-dev-u-boot.dtsi | 167 ++ arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts | 22 + arch/arm/mach-k3/am62px/Kconfig | 1 + board/toradex/verdin-am62p/Kconfig | 83 + board/toradex/verdin-am62p/MAINTAINERS | 17 + board/toradex/verdin-am62p/Makefile | 6 + board/toradex/verdin-am62p/board-cfg.yaml | 37 + board/toradex/verdin-am62p/pm-cfg.yaml | 12 + board/toradex/verdin-am62p/rm-cfg.yaml | 1083 ++++++++ board/toradex/verdin-am62p/sec-cfg.yaml | 378 +++ board/toradex/verdin-am62p/tifs-rm-cfg.yaml | 927 +++++++ board/toradex/verdin-am62p/verdin-am62p.c | 151 ++ board/toradex/verdin-am62p/verdin-am62p.env | 41 + configs/verdin-am62p_a53_defconfig | 199 ++ configs/verdin-am62p_r5_defconfig | 117 + doc/board/ti/k3.rst | 1 + doc/board/toradex/index.rst | 1 + doc/board/toradex/verdin-am62p.rst | 196 ++ include/configs/verdin-am62p.h | 15 + 26 files changed, 8340 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/k3-am62p-verdin-dev.dtsi create mode 100644 arch/arm/dts/k3-am62p-verdin-wifi.dtsi create mode 100644 arch/arm/dts/k3-am62p-verdin.dtsi create mode 100644 arch/arm/dts/k3-am62p5-verdin-lpddr4-1600.dtsi create mode 100644 arch/arm/dts/k3-am62p5-verdin-r5.dts create mode 100644 arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi create mode 100644 arch/arm/dts/k3-am62p5-verdin-wifi-dev-u-boot.dtsi create mode 100644 arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts create mode 100644 board/toradex/verdin-am62p/Kconfig create mode 100644 board/toradex/verdin-am62p/MAINTAINERS create mode 100644 board/toradex/verdin-am62p/Makefile create mode 100644 board/toradex/verdin-am62p/board-cfg.yaml create mode 100644 board/toradex/verdin-am62p/pm-cfg.yaml create mode 100644 board/toradex/verdin-am62p/rm-cfg.yaml create mode 100644 board/toradex/verdin-am62p/sec-cfg.yaml create mode 100644 board/toradex/verdin-am62p/tifs-rm-cfg.yaml create mode 100644 board/toradex/verdin-am62p/verdin-am62p.c create mode 100644 board/toradex/verdin-am62p/verdin-am62p.env create mode 100644 configs/verdin-am62p_a53_defconfig create mode 100644 configs/verdin-am62p_r5_defconfig create mode 100644 doc/board/toradex/verdin-am62p.rst create mode 100644 include/configs/verdin-am62p.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 976dbda48c3..10404ce076e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1111,7 +1111,9 @@ dtb-$(CONFIG_SOC_K3_AM62A7) += \ k3-am62a7-r5-sk.dtb \ k3-am62a7-r5-phycore-som-2gb.dtb -dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb +dtb-$(CONFIG_SOC_K3_AM62P5) += k3-am62p5-r5-sk.dtb \ + k3-am62p5-verdin-r5.dtb \ + k3-am62p5-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ diff --git a/arch/arm/dts/k3-am62p-verdin-dev.dtsi b/arch/arm/dts/k3-am62p-verdin-dev.dtsi new file mode 100644 index 00000000000..4cf38226077 --- /dev/null +++ b/arch/arm/dts/k3-am62p-verdin-dev.dtsi @@ -0,0 +1,243 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * Common dtsi for Verdin AM62P SoM on Development carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/ { + aliases { + eeprom1 = &carrier_eeprom; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "verdin-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&nau8822_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + }; + }; +}; + +/* Verdin ETHs */ +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>, <&pinctrl_rgmii2>; + status = "okay"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + status = "okay"; + + carrier_eth_phy: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth2_rgmii_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <42 IRQ_TYPE_EDGE_FALLING>; + micrel,led-mode = <0>; + }; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + status = "okay"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + phy-handle = <&carrier_eth_phy>; + phy-mode = "rgmii-rxid"; + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&epwm0 { + status = "okay"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm2 { + status = "okay"; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_1_reset>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>, + <&pinctrl_gpio_8>; +}; + +/* Verdin I2C_1 */ +&main_i2c0 { + status = "okay"; + + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s1_mclk>; + #sound-dai-cells = <0>; + }; + + carrier_gpio_expander: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c1 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + status = "okay"; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + status = "okay"; +}; + +/* Verdin UART_1, connector X50 through RS485 transceiver */ +&main_uart1 { + rs485-rx-during-tx; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + status = "okay"; +}; + +&mcu_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&mcu_mcan0 { + status = "okay"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbss0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbss1 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +/* Verdin CTRL_WAKE1_MICO# */ +&verdin_gpio_keys { + status = "okay"; +}; + +/* Verdin PCIE_1_RESET# */ +&verdin_pcie_1_reset_hog { + status = "okay"; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/k3-am62p-verdin-wifi.dtsi b/arch/arm/dts/k3-am62p-verdin-wifi.dtsi new file mode 100644 index 00000000000..04d3124b5e0 --- /dev/null +++ b/arch/arm/dts/k3-am62p-verdin-wifi.dtsi @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * Common dtsi for Verdin AM62P SoM WB variant + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + */ + +/* On-module Bluetooth */ +&main_uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "nxp,88w8987-bt"; + fw-init-baudrate = <3000000>; + }; +}; + +/* On-module Wi-Fi */ +&sdhci2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci2>; + keep-power-in-suspend; + non-removable; + ti,fails-without-test-cd; + status = "okay"; +}; diff --git a/arch/arm/dts/k3-am62p-verdin.dtsi b/arch/arm/dts/k3-am62p-verdin.dtsi new file mode 100644 index 00000000000..b78b2ac76f3 --- /dev/null +++ b/arch/arm/dts/k3-am62p-verdin.dtsi @@ -0,0 +1,1399 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * Common dtsi for Verdin AM62P SoM + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + */ + +#include +#include +#include +#include +#include + +/ { + aliases { + can0 = &main_mcan0; + can1 = &mcu_mcan0; + eeprom0 = &som_eeprom; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; + i2c0 = &wkup_i2c0; + i2c1 = &main_i2c0; + i2c2 = &main_i2c1; + i2c3 = &mcu_i2c0; + i2c4 = &main_i2c3; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + rtc0 = &som_rtc_i2c; + rtc1 = &wkup_rtc0; + serial0 = &main_uart1; + serial1 = &wkup_uart0; + serial2 = &main_uart0; + serial3 = &mcu_uart0; + serial4 = &main_uart6; + usb0 = &usb0; + usb1 = &usb1; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_id>; + id-gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + label = "USB_1"; + self-powered; + vbus-supply = <®_usb0_vbus>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb0_ep>; + }; + }; + }; + + verdin_gpio_keys: gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + status = "disabled"; + + key-wakeup { + debounce-interval = <10>; + /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ + gpios = <&main_gpio0 1 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + memory@80000000 { + /* 2G RAM */ + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; + device_type = "memory"; + }; + + opp-table { + /* Add 1.4GHz OPP. Requires VDD_CORE to be at 0.85V */ + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-supported-hw = <0x01 0x0004>; + clock-latency-ns = <6000000>; + }; + }; + + reg_force_sleep_moci: regulator-force-sleep-moci { + compatible = "regulator-fixed"; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <&som_gpio_expander 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + regulator-name = "CTRL_SLEEP_MOCI#"; + }; + + /* Verdin SD_1 Power Supply */ + reg_sd1_vmmc: regulator-sdhci1-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_pwr_en>; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpios = <&main_gpio0 47 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SD"; + startup-delay-us = <2000>; + }; + + reg_sd1_vqmmc: regulator-sdhci1-vqmmc { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd_vsel>; + /* PMIC_VSEL_SD */ + gpios = <&main_gpio0 21 GPIO_ACTIVE_HIGH>; + regulator-name = "LDO1-VSEL-SD (PMIC)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x0>, + <3300000 0x1>; + vin-supply = <®_sd_3v3_1v8>; + }; + + reg_usb0_vbus: regulator-usb0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0_en>; + /* Verdin USB_1_EN (SODIMM 155) */ + gpios = <&main_gpio1 50 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_1_EN"; + }; + + /* Module Power Supply */ + reg_vsodimm: regulator-vsodimm { + compatible = "regulator-fixed"; + regulator-name = "+V_SODIMM"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + secure_tfa_ddr: tfa@9e780000 { + reg = <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible = "shared-dma-pool"; + reg = <0x00 0x9c900000 0x00 0x01e00000>; + no-map; + }; + }; +}; + +&main_pmx0 { + /* Verdin PWM_3_DSI */ + pinctrl_epwm0_b: main-epwm0b-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 2) /* (E20) SPI0_CS1.EHRPWM0_B */ /* SODIMM 19 */ + >; + }; + + /* Verdin PWM_2 */ + pinctrl_epwm2_a: main-epwm2a-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0124, PIN_OUTPUT, 4) /* (J25) MMC2_SDCD.EHRPWM2_A */ /* SODIMM 16 */ + >; + }; + + /* Verdin PWM_1 */ + pinctrl_epwm2_b: main-epwm2b-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0128, PIN_OUTPUT, 4) /* (K25) MMC2_SDWP.EHRPWM2_B */ /* SODIMM 15 */ + >; + }; + + /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_clk_gpio: main-gpio0-0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0000, PIN_INPUT, 7) /* (P23) OSPI0_CLK.GPIO0_0 */ /* SODIMM 52 */ + >; + }; + + /* Verdin CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: main-gpio0-1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0004, PIN_INPUT, 7) /* (N23) OSPI0_LBCLKO.GPIO0_1 */ /* SODIMM 252 */ + >; + }; + + /* Verdin QSPI_1_DQS as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_dqs_gpio: main-gpio0-2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0008, PIN_INPUT, 7) /* (P22) OSPI0_DQS.GPIO0_2 */ /* SODIMM 66 */ + >; + }; + + /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io0_gpio: main-gpio0-3-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x000c, PIN_INPUT, 7) /* (L25) OSPI0_D0.GPIO0_3 */ /* SODIMM 56 */ + >; + }; + + /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io1_gpio: main-gpio0-4-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0010, PIN_INPUT, 7) /* (N24) OSPI0_D1.GPIO0_4 */ /* SODIMM 58 */ + >; + }; + + /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io2_gpio: main-gpio0-5-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0014, PIN_INPUT, 7) /* (N25) OSPI0_D2.GPIO0_5 */ /* SODIMM 60 */ + >; + }; + + /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_io3_gpio: main-gpio0-6-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0018, PIN_INPUT, 7) /* (M24) OSPI0_D3.GPIO0_6 */ /* SODIMM 62 */ + >; + }; + + /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs_gpio: main-gpio0-11-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x002c, PIN_INPUT, 7) /* (M25) OSPI0_CSn0.GPIO0_11 */ /* SODIMM 54 */ + >; + }; + + /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */ + pinctrl_qspi1_cs2_gpio: main-gpio0-12-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0030, PIN_INPUT, 7) /* (L24) OSPI0_CSn1.GPIO0_12 */ /* SODIMM 64 */ + >; + }; + + /* Verdin MSP_37 as GPIO */ + pinctrl_msp37_gpio: main-gpio0-13-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0034, PIN_INPUT, 7) /* (L22) OSPI0_CSn2.GPIO0_13 */ /* SODIMM 174 - WiFi_W_WKUP_HOST# */ + >; + }; + + /* Verdin PCIE_1_RESET# */ + pinctrl_pcie_1_reset: main-gpio0-14-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0038, PIN_INPUT, 7) /* (L23) OSPI0_CSn3.GPIO0_14 */ /* SODIMM 244 */ + >; + }; + + pinctrl_sd_vsel: main-gpio0-21-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0054, PIN_INPUT, 7) /* (V24) GPMC0_AD6.GPIO0_21 */ /* PMIC_SD_VSEL */ + >; + }; + + pinctrl_tpm_extint: main-gpio0-25-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0064, PIN_INPUT, 7) /* (AA25) GPMC0_AD10.GPIO0_25 */ /* TPM_EXTINT# */ + >; + }; + + pinctrl_wifi_wkup_bt: main-gpio0-29-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0074, PIN_INPUT, 7) /* (AB24) GPMC0_AD14.GPIO0_29 */ /* WiFi_WKUP_BT# */ + >; + }; + + pinctrl_wifi_wkup_wlan: main-gpio0-30-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0078, PIN_INPUT, 7) /* (AC24) GPMC0_AD15.GPIO0_30 */ /* WiFi_WKUP_WLAN# */ + >; + }; + + /* Verdin USB_1_ID */ + pinctrl_usb0_id: main-gpio0-31-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x007c, PIN_INPUT, 7) /* (Y25) GPMC0_CLK.GPIO0_31 */ /* SODIMM 161 */ + >; + }; + + /* Verdin USB_1_OC# */ + pinctrl_usb1_oc: main-gpio0-32-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0084, PIN_INPUT, 7) /* (R25) GPMC0_ADVn_ALE.GPIO0_32 */ /* SODIMM 157 */ + >; + }; + + /* Verdin I2S_2_D_IN as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_d_in_gpio: main-gpio0-33-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0088, PIN_INPUT, 7) /* (R24) GPMC0_OEn_REn.GPIO0_33 */ /* SODIMM 48 */ + >; + }; + + /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_d_out_gpio: main-gpio0-34-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x008c, PIN_INPUT, 7) /* (T25) GPMC0_WEn.GPIO0_34 */ /* SODIMM 46 */ + >; + }; + + /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_bclk_gpio: main-gpio0-35-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0090, PIN_INPUT, 7) /* (U24) GPMC0_BE0n_CLE.GPIO0_35 */ /* SODIMM 42 */ + >; + }; + + pinctrl_eth_int: main-gpio0-36-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0094, PIN_INPUT, 7) /* (T24) GPMC0_BE1n.GPIO0_36 */ /* ETH_INT# */ + >; + }; + + /* Verdin I2S_2_SYNC as GPIO (conflict with Verdin I2S_2 interface) */ + pinctrl_i2s_2_sync_gpio: main-gpio0-37-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0098, PIN_INPUT, 7) /* (AA24) GPMC0_WAIT0.GPIO0_37 */ /* SODIMM 44 */ + >; + }; + + /* Verdin DSI_1_INT# */ + pinctrl_dsi1_int: main-gpio0-38-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x009c, PIN_INPUT, 7) /* (AD24) GPMC0_WAIT1.GPIO0_38 */ /* SODIMM 17 */ + >; + }; + + /* Verdin DSI_1_BLK_EN# */ + pinctrl_dsi1_bkl_en: main-gpio0-39-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00a0, PIN_INPUT, 7) /* (P24) GPMC0_WPn.GPIO0_39 */ /* SODIMM 21 */ + >; + }; + + /* Verdin USB_2_OC# */ + pinctrl_usb2_oc: main-gpio0-41-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00a8, PIN_INPUT, 7) /* (T23) GPMC0_CSn0.GPIO0_41 */ /* SODIMM 187 */ + >; + }; + + /* Verdin ETH_2_RGMII_INT# */ + pinctrl_eth2_rgmii_int: main-gpio0-42-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00ac, PIN_INPUT, 7) /* (U23) GPMC0_CSn1.GPIO0_42 */ /* SODIMM 189 */ + >; + }; + + /* Verdin SD_1_PWR_EN */ + pinctrl_sd1_pwr_en: main-gpio0-47-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00c0, PIN_INPUT, 7) /* (AA23) VOUT0_DATA2.GPIO0_47 */ /* SODIMM 76 */ + >; + }; + + /* Verdin GPIO_5 */ + pinctrl_gpio_5: main-gpio0-49-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00c8, PIN_INPUT, 7) /* (AB23) VOUT0_DATA4.GPIO0_49 */ /* SODIMM 216 */ + >; + }; + + /* Verdin GPIO_6 */ + pinctrl_gpio_6: main-gpio0-50-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00cc, PIN_INPUT, 7) /* (AD23) VOUT0_DATA5.GPIO0_50 */ /* SODIMM 218 */ + >; + }; + + /* Verdin GPIO_7 */ + pinctrl_gpio_7: main-gpio0-51-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00d0, PIN_INPUT, 7) /* (AC23) VOUT0_DATA6.GPIO0_51 */ /* SODIMM 220 */ + >; + }; + + /* Verdin GPIO_8 */ + pinctrl_gpio_8: main-gpio0-52-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00d4, PIN_INPUT, 7) /* (AE23) VOUT0_DATA7.GPIO0_52 */ /* SODIMM 222 */ + >; + }; + + /* Verdin MSP_36 as GPIO */ + pinctrl_msp36_gpio: main-gpio0-57-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00e8, PIN_INPUT, 7) /* (AD21) VOUT0_DATA12.GPIO0_57 */ /* SODIMM 172 - WiFi_BT_WKUP_HOST# */ + >; + }; + + pinctrl_wifi_sd_int: main-gpio0-59-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00f0, PIN_INPUT, 7) /* (AA20) VOUT0_DATA14.GPIO0_59 */ /* WIFI_SD_INT */ + >; + }; + + pinctrl_wifi_spi_cs: main-gpio0-60-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00f4, PIN_INPUT, 7) /* (Y20) VOUT0_DATA15.GPIO0_60 */ /* WIFI_SPI_CS# */ + >; + }; + + /* Verdin PWM_3_DSI as GPIO */ + pinctrl_pwm3_dsi_gpio: main-gpio1-16-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01b8, PIN_OUTPUT, 7) /* (E20) SPI0_CS1.GPIO1_16 */ /* SODIMM 19 */ + >; + }; + + /* Verdin SD_1_CD# */ + pinctrl_sd1_cd: main-gpio1-48-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0240, PIN_INPUT, 7) /* (D23) MMC1_SDCD.GPIO1_48 */ /* SODIMM 84 */ + >; + }; + + /* Verdin MSP_29 as GPIO */ + pinctl_msp29_gpio: main-gpio1-49-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0244, PIN_INPUT, 7) /* (D24) MMC1_SDWP.GPIO1_49 */ /* SODIMM 154 */ + >; + }; + + /* Verdin USB_1_EN */ + pinctrl_usb0_en: main-gpio1-50-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0254, PIN_INPUT, 7) /* (G22) USB0_DRVVBUS.GPIO1_50 */ /* SODIMM 155 */ + >; + }; + + /* Verdin I2C_1 */ + pinctrl_main_i2c0: main-i2c0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B25) I2C0_SCL */ /* SODIMM 14 */ + AM62PX_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A24) I2C0_SDA */ /* SODIMM 12 */ + >; + }; + + /* Verdin I2C_2_DSI */ + pinctrl_main_i2c1: main-i2c1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (C24) I2C1_SCL */ /* SODIMM 55 */ + AM62PX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B24) I2C1_SDA */ /* SODIMM 53 */ + >; + }; + + /* Verdin I2C_4_CSI */ + pinctrl_main_i2c3: main-i2c3-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A23) UART0_CTSn.I2C3_SCL */ /* SODIMM 95 */ + AM62PX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (C22) UART0_RTSn.I2C3_SDA */ /* SODIMM 93 */ + >; + }; + + /* Verdin CAN_1 */ + pinctrl_main_mcan0: main-mcan0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01dc, PIN_INPUT, 0) /* (F20) MCAN0_RX */ /* SODIMM 22 */ + AM62PX_IOPAD(0x01d8, PIN_OUTPUT, 0) /* (B23) MCAN0_TX */ /* SODIMM 20 */ + >; + }; + + /* Verdin MSP_3/MSP_8 as CAN */ + pinctrl_main_mcan1: main-mcan1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00b4, PIN_INPUT, 5) /* (U25) GPMC0_CSn3.MCAN1_RX */ /* SODIMM 92 */ + AM62PX_IOPAD(0x00b0, PIN_OUTPUT, 5) /* (T22) GPMC0_CSn2.MCAN1_TX */ /* SODIMM 104 */ + >; + }; + + /* Verdin SD_1 */ + pinctrl_sdhci1: main-mmc1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x023c, PIN_INPUT, 0) /* (H20) MMC1_CMD */ /* SODIMM 74 */ + AM62PX_IOPAD(0x0234, PIN_OUTPUT, 0) /* (J24) MMC1_CLK */ /* SODIMM 78 */ + AM62PX_IOPAD(0x0230, PIN_INPUT, 0) /* (H21) MMC1_DAT0 */ /* SODIMM 80 */ + AM62PX_IOPAD(0x022c, PIN_INPUT, 0) /* (H23) MMC1_DAT1 */ /* SODIMM 82 */ + AM62PX_IOPAD(0x0228, PIN_INPUT, 0) /* (H22) MMC1_DAT2 */ /* SODIMM 70 */ + AM62PX_IOPAD(0x0224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */ /* SODIMM 72 */ + >; + }; + + /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */ + pinctrl_sdhci2: main-mmc2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0120, PIN_INPUT, 0) /* (K24) MMC2_CMD */ /* SODIMM 160, WiFi_SDIO_CMD */ + AM62PX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (K21) MMC2_CLK */ /* SODIMM 156, WiFi_SDIO_CLK */ + AM62PX_IOPAD(0x011C, PIN_INPUT, 0) /* () MMC2_CLKLB */ + AM62PX_IOPAD(0x0114, PIN_INPUT, 0) /* (K23) MMC2_DAT0 */ /* SODIMM 162, WiFi_SDIO_DATA0 */ + AM62PX_IOPAD(0x0110, PIN_INPUT, 0) /* (K22) MMC2_DAT1 */ /* SODIMM 164, WiFi_SDIO_DATA1 */ + AM62PX_IOPAD(0x010c, PIN_INPUT, 0) /* (L20) MMC2_DAT2 */ /* SODIMM 166, WiFi_SDIO_DATA2 */ + AM62PX_IOPAD(0x0108, PIN_INPUT, 0) /* (L21) MMC2_DAT3 */ /* SODIMM 168, WiFi_SDIO_DATA3 */ + >; + }; + + /* Verdin QSPI_1 */ + pinctrl_ospi0: main-ospi0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0000, PIN_OUTPUT, 0) /* (P23) OSPI0_CLK */ /* SODIMM 52 */ + AM62PX_IOPAD(0x002c, PIN_OUTPUT, 0) /* (M25) OSPI0_CSn0 */ /* SODIMM 54 */ + AM62PX_IOPAD(0x0030, PIN_OUTPUT, 0) /* (L24) OSPI0_CSn1 */ /* SODIMM 64 */ + AM62PX_IOPAD(0x000c, PIN_INPUT, 0) /* (L25) OSPI0_D0 */ /* SODIMM 56 */ + AM62PX_IOPAD(0x0010, PIN_INPUT, 0) /* (N24) OSPI0_D1 */ /* SODIMM 58 */ + AM62PX_IOPAD(0x0014, PIN_INPUT, 0) /* (N25) OSPI0_D2 */ /* SODIMM 60 */ + AM62PX_IOPAD(0x0018, PIN_INPUT, 0) /* (M24) OSPI0_D3 */ /* SODIMM 62 */ + AM62PX_IOPAD(0x0008, PIN_INPUT, 0) /* (P22) OSPI0_DQS */ /* SODIMM 66 */ + >; + }; + + /* Verdin ETH_1 RGMII (On-module PHY) */ + pinctrl_rgmii1: main-rgmii1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x014c, PIN_INPUT, 0) /* (B15) RGMII1_RD0 */ /* RGMII_RXD0 */ + AM62PX_IOPAD(0x0150, PIN_INPUT, 0) /* (B16) RGMII1_RD1 */ /* RGMII_RXD1 */ + AM62PX_IOPAD(0x0154, PIN_INPUT, 0) /* (A14) RGMII1_RD2 */ /* RGMII_RXD2 */ + AM62PX_IOPAD(0x0158, PIN_INPUT, 0) /* (B14) RGMII1_RD3 */ /* RGMII_RXD3 */ + AM62PX_IOPAD(0x0148, PIN_INPUT, 0) /* (A16) RGMII1_RXC */ /* RGMII_RXC */ + AM62PX_IOPAD(0x0144, PIN_INPUT, 0) /* (A15) RGMII1_RX_CTL */ /* RGMII_RX_CTL */ + AM62PX_IOPAD(0x0134, PIN_INPUT, 0) /* (A18) RGMII1_TD0 */ /* RGMII_TXD0 */ + AM62PX_IOPAD(0x0138, PIN_INPUT, 0) /* (C17) RGMII1_TD1 */ /* RGMII_TXD1 */ + AM62PX_IOPAD(0x013c, PIN_INPUT, 0) /* (A17) RGMII1_TD2 */ /* RGMII_TXD2 */ + AM62PX_IOPAD(0x0140, PIN_INPUT, 0) /* (C16) RGMII1_TD3 */ /* RGMII_TXD3 */ + AM62PX_IOPAD(0x0130, PIN_INPUT, 0) /* (B17) RGMII1_TXC */ /* RGMII_TXC */ + AM62PX_IOPAD(0x012c, PIN_INPUT, 0) /* (B18) RGMII1_TX_CTL */ /* RGMII_TX_CTL */ + >; + }; + + /* Verdin ETH_2 RGMII */ + pinctrl_rgmii2: main-rgmii2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0184, PIN_INPUT, 0) /* (E19) RGMII2_RD0 */ /* SODIMM 201 */ + AM62PX_IOPAD(0x0188, PIN_INPUT, 0) /* (E16) RGMII2_RD1 */ /* SODIMM 203 */ + AM62PX_IOPAD(0x018c, PIN_INPUT, 0) /* (E17) RGMII2_RD2 */ /* SODIMM 205 */ + AM62PX_IOPAD(0x0190, PIN_INPUT, 0) /* (C19) RGMII2_RD3 */ /* SODIMM 207 */ + AM62PX_IOPAD(0x0180, PIN_INPUT, 0) /* (D19) RGMII2_RXC */ /* SODIMM 197 */ + AM62PX_IOPAD(0x017c, PIN_INPUT, 0) /* (F19) RGMII2_RX_CTL */ /* SODIMM 199 */ + AM62PX_IOPAD(0x016c, PIN_INPUT, 0) /* (B19) RGMII2_TD0 */ /* SODIMM 221 */ + AM62PX_IOPAD(0x0170, PIN_INPUT, 0) /* (A21) RGMII2_TD1 */ /* SODIMM 219 */ + AM62PX_IOPAD(0x0174, PIN_INPUT, 0) /* (D17) RGMII2_TD2 */ /* SODIMM 217 */ + AM62PX_IOPAD(0x0178, PIN_INPUT, 0) /* (A19) RGMII2_TD3 */ /* SODIMM 215 */ + AM62PX_IOPAD(0x0168, PIN_INPUT, 0) /* (D16) RGMII2_TXC */ /* SODIMM 213 */ + AM62PX_IOPAD(0x0164, PIN_INPUT, 0) /* (A20) RGMII2_TX_CTL */ /* SODIMM 211 */ + >; + }; + + /* TPM SPI, Optional Module Specific SPI */ + pinctrl_main_spi0: main-spi0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01bc, PIN_INPUT, 0) /* (B21) SPI0_CLK */ /* TPM_SPI_CLK - SODIMM 148 */ + AM62PX_IOPAD(0x01c0, PIN_OUTPUT, 0) /* (B20) SPI0_D0 */ /* TPM_SPI_MOSI - SODIMM 150 */ + AM62PX_IOPAD(0x01c4, PIN_INPUT, 0) /* (C21) SPI0_D1 */ /* TPM_SPI_MISO - SODIMM 152 */ + AM62PX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D20) SPI0_CS0 */ /* TPM_SPI_CS */ + >; + }; + + /* Verdin SPI_1 */ + pinctrl_main_spi1: main-spi1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0020, PIN_INPUT, 1) /* (N22) OSPI0_D5.SPI1_CLK */ /* SODIMM 196 */ + AM62PX_IOPAD(0x0024, PIN_OUTPUT, 1) /* (P21) OSPI0_D6.SPI1_D0 */ /* SODIMM 200 */ + AM62PX_IOPAD(0x0028, PIN_INPUT, 1) /* (N20) OSPI0_D7.SPI1_D1 */ /* SODIMM 198 */ + >; + }; + + /* Verdin SPI_1_CS */ + pinctrl_main_spi1_cs0: main-spi1-cs0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x001c, PIN_OUTPUT, 1) /* (N21) OSPI0_D4.SPI1_CS0 */ /* SODIMM 202 */ + >; + }; + + /* Verdin I2S_1 MCLK */ + pinctrl_i2s1_mclk: main-system-audio-ext-reflock0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00c4, PIN_OUTPUT, 5) /* (Y23) VOUT0_DATA3.AUDIO_EXT_REFCLK0 */ /* SODIMM 38 */ + >; + }; + + pinctrl_eth_clock: main-system-clkout0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01f0, PIN_OUTPUT_PULLUP, 5) /* (C25) EXT_REFCLK1.CLKOUT0 */ /* ETH_25MHz_CLK */ + >; + }; + + pinctrl_pmic_extint: main-system-extint-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01f4, PIN_INPUT, 0) /* (C23) EXTINTn */ /* PMIC_EXTINT# */ + >; + }; + + /* Verdin UART_3, used as the Linux console */ + pinctrl_uart0: main-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */ /* SODIMM 147 */ + AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */ /* SODIMM 149 */ + >; + }; + + /* Verdin UART_1 */ + pinctrl_uart1: main-uart1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01ac, PIN_INPUT, 2) /* (G23) MCASP0_AFSR.UART1_RXD */ /* SODIMM 129 */ + AM62PX_IOPAD(0x01b0, PIN_OUTPUT, 2) /* (G20) MCASP0_ACLKR.UART1_TXD */ /* SODIMM 131 */ + AM62PX_IOPAD(0x0194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3.UART1_CTSn */ /* SODIMM 135 */ + AM62PX_IOPAD(0x0198, PIN_OUTPUT, 2) /* (E25) MCASP0_AXR2.UART1_RTSn */ /* SODIMM 133 */ + >; + }; + + /* Verdin MSP 41, 42, 44 and 45 as UART */ + pinctrl_uart2: main-uart2-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00b8, PIN_INPUT, 4) /* (AE24) VOUT0_DATA0.UART2_RXD */ /* SODIMM 192 */ + AM62PX_IOPAD(0x00bc, PIN_OUTPUT, 4) /* (W23) VOUT0_DATA1.UART2_TXD */ /* SODIMM 190 */ + AM62PX_IOPAD(0x0104, PIN_INPUT, 4) /* (Y21) VOUT0_PCLK.UART2_CTSn */ /* SODIMM 184 */ + AM62PX_IOPAD(0x0100, PIN_OUTPUT, 4) /* (W20) VOUT0_VSYNC.UART2_RTSn */ /* SODIMM 186 */ + >; + }; + + /* Bluetooth on WB SKUs */ + pinctrl_uart6: main-uart6-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x00d8, PIN_INPUT, 4) /* (AE22) VOUT0_DATA8.UART6_RXD */ /* WiFi_UART_RXD */ + AM62PX_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (AC22) VOUT0_DATA9.UART6_TXD */ /* WiFi_UART_TXD */ + AM62PX_IOPAD(0x00e4, PIN_INPUT, 4) /* (AE21) VOUT0_DATA11.UART6_CTSn */ /* WiFi_UART_CTS */ + AM62PX_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (W22) VOUT0_DATA10.UART6_RTSn */ /* WiFi_UART_RTS */ + >; + }; + + /* Verdin USB_2_EN */ + pinctrl_usb1: main-usb1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (G21) USB1_DRVVBUS */ /* SODIMM 185 */ + >; + }; + + /* Verdin I2S_1 */ + pinctrl_mcasp0: mcasp0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x01a4, PIN_INPUT, 0) /* (F24) MCASP0_ACLKX */ /* SODIMM 30 */ + AM62PX_IOPAD(0x01a8, PIN_INPUT, 0) /* (F25) MCASP0_AFSX */ /* SODIMM 32 */ + AM62PX_IOPAD(0x01a0, PIN_INPUT, 0) /* (F23) MCASP0_AXR0 */ /* SODIMM 34 */ + AM62PX_IOPAD(0x019c, PIN_INPUT, 0) /* (E24) MCASP0_AXR1 */ /* SODIMM 36 */ + >; + }; + + /* Verdin I2S_2 */ + pinctrl_mcasp1: mcasp1-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0090, PIN_INPUT, 2) /* (U24) GPMC0_BE0n_CLE.MCASP1_ACLKX */ /* SODIMM 42 */ + AM62PX_IOPAD(0x0098, PIN_INPUT, 2) /* (AA24) GPMC0_WAIT0.MCASP1_AFSX */ /* SODIMM 44 */ + AM62PX_IOPAD(0x008c, PIN_INPUT, 2) /* (T25) GPMC0_WEn.MCASP1_AXR0 */ /* SODIMM 46 */ + AM62PX_IOPAD(0x0088, PIN_INPUT, 2) /* (R24) GPMC0_OEn_REn.MCASP1_AXR1 */ /* SODIMM 48 */ + >; + }; + + /* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ + pinctrl_mdio: mdio0-default-pins { + pinctrl-single,pins = < + AM62PX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (F17) MDIO0_MDC */ /* SODIMM 193 */ + AM62PX_IOPAD(0x015c, PIN_INPUT, 0) /* (F16) MDIO0_MDIO */ /* SODIMM 191 */ + >; + }; +}; + +&mcu_pmx0 { + /* Verdin GPIO_1 */ + pinctrl_gpio_1: mcu-gpio0-1-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0004, PIN_INPUT, 7) /* (E10) MCU_SPI0_CS1.MCU_GPIO0_1 */ /* SODIMM 206 */ + >; + }; + + /* Verdin GPIO_2 */ + pinctrl_gpio_2: mcu-gpio0-2-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0008, PIN_INPUT, 7) /* (C10) MCU_SPI0_CLK.MCU_GPIO0_2 */ /* SODIMM 208 */ + >; + }; + + /* Verdin GPIO_3 */ + pinctrl_gpio_3: mcu-gpio0-3-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x000c, PIN_INPUT, 7) /* (B11) MCU_SPI0_D0.MCU_GPIO0_3 */ /* SODIMM 210 */ + >; + }; + + /* Verdin GPIO_4 */ + pinctrl_gpio_4: mcu-gpio0-4-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0010, PIN_INPUT, 7) /* (D10) MCU_SPI0_D1.MCU_GPIO0_4 */ /* SODIMM 212 */ + >; + }; + + /* Verdin I2C_3_HDMI */ + pinctrl_mcu_i2c0: mcu-i2c0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (E11) MCU_I2C0_SCL */ /* SODIMM 59 */ + AM62PX_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D11) MCU_I2C0_SDA */ /* SODIMM 57 */ + >; + }; + + /* Verdin CAN_2 */ + pinctrl_mcu_mcan0: mcu-mcan0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0038, PIN_INPUT, 0) /* (D6) MCU_MCAN0_RX */ /* SODIMM 22 */ + AM62PX_MCU_IOPAD(0x0034, PIN_OUTPUT, 0) /* (E8) MCU_MCAN0_TX */ /* SODIMM 20 */ + >; + }; + + /* Verdin MSP_13/MSP_18 as CAN */ + pinctrl_mcu_mcan1: mcu-mcan1-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0040, PIN_INPUT, 0) /* (E7) MCU_MCAN1_RX */ /* SODIMM 116 */ + AM62PX_MCU_IOPAD(0x003c, PIN_OUTPUT, 0) /* (F8) MCU_MCAN1_TX */ /* SODIMM 128 */ + >; + }; + + /* Verdin UART_4 */ + pinctrl_mcu_uart0: mcu-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0014, PIN_INPUT, 0) /* (B6) MCU_UART0_RXD */ /* SODIMM 151 */ + AM62PX_MCU_IOPAD(0x0018, PIN_OUTPUT, 0) /* (C8) MCU_UART0_TXD */ /* SODIMM 153 */ + >; + }; + + /* On-module I2C - PMIC_I2C */ + pinctrl_wkup_i2c0: wkup-i2c0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x004c, PIN_INPUT, 0) /* (A13) WKUP_I2C0_SCL */ /* PMIC_I2C_SCL */ + AM62PX_MCU_IOPAD(0x0050, PIN_INPUT, 0) /* (C11) WKUP_I2C0_SDA */ /* PMIC_I2C_SDA */ + >; + }; + + /* Verdin CSI_1_MCLK */ + pinctrl_wkup_clkout0: wkup-system-clkout0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (F13) WKUP_CLKOUT0 */ /* SODIMM 91 */ + >; + }; + + /* Verdin UART_2 */ + pinctrl_wkup_uart0: wkup-uart0-default-pins { + pinctrl-single,pins = < + AM62PX_MCU_IOPAD(0x002c, PIN_INPUT, 0) /* (C7) WKUP_UART0_CTSn */ /* SODIMM 143 */ + AM62PX_MCU_IOPAD(0x0030, PIN_OUTPUT, 0) /* (C6) WKUP_UART0_RTSn */ /* SODIMM 141 */ + AM62PX_MCU_IOPAD(0x0024, PIN_INPUT, 0) /* (D8) WKUP_UART0_RXD */ /* SODIMM 137 */ + AM62PX_MCU_IOPAD(0x0028, PIN_OUTPUT, 0) /* (D7) WKUP_UART0_TXD */ /* SODIMM 139 */ + >; + }; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii1>; + status = "disabled"; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio>, <&pinctrl_eth_clock>; + assigned-clocks = <&k3_clks 157 36>; + assigned-clock-parents = <&k3_clks 157 38>; + assigned-clock-rates = <25000000>; + status = "disabled"; + + som_eth_phy: ethernet-phy@0 { + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth_int>; + interrupt-parent = <&main_gpio0>; + interrupts = <36 IRQ_TYPE_EDGE_FALLING>; + ti,clk-output-sel = ; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + }; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + phy-handle = <&som_eth_phy>; + phy-mode = "rgmii-rxid"; + status = "disabled"; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + status = "disabled"; +}; + +/* Verdin PWM_3_DSI */ +&epwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epwm0_b>; + status = "disabled"; +}; + +/* Verdin PWM_1, PWM_2 */ +&epwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epwm2_a>, <&pinctrl_epwm2_b>; + status = "disabled"; +}; + +&mailbox0_cluster0 { + status = "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + status = "okay"; + + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx = <0 0 0>; + ti,mbox-tx = <1 0 0>; + }; +}; + +&main_gpio0 { + gpio-line-names = + "SODIMM_52", + "SODIMM_252", + "SODIMM_66", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "", + "", + "", + "", /* 10 */ + "SODIMM_54", + "SODIMM_64", + "SODIMM_174", + "SODIMM_244", + "", + "", + "", + "", + "", + "", /* 20 */ + "PMIC_SD_VSEL", + "", + "", + "", + "TPM_EXTINT#", + "", + "", + "", + "WiFi_WKUP_BT#", + "WiFi_WKUP_WLAN#", /* 30 */ + "SODIMM_161", + "SODIMM_157", + "", + "", + "", + "ETH_INT#", + "", + "SODIMM_17", + "SODIMM_21", + "", /* 40 */ + "SODIMM_187", + "SODIMM_189", + "", + "", + "", + "", + "SODIMM_76", + "", + "SODIMM_216", + "SODIMM_218", /* 50 */ + "SODIMM_220", + "SODIMM_222", + "", + "", + "", + "", + "SODIMM_172", + "", + "WIFI_SD_INT", + "WIFI_SPI_CS#", /* 60 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 80 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 90 */ + ""; + + verdin_pcie_1_reset_hog: pcie-1-reset-hog { + gpio-hog; + /* Verdin PCIE_1_RESET# (SODIMM 244) */ + gpios = <14 GPIO_ACTIVE_LOW>; + line-name = "PCIE_1_RESET#"; + output-low; + status = "disabled"; + }; +}; + +&main_gpio1 { + gpio-line-names = + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 30 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 40 */ + "", + "", + "", + "", + "", + "", + "", + "SODIMM_84", + "SODIMM_154", + "SODIMM_155", /* 50 */ + ""; +}; + +/* Verdin I2C_1 */ +&main_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_i2c0>; + status = "disabled"; +}; + +/* Verdin I2C_2_DSI */ +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_i2c1>; + status = "disabled"; +}; + +/* Verdin I2C_4_CSI */ +&main_i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_i2c3>; + status = "disabled"; +}; + +/* Verdin CAN_1 */ +&main_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_mcan0>; + status = "disabled"; +}; + +/* TPM SPI, optional SPI on module specific pins */ +&main_spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_spi0>; + ti,pindir-d0-out-d1-in; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm_extint>; + interrupt-parent = <&main_gpio0>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <18500000>; + }; +}; + +/* Verdin SPI_1 */ +&main_spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_main_spi1>, <&pinctrl_main_spi1_cs0>; + ti,pindir-d0-out-d1-in; + status = "disabled"; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "disabled"; +}; + +/* Verdin UART_1 */ +&main_uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "disabled"; +}; + +/* Verdin I2S_1 */ +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp0>; + op-mode = <0>; /* I2S mode */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + rx-num-evt = <0>; + tx-num-evt = <0>; + #sound-dai-cells = <0>; + status = "disabled"; +}; + +/* Verdin I2S_2 */ +&mcasp1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcasp1>; + op-mode = <0>; /* I2S mode */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + >; + tdm-slots = <2>; + rx-num-evt = <0>; + tx-num-evt = <0>; + #sound-dai-cells = <0>; + status = "disabled"; +}; + +&mcu_gpio0 { + gpio-line-names = + "", + "SODIMM_206", + "SODIMM_208", + "SODIMM_210", + "SODIMM_212", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 20 */ + "", + "", + ""; +}; + +/* Verdin I2C_3_HDMI */ +&mcu_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_i2c0>; + status = "disabled"; +}; + +/* Verdin CAN_2 */ +&mcu_mcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_mcan0>; + status = "disabled"; +}; + +/* Verdin UART_4 */ +&mcu_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mcu_uart0>; + status = "disabled"; +}; + +/* Verdin QSPI_1 */ +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ospi0>; + status = "disabled"; +}; + +/* On-module eMMC */ +&sdhci0 { + no-mmc-hs400; + non-removable; + ti,driver-strength-ohm = <50>; + status = "okay"; +}; + +/* Verdin SD_1 */ +&sdhci1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdhci1>, <&pinctrl_sd1_cd>; + cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; + disable-wp; + vmmc-supply = <®_sd1_vmmc>; + vqmmc-supply = <®_sd1_vqmmc>; + ti,fails-without-test-cd; + status = "disabled"; +}; + +/* Verdin USB_1 */ +&usbss0 { + ti,vbus-divider; + status = "disabled"; +}; + +&usb0 { + adp-disable; + usb-role-switch; + status = "disabled"; + + port { + usb0_ep: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; + }; +}; + +/* Verdin USB_2 */ +&usbss1 { + ti,vbus-divider; + status = "disabled"; +}; + +&usb1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + dr_mode = "host"; + status = "disabled"; +}; + +/* On-module I2C - PMIC_I2C */ +&wkup_i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wkup_i2c0>; + clock-frequency = <400000>; + status = "okay"; + + som_gpio_expander: gpio@21 { + compatible = "nxp,pcal6408"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = "SODIMM_256"; + }; + + pmic@30 { + compatible = "ti,tps65219"; + reg = <0x30>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic_extint>; + interrupt-parent = <&gic500>; + interrupts = ; + + buck1-supply = <®_vsodimm>; + buck2-supply = <®_vsodimm>; + buck3-supply = <®_vsodimm>; + ldo1-supply = <®_3v3>; + ldo2-supply = <®_1v8>; + ldo3-supply = <®_3v3>; + ldo4-supply = <®_3v3>; + system-power-controller; + ti,power-button; + + regulators { + reg_3v3: buck1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3 (PMIC BUCK1)"; + }; + + reg_1v8: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8 (PMIC BUCK2)"; /* On-module and SODIMM 214 */ + }; + + buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1100000>; + regulator-min-microvolt = <1100000>; + regulator-name = "+VDD_DDR (PMIC BUCK3)"; + }; + + reg_sd_3v3_1v8: ldo1 { + regulator-allow-bypass; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_1.8_SD (PMIC LDO1)"; + }; + + ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <850000>; + regulator-min-microvolt = <850000>; + regulator-name = "+V_PMIC_LDO2 (PMIC LDO4)"; // +VDDR_CORE + }; + + ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8A (PMIC LDO3)"; + }; + + ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <2500000>; + regulator-name = "+V2.5_ETH (PMIC LDO4)"; + }; + }; + }; + + som_rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + som_adc: adc@49 { + compatible = "ti,tla2024"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + /* Verdin (ADC_4 - ADC_3) */ + channel@0 { + reg = <0>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin (ADC_4 - ADC_1) */ + channel@1 { + reg = <1>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin (ADC_3 - ADC_1) */ + channel@2 { + reg = <2>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin (ADC_2 - ADC_1) */ + channel@3 { + reg = <3>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin ADC_4 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin ADC_3 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin ADC_2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin ADC_1 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <2>; + }; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Verdin UART_2 */ +&wkup_uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wkup_uart0>; + uart-has-rtscts; + status = "disabled"; +}; diff --git a/arch/arm/dts/k3-am62p5-verdin-lpddr4-1600.dtsi b/arch/arm/dts/k3-am62p5-verdin-lpddr4-1600.dtsi new file mode 100644 index 00000000000..4534b0ae44b --- /dev/null +++ b/arch/arm/dts/k3-am62p5-verdin-lpddr4-1600.dtsi @@ -0,0 +1,2801 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * This file was generated with the + * AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px, AM62Dx, AM62Lx v0.10.30 + * Sun Mar 09 2025 17:28:17 GMT+0100 (Central European Standard Time) + * DDR Type: LPDDR4 + * F0 = 50MHz F1 = NA F2 = 1600MHz + * Density (per channel): 8Gb + * Number of Ranks: 1 +*/ + + +#define DDRSS_PLL_FHS_CNT 3 +#define DDRSS_PLL_FREQUENCY_1 800000000 +#define DDRSS_PLL_FREQUENCY_2 800000000 +#define DDRSS_SDRAM_IDX 15 +#define DDRSS_REGION_IDX 17 + +#define DDRSS_CTL_0_DATA 0x00000B00 +#define DDRSS_CTL_1_DATA 0x00000000 +#define DDRSS_CTL_2_DATA 0x00000000 +#define DDRSS_CTL_3_DATA 0x00000000 +#define DDRSS_CTL_4_DATA 0x00000000 +#define DDRSS_CTL_5_DATA 0x00000000 +#define DDRSS_CTL_6_DATA 0x00000000 +#define DDRSS_CTL_7_DATA 0x00002710 +#define DDRSS_CTL_8_DATA 0x000186A0 +#define DDRSS_CTL_9_DATA 0x00000005 +#define DDRSS_CTL_10_DATA 0x00000064 +#define DDRSS_CTL_11_DATA 0x0004E200 +#define DDRSS_CTL_12_DATA 0x0030D400 +#define DDRSS_CTL_13_DATA 0x00000005 +#define DDRSS_CTL_14_DATA 0x00000C80 +#define DDRSS_CTL_15_DATA 0x0004E200 +#define DDRSS_CTL_16_DATA 0x0030D400 +#define DDRSS_CTL_17_DATA 0x00000005 +#define DDRSS_CTL_18_DATA 0x00000C80 +#define DDRSS_CTL_19_DATA 0x01010100 +#define DDRSS_CTL_20_DATA 0x01010100 +#define DDRSS_CTL_21_DATA 0x01000110 +#define DDRSS_CTL_22_DATA 0x02010002 +#define DDRSS_CTL_23_DATA 0x0000000A +#define DDRSS_CTL_24_DATA 0x000186A0 +#define DDRSS_CTL_25_DATA 0x00000000 +#define DDRSS_CTL_26_DATA 0x00000000 +#define DDRSS_CTL_27_DATA 0x00000000 +#define DDRSS_CTL_28_DATA 0x00000000 +#define DDRSS_CTL_29_DATA 0x00020200 +#define DDRSS_CTL_30_DATA 0x00000000 +#define DDRSS_CTL_31_DATA 0x00000000 +#define DDRSS_CTL_32_DATA 0x00000000 +#define DDRSS_CTL_33_DATA 0x00000000 +#define DDRSS_CTL_34_DATA 0x08000010 +#define DDRSS_CTL_35_DATA 0x00004040 +#define DDRSS_CTL_36_DATA 0x00000000 +#define DDRSS_CTL_37_DATA 0x00000000 +#define DDRSS_CTL_38_DATA 0x00000000 +#define DDRSS_CTL_39_DATA 0x00000000 +#define DDRSS_CTL_40_DATA 0x0000040C +#define DDRSS_CTL_41_DATA 0x00000000 +#define DDRSS_CTL_42_DATA 0x00000E38 +#define DDRSS_CTL_43_DATA 0x00000000 +#define DDRSS_CTL_44_DATA 0x00000E38 +#define DDRSS_CTL_45_DATA 0x00000000 +#define DDRSS_CTL_46_DATA 0x05000804 +#define DDRSS_CTL_47_DATA 0x00000A00 +#define DDRSS_CTL_48_DATA 0x09090004 +#define DDRSS_CTL_49_DATA 0x00000303 +#define DDRSS_CTL_50_DATA 0x006B0014 +#define DDRSS_CTL_51_DATA 0x09110048 +#define DDRSS_CTL_52_DATA 0x00004220 +#define DDRSS_CTL_53_DATA 0x006B0014 +#define DDRSS_CTL_54_DATA 0x09110048 +#define DDRSS_CTL_55_DATA 0x09004220 +#define DDRSS_CTL_56_DATA 0x000A0A09 +#define DDRSS_CTL_57_DATA 0x040001B6 +#define DDRSS_CTL_58_DATA 0x090D2005 +#define DDRSS_CTL_59_DATA 0x00001710 +#define DDRSS_CTL_60_DATA 0x0C0036D8 +#define DDRSS_CTL_61_DATA 0x090D200D +#define DDRSS_CTL_62_DATA 0x00001710 +#define DDRSS_CTL_63_DATA 0x0C0036D8 +#define DDRSS_CTL_64_DATA 0x0304200D +#define DDRSS_CTL_65_DATA 0x04050002 +#define DDRSS_CTL_66_DATA 0x1F211F21 +#define DDRSS_CTL_67_DATA 0x01010008 +#define DDRSS_CTL_68_DATA 0x043F3F07 +#define DDRSS_CTL_69_DATA 0x03252503 +#define DDRSS_CTL_70_DATA 0x00002525 +#define DDRSS_CTL_71_DATA 0x00000101 +#define DDRSS_CTL_72_DATA 0x00000000 +#define DDRSS_CTL_73_DATA 0x01000000 +#define DDRSS_CTL_74_DATA 0x000E0803 +#define DDRSS_CTL_75_DATA 0x000000BB +#define DDRSS_CTL_76_DATA 0x000001C0 +#define DDRSS_CTL_77_DATA 0x0000185E +#define DDRSS_CTL_78_DATA 0x000001C0 +#define DDRSS_CTL_79_DATA 0x0000185E +#define DDRSS_CTL_80_DATA 0x00000005 +#define DDRSS_CTL_81_DATA 0x00000007 +#define DDRSS_CTL_82_DATA 0x00000010 +#define DDRSS_CTL_83_DATA 0x000000E0 +#define DDRSS_CTL_84_DATA 0x00000304 +#define DDRSS_CTL_85_DATA 0x000000E0 +#define DDRSS_CTL_86_DATA 0x00000304 +#define DDRSS_CTL_87_DATA 0x03004000 +#define DDRSS_CTL_88_DATA 0x00001201 +#define DDRSS_CTL_89_DATA 0x000C0005 +#define DDRSS_CTL_90_DATA 0x2408000C +#define DDRSS_CTL_91_DATA 0x0A050524 +#define DDRSS_CTL_92_DATA 0x170C0803 +#define DDRSS_CTL_93_DATA 0x170C0803 +#define DDRSS_CTL_94_DATA 0x03010103 +#define DDRSS_CTL_95_DATA 0x00010301 +#define DDRSS_CTL_96_DATA 0x000F000F +#define DDRSS_CTL_97_DATA 0x01CC01CC +#define DDRSS_CTL_98_DATA 0x01CC01CC +#define DDRSS_CTL_99_DATA 0x00000000 +#define DDRSS_CTL_100_DATA 0x03030000 +#define DDRSS_CTL_101_DATA 0x05050501 +#define DDRSS_CTL_102_DATA 0x03031804 +#define DDRSS_CTL_103_DATA 0x0C080C08 +#define DDRSS_CTL_104_DATA 0x08030318 +#define DDRSS_CTL_105_DATA 0x030C080C +#define DDRSS_CTL_106_DATA 0x00000303 +#define DDRSS_CTL_107_DATA 0x00000301 +#define DDRSS_CTL_108_DATA 0x00000001 +#define DDRSS_CTL_109_DATA 0x00000000 +#define DDRSS_CTL_110_DATA 0x40020100 +#define DDRSS_CTL_111_DATA 0x00038010 +#define DDRSS_CTL_112_DATA 0x00050004 +#define DDRSS_CTL_113_DATA 0x00000004 +#define DDRSS_CTL_114_DATA 0x00040003 +#define DDRSS_CTL_115_DATA 0x00040005 +#define DDRSS_CTL_116_DATA 0x00030000 +#define DDRSS_CTL_117_DATA 0x00050004 +#define DDRSS_CTL_118_DATA 0x00000004 +#define DDRSS_CTL_119_DATA 0x00002EC0 +#define DDRSS_CTL_120_DATA 0x00002EC0 +#define DDRSS_CTL_121_DATA 0x00002EC0 +#define DDRSS_CTL_122_DATA 0x00002EC0 +#define DDRSS_CTL_123_DATA 0x00002EC0 +#define DDRSS_CTL_124_DATA 0x00000000 +#define DDRSS_CTL_125_DATA 0x0000051D +#define DDRSS_CTL_126_DATA 0x00061780 +#define DDRSS_CTL_127_DATA 0x00061780 +#define DDRSS_CTL_128_DATA 0x00061780 +#define DDRSS_CTL_129_DATA 0x00061780 +#define DDRSS_CTL_130_DATA 0x00061780 +#define DDRSS_CTL_131_DATA 0x00000000 +#define DDRSS_CTL_132_DATA 0x0000AA92 +#define DDRSS_CTL_133_DATA 0x00061780 +#define DDRSS_CTL_134_DATA 0x00061780 +#define DDRSS_CTL_135_DATA 0x00061780 +#define DDRSS_CTL_136_DATA 0x00061780 +#define DDRSS_CTL_137_DATA 0x00061780 +#define DDRSS_CTL_138_DATA 0x00000000 +#define DDRSS_CTL_139_DATA 0x0000AA92 +#define DDRSS_CTL_140_DATA 0x00000000 +#define DDRSS_CTL_141_DATA 0x00000000 +#define DDRSS_CTL_142_DATA 0x00000000 +#define DDRSS_CTL_143_DATA 0x00000000 +#define DDRSS_CTL_144_DATA 0x00000000 +#define DDRSS_CTL_145_DATA 0x00000000 +#define DDRSS_CTL_146_DATA 0x00000000 +#define DDRSS_CTL_147_DATA 0x00000000 +#define DDRSS_CTL_148_DATA 0x00000000 +#define DDRSS_CTL_149_DATA 0x00000000 +#define DDRSS_CTL_150_DATA 0x00000000 +#define DDRSS_CTL_151_DATA 0x00000000 +#define DDRSS_CTL_152_DATA 0x00000000 +#define DDRSS_CTL_153_DATA 0x00000000 +#define DDRSS_CTL_154_DATA 0x00000000 +#define DDRSS_CTL_155_DATA 0x00000000 +#define DDRSS_CTL_156_DATA 0x00000000 +#define DDRSS_CTL_157_DATA 0x00000000 +#define DDRSS_CTL_158_DATA 0x03050000 +#define DDRSS_CTL_159_DATA 0x03080308 +#define DDRSS_CTL_160_DATA 0x00000000 +#define DDRSS_CTL_161_DATA 0x08010000 +#define DDRSS_CTL_162_DATA 0x000E0808 +#define DDRSS_CTL_163_DATA 0x01000000 +#define DDRSS_CTL_164_DATA 0x0E080808 +#define DDRSS_CTL_165_DATA 0x00000000 +#define DDRSS_CTL_166_DATA 0x08080801 +#define DDRSS_CTL_167_DATA 0x0000080E +#define DDRSS_CTL_168_DATA 0x00040003 +#define DDRSS_CTL_169_DATA 0x00000007 +#define DDRSS_CTL_170_DATA 0x00000000 +#define DDRSS_CTL_171_DATA 0x00000000 +#define DDRSS_CTL_172_DATA 0x00000000 +#define DDRSS_CTL_173_DATA 0x00000000 +#define DDRSS_CTL_174_DATA 0x00000000 +#define DDRSS_CTL_175_DATA 0x00000000 +#define DDRSS_CTL_176_DATA 0x01000000 +#define DDRSS_CTL_177_DATA 0x00000000 +#define DDRSS_CTL_178_DATA 0x00001700 +#define DDRSS_CTL_179_DATA 0x0000100E +#define DDRSS_CTL_180_DATA 0x00000002 +#define DDRSS_CTL_181_DATA 0x00000000 +#define DDRSS_CTL_182_DATA 0x00000001 +#define DDRSS_CTL_183_DATA 0x00000002 +#define DDRSS_CTL_184_DATA 0x00000C00 +#define DDRSS_CTL_185_DATA 0x00008000 +#define DDRSS_CTL_186_DATA 0x00000C00 +#define DDRSS_CTL_187_DATA 0x00008000 +#define DDRSS_CTL_188_DATA 0x00000C00 +#define DDRSS_CTL_189_DATA 0x00008000 +#define DDRSS_CTL_190_DATA 0x00000000 +#define DDRSS_CTL_191_DATA 0x00000000 +#define DDRSS_CTL_192_DATA 0x00000000 +#define DDRSS_CTL_193_DATA 0x00000000 +#define DDRSS_CTL_194_DATA 0x00000000 +#define DDRSS_CTL_195_DATA 0x0005000A +#define DDRSS_CTL_196_DATA 0x0404000D +#define DDRSS_CTL_197_DATA 0x0000000D +#define DDRSS_CTL_198_DATA 0x00A00140 +#define DDRSS_CTL_199_DATA 0x0C0C0190 +#define DDRSS_CTL_200_DATA 0x00000190 +#define DDRSS_CTL_201_DATA 0x00A00140 +#define DDRSS_CTL_202_DATA 0x0C0C0190 +#define DDRSS_CTL_203_DATA 0x00000190 +#define DDRSS_CTL_204_DATA 0x00000000 +#define DDRSS_CTL_205_DATA 0x00000000 +#define DDRSS_CTL_206_DATA 0x00000000 +#define DDRSS_CTL_207_DATA 0x00000000 +#define DDRSS_CTL_208_DATA 0x00000004 +#define DDRSS_CTL_209_DATA 0x00000000 +#define DDRSS_CTL_210_DATA 0x00000000 +#define DDRSS_CTL_211_DATA 0x00000054 +#define DDRSS_CTL_212_DATA 0x0000002D +#define DDRSS_CTL_213_DATA 0x00000000 +#define DDRSS_CTL_214_DATA 0x00000054 +#define DDRSS_CTL_215_DATA 0x0000002D +#define DDRSS_CTL_216_DATA 0x00000000 +#define DDRSS_CTL_217_DATA 0x00000004 +#define DDRSS_CTL_218_DATA 0x00000000 +#define DDRSS_CTL_219_DATA 0x00000000 +#define DDRSS_CTL_220_DATA 0x00000054 +#define DDRSS_CTL_221_DATA 0x0000002D +#define DDRSS_CTL_222_DATA 0x00000000 +#define DDRSS_CTL_223_DATA 0x00000054 +#define DDRSS_CTL_224_DATA 0x0000002D +#define DDRSS_CTL_225_DATA 0x00000000 +#define DDRSS_CTL_226_DATA 0x00000000 +#define DDRSS_CTL_227_DATA 0x00000029 +#define DDRSS_CTL_228_DATA 0x000000A9 +#define DDRSS_CTL_229_DATA 0x000000A9 +#define DDRSS_CTL_230_DATA 0x00000029 +#define DDRSS_CTL_231_DATA 0x000000A9 +#define DDRSS_CTL_232_DATA 0x000000A9 +#define DDRSS_CTL_233_DATA 0x00000000 +#define DDRSS_CTL_234_DATA 0x00000000 +#define DDRSS_CTL_235_DATA 0x00000000 +#define DDRSS_CTL_236_DATA 0x00000000 +#define DDRSS_CTL_237_DATA 0x00000000 +#define DDRSS_CTL_238_DATA 0x00000000 +#define DDRSS_CTL_239_DATA 0x00000000 +#define DDRSS_CTL_240_DATA 0x00000000 +#define DDRSS_CTL_241_DATA 0x00000000 +#define DDRSS_CTL_242_DATA 0x00000000 +#define DDRSS_CTL_243_DATA 0x00000000 +#define DDRSS_CTL_244_DATA 0x00000000 +#define DDRSS_CTL_245_DATA 0x00000000 +#define DDRSS_CTL_246_DATA 0x00000000 +#define DDRSS_CTL_247_DATA 0x00000000 +#define DDRSS_CTL_248_DATA 0x00000000 +#define DDRSS_CTL_249_DATA 0x00000000 +#define DDRSS_CTL_250_DATA 0x00000000 +#define DDRSS_CTL_251_DATA 0x00000000 +#define DDRSS_CTL_252_DATA 0x00000000 +#define DDRSS_CTL_253_DATA 0x00000000 +#define DDRSS_CTL_254_DATA 0x00000000 +#define DDRSS_CTL_255_DATA 0x00000000 +#define DDRSS_CTL_256_DATA 0x00000000 +#define DDRSS_CTL_257_DATA 0x35003535 +#define DDRSS_CTL_258_DATA 0x00002735 +#define DDRSS_CTL_259_DATA 0x00000027 +#define DDRSS_CTL_260_DATA 0x00000027 +#define DDRSS_CTL_261_DATA 0x00000027 +#define DDRSS_CTL_262_DATA 0x00000027 +#define DDRSS_CTL_263_DATA 0x00000027 +#define DDRSS_CTL_264_DATA 0x00000000 +#define DDRSS_CTL_265_DATA 0x00000000 +#define DDRSS_CTL_266_DATA 0x0000002B +#define DDRSS_CTL_267_DATA 0x0000002B +#define DDRSS_CTL_268_DATA 0x0000002B +#define DDRSS_CTL_269_DATA 0x0000002B +#define DDRSS_CTL_270_DATA 0x0000002B +#define DDRSS_CTL_271_DATA 0x0000002B +#define DDRSS_CTL_272_DATA 0x00000000 +#define DDRSS_CTL_273_DATA 0x00000000 +#define DDRSS_CTL_274_DATA 0x00000015 +#define DDRSS_CTL_275_DATA 0x00000015 +#define DDRSS_CTL_276_DATA 0x00000000 +#define DDRSS_CTL_277_DATA 0x00000015 +#define DDRSS_CTL_278_DATA 0x00000015 +#define DDRSS_CTL_279_DATA 0x00000020 +#define DDRSS_CTL_280_DATA 0x00010000 +#define DDRSS_CTL_281_DATA 0x00000100 +#define DDRSS_CTL_282_DATA 0x00000000 +#define DDRSS_CTL_283_DATA 0x00000000 +#define DDRSS_CTL_284_DATA 0x00000101 +#define DDRSS_CTL_285_DATA 0x00000000 +#define DDRSS_CTL_286_DATA 0x00000000 +#define DDRSS_CTL_287_DATA 0x00000000 +#define DDRSS_CTL_288_DATA 0x00000000 +#define DDRSS_CTL_289_DATA 0x00000000 +#define DDRSS_CTL_290_DATA 0x00000000 +#define DDRSS_CTL_291_DATA 0x00000000 +#define DDRSS_CTL_292_DATA 0x00000000 +#define DDRSS_CTL_293_DATA 0x00000000 +#define DDRSS_CTL_294_DATA 0x00000000 +#define DDRSS_CTL_295_DATA 0x00000000 +#define DDRSS_CTL_296_DATA 0x0C181511 +#define DDRSS_CTL_297_DATA 0x00000304 +#define DDRSS_CTL_298_DATA 0x00000000 +#define DDRSS_CTL_299_DATA 0x00000000 +#define DDRSS_CTL_300_DATA 0x00000000 +#define DDRSS_CTL_301_DATA 0x00000000 +#define DDRSS_CTL_302_DATA 0x00000000 +#define DDRSS_CTL_303_DATA 0x00000000 +#define DDRSS_CTL_304_DATA 0x00000000 +#define DDRSS_CTL_305_DATA 0x00000000 +#define DDRSS_CTL_306_DATA 0x00000000 +#define DDRSS_CTL_307_DATA 0x00000000 +#define DDRSS_CTL_308_DATA 0x00000000 +#define DDRSS_CTL_309_DATA 0x00000000 +#define DDRSS_CTL_310_DATA 0x00000000 +#define DDRSS_CTL_311_DATA 0x00020000 +#define DDRSS_CTL_312_DATA 0x00400100 +#define DDRSS_CTL_313_DATA 0x00080032 +#define DDRSS_CTL_314_DATA 0x01000200 +#define DDRSS_CTL_315_DATA 0x06400040 +#define DDRSS_CTL_316_DATA 0x00020030 +#define DDRSS_CTL_317_DATA 0x00400100 +#define DDRSS_CTL_318_DATA 0x00300640 +#define DDRSS_CTL_319_DATA 0x00030000 +#define DDRSS_CTL_320_DATA 0x00500050 +#define DDRSS_CTL_321_DATA 0x00000100 +#define DDRSS_CTL_322_DATA 0x01010000 +#define DDRSS_CTL_323_DATA 0x00000101 +#define DDRSS_CTL_324_DATA 0x1FFF0000 +#define DDRSS_CTL_325_DATA 0x000FFF00 +#define DDRSS_CTL_326_DATA 0xFFFFFFFF +#define DDRSS_CTL_327_DATA 0x00FFFF00 +#define DDRSS_CTL_328_DATA 0x0B000000 +#define DDRSS_CTL_329_DATA 0x0001FFFF +#define DDRSS_CTL_330_DATA 0x01010101 +#define DDRSS_CTL_331_DATA 0x01010101 +#define DDRSS_CTL_332_DATA 0x00000118 +#define DDRSS_CTL_333_DATA 0x00000C01 +#define DDRSS_CTL_334_DATA 0x00040100 +#define DDRSS_CTL_335_DATA 0x00040100 +#define DDRSS_CTL_336_DATA 0x00000000 +#define DDRSS_CTL_337_DATA 0x00000000 +#define DDRSS_CTL_338_DATA 0x01030303 +#define DDRSS_CTL_339_DATA 0x00000001 +#define DDRSS_CTL_340_DATA 0x00000000 +#define DDRSS_CTL_341_DATA 0x00000000 +#define DDRSS_CTL_342_DATA 0x00000000 +#define DDRSS_CTL_343_DATA 0x7FFFFFFF +#define DDRSS_CTL_344_DATA 0x00000000 +#define DDRSS_CTL_345_DATA 0x00000000 +#define DDRSS_CTL_346_DATA 0x00000000 +#define DDRSS_CTL_347_DATA 0x00000000 +#define DDRSS_CTL_348_DATA 0x00000000 +#define DDRSS_CTL_349_DATA 0x00000000 +#define DDRSS_CTL_350_DATA 0x00000000 +#define DDRSS_CTL_351_DATA 0x00000000 +#define DDRSS_CTL_352_DATA 0x00000000 +#define DDRSS_CTL_353_DATA 0x00000000 +#define DDRSS_CTL_354_DATA 0x00000000 +#define DDRSS_CTL_355_DATA 0x00000000 +#define DDRSS_CTL_356_DATA 0x00000000 +#define DDRSS_CTL_357_DATA 0x00000000 +#define DDRSS_CTL_358_DATA 0x00000000 +#define DDRSS_CTL_359_DATA 0x00000000 +#define DDRSS_CTL_360_DATA 0xFFFFFFFF +#define DDRSS_CTL_361_DATA 0xFFFF0000 +#define DDRSS_CTL_362_DATA 0x00000000 +#define DDRSS_CTL_363_DATA 0xFFFFFFFF +#define DDRSS_CTL_364_DATA 0x00000000 +#define DDRSS_CTL_365_DATA 0x00FFFFFF +#define DDRSS_CTL_366_DATA 0xFFFF00FF +#define DDRSS_CTL_367_DATA 0x0000FFFF +#define DDRSS_CTL_368_DATA 0x00000000 +#define DDRSS_CTL_369_DATA 0x00000000 +#define DDRSS_CTL_370_DATA 0x00000000 +#define DDRSS_CTL_371_DATA 0x00000000 +#define DDRSS_CTL_372_DATA 0x00000000 +#define DDRSS_CTL_373_DATA 0x00000000 +#define DDRSS_CTL_374_DATA 0x00000000 +#define DDRSS_CTL_375_DATA 0x00000000 +#define DDRSS_CTL_376_DATA 0x00000000 +#define DDRSS_CTL_377_DATA 0x00000000 +#define DDRSS_CTL_378_DATA 0x00000000 +#define DDRSS_CTL_379_DATA 0x00000000 +#define DDRSS_CTL_380_DATA 0x00000000 +#define DDRSS_CTL_381_DATA 0x00000000 +#define DDRSS_CTL_382_DATA 0x00000000 +#define DDRSS_CTL_383_DATA 0x01000101 +#define DDRSS_CTL_384_DATA 0x01010001 +#define DDRSS_CTL_385_DATA 0x00010101 +#define DDRSS_CTL_386_DATA 0x01080803 +#define DDRSS_CTL_387_DATA 0x05020201 +#define DDRSS_CTL_388_DATA 0x0C081818 +#define DDRSS_CTL_389_DATA 0x0008040C +#define DDRSS_CTL_390_DATA 0x0B100406 +#define DDRSS_CTL_391_DATA 0x0B100406 +#define DDRSS_CTL_392_DATA 0x10100806 +#define DDRSS_CTL_393_DATA 0x01000000 +#define DDRSS_CTL_394_DATA 0x06030601 +#define DDRSS_CTL_395_DATA 0x04000103 +#define DDRSS_CTL_396_DATA 0x1B000004 +#define DDRSS_CTL_397_DATA 0x00000176 +#define DDRSS_CTL_398_DATA 0x00000200 +#define DDRSS_CTL_399_DATA 0x00000200 +#define DDRSS_CTL_400_DATA 0x00000200 +#define DDRSS_CTL_401_DATA 0x00000200 +#define DDRSS_CTL_402_DATA 0x00000693 +#define DDRSS_CTL_403_DATA 0x00000E9C +#define DDRSS_CTL_404_DATA 0x03000202 +#define DDRSS_CTL_405_DATA 0x33200404 +#define DDRSS_CTL_406_DATA 0x000030BC +#define DDRSS_CTL_407_DATA 0x00000200 +#define DDRSS_CTL_408_DATA 0x00000200 +#define DDRSS_CTL_409_DATA 0x00000200 +#define DDRSS_CTL_410_DATA 0x00000200 +#define DDRSS_CTL_411_DATA 0x0000DB4E +#define DDRSS_CTL_412_DATA 0x0001E758 +#define DDRSS_CTL_413_DATA 0x0F160402 +#define DDRSS_CTL_414_DATA 0x33200A07 +#define DDRSS_CTL_415_DATA 0x000030BC +#define DDRSS_CTL_416_DATA 0x00000200 +#define DDRSS_CTL_417_DATA 0x00000200 +#define DDRSS_CTL_418_DATA 0x00000200 +#define DDRSS_CTL_419_DATA 0x00000200 +#define DDRSS_CTL_420_DATA 0x0000DB4E +#define DDRSS_CTL_421_DATA 0x0001E758 +#define DDRSS_CTL_422_DATA 0x0F160402 +#define DDRSS_CTL_423_DATA 0x00200A07 +#define DDRSS_CTL_424_DATA 0x00000000 +#define DDRSS_CTL_425_DATA 0x02000A00 +#define DDRSS_CTL_426_DATA 0x00050003 +#define DDRSS_CTL_427_DATA 0x00010101 +#define DDRSS_CTL_428_DATA 0x00010101 +#define DDRSS_CTL_429_DATA 0x00010001 +#define DDRSS_CTL_430_DATA 0x00000101 +#define DDRSS_CTL_431_DATA 0x02000201 +#define DDRSS_CTL_432_DATA 0x02010000 +#define DDRSS_CTL_433_DATA 0x06000200 +#define DDRSS_CTL_434_DATA 0x00001E1E +#define DDRSS_PI_0_DATA 0x00000B00 +#define DDRSS_PI_1_DATA 0x00000000 +#define DDRSS_PI_2_DATA 0x00000000 +#define DDRSS_PI_3_DATA 0x01000000 +#define DDRSS_PI_4_DATA 0x00000001 +#define DDRSS_PI_5_DATA 0x00010064 +#define DDRSS_PI_6_DATA 0x00000000 +#define DDRSS_PI_7_DATA 0x00000000 +#define DDRSS_PI_8_DATA 0x00000000 +#define DDRSS_PI_9_DATA 0x00000000 +#define DDRSS_PI_10_DATA 0x00000000 +#define DDRSS_PI_11_DATA 0x00000002 +#define DDRSS_PI_12_DATA 0x00000005 +#define DDRSS_PI_13_DATA 0x00050001 +#define DDRSS_PI_14_DATA 0x08000000 +#define DDRSS_PI_15_DATA 0x00010300 +#define DDRSS_PI_16_DATA 0x00000005 +#define DDRSS_PI_17_DATA 0x00000000 +#define DDRSS_PI_18_DATA 0x00000000 +#define DDRSS_PI_19_DATA 0x00000000 +#define DDRSS_PI_20_DATA 0x00000000 +#define DDRSS_PI_21_DATA 0x00000000 +#define DDRSS_PI_22_DATA 0x00000000 +#define DDRSS_PI_23_DATA 0x00000000 +#define DDRSS_PI_24_DATA 0x00000000 +#define DDRSS_PI_25_DATA 0x00000000 +#define DDRSS_PI_26_DATA 0x01010000 +#define DDRSS_PI_27_DATA 0x0A000100 +#define DDRSS_PI_28_DATA 0x00000028 +#define DDRSS_PI_29_DATA 0x05000000 +#define DDRSS_PI_30_DATA 0x00320000 +#define DDRSS_PI_31_DATA 0x00000000 +#define DDRSS_PI_32_DATA 0x00000000 +#define DDRSS_PI_33_DATA 0x01010102 +#define DDRSS_PI_34_DATA 0x00000000 +#define DDRSS_PI_35_DATA 0x00000000 +#define DDRSS_PI_36_DATA 0x00000000 +#define DDRSS_PI_37_DATA 0x00000001 +#define DDRSS_PI_38_DATA 0x000000AA +#define DDRSS_PI_39_DATA 0x00000055 +#define DDRSS_PI_40_DATA 0x000000B5 +#define DDRSS_PI_41_DATA 0x0000004A +#define DDRSS_PI_42_DATA 0x00000056 +#define DDRSS_PI_43_DATA 0x000000A9 +#define DDRSS_PI_44_DATA 0x000000A9 +#define DDRSS_PI_45_DATA 0x000000B5 +#define DDRSS_PI_46_DATA 0x00000000 +#define DDRSS_PI_47_DATA 0x00000000 +#define DDRSS_PI_48_DATA 0x00050500 +#define DDRSS_PI_49_DATA 0x00000019 +#define DDRSS_PI_50_DATA 0x000007D0 +#define DDRSS_PI_51_DATA 0x00000300 +#define DDRSS_PI_52_DATA 0x00000000 +#define DDRSS_PI_53_DATA 0x00000000 +#define DDRSS_PI_54_DATA 0x01000000 +#define DDRSS_PI_55_DATA 0x00010101 +#define DDRSS_PI_56_DATA 0x01000000 +#define DDRSS_PI_57_DATA 0x03000000 +#define DDRSS_PI_58_DATA 0x00000000 +#define DDRSS_PI_59_DATA 0x00001705 +#define DDRSS_PI_60_DATA 0x00000000 +#define DDRSS_PI_61_DATA 0x00000000 +#define DDRSS_PI_62_DATA 0x00000000 +#define DDRSS_PI_63_DATA 0x0A0A140A +#define DDRSS_PI_64_DATA 0x10020101 +#define DDRSS_PI_65_DATA 0x01000210 +#define DDRSS_PI_66_DATA 0x05000404 +#define DDRSS_PI_67_DATA 0x00010001 +#define DDRSS_PI_68_DATA 0x0001000E +#define DDRSS_PI_69_DATA 0x01010500 +#define DDRSS_PI_70_DATA 0x00010000 +#define DDRSS_PI_71_DATA 0x00000034 +#define DDRSS_PI_72_DATA 0x00000000 +#define DDRSS_PI_73_DATA 0x00000000 +#define DDRSS_PI_74_DATA 0x0000FFFF +#define DDRSS_PI_75_DATA 0x00000000 +#define DDRSS_PI_76_DATA 0x00000000 +#define DDRSS_PI_77_DATA 0x00000000 +#define DDRSS_PI_78_DATA 0x00000000 +#define DDRSS_PI_79_DATA 0x01000000 +#define DDRSS_PI_80_DATA 0x01010001 +#define DDRSS_PI_81_DATA 0x02000008 +#define DDRSS_PI_82_DATA 0x01000200 +#define DDRSS_PI_83_DATA 0x00000100 +#define DDRSS_PI_84_DATA 0x02000100 +#define DDRSS_PI_85_DATA 0x02000200 +#define DDRSS_PI_86_DATA 0x00000000 +#define DDRSS_PI_87_DATA 0x00000000 +#define DDRSS_PI_88_DATA 0x00000000 +#define DDRSS_PI_89_DATA 0x00000000 +#define DDRSS_PI_90_DATA 0x00000000 +#define DDRSS_PI_91_DATA 0x00000000 +#define DDRSS_PI_92_DATA 0x00000000 +#define DDRSS_PI_93_DATA 0x00000000 +#define DDRSS_PI_94_DATA 0x00000000 +#define DDRSS_PI_95_DATA 0x00000000 +#define DDRSS_PI_96_DATA 0x00000000 +#define DDRSS_PI_97_DATA 0x00000000 +#define DDRSS_PI_98_DATA 0x00000000 +#define DDRSS_PI_99_DATA 0x01000400 +#define DDRSS_PI_100_DATA 0x0E0D0F10 +#define DDRSS_PI_101_DATA 0x080A1413 +#define DDRSS_PI_102_DATA 0x01000009 +#define DDRSS_PI_103_DATA 0x00000302 +#define DDRSS_PI_104_DATA 0x00000008 +#define DDRSS_PI_105_DATA 0x08000000 +#define DDRSS_PI_106_DATA 0x00000100 +#define DDRSS_PI_107_DATA 0x00000000 +#define DDRSS_PI_108_DATA 0x0000AA00 +#define DDRSS_PI_109_DATA 0x00000000 +#define DDRSS_PI_110_DATA 0x00000000 +#define DDRSS_PI_111_DATA 0x00010000 +#define DDRSS_PI_112_DATA 0x00000000 +#define DDRSS_PI_113_DATA 0x00000000 +#define DDRSS_PI_114_DATA 0x00000000 +#define DDRSS_PI_115_DATA 0x00000000 +#define DDRSS_PI_116_DATA 0x00000000 +#define DDRSS_PI_117_DATA 0x00000000 +#define DDRSS_PI_118_DATA 0x00000000 +#define DDRSS_PI_119_DATA 0x00000000 +#define DDRSS_PI_120_DATA 0x00000000 +#define DDRSS_PI_121_DATA 0x00000000 +#define DDRSS_PI_122_DATA 0x00000000 +#define DDRSS_PI_123_DATA 0x00000000 +#define DDRSS_PI_124_DATA 0x00000000 +#define DDRSS_PI_125_DATA 0x00000000 +#define DDRSS_PI_126_DATA 0x00000000 +#define DDRSS_PI_127_DATA 0x00000000 +#define DDRSS_PI_128_DATA 0x00000000 +#define DDRSS_PI_129_DATA 0x00000000 +#define DDRSS_PI_130_DATA 0x00000000 +#define DDRSS_PI_131_DATA 0x00000000 +#define DDRSS_PI_132_DATA 0x00000000 +#define DDRSS_PI_133_DATA 0x00000000 +#define DDRSS_PI_134_DATA 0x00000000 +#define DDRSS_PI_135_DATA 0x00000000 +#define DDRSS_PI_136_DATA 0x00000008 +#define DDRSS_PI_137_DATA 0x00000000 +#define DDRSS_PI_138_DATA 0x00000000 +#define DDRSS_PI_139_DATA 0x00000000 +#define DDRSS_PI_140_DATA 0x00000000 +#define DDRSS_PI_141_DATA 0x00000000 +#define DDRSS_PI_142_DATA 0x00000000 +#define DDRSS_PI_143_DATA 0x00000000 +#define DDRSS_PI_144_DATA 0x00000000 +#define DDRSS_PI_145_DATA 0x00010000 +#define DDRSS_PI_146_DATA 0x00000000 +#define DDRSS_PI_147_DATA 0x00000000 +#define DDRSS_PI_148_DATA 0x0000000A +#define DDRSS_PI_149_DATA 0x000186A0 +#define DDRSS_PI_150_DATA 0x00000100 +#define DDRSS_PI_151_DATA 0x00000000 +#define DDRSS_PI_152_DATA 0x00000000 +#define DDRSS_PI_153_DATA 0x00000000 +#define DDRSS_PI_154_DATA 0x00000000 +#define DDRSS_PI_155_DATA 0x00000000 +#define DDRSS_PI_156_DATA 0x01000000 +#define DDRSS_PI_157_DATA 0x00010003 +#define DDRSS_PI_158_DATA 0x02000101 +#define DDRSS_PI_159_DATA 0x01030001 +#define DDRSS_PI_160_DATA 0x00010400 +#define DDRSS_PI_161_DATA 0x06000105 +#define DDRSS_PI_162_DATA 0x01070001 +#define DDRSS_PI_163_DATA 0x00000000 +#define DDRSS_PI_164_DATA 0x00000000 +#define DDRSS_PI_165_DATA 0x00000000 +#define DDRSS_PI_166_DATA 0x00010001 +#define DDRSS_PI_167_DATA 0x00000000 +#define DDRSS_PI_168_DATA 0x00000000 +#define DDRSS_PI_169_DATA 0x00000000 +#define DDRSS_PI_170_DATA 0x00000000 +#define DDRSS_PI_171_DATA 0x00010000 +#define DDRSS_PI_172_DATA 0x00000004 +#define DDRSS_PI_173_DATA 0x00000000 +#define DDRSS_PI_174_DATA 0x00010000 +#define DDRSS_PI_175_DATA 0x00000000 +#define DDRSS_PI_176_DATA 0x00080000 +#define DDRSS_PI_177_DATA 0x00F000F0 +#define DDRSS_PI_178_DATA 0x00202001 +#define DDRSS_PI_179_DATA 0x00000034 +#define DDRSS_PI_180_DATA 0x00000058 +#define DDRSS_PI_181_DATA 0x00020058 +#define DDRSS_PI_182_DATA 0x02000200 +#define DDRSS_PI_183_DATA 0x00000004 +#define DDRSS_PI_184_DATA 0x00000E0C +#define DDRSS_PI_185_DATA 0x000E3800 +#define DDRSS_PI_186_DATA 0x00380000 +#define DDRSS_PI_187_DATA 0x0000000E +#define DDRSS_PI_188_DATA 0x000000BB +#define DDRSS_PI_189_DATA 0x000001C0 +#define DDRSS_PI_190_DATA 0x0000185E +#define DDRSS_PI_191_DATA 0x000001C0 +#define DDRSS_PI_192_DATA 0x0400185E +#define DDRSS_PI_193_DATA 0x01010404 +#define DDRSS_PI_194_DATA 0x00001501 +#define DDRSS_PI_195_DATA 0x00250025 +#define DDRSS_PI_196_DATA 0x01000100 +#define DDRSS_PI_197_DATA 0x00000100 +#define DDRSS_PI_198_DATA 0x00000000 +#define DDRSS_PI_199_DATA 0x05080803 +#define DDRSS_PI_200_DATA 0x01011818 +#define DDRSS_PI_201_DATA 0x01010101 +#define DDRSS_PI_202_DATA 0x000C0C0A +#define DDRSS_PI_203_DATA 0x00000000 +#define DDRSS_PI_204_DATA 0x00000000 +#define DDRSS_PI_205_DATA 0x04000000 +#define DDRSS_PI_206_DATA 0x0A021010 +#define DDRSS_PI_207_DATA 0x0404020A +#define DDRSS_PI_208_DATA 0x00090031 +#define DDRSS_PI_209_DATA 0x00190041 +#define DDRSS_PI_210_DATA 0x00190041 +#define DDRSS_PI_211_DATA 0x01010101 +#define DDRSS_PI_212_DATA 0x0003000D +#define DDRSS_PI_213_DATA 0x00030190 +#define DDRSS_PI_214_DATA 0x01000190 +#define DDRSS_PI_215_DATA 0x000E000E +#define DDRSS_PI_216_DATA 0x01910100 +#define DDRSS_PI_217_DATA 0x01000191 +#define DDRSS_PI_218_DATA 0x01910191 +#define DDRSS_PI_219_DATA 0x301B3200 +#define DDRSS_PI_220_DATA 0x0101301B +#define DDRSS_PI_221_DATA 0x0A070601 +#define DDRSS_PI_222_DATA 0x180F090D +#define DDRSS_PI_223_DATA 0x180F0911 +#define DDRSS_PI_224_DATA 0x000C0011 +#define DDRSS_PI_225_DATA 0x00001000 +#define DDRSS_PI_226_DATA 0x00000C00 +#define DDRSS_PI_227_DATA 0x00001000 +#define DDRSS_PI_228_DATA 0x00000C00 +#define DDRSS_PI_229_DATA 0x02001000 +#define DDRSS_PI_230_DATA 0x001E000D +#define DDRSS_PI_231_DATA 0x001E0190 +#define DDRSS_PI_232_DATA 0x00000190 +#define DDRSS_PI_233_DATA 0x00001900 +#define DDRSS_PI_234_DATA 0x32000056 +#define DDRSS_PI_235_DATA 0x06000101 +#define DDRSS_PI_236_DATA 0x00230204 +#define DDRSS_PI_237_DATA 0x3212005A +#define DDRSS_PI_238_DATA 0x13000101 +#define DDRSS_PI_239_DATA 0x00230A10 +#define DDRSS_PI_240_DATA 0x3212005A +#define DDRSS_PI_241_DATA 0x13000101 +#define DDRSS_PI_242_DATA 0x00000A10 +#define DDRSS_PI_243_DATA 0x05030900 +#define DDRSS_PI_244_DATA 0x00040900 +#define DDRSS_PI_245_DATA 0x0000018A +#define DDRSS_PI_246_DATA 0x20010004 +#define DDRSS_PI_247_DATA 0x0A0A0A03 +#define DDRSS_PI_248_DATA 0x250D0000 +#define DDRSS_PI_249_DATA 0x1F090021 +#define DDRSS_PI_250_DATA 0x0000315C +#define DDRSS_PI_251_DATA 0x20060048 +#define DDRSS_PI_252_DATA 0x17101718 +#define DDRSS_PI_253_DATA 0x250D0000 +#define DDRSS_PI_254_DATA 0x1F090021 +#define DDRSS_PI_255_DATA 0x0000315C +#define DDRSS_PI_256_DATA 0x20060048 +#define DDRSS_PI_257_DATA 0x17101718 +#define DDRSS_PI_258_DATA 0x00000000 +#define DDRSS_PI_259_DATA 0x00000176 +#define DDRSS_PI_260_DATA 0x00000E9C +#define DDRSS_PI_261_DATA 0x000030BC +#define DDRSS_PI_262_DATA 0x0001E758 +#define DDRSS_PI_263_DATA 0x000030BC +#define DDRSS_PI_264_DATA 0x0001E758 +#define DDRSS_PI_265_DATA 0x01CC000F +#define DDRSS_PI_266_DATA 0x030301CC +#define DDRSS_PI_267_DATA 0x00000003 +#define DDRSS_PI_268_DATA 0x00000000 +#define DDRSS_PI_269_DATA 0x08030503 +#define DDRSS_PI_270_DATA 0x00000803 +#define DDRSS_PI_271_DATA 0x00002710 +#define DDRSS_PI_272_DATA 0x000186A0 +#define DDRSS_PI_273_DATA 0x00000005 +#define DDRSS_PI_274_DATA 0x00000064 +#define DDRSS_PI_275_DATA 0x0000000F +#define DDRSS_PI_276_DATA 0x0004E200 +#define DDRSS_PI_277_DATA 0x000186A0 +#define DDRSS_PI_278_DATA 0x00000005 +#define DDRSS_PI_279_DATA 0x00000C80 +#define DDRSS_PI_280_DATA 0x000001CC +#define DDRSS_PI_281_DATA 0x0004E200 +#define DDRSS_PI_282_DATA 0x000186A0 +#define DDRSS_PI_283_DATA 0x00000005 +#define DDRSS_PI_284_DATA 0x00000C80 +#define DDRSS_PI_285_DATA 0x010001CC +#define DDRSS_PI_286_DATA 0x00320040 +#define DDRSS_PI_287_DATA 0x00010008 +#define DDRSS_PI_288_DATA 0x06400040 +#define DDRSS_PI_289_DATA 0x00010030 +#define DDRSS_PI_290_DATA 0x06400040 +#define DDRSS_PI_291_DATA 0x00000330 +#define DDRSS_PI_292_DATA 0x00280050 +#define DDRSS_PI_293_DATA 0x03040404 +#define DDRSS_PI_294_DATA 0x00000303 +#define DDRSS_PI_295_DATA 0x01010000 +#define DDRSS_PI_296_DATA 0x04040202 +#define DDRSS_PI_297_DATA 0x67670808 +#define DDRSS_PI_298_DATA 0x67676767 +#define DDRSS_PI_299_DATA 0x67676767 +#define DDRSS_PI_300_DATA 0x67676767 +#define DDRSS_PI_301_DATA 0x00006767 +#define DDRSS_PI_302_DATA 0x00000000 +#define DDRSS_PI_303_DATA 0x00000000 +#define DDRSS_PI_304_DATA 0x00000000 +#define DDRSS_PI_305_DATA 0x00000000 +#define DDRSS_PI_306_DATA 0x55000000 +#define DDRSS_PI_307_DATA 0x00000000 +#define DDRSS_PI_308_DATA 0x3C00005A +#define DDRSS_PI_309_DATA 0x00005500 +#define DDRSS_PI_310_DATA 0x00005A00 +#define DDRSS_PI_311_DATA 0x0055003C +#define DDRSS_PI_312_DATA 0x00000000 +#define DDRSS_PI_313_DATA 0x3C00005A +#define DDRSS_PI_314_DATA 0x00005500 +#define DDRSS_PI_315_DATA 0x00005A00 +#define DDRSS_PI_316_DATA 0x1716153C +#define DDRSS_PI_317_DATA 0x13121118 +#define DDRSS_PI_318_DATA 0x06050414 +#define DDRSS_PI_319_DATA 0x02010007 +#define DDRSS_PI_320_DATA 0x00000003 +#define DDRSS_PI_321_DATA 0x00000000 +#define DDRSS_PI_322_DATA 0x00000000 +#define DDRSS_PI_323_DATA 0x01000000 +#define DDRSS_PI_324_DATA 0x04020201 +#define DDRSS_PI_325_DATA 0x00080804 +#define DDRSS_PI_326_DATA 0x00000000 +#define DDRSS_PI_327_DATA 0x00000000 +#define DDRSS_PI_328_DATA 0x00000000 +#define DDRSS_PI_329_DATA 0x00000004 +#define DDRSS_PI_330_DATA 0x00000000 +#define DDRSS_PI_331_DATA 0x00000029 +#define DDRSS_PI_332_DATA 0x00000000 +#define DDRSS_PI_333_DATA 0x00000000 +#define DDRSS_PI_334_DATA 0x00000000 +#define DDRSS_PI_335_DATA 0x20002B27 +#define DDRSS_PI_336_DATA 0x00000000 +#define DDRSS_PI_337_DATA 0x00000054 +#define DDRSS_PI_338_DATA 0x0000002D +#define DDRSS_PI_339_DATA 0x000000A9 +#define DDRSS_PI_340_DATA 0x00000000 +#define DDRSS_PI_341_DATA 0x00000000 +#define DDRSS_PI_342_DATA 0x35000000 +#define DDRSS_PI_343_DATA 0x20152B27 +#define DDRSS_PI_344_DATA 0x00000000 +#define DDRSS_PI_345_DATA 0x00000054 +#define DDRSS_PI_346_DATA 0x0000002D +#define DDRSS_PI_347_DATA 0x000000A9 +#define DDRSS_PI_348_DATA 0x00000000 +#define DDRSS_PI_349_DATA 0x00000000 +#define DDRSS_PI_350_DATA 0x35000000 +#define DDRSS_PI_351_DATA 0x20152B27 +#define DDRSS_PI_352_DATA 0x00000000 +#define DDRSS_PI_353_DATA 0x00000004 +#define DDRSS_PI_354_DATA 0x00000000 +#define DDRSS_PI_355_DATA 0x00000029 +#define DDRSS_PI_356_DATA 0x00000000 +#define DDRSS_PI_357_DATA 0x00000000 +#define DDRSS_PI_358_DATA 0x00000000 +#define DDRSS_PI_359_DATA 0x20002B27 +#define DDRSS_PI_360_DATA 0x00000000 +#define DDRSS_PI_361_DATA 0x00000054 +#define DDRSS_PI_362_DATA 0x0000002D +#define DDRSS_PI_363_DATA 0x000000A9 +#define DDRSS_PI_364_DATA 0x00000000 +#define DDRSS_PI_365_DATA 0x00000000 +#define DDRSS_PI_366_DATA 0x35000000 +#define DDRSS_PI_367_DATA 0x20152B27 +#define DDRSS_PI_368_DATA 0x00000000 +#define DDRSS_PI_369_DATA 0x00000054 +#define DDRSS_PI_370_DATA 0x0000002D +#define DDRSS_PI_371_DATA 0x000000A9 +#define DDRSS_PI_372_DATA 0x00000000 +#define DDRSS_PI_373_DATA 0x00000000 +#define DDRSS_PI_374_DATA 0x35000000 +#define DDRSS_PI_375_DATA 0x20152B27 +#define DDRSS_PI_376_DATA 0x00000000 +#define DDRSS_PI_377_DATA 0x00000004 +#define DDRSS_PI_378_DATA 0x00000000 +#define DDRSS_PI_379_DATA 0x00000029 +#define DDRSS_PI_380_DATA 0x00000000 +#define DDRSS_PI_381_DATA 0x00000000 +#define DDRSS_PI_382_DATA 0x00000000 +#define DDRSS_PI_383_DATA 0x20002B27 +#define DDRSS_PI_384_DATA 0x00000000 +#define DDRSS_PI_385_DATA 0x00000054 +#define DDRSS_PI_386_DATA 0x0000002D +#define DDRSS_PI_387_DATA 0x000000A9 +#define DDRSS_PI_388_DATA 0x00000000 +#define DDRSS_PI_389_DATA 0x00000000 +#define DDRSS_PI_390_DATA 0x35000000 +#define DDRSS_PI_391_DATA 0x20152B27 +#define DDRSS_PI_392_DATA 0x00000000 +#define DDRSS_PI_393_DATA 0x00000054 +#define DDRSS_PI_394_DATA 0x0000002D +#define DDRSS_PI_395_DATA 0x000000A9 +#define DDRSS_PI_396_DATA 0x00000000 +#define DDRSS_PI_397_DATA 0x00000000 +#define DDRSS_PI_398_DATA 0x35000000 +#define DDRSS_PI_399_DATA 0x20152B27 +#define DDRSS_PI_400_DATA 0x00000000 +#define DDRSS_PI_401_DATA 0x00000004 +#define DDRSS_PI_402_DATA 0x00000000 +#define DDRSS_PI_403_DATA 0x00000029 +#define DDRSS_PI_404_DATA 0x00000000 +#define DDRSS_PI_405_DATA 0x00000000 +#define DDRSS_PI_406_DATA 0x00000000 +#define DDRSS_PI_407_DATA 0x20002B27 +#define DDRSS_PI_408_DATA 0x00000000 +#define DDRSS_PI_409_DATA 0x00000054 +#define DDRSS_PI_410_DATA 0x0000002D +#define DDRSS_PI_411_DATA 0x000000A9 +#define DDRSS_PI_412_DATA 0x00000000 +#define DDRSS_PI_413_DATA 0x00000000 +#define DDRSS_PI_414_DATA 0x35000000 +#define DDRSS_PI_415_DATA 0x20152B27 +#define DDRSS_PI_416_DATA 0x00000000 +#define DDRSS_PI_417_DATA 0x00000054 +#define DDRSS_PI_418_DATA 0x0000002D +#define DDRSS_PI_419_DATA 0x000000A9 +#define DDRSS_PI_420_DATA 0x00000000 +#define DDRSS_PI_421_DATA 0x00000000 +#define DDRSS_PI_422_DATA 0x35000000 +#define DDRSS_PI_423_DATA 0x20152B27 +#define DDRSS_PHY_0_DATA 0x04F00000 +#define DDRSS_PHY_1_DATA 0x00000000 +#define DDRSS_PHY_2_DATA 0x00030200 +#define DDRSS_PHY_3_DATA 0x00000000 +#define DDRSS_PHY_4_DATA 0x00000000 +#define DDRSS_PHY_5_DATA 0x01030000 +#define DDRSS_PHY_6_DATA 0x00010000 +#define DDRSS_PHY_7_DATA 0x01030004 +#define DDRSS_PHY_8_DATA 0x01000000 +#define DDRSS_PHY_9_DATA 0x00000000 +#define DDRSS_PHY_10_DATA 0x00000000 +#define DDRSS_PHY_11_DATA 0x00000000 +#define DDRSS_PHY_12_DATA 0x01010000 +#define DDRSS_PHY_13_DATA 0x00010000 +#define DDRSS_PHY_14_DATA 0x00C00001 +#define DDRSS_PHY_15_DATA 0x00CC0008 +#define DDRSS_PHY_16_DATA 0x00660601 +#define DDRSS_PHY_17_DATA 0x00000003 +#define DDRSS_PHY_18_DATA 0x00000000 +#define DDRSS_PHY_19_DATA 0x00000001 +#define DDRSS_PHY_20_DATA 0x0000AAAA +#define DDRSS_PHY_21_DATA 0x00005555 +#define DDRSS_PHY_22_DATA 0x0000B5B5 +#define DDRSS_PHY_23_DATA 0x00004A4A +#define DDRSS_PHY_24_DATA 0x00005656 +#define DDRSS_PHY_25_DATA 0x0000A9A9 +#define DDRSS_PHY_26_DATA 0x0000B7B7 +#define DDRSS_PHY_27_DATA 0x00004848 +#define DDRSS_PHY_28_DATA 0x00000000 +#define DDRSS_PHY_29_DATA 0x00000000 +#define DDRSS_PHY_30_DATA 0x08000000 +#define DDRSS_PHY_31_DATA 0x0F000008 +#define DDRSS_PHY_32_DATA 0x00000F0F +#define DDRSS_PHY_33_DATA 0x00E4E400 +#define DDRSS_PHY_34_DATA 0x00071020 +#define DDRSS_PHY_35_DATA 0x000C0020 +#define DDRSS_PHY_36_DATA 0x00062000 +#define DDRSS_PHY_37_DATA 0x00000000 +#define DDRSS_PHY_38_DATA 0x55555555 +#define DDRSS_PHY_39_DATA 0xAAAAAAAA +#define DDRSS_PHY_40_DATA 0x55555555 +#define DDRSS_PHY_41_DATA 0xAAAAAAAA +#define DDRSS_PHY_42_DATA 0x00005555 +#define DDRSS_PHY_43_DATA 0x01000100 +#define DDRSS_PHY_44_DATA 0x00800180 +#define DDRSS_PHY_45_DATA 0x00000001 +#define DDRSS_PHY_46_DATA 0x00000000 +#define DDRSS_PHY_47_DATA 0x00000000 +#define DDRSS_PHY_48_DATA 0x00000000 +#define DDRSS_PHY_49_DATA 0x00000000 +#define DDRSS_PHY_50_DATA 0x00000000 +#define DDRSS_PHY_51_DATA 0x00000000 +#define DDRSS_PHY_52_DATA 0x00000000 +#define DDRSS_PHY_53_DATA 0x00000000 +#define DDRSS_PHY_54_DATA 0x00000000 +#define DDRSS_PHY_55_DATA 0x00000000 +#define DDRSS_PHY_56_DATA 0x00000000 +#define DDRSS_PHY_57_DATA 0x00000000 +#define DDRSS_PHY_58_DATA 0x00000000 +#define DDRSS_PHY_59_DATA 0x00000000 +#define DDRSS_PHY_60_DATA 0x00000000 +#define DDRSS_PHY_61_DATA 0x00000000 +#define DDRSS_PHY_62_DATA 0x00000000 +#define DDRSS_PHY_63_DATA 0x00000000 +#define DDRSS_PHY_64_DATA 0x00000000 +#define DDRSS_PHY_65_DATA 0x00000000 +#define DDRSS_PHY_66_DATA 0x00000000 +#define DDRSS_PHY_67_DATA 0x00000104 +#define DDRSS_PHY_68_DATA 0x00000000 +#define DDRSS_PHY_69_DATA 0x00000000 +#define DDRSS_PHY_70_DATA 0x00000000 +#define DDRSS_PHY_71_DATA 0x00000000 +#define DDRSS_PHY_72_DATA 0x00000000 +#define DDRSS_PHY_73_DATA 0x00000000 +#define DDRSS_PHY_74_DATA 0x081F07FF +#define DDRSS_PHY_75_DATA 0x10200080 +#define DDRSS_PHY_76_DATA 0x00000008 +#define DDRSS_PHY_77_DATA 0x00000401 +#define DDRSS_PHY_78_DATA 0x00000000 +#define DDRSS_PHY_79_DATA 0x01CC0B01 +#define DDRSS_PHY_80_DATA 0x1003CC0B +#define DDRSS_PHY_81_DATA 0x20000140 +#define DDRSS_PHY_82_DATA 0x07FF0200 +#define DDRSS_PHY_83_DATA 0x0000DD01 +#define DDRSS_PHY_84_DATA 0x00100303 +#define DDRSS_PHY_85_DATA 0x00000000 +#define DDRSS_PHY_86_DATA 0x00000000 +#define DDRSS_PHY_87_DATA 0x00031000 +#define DDRSS_PHY_88_DATA 0x00100010 +#define DDRSS_PHY_89_DATA 0x00100010 +#define DDRSS_PHY_90_DATA 0x00100010 +#define DDRSS_PHY_91_DATA 0x00100010 +#define DDRSS_PHY_92_DATA 0x02000010 +#define DDRSS_PHY_93_DATA 0x00000004 +#define DDRSS_PHY_94_DATA 0x51516042 +#define DDRSS_PHY_95_DATA 0x31C06000 +#define DDRSS_PHY_96_DATA 0x07AB0340 +#define DDRSS_PHY_97_DATA 0x00C0C001 +#define DDRSS_PHY_98_DATA 0x0B000000 +#define DDRSS_PHY_99_DATA 0x000B0A0A +#define DDRSS_PHY_100_DATA 0x42100010 +#define DDRSS_PHY_101_DATA 0x010C073E +#define DDRSS_PHY_102_DATA 0x000F0C2D +#define DDRSS_PHY_103_DATA 0x01000140 +#define DDRSS_PHY_104_DATA 0x00F50120 +#define DDRSS_PHY_105_DATA 0x00000C00 +#define DDRSS_PHY_106_DATA 0x00000299 +#define DDRSS_PHY_107_DATA 0x00030200 +#define DDRSS_PHY_108_DATA 0x02800000 +#define DDRSS_PHY_109_DATA 0x80800000 +#define DDRSS_PHY_110_DATA 0x000B2010 +#define DDRSS_PHY_111_DATA 0x43180276 +#define DDRSS_PHY_112_DATA 0x00000005 +#define DDRSS_PHY_113_DATA 0x04190419 +#define DDRSS_PHY_114_DATA 0x04190419 +#define DDRSS_PHY_115_DATA 0x04190419 +#define DDRSS_PHY_116_DATA 0x04190419 +#define DDRSS_PHY_117_DATA 0x00000419 +#define DDRSS_PHY_118_DATA 0x0000A000 +#define DDRSS_PHY_119_DATA 0x00A000A0 +#define DDRSS_PHY_120_DATA 0x00A000A0 +#define DDRSS_PHY_121_DATA 0x00A000A0 +#define DDRSS_PHY_122_DATA 0x00A000A0 +#define DDRSS_PHY_123_DATA 0x00A000A0 +#define DDRSS_PHY_124_DATA 0x00A000A0 +#define DDRSS_PHY_125_DATA 0x00A000A0 +#define DDRSS_PHY_126_DATA 0x00A000A0 +#define DDRSS_PHY_127_DATA 0x01E600A0 +#define DDRSS_PHY_128_DATA 0x01000000 +#define DDRSS_PHY_129_DATA 0x00000000 +#define DDRSS_PHY_130_DATA 0x00000000 +#define DDRSS_PHY_131_DATA 0x00080200 +#define DDRSS_PHY_132_DATA 0x00000000 +#define DDRSS_PHY_133_DATA 0x20202020 +#define DDRSS_PHY_134_DATA 0x20202020 +#define DDRSS_PHY_135_DATA 0xF0F02020 +#define DDRSS_PHY_136_DATA 0x00000000 +#define DDRSS_PHY_137_DATA 0x00000000 +#define DDRSS_PHY_138_DATA 0x00000000 +#define DDRSS_PHY_139_DATA 0x00000000 +#define DDRSS_PHY_140_DATA 0x00000000 +#define DDRSS_PHY_141_DATA 0x00000000 +#define DDRSS_PHY_142_DATA 0x00000000 +#define DDRSS_PHY_143_DATA 0x00000000 +#define DDRSS_PHY_144_DATA 0x00000000 +#define DDRSS_PHY_145_DATA 0x00000000 +#define DDRSS_PHY_146_DATA 0x00000000 +#define DDRSS_PHY_147_DATA 0x00000000 +#define DDRSS_PHY_148_DATA 0x00000000 +#define DDRSS_PHY_149_DATA 0x00000000 +#define DDRSS_PHY_150_DATA 0x00000000 +#define DDRSS_PHY_151_DATA 0x00000000 +#define DDRSS_PHY_152_DATA 0x00000000 +#define DDRSS_PHY_153_DATA 0x00000000 +#define DDRSS_PHY_154_DATA 0x00000000 +#define DDRSS_PHY_155_DATA 0x00000000 +#define DDRSS_PHY_156_DATA 0x00000000 +#define DDRSS_PHY_157_DATA 0x00000000 +#define DDRSS_PHY_158_DATA 0x00000000 +#define DDRSS_PHY_159_DATA 0x00000000 +#define DDRSS_PHY_160_DATA 0x00000000 +#define DDRSS_PHY_161_DATA 0x00000000 +#define DDRSS_PHY_162_DATA 0x00000000 +#define DDRSS_PHY_163_DATA 0x00000000 +#define DDRSS_PHY_164_DATA 0x00000000 +#define DDRSS_PHY_165_DATA 0x00000000 +#define DDRSS_PHY_166_DATA 0x00000000 +#define DDRSS_PHY_167_DATA 0x00000000 +#define DDRSS_PHY_168_DATA 0x00000000 +#define DDRSS_PHY_169_DATA 0x00000000 +#define DDRSS_PHY_170_DATA 0x00000000 +#define DDRSS_PHY_171_DATA 0x00000000 +#define DDRSS_PHY_172_DATA 0x00000000 +#define DDRSS_PHY_173_DATA 0x00000000 +#define DDRSS_PHY_174_DATA 0x00000000 +#define DDRSS_PHY_175_DATA 0x00000000 +#define DDRSS_PHY_176_DATA 0x00000000 +#define DDRSS_PHY_177_DATA 0x00000000 +#define DDRSS_PHY_178_DATA 0x00000000 +#define DDRSS_PHY_179_DATA 0x00000000 +#define DDRSS_PHY_180_DATA 0x00000000 +#define DDRSS_PHY_181_DATA 0x00000000 +#define DDRSS_PHY_182_DATA 0x00000000 +#define DDRSS_PHY_183_DATA 0x00000000 +#define DDRSS_PHY_184_DATA 0x00000000 +#define DDRSS_PHY_185_DATA 0x00000000 +#define DDRSS_PHY_186_DATA 0x00000000 +#define DDRSS_PHY_187_DATA 0x00000000 +#define DDRSS_PHY_188_DATA 0x00000000 +#define DDRSS_PHY_189_DATA 0x00000000 +#define DDRSS_PHY_190_DATA 0x00000000 +#define DDRSS_PHY_191_DATA 0x00000000 +#define DDRSS_PHY_192_DATA 0x00000000 +#define DDRSS_PHY_193_DATA 0x00000000 +#define DDRSS_PHY_194_DATA 0x00000000 +#define DDRSS_PHY_195_DATA 0x00000000 +#define DDRSS_PHY_196_DATA 0x00000000 +#define DDRSS_PHY_197_DATA 0x00000000 +#define DDRSS_PHY_198_DATA 0x00000000 +#define DDRSS_PHY_199_DATA 0x00000000 +#define DDRSS_PHY_200_DATA 0x00000000 +#define DDRSS_PHY_201_DATA 0x00000000 +#define DDRSS_PHY_202_DATA 0x00000000 +#define DDRSS_PHY_203_DATA 0x00000000 +#define DDRSS_PHY_204_DATA 0x00000000 +#define DDRSS_PHY_205_DATA 0x00000000 +#define DDRSS_PHY_206_DATA 0x00000000 +#define DDRSS_PHY_207_DATA 0x00000000 +#define DDRSS_PHY_208_DATA 0x00000000 +#define DDRSS_PHY_209_DATA 0x00000000 +#define DDRSS_PHY_210_DATA 0x00000000 +#define DDRSS_PHY_211_DATA 0x00000000 +#define DDRSS_PHY_212_DATA 0x00000000 +#define DDRSS_PHY_213_DATA 0x00000000 +#define DDRSS_PHY_214_DATA 0x00000000 +#define DDRSS_PHY_215_DATA 0x00000000 +#define DDRSS_PHY_216_DATA 0x00000000 +#define DDRSS_PHY_217_DATA 0x00000000 +#define DDRSS_PHY_218_DATA 0x00000000 +#define DDRSS_PHY_219_DATA 0x00000000 +#define DDRSS_PHY_220_DATA 0x00000000 +#define DDRSS_PHY_221_DATA 0x00000000 +#define DDRSS_PHY_222_DATA 0x00000000 +#define DDRSS_PHY_223_DATA 0x00000000 +#define DDRSS_PHY_224_DATA 0x00000000 +#define DDRSS_PHY_225_DATA 0x00000000 +#define DDRSS_PHY_226_DATA 0x00000000 +#define DDRSS_PHY_227_DATA 0x00000000 +#define DDRSS_PHY_228_DATA 0x00000000 +#define DDRSS_PHY_229_DATA 0x00000000 +#define DDRSS_PHY_230_DATA 0x00000000 +#define DDRSS_PHY_231_DATA 0x00000000 +#define DDRSS_PHY_232_DATA 0x00000000 +#define DDRSS_PHY_233_DATA 0x00000000 +#define DDRSS_PHY_234_DATA 0x00000000 +#define DDRSS_PHY_235_DATA 0x00000000 +#define DDRSS_PHY_236_DATA 0x00000000 +#define DDRSS_PHY_237_DATA 0x00000000 +#define DDRSS_PHY_238_DATA 0x00000000 +#define DDRSS_PHY_239_DATA 0x00000000 +#define DDRSS_PHY_240_DATA 0x00000000 +#define DDRSS_PHY_241_DATA 0x00000000 +#define DDRSS_PHY_242_DATA 0x00000000 +#define DDRSS_PHY_243_DATA 0x00000000 +#define DDRSS_PHY_244_DATA 0x00000000 +#define DDRSS_PHY_245_DATA 0x00000000 +#define DDRSS_PHY_246_DATA 0x00000000 +#define DDRSS_PHY_247_DATA 0x00000000 +#define DDRSS_PHY_248_DATA 0x00000000 +#define DDRSS_PHY_249_DATA 0x00000000 +#define DDRSS_PHY_250_DATA 0x00000000 +#define DDRSS_PHY_251_DATA 0x00000000 +#define DDRSS_PHY_252_DATA 0x00000000 +#define DDRSS_PHY_253_DATA 0x00000000 +#define DDRSS_PHY_254_DATA 0x00000000 +#define DDRSS_PHY_255_DATA 0x00000000 +#define DDRSS_PHY_256_DATA 0x04F00000 +#define DDRSS_PHY_257_DATA 0x00000000 +#define DDRSS_PHY_258_DATA 0x00030200 +#define DDRSS_PHY_259_DATA 0x00000000 +#define DDRSS_PHY_260_DATA 0x00000000 +#define DDRSS_PHY_261_DATA 0x01030000 +#define DDRSS_PHY_262_DATA 0x00010000 +#define DDRSS_PHY_263_DATA 0x01030004 +#define DDRSS_PHY_264_DATA 0x01000000 +#define DDRSS_PHY_265_DATA 0x00000000 +#define DDRSS_PHY_266_DATA 0x00000000 +#define DDRSS_PHY_267_DATA 0x00000000 +#define DDRSS_PHY_268_DATA 0x01010000 +#define DDRSS_PHY_269_DATA 0x00010000 +#define DDRSS_PHY_270_DATA 0x00C00001 +#define DDRSS_PHY_271_DATA 0x00CC0008 +#define DDRSS_PHY_272_DATA 0x00660601 +#define DDRSS_PHY_273_DATA 0x00000003 +#define DDRSS_PHY_274_DATA 0x00000000 +#define DDRSS_PHY_275_DATA 0x00000001 +#define DDRSS_PHY_276_DATA 0x0000AAAA +#define DDRSS_PHY_277_DATA 0x00005555 +#define DDRSS_PHY_278_DATA 0x0000B5B5 +#define DDRSS_PHY_279_DATA 0x00004A4A +#define DDRSS_PHY_280_DATA 0x00005656 +#define DDRSS_PHY_281_DATA 0x0000A9A9 +#define DDRSS_PHY_282_DATA 0x0000B7B7 +#define DDRSS_PHY_283_DATA 0x00004848 +#define DDRSS_PHY_284_DATA 0x00000000 +#define DDRSS_PHY_285_DATA 0x00000000 +#define DDRSS_PHY_286_DATA 0x08000000 +#define DDRSS_PHY_287_DATA 0x0F000008 +#define DDRSS_PHY_288_DATA 0x00000F0F +#define DDRSS_PHY_289_DATA 0x00E4E400 +#define DDRSS_PHY_290_DATA 0x00071020 +#define DDRSS_PHY_291_DATA 0x000C0020 +#define DDRSS_PHY_292_DATA 0x00062000 +#define DDRSS_PHY_293_DATA 0x00000000 +#define DDRSS_PHY_294_DATA 0x55555555 +#define DDRSS_PHY_295_DATA 0xAAAAAAAA +#define DDRSS_PHY_296_DATA 0x55555555 +#define DDRSS_PHY_297_DATA 0xAAAAAAAA +#define DDRSS_PHY_298_DATA 0x00005555 +#define DDRSS_PHY_299_DATA 0x01000100 +#define DDRSS_PHY_300_DATA 0x00800180 +#define DDRSS_PHY_301_DATA 0x00000000 +#define DDRSS_PHY_302_DATA 0x00000000 +#define DDRSS_PHY_303_DATA 0x00000000 +#define DDRSS_PHY_304_DATA 0x00000000 +#define DDRSS_PHY_305_DATA 0x00000000 +#define DDRSS_PHY_306_DATA 0x00000000 +#define DDRSS_PHY_307_DATA 0x00000000 +#define DDRSS_PHY_308_DATA 0x00000000 +#define DDRSS_PHY_309_DATA 0x00000000 +#define DDRSS_PHY_310_DATA 0x00000000 +#define DDRSS_PHY_311_DATA 0x00000000 +#define DDRSS_PHY_312_DATA 0x00000000 +#define DDRSS_PHY_313_DATA 0x00000000 +#define DDRSS_PHY_314_DATA 0x00000000 +#define DDRSS_PHY_315_DATA 0x00000000 +#define DDRSS_PHY_316_DATA 0x00000000 +#define DDRSS_PHY_317_DATA 0x00000000 +#define DDRSS_PHY_318_DATA 0x00000000 +#define DDRSS_PHY_319_DATA 0x00000000 +#define DDRSS_PHY_320_DATA 0x00000000 +#define DDRSS_PHY_321_DATA 0x00000000 +#define DDRSS_PHY_322_DATA 0x00000000 +#define DDRSS_PHY_323_DATA 0x00000104 +#define DDRSS_PHY_324_DATA 0x00000000 +#define DDRSS_PHY_325_DATA 0x00000000 +#define DDRSS_PHY_326_DATA 0x00000000 +#define DDRSS_PHY_327_DATA 0x00000000 +#define DDRSS_PHY_328_DATA 0x00000000 +#define DDRSS_PHY_329_DATA 0x00000000 +#define DDRSS_PHY_330_DATA 0x081F07FF +#define DDRSS_PHY_331_DATA 0x10200080 +#define DDRSS_PHY_332_DATA 0x00000008 +#define DDRSS_PHY_333_DATA 0x00000401 +#define DDRSS_PHY_334_DATA 0x00000000 +#define DDRSS_PHY_335_DATA 0x01CC0B01 +#define DDRSS_PHY_336_DATA 0x1003CC0B +#define DDRSS_PHY_337_DATA 0x20000140 +#define DDRSS_PHY_338_DATA 0x07FF0200 +#define DDRSS_PHY_339_DATA 0x0000DD01 +#define DDRSS_PHY_340_DATA 0x00100303 +#define DDRSS_PHY_341_DATA 0x00000000 +#define DDRSS_PHY_342_DATA 0x00000000 +#define DDRSS_PHY_343_DATA 0x00031000 +#define DDRSS_PHY_344_DATA 0x00100010 +#define DDRSS_PHY_345_DATA 0x00100010 +#define DDRSS_PHY_346_DATA 0x00100010 +#define DDRSS_PHY_347_DATA 0x00100010 +#define DDRSS_PHY_348_DATA 0x02000010 +#define DDRSS_PHY_349_DATA 0x00000004 +#define DDRSS_PHY_350_DATA 0x51516042 +#define DDRSS_PHY_351_DATA 0x31C06000 +#define DDRSS_PHY_352_DATA 0x07AB0340 +#define DDRSS_PHY_353_DATA 0x00C0C001 +#define DDRSS_PHY_354_DATA 0x0B000000 +#define DDRSS_PHY_355_DATA 0x000B0A0A +#define DDRSS_PHY_356_DATA 0x42100010 +#define DDRSS_PHY_357_DATA 0x010C073E +#define DDRSS_PHY_358_DATA 0x000F0C2D +#define DDRSS_PHY_359_DATA 0x01000140 +#define DDRSS_PHY_360_DATA 0x00F50120 +#define DDRSS_PHY_361_DATA 0x00000C00 +#define DDRSS_PHY_362_DATA 0x00000299 +#define DDRSS_PHY_363_DATA 0x00030200 +#define DDRSS_PHY_364_DATA 0x02800000 +#define DDRSS_PHY_365_DATA 0x80800000 +#define DDRSS_PHY_366_DATA 0x000B2010 +#define DDRSS_PHY_367_DATA 0x65328017 +#define DDRSS_PHY_368_DATA 0x00000004 +#define DDRSS_PHY_369_DATA 0x04190419 +#define DDRSS_PHY_370_DATA 0x04190419 +#define DDRSS_PHY_371_DATA 0x04190419 +#define DDRSS_PHY_372_DATA 0x04190419 +#define DDRSS_PHY_373_DATA 0x00000419 +#define DDRSS_PHY_374_DATA 0x0000A000 +#define DDRSS_PHY_375_DATA 0x00A000A0 +#define DDRSS_PHY_376_DATA 0x00A000A0 +#define DDRSS_PHY_377_DATA 0x00A000A0 +#define DDRSS_PHY_378_DATA 0x00A000A0 +#define DDRSS_PHY_379_DATA 0x00A000A0 +#define DDRSS_PHY_380_DATA 0x00A000A0 +#define DDRSS_PHY_381_DATA 0x00A000A0 +#define DDRSS_PHY_382_DATA 0x00A000A0 +#define DDRSS_PHY_383_DATA 0x01E600A0 +#define DDRSS_PHY_384_DATA 0x01000000 +#define DDRSS_PHY_385_DATA 0x00000000 +#define DDRSS_PHY_386_DATA 0x00000000 +#define DDRSS_PHY_387_DATA 0x00080200 +#define DDRSS_PHY_388_DATA 0x00000000 +#define DDRSS_PHY_389_DATA 0x20202020 +#define DDRSS_PHY_390_DATA 0x20202020 +#define DDRSS_PHY_391_DATA 0xF0F02020 +#define DDRSS_PHY_392_DATA 0x00000000 +#define DDRSS_PHY_393_DATA 0x00000000 +#define DDRSS_PHY_394_DATA 0x00000000 +#define DDRSS_PHY_395_DATA 0x00000000 +#define DDRSS_PHY_396_DATA 0x00000000 +#define DDRSS_PHY_397_DATA 0x00000000 +#define DDRSS_PHY_398_DATA 0x00000000 +#define DDRSS_PHY_399_DATA 0x00000000 +#define DDRSS_PHY_400_DATA 0x00000000 +#define DDRSS_PHY_401_DATA 0x00000000 +#define DDRSS_PHY_402_DATA 0x00000000 +#define DDRSS_PHY_403_DATA 0x00000000 +#define DDRSS_PHY_404_DATA 0x00000000 +#define DDRSS_PHY_405_DATA 0x00000000 +#define DDRSS_PHY_406_DATA 0x00000000 +#define DDRSS_PHY_407_DATA 0x00000000 +#define DDRSS_PHY_408_DATA 0x00000000 +#define DDRSS_PHY_409_DATA 0x00000000 +#define DDRSS_PHY_410_DATA 0x00000000 +#define DDRSS_PHY_411_DATA 0x00000000 +#define DDRSS_PHY_412_DATA 0x00000000 +#define DDRSS_PHY_413_DATA 0x00000000 +#define DDRSS_PHY_414_DATA 0x00000000 +#define DDRSS_PHY_415_DATA 0x00000000 +#define DDRSS_PHY_416_DATA 0x00000000 +#define DDRSS_PHY_417_DATA 0x00000000 +#define DDRSS_PHY_418_DATA 0x00000000 +#define DDRSS_PHY_419_DATA 0x00000000 +#define DDRSS_PHY_420_DATA 0x00000000 +#define DDRSS_PHY_421_DATA 0x00000000 +#define DDRSS_PHY_422_DATA 0x00000000 +#define DDRSS_PHY_423_DATA 0x00000000 +#define DDRSS_PHY_424_DATA 0x00000000 +#define DDRSS_PHY_425_DATA 0x00000000 +#define DDRSS_PHY_426_DATA 0x00000000 +#define DDRSS_PHY_427_DATA 0x00000000 +#define DDRSS_PHY_428_DATA 0x00000000 +#define DDRSS_PHY_429_DATA 0x00000000 +#define DDRSS_PHY_430_DATA 0x00000000 +#define DDRSS_PHY_431_DATA 0x00000000 +#define DDRSS_PHY_432_DATA 0x00000000 +#define DDRSS_PHY_433_DATA 0x00000000 +#define DDRSS_PHY_434_DATA 0x00000000 +#define DDRSS_PHY_435_DATA 0x00000000 +#define DDRSS_PHY_436_DATA 0x00000000 +#define DDRSS_PHY_437_DATA 0x00000000 +#define DDRSS_PHY_438_DATA 0x00000000 +#define DDRSS_PHY_439_DATA 0x00000000 +#define DDRSS_PHY_440_DATA 0x00000000 +#define DDRSS_PHY_441_DATA 0x00000000 +#define DDRSS_PHY_442_DATA 0x00000000 +#define DDRSS_PHY_443_DATA 0x00000000 +#define DDRSS_PHY_444_DATA 0x00000000 +#define DDRSS_PHY_445_DATA 0x00000000 +#define DDRSS_PHY_446_DATA 0x00000000 +#define DDRSS_PHY_447_DATA 0x00000000 +#define DDRSS_PHY_448_DATA 0x00000000 +#define DDRSS_PHY_449_DATA 0x00000000 +#define DDRSS_PHY_450_DATA 0x00000000 +#define DDRSS_PHY_451_DATA 0x00000000 +#define DDRSS_PHY_452_DATA 0x00000000 +#define DDRSS_PHY_453_DATA 0x00000000 +#define DDRSS_PHY_454_DATA 0x00000000 +#define DDRSS_PHY_455_DATA 0x00000000 +#define DDRSS_PHY_456_DATA 0x00000000 +#define DDRSS_PHY_457_DATA 0x00000000 +#define DDRSS_PHY_458_DATA 0x00000000 +#define DDRSS_PHY_459_DATA 0x00000000 +#define DDRSS_PHY_460_DATA 0x00000000 +#define DDRSS_PHY_461_DATA 0x00000000 +#define DDRSS_PHY_462_DATA 0x00000000 +#define DDRSS_PHY_463_DATA 0x00000000 +#define DDRSS_PHY_464_DATA 0x00000000 +#define DDRSS_PHY_465_DATA 0x00000000 +#define DDRSS_PHY_466_DATA 0x00000000 +#define DDRSS_PHY_467_DATA 0x00000000 +#define DDRSS_PHY_468_DATA 0x00000000 +#define DDRSS_PHY_469_DATA 0x00000000 +#define DDRSS_PHY_470_DATA 0x00000000 +#define DDRSS_PHY_471_DATA 0x00000000 +#define DDRSS_PHY_472_DATA 0x00000000 +#define DDRSS_PHY_473_DATA 0x00000000 +#define DDRSS_PHY_474_DATA 0x00000000 +#define DDRSS_PHY_475_DATA 0x00000000 +#define DDRSS_PHY_476_DATA 0x00000000 +#define DDRSS_PHY_477_DATA 0x00000000 +#define DDRSS_PHY_478_DATA 0x00000000 +#define DDRSS_PHY_479_DATA 0x00000000 +#define DDRSS_PHY_480_DATA 0x00000000 +#define DDRSS_PHY_481_DATA 0x00000000 +#define DDRSS_PHY_482_DATA 0x00000000 +#define DDRSS_PHY_483_DATA 0x00000000 +#define DDRSS_PHY_484_DATA 0x00000000 +#define DDRSS_PHY_485_DATA 0x00000000 +#define DDRSS_PHY_486_DATA 0x00000000 +#define DDRSS_PHY_487_DATA 0x00000000 +#define DDRSS_PHY_488_DATA 0x00000000 +#define DDRSS_PHY_489_DATA 0x00000000 +#define DDRSS_PHY_490_DATA 0x00000000 +#define DDRSS_PHY_491_DATA 0x00000000 +#define DDRSS_PHY_492_DATA 0x00000000 +#define DDRSS_PHY_493_DATA 0x00000000 +#define DDRSS_PHY_494_DATA 0x00000000 +#define DDRSS_PHY_495_DATA 0x00000000 +#define DDRSS_PHY_496_DATA 0x00000000 +#define DDRSS_PHY_497_DATA 0x00000000 +#define DDRSS_PHY_498_DATA 0x00000000 +#define DDRSS_PHY_499_DATA 0x00000000 +#define DDRSS_PHY_500_DATA 0x00000000 +#define DDRSS_PHY_501_DATA 0x00000000 +#define DDRSS_PHY_502_DATA 0x00000000 +#define DDRSS_PHY_503_DATA 0x00000000 +#define DDRSS_PHY_504_DATA 0x00000000 +#define DDRSS_PHY_505_DATA 0x00000000 +#define DDRSS_PHY_506_DATA 0x00000000 +#define DDRSS_PHY_507_DATA 0x00000000 +#define DDRSS_PHY_508_DATA 0x00000000 +#define DDRSS_PHY_509_DATA 0x00000000 +#define DDRSS_PHY_510_DATA 0x00000000 +#define DDRSS_PHY_511_DATA 0x00000000 +#define DDRSS_PHY_512_DATA 0x04F00000 +#define DDRSS_PHY_513_DATA 0x00000000 +#define DDRSS_PHY_514_DATA 0x00030200 +#define DDRSS_PHY_515_DATA 0x00000000 +#define DDRSS_PHY_516_DATA 0x00000000 +#define DDRSS_PHY_517_DATA 0x01030000 +#define DDRSS_PHY_518_DATA 0x00010000 +#define DDRSS_PHY_519_DATA 0x01030004 +#define DDRSS_PHY_520_DATA 0x01000000 +#define DDRSS_PHY_521_DATA 0x00000000 +#define DDRSS_PHY_522_DATA 0x00000000 +#define DDRSS_PHY_523_DATA 0x00000000 +#define DDRSS_PHY_524_DATA 0x01010000 +#define DDRSS_PHY_525_DATA 0x00010000 +#define DDRSS_PHY_526_DATA 0x00C00001 +#define DDRSS_PHY_527_DATA 0x00CC0008 +#define DDRSS_PHY_528_DATA 0x00660601 +#define DDRSS_PHY_529_DATA 0x00000003 +#define DDRSS_PHY_530_DATA 0x00000000 +#define DDRSS_PHY_531_DATA 0x00000001 +#define DDRSS_PHY_532_DATA 0x0000AAAA +#define DDRSS_PHY_533_DATA 0x00005555 +#define DDRSS_PHY_534_DATA 0x0000B5B5 +#define DDRSS_PHY_535_DATA 0x00004A4A +#define DDRSS_PHY_536_DATA 0x00005656 +#define DDRSS_PHY_537_DATA 0x0000A9A9 +#define DDRSS_PHY_538_DATA 0x0000B7B7 +#define DDRSS_PHY_539_DATA 0x00004848 +#define DDRSS_PHY_540_DATA 0x00000000 +#define DDRSS_PHY_541_DATA 0x00000000 +#define DDRSS_PHY_542_DATA 0x08000000 +#define DDRSS_PHY_543_DATA 0x0F000008 +#define DDRSS_PHY_544_DATA 0x00000F0F +#define DDRSS_PHY_545_DATA 0x00E4E400 +#define DDRSS_PHY_546_DATA 0x00071020 +#define DDRSS_PHY_547_DATA 0x000C0020 +#define DDRSS_PHY_548_DATA 0x00062000 +#define DDRSS_PHY_549_DATA 0x00000000 +#define DDRSS_PHY_550_DATA 0x55555555 +#define DDRSS_PHY_551_DATA 0xAAAAAAAA +#define DDRSS_PHY_552_DATA 0x55555555 +#define DDRSS_PHY_553_DATA 0xAAAAAAAA +#define DDRSS_PHY_554_DATA 0x00005555 +#define DDRSS_PHY_555_DATA 0x01000100 +#define DDRSS_PHY_556_DATA 0x00800180 +#define DDRSS_PHY_557_DATA 0x00000000 +#define DDRSS_PHY_558_DATA 0x00000000 +#define DDRSS_PHY_559_DATA 0x00000000 +#define DDRSS_PHY_560_DATA 0x00000000 +#define DDRSS_PHY_561_DATA 0x00000000 +#define DDRSS_PHY_562_DATA 0x00000000 +#define DDRSS_PHY_563_DATA 0x00000000 +#define DDRSS_PHY_564_DATA 0x00000000 +#define DDRSS_PHY_565_DATA 0x00000000 +#define DDRSS_PHY_566_DATA 0x00000000 +#define DDRSS_PHY_567_DATA 0x00000000 +#define DDRSS_PHY_568_DATA 0x00000000 +#define DDRSS_PHY_569_DATA 0x00000000 +#define DDRSS_PHY_570_DATA 0x00000000 +#define DDRSS_PHY_571_DATA 0x00000000 +#define DDRSS_PHY_572_DATA 0x00000000 +#define DDRSS_PHY_573_DATA 0x00000000 +#define DDRSS_PHY_574_DATA 0x00000000 +#define DDRSS_PHY_575_DATA 0x00000000 +#define DDRSS_PHY_576_DATA 0x00000000 +#define DDRSS_PHY_577_DATA 0x00000000 +#define DDRSS_PHY_578_DATA 0x00000000 +#define DDRSS_PHY_579_DATA 0x00000104 +#define DDRSS_PHY_580_DATA 0x00000000 +#define DDRSS_PHY_581_DATA 0x00000000 +#define DDRSS_PHY_582_DATA 0x00000000 +#define DDRSS_PHY_583_DATA 0x00000000 +#define DDRSS_PHY_584_DATA 0x00000000 +#define DDRSS_PHY_585_DATA 0x00000000 +#define DDRSS_PHY_586_DATA 0x081F07FF +#define DDRSS_PHY_587_DATA 0x10200080 +#define DDRSS_PHY_588_DATA 0x00000008 +#define DDRSS_PHY_589_DATA 0x00000401 +#define DDRSS_PHY_590_DATA 0x00000000 +#define DDRSS_PHY_591_DATA 0x01CC0B01 +#define DDRSS_PHY_592_DATA 0x1003CC0B +#define DDRSS_PHY_593_DATA 0x20000140 +#define DDRSS_PHY_594_DATA 0x07FF0200 +#define DDRSS_PHY_595_DATA 0x0000DD01 +#define DDRSS_PHY_596_DATA 0x00100303 +#define DDRSS_PHY_597_DATA 0x00000000 +#define DDRSS_PHY_598_DATA 0x00000000 +#define DDRSS_PHY_599_DATA 0x00031000 +#define DDRSS_PHY_600_DATA 0x00100010 +#define DDRSS_PHY_601_DATA 0x00100010 +#define DDRSS_PHY_602_DATA 0x00100010 +#define DDRSS_PHY_603_DATA 0x00100010 +#define DDRSS_PHY_604_DATA 0x02000010 +#define DDRSS_PHY_605_DATA 0x00000004 +#define DDRSS_PHY_606_DATA 0x51516042 +#define DDRSS_PHY_607_DATA 0x31C06000 +#define DDRSS_PHY_608_DATA 0x07AB0340 +#define DDRSS_PHY_609_DATA 0x00C0C001 +#define DDRSS_PHY_610_DATA 0x0B000000 +#define DDRSS_PHY_611_DATA 0x000B0A0A +#define DDRSS_PHY_612_DATA 0x42100010 +#define DDRSS_PHY_613_DATA 0x010C073E +#define DDRSS_PHY_614_DATA 0x000F0C2D +#define DDRSS_PHY_615_DATA 0x01000140 +#define DDRSS_PHY_616_DATA 0x00F50120 +#define DDRSS_PHY_617_DATA 0x00000C00 +#define DDRSS_PHY_618_DATA 0x00000299 +#define DDRSS_PHY_619_DATA 0x00030200 +#define DDRSS_PHY_620_DATA 0x02800000 +#define DDRSS_PHY_621_DATA 0x80800000 +#define DDRSS_PHY_622_DATA 0x000B2010 +#define DDRSS_PHY_623_DATA 0x78610245 +#define DDRSS_PHY_624_DATA 0x00000003 +#define DDRSS_PHY_625_DATA 0x04190419 +#define DDRSS_PHY_626_DATA 0x04190419 +#define DDRSS_PHY_627_DATA 0x04190419 +#define DDRSS_PHY_628_DATA 0x04190419 +#define DDRSS_PHY_629_DATA 0x00000419 +#define DDRSS_PHY_630_DATA 0x0000A000 +#define DDRSS_PHY_631_DATA 0x00A000A0 +#define DDRSS_PHY_632_DATA 0x00A000A0 +#define DDRSS_PHY_633_DATA 0x00A000A0 +#define DDRSS_PHY_634_DATA 0x00A000A0 +#define DDRSS_PHY_635_DATA 0x00A000A0 +#define DDRSS_PHY_636_DATA 0x00A000A0 +#define DDRSS_PHY_637_DATA 0x00A000A0 +#define DDRSS_PHY_638_DATA 0x00A000A0 +#define DDRSS_PHY_639_DATA 0x01E600A0 +#define DDRSS_PHY_640_DATA 0x01000000 +#define DDRSS_PHY_641_DATA 0x00000000 +#define DDRSS_PHY_642_DATA 0x00000000 +#define DDRSS_PHY_643_DATA 0x00080200 +#define DDRSS_PHY_644_DATA 0x00000000 +#define DDRSS_PHY_645_DATA 0x20202020 +#define DDRSS_PHY_646_DATA 0x20202020 +#define DDRSS_PHY_647_DATA 0xF0F02020 +#define DDRSS_PHY_648_DATA 0x00000000 +#define DDRSS_PHY_649_DATA 0x00000000 +#define DDRSS_PHY_650_DATA 0x00000000 +#define DDRSS_PHY_651_DATA 0x00000000 +#define DDRSS_PHY_652_DATA 0x00000000 +#define DDRSS_PHY_653_DATA 0x00000000 +#define DDRSS_PHY_654_DATA 0x00000000 +#define DDRSS_PHY_655_DATA 0x00000000 +#define DDRSS_PHY_656_DATA 0x00000000 +#define DDRSS_PHY_657_DATA 0x00000000 +#define DDRSS_PHY_658_DATA 0x00000000 +#define DDRSS_PHY_659_DATA 0x00000000 +#define DDRSS_PHY_660_DATA 0x00000000 +#define DDRSS_PHY_661_DATA 0x00000000 +#define DDRSS_PHY_662_DATA 0x00000000 +#define DDRSS_PHY_663_DATA 0x00000000 +#define DDRSS_PHY_664_DATA 0x00000000 +#define DDRSS_PHY_665_DATA 0x00000000 +#define DDRSS_PHY_666_DATA 0x00000000 +#define DDRSS_PHY_667_DATA 0x00000000 +#define DDRSS_PHY_668_DATA 0x00000000 +#define DDRSS_PHY_669_DATA 0x00000000 +#define DDRSS_PHY_670_DATA 0x00000000 +#define DDRSS_PHY_671_DATA 0x00000000 +#define DDRSS_PHY_672_DATA 0x00000000 +#define DDRSS_PHY_673_DATA 0x00000000 +#define DDRSS_PHY_674_DATA 0x00000000 +#define DDRSS_PHY_675_DATA 0x00000000 +#define DDRSS_PHY_676_DATA 0x00000000 +#define DDRSS_PHY_677_DATA 0x00000000 +#define DDRSS_PHY_678_DATA 0x00000000 +#define DDRSS_PHY_679_DATA 0x00000000 +#define DDRSS_PHY_680_DATA 0x00000000 +#define DDRSS_PHY_681_DATA 0x00000000 +#define DDRSS_PHY_682_DATA 0x00000000 +#define DDRSS_PHY_683_DATA 0x00000000 +#define DDRSS_PHY_684_DATA 0x00000000 +#define DDRSS_PHY_685_DATA 0x00000000 +#define DDRSS_PHY_686_DATA 0x00000000 +#define DDRSS_PHY_687_DATA 0x00000000 +#define DDRSS_PHY_688_DATA 0x00000000 +#define DDRSS_PHY_689_DATA 0x00000000 +#define DDRSS_PHY_690_DATA 0x00000000 +#define DDRSS_PHY_691_DATA 0x00000000 +#define DDRSS_PHY_692_DATA 0x00000000 +#define DDRSS_PHY_693_DATA 0x00000000 +#define DDRSS_PHY_694_DATA 0x00000000 +#define DDRSS_PHY_695_DATA 0x00000000 +#define DDRSS_PHY_696_DATA 0x00000000 +#define DDRSS_PHY_697_DATA 0x00000000 +#define DDRSS_PHY_698_DATA 0x00000000 +#define DDRSS_PHY_699_DATA 0x00000000 +#define DDRSS_PHY_700_DATA 0x00000000 +#define DDRSS_PHY_701_DATA 0x00000000 +#define DDRSS_PHY_702_DATA 0x00000000 +#define DDRSS_PHY_703_DATA 0x00000000 +#define DDRSS_PHY_704_DATA 0x00000000 +#define DDRSS_PHY_705_DATA 0x00000000 +#define DDRSS_PHY_706_DATA 0x00000000 +#define DDRSS_PHY_707_DATA 0x00000000 +#define DDRSS_PHY_708_DATA 0x00000000 +#define DDRSS_PHY_709_DATA 0x00000000 +#define DDRSS_PHY_710_DATA 0x00000000 +#define DDRSS_PHY_711_DATA 0x00000000 +#define DDRSS_PHY_712_DATA 0x00000000 +#define DDRSS_PHY_713_DATA 0x00000000 +#define DDRSS_PHY_714_DATA 0x00000000 +#define DDRSS_PHY_715_DATA 0x00000000 +#define DDRSS_PHY_716_DATA 0x00000000 +#define DDRSS_PHY_717_DATA 0x00000000 +#define DDRSS_PHY_718_DATA 0x00000000 +#define DDRSS_PHY_719_DATA 0x00000000 +#define DDRSS_PHY_720_DATA 0x00000000 +#define DDRSS_PHY_721_DATA 0x00000000 +#define DDRSS_PHY_722_DATA 0x00000000 +#define DDRSS_PHY_723_DATA 0x00000000 +#define DDRSS_PHY_724_DATA 0x00000000 +#define DDRSS_PHY_725_DATA 0x00000000 +#define DDRSS_PHY_726_DATA 0x00000000 +#define DDRSS_PHY_727_DATA 0x00000000 +#define DDRSS_PHY_728_DATA 0x00000000 +#define DDRSS_PHY_729_DATA 0x00000000 +#define DDRSS_PHY_730_DATA 0x00000000 +#define DDRSS_PHY_731_DATA 0x00000000 +#define DDRSS_PHY_732_DATA 0x00000000 +#define DDRSS_PHY_733_DATA 0x00000000 +#define DDRSS_PHY_734_DATA 0x00000000 +#define DDRSS_PHY_735_DATA 0x00000000 +#define DDRSS_PHY_736_DATA 0x00000000 +#define DDRSS_PHY_737_DATA 0x00000000 +#define DDRSS_PHY_738_DATA 0x00000000 +#define DDRSS_PHY_739_DATA 0x00000000 +#define DDRSS_PHY_740_DATA 0x00000000 +#define DDRSS_PHY_741_DATA 0x00000000 +#define DDRSS_PHY_742_DATA 0x00000000 +#define DDRSS_PHY_743_DATA 0x00000000 +#define DDRSS_PHY_744_DATA 0x00000000 +#define DDRSS_PHY_745_DATA 0x00000000 +#define DDRSS_PHY_746_DATA 0x00000000 +#define DDRSS_PHY_747_DATA 0x00000000 +#define DDRSS_PHY_748_DATA 0x00000000 +#define DDRSS_PHY_749_DATA 0x00000000 +#define DDRSS_PHY_750_DATA 0x00000000 +#define DDRSS_PHY_751_DATA 0x00000000 +#define DDRSS_PHY_752_DATA 0x00000000 +#define DDRSS_PHY_753_DATA 0x00000000 +#define DDRSS_PHY_754_DATA 0x00000000 +#define DDRSS_PHY_755_DATA 0x00000000 +#define DDRSS_PHY_756_DATA 0x00000000 +#define DDRSS_PHY_757_DATA 0x00000000 +#define DDRSS_PHY_758_DATA 0x00000000 +#define DDRSS_PHY_759_DATA 0x00000000 +#define DDRSS_PHY_760_DATA 0x00000000 +#define DDRSS_PHY_761_DATA 0x00000000 +#define DDRSS_PHY_762_DATA 0x00000000 +#define DDRSS_PHY_763_DATA 0x00000000 +#define DDRSS_PHY_764_DATA 0x00000000 +#define DDRSS_PHY_765_DATA 0x00000000 +#define DDRSS_PHY_766_DATA 0x00000000 +#define DDRSS_PHY_767_DATA 0x00000000 +#define DDRSS_PHY_768_DATA 0x04F00000 +#define DDRSS_PHY_769_DATA 0x00000000 +#define DDRSS_PHY_770_DATA 0x00030200 +#define DDRSS_PHY_771_DATA 0x00000000 +#define DDRSS_PHY_772_DATA 0x00000000 +#define DDRSS_PHY_773_DATA 0x01030000 +#define DDRSS_PHY_774_DATA 0x00010000 +#define DDRSS_PHY_775_DATA 0x01030004 +#define DDRSS_PHY_776_DATA 0x01000000 +#define DDRSS_PHY_777_DATA 0x00000000 +#define DDRSS_PHY_778_DATA 0x00000000 +#define DDRSS_PHY_779_DATA 0x00000000 +#define DDRSS_PHY_780_DATA 0x01010000 +#define DDRSS_PHY_781_DATA 0x00010000 +#define DDRSS_PHY_782_DATA 0x00C00001 +#define DDRSS_PHY_783_DATA 0x00CC0008 +#define DDRSS_PHY_784_DATA 0x00660601 +#define DDRSS_PHY_785_DATA 0x00000003 +#define DDRSS_PHY_786_DATA 0x00000000 +#define DDRSS_PHY_787_DATA 0x00000001 +#define DDRSS_PHY_788_DATA 0x0000AAAA +#define DDRSS_PHY_789_DATA 0x00005555 +#define DDRSS_PHY_790_DATA 0x0000B5B5 +#define DDRSS_PHY_791_DATA 0x00004A4A +#define DDRSS_PHY_792_DATA 0x00005656 +#define DDRSS_PHY_793_DATA 0x0000A9A9 +#define DDRSS_PHY_794_DATA 0x0000B7B7 +#define DDRSS_PHY_795_DATA 0x00004848 +#define DDRSS_PHY_796_DATA 0x00000000 +#define DDRSS_PHY_797_DATA 0x00000000 +#define DDRSS_PHY_798_DATA 0x08000000 +#define DDRSS_PHY_799_DATA 0x0F000008 +#define DDRSS_PHY_800_DATA 0x00000F0F +#define DDRSS_PHY_801_DATA 0x00E4E400 +#define DDRSS_PHY_802_DATA 0x00071020 +#define DDRSS_PHY_803_DATA 0x000C0020 +#define DDRSS_PHY_804_DATA 0x00062000 +#define DDRSS_PHY_805_DATA 0x00000000 +#define DDRSS_PHY_806_DATA 0x55555555 +#define DDRSS_PHY_807_DATA 0xAAAAAAAA +#define DDRSS_PHY_808_DATA 0x55555555 +#define DDRSS_PHY_809_DATA 0xAAAAAAAA +#define DDRSS_PHY_810_DATA 0x00005555 +#define DDRSS_PHY_811_DATA 0x01000100 +#define DDRSS_PHY_812_DATA 0x00800180 +#define DDRSS_PHY_813_DATA 0x00000001 +#define DDRSS_PHY_814_DATA 0x00000000 +#define DDRSS_PHY_815_DATA 0x00000000 +#define DDRSS_PHY_816_DATA 0x00000000 +#define DDRSS_PHY_817_DATA 0x00000000 +#define DDRSS_PHY_818_DATA 0x00000000 +#define DDRSS_PHY_819_DATA 0x00000000 +#define DDRSS_PHY_820_DATA 0x00000000 +#define DDRSS_PHY_821_DATA 0x00000000 +#define DDRSS_PHY_822_DATA 0x00000000 +#define DDRSS_PHY_823_DATA 0x00000000 +#define DDRSS_PHY_824_DATA 0x00000000 +#define DDRSS_PHY_825_DATA 0x00000000 +#define DDRSS_PHY_826_DATA 0x00000000 +#define DDRSS_PHY_827_DATA 0x00000000 +#define DDRSS_PHY_828_DATA 0x00000000 +#define DDRSS_PHY_829_DATA 0x00000000 +#define DDRSS_PHY_830_DATA 0x00000000 +#define DDRSS_PHY_831_DATA 0x00000000 +#define DDRSS_PHY_832_DATA 0x00000000 +#define DDRSS_PHY_833_DATA 0x00000000 +#define DDRSS_PHY_834_DATA 0x00000000 +#define DDRSS_PHY_835_DATA 0x00000104 +#define DDRSS_PHY_836_DATA 0x00000000 +#define DDRSS_PHY_837_DATA 0x00000000 +#define DDRSS_PHY_838_DATA 0x00000000 +#define DDRSS_PHY_839_DATA 0x00000000 +#define DDRSS_PHY_840_DATA 0x00000000 +#define DDRSS_PHY_841_DATA 0x00000000 +#define DDRSS_PHY_842_DATA 0x081F07FF +#define DDRSS_PHY_843_DATA 0x10200080 +#define DDRSS_PHY_844_DATA 0x00000008 +#define DDRSS_PHY_845_DATA 0x00000401 +#define DDRSS_PHY_846_DATA 0x00000000 +#define DDRSS_PHY_847_DATA 0x01CC0B01 +#define DDRSS_PHY_848_DATA 0x1003CC0B +#define DDRSS_PHY_849_DATA 0x20000140 +#define DDRSS_PHY_850_DATA 0x07FF0200 +#define DDRSS_PHY_851_DATA 0x0000DD01 +#define DDRSS_PHY_852_DATA 0x00100303 +#define DDRSS_PHY_853_DATA 0x00000000 +#define DDRSS_PHY_854_DATA 0x00000000 +#define DDRSS_PHY_855_DATA 0x00031000 +#define DDRSS_PHY_856_DATA 0x00100010 +#define DDRSS_PHY_857_DATA 0x00100010 +#define DDRSS_PHY_858_DATA 0x00100010 +#define DDRSS_PHY_859_DATA 0x00100010 +#define DDRSS_PHY_860_DATA 0x02000010 +#define DDRSS_PHY_861_DATA 0x00000004 +#define DDRSS_PHY_862_DATA 0x51516042 +#define DDRSS_PHY_863_DATA 0x31C06000 +#define DDRSS_PHY_864_DATA 0x07AB0340 +#define DDRSS_PHY_865_DATA 0x00C0C001 +#define DDRSS_PHY_866_DATA 0x0B000000 +#define DDRSS_PHY_867_DATA 0x000B0A0A +#define DDRSS_PHY_868_DATA 0x42100010 +#define DDRSS_PHY_869_DATA 0x010C073E +#define DDRSS_PHY_870_DATA 0x000F0C2D +#define DDRSS_PHY_871_DATA 0x01000140 +#define DDRSS_PHY_872_DATA 0x00F50120 +#define DDRSS_PHY_873_DATA 0x00000C00 +#define DDRSS_PHY_874_DATA 0x00000299 +#define DDRSS_PHY_875_DATA 0x00030200 +#define DDRSS_PHY_876_DATA 0x02800000 +#define DDRSS_PHY_877_DATA 0x80800000 +#define DDRSS_PHY_878_DATA 0x000B2010 +#define DDRSS_PHY_879_DATA 0x01462358 +#define DDRSS_PHY_880_DATA 0x00000007 +#define DDRSS_PHY_881_DATA 0x04190419 +#define DDRSS_PHY_882_DATA 0x04190419 +#define DDRSS_PHY_883_DATA 0x04190419 +#define DDRSS_PHY_884_DATA 0x04190419 +#define DDRSS_PHY_885_DATA 0x00000419 +#define DDRSS_PHY_886_DATA 0x0000A000 +#define DDRSS_PHY_887_DATA 0x00A000A0 +#define DDRSS_PHY_888_DATA 0x00A000A0 +#define DDRSS_PHY_889_DATA 0x00A000A0 +#define DDRSS_PHY_890_DATA 0x00A000A0 +#define DDRSS_PHY_891_DATA 0x00A000A0 +#define DDRSS_PHY_892_DATA 0x00A000A0 +#define DDRSS_PHY_893_DATA 0x00A000A0 +#define DDRSS_PHY_894_DATA 0x00A000A0 +#define DDRSS_PHY_895_DATA 0x01E600A0 +#define DDRSS_PHY_896_DATA 0x01000000 +#define DDRSS_PHY_897_DATA 0x00000000 +#define DDRSS_PHY_898_DATA 0x00000000 +#define DDRSS_PHY_899_DATA 0x00080200 +#define DDRSS_PHY_900_DATA 0x00000000 +#define DDRSS_PHY_901_DATA 0x20202020 +#define DDRSS_PHY_902_DATA 0x20202020 +#define DDRSS_PHY_903_DATA 0xF0F02020 +#define DDRSS_PHY_904_DATA 0x00000000 +#define DDRSS_PHY_905_DATA 0x00000000 +#define DDRSS_PHY_906_DATA 0x00000000 +#define DDRSS_PHY_907_DATA 0x00000000 +#define DDRSS_PHY_908_DATA 0x00000000 +#define DDRSS_PHY_909_DATA 0x00000000 +#define DDRSS_PHY_910_DATA 0x00000000 +#define DDRSS_PHY_911_DATA 0x00000000 +#define DDRSS_PHY_912_DATA 0x00000000 +#define DDRSS_PHY_913_DATA 0x00000000 +#define DDRSS_PHY_914_DATA 0x00000000 +#define DDRSS_PHY_915_DATA 0x00000000 +#define DDRSS_PHY_916_DATA 0x00000000 +#define DDRSS_PHY_917_DATA 0x00000000 +#define DDRSS_PHY_918_DATA 0x00000000 +#define DDRSS_PHY_919_DATA 0x00000000 +#define DDRSS_PHY_920_DATA 0x00000000 +#define DDRSS_PHY_921_DATA 0x00000000 +#define DDRSS_PHY_922_DATA 0x00000000 +#define DDRSS_PHY_923_DATA 0x00000000 +#define DDRSS_PHY_924_DATA 0x00000000 +#define DDRSS_PHY_925_DATA 0x00000000 +#define DDRSS_PHY_926_DATA 0x00000000 +#define DDRSS_PHY_927_DATA 0x00000000 +#define DDRSS_PHY_928_DATA 0x00000000 +#define DDRSS_PHY_929_DATA 0x00000000 +#define DDRSS_PHY_930_DATA 0x00000000 +#define DDRSS_PHY_931_DATA 0x00000000 +#define DDRSS_PHY_932_DATA 0x00000000 +#define DDRSS_PHY_933_DATA 0x00000000 +#define DDRSS_PHY_934_DATA 0x00000000 +#define DDRSS_PHY_935_DATA 0x00000000 +#define DDRSS_PHY_936_DATA 0x00000000 +#define DDRSS_PHY_937_DATA 0x00000000 +#define DDRSS_PHY_938_DATA 0x00000000 +#define DDRSS_PHY_939_DATA 0x00000000 +#define DDRSS_PHY_940_DATA 0x00000000 +#define DDRSS_PHY_941_DATA 0x00000000 +#define DDRSS_PHY_942_DATA 0x00000000 +#define DDRSS_PHY_943_DATA 0x00000000 +#define DDRSS_PHY_944_DATA 0x00000000 +#define DDRSS_PHY_945_DATA 0x00000000 +#define DDRSS_PHY_946_DATA 0x00000000 +#define DDRSS_PHY_947_DATA 0x00000000 +#define DDRSS_PHY_948_DATA 0x00000000 +#define DDRSS_PHY_949_DATA 0x00000000 +#define DDRSS_PHY_950_DATA 0x00000000 +#define DDRSS_PHY_951_DATA 0x00000000 +#define DDRSS_PHY_952_DATA 0x00000000 +#define DDRSS_PHY_953_DATA 0x00000000 +#define DDRSS_PHY_954_DATA 0x00000000 +#define DDRSS_PHY_955_DATA 0x00000000 +#define DDRSS_PHY_956_DATA 0x00000000 +#define DDRSS_PHY_957_DATA 0x00000000 +#define DDRSS_PHY_958_DATA 0x00000000 +#define DDRSS_PHY_959_DATA 0x00000000 +#define DDRSS_PHY_960_DATA 0x00000000 +#define DDRSS_PHY_961_DATA 0x00000000 +#define DDRSS_PHY_962_DATA 0x00000000 +#define DDRSS_PHY_963_DATA 0x00000000 +#define DDRSS_PHY_964_DATA 0x00000000 +#define DDRSS_PHY_965_DATA 0x00000000 +#define DDRSS_PHY_966_DATA 0x00000000 +#define DDRSS_PHY_967_DATA 0x00000000 +#define DDRSS_PHY_968_DATA 0x00000000 +#define DDRSS_PHY_969_DATA 0x00000000 +#define DDRSS_PHY_970_DATA 0x00000000 +#define DDRSS_PHY_971_DATA 0x00000000 +#define DDRSS_PHY_972_DATA 0x00000000 +#define DDRSS_PHY_973_DATA 0x00000000 +#define DDRSS_PHY_974_DATA 0x00000000 +#define DDRSS_PHY_975_DATA 0x00000000 +#define DDRSS_PHY_976_DATA 0x00000000 +#define DDRSS_PHY_977_DATA 0x00000000 +#define DDRSS_PHY_978_DATA 0x00000000 +#define DDRSS_PHY_979_DATA 0x00000000 +#define DDRSS_PHY_980_DATA 0x00000000 +#define DDRSS_PHY_981_DATA 0x00000000 +#define DDRSS_PHY_982_DATA 0x00000000 +#define DDRSS_PHY_983_DATA 0x00000000 +#define DDRSS_PHY_984_DATA 0x00000000 +#define DDRSS_PHY_985_DATA 0x00000000 +#define DDRSS_PHY_986_DATA 0x00000000 +#define DDRSS_PHY_987_DATA 0x00000000 +#define DDRSS_PHY_988_DATA 0x00000000 +#define DDRSS_PHY_989_DATA 0x00000000 +#define DDRSS_PHY_990_DATA 0x00000000 +#define DDRSS_PHY_991_DATA 0x00000000 +#define DDRSS_PHY_992_DATA 0x00000000 +#define DDRSS_PHY_993_DATA 0x00000000 +#define DDRSS_PHY_994_DATA 0x00000000 +#define DDRSS_PHY_995_DATA 0x00000000 +#define DDRSS_PHY_996_DATA 0x00000000 +#define DDRSS_PHY_997_DATA 0x00000000 +#define DDRSS_PHY_998_DATA 0x00000000 +#define DDRSS_PHY_999_DATA 0x00000000 +#define DDRSS_PHY_1000_DATA 0x00000000 +#define DDRSS_PHY_1001_DATA 0x00000000 +#define DDRSS_PHY_1002_DATA 0x00000000 +#define DDRSS_PHY_1003_DATA 0x00000000 +#define DDRSS_PHY_1004_DATA 0x00000000 +#define DDRSS_PHY_1005_DATA 0x00000000 +#define DDRSS_PHY_1006_DATA 0x00000000 +#define DDRSS_PHY_1007_DATA 0x00000000 +#define DDRSS_PHY_1008_DATA 0x00000000 +#define DDRSS_PHY_1009_DATA 0x00000000 +#define DDRSS_PHY_1010_DATA 0x00000000 +#define DDRSS_PHY_1011_DATA 0x00000000 +#define DDRSS_PHY_1012_DATA 0x00000000 +#define DDRSS_PHY_1013_DATA 0x00000000 +#define DDRSS_PHY_1014_DATA 0x00000000 +#define DDRSS_PHY_1015_DATA 0x00000000 +#define DDRSS_PHY_1016_DATA 0x00000000 +#define DDRSS_PHY_1017_DATA 0x00000000 +#define DDRSS_PHY_1018_DATA 0x00000000 +#define DDRSS_PHY_1019_DATA 0x00000000 +#define DDRSS_PHY_1020_DATA 0x00000000 +#define DDRSS_PHY_1021_DATA 0x00000000 +#define DDRSS_PHY_1022_DATA 0x00000000 +#define DDRSS_PHY_1023_DATA 0x00000000 +#define DDRSS_PHY_1024_DATA 0x00000000 +#define DDRSS_PHY_1025_DATA 0x00000000 +#define DDRSS_PHY_1026_DATA 0x00000000 +#define DDRSS_PHY_1027_DATA 0x00000000 +#define DDRSS_PHY_1028_DATA 0x00000000 +#define DDRSS_PHY_1029_DATA 0x00000100 +#define DDRSS_PHY_1030_DATA 0x00000200 +#define DDRSS_PHY_1031_DATA 0x00000000 +#define DDRSS_PHY_1032_DATA 0x00000000 +#define DDRSS_PHY_1033_DATA 0x00000000 +#define DDRSS_PHY_1034_DATA 0x00000000 +#define DDRSS_PHY_1035_DATA 0x00400000 +#define DDRSS_PHY_1036_DATA 0x00000080 +#define DDRSS_PHY_1037_DATA 0x00DCBA98 +#define DDRSS_PHY_1038_DATA 0x03000000 +#define DDRSS_PHY_1039_DATA 0x00200000 +#define DDRSS_PHY_1040_DATA 0x00000000 +#define DDRSS_PHY_1041_DATA 0x00000000 +#define DDRSS_PHY_1042_DATA 0x00000000 +#define DDRSS_PHY_1043_DATA 0x00000000 +#define DDRSS_PHY_1044_DATA 0x00000000 +#define DDRSS_PHY_1045_DATA 0x0000002A +#define DDRSS_PHY_1046_DATA 0x00000015 +#define DDRSS_PHY_1047_DATA 0x00000015 +#define DDRSS_PHY_1048_DATA 0x0000002A +#define DDRSS_PHY_1049_DATA 0x00000033 +#define DDRSS_PHY_1050_DATA 0x0000000C +#define DDRSS_PHY_1051_DATA 0x0000000C +#define DDRSS_PHY_1052_DATA 0x00000033 +#define DDRSS_PHY_1053_DATA 0x0A418820 +#define DDRSS_PHY_1054_DATA 0x003F0000 +#define DDRSS_PHY_1055_DATA 0x000F013F +#define DDRSS_PHY_1056_DATA 0x20202003 +#define DDRSS_PHY_1057_DATA 0x00202020 +#define DDRSS_PHY_1058_DATA 0x20008008 +#define DDRSS_PHY_1059_DATA 0x00000810 +#define DDRSS_PHY_1060_DATA 0x00000F00 +#define DDRSS_PHY_1061_DATA 0x000304CC +#define DDRSS_PHY_1062_DATA 0x03000003 +#define DDRSS_PHY_1063_DATA 0x00030000 +#define DDRSS_PHY_1064_DATA 0x00000300 +#define DDRSS_PHY_1065_DATA 0x00000300 +#define DDRSS_PHY_1066_DATA 0x00000300 +#define DDRSS_PHY_1067_DATA 0x00000300 +#define DDRSS_PHY_1068_DATA 0x42080010 +#define DDRSS_PHY_1069_DATA 0x0000803E +#define DDRSS_PHY_1070_DATA 0x00000001 +#define DDRSS_PHY_1071_DATA 0x01000002 +#define DDRSS_PHY_1072_DATA 0x00008000 +#define DDRSS_PHY_1073_DATA 0x00000000 +#define DDRSS_PHY_1074_DATA 0x00000000 +#define DDRSS_PHY_1075_DATA 0x00000000 +#define DDRSS_PHY_1076_DATA 0x00000000 +#define DDRSS_PHY_1077_DATA 0x00000000 +#define DDRSS_PHY_1078_DATA 0x00000000 +#define DDRSS_PHY_1079_DATA 0x00000000 +#define DDRSS_PHY_1080_DATA 0x00000000 +#define DDRSS_PHY_1081_DATA 0x00000000 +#define DDRSS_PHY_1082_DATA 0x00000000 +#define DDRSS_PHY_1083_DATA 0x00000000 +#define DDRSS_PHY_1084_DATA 0x00000000 +#define DDRSS_PHY_1085_DATA 0x00000000 +#define DDRSS_PHY_1086_DATA 0x00000000 +#define DDRSS_PHY_1087_DATA 0x00000000 +#define DDRSS_PHY_1088_DATA 0x00000000 +#define DDRSS_PHY_1089_DATA 0x00000000 +#define DDRSS_PHY_1090_DATA 0x00000000 +#define DDRSS_PHY_1091_DATA 0x00000000 +#define DDRSS_PHY_1092_DATA 0x00000000 +#define DDRSS_PHY_1093_DATA 0x00000000 +#define DDRSS_PHY_1094_DATA 0x00000000 +#define DDRSS_PHY_1095_DATA 0x00000000 +#define DDRSS_PHY_1096_DATA 0x00000000 +#define DDRSS_PHY_1097_DATA 0x00000000 +#define DDRSS_PHY_1098_DATA 0x00000000 +#define DDRSS_PHY_1099_DATA 0x00000000 +#define DDRSS_PHY_1100_DATA 0x00000000 +#define DDRSS_PHY_1101_DATA 0x00000000 +#define DDRSS_PHY_1102_DATA 0x00000000 +#define DDRSS_PHY_1103_DATA 0x00000000 +#define DDRSS_PHY_1104_DATA 0x00000000 +#define DDRSS_PHY_1105_DATA 0x00000000 +#define DDRSS_PHY_1106_DATA 0x00000000 +#define DDRSS_PHY_1107_DATA 0x00000000 +#define DDRSS_PHY_1108_DATA 0x00000000 +#define DDRSS_PHY_1109_DATA 0x00000000 +#define DDRSS_PHY_1110_DATA 0x00000000 +#define DDRSS_PHY_1111_DATA 0x00000000 +#define DDRSS_PHY_1112_DATA 0x00000000 +#define DDRSS_PHY_1113_DATA 0x00000000 +#define DDRSS_PHY_1114_DATA 0x00000000 +#define DDRSS_PHY_1115_DATA 0x00000000 +#define DDRSS_PHY_1116_DATA 0x00000000 +#define DDRSS_PHY_1117_DATA 0x00000000 +#define DDRSS_PHY_1118_DATA 0x00000000 +#define DDRSS_PHY_1119_DATA 0x00000000 +#define DDRSS_PHY_1120_DATA 0x00000000 +#define DDRSS_PHY_1121_DATA 0x00000000 +#define DDRSS_PHY_1122_DATA 0x00000000 +#define DDRSS_PHY_1123_DATA 0x00000000 +#define DDRSS_PHY_1124_DATA 0x00000000 +#define DDRSS_PHY_1125_DATA 0x00000000 +#define DDRSS_PHY_1126_DATA 0x00000000 +#define DDRSS_PHY_1127_DATA 0x00000000 +#define DDRSS_PHY_1128_DATA 0x00000000 +#define DDRSS_PHY_1129_DATA 0x00000000 +#define DDRSS_PHY_1130_DATA 0x00000000 +#define DDRSS_PHY_1131_DATA 0x00000000 +#define DDRSS_PHY_1132_DATA 0x00000000 +#define DDRSS_PHY_1133_DATA 0x00000000 +#define DDRSS_PHY_1134_DATA 0x00000000 +#define DDRSS_PHY_1135_DATA 0x00000000 +#define DDRSS_PHY_1136_DATA 0x00000000 +#define DDRSS_PHY_1137_DATA 0x00000000 +#define DDRSS_PHY_1138_DATA 0x00000000 +#define DDRSS_PHY_1139_DATA 0x00000000 +#define DDRSS_PHY_1140_DATA 0x00000000 +#define DDRSS_PHY_1141_DATA 0x00000000 +#define DDRSS_PHY_1142_DATA 0x00000000 +#define DDRSS_PHY_1143_DATA 0x00000000 +#define DDRSS_PHY_1144_DATA 0x00000000 +#define DDRSS_PHY_1145_DATA 0x00000000 +#define DDRSS_PHY_1146_DATA 0x00000000 +#define DDRSS_PHY_1147_DATA 0x00000000 +#define DDRSS_PHY_1148_DATA 0x00000000 +#define DDRSS_PHY_1149_DATA 0x00000000 +#define DDRSS_PHY_1150_DATA 0x00000000 +#define DDRSS_PHY_1151_DATA 0x00000000 +#define DDRSS_PHY_1152_DATA 0x00000000 +#define DDRSS_PHY_1153_DATA 0x00000000 +#define DDRSS_PHY_1154_DATA 0x00000000 +#define DDRSS_PHY_1155_DATA 0x00000000 +#define DDRSS_PHY_1156_DATA 0x00000000 +#define DDRSS_PHY_1157_DATA 0x00000000 +#define DDRSS_PHY_1158_DATA 0x00000000 +#define DDRSS_PHY_1159_DATA 0x00000000 +#define DDRSS_PHY_1160_DATA 0x00000000 +#define DDRSS_PHY_1161_DATA 0x00000000 +#define DDRSS_PHY_1162_DATA 0x00000000 +#define DDRSS_PHY_1163_DATA 0x00000000 +#define DDRSS_PHY_1164_DATA 0x00000000 +#define DDRSS_PHY_1165_DATA 0x00000000 +#define DDRSS_PHY_1166_DATA 0x00000000 +#define DDRSS_PHY_1167_DATA 0x00000000 +#define DDRSS_PHY_1168_DATA 0x00000000 +#define DDRSS_PHY_1169_DATA 0x00000000 +#define DDRSS_PHY_1170_DATA 0x00000000 +#define DDRSS_PHY_1171_DATA 0x00000000 +#define DDRSS_PHY_1172_DATA 0x00000000 +#define DDRSS_PHY_1173_DATA 0x00000000 +#define DDRSS_PHY_1174_DATA 0x00000000 +#define DDRSS_PHY_1175_DATA 0x00000000 +#define DDRSS_PHY_1176_DATA 0x00000000 +#define DDRSS_PHY_1177_DATA 0x00000000 +#define DDRSS_PHY_1178_DATA 0x00000000 +#define DDRSS_PHY_1179_DATA 0x00000000 +#define DDRSS_PHY_1180_DATA 0x00000000 +#define DDRSS_PHY_1181_DATA 0x00000000 +#define DDRSS_PHY_1182_DATA 0x00000000 +#define DDRSS_PHY_1183_DATA 0x00000000 +#define DDRSS_PHY_1184_DATA 0x00000000 +#define DDRSS_PHY_1185_DATA 0x00000000 +#define DDRSS_PHY_1186_DATA 0x00000000 +#define DDRSS_PHY_1187_DATA 0x00000000 +#define DDRSS_PHY_1188_DATA 0x00000000 +#define DDRSS_PHY_1189_DATA 0x00000000 +#define DDRSS_PHY_1190_DATA 0x00000000 +#define DDRSS_PHY_1191_DATA 0x00000000 +#define DDRSS_PHY_1192_DATA 0x00000000 +#define DDRSS_PHY_1193_DATA 0x00000000 +#define DDRSS_PHY_1194_DATA 0x00000000 +#define DDRSS_PHY_1195_DATA 0x00000000 +#define DDRSS_PHY_1196_DATA 0x00000000 +#define DDRSS_PHY_1197_DATA 0x00000000 +#define DDRSS_PHY_1198_DATA 0x00000000 +#define DDRSS_PHY_1199_DATA 0x00000000 +#define DDRSS_PHY_1200_DATA 0x00000000 +#define DDRSS_PHY_1201_DATA 0x00000000 +#define DDRSS_PHY_1202_DATA 0x00000000 +#define DDRSS_PHY_1203_DATA 0x00000000 +#define DDRSS_PHY_1204_DATA 0x00000000 +#define DDRSS_PHY_1205_DATA 0x00000000 +#define DDRSS_PHY_1206_DATA 0x00000000 +#define DDRSS_PHY_1207_DATA 0x00000000 +#define DDRSS_PHY_1208_DATA 0x00000000 +#define DDRSS_PHY_1209_DATA 0x00000000 +#define DDRSS_PHY_1210_DATA 0x00000000 +#define DDRSS_PHY_1211_DATA 0x00000000 +#define DDRSS_PHY_1212_DATA 0x00000000 +#define DDRSS_PHY_1213_DATA 0x00000000 +#define DDRSS_PHY_1214_DATA 0x00000000 +#define DDRSS_PHY_1215_DATA 0x00000000 +#define DDRSS_PHY_1216_DATA 0x00000000 +#define DDRSS_PHY_1217_DATA 0x00000000 +#define DDRSS_PHY_1218_DATA 0x00000000 +#define DDRSS_PHY_1219_DATA 0x00000000 +#define DDRSS_PHY_1220_DATA 0x00000000 +#define DDRSS_PHY_1221_DATA 0x00000000 +#define DDRSS_PHY_1222_DATA 0x00000000 +#define DDRSS_PHY_1223_DATA 0x00000000 +#define DDRSS_PHY_1224_DATA 0x00000000 +#define DDRSS_PHY_1225_DATA 0x00000000 +#define DDRSS_PHY_1226_DATA 0x00000000 +#define DDRSS_PHY_1227_DATA 0x00000000 +#define DDRSS_PHY_1228_DATA 0x00000000 +#define DDRSS_PHY_1229_DATA 0x00000000 +#define DDRSS_PHY_1230_DATA 0x00000000 +#define DDRSS_PHY_1231_DATA 0x00000000 +#define DDRSS_PHY_1232_DATA 0x00000000 +#define DDRSS_PHY_1233_DATA 0x00000000 +#define DDRSS_PHY_1234_DATA 0x00000000 +#define DDRSS_PHY_1235_DATA 0x00000000 +#define DDRSS_PHY_1236_DATA 0x00000000 +#define DDRSS_PHY_1237_DATA 0x00000000 +#define DDRSS_PHY_1238_DATA 0x00000000 +#define DDRSS_PHY_1239_DATA 0x00000000 +#define DDRSS_PHY_1240_DATA 0x00000000 +#define DDRSS_PHY_1241_DATA 0x00000000 +#define DDRSS_PHY_1242_DATA 0x00000000 +#define DDRSS_PHY_1243_DATA 0x00000000 +#define DDRSS_PHY_1244_DATA 0x00000000 +#define DDRSS_PHY_1245_DATA 0x00000000 +#define DDRSS_PHY_1246_DATA 0x00000000 +#define DDRSS_PHY_1247_DATA 0x00000000 +#define DDRSS_PHY_1248_DATA 0x00000000 +#define DDRSS_PHY_1249_DATA 0x00000000 +#define DDRSS_PHY_1250_DATA 0x00000000 +#define DDRSS_PHY_1251_DATA 0x00000000 +#define DDRSS_PHY_1252_DATA 0x00000000 +#define DDRSS_PHY_1253_DATA 0x00000000 +#define DDRSS_PHY_1254_DATA 0x00000000 +#define DDRSS_PHY_1255_DATA 0x00000000 +#define DDRSS_PHY_1256_DATA 0x00000000 +#define DDRSS_PHY_1257_DATA 0x00000000 +#define DDRSS_PHY_1258_DATA 0x00000000 +#define DDRSS_PHY_1259_DATA 0x00000000 +#define DDRSS_PHY_1260_DATA 0x00000000 +#define DDRSS_PHY_1261_DATA 0x00000000 +#define DDRSS_PHY_1262_DATA 0x00000000 +#define DDRSS_PHY_1263_DATA 0x00000000 +#define DDRSS_PHY_1264_DATA 0x00000000 +#define DDRSS_PHY_1265_DATA 0x00000000 +#define DDRSS_PHY_1266_DATA 0x00000000 +#define DDRSS_PHY_1267_DATA 0x00000000 +#define DDRSS_PHY_1268_DATA 0x00000000 +#define DDRSS_PHY_1269_DATA 0x00000000 +#define DDRSS_PHY_1270_DATA 0x00000000 +#define DDRSS_PHY_1271_DATA 0x00000000 +#define DDRSS_PHY_1272_DATA 0x00000000 +#define DDRSS_PHY_1273_DATA 0x00000000 +#define DDRSS_PHY_1274_DATA 0x00000000 +#define DDRSS_PHY_1275_DATA 0x00000000 +#define DDRSS_PHY_1276_DATA 0x00000000 +#define DDRSS_PHY_1277_DATA 0x00000000 +#define DDRSS_PHY_1278_DATA 0x00000000 +#define DDRSS_PHY_1279_DATA 0x00000000 +#define DDRSS_PHY_1280_DATA 0x00000000 +#define DDRSS_PHY_1281_DATA 0x00000000 +#define DDRSS_PHY_1282_DATA 0x00000000 +#define DDRSS_PHY_1283_DATA 0x00000000 +#define DDRSS_PHY_1284_DATA 0x00000000 +#define DDRSS_PHY_1285_DATA 0x00000100 +#define DDRSS_PHY_1286_DATA 0x00000200 +#define DDRSS_PHY_1287_DATA 0x00000000 +#define DDRSS_PHY_1288_DATA 0x00000000 +#define DDRSS_PHY_1289_DATA 0x00000000 +#define DDRSS_PHY_1290_DATA 0x00000000 +#define DDRSS_PHY_1291_DATA 0x00400000 +#define DDRSS_PHY_1292_DATA 0x00000080 +#define DDRSS_PHY_1293_DATA 0x00DCBA98 +#define DDRSS_PHY_1294_DATA 0x03000000 +#define DDRSS_PHY_1295_DATA 0x00200000 +#define DDRSS_PHY_1296_DATA 0x00000000 +#define DDRSS_PHY_1297_DATA 0x00000000 +#define DDRSS_PHY_1298_DATA 0x00000000 +#define DDRSS_PHY_1299_DATA 0x00000000 +#define DDRSS_PHY_1300_DATA 0x00000000 +#define DDRSS_PHY_1301_DATA 0x0000002A +#define DDRSS_PHY_1302_DATA 0x00000015 +#define DDRSS_PHY_1303_DATA 0x00000015 +#define DDRSS_PHY_1304_DATA 0x0000002A +#define DDRSS_PHY_1305_DATA 0x00000033 +#define DDRSS_PHY_1306_DATA 0x0000000C +#define DDRSS_PHY_1307_DATA 0x0000000C +#define DDRSS_PHY_1308_DATA 0x00000033 +#define DDRSS_PHY_1309_DATA 0x0A418820 +#define DDRSS_PHY_1310_DATA 0x00000000 +#define DDRSS_PHY_1311_DATA 0x000F0000 +#define DDRSS_PHY_1312_DATA 0x20202003 +#define DDRSS_PHY_1313_DATA 0x00202020 +#define DDRSS_PHY_1314_DATA 0x20008008 +#define DDRSS_PHY_1315_DATA 0x00000810 +#define DDRSS_PHY_1316_DATA 0x00000F00 +#define DDRSS_PHY_1317_DATA 0x000304CC +#define DDRSS_PHY_1318_DATA 0x03000003 +#define DDRSS_PHY_1319_DATA 0x00030000 +#define DDRSS_PHY_1320_DATA 0x00000300 +#define DDRSS_PHY_1321_DATA 0x00000300 +#define DDRSS_PHY_1322_DATA 0x00000300 +#define DDRSS_PHY_1323_DATA 0x00000300 +#define DDRSS_PHY_1324_DATA 0x42080010 +#define DDRSS_PHY_1325_DATA 0x0000803E +#define DDRSS_PHY_1326_DATA 0x00000001 +#define DDRSS_PHY_1327_DATA 0x01000002 +#define DDRSS_PHY_1328_DATA 0x00008000 +#define DDRSS_PHY_1329_DATA 0x00000000 +#define DDRSS_PHY_1330_DATA 0x00000000 +#define DDRSS_PHY_1331_DATA 0x00000000 +#define DDRSS_PHY_1332_DATA 0x00000000 +#define DDRSS_PHY_1333_DATA 0x00000000 +#define DDRSS_PHY_1334_DATA 0x00000000 +#define DDRSS_PHY_1335_DATA 0x00000000 +#define DDRSS_PHY_1336_DATA 0x00000000 +#define DDRSS_PHY_1337_DATA 0x00000000 +#define DDRSS_PHY_1338_DATA 0x00000000 +#define DDRSS_PHY_1339_DATA 0x00000000 +#define DDRSS_PHY_1340_DATA 0x00000000 +#define DDRSS_PHY_1341_DATA 0x00000000 +#define DDRSS_PHY_1342_DATA 0x00000000 +#define DDRSS_PHY_1343_DATA 0x00000000 +#define DDRSS_PHY_1344_DATA 0x00000000 +#define DDRSS_PHY_1345_DATA 0x00000000 +#define DDRSS_PHY_1346_DATA 0x00000000 +#define DDRSS_PHY_1347_DATA 0x00000000 +#define DDRSS_PHY_1348_DATA 0x00000000 +#define DDRSS_PHY_1349_DATA 0x00000000 +#define DDRSS_PHY_1350_DATA 0x00000000 +#define DDRSS_PHY_1351_DATA 0x00000000 +#define DDRSS_PHY_1352_DATA 0x00000000 +#define DDRSS_PHY_1353_DATA 0x00000000 +#define DDRSS_PHY_1354_DATA 0x00000000 +#define DDRSS_PHY_1355_DATA 0x00000000 +#define DDRSS_PHY_1356_DATA 0x00000000 +#define DDRSS_PHY_1357_DATA 0x00000000 +#define DDRSS_PHY_1358_DATA 0x00000000 +#define DDRSS_PHY_1359_DATA 0x00000000 +#define DDRSS_PHY_1360_DATA 0x00000000 +#define DDRSS_PHY_1361_DATA 0x00000000 +#define DDRSS_PHY_1362_DATA 0x00000000 +#define DDRSS_PHY_1363_DATA 0x00000000 +#define DDRSS_PHY_1364_DATA 0x00000000 +#define DDRSS_PHY_1365_DATA 0x00000000 +#define DDRSS_PHY_1366_DATA 0x00000000 +#define DDRSS_PHY_1367_DATA 0x00000000 +#define DDRSS_PHY_1368_DATA 0x00000000 +#define DDRSS_PHY_1369_DATA 0x00000000 +#define DDRSS_PHY_1370_DATA 0x00000000 +#define DDRSS_PHY_1371_DATA 0x00000000 +#define DDRSS_PHY_1372_DATA 0x00000000 +#define DDRSS_PHY_1373_DATA 0x00000000 +#define DDRSS_PHY_1374_DATA 0x00000000 +#define DDRSS_PHY_1375_DATA 0x00000000 +#define DDRSS_PHY_1376_DATA 0x00000000 +#define DDRSS_PHY_1377_DATA 0x00000000 +#define DDRSS_PHY_1378_DATA 0x00000000 +#define DDRSS_PHY_1379_DATA 0x00000000 +#define DDRSS_PHY_1380_DATA 0x00000000 +#define DDRSS_PHY_1381_DATA 0x00000000 +#define DDRSS_PHY_1382_DATA 0x00000000 +#define DDRSS_PHY_1383_DATA 0x00000000 +#define DDRSS_PHY_1384_DATA 0x00000000 +#define DDRSS_PHY_1385_DATA 0x00000000 +#define DDRSS_PHY_1386_DATA 0x00000000 +#define DDRSS_PHY_1387_DATA 0x00000000 +#define DDRSS_PHY_1388_DATA 0x00000000 +#define DDRSS_PHY_1389_DATA 0x00000000 +#define DDRSS_PHY_1390_DATA 0x00000000 +#define DDRSS_PHY_1391_DATA 0x00000000 +#define DDRSS_PHY_1392_DATA 0x00000000 +#define DDRSS_PHY_1393_DATA 0x00000000 +#define DDRSS_PHY_1394_DATA 0x00000000 +#define DDRSS_PHY_1395_DATA 0x00000000 +#define DDRSS_PHY_1396_DATA 0x00000000 +#define DDRSS_PHY_1397_DATA 0x00000000 +#define DDRSS_PHY_1398_DATA 0x00000000 +#define DDRSS_PHY_1399_DATA 0x00000000 +#define DDRSS_PHY_1400_DATA 0x00000000 +#define DDRSS_PHY_1401_DATA 0x00000000 +#define DDRSS_PHY_1402_DATA 0x00000000 +#define DDRSS_PHY_1403_DATA 0x00000000 +#define DDRSS_PHY_1404_DATA 0x00000000 +#define DDRSS_PHY_1405_DATA 0x00000000 +#define DDRSS_PHY_1406_DATA 0x00000000 +#define DDRSS_PHY_1407_DATA 0x00000000 +#define DDRSS_PHY_1408_DATA 0x00000000 +#define DDRSS_PHY_1409_DATA 0x00000000 +#define DDRSS_PHY_1410_DATA 0x00000000 +#define DDRSS_PHY_1411_DATA 0x00000000 +#define DDRSS_PHY_1412_DATA 0x00000000 +#define DDRSS_PHY_1413_DATA 0x00000000 +#define DDRSS_PHY_1414_DATA 0x00000000 +#define DDRSS_PHY_1415_DATA 0x00000000 +#define DDRSS_PHY_1416_DATA 0x00000000 +#define DDRSS_PHY_1417_DATA 0x00000000 +#define DDRSS_PHY_1418_DATA 0x00000000 +#define DDRSS_PHY_1419_DATA 0x00000000 +#define DDRSS_PHY_1420_DATA 0x00000000 +#define DDRSS_PHY_1421_DATA 0x00000000 +#define DDRSS_PHY_1422_DATA 0x00000000 +#define DDRSS_PHY_1423_DATA 0x00000000 +#define DDRSS_PHY_1424_DATA 0x00000000 +#define DDRSS_PHY_1425_DATA 0x00000000 +#define DDRSS_PHY_1426_DATA 0x00000000 +#define DDRSS_PHY_1427_DATA 0x00000000 +#define DDRSS_PHY_1428_DATA 0x00000000 +#define DDRSS_PHY_1429_DATA 0x00000000 +#define DDRSS_PHY_1430_DATA 0x00000000 +#define DDRSS_PHY_1431_DATA 0x00000000 +#define DDRSS_PHY_1432_DATA 0x00000000 +#define DDRSS_PHY_1433_DATA 0x00000000 +#define DDRSS_PHY_1434_DATA 0x00000000 +#define DDRSS_PHY_1435_DATA 0x00000000 +#define DDRSS_PHY_1436_DATA 0x00000000 +#define DDRSS_PHY_1437_DATA 0x00000000 +#define DDRSS_PHY_1438_DATA 0x00000000 +#define DDRSS_PHY_1439_DATA 0x00000000 +#define DDRSS_PHY_1440_DATA 0x00000000 +#define DDRSS_PHY_1441_DATA 0x00000000 +#define DDRSS_PHY_1442_DATA 0x00000000 +#define DDRSS_PHY_1443_DATA 0x00000000 +#define DDRSS_PHY_1444_DATA 0x00000000 +#define DDRSS_PHY_1445_DATA 0x00000000 +#define DDRSS_PHY_1446_DATA 0x00000000 +#define DDRSS_PHY_1447_DATA 0x00000000 +#define DDRSS_PHY_1448_DATA 0x00000000 +#define DDRSS_PHY_1449_DATA 0x00000000 +#define DDRSS_PHY_1450_DATA 0x00000000 +#define DDRSS_PHY_1451_DATA 0x00000000 +#define DDRSS_PHY_1452_DATA 0x00000000 +#define DDRSS_PHY_1453_DATA 0x00000000 +#define DDRSS_PHY_1454_DATA 0x00000000 +#define DDRSS_PHY_1455_DATA 0x00000000 +#define DDRSS_PHY_1456_DATA 0x00000000 +#define DDRSS_PHY_1457_DATA 0x00000000 +#define DDRSS_PHY_1458_DATA 0x00000000 +#define DDRSS_PHY_1459_DATA 0x00000000 +#define DDRSS_PHY_1460_DATA 0x00000000 +#define DDRSS_PHY_1461_DATA 0x00000000 +#define DDRSS_PHY_1462_DATA 0x00000000 +#define DDRSS_PHY_1463_DATA 0x00000000 +#define DDRSS_PHY_1464_DATA 0x00000000 +#define DDRSS_PHY_1465_DATA 0x00000000 +#define DDRSS_PHY_1466_DATA 0x00000000 +#define DDRSS_PHY_1467_DATA 0x00000000 +#define DDRSS_PHY_1468_DATA 0x00000000 +#define DDRSS_PHY_1469_DATA 0x00000000 +#define DDRSS_PHY_1470_DATA 0x00000000 +#define DDRSS_PHY_1471_DATA 0x00000000 +#define DDRSS_PHY_1472_DATA 0x00000000 +#define DDRSS_PHY_1473_DATA 0x00000000 +#define DDRSS_PHY_1474_DATA 0x00000000 +#define DDRSS_PHY_1475_DATA 0x00000000 +#define DDRSS_PHY_1476_DATA 0x00000000 +#define DDRSS_PHY_1477_DATA 0x00000000 +#define DDRSS_PHY_1478_DATA 0x00000000 +#define DDRSS_PHY_1479_DATA 0x00000000 +#define DDRSS_PHY_1480_DATA 0x00000000 +#define DDRSS_PHY_1481_DATA 0x00000000 +#define DDRSS_PHY_1482_DATA 0x00000000 +#define DDRSS_PHY_1483_DATA 0x00000000 +#define DDRSS_PHY_1484_DATA 0x00000000 +#define DDRSS_PHY_1485_DATA 0x00000000 +#define DDRSS_PHY_1486_DATA 0x00000000 +#define DDRSS_PHY_1487_DATA 0x00000000 +#define DDRSS_PHY_1488_DATA 0x00000000 +#define DDRSS_PHY_1489_DATA 0x00000000 +#define DDRSS_PHY_1490_DATA 0x00000000 +#define DDRSS_PHY_1491_DATA 0x00000000 +#define DDRSS_PHY_1492_DATA 0x00000000 +#define DDRSS_PHY_1493_DATA 0x00000000 +#define DDRSS_PHY_1494_DATA 0x00000000 +#define DDRSS_PHY_1495_DATA 0x00000000 +#define DDRSS_PHY_1496_DATA 0x00000000 +#define DDRSS_PHY_1497_DATA 0x00000000 +#define DDRSS_PHY_1498_DATA 0x00000000 +#define DDRSS_PHY_1499_DATA 0x00000000 +#define DDRSS_PHY_1500_DATA 0x00000000 +#define DDRSS_PHY_1501_DATA 0x00000000 +#define DDRSS_PHY_1502_DATA 0x00000000 +#define DDRSS_PHY_1503_DATA 0x00000000 +#define DDRSS_PHY_1504_DATA 0x00000000 +#define DDRSS_PHY_1505_DATA 0x00000000 +#define DDRSS_PHY_1506_DATA 0x00000000 +#define DDRSS_PHY_1507_DATA 0x00000000 +#define DDRSS_PHY_1508_DATA 0x00000000 +#define DDRSS_PHY_1509_DATA 0x00000000 +#define DDRSS_PHY_1510_DATA 0x00000000 +#define DDRSS_PHY_1511_DATA 0x00000000 +#define DDRSS_PHY_1512_DATA 0x00000000 +#define DDRSS_PHY_1513_DATA 0x00000000 +#define DDRSS_PHY_1514_DATA 0x00000000 +#define DDRSS_PHY_1515_DATA 0x00000000 +#define DDRSS_PHY_1516_DATA 0x00000000 +#define DDRSS_PHY_1517_DATA 0x00000000 +#define DDRSS_PHY_1518_DATA 0x00000000 +#define DDRSS_PHY_1519_DATA 0x00000000 +#define DDRSS_PHY_1520_DATA 0x00000000 +#define DDRSS_PHY_1521_DATA 0x00000000 +#define DDRSS_PHY_1522_DATA 0x00000000 +#define DDRSS_PHY_1523_DATA 0x00000000 +#define DDRSS_PHY_1524_DATA 0x00000000 +#define DDRSS_PHY_1525_DATA 0x00000000 +#define DDRSS_PHY_1526_DATA 0x00000000 +#define DDRSS_PHY_1527_DATA 0x00000000 +#define DDRSS_PHY_1528_DATA 0x00000000 +#define DDRSS_PHY_1529_DATA 0x00000000 +#define DDRSS_PHY_1530_DATA 0x00000000 +#define DDRSS_PHY_1531_DATA 0x00000000 +#define DDRSS_PHY_1532_DATA 0x00000000 +#define DDRSS_PHY_1533_DATA 0x00000000 +#define DDRSS_PHY_1534_DATA 0x00000000 +#define DDRSS_PHY_1535_DATA 0x00000000 +#define DDRSS_PHY_1536_DATA 0x00000000 +#define DDRSS_PHY_1537_DATA 0x00000000 +#define DDRSS_PHY_1538_DATA 0x00000000 +#define DDRSS_PHY_1539_DATA 0x00000000 +#define DDRSS_PHY_1540_DATA 0x00000000 +#define DDRSS_PHY_1541_DATA 0x00000100 +#define DDRSS_PHY_1542_DATA 0x00000200 +#define DDRSS_PHY_1543_DATA 0x00000000 +#define DDRSS_PHY_1544_DATA 0x00000000 +#define DDRSS_PHY_1545_DATA 0x00000000 +#define DDRSS_PHY_1546_DATA 0x00000000 +#define DDRSS_PHY_1547_DATA 0x00400000 +#define DDRSS_PHY_1548_DATA 0x00000080 +#define DDRSS_PHY_1549_DATA 0x00DCBA98 +#define DDRSS_PHY_1550_DATA 0x03000000 +#define DDRSS_PHY_1551_DATA 0x00200000 +#define DDRSS_PHY_1552_DATA 0x00000000 +#define DDRSS_PHY_1553_DATA 0x00000000 +#define DDRSS_PHY_1554_DATA 0x00000000 +#define DDRSS_PHY_1555_DATA 0x00000000 +#define DDRSS_PHY_1556_DATA 0x00000000 +#define DDRSS_PHY_1557_DATA 0x0000002A +#define DDRSS_PHY_1558_DATA 0x00000015 +#define DDRSS_PHY_1559_DATA 0x00000015 +#define DDRSS_PHY_1560_DATA 0x0000002A +#define DDRSS_PHY_1561_DATA 0x00000033 +#define DDRSS_PHY_1562_DATA 0x0000000C +#define DDRSS_PHY_1563_DATA 0x0000000C +#define DDRSS_PHY_1564_DATA 0x00000033 +#define DDRSS_PHY_1565_DATA 0x0A418820 +#define DDRSS_PHY_1566_DATA 0x10000000 +#define DDRSS_PHY_1567_DATA 0x000F0000 +#define DDRSS_PHY_1568_DATA 0x20202003 +#define DDRSS_PHY_1569_DATA 0x00202020 +#define DDRSS_PHY_1570_DATA 0x20008008 +#define DDRSS_PHY_1571_DATA 0x00000810 +#define DDRSS_PHY_1572_DATA 0x00000F00 +#define DDRSS_PHY_1573_DATA 0x000304CC +#define DDRSS_PHY_1574_DATA 0x03000003 +#define DDRSS_PHY_1575_DATA 0x00030000 +#define DDRSS_PHY_1576_DATA 0x00000300 +#define DDRSS_PHY_1577_DATA 0x00000300 +#define DDRSS_PHY_1578_DATA 0x00000300 +#define DDRSS_PHY_1579_DATA 0x00000300 +#define DDRSS_PHY_1580_DATA 0x42080010 +#define DDRSS_PHY_1581_DATA 0x0000803E +#define DDRSS_PHY_1582_DATA 0x00000001 +#define DDRSS_PHY_1583_DATA 0x01000002 +#define DDRSS_PHY_1584_DATA 0x00008000 +#define DDRSS_PHY_1585_DATA 0x00000000 +#define DDRSS_PHY_1586_DATA 0x00000000 +#define DDRSS_PHY_1587_DATA 0x00000000 +#define DDRSS_PHY_1588_DATA 0x00000000 +#define DDRSS_PHY_1589_DATA 0x00000000 +#define DDRSS_PHY_1590_DATA 0x00000000 +#define DDRSS_PHY_1591_DATA 0x00000000 +#define DDRSS_PHY_1592_DATA 0x00000000 +#define DDRSS_PHY_1593_DATA 0x00000000 +#define DDRSS_PHY_1594_DATA 0x00000000 +#define DDRSS_PHY_1595_DATA 0x00000000 +#define DDRSS_PHY_1596_DATA 0x00000000 +#define DDRSS_PHY_1597_DATA 0x00000000 +#define DDRSS_PHY_1598_DATA 0x00000000 +#define DDRSS_PHY_1599_DATA 0x00000000 +#define DDRSS_PHY_1600_DATA 0x00000000 +#define DDRSS_PHY_1601_DATA 0x00000000 +#define DDRSS_PHY_1602_DATA 0x00000000 +#define DDRSS_PHY_1603_DATA 0x00000000 +#define DDRSS_PHY_1604_DATA 0x00000000 +#define DDRSS_PHY_1605_DATA 0x00000000 +#define DDRSS_PHY_1606_DATA 0x00000000 +#define DDRSS_PHY_1607_DATA 0x00000000 +#define DDRSS_PHY_1608_DATA 0x00000000 +#define DDRSS_PHY_1609_DATA 0x00000000 +#define DDRSS_PHY_1610_DATA 0x00000000 +#define DDRSS_PHY_1611_DATA 0x00000000 +#define DDRSS_PHY_1612_DATA 0x00000000 +#define DDRSS_PHY_1613_DATA 0x00000000 +#define DDRSS_PHY_1614_DATA 0x00000000 +#define DDRSS_PHY_1615_DATA 0x00000000 +#define DDRSS_PHY_1616_DATA 0x00000000 +#define DDRSS_PHY_1617_DATA 0x00000000 +#define DDRSS_PHY_1618_DATA 0x00000000 +#define DDRSS_PHY_1619_DATA 0x00000000 +#define DDRSS_PHY_1620_DATA 0x00000000 +#define DDRSS_PHY_1621_DATA 0x00000000 +#define DDRSS_PHY_1622_DATA 0x00000000 +#define DDRSS_PHY_1623_DATA 0x00000000 +#define DDRSS_PHY_1624_DATA 0x00000000 +#define DDRSS_PHY_1625_DATA 0x00000000 +#define DDRSS_PHY_1626_DATA 0x00000000 +#define DDRSS_PHY_1627_DATA 0x00000000 +#define DDRSS_PHY_1628_DATA 0x00000000 +#define DDRSS_PHY_1629_DATA 0x00000000 +#define DDRSS_PHY_1630_DATA 0x00000000 +#define DDRSS_PHY_1631_DATA 0x00000000 +#define DDRSS_PHY_1632_DATA 0x00000000 +#define DDRSS_PHY_1633_DATA 0x00000000 +#define DDRSS_PHY_1634_DATA 0x00000000 +#define DDRSS_PHY_1635_DATA 0x00000000 +#define DDRSS_PHY_1636_DATA 0x00000000 +#define DDRSS_PHY_1637_DATA 0x00000000 +#define DDRSS_PHY_1638_DATA 0x00000000 +#define DDRSS_PHY_1639_DATA 0x00000000 +#define DDRSS_PHY_1640_DATA 0x00000000 +#define DDRSS_PHY_1641_DATA 0x00000000 +#define DDRSS_PHY_1642_DATA 0x00000000 +#define DDRSS_PHY_1643_DATA 0x00000000 +#define DDRSS_PHY_1644_DATA 0x00000000 +#define DDRSS_PHY_1645_DATA 0x00000000 +#define DDRSS_PHY_1646_DATA 0x00000000 +#define DDRSS_PHY_1647_DATA 0x00000000 +#define DDRSS_PHY_1648_DATA 0x00000000 +#define DDRSS_PHY_1649_DATA 0x00000000 +#define DDRSS_PHY_1650_DATA 0x00000000 +#define DDRSS_PHY_1651_DATA 0x00000000 +#define DDRSS_PHY_1652_DATA 0x00000000 +#define DDRSS_PHY_1653_DATA 0x00000000 +#define DDRSS_PHY_1654_DATA 0x00000000 +#define DDRSS_PHY_1655_DATA 0x00000000 +#define DDRSS_PHY_1656_DATA 0x00000000 +#define DDRSS_PHY_1657_DATA 0x00000000 +#define DDRSS_PHY_1658_DATA 0x00000000 +#define DDRSS_PHY_1659_DATA 0x00000000 +#define DDRSS_PHY_1660_DATA 0x00000000 +#define DDRSS_PHY_1661_DATA 0x00000000 +#define DDRSS_PHY_1662_DATA 0x00000000 +#define DDRSS_PHY_1663_DATA 0x00000000 +#define DDRSS_PHY_1664_DATA 0x00000000 +#define DDRSS_PHY_1665_DATA 0x00000000 +#define DDRSS_PHY_1666_DATA 0x00000000 +#define DDRSS_PHY_1667_DATA 0x00000000 +#define DDRSS_PHY_1668_DATA 0x00000000 +#define DDRSS_PHY_1669_DATA 0x00000000 +#define DDRSS_PHY_1670_DATA 0x00000000 +#define DDRSS_PHY_1671_DATA 0x00000000 +#define DDRSS_PHY_1672_DATA 0x00000000 +#define DDRSS_PHY_1673_DATA 0x00000000 +#define DDRSS_PHY_1674_DATA 0x00000000 +#define DDRSS_PHY_1675_DATA 0x00000000 +#define DDRSS_PHY_1676_DATA 0x00000000 +#define DDRSS_PHY_1677_DATA 0x00000000 +#define DDRSS_PHY_1678_DATA 0x00000000 +#define DDRSS_PHY_1679_DATA 0x00000000 +#define DDRSS_PHY_1680_DATA 0x00000000 +#define DDRSS_PHY_1681_DATA 0x00000000 +#define DDRSS_PHY_1682_DATA 0x00000000 +#define DDRSS_PHY_1683_DATA 0x00000000 +#define DDRSS_PHY_1684_DATA 0x00000000 +#define DDRSS_PHY_1685_DATA 0x00000000 +#define DDRSS_PHY_1686_DATA 0x00000000 +#define DDRSS_PHY_1687_DATA 0x00000000 +#define DDRSS_PHY_1688_DATA 0x00000000 +#define DDRSS_PHY_1689_DATA 0x00000000 +#define DDRSS_PHY_1690_DATA 0x00000000 +#define DDRSS_PHY_1691_DATA 0x00000000 +#define DDRSS_PHY_1692_DATA 0x00000000 +#define DDRSS_PHY_1693_DATA 0x00000000 +#define DDRSS_PHY_1694_DATA 0x00000000 +#define DDRSS_PHY_1695_DATA 0x00000000 +#define DDRSS_PHY_1696_DATA 0x00000000 +#define DDRSS_PHY_1697_DATA 0x00000000 +#define DDRSS_PHY_1698_DATA 0x00000000 +#define DDRSS_PHY_1699_DATA 0x00000000 +#define DDRSS_PHY_1700_DATA 0x00000000 +#define DDRSS_PHY_1701_DATA 0x00000000 +#define DDRSS_PHY_1702_DATA 0x00000000 +#define DDRSS_PHY_1703_DATA 0x00000000 +#define DDRSS_PHY_1704_DATA 0x00000000 +#define DDRSS_PHY_1705_DATA 0x00000000 +#define DDRSS_PHY_1706_DATA 0x00000000 +#define DDRSS_PHY_1707_DATA 0x00000000 +#define DDRSS_PHY_1708_DATA 0x00000000 +#define DDRSS_PHY_1709_DATA 0x00000000 +#define DDRSS_PHY_1710_DATA 0x00000000 +#define DDRSS_PHY_1711_DATA 0x00000000 +#define DDRSS_PHY_1712_DATA 0x00000000 +#define DDRSS_PHY_1713_DATA 0x00000000 +#define DDRSS_PHY_1714_DATA 0x00000000 +#define DDRSS_PHY_1715_DATA 0x00000000 +#define DDRSS_PHY_1716_DATA 0x00000000 +#define DDRSS_PHY_1717_DATA 0x00000000 +#define DDRSS_PHY_1718_DATA 0x00000000 +#define DDRSS_PHY_1719_DATA 0x00000000 +#define DDRSS_PHY_1720_DATA 0x00000000 +#define DDRSS_PHY_1721_DATA 0x00000000 +#define DDRSS_PHY_1722_DATA 0x00000000 +#define DDRSS_PHY_1723_DATA 0x00000000 +#define DDRSS_PHY_1724_DATA 0x00000000 +#define DDRSS_PHY_1725_DATA 0x00000000 +#define DDRSS_PHY_1726_DATA 0x00000000 +#define DDRSS_PHY_1727_DATA 0x00000000 +#define DDRSS_PHY_1728_DATA 0x00000000 +#define DDRSS_PHY_1729_DATA 0x00000000 +#define DDRSS_PHY_1730_DATA 0x00000000 +#define DDRSS_PHY_1731_DATA 0x00000000 +#define DDRSS_PHY_1732_DATA 0x00000000 +#define DDRSS_PHY_1733_DATA 0x00000000 +#define DDRSS_PHY_1734_DATA 0x00000000 +#define DDRSS_PHY_1735_DATA 0x00000000 +#define DDRSS_PHY_1736_DATA 0x00000000 +#define DDRSS_PHY_1737_DATA 0x00000000 +#define DDRSS_PHY_1738_DATA 0x00000000 +#define DDRSS_PHY_1739_DATA 0x00000000 +#define DDRSS_PHY_1740_DATA 0x00000000 +#define DDRSS_PHY_1741_DATA 0x00000000 +#define DDRSS_PHY_1742_DATA 0x00000000 +#define DDRSS_PHY_1743_DATA 0x00000000 +#define DDRSS_PHY_1744_DATA 0x00000000 +#define DDRSS_PHY_1745_DATA 0x00000000 +#define DDRSS_PHY_1746_DATA 0x00000000 +#define DDRSS_PHY_1747_DATA 0x00000000 +#define DDRSS_PHY_1748_DATA 0x00000000 +#define DDRSS_PHY_1749_DATA 0x00000000 +#define DDRSS_PHY_1750_DATA 0x00000000 +#define DDRSS_PHY_1751_DATA 0x00000000 +#define DDRSS_PHY_1752_DATA 0x00000000 +#define DDRSS_PHY_1753_DATA 0x00000000 +#define DDRSS_PHY_1754_DATA 0x00000000 +#define DDRSS_PHY_1755_DATA 0x00000000 +#define DDRSS_PHY_1756_DATA 0x00000000 +#define DDRSS_PHY_1757_DATA 0x00000000 +#define DDRSS_PHY_1758_DATA 0x00000000 +#define DDRSS_PHY_1759_DATA 0x00000000 +#define DDRSS_PHY_1760_DATA 0x00000000 +#define DDRSS_PHY_1761_DATA 0x00000000 +#define DDRSS_PHY_1762_DATA 0x00000000 +#define DDRSS_PHY_1763_DATA 0x00000000 +#define DDRSS_PHY_1764_DATA 0x00000000 +#define DDRSS_PHY_1765_DATA 0x00000000 +#define DDRSS_PHY_1766_DATA 0x00000000 +#define DDRSS_PHY_1767_DATA 0x00000000 +#define DDRSS_PHY_1768_DATA 0x00000000 +#define DDRSS_PHY_1769_DATA 0x00000000 +#define DDRSS_PHY_1770_DATA 0x00000000 +#define DDRSS_PHY_1771_DATA 0x00000000 +#define DDRSS_PHY_1772_DATA 0x00000000 +#define DDRSS_PHY_1773_DATA 0x00000000 +#define DDRSS_PHY_1774_DATA 0x00000000 +#define DDRSS_PHY_1775_DATA 0x00000000 +#define DDRSS_PHY_1776_DATA 0x00000000 +#define DDRSS_PHY_1777_DATA 0x00000000 +#define DDRSS_PHY_1778_DATA 0x00000000 +#define DDRSS_PHY_1779_DATA 0x00000000 +#define DDRSS_PHY_1780_DATA 0x00000000 +#define DDRSS_PHY_1781_DATA 0x00000000 +#define DDRSS_PHY_1782_DATA 0x00000000 +#define DDRSS_PHY_1783_DATA 0x00000000 +#define DDRSS_PHY_1784_DATA 0x00000000 +#define DDRSS_PHY_1785_DATA 0x00000000 +#define DDRSS_PHY_1786_DATA 0x00000000 +#define DDRSS_PHY_1787_DATA 0x00000000 +#define DDRSS_PHY_1788_DATA 0x00000000 +#define DDRSS_PHY_1789_DATA 0x00000000 +#define DDRSS_PHY_1790_DATA 0x00000000 +#define DDRSS_PHY_1791_DATA 0x00000000 +#define DDRSS_PHY_1792_DATA 0x00000000 +#define DDRSS_PHY_1793_DATA 0x00010100 +#define DDRSS_PHY_1794_DATA 0x00000000 +#define DDRSS_PHY_1795_DATA 0x00000000 +#define DDRSS_PHY_1796_DATA 0x00000000 +#define DDRSS_PHY_1797_DATA 0x00000000 +#define DDRSS_PHY_1798_DATA 0x00050000 +#define DDRSS_PHY_1799_DATA 0x04000000 +#define DDRSS_PHY_1800_DATA 0x00000055 +#define DDRSS_PHY_1801_DATA 0x00000000 +#define DDRSS_PHY_1802_DATA 0x00000000 +#define DDRSS_PHY_1803_DATA 0x00000000 +#define DDRSS_PHY_1804_DATA 0x00000000 +#define DDRSS_PHY_1805_DATA 0x00002001 +#define DDRSS_PHY_1806_DATA 0x00004003 +#define DDRSS_PHY_1807_DATA 0x50020028 +#define DDRSS_PHY_1808_DATA 0x01010000 +#define DDRSS_PHY_1809_DATA 0x80080001 +#define DDRSS_PHY_1810_DATA 0x10200000 +#define DDRSS_PHY_1811_DATA 0x00000008 +#define DDRSS_PHY_1812_DATA 0x00000000 +#define DDRSS_PHY_1813_DATA 0x06000000 +#define DDRSS_PHY_1814_DATA 0x010F0F0E +#define DDRSS_PHY_1815_DATA 0x00040101 +#define DDRSS_PHY_1816_DATA 0x0000010F +#define DDRSS_PHY_1817_DATA 0x00000000 +#define DDRSS_PHY_1818_DATA 0x00000064 +#define DDRSS_PHY_1819_DATA 0x00000000 +#define DDRSS_PHY_1820_DATA 0x00000000 +#define DDRSS_PHY_1821_DATA 0x0F0F0F01 +#define DDRSS_PHY_1822_DATA 0x0F0F0F02 +#define DDRSS_PHY_1823_DATA 0x0F0F0F0F +#define DDRSS_PHY_1824_DATA 0x0F0F0804 +#define DDRSS_PHY_1825_DATA 0x00800120 +#define DDRSS_PHY_1826_DATA 0x00041B42 +#define DDRSS_PHY_1827_DATA 0x00004201 +#define DDRSS_PHY_1828_DATA 0x00000000 +#define DDRSS_PHY_1829_DATA 0x00000000 +#define DDRSS_PHY_1830_DATA 0x00000000 +#define DDRSS_PHY_1831_DATA 0x00000000 +#define DDRSS_PHY_1832_DATA 0x00000000 +#define DDRSS_PHY_1833_DATA 0x00000000 +#define DDRSS_PHY_1834_DATA 0x03010100 +#define DDRSS_PHY_1835_DATA 0x00540007 +#define DDRSS_PHY_1836_DATA 0x000040A2 +#define DDRSS_PHY_1837_DATA 0x00024410 +#define DDRSS_PHY_1838_DATA 0x00004410 +#define DDRSS_PHY_1839_DATA 0x00004410 +#define DDRSS_PHY_1840_DATA 0x00004410 +#define DDRSS_PHY_1841_DATA 0x00004410 +#define DDRSS_PHY_1842_DATA 0x00004410 +#define DDRSS_PHY_1843_DATA 0x00004410 +#define DDRSS_PHY_1844_DATA 0x00004410 +#define DDRSS_PHY_1845_DATA 0x00004410 +#define DDRSS_PHY_1846_DATA 0x00004410 +#define DDRSS_PHY_1847_DATA 0x00000000 +#define DDRSS_PHY_1848_DATA 0x00000076 +#define DDRSS_PHY_1849_DATA 0x00000400 +#define DDRSS_PHY_1850_DATA 0x00000008 +#define DDRSS_PHY_1851_DATA 0x00000000 +#define DDRSS_PHY_1852_DATA 0x00000000 +#define DDRSS_PHY_1853_DATA 0x00000000 +#define DDRSS_PHY_1854_DATA 0x00000000 +#define DDRSS_PHY_1855_DATA 0x00000000 +#define DDRSS_PHY_1856_DATA 0x03000000 +#define DDRSS_PHY_1857_DATA 0x00000000 +#define DDRSS_PHY_1858_DATA 0x00000000 +#define DDRSS_PHY_1859_DATA 0x00000000 +#define DDRSS_PHY_1860_DATA 0x04102006 +#define DDRSS_PHY_1861_DATA 0x00041020 +#define DDRSS_PHY_1862_DATA 0x01C98C98 +#define DDRSS_PHY_1863_DATA 0x3F400000 +#define DDRSS_PHY_1864_DATA 0x3F3F1F3F +#define DDRSS_PHY_1865_DATA 0x0000001F +#define DDRSS_PHY_1866_DATA 0x00000000 +#define DDRSS_PHY_1867_DATA 0x00000000 +#define DDRSS_PHY_1868_DATA 0x00000000 +#define DDRSS_PHY_1869_DATA 0x00000001 +#define DDRSS_PHY_1870_DATA 0x00000000 +#define DDRSS_PHY_1871_DATA 0x00000000 +#define DDRSS_PHY_1872_DATA 0x00000000 +#define DDRSS_PHY_1873_DATA 0x00000000 +#define DDRSS_PHY_1874_DATA 0x76542310 +#define DDRSS_PHY_1875_DATA 0x06010198 +#define DDRSS_PHY_1876_DATA 0x00000000 +#define DDRSS_PHY_1877_DATA 0x00000000 +#define DDRSS_PHY_1878_DATA 0x00000000 +#define DDRSS_PHY_1879_DATA 0x00040700 +#define DDRSS_PHY_1880_DATA 0x00000000 +#define DDRSS_PHY_1881_DATA 0x00000000 +#define DDRSS_PHY_1882_DATA 0x00000000 +#define DDRSS_PHY_1883_DATA 0x00000000 +#define DDRSS_PHY_1884_DATA 0x00000000 +#define DDRSS_PHY_1885_DATA 0x00000002 +#define DDRSS_PHY_1886_DATA 0x00000000 +#define DDRSS_PHY_1887_DATA 0x00000000 +#define DDRSS_PHY_1888_DATA 0x0001F7C3 +#define DDRSS_PHY_1889_DATA 0x03000003 +#define DDRSS_PHY_1890_DATA 0x00000000 +#define DDRSS_PHY_1891_DATA 0x00001142 +#define DDRSS_PHY_1892_DATA 0x01020000 +#define DDRSS_PHY_1893_DATA 0x00000080 +#define DDRSS_PHY_1894_DATA 0x03900390 +#define DDRSS_PHY_1895_DATA 0x03900390 +#define DDRSS_PHY_1896_DATA 0x03900390 +#define DDRSS_PHY_1897_DATA 0x03900390 +#define DDRSS_PHY_1898_DATA 0x03000300 +#define DDRSS_PHY_1899_DATA 0x03000300 +#define DDRSS_PHY_1900_DATA 0x00000300 +#define DDRSS_PHY_1901_DATA 0x00000300 +#define DDRSS_PHY_1902_DATA 0x00000300 +#define DDRSS_PHY_1903_DATA 0x00000300 +#define DDRSS_PHY_1904_DATA 0x00000004 +#define DDRSS_PHY_1905_DATA 0x3183BF77 +#define DDRSS_PHY_1906_DATA 0x00000000 +#define DDRSS_PHY_1907_DATA 0x0C000DFF +#define DDRSS_PHY_1908_DATA 0x30000DFF +#define DDRSS_PHY_1909_DATA 0x3F0DFF11 +#define DDRSS_PHY_1910_DATA 0x00EF0000 +#define DDRSS_PHY_1911_DATA 0x780DFFCC +#define DDRSS_PHY_1912_DATA 0x00000C11 +#define DDRSS_PHY_1913_DATA 0x00018011 +#define DDRSS_PHY_1914_DATA 0x0089FF00 +#define DDRSS_PHY_1915_DATA 0x000C3F11 +#define DDRSS_PHY_1916_DATA 0x01990000 +#define DDRSS_PHY_1917_DATA 0x000C3F91 +#define DDRSS_PHY_1918_DATA 0x01990000 +#define DDRSS_PHY_1919_DATA 0x3F0DFF11 +#define DDRSS_PHY_1920_DATA 0x00EF0000 +#define DDRSS_PHY_1921_DATA 0x00018011 +#define DDRSS_PHY_1922_DATA 0x0089FF00 +#define DDRSS_PHY_1923_DATA 0x20040005 diff --git a/arch/arm/dts/k3-am62p5-verdin-r5.dts b/arch/arm/dts/k3-am62p5-verdin-r5.dts new file mode 100644 index 00000000000..983a3bfe670 --- /dev/null +++ b/arch/arm/dts/k3-am62p5-verdin-r5.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Toradex Verdin AM62P dts file for R5 SPL + * Copyright 2025 Toradex - https://www.toradex.com/ + */ + +#include "k3-am62p5-verdin-wifi-dev.dts" +#include "k3-am62p5-verdin-lpddr4-1600.dtsi" +#include "k3-am62a-ddr.dtsi" + +#include "k3-am62p5-verdin-wifi-dev-u-boot.dtsi" + +/ { + aliases { + remoteproc0 = &sysctrler; + remoteproc1 = &a53_0; + }; + + a53_0: a53@0 { + compatible = "ti,am654-rproc"; + reg = <0x00 0x00a90000 0x00 0x10>; + power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>, + <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; + resets = <&k3_reset 135 0>; + clocks = <&k3_clks 61 0>, <&k3_clks 135 0>; + clock-names = "gtc", "core"; + assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>, <&k3_clks 157 36>; + assigned-clock-parents = <&k3_clks 61 2>, <0>, <&k3_clks 157 38>; + assigned-clock-rates = <200000000>, <1200000000>, <25000000>; + ti,sci = <&dmsc>; + ti,sci-proc-id = <32>; + ti,sci-host-id = <10>; + bootph-all; + }; + + dm_tifs: dm-tifs { + compatible = "ti,j721e-dm-sci"; + ti,host-id = <36>; + ti,secure-host; + mbox-names = "rx", "tx"; + mboxes= <&secure_proxy_main 20>, + <&secure_proxy_main 21>; + bootph-all; + }; +}; + +&cbass_main { + sa3_secproxy: secproxy@44880000 { + compatible = "ti,am654-secure-proxy"; + #mbox-cells = <1>; + reg = <0x00 0x44880000 0x00 0x20000>, + <0x00 0x44860000 0x00 0x20000>, + <0x00 0x43600000 0x00 0x10000>; + reg-names = "rt", "scfg", "target_data"; + bootph-all; + }; + + sysctrler: sysctrler { + compatible = "ti,am654-system-controller"; + mboxes= <&secure_proxy_main 1>, + <&secure_proxy_main 0>, + <&sa3_secproxy 0>; + mbox-names = "tx", "rx", "boot_notify"; + bootph-all; + }; +}; + +&dmsc { + mboxes= <&secure_proxy_main 0>, + <&secure_proxy_main 1>, + <&secure_proxy_main 0>; + mbox-names = "rx", "tx", "notify"; + ti,host-id = <35>; + ti,secure-host; +}; + +&main_timer0 { + /delete-property/ clocks; + /delete-property/ clocks-names; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + clock-frequency = <25000000>; +}; diff --git a/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi new file mode 100644 index 00000000000..13fac18d7aa --- /dev/null +++ b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi @@ -0,0 +1,325 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + */ + +#include "k3-binman.dtsi" + +#if IS_ENABLED(CONFIG_TARGET_VERDIN_AM62P_R5) + +&binman { + tiboot3-am62px-hs-fs-verdin.bin { + filename = "tiboot3-am62px-hs-fs-verdin.bin"; + symlink = "tiboot3.bin"; + + ti-secure-rom { + content = <&u_boot_spl_fs>, <&ti_fs_enc_fs>, <&combined_tifs_cfg_fs>, + <&combined_dm_cfg_fs>, <&sysfw_inner_cert_fs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_fs>; + content-sysfw = <&ti_fs_enc_fs>; + content-sysfw-data = <&combined_tifs_cfg_fs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_fs>; + content-dm-data = <&combined_dm_cfg_fs>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c4a800>; + }; + + u_boot_spl_fs: u-boot-spl { + no-expanded; + }; + + ti_fs_enc_fs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-enc.bin"; + type = "blob-ext"; + optional; + }; + + combined_tifs_cfg_fs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + + sysfw_inner_cert_fs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-fs-cert.bin"; + type = "blob-ext"; + optional; + }; + + combined_dm_cfg_fs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; + + tiboot3-am62px-hs-verdin.bin { + filename = "tiboot3-am62px-hs-verdin.bin"; + + ti-secure-rom { + content = <&u_boot_spl_hs>, <&ti_fs_enc_hs>, <&combined_tifs_cfg_hs>, + <&combined_dm_cfg_hs>, <&sysfw_inner_cert_hs>; + combined; + dm-data; + sysfw-inner-cert; + keyfile = "custMpk.pem"; + sw-rev = <1>; + content-sbl = <&u_boot_spl_hs>; + content-sysfw = <&ti_fs_enc_hs>; + content-sysfw-data = <&combined_tifs_cfg_hs>; + content-sysfw-inner-cert = <&sysfw_inner_cert_hs>; + content-dm-data = <&combined_dm_cfg_hs>; + load = <0x43c00000>; + load-sysfw = <0x40000>; + load-sysfw-data = <0x67000>; + load-dm-data = <0x43c4a800>; + }; + + u_boot_spl_hs: u-boot-spl { + no-expanded; + }; + + ti_fs_enc_hs: ti-fs-enc.bin { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + combined_tifs_cfg_hs: combined-tifs-cfg.bin { + filename = "combined-tifs-cfg.bin"; + type = "blob-ext"; + }; + + sysfw_inner_cert_hs: sysfw-inner-cert { + filename = "ti-sysfw/ti-fs-firmware-am62px-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + + combined_dm_cfg_hs: combined-dm-cfg.bin { + filename = "combined-dm-cfg.bin"; + type = "blob-ext"; + }; + }; +}; + +#endif /* CONFIG_TARGET_VERDIN_AM62P_R5 */ + +#if IS_ENABLED(CONFIG_TARGET_VERDIN_AM62P_A53) + +#define SPL_VERDIN_AM62P_DTB "spl/dts/k3-am62p5-verdin-wifi-dev.dtb" +#define VERDIN_AM62P_DTB "u-boot.dtb" + +&binman { + tifsstub-hs { + filename = "tifsstub.bin_hs"; + ti-secure-rom { + content = <&tifsstub_hs_cert>; + core = "secure"; + load = <0x60000>; + sw-rev = ; + keyfile = "custMpk.pem"; + countersign; + tifsstub; + }; + tifsstub_hs_cert: tifsstub-hs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_hs_enc: tifsstub-hs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + }; + + tifsstub-fs { + filename = "tifsstub.bin_fs"; + tifsstub_fs_cert: tifsstub-fs-cert.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-cert.bin"; + type = "blob-ext"; + optional; + }; + tifsstub_fs_enc: tifsstub-fs-enc.bin { + filename = "ti-sysfw/ti-fs-stub-firmware-am62px-hs-enc.bin"; + type = "blob-ext"; + optional; + }; + + }; + + ti-spl { + insert-template = <&ti_spl_template>; + + fit { + images { + tifsstub-hs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-hs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_hs"; + }; + }; + + tifsstub-fs { + description = "TIFSSTUB"; + type = "firmware"; + arch = "arm32"; + compression = "none"; + os = "tifsstub-fs"; + load = <0x9ca00000>; + entry = <0x9ca00000>; + blob-ext { + filename = "tifsstub.bin_fs"; + }; + }; + dm { + ti-secure { + content = <&dm>; + keyfile = "custMpk.pem"; + }; + + dm: ti-dm { + filename = "ti-dm/am62pxx/ipc_echo_testb_mcu1_0_release_strip.xer5f"; + optional; + }; + }; + + fdt-0 { + description = "k3-am62p5-verdin-wifi-dev"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + ti-secure { + content = <&spl_verdin_am62p_dtb>; + keyfile = "custMpk.pem"; + }; + + spl_verdin_am62p_dtb: blob-ext { + filename = SPL_VERDIN_AM62P_DTB; + }; + + }; + + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62p5-verdin-wifi-dev"; + firmware = "atf"; + loadables = "tee", "tifsstub-hs", "tifsstub-fs", + "dm", "spl"; + fdt = "fdt-0"; + }; + }; + }; + }; +}; + +&binman { + u-boot { + insert-template = <&u_boot_template>; + + fit { + images { + uboot { + description = "U-Boot for Verdin AM62P5 Boards"; + }; + + fdt-0 { + description = "k3-am62p5-verdin-wifi-dev"; + type = "flat_dt"; + arch = "arm"; + compression = "none"; + + ti-secure { + content = <&verdin_am62p_dtb>; + keyfile = "custMpk.pem"; + }; + + verdin_am62p_dtb: blob-ext { + filename = VERDIN_AM62P_DTB; + }; + + hash { + algo = "crc32"; + }; + }; + }; + + configurations { + default = "conf-0"; + + conf-0 { + description = "k3-am62p5-verdin-wifi-dev"; + firmware = "uboot"; + loadables = "uboot"; + fdt = "fdt-0"; + }; + + }; + }; + }; +}; + +&binman { + firmware-verdin-am62px-hs.bin { + filename = "firmware-verdin-am62px-hs.bin"; + + blob-ext@1 { + filename = "tiboot3-am62px-hs-verdin.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; + + firmware-verdin-am62px-hs-fs.bin { + filename = "firmware-verdin-am62px-hs-fs.bin"; + + blob-ext@1 { + filename = "tiboot3-am62px-hs-fs-verdin.bin"; + }; + + blob-ext@2 { + filename = "tispl.bin"; + /* + * This value matches CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR + * from R5 SPL config. + */ + offset = <0x80000>; + }; + + blob-ext@3 { + filename = "u-boot.img"; + offset = <(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)>; + }; + }; +}; + +#endif /* CONFIG_TARGET_VERDIN_AM62P_A53 */ diff --git a/arch/arm/dts/k3-am62p5-verdin-wifi-dev-u-boot.dtsi b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-u-boot.dtsi new file mode 100644 index 00000000000..366867d1e6a --- /dev/null +++ b/arch/arm/dts/k3-am62p5-verdin-wifi-dev-u-boot.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + */ + +#include "k3-am62p5-verdin-wifi-dev-binman.dtsi" + +/ { + chosen { + tick-timer = &main_timer0; + }; + + memory@80000000 { + bootph-pre-ram; + }; + + sysinfo { + compatible = "toradex,sysinfo"; + }; +}; + +&carrier_eth_phy { + bootph-all; +}; + +&cpsw3g { + ethernet-ports { + bootph-all; + }; +}; + +/* MDIO, shared by Verdin ETH_1 (On-module PHY) and Verdin ETH_2_RGMII */ +&cpsw3g_mdio { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; + /delete-property/ assigned-clock-rates; + bootph-all; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&cpsw_port1 { + bootph-all; +}; + +/* Verdin ETH_2_RGMII */ +&cpsw_port2 { + bootph-all; +}; + +&dmsc { + bootph-all; +}; + +&k3_clks { + bootph-all; +}; + +&k3_pds { + bootph-all; +}; + +&k3_reset { + bootph-all; +}; + +&main_gpio0 { + bootph-all; +}; + +/* Verdin I2C_1 */ +&main_i2c0 { + bootph-all; +}; + +&main_pktdma { + bootph-all; +}; + +&mcu_pmx0 { + bootph-all; +}; + +/* Verdin UART_3, used as the Linux console */ +&main_uart0 { + bootph-all; +}; + +&main_pmx0 { + bootph-all; +}; + +&pinctrl_main_i2c0 { + bootph-all; +}; + +&pinctrl_mdio { + bootph-all; +}; + +&pinctrl_rgmii1 { + bootph-all; +}; + +&pinctrl_rgmii2 { + bootph-all; +}; + +&pinctrl_uart0 { + bootph-all; +}; + +&pinctrl_wkup_i2c0 { + bootph-all; +}; + +&phy_gmii_sel { + bootph-all; +}; + +&sdhci0 { + bootph-all; +}; + +&sdhci2 { + status = "disabled"; +}; + +&som_eth_phy { + bootph-all; +}; + +&som_gpio_expander { + bootph-all; + + ctrl-sleep-moci-hog { + bootph-all; + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + }; +}; + +/* Required for USB DFU Boot */ +&usb0 { + /* Enable peripheral mode only during bootup + * to support DFU while allowing Linux to stay + * in OTG mode + */ + dr_mode = "peripheral"; + bootph-all; +}; + +/* Required for USB DFU Boot */ +&usb0_phy_ctrl { + bootph-all; +}; + +/* Required for USB DFU Boot */ +&usbss0 { + bootph-all; +}; + +/* On-module I2C - PMIC_I2C */ +&wkup_i2c0 { + bootph-all; +}; diff --git a/arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts b/arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts new file mode 100644 index 00000000000..bbc2770d5f5 --- /dev/null +++ b/arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2025 Toradex + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p + * https://www.toradex.com/products/carrier-board/verdin-development-board-kit + */ + +/dts-v1/; + +#include "k3-am62p5.dtsi" +#include "k3-am62p-verdin.dtsi" +#include "k3-am62p-verdin-wifi.dtsi" +#include "k3-am62p-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin AM62P WB on Verdin Development Board"; + compatible = "toradex,verdin-am62p-wifi-dev", + "toradex,verdin-am62p-wifi", + "toradex,verdin-am62p", + "ti,am62p5"; +}; diff --git a/arch/arm/mach-k3/am62px/Kconfig b/arch/arm/mach-k3/am62px/Kconfig index 76ae86b6622..0f1fcfab5fc 100644 --- a/arch/arm/mach-k3/am62px/Kconfig +++ b/arch/arm/mach-k3/am62px/Kconfig @@ -29,5 +29,6 @@ config TARGET_AM62P5_R5_EVM endchoice source "board/ti/am62px/Kconfig" +source "board/toradex/verdin-am62p/Kconfig" endif diff --git a/board/toradex/verdin-am62p/Kconfig b/board/toradex/verdin-am62p/Kconfig new file mode 100644 index 00000000000..7bf0133b669 --- /dev/null +++ b/board/toradex/verdin-am62p/Kconfig @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright 2025 Toradex +# + +choice + prompt "Toradex Verdin AM62P based boards" + optional + +config TARGET_VERDIN_AM62P_A53 + bool "Toradex Verdin AM62P running on A53" + select ARM64 + select BINMAN + select OF_SYSTEM_SETUP + +config TARGET_VERDIN_AM62P_R5 + bool "Toradex Verdin AM62P running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF + +endchoice + +if TARGET_VERDIN_AM62P_A53 + +config SYS_BOARD + default "verdin-am62p" + +config SYS_CONFIG_NAME + default "verdin-am62p" + +config SYS_VENDOR + default "toradex" + +config TDX_CFG_BLOCK + default y + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_EXTRA + default y + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CFG_BLOCK_PART + default "1" + +config TDX_HAVE_EEPROM_EXTRA + default y + +config TDX_HAVE_MMC + default y + +source "board/toradex/common/Kconfig" + +endif + +if TARGET_VERDIN_AM62P_R5 + +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + +config SYS_BOARD + default "verdin-am62p" + +config SYS_CONFIG_NAME + default "verdin-am62p" + +config SYS_VENDOR + default "toradex" + +endif diff --git a/board/toradex/verdin-am62p/MAINTAINERS b/board/toradex/verdin-am62p/MAINTAINERS new file mode 100644 index 00000000000..97094e0e756 --- /dev/null +++ b/board/toradex/verdin-am62p/MAINTAINERS @@ -0,0 +1,17 @@ +Verdin AM62P +M: Francesco Dolcini +W: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p +S: Maintained +F: arch/arm/dts/k3-am62p-verdin-dev.dtsi +F: arch/arm/dts/k3-am62p-verdin-wifi.dtsi +F: arch/arm/dts/k3-am62p-verdin.dtsi +F: arch/arm/dts/k3-am62p5-verdin-lpddr4-1600.dtsi +F: arch/arm/dts/k3-am62p5-verdin-r5.dts +F: arch/arm/dts/k3-am62p5-verdin-wifi-dev-binman.dtsi +F: arch/arm/dts/k3-am62p5-verdin-wifi-dev-u-boot.dtsi +F: arch/arm/dts/k3-am62p5-verdin-wifi-dev.dts +F: board/toradex/verdin-am62p/ +F: configs/verdin-am62p_a53_defconfig +F: configs/verdin-am62p_r5_defconfig +F: doc/board/toradex/verdin-am62p.rst +F: include/configs/verdin-am62p.h diff --git a/board/toradex/verdin-am62p/Makefile b/board/toradex/verdin-am62p/Makefile new file mode 100644 index 00000000000..2eef6f4f592 --- /dev/null +++ b/board/toradex/verdin-am62p/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright 2025 Toradex +# + +obj-y += verdin-am62p.o diff --git a/board/toradex/verdin-am62p/board-cfg.yaml b/board/toradex/verdin-am62p/board-cfg.yaml new file mode 100644 index 00000000000..d539011aff9 --- /dev/null +++ b/board/toradex/verdin-am62p/board-cfg.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Board configuration for AM62Px SoCs +# + +--- + +board-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + control: + subhdr: + magic: 0xC1D3 + size: 7 + main_isolation_enable: 0x5A + main_isolation_hostid: 0x2 + secproxy: + subhdr: + magic: 0x1207 + size: 7 + scaling_factor: 0x1 + scaling_profile: 0x1 + disable_main_nav_secure_proxy: 0 + msmc: + subhdr: + magic: 0xA5C3 + size: 5 + msmc_cache_size: 0x10 + debug_cfg: + subhdr: + magic: 0x020C + size: 8 + trace_dst_enables: 0x00 + trace_src_enables: 0x00 diff --git a/board/toradex/verdin-am62p/pm-cfg.yaml b/board/toradex/verdin-am62p/pm-cfg.yaml new file mode 100644 index 00000000000..3ff27ce702c --- /dev/null +++ b/board/toradex/verdin-am62p/pm-cfg.yaml @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Power management configuration for AM62Px +# +# +--- +pm-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 diff --git a/board/toradex/verdin-am62p/rm-cfg.yaml b/board/toradex/verdin-am62p/rm-cfg.yaml new file mode 100644 index 00000000000..73da85eeade --- /dev/null +++ b/board/toradex/verdin-am62p/rm-cfg.yaml @@ -0,0 +1,1083 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62P +# + +--- + +rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size: 356 + host_cfg_entries: + - # 1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - # 4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - # 32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + resasg: + subhdr: + magic: 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b/board/toradex/verdin-am62p/sec-cfg.yaml new file mode 100644 index 00000000000..bfd6a4e5dbd --- /dev/null +++ b/board/toradex/verdin-am62p/sec-cfg.yaml @@ -0,0 +1,378 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ +# +# Security configuration for AM62Px +# +--- +sec-cfg: + rev: + boardcfg_abi_maj: 0x0 + boardcfg_abi_min: 0x1 + processor_acl_list: + subhdr: + magic: 0xF1EA + size: 164 + proc_acl_entries: + - # 1 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 2 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 3 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 4 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 5 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 6 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 7 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 8 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 9 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 10 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 11 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 12 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 13 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 14 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 15 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 16 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 17 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 18 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 19 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 20 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 21 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 22 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 23 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 24 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 25 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 26 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 27 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 28 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 29 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 30 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 31 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + - # 32 + processor_id: 0 + proc_access_master: 0 + proc_access_secondary: [0, 0, 0] + host_hierarchy: + subhdr: + magic: 0x8D27 + size: 68 + host_hierarchy_entries: + - # 1 + host_id: 0 + supervisor_host_id: 0 + - # 2 + host_id: 0 + supervisor_host_id: 0 + - # 3 + host_id: 0 + supervisor_host_id: 0 + - # 4 + host_id: 0 + supervisor_host_id: 0 + - # 5 + host_id: 0 + supervisor_host_id: 0 + - # 6 + host_id: 0 + supervisor_host_id: 0 + - # 7 + host_id: 0 + supervisor_host_id: 0 + - # 8 + host_id: 0 + supervisor_host_id: 0 + - # 9 + host_id: 0 + supervisor_host_id: 0 + - # 10 + host_id: 0 + supervisor_host_id: 0 + - # 11 + host_id: 0 + supervisor_host_id: 0 + - # 12 + host_id: 0 + supervisor_host_id: 0 + - # 13 + host_id: 0 + supervisor_host_id: 0 + - # 14 + host_id: 0 + supervisor_host_id: 0 + - # 15 + host_id: 0 + supervisor_host_id: 0 + - # 16 + host_id: 0 + supervisor_host_id: 0 + - # 17 + host_id: 0 + supervisor_host_id: 0 + - # 18 + host_id: 0 + supervisor_host_id: 0 + - # 19 + host_id: 0 + supervisor_host_id: 0 + - # 20 + host_id: 0 + supervisor_host_id: 0 + - # 21 + host_id: 0 + supervisor_host_id: 0 + - # 22 + host_id: 0 + supervisor_host_id: 0 + - # 23 + host_id: 0 + supervisor_host_id: 0 + - # 24 + host_id: 0 + supervisor_host_id: 0 + - # 25 + host_id: 0 + supervisor_host_id: 0 + - # 26 + host_id: 0 + supervisor_host_id: 0 + - # 27 + host_id: 0 + supervisor_host_id: 0 + - # 28 + host_id: 0 + supervisor_host_id: 0 + - # 29 + host_id: 0 + supervisor_host_id: 0 + - # 30 + host_id: 0 + supervisor_host_id: 0 + - # 31 + host_id: 0 + supervisor_host_id: 0 + - # 32 + host_id: 0 + supervisor_host_id: 0 + otp_config: + subhdr: + magic: 0x4081 + size: 69 + otp_entry: + - # 1 + host_id: 0 + host_perms: 0 + - # 2 + host_id: 0 + host_perms: 0 + - # 3 + host_id: 0 + host_perms: 0 + - # 4 + host_id: 0 + host_perms: 0 + - # 5 + host_id: 0 + host_perms: 0 + - # 6 + host_id: 0 + host_perms: 0 + - # 7 + host_id: 0 + host_perms: 0 + - # 8 + host_id: 0 + host_perms: 0 + - # 9 + host_id: 0 + host_perms: 0 + - # 10 + host_id: 0 + host_perms: 0 + - # 11 + host_id: 0 + host_perms: 0 + - # 12 + host_id: 0 + host_perms: 0 + - # 13 + host_id: 0 + host_perms: 0 + - # 14 + host_id: 0 + host_perms: 0 + - # 15 + host_id: 0 + host_perms: 0 + - # 16 + host_id: 0 + host_perms: 0 + - # 17 + host_id: 0 + host_perms: 0 + - # 18 + host_id: 0 + host_perms: 0 + - # 19 + host_id: 0 + host_perms: 0 + - # 20 + host_id: 0 + host_perms: 0 + - # 21 + host_id: 0 + host_perms: 0 + - # 22 + host_id: 0 + host_perms: 0 + - # 23 + host_id: 0 + host_perms: 0 + - # 24 + host_id: 0 + host_perms: 0 + - # 25 + host_id: 0 + host_perms: 0 + - # 26 + host_id: 0 + host_perms: 0 + - # 27 + host_id: 0 + host_perms: 0 + - # 28 + host_id: 0 + host_perms: 0 + - # 29 + host_id: 0 + host_perms: 0 + - # 30 + host_id: 0 + host_perms: 0 + - # 31 + host_id: 0 + host_perms: 0 + - # 32 + host_id: 0 + host_perms: 0 + write_host_id: 0 + dkek_config: + subhdr: + magic: 0x5170 + size: 12 + allowed_hosts: [128, 0, 0, 0] + allow_dkek_export_tisci: 0x5A + rsvd: [0, 0, 0] + sa2ul_cfg: + subhdr: + magic: 0x23BE + size: 0 + auth_resource_owner: 0 + enable_saul_psil_global_config_writes: 0x5A + rsvd: [0, 0] + sec_dbg_config: + subhdr: + magic: 0x42AF + size: 16 + allow_jtag_unlock: 0x5A + allow_wildcard_unlock: 0x5A + allowed_debug_level_rsvd: 0 + rsvd: 0 + min_cert_rev: 0x0 + jtag_unlock_hosts: [0, 0, 0, 0] + sec_handover_cfg: + subhdr: + magic: 0x608F + size: 10 + handover_msg_sender: 0 + handover_to_host_id: 0 + rsvd: [0, 0, 0, 0] diff --git a/board/toradex/verdin-am62p/tifs-rm-cfg.yaml b/board/toradex/verdin-am62p/tifs-rm-cfg.yaml new file mode 100644 index 00000000000..80269748057 --- /dev/null +++ b/board/toradex/verdin-am62p/tifs-rm-cfg.yaml @@ -0,0 +1,927 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (C) 2022-2025 Texas Instruments Incorporated - https://www.ti.com/ +# +# Resource management configuration for AM62P +# + +--- + +tifs-rm-cfg: + rm_boardcfg: + rev: + boardcfg_abi_maj : 0x0 + boardcfg_abi_min : 0x1 + host_cfg: + subhdr: + magic: 0x4C41 + size : 356 + host_cfg_entries: + - #1 + host_id: 12 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #2 + host_id: 30 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #3 + host_id: 36 + allowed_atype: 0x2A + allowed_qos: 0xAAAA + allowed_orderid: 0xAAAAAAAA + allowed_priority: 0xAAAA + allowed_sched_priority: 0xAA + - #4 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #5 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #6 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #7 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #8 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #9 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #10 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #11 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #12 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #13 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #14 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #15 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #16 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #17 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #18 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #19 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #20 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #21 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #22 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #23 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #24 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #25 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #26 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #27 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #28 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #29 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #30 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #31 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + - #32 + host_id: 0 + allowed_atype: 0 + allowed_qos: 0 + allowed_orderid: 0 + allowed_priority: 0 + allowed_sched_priority: 0 + resasg: + subhdr: + magic: 0x7B25 + size: 8 + resasg_entries_size: 904 + reserved: 0 + resasg_entries: + - + start_resource: 0 + num_resource: 18 + type: 1677 + host_id: 12 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1677 + host_id: 35 + reserved: 0 + - + start_resource: 18 + num_resource: 6 + type: 1677 + host_id: 36 + reserved: 0 + - + start_resource: 24 + num_resource: 2 + type: 1677 + host_id: 30 + reserved: 0 + - + start_resource: 26 + num_resource: 6 + type: 1677 + host_id: 128 + reserved: 0 + - + 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host_id: 128 + reserved: 0 + - + start_resource: 3584 + num_resource: 6 + type: 12827 + host_id: 128 + reserved: 0 + - + start_resource: 4096 + num_resource: 6 + type: 12828 + host_id: 128 + reserved: 0 diff --git a/board/toradex/verdin-am62p/verdin-am62p.c b/board/toradex/verdin-am62p/verdin-am62p.c new file mode 100644 index 00000000000..105b3120fc0 --- /dev/null +++ b/board/toradex/verdin-am62p/verdin-am62p.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Board specific initialization for Verdin AM62P SoM + * + * Copyright 2025 Toradex - https://www.toradex.com/ + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tdx-cfg-block.h" + +DECLARE_GLOBAL_DATA_PTR; +static u8 hw_cfg; + +static void read_hw_cfg(void) +{ + struct gpio_desc gpio_hw_cfg; + static const int gpios[] = { 58, 61, 62 }; /* HW_CFG0, HW_CFG1, HW_CFG2 */ + char gpio_name[20]; + int i; + + printf("HW CFG: "); + + for (i = 0; i < ARRAY_SIZE(gpios); i++) { + snprintf(gpio_name, sizeof(gpio_name), "gpio@600000_%d", gpios[i]); + + if (dm_gpio_lookup_name(gpio_name, &gpio_hw_cfg) < 0) { + printf("Lookup error: GPIO %d\n", gpios[i]); + continue; + } + + if (dm_gpio_request(&gpio_hw_cfg, "hw_cfg")) { + printf("GPIO request error: %d\n", gpios[i]); + continue; + } + + if (dm_gpio_get_value(&gpio_hw_cfg) == 1) + hw_cfg |= BIT(i); + + dm_gpio_free(NULL, &gpio_hw_cfg); + } + + printf("0x%02x\n", hw_cfg); +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, CFG_SYS_SDRAM_SIZE); + + if (gd->ram_size < SZ_1G) + puts("## WARNING: Less than 1GB RAM detected\n"); + + return 0; +} + +int dram_init_banksize(void) +{ + s32 ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + printf("Error setting up memory banksize. %d\n", ret); + + /* Use the detected RAM size, we only support 1 bank right now. */ + gd->bd->bi_dram[0].size = gd->ram_size; + + return ret; +} + +#if IS_ENABLED(CONFIG_SPL_LOAD_FIT) +int board_fit_config_name_match(const char *name) +{ + return 0; +} +#endif + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + +static void select_dt_from_module_version(void) +{ + char variant[32]; + char *env_variant = env_get("variant"); + int is_wifi = 0; + + if (IS_ENABLED(CONFIG_TDX_CFG_BLOCK)) { + /* + * If we have a valid config block and it says we are a module with + * Wi-Fi/Bluetooth make sure we use the -wifi device tree. + */ + is_wifi = (tdx_hw_tag.prodid == VERDIN_AM62PQ_2G_WIFI_BT_IT); + } + + if (is_wifi) + strlcpy(&variant[0], "wifi", sizeof(variant)); + else + strlcpy(&variant[0], "nonwifi", sizeof(variant)); + + if (strcmp(variant, env_variant)) { + printf("Setting variant to %s\n", variant); + env_set("variant", variant); + } +} + +int board_late_init(void) +{ + select_dt_from_module_version(); + + return 0; +} + +#define MCU_CTRL_LFXOSC_32K_BYPASS_VAL BIT(4) + +void spl_board_init(void) +{ + u32 val; + + /* + * We use the 32k FOUT from the Epson RX8130CE RTC chip, + * configure LFXOSC accordingly, see AM62P datasheet, + * Table 6-23, LFXOSC Modes of Operation. + */ + val = readl(MCU_CTRL_LFXOSC_CTRL); + val &= ~MCU_CTRL_LFXOSC_32K_DISABLE_VAL; + val |= MCU_CTRL_LFXOSC_32K_BYPASS_VAL; + writel(val, MCU_CTRL_LFXOSC_CTRL); + /* Make sure to mux up to take the SoC 32k from the LFOSC input */ + writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, + MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); + + read_hw_cfg(); +} diff --git a/board/toradex/verdin-am62p/verdin-am62p.env b/board/toradex/verdin-am62p/verdin-am62p.env new file mode 100644 index 00000000000..f8b7363dcf5 --- /dev/null +++ b/board/toradex/verdin-am62p/verdin-am62p.env @@ -0,0 +1,41 @@ +#define CFG_RAMDISK_ADDR_R 0x90300000 +#define CFG_SCRIPTADDR 0x90280000 + +boot_script_dhcp=boot.scr +boot_targets=mmc1 mmc0 dhcp +console=ttyS2 +fdt_addr_r=0x90200000 +fdt_board=dev +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x80200000 +kernel_comp_size=0x08000000 +ramdisk_addr_r=CFG_RAMDISK_ADDR_R +scriptaddr=CFG_SCRIPTADDR + +dfu_alt_info_ram= + tispl.bin ram 0x80080000 0x200000; + u-boot.img ram 0x81000000 0x400000; + loadaddr ram CONFIG_SYS_LOAD_ADDR 0x80000; + scriptaddr ram CFG_SCRIPTADDR 0x80000; + ramdisk_addr_r ram CFG_RAMDISK_ADDR_R 0x8000000 + +update_tiboot3= + askenv confirm Did you load tiboot3.bin (y/N)?; + if test $confirm = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; + mmc dev 0 1; mmc write ${loadaddr} 0x0 ${blkcnt}; + fi + +update_tispl= + askenv confirm Did you load tispl.bin (y/N)?; + if test $confirm = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; + mmc dev 0 1; mmc write ${loadaddr} 0x400 ${blkcnt}; + fi + +update_uboot= + askenv confirm Did you load u-boot.img (y/N)?; + if test $confirm = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200; + mmc dev 0 1; mmc write ${loadaddr} 0x1400 ${blkcnt}; + fi diff --git a/configs/verdin-am62p_a53_defconfig b/configs/verdin-am62p_a53_defconfig new file mode 100644 index 00000000000..cb0bf2c7838 --- /dev/null +++ b/configs/verdin-am62p_a53_defconfig @@ -0,0 +1,199 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SOC_K3_AM62P5=y +CONFIG_TARGET_VERDIN_AM62P_A53=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-verdin-wifi-dev" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_TEXT_BASE=0x80080000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x80c80000 +CONFIG_SPL_BSS_MAX_SIZE=0x80000 +CONFIG_SPL_STACK_R=y +CONFIG_SYS_BOOTM_LEN=0x40000000 +CONFIG_SYS_LOAD_ADDR=0x88200000 +CONFIG_SPL_SIZE_LIMIT=0x80000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x800 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0xB0000000 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000 +CONFIG_BOOTSTD_FULL=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_BOOTDELAY=1 +CONFIG_BOOTCOMMAND="bootflow scan -b" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile k3-am62p5-verdin-${variant}-${fdt_board}.dtb" +CONFIG_LOG=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x80000 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SPL_DMA=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_THERMAL=y +CONFIG_SYS_PROMPT="Verdin AM62P # " +CONFIG_CMD_ADTIMG=y +CONFIG_CMD_ASKENV=y +# CONFIG_CMD_EXPORTENV is not set +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_BCB=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_READ=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BOOTCOUNT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_UUID=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT=y +CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +CONFIG_VERSION_VARIABLE=y +CONFIG_IP_DEFRAG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_TI_SCI=y +CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000 +CONFIG_DMA_CHANNELS=y +CONFIG_TI_K3_NAVSS_UDMA=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x88200000 +CONFIG_FASTBOOT_BUF_SIZE=0x8000000 +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_GPIO_HOG=y +CONFIG_SPL_GPIO_HOG=y +CONFIG_SPL_DM_GPIO_LOOKUP_LABEL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_DM_I2C_GPIO=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_I2C_EEPROM=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_SPL_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_SPL_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_ETHERNET_ID=y +CONFIG_DM_ETH_PHY=y +CONFIG_RGMII=y +CONFIG_TI_AM65_CPSW_NUSS=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_SCI_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_TPS65219=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPL_DM_REGULATOR_GPIO=y +CONFIG_DM_REGULATOR_TPS65219=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_REMOTEPROC_TI_K3_DSP=y +CONFIG_REMOTEPROC_TI_K3_R5F=y +CONFIG_RESET_TI_SCI=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_TI_SCI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_DWC3_AM62=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_SPL_DFU=y +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 +CONFIG_HEXDUMP=y diff --git a/configs/verdin-am62p_r5_defconfig b/configs/verdin-am62p_r5_defconfig new file mode 100644 index 00000000000..d1cc9b81640 --- /dev/null +++ b/configs/verdin-am62p_r5_defconfig @@ -0,0 +1,117 @@ +CONFIG_ARM=y +CONFIG_ARCH_K3=y +CONFIG_SYS_MALLOC_LEN=0x08000000 +CONFIG_SYS_MALLOC_F_LEN=0x9000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SOC_K3_AM62P5=y +CONFIG_K3_QOS=y +CONFIG_TARGET_VERDIN_AM62P_R5=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c4a7f0 +CONFIG_ENV_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="k3-am62p5-verdin-r5" +CONFIG_DM_RESET=y +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK_R_ADDR=0x82000000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_TEXT_BASE=0x43c00000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x43c4b000 +CONFIG_SPL_BSS_MAX_SIZE=0x3000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_SIZE_LIMIT=0x3C000 +CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x5000 +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y +CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y +CONFIG_SPL_MAX_SIZE=0x3B000 +CONFIG_SPL_PAD_TO=0x0 +CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 +CONFIG_SPL_EARLY_BSS=y +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_RAM_DEVICE=y +CONFIG_SPL_REMOTEPROC=y +CONFIG_CMD_DFU=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_SPL_CLK_K3_PLL=y +CONFIG_SPL_CLK_K3=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000 +CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DA8XX_GPIO=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y +CONFIG_DM_MAILBOX=y +CONFIG_K3_SEC_PROXY=y +CONFIG_MISC=y +CONFIG_ESM_K3=y +CONFIG_SPL_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_SPL_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_AM654=y +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_GENERIC is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_GENERIC is not set +CONFIG_PINCTRL_SINGLE=y +CONFIG_POWER_DOMAIN=y +CONFIG_TI_POWER_DOMAIN=y +CONFIG_K3_SYSTEM_CONTROLLER=y +CONFIG_REMOTEPROC_TI_K3_ARM64=y +CONFIG_RESET_TI_SCI=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SOC_DEVICE=y +CONFIG_SOC_DEVICE_TI_K3=y +CONFIG_SOC_TI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_OMAP_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_AM62=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y +CONFIG_LIB_RATIONAL=y +CONFIG_SPL_LIB_RATIONAL=y diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index 0d9ccd5a768..01fb9411688 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -49,6 +49,7 @@ K3 SoC based boards in other sections * :doc:`../phytec/phycore-am62x` * :doc:`../phytec/phycore-am62ax` * :doc:`../toradex/verdin-am62` +* :doc:`../toradex/verdin-am62p` Boot Flow Overview ------------------ diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst index 7d510a80112..68934566ad7 100644 --- a/doc/board/toradex/index.rst +++ b/doc/board/toradex/index.rst @@ -11,5 +11,6 @@ Toradex colibri-imx8x smarc-imx8mp verdin-am62 + verdin-am62p verdin-imx8mm verdin-imx8mp diff --git a/doc/board/toradex/verdin-am62p.rst b/doc/board/toradex/verdin-am62p.rst new file mode 100644 index 00000000000..2f3262b8d1e --- /dev/null +++ b/doc/board/toradex/verdin-am62p.rst @@ -0,0 +1,196 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later +.. sectionauthor:: Parth Pancholi + +Verdin AM62P Module +=================== + +- SoM: https://www.toradex.com/computer-on-modules/verdin-arm-family/ti-am62p +- Carrier board: https://www.toradex.com/products/carrier-board/verdin-development-board-kit + +Quick Start +----------- + +- Setup environment variables +- Get binary-only TI Linux firmware +- Build the ARM trusted firmware binary +- Build the OPTEE binary +- Build U-Boot for the R5 +- Build U-Boot for the A53 +- Flash to eMMC +- Boot + +Setup environment +----------------- + +Suggested current toolchains are ARM 11.3 (https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads): + +- https://developer.arm.com/-/media/Files/downloads/gnu/11.3.rel1/binrel/arm-gnu-toolchain-11.3.rel1-x86_64-arm-none-linux-gnueabihf.tar.xz +- https://developer.arm.com/-/media/Files/downloads/gnu/11.3.rel1/binrel/arm-gnu-toolchain-11.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz + +.. code-block:: bash + + $ export CROSS_COMPILE_32=arm-none-linux-gnueabihf- + $ export CROSS_COMPILE_64=aarch64-none-linux-gnu- + +Get the TI Linux Firmware +------------------------- + +.. code-block:: bash + + $ echo "Downloading TI Linux Firmware..." + $ git clone -b ti-linux-firmware https://git.ti.com/git/processor-firmware/ti-linux-firmware.git + +Get and Build the ARM Trusted Firmware (Trusted Firmware A) +----------------------------------------------------------- + +.. code-block:: bash + + $ echo "Downloading and building TF-A..." + $ git clone https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git + $ cd trusted-firmware-a + +Then build ATF (TF-A): + +.. code-block:: bash + + $ export CROSS_COMPILE="$CROSS_COMPILE_64" + $ make PLAT=k3 K3_PM_SYSTEM_SUSPEND=1 TARGET_BOARD=lite SPD=opteed + +Get and Build OPTEE +------------------- + +.. code-block:: bash + + $ echo "Downloading and building OPTEE..." + $ git clone https://github.com/OP-TEE/optee_os.git + $ cd optee_os + +Then build OPTEE: + +.. code-block:: bash + + $ export CROSS_COMPILE="$CROSS_COMPILE_32" + $ export CROSS_COMPILE64="$CROSS_COMPILE_64" + $ make PLATFORM=k3-am62px CFG_ARM64_core=y + +Build U-Boot for R5 +------------------- + +.. code-block:: bash + + $ export CROSS_COMPILE="$CROSS_COMPILE_32" + $ export BINMAN_INDIRS= + $ make O=/tmp/verdin-am62p-r5 verdin-am62p_r5_defconfig + $ make O=/tmp/verdin-am62p-r5 + +Build U-Boot for A53 +-------------------- + +.. code-block:: bash + + $ export CROSS_COMPILE=$CROSS_COMPILE_64 + $ export BL31=/build/k3/lite/release/bl31.bin + $ export TEE=/out/arm-plat-k3/core/tee-pager_v2.bin + $ export BINMAN_INDIRS=" /tmp/verdin-am62p-r5" + $ make O=/tmp/verdin-am62p-a53 verdin-am62p_a53_defconfig + $ make O=/tmp/verdin-am62p-a53 + +Flash to eMMC +------------- + +.. code-block:: console + + => mmc dev 0 1 + => fatload mmc 1 ${loadaddr} tiboot3.bin + => mmc write ${loadaddr} 0x0 0x400 + => fatload mmc 1 ${loadaddr} tispl.bin + => mmc write ${loadaddr} 0x400 0x1000 + => fatload mmc 1 ${loadaddr} u-boot.img + => mmc write ${loadaddr} 0x1400 0x2000 + +As a convenience, instead of having to remember all those addresses and sizes, +one may also use the update U-Boot wrappers: + +.. code-block:: console + + => tftpboot ${loadaddr} tiboot3.bin + => run update_tiboot3 + + => tftpboot ${loadaddr} tispl.bin + => run update_tispl + + => tftpboot ${loadaddr} u-boot.img + => run update_uboot + +Boot +---- + +Output: + +.. code-block:: console + +U-Boot SPL 2025.04-00006-g51dc98d36470 (May 12 2025 - 15:46:57 +0100) +SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.7--v11.00.07 (Fancy Rat)') +Changed A53 CPU frequency to 1250000000Hz (U grade) in DT +SPL initial stack usage: 17080 bytes +Trying to boot from MMC1 +Authentication passed +Authentication passed +Authentication passed +Loading Environment from nowhere... OK +init_env from device 9 not supported! +Authentication passed +Authentication passed +Starting ATF on ARM64 core... + +NOTICE: BL31: v2.12.0(release):v2.12.0-1106-g4301798db096 +NOTICE: BL31: Built : 10:57:58, May 9 2025 +I/TC: +I/TC: OP-TEE version: 4.6.0-18-g76d920d354df (gcc version 12.3.1 20230626 (Arm GNU Toolchain 12.3.Rel1 (Build arm-12.35))) #4 Tue May 6 19:48:13 UTC 2025 aarch64 +I/TC: WARNING: This OP-TEE configuration might be insecure! +I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html +I/TC: Primary CPU initializing +I/TC: GIC redistributor base address not provided +I/TC: Assuming default GIC group status and modifier +I/TC: SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.7--v11.00.07 (Fancy Rat)') +I/TC: Activated SA2UL device +I/TC: Enabled firewalls for SA2UL TRNG device +I/TC: SA2UL TRNG initialized +I/TC: SA2UL Drivers initialized +I/TC: HUK Initialized +I/TC: Primary CPU switching to normal world boot + +U-Boot SPL 2025.04-00006-g51dc98d36470 (May 12 2025 - 15:47:54 +0100) +SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.7--v11.00.07 (Fancy Rat)') +SPL initial stack usage: 1760 bytes +HW CFG: 0x00 +Trying to boot from MMC1 +Authentication passed +Authentication passed + + +U-Boot 2025.04-00006-g51dc98d36470 (May 12 2025 - 15:47:54 +0100) + +SoC: AM62PX SR1.0 HS-FS +DRAM: 2 GiB +Core: 147 devices, 31 uclasses, devicetree: separate +MMC: mmc@fa10000: 0, mmc@fa00000: 1 +Loading Environment from MMC... Reading from MMC(0)... OK +In: serial@2800000 +Out: serial@2800000 +Err: serial@2800000 +Model: Toradex 0099 Verdin AM62P Quad 2GB WB IT V1.0A +Serial#: 15664919 +Carrier: Toradex Dahlia V1.1D, Serial# 11287149 +am65_cpsw_nuss ethernet@8000000: K3 CPSW: nuss_ver: 0x6BA01903 cpsw_ver: 0x6BA81903 ale_ver: 0x00290105 Ports:2 +Setting variant to wifi +Net: +Warning: ethernet@8000000port@1 MAC addresses don't match: +Address in ROM is 58:a1:5f:b8:93:f9 +Address in environment is 00:14:2d:ef:07:17 +eth0: ethernet@8000000port@1 [PRIME]Could not get PHY for mdio@f00: addr 7 +am65_cpsw_nuss_port ethernet@8000000port@2: phy_connect() failed + +Hit any key to stop autoboot: 0 +Verdin AM62P # + diff --git a/include/configs/verdin-am62p.h b/include/configs/verdin-am62p.h new file mode 100644 index 00000000000..eef360ee9b6 --- /dev/null +++ b/include/configs/verdin-am62p.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Configuration header file for Verdin AM62P SoM + * + * Copyright 2025 Toradex - https://www.toradex.com/ + */ + +#ifndef __VERDIN_AM62P_H +#define __VERDIN_AM62P_H + +/* DDR Configuration */ +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_SDRAM_SIZE SZ_2G /* Maximum supported size */ + +#endif /* __VERDIN_AM62P_H */ -- cgit v1.3.1 From 8c986521c3c961338dc86a279757e67e8e23513f Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sun, 25 May 2025 15:43:58 +0200 Subject: cmd: bootmenu: permit to select bootmenu entry with a shortcut MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Permit to select a bootmenu entry with a key shortcut. This is especially useful in production or testing scenario to automate flashing procedure or testing procedure. The boot entry are changed to append the shortcut key to it. Example: 1. Run default boot command. 2. Boot system via TFTP. 3. Boot production system from NAND. 4. Boot recovery system from NAND. 5. Load production system via TFTP then write to NAND. 6. Load recovery system via TFTP then write to NAND. 7. Load BL31+U-Boot FIP via TFTP then write to NAND. 8. Load BL2 preloader via TFTP then write to NAND. 9. Reboot. a. Reset all settings to factory defaults. 0. Exit 0 is always reserved for Exit to console. On pressing the keyboard key 2, the bootmenu entry 2 is selected and executed. Up to 34 key shortcut (0 excluded as reserved) are supported from 1-9 and a-z. If a shortcut key not present in the bootmenu list is pressed, it is simply ignored and eventually the autoboot is interrupted. Capital A-Z are converted to lower a-z and the related option is selected. Suggested-by: Weijie Gao Signed-off-by: Christian Marangi Tested-by: Petr Štetiar --- cmd/bootmenu.c | 41 ++++++++++++++++++++++++++++++++++++++--- common/menu.c | 44 ++++++++++++++++++++++++++++++++++++++++++-- include/cli.h | 2 ++ include/menu.h | 3 +++ 4 files changed, 85 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c index a5c979079f4..d3108778c6f 100644 --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c @@ -114,6 +114,14 @@ static char *bootmenu_choice_entry(void *data) ++menu->active; /* no menu key selected, regenerate menu */ return NULL; + case BKEY_SHORTCUT: + /* invalid shortcut, regenerate menu */ + if (cch->shortcut_key >= menu->count - 1) + return NULL; + /* shortcut_key value for Exit is is -1 */ + menu->active = cch->shortcut_key < 0 ? menu->count - 1 : + cch->shortcut_key; + fallthrough; case BKEY_SELECT: iter = menu->first; for (i = 0; i < menu->active; ++i) @@ -161,6 +169,21 @@ static void bootmenu_destroy(struct bootmenu_data *menu) free(menu); } +static char bootmenu_entry_shortcut_key(int index) +{ + switch (index) { + /* 1-9 shortcut key (0 reserved) */ + case 0 ... 8: + return '1' + index; + /* a-z shortcut key */ + case 9 ... 34: + return 'a' + index - 9; + /* We support shortcut for up to 34 options (0 reserved) */ + default: + return -ENOENT; + } +} + /** * prepare_bootmenu_entry() - generate the bootmenu_xx entries * @@ -184,6 +207,8 @@ static int prepare_bootmenu_entry(struct bootmenu_data *menu, struct bootmenu_entry *iter = *current; while ((option = bootmenu_getoption(i))) { + char shortcut_key; + int len; /* bootmenu_[num] format is "[title]=[commands]" */ sep = strchr(option, '='); @@ -196,12 +221,22 @@ static int prepare_bootmenu_entry(struct bootmenu_data *menu, if (!entry) return -ENOMEM; - entry->title = strndup(option, sep - option); + /* Add shotcut key option: %c. %s\0 */ + len = sep - option + 4; + + entry->title = malloc(len); if (!entry->title) { free(entry); return -ENOMEM; } + shortcut_key = bootmenu_entry_shortcut_key(i); + /* Use emtpy space if entry doesn't support shortcut key */ + snprintf(entry->title, len, "%c%c %s", + shortcut_key > 0 ? shortcut_key : ' ', + shortcut_key > 0 ? '.' : ' ', + option); + entry->command = strdup(sep + 1); if (!entry->command) { free(entry->title); @@ -388,9 +423,9 @@ static struct bootmenu_data *bootmenu_create(int uefi, int delay) /* Add Quit entry if exiting bootmenu is disabled */ if (!IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE)) - entry->title = strdup("Exit"); + entry->title = strdup("0. Exit"); else - entry->title = strdup("Quit"); + entry->title = strdup("0. Quit"); if (!entry->title) { free(entry); diff --git a/common/menu.c b/common/menu.c index 5a2126aa01a..ae5afa14766 100644 --- a/common/menu.c +++ b/common/menu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -436,6 +437,29 @@ int menu_destroy(struct menu *m) return 1; } +static int bootmenu_conv_shortcut_key(struct bootmenu_data *menu, int ichar) +{ + int shortcut_key; + + ichar = tolower(ichar); + switch (ichar) { + /* a-z for bootmenu entry > 9 */ + case 'a' ... 'z': + shortcut_key = ichar - 'a' + 9; + break; + /* 1-9 for bootmenu entry <= 9 */ + case '1' ... '9': + shortcut_key = ichar - '1'; + break; + /* Reserve 0 for last option (aka Exit) */ + case '0': + default: + return -1; + } + + return shortcut_key; +} + enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu, struct cli_ch_state *cch) { @@ -443,12 +467,12 @@ enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu, int i, c; while (menu->delay > 0) { + int ichar; + if (ansi) printf(ANSI_CURSOR_POSITION, menu->count + 5, 3); printf("Hit any key to stop autoboot: %d ", menu->delay); for (i = 0; i < 100; ++i) { - int ichar; - if (!tstc()) { schedule(); mdelay(10); @@ -470,6 +494,11 @@ enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu, case 0x3: /* ^C */ key = BKEY_QUIT; break; + case 'A' ... 'Z': + case 'a' ... 'z': + case '0' ... '9': + key = BKEY_SHORTCUT; + break; default: key = BKEY_NONE; break; @@ -477,6 +506,9 @@ enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu, break; } + if (key == BKEY_SHORTCUT) + cch->shortcut_key = bootmenu_conv_shortcut_key(menu, ichar); + if (menu->delay < 0) break; @@ -524,6 +556,11 @@ enum bootmenu_key bootmenu_conv_key(int ichar) case ' ': key = BKEY_SPACE; break; + case 'A' ... 'Z': + case 'a' ... 'z': + case '0' ... '9': + key = BKEY_SHORTCUT; + break; default: key = BKEY_NONE; break; @@ -554,5 +591,8 @@ enum bootmenu_key bootmenu_loop(struct bootmenu_data *menu, key = bootmenu_conv_key(c); + if (key == BKEY_SHORTCUT) + cch->shortcut_key = bootmenu_conv_shortcut_key(menu, c); + return key; } diff --git a/include/cli.h b/include/cli.h index e183d561369..453e88fa96d 100644 --- a/include/cli.h +++ b/include/cli.h @@ -17,12 +17,14 @@ * @esc_save: Escape characters collected so far * @emit_upto: Next index to emit from esc_save * @emitting: true if emitting from esc_save + * @shortcut_key: Selected shortcut option index */ struct cli_ch_state { int esc_len; char esc_save[8]; int emit_upto; bool emitting; + int shortcut_key; }; /** diff --git a/include/menu.h b/include/menu.h index 6cede89b950..54ff3b2e17a 100644 --- a/include/menu.h +++ b/include/menu.h @@ -54,6 +54,9 @@ enum bootmenu_key { BKEY_QUIT, BKEY_SAVE, + /* shortcut key to select menu option directly */ + BKEY_SHORTCUT, + /* 'extra' keys, which are used by menus but not cedit */ BKEY_PLUS, BKEY_MINUS, -- cgit v1.3.1 From ceeda322e79c061968aa0f7365ee5af312f4f0be Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 27 May 2025 16:18:33 -0600 Subject: include/dt-bindings: Remove unused headers As part of moving to using OF_UPSTREAM and so the upstream dt-bindings headers we have a number of these headers that are in our include directory and not referenced by any code outside of dts/upstream. We can remove these now to prevent future conflicts. Signed-off-by: Tom Rini --- include/dt-bindings/arm/coresight-cti-dt.h | 37 ---- include/dt-bindings/clock/omap4.h | 149 ---------------- include/dt-bindings/clock/omap5.h | 129 -------------- include/dt-bindings/clock/sun4i-a10-pll2.h | 53 ------ include/dt-bindings/clock/xlnx-versal-clk.h | 123 ------------- include/dt-bindings/interrupt-controller/irq-st.h | 30 ---- .../dt-bindings/interrupt-controller/mips-gic.h | 9 - include/dt-bindings/leds/leds-netxbig.h | 18 -- include/dt-bindings/leds/leds-ns2.h | 9 - include/dt-bindings/mux/ti-serdes.h | 190 --------------------- include/dt-bindings/net/mscc-phy-vsc8531.h | 31 ---- include/dt-bindings/phy/phy-am654-serdes.h | 13 -- include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h | 41 ----- include/dt-bindings/pinctrl/k3.h | 50 ------ include/dt-bindings/reset/xlnx-versal-resets.h | 105 ------------ include/dt-bindings/sound/tlv320aic31xx.h | 14 -- 16 files changed, 1001 deletions(-) delete mode 100644 include/dt-bindings/arm/coresight-cti-dt.h delete mode 100644 include/dt-bindings/clock/omap4.h delete mode 100644 include/dt-bindings/clock/omap5.h delete mode 100644 include/dt-bindings/clock/sun4i-a10-pll2.h delete mode 100644 include/dt-bindings/clock/xlnx-versal-clk.h delete mode 100644 include/dt-bindings/interrupt-controller/irq-st.h delete mode 100644 include/dt-bindings/interrupt-controller/mips-gic.h delete mode 100644 include/dt-bindings/leds/leds-netxbig.h delete mode 100644 include/dt-bindings/leds/leds-ns2.h delete mode 100644 include/dt-bindings/mux/ti-serdes.h delete mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h delete mode 100644 include/dt-bindings/phy/phy-am654-serdes.h delete mode 100644 include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h delete mode 100644 include/dt-bindings/pinctrl/k3.h delete mode 100644 include/dt-bindings/reset/xlnx-versal-resets.h delete mode 100644 include/dt-bindings/sound/tlv320aic31xx.h (limited to 'include') diff --git a/include/dt-bindings/arm/coresight-cti-dt.h b/include/dt-bindings/arm/coresight-cti-dt.h deleted file mode 100644 index 61e7bdf8ea6..00000000000 --- a/include/dt-bindings/arm/coresight-cti-dt.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for the defined trigger signal - * types on CoreSight CTI. - */ - -#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H -#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H - -#define GEN_IO 0 -#define GEN_INTREQ 1 -#define GEN_INTACK 2 -#define GEN_HALTREQ 3 -#define GEN_RESTARTREQ 4 -#define PE_EDBGREQ 5 -#define PE_DBGRESTART 6 -#define PE_CTIIRQ 7 -#define PE_PMUIRQ 8 -#define PE_DBGTRIGGER 9 -#define ETM_EXTOUT 10 -#define ETM_EXTIN 11 -#define SNK_FULL 12 -#define SNK_ACQCOMP 13 -#define SNK_FLUSHCOMP 14 -#define SNK_FLUSHIN 15 -#define SNK_TRIGIN 16 -#define STM_ASYNCOUT 17 -#define STM_TOUT_SPTE 18 -#define STM_TOUT_SW 19 -#define STM_TOUT_HETE 20 -#define STM_HWEVENT 21 -#define ELA_TSTART 22 -#define ELA_TSTOP 23 -#define ELA_DBGREQ 24 -#define CTI_TRIG_MAX 25 - -#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */ diff --git a/include/dt-bindings/clock/omap4.h b/include/dt-bindings/clock/omap4.h deleted file mode 100644 index 88d73be84b9..00000000000 --- a/include/dt-bindings/clock/omap4.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_OMAP4_H -#define __DT_BINDINGS_CLK_OMAP4_H - -#define OMAP4_CLKCTRL_OFFSET 0x20 -#define OMAP4_CLKCTRL_INDEX(offset) ((offset) - OMAP4_CLKCTRL_OFFSET) - -/* mpuss clocks */ -#define OMAP4_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* tesla clocks */ -#define OMAP4_DSP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* abe clocks */ -#define OMAP4_L4_ABE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_AESS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MCPDM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_DMIC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_MCASP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_MCBSP1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) -#define OMAP4_MCBSP2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_MCBSP3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_SLIMBUS1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_TIMER5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_TIMER6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) -#define OMAP4_TIMER7_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) -#define OMAP4_TIMER8_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) -#define OMAP4_WD_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) - -/* l4_ao clocks */ -#define OMAP4_SMARTREFLEX_MPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_SMARTREFLEX_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_SMARTREFLEX_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) - -/* l3_1 clocks */ -#define OMAP4_L3_MAIN_1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_2 clocks */ -#define OMAP4_L3_MAIN_2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_GPMC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_OCMC_RAM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) - -/* ducati clocks */ -#define OMAP4_IPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_dma clocks */ -#define OMAP4_DMA_SYSTEM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_emif clocks */ -#define OMAP4_DMM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_EMIF1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_EMIF2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) - -/* d2d clocks */ -#define OMAP4_C2C_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l4_cfg clocks */ -#define OMAP4_L4_CFG_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_SPINLOCK_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MAILBOX_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) - -/* l3_instr clocks */ -#define OMAP4_L3_MAIN_3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_L3_INSTR_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_OCP_WP_NOC_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) - -/* ivahd clocks */ -#define OMAP4_IVA_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_SL2IF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) - -/* iss clocks */ -#define OMAP4_ISS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_FDIF_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) - -/* l3_dss clocks */ -#define OMAP4_DSS_CORE_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_gfx clocks */ -#define OMAP4_GPU_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -/* l3_init clocks */ -#define OMAP4_MMC1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_MMC2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_HSI_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_USB_HOST_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_USB_OTG_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_USB_TLL_HS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_USB_HOST_FS_CLKCTRL OMAP4_CLKCTRL_INDEX(0xd0) -#define OMAP4_OCP2SCP_USB_PHY_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) - -/* l4_per clocks */ -#define OMAP4_TIMER10_CLKCTRL OMAP4_CLKCTRL_INDEX(0x28) -#define OMAP4_TIMER11_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_TIMER3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_TIMER4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x48) -#define OMAP4_TIMER9_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_ELM_CLKCTRL OMAP4_CLKCTRL_INDEX(0x58) -#define OMAP4_GPIO2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x60) -#define OMAP4_GPIO3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x68) -#define OMAP4_GPIO4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x70) -#define OMAP4_GPIO5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) -#define OMAP4_GPIO6_CLKCTRL OMAP4_CLKCTRL_INDEX(0x80) -#define OMAP4_HDQ1W_CLKCTRL OMAP4_CLKCTRL_INDEX(0x88) -#define OMAP4_I2C1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa0) -#define OMAP4_I2C2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xa8) -#define OMAP4_I2C3_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb0) -#define OMAP4_I2C4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xb8) -#define OMAP4_L4_PER_CLKCTRL OMAP4_CLKCTRL_INDEX(0xc0) -#define OMAP4_MCBSP4_CLKCTRL OMAP4_CLKCTRL_INDEX(0xe0) -#define OMAP4_MCSPI1_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf0) -#define OMAP4_MCSPI2_CLKCTRL OMAP4_CLKCTRL_INDEX(0xf8) -#define OMAP4_MCSPI3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x100) -#define OMAP4_MCSPI4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x108) -#define OMAP4_MMC3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x120) -#define OMAP4_MMC4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x128) -#define OMAP4_SLIMBUS2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x138) -#define OMAP4_UART1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x140) -#define OMAP4_UART2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x148) -#define OMAP4_UART3_CLKCTRL OMAP4_CLKCTRL_INDEX(0x150) -#define OMAP4_UART4_CLKCTRL OMAP4_CLKCTRL_INDEX(0x158) -#define OMAP4_MMC5_CLKCTRL OMAP4_CLKCTRL_INDEX(0x160) - -/* l4_secure clocks */ -#define OMAP4_L4_SECURE_CLKCTRL_OFFSET 0x1a0 -#define OMAP4_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP4_L4_SECURE_CLKCTRL_OFFSET) -#define OMAP4_AES1_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a0) -#define OMAP4_AES2_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1a8) -#define OMAP4_DES3DES_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b0) -#define OMAP4_PKA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1b8) -#define OMAP4_RNG_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c0) -#define OMAP4_SHA2MD5_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1c8) -#define OMAP4_CRYPTODMA_CLKCTRL OMAP4_L4_SECURE_CLKCTRL_INDEX(0x1d8) - -/* l4_wkup clocks */ -#define OMAP4_L4_WKUP_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) -#define OMAP4_WD_TIMER2_CLKCTRL OMAP4_CLKCTRL_INDEX(0x30) -#define OMAP4_GPIO1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x38) -#define OMAP4_TIMER1_CLKCTRL OMAP4_CLKCTRL_INDEX(0x40) -#define OMAP4_COUNTER_32K_CLKCTRL OMAP4_CLKCTRL_INDEX(0x50) -#define OMAP4_KBD_CLKCTRL OMAP4_CLKCTRL_INDEX(0x78) - -/* emu_sys clocks */ -#define OMAP4_DEBUGSS_CLKCTRL OMAP4_CLKCTRL_INDEX(0x20) - -#endif diff --git a/include/dt-bindings/clock/omap5.h b/include/dt-bindings/clock/omap5.h deleted file mode 100644 index 41775272fd2..00000000000 --- a/include/dt-bindings/clock/omap5.h +++ /dev/null @@ -1,129 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2017 Texas Instruments, Inc. - */ -#ifndef __DT_BINDINGS_CLK_OMAP5_H -#define __DT_BINDINGS_CLK_OMAP5_H - -#define OMAP5_CLKCTRL_OFFSET 0x20 -#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET) - -/* mpu clocks */ -#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* dsp clocks */ -#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* abe clocks */ -#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) -#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) -#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) -#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) -#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) - -/* l3main1 clocks */ -#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* l3main2 clocks */ -#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* ipu clocks */ -#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* dma clocks */ -#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* emif clocks */ -#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) - -/* l4cfg clocks */ -#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) - -/* l3instr clocks */ -#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) - -/* l4per clocks */ -#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) -#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48) -#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60) -#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70) -#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) -#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80) -#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0) -#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8) -#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0) -#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8) -#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0) -#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) -#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8) -#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100) -#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108) -#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110) -#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118) -#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120) -#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128) -#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140) -#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148) -#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150) -#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158) -#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160) -#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168) -#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170) -#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178) - -/* l4_secure clocks */ -#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0 -#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET) -#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0) -#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8) -#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0) -#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8) -#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0) -#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8) -#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8) - -/* iva clocks */ -#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) - -/* dss clocks */ -#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* gpu clocks */ -#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) - -/* l3init clocks */ -#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28) -#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58) -#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68) -#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88) -#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0) -#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8) -#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0) - -/* wkupaon clocks */ -#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20) -#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30) -#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38) -#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40) -#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50) -#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78) - -#endif diff --git a/include/dt-bindings/clock/sun4i-a10-pll2.h b/include/dt-bindings/clock/sun4i-a10-pll2.h deleted file mode 100644 index 071c8112d53..00000000000 --- a/include/dt-bindings/clock/sun4i-a10-pll2.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright 2015 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ -#define __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ - -#define SUN4I_A10_PLL2_1X 0 -#define SUN4I_A10_PLL2_2X 1 -#define SUN4I_A10_PLL2_4X 2 -#define SUN4I_A10_PLL2_8X 3 - -#endif /* __DT_BINDINGS_CLOCK_SUN4I_A10_PLL2_H_ */ diff --git a/include/dt-bindings/clock/xlnx-versal-clk.h b/include/dt-bindings/clock/xlnx-versal-clk.h deleted file mode 100644 index 264d634d226..00000000000 --- a/include/dt-bindings/clock/xlnx-versal-clk.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Xilinx Inc. - * - */ - -#ifndef _DT_BINDINGS_CLK_VERSAL_H -#define _DT_BINDINGS_CLK_VERSAL_H - -#define PMC_PLL 1 -#define APU_PLL 2 -#define RPU_PLL 3 -#define CPM_PLL 4 -#define NOC_PLL 5 -#define PLL_MAX 6 -#define PMC_PRESRC 7 -#define PMC_POSTCLK 8 -#define PMC_PLL_OUT 9 -#define PPLL 10 -#define NOC_PRESRC 11 -#define NOC_POSTCLK 12 -#define NOC_PLL_OUT 13 -#define NPLL 14 -#define APU_PRESRC 15 -#define APU_POSTCLK 16 -#define APU_PLL_OUT 17 -#define APLL 18 -#define RPU_PRESRC 19 -#define RPU_POSTCLK 20 -#define RPU_PLL_OUT 21 -#define RPLL 22 -#define CPM_PRESRC 23 -#define CPM_POSTCLK 24 -#define CPM_PLL_OUT 25 -#define CPLL 26 -#define PPLL_TO_XPD 27 -#define NPLL_TO_XPD 28 -#define APLL_TO_XPD 29 -#define RPLL_TO_XPD 30 -#define EFUSE_REF 31 -#define SYSMON_REF 32 -#define IRO_SUSPEND_REF 33 -#define USB_SUSPEND 34 -#define SWITCH_TIMEOUT 35 -#define RCLK_PMC 36 -#define RCLK_LPD 37 -#define WDT 38 -#define TTC0 39 -#define TTC1 40 -#define TTC2 41 -#define TTC3 42 -#define GEM_TSU 43 -#define GEM_TSU_LB 44 -#define MUXED_IRO_DIV2 45 -#define MUXED_IRO_DIV4 46 -#define PSM_REF 47 -#define GEM0_RX 48 -#define GEM0_TX 49 -#define GEM1_RX 50 -#define GEM1_TX 51 -#define CPM_CORE_REF 52 -#define CPM_LSBUS_REF 53 -#define CPM_DBG_REF 54 -#define CPM_AUX0_REF 55 -#define CPM_AUX1_REF 56 -#define QSPI_REF 57 -#define OSPI_REF 58 -#define SDIO0_REF 59 -#define SDIO1_REF 60 -#define PMC_LSBUS_REF 61 -#define I2C_REF 62 -#define TEST_PATTERN_REF 63 -#define DFT_OSC_REF 64 -#define PMC_PL0_REF 65 -#define PMC_PL1_REF 66 -#define PMC_PL2_REF 67 -#define PMC_PL3_REF 68 -#define CFU_REF 69 -#define SPARE_REF 70 -#define NPI_REF 71 -#define HSM0_REF 72 -#define HSM1_REF 73 -#define SD_DLL_REF 74 -#define FPD_TOP_SWITCH 75 -#define FPD_LSBUS 76 -#define ACPU 77 -#define DBG_TRACE 78 -#define DBG_FPD 79 -#define LPD_TOP_SWITCH 80 -#define ADMA 81 -#define LPD_LSBUS 82 -#define CPU_R5 83 -#define CPU_R5_CORE 84 -#define CPU_R5_OCM 85 -#define CPU_R5_OCM2 86 -#define IOU_SWITCH 87 -#define GEM0_REF 88 -#define GEM1_REF 89 -#define GEM_TSU_REF 90 -#define USB0_BUS_REF 91 -#define UART0_REF 92 -#define UART1_REF 93 -#define SPI0_REF 94 -#define SPI1_REF 95 -#define CAN0_REF 96 -#define CAN1_REF 97 -#define I2C0_REF 98 -#define I2C1_REF 99 -#define DBG_LPD 100 -#define TIMESTAMP_REF 101 -#define DBG_TSTMP 102 -#define CPM_TOPSW_REF 103 -#define USB3_DUAL_REF 104 -#define OUTCLK_MAX 105 -#define REF_CLK 106 -#define PL_ALT_REF_CLK 107 -#define MUXED_IRO 108 -#define PL_EXT 109 -#define PL_LB 110 -#define MIO_50_OR_51 111 -#define MIO_24_OR_25 112 - -#endif diff --git a/include/dt-bindings/interrupt-controller/irq-st.h b/include/dt-bindings/interrupt-controller/irq-st.h deleted file mode 100644 index 6baa9ad2644..00000000000 --- a/include/dt-bindings/interrupt-controller/irq-st.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * include/linux/irqchip/irq-st.h - * - * Copyright (C) 2014 STMicroelectronics All Rights Reserved - * - * Author: Lee Jones - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ST_H - -#define ST_IRQ_SYSCFG_EXT_0 0 -#define ST_IRQ_SYSCFG_EXT_1 1 -#define ST_IRQ_SYSCFG_EXT_2 2 -#define ST_IRQ_SYSCFG_CTI_0 3 -#define ST_IRQ_SYSCFG_CTI_1 4 -#define ST_IRQ_SYSCFG_PMU_0 5 -#define ST_IRQ_SYSCFG_PMU_1 6 -#define ST_IRQ_SYSCFG_pl310_L2 7 -#define ST_IRQ_SYSCFG_DISABLED 0xFFFFFFFF - -#define ST_IRQ_SYSCFG_EXT_1_INV 0x1 -#define ST_IRQ_SYSCFG_EXT_2_INV 0x2 -#define ST_IRQ_SYSCFG_EXT_3_INV 0x4 - -#endif diff --git a/include/dt-bindings/interrupt-controller/mips-gic.h b/include/dt-bindings/interrupt-controller/mips-gic.h deleted file mode 100644 index cf35a577e37..00000000000 --- a/include/dt-bindings/interrupt-controller/mips-gic.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MIPS_GIC_H - -#include - -#define GIC_SHARED 0 -#define GIC_LOCAL 1 - -#endif diff --git a/include/dt-bindings/leds/leds-netxbig.h b/include/dt-bindings/leds/leds-netxbig.h deleted file mode 100644 index 92658b0310b..00000000000 --- a/include/dt-bindings/leds/leds-netxbig.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This header provides constants for netxbig LED bindings. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef _DT_BINDINGS_LEDS_NETXBIG_H -#define _DT_BINDINGS_LEDS_NETXBIG_H - -#define NETXBIG_LED_OFF 0 -#define NETXBIG_LED_ON 1 -#define NETXBIG_LED_SATA 2 -#define NETXBIG_LED_TIMER1 3 -#define NETXBIG_LED_TIMER2 4 - -#endif /* _DT_BINDINGS_LEDS_NETXBIG_H */ diff --git a/include/dt-bindings/leds/leds-ns2.h b/include/dt-bindings/leds/leds-ns2.h deleted file mode 100644 index fd615749e70..00000000000 --- a/include/dt-bindings/leds/leds-ns2.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_LEDS_NS2_H -#define _DT_BINDINGS_LEDS_NS2_H - -#define NS_V2_LED_OFF 0 -#define NS_V2_LED_ON 1 -#define NS_V2_LED_SATA 2 - -#endif diff --git a/include/dt-bindings/mux/ti-serdes.h b/include/dt-bindings/mux/ti-serdes.h deleted file mode 100644 index b0b1091aad6..00000000000 --- a/include/dt-bindings/mux/ti-serdes.h +++ /dev/null @@ -1,190 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for SERDES MUX for TI SoCs - */ - -#ifndef _DT_BINDINGS_MUX_TI_SERDES -#define _DT_BINDINGS_MUX_TI_SERDES - -/* - * These bindings are deprecated, because they do not match the actual - * concept of bindings but rather contain pure constants values used only - * in DTS board files. - * Instead include the header in the DTS source directory. - */ -#warning "These bindings are deprecated. Instead, use the header in the DTS source directory." - -/* J721E */ - -#define J721E_SERDES0_LANE0_QSGMII_LANE1 0x0 -#define J721E_SERDES0_LANE0_PCIE0_LANE0 0x1 -#define J721E_SERDES0_LANE0_USB3_0_SWAP 0x2 -#define J721E_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J721E_SERDES0_LANE1_QSGMII_LANE2 0x0 -#define J721E_SERDES0_LANE1_PCIE0_LANE1 0x1 -#define J721E_SERDES0_LANE1_USB3_0 0x2 -#define J721E_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J721E_SERDES1_LANE0_QSGMII_LANE3 0x0 -#define J721E_SERDES1_LANE0_PCIE1_LANE0 0x1 -#define J721E_SERDES1_LANE0_USB3_1_SWAP 0x2 -#define J721E_SERDES1_LANE0_SGMII_LANE0 0x3 - -#define J721E_SERDES1_LANE1_QSGMII_LANE4 0x0 -#define J721E_SERDES1_LANE1_PCIE1_LANE1 0x1 -#define J721E_SERDES1_LANE1_USB3_1 0x2 -#define J721E_SERDES1_LANE1_SGMII_LANE1 0x3 - -#define J721E_SERDES2_LANE0_IP1_UNUSED 0x0 -#define J721E_SERDES2_LANE0_PCIE2_LANE0 0x1 -#define J721E_SERDES2_LANE0_USB3_1_SWAP 0x2 -#define J721E_SERDES2_LANE0_SGMII_LANE0 0x3 - -#define J721E_SERDES2_LANE1_IP1_UNUSED 0x0 -#define J721E_SERDES2_LANE1_PCIE2_LANE1 0x1 -#define J721E_SERDES2_LANE1_USB3_1 0x2 -#define J721E_SERDES2_LANE1_SGMII_LANE1 0x3 - -#define J721E_SERDES3_LANE0_IP1_UNUSED 0x0 -#define J721E_SERDES3_LANE0_PCIE3_LANE0 0x1 -#define J721E_SERDES3_LANE0_USB3_0_SWAP 0x2 -#define J721E_SERDES3_LANE0_IP4_UNUSED 0x3 - -#define J721E_SERDES3_LANE1_IP1_UNUSED 0x0 -#define J721E_SERDES3_LANE1_PCIE3_LANE1 0x1 -#define J721E_SERDES3_LANE1_USB3_0 0x2 -#define J721E_SERDES3_LANE1_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE0_EDP_LANE0 0x0 -#define J721E_SERDES4_LANE0_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE0_QSGMII_LANE5 0x2 -#define J721E_SERDES4_LANE0_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE1_EDP_LANE1 0x0 -#define J721E_SERDES4_LANE1_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE1_QSGMII_LANE6 0x2 -#define J721E_SERDES4_LANE1_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE2_EDP_LANE2 0x0 -#define J721E_SERDES4_LANE2_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE2_QSGMII_LANE7 0x2 -#define J721E_SERDES4_LANE2_IP4_UNUSED 0x3 - -#define J721E_SERDES4_LANE3_EDP_LANE3 0x0 -#define J721E_SERDES4_LANE3_IP2_UNUSED 0x1 -#define J721E_SERDES4_LANE3_QSGMII_LANE8 0x2 -#define J721E_SERDES4_LANE3_IP4_UNUSED 0x3 - -/* J7200 */ - -#define J7200_SERDES0_LANE0_QSGMII_LANE3 0x0 -#define J7200_SERDES0_LANE0_PCIE1_LANE0 0x1 -#define J7200_SERDES0_LANE0_IP3_UNUSED 0x2 -#define J7200_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J7200_SERDES0_LANE1_QSGMII_LANE4 0x0 -#define J7200_SERDES0_LANE1_PCIE1_LANE1 0x1 -#define J7200_SERDES0_LANE1_IP3_UNUSED 0x2 -#define J7200_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J7200_SERDES0_LANE2_QSGMII_LANE1 0x0 -#define J7200_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J7200_SERDES0_LANE2_IP3_UNUSED 0x2 -#define J7200_SERDES0_LANE2_IP4_UNUSED 0x3 - -#define J7200_SERDES0_LANE3_QSGMII_LANE2 0x0 -#define J7200_SERDES0_LANE3_PCIE1_LANE3 0x1 -#define J7200_SERDES0_LANE3_USB 0x2 -#define J7200_SERDES0_LANE3_IP4_UNUSED 0x3 - -/* AM64 */ - -#define AM64_SERDES0_LANE0_PCIE0 0x0 -#define AM64_SERDES0_LANE0_USB 0x1 - -/* J721S2 */ - -#define J721S2_SERDES0_LANE0_EDP_LANE0 0x0 -#define J721S2_SERDES0_LANE0_PCIE1_LANE0 0x1 -#define J721S2_SERDES0_LANE0_IP3_UNUSED 0x2 -#define J721S2_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J721S2_SERDES0_LANE1_EDP_LANE1 0x0 -#define J721S2_SERDES0_LANE1_PCIE1_LANE1 0x1 -#define J721S2_SERDES0_LANE1_USB 0x2 -#define J721S2_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J721S2_SERDES0_LANE2_EDP_LANE2 0x0 -#define J721S2_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J721S2_SERDES0_LANE2_IP3_UNUSED 0x2 -#define J721S2_SERDES0_LANE2_IP4_UNUSED 0x3 - -#define J721S2_SERDES0_LANE3_EDP_LANE3 0x0 -#define J721S2_SERDES0_LANE3_PCIE1_LANE3 0x1 -#define J721S2_SERDES0_LANE3_USB 0x2 -#define J721S2_SERDES0_LANE3_IP4_UNUSED 0x3 - -/* J784S4 */ - -#define J784S4_SERDES0_LANE0_IP1_UNUSED 0x0 -#define J784S4_SERDES0_LANE0_PCIE1_LANE0 0x1 -#define J784S4_SERDES0_LANE0_IP3_UNUSED 0x2 -#define J784S4_SERDES0_LANE0_IP4_UNUSED 0x3 - -#define J784S4_SERDES0_LANE1_IP1_UNUSED 0x0 -#define J784S4_SERDES0_LANE1_PCIE1_LANE1 0x1 -#define J784S4_SERDES0_LANE1_IP3_UNUSED 0x2 -#define J784S4_SERDES0_LANE1_IP4_UNUSED 0x3 - -#define J784S4_SERDES0_LANE2_PCIE3_LANE0 0x0 -#define J784S4_SERDES0_LANE2_PCIE1_LANE2 0x1 -#define J784S4_SERDES0_LANE2_IP3_UNUSED 0x2 -#define J784S4_SERDES0_LANE2_IP4_UNUSED 0x3 - -#define J784S4_SERDES0_LANE3_PCIE3_LANE1 0x0 -#define J784S4_SERDES0_LANE3_PCIE1_LANE3 0x1 -#define J784S4_SERDES0_LANE3_USB 0x2 -#define J784S4_SERDES0_LANE3_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE0_QSGMII_LANE3 0x0 -#define J784S4_SERDES1_LANE0_PCIE0_LANE0 0x1 -#define J784S4_SERDES1_LANE0_IP3_UNUSED 0x2 -#define J784S4_SERDES1_LANE0_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE1_QSGMII_LANE4 0x0 -#define J784S4_SERDES1_LANE1_PCIE0_LANE1 0x1 -#define J784S4_SERDES1_LANE1_IP3_UNUSED 0x2 -#define J784S4_SERDES1_LANE1_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE2_QSGMII_LANE1 0x0 -#define J784S4_SERDES1_LANE2_PCIE0_LANE2 0x1 -#define J784S4_SERDES1_LANE2_PCIE2_LANE0 0x2 -#define J784S4_SERDES1_LANE2_IP4_UNUSED 0x3 - -#define J784S4_SERDES1_LANE3_QSGMII_LANE2 0x0 -#define J784S4_SERDES1_LANE3_PCIE0_LANE3 0x1 -#define J784S4_SERDES1_LANE3_PCIE2_LANE1 0x2 -#define J784S4_SERDES1_LANE3_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE0_QSGMII_LANE5 0x0 -#define J784S4_SERDES2_LANE0_IP2_UNUSED 0x1 -#define J784S4_SERDES2_LANE0_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE0_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE1_QSGMII_LANE6 0x0 -#define J784S4_SERDES2_LANE1_IP2_UNUSED 0x1 -#define J784S4_SERDES2_LANE1_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE1_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE2_QSGMII_LANE7 0x0 -#define J784S4_SERDES2_LANE2_QSGMII_LANE1 0x1 -#define J784S4_SERDES2_LANE2_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE2_IP4_UNUSED 0x3 - -#define J784S4_SERDES2_LANE3_QSGMII_LANE8 0x0 -#define J784S4_SERDES2_LANE3_QSGMII_LANE2 0x1 -#define J784S4_SERDES2_LANE3_IP3_UNUSED 0x2 -#define J784S4_SERDES2_LANE3_IP4_UNUSED 0x3 - -#endif /* _DT_BINDINGS_MUX_TI_SERDES */ diff --git a/include/dt-bindings/net/mscc-phy-vsc8531.h b/include/dt-bindings/net/mscc-phy-vsc8531.h deleted file mode 100644 index c340437414f..00000000000 --- a/include/dt-bindings/net/mscc-phy-vsc8531.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Device Tree constants for Microsemi VSC8531 PHY - * - * Author: Nagaraju Lakkaraju - * - * Copyright (c) 2017 Microsemi Corporation - */ - -#ifndef _DT_BINDINGS_MSCC_VSC8531_H -#define _DT_BINDINGS_MSCC_VSC8531_H - -/* PHY LED Modes */ -#define VSC8531_LINK_ACTIVITY 0 -#define VSC8531_LINK_1000_ACTIVITY 1 -#define VSC8531_LINK_100_ACTIVITY 2 -#define VSC8531_LINK_10_ACTIVITY 3 -#define VSC8531_LINK_100_1000_ACTIVITY 4 -#define VSC8531_LINK_10_1000_ACTIVITY 5 -#define VSC8531_LINK_10_100_ACTIVITY 6 -#define VSC8584_LINK_100FX_1000X_ACTIVITY 7 -#define VSC8531_DUPLEX_COLLISION 8 -#define VSC8531_COLLISION 9 -#define VSC8531_ACTIVITY 10 -#define VSC8584_100FX_1000X_ACTIVITY 11 -#define VSC8531_AUTONEG_FAULT 12 -#define VSC8531_SERIAL_MODE 13 -#define VSC8531_FORCE_LED_OFF 14 -#define VSC8531_FORCE_LED_ON 15 - -#endif diff --git a/include/dt-bindings/phy/phy-am654-serdes.h b/include/dt-bindings/phy/phy-am654-serdes.h deleted file mode 100644 index e8d901729ed..00000000000 --- a/include/dt-bindings/phy/phy-am654-serdes.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for AM654 SERDES. - */ - -#ifndef _DT_BINDINGS_AM654_SERDES -#define _DT_BINDINGS_AM654_SERDES - -#define AM654_SERDES_CMU_REFCLK 0 -#define AM654_SERDES_LO_REFCLK 1 -#define AM654_SERDES_RO_REFCLK 2 - -#endif /* _DT_BINDINGS_AM654_SERDES */ diff --git a/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h b/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h deleted file mode 100644 index 81ebd58ca50..00000000000 --- a/include/dt-bindings/pinctrl/brcm,pinctrl-ns3.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2020 Broadcom. - */ - -#ifndef __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__ -#define __DT_BINDINGS_PINCTRL_BRCM_STINGRAY_H__ - -/* Alternate functions available in MUX controller */ -#define MODE_NITRO 0 -#define MODE_NAND 1 -#define MODE_PNOR 2 -#define MODE_GPIO 3 - -/* Pad configuration attribute */ -#define PAD_SLEW_RATE_ENA BIT(0) -#define PAD_SLEW_RATE_ENA_MASK BIT(0) - -#define PAD_DRIVE_STRENGTH_2_MA (0 << 1) -#define PAD_DRIVE_STRENGTH_4_MA BIT(1) -#define PAD_DRIVE_STRENGTH_6_MA (2 << 1) -#define PAD_DRIVE_STRENGTH_8_MA (3 << 1) -#define PAD_DRIVE_STRENGTH_10_MA (4 << 1) -#define PAD_DRIVE_STRENGTH_12_MA (5 << 1) -#define PAD_DRIVE_STRENGTH_14_MA (6 << 1) -#define PAD_DRIVE_STRENGTH_16_MA (7 << 1) -#define PAD_DRIVE_STRENGTH_MASK (7 << 1) - -#define PAD_PULL_UP_ENA BIT(4) -#define PAD_PULL_UP_ENA_MASK BIT(4) - -#define PAD_PULL_DOWN_ENA BIT(5) -#define PAD_PULL_DOWN_ENA_MASK BIT(5) - -#define PAD_INPUT_PATH_DIS BIT(6) -#define PAD_INPUT_PATH_DIS_MASK BIT(6) - -#define PAD_HYSTERESIS_ENA BIT(7) -#define PAD_HYSTERESIS_ENA_MASK BIT(7) - -#endif diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h deleted file mode 100644 index e8418318eb9..00000000000 --- a/include/dt-bindings/pinctrl/k3.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for pinctrl bindings for TI's K3 SoC - * family. - * - * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ - */ -#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H -#define _DT_BINDINGS_PINCTRL_TI_K3_H - -#define PULLUDEN_SHIFT (16) -#define PULLTYPESEL_SHIFT (17) -#define RXACTIVE_SHIFT (18) - -#define PULL_DISABLE (1 << PULLUDEN_SHIFT) -#define PULL_ENABLE (0 << PULLUDEN_SHIFT) - -#define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) -#define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) - -#define INPUT_EN (1 << RXACTIVE_SHIFT) -#define INPUT_DISABLE (0 << RXACTIVE_SHIFT) - -/* Only these macros are expected be used directly in device tree files */ -#define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) -#define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) -#define PIN_INPUT (INPUT_EN | PULL_DISABLE) -#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) - -#define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) -#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) - -#endif diff --git a/include/dt-bindings/reset/xlnx-versal-resets.h b/include/dt-bindings/reset/xlnx-versal-resets.h deleted file mode 100644 index 895424e9b0e..00000000000 --- a/include/dt-bindings/reset/xlnx-versal-resets.h +++ /dev/null @@ -1,105 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2020 Xilinx, Inc. - */ - -#ifndef _DT_BINDINGS_VERSAL_RESETS_H -#define _DT_BINDINGS_VERSAL_RESETS_H - -#define VERSAL_RST_PMC_POR (0xc30c001U) -#define VERSAL_RST_PMC (0xc410002U) -#define VERSAL_RST_PS_POR (0xc30c003U) -#define VERSAL_RST_PL_POR (0xc30c004U) -#define VERSAL_RST_NOC_POR (0xc30c005U) -#define VERSAL_RST_FPD_POR (0xc30c006U) -#define VERSAL_RST_ACPU_0_POR (0xc30c007U) -#define VERSAL_RST_ACPU_1_POR (0xc30c008U) -#define VERSAL_RST_OCM2_POR (0xc30c009U) -#define VERSAL_RST_PS_SRST (0xc41000aU) -#define VERSAL_RST_PL_SRST (0xc41000bU) -#define VERSAL_RST_NOC (0xc41000cU) -#define VERSAL_RST_NPI (0xc41000dU) -#define VERSAL_RST_SYS_RST_1 (0xc41000eU) -#define VERSAL_RST_SYS_RST_2 (0xc41000fU) -#define VERSAL_RST_SYS_RST_3 (0xc410010U) -#define VERSAL_RST_FPD (0xc410011U) -#define VERSAL_RST_PL0 (0xc410012U) -#define VERSAL_RST_PL1 (0xc410013U) -#define VERSAL_RST_PL2 (0xc410014U) -#define VERSAL_RST_PL3 (0xc410015U) -#define VERSAL_RST_APU (0xc410016U) -#define VERSAL_RST_ACPU_0 (0xc410017U) -#define VERSAL_RST_ACPU_1 (0xc410018U) -#define VERSAL_RST_ACPU_L2 (0xc410019U) -#define VERSAL_RST_ACPU_GIC (0xc41001aU) -#define VERSAL_RST_RPU_ISLAND (0xc41001bU) -#define VERSAL_RST_RPU_AMBA (0xc41001cU) -#define VERSAL_RST_R5_0 (0xc41001dU) -#define VERSAL_RST_R5_1 (0xc41001eU) -#define VERSAL_RST_SYSMON_PMC_SEQ_RST (0xc41001fU) -#define VERSAL_RST_SYSMON_PMC_CFG_RST (0xc410020U) -#define VERSAL_RST_SYSMON_FPD_CFG_RST (0xc410021U) -#define VERSAL_RST_SYSMON_FPD_SEQ_RST (0xc410022U) -#define VERSAL_RST_SYSMON_LPD (0xc410023U) -#define VERSAL_RST_PDMA_RST1 (0xc410024U) -#define VERSAL_RST_PDMA_RST0 (0xc410025U) -#define VERSAL_RST_ADMA (0xc410026U) -#define VERSAL_RST_TIMESTAMP (0xc410027U) -#define VERSAL_RST_OCM (0xc410028U) -#define VERSAL_RST_OCM2_RST (0xc410029U) -#define VERSAL_RST_IPI (0xc41002aU) -#define VERSAL_RST_SBI (0xc41002bU) -#define VERSAL_RST_LPD (0xc41002cU) -#define VERSAL_RST_QSPI (0xc10402dU) -#define VERSAL_RST_OSPI (0xc10402eU) -#define VERSAL_RST_SDIO_0 (0xc10402fU) -#define VERSAL_RST_SDIO_1 (0xc104030U) -#define VERSAL_RST_I2C_PMC (0xc104031U) -#define VERSAL_RST_GPIO_PMC (0xc104032U) -#define VERSAL_RST_GEM_0 (0xc104033U) -#define VERSAL_RST_GEM_1 (0xc104034U) -#define VERSAL_RST_SPARE (0xc104035U) -#define VERSAL_RST_USB_0 (0xc104036U) -#define VERSAL_RST_UART_0 (0xc104037U) -#define VERSAL_RST_UART_1 (0xc104038U) -#define VERSAL_RST_SPI_0 (0xc104039U) -#define VERSAL_RST_SPI_1 (0xc10403aU) -#define VERSAL_RST_CAN_FD_0 (0xc10403bU) -#define VERSAL_RST_CAN_FD_1 (0xc10403cU) -#define VERSAL_RST_I2C_0 (0xc10403dU) -#define VERSAL_RST_I2C_1 (0xc10403eU) -#define VERSAL_RST_GPIO_LPD (0xc10403fU) -#define VERSAL_RST_TTC_0 (0xc104040U) -#define VERSAL_RST_TTC_1 (0xc104041U) -#define VERSAL_RST_TTC_2 (0xc104042U) -#define VERSAL_RST_TTC_3 (0xc104043U) -#define VERSAL_RST_SWDT_FPD (0xc104044U) -#define VERSAL_RST_SWDT_LPD (0xc104045U) -#define VERSAL_RST_USB (0xc104046U) -#define VERSAL_RST_DPC (0xc208047U) -#define VERSAL_RST_PMCDBG (0xc208048U) -#define VERSAL_RST_DBG_TRACE (0xc208049U) -#define VERSAL_RST_DBG_FPD (0xc20804aU) -#define VERSAL_RST_DBG_TSTMP (0xc20804bU) -#define VERSAL_RST_RPU0_DBG (0xc20804cU) -#define VERSAL_RST_RPU1_DBG (0xc20804dU) -#define VERSAL_RST_HSDP (0xc20804eU) -#define VERSAL_RST_DBG_LPD (0xc20804fU) -#define VERSAL_RST_CPM_POR (0xc30c050U) -#define VERSAL_RST_CPM (0xc410051U) -#define VERSAL_RST_CPMDBG (0xc208052U) -#define VERSAL_RST_PCIE_CFG (0xc410053U) -#define VERSAL_RST_PCIE_CORE0 (0xc410054U) -#define VERSAL_RST_PCIE_CORE1 (0xc410055U) -#define VERSAL_RST_PCIE_DMA (0xc410056U) -#define VERSAL_RST_CMN (0xc410057U) -#define VERSAL_RST_L2_0 (0xc410058U) -#define VERSAL_RST_L2_1 (0xc410059U) -#define VERSAL_RST_ADDR_REMAP (0xc41005aU) -#define VERSAL_RST_CPI0 (0xc41005bU) -#define VERSAL_RST_CPI1 (0xc41005cU) -#define VERSAL_RST_XRAM (0xc30c05dU) -#define VERSAL_RST_AIE_ARRAY (0xc10405eU) -#define VERSAL_RST_AIE_SHIM (0xc10405fU) - -#endif diff --git a/include/dt-bindings/sound/tlv320aic31xx.h b/include/dt-bindings/sound/tlv320aic31xx.h deleted file mode 100644 index 4a80238ab25..00000000000 --- a/include/dt-bindings/sound/tlv320aic31xx.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_TLV320AIC31XX_H -#define __DT_TLV320AIC31XX_H - -#define MICBIAS_2_0V 1 -#define MICBIAS_2_5V 2 -#define MICBIAS_AVDDV 3 - -#define PLL_CLKIN_MCLK 0x00 -#define PLL_CLKIN_BCLK 0x01 -#define PLL_CLKIN_GPIO1 0x02 -#define PLL_CLKIN_DIN 0x03 - -#endif /* __DT_TLV320AIC31XX_H */ -- cgit v1.3.1 From f335f5265bfd3464dfb2bfc716fa2b5f7aab360b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 27 May 2025 16:18:34 -0600 Subject: include/dt-bindings: Remove identical headers As part of moving to using OF_UPSTREAM and so the upstream dt-bindings headers we have a number of these headers that are in our include directory and are currently identical to the versions in dts/upstream. We can remove these now to prevent future conflicts. Signed-off-by: Tom Rini --- include/dt-bindings/arm/ux500_pm_domains.h | 15 - include/dt-bindings/bus/moxtet.h | 16 - include/dt-bindings/clock/actions,s700-cmu.h | 118 --- include/dt-bindings/clock/actions,s900-cmu.h | 129 ---- include/dt-bindings/clock/bcm-nsp.h | 51 -- include/dt-bindings/clock/bcm2835-aux.h | 9 - include/dt-bindings/clock/bcm2835.h | 62 -- include/dt-bindings/clock/fsl,qoriq-clockgen.h | 15 - include/dt-bindings/clock/hi3660-clock.h | 214 ----- include/dt-bindings/clock/lpc32xx-clock.h | 58 -- include/dt-bindings/clock/r7s72100-clock.h | 112 --- include/dt-bindings/clock/r9a06g032-sysctrl.h | 149 ---- include/dt-bindings/clock/sifive-fu740-prci.h | 24 - include/dt-bindings/clock/sophgo,cv1800.h | 176 ----- include/dt-bindings/clock/ste-ab8500.h | 12 - include/dt-bindings/clock/sun20i-d1-ccu.h | 158 ---- include/dt-bindings/clock/sun20i-d1-r-ccu.h | 19 - include/dt-bindings/clock/sun4i-a10-ccu.h | 202 ----- include/dt-bindings/clock/sun50i-h6-ccu.h | 125 --- include/dt-bindings/clock/sun50i-h6-r-ccu.h | 27 - include/dt-bindings/clock/sun5i-ccu.h | 97 --- include/dt-bindings/clock/sun6i-a31-ccu.h | 193 ----- include/dt-bindings/clock/sun6i-rtc.h | 10 - include/dt-bindings/clock/sun7i-a20-ccu.h | 53 -- include/dt-bindings/clock/sun8i-a23-a33-ccu.h | 129 ---- include/dt-bindings/clock/sun8i-a83t-ccu.h | 140 ---- include/dt-bindings/clock/sun8i-de2.h | 21 - include/dt-bindings/clock/sun8i-h3-ccu.h | 152 ---- include/dt-bindings/clock/sun8i-r-ccu.h | 59 -- include/dt-bindings/clock/sun8i-r40-ccu.h | 191 ----- include/dt-bindings/clock/sun8i-tcon-top.h | 11 - include/dt-bindings/clock/sun8i-v3s-ccu.h | 111 --- include/dt-bindings/clock/sun9i-a80-ccu.h | 162 ---- include/dt-bindings/clock/sun9i-a80-de.h | 80 -- include/dt-bindings/clock/sun9i-a80-usb.h | 59 -- include/dt-bindings/clock/suniv-ccu-f1c100s.h | 72 -- include/dt-bindings/clock/versaclock.h | 13 - include/dt-bindings/clock/vf610-clock.h | 202 ----- include/dt-bindings/display/tda998x.h | 8 - include/dt-bindings/dma/sun4i-a10.h | 56 -- include/dt-bindings/dma/xlnx-zynqmp-dpdma.h | 16 - include/dt-bindings/gpio/uniphier-gpio.h | 18 - include/dt-bindings/leds/leds-pca9532.h | 18 - include/dt-bindings/media/tda1997x.h | 74 -- include/dt-bindings/mfd/at91-usart.h | 17 - include/dt-bindings/mfd/atmel-flexcom.h | 15 - include/dt-bindings/net/microchip-lan78xx.h | 21 - include/dt-bindings/net/qca-ar803x.h | 13 - include/dt-bindings/phy/phy-ti.h | 21 - include/dt-bindings/pinctrl/am33xx.h | 172 ----- include/dt-bindings/pinctrl/apple.h | 13 - include/dt-bindings/pinctrl/bcm2835.h | 26 - include/dt-bindings/pinctrl/mt8365-pinfunc.h | 858 --------------------- include/dt-bindings/pinctrl/pinctrl-zynqmp.h | 19 - include/dt-bindings/pinctrl/rzn1-pinctrl.h | 141 ---- include/dt-bindings/pinctrl/sun4i-a10.h | 62 -- include/dt-bindings/power/mediatek,mt8365-power.h | 19 - include/dt-bindings/power/owl-s700-powergate.h | 19 - include/dt-bindings/power/rk3228-power.h | 21 - include/dt-bindings/power/xlnx-zynqmp-power.h | 45 -- .../dt-bindings/regulator/dlg,da9063-regulator.h | 16 - include/dt-bindings/reset/actions,s700-reset.h | 34 - include/dt-bindings/reset/actions,s900-reset.h | 65 -- .../dt-bindings/reset/raspberrypi,firmware-reset.h | 13 - include/dt-bindings/reset/sama7g5-reset.h | 10 - include/dt-bindings/reset/snps,hsdk-reset.h | 17 - include/dt-bindings/reset/sun20i-d1-ccu.h | 79 -- include/dt-bindings/reset/sun20i-d1-r-ccu.h | 16 - include/dt-bindings/reset/sun4i-a10-ccu.h | 69 -- include/dt-bindings/reset/sun50i-a64-ccu.h | 98 --- include/dt-bindings/reset/sun50i-h6-ccu.h | 73 -- include/dt-bindings/reset/sun50i-h6-r-ccu.h | 18 - include/dt-bindings/reset/sun5i-ccu.h | 23 - include/dt-bindings/reset/sun6i-a31-ccu.h | 106 --- include/dt-bindings/reset/sun8i-a23-a33-ccu.h | 87 --- include/dt-bindings/reset/sun8i-a83t-ccu.h | 98 --- include/dt-bindings/reset/sun8i-de2.h | 15 - include/dt-bindings/reset/sun8i-h3-ccu.h | 106 --- include/dt-bindings/reset/sun8i-r-ccu.h | 53 -- include/dt-bindings/reset/sun8i-r40-ccu.h | 130 ---- include/dt-bindings/reset/sun8i-v3s-ccu.h | 81 -- include/dt-bindings/reset/sun9i-a80-ccu.h | 102 --- include/dt-bindings/reset/sun9i-a80-de.h | 58 -- include/dt-bindings/reset/sun9i-a80-usb.h | 56 -- include/dt-bindings/reset/suniv-ccu-f1c100s.h | 38 - include/dt-bindings/reset/xlnx-zynqmp-resets.h | 130 ---- include/dt-bindings/soc/bcm2835-pm.h | 28 - include/dt-bindings/soc/ti,sci_pm_domain.h | 9 - include/dt-bindings/sound/apq8016-lpass.h | 9 - include/dt-bindings/sound/microchip,pdmc.h | 13 - 90 files changed, 6768 deletions(-) delete mode 100644 include/dt-bindings/arm/ux500_pm_domains.h delete mode 100644 include/dt-bindings/bus/moxtet.h delete mode 100644 include/dt-bindings/clock/actions,s700-cmu.h delete mode 100644 include/dt-bindings/clock/actions,s900-cmu.h delete mode 100644 include/dt-bindings/clock/bcm-nsp.h delete mode 100644 include/dt-bindings/clock/bcm2835-aux.h delete mode 100644 include/dt-bindings/clock/bcm2835.h delete mode 100644 include/dt-bindings/clock/fsl,qoriq-clockgen.h delete mode 100644 include/dt-bindings/clock/hi3660-clock.h delete mode 100644 include/dt-bindings/clock/lpc32xx-clock.h delete mode 100644 include/dt-bindings/clock/r7s72100-clock.h delete mode 100644 include/dt-bindings/clock/r9a06g032-sysctrl.h delete mode 100644 include/dt-bindings/clock/sifive-fu740-prci.h delete mode 100644 include/dt-bindings/clock/sophgo,cv1800.h delete mode 100644 include/dt-bindings/clock/ste-ab8500.h delete mode 100644 include/dt-bindings/clock/sun20i-d1-ccu.h delete mode 100644 include/dt-bindings/clock/sun20i-d1-r-ccu.h delete mode 100644 include/dt-bindings/clock/sun4i-a10-ccu.h delete mode 100644 include/dt-bindings/clock/sun50i-h6-ccu.h delete mode 100644 include/dt-bindings/clock/sun50i-h6-r-ccu.h delete mode 100644 include/dt-bindings/clock/sun5i-ccu.h delete mode 100644 include/dt-bindings/clock/sun6i-a31-ccu.h delete mode 100644 include/dt-bindings/clock/sun6i-rtc.h delete mode 100644 include/dt-bindings/clock/sun7i-a20-ccu.h delete mode 100644 include/dt-bindings/clock/sun8i-a23-a33-ccu.h delete mode 100644 include/dt-bindings/clock/sun8i-a83t-ccu.h delete mode 100644 include/dt-bindings/clock/sun8i-de2.h delete mode 100644 include/dt-bindings/clock/sun8i-h3-ccu.h delete mode 100644 include/dt-bindings/clock/sun8i-r-ccu.h delete mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h delete mode 100644 include/dt-bindings/clock/sun8i-tcon-top.h delete mode 100644 include/dt-bindings/clock/sun8i-v3s-ccu.h delete mode 100644 include/dt-bindings/clock/sun9i-a80-ccu.h delete mode 100644 include/dt-bindings/clock/sun9i-a80-de.h delete mode 100644 include/dt-bindings/clock/sun9i-a80-usb.h delete mode 100644 include/dt-bindings/clock/suniv-ccu-f1c100s.h delete mode 100644 include/dt-bindings/clock/versaclock.h delete mode 100644 include/dt-bindings/clock/vf610-clock.h delete mode 100644 include/dt-bindings/display/tda998x.h delete mode 100644 include/dt-bindings/dma/sun4i-a10.h delete mode 100644 include/dt-bindings/dma/xlnx-zynqmp-dpdma.h delete mode 100644 include/dt-bindings/gpio/uniphier-gpio.h delete mode 100644 include/dt-bindings/leds/leds-pca9532.h delete mode 100644 include/dt-bindings/media/tda1997x.h delete mode 100644 include/dt-bindings/mfd/at91-usart.h delete mode 100644 include/dt-bindings/mfd/atmel-flexcom.h delete mode 100644 include/dt-bindings/net/microchip-lan78xx.h delete mode 100644 include/dt-bindings/net/qca-ar803x.h delete mode 100644 include/dt-bindings/phy/phy-ti.h delete mode 100644 include/dt-bindings/pinctrl/am33xx.h delete mode 100644 include/dt-bindings/pinctrl/apple.h delete mode 100644 include/dt-bindings/pinctrl/bcm2835.h delete mode 100644 include/dt-bindings/pinctrl/mt8365-pinfunc.h delete mode 100644 include/dt-bindings/pinctrl/pinctrl-zynqmp.h delete mode 100644 include/dt-bindings/pinctrl/rzn1-pinctrl.h delete mode 100644 include/dt-bindings/pinctrl/sun4i-a10.h delete mode 100644 include/dt-bindings/power/mediatek,mt8365-power.h delete mode 100644 include/dt-bindings/power/owl-s700-powergate.h delete mode 100644 include/dt-bindings/power/rk3228-power.h delete mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h delete mode 100644 include/dt-bindings/regulator/dlg,da9063-regulator.h delete mode 100644 include/dt-bindings/reset/actions,s700-reset.h delete mode 100644 include/dt-bindings/reset/actions,s900-reset.h delete mode 100644 include/dt-bindings/reset/raspberrypi,firmware-reset.h delete mode 100644 include/dt-bindings/reset/sama7g5-reset.h delete mode 100644 include/dt-bindings/reset/snps,hsdk-reset.h delete mode 100644 include/dt-bindings/reset/sun20i-d1-ccu.h delete mode 100644 include/dt-bindings/reset/sun20i-d1-r-ccu.h delete mode 100644 include/dt-bindings/reset/sun4i-a10-ccu.h delete mode 100644 include/dt-bindings/reset/sun50i-a64-ccu.h delete mode 100644 include/dt-bindings/reset/sun50i-h6-ccu.h delete mode 100644 include/dt-bindings/reset/sun50i-h6-r-ccu.h delete mode 100644 include/dt-bindings/reset/sun5i-ccu.h delete mode 100644 include/dt-bindings/reset/sun6i-a31-ccu.h delete mode 100644 include/dt-bindings/reset/sun8i-a23-a33-ccu.h delete mode 100644 include/dt-bindings/reset/sun8i-a83t-ccu.h delete mode 100644 include/dt-bindings/reset/sun8i-de2.h delete mode 100644 include/dt-bindings/reset/sun8i-h3-ccu.h delete mode 100644 include/dt-bindings/reset/sun8i-r-ccu.h delete mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h delete mode 100644 include/dt-bindings/reset/sun8i-v3s-ccu.h delete mode 100644 include/dt-bindings/reset/sun9i-a80-ccu.h delete mode 100644 include/dt-bindings/reset/sun9i-a80-de.h delete mode 100644 include/dt-bindings/reset/sun9i-a80-usb.h delete mode 100644 include/dt-bindings/reset/suniv-ccu-f1c100s.h delete mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h delete mode 100644 include/dt-bindings/soc/bcm2835-pm.h delete mode 100644 include/dt-bindings/soc/ti,sci_pm_domain.h delete mode 100644 include/dt-bindings/sound/apq8016-lpass.h delete mode 100644 include/dt-bindings/sound/microchip,pdmc.h (limited to 'include') diff --git a/include/dt-bindings/arm/ux500_pm_domains.h b/include/dt-bindings/arm/ux500_pm_domains.h deleted file mode 100644 index 9bd764f0c9e..00000000000 --- a/include/dt-bindings/arm/ux500_pm_domains.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (C) 2014 Linaro Ltd. - * - * Author: Ulf Hansson - */ -#ifndef _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H -#define _DT_BINDINGS_ARM_UX500_PM_DOMAINS_H - -#define DOMAIN_VAPE 0 - -/* Number of PM domains. */ -#define NR_DOMAINS (DOMAIN_VAPE + 1) - -#endif diff --git a/include/dt-bindings/bus/moxtet.h b/include/dt-bindings/bus/moxtet.h deleted file mode 100644 index 10528de7b3e..00000000000 --- a/include/dt-bindings/bus/moxtet.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Constant for device tree bindings for Turris Mox module configuration bus - * - * Copyright (C) 2019 Marek Behún - */ - -#ifndef _DT_BINDINGS_BUS_MOXTET_H -#define _DT_BINDINGS_BUS_MOXTET_H - -#define MOXTET_IRQ_PCI 0 -#define MOXTET_IRQ_USB3 4 -#define MOXTET_IRQ_PERIDOT(n) (8 + (n)) -#define MOXTET_IRQ_TOPAZ 12 - -#endif /* _DT_BINDINGS_BUS_MOXTET_H */ diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h deleted file mode 100644 index 3e194299672..00000000000 --- a/include/dt-bindings/clock/actions,s700-cmu.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Device Tree binding constants for Actions Semi S700 Clock Management Unit - * - * Copyright (c) 2014 Actions Semi Inc. - * Author: David Liu - * - * Author: Pathiban Nallathambi - * Author: Saravanan Sekar - */ - -#ifndef __DT_BINDINGS_CLOCK_S700_H -#define __DT_BINDINGS_CLOCK_S700_H - -#define CLK_NONE 0 - -/* pll clocks */ -#define CLK_CORE_PLL 1 -#define CLK_DEV_PLL 2 -#define CLK_DDR_PLL 3 -#define CLK_NAND_PLL 4 -#define CLK_DISPLAY_PLL 5 -#define CLK_TVOUT_PLL 6 -#define CLK_CVBS_PLL 7 -#define CLK_AUDIO_PLL 8 -#define CLK_ETHERNET_PLL 9 - -/* system clock */ -#define CLK_CPU 10 -#define CLK_DEV 11 -#define CLK_AHB 12 -#define CLK_APB 13 -#define CLK_DMAC 14 -#define CLK_NOC0_CLK_MUX 15 -#define CLK_NOC1_CLK_MUX 16 -#define CLK_HP_CLK_MUX 17 -#define CLK_HP_CLK_DIV 18 -#define CLK_NOC1_CLK_DIV 19 -#define CLK_NOC0 20 -#define CLK_NOC1 21 -#define CLK_SENOR_SRC 22 - -/* peripheral device clock */ -#define CLK_GPIO 23 -#define CLK_TIMER 24 -#define CLK_DSI 25 -#define CLK_CSI 26 -#define CLK_SI 27 -#define CLK_DE 28 -#define CLK_HDE 29 -#define CLK_VDE 30 -#define CLK_VCE 31 -#define CLK_NAND 32 -#define CLK_SD0 33 -#define CLK_SD1 34 -#define CLK_SD2 35 - -#define CLK_UART0 36 -#define CLK_UART1 37 -#define CLK_UART2 38 -#define CLK_UART3 39 -#define CLK_UART4 40 -#define CLK_UART5 41 -#define CLK_UART6 42 - -#define CLK_PWM0 43 -#define CLK_PWM1 44 -#define CLK_PWM2 45 -#define CLK_PWM3 46 -#define CLK_PWM4 47 -#define CLK_PWM5 48 -#define CLK_GPU3D 49 - -#define CLK_I2C0 50 -#define CLK_I2C1 51 -#define CLK_I2C2 52 -#define CLK_I2C3 53 - -#define CLK_SPI0 54 -#define CLK_SPI1 55 -#define CLK_SPI2 56 -#define CLK_SPI3 57 - -#define CLK_USB3_480MPLL0 58 -#define CLK_USB3_480MPHY0 59 -#define CLK_USB3_5GPHY 60 -#define CLK_USB3_CCE 61 -#define CLK_USB3_MAC 62 - -#define CLK_LCD 63 -#define CLK_HDMI_AUDIO 64 -#define CLK_I2SRX 65 -#define CLK_I2STX 66 - -#define CLK_SENSOR0 67 -#define CLK_SENSOR1 68 - -#define CLK_HDMI_DEV 69 - -#define CLK_ETHERNET 70 -#define CLK_RMII_REF 71 - -#define CLK_USB2H0_PLLEN 72 -#define CLK_USB2H0_PHY 73 -#define CLK_USB2H0_CCE 74 -#define CLK_USB2H1_PLLEN 75 -#define CLK_USB2H1_PHY 76 -#define CLK_USB2H1_CCE 77 - -#define CLK_TVOUT 78 - -#define CLK_THERMAL_SENSOR 79 - -#define CLK_IRC_SWITCH 80 -#define CLK_PCM1 81 -#define CLK_NR_CLKS (CLK_PCM1 + 1) - -#endif /* __DT_BINDINGS_CLOCK_S700_H */ diff --git a/include/dt-bindings/clock/actions,s900-cmu.h b/include/dt-bindings/clock/actions,s900-cmu.h deleted file mode 100644 index 7c1251565f4..00000000000 --- a/include/dt-bindings/clock/actions,s900-cmu.h +++ /dev/null @@ -1,129 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -// -// Device Tree binding constants for Actions Semi S900 Clock Management Unit -// -// Copyright (c) 2014 Actions Semi Inc. -// Copyright (c) 2018 Linaro Ltd. - -#ifndef __DT_BINDINGS_CLOCK_S900_CMU_H -#define __DT_BINDINGS_CLOCK_S900_CMU_H - -#define CLK_NONE 0 - -/* fixed rate clocks */ -#define CLK_LOSC 1 -#define CLK_HOSC 2 - -/* pll clocks */ -#define CLK_CORE_PLL 3 -#define CLK_DEV_PLL 4 -#define CLK_DDR_PLL 5 -#define CLK_NAND_PLL 6 -#define CLK_DISPLAY_PLL 7 -#define CLK_DSI_PLL 8 -#define CLK_ASSIST_PLL 9 -#define CLK_AUDIO_PLL 10 - -/* system clock */ -#define CLK_CPU 15 -#define CLK_DEV 16 -#define CLK_NOC 17 -#define CLK_NOC_MUX 18 -#define CLK_NOC_DIV 19 -#define CLK_AHB 20 -#define CLK_APB 21 -#define CLK_DMAC 22 - -/* peripheral device clock */ -#define CLK_GPIO 23 - -#define CLK_BISP 24 -#define CLK_CSI0 25 -#define CLK_CSI1 26 - -#define CLK_DE0 27 -#define CLK_DE1 28 -#define CLK_DE2 29 -#define CLK_DE3 30 -#define CLK_DSI 32 - -#define CLK_GPU 33 -#define CLK_GPU_CORE 34 -#define CLK_GPU_MEM 35 -#define CLK_GPU_SYS 36 - -#define CLK_HDE 37 -#define CLK_I2C0 38 -#define CLK_I2C1 39 -#define CLK_I2C2 40 -#define CLK_I2C3 41 -#define CLK_I2C4 42 -#define CLK_I2C5 43 -#define CLK_I2SRX 44 -#define CLK_I2STX 45 -#define CLK_IMX 46 -#define CLK_LCD 47 -#define CLK_NAND0 48 -#define CLK_NAND1 49 -#define CLK_PWM0 50 -#define CLK_PWM1 51 -#define CLK_PWM2 52 -#define CLK_PWM3 53 -#define CLK_PWM4 54 -#define CLK_PWM5 55 -#define CLK_SD0 56 -#define CLK_SD1 57 -#define CLK_SD2 58 -#define CLK_SD3 59 -#define CLK_SENSOR 60 -#define CLK_SPEED_SENSOR 61 -#define CLK_SPI0 62 -#define CLK_SPI1 63 -#define CLK_SPI2 64 -#define CLK_SPI3 65 -#define CLK_THERMAL_SENSOR 66 -#define CLK_UART0 67 -#define CLK_UART1 68 -#define CLK_UART2 69 -#define CLK_UART3 70 -#define CLK_UART4 71 -#define CLK_UART5 72 -#define CLK_UART6 73 -#define CLK_VCE 74 -#define CLK_VDE 75 - -#define CLK_USB3_480MPLL0 76 -#define CLK_USB3_480MPHY0 77 -#define CLK_USB3_5GPHY 78 -#define CLK_USB3_CCE 79 -#define CLK_USB3_MAC 80 - -#define CLK_TIMER 83 - -#define CLK_HDMI_AUDIO 84 - -#define CLK_24M 85 - -#define CLK_EDP 86 - -#define CLK_24M_EDP 87 -#define CLK_EDP_PLL 88 -#define CLK_EDP_LINK 89 - -#define CLK_USB2H0_PLLEN 90 -#define CLK_USB2H0_PHY 91 -#define CLK_USB2H0_CCE 92 -#define CLK_USB2H1_PLLEN 93 -#define CLK_USB2H1_PHY 94 -#define CLK_USB2H1_CCE 95 - -#define CLK_DDR0 96 -#define CLK_DDR1 97 -#define CLK_DMM 98 - -#define CLK_ETH_MAC 99 -#define CLK_RMII_REF 100 - -#define CLK_NR_CLKS (CLK_RMII_REF + 1) - -#endif /* __DT_BINDINGS_CLOCK_S900_CMU_H */ diff --git a/include/dt-bindings/clock/bcm-nsp.h b/include/dt-bindings/clock/bcm-nsp.h deleted file mode 100644 index ad5827cde78..00000000000 --- a/include/dt-bindings/clock/bcm-nsp.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * BSD LICENSE - * - * Copyright(c) 2015 Broadcom Corporation. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Broadcom Corporation nor the names of its - * contributors may be used to endorse or promote products derived - * from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef _CLOCK_BCM_NSP_H -#define _CLOCK_BCM_NSP_H - -/* GENPLL clock channel ID */ -#define BCM_NSP_GENPLL 0 -#define BCM_NSP_GENPLL_PHY_CLK 1 -#define BCM_NSP_GENPLL_ENET_SW_CLK 2 -#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3 -#define BCM_NSP_GENPLL_IPROCFAST_CLK 4 -#define BCM_NSP_GENPLL_SATA1_CLK 5 -#define BCM_NSP_GENPLL_SATA2_CLK 6 - -/* LCPLL0 clock channel ID */ -#define BCM_NSP_LCPLL0 0 -#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1 -#define BCM_NSP_LCPLL0_SDIO_CLK 2 -#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3 - -#endif /* _CLOCK_BCM_NSP_H */ diff --git a/include/dt-bindings/clock/bcm2835-aux.h b/include/dt-bindings/clock/bcm2835-aux.h deleted file mode 100644 index bb79de383a3..00000000000 --- a/include/dt-bindings/clock/bcm2835-aux.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2015 Broadcom Corporation - */ - -#define BCM2835_AUX_CLOCK_UART 0 -#define BCM2835_AUX_CLOCK_SPI1 1 -#define BCM2835_AUX_CLOCK_SPI2 2 -#define BCM2835_AUX_CLOCK_COUNT 3 diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h deleted file mode 100644 index b60c03430cf..00000000000 --- a/include/dt-bindings/clock/bcm2835.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2015 Broadcom Corporation - */ - -#define BCM2835_PLLA 0 -#define BCM2835_PLLB 1 -#define BCM2835_PLLC 2 -#define BCM2835_PLLD 3 -#define BCM2835_PLLH 4 - -#define BCM2835_PLLA_CORE 5 -#define BCM2835_PLLA_PER 6 -#define BCM2835_PLLB_ARM 7 -#define BCM2835_PLLC_CORE0 8 -#define BCM2835_PLLC_CORE1 9 -#define BCM2835_PLLC_CORE2 10 -#define BCM2835_PLLC_PER 11 -#define BCM2835_PLLD_CORE 12 -#define BCM2835_PLLD_PER 13 -#define BCM2835_PLLH_RCAL 14 -#define BCM2835_PLLH_AUX 15 -#define BCM2835_PLLH_PIX 16 - -#define BCM2835_CLOCK_TIMER 17 -#define BCM2835_CLOCK_OTP 18 -#define BCM2835_CLOCK_UART 19 -#define BCM2835_CLOCK_VPU 20 -#define BCM2835_CLOCK_V3D 21 -#define BCM2835_CLOCK_ISP 22 -#define BCM2835_CLOCK_H264 23 -#define BCM2835_CLOCK_VEC 24 -#define BCM2835_CLOCK_HSM 25 -#define BCM2835_CLOCK_SDRAM 26 -#define BCM2835_CLOCK_TSENS 27 -#define BCM2835_CLOCK_EMMC 28 -#define BCM2835_CLOCK_PERI_IMAGE 29 -#define BCM2835_CLOCK_PWM 30 -#define BCM2835_CLOCK_PCM 31 - -#define BCM2835_PLLA_DSI0 32 -#define BCM2835_PLLA_CCP2 33 -#define BCM2835_PLLD_DSI0 34 -#define BCM2835_PLLD_DSI1 35 - -#define BCM2835_CLOCK_AVEO 36 -#define BCM2835_CLOCK_DFT 37 -#define BCM2835_CLOCK_GP0 38 -#define BCM2835_CLOCK_GP1 39 -#define BCM2835_CLOCK_GP2 40 -#define BCM2835_CLOCK_SLIM 41 -#define BCM2835_CLOCK_SMI 42 -#define BCM2835_CLOCK_TEC 43 -#define BCM2835_CLOCK_DPI 44 -#define BCM2835_CLOCK_CAM0 45 -#define BCM2835_CLOCK_CAM1 46 -#define BCM2835_CLOCK_DSI0E 47 -#define BCM2835_CLOCK_DSI1E 48 -#define BCM2835_CLOCK_DSI0P 49 -#define BCM2835_CLOCK_DSI1P 50 - -#define BCM2711_CLOCK_EMMC2 51 diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h b/include/dt-bindings/clock/fsl,qoriq-clockgen.h deleted file mode 100644 index ddec7d0bdc7..00000000000 --- a/include/dt-bindings/clock/fsl,qoriq-clockgen.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H -#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H - -#define QORIQ_CLK_SYSCLK 0 -#define QORIQ_CLK_CMUX 1 -#define QORIQ_CLK_HWACCEL 2 -#define QORIQ_CLK_FMAN 3 -#define QORIQ_CLK_PLATFORM_PLL 4 -#define QORIQ_CLK_CORECLK 5 - -#define QORIQ_CLK_PLL_DIV(x) ((x) - 1) - -#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */ diff --git a/include/dt-bindings/clock/hi3660-clock.h b/include/dt-bindings/clock/hi3660-clock.h deleted file mode 100644 index e1374e18094..00000000000 --- a/include/dt-bindings/clock/hi3660-clock.h +++ /dev/null @@ -1,214 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2016-2017 Linaro Ltd. - * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. - */ - -#ifndef __DTS_HI3660_CLOCK_H -#define __DTS_HI3660_CLOCK_H - -/* fixed rate clocks */ -#define HI3660_CLKIN_SYS 0 -#define HI3660_CLKIN_REF 1 -#define HI3660_CLK_FLL_SRC 2 -#define HI3660_CLK_PPLL0 3 -#define HI3660_CLK_PPLL1 4 -#define HI3660_CLK_PPLL2 5 -#define HI3660_CLK_PPLL3 6 -#define HI3660_CLK_SCPLL 7 -#define HI3660_PCLK 8 -#define HI3660_CLK_UART0_DBG 9 -#define HI3660_CLK_UART6 10 -#define HI3660_OSC32K 11 -#define HI3660_OSC19M 12 -#define HI3660_CLK_480M 13 -#define HI3660_CLK_INV 14 - -/* clk in crgctrl */ -#define HI3660_FACTOR_UART3 15 -#define HI3660_CLK_FACTOR_MMC 16 -#define HI3660_CLK_GATE_I2C0 17 -#define HI3660_CLK_GATE_I2C1 18 -#define HI3660_CLK_GATE_I2C2 19 -#define HI3660_CLK_GATE_I2C6 20 -#define HI3660_CLK_DIV_SYSBUS 21 -#define HI3660_CLK_DIV_320M 22 -#define HI3660_CLK_DIV_A53 23 -#define HI3660_CLK_GATE_SPI0 24 -#define HI3660_CLK_GATE_SPI2 25 -#define HI3660_PCIEPHY_REF 26 -#define HI3660_CLK_ABB_USB 27 -#define HI3660_HCLK_GATE_SDIO0 28 -#define HI3660_HCLK_GATE_SD 29 -#define HI3660_CLK_GATE_AOMM 30 -#define HI3660_PCLK_GPIO0 31 -#define HI3660_PCLK_GPIO1 32 -#define HI3660_PCLK_GPIO2 33 -#define HI3660_PCLK_GPIO3 34 -#define HI3660_PCLK_GPIO4 35 -#define HI3660_PCLK_GPIO5 36 -#define HI3660_PCLK_GPIO6 37 -#define HI3660_PCLK_GPIO7 38 -#define HI3660_PCLK_GPIO8 39 -#define HI3660_PCLK_GPIO9 40 -#define HI3660_PCLK_GPIO10 41 -#define HI3660_PCLK_GPIO11 42 -#define HI3660_PCLK_GPIO12 43 -#define HI3660_PCLK_GPIO13 44 -#define HI3660_PCLK_GPIO14 45 -#define HI3660_PCLK_GPIO15 46 -#define HI3660_PCLK_GPIO16 47 -#define HI3660_PCLK_GPIO17 48 -#define HI3660_PCLK_GPIO18 49 -#define HI3660_PCLK_GPIO19 50 -#define HI3660_PCLK_GPIO20 51 -#define HI3660_PCLK_GPIO21 52 -#define HI3660_CLK_GATE_SPI3 53 -#define HI3660_CLK_GATE_I2C7 54 -#define HI3660_CLK_GATE_I2C3 55 -#define HI3660_CLK_GATE_SPI1 56 -#define HI3660_CLK_GATE_UART1 57 -#define HI3660_CLK_GATE_UART2 58 -#define HI3660_CLK_GATE_UART4 59 -#define HI3660_CLK_GATE_UART5 60 -#define HI3660_CLK_GATE_I2C4 61 -#define HI3660_CLK_GATE_DMAC 62 -#define HI3660_PCLK_GATE_DSS 63 -#define HI3660_ACLK_GATE_DSS 64 -#define HI3660_CLK_GATE_LDI1 65 -#define HI3660_CLK_GATE_LDI0 66 -#define HI3660_CLK_GATE_VIVOBUS 67 -#define HI3660_CLK_GATE_EDC0 68 -#define HI3660_CLK_GATE_TXDPHY0_CFG 69 -#define HI3660_CLK_GATE_TXDPHY0_REF 70 -#define HI3660_CLK_GATE_TXDPHY1_CFG 71 -#define HI3660_CLK_GATE_TXDPHY1_REF 72 -#define HI3660_ACLK_GATE_USB3OTG 73 -#define HI3660_CLK_GATE_SPI4 74 -#define HI3660_CLK_GATE_SD 75 -#define HI3660_CLK_GATE_SDIO0 76 -#define HI3660_CLK_GATE_UFS_SUBSYS 77 -#define HI3660_PCLK_GATE_DSI0 78 -#define HI3660_PCLK_GATE_DSI1 79 -#define HI3660_ACLK_GATE_PCIE 80 -#define HI3660_PCLK_GATE_PCIE_SYS 81 -#define HI3660_CLK_GATE_PCIEAUX 82 -#define HI3660_PCLK_GATE_PCIE_PHY 83 -#define HI3660_CLK_ANDGT_LDI0 84 -#define HI3660_CLK_ANDGT_LDI1 85 -#define HI3660_CLK_ANDGT_EDC0 86 -#define HI3660_CLK_GATE_UFSPHY_GT 87 -#define HI3660_CLK_ANDGT_MMC 88 -#define HI3660_CLK_ANDGT_SD 89 -#define HI3660_CLK_A53HPM_ANDGT 90 -#define HI3660_CLK_ANDGT_SDIO 91 -#define HI3660_CLK_ANDGT_UART0 92 -#define HI3660_CLK_ANDGT_UART1 93 -#define HI3660_CLK_ANDGT_UARTH 94 -#define HI3660_CLK_ANDGT_SPI 95 -#define HI3660_CLK_VIVOBUS_ANDGT 96 -#define HI3660_CLK_AOMM_ANDGT 97 -#define HI3660_CLK_320M_PLL_GT 98 -#define HI3660_AUTODIV_EMMC0BUS 99 -#define HI3660_AUTODIV_SYSBUS 100 -#define HI3660_CLK_GATE_UFSPHY_CFG 101 -#define HI3660_CLK_GATE_UFSIO_REF 102 -#define HI3660_CLK_MUX_SYSBUS 103 -#define HI3660_CLK_MUX_UART0 104 -#define HI3660_CLK_MUX_UART1 105 -#define HI3660_CLK_MUX_UARTH 106 -#define HI3660_CLK_MUX_SPI 107 -#define HI3660_CLK_MUX_I2C 108 -#define HI3660_CLK_MUX_MMC_PLL 109 -#define HI3660_CLK_MUX_LDI1 110 -#define HI3660_CLK_MUX_LDI0 111 -#define HI3660_CLK_MUX_SD_PLL 112 -#define HI3660_CLK_MUX_SD_SYS 113 -#define HI3660_CLK_MUX_EDC0 114 -#define HI3660_CLK_MUX_SDIO_SYS 115 -#define HI3660_CLK_MUX_SDIO_PLL 116 -#define HI3660_CLK_MUX_VIVOBUS 117 -#define HI3660_CLK_MUX_A53HPM 118 -#define HI3660_CLK_MUX_320M 119 -#define HI3660_CLK_MUX_IOPERI 120 -#define HI3660_CLK_DIV_UART0 121 -#define HI3660_CLK_DIV_UART1 122 -#define HI3660_CLK_DIV_UARTH 123 -#define HI3660_CLK_DIV_MMC 124 -#define HI3660_CLK_DIV_SD 125 -#define HI3660_CLK_DIV_EDC0 126 -#define HI3660_CLK_DIV_LDI0 127 -#define HI3660_CLK_DIV_SDIO 128 -#define HI3660_CLK_DIV_LDI1 129 -#define HI3660_CLK_DIV_SPI 130 -#define HI3660_CLK_DIV_VIVOBUS 131 -#define HI3660_CLK_DIV_I2C 132 -#define HI3660_CLK_DIV_UFSPHY 133 -#define HI3660_CLK_DIV_CFGBUS 134 -#define HI3660_CLK_DIV_MMC0BUS 135 -#define HI3660_CLK_DIV_MMC1BUS 136 -#define HI3660_CLK_DIV_UFSPERI 137 -#define HI3660_CLK_DIV_AOMM 138 -#define HI3660_CLK_DIV_IOPERI 139 -#define HI3660_VENC_VOLT_HOLD 140 -#define HI3660_PERI_VOLT_HOLD 141 -#define HI3660_CLK_GATE_VENC 142 -#define HI3660_CLK_GATE_VDEC 143 -#define HI3660_CLK_ANDGT_VENC 144 -#define HI3660_CLK_ANDGT_VDEC 145 -#define HI3660_CLK_MUX_VENC 146 -#define HI3660_CLK_MUX_VDEC 147 -#define HI3660_CLK_DIV_VENC 148 -#define HI3660_CLK_DIV_VDEC 149 -#define HI3660_CLK_FAC_ISP_SNCLK 150 -#define HI3660_CLK_GATE_ISP_SNCLK0 151 -#define HI3660_CLK_GATE_ISP_SNCLK1 152 -#define HI3660_CLK_GATE_ISP_SNCLK2 153 -#define HI3660_CLK_ANGT_ISP_SNCLK 154 -#define HI3660_CLK_MUX_ISP_SNCLK 155 -#define HI3660_CLK_DIV_ISP_SNCLK 156 - -/* clk in pmuctrl */ -#define HI3660_GATE_ABB_192 0 - -/* clk in pctrl */ -#define HI3660_GATE_UFS_TCXO_EN 0 -#define HI3660_GATE_USB_TCXO_EN 1 - -/* clk in sctrl */ -#define HI3660_PCLK_AO_GPIO0 0 -#define HI3660_PCLK_AO_GPIO1 1 -#define HI3660_PCLK_AO_GPIO2 2 -#define HI3660_PCLK_AO_GPIO3 3 -#define HI3660_PCLK_AO_GPIO4 4 -#define HI3660_PCLK_AO_GPIO5 5 -#define HI3660_PCLK_AO_GPIO6 6 -#define HI3660_PCLK_GATE_MMBUF 7 -#define HI3660_CLK_GATE_DSS_AXI_MM 8 -#define HI3660_PCLK_MMBUF_ANDGT 9 -#define HI3660_CLK_MMBUF_PLL_ANDGT 10 -#define HI3660_CLK_FLL_MMBUF_ANDGT 11 -#define HI3660_CLK_SYS_MMBUF_ANDGT 12 -#define HI3660_CLK_GATE_PCIEPHY_GT 13 -#define HI3660_ACLK_MUX_MMBUF 14 -#define HI3660_CLK_SW_MMBUF 15 -#define HI3660_CLK_DIV_AOBUS 16 -#define HI3660_PCLK_DIV_MMBUF 17 -#define HI3660_ACLK_DIV_MMBUF 18 -#define HI3660_CLK_DIV_PCIEPHY 19 - -/* clk in iomcu */ -#define HI3660_CLK_I2C0_IOMCU 0 -#define HI3660_CLK_I2C1_IOMCU 1 -#define HI3660_CLK_I2C2_IOMCU 2 -#define HI3660_CLK_I2C6_IOMCU 3 -#define HI3660_CLK_IOMCU_PERI0 4 - -/* clk in stub clock */ -#define HI3660_CLK_STUB_CLUSTER0 0 -#define HI3660_CLK_STUB_CLUSTER1 1 -#define HI3660_CLK_STUB_GPU 2 -#define HI3660_CLK_STUB_DDR 3 -#define HI3660_CLK_STUB_NUM 4 - -#endif /* __DTS_HI3660_CLOCK_H */ diff --git a/include/dt-bindings/clock/lpc32xx-clock.h b/include/dt-bindings/clock/lpc32xx-clock.h deleted file mode 100644 index e624d3a5279..00000000000 --- a/include/dt-bindings/clock/lpc32xx-clock.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2015 Vladimir Zapolskiy - * - * This code is released using a dual license strategy: BSD/GPL - * You can choose the licence that better fits your requirements. - * - * Released under the terms of 3-clause BSD License - * Released under the terms of GNU General Public License Version 2.0 - * - */ - -#ifndef __DT_BINDINGS_LPC32XX_CLOCK_H -#define __DT_BINDINGS_LPC32XX_CLOCK_H - -/* LPC32XX System Control Block clocks */ -#define LPC32XX_CLK_RTC 1 -#define LPC32XX_CLK_DMA 2 -#define LPC32XX_CLK_MLC 3 -#define LPC32XX_CLK_SLC 4 -#define LPC32XX_CLK_LCD 5 -#define LPC32XX_CLK_MAC 6 -#define LPC32XX_CLK_SD 7 -#define LPC32XX_CLK_DDRAM 8 -#define LPC32XX_CLK_SSP0 9 -#define LPC32XX_CLK_SSP1 10 -#define LPC32XX_CLK_UART3 11 -#define LPC32XX_CLK_UART4 12 -#define LPC32XX_CLK_UART5 13 -#define LPC32XX_CLK_UART6 14 -#define LPC32XX_CLK_IRDA 15 -#define LPC32XX_CLK_I2C1 16 -#define LPC32XX_CLK_I2C2 17 -#define LPC32XX_CLK_TIMER0 18 -#define LPC32XX_CLK_TIMER1 19 -#define LPC32XX_CLK_TIMER2 20 -#define LPC32XX_CLK_TIMER3 21 -#define LPC32XX_CLK_TIMER4 22 -#define LPC32XX_CLK_TIMER5 23 -#define LPC32XX_CLK_WDOG 24 -#define LPC32XX_CLK_I2S0 25 -#define LPC32XX_CLK_I2S1 26 -#define LPC32XX_CLK_SPI1 27 -#define LPC32XX_CLK_SPI2 28 -#define LPC32XX_CLK_MCPWM 29 -#define LPC32XX_CLK_HSTIMER 30 -#define LPC32XX_CLK_KEY 31 -#define LPC32XX_CLK_PWM1 32 -#define LPC32XX_CLK_PWM2 33 -#define LPC32XX_CLK_ADC 34 -#define LPC32XX_CLK_HCLK_PLL 35 -#define LPC32XX_CLK_PERIPH 36 - -/* LPC32XX USB clocks */ -#define LPC32XX_USB_CLK_I2C 1 -#define LPC32XX_USB_CLK_DEVICE 2 -#define LPC32XX_USB_CLK_HOST 3 - -#endif /* __DT_BINDINGS_LPC32XX_CLOCK_H */ diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h deleted file mode 100644 index a267ac25014..00000000000 --- a/include/dt-bindings/clock/r7s72100-clock.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2014 Renesas Solutions Corp. - * Copyright (C) 2014 Wolfram Sang, Sang Engineering - */ - -#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__ -#define __DT_BINDINGS_CLOCK_R7S72100_H__ - -#define R7S72100_CLK_PLL 0 -#define R7S72100_CLK_I 1 -#define R7S72100_CLK_G 2 - -/* MSTP2 */ -#define R7S72100_CLK_CORESIGHT 0 - -/* MSTP3 */ -#define R7S72100_CLK_IEBUS 7 -#define R7S72100_CLK_IRDA 6 -#define R7S72100_CLK_LIN0 5 -#define R7S72100_CLK_LIN1 4 -#define R7S72100_CLK_MTU2 3 -#define R7S72100_CLK_CAN 2 -#define R7S72100_CLK_ADCPWR 1 -#define R7S72100_CLK_PWM 0 - -/* MSTP4 */ -#define R7S72100_CLK_SCIF0 7 -#define R7S72100_CLK_SCIF1 6 -#define R7S72100_CLK_SCIF2 5 -#define R7S72100_CLK_SCIF3 4 -#define R7S72100_CLK_SCIF4 3 -#define R7S72100_CLK_SCIF5 2 -#define R7S72100_CLK_SCIF6 1 -#define R7S72100_CLK_SCIF7 0 - -/* MSTP5 */ -#define R7S72100_CLK_SCI0 7 -#define R7S72100_CLK_SCI1 6 -#define R7S72100_CLK_SG0 5 -#define R7S72100_CLK_SG1 4 -#define R7S72100_CLK_SG2 3 -#define R7S72100_CLK_SG3 2 -#define R7S72100_CLK_OSTM0 1 -#define R7S72100_CLK_OSTM1 0 - -/* MSTP6 */ -#define R7S72100_CLK_ADC 7 -#define R7S72100_CLK_CEU 6 -#define R7S72100_CLK_DOC0 5 -#define R7S72100_CLK_DOC1 4 -#define R7S72100_CLK_DRC0 3 -#define R7S72100_CLK_DRC1 2 -#define R7S72100_CLK_JCU 1 -#define R7S72100_CLK_RTC 0 - -/* MSTP7 */ -#define R7S72100_CLK_VDEC0 7 -#define R7S72100_CLK_VDEC1 6 -#define R7S72100_CLK_ETHER 4 -#define R7S72100_CLK_NAND 3 -#define R7S72100_CLK_USB0 1 -#define R7S72100_CLK_USB1 0 - -/* MSTP8 */ -#define R7S72100_CLK_IMR0 7 -#define R7S72100_CLK_IMR1 6 -#define R7S72100_CLK_IMRDISP 5 -#define R7S72100_CLK_MMCIF 4 -#define R7S72100_CLK_MLB 3 -#define R7S72100_CLK_ETHAVB 2 -#define R7S72100_CLK_SCUX 1 - -/* MSTP9 */ -#define R7S72100_CLK_I2C0 7 -#define R7S72100_CLK_I2C1 6 -#define R7S72100_CLK_I2C2 5 -#define R7S72100_CLK_I2C3 4 -#define R7S72100_CLK_SPIBSC0 3 -#define R7S72100_CLK_SPIBSC1 2 -#define R7S72100_CLK_VDC50 1 /* and LVDS */ -#define R7S72100_CLK_VDC51 0 - -/* MSTP10 */ -#define R7S72100_CLK_SPI0 7 -#define R7S72100_CLK_SPI1 6 -#define R7S72100_CLK_SPI2 5 -#define R7S72100_CLK_SPI3 4 -#define R7S72100_CLK_SPI4 3 -#define R7S72100_CLK_CDROM 2 -#define R7S72100_CLK_SPDIF 1 -#define R7S72100_CLK_RGPVG2 0 - -/* MSTP11 */ -#define R7S72100_CLK_SSI0 5 -#define R7S72100_CLK_SSI1 4 -#define R7S72100_CLK_SSI2 3 -#define R7S72100_CLK_SSI3 2 -#define R7S72100_CLK_SSI4 1 -#define R7S72100_CLK_SSI5 0 - -/* MSTP12 */ -#define R7S72100_CLK_SDHI00 3 -#define R7S72100_CLK_SDHI01 2 -#define R7S72100_CLK_SDHI10 1 -#define R7S72100_CLK_SDHI11 0 - -/* MSTP13 */ -#define R7S72100_CLK_PIX1 2 -#define R7S72100_CLK_PIX0 1 - -#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */ diff --git a/include/dt-bindings/clock/r9a06g032-sysctrl.h b/include/dt-bindings/clock/r9a06g032-sysctrl.h deleted file mode 100644 index d9d7b8b4f42..00000000000 --- a/include/dt-bindings/clock/r9a06g032-sysctrl.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * R9A06G032 sysctrl IDs - * - * Copyright (C) 2018 Renesas Electronics Europe Limited - * - * Michel Pollet , - */ - -#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__ -#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__ - -#define R9A06G032_CLK_PLL_USB 1 -#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */ -#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */ -#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */ -#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */ -#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */ -#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */ -#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */ -#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */ -#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */ -#define R9A06G032_CLK_25_PG4 26 -#define R9A06G032_CLK_25_PG5 27 -#define R9A06G032_CLK_25_PG6 28 -#define R9A06G032_CLK_25_PG7 29 -#define R9A06G032_CLK_25_PG8 30 -#define R9A06G032_CLK_ADC 31 -#define R9A06G032_CLK_ECAT100 32 -#define R9A06G032_CLK_HSR100 33 -#define R9A06G032_CLK_I2C0 34 -#define R9A06G032_CLK_I2C1 35 -#define R9A06G032_CLK_MII_REF 36 -#define R9A06G032_CLK_NAND 37 -#define R9A06G032_CLK_NOUSBP2_PG6 38 -#define R9A06G032_CLK_P1_PG2 39 -#define R9A06G032_CLK_P1_PG3 40 -#define R9A06G032_CLK_P1_PG4 41 -#define R9A06G032_CLK_P4_PG3 42 -#define R9A06G032_CLK_P4_PG4 43 -#define R9A06G032_CLK_P6_PG1 44 -#define R9A06G032_CLK_P6_PG2 45 -#define R9A06G032_CLK_P6_PG3 46 -#define R9A06G032_CLK_P6_PG4 47 -#define R9A06G032_CLK_PCI_USB 48 -#define R9A06G032_CLK_QSPI0 49 -#define R9A06G032_CLK_QSPI1 50 -#define R9A06G032_CLK_RGMII_REF 51 -#define R9A06G032_CLK_RMII_REF 52 -#define R9A06G032_CLK_SDIO0 53 -#define R9A06G032_CLK_SDIO1 54 -#define R9A06G032_CLK_SERCOS100 55 -#define R9A06G032_CLK_SLCD 56 -#define R9A06G032_CLK_SPI0 57 -#define R9A06G032_CLK_SPI1 58 -#define R9A06G032_CLK_SPI2 59 -#define R9A06G032_CLK_SPI3 60 -#define R9A06G032_CLK_SPI4 61 -#define R9A06G032_CLK_SPI5 62 -#define R9A06G032_CLK_SWITCH 63 -#define R9A06G032_HCLK_ECAT125 65 -#define R9A06G032_HCLK_PINCONFIG 66 -#define R9A06G032_HCLK_SERCOS 67 -#define R9A06G032_HCLK_SGPIO2 68 -#define R9A06G032_HCLK_SGPIO3 69 -#define R9A06G032_HCLK_SGPIO4 70 -#define R9A06G032_HCLK_TIMER0 71 -#define R9A06G032_HCLK_TIMER1 72 -#define R9A06G032_HCLK_USBF 73 -#define R9A06G032_HCLK_USBH 74 -#define R9A06G032_HCLK_USBPM 75 -#define R9A06G032_CLK_48_PG_F 76 -#define R9A06G032_CLK_48_PG4 77 -#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */ -#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */ -#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */ -#define R9A06G032_CLK_WATCHDOG 82 /* AKA CLK_REF_SYNC_D8 */ -#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */ -#define R9A06G032_HCLK_CAN0 85 -#define R9A06G032_HCLK_CAN1 86 -#define R9A06G032_HCLK_DELTASIGMA 87 -#define R9A06G032_HCLK_PWMPTO 88 -#define R9A06G032_HCLK_RSV 89 -#define R9A06G032_HCLK_SGPIO0 90 -#define R9A06G032_HCLK_SGPIO1 91 -#define R9A06G032_RTOS_MDC 92 -#define R9A06G032_CLK_CM3 93 -#define R9A06G032_CLK_DDRC 94 -#define R9A06G032_CLK_ECAT25 95 -#define R9A06G032_CLK_HSR50 96 -#define R9A06G032_CLK_HW_RTOS 97 -#define R9A06G032_CLK_SERCOS50 98 -#define R9A06G032_HCLK_ADC 99 -#define R9A06G032_HCLK_CM3 100 -#define R9A06G032_HCLK_CRYPTO_EIP150 101 -#define R9A06G032_HCLK_CRYPTO_EIP93 102 -#define R9A06G032_HCLK_DDRC 103 -#define R9A06G032_HCLK_DMA0 104 -#define R9A06G032_HCLK_DMA1 105 -#define R9A06G032_HCLK_GMAC0 106 -#define R9A06G032_HCLK_GMAC1 107 -#define R9A06G032_HCLK_GPIO0 108 -#define R9A06G032_HCLK_GPIO1 109 -#define R9A06G032_HCLK_GPIO2 110 -#define R9A06G032_HCLK_HSR 111 -#define R9A06G032_HCLK_I2C0 112 -#define R9A06G032_HCLK_I2C1 113 -#define R9A06G032_HCLK_LCD 114 -#define R9A06G032_HCLK_MSEBI_M 115 -#define R9A06G032_HCLK_MSEBI_S 116 -#define R9A06G032_HCLK_NAND 117 -#define R9A06G032_HCLK_PG_I 118 -#define R9A06G032_HCLK_PG19 119 -#define R9A06G032_HCLK_PG20 120 -#define R9A06G032_HCLK_PG3 121 -#define R9A06G032_HCLK_PG4 122 -#define R9A06G032_HCLK_QSPI0 123 -#define R9A06G032_HCLK_QSPI1 124 -#define R9A06G032_HCLK_ROM 125 -#define R9A06G032_HCLK_RTC 126 -#define R9A06G032_HCLK_SDIO0 127 -#define R9A06G032_HCLK_SDIO1 128 -#define R9A06G032_HCLK_SEMAP 129 -#define R9A06G032_HCLK_SPI0 130 -#define R9A06G032_HCLK_SPI1 131 -#define R9A06G032_HCLK_SPI2 132 -#define R9A06G032_HCLK_SPI3 133 -#define R9A06G032_HCLK_SPI4 134 -#define R9A06G032_HCLK_SPI5 135 -#define R9A06G032_HCLK_SWITCH 136 -#define R9A06G032_HCLK_SWITCH_RG 137 -#define R9A06G032_HCLK_UART0 138 -#define R9A06G032_HCLK_UART1 139 -#define R9A06G032_HCLK_UART2 140 -#define R9A06G032_HCLK_UART3 141 -#define R9A06G032_HCLK_UART4 142 -#define R9A06G032_HCLK_UART5 143 -#define R9A06G032_HCLK_UART6 144 -#define R9A06G032_HCLK_UART7 145 -#define R9A06G032_CLK_UART0 146 -#define R9A06G032_CLK_UART1 147 -#define R9A06G032_CLK_UART2 148 -#define R9A06G032_CLK_UART3 149 -#define R9A06G032_CLK_UART4 150 -#define R9A06G032_CLK_UART5 151 -#define R9A06G032_CLK_UART6 152 -#define R9A06G032_CLK_UART7 153 - -#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */ diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bindings/clock/sifive-fu740-prci.h deleted file mode 100644 index 672bdadbf6c..00000000000 --- a/include/dt-bindings/clock/sifive-fu740-prci.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (C) 2019 SiFive, Inc. - * Wesley Terpstra - * Paul Walmsley - * Zong Li - */ - -#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H -#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H - -/* Clock indexes for use by Device Tree data and the PRCI driver */ - -#define FU740_PRCI_CLK_COREPLL 0 -#define FU740_PRCI_CLK_DDRPLL 1 -#define FU740_PRCI_CLK_GEMGXLPLL 2 -#define FU740_PRCI_CLK_DVFSCOREPLL 3 -#define FU740_PRCI_CLK_HFPCLKPLL 4 -#define FU740_PRCI_CLK_CLTXPLL 5 -#define FU740_PRCI_CLK_TLCLK 6 -#define FU740_PRCI_CLK_PCLK 7 -#define FU740_PRCI_CLK_PCIE_AUX 8 - -#endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */ diff --git a/include/dt-bindings/clock/sophgo,cv1800.h b/include/dt-bindings/clock/sophgo,cv1800.h deleted file mode 100644 index cfbeca25a65..00000000000 --- a/include/dt-bindings/clock/sophgo,cv1800.h +++ /dev/null @@ -1,176 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -/* - * Copyright (C) 2023 Sophgo Ltd. - */ - -#ifndef __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ -#define __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ - -#define CLK_MPLL 0 -#define CLK_TPLL 1 -#define CLK_FPLL 2 -#define CLK_MIPIMPLL 3 -#define CLK_A0PLL 4 -#define CLK_DISPPLL 5 -#define CLK_CAM0PLL 6 -#define CLK_CAM1PLL 7 - -#define CLK_MIPIMPLL_D3 8 -#define CLK_CAM0PLL_D2 9 -#define CLK_CAM0PLL_D3 10 - -#define CLK_TPU 11 -#define CLK_TPU_FAB 12 -#define CLK_AHB_ROM 13 -#define CLK_DDR_AXI_REG 14 -#define CLK_RTC_25M 15 -#define CLK_SRC_RTC_SYS_0 16 -#define CLK_TEMPSEN 17 -#define CLK_SARADC 18 -#define CLK_EFUSE 19 -#define CLK_APB_EFUSE 20 -#define CLK_DEBUG 21 -#define CLK_AP_DEBUG 22 -#define CLK_XTAL_MISC 23 -#define CLK_AXI4_EMMC 24 -#define CLK_EMMC 25 -#define CLK_EMMC_100K 26 -#define CLK_AXI4_SD0 27 -#define CLK_SD0 28 -#define CLK_SD0_100K 29 -#define CLK_AXI4_SD1 30 -#define CLK_SD1 31 -#define CLK_SD1_100K 32 -#define CLK_SPI_NAND 33 -#define CLK_ETH0_500M 34 -#define CLK_AXI4_ETH0 35 -#define CLK_ETH1_500M 36 -#define CLK_AXI4_ETH1 37 -#define CLK_APB_GPIO 38 -#define CLK_APB_GPIO_INTR 39 -#define CLK_GPIO_DB 40 -#define CLK_AHB_SF 41 -#define CLK_AHB_SF1 42 -#define CLK_A24M 43 -#define CLK_AUDSRC 44 -#define CLK_APB_AUDSRC 45 -#define CLK_SDMA_AXI 46 -#define CLK_SDMA_AUD0 47 -#define CLK_SDMA_AUD1 48 -#define CLK_SDMA_AUD2 49 -#define CLK_SDMA_AUD3 50 -#define CLK_I2C 51 -#define CLK_APB_I2C 52 -#define CLK_APB_I2C0 53 -#define CLK_APB_I2C1 54 -#define CLK_APB_I2C2 55 -#define CLK_APB_I2C3 56 -#define CLK_APB_I2C4 57 -#define CLK_APB_WDT 58 -#define CLK_PWM_SRC 59 -#define CLK_PWM 60 -#define CLK_SPI 61 -#define CLK_APB_SPI0 62 -#define CLK_APB_SPI1 63 -#define CLK_APB_SPI2 64 -#define CLK_APB_SPI3 65 -#define CLK_1M 66 -#define CLK_CAM0_200 67 -#define CLK_PM 68 -#define CLK_TIMER0 69 -#define CLK_TIMER1 70 -#define CLK_TIMER2 71 -#define CLK_TIMER3 72 -#define CLK_TIMER4 73 -#define CLK_TIMER5 74 -#define CLK_TIMER6 75 -#define CLK_TIMER7 76 -#define CLK_UART0 77 -#define CLK_APB_UART0 78 -#define CLK_UART1 79 -#define CLK_APB_UART1 80 -#define CLK_UART2 81 -#define CLK_APB_UART2 82 -#define CLK_UART3 83 -#define CLK_APB_UART3 84 -#define CLK_UART4 85 -#define CLK_APB_UART4 86 -#define CLK_APB_I2S0 87 -#define CLK_APB_I2S1 88 -#define CLK_APB_I2S2 89 -#define CLK_APB_I2S3 90 -#define CLK_AXI4_USB 91 -#define CLK_APB_USB 92 -#define CLK_USB_125M 93 -#define CLK_USB_33K 94 -#define CLK_USB_12M 95 -#define CLK_AXI4 96 -#define CLK_AXI6 97 -#define CLK_DSI_ESC 98 -#define CLK_AXI_VIP 99 -#define CLK_SRC_VIP_SYS_0 100 -#define CLK_SRC_VIP_SYS_1 101 -#define CLK_SRC_VIP_SYS_2 102 -#define CLK_SRC_VIP_SYS_3 103 -#define CLK_SRC_VIP_SYS_4 104 -#define CLK_CSI_BE_VIP 105 -#define CLK_CSI_MAC0_VIP 106 -#define CLK_CSI_MAC1_VIP 107 -#define CLK_CSI_MAC2_VIP 108 -#define CLK_CSI0_RX_VIP 109 -#define CLK_CSI1_RX_VIP 110 -#define CLK_ISP_TOP_VIP 111 -#define CLK_IMG_D_VIP 112 -#define CLK_IMG_V_VIP 113 -#define CLK_SC_TOP_VIP 114 -#define CLK_SC_D_VIP 115 -#define CLK_SC_V1_VIP 116 -#define CLK_SC_V2_VIP 117 -#define CLK_SC_V3_VIP 118 -#define CLK_DWA_VIP 119 -#define CLK_BT_VIP 120 -#define CLK_DISP_VIP 121 -#define CLK_DSI_MAC_VIP 122 -#define CLK_LVDS0_VIP 123 -#define CLK_LVDS1_VIP 124 -#define CLK_PAD_VI_VIP 125 -#define CLK_PAD_VI1_VIP 126 -#define CLK_PAD_VI2_VIP 127 -#define CLK_CFG_REG_VIP 128 -#define CLK_VIP_IP0 129 -#define CLK_VIP_IP1 130 -#define CLK_VIP_IP2 131 -#define CLK_VIP_IP3 132 -#define CLK_IVE_VIP 133 -#define CLK_RAW_VIP 134 -#define CLK_OSDC_VIP 135 -#define CLK_CAM0_VIP 136 -#define CLK_AXI_VIDEO_CODEC 137 -#define CLK_VC_SRC0 138 -#define CLK_VC_SRC1 139 -#define CLK_VC_SRC2 140 -#define CLK_H264C 141 -#define CLK_APB_H264C 142 -#define CLK_H265C 143 -#define CLK_APB_H265C 144 -#define CLK_JPEG 145 -#define CLK_APB_JPEG 146 -#define CLK_CAM0 147 -#define CLK_CAM1 148 -#define CLK_WGN 149 -#define CLK_WGN0 150 -#define CLK_WGN1 151 -#define CLK_WGN2 152 -#define CLK_KEYSCAN 153 -#define CLK_CFG_REG_VC 154 -#define CLK_C906_0 155 -#define CLK_C906_1 156 -#define CLK_A53 157 -#define CLK_CPU_AXI0 158 -#define CLK_CPU_GIC 159 -#define CLK_XTAL_AP 160 - -// Only for CV181x -#define CLK_DISP_SRC_VIP 161 - -#endif /* __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ */ diff --git a/include/dt-bindings/clock/ste-ab8500.h b/include/dt-bindings/clock/ste-ab8500.h deleted file mode 100644 index fb42dd0cab5..00000000000 --- a/include/dt-bindings/clock/ste-ab8500.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __STE_CLK_AB8500_H__ -#define __STE_CLK_AB8500_H__ - -#define AB8500_SYSCLK_BUF2 0 -#define AB8500_SYSCLK_BUF3 1 -#define AB8500_SYSCLK_BUF4 2 -#define AB8500_SYSCLK_ULP 3 -#define AB8500_SYSCLK_INT 4 -#define AB8500_SYSCLK_AUDIO 5 - -#endif diff --git a/include/dt-bindings/clock/sun20i-d1-ccu.h b/include/dt-bindings/clock/sun20i-d1-ccu.h deleted file mode 100644 index fdbfb404f92..00000000000 --- a/include/dt-bindings/clock/sun20i-d1-ccu.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2020 huangzhenwei@allwinnertech.com - * Copyright (C) 2021 Samuel Holland - */ - -#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ -#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ - -#define CLK_PLL_CPUX 0 -#define CLK_PLL_DDR0 1 -#define CLK_PLL_PERIPH0_4X 2 -#define CLK_PLL_PERIPH0_2X 3 -#define CLK_PLL_PERIPH0_800M 4 -#define CLK_PLL_PERIPH0 5 -#define CLK_PLL_PERIPH0_DIV3 6 -#define CLK_PLL_VIDEO0_4X 7 -#define CLK_PLL_VIDEO0_2X 8 -#define CLK_PLL_VIDEO0 9 -#define CLK_PLL_VIDEO1_4X 10 -#define CLK_PLL_VIDEO1_2X 11 -#define CLK_PLL_VIDEO1 12 -#define CLK_PLL_VE 13 -#define CLK_PLL_AUDIO0_4X 14 -#define CLK_PLL_AUDIO0_2X 15 -#define CLK_PLL_AUDIO0 16 -#define CLK_PLL_AUDIO1 17 -#define CLK_PLL_AUDIO1_DIV2 18 -#define CLK_PLL_AUDIO1_DIV5 19 -#define CLK_CPUX 20 -#define CLK_CPUX_AXI 21 -#define CLK_CPUX_APB 22 -#define CLK_PSI_AHB 23 -#define CLK_APB0 24 -#define CLK_APB1 25 -#define CLK_MBUS 26 -#define CLK_DE 27 -#define CLK_BUS_DE 28 -#define CLK_DI 29 -#define CLK_BUS_DI 30 -#define CLK_G2D 31 -#define CLK_BUS_G2D 32 -#define CLK_CE 33 -#define CLK_BUS_CE 34 -#define CLK_VE 35 -#define CLK_BUS_VE 36 -#define CLK_BUS_DMA 37 -#define CLK_BUS_MSGBOX0 38 -#define CLK_BUS_MSGBOX1 39 -#define CLK_BUS_MSGBOX2 40 -#define CLK_BUS_SPINLOCK 41 -#define CLK_BUS_HSTIMER 42 -#define CLK_AVS 43 -#define CLK_BUS_DBG 44 -#define CLK_BUS_PWM 45 -#define CLK_BUS_IOMMU 46 -#define CLK_DRAM 47 -#define CLK_MBUS_DMA 48 -#define CLK_MBUS_VE 49 -#define CLK_MBUS_CE 50 -#define CLK_MBUS_TVIN 51 -#define CLK_MBUS_CSI 52 -#define CLK_MBUS_G2D 53 -#define CLK_MBUS_RISCV 54 -#define CLK_BUS_DRAM 55 -#define CLK_MMC0 56 -#define CLK_MMC1 57 -#define CLK_MMC2 58 -#define CLK_BUS_MMC0 59 -#define CLK_BUS_MMC1 60 -#define CLK_BUS_MMC2 61 -#define CLK_BUS_UART0 62 -#define CLK_BUS_UART1 63 -#define CLK_BUS_UART2 64 -#define CLK_BUS_UART3 65 -#define CLK_BUS_UART4 66 -#define CLK_BUS_UART5 67 -#define CLK_BUS_I2C0 68 -#define CLK_BUS_I2C1 69 -#define CLK_BUS_I2C2 70 -#define CLK_BUS_I2C3 71 -#define CLK_SPI0 72 -#define CLK_SPI1 73 -#define CLK_BUS_SPI0 74 -#define CLK_BUS_SPI1 75 -#define CLK_EMAC_25M 76 -#define CLK_BUS_EMAC 77 -#define CLK_IR_TX 78 -#define CLK_BUS_IR_TX 79 -#define CLK_BUS_GPADC 80 -#define CLK_BUS_THS 81 -#define CLK_I2S0 82 -#define CLK_I2S1 83 -#define CLK_I2S2 84 -#define CLK_I2S2_ASRC 85 -#define CLK_BUS_I2S0 86 -#define CLK_BUS_I2S1 87 -#define CLK_BUS_I2S2 88 -#define CLK_SPDIF_TX 89 -#define CLK_SPDIF_RX 90 -#define CLK_BUS_SPDIF 91 -#define CLK_DMIC 92 -#define CLK_BUS_DMIC 93 -#define CLK_AUDIO_DAC 94 -#define CLK_AUDIO_ADC 95 -#define CLK_BUS_AUDIO 96 -#define CLK_USB_OHCI0 97 -#define CLK_USB_OHCI1 98 -#define CLK_BUS_OHCI0 99 -#define CLK_BUS_OHCI1 100 -#define CLK_BUS_EHCI0 101 -#define CLK_BUS_EHCI1 102 -#define CLK_BUS_OTG 103 -#define CLK_BUS_LRADC 104 -#define CLK_BUS_DPSS_TOP 105 -#define CLK_HDMI_24M 106 -#define CLK_HDMI_CEC_32K 107 -#define CLK_HDMI_CEC 108 -#define CLK_BUS_HDMI 109 -#define CLK_MIPI_DSI 110 -#define CLK_BUS_MIPI_DSI 111 -#define CLK_TCON_LCD0 112 -#define CLK_BUS_TCON_LCD0 113 -#define CLK_TCON_TV 114 -#define CLK_BUS_TCON_TV 115 -#define CLK_TVE 116 -#define CLK_BUS_TVE_TOP 117 -#define CLK_BUS_TVE 118 -#define CLK_TVD 119 -#define CLK_BUS_TVD_TOP 120 -#define CLK_BUS_TVD 121 -#define CLK_LEDC 122 -#define CLK_BUS_LEDC 123 -#define CLK_CSI_TOP 124 -#define CLK_CSI_MCLK 125 -#define CLK_BUS_CSI 126 -#define CLK_TPADC 127 -#define CLK_BUS_TPADC 128 -#define CLK_BUS_TZMA 129 -#define CLK_DSP 130 -#define CLK_BUS_DSP_CFG 131 -#define CLK_RISCV 132 -#define CLK_RISCV_AXI 133 -#define CLK_BUS_RISCV_CFG 134 -#define CLK_FANOUT_24M 135 -#define CLK_FANOUT_12M 136 -#define CLK_FANOUT_16M 137 -#define CLK_FANOUT_25M 138 -#define CLK_FANOUT_32K 139 -#define CLK_FANOUT_27M 140 -#define CLK_FANOUT_PCLK 141 -#define CLK_FANOUT0 142 -#define CLK_FANOUT1 143 -#define CLK_FANOUT2 144 -#define CLK_BUS_CAN0 145 -#define CLK_BUS_CAN1 146 - -#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun20i-d1-r-ccu.h b/include/dt-bindings/clock/sun20i-d1-r-ccu.h deleted file mode 100644 index f95c170711e..00000000000 --- a/include/dt-bindings/clock/sun20i-d1-r-ccu.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2021 Samuel Holland - */ - -#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ -#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ - -#define CLK_R_AHB 0 - -#define CLK_BUS_R_TIMER 2 -#define CLK_BUS_R_TWD 3 -#define CLK_BUS_R_PPU 4 -#define CLK_R_IR_RX 5 -#define CLK_BUS_R_IR_RX 6 -#define CLK_BUS_R_RTC 7 -#define CLK_BUS_R_CPUCFG 8 - -#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun4i-a10-ccu.h b/include/dt-bindings/clock/sun4i-a10-ccu.h deleted file mode 100644 index e4fa61be5c7..00000000000 --- a/include/dt-bindings/clock/sun4i-a10-ccu.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (C) 2017 Priit Laes - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_ -#define _DT_BINDINGS_CLK_SUN4I_A10_H_ - -#define CLK_HOSC 1 -#define CLK_PLL_VIDEO0_2X 9 -#define CLK_PLL_VIDEO1_2X 18 -#define CLK_CPU 20 - -/* AHB Gates */ -#define CLK_AHB_OTG 26 -#define CLK_AHB_EHCI0 27 -#define CLK_AHB_OHCI0 28 -#define CLK_AHB_EHCI1 29 -#define CLK_AHB_OHCI1 30 -#define CLK_AHB_SS 31 -#define CLK_AHB_DMA 32 -#define CLK_AHB_BIST 33 -#define CLK_AHB_MMC0 34 -#define CLK_AHB_MMC1 35 -#define CLK_AHB_MMC2 36 -#define CLK_AHB_MMC3 37 -#define CLK_AHB_MS 38 -#define CLK_AHB_NAND 39 -#define CLK_AHB_SDRAM 40 -#define CLK_AHB_ACE 41 -#define CLK_AHB_EMAC 42 -#define CLK_AHB_TS 43 -#define CLK_AHB_SPI0 44 -#define CLK_AHB_SPI1 45 -#define CLK_AHB_SPI2 46 -#define CLK_AHB_SPI3 47 -#define CLK_AHB_PATA 48 -#define CLK_AHB_SATA 49 -#define CLK_AHB_GPS 50 -#define CLK_AHB_HSTIMER 51 -#define CLK_AHB_VE 52 -#define CLK_AHB_TVD 53 -#define CLK_AHB_TVE0 54 -#define CLK_AHB_TVE1 55 -#define CLK_AHB_LCD0 56 -#define CLK_AHB_LCD1 57 -#define CLK_AHB_CSI0 58 -#define CLK_AHB_CSI1 59 -#define CLK_AHB_HDMI0 60 -#define CLK_AHB_HDMI1 61 -#define CLK_AHB_DE_BE0 62 -#define CLK_AHB_DE_BE1 63 -#define CLK_AHB_DE_FE0 64 -#define CLK_AHB_DE_FE1 65 -#define CLK_AHB_GMAC 66 -#define CLK_AHB_MP 67 -#define CLK_AHB_GPU 68 - -/* APB0 Gates */ -#define CLK_APB0_CODEC 69 -#define CLK_APB0_SPDIF 70 -#define CLK_APB0_I2S0 71 -#define CLK_APB0_AC97 72 -#define CLK_APB0_I2S1 73 -#define CLK_APB0_PIO 74 -#define CLK_APB0_IR0 75 -#define CLK_APB0_IR1 76 -#define CLK_APB0_I2S2 77 -#define CLK_APB0_KEYPAD 78 - -/* APB1 Gates */ -#define CLK_APB1_I2C0 79 -#define CLK_APB1_I2C1 80 -#define CLK_APB1_I2C2 81 -#define CLK_APB1_I2C3 82 -#define CLK_APB1_CAN 83 -#define CLK_APB1_SCR 84 -#define CLK_APB1_PS20 85 -#define CLK_APB1_PS21 86 -#define CLK_APB1_I2C4 87 -#define CLK_APB1_UART0 88 -#define CLK_APB1_UART1 89 -#define CLK_APB1_UART2 90 -#define CLK_APB1_UART3 91 -#define CLK_APB1_UART4 92 -#define CLK_APB1_UART5 93 -#define CLK_APB1_UART6 94 -#define CLK_APB1_UART7 95 - -/* IP clocks */ -#define CLK_NAND 96 -#define CLK_MS 97 -#define CLK_MMC0 98 -#define CLK_MMC0_OUTPUT 99 -#define CLK_MMC0_SAMPLE 100 -#define CLK_MMC1 101 -#define CLK_MMC1_OUTPUT 102 -#define CLK_MMC1_SAMPLE 103 -#define CLK_MMC2 104 -#define CLK_MMC2_OUTPUT 105 -#define CLK_MMC2_SAMPLE 106 -#define CLK_MMC3 107 -#define CLK_MMC3_OUTPUT 108 -#define CLK_MMC3_SAMPLE 109 -#define CLK_TS 110 -#define CLK_SS 111 -#define CLK_SPI0 112 -#define CLK_SPI1 113 -#define CLK_SPI2 114 -#define CLK_PATA 115 -#define CLK_IR0 116 -#define CLK_IR1 117 -#define CLK_I2S0 118 -#define CLK_AC97 119 -#define CLK_SPDIF 120 -#define CLK_KEYPAD 121 -#define CLK_SATA 122 -#define CLK_USB_OHCI0 123 -#define CLK_USB_OHCI1 124 -#define CLK_USB_PHY 125 -#define CLK_GPS 126 -#define CLK_SPI3 127 -#define CLK_I2S1 128 -#define CLK_I2S2 129 - -/* DRAM Gates */ -#define CLK_DRAM_VE 130 -#define CLK_DRAM_CSI0 131 -#define CLK_DRAM_CSI1 132 -#define CLK_DRAM_TS 133 -#define CLK_DRAM_TVD 134 -#define CLK_DRAM_TVE0 135 -#define CLK_DRAM_TVE1 136 -#define CLK_DRAM_OUT 137 -#define CLK_DRAM_DE_FE1 138 -#define CLK_DRAM_DE_FE0 139 -#define CLK_DRAM_DE_BE0 140 -#define CLK_DRAM_DE_BE1 141 -#define CLK_DRAM_MP 142 -#define CLK_DRAM_ACE 143 - -/* Display Engine Clocks */ -#define CLK_DE_BE0 144 -#define CLK_DE_BE1 145 -#define CLK_DE_FE0 146 -#define CLK_DE_FE1 147 -#define CLK_DE_MP 148 -#define CLK_TCON0_CH0 149 -#define CLK_TCON1_CH0 150 -#define CLK_CSI_SCLK 151 -#define CLK_TVD_SCLK2 152 -#define CLK_TVD 153 -#define CLK_TCON0_CH1_SCLK2 154 -#define CLK_TCON0_CH1 155 -#define CLK_TCON1_CH1_SCLK2 156 -#define CLK_TCON1_CH1 157 -#define CLK_CSI0 158 -#define CLK_CSI1 159 -#define CLK_CODEC 160 -#define CLK_VE 161 -#define CLK_AVS 162 -#define CLK_ACE 163 -#define CLK_HDMI 164 -#define CLK_GPU 165 - -#endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h6-ccu.h b/include/dt-bindings/clock/sun50i-h6-ccu.h deleted file mode 100644 index ef9123d8193..00000000000 --- a/include/dt-bindings/clock/sun50i-h6-ccu.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2017 Icenowy Zheng - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_ -#define _DT_BINDINGS_CLK_SUN50I_H6_H_ - -#define CLK_PLL_PERIPH0 3 - -#define CLK_CPUX 21 - -#define CLK_APB1 26 - -#define CLK_DE 29 -#define CLK_BUS_DE 30 -#define CLK_DEINTERLACE 31 -#define CLK_BUS_DEINTERLACE 32 -#define CLK_GPU 33 -#define CLK_BUS_GPU 34 -#define CLK_CE 35 -#define CLK_BUS_CE 36 -#define CLK_VE 37 -#define CLK_BUS_VE 38 -#define CLK_EMCE 39 -#define CLK_BUS_EMCE 40 -#define CLK_VP9 41 -#define CLK_BUS_VP9 42 -#define CLK_BUS_DMA 43 -#define CLK_BUS_MSGBOX 44 -#define CLK_BUS_SPINLOCK 45 -#define CLK_BUS_HSTIMER 46 -#define CLK_AVS 47 -#define CLK_BUS_DBG 48 -#define CLK_BUS_PSI 49 -#define CLK_BUS_PWM 50 -#define CLK_BUS_IOMMU 51 - -#define CLK_MBUS_DMA 53 -#define CLK_MBUS_VE 54 -#define CLK_MBUS_CE 55 -#define CLK_MBUS_TS 56 -#define CLK_MBUS_NAND 57 -#define CLK_MBUS_CSI 58 -#define CLK_MBUS_DEINTERLACE 59 - -#define CLK_NAND0 61 -#define CLK_NAND1 62 -#define CLK_BUS_NAND 63 -#define CLK_MMC0 64 -#define CLK_MMC1 65 -#define CLK_MMC2 66 -#define CLK_BUS_MMC0 67 -#define CLK_BUS_MMC1 68 -#define CLK_BUS_MMC2 69 -#define CLK_BUS_UART0 70 -#define CLK_BUS_UART1 71 -#define CLK_BUS_UART2 72 -#define CLK_BUS_UART3 73 -#define CLK_BUS_I2C0 74 -#define CLK_BUS_I2C1 75 -#define CLK_BUS_I2C2 76 -#define CLK_BUS_I2C3 77 -#define CLK_BUS_SCR0 78 -#define CLK_BUS_SCR1 79 -#define CLK_SPI0 80 -#define CLK_SPI1 81 -#define CLK_BUS_SPI0 82 -#define CLK_BUS_SPI1 83 -#define CLK_BUS_EMAC 84 -#define CLK_TS 85 -#define CLK_BUS_TS 86 -#define CLK_IR_TX 87 -#define CLK_BUS_IR_TX 88 -#define CLK_BUS_THS 89 -#define CLK_I2S3 90 -#define CLK_I2S0 91 -#define CLK_I2S1 92 -#define CLK_I2S2 93 -#define CLK_BUS_I2S0 94 -#define CLK_BUS_I2S1 95 -#define CLK_BUS_I2S2 96 -#define CLK_BUS_I2S3 97 -#define CLK_SPDIF 98 -#define CLK_BUS_SPDIF 99 -#define CLK_DMIC 100 -#define CLK_BUS_DMIC 101 -#define CLK_AUDIO_HUB 102 -#define CLK_BUS_AUDIO_HUB 103 -#define CLK_USB_OHCI0 104 -#define CLK_USB_PHY0 105 -#define CLK_USB_PHY1 106 -#define CLK_USB_OHCI3 107 -#define CLK_USB_PHY3 108 -#define CLK_USB_HSIC_12M 109 -#define CLK_USB_HSIC 110 -#define CLK_BUS_OHCI0 111 -#define CLK_BUS_OHCI3 112 -#define CLK_BUS_EHCI0 113 -#define CLK_BUS_XHCI 114 -#define CLK_BUS_EHCI3 115 -#define CLK_BUS_OTG 116 -#define CLK_PCIE_REF_100M 117 -#define CLK_PCIE_REF 118 -#define CLK_PCIE_REF_OUT 119 -#define CLK_PCIE_MAXI 120 -#define CLK_PCIE_AUX 121 -#define CLK_BUS_PCIE 122 -#define CLK_HDMI 123 -#define CLK_HDMI_SLOW 124 -#define CLK_HDMI_CEC 125 -#define CLK_BUS_HDMI 126 -#define CLK_BUS_TCON_TOP 127 -#define CLK_TCON_LCD0 128 -#define CLK_BUS_TCON_LCD0 129 -#define CLK_TCON_TV0 130 -#define CLK_BUS_TCON_TV0 131 -#define CLK_CSI_CCI 132 -#define CLK_CSI_TOP 133 -#define CLK_CSI_MCLK 134 -#define CLK_BUS_CSI 135 -#define CLK_HDCP 136 -#define CLK_BUS_HDCP 137 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */ diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-bindings/clock/sun50i-h6-r-ccu.h deleted file mode 100644 index a96087abc86..00000000000 --- a/include/dt-bindings/clock/sun50i-h6-r-ccu.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2017 Icenowy Zheng - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ -#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ - -#define CLK_AR100 0 - -#define CLK_R_APB1 2 - -#define CLK_R_APB1_TIMER 4 -#define CLK_R_APB1_TWD 5 -#define CLK_R_APB1_PWM 6 -#define CLK_R_APB2_UART 7 -#define CLK_R_APB2_I2C 8 -#define CLK_R_APB1_IR 9 -#define CLK_R_APB1_W1 10 - -#define CLK_IR 11 -#define CLK_W1 12 - -#define CLK_R_APB2_RSB 13 -#define CLK_R_APB1_RTC 14 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun5i-ccu.h b/include/dt-bindings/clock/sun5i-ccu.h deleted file mode 100644 index 75fe5619c3d..00000000000 --- a/include/dt-bindings/clock/sun5i-ccu.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2016 Maxime Ripard - * - * Maxime Ripard - */ - -#ifndef _DT_BINDINGS_CLK_SUN5I_H_ -#define _DT_BINDINGS_CLK_SUN5I_H_ - -#define CLK_HOSC 1 - -#define CLK_PLL_VIDEO0_2X 9 - -#define CLK_PLL_VIDEO1_2X 16 -#define CLK_CPU 17 - -#define CLK_AHB_OTG 23 -#define CLK_AHB_EHCI 24 -#define CLK_AHB_OHCI 25 -#define CLK_AHB_SS 26 -#define CLK_AHB_DMA 27 -#define CLK_AHB_BIST 28 -#define CLK_AHB_MMC0 29 -#define CLK_AHB_MMC1 30 -#define CLK_AHB_MMC2 31 -#define CLK_AHB_NAND 32 -#define CLK_AHB_SDRAM 33 -#define CLK_AHB_EMAC 34 -#define CLK_AHB_TS 35 -#define CLK_AHB_SPI0 36 -#define CLK_AHB_SPI1 37 -#define CLK_AHB_SPI2 38 -#define CLK_AHB_GPS 39 -#define CLK_AHB_HSTIMER 40 -#define CLK_AHB_VE 41 -#define CLK_AHB_TVE 42 -#define CLK_AHB_LCD 43 -#define CLK_AHB_CSI 44 -#define CLK_AHB_HDMI 45 -#define CLK_AHB_DE_BE 46 -#define CLK_AHB_DE_FE 47 -#define CLK_AHB_IEP 48 -#define CLK_AHB_GPU 49 -#define CLK_APB0_CODEC 50 -#define CLK_APB0_SPDIF 51 -#define CLK_APB0_I2S 52 -#define CLK_APB0_PIO 53 -#define CLK_APB0_IR 54 -#define CLK_APB0_KEYPAD 55 -#define CLK_APB1_I2C0 56 -#define CLK_APB1_I2C1 57 -#define CLK_APB1_I2C2 58 -#define CLK_APB1_UART0 59 -#define CLK_APB1_UART1 60 -#define CLK_APB1_UART2 61 -#define CLK_APB1_UART3 62 -#define CLK_NAND 63 -#define CLK_MMC0 64 -#define CLK_MMC1 65 -#define CLK_MMC2 66 -#define CLK_TS 67 -#define CLK_SS 68 -#define CLK_SPI0 69 -#define CLK_SPI1 70 -#define CLK_SPI2 71 -#define CLK_IR 72 -#define CLK_I2S 73 -#define CLK_SPDIF 74 -#define CLK_KEYPAD 75 -#define CLK_USB_OHCI 76 -#define CLK_USB_PHY0 77 -#define CLK_USB_PHY1 78 -#define CLK_GPS 79 -#define CLK_DRAM_VE 80 -#define CLK_DRAM_CSI 81 -#define CLK_DRAM_TS 82 -#define CLK_DRAM_TVE 83 -#define CLK_DRAM_DE_FE 84 -#define CLK_DRAM_DE_BE 85 -#define CLK_DRAM_ACE 86 -#define CLK_DRAM_IEP 87 -#define CLK_DE_BE 88 -#define CLK_DE_FE 89 -#define CLK_TCON_CH0 90 - -#define CLK_TCON_CH1 92 -#define CLK_CSI 93 -#define CLK_VE 94 -#define CLK_CODEC 95 -#define CLK_AVS 96 -#define CLK_HDMI 97 -#define CLK_GPU 98 -#define CLK_MBUS 99 -#define CLK_IEP 100 - -#endif /* _DT_BINDINGS_CLK_SUN5I_H_ */ diff --git a/include/dt-bindings/clock/sun6i-a31-ccu.h b/include/dt-bindings/clock/sun6i-a31-ccu.h deleted file mode 100644 index 39878d9dce9..00000000000 --- a/include/dt-bindings/clock/sun6i-a31-ccu.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_ -#define _DT_BINDINGS_CLK_SUN6I_A31_H_ - -#define CLK_PLL_VIDEO0_2X 7 - -#define CLK_PLL_PERIPH 10 - -#define CLK_PLL_VIDEO1_2X 13 - -#define CLK_PLL_MIPI 15 - -#define CLK_CPU 18 - -#define CLK_AHB1_MIPIDSI 23 -#define CLK_AHB1_SS 24 -#define CLK_AHB1_DMA 25 -#define CLK_AHB1_MMC0 26 -#define CLK_AHB1_MMC1 27 -#define CLK_AHB1_MMC2 28 -#define CLK_AHB1_MMC3 29 -#define CLK_AHB1_NAND1 30 -#define CLK_AHB1_NAND0 31 -#define CLK_AHB1_SDRAM 32 -#define CLK_AHB1_EMAC 33 -#define CLK_AHB1_TS 34 -#define CLK_AHB1_HSTIMER 35 -#define CLK_AHB1_SPI0 36 -#define CLK_AHB1_SPI1 37 -#define CLK_AHB1_SPI2 38 -#define CLK_AHB1_SPI3 39 -#define CLK_AHB1_OTG 40 -#define CLK_AHB1_EHCI0 41 -#define CLK_AHB1_EHCI1 42 -#define CLK_AHB1_OHCI0 43 -#define CLK_AHB1_OHCI1 44 -#define CLK_AHB1_OHCI2 45 -#define CLK_AHB1_VE 46 -#define CLK_AHB1_LCD0 47 -#define CLK_AHB1_LCD1 48 -#define CLK_AHB1_CSI 49 -#define CLK_AHB1_HDMI 50 -#define CLK_AHB1_BE0 51 -#define CLK_AHB1_BE1 52 -#define CLK_AHB1_FE0 53 -#define CLK_AHB1_FE1 54 -#define CLK_AHB1_MP 55 -#define CLK_AHB1_GPU 56 -#define CLK_AHB1_DEU0 57 -#define CLK_AHB1_DEU1 58 -#define CLK_AHB1_DRC0 59 -#define CLK_AHB1_DRC1 60 - -#define CLK_APB1_CODEC 61 -#define CLK_APB1_SPDIF 62 -#define CLK_APB1_DIGITAL_MIC 63 -#define CLK_APB1_PIO 64 -#define CLK_APB1_DAUDIO0 65 -#define CLK_APB1_DAUDIO1 66 - -#define CLK_APB2_I2C0 67 -#define CLK_APB2_I2C1 68 -#define CLK_APB2_I2C2 69 -#define CLK_APB2_I2C3 70 -#define CLK_APB2_UART0 71 -#define CLK_APB2_UART1 72 -#define CLK_APB2_UART2 73 -#define CLK_APB2_UART3 74 -#define CLK_APB2_UART4 75 -#define CLK_APB2_UART5 76 - -#define CLK_NAND0 77 -#define CLK_NAND1 78 -#define CLK_MMC0 79 -#define CLK_MMC0_SAMPLE 80 -#define CLK_MMC0_OUTPUT 81 -#define CLK_MMC1 82 -#define CLK_MMC1_SAMPLE 83 -#define CLK_MMC1_OUTPUT 84 -#define CLK_MMC2 85 -#define CLK_MMC2_SAMPLE 86 -#define CLK_MMC2_OUTPUT 87 -#define CLK_MMC3 88 -#define CLK_MMC3_SAMPLE 89 -#define CLK_MMC3_OUTPUT 90 -#define CLK_TS 91 -#define CLK_SS 92 -#define CLK_SPI0 93 -#define CLK_SPI1 94 -#define CLK_SPI2 95 -#define CLK_SPI3 96 -#define CLK_DAUDIO0 97 -#define CLK_DAUDIO1 98 -#define CLK_SPDIF 99 -#define CLK_USB_PHY0 100 -#define CLK_USB_PHY1 101 -#define CLK_USB_PHY2 102 -#define CLK_USB_OHCI0 103 -#define CLK_USB_OHCI1 104 -#define CLK_USB_OHCI2 105 - -#define CLK_DRAM_VE 110 -#define CLK_DRAM_CSI_ISP 111 -#define CLK_DRAM_TS 112 -#define CLK_DRAM_DRC0 113 -#define CLK_DRAM_DRC1 114 -#define CLK_DRAM_DEU0 115 -#define CLK_DRAM_DEU1 116 -#define CLK_DRAM_FE0 117 -#define CLK_DRAM_FE1 118 -#define CLK_DRAM_BE0 119 -#define CLK_DRAM_BE1 120 -#define CLK_DRAM_MP 121 - -#define CLK_BE0 122 -#define CLK_BE1 123 -#define CLK_FE0 124 -#define CLK_FE1 125 -#define CLK_MP 126 -#define CLK_LCD0_CH0 127 -#define CLK_LCD1_CH0 128 -#define CLK_LCD0_CH1 129 -#define CLK_LCD1_CH1 130 -#define CLK_CSI0_SCLK 131 -#define CLK_CSI0_MCLK 132 -#define CLK_CSI1_MCLK 133 -#define CLK_VE 134 -#define CLK_CODEC 135 -#define CLK_AVS 136 -#define CLK_DIGITAL_MIC 137 -#define CLK_HDMI 138 -#define CLK_HDMI_DDC 139 -#define CLK_PS 140 - -#define CLK_MIPI_DSI 143 -#define CLK_MIPI_DSI_DPHY 144 -#define CLK_MIPI_CSI_DPHY 145 -#define CLK_IEP_DRC0 146 -#define CLK_IEP_DRC1 147 -#define CLK_IEP_DEU0 148 -#define CLK_IEP_DEU1 149 -#define CLK_GPU_CORE 150 -#define CLK_GPU_MEMORY 151 -#define CLK_GPU_HYD 152 -#define CLK_ATS 153 -#define CLK_TRACE 154 - -#define CLK_OUT_A 155 -#define CLK_OUT_B 156 -#define CLK_OUT_C 157 - -#endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */ diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h deleted file mode 100644 index 3bd3aa3d57c..00000000000 --- a/include/dt-bindings/clock/sun6i-rtc.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -#ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_ -#define _DT_BINDINGS_CLK_SUN6I_RTC_H_ - -#define CLK_OSC32K 0 -#define CLK_OSC32K_FANOUT 1 -#define CLK_IOSC 2 - -#endif /* _DT_BINDINGS_CLK_SUN6I_RTC_H_ */ diff --git a/include/dt-bindings/clock/sun7i-a20-ccu.h b/include/dt-bindings/clock/sun7i-a20-ccu.h deleted file mode 100644 index 045a5178da0..00000000000 --- a/include/dt-bindings/clock/sun7i-a20-ccu.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2017 Priit Laes - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN7I_A20_H_ -#define _DT_BINDINGS_CLK_SUN7I_A20_H_ - -#include - -#define CLK_MBUS 166 -#define CLK_HDMI1_SLOW 167 -#define CLK_HDMI1 168 -#define CLK_OUT_A 169 -#define CLK_OUT_B 170 - -#endif /* _DT_BINDINGS_CLK_SUN7I_A20_H_ */ diff --git a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h b/include/dt-bindings/clock/sun8i-a23-a33-ccu.h deleted file mode 100644 index eb524d0bbd0..00000000000 --- a/include/dt-bindings/clock/sun8i-a23-a33-ccu.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ -#define _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ - -#define CLK_PLL_MIPI 13 - -#define CLK_CPUX 18 - -#define CLK_BUS_MIPI_DSI 23 -#define CLK_BUS_SS 24 -#define CLK_BUS_DMA 25 -#define CLK_BUS_MMC0 26 -#define CLK_BUS_MMC1 27 -#define CLK_BUS_MMC2 28 -#define CLK_BUS_NAND 29 -#define CLK_BUS_DRAM 30 -#define CLK_BUS_HSTIMER 31 -#define CLK_BUS_SPI0 32 -#define CLK_BUS_SPI1 33 -#define CLK_BUS_OTG 34 -#define CLK_BUS_EHCI 35 -#define CLK_BUS_OHCI 36 -#define CLK_BUS_VE 37 -#define CLK_BUS_LCD 38 -#define CLK_BUS_CSI 39 -#define CLK_BUS_DE_BE 40 -#define CLK_BUS_DE_FE 41 -#define CLK_BUS_GPU 42 -#define CLK_BUS_MSGBOX 43 -#define CLK_BUS_SPINLOCK 44 -#define CLK_BUS_DRC 45 -#define CLK_BUS_SAT 46 -#define CLK_BUS_CODEC 47 -#define CLK_BUS_PIO 48 -#define CLK_BUS_I2S0 49 -#define CLK_BUS_I2S1 50 -#define CLK_BUS_I2C0 51 -#define CLK_BUS_I2C1 52 -#define CLK_BUS_I2C2 53 -#define CLK_BUS_UART0 54 -#define CLK_BUS_UART1 55 -#define CLK_BUS_UART2 56 -#define CLK_BUS_UART3 57 -#define CLK_BUS_UART4 58 -#define CLK_NAND 59 -#define CLK_MMC0 60 -#define CLK_MMC0_SAMPLE 61 -#define CLK_MMC0_OUTPUT 62 -#define CLK_MMC1 63 -#define CLK_MMC1_SAMPLE 64 -#define CLK_MMC1_OUTPUT 65 -#define CLK_MMC2 66 -#define CLK_MMC2_SAMPLE 67 -#define CLK_MMC2_OUTPUT 68 -#define CLK_SS 69 -#define CLK_SPI0 70 -#define CLK_SPI1 71 -#define CLK_I2S0 72 -#define CLK_I2S1 73 -#define CLK_USB_PHY0 74 -#define CLK_USB_PHY1 75 -#define CLK_USB_HSIC 76 -#define CLK_USB_HSIC_12M 77 -#define CLK_USB_OHCI 78 - -#define CLK_DRAM_VE 80 -#define CLK_DRAM_CSI 81 -#define CLK_DRAM_DRC 82 -#define CLK_DRAM_DE_FE 83 -#define CLK_DRAM_DE_BE 84 -#define CLK_DE_BE 85 -#define CLK_DE_FE 86 -#define CLK_LCD_CH0 87 -#define CLK_LCD_CH1 88 -#define CLK_CSI_SCLK 89 -#define CLK_CSI_MCLK 90 -#define CLK_VE 91 -#define CLK_AC_DIG 92 -#define CLK_AC_DIG_4X 93 -#define CLK_AVS 94 - -#define CLK_DSI_SCLK 96 -#define CLK_DSI_DPHY 97 -#define CLK_DRC 98 -#define CLK_GPU 99 -#define CLK_ATS 100 - -#endif /* _DT_BINDINGS_CLK_SUN8I_A23_A33_H_ */ diff --git a/include/dt-bindings/clock/sun8i-a83t-ccu.h b/include/dt-bindings/clock/sun8i-a83t-ccu.h deleted file mode 100644 index 78af5085f63..00000000000 --- a/include/dt-bindings/clock/sun8i-a83t-ccu.h +++ /dev/null @@ -1,140 +0,0 @@ -/* - * Copyright (C) 2017 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ - -#define CLK_PLL_PERIPH 6 - -#define CLK_PLL_DE 9 - -#define CLK_C0CPUX 11 -#define CLK_C1CPUX 12 - -#define CLK_BUS_MIPI_DSI 19 -#define CLK_BUS_SS 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_NAND 25 -#define CLK_BUS_DRAM 26 -#define CLK_BUS_EMAC 27 -#define CLK_BUS_HSTIMER 28 -#define CLK_BUS_SPI0 29 -#define CLK_BUS_SPI1 30 -#define CLK_BUS_OTG 31 -#define CLK_BUS_EHCI0 32 -#define CLK_BUS_EHCI1 33 -#define CLK_BUS_OHCI0 34 - -#define CLK_BUS_VE 35 -#define CLK_BUS_TCON0 36 -#define CLK_BUS_TCON1 37 -#define CLK_BUS_CSI 38 -#define CLK_BUS_HDMI 39 -#define CLK_BUS_DE 40 -#define CLK_BUS_GPU 41 -#define CLK_BUS_MSGBOX 42 -#define CLK_BUS_SPINLOCK 43 - -#define CLK_BUS_SPDIF 44 -#define CLK_BUS_PIO 45 -#define CLK_BUS_I2S0 46 -#define CLK_BUS_I2S1 47 -#define CLK_BUS_I2S2 48 -#define CLK_BUS_TDM 49 - -#define CLK_BUS_I2C0 50 -#define CLK_BUS_I2C1 51 -#define CLK_BUS_I2C2 52 -#define CLK_BUS_UART0 53 -#define CLK_BUS_UART1 54 -#define CLK_BUS_UART2 55 -#define CLK_BUS_UART3 56 -#define CLK_BUS_UART4 57 - -#define CLK_NAND 59 -#define CLK_MMC0 60 -#define CLK_MMC0_SAMPLE 61 -#define CLK_MMC0_OUTPUT 62 -#define CLK_MMC1 63 -#define CLK_MMC1_SAMPLE 64 -#define CLK_MMC1_OUTPUT 65 -#define CLK_MMC2 66 -#define CLK_MMC2_SAMPLE 67 -#define CLK_MMC2_OUTPUT 68 -#define CLK_SS 69 -#define CLK_SPI0 70 -#define CLK_SPI1 71 -#define CLK_I2S0 72 -#define CLK_I2S1 73 -#define CLK_I2S2 74 -#define CLK_TDM 75 -#define CLK_SPDIF 76 -#define CLK_USB_PHY0 77 -#define CLK_USB_PHY1 78 -#define CLK_USB_HSIC 79 -#define CLK_USB_HSIC_12M 80 -#define CLK_USB_OHCI0 81 - -#define CLK_DRAM_VE 83 -#define CLK_DRAM_CSI 84 - -#define CLK_TCON0 85 -#define CLK_TCON1 86 -#define CLK_CSI_MISC 87 -#define CLK_MIPI_CSI 88 -#define CLK_CSI_MCLK 89 -#define CLK_CSI_SCLK 90 -#define CLK_VE 91 -#define CLK_AVS 92 -#define CLK_HDMI 93 -#define CLK_HDMI_SLOW 94 - -#define CLK_MIPI_DSI0 96 -#define CLK_MIPI_DSI1 97 -#define CLK_GPU_CORE 98 -#define CLK_GPU_MEMORY 99 -#define CLK_GPU_HYD 100 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_A83T_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun8i-de2.h b/include/dt-bindings/clock/sun8i-de2.h deleted file mode 100644 index 7768f73b051..00000000000 --- a/include/dt-bindings/clock/sun8i-de2.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ - -#define CLK_BUS_MIXER0 0 -#define CLK_BUS_MIXER1 1 -#define CLK_BUS_WB 2 - -#define CLK_MIXER0 6 -#define CLK_MIXER1 7 -#define CLK_WB 8 - -#define CLK_BUS_ROT 9 -#define CLK_ROT 10 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_DE2_H_ */ diff --git a/include/dt-bindings/clock/sun8i-h3-ccu.h b/include/dt-bindings/clock/sun8i-h3-ccu.h deleted file mode 100644 index 5d4ada2c22e..00000000000 --- a/include/dt-bindings/clock/sun8i-h3-ccu.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_ -#define _DT_BINDINGS_CLK_SUN8I_H3_H_ - -#define CLK_PLL_VIDEO 6 - -#define CLK_PLL_PERIPH0 9 - -#define CLK_CPUX 14 - -#define CLK_BUS_CE 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_NAND 25 -#define CLK_BUS_DRAM 26 -#define CLK_BUS_EMAC 27 -#define CLK_BUS_TS 28 -#define CLK_BUS_HSTIMER 29 -#define CLK_BUS_SPI0 30 -#define CLK_BUS_SPI1 31 -#define CLK_BUS_OTG 32 -#define CLK_BUS_EHCI0 33 -#define CLK_BUS_EHCI1 34 -#define CLK_BUS_EHCI2 35 -#define CLK_BUS_EHCI3 36 -#define CLK_BUS_OHCI0 37 -#define CLK_BUS_OHCI1 38 -#define CLK_BUS_OHCI2 39 -#define CLK_BUS_OHCI3 40 -#define CLK_BUS_VE 41 -#define CLK_BUS_TCON0 42 -#define CLK_BUS_TCON1 43 -#define CLK_BUS_DEINTERLACE 44 -#define CLK_BUS_CSI 45 -#define CLK_BUS_TVE 46 -#define CLK_BUS_HDMI 47 -#define CLK_BUS_DE 48 -#define CLK_BUS_GPU 49 -#define CLK_BUS_MSGBOX 50 -#define CLK_BUS_SPINLOCK 51 -#define CLK_BUS_CODEC 52 -#define CLK_BUS_SPDIF 53 -#define CLK_BUS_PIO 54 -#define CLK_BUS_THS 55 -#define CLK_BUS_I2S0 56 -#define CLK_BUS_I2S1 57 -#define CLK_BUS_I2S2 58 -#define CLK_BUS_I2C0 59 -#define CLK_BUS_I2C1 60 -#define CLK_BUS_I2C2 61 -#define CLK_BUS_UART0 62 -#define CLK_BUS_UART1 63 -#define CLK_BUS_UART2 64 -#define CLK_BUS_UART3 65 -#define CLK_BUS_SCR0 66 -#define CLK_BUS_EPHY 67 -#define CLK_BUS_DBG 68 - -#define CLK_THS 69 -#define CLK_NAND 70 -#define CLK_MMC0 71 -#define CLK_MMC0_SAMPLE 72 -#define CLK_MMC0_OUTPUT 73 -#define CLK_MMC1 74 -#define CLK_MMC1_SAMPLE 75 -#define CLK_MMC1_OUTPUT 76 -#define CLK_MMC2 77 -#define CLK_MMC2_SAMPLE 78 -#define CLK_MMC2_OUTPUT 79 -#define CLK_TS 80 -#define CLK_CE 81 -#define CLK_SPI0 82 -#define CLK_SPI1 83 -#define CLK_I2S0 84 -#define CLK_I2S1 85 -#define CLK_I2S2 86 -#define CLK_SPDIF 87 -#define CLK_USB_PHY0 88 -#define CLK_USB_PHY1 89 -#define CLK_USB_PHY2 90 -#define CLK_USB_PHY3 91 -#define CLK_USB_OHCI0 92 -#define CLK_USB_OHCI1 93 -#define CLK_USB_OHCI2 94 -#define CLK_USB_OHCI3 95 -#define CLK_DRAM 96 -#define CLK_DRAM_VE 97 -#define CLK_DRAM_CSI 98 -#define CLK_DRAM_DEINTERLACE 99 -#define CLK_DRAM_TS 100 -#define CLK_DE 101 -#define CLK_TCON0 102 -#define CLK_TVE 103 -#define CLK_DEINTERLACE 104 -#define CLK_CSI_MISC 105 -#define CLK_CSI_SCLK 106 -#define CLK_CSI_MCLK 107 -#define CLK_VE 108 -#define CLK_AC_DIG 109 -#define CLK_AVS 110 -#define CLK_HDMI 111 -#define CLK_HDMI_DDC 112 -#define CLK_MBUS 113 -#define CLK_GPU 114 - -/* New clocks imported in H5 */ -#define CLK_BUS_SCR1 115 - -#endif /* _DT_BINDINGS_CLK_SUN8I_H3_H_ */ diff --git a/include/dt-bindings/clock/sun8i-r-ccu.h b/include/dt-bindings/clock/sun8i-r-ccu.h deleted file mode 100644 index 779d20aa0d0..00000000000 --- a/include/dt-bindings/clock/sun8i-r-ccu.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (c) 2016 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ -#define _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ - -#define CLK_AR100 0 - -#define CLK_APB0_PIO 3 -#define CLK_APB0_IR 4 -#define CLK_APB0_TIMER 5 -#define CLK_APB0_RSB 6 -#define CLK_APB0_UART 7 -/* 8 is reserved for CLK_APB0_W1 on A31 */ -#define CLK_APB0_I2C 9 -#define CLK_APB0_TWD 10 - -#define CLK_IR 11 - -#endif /* _DT_BINDINGS_CLK_SUN8I_R_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h deleted file mode 100644 index d7337b55a4e..00000000000 --- a/include/dt-bindings/clock/sun8i-r40-ccu.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * Copyright (C) 2017 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_ -#define _DT_BINDINGS_CLK_SUN8I_R40_H_ - -#define CLK_PLL_VIDEO0 7 - -#define CLK_PLL_VIDEO1 16 - -#define CLK_CPU 24 - -#define CLK_BUS_MIPI_DSI 29 -#define CLK_BUS_CE 30 -#define CLK_BUS_DMA 31 -#define CLK_BUS_MMC0 32 -#define CLK_BUS_MMC1 33 -#define CLK_BUS_MMC2 34 -#define CLK_BUS_MMC3 35 -#define CLK_BUS_NAND 36 -#define CLK_BUS_DRAM 37 -#define CLK_BUS_EMAC 38 -#define CLK_BUS_TS 39 -#define CLK_BUS_HSTIMER 40 -#define CLK_BUS_SPI0 41 -#define CLK_BUS_SPI1 42 -#define CLK_BUS_SPI2 43 -#define CLK_BUS_SPI3 44 -#define CLK_BUS_SATA 45 -#define CLK_BUS_OTG 46 -#define CLK_BUS_EHCI0 47 -#define CLK_BUS_EHCI1 48 -#define CLK_BUS_EHCI2 49 -#define CLK_BUS_OHCI0 50 -#define CLK_BUS_OHCI1 51 -#define CLK_BUS_OHCI2 52 -#define CLK_BUS_VE 53 -#define CLK_BUS_MP 54 -#define CLK_BUS_DEINTERLACE 55 -#define CLK_BUS_CSI0 56 -#define CLK_BUS_CSI1 57 -#define CLK_BUS_HDMI1 58 -#define CLK_BUS_HDMI0 59 -#define CLK_BUS_DE 60 -#define CLK_BUS_TVE0 61 -#define CLK_BUS_TVE1 62 -#define CLK_BUS_TVE_TOP 63 -#define CLK_BUS_GMAC 64 -#define CLK_BUS_GPU 65 -#define CLK_BUS_TVD0 66 -#define CLK_BUS_TVD1 67 -#define CLK_BUS_TVD2 68 -#define CLK_BUS_TVD3 69 -#define CLK_BUS_TVD_TOP 70 -#define CLK_BUS_TCON_LCD0 71 -#define CLK_BUS_TCON_LCD1 72 -#define CLK_BUS_TCON_TV0 73 -#define CLK_BUS_TCON_TV1 74 -#define CLK_BUS_TCON_TOP 75 -#define CLK_BUS_CODEC 76 -#define CLK_BUS_SPDIF 77 -#define CLK_BUS_AC97 78 -#define CLK_BUS_PIO 79 -#define CLK_BUS_IR0 80 -#define CLK_BUS_IR1 81 -#define CLK_BUS_THS 82 -#define CLK_BUS_KEYPAD 83 -#define CLK_BUS_I2S0 84 -#define CLK_BUS_I2S1 85 -#define CLK_BUS_I2S2 86 -#define CLK_BUS_I2C0 87 -#define CLK_BUS_I2C1 88 -#define CLK_BUS_I2C2 89 -#define CLK_BUS_I2C3 90 -#define CLK_BUS_CAN 91 -#define CLK_BUS_SCR 92 -#define CLK_BUS_PS20 93 -#define CLK_BUS_PS21 94 -#define CLK_BUS_I2C4 95 -#define CLK_BUS_UART0 96 -#define CLK_BUS_UART1 97 -#define CLK_BUS_UART2 98 -#define CLK_BUS_UART3 99 -#define CLK_BUS_UART4 100 -#define CLK_BUS_UART5 101 -#define CLK_BUS_UART6 102 -#define CLK_BUS_UART7 103 -#define CLK_BUS_DBG 104 - -#define CLK_THS 105 -#define CLK_NAND 106 -#define CLK_MMC0 107 -#define CLK_MMC1 108 -#define CLK_MMC2 109 -#define CLK_MMC3 110 -#define CLK_TS 111 -#define CLK_CE 112 -#define CLK_SPI0 113 -#define CLK_SPI1 114 -#define CLK_SPI2 115 -#define CLK_SPI3 116 -#define CLK_I2S0 117 -#define CLK_I2S1 118 -#define CLK_I2S2 119 -#define CLK_AC97 120 -#define CLK_SPDIF 121 -#define CLK_KEYPAD 122 -#define CLK_SATA 123 -#define CLK_USB_PHY0 124 -#define CLK_USB_PHY1 125 -#define CLK_USB_PHY2 126 -#define CLK_USB_OHCI0 127 -#define CLK_USB_OHCI1 128 -#define CLK_USB_OHCI2 129 -#define CLK_IR0 130 -#define CLK_IR1 131 - -#define CLK_DRAM_VE 133 -#define CLK_DRAM_CSI0 134 -#define CLK_DRAM_CSI1 135 -#define CLK_DRAM_TS 136 -#define CLK_DRAM_TVD 137 -#define CLK_DRAM_MP 138 -#define CLK_DRAM_DEINTERLACE 139 -#define CLK_DE 140 -#define CLK_MP 141 -#define CLK_TCON_LCD0 142 -#define CLK_TCON_LCD1 143 -#define CLK_TCON_TV0 144 -#define CLK_TCON_TV1 145 -#define CLK_DEINTERLACE 146 -#define CLK_CSI1_MCLK 147 -#define CLK_CSI_SCLK 148 -#define CLK_CSI0_MCLK 149 -#define CLK_VE 150 -#define CLK_CODEC 151 -#define CLK_AVS 152 -#define CLK_HDMI 153 -#define CLK_HDMI_SLOW 154 -#define CLK_MBUS 155 -#define CLK_DSI_DPHY 156 -#define CLK_TVE0 157 -#define CLK_TVE1 158 -#define CLK_TVD0 159 -#define CLK_TVD1 160 -#define CLK_TVD2 161 -#define CLK_TVD3 162 -#define CLK_GPU 163 -#define CLK_OUTA 164 -#define CLK_OUTB 165 - -#endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */ diff --git a/include/dt-bindings/clock/sun8i-tcon-top.h b/include/dt-bindings/clock/sun8i-tcon-top.h deleted file mode 100644 index 25164d76783..00000000000 --- a/include/dt-bindings/clock/sun8i-tcon-top.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* Copyright (C) 2018 Jernej Skrabec */ - -#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ -#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ - -#define CLK_TCON_TOP_TV0 0 -#define CLK_TCON_TOP_TV1 1 -#define CLK_TCON_TOP_DSI 2 - -#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */ diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h deleted file mode 100644 index 014ac6123d1..00000000000 --- a/include/dt-bindings/clock/sun8i-v3s-ccu.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2016 Icenowy Zheng - * - * Based on sun8i-h3-ccu.h, which is: - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_ -#define _DT_BINDINGS_CLK_SUN8I_V3S_H_ - -#define CLK_CPU 14 - -#define CLK_BUS_CE 20 -#define CLK_BUS_DMA 21 -#define CLK_BUS_MMC0 22 -#define CLK_BUS_MMC1 23 -#define CLK_BUS_MMC2 24 -#define CLK_BUS_DRAM 25 -#define CLK_BUS_EMAC 26 -#define CLK_BUS_HSTIMER 27 -#define CLK_BUS_SPI0 28 -#define CLK_BUS_OTG 29 -#define CLK_BUS_EHCI0 30 -#define CLK_BUS_OHCI0 31 -#define CLK_BUS_VE 32 -#define CLK_BUS_TCON0 33 -#define CLK_BUS_CSI 34 -#define CLK_BUS_DE 35 -#define CLK_BUS_CODEC 36 -#define CLK_BUS_PIO 37 -#define CLK_BUS_I2C0 38 -#define CLK_BUS_I2C1 39 -#define CLK_BUS_UART0 40 -#define CLK_BUS_UART1 41 -#define CLK_BUS_UART2 42 -#define CLK_BUS_EPHY 43 -#define CLK_BUS_DBG 44 - -#define CLK_MMC0 45 -#define CLK_MMC0_SAMPLE 46 -#define CLK_MMC0_OUTPUT 47 -#define CLK_MMC1 48 -#define CLK_MMC1_SAMPLE 49 -#define CLK_MMC1_OUTPUT 50 -#define CLK_MMC2 51 -#define CLK_MMC2_SAMPLE 52 -#define CLK_MMC2_OUTPUT 53 -#define CLK_CE 54 -#define CLK_SPI0 55 -#define CLK_USB_PHY0 56 -#define CLK_USB_OHCI0 57 - -#define CLK_DRAM_VE 59 -#define CLK_DRAM_CSI 60 -#define CLK_DRAM_EHCI 61 -#define CLK_DRAM_OHCI 62 -#define CLK_DE 63 -#define CLK_TCON0 64 -#define CLK_CSI_MISC 65 -#define CLK_CSI0_MCLK 66 -#define CLK_CSI1_SCLK 67 -#define CLK_CSI1_MCLK 68 -#define CLK_VE 69 -#define CLK_AC_DIG 70 -#define CLK_AVS 71 - -#define CLK_MIPI_CSI 73 - -/* Clocks not available on V3s */ -#define CLK_BUS_I2S0 75 -#define CLK_I2S0 76 - -#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-ccu.h b/include/dt-bindings/clock/sun9i-a80-ccu.h deleted file mode 100644 index 6ea1492a73a..00000000000 --- a/include/dt-bindings/clock/sun9i-a80-ccu.h +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ - -#define CLK_PLL_AUDIO 2 -#define CLK_PLL_PERIPH0 3 - -#define CLK_C0CPUX 12 -#define CLK_C1CPUX 13 - -#define CLK_OUT_A 27 -#define CLK_OUT_B 28 - -#define CLK_NAND0_0 29 -#define CLK_NAND0_1 30 -#define CLK_NAND1_0 31 -#define CLK_NAND1_1 32 -#define CLK_MMC0 33 -#define CLK_MMC0_SAMPLE 34 -#define CLK_MMC0_OUTPUT 35 -#define CLK_MMC1 36 -#define CLK_MMC1_SAMPLE 37 -#define CLK_MMC1_OUTPUT 38 -#define CLK_MMC2 39 -#define CLK_MMC2_SAMPLE 40 -#define CLK_MMC2_OUTPUT 41 -#define CLK_MMC3 42 -#define CLK_MMC3_SAMPLE 43 -#define CLK_MMC3_OUTPUT 44 -#define CLK_TS 45 -#define CLK_SS 46 -#define CLK_SPI0 47 -#define CLK_SPI1 48 -#define CLK_SPI2 49 -#define CLK_SPI3 50 -#define CLK_I2S0 51 -#define CLK_I2S1 52 -#define CLK_SPDIF 53 -#define CLK_SDRAM 54 -#define CLK_DE 55 -#define CLK_EDP 56 -#define CLK_MP 57 -#define CLK_LCD0 58 -#define CLK_LCD1 59 -#define CLK_MIPI_DSI0 60 -#define CLK_MIPI_DSI1 61 -#define CLK_HDMI 62 -#define CLK_HDMI_SLOW 63 -#define CLK_MIPI_CSI 64 -#define CLK_CSI_ISP 65 -#define CLK_CSI_MISC 66 -#define CLK_CSI0_MCLK 67 -#define CLK_CSI1_MCLK 68 -#define CLK_FD 69 -#define CLK_VE 70 -#define CLK_AVS 71 -#define CLK_GPU_CORE 72 -#define CLK_GPU_MEMORY 73 -#define CLK_GPU_AXI 74 -#define CLK_SATA 75 -#define CLK_AC97 76 -#define CLK_MIPI_HSI 77 -#define CLK_GPADC 78 -#define CLK_CIR_TX 79 - -#define CLK_BUS_FD 80 -#define CLK_BUS_VE 81 -#define CLK_BUS_GPU_CTRL 82 -#define CLK_BUS_SS 83 -#define CLK_BUS_MMC 84 -#define CLK_BUS_NAND0 85 -#define CLK_BUS_NAND1 86 -#define CLK_BUS_SDRAM 87 -#define CLK_BUS_MIPI_HSI 88 -#define CLK_BUS_SATA 89 -#define CLK_BUS_TS 90 -#define CLK_BUS_SPI0 91 -#define CLK_BUS_SPI1 92 -#define CLK_BUS_SPI2 93 -#define CLK_BUS_SPI3 94 - -#define CLK_BUS_OTG 95 -#define CLK_BUS_USB 96 -#define CLK_BUS_GMAC 97 -#define CLK_BUS_MSGBOX 98 -#define CLK_BUS_SPINLOCK 99 -#define CLK_BUS_HSTIMER 100 -#define CLK_BUS_DMA 101 - -#define CLK_BUS_LCD0 102 -#define CLK_BUS_LCD1 103 -#define CLK_BUS_EDP 104 -#define CLK_BUS_CSI 105 -#define CLK_BUS_HDMI 106 -#define CLK_BUS_DE 107 -#define CLK_BUS_MP 108 -#define CLK_BUS_MIPI_DSI 109 - -#define CLK_BUS_SPDIF 110 -#define CLK_BUS_PIO 111 -#define CLK_BUS_AC97 112 -#define CLK_BUS_I2S0 113 -#define CLK_BUS_I2S1 114 -#define CLK_BUS_LRADC 115 -#define CLK_BUS_GPADC 116 -#define CLK_BUS_TWD 117 -#define CLK_BUS_CIR_TX 118 - -#define CLK_BUS_I2C0 119 -#define CLK_BUS_I2C1 120 -#define CLK_BUS_I2C2 121 -#define CLK_BUS_I2C3 122 -#define CLK_BUS_I2C4 123 -#define CLK_BUS_UART0 124 -#define CLK_BUS_UART1 125 -#define CLK_BUS_UART2 126 -#define CLK_BUS_UART3 127 -#define CLK_BUS_UART4 128 -#define CLK_BUS_UART5 129 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-de.h b/include/dt-bindings/clock/sun9i-a80-de.h deleted file mode 100644 index 3dad6c3cd13..00000000000 --- a/include/dt-bindings/clock/sun9i-a80-de.h +++ /dev/null @@ -1,80 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ - -#define CLK_FE0 0 -#define CLK_FE1 1 -#define CLK_FE2 2 -#define CLK_IEP_DEU0 3 -#define CLK_IEP_DEU1 4 -#define CLK_BE0 5 -#define CLK_BE1 6 -#define CLK_BE2 7 -#define CLK_IEP_DRC0 8 -#define CLK_IEP_DRC1 9 -#define CLK_MERGE 10 - -#define CLK_DRAM_FE0 11 -#define CLK_DRAM_FE1 12 -#define CLK_DRAM_FE2 13 -#define CLK_DRAM_DEU0 14 -#define CLK_DRAM_DEU1 15 -#define CLK_DRAM_BE0 16 -#define CLK_DRAM_BE1 17 -#define CLK_DRAM_BE2 18 -#define CLK_DRAM_DRC0 19 -#define CLK_DRAM_DRC1 20 - -#define CLK_BUS_FE0 21 -#define CLK_BUS_FE1 22 -#define CLK_BUS_FE2 23 -#define CLK_BUS_DEU0 24 -#define CLK_BUS_DEU1 25 -#define CLK_BUS_BE0 26 -#define CLK_BUS_BE1 27 -#define CLK_BUS_BE2 28 -#define CLK_BUS_DRC0 29 -#define CLK_BUS_DRC1 30 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_DE_H_ */ diff --git a/include/dt-bindings/clock/sun9i-a80-usb.h b/include/dt-bindings/clock/sun9i-a80-usb.h deleted file mode 100644 index 783a60d2cce..00000000000 --- a/include/dt-bindings/clock/sun9i-a80-usb.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ -#define _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ - -#define CLK_BUS_HCI0 0 -#define CLK_USB_OHCI0 1 -#define CLK_BUS_HCI1 2 -#define CLK_BUS_HCI2 3 -#define CLK_USB_OHCI2 4 - -#define CLK_USB0_PHY 5 -#define CLK_USB1_HSIC 6 -#define CLK_USB1_PHY 7 -#define CLK_USB2_HSIC 8 -#define CLK_USB2_PHY 9 -#define CLK_USB_HSIC 10 - -#endif /* _DT_BINDINGS_CLOCK_SUN9I_A80_USB_H_ */ diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h b/include/dt-bindings/clock/suniv-ccu-f1c100s.h deleted file mode 100644 index d7570765f42..00000000000 --- a/include/dt-bindings/clock/suniv-ccu-f1c100s.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) - * - * Copyright (c) 2018 Icenowy Zheng - * - */ - -#ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ -#define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_ - -#define CLK_CPU 11 - -#define CLK_BUS_DMA 14 -#define CLK_BUS_MMC0 15 -#define CLK_BUS_MMC1 16 -#define CLK_BUS_DRAM 17 -#define CLK_BUS_SPI0 18 -#define CLK_BUS_SPI1 19 -#define CLK_BUS_OTG 20 -#define CLK_BUS_VE 21 -#define CLK_BUS_LCD 22 -#define CLK_BUS_DEINTERLACE 23 -#define CLK_BUS_CSI 24 -#define CLK_BUS_TVD 25 -#define CLK_BUS_TVE 26 -#define CLK_BUS_DE_BE 27 -#define CLK_BUS_DE_FE 28 -#define CLK_BUS_CODEC 29 -#define CLK_BUS_SPDIF 30 -#define CLK_BUS_IR 31 -#define CLK_BUS_RSB 32 -#define CLK_BUS_I2S0 33 -#define CLK_BUS_I2C0 34 -#define CLK_BUS_I2C1 35 -#define CLK_BUS_I2C2 36 -#define CLK_BUS_PIO 37 -#define CLK_BUS_UART0 38 -#define CLK_BUS_UART1 39 -#define CLK_BUS_UART2 40 - -#define CLK_MMC0 41 -#define CLK_MMC0_SAMPLE 42 -#define CLK_MMC0_OUTPUT 43 -#define CLK_MMC1 44 -#define CLK_MMC1_SAMPLE 45 -#define CLK_MMC1_OUTPUT 46 -#define CLK_I2S 47 -#define CLK_SPDIF 48 - -#define CLK_USB_PHY0 49 - -#define CLK_DRAM_VE 50 -#define CLK_DRAM_CSI 51 -#define CLK_DRAM_DEINTERLACE 52 -#define CLK_DRAM_TVD 53 -#define CLK_DRAM_DE_FE 54 -#define CLK_DRAM_DE_BE 55 - -#define CLK_DE_BE 56 -#define CLK_DE_FE 57 -#define CLK_TCON 58 -#define CLK_DEINTERLACE 59 -#define CLK_TVE2_CLK 60 -#define CLK_TVE1_CLK 61 -#define CLK_TVD 62 -#define CLK_CSI 63 -#define CLK_VE 64 -#define CLK_CODEC 65 -#define CLK_AVS 66 - -#define CLK_IR 67 - -#endif diff --git a/include/dt-bindings/clock/versaclock.h b/include/dt-bindings/clock/versaclock.h deleted file mode 100644 index c6a6a094656..00000000000 --- a/include/dt-bindings/clock/versaclock.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -/* This file defines field values used by the versaclock 6 family - * for defining output type - */ - -#define VC5_LVPECL 0 -#define VC5_CMOS 1 -#define VC5_HCSL33 2 -#define VC5_LVDS 3 -#define VC5_CMOS2 4 -#define VC5_CMOSD 5 -#define VC5_HCSL25 6 diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h deleted file mode 100644 index 373644e4674..00000000000 --- a/include/dt-bindings/clock/vf610-clock.h +++ /dev/null @@ -1,202 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __DT_BINDINGS_CLOCK_VF610_H -#define __DT_BINDINGS_CLOCK_VF610_H - -#define VF610_CLK_DUMMY 0 -#define VF610_CLK_SIRC_128K 1 -#define VF610_CLK_SIRC_32K 2 -#define VF610_CLK_FIRC 3 -#define VF610_CLK_SXOSC 4 -#define VF610_CLK_FXOSC 5 -#define VF610_CLK_FXOSC_HALF 6 -#define VF610_CLK_SLOW_CLK_SEL 7 -#define VF610_CLK_FASK_CLK_SEL 8 -#define VF610_CLK_AUDIO_EXT 9 -#define VF610_CLK_ENET_EXT 10 -#define VF610_CLK_PLL1_SYS 11 -#define VF610_CLK_PLL1_PFD1 12 -#define VF610_CLK_PLL1_PFD2 13 -#define VF610_CLK_PLL1_PFD3 14 -#define VF610_CLK_PLL1_PFD4 15 -#define VF610_CLK_PLL2_BUS 16 -#define VF610_CLK_PLL2_PFD1 17 -#define VF610_CLK_PLL2_PFD2 18 -#define VF610_CLK_PLL2_PFD3 19 -#define VF610_CLK_PLL2_PFD4 20 -#define VF610_CLK_PLL3_USB_OTG 21 -#define VF610_CLK_PLL3_PFD1 22 -#define VF610_CLK_PLL3_PFD2 23 -#define VF610_CLK_PLL3_PFD3 24 -#define VF610_CLK_PLL3_PFD4 25 -#define VF610_CLK_PLL4_AUDIO 26 -#define VF610_CLK_PLL5_ENET 27 -#define VF610_CLK_PLL6_VIDEO 28 -#define VF610_CLK_PLL3_MAIN_DIV 29 -#define VF610_CLK_PLL4_MAIN_DIV 30 -#define VF610_CLK_PLL6_MAIN_DIV 31 -#define VF610_CLK_PLL1_PFD_SEL 32 -#define VF610_CLK_PLL2_PFD_SEL 33 -#define VF610_CLK_SYS_SEL 34 -#define VF610_CLK_DDR_SEL 35 -#define VF610_CLK_SYS_BUS 36 -#define VF610_CLK_PLATFORM_BUS 37 -#define VF610_CLK_IPG_BUS 38 -#define VF610_CLK_UART0 39 -#define VF610_CLK_UART1 40 -#define VF610_CLK_UART2 41 -#define VF610_CLK_UART3 42 -#define VF610_CLK_UART4 43 -#define VF610_CLK_UART5 44 -#define VF610_CLK_PIT 45 -#define VF610_CLK_I2C0 46 -#define VF610_CLK_I2C1 47 -#define VF610_CLK_I2C2 48 -#define VF610_CLK_I2C3 49 -#define VF610_CLK_FTM0_EXT_SEL 50 -#define VF610_CLK_FTM0_FIX_SEL 51 -#define VF610_CLK_FTM0_EXT_FIX_EN 52 -#define VF610_CLK_FTM1_EXT_SEL 53 -#define VF610_CLK_FTM1_FIX_SEL 54 -#define VF610_CLK_FTM1_EXT_FIX_EN 55 -#define VF610_CLK_FTM2_EXT_SEL 56 -#define VF610_CLK_FTM2_FIX_SEL 57 -#define VF610_CLK_FTM2_EXT_FIX_EN 58 -#define VF610_CLK_FTM3_EXT_SEL 59 -#define VF610_CLK_FTM3_FIX_SEL 60 -#define VF610_CLK_FTM3_EXT_FIX_EN 61 -#define VF610_CLK_FTM0 62 -#define VF610_CLK_FTM1 63 -#define VF610_CLK_FTM2 64 -#define VF610_CLK_FTM3 65 -#define VF610_CLK_ENET_50M 66 -#define VF610_CLK_ENET_25M 67 -#define VF610_CLK_ENET_SEL 68 -#define VF610_CLK_ENET 69 -#define VF610_CLK_ENET_TS_SEL 70 -#define VF610_CLK_ENET_TS 71 -#define VF610_CLK_DSPI0 72 -#define VF610_CLK_DSPI1 73 -#define VF610_CLK_DSPI2 74 -#define VF610_CLK_DSPI3 75 -#define VF610_CLK_WDT 76 -#define VF610_CLK_ESDHC0_SEL 77 -#define VF610_CLK_ESDHC0_EN 78 -#define VF610_CLK_ESDHC0_DIV 79 -#define VF610_CLK_ESDHC0 80 -#define VF610_CLK_ESDHC1_SEL 81 -#define VF610_CLK_ESDHC1_EN 82 -#define VF610_CLK_ESDHC1_DIV 83 -#define VF610_CLK_ESDHC1 84 -#define VF610_CLK_DCU0_SEL 85 -#define VF610_CLK_DCU0_EN 86 -#define VF610_CLK_DCU0_DIV 87 -#define VF610_CLK_DCU0 88 -#define VF610_CLK_DCU1_SEL 89 -#define VF610_CLK_DCU1_EN 90 -#define VF610_CLK_DCU1_DIV 91 -#define VF610_CLK_DCU1 92 -#define VF610_CLK_ESAI_SEL 93 -#define VF610_CLK_ESAI_EN 94 -#define VF610_CLK_ESAI_DIV 95 -#define VF610_CLK_ESAI 96 -#define VF610_CLK_SAI0_SEL 97 -#define VF610_CLK_SAI0_EN 98 -#define VF610_CLK_SAI0_DIV 99 -#define VF610_CLK_SAI0 100 -#define VF610_CLK_SAI1_SEL 101 -#define VF610_CLK_SAI1_EN 102 -#define VF610_CLK_SAI1_DIV 103 -#define VF610_CLK_SAI1 104 -#define VF610_CLK_SAI2_SEL 105 -#define VF610_CLK_SAI2_EN 106 -#define VF610_CLK_SAI2_DIV 107 -#define VF610_CLK_SAI2 108 -#define VF610_CLK_SAI3_SEL 109 -#define VF610_CLK_SAI3_EN 110 -#define VF610_CLK_SAI3_DIV 111 -#define VF610_CLK_SAI3 112 -#define VF610_CLK_USBC0 113 -#define VF610_CLK_USBC1 114 -#define VF610_CLK_QSPI0_SEL 115 -#define VF610_CLK_QSPI0_EN 116 -#define VF610_CLK_QSPI0_X4_DIV 117 -#define VF610_CLK_QSPI0_X2_DIV 118 -#define VF610_CLK_QSPI0_X1_DIV 119 -#define VF610_CLK_QSPI1_SEL 120 -#define VF610_CLK_QSPI1_EN 121 -#define VF610_CLK_QSPI1_X4_DIV 122 -#define VF610_CLK_QSPI1_X2_DIV 123 -#define VF610_CLK_QSPI1_X1_DIV 124 -#define VF610_CLK_QSPI0 125 -#define VF610_CLK_QSPI1 126 -#define VF610_CLK_NFC_SEL 127 -#define VF610_CLK_NFC_EN 128 -#define VF610_CLK_NFC_PRE_DIV 129 -#define VF610_CLK_NFC_FRAC_DIV 130 -#define VF610_CLK_NFC_INV 131 -#define VF610_CLK_NFC 132 -#define VF610_CLK_VADC_SEL 133 -#define VF610_CLK_VADC_EN 134 -#define VF610_CLK_VADC_DIV 135 -#define VF610_CLK_VADC_DIV_HALF 136 -#define VF610_CLK_VADC 137 -#define VF610_CLK_ADC0 138 -#define VF610_CLK_ADC1 139 -#define VF610_CLK_DAC0 140 -#define VF610_CLK_DAC1 141 -#define VF610_CLK_FLEXCAN0 142 -#define VF610_CLK_FLEXCAN1 143 -#define VF610_CLK_ASRC 144 -#define VF610_CLK_GPU_SEL 145 -#define VF610_CLK_GPU_EN 146 -#define VF610_CLK_GPU2D 147 -#define VF610_CLK_ENET0 148 -#define VF610_CLK_ENET1 149 -#define VF610_CLK_DMAMUX0 150 -#define VF610_CLK_DMAMUX1 151 -#define VF610_CLK_DMAMUX2 152 -#define VF610_CLK_DMAMUX3 153 -#define VF610_CLK_FLEXCAN0_EN 154 -#define VF610_CLK_FLEXCAN1_EN 155 -#define VF610_CLK_PLL7_USB_HOST 156 -#define VF610_CLK_USBPHY0 157 -#define VF610_CLK_USBPHY1 158 -#define VF610_CLK_LVDS1_IN 159 -#define VF610_CLK_ANACLK1 160 -#define VF610_CLK_PLL1_BYPASS_SRC 161 -#define VF610_CLK_PLL2_BYPASS_SRC 162 -#define VF610_CLK_PLL3_BYPASS_SRC 163 -#define VF610_CLK_PLL4_BYPASS_SRC 164 -#define VF610_CLK_PLL5_BYPASS_SRC 165 -#define VF610_CLK_PLL6_BYPASS_SRC 166 -#define VF610_CLK_PLL7_BYPASS_SRC 167 -#define VF610_CLK_PLL1 168 -#define VF610_CLK_PLL2 169 -#define VF610_CLK_PLL3 170 -#define VF610_CLK_PLL4 171 -#define VF610_CLK_PLL5 172 -#define VF610_CLK_PLL6 173 -#define VF610_CLK_PLL7 174 -#define VF610_PLL1_BYPASS 175 -#define VF610_PLL2_BYPASS 176 -#define VF610_PLL3_BYPASS 177 -#define VF610_PLL4_BYPASS 178 -#define VF610_PLL5_BYPASS 179 -#define VF610_PLL6_BYPASS 180 -#define VF610_PLL7_BYPASS 181 -#define VF610_CLK_SNVS 182 -#define VF610_CLK_DAP 183 -#define VF610_CLK_OCOTP 184 -#define VF610_CLK_DDRMC 185 -#define VF610_CLK_WKPU 186 -#define VF610_CLK_TCON0 187 -#define VF610_CLK_TCON1 188 -#define VF610_CLK_CAAM 189 -#define VF610_CLK_CRC 190 -#define VF610_CLK_END 191 - -#endif /* __DT_BINDINGS_CLOCK_VF610_H */ diff --git a/include/dt-bindings/display/tda998x.h b/include/dt-bindings/display/tda998x.h deleted file mode 100644 index 746831ff396..00000000000 --- a/include/dt-bindings/display/tda998x.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_TDA998X_H -#define _DT_BINDINGS_TDA998X_H - -#define TDA998x_SPDIF 1 -#define TDA998x_I2S 2 - -#endif /*_DT_BINDINGS_TDA998X_H */ diff --git a/include/dt-bindings/dma/sun4i-a10.h b/include/dt-bindings/dma/sun4i-a10.h deleted file mode 100644 index 8caba9ef7e9..00000000000 --- a/include/dt-bindings/dma/sun4i-a10.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright 2014 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __DT_BINDINGS_DMA_SUN4I_A10_H_ -#define __DT_BINDINGS_DMA_SUN4I_A10_H_ - -#define SUN4I_DMA_NORMAL 0 -#define SUN4I_DMA_DEDICATED 1 - -#endif /* __DT_BINDINGS_DMA_SUN4I_A10_H_ */ diff --git a/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h b/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h deleted file mode 100644 index 3719cda5679..00000000000 --- a/include/dt-bindings/dma/xlnx-zynqmp-dpdma.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright 2019 Laurent Pinchart - */ - -#ifndef __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ -#define __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ - -#define ZYNQMP_DPDMA_VIDEO0 0 -#define ZYNQMP_DPDMA_VIDEO1 1 -#define ZYNQMP_DPDMA_VIDEO2 2 -#define ZYNQMP_DPDMA_GRAPHICS 3 -#define ZYNQMP_DPDMA_AUDIO0 4 -#define ZYNQMP_DPDMA_AUDIO1 5 - -#endif /* __DT_BINDINGS_DMA_XLNX_ZYNQMP_DPDMA_H__ */ diff --git a/include/dt-bindings/gpio/uniphier-gpio.h b/include/dt-bindings/gpio/uniphier-gpio.h deleted file mode 100644 index 9f0ad174f61..00000000000 --- a/include/dt-bindings/gpio/uniphier-gpio.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2017 Socionext Inc. - * Author: Masahiro Yamada - */ - -#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H -#define _DT_BINDINGS_GPIO_UNIPHIER_H - -#define UNIPHIER_GPIO_LINES_PER_BANK 8 - -#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15) - -#define UNIPHIER_GPIO_PORT(bank, line) \ - ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line)) - -#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n)) - -#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */ diff --git a/include/dt-bindings/leds/leds-pca9532.h b/include/dt-bindings/leds/leds-pca9532.h deleted file mode 100644 index 4d917aab7e1..00000000000 --- a/include/dt-bindings/leds/leds-pca9532.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This header provides constants for pca9532 LED bindings. - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef _DT_BINDINGS_LEDS_PCA9532_H -#define _DT_BINDINGS_LEDS_PCA9532_H - -#define PCA9532_TYPE_NONE 0 -#define PCA9532_TYPE_LED 1 -#define PCA9532_TYPE_N2100_BEEP 2 -#define PCA9532_TYPE_GPIO 3 -#define PCA9532_LED_TIMER2 4 - -#endif /* _DT_BINDINGS_LEDS_PCA9532_H */ diff --git a/include/dt-bindings/media/tda1997x.h b/include/dt-bindings/media/tda1997x.h deleted file mode 100644 index bd9fbd718ec..00000000000 --- a/include/dt-bindings/media/tda1997x.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2017 Gateworks Corporation - */ -#ifndef _DT_BINDINGS_MEDIA_TDA1997X_H -#define _DT_BINDINGS_MEDIA_TDA1997X_H - -/* TDA19973 36bit Video Port control registers */ -#define TDA1997X_VP36_35_32 0 -#define TDA1997X_VP36_31_28 1 -#define TDA1997X_VP36_27_24 2 -#define TDA1997X_VP36_23_20 3 -#define TDA1997X_VP36_19_16 4 -#define TDA1997X_VP36_15_12 5 -#define TDA1997X_VP36_11_08 6 -#define TDA1997X_VP36_07_04 7 -#define TDA1997X_VP36_03_00 8 - -/* TDA19971 24bit Video Port control registers */ -#define TDA1997X_VP24_V23_20 0 -#define TDA1997X_VP24_V19_16 1 -#define TDA1997X_VP24_V15_12 3 -#define TDA1997X_VP24_V11_08 4 -#define TDA1997X_VP24_V07_04 6 -#define TDA1997X_VP24_V03_00 7 - -/* Pin groups */ -#define TDA1997X_VP_OUT_EN 0x80 /* enable output group */ -#define TDA1997X_VP_HIZ 0x40 /* hi-Z output group when not used */ -#define TDA1997X_VP_SWP 0x10 /* pin-swap output group */ -#define TDA1997X_R_CR_CBCR_3_0 (0 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_R_CR_CBCR_7_4 (1 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_R_CR_CBCR_11_8 (2 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_B_CB_3_0 (3 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_B_CB_7_4 (4 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_B_CB_11_8 (5 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_G_Y_3_0 (6 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_G_Y_7_4 (7 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -#define TDA1997X_G_Y_11_8 (8 | TDA1997X_VP_OUT_EN | TDA1997X_VP_HIZ) -/* pinswapped groups */ -#define TDA1997X_R_CR_CBCR_3_0_S (TDA1997X_R_CR_CBCR_3_0 | TDA1997X_VP_SWAP) -#define TDA1997X_R_CR_CBCR_7_4_S (TDA1997X_R_CR_CBCR_7_4 | TDA1997X_VP_SWAP) -#define TDA1997X_R_CR_CBCR_11_8_S (TDA1997X_R_CR_CBCR_11_8 | TDA1997X_VP_SWAP) -#define TDA1997X_B_CB_3_0_S (TDA1997X_B_CB_3_0 | TDA1997X_VP_SWAP) -#define TDA1997X_B_CB_7_4_S (TDA1997X_B_CB_7_4 | TDA1997X_VP_SWAP) -#define TDA1997X_B_CB_11_8_S (TDA1997X_B_CB_11_8 | TDA1997X_VP_SWAP) -#define TDA1997X_G_Y_3_0_S (TDA1997X_G_Y_3_0 | TDA1997X_VP_SWAP) -#define TDA1997X_G_Y_7_4_S (TDA1997X_G_Y_7_4 | TDA1997X_VP_SWAP) -#define TDA1997X_G_Y_11_8_S (TDA1997X_G_Y_11_8 | TDA1997X_VP_SWAP) - -/* Audio bus DAI format */ -#define TDA1997X_I2S16 1 /* I2S 16bit */ -#define TDA1997X_I2S32 2 /* I2S 32bit */ -#define TDA1997X_SPDIF 3 /* SPDIF */ -#define TDA1997X_OBA 4 /* One Bit Audio */ -#define TDA1997X_DST 5 /* Direct Stream Transfer */ -#define TDA1997X_I2S16_HBR 6 /* HBR straight in I2S 16bit mode */ -#define TDA1997X_I2S16_HBR_DEMUX 7 /* HBR demux in I2S 16bit mode */ -#define TDA1997X_I2S32_HBR_DEMUX 8 /* HBR demux in I2S 32bit mode */ -#define TDA1997X_SPDIF_HBR_DEMUX 9 /* HBR demux in SPDIF mode */ - -/* Audio bus channel layout */ -#define TDA1997X_LAYOUT0 0 /* 2-channel */ -#define TDA1997X_LAYOUT1 1 /* 8-channel */ - -/* Audio bus clock */ -#define TDA1997X_ACLK_16FS 0 -#define TDA1997X_ACLK_32FS 1 -#define TDA1997X_ACLK_64FS 2 -#define TDA1997X_ACLK_128FS 3 -#define TDA1997X_ACLK_256FS 4 -#define TDA1997X_ACLK_512FS 5 - -#endif /* _DT_BINDINGS_MEDIA_TDA1997X_H */ diff --git a/include/dt-bindings/mfd/at91-usart.h b/include/dt-bindings/mfd/at91-usart.h deleted file mode 100644 index 2de5bc312e1..00000000000 --- a/include/dt-bindings/mfd/at91-usart.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides macros for AT91 USART DT bindings. - * - * Copyright (C) 2018 Microchip Technology - * - * Author: Radu Pirea - * - */ - -#ifndef __DT_BINDINGS_AT91_USART_H__ -#define __DT_BINDINGS_AT91_USART_H__ - -#define AT91_USART_MODE_SERIAL 0 -#define AT91_USART_MODE_SPI 1 - -#endif /* __DT_BINDINGS_AT91_USART_H__ */ diff --git a/include/dt-bindings/mfd/atmel-flexcom.h b/include/dt-bindings/mfd/atmel-flexcom.h deleted file mode 100644 index 4e2fc323639..00000000000 --- a/include/dt-bindings/mfd/atmel-flexcom.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * This header provides macros for Atmel Flexcom DT bindings. - * - * Copyright (C) 2015 Cyrille Pitchen - */ - -#ifndef __DT_BINDINGS_ATMEL_FLEXCOM_H__ -#define __DT_BINDINGS_ATMEL_FLEXCOM_H__ - -#define ATMEL_FLEXCOM_MODE_USART 1 -#define ATMEL_FLEXCOM_MODE_SPI 2 -#define ATMEL_FLEXCOM_MODE_TWI 3 - -#endif /* __DT_BINDINGS_ATMEL_FLEXCOM_H__ */ diff --git a/include/dt-bindings/net/microchip-lan78xx.h b/include/dt-bindings/net/microchip-lan78xx.h deleted file mode 100644 index 0742ff07530..00000000000 --- a/include/dt-bindings/net/microchip-lan78xx.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _DT_BINDINGS_MICROCHIP_LAN78XX_H -#define _DT_BINDINGS_MICROCHIP_LAN78XX_H - -/* LED modes for LAN7800/LAN7850 embedded PHY */ - -#define LAN78XX_LINK_ACTIVITY 0 -#define LAN78XX_LINK_1000_ACTIVITY 1 -#define LAN78XX_LINK_100_ACTIVITY 2 -#define LAN78XX_LINK_10_ACTIVITY 3 -#define LAN78XX_LINK_100_1000_ACTIVITY 4 -#define LAN78XX_LINK_10_1000_ACTIVITY 5 -#define LAN78XX_LINK_10_100_ACTIVITY 6 -#define LAN78XX_DUPLEX_COLLISION 8 -#define LAN78XX_COLLISION 9 -#define LAN78XX_ACTIVITY 10 -#define LAN78XX_AUTONEG_FAULT 12 -#define LAN78XX_FORCE_LED_OFF 14 -#define LAN78XX_FORCE_LED_ON 15 - -#endif diff --git a/include/dt-bindings/net/qca-ar803x.h b/include/dt-bindings/net/qca-ar803x.h deleted file mode 100644 index 9c046c7242e..00000000000 --- a/include/dt-bindings/net/qca-ar803x.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Device Tree constants for the Qualcomm Atheros AR803x PHYs - */ - -#ifndef _DT_BINDINGS_QCA_AR803X_H -#define _DT_BINDINGS_QCA_AR803X_H - -#define AR803X_STRENGTH_FULL 0 -#define AR803X_STRENGTH_HALF 1 -#define AR803X_STRENGTH_QUARTER 2 - -#endif diff --git a/include/dt-bindings/phy/phy-ti.h b/include/dt-bindings/phy/phy-ti.h deleted file mode 100644 index ad955d3a56b..00000000000 --- a/include/dt-bindings/phy/phy-ti.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for TI SERDES. - */ - -#ifndef _DT_BINDINGS_TI_SERDES -#define _DT_BINDINGS_TI_SERDES - -/* Clock index for output clocks from WIZ */ - -/* MUX Clocks */ -#define TI_WIZ_PLL0_REFCLK 0 -#define TI_WIZ_PLL1_REFCLK 1 -#define TI_WIZ_REFCLK_DIG 2 - -/* Reserve index here for future additions */ - -/* MISC Clocks */ -#define TI_WIZ_PHY_EN_REFCLK 16 - -#endif /* _DT_BINDINGS_TI_SERDES */ diff --git a/include/dt-bindings/pinctrl/am33xx.h b/include/dt-bindings/pinctrl/am33xx.h deleted file mode 100644 index 17877e85980..00000000000 --- a/include/dt-bindings/pinctrl/am33xx.h +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants specific to AM33XX pinctrl bindings. - */ - -#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H -#define _DT_BINDINGS_PINCTRL_AM33XX_H - -#include - -/* am33xx specific mux bit defines */ -#undef PULL_ENA -#undef INPUT_EN - -#define PULL_DISABLE (1 << 3) -#define INPUT_EN (1 << 5) -#define SLEWCTRL_SLOW (1 << 6) -#define SLEWCTRL_FAST 0 - -/* update macro depending on INPUT_EN and PULL_ENA */ -#undef PIN_OUTPUT -#undef PIN_OUTPUT_PULLUP -#undef PIN_OUTPUT_PULLDOWN -#undef PIN_INPUT -#undef PIN_INPUT_PULLUP -#undef PIN_INPUT_PULLDOWN - -#define PIN_OUTPUT (PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN 0 -#define PIN_INPUT (INPUT_EN | PULL_DISABLE) -#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN) - -/* undef non-existing modes */ -#undef PIN_OFF_NONE -#undef PIN_OFF_OUTPUT_HIGH -#undef PIN_OFF_OUTPUT_LOW -#undef PIN_OFF_INPUT_PULLUP -#undef PIN_OFF_INPUT_PULLDOWN -#undef PIN_OFF_WAKEUPENABLE - -#define AM335X_PIN_OFFSET_MIN 0x0800U - -#define AM335X_PIN_GPMC_AD0 0x800 -#define AM335X_PIN_GPMC_AD1 0x804 -#define AM335X_PIN_GPMC_AD2 0x808 -#define AM335X_PIN_GPMC_AD3 0x80c -#define AM335X_PIN_GPMC_AD4 0x810 -#define AM335X_PIN_GPMC_AD5 0x814 -#define AM335X_PIN_GPMC_AD6 0x818 -#define AM335X_PIN_GPMC_AD7 0x81c -#define AM335X_PIN_GPMC_AD8 0x820 -#define AM335X_PIN_GPMC_AD9 0x824 -#define AM335X_PIN_GPMC_AD10 0x828 -#define AM335X_PIN_GPMC_AD11 0x82c -#define AM335X_PIN_GPMC_AD12 0x830 -#define AM335X_PIN_GPMC_AD13 0x834 -#define AM335X_PIN_GPMC_AD14 0x838 -#define AM335X_PIN_GPMC_AD15 0x83c -#define AM335X_PIN_GPMC_A0 0x840 -#define AM335X_PIN_GPMC_A1 0x844 -#define AM335X_PIN_GPMC_A2 0x848 -#define AM335X_PIN_GPMC_A3 0x84c -#define AM335X_PIN_GPMC_A4 0x850 -#define AM335X_PIN_GPMC_A5 0x854 -#define AM335X_PIN_GPMC_A6 0x858 -#define AM335X_PIN_GPMC_A7 0x85c -#define AM335X_PIN_GPMC_A8 0x860 -#define AM335X_PIN_GPMC_A9 0x864 -#define AM335X_PIN_GPMC_A10 0x868 -#define AM335X_PIN_GPMC_A11 0x86c -#define AM335X_PIN_GPMC_WAIT0 0x870 -#define AM335X_PIN_GPMC_WPN 0x874 -#define AM335X_PIN_GPMC_BEN1 0x878 -#define AM335X_PIN_GPMC_CSN0 0x87c -#define AM335X_PIN_GPMC_CSN1 0x880 -#define AM335X_PIN_GPMC_CSN2 0x884 -#define AM335X_PIN_GPMC_CSN3 0x888 -#define AM335X_PIN_GPMC_CLK 0x88c -#define AM335X_PIN_GPMC_ADVN_ALE 0x890 -#define AM335X_PIN_GPMC_OEN_REN 0x894 -#define AM335X_PIN_GPMC_WEN 0x898 -#define AM335X_PIN_GPMC_BEN0_CLE 0x89c -#define AM335X_PIN_LCD_DATA0 0x8a0 -#define AM335X_PIN_LCD_DATA1 0x8a4 -#define AM335X_PIN_LCD_DATA2 0x8a8 -#define AM335X_PIN_LCD_DATA3 0x8ac -#define AM335X_PIN_LCD_DATA4 0x8b0 -#define AM335X_PIN_LCD_DATA5 0x8b4 -#define AM335X_PIN_LCD_DATA6 0x8b8 -#define AM335X_PIN_LCD_DATA7 0x8bc -#define AM335X_PIN_LCD_DATA8 0x8c0 -#define AM335X_PIN_LCD_DATA9 0x8c4 -#define AM335X_PIN_LCD_DATA10 0x8c8 -#define AM335X_PIN_LCD_DATA11 0x8cc -#define AM335X_PIN_LCD_DATA12 0x8d0 -#define AM335X_PIN_LCD_DATA13 0x8d4 -#define AM335X_PIN_LCD_DATA14 0x8d8 -#define AM335X_PIN_LCD_DATA15 0x8dc -#define AM335X_PIN_LCD_VSYNC 0x8e0 -#define AM335X_PIN_LCD_HSYNC 0x8e4 -#define AM335X_PIN_LCD_PCLK 0x8e8 -#define AM335X_PIN_LCD_AC_BIAS_EN 0x8ec -#define AM335X_PIN_MMC0_DAT3 0x8f0 -#define AM335X_PIN_MMC0_DAT2 0x8f4 -#define AM335X_PIN_MMC0_DAT1 0x8f8 -#define AM335X_PIN_MMC0_DAT0 0x8fc -#define AM335X_PIN_MMC0_CLK 0x900 -#define AM335X_PIN_MMC0_CMD 0x904 -#define AM335X_PIN_MII1_COL 0x908 -#define AM335X_PIN_MII1_CRS 0x90c -#define AM335X_PIN_MII1_RX_ER 0x910 -#define AM335X_PIN_MII1_TX_EN 0x914 -#define AM335X_PIN_MII1_RX_DV 0x918 -#define AM335X_PIN_MII1_TXD3 0x91c -#define AM335X_PIN_MII1_TXD2 0x920 -#define AM335X_PIN_MII1_TXD1 0x924 -#define AM335X_PIN_MII1_TXD0 0x928 -#define AM335X_PIN_MII1_TX_CLK 0x92c -#define AM335X_PIN_MII1_RX_CLK 0x930 -#define AM335X_PIN_MII1_RXD3 0x934 -#define AM335X_PIN_MII1_RXD2 0x938 -#define AM335X_PIN_MII1_RXD1 0x93c -#define AM335X_PIN_MII1_RXD0 0x940 -#define AM335X_PIN_RMII1_REF_CLK 0x944 -#define AM335X_PIN_MDIO 0x948 -#define AM335X_PIN_MDC 0x94c -#define AM335X_PIN_SPI0_SCLK 0x950 -#define AM335X_PIN_SPI0_D0 0x954 -#define AM335X_PIN_SPI0_D1 0x958 -#define AM335X_PIN_SPI0_CS0 0x95c -#define AM335X_PIN_SPI0_CS1 0x960 -#define AM335X_PIN_ECAP0_IN_PWM0_OUT 0x964 -#define AM335X_PIN_UART0_CTSN 0x968 -#define AM335X_PIN_UART0_RTSN 0x96c -#define AM335X_PIN_UART0_RXD 0x970 -#define AM335X_PIN_UART0_TXD 0x974 -#define AM335X_PIN_UART1_CTSN 0x978 -#define AM335X_PIN_UART1_RTSN 0x97c -#define AM335X_PIN_UART1_RXD 0x980 -#define AM335X_PIN_UART1_TXD 0x984 -#define AM335X_PIN_I2C0_SDA 0x988 -#define AM335X_PIN_I2C0_SCL 0x98c -#define AM335X_PIN_MCASP0_ACLKX 0x990 -#define AM335X_PIN_MCASP0_FSX 0x994 -#define AM335X_PIN_MCASP0_AXR0 0x998 -#define AM335X_PIN_MCASP0_AHCLKR 0x99c -#define AM335X_PIN_MCASP0_ACLKR 0x9a0 -#define AM335X_PIN_MCASP0_FSR 0x9a4 -#define AM335X_PIN_MCASP0_AXR1 0x9a8 -#define AM335X_PIN_MCASP0_AHCLKX 0x9ac -#define AM335X_PIN_XDMA_EVENT_INTR0 0x9b0 -#define AM335X_PIN_XDMA_EVENT_INTR1 0x9b4 -#define AM335X_PIN_WARMRSTN 0x9b8 -#define AM335X_PIN_NNMI 0x9c0 -#define AM335X_PIN_TMS 0x9d0 -#define AM335X_PIN_TDI 0x9d4 -#define AM335X_PIN_TDO 0x9d8 -#define AM335X_PIN_TCK 0x9dc -#define AM335X_PIN_TRSTN 0x9e0 -#define AM335X_PIN_EMU0 0x9e4 -#define AM335X_PIN_EMU1 0x9e8 -#define AM335X_PIN_RTC_PWRONRSTN 0x9f8 -#define AM335X_PIN_PMIC_POWER_EN 0x9fc -#define AM335X_PIN_EXT_WAKEUP 0xa00 -#define AM335X_PIN_USB0_DRVVBUS 0xa1c -#define AM335X_PIN_USB1_DRVVBUS 0xa34 - -#define AM335X_PIN_OFFSET_MAX 0x0a34U - -#endif diff --git a/include/dt-bindings/pinctrl/apple.h b/include/dt-bindings/pinctrl/apple.h deleted file mode 100644 index ea0a6f46659..00000000000 --- a/include/dt-bindings/pinctrl/apple.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR MIT */ -/* - * This header provides constants for Apple pinctrl bindings. - */ - -#ifndef _DT_BINDINGS_PINCTRL_APPLE_H -#define _DT_BINDINGS_PINCTRL_APPLE_H - -#define APPLE_PINMUX(pin, func) ((pin) | ((func) << 16)) -#define APPLE_PIN(pinmux) ((pinmux) & 0xffff) -#define APPLE_FUNC(pinmux) ((pinmux) >> 16) - -#endif /* _DT_BINDINGS_PINCTRL_APPLE_H */ diff --git a/include/dt-bindings/pinctrl/bcm2835.h b/include/dt-bindings/pinctrl/bcm2835.h deleted file mode 100644 index b5b2654a0e4..00000000000 --- a/include/dt-bindings/pinctrl/bcm2835.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Header providing constants for bcm2835 pinctrl bindings. - * - * Copyright (C) 2015 Stefan Wahren - */ - -#ifndef __DT_BINDINGS_PINCTRL_BCM2835_H__ -#define __DT_BINDINGS_PINCTRL_BCM2835_H__ - -/* brcm,function property */ -#define BCM2835_FSEL_GPIO_IN 0 -#define BCM2835_FSEL_GPIO_OUT 1 -#define BCM2835_FSEL_ALT5 2 -#define BCM2835_FSEL_ALT4 3 -#define BCM2835_FSEL_ALT0 4 -#define BCM2835_FSEL_ALT1 5 -#define BCM2835_FSEL_ALT2 6 -#define BCM2835_FSEL_ALT3 7 - -/* brcm,pull property */ -#define BCM2835_PUD_OFF 0 -#define BCM2835_PUD_DOWN 1 -#define BCM2835_PUD_UP 2 - -#endif /* __DT_BINDINGS_PINCTRL_BCM2835_H__ */ diff --git a/include/dt-bindings/pinctrl/mt8365-pinfunc.h b/include/dt-bindings/pinctrl/mt8365-pinfunc.h deleted file mode 100644 index e2ec8af57dc..00000000000 --- a/include/dt-bindings/pinctrl/mt8365-pinfunc.h +++ /dev/null @@ -1,858 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 MediaTek Inc. - */ -#ifndef __MT8365_PINFUNC_H -#define __MT8365_PINFUNC_H - -#include - -#define MT8365_PIN_0_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) -#define MT8365_PIN_0_GPIO0__FUNC_DPI_D0 (MTK_PIN_NO(0) | 1) -#define MT8365_PIN_0_GPIO0__FUNC_PWM_A (MTK_PIN_NO(0) | 2) -#define MT8365_PIN_0_GPIO0__FUNC_I2S2_BCK (MTK_PIN_NO(0) | 3) -#define MT8365_PIN_0_GPIO0__FUNC_EXT_TXD0 (MTK_PIN_NO(0) | 4) -#define MT8365_PIN_0_GPIO0__FUNC_CONN_MCU_TDO (MTK_PIN_NO(0) | 5) -#define MT8365_PIN_0_GPIO0__FUNC_DBG_MON_A0 (MTK_PIN_NO(0) | 7) - -#define MT8365_PIN_1_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) -#define MT8365_PIN_1_GPIO1__FUNC_DPI_D1 (MTK_PIN_NO(1) | 1) -#define MT8365_PIN_1_GPIO1__FUNC_PWM_B (MTK_PIN_NO(1) | 2) -#define MT8365_PIN_1_GPIO1__FUNC_I2S2_LRCK (MTK_PIN_NO(1) | 3) -#define MT8365_PIN_1_GPIO1__FUNC_EXT_TXD1 (MTK_PIN_NO(1) | 4) -#define MT8365_PIN_1_GPIO1__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(1) | 5) -#define MT8365_PIN_1_GPIO1__FUNC_DBG_MON_A1 (MTK_PIN_NO(1) | 7) - -#define MT8365_PIN_2_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) -#define MT8365_PIN_2_GPIO2__FUNC_DPI_D2 (MTK_PIN_NO(2) | 1) -#define MT8365_PIN_2_GPIO2__FUNC_PWM_C (MTK_PIN_NO(2) | 2) -#define MT8365_PIN_2_GPIO2__FUNC_I2S2_MCK (MTK_PIN_NO(2) | 3) -#define MT8365_PIN_2_GPIO2__FUNC_EXT_TXD2 (MTK_PIN_NO(2) | 4) -#define MT8365_PIN_2_GPIO2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(2) | 5) -#define MT8365_PIN_2_GPIO2__FUNC_DBG_MON_A2 (MTK_PIN_NO(2) | 7) - -#define MT8365_PIN_3_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) -#define MT8365_PIN_3_GPIO3__FUNC_DPI_D3 (MTK_PIN_NO(3) | 1) -#define MT8365_PIN_3_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 2) -#define MT8365_PIN_3_GPIO3__FUNC_I2S2_DI (MTK_PIN_NO(3) | 3) -#define MT8365_PIN_3_GPIO3__FUNC_EXT_TXD3 (MTK_PIN_NO(3) | 4) -#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_TCK (MTK_PIN_NO(3) | 5) -#define MT8365_PIN_3_GPIO3__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(3) | 6) -#define MT8365_PIN_3_GPIO3__FUNC_DBG_MON_A3 (MTK_PIN_NO(3) | 7) - -#define MT8365_PIN_4_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) -#define MT8365_PIN_4_GPIO4__FUNC_DPI_D4 (MTK_PIN_NO(4) | 1) -#define MT8365_PIN_4_GPIO4__FUNC_CLKM1 (MTK_PIN_NO(4) | 2) -#define MT8365_PIN_4_GPIO4__FUNC_I2S1_BCK (MTK_PIN_NO(4) | 3) -#define MT8365_PIN_4_GPIO4__FUNC_EXT_TXC (MTK_PIN_NO(4) | 4) -#define MT8365_PIN_4_GPIO4__FUNC_CONN_MCU_TDI (MTK_PIN_NO(4) | 5) -#define MT8365_PIN_4_GPIO4__FUNC_VDEC_TEST_CK (MTK_PIN_NO(4) | 6) -#define MT8365_PIN_4_GPIO4__FUNC_DBG_MON_A4 (MTK_PIN_NO(4) | 7) - -#define MT8365_PIN_5_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) -#define MT8365_PIN_5_GPIO5__FUNC_DPI_D5 (MTK_PIN_NO(5) | 1) -#define MT8365_PIN_5_GPIO5__FUNC_CLKM2 (MTK_PIN_NO(5) | 2) -#define MT8365_PIN_5_GPIO5__FUNC_I2S1_LRCK (MTK_PIN_NO(5) | 3) -#define MT8365_PIN_5_GPIO5__FUNC_EXT_RXER (MTK_PIN_NO(5) | 4) -#define MT8365_PIN_5_GPIO5__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(5) | 5) -#define MT8365_PIN_5_GPIO5__FUNC_MM_TEST_CK (MTK_PIN_NO(5) | 6) -#define MT8365_PIN_5_GPIO5__FUNC_DBG_MON_A5 (MTK_PIN_NO(5) | 7) - -#define MT8365_PIN_6_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) -#define MT8365_PIN_6_GPIO6__FUNC_DPI_D6 (MTK_PIN_NO(6) | 1) -#define MT8365_PIN_6_GPIO6__FUNC_CLKM3 (MTK_PIN_NO(6) | 2) -#define MT8365_PIN_6_GPIO6__FUNC_I2S1_MCK (MTK_PIN_NO(6) | 3) -#define MT8365_PIN_6_GPIO6__FUNC_EXT_RXC (MTK_PIN_NO(6) | 4) -#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_TMS (MTK_PIN_NO(6) | 5) -#define MT8365_PIN_6_GPIO6__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(6) | 6) -#define MT8365_PIN_6_GPIO6__FUNC_DBG_MON_A6 (MTK_PIN_NO(6) | 7) - -#define MT8365_PIN_7_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) -#define MT8365_PIN_7_GPIO7__FUNC_DPI_D7 (MTK_PIN_NO(7) | 1) -#define MT8365_PIN_7_GPIO7__FUNC_I2S1_DO (MTK_PIN_NO(7) | 3) -#define MT8365_PIN_7_GPIO7__FUNC_EXT_RXDV (MTK_PIN_NO(7) | 4) -#define MT8365_PIN_7_GPIO7__FUNC_CONN_DSP_JCK (MTK_PIN_NO(7) | 5) -#define MT8365_PIN_7_GPIO7__FUNC_DBG_MON_A7 (MTK_PIN_NO(7) | 7) - -#define MT8365_PIN_8_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) -#define MT8365_PIN_8_GPIO8__FUNC_DPI_D8 (MTK_PIN_NO(8) | 1) -#define MT8365_PIN_8_GPIO8__FUNC_SPI_CLK (MTK_PIN_NO(8) | 2) -#define MT8365_PIN_8_GPIO8__FUNC_I2S0_BCK (MTK_PIN_NO(8) | 3) -#define MT8365_PIN_8_GPIO8__FUNC_EXT_RXD0 (MTK_PIN_NO(8) | 4) -#define MT8365_PIN_8_GPIO8__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(8) | 5) -#define MT8365_PIN_8_GPIO8__FUNC_DBG_MON_A8 (MTK_PIN_NO(8) | 7) - -#define MT8365_PIN_9_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) -#define MT8365_PIN_9_GPIO9__FUNC_DPI_D9 (MTK_PIN_NO(9) | 1) -#define MT8365_PIN_9_GPIO9__FUNC_SPI_CSB (MTK_PIN_NO(9) | 2) -#define MT8365_PIN_9_GPIO9__FUNC_I2S0_LRCK (MTK_PIN_NO(9) | 3) -#define MT8365_PIN_9_GPIO9__FUNC_EXT_RXD1 (MTK_PIN_NO(9) | 4) -#define MT8365_PIN_9_GPIO9__FUNC_CONN_DSP_JDI (MTK_PIN_NO(9) | 5) -#define MT8365_PIN_9_GPIO9__FUNC_DBG_MON_A9 (MTK_PIN_NO(9) | 7) - -#define MT8365_PIN_10_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) -#define MT8365_PIN_10_GPIO10__FUNC_DPI_D10 (MTK_PIN_NO(10) | 1) -#define MT8365_PIN_10_GPIO10__FUNC_SPI_MI (MTK_PIN_NO(10) | 2) -#define MT8365_PIN_10_GPIO10__FUNC_I2S0_MCK (MTK_PIN_NO(10) | 3) -#define MT8365_PIN_10_GPIO10__FUNC_EXT_RXD2 (MTK_PIN_NO(10) | 4) -#define MT8365_PIN_10_GPIO10__FUNC_CONN_DSP_JMS (MTK_PIN_NO(10) | 5) -#define MT8365_PIN_10_GPIO10__FUNC_DBG_MON_A10 (MTK_PIN_NO(10) | 7) - -#define MT8365_PIN_11_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) -#define MT8365_PIN_11_GPIO11__FUNC_DPI_D11 (MTK_PIN_NO(11) | 1) -#define MT8365_PIN_11_GPIO11__FUNC_SPI_MO (MTK_PIN_NO(11) | 2) -#define MT8365_PIN_11_GPIO11__FUNC_I2S0_DI (MTK_PIN_NO(11) | 3) -#define MT8365_PIN_11_GPIO11__FUNC_EXT_RXD3 (MTK_PIN_NO(11) | 4) -#define MT8365_PIN_11_GPIO11__FUNC_CONN_DSP_JDO (MTK_PIN_NO(11) | 5) -#define MT8365_PIN_11_GPIO11__FUNC_DBG_MON_A11 (MTK_PIN_NO(11) | 7) - -#define MT8365_PIN_12_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) -#define MT8365_PIN_12_GPIO12__FUNC_DPI_DE (MTK_PIN_NO(12) | 1) -#define MT8365_PIN_12_GPIO12__FUNC_UCTS1 (MTK_PIN_NO(12) | 2) -#define MT8365_PIN_12_GPIO12__FUNC_I2S3_BCK (MTK_PIN_NO(12) | 3) -#define MT8365_PIN_12_GPIO12__FUNC_EXT_TXEN (MTK_PIN_NO(12) | 4) -#define MT8365_PIN_12_GPIO12__FUNC_O_WIFI_TXD (MTK_PIN_NO(12) | 5) -#define MT8365_PIN_12_GPIO12__FUNC_DBG_MON_A12 (MTK_PIN_NO(12) | 7) - -#define MT8365_PIN_13_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) -#define MT8365_PIN_13_GPIO13__FUNC_DPI_VSYNC (MTK_PIN_NO(13) | 1) -#define MT8365_PIN_13_GPIO13__FUNC_URTS1 (MTK_PIN_NO(13) | 2) -#define MT8365_PIN_13_GPIO13__FUNC_I2S3_LRCK (MTK_PIN_NO(13) | 3) -#define MT8365_PIN_13_GPIO13__FUNC_EXT_COL (MTK_PIN_NO(13) | 4) -#define MT8365_PIN_13_GPIO13__FUNC_SPDIF_IN (MTK_PIN_NO(13) | 5) -#define MT8365_PIN_13_GPIO13__FUNC_DBG_MON_A13 (MTK_PIN_NO(13) | 7) - -#define MT8365_PIN_14_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) -#define MT8365_PIN_14_GPIO14__FUNC_DPI_CK (MTK_PIN_NO(14) | 1) -#define MT8365_PIN_14_GPIO14__FUNC_UCTS2 (MTK_PIN_NO(14) | 2) -#define MT8365_PIN_14_GPIO14__FUNC_I2S3_MCK (MTK_PIN_NO(14) | 3) -#define MT8365_PIN_14_GPIO14__FUNC_EXT_MDIO (MTK_PIN_NO(14) | 4) -#define MT8365_PIN_14_GPIO14__FUNC_SPDIF_OUT (MTK_PIN_NO(14) | 5) -#define MT8365_PIN_14_GPIO14__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(14) | 6) -#define MT8365_PIN_14_GPIO14__FUNC_DBG_MON_A14 (MTK_PIN_NO(14) | 7) - -#define MT8365_PIN_15_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) -#define MT8365_PIN_15_GPIO15__FUNC_DPI_HSYNC (MTK_PIN_NO(15) | 1) -#define MT8365_PIN_15_GPIO15__FUNC_URTS2 (MTK_PIN_NO(15) | 2) -#define MT8365_PIN_15_GPIO15__FUNC_I2S3_DO (MTK_PIN_NO(15) | 3) -#define MT8365_PIN_15_GPIO15__FUNC_EXT_MDC (MTK_PIN_NO(15) | 4) -#define MT8365_PIN_15_GPIO15__FUNC_IRRX (MTK_PIN_NO(15) | 5) -#define MT8365_PIN_15_GPIO15__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(15) | 6) -#define MT8365_PIN_15_GPIO15__FUNC_DBG_MON_A15 (MTK_PIN_NO(15) | 7) - -#define MT8365_PIN_16_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) -#define MT8365_PIN_16_GPIO16__FUNC_DPI_D12 (MTK_PIN_NO(16) | 1) -#define MT8365_PIN_16_GPIO16__FUNC_USB_DRVVBUS (MTK_PIN_NO(16) | 2) -#define MT8365_PIN_16_GPIO16__FUNC_PWM_A (MTK_PIN_NO(16) | 3) -#define MT8365_PIN_16_GPIO16__FUNC_CLKM0 (MTK_PIN_NO(16) | 4) -#define MT8365_PIN_16_GPIO16__FUNC_ANT_SEL0 (MTK_PIN_NO(16) | 5) -#define MT8365_PIN_16_GPIO16__FUNC_TSF_IN (MTK_PIN_NO(16) | 6) -#define MT8365_PIN_16_GPIO16__FUNC_DBG_MON_A16 (MTK_PIN_NO(16) | 7) - -#define MT8365_PIN_17_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) -#define MT8365_PIN_17_GPIO17__FUNC_DPI_D13 (MTK_PIN_NO(17) | 1) -#define MT8365_PIN_17_GPIO17__FUNC_IDDIG (MTK_PIN_NO(17) | 2) -#define MT8365_PIN_17_GPIO17__FUNC_PWM_B (MTK_PIN_NO(17) | 3) -#define MT8365_PIN_17_GPIO17__FUNC_CLKM1 (MTK_PIN_NO(17) | 4) -#define MT8365_PIN_17_GPIO17__FUNC_ANT_SEL1 (MTK_PIN_NO(17) | 5) -#define MT8365_PIN_17_GPIO17__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(17) | 6) -#define MT8365_PIN_17_GPIO17__FUNC_DBG_MON_A17 (MTK_PIN_NO(17) | 7) - -#define MT8365_PIN_18_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) -#define MT8365_PIN_18_GPIO18__FUNC_DPI_D14 (MTK_PIN_NO(18) | 1) -#define MT8365_PIN_18_GPIO18__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(18) | 2) -#define MT8365_PIN_18_GPIO18__FUNC_PWM_C (MTK_PIN_NO(18) | 3) -#define MT8365_PIN_18_GPIO18__FUNC_CLKM2 (MTK_PIN_NO(18) | 4) -#define MT8365_PIN_18_GPIO18__FUNC_ANT_SEL2 (MTK_PIN_NO(18) | 5) -#define MT8365_PIN_18_GPIO18__FUNC_MFG_TEST_CK (MTK_PIN_NO(18) | 6) -#define MT8365_PIN_18_GPIO18__FUNC_DBG_MON_A18 (MTK_PIN_NO(18) | 7) - -#define MT8365_PIN_19_DISP_PWM__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) -#define MT8365_PIN_19_DISP_PWM__FUNC_DISP_PWM (MTK_PIN_NO(19) | 1) -#define MT8365_PIN_19_DISP_PWM__FUNC_PWM_A (MTK_PIN_NO(19) | 2) -#define MT8365_PIN_19_DISP_PWM__FUNC_DBG_MON_A19 (MTK_PIN_NO(19) | 7) - -#define MT8365_PIN_20_LCM_RST__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) -#define MT8365_PIN_20_LCM_RST__FUNC_LCM_RST (MTK_PIN_NO(20) | 1) -#define MT8365_PIN_20_LCM_RST__FUNC_PWM_B (MTK_PIN_NO(20) | 2) -#define MT8365_PIN_20_LCM_RST__FUNC_DBG_MON_A20 (MTK_PIN_NO(20) | 7) - -#define MT8365_PIN_21_DSI_TE__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) -#define MT8365_PIN_21_DSI_TE__FUNC_DSI_TE (MTK_PIN_NO(21) | 1) -#define MT8365_PIN_21_DSI_TE__FUNC_PWM_C (MTK_PIN_NO(21) | 2) -#define MT8365_PIN_21_DSI_TE__FUNC_ANT_SEL0 (MTK_PIN_NO(21) | 3) -#define MT8365_PIN_21_DSI_TE__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(21) | 4) -#define MT8365_PIN_21_DSI_TE__FUNC_DBG_MON_A21 (MTK_PIN_NO(21) | 7) - -#define MT8365_PIN_22_KPROW0__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) -#define MT8365_PIN_22_KPROW0__FUNC_KPROW0 (MTK_PIN_NO(22) | 1) -#define MT8365_PIN_22_KPROW0__FUNC_DBG_MON_A22 (MTK_PIN_NO(22) | 7) - -#define MT8365_PIN_23_KPROW1__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) -#define MT8365_PIN_23_KPROW1__FUNC_KPROW1 (MTK_PIN_NO(23) | 1) -#define MT8365_PIN_23_KPROW1__FUNC_IDDIG (MTK_PIN_NO(23) | 2) -#define MT8365_PIN_23_KPROW1__FUNC_WIFI_TXD (MTK_PIN_NO(23) | 3) -#define MT8365_PIN_23_KPROW1__FUNC_CLKM3 (MTK_PIN_NO(23) | 4) -#define MT8365_PIN_23_KPROW1__FUNC_ANT_SEL1 (MTK_PIN_NO(23) | 5) -#define MT8365_PIN_23_KPROW1__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(23) | 6) -#define MT8365_PIN_23_KPROW1__FUNC_DBG_MON_B0 (MTK_PIN_NO(23) | 7) - -#define MT8365_PIN_24_KPCOL0__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) -#define MT8365_PIN_24_KPCOL0__FUNC_KPCOL0 (MTK_PIN_NO(24) | 1) -#define MT8365_PIN_24_KPCOL0__FUNC_DBG_MON_A23 (MTK_PIN_NO(24) | 7) - -#define MT8365_PIN_25_KPCOL1__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) -#define MT8365_PIN_25_KPCOL1__FUNC_KPCOL1 (MTK_PIN_NO(25) | 1) -#define MT8365_PIN_25_KPCOL1__FUNC_USB_DRVVBUS (MTK_PIN_NO(25) | 2) -#define MT8365_PIN_25_KPCOL1__FUNC_APU_JTAG_TRST (MTK_PIN_NO(25) | 3) -#define MT8365_PIN_25_KPCOL1__FUNC_UDI_NTRST_XI (MTK_PIN_NO(25) | 4) -#define MT8365_PIN_25_KPCOL1__FUNC_DFD_NTRST_XI (MTK_PIN_NO(25) | 5) -#define MT8365_PIN_25_KPCOL1__FUNC_CONN_TEST_CK (MTK_PIN_NO(25) | 6) -#define MT8365_PIN_25_KPCOL1__FUNC_DBG_MON_B1 (MTK_PIN_NO(25) | 7) - -#define MT8365_PIN_26_SPI_CS__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) -#define MT8365_PIN_26_SPI_CS__FUNC_SPI_CSB (MTK_PIN_NO(26) | 1) -#define MT8365_PIN_26_SPI_CS__FUNC_APU_JTAG_TMS (MTK_PIN_NO(26) | 3) -#define MT8365_PIN_26_SPI_CS__FUNC_UDI_TMS_XI (MTK_PIN_NO(26) | 4) -#define MT8365_PIN_26_SPI_CS__FUNC_DFD_TMS_XI (MTK_PIN_NO(26) | 5) -#define MT8365_PIN_26_SPI_CS__FUNC_CONN_TEST_CK (MTK_PIN_NO(26) | 6) -#define MT8365_PIN_26_SPI_CS__FUNC_DBG_MON_A24 (MTK_PIN_NO(26) | 7) - -#define MT8365_PIN_27_SPI_CK__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) -#define MT8365_PIN_27_SPI_CK__FUNC_SPI_CLK (MTK_PIN_NO(27) | 1) -#define MT8365_PIN_27_SPI_CK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(27) | 3) -#define MT8365_PIN_27_SPI_CK__FUNC_UDI_TCK_XI (MTK_PIN_NO(27) | 4) -#define MT8365_PIN_27_SPI_CK__FUNC_DFD_TCK_XI (MTK_PIN_NO(27) | 5) -#define MT8365_PIN_27_SPI_CK__FUNC_APU_TEST_CK (MTK_PIN_NO(27) | 6) -#define MT8365_PIN_27_SPI_CK__FUNC_DBG_MON_A25 (MTK_PIN_NO(27) | 7) - -#define MT8365_PIN_28_SPI_MI__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) -#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MI (MTK_PIN_NO(28) | 1) -#define MT8365_PIN_28_SPI_MI__FUNC_SPI_MO (MTK_PIN_NO(28) | 2) -#define MT8365_PIN_28_SPI_MI__FUNC_APU_JTAG_TDI (MTK_PIN_NO(28) | 3) -#define MT8365_PIN_28_SPI_MI__FUNC_UDI_TDI_XI (MTK_PIN_NO(28) | 4) -#define MT8365_PIN_28_SPI_MI__FUNC_DFD_TDI_XI (MTK_PIN_NO(28) | 5) -#define MT8365_PIN_28_SPI_MI__FUNC_DSP_TEST_CK (MTK_PIN_NO(28) | 6) -#define MT8365_PIN_28_SPI_MI__FUNC_DBG_MON_A26 (MTK_PIN_NO(28) | 7) - -#define MT8365_PIN_29_SPI_MO__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) -#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MO (MTK_PIN_NO(29) | 1) -#define MT8365_PIN_29_SPI_MO__FUNC_SPI_MI (MTK_PIN_NO(29) | 2) -#define MT8365_PIN_29_SPI_MO__FUNC_APU_JTAG_TDO (MTK_PIN_NO(29) | 3) -#define MT8365_PIN_29_SPI_MO__FUNC_UDI_TDO (MTK_PIN_NO(29) | 4) -#define MT8365_PIN_29_SPI_MO__FUNC_DFD_TDO (MTK_PIN_NO(29) | 5) -#define MT8365_PIN_29_SPI_MO__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(29) | 6) -#define MT8365_PIN_29_SPI_MO__FUNC_DBG_MON_A27 (MTK_PIN_NO(29) | 7) - -#define MT8365_PIN_30_JTMS__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) -#define MT8365_PIN_30_JTMS__FUNC_JTMS (MTK_PIN_NO(30) | 1) -#define MT8365_PIN_30_JTMS__FUNC_DFD_TMS_XI (MTK_PIN_NO(30) | 2) -#define MT8365_PIN_30_JTMS__FUNC_UDI_TMS_XI (MTK_PIN_NO(30) | 3) -#define MT8365_PIN_30_JTMS__FUNC_MCU_SPM_TMS (MTK_PIN_NO(30) | 4) -#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_TMS (MTK_PIN_NO(30) | 5) -#define MT8365_PIN_30_JTMS__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(30) | 6) - -#define MT8365_PIN_31_JTCK__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) -#define MT8365_PIN_31_JTCK__FUNC_JTCK (MTK_PIN_NO(31) | 1) -#define MT8365_PIN_31_JTCK__FUNC_DFD_TCK_XI (MTK_PIN_NO(31) | 2) -#define MT8365_PIN_31_JTCK__FUNC_UDI_TCK_XI (MTK_PIN_NO(31) | 3) -#define MT8365_PIN_31_JTCK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(31) | 4) -#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_TCK (MTK_PIN_NO(31) | 5) -#define MT8365_PIN_31_JTCK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(31) | 6) - -#define MT8365_PIN_32_JTDI__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) -#define MT8365_PIN_32_JTDI__FUNC_JTDI (MTK_PIN_NO(32) | 1) -#define MT8365_PIN_32_JTDI__FUNC_DFD_TDI_XI (MTK_PIN_NO(32) | 2) -#define MT8365_PIN_32_JTDI__FUNC_UDI_TDI_XI (MTK_PIN_NO(32) | 3) -#define MT8365_PIN_32_JTDI__FUNC_MCU_SPM_TDI (MTK_PIN_NO(32) | 4) -#define MT8365_PIN_32_JTDI__FUNC_CONN_MCU_TDI (MTK_PIN_NO(32) | 5) - -#define MT8365_PIN_33_JTDO__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) -#define MT8365_PIN_33_JTDO__FUNC_JTDO (MTK_PIN_NO(33) | 1) -#define MT8365_PIN_33_JTDO__FUNC_DFD_TDO (MTK_PIN_NO(33) | 2) -#define MT8365_PIN_33_JTDO__FUNC_UDI_TDO (MTK_PIN_NO(33) | 3) -#define MT8365_PIN_33_JTDO__FUNC_MCU_SPM_TDO (MTK_PIN_NO(33) | 4) -#define MT8365_PIN_33_JTDO__FUNC_CONN_MCU_TDO (MTK_PIN_NO(33) | 5) - -#define MT8365_PIN_34_JTRST__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) -#define MT8365_PIN_34_JTRST__FUNC_JTRST (MTK_PIN_NO(34) | 1) -#define MT8365_PIN_34_JTRST__FUNC_DFD_NTRST_XI (MTK_PIN_NO(34) | 2) -#define MT8365_PIN_34_JTRST__FUNC_UDI_NTRST_XI (MTK_PIN_NO(34) | 3) -#define MT8365_PIN_34_JTRST__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(34) | 4) -#define MT8365_PIN_34_JTRST__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(34) | 5) - -#define MT8365_PIN_35_URXD0__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) -#define MT8365_PIN_35_URXD0__FUNC_URXD0 (MTK_PIN_NO(35) | 1) -#define MT8365_PIN_35_URXD0__FUNC_UTXD0 (MTK_PIN_NO(35) | 2) -#define MT8365_PIN_35_URXD0__FUNC_DSP_URXD0 (MTK_PIN_NO(35) | 7) - -#define MT8365_PIN_36_UTXD0__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) -#define MT8365_PIN_36_UTXD0__FUNC_UTXD0 (MTK_PIN_NO(36) | 1) -#define MT8365_PIN_36_UTXD0__FUNC_URXD0 (MTK_PIN_NO(36) | 2) -#define MT8365_PIN_36_UTXD0__FUNC_DSP_UTXD0 (MTK_PIN_NO(36) | 7) - -#define MT8365_PIN_37_URXD1__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) -#define MT8365_PIN_37_URXD1__FUNC_URXD1 (MTK_PIN_NO(37) | 1) -#define MT8365_PIN_37_URXD1__FUNC_UTXD1 (MTK_PIN_NO(37) | 2) -#define MT8365_PIN_37_URXD1__FUNC_UCTS2 (MTK_PIN_NO(37) | 3) -#define MT8365_PIN_37_URXD1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(37) | 4) -#define MT8365_PIN_37_URXD1__FUNC_CONN_UART0_RXD (MTK_PIN_NO(37) | 5) -#define MT8365_PIN_37_URXD1__FUNC_I2S0_MCK (MTK_PIN_NO(37) | 6) -#define MT8365_PIN_37_URXD1__FUNC_DSP_URXD0 (MTK_PIN_NO(37) | 7) - -#define MT8365_PIN_38_UTXD1__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) -#define MT8365_PIN_38_UTXD1__FUNC_UTXD1 (MTK_PIN_NO(38) | 1) -#define MT8365_PIN_38_UTXD1__FUNC_URXD1 (MTK_PIN_NO(38) | 2) -#define MT8365_PIN_38_UTXD1__FUNC_URTS2 (MTK_PIN_NO(38) | 3) -#define MT8365_PIN_38_UTXD1__FUNC_ANT_SEL2 (MTK_PIN_NO(38) | 4) -#define MT8365_PIN_38_UTXD1__FUNC_CONN_UART0_TXD (MTK_PIN_NO(38) | 5) -#define MT8365_PIN_38_UTXD1__FUNC_I2S1_MCK (MTK_PIN_NO(38) | 6) -#define MT8365_PIN_38_UTXD1__FUNC_DSP_UTXD0 (MTK_PIN_NO(38) | 7) - -#define MT8365_PIN_39_URXD2__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) -#define MT8365_PIN_39_URXD2__FUNC_URXD2 (MTK_PIN_NO(39) | 1) -#define MT8365_PIN_39_URXD2__FUNC_UTXD2 (MTK_PIN_NO(39) | 2) -#define MT8365_PIN_39_URXD2__FUNC_UCTS1 (MTK_PIN_NO(39) | 3) -#define MT8365_PIN_39_URXD2__FUNC_IDDIG (MTK_PIN_NO(39) | 4) -#define MT8365_PIN_39_URXD2__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(39) | 5) -#define MT8365_PIN_39_URXD2__FUNC_I2S2_MCK (MTK_PIN_NO(39) | 6) -#define MT8365_PIN_39_URXD2__FUNC_DSP_URXD0 (MTK_PIN_NO(39) | 7) - -#define MT8365_PIN_40_UTXD2__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) -#define MT8365_PIN_40_UTXD2__FUNC_UTXD2 (MTK_PIN_NO(40) | 1) -#define MT8365_PIN_40_UTXD2__FUNC_URXD2 (MTK_PIN_NO(40) | 2) -#define MT8365_PIN_40_UTXD2__FUNC_URTS1 (MTK_PIN_NO(40) | 3) -#define MT8365_PIN_40_UTXD2__FUNC_USB_DRVVBUS (MTK_PIN_NO(40) | 4) -#define MT8365_PIN_40_UTXD2__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(40) | 5) -#define MT8365_PIN_40_UTXD2__FUNC_I2S3_MCK (MTK_PIN_NO(40) | 6) -#define MT8365_PIN_40_UTXD2__FUNC_DSP_UTXD0 (MTK_PIN_NO(40) | 7) - -#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) -#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(41) | 1) -#define MT8365_PIN_41_PWRAP_SPI0_MI__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(41) | 2) - -#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) -#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(42) | 1) -#define MT8365_PIN_42_PWRAP_SPI0_MO__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(42) | 2) - -#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) -#define MT8365_PIN_43_PWRAP_SPI0_CK__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(43) | 1) - -#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) -#define MT8365_PIN_44_PWRAP_SPI0_CSN__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(44) | 1) - -#define MT8365_PIN_45_RTC32K_CK__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) -#define MT8365_PIN_45_RTC32K_CK__FUNC_RTC32K_CK (MTK_PIN_NO(45) | 1) - -#define MT8365_PIN_46_WATCHDOG__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) -#define MT8365_PIN_46_WATCHDOG__FUNC_WATCHDOG (MTK_PIN_NO(46) | 1) - -#define MT8365_PIN_47_SRCLKENA0__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) -#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA0 (MTK_PIN_NO(47) | 1) -#define MT8365_PIN_47_SRCLKENA0__FUNC_SRCLKENA1 (MTK_PIN_NO(47) | 2) - -#define MT8365_PIN_48_SRCLKENA1__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) -#define MT8365_PIN_48_SRCLKENA1__FUNC_SRCLKENA1 (MTK_PIN_NO(48) | 1) - -#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) -#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(49) | 1) -#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_AUD_CLK_MISO (MTK_PIN_NO(49) | 2) -#define MT8365_PIN_49_AUD_CLK_MOSI__FUNC_I2S1_MCK (MTK_PIN_NO(49) | 3) - -#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) -#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(50) | 1) -#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(50) | 2) -#define MT8365_PIN_50_AUD_SYNC_MOSI__FUNC_I2S1_BCK (MTK_PIN_NO(50) | 3) - -#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) -#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(51) | 1) -#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(51) | 2) -#define MT8365_PIN_51_AUD_DAT_MOSI0__FUNC_I2S1_LRCK (MTK_PIN_NO(51) | 3) - -#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) -#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(52) | 1) -#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(52) | 2) -#define MT8365_PIN_52_AUD_DAT_MOSI1__FUNC_I2S1_DO (MTK_PIN_NO(52) | 3) - -#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) -#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MISO (MTK_PIN_NO(53) | 1) -#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(53) | 2) -#define MT8365_PIN_53_AUD_CLK_MISO__FUNC_I2S2_MCK (MTK_PIN_NO(53) | 3) - -#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) -#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(54) | 1) -#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(54) | 2) -#define MT8365_PIN_54_AUD_SYNC_MISO__FUNC_I2S2_BCK (MTK_PIN_NO(54) | 3) - -#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) -#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(55) | 1) -#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(55) | 2) -#define MT8365_PIN_55_AUD_DAT_MISO0__FUNC_I2S2_LRCK (MTK_PIN_NO(55) | 3) - -#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) -#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(56) | 1) -#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(56) | 2) -#define MT8365_PIN_56_AUD_DAT_MISO1__FUNC_I2S2_DI (MTK_PIN_NO(56) | 3) - -#define MT8365_PIN_57_SDA0__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) -#define MT8365_PIN_57_SDA0__FUNC_SDA0_0 (MTK_PIN_NO(57) | 1) - -#define MT8365_PIN_58_SCL0__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) -#define MT8365_PIN_58_SCL0__FUNC_SCL0_0 (MTK_PIN_NO(58) | 1) - -#define MT8365_PIN_59_SDA1__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) -#define MT8365_PIN_59_SDA1__FUNC_SDA1_0 (MTK_PIN_NO(59) | 1) -#define MT8365_PIN_59_SDA1__FUNC_USB_SDA (MTK_PIN_NO(59) | 6) -#define MT8365_PIN_59_SDA1__FUNC_DBG_SDA (MTK_PIN_NO(59) | 7) - -#define MT8365_PIN_60_SCL1__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) -#define MT8365_PIN_60_SCL1__FUNC_SCL1_0 (MTK_PIN_NO(60) | 1) -#define MT8365_PIN_60_SCL1__FUNC_USB_SCL (MTK_PIN_NO(60) | 6) -#define MT8365_PIN_60_SCL1__FUNC_DBG_SCL (MTK_PIN_NO(60) | 7) - -#define MT8365_PIN_61_SDA2__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) -#define MT8365_PIN_61_SDA2__FUNC_SDA2_0 (MTK_PIN_NO(61) | 1) - -#define MT8365_PIN_62_SCL2__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) -#define MT8365_PIN_62_SCL2__FUNC_SCL2_0 (MTK_PIN_NO(62) | 1) - -#define MT8365_PIN_63_SDA3__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) -#define MT8365_PIN_63_SDA3__FUNC_SDA3_0 (MTK_PIN_NO(63) | 1) - -#define MT8365_PIN_64_SCL3__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) -#define MT8365_PIN_64_SCL3__FUNC_SCL3_0 (MTK_PIN_NO(64) | 1) - -#define MT8365_PIN_65_CMMCLK0__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) -#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK0 (MTK_PIN_NO(65) | 1) -#define MT8365_PIN_65_CMMCLK0__FUNC_CMMCLK1 (MTK_PIN_NO(65) | 2) -#define MT8365_PIN_65_CMMCLK0__FUNC_DBG_MON_A28 (MTK_PIN_NO(65) | 7) - -#define MT8365_PIN_66_CMMCLK1__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) -#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK1 (MTK_PIN_NO(66) | 1) -#define MT8365_PIN_66_CMMCLK1__FUNC_CMMCLK0 (MTK_PIN_NO(66) | 2) -#define MT8365_PIN_66_CMMCLK1__FUNC_DBG_MON_B2 (MTK_PIN_NO(66) | 7) - -#define MT8365_PIN_67_CMPCLK__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) -#define MT8365_PIN_67_CMPCLK__FUNC_CMPCLK (MTK_PIN_NO(67) | 1) -#define MT8365_PIN_67_CMPCLK__FUNC_ANT_SEL0 (MTK_PIN_NO(67) | 2) -#define MT8365_PIN_67_CMPCLK__FUNC_TDM_RX_BCK (MTK_PIN_NO(67) | 4) -#define MT8365_PIN_67_CMPCLK__FUNC_I2S0_BCK (MTK_PIN_NO(67) | 5) -#define MT8365_PIN_67_CMPCLK__FUNC_DBG_MON_B3 (MTK_PIN_NO(67) | 7) - -#define MT8365_PIN_68_CMDAT0__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) -#define MT8365_PIN_68_CMDAT0__FUNC_CMDAT0 (MTK_PIN_NO(68) | 1) -#define MT8365_PIN_68_CMDAT0__FUNC_ANT_SEL1 (MTK_PIN_NO(68) | 2) -#define MT8365_PIN_68_CMDAT0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(68) | 4) -#define MT8365_PIN_68_CMDAT0__FUNC_I2S0_LRCK (MTK_PIN_NO(68) | 5) -#define MT8365_PIN_68_CMDAT0__FUNC_DBG_MON_B4 (MTK_PIN_NO(68) | 7) - -#define MT8365_PIN_69_CMDAT1__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) -#define MT8365_PIN_69_CMDAT1__FUNC_CMDAT1 (MTK_PIN_NO(69) | 1) -#define MT8365_PIN_69_CMDAT1__FUNC_ANT_SEL2 (MTK_PIN_NO(69) | 2) -#define MT8365_PIN_69_CMDAT1__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(69) | 3) -#define MT8365_PIN_69_CMDAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(69) | 4) -#define MT8365_PIN_69_CMDAT1__FUNC_I2S0_MCK (MTK_PIN_NO(69) | 5) -#define MT8365_PIN_69_CMDAT1__FUNC_DBG_MON_B5 (MTK_PIN_NO(69) | 7) - -#define MT8365_PIN_70_CMDAT2__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) -#define MT8365_PIN_70_CMDAT2__FUNC_CMDAT2 (MTK_PIN_NO(70) | 1) -#define MT8365_PIN_70_CMDAT2__FUNC_ANT_SEL3 (MTK_PIN_NO(70) | 2) -#define MT8365_PIN_70_CMDAT2__FUNC_TDM_RX_DI (MTK_PIN_NO(70) | 4) -#define MT8365_PIN_70_CMDAT2__FUNC_I2S0_DI (MTK_PIN_NO(70) | 5) -#define MT8365_PIN_70_CMDAT2__FUNC_DBG_MON_B6 (MTK_PIN_NO(70) | 7) - -#define MT8365_PIN_71_CMDAT3__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) -#define MT8365_PIN_71_CMDAT3__FUNC_CMDAT3 (MTK_PIN_NO(71) | 1) -#define MT8365_PIN_71_CMDAT3__FUNC_ANT_SEL4 (MTK_PIN_NO(71) | 2) -#define MT8365_PIN_71_CMDAT3__FUNC_DBG_MON_B7 (MTK_PIN_NO(71) | 7) - -#define MT8365_PIN_72_CMDAT4__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) -#define MT8365_PIN_72_CMDAT4__FUNC_CMDAT4 (MTK_PIN_NO(72) | 1) -#define MT8365_PIN_72_CMDAT4__FUNC_ANT_SEL5 (MTK_PIN_NO(72) | 2) -#define MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK (MTK_PIN_NO(72) | 5) -#define MT8365_PIN_72_CMDAT4__FUNC_DBG_MON_B8 (MTK_PIN_NO(72) | 7) - -#define MT8365_PIN_73_CMDAT5__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) -#define MT8365_PIN_73_CMDAT5__FUNC_CMDAT5 (MTK_PIN_NO(73) | 1) -#define MT8365_PIN_73_CMDAT5__FUNC_ANT_SEL6 (MTK_PIN_NO(73) | 2) -#define MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK (MTK_PIN_NO(73) | 5) -#define MT8365_PIN_73_CMDAT5__FUNC_DBG_MON_B9 (MTK_PIN_NO(73) | 7) - -#define MT8365_PIN_74_CMDAT6__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) -#define MT8365_PIN_74_CMDAT6__FUNC_CMDAT6 (MTK_PIN_NO(74) | 1) -#define MT8365_PIN_74_CMDAT6__FUNC_ANT_SEL7 (MTK_PIN_NO(74) | 2) -#define MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK (MTK_PIN_NO(74) | 5) -#define MT8365_PIN_74_CMDAT6__FUNC_DBG_MON_B10 (MTK_PIN_NO(74) | 7) - -#define MT8365_PIN_75_CMDAT7__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) -#define MT8365_PIN_75_CMDAT7__FUNC_CMDAT7 (MTK_PIN_NO(75) | 1) -#define MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO (MTK_PIN_NO(75) | 5) -#define MT8365_PIN_75_CMDAT7__FUNC_DBG_MON_B11 (MTK_PIN_NO(75) | 7) - -#define MT8365_PIN_76_CMDAT8__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) -#define MT8365_PIN_76_CMDAT8__FUNC_CMDAT8 (MTK_PIN_NO(76) | 1) -#define MT8365_PIN_76_CMDAT8__FUNC_PCM_CLK (MTK_PIN_NO(76) | 5) -#define MT8365_PIN_76_CMDAT8__FUNC_DBG_MON_A29 (MTK_PIN_NO(76) | 7) - -#define MT8365_PIN_77_CMDAT9__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) -#define MT8365_PIN_77_CMDAT9__FUNC_CMDAT9 (MTK_PIN_NO(77) | 1) -#define MT8365_PIN_77_CMDAT9__FUNC_PCM_SYNC (MTK_PIN_NO(77) | 5) -#define MT8365_PIN_77_CMDAT9__FUNC_DBG_MON_A30 (MTK_PIN_NO(77) | 7) - -#define MT8365_PIN_78_CMHSYNC__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) -#define MT8365_PIN_78_CMHSYNC__FUNC_CMHSYNC (MTK_PIN_NO(78) | 1) -#define MT8365_PIN_78_CMHSYNC__FUNC_PCM_RX (MTK_PIN_NO(78) | 5) -#define MT8365_PIN_78_CMHSYNC__FUNC_DBG_MON_A31 (MTK_PIN_NO(78) | 7) - -#define MT8365_PIN_79_CMVSYNC__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) -#define MT8365_PIN_79_CMVSYNC__FUNC_CMVSYNC (MTK_PIN_NO(79) | 1) -#define MT8365_PIN_79_CMVSYNC__FUNC_PCM_TX (MTK_PIN_NO(79) | 5) -#define MT8365_PIN_79_CMVSYNC__FUNC_DBG_MON_A32 (MTK_PIN_NO(79) | 7) - -#define MT8365_PIN_80_MSDC2_CMD__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) -#define MT8365_PIN_80_MSDC2_CMD__FUNC_MSDC2_CMD (MTK_PIN_NO(80) | 1) -#define MT8365_PIN_80_MSDC2_CMD__FUNC_TDM_TX_LRCK (MTK_PIN_NO(80) | 2) -#define MT8365_PIN_80_MSDC2_CMD__FUNC_UTXD1 (MTK_PIN_NO(80) | 3) -#define MT8365_PIN_80_MSDC2_CMD__FUNC_DPI_D19 (MTK_PIN_NO(80) | 4) -#define MT8365_PIN_80_MSDC2_CMD__FUNC_UDI_TMS_XI (MTK_PIN_NO(80) | 5) -#define MT8365_PIN_80_MSDC2_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(80) | 6) - -#define MT8365_PIN_81_MSDC2_CLK__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) -#define MT8365_PIN_81_MSDC2_CLK__FUNC_MSDC2_CLK (MTK_PIN_NO(81) | 1) -#define MT8365_PIN_81_MSDC2_CLK__FUNC_TDM_TX_BCK (MTK_PIN_NO(81) | 2) -#define MT8365_PIN_81_MSDC2_CLK__FUNC_URXD1 (MTK_PIN_NO(81) | 3) -#define MT8365_PIN_81_MSDC2_CLK__FUNC_DPI_D20 (MTK_PIN_NO(81) | 4) -#define MT8365_PIN_81_MSDC2_CLK__FUNC_UDI_TCK_XI (MTK_PIN_NO(81) | 5) -#define MT8365_PIN_81_MSDC2_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(81) | 6) - -#define MT8365_PIN_82_MSDC2_DAT0__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) -#define MT8365_PIN_82_MSDC2_DAT0__FUNC_MSDC2_DAT0 (MTK_PIN_NO(82) | 1) -#define MT8365_PIN_82_MSDC2_DAT0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(82) | 2) -#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UTXD2 (MTK_PIN_NO(82) | 3) -#define MT8365_PIN_82_MSDC2_DAT0__FUNC_DPI_D21 (MTK_PIN_NO(82) | 4) -#define MT8365_PIN_82_MSDC2_DAT0__FUNC_UDI_TDI_XI (MTK_PIN_NO(82) | 5) -#define MT8365_PIN_82_MSDC2_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(82) | 6) - -#define MT8365_PIN_83_MSDC2_DAT1__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) -#define MT8365_PIN_83_MSDC2_DAT1__FUNC_MSDC2_DAT1 (MTK_PIN_NO(83) | 1) -#define MT8365_PIN_83_MSDC2_DAT1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(83) | 2) -#define MT8365_PIN_83_MSDC2_DAT1__FUNC_URXD2 (MTK_PIN_NO(83) | 3) -#define MT8365_PIN_83_MSDC2_DAT1__FUNC_DPI_D22 (MTK_PIN_NO(83) | 4) -#define MT8365_PIN_83_MSDC2_DAT1__FUNC_UDI_TDO (MTK_PIN_NO(83) | 5) -#define MT8365_PIN_83_MSDC2_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(83) | 6) - -#define MT8365_PIN_84_MSDC2_DAT2__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) -#define MT8365_PIN_84_MSDC2_DAT2__FUNC_MSDC2_DAT2 (MTK_PIN_NO(84) | 1) -#define MT8365_PIN_84_MSDC2_DAT2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(84) | 2) -#define MT8365_PIN_84_MSDC2_DAT2__FUNC_PWM_A (MTK_PIN_NO(84) | 3) -#define MT8365_PIN_84_MSDC2_DAT2__FUNC_DPI_D23 (MTK_PIN_NO(84) | 4) -#define MT8365_PIN_84_MSDC2_DAT2__FUNC_UDI_NTRST_XI (MTK_PIN_NO(84) | 5) -#define MT8365_PIN_84_MSDC2_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(84) | 6) - -#define MT8365_PIN_85_MSDC2_DAT3__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) -#define MT8365_PIN_85_MSDC2_DAT3__FUNC_MSDC2_DAT3 (MTK_PIN_NO(85) | 1) -#define MT8365_PIN_85_MSDC2_DAT3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(85) | 2) -#define MT8365_PIN_85_MSDC2_DAT3__FUNC_PWM_B (MTK_PIN_NO(85) | 3) -#define MT8365_PIN_85_MSDC2_DAT3__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(85) | 5) - -#define MT8365_PIN_86_MSDC2_DSL__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) -#define MT8365_PIN_86_MSDC2_DSL__FUNC_MSDC2_DSL (MTK_PIN_NO(86) | 1) -#define MT8365_PIN_86_MSDC2_DSL__FUNC_TDM_TX_MCK (MTK_PIN_NO(86) | 2) -#define MT8365_PIN_86_MSDC2_DSL__FUNC_PWM_C (MTK_PIN_NO(86) | 3) - -#define MT8365_PIN_87_MSDC1_CMD__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) -#define MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD (MTK_PIN_NO(87) | 1) -#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(87) | 2) -#define MT8365_PIN_87_MSDC1_CMD__FUNC_DFD_TMS_XI (MTK_PIN_NO(87) | 3) -#define MT8365_PIN_87_MSDC1_CMD__FUNC_APU_JTAG_TMS (MTK_PIN_NO(87) | 4) -#define MT8365_PIN_87_MSDC1_CMD__FUNC_MCU_SPM_TMS (MTK_PIN_NO(87) | 5) -#define MT8365_PIN_87_MSDC1_CMD__FUNC_CONN_DSP_JMS (MTK_PIN_NO(87) | 6) -#define MT8365_PIN_87_MSDC1_CMD__FUNC_ADSP_JTAG_TMS (MTK_PIN_NO(87) | 7) - -#define MT8365_PIN_88_MSDC1_CLK__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) -#define MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK (MTK_PIN_NO(88) | 1) -#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(88) | 2) -#define MT8365_PIN_88_MSDC1_CLK__FUNC_DFD_TCK_XI (MTK_PIN_NO(88) | 3) -#define MT8365_PIN_88_MSDC1_CLK__FUNC_APU_JTAG_TCK (MTK_PIN_NO(88) | 4) -#define MT8365_PIN_88_MSDC1_CLK__FUNC_MCU_SPM_TCK (MTK_PIN_NO(88) | 5) -#define MT8365_PIN_88_MSDC1_CLK__FUNC_CONN_DSP_JCK (MTK_PIN_NO(88) | 6) -#define MT8365_PIN_88_MSDC1_CLK__FUNC_ADSP_JTAG_TCK (MTK_PIN_NO(88) | 7) - -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MSDC1_DAT0 (MTK_PIN_NO(89) | 1) -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_PWM_C (MTK_PIN_NO(89) | 2) -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_DFD_TDI_XI (MTK_PIN_NO(89) | 3) -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_APU_JTAG_TDI (MTK_PIN_NO(89) | 4) -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_MCU_SPM_TDI (MTK_PIN_NO(89) | 5) -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_CONN_DSP_JDI (MTK_PIN_NO(89) | 6) -#define MT8365_PIN_89_MSDC1_DAT0__FUNC_ADSP_JTAG_TDI (MTK_PIN_NO(89) | 7) - -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MSDC1_DAT1 (MTK_PIN_NO(90) | 1) -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_SPDIF_IN (MTK_PIN_NO(90) | 2) -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_DFD_TDO (MTK_PIN_NO(90) | 3) -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_APU_JTAG_TDO (MTK_PIN_NO(90) | 4) -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_MCU_SPM_TDO (MTK_PIN_NO(90) | 5) -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_CONN_DSP_JDO (MTK_PIN_NO(90) | 6) -#define MT8365_PIN_90_MSDC1_DAT1__FUNC_ADSP_JTAG_TDO (MTK_PIN_NO(90) | 7) - -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MSDC1_DAT2 (MTK_PIN_NO(91) | 1) -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_SPDIF_OUT (MTK_PIN_NO(91) | 2) -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_DFD_NTRST_XI (MTK_PIN_NO(91) | 3) -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_APU_JTAG_TRST (MTK_PIN_NO(91) | 4) -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_MCU_SPM_NTRST (MTK_PIN_NO(91) | 5) -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(91) | 6) -#define MT8365_PIN_91_MSDC1_DAT2__FUNC_ADSP_JTAG_TRST (MTK_PIN_NO(91) | 7) - -#define MT8365_PIN_92_MSDC1_DAT3__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) -#define MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3 (MTK_PIN_NO(92) | 1) -#define MT8365_PIN_92_MSDC1_DAT3__FUNC_IRRX (MTK_PIN_NO(92) | 2) -#define MT8365_PIN_92_MSDC1_DAT3__FUNC_PWM_A (MTK_PIN_NO(92) | 3) - -#define MT8365_PIN_93_MSDC0_DAT7__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) -#define MT8365_PIN_93_MSDC0_DAT7__FUNC_MSDC0_DAT7 (MTK_PIN_NO(93) | 1) -#define MT8365_PIN_93_MSDC0_DAT7__FUNC_NLD7 (MTK_PIN_NO(93) | 2) - -#define MT8365_PIN_94_MSDC0_DAT6__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) -#define MT8365_PIN_94_MSDC0_DAT6__FUNC_MSDC0_DAT6 (MTK_PIN_NO(94) | 1) -#define MT8365_PIN_94_MSDC0_DAT6__FUNC_NLD6 (MTK_PIN_NO(94) | 2) - -#define MT8365_PIN_95_MSDC0_DAT5__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) -#define MT8365_PIN_95_MSDC0_DAT5__FUNC_MSDC0_DAT5 (MTK_PIN_NO(95) | 1) -#define MT8365_PIN_95_MSDC0_DAT5__FUNC_NLD4 (MTK_PIN_NO(95) | 2) - -#define MT8365_PIN_96_MSDC0_DAT4__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) -#define MT8365_PIN_96_MSDC0_DAT4__FUNC_MSDC0_DAT4 (MTK_PIN_NO(96) | 1) -#define MT8365_PIN_96_MSDC0_DAT4__FUNC_NLD3 (MTK_PIN_NO(96) | 2) - -#define MT8365_PIN_97_MSDC0_RSTB__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) -#define MT8365_PIN_97_MSDC0_RSTB__FUNC_MSDC0_RSTB (MTK_PIN_NO(97) | 1) -#define MT8365_PIN_97_MSDC0_RSTB__FUNC_NLD0 (MTK_PIN_NO(97) | 2) - -#define MT8365_PIN_98_MSDC0_CMD__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) -#define MT8365_PIN_98_MSDC0_CMD__FUNC_MSDC0_CMD (MTK_PIN_NO(98) | 1) -#define MT8365_PIN_98_MSDC0_CMD__FUNC_NALE (MTK_PIN_NO(98) | 2) - -#define MT8365_PIN_99_MSDC0_CLK__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) -#define MT8365_PIN_99_MSDC0_CLK__FUNC_MSDC0_CLK (MTK_PIN_NO(99) | 1) -#define MT8365_PIN_99_MSDC0_CLK__FUNC_NWEB (MTK_PIN_NO(99) | 2) - -#define MT8365_PIN_100_MSDC0_DAT3__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) -#define MT8365_PIN_100_MSDC0_DAT3__FUNC_MSDC0_DAT3 (MTK_PIN_NO(100) | 1) -#define MT8365_PIN_100_MSDC0_DAT3__FUNC_NLD1 (MTK_PIN_NO(100) | 2) - -#define MT8365_PIN_101_MSDC0_DAT2__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) -#define MT8365_PIN_101_MSDC0_DAT2__FUNC_MSDC0_DAT2 (MTK_PIN_NO(101) | 1) -#define MT8365_PIN_101_MSDC0_DAT2__FUNC_NLD5 (MTK_PIN_NO(101) | 2) - -#define MT8365_PIN_102_MSDC0_DAT1__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) -#define MT8365_PIN_102_MSDC0_DAT1__FUNC_MSDC0_DAT1 (MTK_PIN_NO(102) | 1) -#define MT8365_PIN_102_MSDC0_DAT1__FUNC_NDQS (MTK_PIN_NO(102) | 2) - -#define MT8365_PIN_103_MSDC0_DAT0__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) -#define MT8365_PIN_103_MSDC0_DAT0__FUNC_MSDC0_DAT0 (MTK_PIN_NO(103) | 1) -#define MT8365_PIN_103_MSDC0_DAT0__FUNC_NLD2 (MTK_PIN_NO(103) | 2) - -#define MT8365_PIN_104_MSDC0_DSL__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) -#define MT8365_PIN_104_MSDC0_DSL__FUNC_MSDC0_DSL (MTK_PIN_NO(104) | 1) - -#define MT8365_PIN_105_NCLE__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) -#define MT8365_PIN_105_NCLE__FUNC_NCLE (MTK_PIN_NO(105) | 1) -#define MT8365_PIN_105_NCLE__FUNC_TDM_RX_MCK (MTK_PIN_NO(105) | 2) -#define MT8365_PIN_105_NCLE__FUNC_DBG_MON_B12 (MTK_PIN_NO(105) | 7) - -#define MT8365_PIN_106_NCEB1__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) -#define MT8365_PIN_106_NCEB1__FUNC_NCEB1 (MTK_PIN_NO(106) | 1) -#define MT8365_PIN_106_NCEB1__FUNC_TDM_RX_BCK (MTK_PIN_NO(106) | 2) -#define MT8365_PIN_106_NCEB1__FUNC_DBG_MON_B13 (MTK_PIN_NO(106) | 7) - -#define MT8365_PIN_107_NCEB0__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) -#define MT8365_PIN_107_NCEB0__FUNC_NCEB0 (MTK_PIN_NO(107) | 1) -#define MT8365_PIN_107_NCEB0__FUNC_TDM_RX_LRCK (MTK_PIN_NO(107) | 2) -#define MT8365_PIN_107_NCEB0__FUNC_DBG_MON_B14 (MTK_PIN_NO(107) | 7) - -#define MT8365_PIN_108_NREB__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) -#define MT8365_PIN_108_NREB__FUNC_NREB (MTK_PIN_NO(108) | 1) -#define MT8365_PIN_108_NREB__FUNC_TDM_RX_DI (MTK_PIN_NO(108) | 2) -#define MT8365_PIN_108_NREB__FUNC_DBG_MON_B15 (MTK_PIN_NO(108) | 7) - -#define MT8365_PIN_109_NRNB__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) -#define MT8365_PIN_109_NRNB__FUNC_NRNB (MTK_PIN_NO(109) | 1) -#define MT8365_PIN_109_NRNB__FUNC_TSF_IN (MTK_PIN_NO(109) | 2) -#define MT8365_PIN_109_NRNB__FUNC_DBG_MON_B16 (MTK_PIN_NO(109) | 7) - -#define MT8365_PIN_110_PCM_CLK__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) -#define MT8365_PIN_110_PCM_CLK__FUNC_PCM_CLK (MTK_PIN_NO(110) | 1) -#define MT8365_PIN_110_PCM_CLK__FUNC_I2S0_BCK (MTK_PIN_NO(110) | 2) -#define MT8365_PIN_110_PCM_CLK__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 3) -#define MT8365_PIN_110_PCM_CLK__FUNC_SPDIF_IN (MTK_PIN_NO(110) | 4) -#define MT8365_PIN_110_PCM_CLK__FUNC_DPI_D15 (MTK_PIN_NO(110) | 5) - -#define MT8365_PIN_111_PCM_SYNC__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) -#define MT8365_PIN_111_PCM_SYNC__FUNC_PCM_SYNC (MTK_PIN_NO(111) | 1) -#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S0_LRCK (MTK_PIN_NO(111) | 2) -#define MT8365_PIN_111_PCM_SYNC__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 3) -#define MT8365_PIN_111_PCM_SYNC__FUNC_SPDIF_OUT (MTK_PIN_NO(111) | 4) -#define MT8365_PIN_111_PCM_SYNC__FUNC_DPI_D16 (MTK_PIN_NO(111) | 5) - -#define MT8365_PIN_112_PCM_RX__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) -#define MT8365_PIN_112_PCM_RX__FUNC_PCM_RX (MTK_PIN_NO(112) | 1) -#define MT8365_PIN_112_PCM_RX__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2) -#define MT8365_PIN_112_PCM_RX__FUNC_I2S3_MCK (MTK_PIN_NO(112) | 3) -#define MT8365_PIN_112_PCM_RX__FUNC_IRRX (MTK_PIN_NO(112) | 4) -#define MT8365_PIN_112_PCM_RX__FUNC_DPI_D17 (MTK_PIN_NO(112) | 5) - -#define MT8365_PIN_113_PCM_TX__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) -#define MT8365_PIN_113_PCM_TX__FUNC_PCM_TX (MTK_PIN_NO(113) | 1) -#define MT8365_PIN_113_PCM_TX__FUNC_I2S0_MCK (MTK_PIN_NO(113) | 2) -#define MT8365_PIN_113_PCM_TX__FUNC_I2S3_DO (MTK_PIN_NO(113) | 3) -#define MT8365_PIN_113_PCM_TX__FUNC_PWM_B (MTK_PIN_NO(113) | 4) -#define MT8365_PIN_113_PCM_TX__FUNC_DPI_D18 (MTK_PIN_NO(113) | 5) - -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S0_DI (MTK_PIN_NO(114) | 1) -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S1_DO (MTK_PIN_NO(114) | 2) -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S2_DI (MTK_PIN_NO(114) | 3) -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_I2S3_DO (MTK_PIN_NO(114) | 4) -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_PWM_A (MTK_PIN_NO(114) | 5) -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_SPDIF_IN (MTK_PIN_NO(114) | 6) -#define MT8365_PIN_114_I2S_DATA_IN__FUNC_DBG_MON_B17 (MTK_PIN_NO(114) | 7) - -#define MT8365_PIN_115_I2S_LRCK__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) -#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S0_LRCK (MTK_PIN_NO(115) | 1) -#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S1_LRCK (MTK_PIN_NO(115) | 2) -#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S2_LRCK (MTK_PIN_NO(115) | 3) -#define MT8365_PIN_115_I2S_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(115) | 4) -#define MT8365_PIN_115_I2S_LRCK__FUNC_PWM_B (MTK_PIN_NO(115) | 5) -#define MT8365_PIN_115_I2S_LRCK__FUNC_SPDIF_OUT (MTK_PIN_NO(115) | 6) -#define MT8365_PIN_115_I2S_LRCK__FUNC_DBG_MON_B18 (MTK_PIN_NO(115) | 7) - -#define MT8365_PIN_116_I2S_BCK__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) -#define MT8365_PIN_116_I2S_BCK__FUNC_I2S0_BCK (MTK_PIN_NO(116) | 1) -#define MT8365_PIN_116_I2S_BCK__FUNC_I2S1_BCK (MTK_PIN_NO(116) | 2) -#define MT8365_PIN_116_I2S_BCK__FUNC_I2S2_BCK (MTK_PIN_NO(116) | 3) -#define MT8365_PIN_116_I2S_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(116) | 4) -#define MT8365_PIN_116_I2S_BCK__FUNC_PWM_C (MTK_PIN_NO(116) | 5) -#define MT8365_PIN_116_I2S_BCK__FUNC_IRRX (MTK_PIN_NO(116) | 6) -#define MT8365_PIN_116_I2S_BCK__FUNC_DBG_MON_B19 (MTK_PIN_NO(116) | 7) - -#define MT8365_PIN_117_DMIC0_CLK__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) -#define MT8365_PIN_117_DMIC0_CLK__FUNC_DMIC0_CLK (MTK_PIN_NO(117) | 1) -#define MT8365_PIN_117_DMIC0_CLK__FUNC_I2S2_BCK (MTK_PIN_NO(117) | 2) -#define MT8365_PIN_117_DMIC0_CLK__FUNC_DBG_MON_B20 (MTK_PIN_NO(117) | 7) - -#define MT8365_PIN_118_DMIC0_DAT0__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) -#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DMIC0_DAT0 (MTK_PIN_NO(118) | 1) -#define MT8365_PIN_118_DMIC0_DAT0__FUNC_I2S2_DI (MTK_PIN_NO(118) | 2) -#define MT8365_PIN_118_DMIC0_DAT0__FUNC_DBG_MON_B21 (MTK_PIN_NO(118) | 7) - -#define MT8365_PIN_119_DMIC0_DAT1__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) -#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DMIC0_DAT1 (MTK_PIN_NO(119) | 1) -#define MT8365_PIN_119_DMIC0_DAT1__FUNC_I2S2_LRCK (MTK_PIN_NO(119) | 2) -#define MT8365_PIN_119_DMIC0_DAT1__FUNC_DBG_MON_B22 (MTK_PIN_NO(119) | 7) - -#define MT8365_PIN_120_DMIC1_CLK__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) -#define MT8365_PIN_120_DMIC1_CLK__FUNC_DMIC1_CLK (MTK_PIN_NO(120) | 1) -#define MT8365_PIN_120_DMIC1_CLK__FUNC_I2S2_MCK (MTK_PIN_NO(120) | 2) -#define MT8365_PIN_120_DMIC1_CLK__FUNC_DBG_MON_B23 (MTK_PIN_NO(120) | 7) - -#define MT8365_PIN_121_DMIC1_DAT0__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) -#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DMIC1_DAT0 (MTK_PIN_NO(121) | 1) -#define MT8365_PIN_121_DMIC1_DAT0__FUNC_I2S1_BCK (MTK_PIN_NO(121) | 2) -#define MT8365_PIN_121_DMIC1_DAT0__FUNC_DBG_MON_B24 (MTK_PIN_NO(121) | 7) - -#define MT8365_PIN_122_DMIC1_DAT1__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) -#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DMIC1_DAT1 (MTK_PIN_NO(122) | 1) -#define MT8365_PIN_122_DMIC1_DAT1__FUNC_I2S1_LRCK (MTK_PIN_NO(122) | 2) -#define MT8365_PIN_122_DMIC1_DAT1__FUNC_DBG_MON_B25 (MTK_PIN_NO(122) | 7) - -#define MT8365_PIN_123_DMIC2_CLK__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) -#define MT8365_PIN_123_DMIC2_CLK__FUNC_DMIC2_CLK (MTK_PIN_NO(123) | 1) -#define MT8365_PIN_123_DMIC2_CLK__FUNC_I2S1_MCK (MTK_PIN_NO(123) | 2) -#define MT8365_PIN_123_DMIC2_CLK__FUNC_DBG_MON_B26 (MTK_PIN_NO(123) | 7) - -#define MT8365_PIN_124_DMIC2_DAT0__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) -#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DMIC2_DAT0 (MTK_PIN_NO(124) | 1) -#define MT8365_PIN_124_DMIC2_DAT0__FUNC_I2S1_DO (MTK_PIN_NO(124) | 2) -#define MT8365_PIN_124_DMIC2_DAT0__FUNC_DBG_MON_B27 (MTK_PIN_NO(124) | 7) - -#define MT8365_PIN_125_DMIC2_DAT1__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) -#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DMIC2_DAT1 (MTK_PIN_NO(125) | 1) -#define MT8365_PIN_125_DMIC2_DAT1__FUNC_TDM_RX_BCK (MTK_PIN_NO(125) | 2) -#define MT8365_PIN_125_DMIC2_DAT1__FUNC_DBG_MON_B28 (MTK_PIN_NO(125) | 7) - -#define MT8365_PIN_126_DMIC3_CLK__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) -#define MT8365_PIN_126_DMIC3_CLK__FUNC_DMIC3_CLK (MTK_PIN_NO(126) | 1) -#define MT8365_PIN_126_DMIC3_CLK__FUNC_TDM_RX_LRCK (MTK_PIN_NO(126) | 2) - -#define MT8365_PIN_127_DMIC3_DAT0__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) -#define MT8365_PIN_127_DMIC3_DAT0__FUNC_DMIC3_DAT0 (MTK_PIN_NO(127) | 1) -#define MT8365_PIN_127_DMIC3_DAT0__FUNC_TDM_RX_DI (MTK_PIN_NO(127) | 2) - -#define MT8365_PIN_128_DMIC3_DAT1__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) -#define MT8365_PIN_128_DMIC3_DAT1__FUNC_DMIC3_DAT1 (MTK_PIN_NO(128) | 1) -#define MT8365_PIN_128_DMIC3_DAT1__FUNC_TDM_RX_MCK (MTK_PIN_NO(128) | 2) -#define MT8365_PIN_128_DMIC3_DAT1__FUNC_VAD_CLK (MTK_PIN_NO(128) | 3) - -#define MT8365_PIN_129_TDM_TX_BCK__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) -#define MT8365_PIN_129_TDM_TX_BCK__FUNC_TDM_TX_BCK (MTK_PIN_NO(129) | 1) -#define MT8365_PIN_129_TDM_TX_BCK__FUNC_I2S3_BCK (MTK_PIN_NO(129) | 2) -#define MT8365_PIN_129_TDM_TX_BCK__FUNC_ckmon1_ck (MTK_PIN_NO(129) | 3) - -#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) -#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_TDM_TX_LRCK (MTK_PIN_NO(130) | 1) -#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_I2S3_LRCK (MTK_PIN_NO(130) | 2) -#define MT8365_PIN_130_TDM_TX_LRCK__FUNC_ckmon2_ck (MTK_PIN_NO(130) | 3) - -#define MT8365_PIN_131_TDM_TX_MCK__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) -#define MT8365_PIN_131_TDM_TX_MCK__FUNC_TDM_TX_MCK (MTK_PIN_NO(131) | 1) -#define MT8365_PIN_131_TDM_TX_MCK__FUNC_I2S3_MCK (MTK_PIN_NO(131) | 2) -#define MT8365_PIN_131_TDM_TX_MCK__FUNC_ckmon3_ck (MTK_PIN_NO(131) | 3) - -#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) -#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_TDM_TX_DATA0 (MTK_PIN_NO(132) | 1) -#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_I2S3_DO (MTK_PIN_NO(132) | 2) -#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_ckmon4_ck (MTK_PIN_NO(132) | 3) -#define MT8365_PIN_132_TDM_TX_DATA0__FUNC_DBG_MON_B29 (MTK_PIN_NO(132) | 7) - -#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) -#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_TDM_TX_DATA1 (MTK_PIN_NO(133) | 1) -#define MT8365_PIN_133_TDM_TX_DATA1__FUNC_DBG_MON_B30 (MTK_PIN_NO(133) | 7) - -#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) -#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_TDM_TX_DATA2 (MTK_PIN_NO(134) | 1) -#define MT8365_PIN_134_TDM_TX_DATA2__FUNC_DBG_MON_B31 (MTK_PIN_NO(134) | 7) - -#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) -#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_TDM_TX_DATA3 (MTK_PIN_NO(135) | 1) -#define MT8365_PIN_135_TDM_TX_DATA3__FUNC_DBG_MON_B32 (MTK_PIN_NO(135) | 7) - -#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) -#define MT8365_PIN_136_CONN_TOP_CLK__FUNC_CONN_TOP_CLK (MTK_PIN_NO(136) | 1) - -#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) -#define MT8365_PIN_137_CONN_TOP_DATA__FUNC_CONN_TOP_DATA (MTK_PIN_NO(137) | 1) - -#define MT8365_PIN_138_CONN_HRST_B__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) -#define MT8365_PIN_138_CONN_HRST_B__FUNC_CONN_HRST_B (MTK_PIN_NO(138) | 1) - -#define MT8365_PIN_139_CONN_WB_PTA__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) -#define MT8365_PIN_139_CONN_WB_PTA__FUNC_CONN_WB_PTA (MTK_PIN_NO(139) | 1) - -#define MT8365_PIN_140_CONN_BT_CLK__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) -#define MT8365_PIN_140_CONN_BT_CLK__FUNC_CONN_BT_CLK (MTK_PIN_NO(140) | 1) - -#define MT8365_PIN_141_CONN_BT_DATA__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) -#define MT8365_PIN_141_CONN_BT_DATA__FUNC_CONN_BT_DATA (MTK_PIN_NO(141) | 1) - -#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) -#define MT8365_PIN_142_CONN_WF_CTRL0__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(142) | 1) - -#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) -#define MT8365_PIN_143_CONN_WF_CTRL1__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(143) | 1) - -#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) -#define MT8365_PIN_144_CONN_WF_CTRL2__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(144) | 1) - -#endif /* __MT8365_PINFUNC_H */ diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h deleted file mode 100644 index cdb215734bd..00000000000 --- a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * MIO pin configuration defines for Xilinx ZynqMP - * - * Copyright (C) 2020 Xilinx, Inc. - */ - -#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H -#define _DT_BINDINGS_PINCTRL_ZYNQMP_H - -/* Bit value for different voltage levels */ -#define IO_STANDARD_LVCMOS33 0 -#define IO_STANDARD_LVCMOS18 1 - -/* Bit values for Slew Rates */ -#define SLEW_RATE_FAST 0 -#define SLEW_RATE_SLOW 1 - -#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */ diff --git a/include/dt-bindings/pinctrl/rzn1-pinctrl.h b/include/dt-bindings/pinctrl/rzn1-pinctrl.h deleted file mode 100644 index 21d6cc4d59f..00000000000 --- a/include/dt-bindings/pinctrl/rzn1-pinctrl.h +++ /dev/null @@ -1,141 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Defines macros and constants for Renesas RZ/N1 pin controller pin - * muxing functions. - */ -#ifndef __DT_BINDINGS_RZN1_PINCTRL_H -#define __DT_BINDINGS_RZN1_PINCTRL_H - -#define RZN1_PINMUX(_gpio, _func) \ - (((_func) << 8) | (_gpio)) - -/* - * Given the different levels of muxing on the SoC, it was decided to - * 'linearize' them into one numerical space. So mux level 1, 2 and the MDIO - * muxes are all represented by one single value. - * - * You can derive the hardware value pretty easily too, as - * 0...9 are Level 1 - * 10...71 are Level 2. The Level 2 mux will be set to this - * value - RZN1_FUNC_L2_OFFSET, and the Level 1 mux will be - * set accordingly. - * 72...103 are for the 2 MDIO muxes. - */ -#define RZN1_FUNC_HIGHZ 0 -#define RZN1_FUNC_0L 1 -#define RZN1_FUNC_CLK_ETH_MII_RGMII_RMII 2 -#define RZN1_FUNC_CLK_ETH_NAND 3 -#define RZN1_FUNC_QSPI 4 -#define RZN1_FUNC_SDIO 5 -#define RZN1_FUNC_LCD 6 -#define RZN1_FUNC_LCD_E 7 -#define RZN1_FUNC_MSEBIM 8 -#define RZN1_FUNC_MSEBIS 9 -#define RZN1_FUNC_L2_OFFSET 10 /* I'm Special */ - -#define RZN1_FUNC_HIGHZ1 (RZN1_FUNC_L2_OFFSET + 0) -#define RZN1_FUNC_ETHERCAT (RZN1_FUNC_L2_OFFSET + 1) -#define RZN1_FUNC_SERCOS3 (RZN1_FUNC_L2_OFFSET + 2) -#define RZN1_FUNC_SDIO_E (RZN1_FUNC_L2_OFFSET + 3) -#define RZN1_FUNC_ETH_MDIO (RZN1_FUNC_L2_OFFSET + 4) -#define RZN1_FUNC_ETH_MDIO_E1 (RZN1_FUNC_L2_OFFSET + 5) -#define RZN1_FUNC_USB (RZN1_FUNC_L2_OFFSET + 6) -#define RZN1_FUNC_MSEBIM_E (RZN1_FUNC_L2_OFFSET + 7) -#define RZN1_FUNC_MSEBIS_E (RZN1_FUNC_L2_OFFSET + 8) -#define RZN1_FUNC_RSV (RZN1_FUNC_L2_OFFSET + 9) -#define RZN1_FUNC_RSV_E (RZN1_FUNC_L2_OFFSET + 10) -#define RZN1_FUNC_RSV_E1 (RZN1_FUNC_L2_OFFSET + 11) -#define RZN1_FUNC_UART0_I (RZN1_FUNC_L2_OFFSET + 12) -#define RZN1_FUNC_UART0_I_E (RZN1_FUNC_L2_OFFSET + 13) -#define RZN1_FUNC_UART1_I (RZN1_FUNC_L2_OFFSET + 14) -#define RZN1_FUNC_UART1_I_E (RZN1_FUNC_L2_OFFSET + 15) -#define RZN1_FUNC_UART2_I (RZN1_FUNC_L2_OFFSET + 16) -#define RZN1_FUNC_UART2_I_E (RZN1_FUNC_L2_OFFSET + 17) -#define RZN1_FUNC_UART0 (RZN1_FUNC_L2_OFFSET + 18) -#define RZN1_FUNC_UART0_E (RZN1_FUNC_L2_OFFSET + 19) -#define RZN1_FUNC_UART1 (RZN1_FUNC_L2_OFFSET + 20) -#define RZN1_FUNC_UART1_E (RZN1_FUNC_L2_OFFSET + 21) -#define RZN1_FUNC_UART2 (RZN1_FUNC_L2_OFFSET + 22) -#define RZN1_FUNC_UART2_E (RZN1_FUNC_L2_OFFSET + 23) -#define RZN1_FUNC_UART3 (RZN1_FUNC_L2_OFFSET + 24) -#define RZN1_FUNC_UART3_E (RZN1_FUNC_L2_OFFSET + 25) -#define RZN1_FUNC_UART4 (RZN1_FUNC_L2_OFFSET + 26) -#define RZN1_FUNC_UART4_E (RZN1_FUNC_L2_OFFSET + 27) -#define RZN1_FUNC_UART5 (RZN1_FUNC_L2_OFFSET + 28) -#define RZN1_FUNC_UART5_E (RZN1_FUNC_L2_OFFSET + 29) -#define RZN1_FUNC_UART6 (RZN1_FUNC_L2_OFFSET + 30) -#define RZN1_FUNC_UART6_E (RZN1_FUNC_L2_OFFSET + 31) -#define RZN1_FUNC_UART7 (RZN1_FUNC_L2_OFFSET + 32) -#define RZN1_FUNC_UART7_E (RZN1_FUNC_L2_OFFSET + 33) -#define RZN1_FUNC_SPI0_M (RZN1_FUNC_L2_OFFSET + 34) -#define RZN1_FUNC_SPI0_M_E (RZN1_FUNC_L2_OFFSET + 35) -#define RZN1_FUNC_SPI1_M (RZN1_FUNC_L2_OFFSET + 36) -#define RZN1_FUNC_SPI1_M_E (RZN1_FUNC_L2_OFFSET + 37) -#define RZN1_FUNC_SPI2_M (RZN1_FUNC_L2_OFFSET + 38) -#define RZN1_FUNC_SPI2_M_E (RZN1_FUNC_L2_OFFSET + 39) -#define RZN1_FUNC_SPI3_M (RZN1_FUNC_L2_OFFSET + 40) -#define RZN1_FUNC_SPI3_M_E (RZN1_FUNC_L2_OFFSET + 41) -#define RZN1_FUNC_SPI4_S (RZN1_FUNC_L2_OFFSET + 42) -#define RZN1_FUNC_SPI4_S_E (RZN1_FUNC_L2_OFFSET + 43) -#define RZN1_FUNC_SPI5_S (RZN1_FUNC_L2_OFFSET + 44) -#define RZN1_FUNC_SPI5_S_E (RZN1_FUNC_L2_OFFSET + 45) -#define RZN1_FUNC_SGPIO0_M (RZN1_FUNC_L2_OFFSET + 46) -#define RZN1_FUNC_SGPIO1_M (RZN1_FUNC_L2_OFFSET + 47) -#define RZN1_FUNC_GPIO (RZN1_FUNC_L2_OFFSET + 48) -#define RZN1_FUNC_CAN (RZN1_FUNC_L2_OFFSET + 49) -#define RZN1_FUNC_I2C (RZN1_FUNC_L2_OFFSET + 50) -#define RZN1_FUNC_SAFE (RZN1_FUNC_L2_OFFSET + 51) -#define RZN1_FUNC_PTO_PWM (RZN1_FUNC_L2_OFFSET + 52) -#define RZN1_FUNC_PTO_PWM1 (RZN1_FUNC_L2_OFFSET + 53) -#define RZN1_FUNC_PTO_PWM2 (RZN1_FUNC_L2_OFFSET + 54) -#define RZN1_FUNC_PTO_PWM3 (RZN1_FUNC_L2_OFFSET + 55) -#define RZN1_FUNC_PTO_PWM4 (RZN1_FUNC_L2_OFFSET + 56) -#define RZN1_FUNC_DELTA_SIGMA (RZN1_FUNC_L2_OFFSET + 57) -#define RZN1_FUNC_SGPIO2_M (RZN1_FUNC_L2_OFFSET + 58) -#define RZN1_FUNC_SGPIO3_M (RZN1_FUNC_L2_OFFSET + 59) -#define RZN1_FUNC_SGPIO4_S (RZN1_FUNC_L2_OFFSET + 60) -#define RZN1_FUNC_MAC_MTIP_SWITCH (RZN1_FUNC_L2_OFFSET + 61) - -#define RZN1_FUNC_MDIO_OFFSET (RZN1_FUNC_L2_OFFSET + 62) - -/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO function */ -#define RZN1_FUNC_MDIO0_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 0) -#define RZN1_FUNC_MDIO0_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 1) -#define RZN1_FUNC_MDIO0_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 2) -#define RZN1_FUNC_MDIO0_ECAT (RZN1_FUNC_MDIO_OFFSET + 3) -#define RZN1_FUNC_MDIO0_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 4) -#define RZN1_FUNC_MDIO0_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 5) -#define RZN1_FUNC_MDIO0_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 6) -#define RZN1_FUNC_MDIO0_SWITCH (RZN1_FUNC_MDIO_OFFSET + 7) -/* These are MDIO0 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ -#define RZN1_FUNC_MDIO0_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 8) -#define RZN1_FUNC_MDIO0_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 9) -#define RZN1_FUNC_MDIO0_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 10) -#define RZN1_FUNC_MDIO0_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 11) -#define RZN1_FUNC_MDIO0_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 12) -#define RZN1_FUNC_MDIO0_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 13) -#define RZN1_FUNC_MDIO0_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 14) -#define RZN1_FUNC_MDIO0_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 15) - -/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO function */ -#define RZN1_FUNC_MDIO1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 16) -#define RZN1_FUNC_MDIO1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 17) -#define RZN1_FUNC_MDIO1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 18) -#define RZN1_FUNC_MDIO1_ECAT (RZN1_FUNC_MDIO_OFFSET + 19) -#define RZN1_FUNC_MDIO1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 20) -#define RZN1_FUNC_MDIO1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 21) -#define RZN1_FUNC_MDIO1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 22) -#define RZN1_FUNC_MDIO1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 23) -/* These are MDIO1 peripherals for the RZN1_FUNC_ETH_MDIO_E1 function */ -#define RZN1_FUNC_MDIO1_E1_HIGHZ (RZN1_FUNC_MDIO_OFFSET + 24) -#define RZN1_FUNC_MDIO1_E1_GMAC0 (RZN1_FUNC_MDIO_OFFSET + 25) -#define RZN1_FUNC_MDIO1_E1_GMAC1 (RZN1_FUNC_MDIO_OFFSET + 26) -#define RZN1_FUNC_MDIO1_E1_ECAT (RZN1_FUNC_MDIO_OFFSET + 27) -#define RZN1_FUNC_MDIO1_E1_S3_MDIO0 (RZN1_FUNC_MDIO_OFFSET + 28) -#define RZN1_FUNC_MDIO1_E1_S3_MDIO1 (RZN1_FUNC_MDIO_OFFSET + 29) -#define RZN1_FUNC_MDIO1_E1_HWRTOS (RZN1_FUNC_MDIO_OFFSET + 30) -#define RZN1_FUNC_MDIO1_E1_SWITCH (RZN1_FUNC_MDIO_OFFSET + 31) - -#define RZN1_FUNC_MAX (RZN1_FUNC_MDIO_OFFSET + 32) - -#endif /* __DT_BINDINGS_RZN1_PINCTRL_H */ diff --git a/include/dt-bindings/pinctrl/sun4i-a10.h b/include/dt-bindings/pinctrl/sun4i-a10.h deleted file mode 100644 index f7553c143b4..00000000000 --- a/include/dt-bindings/pinctrl/sun4i-a10.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2014 Maxime Ripard - * - * Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ -#define __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ - -#define SUN4I_PINCTRL_10_MA 0 -#define SUN4I_PINCTRL_20_MA 1 -#define SUN4I_PINCTRL_30_MA 2 -#define SUN4I_PINCTRL_40_MA 3 - -#define SUN4I_PINCTRL_NO_PULL 0 -#define SUN4I_PINCTRL_PULL_UP 1 -#define SUN4I_PINCTRL_PULL_DOWN 2 - -#endif /* __DT_BINDINGS_PINCTRL_SUN4I_A10_H_ */ diff --git a/include/dt-bindings/power/mediatek,mt8365-power.h b/include/dt-bindings/power/mediatek,mt8365-power.h deleted file mode 100644 index e6cfd0ec787..00000000000 --- a/include/dt-bindings/power/mediatek,mt8365-power.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ -/* - * Copyright (c) 2022 MediaTek Inc. - */ - -#ifndef _DT_BINDINGS_POWER_MT8365_POWER_H -#define _DT_BINDINGS_POWER_MT8365_POWER_H - -#define MT8365_POWER_DOMAIN_MM 0 -#define MT8365_POWER_DOMAIN_CONN 1 -#define MT8365_POWER_DOMAIN_MFG 2 -#define MT8365_POWER_DOMAIN_AUDIO 3 -#define MT8365_POWER_DOMAIN_CAM 4 -#define MT8365_POWER_DOMAIN_DSP 5 -#define MT8365_POWER_DOMAIN_VDEC 6 -#define MT8365_POWER_DOMAIN_VENC 7 -#define MT8365_POWER_DOMAIN_APU 8 - -#endif /* _DT_BINDINGS_POWER_MT8365_POWER_H */ diff --git a/include/dt-bindings/power/owl-s700-powergate.h b/include/dt-bindings/power/owl-s700-powergate.h deleted file mode 100644 index 4cf1aefbf09..00000000000 --- a/include/dt-bindings/power/owl-s700-powergate.h +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Actions Semi S700 SPS - * - * Copyright (c) 2017 Andreas Färber - */ -#ifndef DT_BINDINGS_POWER_OWL_S700_POWERGATE_H -#define DT_BINDINGS_POWER_OWL_S700_POWERGATE_H - -#define S700_PD_VDE 0 -#define S700_PD_VCE_SI 1 -#define S700_PD_USB2_1 2 -#define S700_PD_HDE 3 -#define S700_PD_DMA 4 -#define S700_PD_DS 5 -#define S700_PD_USB3 6 -#define S700_PD_USB2_0 7 - -#endif diff --git a/include/dt-bindings/power/rk3228-power.h b/include/dt-bindings/power/rk3228-power.h deleted file mode 100644 index 6a8dc1bf76c..00000000000 --- a/include/dt-bindings/power/rk3228-power.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_POWER_RK3228_POWER_H__ -#define __DT_BINDINGS_POWER_RK3228_POWER_H__ - -/** - * RK3228 idle id Summary. - */ - -#define RK3228_PD_CORE 0 -#define RK3228_PD_MSCH 1 -#define RK3228_PD_BUS 2 -#define RK3228_PD_SYS 3 -#define RK3228_PD_VIO 4 -#define RK3228_PD_VOP 5 -#define RK3228_PD_VPU 6 -#define RK3228_PD_RKVDEC 7 -#define RK3228_PD_GPU 8 -#define RK3228_PD_PERI 9 -#define RK3228_PD_GMAC 10 - -#endif diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h deleted file mode 100644 index 618024cbb20..00000000000 --- a/include/dt-bindings/power/xlnx-zynqmp-power.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Xilinx, Inc. - */ - -#ifndef _DT_BINDINGS_ZYNQMP_POWER_H -#define _DT_BINDINGS_ZYNQMP_POWER_H - -#define PD_RPU_0 7 -#define PD_RPU_1 8 -#define PD_R5_0_ATCM 15 -#define PD_R5_0_BTCM 16 -#define PD_R5_1_ATCM 17 -#define PD_R5_1_BTCM 18 -#define PD_USB_0 22 -#define PD_USB_1 23 -#define PD_TTC_0 24 -#define PD_TTC_1 25 -#define PD_TTC_2 26 -#define PD_TTC_3 27 -#define PD_SATA 28 -#define PD_ETH_0 29 -#define PD_ETH_1 30 -#define PD_ETH_2 31 -#define PD_ETH_3 32 -#define PD_UART_0 33 -#define PD_UART_1 34 -#define PD_SPI_0 35 -#define PD_SPI_1 36 -#define PD_I2C_0 37 -#define PD_I2C_1 38 -#define PD_SD_0 39 -#define PD_SD_1 40 -#define PD_DP 41 -#define PD_GDMA 42 -#define PD_ADMA 43 -#define PD_NAND 44 -#define PD_QSPI 45 -#define PD_GPIO 46 -#define PD_CAN_0 47 -#define PD_CAN_1 48 -#define PD_GPU 58 -#define PD_PCIE 59 - -#endif diff --git a/include/dt-bindings/regulator/dlg,da9063-regulator.h b/include/dt-bindings/regulator/dlg,da9063-regulator.h deleted file mode 100644 index 1de710dd089..00000000000 --- a/include/dt-bindings/regulator/dlg,da9063-regulator.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef _DT_BINDINGS_REGULATOR_DLG_DA9063_H -#define _DT_BINDINGS_REGULATOR_DLG_DA9063_H - -/* - * These buck mode constants may be used to specify values in device tree - * properties (e.g. regulator-initial-mode). - * A description of the following modes is in the manufacturers datasheet. - */ - -#define DA9063_BUCK_MODE_SLEEP 1 -#define DA9063_BUCK_MODE_SYNC 2 -#define DA9063_BUCK_MODE_AUTO 3 - -#endif diff --git a/include/dt-bindings/reset/actions,s700-reset.h b/include/dt-bindings/reset/actions,s700-reset.h deleted file mode 100644 index 5e3b16b8ef5..00000000000 --- a/include/dt-bindings/reset/actions,s700-reset.h +++ /dev/null @@ -1,34 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -// -// Device Tree binding constants for Actions Semi S700 Reset Management Unit -// -// Copyright (c) 2018 Linaro Ltd. - -#ifndef __DT_BINDINGS_ACTIONS_S700_RESET_H -#define __DT_BINDINGS_ACTIONS_S700_RESET_H - -#define RESET_AUDIO 0 -#define RESET_CSI 1 -#define RESET_DE 2 -#define RESET_DSI 3 -#define RESET_GPIO 4 -#define RESET_I2C0 5 -#define RESET_I2C1 6 -#define RESET_I2C2 7 -#define RESET_I2C3 8 -#define RESET_KEY 9 -#define RESET_LCD0 10 -#define RESET_SI 11 -#define RESET_SPI0 12 -#define RESET_SPI1 13 -#define RESET_SPI2 14 -#define RESET_SPI3 15 -#define RESET_UART0 16 -#define RESET_UART1 17 -#define RESET_UART2 18 -#define RESET_UART3 19 -#define RESET_UART4 20 -#define RESET_UART5 21 -#define RESET_UART6 22 - -#endif /* __DT_BINDINGS_ACTIONS_S700_RESET_H */ diff --git a/include/dt-bindings/reset/actions,s900-reset.h b/include/dt-bindings/reset/actions,s900-reset.h deleted file mode 100644 index 42c19d02e43..00000000000 --- a/include/dt-bindings/reset/actions,s900-reset.h +++ /dev/null @@ -1,65 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) -// -// Device Tree binding constants for Actions Semi S900 Reset Management Unit -// -// Copyright (c) 2018 Linaro Ltd. - -#ifndef __DT_BINDINGS_ACTIONS_S900_RESET_H -#define __DT_BINDINGS_ACTIONS_S900_RESET_H - -#define RESET_CHIPID 0 -#define RESET_CPU_SCNT 1 -#define RESET_SRAMI 2 -#define RESET_DDR_CTL_PHY 3 -#define RESET_DMAC 4 -#define RESET_GPIO 5 -#define RESET_BISP_AXI 6 -#define RESET_CSI0 7 -#define RESET_CSI1 8 -#define RESET_DE 9 -#define RESET_DSI 10 -#define RESET_GPU3D_PA 11 -#define RESET_GPU3D_PB 12 -#define RESET_HDE 13 -#define RESET_I2C0 14 -#define RESET_I2C1 15 -#define RESET_I2C2 16 -#define RESET_I2C3 17 -#define RESET_I2C4 18 -#define RESET_I2C5 19 -#define RESET_IMX 20 -#define RESET_NANDC0 21 -#define RESET_NANDC1 22 -#define RESET_SD0 23 -#define RESET_SD1 24 -#define RESET_SD2 25 -#define RESET_SD3 26 -#define RESET_SPI0 27 -#define RESET_SPI1 28 -#define RESET_SPI2 29 -#define RESET_SPI3 30 -#define RESET_UART0 31 -#define RESET_UART1 32 -#define RESET_UART2 33 -#define RESET_UART3 34 -#define RESET_UART4 35 -#define RESET_UART5 36 -#define RESET_UART6 37 -#define RESET_HDMI 38 -#define RESET_LVDS 39 -#define RESET_EDP 40 -#define RESET_USB2HUB 41 -#define RESET_USB2HSIC 42 -#define RESET_USB3 43 -#define RESET_PCM1 44 -#define RESET_AUDIO 45 -#define RESET_PCM0 46 -#define RESET_SE 47 -#define RESET_GIC 48 -#define RESET_DDR_CTL_PHY_AXI 49 -#define RESET_CMU_DDR 50 -#define RESET_DMM 51 -#define RESET_HDCP2TX 52 -#define RESET_ETHERNET 53 - -#endif /* __DT_BINDINGS_ACTIONS_S900_RESET_H */ diff --git a/include/dt-bindings/reset/raspberrypi,firmware-reset.h b/include/dt-bindings/reset/raspberrypi,firmware-reset.h deleted file mode 100644 index 1a4f4c79272..00000000000 --- a/include/dt-bindings/reset/raspberrypi,firmware-reset.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2020 Nicolas Saenz Julienne - * Author: Nicolas Saenz Julienne - */ - -#ifndef _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H -#define _DT_BINDINGS_RASPBERRYPI_FIRMWARE_RESET_H - -#define RASPBERRYPI_FIRMWARE_RESET_ID_USB 0 -#define RASPBERRYPI_FIRMWARE_RESET_NUM_IDS 1 - -#endif diff --git a/include/dt-bindings/reset/sama7g5-reset.h b/include/dt-bindings/reset/sama7g5-reset.h deleted file mode 100644 index 2116f41d04e..00000000000 --- a/include/dt-bindings/reset/sama7g5-reset.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ - -#ifndef __DT_BINDINGS_RESET_SAMA7G5_H -#define __DT_BINDINGS_RESET_SAMA7G5_H - -#define SAMA7G5_RESET_USB_PHY1 4 -#define SAMA7G5_RESET_USB_PHY2 5 -#define SAMA7G5_RESET_USB_PHY3 6 - -#endif /* __DT_BINDINGS_RESET_SAMA7G5_H */ diff --git a/include/dt-bindings/reset/snps,hsdk-reset.h b/include/dt-bindings/reset/snps,hsdk-reset.h deleted file mode 100644 index e1a643e4bc9..00000000000 --- a/include/dt-bindings/reset/snps,hsdk-reset.h +++ /dev/null @@ -1,17 +0,0 @@ -/** - * This header provides index for the HSDK reset controller. - */ -#ifndef _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK -#define _DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK - -#define HSDK_APB_RESET 0 -#define HSDK_AXI_RESET 1 -#define HSDK_ETH_RESET 2 -#define HSDK_USB_RESET 3 -#define HSDK_SDIO_RESET 4 -#define HSDK_HDMI_RESET 5 -#define HSDK_GFX_RESET 6 -#define HSDK_DMAC_RESET 7 -#define HSDK_EBI_RESET 8 - -#endif /*_DT_BINDINGS_RESET_CONTROLLER_SNPS_HSDK*/ diff --git a/include/dt-bindings/reset/sun20i-d1-ccu.h b/include/dt-bindings/reset/sun20i-d1-ccu.h deleted file mode 100644 index 79e52aca591..00000000000 --- a/include/dt-bindings/reset/sun20i-d1-ccu.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2020 huangzhenwei@allwinnertech.com - * Copyright (C) 2021 Samuel Holland - */ - -#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ -#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ - -#define RST_MBUS 0 -#define RST_BUS_DE 1 -#define RST_BUS_DI 2 -#define RST_BUS_G2D 3 -#define RST_BUS_CE 4 -#define RST_BUS_VE 5 -#define RST_BUS_DMA 6 -#define RST_BUS_MSGBOX0 7 -#define RST_BUS_MSGBOX1 8 -#define RST_BUS_MSGBOX2 9 -#define RST_BUS_SPINLOCK 10 -#define RST_BUS_HSTIMER 11 -#define RST_BUS_DBG 12 -#define RST_BUS_PWM 13 -#define RST_BUS_DRAM 14 -#define RST_BUS_MMC0 15 -#define RST_BUS_MMC1 16 -#define RST_BUS_MMC2 17 -#define RST_BUS_UART0 18 -#define RST_BUS_UART1 19 -#define RST_BUS_UART2 20 -#define RST_BUS_UART3 21 -#define RST_BUS_UART4 22 -#define RST_BUS_UART5 23 -#define RST_BUS_I2C0 24 -#define RST_BUS_I2C1 25 -#define RST_BUS_I2C2 26 -#define RST_BUS_I2C3 27 -#define RST_BUS_SPI0 28 -#define RST_BUS_SPI1 29 -#define RST_BUS_EMAC 30 -#define RST_BUS_IR_TX 31 -#define RST_BUS_GPADC 32 -#define RST_BUS_THS 33 -#define RST_BUS_I2S0 34 -#define RST_BUS_I2S1 35 -#define RST_BUS_I2S2 36 -#define RST_BUS_SPDIF 37 -#define RST_BUS_DMIC 38 -#define RST_BUS_AUDIO 39 -#define RST_USB_PHY0 40 -#define RST_USB_PHY1 41 -#define RST_BUS_OHCI0 42 -#define RST_BUS_OHCI1 43 -#define RST_BUS_EHCI0 44 -#define RST_BUS_EHCI1 45 -#define RST_BUS_OTG 46 -#define RST_BUS_LRADC 47 -#define RST_BUS_DPSS_TOP 48 -#define RST_BUS_HDMI_SUB 49 -#define RST_BUS_HDMI_MAIN 50 -#define RST_BUS_MIPI_DSI 51 -#define RST_BUS_TCON_LCD0 52 -#define RST_BUS_TCON_TV 53 -#define RST_BUS_LVDS0 54 -#define RST_BUS_TVE 55 -#define RST_BUS_TVE_TOP 56 -#define RST_BUS_TVD 57 -#define RST_BUS_TVD_TOP 58 -#define RST_BUS_LEDC 59 -#define RST_BUS_CSI 60 -#define RST_BUS_TPADC 61 -#define RST_DSP 62 -#define RST_BUS_DSP_CFG 63 -#define RST_BUS_DSP_DBG 64 -#define RST_BUS_RISCV_CFG 65 -#define RST_BUS_CAN0 66 -#define RST_BUS_CAN1 67 - -#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun20i-d1-r-ccu.h b/include/dt-bindings/reset/sun20i-d1-r-ccu.h deleted file mode 100644 index e20babc990a..00000000000 --- a/include/dt-bindings/reset/sun20i-d1-r-ccu.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2021 Samuel Holland - */ - -#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ -#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ - -#define RST_BUS_R_TIMER 0 -#define RST_BUS_R_TWD 1 -#define RST_BUS_R_PPU 2 -#define RST_BUS_R_IR_RX 3 -#define RST_BUS_R_RTC 4 -#define RST_BUS_R_CPUCFG 5 - -#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun4i-a10-ccu.h b/include/dt-bindings/reset/sun4i-a10-ccu.h deleted file mode 100644 index 5f4480bedc8..00000000000 --- a/include/dt-bindings/reset/sun4i-a10-ccu.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (C) 2017 Priit Laes - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN4I_A10_H -#define _DT_BINDINGS_RST_SUN4I_A10_H - -#define RST_USB_PHY0 1 -#define RST_USB_PHY1 2 -#define RST_USB_PHY2 3 -#define RST_GPS 4 -#define RST_DE_BE0 5 -#define RST_DE_BE1 6 -#define RST_DE_FE0 7 -#define RST_DE_FE1 8 -#define RST_DE_MP 9 -#define RST_TVE0 10 -#define RST_TCON0 11 -#define RST_TVE1 12 -#define RST_TCON1 13 -#define RST_CSI0 14 -#define RST_CSI1 15 -#define RST_VE 16 -#define RST_ACE 17 -#define RST_LVDS 18 -#define RST_GPU 19 -#define RST_HDMI_H 20 -#define RST_HDMI_SYS 21 -#define RST_HDMI_AUDIO_DMA 22 - -#endif /* DT_BINDINGS_RST_SUN4I_A10_H */ diff --git a/include/dt-bindings/reset/sun50i-a64-ccu.h b/include/dt-bindings/reset/sun50i-a64-ccu.h deleted file mode 100644 index db60b29ddb1..00000000000 --- a/include/dt-bindings/reset/sun50i-a64-ccu.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN50I_A64_H_ -#define _DT_BINDINGS_RST_SUN50I_A64_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_HSIC 2 -#define RST_DRAM 3 -#define RST_MBUS 4 -#define RST_BUS_MIPI_DSI 5 -#define RST_BUS_CE 6 -#define RST_BUS_DMA 7 -#define RST_BUS_MMC0 8 -#define RST_BUS_MMC1 9 -#define RST_BUS_MMC2 10 -#define RST_BUS_NAND 11 -#define RST_BUS_DRAM 12 -#define RST_BUS_EMAC 13 -#define RST_BUS_TS 14 -#define RST_BUS_HSTIMER 15 -#define RST_BUS_SPI0 16 -#define RST_BUS_SPI1 17 -#define RST_BUS_OTG 18 -#define RST_BUS_EHCI0 19 -#define RST_BUS_EHCI1 20 -#define RST_BUS_OHCI0 21 -#define RST_BUS_OHCI1 22 -#define RST_BUS_VE 23 -#define RST_BUS_TCON0 24 -#define RST_BUS_TCON1 25 -#define RST_BUS_DEINTERLACE 26 -#define RST_BUS_CSI 27 -#define RST_BUS_HDMI0 28 -#define RST_BUS_HDMI1 29 -#define RST_BUS_DE 30 -#define RST_BUS_GPU 31 -#define RST_BUS_MSGBOX 32 -#define RST_BUS_SPINLOCK 33 -#define RST_BUS_DBG 34 -#define RST_BUS_LVDS 35 -#define RST_BUS_CODEC 36 -#define RST_BUS_SPDIF 37 -#define RST_BUS_THS 38 -#define RST_BUS_I2S0 39 -#define RST_BUS_I2S1 40 -#define RST_BUS_I2S2 41 -#define RST_BUS_I2C0 42 -#define RST_BUS_I2C1 43 -#define RST_BUS_I2C2 44 -#define RST_BUS_SCR 45 -#define RST_BUS_UART0 46 -#define RST_BUS_UART1 47 -#define RST_BUS_UART2 48 -#define RST_BUS_UART3 49 -#define RST_BUS_UART4 50 - -#endif /* _DT_BINDINGS_RST_SUN50I_A64_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h6-ccu.h b/include/dt-bindings/reset/sun50i-h6-ccu.h deleted file mode 100644 index d038ddfa481..00000000000 --- a/include/dt-bindings/reset/sun50i-h6-ccu.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2017 Icenowy Zheng - */ - -#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_ -#define _DT_BINDINGS_RESET_SUN50I_H6_H_ - -#define RST_MBUS 0 -#define RST_BUS_DE 1 -#define RST_BUS_DEINTERLACE 2 -#define RST_BUS_GPU 3 -#define RST_BUS_CE 4 -#define RST_BUS_VE 5 -#define RST_BUS_EMCE 6 -#define RST_BUS_VP9 7 -#define RST_BUS_DMA 8 -#define RST_BUS_MSGBOX 9 -#define RST_BUS_SPINLOCK 10 -#define RST_BUS_HSTIMER 11 -#define RST_BUS_DBG 12 -#define RST_BUS_PSI 13 -#define RST_BUS_PWM 14 -#define RST_BUS_IOMMU 15 -#define RST_BUS_DRAM 16 -#define RST_BUS_NAND 17 -#define RST_BUS_MMC0 18 -#define RST_BUS_MMC1 19 -#define RST_BUS_MMC2 20 -#define RST_BUS_UART0 21 -#define RST_BUS_UART1 22 -#define RST_BUS_UART2 23 -#define RST_BUS_UART3 24 -#define RST_BUS_I2C0 25 -#define RST_BUS_I2C1 26 -#define RST_BUS_I2C2 27 -#define RST_BUS_I2C3 28 -#define RST_BUS_SCR0 29 -#define RST_BUS_SCR1 30 -#define RST_BUS_SPI0 31 -#define RST_BUS_SPI1 32 -#define RST_BUS_EMAC 33 -#define RST_BUS_TS 34 -#define RST_BUS_IR_TX 35 -#define RST_BUS_THS 36 -#define RST_BUS_I2S0 37 -#define RST_BUS_I2S1 38 -#define RST_BUS_I2S2 39 -#define RST_BUS_I2S3 40 -#define RST_BUS_SPDIF 41 -#define RST_BUS_DMIC 42 -#define RST_BUS_AUDIO_HUB 43 -#define RST_USB_PHY0 44 -#define RST_USB_PHY1 45 -#define RST_USB_PHY3 46 -#define RST_USB_HSIC 47 -#define RST_BUS_OHCI0 48 -#define RST_BUS_OHCI3 49 -#define RST_BUS_EHCI0 50 -#define RST_BUS_XHCI 51 -#define RST_BUS_EHCI3 52 -#define RST_BUS_OTG 53 -#define RST_BUS_PCIE 54 -#define RST_PCIE_POWERUP 55 -#define RST_BUS_HDMI 56 -#define RST_BUS_HDMI_SUB 57 -#define RST_BUS_TCON_TOP 58 -#define RST_BUS_TCON_LCD0 59 -#define RST_BUS_TCON_TV0 60 -#define RST_BUS_CSI 61 -#define RST_BUS_HDCP 62 - -#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */ diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h deleted file mode 100644 index d541ade884f..00000000000 --- a/include/dt-bindings/reset/sun50i-h6-r-ccu.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (C) 2016 Icenowy Zheng - */ - -#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ -#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ - -#define RST_R_APB1_TIMER 0 -#define RST_R_APB1_TWD 1 -#define RST_R_APB1_PWM 2 -#define RST_R_APB2_UART 3 -#define RST_R_APB2_I2C 4 -#define RST_R_APB1_IR 5 -#define RST_R_APB1_W1 6 -#define RST_R_APB2_RSB 7 - -#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun5i-ccu.h b/include/dt-bindings/reset/sun5i-ccu.h deleted file mode 100644 index 40cc22ae763..00000000000 --- a/include/dt-bindings/reset/sun5i-ccu.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright 2016 Maxime Ripard - * - * Maxime Ripard - */ - -#ifndef _RST_SUN5I_H_ -#define _RST_SUN5I_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_GPS 2 -#define RST_DE_BE 3 -#define RST_DE_FE 4 -#define RST_TVE 5 -#define RST_LCD 6 -#define RST_CSI 7 -#define RST_VE 8 -#define RST_GPU 9 -#define RST_IEP 10 - -#endif /* _RST_SUN5I_H_ */ diff --git a/include/dt-bindings/reset/sun6i-a31-ccu.h b/include/dt-bindings/reset/sun6i-a31-ccu.h deleted file mode 100644 index fbff365ed6e..00000000000 --- a/include/dt-bindings/reset/sun6i-a31-ccu.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN6I_A31_H_ -#define _DT_BINDINGS_RST_SUN6I_A31_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_PHY2 2 - -#define RST_AHB1_MIPI_DSI 3 -#define RST_AHB1_SS 4 -#define RST_AHB1_DMA 5 -#define RST_AHB1_MMC0 6 -#define RST_AHB1_MMC1 7 -#define RST_AHB1_MMC2 8 -#define RST_AHB1_MMC3 9 -#define RST_AHB1_NAND1 10 -#define RST_AHB1_NAND0 11 -#define RST_AHB1_SDRAM 12 -#define RST_AHB1_EMAC 13 -#define RST_AHB1_TS 14 -#define RST_AHB1_HSTIMER 15 -#define RST_AHB1_SPI0 16 -#define RST_AHB1_SPI1 17 -#define RST_AHB1_SPI2 18 -#define RST_AHB1_SPI3 19 -#define RST_AHB1_OTG 20 -#define RST_AHB1_EHCI0 21 -#define RST_AHB1_EHCI1 22 -#define RST_AHB1_OHCI0 23 -#define RST_AHB1_OHCI1 24 -#define RST_AHB1_OHCI2 25 -#define RST_AHB1_VE 26 -#define RST_AHB1_LCD0 27 -#define RST_AHB1_LCD1 28 -#define RST_AHB1_CSI 29 -#define RST_AHB1_HDMI 30 -#define RST_AHB1_BE0 31 -#define RST_AHB1_BE1 32 -#define RST_AHB1_FE0 33 -#define RST_AHB1_FE1 34 -#define RST_AHB1_MP 35 -#define RST_AHB1_GPU 36 -#define RST_AHB1_DEU0 37 -#define RST_AHB1_DEU1 38 -#define RST_AHB1_DRC0 39 -#define RST_AHB1_DRC1 40 -#define RST_AHB1_LVDS 41 - -#define RST_APB1_CODEC 42 -#define RST_APB1_SPDIF 43 -#define RST_APB1_DIGITAL_MIC 44 -#define RST_APB1_DAUDIO0 45 -#define RST_APB1_DAUDIO1 46 -#define RST_APB2_I2C0 47 -#define RST_APB2_I2C1 48 -#define RST_APB2_I2C2 49 -#define RST_APB2_I2C3 50 -#define RST_APB2_UART0 51 -#define RST_APB2_UART1 52 -#define RST_APB2_UART2 53 -#define RST_APB2_UART3 54 -#define RST_APB2_UART4 55 -#define RST_APB2_UART5 56 - -#endif /* _DT_BINDINGS_RST_SUN6I_A31_H_ */ diff --git a/include/dt-bindings/reset/sun8i-a23-a33-ccu.h b/include/dt-bindings/reset/sun8i-a23-a33-ccu.h deleted file mode 100644 index 6121f2b0cd0..00000000000 --- a/include/dt-bindings/reset/sun8i-a23-a33-ccu.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_A23_A33_H_ -#define _DT_BINDINGS_RST_SUN8I_A23_A33_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_HSIC 2 -#define RST_MBUS 3 -#define RST_BUS_MIPI_DSI 4 -#define RST_BUS_SS 5 -#define RST_BUS_DMA 6 -#define RST_BUS_MMC0 7 -#define RST_BUS_MMC1 8 -#define RST_BUS_MMC2 9 -#define RST_BUS_NAND 10 -#define RST_BUS_DRAM 11 -#define RST_BUS_HSTIMER 12 -#define RST_BUS_SPI0 13 -#define RST_BUS_SPI1 14 -#define RST_BUS_OTG 15 -#define RST_BUS_EHCI 16 -#define RST_BUS_OHCI 17 -#define RST_BUS_VE 18 -#define RST_BUS_LCD 19 -#define RST_BUS_CSI 20 -#define RST_BUS_DE_BE 21 -#define RST_BUS_DE_FE 22 -#define RST_BUS_GPU 23 -#define RST_BUS_MSGBOX 24 -#define RST_BUS_SPINLOCK 25 -#define RST_BUS_DRC 26 -#define RST_BUS_SAT 27 -#define RST_BUS_LVDS 28 -#define RST_BUS_CODEC 29 -#define RST_BUS_I2S0 30 -#define RST_BUS_I2S1 31 -#define RST_BUS_I2C0 32 -#define RST_BUS_I2C1 33 -#define RST_BUS_I2C2 34 -#define RST_BUS_UART0 35 -#define RST_BUS_UART1 36 -#define RST_BUS_UART2 37 -#define RST_BUS_UART3 38 -#define RST_BUS_UART4 39 - -#endif /* _DT_BINDINGS_RST_SUN8I_A23_A33_H_ */ diff --git a/include/dt-bindings/reset/sun8i-a83t-ccu.h b/include/dt-bindings/reset/sun8i-a83t-ccu.h deleted file mode 100644 index 784f6e11664..00000000000 --- a/include/dt-bindings/reset/sun8i-a83t-ccu.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (C) 2017 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ -#define _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_HSIC 2 - -#define RST_DRAM 3 -#define RST_MBUS 4 - -#define RST_BUS_MIPI_DSI 5 -#define RST_BUS_SS 6 -#define RST_BUS_DMA 7 -#define RST_BUS_MMC0 8 -#define RST_BUS_MMC1 9 -#define RST_BUS_MMC2 10 -#define RST_BUS_NAND 11 -#define RST_BUS_DRAM 12 -#define RST_BUS_EMAC 13 -#define RST_BUS_HSTIMER 14 -#define RST_BUS_SPI0 15 -#define RST_BUS_SPI1 16 -#define RST_BUS_OTG 17 -#define RST_BUS_EHCI0 18 -#define RST_BUS_EHCI1 19 -#define RST_BUS_OHCI0 20 - -#define RST_BUS_VE 21 -#define RST_BUS_TCON0 22 -#define RST_BUS_TCON1 23 -#define RST_BUS_CSI 24 -#define RST_BUS_HDMI0 25 -#define RST_BUS_HDMI1 26 -#define RST_BUS_DE 27 -#define RST_BUS_GPU 28 -#define RST_BUS_MSGBOX 29 -#define RST_BUS_SPINLOCK 30 - -#define RST_BUS_LVDS 31 - -#define RST_BUS_SPDIF 32 -#define RST_BUS_I2S0 33 -#define RST_BUS_I2S1 34 -#define RST_BUS_I2S2 35 -#define RST_BUS_TDM 36 - -#define RST_BUS_I2C0 37 -#define RST_BUS_I2C1 38 -#define RST_BUS_I2C2 39 -#define RST_BUS_UART0 40 -#define RST_BUS_UART1 41 -#define RST_BUS_UART2 42 -#define RST_BUS_UART3 43 -#define RST_BUS_UART4 44 - -#endif /* _DT_BINDINGS_RESET_SUN8I_A83T_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun8i-de2.h b/include/dt-bindings/reset/sun8i-de2.h deleted file mode 100644 index 1c36a6ac86d..00000000000 --- a/include/dt-bindings/reset/sun8i-de2.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * SPDX-License-Identifier: (GPL-2.0+ OR MIT) - */ - -#ifndef _DT_BINDINGS_RESET_SUN8I_DE2_H_ -#define _DT_BINDINGS_RESET_SUN8I_DE2_H_ - -#define RST_MIXER0 0 -#define RST_MIXER1 1 -#define RST_WB 2 -#define RST_ROT 3 - -#endif /* _DT_BINDINGS_RESET_SUN8I_DE2_H_ */ diff --git a/include/dt-bindings/reset/sun8i-h3-ccu.h b/include/dt-bindings/reset/sun8i-h3-ccu.h deleted file mode 100644 index 484c2a22919..00000000000 --- a/include/dt-bindings/reset/sun8i-h3-ccu.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_H3_H_ -#define _DT_BINDINGS_RST_SUN8I_H3_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_PHY2 2 -#define RST_USB_PHY3 3 - -#define RST_MBUS 4 - -#define RST_BUS_CE 5 -#define RST_BUS_DMA 6 -#define RST_BUS_MMC0 7 -#define RST_BUS_MMC1 8 -#define RST_BUS_MMC2 9 -#define RST_BUS_NAND 10 -#define RST_BUS_DRAM 11 -#define RST_BUS_EMAC 12 -#define RST_BUS_TS 13 -#define RST_BUS_HSTIMER 14 -#define RST_BUS_SPI0 15 -#define RST_BUS_SPI1 16 -#define RST_BUS_OTG 17 -#define RST_BUS_EHCI0 18 -#define RST_BUS_EHCI1 19 -#define RST_BUS_EHCI2 20 -#define RST_BUS_EHCI3 21 -#define RST_BUS_OHCI0 22 -#define RST_BUS_OHCI1 23 -#define RST_BUS_OHCI2 24 -#define RST_BUS_OHCI3 25 -#define RST_BUS_VE 26 -#define RST_BUS_TCON0 27 -#define RST_BUS_TCON1 28 -#define RST_BUS_DEINTERLACE 29 -#define RST_BUS_CSI 30 -#define RST_BUS_TVE 31 -#define RST_BUS_HDMI0 32 -#define RST_BUS_HDMI1 33 -#define RST_BUS_DE 34 -#define RST_BUS_GPU 35 -#define RST_BUS_MSGBOX 36 -#define RST_BUS_SPINLOCK 37 -#define RST_BUS_DBG 38 -#define RST_BUS_EPHY 39 -#define RST_BUS_CODEC 40 -#define RST_BUS_SPDIF 41 -#define RST_BUS_THS 42 -#define RST_BUS_I2S0 43 -#define RST_BUS_I2S1 44 -#define RST_BUS_I2S2 45 -#define RST_BUS_I2C0 46 -#define RST_BUS_I2C1 47 -#define RST_BUS_I2C2 48 -#define RST_BUS_UART0 49 -#define RST_BUS_UART1 50 -#define RST_BUS_UART2 51 -#define RST_BUS_UART3 52 -#define RST_BUS_SCR0 53 - -/* New resets imported in H5 */ -#define RST_BUS_SCR1 54 - -#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ diff --git a/include/dt-bindings/reset/sun8i-r-ccu.h b/include/dt-bindings/reset/sun8i-r-ccu.h deleted file mode 100644 index 4ba64f3d6fc..00000000000 --- a/include/dt-bindings/reset/sun8i-r-ccu.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_R_CCU_H_ -#define _DT_BINDINGS_RST_SUN8I_R_CCU_H_ - -#define RST_APB0_IR 0 -#define RST_APB0_TIMER 1 -#define RST_APB0_RSB 2 -#define RST_APB0_UART 3 -/* 4 is reserved for RST_APB0_W1 on A31 */ -#define RST_APB0_I2C 5 - -#endif /* _DT_BINDINGS_RST_SUN8I_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun8i-r40-ccu.h b/include/dt-bindings/reset/sun8i-r40-ccu.h deleted file mode 100644 index c5ebcf6672e..00000000000 --- a/include/dt-bindings/reset/sun8i-r40-ccu.h +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright (C) 2017 Icenowy Zheng - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_R40_H_ -#define _DT_BINDINGS_RST_SUN8I_R40_H_ - -#define RST_USB_PHY0 0 -#define RST_USB_PHY1 1 -#define RST_USB_PHY2 2 - -#define RST_DRAM 3 -#define RST_MBUS 4 - -#define RST_BUS_MIPI_DSI 5 -#define RST_BUS_CE 6 -#define RST_BUS_DMA 7 -#define RST_BUS_MMC0 8 -#define RST_BUS_MMC1 9 -#define RST_BUS_MMC2 10 -#define RST_BUS_MMC3 11 -#define RST_BUS_NAND 12 -#define RST_BUS_DRAM 13 -#define RST_BUS_EMAC 14 -#define RST_BUS_TS 15 -#define RST_BUS_HSTIMER 16 -#define RST_BUS_SPI0 17 -#define RST_BUS_SPI1 18 -#define RST_BUS_SPI2 19 -#define RST_BUS_SPI3 20 -#define RST_BUS_SATA 21 -#define RST_BUS_OTG 22 -#define RST_BUS_EHCI0 23 -#define RST_BUS_EHCI1 24 -#define RST_BUS_EHCI2 25 -#define RST_BUS_OHCI0 26 -#define RST_BUS_OHCI1 27 -#define RST_BUS_OHCI2 28 -#define RST_BUS_VE 29 -#define RST_BUS_MP 30 -#define RST_BUS_DEINTERLACE 31 -#define RST_BUS_CSI0 32 -#define RST_BUS_CSI1 33 -#define RST_BUS_HDMI0 34 -#define RST_BUS_HDMI1 35 -#define RST_BUS_DE 36 -#define RST_BUS_TVE0 37 -#define RST_BUS_TVE1 38 -#define RST_BUS_TVE_TOP 39 -#define RST_BUS_GMAC 40 -#define RST_BUS_GPU 41 -#define RST_BUS_TVD0 42 -#define RST_BUS_TVD1 43 -#define RST_BUS_TVD2 44 -#define RST_BUS_TVD3 45 -#define RST_BUS_TVD_TOP 46 -#define RST_BUS_TCON_LCD0 47 -#define RST_BUS_TCON_LCD1 48 -#define RST_BUS_TCON_TV0 49 -#define RST_BUS_TCON_TV1 50 -#define RST_BUS_TCON_TOP 51 -#define RST_BUS_DBG 52 -#define RST_BUS_LVDS 53 -#define RST_BUS_CODEC 54 -#define RST_BUS_SPDIF 55 -#define RST_BUS_AC97 56 -#define RST_BUS_IR0 57 -#define RST_BUS_IR1 58 -#define RST_BUS_THS 59 -#define RST_BUS_KEYPAD 60 -#define RST_BUS_I2S0 61 -#define RST_BUS_I2S1 62 -#define RST_BUS_I2S2 63 -#define RST_BUS_I2C0 64 -#define RST_BUS_I2C1 65 -#define RST_BUS_I2C2 66 -#define RST_BUS_I2C3 67 -#define RST_BUS_CAN 68 -#define RST_BUS_SCR 69 -#define RST_BUS_PS20 70 -#define RST_BUS_PS21 71 -#define RST_BUS_I2C4 72 -#define RST_BUS_UART0 73 -#define RST_BUS_UART1 74 -#define RST_BUS_UART2 75 -#define RST_BUS_UART3 76 -#define RST_BUS_UART4 77 -#define RST_BUS_UART5 78 -#define RST_BUS_UART6 79 -#define RST_BUS_UART7 80 - -#endif /* _DT_BINDINGS_RST_SUN8I_R40_H_ */ diff --git a/include/dt-bindings/reset/sun8i-v3s-ccu.h b/include/dt-bindings/reset/sun8i-v3s-ccu.h deleted file mode 100644 index b6790173afd..00000000000 --- a/include/dt-bindings/reset/sun8i-v3s-ccu.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (C) 2016 Icenowy Zheng - * - * Based on sun8i-v3s-ccu.h, which is - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RST_SUN8I_V3S_H_ -#define _DT_BINDINGS_RST_SUN8I_V3S_H_ - -#define RST_USB_PHY0 0 - -#define RST_MBUS 1 - -#define RST_BUS_CE 5 -#define RST_BUS_DMA 6 -#define RST_BUS_MMC0 7 -#define RST_BUS_MMC1 8 -#define RST_BUS_MMC2 9 -#define RST_BUS_DRAM 11 -#define RST_BUS_EMAC 12 -#define RST_BUS_HSTIMER 14 -#define RST_BUS_SPI0 15 -#define RST_BUS_OTG 17 -#define RST_BUS_EHCI0 18 -#define RST_BUS_OHCI0 22 -#define RST_BUS_VE 26 -#define RST_BUS_TCON0 27 -#define RST_BUS_CSI 30 -#define RST_BUS_DE 34 -#define RST_BUS_DBG 38 -#define RST_BUS_EPHY 39 -#define RST_BUS_CODEC 40 -#define RST_BUS_I2C0 46 -#define RST_BUS_I2C1 47 -#define RST_BUS_UART0 49 -#define RST_BUS_UART1 50 -#define RST_BUS_UART2 51 - -/* Reset lines not available on V3s */ -#define RST_BUS_I2S0 52 - -#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */ diff --git a/include/dt-bindings/reset/sun9i-a80-ccu.h b/include/dt-bindings/reset/sun9i-a80-ccu.h deleted file mode 100644 index 4b8df4b3678..00000000000 --- a/include/dt-bindings/reset/sun9i-a80-ccu.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ -#define _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ - -#define RST_BUS_FD 0 -#define RST_BUS_VE 1 -#define RST_BUS_GPU_CTRL 2 -#define RST_BUS_SS 3 -#define RST_BUS_MMC 4 -#define RST_BUS_NAND0 5 -#define RST_BUS_NAND1 6 -#define RST_BUS_SDRAM 7 -#define RST_BUS_SATA 8 -#define RST_BUS_TS 9 -#define RST_BUS_SPI0 10 -#define RST_BUS_SPI1 11 -#define RST_BUS_SPI2 12 -#define RST_BUS_SPI3 13 - -#define RST_BUS_OTG 14 -#define RST_BUS_OTG_PHY 15 -#define RST_BUS_MIPI_HSI 16 -#define RST_BUS_GMAC 17 -#define RST_BUS_MSGBOX 18 -#define RST_BUS_SPINLOCK 19 -#define RST_BUS_HSTIMER 20 -#define RST_BUS_DMA 21 - -#define RST_BUS_LCD0 22 -#define RST_BUS_LCD1 23 -#define RST_BUS_EDP 24 -#define RST_BUS_LVDS 25 -#define RST_BUS_CSI 26 -#define RST_BUS_HDMI0 27 -#define RST_BUS_HDMI1 28 -#define RST_BUS_DE 29 -#define RST_BUS_MP 30 -#define RST_BUS_GPU 31 -#define RST_BUS_MIPI_DSI 32 - -#define RST_BUS_SPDIF 33 -#define RST_BUS_AC97 34 -#define RST_BUS_I2S0 35 -#define RST_BUS_I2S1 36 -#define RST_BUS_LRADC 37 -#define RST_BUS_GPADC 38 -#define RST_BUS_CIR_TX 39 - -#define RST_BUS_I2C0 40 -#define RST_BUS_I2C1 41 -#define RST_BUS_I2C2 42 -#define RST_BUS_I2C3 43 -#define RST_BUS_I2C4 44 -#define RST_BUS_UART0 45 -#define RST_BUS_UART1 46 -#define RST_BUS_UART2 47 -#define RST_BUS_UART3 48 -#define RST_BUS_UART4 49 -#define RST_BUS_UART5 50 - -#endif /* _DT_BINDINGS_RESET_SUN9I_A80_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun9i-a80-de.h b/include/dt-bindings/reset/sun9i-a80-de.h deleted file mode 100644 index 20507277017..00000000000 --- a/include/dt-bindings/reset/sun9i-a80-de.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ -#define _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ - -#define RST_FE0 0 -#define RST_FE1 1 -#define RST_FE2 2 -#define RST_DEU0 3 -#define RST_DEU1 4 -#define RST_BE0 5 -#define RST_BE1 6 -#define RST_BE2 7 -#define RST_DRC0 8 -#define RST_DRC1 9 -#define RST_MERGE 10 - -#endif /* _DT_BINDINGS_RESET_SUN9I_A80_DE_H_ */ diff --git a/include/dt-bindings/reset/sun9i-a80-usb.h b/include/dt-bindings/reset/sun9i-a80-usb.h deleted file mode 100644 index ee492864c2a..00000000000 --- a/include/dt-bindings/reset/sun9i-a80-usb.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2016 Chen-Yu Tsai - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ -#define _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ - -#define RST_USB0_HCI 0 -#define RST_USB1_HCI 1 -#define RST_USB2_HCI 2 - -#define RST_USB0_PHY 3 -#define RST_USB1_HSIC 4 -#define RST_USB1_PHY 5 -#define RST_USB2_HSIC 6 -#define RST_USB2_PHY 7 - -#endif /* _DT_BINDINGS_RESET_SUN9I_A80_USB_H_ */ diff --git a/include/dt-bindings/reset/suniv-ccu-f1c100s.h b/include/dt-bindings/reset/suniv-ccu-f1c100s.h deleted file mode 100644 index 6a4b4385fe5..00000000000 --- a/include/dt-bindings/reset/suniv-ccu-f1c100s.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) - * - * Copyright (C) 2018 Icenowy Zheng - * - */ - -#ifndef _DT_BINDINGS_RST_SUNIV_F1C100S_H_ -#define _DT_BINDINGS_RST_SUNIV_F1C100S_H_ - -#define RST_USB_PHY0 0 -#define RST_BUS_DMA 1 -#define RST_BUS_MMC0 2 -#define RST_BUS_MMC1 3 -#define RST_BUS_DRAM 4 -#define RST_BUS_SPI0 5 -#define RST_BUS_SPI1 6 -#define RST_BUS_OTG 7 -#define RST_BUS_VE 8 -#define RST_BUS_LCD 9 -#define RST_BUS_DEINTERLACE 10 -#define RST_BUS_CSI 11 -#define RST_BUS_TVD 12 -#define RST_BUS_TVE 13 -#define RST_BUS_DE_BE 14 -#define RST_BUS_DE_FE 15 -#define RST_BUS_CODEC 16 -#define RST_BUS_SPDIF 17 -#define RST_BUS_IR 18 -#define RST_BUS_RSB 19 -#define RST_BUS_I2S0 20 -#define RST_BUS_I2C0 21 -#define RST_BUS_I2C1 22 -#define RST_BUS_I2C2 23 -#define RST_BUS_UART0 24 -#define RST_BUS_UART1 25 -#define RST_BUS_UART2 26 - -#endif /* _DT_BINDINGS_RST_SUNIV_F1C100S_H_ */ diff --git a/include/dt-bindings/reset/xlnx-zynqmp-resets.h b/include/dt-bindings/reset/xlnx-zynqmp-resets.h deleted file mode 100644 index d44525b9f8d..00000000000 --- a/include/dt-bindings/reset/xlnx-zynqmp-resets.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 Xilinx, Inc. - */ - -#ifndef _DT_BINDINGS_ZYNQMP_RESETS_H -#define _DT_BINDINGS_ZYNQMP_RESETS_H - -#define ZYNQMP_RESET_PCIE_CFG 0 -#define ZYNQMP_RESET_PCIE_BRIDGE 1 -#define ZYNQMP_RESET_PCIE_CTRL 2 -#define ZYNQMP_RESET_DP 3 -#define ZYNQMP_RESET_SWDT_CRF 4 -#define ZYNQMP_RESET_AFI_FM5 5 -#define ZYNQMP_RESET_AFI_FM4 6 -#define ZYNQMP_RESET_AFI_FM3 7 -#define ZYNQMP_RESET_AFI_FM2 8 -#define ZYNQMP_RESET_AFI_FM1 9 -#define ZYNQMP_RESET_AFI_FM0 10 -#define ZYNQMP_RESET_GDMA 11 -#define ZYNQMP_RESET_GPU_PP1 12 -#define ZYNQMP_RESET_GPU_PP0 13 -#define ZYNQMP_RESET_GPU 14 -#define ZYNQMP_RESET_GT 15 -#define ZYNQMP_RESET_SATA 16 -#define ZYNQMP_RESET_ACPU3_PWRON 17 -#define ZYNQMP_RESET_ACPU2_PWRON 18 -#define ZYNQMP_RESET_ACPU1_PWRON 19 -#define ZYNQMP_RESET_ACPU0_PWRON 20 -#define ZYNQMP_RESET_APU_L2 21 -#define ZYNQMP_RESET_ACPU3 22 -#define ZYNQMP_RESET_ACPU2 23 -#define ZYNQMP_RESET_ACPU1 24 -#define ZYNQMP_RESET_ACPU0 25 -#define ZYNQMP_RESET_DDR 26 -#define ZYNQMP_RESET_APM_FPD 27 -#define ZYNQMP_RESET_SOFT 28 -#define ZYNQMP_RESET_GEM0 29 -#define ZYNQMP_RESET_GEM1 30 -#define ZYNQMP_RESET_GEM2 31 -#define ZYNQMP_RESET_GEM3 32 -#define ZYNQMP_RESET_QSPI 33 -#define ZYNQMP_RESET_UART0 34 -#define ZYNQMP_RESET_UART1 35 -#define ZYNQMP_RESET_SPI0 36 -#define ZYNQMP_RESET_SPI1 37 -#define ZYNQMP_RESET_SDIO0 38 -#define ZYNQMP_RESET_SDIO1 39 -#define ZYNQMP_RESET_CAN0 40 -#define ZYNQMP_RESET_CAN1 41 -#define ZYNQMP_RESET_I2C0 42 -#define ZYNQMP_RESET_I2C1 43 -#define ZYNQMP_RESET_TTC0 44 -#define ZYNQMP_RESET_TTC1 45 -#define ZYNQMP_RESET_TTC2 46 -#define ZYNQMP_RESET_TTC3 47 -#define ZYNQMP_RESET_SWDT_CRL 48 -#define ZYNQMP_RESET_NAND 49 -#define ZYNQMP_RESET_ADMA 50 -#define ZYNQMP_RESET_GPIO 51 -#define ZYNQMP_RESET_IOU_CC 52 -#define ZYNQMP_RESET_TIMESTAMP 53 -#define ZYNQMP_RESET_RPU_R50 54 -#define ZYNQMP_RESET_RPU_R51 55 -#define ZYNQMP_RESET_RPU_AMBA 56 -#define ZYNQMP_RESET_OCM 57 -#define ZYNQMP_RESET_RPU_PGE 58 -#define ZYNQMP_RESET_USB0_CORERESET 59 -#define ZYNQMP_RESET_USB1_CORERESET 60 -#define ZYNQMP_RESET_USB0_HIBERRESET 61 -#define ZYNQMP_RESET_USB1_HIBERRESET 62 -#define ZYNQMP_RESET_USB0_APB 63 -#define ZYNQMP_RESET_USB1_APB 64 -#define ZYNQMP_RESET_IPI 65 -#define ZYNQMP_RESET_APM_LPD 66 -#define ZYNQMP_RESET_RTC 67 -#define ZYNQMP_RESET_SYSMON 68 -#define ZYNQMP_RESET_AFI_FM6 69 -#define ZYNQMP_RESET_LPD_SWDT 70 -#define ZYNQMP_RESET_FPD 71 -#define ZYNQMP_RESET_RPU_DBG1 72 -#define ZYNQMP_RESET_RPU_DBG0 73 -#define ZYNQMP_RESET_DBG_LPD 74 -#define ZYNQMP_RESET_DBG_FPD 75 -#define ZYNQMP_RESET_APLL 76 -#define ZYNQMP_RESET_DPLL 77 -#define ZYNQMP_RESET_VPLL 78 -#define ZYNQMP_RESET_IOPLL 79 -#define ZYNQMP_RESET_RPLL 80 -#define ZYNQMP_RESET_GPO3_PL_0 81 -#define ZYNQMP_RESET_GPO3_PL_1 82 -#define ZYNQMP_RESET_GPO3_PL_2 83 -#define ZYNQMP_RESET_GPO3_PL_3 84 -#define ZYNQMP_RESET_GPO3_PL_4 85 -#define ZYNQMP_RESET_GPO3_PL_5 86 -#define ZYNQMP_RESET_GPO3_PL_6 87 -#define ZYNQMP_RESET_GPO3_PL_7 88 -#define ZYNQMP_RESET_GPO3_PL_8 89 -#define ZYNQMP_RESET_GPO3_PL_9 90 -#define ZYNQMP_RESET_GPO3_PL_10 91 -#define ZYNQMP_RESET_GPO3_PL_11 92 -#define ZYNQMP_RESET_GPO3_PL_12 93 -#define ZYNQMP_RESET_GPO3_PL_13 94 -#define ZYNQMP_RESET_GPO3_PL_14 95 -#define ZYNQMP_RESET_GPO3_PL_15 96 -#define ZYNQMP_RESET_GPO3_PL_16 97 -#define ZYNQMP_RESET_GPO3_PL_17 98 -#define ZYNQMP_RESET_GPO3_PL_18 99 -#define ZYNQMP_RESET_GPO3_PL_19 100 -#define ZYNQMP_RESET_GPO3_PL_20 101 -#define ZYNQMP_RESET_GPO3_PL_21 102 -#define ZYNQMP_RESET_GPO3_PL_22 103 -#define ZYNQMP_RESET_GPO3_PL_23 104 -#define ZYNQMP_RESET_GPO3_PL_24 105 -#define ZYNQMP_RESET_GPO3_PL_25 106 -#define ZYNQMP_RESET_GPO3_PL_26 107 -#define ZYNQMP_RESET_GPO3_PL_27 108 -#define ZYNQMP_RESET_GPO3_PL_28 109 -#define ZYNQMP_RESET_GPO3_PL_29 110 -#define ZYNQMP_RESET_GPO3_PL_30 111 -#define ZYNQMP_RESET_GPO3_PL_31 112 -#define ZYNQMP_RESET_RPU_LS 113 -#define ZYNQMP_RESET_PS_ONLY 114 -#define ZYNQMP_RESET_PL 115 -#define ZYNQMP_RESET_PS_PL0 116 -#define ZYNQMP_RESET_PS_PL1 117 -#define ZYNQMP_RESET_PS_PL2 118 -#define ZYNQMP_RESET_PS_PL3 119 - -#endif diff --git a/include/dt-bindings/soc/bcm2835-pm.h b/include/dt-bindings/soc/bcm2835-pm.h deleted file mode 100644 index 153d75b8d99..00000000000 --- a/include/dt-bindings/soc/bcm2835-pm.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -#ifndef _DT_BINDINGS_ARM_BCM2835_PM_H -#define _DT_BINDINGS_ARM_BCM2835_PM_H - -#define BCM2835_POWER_DOMAIN_GRAFX 0 -#define BCM2835_POWER_DOMAIN_GRAFX_V3D 1 -#define BCM2835_POWER_DOMAIN_IMAGE 2 -#define BCM2835_POWER_DOMAIN_IMAGE_PERI 3 -#define BCM2835_POWER_DOMAIN_IMAGE_ISP 4 -#define BCM2835_POWER_DOMAIN_IMAGE_H264 5 -#define BCM2835_POWER_DOMAIN_USB 6 -#define BCM2835_POWER_DOMAIN_DSI0 7 -#define BCM2835_POWER_DOMAIN_DSI1 8 -#define BCM2835_POWER_DOMAIN_CAM0 9 -#define BCM2835_POWER_DOMAIN_CAM1 10 -#define BCM2835_POWER_DOMAIN_CCP2TX 11 -#define BCM2835_POWER_DOMAIN_HDMI 12 - -#define BCM2835_POWER_DOMAIN_COUNT 13 - -#define BCM2835_RESET_V3D 0 -#define BCM2835_RESET_ISP 1 -#define BCM2835_RESET_H264 2 - -#define BCM2835_RESET_COUNT 3 - -#endif /* _DT_BINDINGS_ARM_BCM2835_PM_H */ diff --git a/include/dt-bindings/soc/ti,sci_pm_domain.h b/include/dt-bindings/soc/ti,sci_pm_domain.h deleted file mode 100644 index 8f2a7360b65..00000000000 --- a/include/dt-bindings/soc/ti,sci_pm_domain.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H -#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H - -#define TI_SCI_PD_EXCLUSIVE 1 -#define TI_SCI_PD_SHARED 0 - -#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */ diff --git a/include/dt-bindings/sound/apq8016-lpass.h b/include/dt-bindings/sound/apq8016-lpass.h deleted file mode 100644 index dc605c4bc22..00000000000 --- a/include/dt-bindings/sound/apq8016-lpass.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_APQ8016_LPASS_H -#define __DT_APQ8016_LPASS_H - -#include - -/* NOTE: Use qcom,lpass.h to define any AIF ID's for LPASS */ - -#endif /* __DT_APQ8016_LPASS_H */ diff --git a/include/dt-bindings/sound/microchip,pdmc.h b/include/dt-bindings/sound/microchip,pdmc.h deleted file mode 100644 index 96cde94ce74..00000000000 --- a/include/dt-bindings/sound/microchip,pdmc.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __DT_BINDINGS_MICROCHIP_PDMC_H__ -#define __DT_BINDINGS_MICROCHIP_PDMC_H__ - -/* PDM microphone's pin placement */ -#define MCHP_PDMC_DS0 0 -#define MCHP_PDMC_DS1 1 - -/* PDM microphone clock edge sampling */ -#define MCHP_PDMC_CLK_POSITIVE 0 -#define MCHP_PDMC_CLK_NEGATIVE 1 - -#endif /* __DT_BINDINGS_MICROCHIP_PDMC_H__ */ -- cgit v1.3.1 From 9006969b6d402992e89dc2c2810aff08249b2e4a Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 27 May 2025 17:50:37 -0600 Subject: include/dt-bindings: Remove functionally identical headers As part of moving to using OF_UPSTREAM and so the upstream dt-bindings headers we have a number of these headers that are in our include directory and differ only in combinations of spacing changes and/or switching to SPDX license tags. We can safely remove the copies under include/dt-bindings now to prevent future conflicts. Signed-off-by: Tom Rini --- include/dt-bindings/bus/ti-sysc.h | 28 - include/dt-bindings/clock/bcm6328-clock.h | 24 - include/dt-bindings/clock/maxim,max77802.h | 22 - include/dt-bindings/clock/tegra124-car.h | 19 - include/dt-bindings/clock/tegra186-clock.h | 940 ---------------------- include/dt-bindings/dma/at91.h | 51 -- include/dt-bindings/gpio/aspeed-gpio.h | 51 -- include/dt-bindings/gpio/tegra-gpio.h | 51 -- include/dt-bindings/media/omap3-isp.h | 22 - include/dt-bindings/mfd/st,stpmic1.h | 50 -- include/dt-bindings/net/ti-dp83867.h | 53 -- include/dt-bindings/pinctrl/dra.h | 79 -- include/dt-bindings/pinctrl/hisi.h | 74 -- include/dt-bindings/pinctrl/mt65xx.h | 41 - include/dt-bindings/pinctrl/omap.h | 91 --- include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h | 7 - include/dt-bindings/pinctrl/pinctrl-tegra.h | 37 - include/dt-bindings/pinctrl/r7s72100-pinctrl.h | 18 - include/dt-bindings/power/raspberrypi-power.h | 41 - include/dt-bindings/power/tegra186-powergate.h | 28 - include/dt-bindings/regulator/maxim,max77802.h | 18 - include/dt-bindings/reset/altr,rst-mgr-a10.h | 110 --- include/dt-bindings/reset/altr,rst-mgr.h | 82 -- include/dt-bindings/reset/bcm6328-reset.h | 23 - include/dt-bindings/reset/bcm6358-reset.h | 20 - include/dt-bindings/reset/bcm6362-reset.h | 27 - include/dt-bindings/reset/bcm6368-reset.h | 21 - include/dt-bindings/reset/nuvoton,npcm7xx-reset.h | 91 --- include/dt-bindings/reset/tegra124-car.h | 12 - include/dt-bindings/reset/tegra186-reset.h | 205 ----- include/dt-bindings/reset/ti-syscon.h | 38 - 31 files changed, 2374 deletions(-) delete mode 100644 include/dt-bindings/bus/ti-sysc.h delete mode 100644 include/dt-bindings/clock/bcm6328-clock.h delete mode 100644 include/dt-bindings/clock/maxim,max77802.h delete mode 100644 include/dt-bindings/clock/tegra124-car.h delete mode 100644 include/dt-bindings/clock/tegra186-clock.h delete mode 100644 include/dt-bindings/dma/at91.h delete mode 100644 include/dt-bindings/gpio/aspeed-gpio.h delete mode 100644 include/dt-bindings/gpio/tegra-gpio.h delete mode 100644 include/dt-bindings/media/omap3-isp.h delete mode 100644 include/dt-bindings/mfd/st,stpmic1.h delete mode 100644 include/dt-bindings/net/ti-dp83867.h delete mode 100644 include/dt-bindings/pinctrl/dra.h delete mode 100644 include/dt-bindings/pinctrl/hisi.h delete mode 100644 include/dt-bindings/pinctrl/mt65xx.h delete mode 100644 include/dt-bindings/pinctrl/omap.h delete mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h delete mode 100644 include/dt-bindings/pinctrl/pinctrl-tegra.h delete mode 100644 include/dt-bindings/pinctrl/r7s72100-pinctrl.h delete mode 100644 include/dt-bindings/power/raspberrypi-power.h delete mode 100644 include/dt-bindings/power/tegra186-powergate.h delete mode 100644 include/dt-bindings/regulator/maxim,max77802.h delete mode 100644 include/dt-bindings/reset/altr,rst-mgr-a10.h delete mode 100644 include/dt-bindings/reset/altr,rst-mgr.h delete mode 100644 include/dt-bindings/reset/bcm6328-reset.h delete mode 100644 include/dt-bindings/reset/bcm6358-reset.h delete mode 100644 include/dt-bindings/reset/bcm6362-reset.h delete mode 100644 include/dt-bindings/reset/bcm6368-reset.h delete mode 100644 include/dt-bindings/reset/nuvoton,npcm7xx-reset.h delete mode 100644 include/dt-bindings/reset/tegra124-car.h delete mode 100644 include/dt-bindings/reset/tegra186-reset.h delete mode 100644 include/dt-bindings/reset/ti-syscon.h (limited to 'include') diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h deleted file mode 100644 index eae42745437..00000000000 --- a/include/dt-bindings/bus/ti-sysc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* TI sysc interconnect target module defines */ - -/* Generic sysc found on omap2 and later, also known as type1 */ -#define SYSC_OMAP2_CLOCKACTIVITY (3 << 8) -#define SYSC_OMAP2_EMUFREE (1 << 5) -#define SYSC_OMAP2_ENAWAKEUP (1 << 2) -#define SYSC_OMAP2_SOFTRESET (1 << 1) -#define SYSC_OMAP2_AUTOIDLE (1 << 0) - -/* Generic sysc found on omap4 and later, also known as type2 */ -#define SYSC_OMAP4_DMADISABLE (1 << 16) -#define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */ -#define SYSC_OMAP4_SOFTRESET (1 << 0) - -/* SmartReflex sysc found on 36xx and later */ -#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26) - -#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4) - -/* PRUSS sysc found on AM33xx/AM43xx/AM57xx */ -#define SYSC_PRUSS_SUB_MWAIT (1 << 5) -#define SYSC_PRUSS_STANDBY_INIT (1 << 4) - -/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ -#define SYSC_IDLE_FORCE 0 -#define SYSC_IDLE_NO 1 -#define SYSC_IDLE_SMART 2 -#define SYSC_IDLE_SMART_WKUP 3 diff --git a/include/dt-bindings/clock/bcm6328-clock.h b/include/dt-bindings/clock/bcm6328-clock.h deleted file mode 100644 index 6f1e018a74b..00000000000 --- a/include/dt-bindings/clock/bcm6328-clock.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - * - * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h - */ - -#ifndef __DT_BINDINGS_CLOCK_BCM6328_H -#define __DT_BINDINGS_CLOCK_BCM6328_H - -#define BCM6328_CLK_PHYMIPS 0 -#define BCM6328_CLK_ADSL_QPROC 1 -#define BCM6328_CLK_ADSL_AFE 2 -#define BCM6328_CLK_ADSL 3 -#define BCM6328_CLK_MIPS 4 -#define BCM6328_CLK_SAR 5 -#define BCM6328_CLK_PCM 6 -#define BCM6328_CLK_USBD 7 -#define BCM6328_CLK_USBH 8 -#define BCM6328_CLK_HSSPI 9 -#define BCM6328_CLK_PCIE 10 -#define BCM6328_CLK_ROBOSW 11 - -#endif /* __DT_BINDINGS_CLOCK_BCM6328_H */ diff --git a/include/dt-bindings/clock/maxim,max77802.h b/include/dt-bindings/clock/maxim,max77802.h deleted file mode 100644 index 997312edcbb..00000000000 --- a/include/dt-bindings/clock/maxim,max77802.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (C) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants clocks for the Maxim 77802 PMIC. - */ - -#ifndef _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H -#define _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H - -/* Fixed rate clocks. */ - -#define MAX77802_CLK_32K_AP 0 -#define MAX77802_CLK_32K_CP 1 - -/* Total number of clocks. */ -#define MAX77802_CLKS_NUM (MAX77802_CLK_32K_CP + 1) - -#endif /* _DT_BINDINGS_CLOCK_MAXIM_MAX77802_CLOCK_H */ diff --git a/include/dt-bindings/clock/tegra124-car.h b/include/dt-bindings/clock/tegra124-car.h deleted file mode 100644 index 2860737f044..00000000000 --- a/include/dt-bindings/clock/tegra124-car.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This header provides Tegra124-specific constants for binding - * nvidia,tegra124-car. - */ - -#include - -#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_H - -#define TEGRA124_CLK_PLL_X 227 -#define TEGRA124_CLK_PLL_X_OUT0 228 - -#define TEGRA124_CLK_CCLK_G 262 -#define TEGRA124_CLK_CCLK_LP 263 - -#define TEGRA124_CLK_CLK_MAX 315 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */ diff --git a/include/dt-bindings/clock/tegra186-clock.h b/include/dt-bindings/clock/tegra186-clock.h deleted file mode 100644 index f73d32098f9..00000000000 --- a/include/dt-bindings/clock/tegra186-clock.h +++ /dev/null @@ -1,940 +0,0 @@ -/** @file */ - -#ifndef _MACH_T186_CLK_T186_H -#define _MACH_T186_CLK_T186_H - -/** - * @defgroup clock_ids Clock Identifiers - * @{ - * @defgroup extern_input external input clocks - * @{ - * @def TEGRA186_CLK_OSC - * @def TEGRA186_CLK_CLK_32K - * @def TEGRA186_CLK_DTV_INPUT - * @def TEGRA186_CLK_SOR0_PAD_CLKOUT - * @def TEGRA186_CLK_SOR1_PAD_CLKOUT - * @def TEGRA186_CLK_I2S1_SYNC_INPUT - * @def TEGRA186_CLK_I2S2_SYNC_INPUT - * @def TEGRA186_CLK_I2S3_SYNC_INPUT - * @def TEGRA186_CLK_I2S4_SYNC_INPUT - * @def TEGRA186_CLK_I2S5_SYNC_INPUT - * @def TEGRA186_CLK_I2S6_SYNC_INPUT - * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT - * @} - * - * @defgroup extern_output external output clocks - * @{ - * @def TEGRA186_CLK_EXTPERIPH1 - * @def TEGRA186_CLK_EXTPERIPH2 - * @def TEGRA186_CLK_EXTPERIPH3 - * @def TEGRA186_CLK_EXTPERIPH4 - * @} - * - * @defgroup display_clks display related clocks - * @{ - * @def TEGRA186_CLK_CEC - * @def TEGRA186_CLK_DSIC - * @def TEGRA186_CLK_DSIC_LP - * @def TEGRA186_CLK_DSID - * @def TEGRA186_CLK_DSID_LP - * @def TEGRA186_CLK_DPAUX1 - * @def TEGRA186_CLK_DPAUX - * @def TEGRA186_CLK_HDA2HDMICODEC - * @def TEGRA186_CLK_NVDISPLAY_DISP - * @def TEGRA186_CLK_NVDISPLAY_DSC - * @def TEGRA186_CLK_NVDISPLAY_P0 - * @def TEGRA186_CLK_NVDISPLAY_P1 - * @def TEGRA186_CLK_NVDISPLAY_P2 - * @def TEGRA186_CLK_NVDISPLAYHUB - * @def TEGRA186_CLK_SOR_SAFE - * @def TEGRA186_CLK_SOR0 - * @def TEGRA186_CLK_SOR0_OUT - * @def TEGRA186_CLK_SOR1 - * @def TEGRA186_CLK_SOR1_OUT - * @def TEGRA186_CLK_DSI - * @def TEGRA186_CLK_MIPI_CAL - * @def TEGRA186_CLK_DSIA_LP - * @def TEGRA186_CLK_DSIB - * @def TEGRA186_CLK_DSIB_LP - * @} - * - * @defgroup camera_clks camera related clocks - * @{ - * @def TEGRA186_CLK_NVCSI - * @def TEGRA186_CLK_NVCSILP - * @def TEGRA186_CLK_VI - * @} - * - * @defgroup audio_clks audio related clocks - * @{ - * @def TEGRA186_CLK_ACLK - * @def TEGRA186_CLK_ADSP - * @def TEGRA186_CLK_ADSPNEON - * @def TEGRA186_CLK_AHUB - * @def TEGRA186_CLK_APE - * @def TEGRA186_CLK_APB2APE - * @def TEGRA186_CLK_AUD_MCLK - * @def TEGRA186_CLK_DMIC1 - * @def TEGRA186_CLK_DMIC2 - * @def TEGRA186_CLK_DMIC3 - * @def TEGRA186_CLK_DMIC4 - * @def TEGRA186_CLK_DSPK1 - * @def TEGRA186_CLK_DSPK2 - * @def TEGRA186_CLK_HDA - * @def TEGRA186_CLK_HDA2CODEC_2X - * @def TEGRA186_CLK_I2S1 - * @def TEGRA186_CLK_I2S2 - * @def TEGRA186_CLK_I2S3 - * @def TEGRA186_CLK_I2S4 - * @def TEGRA186_CLK_I2S5 - * @def TEGRA186_CLK_I2S6 - * @def TEGRA186_CLK_MAUD - * @def TEGRA186_CLK_PLL_A_OUT0 - * @def TEGRA186_CLK_SPDIF_DOUBLER - * @def TEGRA186_CLK_SPDIF_IN - * @def TEGRA186_CLK_SPDIF_OUT - * @def TEGRA186_CLK_SYNC_DMIC1 - * @def TEGRA186_CLK_SYNC_DMIC2 - * @def TEGRA186_CLK_SYNC_DMIC3 - * @def TEGRA186_CLK_SYNC_DMIC4 - * @def TEGRA186_CLK_SYNC_DMIC5 - * @def TEGRA186_CLK_SYNC_DSPK1 - * @def TEGRA186_CLK_SYNC_DSPK2 - * @def TEGRA186_CLK_SYNC_I2S1 - * @def TEGRA186_CLK_SYNC_I2S2 - * @def TEGRA186_CLK_SYNC_I2S3 - * @def TEGRA186_CLK_SYNC_I2S4 - * @def TEGRA186_CLK_SYNC_I2S5 - * @def TEGRA186_CLK_SYNC_I2S6 - * @def TEGRA186_CLK_SYNC_SPDIF - * @} - * - * @defgroup uart_clks UART clocks - * @{ - * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL - * @def TEGRA186_CLK_UARTA - * @def TEGRA186_CLK_UARTB - * @def TEGRA186_CLK_UARTC - * @def TEGRA186_CLK_UARTD - * @def TEGRA186_CLK_UARTE - * @def TEGRA186_CLK_UARTF - * @def TEGRA186_CLK_UARTG - * @def TEGRA186_CLK_UART_FST_MIPI_CAL - * @} - * - * @defgroup i2c_clks I2C clocks - * @{ - * @def TEGRA186_CLK_AON_I2C_SLOW - * @def TEGRA186_CLK_I2C1 - * @def TEGRA186_CLK_I2C2 - * @def TEGRA186_CLK_I2C3 - * @def TEGRA186_CLK_I2C4 - * @def TEGRA186_CLK_I2C5 - * @def TEGRA186_CLK_I2C6 - * @def TEGRA186_CLK_I2C8 - * @def TEGRA186_CLK_I2C9 - * @def TEGRA186_CLK_I2C1 - * @def TEGRA186_CLK_I2C12 - * @def TEGRA186_CLK_I2C13 - * @def TEGRA186_CLK_I2C14 - * @def TEGRA186_CLK_I2C_SLOW - * @def TEGRA186_CLK_VI_I2C - * @} - * - * @defgroup spi_clks SPI clocks - * @{ - * @def TEGRA186_CLK_SPI1 - * @def TEGRA186_CLK_SPI2 - * @def TEGRA186_CLK_SPI3 - * @def TEGRA186_CLK_SPI4 - * @} - * - * @defgroup storage storage related clocks - * @{ - * @def TEGRA186_CLK_SATA - * @def TEGRA186_CLK_SATA_OOB - * @def TEGRA186_CLK_SATA_IOBIST - * @def TEGRA186_CLK_SDMMC_LEGACY_TM - * @def TEGRA186_CLK_SDMMC1 - * @def TEGRA186_CLK_SDMMC2 - * @def TEGRA186_CLK_SDMMC3 - * @def TEGRA186_CLK_SDMMC4 - * @def TEGRA186_CLK_QSPI - * @def TEGRA186_CLK_QSPI_OUT - * @def TEGRA186_CLK_UFSDEV_REF - * @def TEGRA186_CLK_UFSHC - * @} - * - * @defgroup pwm_clks PWM clocks - * @{ - * @def TEGRA186_CLK_PWM1 - * @def TEGRA186_CLK_PWM2 - * @def TEGRA186_CLK_PWM3 - * @def TEGRA186_CLK_PWM4 - * @def TEGRA186_CLK_PWM5 - * @def TEGRA186_CLK_PWM6 - * @def TEGRA186_CLK_PWM7 - * @def TEGRA186_CLK_PWM8 - * @} - * - * @defgroup plls PLLs and related clocks - * @{ - * @def TEGRA186_CLK_PLLREFE_OUT_GATED - * @def TEGRA186_CLK_PLLREFE_OUT1 - * @def TEGRA186_CLK_PLLD_OUT1 - * @def TEGRA186_CLK_PLLP_OUT0 - * @def TEGRA186_CLK_PLLP_OUT5 - * @def TEGRA186_CLK_PLLA - * @def TEGRA186_CLK_PLLE_PWRSEQ - * @def TEGRA186_CLK_PLLA_OUT1 - * @def TEGRA186_CLK_PLLREFE_REF - * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ - * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ - * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH - * @def TEGRA186_CLK_PLLREFE_PEX - * @def TEGRA186_CLK_PLLREFE_IDDQ - * @def TEGRA186_CLK_PLLC_OUT_AON - * @def TEGRA186_CLK_PLLC_OUT_ISP - * @def TEGRA186_CLK_PLLC_OUT_VE - * @def TEGRA186_CLK_PLLC4_OUT - * @def TEGRA186_CLK_PLLREFE_OUT - * @def TEGRA186_CLK_PLLREFE_PLL_REF - * @def TEGRA186_CLK_PLLE - * @def TEGRA186_CLK_PLLC - * @def TEGRA186_CLK_PLLP - * @def TEGRA186_CLK_PLLD - * @def TEGRA186_CLK_PLLD2 - * @def TEGRA186_CLK_PLLREFE_VCO - * @def TEGRA186_CLK_PLLC2 - * @def TEGRA186_CLK_PLLC3 - * @def TEGRA186_CLK_PLLDP - * @def TEGRA186_CLK_PLLC4_VCO - * @def TEGRA186_CLK_PLLA1 - * @def TEGRA186_CLK_PLLNVCSI - * @def TEGRA186_CLK_PLLDISPHUB - * @def TEGRA186_CLK_PLLD3 - * @def TEGRA186_CLK_PLLBPMPCAM - * @def TEGRA186_CLK_PLLAON - * @def TEGRA186_CLK_PLLU - * @def TEGRA186_CLK_PLLC4_VCO_DIV2 - * @def TEGRA186_CLK_PLL_REF - * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5 - * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ - * @def TEGRA186_CLK_PLL_U_48M - * @def TEGRA186_CLK_PLL_U_480M - * @def TEGRA186_CLK_PLLC4_OUT0 - * @def TEGRA186_CLK_PLLC4_OUT1 - * @def TEGRA186_CLK_PLLC4_OUT2 - * @def TEGRA186_CLK_PLLC4_OUT_MUX - * @def TEGRA186_CLK_DFLLDISP_DIV - * @def TEGRA186_CLK_PLLDISPHUB_DIV - * @def TEGRA186_CLK_PLLP_DIV8 - * @} - * - * @defgroup nafll_clks NAFLL clock sources - * @{ - * @def TEGRA186_CLK_NAFLL_AXI_CBB - * @def TEGRA186_CLK_NAFLL_BCPU - * @def TEGRA186_CLK_NAFLL_BPMP - * @def TEGRA186_CLK_NAFLL_DISP - * @def TEGRA186_CLK_NAFLL_GPU - * @def TEGRA186_CLK_NAFLL_ISP - * @def TEGRA186_CLK_NAFLL_MCPU - * @def TEGRA186_CLK_NAFLL_NVDEC - * @def TEGRA186_CLK_NAFLL_NVENC - * @def TEGRA186_CLK_NAFLL_NVJPG - * @def TEGRA186_CLK_NAFLL_SCE - * @def TEGRA186_CLK_NAFLL_SE - * @def TEGRA186_CLK_NAFLL_TSEC - * @def TEGRA186_CLK_NAFLL_TSECB - * @def TEGRA186_CLK_NAFLL_VI - * @def TEGRA186_CLK_NAFLL_VIC - * @} - * - * @defgroup mphy MPHY related clocks - * @{ - * @def TEGRA186_CLK_MPHY_L0_RX_SYMB - * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT - * @def TEGRA186_CLK_MPHY_L0_TX_SYMB - * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT - * @def TEGRA186_CLK_MPHY_L0_RX_ANA - * @def TEGRA186_CLK_MPHY_L1_RX_ANA - * @def TEGRA186_CLK_MPHY_IOBIST - * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF - * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED - * @} - * - * @defgroup eavb EAVB related clocks - * @{ - * @def TEGRA186_CLK_EQOS_AXI - * @def TEGRA186_CLK_EQOS_PTP_REF - * @def TEGRA186_CLK_EQOS_RX - * @def TEGRA186_CLK_EQOS_RX_INPUT - * @def TEGRA186_CLK_EQOS_TX - * @} - * - * @defgroup usb USB related clocks - * @{ - * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT - * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT - * @def TEGRA186_CLK_HSIC_TRK - * @def TEGRA186_CLK_USB2_TRK - * @def TEGRA186_CLK_USB2_HSIC_TRK - * @def TEGRA186_CLK_XUSB_CORE_SS - * @def TEGRA186_CLK_XUSB_CORE_DEV - * @def TEGRA186_CLK_XUSB_FALCON - * @def TEGRA186_CLK_XUSB_FS - * @def TEGRA186_CLK_XUSB - * @def TEGRA186_CLK_XUSB_DEV - * @def TEGRA186_CLK_XUSB_HOST - * @def TEGRA186_CLK_XUSB_SS - * @} - * - * @defgroup bigblock compute block related clocks - * @{ - * @def TEGRA186_CLK_GPCCLK - * @def TEGRA186_CLK_GPC2CLK - * @def TEGRA186_CLK_GPU - * @def TEGRA186_CLK_HOST1X - * @def TEGRA186_CLK_ISP - * @def TEGRA186_CLK_NVDEC - * @def TEGRA186_CLK_NVENC - * @def TEGRA186_CLK_NVJPG - * @def TEGRA186_CLK_SE - * @def TEGRA186_CLK_TSEC - * @def TEGRA186_CLK_TSECB - * @def TEGRA186_CLK_VIC - * @} - * - * @defgroup can CAN bus related clocks - * @{ - * @def TEGRA186_CLK_CAN1 - * @def TEGRA186_CLK_CAN1_HOST - * @def TEGRA186_CLK_CAN2 - * @def TEGRA186_CLK_CAN2_HOST - * @} - * - * @defgroup system basic system clocks - * @{ - * @def TEGRA186_CLK_ACTMON - * @def TEGRA186_CLK_AON_APB - * @def TEGRA186_CLK_AON_CPU_NIC - * @def TEGRA186_CLK_AON_NIC - * @def TEGRA186_CLK_AXI_CBB - * @def TEGRA186_CLK_BPMP_APB - * @def TEGRA186_CLK_BPMP_CPU_NIC - * @def TEGRA186_CLK_BPMP_NIC_RATE - * @def TEGRA186_CLK_CLK_M - * @def TEGRA186_CLK_EMC - * @def TEGRA186_CLK_MSS_ENCRYPT - * @def TEGRA186_CLK_SCE_APB - * @def TEGRA186_CLK_SCE_CPU_NIC - * @def TEGRA186_CLK_SCE_NIC - * @def TEGRA186_CLK_TSC - * @} - * - * @defgroup pcie_clks PCIe related clocks - * @{ - * @def TEGRA186_CLK_AFI - * @def TEGRA186_CLK_PCIE - * @def TEGRA186_CLK_PCIE2_IOBIST - * @def TEGRA186_CLK_PCIERX0 - * @def TEGRA186_CLK_PCIERX1 - * @def TEGRA186_CLK_PCIERX2 - * @def TEGRA186_CLK_PCIERX3 - * @def TEGRA186_CLK_PCIERX4 - * @} - */ - -/** @brief output of gate CLK_ENB_FUSE */ -#define TEGRA186_CLK_FUSE 0 -/** - * @brief It's not what you think - * @details output of gate CLK_ENB_GPU. This output connects to the GPU - * pwrclk. @warning: This is almost certainly not the clock you think - * it is. If you're looking for the clock of the graphics engine, see - * TEGRA186_GPCCLK - */ -#define TEGRA186_CLK_GPU 1 -/** @brief output of gate CLK_ENB_PCIE */ -#define TEGRA186_CLK_PCIE 3 -/** @brief output of the divider IPFS_CLK_DIVISOR */ -#define TEGRA186_CLK_AFI 4 -/** @brief output of gate CLK_ENB_PCIE2_IOBIST */ -#define TEGRA186_CLK_PCIE2_IOBIST 5 -/** @brief output of gate CLK_ENB_PCIERX0*/ -#define TEGRA186_CLK_PCIERX0 6 -/** @brief output of gate CLK_ENB_PCIERX1*/ -#define TEGRA186_CLK_PCIERX1 7 -/** @brief output of gate CLK_ENB_PCIERX2*/ -#define TEGRA186_CLK_PCIERX2 8 -/** @brief output of gate CLK_ENB_PCIERX3*/ -#define TEGRA186_CLK_PCIERX3 9 -/** @brief output of gate CLK_ENB_PCIERX4*/ -#define TEGRA186_CLK_PCIERX4 10 -/** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */ -#define TEGRA186_CLK_PLLC_OUT_ISP 11 -/** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */ -#define TEGRA186_CLK_PLLC_OUT_VE 12 -/** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */ -#define TEGRA186_CLK_PLLC_OUT_AON 13 -/** @brief output of gate CLK_ENB_SOR_SAFE */ -#define TEGRA186_CLK_SOR_SAFE 39 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */ -#define TEGRA186_CLK_I2S2 42 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */ -#define TEGRA186_CLK_I2S3 43 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */ -#define TEGRA186_CLK_SPDIF_IN 44 -/** @brief output of gate CLK_ENB_SPDIF_DOUBLER */ -#define TEGRA186_CLK_SPDIF_DOUBLER 45 -/** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */ -#define TEGRA186_CLK_SPI3 46 -/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */ -#define TEGRA186_CLK_I2C1 47 -/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */ -#define TEGRA186_CLK_I2C5 48 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */ -#define TEGRA186_CLK_SPI1 49 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */ -#define TEGRA186_CLK_ISP 50 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */ -#define TEGRA186_CLK_VI 51 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */ -#define TEGRA186_CLK_SDMMC1 52 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */ -#define TEGRA186_CLK_SDMMC2 53 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ -#define TEGRA186_CLK_SDMMC4 54 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ -#define TEGRA186_CLK_UARTA 55 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */ -#define TEGRA186_CLK_UARTB 56 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */ -#define TEGRA186_CLK_HOST1X 57 -/** - * @brief controls the EMC clock frequency. - * @details Doing a clk_set_rate on this clock will select the - * appropriate clock source, program the source rate and execute a - * specific sequence to switch to the new clock source for both memory - * controllers. This can be used to control the balance between memory - * throughput and memory controller power. - */ -#define TEGRA186_CLK_EMC 58 -/* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */ -#define TEGRA186_CLK_EXTPERIPH4 73 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */ -#define TEGRA186_CLK_SPI4 74 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */ -#define TEGRA186_CLK_I2C3 75 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */ -#define TEGRA186_CLK_SDMMC3 76 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */ -#define TEGRA186_CLK_UARTD 77 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */ -#define TEGRA186_CLK_I2S1 79 -/** output of gate CLK_ENB_DTV */ -#define TEGRA186_CLK_DTV 80 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */ -#define TEGRA186_CLK_TSEC 81 -/** @brief output of gate CLK_ENB_DP2 */ -#define TEGRA186_CLK_DP2 82 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */ -#define TEGRA186_CLK_I2S4 84 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */ -#define TEGRA186_CLK_I2S5 85 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */ -#define TEGRA186_CLK_I2C4 86 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */ -#define TEGRA186_CLK_AHUB 87 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */ -#define TEGRA186_CLK_HDA2CODEC_2X 88 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */ -#define TEGRA186_CLK_EXTPERIPH1 89 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */ -#define TEGRA186_CLK_EXTPERIPH2 90 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */ -#define TEGRA186_CLK_EXTPERIPH3 91 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */ -#define TEGRA186_CLK_I2C_SLOW 92 -/** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ -#define TEGRA186_CLK_SOR1 93 -/** @brief output of gate CLK_ENB_CEC */ -#define TEGRA186_CLK_CEC 94 -/** @brief output of gate CLK_ENB_DPAUX1 */ -#define TEGRA186_CLK_DPAUX1 95 -/** @brief output of gate CLK_ENB_DPAUX */ -#define TEGRA186_CLK_DPAUX 96 -/** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ -#define TEGRA186_CLK_SOR0 97 -/** @brief output of gate CLK_ENB_HDA2HDMICODEC */ -#define TEGRA186_CLK_HDA2HDMICODEC 98 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */ -#define TEGRA186_CLK_SATA 99 -/** @brief output of gate CLK_ENB_SATA_OOB */ -#define TEGRA186_CLK_SATA_OOB 100 -/** @brief output of gate CLK_ENB_SATA_IOBIST */ -#define TEGRA186_CLK_SATA_IOBIST 101 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */ -#define TEGRA186_CLK_HDA 102 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */ -#define TEGRA186_CLK_SE 103 -/** @brief output of gate CLK_ENB_APB2APE */ -#define TEGRA186_CLK_APB2APE 104 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */ -#define TEGRA186_CLK_APE 105 -/** @brief output of gate CLK_ENB_IQC1 */ -#define TEGRA186_CLK_IQC1 106 -/** @brief output of gate CLK_ENB_IQC2 */ -#define TEGRA186_CLK_IQC2 107 -/** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */ -#define TEGRA186_CLK_PLLREFE_OUT 108 -/** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */ -#define TEGRA186_CLK_PLLREFE_PLL_REF 109 -/** @brief output of gate CLK_ENB_PLLC4_OUT */ -#define TEGRA186_CLK_PLLC4_OUT 110 -/** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB 111 -/** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_DEV 112 -/** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_HOST 113 -/** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_SS 114 -/** @brief output of gate CLK_ENB_DSI */ -#define TEGRA186_CLK_DSI 115 -/** @brief output of gate CLK_ENB_MIPI_CAL */ -#define TEGRA186_CLK_MIPI_CAL 116 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */ -#define TEGRA186_CLK_DSIA_LP 117 -/** @brief output of gate CLK_ENB_DSIB */ -#define TEGRA186_CLK_DSIB 118 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */ -#define TEGRA186_CLK_DSIB_LP 119 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */ -#define TEGRA186_CLK_DMIC1 122 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */ -#define TEGRA186_CLK_DMIC2 123 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */ -#define TEGRA186_CLK_AUD_MCLK 124 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ -#define TEGRA186_CLK_I2C6 125 -/**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */ -#define TEGRA186_CLK_UART_FST_MIPI_CAL 126 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */ -#define TEGRA186_CLK_VIC 127 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */ -#define TEGRA186_CLK_SDMMC_LEGACY_TM 128 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */ -#define TEGRA186_CLK_NVDEC 129 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */ -#define TEGRA186_CLK_NVJPG 130 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */ -#define TEGRA186_CLK_NVENC 131 -/** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ -#define TEGRA186_CLK_QSPI 132 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */ -#define TEGRA186_CLK_VI_I2C 133 -/** @brief output of gate CLK_ENB_HSIC_TRK */ -#define TEGRA186_CLK_HSIC_TRK 134 -/** @brief output of gate CLK_ENB_USB2_TRK */ -#define TEGRA186_CLK_USB2_TRK 135 -/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */ -#define TEGRA186_CLK_MAUD 136 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */ -#define TEGRA186_CLK_TSECB 137 -/** @brief output of gate CLK_ENB_ADSP */ -#define TEGRA186_CLK_ADSP 138 -/** @brief output of gate CLK_ENB_ADSPNEON */ -#define TEGRA186_CLK_ADSPNEON 139 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */ -#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140 -/** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */ -#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */ -#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142 -/** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */ -#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143 -/** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */ -#define TEGRA186_CLK_MPHY_L0_RX_ANA 144 -/** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */ -#define TEGRA186_CLK_MPHY_L1_RX_ANA 145 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */ -#define TEGRA186_CLK_MPHY_IOBIST 146 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */ -#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */ -#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */ -#define TEGRA186_CLK_AXI_CBB 149 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */ -#define TEGRA186_CLK_DMIC3 150 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */ -#define TEGRA186_CLK_DMIC4 151 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */ -#define TEGRA186_CLK_DSPK1 152 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */ -#define TEGRA186_CLK_DSPK2 153 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */ -#define TEGRA186_CLK_I2S6 154 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */ -#define TEGRA186_CLK_NVDISPLAY_P0 155 -/** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */ -#define TEGRA186_CLK_NVDISPLAY_DISP 156 -/** @brief output of gate CLK_ENB_NVDISPLAY_DSC */ -#define TEGRA186_CLK_NVDISPLAY_DSC 157 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */ -#define TEGRA186_CLK_NVDISPLAYHUB 158 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */ -#define TEGRA186_CLK_NVDISPLAY_P1 159 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */ -#define TEGRA186_CLK_NVDISPLAY_P2 160 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */ -#define TEGRA186_CLK_TACH 166 -/** @brief output of gate CLK_ENB_EQOS */ -#define TEGRA186_CLK_EQOS_AXI 167 -/** @brief output of gate CLK_ENB_EQOS_RX */ -#define TEGRA186_CLK_EQOS_RX 168 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */ -#define TEGRA186_CLK_UFSHC 178 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */ -#define TEGRA186_CLK_UFSDEV_REF 179 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */ -#define TEGRA186_CLK_NVCSI 180 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */ -#define TEGRA186_CLK_NVCSILP 181 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */ -#define TEGRA186_CLK_I2C7 182 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */ -#define TEGRA186_CLK_I2C9 183 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */ -#define TEGRA186_CLK_I2C12 184 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */ -#define TEGRA186_CLK_I2C13 185 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */ -#define TEGRA186_CLK_I2C14 186 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */ -#define TEGRA186_CLK_PWM1 187 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */ -#define TEGRA186_CLK_PWM2 188 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */ -#define TEGRA186_CLK_PWM3 189 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */ -#define TEGRA186_CLK_PWM5 190 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */ -#define TEGRA186_CLK_PWM6 191 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */ -#define TEGRA186_CLK_PWM7 192 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */ -#define TEGRA186_CLK_PWM8 193 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */ -#define TEGRA186_CLK_UARTE 194 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */ -#define TEGRA186_CLK_UARTF 195 -/** @deprecated */ -#define TEGRA186_CLK_DBGAPB 196 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */ -#define TEGRA186_CLK_BPMP_CPU_NIC 197 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */ -#define TEGRA186_CLK_BPMP_APB 199 -/** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */ -#define TEGRA186_CLK_ACTMON 201 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */ -#define TEGRA186_CLK_AON_CPU_NIC 208 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */ -#define TEGRA186_CLK_CAN1 210 -/** @brief output of gate CLK_ENB_CAN1_HOST */ -#define TEGRA186_CLK_CAN1_HOST 211 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */ -#define TEGRA186_CLK_CAN2 212 -/** @brief output of gate CLK_ENB_CAN2_HOST */ -#define TEGRA186_CLK_CAN2_HOST 213 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */ -#define TEGRA186_CLK_AON_APB 214 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */ -#define TEGRA186_CLK_UARTC 215 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */ -#define TEGRA186_CLK_UARTG 216 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */ -#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */ -#define TEGRA186_CLK_I2C2 218 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */ -#define TEGRA186_CLK_I2C8 219 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */ -#define TEGRA186_CLK_I2C10 220 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */ -#define TEGRA186_CLK_AON_I2C_SLOW 221 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */ -#define TEGRA186_CLK_SPI2 222 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */ -#define TEGRA186_CLK_DMIC5 223 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */ -#define TEGRA186_CLK_AON_TOUCH 224 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */ -#define TEGRA186_CLK_PWM4 225 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */ -#define TEGRA186_CLK_TSC 226 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */ -#define TEGRA186_CLK_MSS_ENCRYPT 227 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */ -#define TEGRA186_CLK_SCE_CPU_NIC 228 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */ -#define TEGRA186_CLK_SCE_APB 230 -/** @brief output of gate CLK_ENB_DSIC */ -#define TEGRA186_CLK_DSIC 231 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */ -#define TEGRA186_CLK_DSIC_LP 232 -/** @brief output of gate CLK_ENB_DSID */ -#define TEGRA186_CLK_DSID 233 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */ -#define TEGRA186_CLK_DSID_LP 234 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */ -#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */ -#define TEGRA186_CLK_SPDIF_OUT 238 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */ -#define TEGRA186_CLK_EQOS_PTP_REF 239 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */ -#define TEGRA186_CLK_EQOS_TX 240 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */ -#define TEGRA186_CLK_USB2_HSIC_TRK 241 -/** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_CORE_SS 242 -/** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_CORE_DEV 243 -/** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_FALCON 244 -/** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */ -#define TEGRA186_CLK_XUSB_FS 245 -/** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */ -#define TEGRA186_CLK_PLL_A_OUT0 246 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */ -#define TEGRA186_CLK_SYNC_I2S1 247 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */ -#define TEGRA186_CLK_SYNC_I2S2 248 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */ -#define TEGRA186_CLK_SYNC_I2S3 249 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */ -#define TEGRA186_CLK_SYNC_I2S4 250 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */ -#define TEGRA186_CLK_SYNC_I2S5 251 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */ -#define TEGRA186_CLK_SYNC_I2S6 252 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */ -#define TEGRA186_CLK_SYNC_DSPK1 253 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */ -#define TEGRA186_CLK_SYNC_DSPK2 254 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */ -#define TEGRA186_CLK_SYNC_DMIC1 255 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */ -#define TEGRA186_CLK_SYNC_DMIC2 256 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */ -#define TEGRA186_CLK_SYNC_DMIC3 257 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */ -#define TEGRA186_CLK_SYNC_DMIC4 259 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */ -#define TEGRA186_CLK_SYNC_SPDIF 260 -/** @brief output of gate CLK_ENB_PLLREFE_OUT */ -#define TEGRA186_CLK_PLLREFE_OUT_GATED 261 -/** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs: - * * VCO/pdiv defined by this clock object - * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT - */ -#define TEGRA186_CLK_PLLREFE_OUT1 262 -#define TEGRA186_CLK_PLLD_OUT1 267 -/** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */ -#define TEGRA186_CLK_PLLP_OUT0 269 -/** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */ -#define TEGRA186_CLK_PLLP_OUT5 270 -/** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */ -#define TEGRA186_CLK_PLLA 271 -/** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */ -#define TEGRA186_CLK_ACLK 273 -/** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */ -#define TEGRA186_CLK_PLL_U_48M 274 -/** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */ -#define TEGRA186_CLK_PLL_U_480M 275 -/** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */ -#define TEGRA186_CLK_PLLC4_OUT0 276 -/** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */ -#define TEGRA186_CLK_PLLC4_OUT1 277 -/** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */ -#define TEGRA186_CLK_PLLC4_OUT2 278 -/** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */ -#define TEGRA186_CLK_PLLC4_OUT_MUX 279 -/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ -#define TEGRA186_CLK_DFLLDISP_DIV 284 -/** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */ -#define TEGRA186_CLK_PLLDISPHUB_DIV 285 -/** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */ -#define TEGRA186_CLK_PLLP_DIV8 286 -/** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */ -#define TEGRA186_CLK_BPMP_NIC 287 -/** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */ -#define TEGRA186_CLK_PLL_A_OUT1 288 -/** @deprecated */ -#define TEGRA186_CLK_GPC2CLK 289 -/** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */ -#define TEGRA186_CLK_KFUSE 293 -/** - * @brief controls the PLLE hardware sequencer. - * @details This clock only has enable and disable methods. When the - * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by - * hw based on the control signals from the PCIe, SATA and XUSB - * clocks. When the PLLE hw sequencer is disabled, the state of PLLE - * is controlled by sw using clk_enable/clk_disable on - * TEGRA186_CLK_PLLE. - */ -#define TEGRA186_CLK_PLLE_PWRSEQ 294 -/** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */ -#define TEGRA186_CLK_PLLREFE_REF 295 -/** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */ -#define TEGRA186_CLK_SOR0_OUT 296 -/** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */ -#define TEGRA186_CLK_SOR1_OUT 297 -/** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */ -#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298 -/** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */ -#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */ -#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302 -/** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */ -#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303 -/** @brief controls the UPHY_PLL0 hardware sqeuencer */ -#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304 -/** @brief controls the UPHY_PLL1 hardware sqeuencer */ -#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305 -/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */ -#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306 -/** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */ -#define TEGRA186_CLK_PLLREFE_PEX 307 -/** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */ -#define TEGRA186_CLK_PLLREFE_IDDQ 308 -/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */ -#define TEGRA186_CLK_QSPI_OUT 309 -/** - * @brief GPC2CLK-div-2 - * @details fixed /2 divider. Output frequency is - * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the - * frequency at which the GPU graphics engine runs. */ -#define TEGRA186_CLK_GPCCLK 310 -/** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */ -#define TEGRA186_CLK_AON_NIC 450 -/** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */ -#define TEGRA186_CLK_SCE_NIC 451 -/** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */ -#define TEGRA186_CLK_PLLE 512 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */ -#define TEGRA186_CLK_PLLC 513 -/** Fixed 408MHz PLL for use by peripheral clocks */ -#define TEGRA186_CLK_PLLP 516 -/** @deprecated */ -#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */ -#define TEGRA186_CLK_PLLD 518 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */ -#define TEGRA186_CLK_PLLD2 519 -/** - * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE. - * @details Note that this clock only controls the VCO output, before - * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more - * information. - */ -#define TEGRA186_CLK_PLLREFE_VCO 520 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */ -#define TEGRA186_CLK_PLLC2 521 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */ -#define TEGRA186_CLK_PLLC3 522 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */ -#define TEGRA186_CLK_PLLDP 523 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */ -#define TEGRA186_CLK_PLLC4_VCO 524 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */ -#define TEGRA186_CLK_PLLA1 525 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */ -#define TEGRA186_CLK_PLLNVCSI 526 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */ -#define TEGRA186_CLK_PLLDISPHUB 527 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */ -#define TEGRA186_CLK_PLLD3 528 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */ -#define TEGRA186_CLK_PLLBPMPCAM 531 -/** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */ -#define TEGRA186_CLK_PLLAON 532 -/** Fixed frequency 960MHz PLL for USB and EAVB */ -#define TEGRA186_CLK_PLLU 533 -/** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */ -#define TEGRA186_CLK_PLLC4_VCO_DIV2 535 -/** @brief NAFLL clock source for AXI_CBB */ -#define TEGRA186_CLK_NAFLL_AXI_CBB 564 -/** @brief NAFLL clock source for BPMP */ -#define TEGRA186_CLK_NAFLL_BPMP 565 -/** @brief NAFLL clock source for ISP */ -#define TEGRA186_CLK_NAFLL_ISP 566 -/** @brief NAFLL clock source for NVDEC */ -#define TEGRA186_CLK_NAFLL_NVDEC 567 -/** @brief NAFLL clock source for NVENC */ -#define TEGRA186_CLK_NAFLL_NVENC 568 -/** @brief NAFLL clock source for NVJPG */ -#define TEGRA186_CLK_NAFLL_NVJPG 569 -/** @brief NAFLL clock source for SCE */ -#define TEGRA186_CLK_NAFLL_SCE 570 -/** @brief NAFLL clock source for SE */ -#define TEGRA186_CLK_NAFLL_SE 571 -/** @brief NAFLL clock source for TSEC */ -#define TEGRA186_CLK_NAFLL_TSEC 572 -/** @brief NAFLL clock source for TSECB */ -#define TEGRA186_CLK_NAFLL_TSECB 573 -/** @brief NAFLL clock source for VI */ -#define TEGRA186_CLK_NAFLL_VI 574 -/** @brief NAFLL clock source for VIC */ -#define TEGRA186_CLK_NAFLL_VIC 575 -/** @brief NAFLL clock source for DISP */ -#define TEGRA186_CLK_NAFLL_DISP 576 -/** @brief NAFLL clock source for GPU */ -#define TEGRA186_CLK_NAFLL_GPU 577 -/** @brief NAFLL clock source for M-CPU cluster */ -#define TEGRA186_CLK_NAFLL_MCPU 578 -/** @brief NAFLL clock source for B-CPU cluster */ -#define TEGRA186_CLK_NAFLL_BCPU 579 -/** @brief input from Tegra's CLK_32K_IN pad */ -#define TEGRA186_CLK_CLK_32K 608 -/** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */ -#define TEGRA186_CLK_CLK_M 609 -/** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */ -#define TEGRA186_CLK_PLL_REF 610 -/** @brief input from Tegra's XTAL_IN */ -#define TEGRA186_CLK_OSC 612 -/** @brief clock recovered from EAVB input */ -#define TEGRA186_CLK_EQOS_RX_INPUT 613 -/** @brief clock recovered from DTV input */ -#define TEGRA186_CLK_DTV_INPUT 614 -/** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/ -#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615 -/** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/ -#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616 -/** @brief clock recovered from I2S1 input */ -#define TEGRA186_CLK_I2S1_SYNC_INPUT 617 -/** @brief clock recovered from I2S2 input */ -#define TEGRA186_CLK_I2S2_SYNC_INPUT 618 -/** @brief clock recovered from I2S3 input */ -#define TEGRA186_CLK_I2S3_SYNC_INPUT 619 -/** @brief clock recovered from I2S4 input */ -#define TEGRA186_CLK_I2S4_SYNC_INPUT 620 -/** @brief clock recovered from I2S5 input */ -#define TEGRA186_CLK_I2S5_SYNC_INPUT 621 -/** @brief clock recovered from I2S6 input */ -#define TEGRA186_CLK_I2S6_SYNC_INPUT 622 -/** @brief clock recovered from SPDIFIN input */ -#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623 - -/** - * @brief subject to change - * @details maximum clock identifier value plus one. - */ -#define TEGRA186_CLK_CLK_MAX 624 - -/** @} */ - -#endif diff --git a/include/dt-bindings/dma/at91.h b/include/dt-bindings/dma/at91.h deleted file mode 100644 index 0e7814b0dce..00000000000 --- a/include/dt-bindings/dma/at91.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This header provides macros for at91 dma bindings. - * - * Copyright (C) 2013 Ludovic Desroches - * - * GPLv2 only - */ - -#ifndef __DT_BINDINGS_AT91_DMA_H__ -#define __DT_BINDINGS_AT91_DMA_H__ - -/* ---------- HDMAC ---------- */ - -/* - * Source and/or destination peripheral ID - */ -#define AT91_DMA_CFG_PER_ID_MASK (0xff) -#define AT91_DMA_CFG_PER_ID(id) (id & AT91_DMA_CFG_PER_ID_MASK) - -/* - * FIFO configuration: it defines when a request is serviced. - */ -#define AT91_DMA_CFG_FIFOCFG_OFFSET (8) -#define AT91_DMA_CFG_FIFOCFG_MASK (0xf << AT91_DMA_CFG_FIFOCFG_OFFSET) -#define AT91_DMA_CFG_FIFOCFG_HALF (0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* half FIFO (default behavior) */ -#define AT91_DMA_CFG_FIFOCFG_ALAP (0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* largest defined AHB burst */ -#define AT91_DMA_CFG_FIFOCFG_ASAP (0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET) /* single AHB access */ - -/* ---------- XDMAC ---------- */ -#define AT91_XDMAC_DT_MEM_IF_MASK (0x1) -#define AT91_XDMAC_DT_MEM_IF_OFFSET (13) -#define AT91_XDMAC_DT_MEM_IF(mem_if) (((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \ - << AT91_XDMAC_DT_MEM_IF_OFFSET) -#define AT91_XDMAC_DT_GET_MEM_IF(cfg) (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \ - & AT91_XDMAC_DT_MEM_IF_MASK) - -#define AT91_XDMAC_DT_PER_IF_MASK (0x1) -#define AT91_XDMAC_DT_PER_IF_OFFSET (14) -#define AT91_XDMAC_DT_PER_IF(per_if) (((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \ - << AT91_XDMAC_DT_PER_IF_OFFSET) -#define AT91_XDMAC_DT_GET_PER_IF(cfg) (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \ - & AT91_XDMAC_DT_PER_IF_MASK) - -#define AT91_XDMAC_DT_PERID_MASK (0x7f) -#define AT91_XDMAC_DT_PERID_OFFSET (24) -#define AT91_XDMAC_DT_PERID(perid) (((perid) & AT91_XDMAC_DT_PERID_MASK) \ - << AT91_XDMAC_DT_PERID_OFFSET) -#define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ - & AT91_XDMAC_DT_PERID_MASK) - -#endif /* __DT_BINDINGS_AT91_DMA_H__ */ diff --git a/include/dt-bindings/gpio/aspeed-gpio.h b/include/dt-bindings/gpio/aspeed-gpio.h deleted file mode 100644 index a49f5d5b5af..00000000000 --- a/include/dt-bindings/gpio/aspeed-gpio.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2022 IBM Corp. - * - * This header provides constants for binding aspeed,*-gpio. - * - * The first cell in Aspeed's GPIO specifier is the GPIO ID. The macros below - * provide names for this. - * - * The second cell contains standard flag values specified in gpio.h. - */ - -#ifndef _DT_BINDINGS_GPIO_ASPEED_GPIO_H -#define _DT_BINDINGS_GPIO_ASPEED_GPIO_H - -#include - -#define ASPEED_GPIO_PORT_A 0 -#define ASPEED_GPIO_PORT_B 1 -#define ASPEED_GPIO_PORT_C 2 -#define ASPEED_GPIO_PORT_D 3 -#define ASPEED_GPIO_PORT_E 4 -#define ASPEED_GPIO_PORT_F 5 -#define ASPEED_GPIO_PORT_G 6 -#define ASPEED_GPIO_PORT_H 7 -#define ASPEED_GPIO_PORT_I 8 -#define ASPEED_GPIO_PORT_J 9 -#define ASPEED_GPIO_PORT_K 10 -#define ASPEED_GPIO_PORT_L 11 -#define ASPEED_GPIO_PORT_M 12 -#define ASPEED_GPIO_PORT_N 13 -#define ASPEED_GPIO_PORT_O 14 -#define ASPEED_GPIO_PORT_P 15 -#define ASPEED_GPIO_PORT_Q 16 -#define ASPEED_GPIO_PORT_R 17 -#define ASPEED_GPIO_PORT_S 18 -#define ASPEED_GPIO_PORT_T 19 -#define ASPEED_GPIO_PORT_U 20 -#define ASPEED_GPIO_PORT_V 21 -#define ASPEED_GPIO_PORT_W 22 -#define ASPEED_GPIO_PORT_X 23 -#define ASPEED_GPIO_PORT_Y 24 -#define ASPEED_GPIO_PORT_Z 25 -#define ASPEED_GPIO_PORT_AA 26 -#define ASPEED_GPIO_PORT_AB 27 -#define ASPEED_GPIO_PORT_AC 28 - -#define ASPEED_GPIO(port, offset) \ - ((ASPEED_GPIO_PORT_##port * 8) + (offset)) - -#endif diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h deleted file mode 100644 index a1c09e88e80..00000000000 --- a/include/dt-bindings/gpio/tegra-gpio.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra*-gpio. - * - * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below - * provide names for this. - * - * The second cell contains standard flag values specified in gpio.h. - */ - -#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H -#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H - -#include - -#define TEGRA_GPIO_PORT_A 0 -#define TEGRA_GPIO_PORT_B 1 -#define TEGRA_GPIO_PORT_C 2 -#define TEGRA_GPIO_PORT_D 3 -#define TEGRA_GPIO_PORT_E 4 -#define TEGRA_GPIO_PORT_F 5 -#define TEGRA_GPIO_PORT_G 6 -#define TEGRA_GPIO_PORT_H 7 -#define TEGRA_GPIO_PORT_I 8 -#define TEGRA_GPIO_PORT_J 9 -#define TEGRA_GPIO_PORT_K 10 -#define TEGRA_GPIO_PORT_L 11 -#define TEGRA_GPIO_PORT_M 12 -#define TEGRA_GPIO_PORT_N 13 -#define TEGRA_GPIO_PORT_O 14 -#define TEGRA_GPIO_PORT_P 15 -#define TEGRA_GPIO_PORT_Q 16 -#define TEGRA_GPIO_PORT_R 17 -#define TEGRA_GPIO_PORT_S 18 -#define TEGRA_GPIO_PORT_T 19 -#define TEGRA_GPIO_PORT_U 20 -#define TEGRA_GPIO_PORT_V 21 -#define TEGRA_GPIO_PORT_W 22 -#define TEGRA_GPIO_PORT_X 23 -#define TEGRA_GPIO_PORT_Y 24 -#define TEGRA_GPIO_PORT_Z 25 -#define TEGRA_GPIO_PORT_AA 26 -#define TEGRA_GPIO_PORT_BB 27 -#define TEGRA_GPIO_PORT_CC 28 -#define TEGRA_GPIO_PORT_DD 29 -#define TEGRA_GPIO_PORT_EE 30 -#define TEGRA_GPIO_PORT_FF 31 - -#define TEGRA_GPIO(port, offset) \ - ((TEGRA_GPIO_PORT_##port * 8) + offset) - -#endif diff --git a/include/dt-bindings/media/omap3-isp.h b/include/dt-bindings/media/omap3-isp.h deleted file mode 100644 index 4e420846214..00000000000 --- a/include/dt-bindings/media/omap3-isp.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * include/dt-bindings/media/omap3-isp.h - * - * Copyright (C) 2015 Sakari Ailus - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - */ - -#ifndef __DT_BINDINGS_OMAP3_ISP_H__ -#define __DT_BINDINGS_OMAP3_ISP_H__ - -#define OMAP3ISP_PHY_TYPE_COMPLEX_IO 0 -#define OMAP3ISP_PHY_TYPE_CSIPHY 1 - -#endif /* __DT_BINDINGS_OMAP3_ISP_H__ */ diff --git a/include/dt-bindings/mfd/st,stpmic1.h b/include/dt-bindings/mfd/st,stpmic1.h deleted file mode 100644 index 321cd08797d..00000000000 --- a/include/dt-bindings/mfd/st,stpmic1.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) STMicroelectronics 2018 - All Rights Reserved - * Author: Philippe Peurichard , - * Pascal Paillet for STMicroelectronics. - */ - -#ifndef __DT_BINDINGS_STPMIC1_H__ -#define __DT_BINDINGS_STPMIC1_H__ - -/* IRQ definitions */ -#define IT_PONKEY_F 0 -#define IT_PONKEY_R 1 -#define IT_WAKEUP_F 2 -#define IT_WAKEUP_R 3 -#define IT_VBUS_OTG_F 4 -#define IT_VBUS_OTG_R 5 -#define IT_SWOUT_F 6 -#define IT_SWOUT_R 7 - -#define IT_CURLIM_BUCK1 8 -#define IT_CURLIM_BUCK2 9 -#define IT_CURLIM_BUCK3 10 -#define IT_CURLIM_BUCK4 11 -#define IT_OCP_OTG 12 -#define IT_OCP_SWOUT 13 -#define IT_OCP_BOOST 14 -#define IT_OVP_BOOST 15 - -#define IT_CURLIM_LDO1 16 -#define IT_CURLIM_LDO2 17 -#define IT_CURLIM_LDO3 18 -#define IT_CURLIM_LDO4 19 -#define IT_CURLIM_LDO5 20 -#define IT_CURLIM_LDO6 21 -#define IT_SHORT_SWOTG 22 -#define IT_SHORT_SWOUT 23 - -#define IT_TWARN_F 24 -#define IT_TWARN_R 25 -#define IT_VINLOW_F 26 -#define IT_VINLOW_R 27 -#define IT_SWIN_F 30 -#define IT_SWIN_R 31 - -/* BUCK MODES definitions */ -#define STPMIC1_BUCK_MODE_NORMAL 0 -#define STPMIC1_BUCK_MODE_LP 2 - -#endif /* __DT_BINDINGS_STPMIC1_H__ */ diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h deleted file mode 100644 index 6fc4b445d3a..00000000000 --- a/include/dt-bindings/net/ti-dp83867.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Device Tree constants for the Texas Instruments DP83867 PHY - * - * Author: Dan Murphy - * - * Copyright: (C) 2015 Texas Instruments, Inc. - */ - -#ifndef _DT_BINDINGS_TI_DP83867_H -#define _DT_BINDINGS_TI_DP83867_H - -/* PHY CTRL bits */ -#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 -#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 -#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 -#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 - -/* RGMIIDCTL internal delay for rx and tx */ -#define DP83867_RGMIIDCTL_250_PS 0x0 -#define DP83867_RGMIIDCTL_500_PS 0x1 -#define DP83867_RGMIIDCTL_750_PS 0x2 -#define DP83867_RGMIIDCTL_1_NS 0x3 -#define DP83867_RGMIIDCTL_1_25_NS 0x4 -#define DP83867_RGMIIDCTL_1_50_NS 0x5 -#define DP83867_RGMIIDCTL_1_75_NS 0x6 -#define DP83867_RGMIIDCTL_2_00_NS 0x7 -#define DP83867_RGMIIDCTL_2_25_NS 0x8 -#define DP83867_RGMIIDCTL_2_50_NS 0x9 -#define DP83867_RGMIIDCTL_2_75_NS 0xa -#define DP83867_RGMIIDCTL_3_00_NS 0xb -#define DP83867_RGMIIDCTL_3_25_NS 0xc -#define DP83867_RGMIIDCTL_3_50_NS 0xd -#define DP83867_RGMIIDCTL_3_75_NS 0xe -#define DP83867_RGMIIDCTL_4_00_NS 0xf - -/* IO_MUX_CFG - Clock output selection */ -#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0 -#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1 -#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2 -#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3 -#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4 -#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5 -#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6 -#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7 -#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8 -#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9 -#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA -#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB -#define DP83867_CLK_O_SEL_REF_CLK 0xC -/* Special flag to indicate clock should be off */ -#define DP83867_CLK_O_SEL_OFF 0xFFFFFFFF -#endif diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h deleted file mode 100644 index 765c385f7b2..00000000000 --- a/include/dt-bindings/pinctrl/dra.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This header provides constants for DRA pinctrl bindings. - * - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ - * Author: Rajendra Nayak - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _DT_BINDINGS_PINCTRL_DRA_H -#define _DT_BINDINGS_PINCTRL_DRA_H - -/* DRA7 mux mode options for each pin. See TRM for options */ -#define MUX_MODE0 0x0 -#define MUX_MODE1 0x1 -#define MUX_MODE2 0x2 -#define MUX_MODE3 0x3 -#define MUX_MODE4 0x4 -#define MUX_MODE5 0x5 -#define MUX_MODE6 0x6 -#define MUX_MODE7 0x7 -#define MUX_MODE8 0x8 -#define MUX_MODE9 0x9 -#define MUX_MODE10 0xa -#define MUX_MODE11 0xb -#define MUX_MODE12 0xc -#define MUX_MODE13 0xd -#define MUX_MODE14 0xe -#define MUX_MODE15 0xf - -/* Certain pins need virtual mode, but note: they may glitch */ -#define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4)) -#define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4)) -#define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4)) -#define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4)) -#define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4)) -#define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4)) -#define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4)) -#define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4)) -#define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4)) -#define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4)) -#define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4)) -#define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4)) -#define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4)) -#define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4)) -#define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4)) -#define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4)) - -#define MODE_SELECT (1 << 8) - -#define PULL_ENA (0 << 16) -#define PULL_DIS (1 << 16) -#define PULL_UP (1 << 17) -#define INPUT_EN (1 << 18) -#define SLEWCONTROL (1 << 19) -#define WAKEUP_EN (1 << 24) -#define WAKEUP_EVENT (1 << 25) - -/* Active pin states */ -#define PIN_OUTPUT (0 | PULL_DIS) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN (0) -#define PIN_INPUT (INPUT_EN | PULL_DIS) -#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL) -#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) - -/* - * Macro to allow using the absolute physical address instead of the - * padconf registers instead of the offset from padconf base. - */ -#define DRA7XX_CORE_IOPAD(pa, val) (((pa) & 0xffff) - 0x3400) (val) - -/* DRA7 IODELAY configuration parameters */ -#define A_DELAY_PS(val) ((val) & 0xffff) -#define G_DELAY_PS(val) ((val) & 0xffff) -#endif diff --git a/include/dt-bindings/pinctrl/hisi.h b/include/dt-bindings/pinctrl/hisi.h deleted file mode 100644 index 0359bfdc911..00000000000 --- a/include/dt-bindings/pinctrl/hisi.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This header provides constants for hisilicon pinctrl bindings. - * - * Copyright (c) 2015 Hisilicon Limited. - * Copyright (c) 2015 Linaro Limited. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_PINCTRL_HISI_H -#define _DT_BINDINGS_PINCTRL_HISI_H - -/* iomg bit definition */ -#define MUX_M0 0 -#define MUX_M1 1 -#define MUX_M2 2 -#define MUX_M3 3 -#define MUX_M4 4 -#define MUX_M5 5 -#define MUX_M6 6 -#define MUX_M7 7 - -/* iocg bit definition */ -#define PULL_MASK (3) -#define PULL_DIS (0) -#define PULL_UP (1 << 0) -#define PULL_DOWN (1 << 1) - -/* drive strength definition */ -#define DRIVE_MASK (7 << 4) -#define DRIVE1_02MA (0 << 4) -#define DRIVE1_04MA (1 << 4) -#define DRIVE1_08MA (2 << 4) -#define DRIVE1_10MA (3 << 4) -#define DRIVE2_02MA (0 << 4) -#define DRIVE2_04MA (1 << 4) -#define DRIVE2_08MA (2 << 4) -#define DRIVE2_10MA (3 << 4) -#define DRIVE3_04MA (0 << 4) -#define DRIVE3_08MA (1 << 4) -#define DRIVE3_12MA (2 << 4) -#define DRIVE3_16MA (3 << 4) -#define DRIVE3_20MA (4 << 4) -#define DRIVE3_24MA (5 << 4) -#define DRIVE3_32MA (6 << 4) -#define DRIVE3_40MA (7 << 4) -#define DRIVE4_02MA (0 << 4) -#define DRIVE4_04MA (2 << 4) -#define DRIVE4_08MA (4 << 4) -#define DRIVE4_10MA (6 << 4) - -/* drive strength definition for hi3660 */ -#define DRIVE6_MASK (15 << 4) -#define DRIVE6_04MA (0 << 4) -#define DRIVE6_12MA (4 << 4) -#define DRIVE6_19MA (8 << 4) -#define DRIVE6_27MA (10 << 4) -#define DRIVE6_32MA (15 << 4) -#define DRIVE7_02MA (0 << 4) -#define DRIVE7_04MA (1 << 4) -#define DRIVE7_06MA (2 << 4) -#define DRIVE7_08MA (3 << 4) -#define DRIVE7_10MA (4 << 4) -#define DRIVE7_12MA (5 << 4) -#define DRIVE7_14MA (6 << 4) -#define DRIVE7_16MA (7 << 4) -#endif diff --git a/include/dt-bindings/pinctrl/mt65xx.h b/include/dt-bindings/pinctrl/mt65xx.h deleted file mode 100644 index fbea8d35bcf..00000000000 --- a/include/dt-bindings/pinctrl/mt65xx.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2022 MediaTek Inc. - * Author: Hongzhou.Yang - */ - -#ifndef _DT_BINDINGS_PINCTRL_MT65XX_H -#define _DT_BINDINGS_PINCTRL_MT65XX_H - -#define MTK_PIN_NO(x) ((x) << 8) -#define MTK_GET_PIN_NO(x) ((x) >> 8) -#define MTK_GET_PIN_FUNC(x) ((x) & 0xf) - -#define MTK_PUPD_SET_R1R0_00 100 -#define MTK_PUPD_SET_R1R0_01 101 -#define MTK_PUPD_SET_R1R0_10 102 -#define MTK_PUPD_SET_R1R0_11 103 - -#define MTK_PULL_SET_RSEL_000 200 -#define MTK_PULL_SET_RSEL_001 201 -#define MTK_PULL_SET_RSEL_010 202 -#define MTK_PULL_SET_RSEL_011 203 -#define MTK_PULL_SET_RSEL_100 204 -#define MTK_PULL_SET_RSEL_101 205 -#define MTK_PULL_SET_RSEL_110 206 -#define MTK_PULL_SET_RSEL_111 207 - -#define MTK_DRIVE_2mA 2 -#define MTK_DRIVE_4mA 4 -#define MTK_DRIVE_6mA 6 -#define MTK_DRIVE_8mA 8 -#define MTK_DRIVE_10mA 10 -#define MTK_DRIVE_12mA 12 -#define MTK_DRIVE_14mA 14 -#define MTK_DRIVE_16mA 16 -#define MTK_DRIVE_20mA 20 -#define MTK_DRIVE_24mA 24 -#define MTK_DRIVE_28mA 28 -#define MTK_DRIVE_32mA 32 - -#endif /* _DT_BINDINGS_PINCTRL_MT65XX_H */ diff --git a/include/dt-bindings/pinctrl/omap.h b/include/dt-bindings/pinctrl/omap.h deleted file mode 100644 index 4c060ee0e0a..00000000000 --- a/include/dt-bindings/pinctrl/omap.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for OMAP pinctrl bindings. - * - * Copyright (C) 2009 Nokia - * Copyright (C) 2009-2010 Texas Instruments - */ - -#ifndef _DT_BINDINGS_PINCTRL_OMAP_H -#define _DT_BINDINGS_PINCTRL_OMAP_H - -/* 34xx mux mode options for each pin. See TRM for options */ -#define MUX_MODE0 0 -#define MUX_MODE1 1 -#define MUX_MODE2 2 -#define MUX_MODE3 3 -#define MUX_MODE4 4 -#define MUX_MODE5 5 -#define MUX_MODE6 6 -#define MUX_MODE7 7 - -/* 24xx/34xx mux bit defines */ -#define PULL_ENA (1 << 3) -#define PULL_UP (1 << 4) -#define ALTELECTRICALSEL (1 << 5) - -/* omap3/4/5 specific mux bit defines */ -#define INPUT_EN (1 << 8) -#define OFF_EN (1 << 9) -#define OFFOUT_EN (1 << 10) -#define OFFOUT_VAL (1 << 11) -#define OFF_PULL_EN (1 << 12) -#define OFF_PULL_UP (1 << 13) -#define WAKEUP_EN (1 << 14) -#define WAKEUP_EVENT (1 << 15) - -/* Active pin states */ -#define PIN_OUTPUT 0 -#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP) -#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA) -#define PIN_INPUT INPUT_EN -#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN) - -/* Off mode states */ -#define PIN_OFF_NONE 0 -#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL) -#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN) -#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFFOUT_EN | OFF_PULL_EN | OFF_PULL_UP) -#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFFOUT_EN | OFF_PULL_EN) -#define PIN_OFF_WAKEUPENABLE WAKEUP_EN - -/* - * Macros to allow using the absolute physical address instead of the - * padconf registers instead of the offset from padconf base. - */ -#define OMAP_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset)) - -#define OMAP2420_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0030) (val) -#define OMAP2430_CORE_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) -#define OMAP3_CORE1_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2030) (val) -#define OMAP3430_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25d8) (val) -#define OMAP3630_CORE2_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x25a0) (val) -#define OMAP3_WKUP_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x2a00) (val) -#define DM814X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define DM816X_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) -#define AM33XX_IOPAD(pa, val) OMAP_IOPAD_OFFSET((pa), 0x0800) (val) (0) -#define AM33XX_PADCONF(pa, conf, mux) OMAP_IOPAD_OFFSET((pa), 0x0800) (conf) (mux) - -/* - * Macros to allow using the offset from the padconf physical address - * instead of the offset from padconf base. - */ -#define OMAP_PADCONF_OFFSET(offset, base_offset) ((offset) - (base_offset)) - -#define OMAP4_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) -#define OMAP5_IOPAD(offset, val) OMAP_PADCONF_OFFSET((offset), 0x0040) (val) - -/* - * Define some commonly used pins configured by the boards. - * Note that some boards use alternative pins, so check - * the schematics before using these. - */ -#define OMAP3_UART1_RX 0x152 -#define OMAP3_UART2_RX 0x14a -#define OMAP3_UART3_RX 0x16e -#define OMAP4_UART2_RX 0xdc -#define OMAP4_UART3_RX 0x104 -#define OMAP4_UART4_RX 0x11c - -#endif diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h b/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h deleted file mode 100644 index 914d56da932..00000000000 --- a/include/dt-bindings/pinctrl/pinctrl-tegra-xusb.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H -#define _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H 1 - -#define TEGRA_XUSB_PADCTL_PCIE 0 -#define TEGRA_XUSB_PADCTL_SATA 1 - -#endif /* _DT_BINDINGS_PINCTRL_TEGRA_XUSB_H */ diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h deleted file mode 100644 index c9b57408de6..00000000000 --- a/include/dt-bindings/pinctrl/pinctrl-tegra.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * This header provides constants for Tegra pinctrl bindings. - * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * Author: Laxman Dewangan - */ - -#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H -#define _DT_BINDINGS_PINCTRL_TEGRA_H - -/* - * Enable/disable for diffeent dt properties. This is applicable for - * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, - * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. - */ -#define TEGRA_PIN_DISABLE 0 -#define TEGRA_PIN_ENABLE 1 - -#define TEGRA_PIN_PULL_NONE 0 -#define TEGRA_PIN_PULL_DOWN 1 -#define TEGRA_PIN_PULL_UP 2 - -/* Low power mode driver */ -#define TEGRA_PIN_LP_DRIVE_DIV_8 0 -#define TEGRA_PIN_LP_DRIVE_DIV_4 1 -#define TEGRA_PIN_LP_DRIVE_DIV_2 2 -#define TEGRA_PIN_LP_DRIVE_DIV_1 3 - -/* Rising/Falling slew rate */ -#define TEGRA_PIN_SLEW_RATE_FASTEST 0 -#define TEGRA_PIN_SLEW_RATE_FAST 1 -#define TEGRA_PIN_SLEW_RATE_SLOW 2 -#define TEGRA_PIN_SLEW_RATE_SLOWEST 3 - -#endif diff --git a/include/dt-bindings/pinctrl/r7s72100-pinctrl.h b/include/dt-bindings/pinctrl/r7s72100-pinctrl.h deleted file mode 100644 index 31ee37610eb..00000000000 --- a/include/dt-bindings/pinctrl/r7s72100-pinctrl.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Defines macros and constants for Renesas RZ/A1 pin controller pin - * muxing functions. - */ -#ifndef __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H -#define __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H - -#define RZA1_PINS_PER_PORT 16 - -/* - * Create the pin index from its bank and position numbers and store in - * the upper 16 bits the alternate function identifier - */ -#define RZA1_PINMUX(b, p, f) \ - ((b) * RZA1_PINS_PER_PORT + (p) | ((f) << 16)) - -#endif /* __DT_BINDINGS_PINCTRL_RENESAS_RZA1_H */ diff --git a/include/dt-bindings/power/raspberrypi-power.h b/include/dt-bindings/power/raspberrypi-power.h deleted file mode 100644 index b3ff8e09a78..00000000000 --- a/include/dt-bindings/power/raspberrypi-power.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright © 2015 Broadcom - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H -#define _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H - -/* These power domain indices are the firmware interface's indices - * minus one. - */ -#define RPI_POWER_DOMAIN_I2C0 0 -#define RPI_POWER_DOMAIN_I2C1 1 -#define RPI_POWER_DOMAIN_I2C2 2 -#define RPI_POWER_DOMAIN_VIDEO_SCALER 3 -#define RPI_POWER_DOMAIN_VPU1 4 -#define RPI_POWER_DOMAIN_HDMI 5 -#define RPI_POWER_DOMAIN_USB 6 -#define RPI_POWER_DOMAIN_VEC 7 -#define RPI_POWER_DOMAIN_JPEG 8 -#define RPI_POWER_DOMAIN_H264 9 -#define RPI_POWER_DOMAIN_V3D 10 -#define RPI_POWER_DOMAIN_ISP 11 -#define RPI_POWER_DOMAIN_UNICAM0 12 -#define RPI_POWER_DOMAIN_UNICAM1 13 -#define RPI_POWER_DOMAIN_CCP2RX 14 -#define RPI_POWER_DOMAIN_CSI2 15 -#define RPI_POWER_DOMAIN_CPI 16 -#define RPI_POWER_DOMAIN_DSI0 17 -#define RPI_POWER_DOMAIN_DSI1 18 -#define RPI_POWER_DOMAIN_TRANSPOSER 19 -#define RPI_POWER_DOMAIN_CCP2TX 20 -#define RPI_POWER_DOMAIN_CDP 21 -#define RPI_POWER_DOMAIN_ARM 22 - -#define RPI_POWER_DOMAIN_COUNT 23 - -#endif /* _DT_BINDINGS_ARM_BCM2835_RPI_POWER_H */ diff --git a/include/dt-bindings/power/tegra186-powergate.h b/include/dt-bindings/power/tegra186-powergate.h deleted file mode 100644 index 17e75498563..00000000000 --- a/include/dt-bindings/power/tegra186-powergate.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2015-2016, NVIDIA CORPORATION. - */ - -#ifndef _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H -#define _DT_BINDINGS_POWER_TEGRA186_POWERGATE_H - -#define TEGRA186_POWER_DOMAIN_AUD 0 -#define TEGRA186_POWER_DOMAIN_DFD 1 -#define TEGRA186_POWER_DOMAIN_DISP 2 -#define TEGRA186_POWER_DOMAIN_DISPB 3 -#define TEGRA186_POWER_DOMAIN_DISPC 4 -#define TEGRA186_POWER_DOMAIN_ISPA 5 -#define TEGRA186_POWER_DOMAIN_NVDEC 6 -#define TEGRA186_POWER_DOMAIN_NVJPG 7 -#define TEGRA186_POWER_DOMAIN_MPE 8 -#define TEGRA186_POWER_DOMAIN_PCX 9 -#define TEGRA186_POWER_DOMAIN_SAX 10 -#define TEGRA186_POWER_DOMAIN_VE 11 -#define TEGRA186_POWER_DOMAIN_VIC 12 -#define TEGRA186_POWER_DOMAIN_XUSBA 13 -#define TEGRA186_POWER_DOMAIN_XUSBB 14 -#define TEGRA186_POWER_DOMAIN_XUSBC 15 -#define TEGRA186_POWER_DOMAIN_GPU 43 -#define TEGRA186_POWER_DOMAIN_MAX 44 - -#endif diff --git a/include/dt-bindings/regulator/maxim,max77802.h b/include/dt-bindings/regulator/maxim,max77802.h deleted file mode 100644 index cf28631d710..00000000000 --- a/include/dt-bindings/regulator/maxim,max77802.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants for the Maxim 77802 PMIC regulators - */ - -#ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H -#define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H - -/* Regulator operating modes */ -#define MAX77802_OPMODE_LP 1 -#define MAX77802_OPMODE_NORMAL 3 - -#endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */ diff --git a/include/dt-bindings/reset/altr,rst-mgr-a10.h b/include/dt-bindings/reset/altr,rst-mgr-a10.h deleted file mode 100644 index acb0bbf4f9f..00000000000 --- a/include/dt-bindings/reset/altr,rst-mgr-a10.h +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2014, Steffen Trumtrar - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H - -/* MPUMODRST */ -#define CPU0_RESET 0 -#define CPU1_RESET 1 -#define WDS_RESET 2 -#define SCUPER_RESET 3 - -/* PER0MODRST */ -#define EMAC0_RESET 32 -#define EMAC1_RESET 33 -#define EMAC2_RESET 34 -#define USB0_RESET 35 -#define USB1_RESET 36 -#define NAND_RESET 37 -#define QSPI_RESET 38 -#define SDMMC_RESET 39 -#define EMAC0_OCP_RESET 40 -#define EMAC1_OCP_RESET 41 -#define EMAC2_OCP_RESET 42 -#define USB0_OCP_RESET 43 -#define USB1_OCP_RESET 44 -#define NAND_OCP_RESET 45 -#define QSPI_OCP_RESET 46 -#define SDMMC_OCP_RESET 47 -#define DMA_RESET 48 -#define SPIM0_RESET 49 -#define SPIM1_RESET 50 -#define SPIS0_RESET 51 -#define SPIS1_RESET 52 -#define DMA_OCP_RESET 53 -#define EMAC_PTP_RESET 54 -/* 55 is empty*/ -#define DMAIF0_RESET 56 -#define DMAIF1_RESET 57 -#define DMAIF2_RESET 58 -#define DMAIF3_RESET 59 -#define DMAIF4_RESET 60 -#define DMAIF5_RESET 61 -#define DMAIF6_RESET 62 -#define DMAIF7_RESET 63 - -/* PER1MODRST */ -#define L4WD0_RESET 64 -#define L4WD1_RESET 65 -#define L4SYSTIMER0_RESET 66 -#define L4SYSTIMER1_RESET 67 -#define SPTIMER0_RESET 68 -#define SPTIMER1_RESET 69 -/* 70-71 is reserved */ -#define I2C0_RESET 72 -#define I2C1_RESET 73 -#define I2C2_RESET 74 -#define I2C3_RESET 75 -#define I2C4_RESET 76 -/* 77-79 is reserved */ -#define UART0_RESET 80 -#define UART1_RESET 81 -/* 82-87 is reserved */ -#define GPIO0_RESET 88 -#define GPIO1_RESET 89 -#define GPIO2_RESET 90 - -/* BRGMODRST */ -#define HPS2FPGA_RESET 96 -#define LWHPS2FPGA_RESET 97 -#define FPGA2HPS_RESET 98 -#define F2SSDRAM0_RESET 99 -#define F2SSDRAM1_RESET 100 -#define F2SSDRAM2_RESET 101 -#define DDRSCH_RESET 102 - -/* SYSMODRST*/ -#define ROM_RESET 128 -#define OCRAM_RESET 129 -/* 130 is reserved */ -#define FPGAMGR_RESET 131 -#define S2F_RESET 132 -#define SYSDBG_RESET 133 -#define OCRAM_OCP_RESET 134 - -/* COLDMODRST */ -#define CLKMGRCOLD_RESET 160 -/* 161-162 is reserved */ -#define S2FCOLD_RESET 163 -#define TIMESTAMPCOLD_RESET 164 -#define TAPCOLD_RESET 165 -#define HMCCOLD_RESET 166 -#define IOMGRCOLD_RESET 167 - -/* NRSTMODRST */ -#define NRSTPINOE_RESET 192 - -/* DBGMODRST */ -#define DBG_RESET 224 -#endif diff --git a/include/dt-bindings/reset/altr,rst-mgr.h b/include/dt-bindings/reset/altr,rst-mgr.h deleted file mode 100644 index 5b7ad739652..00000000000 --- a/include/dt-bindings/reset/altr,rst-mgr.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2014, Steffen Trumtrar - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_H - -/* MPUMODRST */ -#define CPU0_RESET 0 -#define CPU1_RESET 1 -#define WDS_RESET 2 -#define SCUPER_RESET 3 -#define L2_RESET 4 - -/* PERMODRST */ -#define EMAC0_RESET 32 -#define EMAC1_RESET 33 -#define USB0_RESET 34 -#define USB1_RESET 35 -#define NAND_RESET 36 -#define QSPI_RESET 37 -#define L4WD0_RESET 38 -#define L4WD1_RESET 39 -#define OSC1TIMER0_RESET 40 -#define OSC1TIMER1_RESET 41 -#define SPTIMER0_RESET 42 -#define SPTIMER1_RESET 43 -#define I2C0_RESET 44 -#define I2C1_RESET 45 -#define I2C2_RESET 46 -#define I2C3_RESET 47 -#define UART0_RESET 48 -#define UART1_RESET 49 -#define SPIM0_RESET 50 -#define SPIM1_RESET 51 -#define SPIS0_RESET 52 -#define SPIS1_RESET 53 -#define SDMMC_RESET 54 -#define CAN0_RESET 55 -#define CAN1_RESET 56 -#define GPIO0_RESET 57 -#define GPIO1_RESET 58 -#define GPIO2_RESET 59 -#define DMA_RESET 60 -#define SDR_RESET 61 - -/* PER2MODRST */ -#define DMAIF0_RESET 64 -#define DMAIF1_RESET 65 -#define DMAIF2_RESET 66 -#define DMAIF3_RESET 67 -#define DMAIF4_RESET 68 -#define DMAIF5_RESET 69 -#define DMAIF6_RESET 70 -#define DMAIF7_RESET 71 - -/* BRGMODRST */ -#define HPS2FPGA_RESET 96 -#define LWHPS2FPGA_RESET 97 -#define FPGA2HPS_RESET 98 - -/* MISCMODRST*/ -#define ROM_RESET 128 -#define OCRAM_RESET 129 -#define SYSMGR_RESET 130 -#define SYSMGRCOLD_RESET 131 -#define FPGAMGR_RESET 132 -#define ACPIDMAP_RESET 133 -#define S2F_RESET 134 -#define S2FCOLD_RESET 135 -#define NRSTPIN_RESET 136 -#define TIMESTAMPCOLD_RESET 137 -#define CLKMGRCOLD_RESET 138 -#define SCANMGR_RESET 139 -#define FRZCTRLCOLD_RESET 140 -#define SYSDBG_RESET 141 -#define DBG_RESET 142 -#define TAPCOLD_RESET 143 -#define SDRCOLD_RESET 144 - -#endif diff --git a/include/dt-bindings/reset/bcm6328-reset.h b/include/dt-bindings/reset/bcm6328-reset.h deleted file mode 100644 index f2dd4f79cc6..00000000000 --- a/include/dt-bindings/reset/bcm6328-reset.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - * - * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h - */ - -#ifndef __DT_BINDINGS_RESET_BCM6328_H -#define __DT_BINDINGS_RESET_BCM6328_H - -#define BCM6328_RST_SPI 0 -#define BCM6328_RST_EPHY 1 -#define BCM6328_RST_SAR 2 -#define BCM6328_RST_ENETSW 3 -#define BCM6328_RST_USBS 4 -#define BCM6328_RST_USBH 5 -#define BCM6328_RST_PCM 6 -#define BCM6328_RST_PCIE_CORE 7 -#define BCM6328_RST_PCIE 8 -#define BCM6328_RST_PCIE_EXT 9 -#define BCM6328_RST_PCIE_HARD 10 - -#endif /* __DT_BINDINGS_RESET_BCM6328_H */ diff --git a/include/dt-bindings/reset/bcm6358-reset.h b/include/dt-bindings/reset/bcm6358-reset.h deleted file mode 100644 index 075706eff7a..00000000000 --- a/include/dt-bindings/reset/bcm6358-reset.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - * - * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h - */ - -#ifndef __DT_BINDINGS_RESET_BCM6358_H -#define __DT_BINDINGS_RESET_BCM6358_H - -#define BCM6358_RST_SPI 0 -#define BCM6358_RST_ENET 2 -#define BCM6358_RST_MPI 3 -#define BCM6358_RST_EPHY 6 -#define BCM6358_RST_SAR 7 -#define BCM6358_RST_USBH 12 -#define BCM6358_RST_PCM 13 -#define BCM6358_RST_ADSL 14 - -#endif /* __DT_BINDINGS_RESET_BCM6358_H */ diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h deleted file mode 100644 index 8202e499190..00000000000 --- a/include/dt-bindings/reset/bcm6362-reset.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Álvaro Fernández Rojas - * - * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h - */ - -#ifndef __DT_BINDINGS_RESET_BCM6362_H -#define __DT_BINDINGS_RESET_BCM6362_H - -#define BCM6362_RST_SPI 0 -#define BCM6362_RST_IPSEC 1 -#define BCM6362_RST_EPHY 2 -#define BCM6362_RST_SAR 3 -#define BCM6362_RST_ENETSW 4 -#define BCM6362_RST_USBD 5 -#define BCM6362_RST_USBH 6 -#define BCM6362_RST_PCM 7 -#define BCM6362_RST_PCIE_CORE 8 -#define BCM6362_RST_PCIE 9 -#define BCM6362_RST_PCIE_EXT 10 -#define BCM6362_RST_WLAN_SHIM 11 -#define BCM6362_RST_DDR_PHY 12 -#define BCM6362_RST_FAP 13 -#define BCM6362_RST_WLAN_UBUS 14 - -#endif /* __DT_BINDINGS_RESET_BCM6362_H */ diff --git a/include/dt-bindings/reset/bcm6368-reset.h b/include/dt-bindings/reset/bcm6368-reset.h deleted file mode 100644 index 0038a7ccf5c..00000000000 --- a/include/dt-bindings/reset/bcm6368-reset.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - * - * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h - */ - -#ifndef __DT_BINDINGS_RESET_BCM6368_H -#define __DT_BINDINGS_RESET_BCM6368_H - -#define BCM6368_RST_SPI 0 -#define BCM6368_RST_MPI 3 -#define BCM6368_RST_IPSEC 4 -#define BCM6368_RST_EPHY 6 -#define BCM6368_RST_SAR 7 -#define BCM6368_RST_SWITCH 10 -#define BCM6368_RST_USBD 11 -#define BCM6368_RST_USBH 12 -#define BCM6368_RST_PCM 13 - -#endif /* __DT_BINDINGS_RESET_BCM6368_H */ diff --git a/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h b/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h deleted file mode 100644 index 757f5e34c81..00000000000 --- a/include/dt-bindings/reset/nuvoton,npcm7xx-reset.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -// Copyright (c) 2020 Nuvoton Technology corporation. - -#ifndef _DT_BINDINGS_NPCM7XX_RESET_H -#define _DT_BINDINGS_NPCM7XX_RESET_H - -#define NPCM7XX_RESET_IPSRST1 0x20 -#define NPCM7XX_RESET_IPSRST2 0x24 -#define NPCM7XX_RESET_IPSRST3 0x34 - -/* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */ -#define NPCM7XX_RESET_FIU3 1 -#define NPCM7XX_RESET_UDC1 5 -#define NPCM7XX_RESET_EMC1 6 -#define NPCM7XX_RESET_UART_2_3 7 -#define NPCM7XX_RESET_UDC2 8 -#define NPCM7XX_RESET_PECI 9 -#define NPCM7XX_RESET_AES 10 -#define NPCM7XX_RESET_UART_0_1 11 -#define NPCM7XX_RESET_MC 12 -#define NPCM7XX_RESET_SMB2 13 -#define NPCM7XX_RESET_SMB3 14 -#define NPCM7XX_RESET_SMB4 15 -#define NPCM7XX_RESET_SMB5 16 -#define NPCM7XX_RESET_PWM_M0 18 -#define NPCM7XX_RESET_TIMER_0_4 19 -#define NPCM7XX_RESET_TIMER_5_9 20 -#define NPCM7XX_RESET_EMC2 21 -#define NPCM7XX_RESET_UDC4 22 -#define NPCM7XX_RESET_UDC5 23 -#define NPCM7XX_RESET_UDC6 24 -#define NPCM7XX_RESET_UDC3 25 -#define NPCM7XX_RESET_ADC 27 -#define NPCM7XX_RESET_SMB6 28 -#define NPCM7XX_RESET_SMB7 29 -#define NPCM7XX_RESET_SMB0 30 -#define NPCM7XX_RESET_SMB1 31 - -/* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */ -#define NPCM7XX_RESET_MFT0 0 -#define NPCM7XX_RESET_MFT1 1 -#define NPCM7XX_RESET_MFT2 2 -#define NPCM7XX_RESET_MFT3 3 -#define NPCM7XX_RESET_MFT4 4 -#define NPCM7XX_RESET_MFT5 5 -#define NPCM7XX_RESET_MFT6 6 -#define NPCM7XX_RESET_MFT7 7 -#define NPCM7XX_RESET_MMC 8 -#define NPCM7XX_RESET_SDHC 9 -#define NPCM7XX_RESET_GFX_SYS 10 -#define NPCM7XX_RESET_AHB_PCIBRG 11 -#define NPCM7XX_RESET_VDMA 12 -#define NPCM7XX_RESET_ECE 13 -#define NPCM7XX_RESET_VCD 14 -#define NPCM7XX_RESET_OTP 16 -#define NPCM7XX_RESET_SIOX1 18 -#define NPCM7XX_RESET_SIOX2 19 -#define NPCM7XX_RESET_3DES 21 -#define NPCM7XX_RESET_PSPI1 22 -#define NPCM7XX_RESET_PSPI2 23 -#define NPCM7XX_RESET_GMAC2 25 -#define NPCM7XX_RESET_USB_HOST 26 -#define NPCM7XX_RESET_GMAC1 28 -#define NPCM7XX_RESET_CP 31 - -/* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */ -#define NPCM7XX_RESET_PWM_M1 0 -#define NPCM7XX_RESET_SMB12 1 -#define NPCM7XX_RESET_SPIX 2 -#define NPCM7XX_RESET_SMB13 3 -#define NPCM7XX_RESET_UDC0 4 -#define NPCM7XX_RESET_UDC7 5 -#define NPCM7XX_RESET_UDC8 6 -#define NPCM7XX_RESET_UDC9 7 -#define NPCM7XX_RESET_PCI_MAILBOX 9 -#define NPCM7XX_RESET_SMB14 12 -#define NPCM7XX_RESET_SHA 13 -#define NPCM7XX_RESET_SEC_ECC 14 -#define NPCM7XX_RESET_PCIE_RC 15 -#define NPCM7XX_RESET_TIMER_10_14 16 -#define NPCM7XX_RESET_RNG 17 -#define NPCM7XX_RESET_SMB15 18 -#define NPCM7XX_RESET_SMB8 19 -#define NPCM7XX_RESET_SMB9 20 -#define NPCM7XX_RESET_SMB10 21 -#define NPCM7XX_RESET_SMB11 22 -#define NPCM7XX_RESET_ESPI 23 -#define NPCM7XX_RESET_USB_PHY_1 24 -#define NPCM7XX_RESET_USB_PHY_2 25 - -#endif diff --git a/include/dt-bindings/reset/tegra124-car.h b/include/dt-bindings/reset/tegra124-car.h deleted file mode 100644 index 070e4f6e748..00000000000 --- a/include/dt-bindings/reset/tegra124-car.h +++ /dev/null @@ -1,12 +0,0 @@ -/* - * This header provides Tegra124-specific constants for binding - * nvidia,tegra124-car. - */ - -#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H -#define _DT_BINDINGS_RESET_TEGRA124_CAR_H - -#define TEGRA124_RESET(x) (6 * 32 + (x)) -#define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0) - -#endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */ diff --git a/include/dt-bindings/reset/tegra186-reset.h b/include/dt-bindings/reset/tegra186-reset.h deleted file mode 100644 index 7efec920053..00000000000 --- a/include/dt-bindings/reset/tegra186-reset.h +++ /dev/null @@ -1,205 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. - */ - -#ifndef _ABI_MACH_T186_RESET_T186_H_ -#define _ABI_MACH_T186_RESET_T186_H_ - -#define TEGRA186_RESET_ACTMON 0 -#define TEGRA186_RESET_AFI 1 -#define TEGRA186_RESET_CEC 2 -#define TEGRA186_RESET_CSITE 3 -#define TEGRA186_RESET_DP2 4 -#define TEGRA186_RESET_DPAUX 5 -#define TEGRA186_RESET_DSI 6 -#define TEGRA186_RESET_DSIB 7 -#define TEGRA186_RESET_DTV 8 -#define TEGRA186_RESET_DVFS 9 -#define TEGRA186_RESET_ENTROPY 10 -#define TEGRA186_RESET_EXTPERIPH1 11 -#define TEGRA186_RESET_EXTPERIPH2 12 -#define TEGRA186_RESET_EXTPERIPH3 13 -#define TEGRA186_RESET_GPU 14 -#define TEGRA186_RESET_HDA 15 -#define TEGRA186_RESET_HDA2CODEC_2X 16 -#define TEGRA186_RESET_HDA2HDMICODEC 17 -#define TEGRA186_RESET_HOST1X 18 -#define TEGRA186_RESET_I2C1 19 -#define TEGRA186_RESET_I2C2 20 -#define TEGRA186_RESET_I2C3 21 -#define TEGRA186_RESET_I2C4 22 -#define TEGRA186_RESET_I2C5 23 -#define TEGRA186_RESET_I2C6 24 -#define TEGRA186_RESET_ISP 25 -#define TEGRA186_RESET_KFUSE 26 -#define TEGRA186_RESET_LA 27 -#define TEGRA186_RESET_MIPI_CAL 28 -#define TEGRA186_RESET_PCIE 29 -#define TEGRA186_RESET_PCIEXCLK 30 -#define TEGRA186_RESET_SATA 31 -#define TEGRA186_RESET_SATACOLD 32 -#define TEGRA186_RESET_SDMMC1 33 -#define TEGRA186_RESET_SDMMC2 34 -#define TEGRA186_RESET_SDMMC3 35 -#define TEGRA186_RESET_SDMMC4 36 -#define TEGRA186_RESET_SE 37 -#define TEGRA186_RESET_SOC_THERM 38 -#define TEGRA186_RESET_SOR0 39 -#define TEGRA186_RESET_SPI1 40 -#define TEGRA186_RESET_SPI2 41 -#define TEGRA186_RESET_SPI3 42 -#define TEGRA186_RESET_SPI4 43 -#define TEGRA186_RESET_TMR 44 -#define TEGRA186_RESET_TRIG_SYS 45 -#define TEGRA186_RESET_TSEC 46 -#define TEGRA186_RESET_UARTA 47 -#define TEGRA186_RESET_UARTB 48 -#define TEGRA186_RESET_UARTC 49 -#define TEGRA186_RESET_UARTD 50 -#define TEGRA186_RESET_VI 51 -#define TEGRA186_RESET_VIC 52 -#define TEGRA186_RESET_XUSB_DEV 53 -#define TEGRA186_RESET_XUSB_HOST 54 -#define TEGRA186_RESET_XUSB_PADCTL 55 -#define TEGRA186_RESET_XUSB_SS 56 -#define TEGRA186_RESET_AON_APB 57 -#define TEGRA186_RESET_AXI_CBB 58 -#define TEGRA186_RESET_BPMP_APB 59 -#define TEGRA186_RESET_CAN1 60 -#define TEGRA186_RESET_CAN2 61 -#define TEGRA186_RESET_DMIC5 62 -#define TEGRA186_RESET_DSIC 63 -#define TEGRA186_RESET_DSID 64 -#define TEGRA186_RESET_EMC_EMC 65 -#define TEGRA186_RESET_EMC_MEM 66 -#define TEGRA186_RESET_EMCSB_EMC 67 -#define TEGRA186_RESET_EMCSB_MEM 68 -#define TEGRA186_RESET_EQOS 69 -#define TEGRA186_RESET_GPCDMA 70 -#define TEGRA186_RESET_GPIO_CTL0 71 -#define TEGRA186_RESET_GPIO_CTL1 72 -#define TEGRA186_RESET_GPIO_CTL2 73 -#define TEGRA186_RESET_GPIO_CTL3 74 -#define TEGRA186_RESET_GPIO_CTL4 75 -#define TEGRA186_RESET_GPIO_CTL5 76 -#define TEGRA186_RESET_I2C10 77 -#define TEGRA186_RESET_I2C12 78 -#define TEGRA186_RESET_I2C13 79 -#define TEGRA186_RESET_I2C14 80 -#define TEGRA186_RESET_I2C7 81 -#define TEGRA186_RESET_I2C8 82 -#define TEGRA186_RESET_I2C9 83 -#define TEGRA186_RESET_JTAG2AXI 84 -#define TEGRA186_RESET_MPHY_IOBIST 85 -#define TEGRA186_RESET_MPHY_L0_RX 86 -#define TEGRA186_RESET_MPHY_L0_TX 87 -#define TEGRA186_RESET_NVCSI 88 -#define TEGRA186_RESET_NVDISPLAY0_HEAD0 89 -#define TEGRA186_RESET_NVDISPLAY0_HEAD1 90 -#define TEGRA186_RESET_NVDISPLAY0_HEAD2 91 -#define TEGRA186_RESET_NVDISPLAY0_MISC 92 -#define TEGRA186_RESET_NVDISPLAY0_WGRP0 93 -#define TEGRA186_RESET_NVDISPLAY0_WGRP1 94 -#define TEGRA186_RESET_NVDISPLAY0_WGRP2 95 -#define TEGRA186_RESET_NVDISPLAY0_WGRP3 96 -#define TEGRA186_RESET_NVDISPLAY0_WGRP4 97 -#define TEGRA186_RESET_NVDISPLAY0_WGRP5 98 -#define TEGRA186_RESET_PWM1 99 -#define TEGRA186_RESET_PWM2 100 -#define TEGRA186_RESET_PWM3 101 -#define TEGRA186_RESET_PWM4 102 -#define TEGRA186_RESET_PWM5 103 -#define TEGRA186_RESET_PWM6 104 -#define TEGRA186_RESET_PWM7 105 -#define TEGRA186_RESET_PWM8 106 -#define TEGRA186_RESET_SCE_APB 107 -#define TEGRA186_RESET_SOR1 108 -#define TEGRA186_RESET_TACH 109 -#define TEGRA186_RESET_TSC 110 -#define TEGRA186_RESET_UARTF 111 -#define TEGRA186_RESET_UARTG 112 -#define TEGRA186_RESET_UFSHC 113 -#define TEGRA186_RESET_UFSHC_AXI_M 114 -#define TEGRA186_RESET_UPHY 115 -#define TEGRA186_RESET_ADSP 116 -#define TEGRA186_RESET_ADSPDBG 117 -#define TEGRA186_RESET_ADSPINTF 118 -#define TEGRA186_RESET_ADSPNEON 119 -#define TEGRA186_RESET_ADSPPERIPH 120 -#define TEGRA186_RESET_ADSPSCU 121 -#define TEGRA186_RESET_ADSPWDT 122 -#define TEGRA186_RESET_APE 123 -#define TEGRA186_RESET_DPAUX1 124 -#define TEGRA186_RESET_NVDEC 125 -#define TEGRA186_RESET_NVENC 126 -#define TEGRA186_RESET_NVJPG 127 -#define TEGRA186_RESET_PEX_USB_UPHY 128 -#define TEGRA186_RESET_QSPI 129 -#define TEGRA186_RESET_TSECB 130 -#define TEGRA186_RESET_VI_I2C 131 -#define TEGRA186_RESET_UARTE 132 -#define TEGRA186_RESET_TOP_GTE 133 -#define TEGRA186_RESET_SHSP 134 -#define TEGRA186_RESET_PEX_USB_UPHY_L5 135 -#define TEGRA186_RESET_PEX_USB_UPHY_L4 136 -#define TEGRA186_RESET_PEX_USB_UPHY_L3 137 -#define TEGRA186_RESET_PEX_USB_UPHY_L2 138 -#define TEGRA186_RESET_PEX_USB_UPHY_L1 139 -#define TEGRA186_RESET_PEX_USB_UPHY_L0 140 -#define TEGRA186_RESET_PEX_USB_UPHY_PLL1 141 -#define TEGRA186_RESET_PEX_USB_UPHY_PLL0 142 -#define TEGRA186_RESET_TSCTNVI 143 -#define TEGRA186_RESET_EXTPERIPH4 144 -#define TEGRA186_RESET_DSIPADCTL 145 -#define TEGRA186_RESET_AUD_MCLK 146 -#define TEGRA186_RESET_MPHY_CLK_CTL 147 -#define TEGRA186_RESET_MPHY_L1_RX 148 -#define TEGRA186_RESET_MPHY_L1_TX 149 -#define TEGRA186_RESET_UFSHC_LP 150 -#define TEGRA186_RESET_BPMP_NIC 151 -#define TEGRA186_RESET_BPMP_NSYSPORESET 152 -#define TEGRA186_RESET_BPMP_NRESET 153 -#define TEGRA186_RESET_BPMP_DBGRESETN 154 -#define TEGRA186_RESET_BPMP_PRESETDBGN 155 -#define TEGRA186_RESET_BPMP_PM 156 -#define TEGRA186_RESET_BPMP_CVC 157 -#define TEGRA186_RESET_BPMP_DMA 158 -#define TEGRA186_RESET_BPMP_HSP 159 -#define TEGRA186_RESET_TSCTNBPMP 160 -#define TEGRA186_RESET_BPMP_TKE 161 -#define TEGRA186_RESET_BPMP_GTE 162 -#define TEGRA186_RESET_BPMP_PM_ACTMON 163 -#define TEGRA186_RESET_AON_NIC 164 -#define TEGRA186_RESET_AON_NSYSPORESET 165 -#define TEGRA186_RESET_AON_NRESET 166 -#define TEGRA186_RESET_AON_DBGRESETN 167 -#define TEGRA186_RESET_AON_PRESETDBGN 168 -#define TEGRA186_RESET_AON_ACTMON 169 -#define TEGRA186_RESET_AOPM 170 -#define TEGRA186_RESET_AOVC 171 -#define TEGRA186_RESET_AON_DMA 172 -#define TEGRA186_RESET_AON_GPIO 173 -#define TEGRA186_RESET_AON_HSP 174 -#define TEGRA186_RESET_TSCTNAON 175 -#define TEGRA186_RESET_AON_TKE 176 -#define TEGRA186_RESET_AON_GTE 177 -#define TEGRA186_RESET_SCE_NIC 178 -#define TEGRA186_RESET_SCE_NSYSPORESET 179 -#define TEGRA186_RESET_SCE_NRESET 180 -#define TEGRA186_RESET_SCE_DBGRESETN 181 -#define TEGRA186_RESET_SCE_PRESETDBGN 182 -#define TEGRA186_RESET_SCE_ACTMON 183 -#define TEGRA186_RESET_SCE_PM 184 -#define TEGRA186_RESET_SCE_DMA 185 -#define TEGRA186_RESET_SCE_HSP 186 -#define TEGRA186_RESET_TSCTNSCE 187 -#define TEGRA186_RESET_SCE_TKE 188 -#define TEGRA186_RESET_SCE_GTE 189 -#define TEGRA186_RESET_SCE_CFG 190 -#define TEGRA186_RESET_ADSP_ALL 191 -/** @brief controls the power up/down sequence of UFSHC PSW partition. Controls LP_PWR_READY, LP_ISOL_EN, and LP_RESET_N signals */ -#define TEGRA186_RESET_UFSHC_LP_SEQ 192 -#define TEGRA186_RESET_SIZE 193 - -#endif diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h deleted file mode 100644 index 1427ff140f1..00000000000 --- a/include/dt-bindings/reset/ti-syscon.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * TI Syscon Reset definitions - * - * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ -#define __DT_BINDINGS_RESET_TI_SYSCON_H__ - -/* - * The reset does not support the feature and corresponding - * values are not valid - */ -#define ASSERT_NONE (1 << 0) -#define DEASSERT_NONE (1 << 1) -#define STATUS_NONE (1 << 2) - -/* When set this function is activated by setting(vs clearing) this bit */ -#define ASSERT_SET (1 << 3) -#define DEASSERT_SET (1 << 4) -#define STATUS_SET (1 << 5) - -/* The following are the inverse of the above and are added for consistency */ -#define ASSERT_CLEAR (0 << 3) -#define DEASSERT_CLEAR (0 << 4) -#define STATUS_CLEAR (0 << 5) - -#endif -- cgit v1.3.1 From d8ff4a06526816fcb463551dd0ed41c7f696b012 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 27 May 2025 17:50:38 -0600 Subject: include/dt-bindings: Remove strict subset headers As part of moving to using OF_UPSTREAM and so the upstream dt-bindings headers we have a number of these headers that are in our include directory and differ in being a strict subset of what is found upstream. We can safely remove the copies under include/dt-bindings now to prevent future conflicts. Signed-off-by: Tom Rini --- include/dt-bindings/clock/at91.h | 23 -- include/dt-bindings/clock/mt7622-clk.h | 276 --------------------- include/dt-bindings/clock/sun50i-a64-ccu.h | 138 ----------- .../dt-bindings/interrupt-controller/apple-aic.h | 15 -- include/dt-bindings/memory/tegra114-mc.h | 25 -- include/dt-bindings/memory/tegra124-mc.h | 31 --- include/dt-bindings/memory/tegra210-mc.h | 36 --- include/dt-bindings/memory/tegra30-mc.h | 24 -- include/dt-bindings/reset/altr,rst-mgr-s10.h | 96 ------- include/dt-bindings/reset/bcm63268-reset.h | 31 --- include/dt-bindings/thermal/tegra124-soctherm.h | 14 -- 11 files changed, 709 deletions(-) delete mode 100644 include/dt-bindings/clock/at91.h delete mode 100644 include/dt-bindings/clock/mt7622-clk.h delete mode 100644 include/dt-bindings/clock/sun50i-a64-ccu.h delete mode 100644 include/dt-bindings/interrupt-controller/apple-aic.h delete mode 100644 include/dt-bindings/memory/tegra114-mc.h delete mode 100644 include/dt-bindings/memory/tegra124-mc.h delete mode 100644 include/dt-bindings/memory/tegra210-mc.h delete mode 100644 include/dt-bindings/memory/tegra30-mc.h delete mode 100644 include/dt-bindings/reset/altr,rst-mgr-s10.h delete mode 100644 include/dt-bindings/reset/bcm63268-reset.h delete mode 100644 include/dt-bindings/thermal/tegra124-soctherm.h (limited to 'include') diff --git a/include/dt-bindings/clock/at91.h b/include/dt-bindings/clock/at91.h deleted file mode 100644 index ab3ee241d10..00000000000 --- a/include/dt-bindings/clock/at91.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This header provides constants for AT91 pmc status. - * - * The constants defined in this header are being used in dts. - * - * Licensed under GPLv2 or later. - */ - -#ifndef _DT_BINDINGS_CLK_AT91_H -#define _DT_BINDINGS_CLK_AT91_H - -#define AT91_PMC_MOSCS 0 /* MOSCS Flag */ -#define AT91_PMC_LOCKA 1 /* PLLA Lock */ -#define AT91_PMC_LOCKB 2 /* PLLB Lock */ -#define AT91_PMC_MCKRDY 3 /* Master Clock */ -#define AT91_PMC_LOCKU 6 /* UPLL Lock */ -#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */ -#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */ -#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */ -#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */ -#define AT91_PMC_GCKRDY 24 /* Generated Clocks */ - -#endif diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h deleted file mode 100644 index cdbcaef76eb..00000000000 --- a/include/dt-bindings/clock/mt7622-clk.h +++ /dev/null @@ -1,276 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2019 MediaTek Inc. - */ -#ifndef _DT_BINDINGS_CLK_MT7622_H -#define _DT_BINDINGS_CLK_MT7622_H - -/* TOPCKGEN */ - -/* FIXED_CLKS */ -#define CLK_TOP_TO_U2_PHY 0 -#define CLK_TOP_TO_U2_PHY_1P 1 -#define CLK_TOP_PCIE0_PIPE_EN 2 -#define CLK_TOP_PCIE1_PIPE_EN 3 -#define CLK_TOP_SSUSB_TX250M 4 -#define CLK_TOP_SSUSB_EQ_RX250M 5 -#define CLK_TOP_SSUSB_CDR_REF 6 -#define CLK_TOP_SSUSB_CDR_FB 7 -#define CLK_TOP_SATA_ASIC 8 -#define CLK_TOP_SATA_RBC 9 -/* FIXED_DIVS */ -#define CLK_TOP_TO_USB3_SYS 10 -#define CLK_TOP_P1_1MHZ 11 -#define CLK_TOP_4MHZ 12 -#define CLK_TOP_P0_1MHZ 13 -#define CLK_TOP_TXCLK_SRC_PRE 14 -#define CLK_TOP_RTC 15 -#define CLK_TOP_MEMPLL 16 -#define CLK_TOP_DMPLL 17 -#define CLK_TOP_SYSPLL_D2 18 -#define CLK_TOP_SYSPLL1_D2 19 -#define CLK_TOP_SYSPLL1_D4 20 -#define CLK_TOP_SYSPLL1_D8 21 -#define CLK_TOP_SYSPLL2_D4 22 -#define CLK_TOP_SYSPLL2_D8 23 -#define CLK_TOP_SYSPLL_D5 24 -#define CLK_TOP_SYSPLL3_D2 25 -#define CLK_TOP_SYSPLL3_D4 26 -#define CLK_TOP_SYSPLL4_D2 27 -#define CLK_TOP_SYSPLL4_D4 28 -#define CLK_TOP_SYSPLL4_D16 29 -#define CLK_TOP_UNIVPLL 30 -#define CLK_TOP_UNIVPLL_D2 31 -#define CLK_TOP_UNIVPLL1_D2 32 -#define CLK_TOP_UNIVPLL1_D4 33 -#define CLK_TOP_UNIVPLL1_D8 34 -#define CLK_TOP_UNIVPLL1_D16 35 -#define CLK_TOP_UNIVPLL2_D2 36 -#define CLK_TOP_UNIVPLL2_D4 37 -#define CLK_TOP_UNIVPLL2_D8 38 -#define CLK_TOP_UNIVPLL2_D16 39 -#define CLK_TOP_UNIVPLL_D5 40 -#define CLK_TOP_UNIVPLL3_D2 41 -#define CLK_TOP_UNIVPLL3_D4 42 -#define CLK_TOP_UNIVPLL3_D16 43 -#define CLK_TOP_UNIVPLL_D7 44 -#define CLK_TOP_UNIVPLL_D80_D4 45 -#define CLK_TOP_UNIV48M 46 -#define CLK_TOP_SGMIIPLL 47 -#define CLK_TOP_SGMIIPLL_D2 48 -#define CLK_TOP_AUD1PLL 49 -#define CLK_TOP_AUD2PLL 50 -#define CLK_TOP_AUD_I2S2_MCK 51 -#define CLK_TOP_TO_USB3_REF 52 -#define CLK_TOP_PCIE1_MAC_EN 53 -#define CLK_TOP_PCIE0_MAC_EN 54 -#define CLK_TOP_ETH_500M 55 -/* TOP_MUXES */ -#define CLK_TOP_AXI_SEL 56 -#define CLK_TOP_MEM_SEL 57 -#define CLK_TOP_DDRPHYCFG_SEL 58 -#define CLK_TOP_ETH_SEL 59 -#define CLK_TOP_PWM_SEL 60 -#define CLK_TOP_F10M_REF_SEL 61 -#define CLK_TOP_NFI_INFRA_SEL 62 -#define CLK_TOP_FLASH_SEL 63 -#define CLK_TOP_UART_SEL 64 -#define CLK_TOP_SPI0_SEL 65 -#define CLK_TOP_SPI1_SEL 66 -#define CLK_TOP_MSDC50_0_SEL 67 -#define CLK_TOP_MSDC30_0_SEL 68 -#define CLK_TOP_MSDC30_1_SEL 69 -#define CLK_TOP_A1SYS_HP_SEL 70 -#define CLK_TOP_A2SYS_HP_SEL 71 -#define CLK_TOP_INTDIR_SEL 72 -#define CLK_TOP_AUD_INTBUS_SEL 73 -#define CLK_TOP_PMICSPI_SEL 74 -#define CLK_TOP_SCP_SEL 75 -#define CLK_TOP_ATB_SEL 76 -#define CLK_TOP_HIF_SEL 77 -#define CLK_TOP_AUDIO_SEL 78 -#define CLK_TOP_U2_SEL 79 -#define CLK_TOP_AUD1_SEL 80 -#define CLK_TOP_AUD2_SEL 81 -#define CLK_TOP_IRRX_SEL 82 -#define CLK_TOP_IRTX_SEL 83 -#define CLK_TOP_ASM_L_SEL 84 -#define CLK_TOP_ASM_M_SEL 85 -#define CLK_TOP_ASM_H_SEL 86 -#define CLK_TOP_APLL1_SEL 87 -#define CLK_TOP_APLL2_SEL 88 -#define CLK_TOP_I2S0_MCK_SEL 89 -#define CLK_TOP_I2S1_MCK_SEL 90 -#define CLK_TOP_I2S2_MCK_SEL 91 -#define CLK_TOP_I2S3_MCK_SEL 92 -#define CLK_TOP_APLL1_DIV 93 -#define CLK_TOP_APLL2_DIV 94 -#define CLK_TOP_I2S0_MCK_DIV 95 -#define CLK_TOP_I2S1_MCK_DIV 96 -#define CLK_TOP_I2S2_MCK_DIV 97 -#define CLK_TOP_I2S3_MCK_DIV 98 -#define CLK_TOP_A1SYS_HP_DIV 99 -#define CLK_TOP_A2SYS_HP_DIV 100 -#define CLK_TOP_APLL1_DIV_PD 101 -#define CLK_TOP_APLL2_DIV_PD 102 -#define CLK_TOP_I2S0_MCK_DIV_PD 103 -#define CLK_TOP_I2S1_MCK_DIV_PD 104 -#define CLK_TOP_I2S2_MCK_DIV_PD 105 -#define CLK_TOP_I2S3_MCK_DIV_PD 106 -#define CLK_TOP_A1SYS_HP_DIV_PD 107 -#define CLK_TOP_A2SYS_HP_DIV_PD 108 - -/* INFRACFG */ - -#define CLK_INFRA_MUX1_SEL 0 -#define CLK_INFRA_DBGCLK_PD 1 -#define CLK_INFRA_AUDIO_PD 2 -#define CLK_INFRA_IRRX_PD 3 -#define CLK_INFRA_APXGPT_PD 4 -#define CLK_INFRA_PMIC_PD 5 -#define CLK_INFRA_TRNG 6 - -/* PERICFG */ - -#define CLK_PERIBUS_SEL 0 -#define CLK_PERI_THERM_PD 1 -#define CLK_PERI_PWM1_PD 2 -#define CLK_PERI_PWM2_PD 3 -#define CLK_PERI_PWM3_PD 4 -#define CLK_PERI_PWM4_PD 5 -#define CLK_PERI_PWM5_PD 6 -#define CLK_PERI_PWM6_PD 7 -#define CLK_PERI_PWM7_PD 8 -#define CLK_PERI_PWM_PD 9 -#define CLK_PERI_AP_DMA_PD 10 -#define CLK_PERI_MSDC30_0_PD 11 -#define CLK_PERI_MSDC30_1_PD 12 -#define CLK_PERI_UART0_PD 13 -#define CLK_PERI_UART1_PD 14 -#define CLK_PERI_UART2_PD 15 -#define CLK_PERI_UART3_PD 16 -#define CLK_PERI_UART4_PD 17 -#define CLK_PERI_BTIF_PD 18 -#define CLK_PERI_I2C0_PD 19 -#define CLK_PERI_I2C1_PD 20 -#define CLK_PERI_I2C2_PD 21 -#define CLK_PERI_SPI1_PD 22 -#define CLK_PERI_AUXADC_PD 23 -#define CLK_PERI_SPI0_PD 24 -#define CLK_PERI_SNFI_PD 25 -#define CLK_PERI_NFI_PD 26 -#define CLK_PERI_NFIECC_PD 27 -#define CLK_PERI_FLASH_PD 28 -#define CLK_PERI_IRTX_PD 29 - -/* APMIXEDSYS */ - -#define CLK_APMIXED_ARMPLL 0 -#define CLK_APMIXED_MAINPLL 1 -#define CLK_APMIXED_UNIV2PLL 2 -#define CLK_APMIXED_ETH1PLL 3 -#define CLK_APMIXED_ETH2PLL 4 -#define CLK_APMIXED_AUD1PLL 5 -#define CLK_APMIXED_AUD2PLL 6 -#define CLK_APMIXED_TRGPLL 7 -#define CLK_APMIXED_SGMIPLL 8 -#define CLK_APMIXED_MAIN_CORE_EN 9 - -/* AUDIOSYS */ - -#define CLK_AUDIO_AFE 0 -#define CLK_AUDIO_HDMI 1 -#define CLK_AUDIO_SPDF 2 -#define CLK_AUDIO_APLL 3 -#define CLK_AUDIO_I2SIN1 4 -#define CLK_AUDIO_I2SIN2 5 -#define CLK_AUDIO_I2SIN3 6 -#define CLK_AUDIO_I2SIN4 7 -#define CLK_AUDIO_I2SO1 8 -#define CLK_AUDIO_I2SO2 9 -#define CLK_AUDIO_I2SO3 10 -#define CLK_AUDIO_I2SO4 11 -#define CLK_AUDIO_ASRCI1 12 -#define CLK_AUDIO_ASRCI2 13 -#define CLK_AUDIO_ASRCO1 14 -#define CLK_AUDIO_ASRCO2 15 -#define CLK_AUDIO_INTDIR 16 -#define CLK_AUDIO_A1SYS 17 -#define CLK_AUDIO_A2SYS 18 -#define CLK_AUDIO_UL1 19 -#define CLK_AUDIO_UL2 20 -#define CLK_AUDIO_UL3 21 -#define CLK_AUDIO_UL4 22 -#define CLK_AUDIO_UL5 23 -#define CLK_AUDIO_UL6 24 -#define CLK_AUDIO_DL1 25 -#define CLK_AUDIO_DL2 26 -#define CLK_AUDIO_DL3 27 -#define CLK_AUDIO_DL4 28 -#define CLK_AUDIO_DL5 29 -#define CLK_AUDIO_DL6 30 -#define CLK_AUDIO_DLMCH 31 -#define CLK_AUDIO_ARB1 32 -#define CLK_AUDIO_AWB 33 -#define CLK_AUDIO_AWB2 34 -#define CLK_AUDIO_DAI 35 -#define CLK_AUDIO_MOD 36 -#define CLK_AUDIO_ASRCI3 37 -#define CLK_AUDIO_ASRCI4 38 -#define CLK_AUDIO_ASRCO3 39 -#define CLK_AUDIO_ASRCO4 40 -#define CLK_AUDIO_MEM_ASRC1 41 -#define CLK_AUDIO_MEM_ASRC2 42 -#define CLK_AUDIO_MEM_ASRC3 43 -#define CLK_AUDIO_MEM_ASRC4 44 -#define CLK_AUDIO_MEM_ASRC5 45 -#define CLK_AUDIO_AFE_CONN 46 -#define CLK_AUDIO_NR_CLK 47 - -/* SSUSBSYS */ - -#define CLK_SSUSB_U2_PHY_1P_EN 0 -#define CLK_SSUSB_U2_PHY_EN 1 -#define CLK_SSUSB_REF_EN 2 -#define CLK_SSUSB_SYS_EN 3 -#define CLK_SSUSB_MCU_EN 4 -#define CLK_SSUSB_DMA_EN 5 -#define CLK_SSUSB_NR_CLK 6 - -/* PCIESYS */ - -#define CLK_PCIE_P1_AUX_EN 0 -#define CLK_PCIE_P1_OBFF_EN 1 -#define CLK_PCIE_P1_AHB_EN 2 -#define CLK_PCIE_P1_AXI_EN 3 -#define CLK_PCIE_P1_MAC_EN 4 -#define CLK_PCIE_P1_PIPE_EN 5 -#define CLK_PCIE_P0_AUX_EN 6 -#define CLK_PCIE_P0_OBFF_EN 7 -#define CLK_PCIE_P0_AHB_EN 8 -#define CLK_PCIE_P0_AXI_EN 9 -#define CLK_PCIE_P0_MAC_EN 10 -#define CLK_PCIE_P0_PIPE_EN 11 -#define CLK_SATA_AHB_EN 12 -#define CLK_SATA_AXI_EN 13 -#define CLK_SATA_ASIC_EN 14 -#define CLK_SATA_RBC_EN 15 -#define CLK_SATA_PM_EN 16 -#define CLK_PCIE_NR_CLK 17 - -/* ETHSYS */ - -#define CLK_ETH_HSDMA_EN 0 -#define CLK_ETH_ESW_EN 1 -#define CLK_ETH_GP2_EN 2 -#define CLK_ETH_GP1_EN 3 -#define CLK_ETH_GP0_EN 4 - -/* SGMIISYS */ - -#define CLK_SGMII_TX250M_EN 0 -#define CLK_SGMII_RX250M_EN 1 -#define CLK_SGMII_CDR_REF 2 -#define CLK_SGMII_CDR_FB 3 - -#endif /* _DT_BINDINGS_CLK_MT7622_H */ diff --git a/include/dt-bindings/clock/sun50i-a64-ccu.h b/include/dt-bindings/clock/sun50i-a64-ccu.h deleted file mode 100644 index 175892189e9..00000000000 --- a/include/dt-bindings/clock/sun50i-a64-ccu.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (C) 2016 Maxime Ripard - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -#ifndef _DT_BINDINGS_CLK_SUN50I_A64_H_ -#define _DT_BINDINGS_CLK_SUN50I_A64_H_ - -#define CLK_PLL_VIDEO0 7 -#define CLK_PLL_PERIPH0 11 - -#define CLK_CPUX 21 -#define CLK_BUS_MIPI_DSI 28 -#define CLK_BUS_CE 29 -#define CLK_BUS_DMA 30 -#define CLK_BUS_MMC0 31 -#define CLK_BUS_MMC1 32 -#define CLK_BUS_MMC2 33 -#define CLK_BUS_NAND 34 -#define CLK_BUS_DRAM 35 -#define CLK_BUS_EMAC 36 -#define CLK_BUS_TS 37 -#define CLK_BUS_HSTIMER 38 -#define CLK_BUS_SPI0 39 -#define CLK_BUS_SPI1 40 -#define CLK_BUS_OTG 41 -#define CLK_BUS_EHCI0 42 -#define CLK_BUS_EHCI1 43 -#define CLK_BUS_OHCI0 44 -#define CLK_BUS_OHCI1 45 -#define CLK_BUS_VE 46 -#define CLK_BUS_TCON0 47 -#define CLK_BUS_TCON1 48 -#define CLK_BUS_DEINTERLACE 49 -#define CLK_BUS_CSI 50 -#define CLK_BUS_HDMI 51 -#define CLK_BUS_DE 52 -#define CLK_BUS_GPU 53 -#define CLK_BUS_MSGBOX 54 -#define CLK_BUS_SPINLOCK 55 -#define CLK_BUS_CODEC 56 -#define CLK_BUS_SPDIF 57 -#define CLK_BUS_PIO 58 -#define CLK_BUS_THS 59 -#define CLK_BUS_I2S0 60 -#define CLK_BUS_I2S1 61 -#define CLK_BUS_I2S2 62 -#define CLK_BUS_I2C0 63 -#define CLK_BUS_I2C1 64 -#define CLK_BUS_I2C2 65 -#define CLK_BUS_SCR 66 -#define CLK_BUS_UART0 67 -#define CLK_BUS_UART1 68 -#define CLK_BUS_UART2 69 -#define CLK_BUS_UART3 70 -#define CLK_BUS_UART4 71 -#define CLK_BUS_DBG 72 -#define CLK_THS 73 -#define CLK_NAND 74 -#define CLK_MMC0 75 -#define CLK_MMC1 76 -#define CLK_MMC2 77 -#define CLK_TS 78 -#define CLK_CE 79 -#define CLK_SPI0 80 -#define CLK_SPI1 81 -#define CLK_I2S0 82 -#define CLK_I2S1 83 -#define CLK_I2S2 84 -#define CLK_SPDIF 85 -#define CLK_USB_PHY0 86 -#define CLK_USB_PHY1 87 -#define CLK_USB_HSIC 88 -#define CLK_USB_HSIC_12M 89 - -#define CLK_USB_OHCI0 91 - -#define CLK_USB_OHCI1 93 -#define CLK_DRAM 94 -#define CLK_DRAM_VE 95 -#define CLK_DRAM_CSI 96 -#define CLK_DRAM_DEINTERLACE 97 -#define CLK_DRAM_TS 98 -#define CLK_DE 99 -#define CLK_TCON0 100 -#define CLK_TCON1 101 -#define CLK_DEINTERLACE 102 -#define CLK_CSI_MISC 103 -#define CLK_CSI_SCLK 104 -#define CLK_CSI_MCLK 105 -#define CLK_VE 106 -#define CLK_AC_DIG 107 -#define CLK_AC_DIG_4X 108 -#define CLK_AVS 109 -#define CLK_HDMI 110 -#define CLK_HDMI_DDC 111 -#define CLK_MBUS 112 -#define CLK_DSI_DPHY 113 -#define CLK_GPU 114 - -#endif /* _DT_BINDINGS_CLK_SUN50I_H_ */ diff --git a/include/dt-bindings/interrupt-controller/apple-aic.h b/include/dt-bindings/interrupt-controller/apple-aic.h deleted file mode 100644 index 9ac56a7e6d3..00000000000 --- a/include/dt-bindings/interrupt-controller/apple-aic.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_APPLE_AIC_H - -#include - -#define AIC_IRQ 0 -#define AIC_FIQ 1 - -#define AIC_TMR_HV_PHYS 0 -#define AIC_TMR_HV_VIRT 1 -#define AIC_TMR_GUEST_PHYS 2 -#define AIC_TMR_GUEST_VIRT 3 - -#endif diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h deleted file mode 100644 index 8f48985a313..00000000000 --- a/include/dt-bindings/memory/tegra114-mc.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H -#define DT_BINDINGS_MEMORY_TEGRA114_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_EPP 3 -#define TEGRA_SWGROUP_G2 4 -#define TEGRA_SWGROUP_AVPC 5 -#define TEGRA_SWGROUP_NV 6 -#define TEGRA_SWGROUP_HDA 7 -#define TEGRA_SWGROUP_HC 8 -#define TEGRA_SWGROUP_MSENC 9 -#define TEGRA_SWGROUP_PPCS 10 -#define TEGRA_SWGROUP_VDE 11 -#define TEGRA_SWGROUP_MPCORELP 12 -#define TEGRA_SWGROUP_MPCORE 13 -#define TEGRA_SWGROUP_VI 14 -#define TEGRA_SWGROUP_ISP 15 -#define TEGRA_SWGROUP_XUSB_HOST 16 -#define TEGRA_SWGROUP_XUSB_DEV 17 -#define TEGRA_SWGROUP_EMUCIF 18 -#define TEGRA_SWGROUP_TSEC 19 - -#endif diff --git a/include/dt-bindings/memory/tegra124-mc.h b/include/dt-bindings/memory/tegra124-mc.h deleted file mode 100644 index 7d8ee798f34..00000000000 --- a/include/dt-bindings/memory/tegra124-mc.h +++ /dev/null @@ -1,31 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA124_MC_H -#define DT_BINDINGS_MEMORY_TEGRA124_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_AFI 3 -#define TEGRA_SWGROUP_AVPC 4 -#define TEGRA_SWGROUP_HDA 5 -#define TEGRA_SWGROUP_HC 6 -#define TEGRA_SWGROUP_MSENC 7 -#define TEGRA_SWGROUP_PPCS 8 -#define TEGRA_SWGROUP_SATA 9 -#define TEGRA_SWGROUP_VDE 10 -#define TEGRA_SWGROUP_MPCORELP 11 -#define TEGRA_SWGROUP_MPCORE 12 -#define TEGRA_SWGROUP_ISP2 13 -#define TEGRA_SWGROUP_XUSB_HOST 14 -#define TEGRA_SWGROUP_XUSB_DEV 15 -#define TEGRA_SWGROUP_ISP2B 16 -#define TEGRA_SWGROUP_TSEC 17 -#define TEGRA_SWGROUP_A9AVP 18 -#define TEGRA_SWGROUP_GPU 19 -#define TEGRA_SWGROUP_SDMMC1A 20 -#define TEGRA_SWGROUP_SDMMC2A 21 -#define TEGRA_SWGROUP_SDMMC3A 22 -#define TEGRA_SWGROUP_SDMMC4A 23 -#define TEGRA_SWGROUP_VIC 24 -#define TEGRA_SWGROUP_VI 25 - -#endif diff --git a/include/dt-bindings/memory/tegra210-mc.h b/include/dt-bindings/memory/tegra210-mc.h deleted file mode 100644 index d1731bc14db..00000000000 --- a/include/dt-bindings/memory/tegra210-mc.h +++ /dev/null @@ -1,36 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H -#define DT_BINDINGS_MEMORY_TEGRA210_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_AFI 3 -#define TEGRA_SWGROUP_AVPC 4 -#define TEGRA_SWGROUP_HDA 5 -#define TEGRA_SWGROUP_HC 6 -#define TEGRA_SWGROUP_NVENC 7 -#define TEGRA_SWGROUP_PPCS 8 -#define TEGRA_SWGROUP_SATA 9 -#define TEGRA_SWGROUP_MPCORE 10 -#define TEGRA_SWGROUP_ISP2 11 -#define TEGRA_SWGROUP_XUSB_HOST 12 -#define TEGRA_SWGROUP_XUSB_DEV 13 -#define TEGRA_SWGROUP_ISP2B 14 -#define TEGRA_SWGROUP_TSEC 15 -#define TEGRA_SWGROUP_A9AVP 16 -#define TEGRA_SWGROUP_GPU 17 -#define TEGRA_SWGROUP_SDMMC1A 18 -#define TEGRA_SWGROUP_SDMMC2A 19 -#define TEGRA_SWGROUP_SDMMC3A 20 -#define TEGRA_SWGROUP_SDMMC4A 21 -#define TEGRA_SWGROUP_VIC 22 -#define TEGRA_SWGROUP_VI 23 -#define TEGRA_SWGROUP_NVDEC 24 -#define TEGRA_SWGROUP_APE 25 -#define TEGRA_SWGROUP_NVJPG 26 -#define TEGRA_SWGROUP_SE 27 -#define TEGRA_SWGROUP_AXIAP 28 -#define TEGRA_SWGROUP_ETR 29 -#define TEGRA_SWGROUP_TSECB 30 - -#endif diff --git a/include/dt-bindings/memory/tegra30-mc.h b/include/dt-bindings/memory/tegra30-mc.h deleted file mode 100644 index 502beb03d77..00000000000 --- a/include/dt-bindings/memory/tegra30-mc.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef DT_BINDINGS_MEMORY_TEGRA30_MC_H -#define DT_BINDINGS_MEMORY_TEGRA30_MC_H - -#define TEGRA_SWGROUP_PTC 0 -#define TEGRA_SWGROUP_DC 1 -#define TEGRA_SWGROUP_DCB 2 -#define TEGRA_SWGROUP_EPP 3 -#define TEGRA_SWGROUP_G2 4 -#define TEGRA_SWGROUP_MPE 5 -#define TEGRA_SWGROUP_VI 6 -#define TEGRA_SWGROUP_AFI 7 -#define TEGRA_SWGROUP_AVPC 8 -#define TEGRA_SWGROUP_NV 9 -#define TEGRA_SWGROUP_NV2 10 -#define TEGRA_SWGROUP_HDA 11 -#define TEGRA_SWGROUP_HC 12 -#define TEGRA_SWGROUP_PPCS 13 -#define TEGRA_SWGROUP_SATA 14 -#define TEGRA_SWGROUP_VDE 15 -#define TEGRA_SWGROUP_MPCORELP 16 -#define TEGRA_SWGROUP_MPCORE 17 -#define TEGRA_SWGROUP_ISP 18 - -#endif diff --git a/include/dt-bindings/reset/altr,rst-mgr-s10.h b/include/dt-bindings/reset/altr,rst-mgr-s10.h deleted file mode 100644 index 1fdcf8ae153..00000000000 --- a/include/dt-bindings/reset/altr,rst-mgr-s10.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016-2018 Intel Corporation. All rights reserved - * Copyright (C) 2016 Altera Corporation. All rights reserved - * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h" - */ - -#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H -#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H - -/* MPUMODRST */ -#define CPU0_RESET 0 -#define CPU1_RESET 1 -#define CPU2_RESET 2 -#define CPU3_RESET 3 - -/* PER0MODRST */ -#define EMAC0_RESET 32 -#define EMAC1_RESET 33 -#define EMAC2_RESET 34 -#define USB0_RESET 35 -#define USB1_RESET 36 -#define NAND_RESET 37 -/* 38 is empty */ -#define SDMMC_RESET 39 -#define EMAC0_OCP_RESET 40 -#define EMAC1_OCP_RESET 41 -#define EMAC2_OCP_RESET 42 -#define USB0_OCP_RESET 43 -#define USB1_OCP_RESET 44 -#define NAND_OCP_RESET 45 -/* 46 is empty */ -#define SDMMC_OCP_RESET 47 -#define DMA_RESET 48 -#define SPIM0_RESET 49 -#define SPIM1_RESET 50 -#define SPIS0_RESET 51 -#define SPIS1_RESET 52 -#define DMA_OCP_RESET 53 -#define EMAC_PTP_RESET 54 -/* 55 is empty*/ -#define DMAIF0_RESET 56 -#define DMAIF1_RESET 57 -#define DMAIF2_RESET 58 -#define DMAIF3_RESET 59 -#define DMAIF4_RESET 60 -#define DMAIF5_RESET 61 -#define DMAIF6_RESET 62 -#define DMAIF7_RESET 63 - -/* PER1MODRST */ -#define WATCHDOG0_RESET 64 -#define WATCHDOG1_RESET 65 -#define WATCHDOG2_RESET 66 -#define WATCHDOG3_RESET 67 -#define L4SYSTIMER0_RESET 68 -#define L4SYSTIMER1_RESET 69 -#define SPTIMER0_RESET 70 -#define SPTIMER1_RESET 71 -#define I2C0_RESET 72 -#define I2C1_RESET 73 -#define I2C2_RESET 74 -#define I2C3_RESET 75 -#define I2C4_RESET 76 -/* 77-79 is empty */ -#define UART0_RESET 80 -#define UART1_RESET 81 -/* 82-87 is empty */ -#define GPIO0_RESET 88 -#define GPIO1_RESET 89 - -/* BRGMODRST */ -#define SOC2FPGA_RESET 96 -#define LWHPS2FPGA_RESET 97 -#define FPGA2SOC_RESET 98 -#define F2SSDRAM0_RESET 99 -#define F2SSDRAM1_RESET 100 -#define F2SSDRAM2_RESET 101 -#define DDRSCH_RESET 102 - -/* COLDMODRST */ -#define CPUPO0_RESET 160 -#define CPUPO1_RESET 161 -#define CPUPO2_RESET 162 -#define CPUPO3_RESET 163 -/* 164-167 is empty */ -#define L2_RESET 168 - -/* DBGMODRST */ -#define DBG_RESET 224 -#define CSDAP_RESET 225 - -/* TAPMODRST */ -#define TAP_RESET 256 - -#endif diff --git a/include/dt-bindings/reset/bcm63268-reset.h b/include/dt-bindings/reset/bcm63268-reset.h deleted file mode 100644 index a45abed1ceb..00000000000 --- a/include/dt-bindings/reset/bcm63268-reset.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - * - * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h - */ - -#ifndef __DT_BINDINGS_RESET_BCM63268_H -#define __DT_BINDINGS_RESET_BCM63268_H - -#define BCM63268_RST_SPI 0 -#define BCM63268_RST_IPSEC 1 -#define BCM63268_RST_EPHY 2 -#define BCM63268_RST_SAR 3 -#define BCM63268_RST_ENETSW 4 -#define BCM63268_RST_USBS 5 -#define BCM63268_RST_USBH 6 -#define BCM63268_RST_PCM 7 -#define BCM63268_RST_PCIE_CORE 8 -#define BCM63268_RST_PCIE 9 -#define BCM63268_RST_PCIE_EXT 10 -#define BCM63268_RST_WLAN_SHIM 11 -#define BCM63268_RST_DDR_PHY 12 -#define BCM63268_RST_FAP0 13 -#define BCM63268_RST_WLAN_UBUS 14 -#define BCM63268_RST_DECT 15 -#define BCM63268_RST_FAP1 16 -#define BCM63268_RST_PCIE_HARD 17 -#define BCM63268_RST_GPHY 18 - -#endif /* __DT_BINDINGS_RESET_BCM63268_H */ diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h deleted file mode 100644 index 729ab9fc325..00000000000 --- a/include/dt-bindings/thermal/tegra124-soctherm.h +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra124-soctherm. - */ - -#ifndef _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H -#define _DT_BINDINGS_THERMAL_TEGRA124_SOCTHERM_H - -#define TEGRA124_SOCTHERM_SENSOR_CPU 0 -#define TEGRA124_SOCTHERM_SENSOR_MEM 1 -#define TEGRA124_SOCTHERM_SENSOR_GPU 2 -#define TEGRA124_SOCTHERM_SENSOR_PLLX 3 -#define TEGRA124_SOCTHERM_SENSOR_NUM 4 - -#endif -- cgit v1.3.1 From c8612ed98eb6b459e5a5174cdb980a83763544b8 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 27 May 2025 18:03:01 -0600 Subject: include/dt-bindings/reset: Remove local version of bcm6318-reset.h Aside from SPDX tags, the only difference between our version of this header and upstream is that BCM6318_RST_HOSTMIPS was defined to 11 (the same as BCM6318_RST_PHYMIPS) and is now defined to 12. Signed-off-by: Tom Rini --- include/dt-bindings/reset/bcm6318-reset.h | 25 ------------------------- 1 file changed, 25 deletions(-) delete mode 100644 include/dt-bindings/reset/bcm6318-reset.h (limited to 'include') diff --git a/include/dt-bindings/reset/bcm6318-reset.h b/include/dt-bindings/reset/bcm6318-reset.h deleted file mode 100644 index 1422500f8f5..00000000000 --- a/include/dt-bindings/reset/bcm6318-reset.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Álvaro Fernández Rojas - * - * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h - */ - -#ifndef __DT_BINDINGS_RESET_BCM6318_H -#define __DT_BINDINGS_RESET_BCM6318_H - -#define BCM6318_RST_SPI 0 -#define BCM6318_RST_EPHY 1 -#define BCM6318_RST_SAR 2 -#define BCM6318_RST_ENETSW 3 -#define BCM6318_RST_USBD 4 -#define BCM6318_RST_USBH 5 -#define BCM6318_RST_PCIE_CORE 6 -#define BCM6318_RST_PCIE 7 -#define BCM6318_RST_PCIE_EXT 8 -#define BCM6318_RST_PCIE_HARD 9 -#define BCM6318_RST_ADSL 10 -#define BCM6318_RST_PHYMIPS 11 -#define BCM6318_RST_HOSTMIPS 11 - -#endif /* __DT_BINDINGS_RESET_BCM6318_H */ -- cgit v1.3.1 From de3976531649d950dc4f5a6fa6eb4920f6799e47 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 28 May 2025 14:37:45 -0600 Subject: include/dt-bindings: Remove headers we can safely upgrade As part of moving to using OF_UPSTREAM and so the upstream dt-bindings headers we have a number of these headers that are in our include directory and while they are not a strict subset of the upstream version of the headers, all platforms build with the new headers as well. We can remove the copies under include/dt-bindings now to prevent future conflicts. Signed-off-by: Tom Rini --- include/dt-bindings/clock/agilex-clock.h | 71 ----- include/dt-bindings/clock/am3.h | 227 -------------- include/dt-bindings/clock/bcm6358-clock.h | 23 -- include/dt-bindings/clock/bcm6362-clock.h | 32 -- include/dt-bindings/clock/bcm6368-clock.h | 30 -- include/dt-bindings/clock/boston-clock.h | 12 - include/dt-bindings/clock/hi6220-clock.h | 173 ---------- include/dt-bindings/clock/rk3368-cru.h | 381 ---------------------- include/dt-bindings/clock/tegra114-car.h | 343 -------------------- include/dt-bindings/clock/tegra124-car-common.h | 345 -------------------- include/dt-bindings/clock/tegra20-car.h | 158 ---------- include/dt-bindings/clock/tegra210-car.h | 400 ------------------------ include/dt-bindings/clock/tegra30-car.h | 273 ---------------- include/dt-bindings/pinctrl/am43xx.h | 39 --- 14 files changed, 2507 deletions(-) delete mode 100644 include/dt-bindings/clock/agilex-clock.h delete mode 100644 include/dt-bindings/clock/am3.h delete mode 100644 include/dt-bindings/clock/bcm6358-clock.h delete mode 100644 include/dt-bindings/clock/bcm6362-clock.h delete mode 100644 include/dt-bindings/clock/bcm6368-clock.h delete mode 100644 include/dt-bindings/clock/boston-clock.h delete mode 100644 include/dt-bindings/clock/hi6220-clock.h delete mode 100644 include/dt-bindings/clock/rk3368-cru.h delete mode 100644 include/dt-bindings/clock/tegra114-car.h delete mode 100644 include/dt-bindings/clock/tegra124-car-common.h delete mode 100644 include/dt-bindings/clock/tegra20-car.h delete mode 100644 include/dt-bindings/clock/tegra210-car.h delete mode 100644 include/dt-bindings/clock/tegra30-car.h delete mode 100644 include/dt-bindings/pinctrl/am43xx.h (limited to 'include') diff --git a/include/dt-bindings/clock/agilex-clock.h b/include/dt-bindings/clock/agilex-clock.h deleted file mode 100644 index f751aad4daf..00000000000 --- a/include/dt-bindings/clock/agilex-clock.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019, Intel Corporation - */ - -#ifndef __AGILEX_CLOCK_H -#define __AGILEX_CLOCK_H - -/* fixed rate clocks */ -#define AGILEX_OSC1 0 -#define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 -#define AGILEX_CB_INTOSC_LS_CLK 2 -#define AGILEX_L4_SYS_FREE_CLK 3 -#define AGILEX_F2S_FREE_CLK 4 - -/* PLL clocks */ -#define AGILEX_MAIN_PLL_CLK 5 -#define AGILEX_MAIN_PLL_C0_CLK 6 -#define AGILEX_MAIN_PLL_C1_CLK 7 -#define AGILEX_MAIN_PLL_C2_CLK 8 -#define AGILEX_MAIN_PLL_C3_CLK 9 -#define AGILEX_PERIPH_PLL_CLK 10 -#define AGILEX_PERIPH_PLL_C0_CLK 11 -#define AGILEX_PERIPH_PLL_C1_CLK 12 -#define AGILEX_PERIPH_PLL_C2_CLK 13 -#define AGILEX_PERIPH_PLL_C3_CLK 14 -#define AGILEX_MPU_FREE_CLK 15 -#define AGILEX_MPU_CCU_CLK 16 -#define AGILEX_BOOT_CLK 17 - -/* fixed factor clocks */ -#define AGILEX_L3_MAIN_FREE_CLK 18 -#define AGILEX_NOC_FREE_CLK 19 -#define AGILEX_S2F_USR0_CLK 20 -#define AGILEX_NOC_CLK 21 -#define AGILEX_EMAC_A_FREE_CLK 22 -#define AGILEX_EMAC_B_FREE_CLK 23 -#define AGILEX_EMAC_PTP_FREE_CLK 24 -#define AGILEX_GPIO_DB_FREE_CLK 25 -#define AGILEX_SDMMC_FREE_CLK 26 -#define AGILEX_S2F_USER0_FREE_CLK 27 -#define AGILEX_S2F_USER1_FREE_CLK 28 -#define AGILEX_PSI_REF_FREE_CLK 29 - -/* Gate clocks */ -#define AGILEX_MPU_CLK 30 -#define AGILEX_MPU_PERIPH_CLK 31 -#define AGILEX_L4_MAIN_CLK 32 -#define AGILEX_L4_MP_CLK 33 -#define AGILEX_L4_SP_CLK 34 -#define AGILEX_CS_AT_CLK 35 -#define AGILEX_CS_TRACE_CLK 36 -#define AGILEX_CS_PDBG_CLK 37 -#define AGILEX_CS_TIMER_CLK 38 -#define AGILEX_S2F_USER0_CLK 39 -#define AGILEX_EMAC0_CLK 40 -#define AGILEX_EMAC1_CLK 41 -#define AGILEX_EMAC2_CLK 42 -#define AGILEX_EMAC_PTP_CLK 43 -#define AGILEX_GPIO_DB_CLK 44 -#define AGILEX_NAND_CLK 45 -#define AGILEX_PSI_REF_CLK 46 -#define AGILEX_S2F_USER1_CLK 47 -#define AGILEX_SDMMC_CLK 48 -#define AGILEX_SPI_M_CLK 49 -#define AGILEX_USB_CLK 50 -#define AGILEX_NAND_X_CLK 51 -#define AGILEX_NAND_ECC_CLK 52 -#define AGILEX_NUM_CLKS 53 - -#endif /* __AGILEX_CLOCK_H */ diff --git a/include/dt-bindings/clock/am3.h b/include/dt-bindings/clock/am3.h deleted file mode 100644 index 86a8806e214..00000000000 --- a/include/dt-bindings/clock/am3.h +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright 2017 Texas Instruments, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef __DT_BINDINGS_CLK_AM3_H -#define __DT_BINDINGS_CLK_AM3_H - -#define AM3_CLKCTRL_OFFSET 0x0 -#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET) - -/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */ - -/* l4_per clocks */ -#define AM3_L4_PER_CLKCTRL_OFFSET 0x14 -#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET) -#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14) -#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18) -#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c) -#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24) -#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28) -#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c) -#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30) -#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34) -#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38) -#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c) -#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40) -#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44) -#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48) -#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c) -#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50) -#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60) -#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68) -#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c) -#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70) -#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74) -#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78) -#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c) -#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80) -#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84) -#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88) -#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90) -#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94) -#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0) -#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac) -#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0) -#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4) -#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc) -#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0) -#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4) -#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc) -#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4) -#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8) -#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc) -#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0) -#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8) -#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec) -#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0) -#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4) -#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8) -#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc) -#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100) -#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c) -#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110) -#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120) -#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130) -#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c) - -/* l4_wkup clocks */ -#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4 -#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET) -#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4) -#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8) -#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc) -#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14) -#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0) -#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4) -#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8) -#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc) -#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0) -#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4) -#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8) -#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4) - -/* mpu clocks */ -#define AM3_MPU_CLKCTRL_OFFSET 0x4 -#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET) -#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4) - -/* l4_rtc clocks */ -#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) - -/* gfx_l3 clocks */ -#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4 -#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET) -#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4) - -/* l4_cefuse clocks */ -#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20 -#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET) -#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20) - -/* XXX: Compatibility part end */ - -/* l4ls clocks */ -#define AM3_L4LS_CLKCTRL_OFFSET 0x38 -#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET) -#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38) -#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c) -#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40) -#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44) -#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48) -#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c) -#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50) -#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60) -#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c) -#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70) -#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74) -#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78) -#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c) -#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80) -#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84) -#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88) -#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90) -#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac) -#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0) -#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4) -#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0) -#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4) -#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc) -#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4) -#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8) -#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec) -#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0) -#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4) -#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c) -#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110) -#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130) - -/* l3s clocks */ -#define AM3_L3S_CLKCTRL_OFFSET 0x1c -#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET) -#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c) -#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30) -#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34) -#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68) -#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8) - -/* l3 clocks */ -#define AM3_L3_CLKCTRL_OFFSET 0x24 -#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET) -#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24) -#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28) -#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c) -#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94) -#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0) -#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc) -#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc) -#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0) -#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc) -#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100) - -/* l4hs clocks */ -#define AM3_L4HS_CLKCTRL_OFFSET 0x120 -#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET) -#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120) - -/* pruss_ocp clocks */ -#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8 -#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET) -#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8) - -/* cpsw_125mhz clocks */ -#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14) - -/* lcdc clocks */ -#define AM3_LCDC_CLKCTRL_OFFSET 0x18 -#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET) -#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18) - -/* clk_24mhz clocks */ -#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c -#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET) -#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c) - -/* l4_wkup clocks */ -#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4) -#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8) -#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc) -#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4) -#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8) -#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc) -#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0) -#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4) -#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8) -#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4) - -/* l3_aon clocks */ -#define AM3_L3_AON_CLKCTRL_OFFSET 0x14 -#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET) -#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14) - -/* l4_wkup_aon clocks */ -#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0 -#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET) -#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0) - -/* mpu clocks */ -#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4) - -/* l4_rtc clocks */ -#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0) - -/* gfx_l3 clocks */ -#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4) - -/* l4_cefuse clocks */ -#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20) - -#endif diff --git a/include/dt-bindings/clock/bcm6358-clock.h b/include/dt-bindings/clock/bcm6358-clock.h deleted file mode 100644 index a7529bcc030..00000000000 --- a/include/dt-bindings/clock/bcm6358-clock.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - * - * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h - */ - -#ifndef __DT_BINDINGS_CLOCK_BCM6358_H -#define __DT_BINDINGS_CLOCK_BCM6358_H - -#define BCM6358_CLK_ENET 4 -#define BCM6358_CLK_ADSL 5 -#define BCM6358_CLK_PCM 8 -#define BCM6358_CLK_SPI 9 -#define BCM6358_CLK_USBS 10 -#define BCM6358_CLK_SAR 11 -#define BCM6358_CLK_EMUSB 17 -#define BCM6358_CLK_ENET0 18 -#define BCM6358_CLK_ENET1 19 -#define BCM6358_CLK_USBSU 20 -#define BCM6358_CLK_EPHY 21 - -#endif /* __DT_BINDINGS_CLOCK_BCM6358_H */ diff --git a/include/dt-bindings/clock/bcm6362-clock.h b/include/dt-bindings/clock/bcm6362-clock.h deleted file mode 100644 index d3770c50490..00000000000 --- a/include/dt-bindings/clock/bcm6362-clock.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Álvaro Fernández Rojas - * - * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h - */ - -#ifndef __DT_BINDINGS_CLOCK_BCM6362_H -#define __DT_BINDINGS_CLOCK_BCM6362_H - -#define BCM6362_CLK_GLESS 0 -#define BCM6362_CLK_ADSL_QPROC 1 -#define BCM6362_CLK_ADSL_AFE 2 -#define BCM6362_CLK_ADSL 3 -#define BCM6362_CLK_MIPS 4 -#define BCM6362_CLK_WLAN_OCP 5 -#define BCM6362_CLK_SWPKT_USB 7 -#define BCM6362_CLK_SWPKT_SAR 8 -#define BCM6362_CLK_SAR 9 -#define BCM6362_CLK_ROBOSW 10 -#define BCM6362_CLK_PCM 11 -#define BCM6362_CLK_USBD 12 -#define BCM6362_CLK_USBH 13 -#define BCM6362_CLK_IPSEC 14 -#define BCM6362_CLK_SPI 15 -#define BCM6362_CLK_HSSPI 16 -#define BCM6362_CLK_PCIE 17 -#define BCM6362_CLK_FAP 18 -#define BCM6362_CLK_PHYMIPS 19 -#define BCM6362_CLK_NAND 20 - -#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */ diff --git a/include/dt-bindings/clock/bcm6368-clock.h b/include/dt-bindings/clock/bcm6368-clock.h deleted file mode 100644 index 0c857826329..00000000000 --- a/include/dt-bindings/clock/bcm6368-clock.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - * - * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h - */ - -#ifndef __DT_BINDINGS_CLOCK_BCM6368_H -#define __DT_BINDINGS_CLOCK_BCM6368_H - -#define BCM6368_CLK_VDSL_QPROC 2 -#define BCM6368_CLK_VDSL_AFE 3 -#define BCM6368_CLK_VDSL_BONDING 4 -#define BCM6368_CLK_VDSL 5 -#define BCM6368_CLK_PHYMIPS 6 -#define BCM6368_CLK_SWPKT_USB 7 -#define BCM6368_CLK_SWPKT_SAR 8 -#define BCM6368_CLK_SPI 9 -#define BCM6368_CLK_USBD 10 -#define BCM6368_CLK_SAR 11 -#define BCM6368_CLK_ROBOSW 12 -#define BCM6368_CLK_UTOPIA 13 -#define BCM6368_CLK_PCM 14 -#define BCM6368_CLK_USBH 15 -#define BCM6368_CLK_GLESS 16 -#define BCM6368_CLK_NAND 17 -#define BCM6368_CLK_IPSEC 18 -#define BCM6368_CLK_USBH_IDDQ 19 - -#endif /* __DT_BINDINGS_CLOCK_BCM6368_H */ diff --git a/include/dt-bindings/clock/boston-clock.h b/include/dt-bindings/clock/boston-clock.h deleted file mode 100644 index 0b3906247c8..00000000000 --- a/include/dt-bindings/clock/boston-clock.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Imagination Technologies - */ - -#ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ -#define __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ - -#define BOSTON_CLK_SYS 0 -#define BOSTON_CLK_CPU 1 - -#endif /* __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__ */ diff --git a/include/dt-bindings/clock/hi6220-clock.h b/include/dt-bindings/clock/hi6220-clock.h deleted file mode 100644 index 70ee3833a7a..00000000000 --- a/include/dt-bindings/clock/hi6220-clock.h +++ /dev/null @@ -1,173 +0,0 @@ -/* - * Copyright (c) 2015 Hisilicon Limited. - * - * Author: Bintian Wang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __DT_BINDINGS_CLOCK_HI6220_H -#define __DT_BINDINGS_CLOCK_HI6220_H - -/* clk in Hi6220 AO (always on) controller */ -#define HI6220_NONE_CLOCK 0 - -/* fixed rate clocks */ -#define HI6220_REF32K 1 -#define HI6220_CLK_TCXO 2 -#define HI6220_MMC1_PAD 3 -#define HI6220_MMC2_PAD 4 -#define HI6220_MMC0_PAD 5 -#define HI6220_PLL_BBP 6 -#define HI6220_PLL_GPU 7 -#define HI6220_PLL1_DDR 8 -#define HI6220_PLL_SYS 9 -#define HI6220_PLL_SYS_MEDIA 10 -#define HI6220_DDR_SRC 11 -#define HI6220_PLL_MEDIA 12 -#define HI6220_PLL_DDR 13 - -/* fixed factor clocks */ -#define HI6220_300M 14 -#define HI6220_150M 15 -#define HI6220_PICOPHY_SRC 16 -#define HI6220_MMC0_SRC_SEL 17 -#define HI6220_MMC1_SRC_SEL 18 -#define HI6220_MMC2_SRC_SEL 19 -#define HI6220_VPU_CODEC 20 -#define HI6220_MMC0_SMP 21 -#define HI6220_MMC1_SMP 22 -#define HI6220_MMC2_SMP 23 - -/* gate clocks */ -#define HI6220_WDT0_PCLK 24 -#define HI6220_WDT1_PCLK 25 -#define HI6220_WDT2_PCLK 26 -#define HI6220_TIMER0_PCLK 27 -#define HI6220_TIMER1_PCLK 28 -#define HI6220_TIMER2_PCLK 29 -#define HI6220_TIMER3_PCLK 30 -#define HI6220_TIMER4_PCLK 31 -#define HI6220_TIMER5_PCLK 32 -#define HI6220_TIMER6_PCLK 33 -#define HI6220_TIMER7_PCLK 34 -#define HI6220_TIMER8_PCLK 35 -#define HI6220_UART0_PCLK 36 - -#define HI6220_AO_NR_CLKS 37 - -/* clk in Hi6220 systrl */ -/* gate clock */ -#define HI6220_MMC0_CLK 1 -#define HI6220_MMC0_CIUCLK 2 -#define HI6220_MMC1_CLK 3 -#define HI6220_MMC1_CIUCLK 4 -#define HI6220_MMC2_CLK 5 -#define HI6220_MMC2_CIUCLK 6 -#define HI6220_USBOTG_HCLK 7 -#define HI6220_CLK_PICOPHY 8 -#define HI6220_HIFI 9 -#define HI6220_DACODEC_PCLK 10 -#define HI6220_EDMAC_ACLK 11 -#define HI6220_CS_ATB 12 -#define HI6220_I2C0_CLK 13 -#define HI6220_I2C1_CLK 14 -#define HI6220_I2C2_CLK 15 -#define HI6220_I2C3_CLK 16 -#define HI6220_UART1_PCLK 17 -#define HI6220_UART2_PCLK 18 -#define HI6220_UART3_PCLK 19 -#define HI6220_UART4_PCLK 20 -#define HI6220_SPI_CLK 21 -#define HI6220_TSENSOR_CLK 22 -#define HI6220_MMU_CLK 23 -#define HI6220_HIFI_SEL 24 -#define HI6220_MMC0_SYSPLL 25 -#define HI6220_MMC1_SYSPLL 26 -#define HI6220_MMC2_SYSPLL 27 -#define HI6220_MMC0_SEL 28 -#define HI6220_MMC1_SEL 29 -#define HI6220_BBPPLL_SEL 30 -#define HI6220_MEDIA_PLL_SRC 31 -#define HI6220_MMC2_SEL 32 -#define HI6220_CS_ATB_SYSPLL 33 - -/* mux clocks */ -#define HI6220_MMC0_SRC 34 -#define HI6220_MMC0_SMP_IN 35 -#define HI6220_MMC1_SRC 36 -#define HI6220_MMC1_SMP_IN 37 -#define HI6220_MMC2_SRC 38 -#define HI6220_MMC2_SMP_IN 39 -#define HI6220_HIFI_SRC 40 -#define HI6220_UART1_SRC 41 -#define HI6220_UART2_SRC 42 -#define HI6220_UART3_SRC 43 -#define HI6220_UART4_SRC 44 -#define HI6220_MMC0_MUX0 45 -#define HI6220_MMC1_MUX0 46 -#define HI6220_MMC2_MUX0 47 -#define HI6220_MMC0_MUX1 48 -#define HI6220_MMC1_MUX1 49 -#define HI6220_MMC2_MUX1 50 - -/* divider clocks */ -#define HI6220_CLK_BUS 51 -#define HI6220_MMC0_DIV 52 -#define HI6220_MMC1_DIV 53 -#define HI6220_MMC2_DIV 54 -#define HI6220_HIFI_DIV 55 -#define HI6220_BBPPLL0_DIV 56 -#define HI6220_CS_DAPB 57 -#define HI6220_CS_ATB_DIV 58 - -#define HI6220_SYS_NR_CLKS 59 - -/* clk in Hi6220 media controller */ -/* gate clocks */ -#define HI6220_DSI_PCLK 1 -#define HI6220_G3D_PCLK 2 -#define HI6220_ACLK_CODEC_VPU 3 -#define HI6220_ISP_SCLK 4 -#define HI6220_ADE_CORE 5 -#define HI6220_MED_MMU 6 -#define HI6220_CFG_CSI4PHY 7 -#define HI6220_CFG_CSI2PHY 8 -#define HI6220_ISP_SCLK_GATE 9 -#define HI6220_ISP_SCLK_GATE1 10 -#define HI6220_ADE_CORE_GATE 11 -#define HI6220_CODEC_VPU_GATE 12 -#define HI6220_MED_SYSPLL 13 - -/* mux clocks */ -#define HI6220_1440_1200 14 -#define HI6220_1000_1200 15 -#define HI6220_1000_1440 16 - -/* divider clocks */ -#define HI6220_CODEC_JPEG 17 -#define HI6220_ISP_SCLK_SRC 18 -#define HI6220_ISP_SCLK1 19 -#define HI6220_ADE_CORE_SRC 20 -#define HI6220_ADE_PIX_SRC 21 -#define HI6220_G3D_CLK 22 -#define HI6220_CODEC_VPU_SRC 23 - -#define HI6220_MEDIA_NR_CLKS 24 - -/* clk in Hi6220 power controller */ -/* gate clocks */ -#define HI6220_PLL_GPU_GATE 1 -#define HI6220_PLL1_DDR_GATE 2 -#define HI6220_PLL_DDR_GATE 3 -#define HI6220_PLL_MEDIA_GATE 4 -#define HI6220_PLL0_BBP_GATE 5 - -/* divider clocks */ -#define HI6220_DDRC_SRC 6 -#define HI6220_DDRC_AXI1 7 - -#define HI6220_POWER_NR_CLKS 8 -#endif diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h deleted file mode 100644 index 0a06c5f514d..00000000000 --- a/include/dt-bindings/clock/rk3368-cru.h +++ /dev/null @@ -1,381 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2015 Heiko Stuebner - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H - -/* core clocks */ -#define PLL_APLLB 1 -#define PLL_APLLL 2 -#define PLL_DPLL 3 -#define PLL_CPLL 4 -#define PLL_GPLL 5 -#define PLL_NPLL 6 -#define ARMCLKB 7 -#define ARMCLKL 8 - -/* sclk gates (special clocks) */ -#define SCLK_GPU_CORE 64 -#define SCLK_SPI0 65 -#define SCLK_SPI1 66 -#define SCLK_SPI2 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO0 69 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_SARADC 73 -#define SCLK_NANDC0 75 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_UART3 80 -#define SCLK_UART4 81 -#define SCLK_I2S_8CH 82 -#define SCLK_SPDIF_8CH 83 -#define SCLK_I2S_2CH 84 -#define SCLK_TIMER00 85 -#define SCLK_TIMER01 86 -#define SCLK_TIMER02 87 -#define SCLK_TIMER03 88 -#define SCLK_TIMER04 89 -#define SCLK_TIMER05 90 -#define SCLK_OTGPHY0 93 -#define SCLK_OTG_ADP 96 -#define SCLK_HSICPHY480M 97 -#define SCLK_HSICPHY12M 98 -#define SCLK_MACREF 99 -#define SCLK_VOP0_PWM 100 -#define SCLK_MAC_RX 102 -#define SCLK_MAC_TX 103 -#define SCLK_EDP_24M 104 -#define SCLK_EDP 105 -#define SCLK_RGA 106 -#define SCLK_ISP 107 -#define SCLK_HDCP 108 -#define SCLK_HDMI_HDCP 109 -#define SCLK_HDMI_CEC 110 -#define SCLK_HEVC_CABAC 111 -#define SCLK_HEVC_CORE 112 -#define SCLK_I2S_8CH_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO0_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO0_SAMPLE 119 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_USBPHY480M 122 -#define SCLK_PVTM_CORE 123 -#define SCLK_PVTM_GPU 124 -#define SCLK_PVTM_PMU 125 -#define SCLK_SFC 126 -#define SCLK_MAC 127 -#define SCLK_MACREF_OUT 128 -#define SCLK_TIMER10 133 -#define SCLK_TIMER11 134 -#define SCLK_TIMER12 135 -#define SCLK_TIMER13 136 -#define SCLK_TIMER14 137 -#define SCLK_TIMER15 138 - -#define DCLK_VOP 190 -#define MCLK_CRYPTO 191 - -/* aclk gates */ -#define ACLK_GPU_MEM 192 -#define ACLK_GPU_CFG 193 -#define ACLK_DMAC_BUS 194 -#define ACLK_DMAC_PERI 195 -#define ACLK_PERI_MMU 196 -#define ACLK_GMAC 197 -#define ACLK_VOP 198 -#define ACLK_VOP_IEP 199 -#define ACLK_RGA 200 -#define ACLK_HDCP 201 -#define ACLK_IEP 202 -#define ACLK_VIO0_NOC 203 -#define ACLK_VIP 204 -#define ACLK_ISP 205 -#define ACLK_VIO1_NOC 206 -#define ACLK_VIDEO 208 -#define ACLK_BUS 209 -#define ACLK_PERI 210 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_PMUGRF 324 -#define PCLK_MAILBOX 325 -#define PCLK_GRF 329 -#define PCLK_SGRF 330 -#define PCLK_PMU 331 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_I2C4 336 -#define PCLK_I2C5 337 -#define PCLK_SPI0 338 -#define PCLK_SPI1 339 -#define PCLK_SPI2 340 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_UART3 344 -#define PCLK_UART4 345 -#define PCLK_TSADC 346 -#define PCLK_SARADC 347 -#define PCLK_SIM 348 -#define PCLK_GMAC 349 -#define PCLK_PWM0 350 -#define PCLK_PWM1 351 -#define PCLK_TIMER0 353 -#define PCLK_TIMER1 354 -#define PCLK_EDP_CTRL 355 -#define PCLK_MIPI_DSI0 356 -#define PCLK_MIPI_CSI 358 -#define PCLK_HDCP 359 -#define PCLK_HDMI_CTRL 360 -#define PCLK_VIO_H2P 361 -#define PCLK_BUS 362 -#define PCLK_PERI 363 -#define PCLK_DDRUPCTL 364 -#define PCLK_DDRPHY 365 -#define PCLK_ISP 366 -#define PCLK_VIP 367 -#define PCLK_WDT 368 -#define PCLK_EFUSE256 369 - -/* hclk gates */ -#define HCLK_SFC 448 -#define HCLK_OTG0 449 -#define HCLK_HOST0 450 -#define HCLK_HOST1 451 -#define HCLK_HSIC 452 -#define HCLK_NANDC0 453 -#define HCLK_TSP 455 -#define HCLK_SDMMC 456 -#define HCLK_SDIO0 457 -#define HCLK_EMMC 459 -#define HCLK_HSADC 460 -#define HCLK_CRYPTO 461 -#define HCLK_I2S_2CH 462 -#define HCLK_I2S_8CH 463 -#define HCLK_SPDIF 464 -#define HCLK_VOP 465 -#define HCLK_ROM 467 -#define HCLK_IEP 468 -#define HCLK_ISP 469 -#define HCLK_RGA 470 -#define HCLK_VIO_AHB_ARBI 471 -#define HCLK_VIO_NOC 472 -#define HCLK_VIP 473 -#define HCLK_VIO_H2P 474 -#define HCLK_VIO_HDCPMMU 475 -#define HCLK_VIDEO 476 -#define HCLK_BUS 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE_B0 0 -#define SRST_CORE_B1 1 -#define SRST_CORE_B2 2 -#define SRST_CORE_B3 3 -#define SRST_CORE_B0_PO 4 -#define SRST_CORE_B1_PO 5 -#define SRST_CORE_B2_PO 6 -#define SRST_CORE_B3_PO 7 -#define SRST_L2_B 8 -#define SRST_ADB_B 9 -#define SRST_PD_CORE_B_NIU 10 -#define SRST_PDBUS_STRSYS 11 -#define SRST_SOCDBG_B 14 -#define SRST_CORE_B_DBG 15 - -#define SRST_DMAC1 18 -#define SRST_INTMEM 19 -#define SRST_ROM 20 -#define SRST_SPDIF8CH 21 -#define SRST_I2S8CH 23 -#define SRST_MAILBOX 24 -#define SRST_I2S2CH 25 -#define SRST_EFUSE_256 26 -#define SRST_MCU_SYS 28 -#define SRST_MCU_PO 29 -#define SRST_MCU_NOC 30 -#define SRST_EFUSE 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_GPIO4 36 -#define SRST_PMUGRF 41 -#define SRST_I2C0 42 -#define SRST_I2C1 43 -#define SRST_I2C2 44 -#define SRST_I2C3 45 -#define SRST_I2C4 46 -#define SRST_I2C5 47 - -#define SRST_DWPWM 48 -#define SRST_MMC_PERI 49 -#define SRST_PERIPH_MMU 50 -#define SRST_GRF 55 -#define SRST_PMU 56 -#define SRST_PERIPH_AXI 57 -#define SRST_PERIPH_AHB 58 -#define SRST_PERIPH_APB 59 -#define SRST_PERIPH_NIU 60 -#define SRST_PDPERI_AHB_ARBI 61 -#define SRST_EMEM 62 -#define SRST_USB_PERI 63 - -#define SRST_DMAC2 64 -#define SRST_MAC 66 -#define SRST_GPS 67 -#define SRST_RKPWM 69 -#define SRST_USBHOST0 72 -#define SRST_HSIC 73 -#define SRST_HSIC_AUX 74 -#define SRST_HSIC_PHY 75 -#define SRST_HSADC 76 -#define SRST_NANDC0 77 -#define SRST_SFC 79 - -#define SRST_SPI0 83 -#define SRST_SPI1 84 -#define SRST_SPI2 85 -#define SRST_SARADC 87 -#define SRST_PDALIVE_NIU 88 -#define SRST_PDPMU_INTMEM 89 -#define SRST_PDPMU_NIU 90 -#define SRST_SGRF 91 - -#define SRST_VIO_ARBI 96 -#define SRST_RGA_NIU 97 -#define SRST_VIO0_NIU_AXI 98 -#define SRST_VIO_NIU_AHB 99 -#define SRST_LCDC0_AXI 100 -#define SRST_LCDC0_AHB 101 -#define SRST_LCDC0_DCLK 102 -#define SRST_VIP 104 -#define SRST_RGA_CORE 105 -#define SRST_IEP_AXI 106 -#define SRST_IEP_AHB 107 -#define SRST_RGA_AXI 108 -#define SRST_RGA_AHB 109 -#define SRST_ISP 110 -#define SRST_EDP_24M 111 - -#define SRST_VIDEO_AXI 112 -#define SRST_VIDEO_AHB 113 -#define SRST_MIPIDPHYTX 114 -#define SRST_MIPIDSI0 115 -#define SRST_MIPIDPHYRX 116 -#define SRST_MIPICSI 117 -#define SRST_GPU 120 -#define SRST_HDMI 121 -#define SRST_EDP 122 -#define SRST_PMU_PVTM 123 -#define SRST_CORE_PVTM 124 -#define SRST_GPU_PVTM 125 -#define SRST_GPU_SYS 126 -#define SRST_GPU_MEM_NIU 127 - -#define SRST_MMC0 128 -#define SRST_SDIO0 129 -#define SRST_EMMC 131 -#define SRST_USBOTG_AHB 132 -#define SRST_USBOTG_PHY 133 -#define SRST_USBOTG_CON 134 -#define SRST_USBHOST0_AHB 135 -#define SRST_USBHOST0_PHY 136 -#define SRST_USBHOST0_CON 137 -#define SRST_USBOTG_UTMI 138 -#define SRST_USBHOST1_UTMI 139 -#define SRST_USB_ADP 141 - -#define SRST_CORESIGHT 144 -#define SRST_PD_CORE_AHB_NOC 145 -#define SRST_PD_CORE_APB_NOC 146 -#define SRST_GIC 148 -#define SRST_LCDC_PWM0 149 -#define SRST_RGA_H2P_BRG 153 -#define SRST_VIDEO 154 -#define SRST_GPU_CFG_NIU 157 -#define SRST_TSADC 159 - -#define SRST_DDRPHY0 160 -#define SRST_DDRPHY0_APB 161 -#define SRST_DDRCTRL0 162 -#define SRST_DDRCTRL0_APB 163 -#define SRST_VIDEO_NIU 165 -#define SRST_VIDEO_NIU_AHB 167 -#define SRST_DDRMSCH0 170 -#define SRST_PDBUS_AHB 173 -#define SRST_CRYPTO 174 - -#define SRST_UART0 179 -#define SRST_UART1 180 -#define SRST_UART2 181 -#define SRST_UART3 182 -#define SRST_UART4 183 -#define SRST_SIMC 186 -#define SRST_TSP 188 -#define SRST_TSP_CLKIN0 189 - -#define SRST_CORE_L0 192 -#define SRST_CORE_L1 193 -#define SRST_CORE_L2 194 -#define SRST_CORE_L3 195 -#define SRST_CORE_L0_PO 195 -#define SRST_CORE_L1_PO 197 -#define SRST_CORE_L2_PO 198 -#define SRST_CORE_L3_PO 199 -#define SRST_L2_L 200 -#define SRST_ADB_L 201 -#define SRST_PD_CORE_L_NIU 202 -#define SRST_CCI_SYS 203 -#define SRST_CCI_DDR 204 -#define SRST_CCI 205 -#define SRST_SOCDBG_L 206 -#define SRST_CORE_L_DBG 207 - -#define SRST_CORE_B0_NC 208 -#define SRST_CORE_B0_PO_NC 209 -#define SRST_L2_B_NC 210 -#define SRST_ADB_B_NC 211 -#define SRST_PD_CORE_B_NIU_NC 212 -#define SRST_PDBUS_STRSYS_NC 213 -#define SRST_CORE_L0_NC 214 -#define SRST_CORE_L0_PO_NC 215 -#define SRST_L2_L_NC 216 -#define SRST_ADB_L_NC 217 -#define SRST_PD_CORE_L_NIU_NC 218 -#define SRST_CCI_SYS_NC 219 -#define SRST_CCI_DDR_NC 220 -#define SRST_CCI_NC 221 -#define SRST_TRACE_NC 222 - -#define SRST_TIMER00 224 -#define SRST_TIMER01 225 -#define SRST_TIMER02 226 -#define SRST_TIMER03 227 -#define SRST_TIMER04 228 -#define SRST_TIMER05 229 -#define SRST_TIMER10 230 -#define SRST_TIMER11 231 -#define SRST_TIMER12 232 -#define SRST_TIMER13 233 -#define SRST_TIMER14 234 -#define SRST_TIMER15 235 -#define SRST_TIMER0_APB 236 -#define SRST_TIMER1_APB 237 - -#endif diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h deleted file mode 100644 index 534c03f8ad7..00000000000 --- a/include/dt-bindings/clock/tegra114-car.h +++ /dev/null @@ -1,343 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra114-car. - * - * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 160 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 160 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H - -/* 0 */ -/* 1 */ -/* 2 */ -/* 3 */ -#define TEGRA114_CLK_RTC 4 -#define TEGRA114_CLK_TIMER 5 -#define TEGRA114_CLK_UARTA 6 -/* 7 (register bit affects uartb and vfir) */ -/* 8 */ -#define TEGRA114_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA114_CLK_I2S1 11 -#define TEGRA114_CLK_I2C1 12 -#define TEGRA114_CLK_NDFLASH 13 -#define TEGRA114_CLK_SDMMC1 14 -#define TEGRA114_CLK_SDMMC4 15 -/* 16 */ -#define TEGRA114_CLK_PWM 17 -#define TEGRA114_CLK_I2S2 18 -#define TEGRA114_CLK_EPP 19 -/* 20 (register bit affects vi and vi_sensor) */ -#define TEGRA114_CLK_GR2D 21 -#define TEGRA114_CLK_USBD 22 -#define TEGRA114_CLK_ISP 23 -#define TEGRA114_CLK_GR3D 24 -/* 25 */ -#define TEGRA114_CLK_DISP2 26 -#define TEGRA114_CLK_DISP1 27 -#define TEGRA114_CLK_HOST1X 28 -#define TEGRA114_CLK_VCP 29 -#define TEGRA114_CLK_I2S0 30 -/* 31 */ - -#define TEGRA114_CLK_MC 32 -/* 33 */ -#define TEGRA114_CLK_APBDMA 34 -/* 35 */ -#define TEGRA114_CLK_KBC 36 -/* 37 */ -/* 38 */ -/* 39 (register bit affects fuse and fuse_burn) */ -#define TEGRA114_CLK_KFUSE 40 -#define TEGRA114_CLK_SBC1 41 -#define TEGRA114_CLK_NOR 42 -/* 43 */ -#define TEGRA114_CLK_SBC2 44 -/* 45 */ -#define TEGRA114_CLK_SBC3 46 -#define TEGRA114_CLK_I2C5 47 -#define TEGRA114_CLK_DSIA 48 -/* 49 */ -#define TEGRA114_CLK_MIPI 50 -#define TEGRA114_CLK_HDMI 51 -#define TEGRA114_CLK_CSI 52 -/* 53 */ -#define TEGRA114_CLK_I2C2 54 -#define TEGRA114_CLK_UARTC 55 -#define TEGRA114_CLK_MIPI_CAL 56 -#define TEGRA114_CLK_EMC 57 -#define TEGRA114_CLK_USB2 58 -#define TEGRA114_CLK_USB3 59 -/* 60 */ -#define TEGRA114_CLK_VDE 61 -#define TEGRA114_CLK_BSEA 62 -#define TEGRA114_CLK_BSEV 63 - -/* 64 */ -#define TEGRA114_CLK_UARTD 65 -/* 66 */ -#define TEGRA114_CLK_I2C3 67 -#define TEGRA114_CLK_SBC4 68 -#define TEGRA114_CLK_SDMMC3 69 -/* 70 */ -#define TEGRA114_CLK_OWR 71 -/* 72 */ -#define TEGRA114_CLK_CSITE 73 -/* 74 */ -/* 75 */ -#define TEGRA114_CLK_LA 76 -#define TEGRA114_CLK_TRACE 77 -#define TEGRA114_CLK_SOC_THERM 78 -#define TEGRA114_CLK_DTV 79 -#define TEGRA114_CLK_NDSPEED 80 -#define TEGRA114_CLK_I2CSLOW 81 -#define TEGRA114_CLK_DSIB 82 -#define TEGRA114_CLK_TSEC 83 -/* 84 */ -/* 85 */ -/* 86 */ -/* 87 */ -/* 88 */ -#define TEGRA114_CLK_XUSB_HOST 89 -/* 90 */ -#define TEGRA114_CLK_MSENC 91 -#define TEGRA114_CLK_CSUS 92 -/* 93 */ -/* 94 */ -/* 95 (bit affects xusb_dev and xusb_dev_src) */ - -/* 96 */ -/* 97 */ -/* 98 */ -#define TEGRA114_CLK_MSELECT 99 -#define TEGRA114_CLK_TSENSOR 100 -#define TEGRA114_CLK_I2S3 101 -#define TEGRA114_CLK_I2S4 102 -#define TEGRA114_CLK_I2C4 103 -#define TEGRA114_CLK_SBC5 104 -#define TEGRA114_CLK_SBC6 105 -#define TEGRA114_CLK_D_AUDIO 106 -#define TEGRA114_CLK_APBIF 107 -#define TEGRA114_CLK_DAM0 108 -#define TEGRA114_CLK_DAM1 109 -#define TEGRA114_CLK_DAM2 110 -#define TEGRA114_CLK_HDA2CODEC_2X 111 -/* 112 */ -#define TEGRA114_CLK_AUDIO0_2X 113 -#define TEGRA114_CLK_AUDIO1_2X 114 -#define TEGRA114_CLK_AUDIO2_2X 115 -#define TEGRA114_CLK_AUDIO3_2X 116 -#define TEGRA114_CLK_AUDIO4_2X 117 -#define TEGRA114_CLK_SPDIF_2X 118 -#define TEGRA114_CLK_ACTMON 119 -#define TEGRA114_CLK_EXTERN1 120 -#define TEGRA114_CLK_EXTERN2 121 -#define TEGRA114_CLK_EXTERN3 122 -/* 123 */ -/* 124 */ -#define TEGRA114_CLK_HDA 125 -/* 126 */ -#define TEGRA114_CLK_SE 127 - -#define TEGRA114_CLK_HDA2HDMI 128 -/* 129 */ -/* 130 */ -/* 131 */ -/* 132 */ -/* 133 */ -/* 134 */ -/* 135 */ -/* 136 */ -/* 137 */ -/* 138 */ -/* 139 */ -/* 140 */ -/* 141 */ -/* 142 */ -/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ -/* xusb_host_src and xusb_ss_src) */ -#define TEGRA114_CLK_CILAB 144 -#define TEGRA114_CLK_CILCD 145 -#define TEGRA114_CLK_CILE 146 -#define TEGRA114_CLK_DSIALP 147 -#define TEGRA114_CLK_DSIBLP 148 -/* 149 */ -#define TEGRA114_CLK_DDS 150 -/* 151 */ -#define TEGRA114_CLK_DP2 152 -#define TEGRA114_CLK_AMX 153 -#define TEGRA114_CLK_ADX 154 -/* 155 (bit affects dfll_ref and dfll_soc) */ -#define TEGRA114_CLK_XUSB_SS 156 -/* 157 */ -/* 158 */ -/* 159 */ - -/* 160 */ -/* 161 */ -/* 162 */ -/* 163 */ -/* 164 */ -/* 165 */ -/* 166 */ -/* 167 */ -/* 168 */ -/* 169 */ -/* 170 */ -/* 171 */ -/* 172 */ -/* 173 */ -/* 174 */ -/* 175 */ -/* 176 */ -/* 177 */ -/* 178 */ -/* 179 */ -/* 180 */ -/* 181 */ -/* 182 */ -/* 183 */ -/* 184 */ -/* 185 */ -/* 186 */ -/* 187 */ -/* 188 */ -/* 189 */ -/* 190 */ -/* 191 */ - -#define TEGRA114_CLK_UARTB 192 -#define TEGRA114_CLK_VFIR 193 -#define TEGRA114_CLK_SPDIF_IN 194 -#define TEGRA114_CLK_SPDIF_OUT 195 -#define TEGRA114_CLK_VI 196 -#define TEGRA114_CLK_VI_SENSOR 197 -#define TEGRA114_CLK_FUSE 198 -#define TEGRA114_CLK_FUSE_BURN 199 -#define TEGRA114_CLK_CLK_32K 200 -#define TEGRA114_CLK_CLK_M 201 -#define TEGRA114_CLK_CLK_M_DIV2 202 -#define TEGRA114_CLK_CLK_M_DIV4 203 -#define TEGRA114_CLK_PLL_REF 204 -#define TEGRA114_CLK_PLL_C 205 -#define TEGRA114_CLK_PLL_C_OUT1 206 -#define TEGRA114_CLK_PLL_C2 207 -#define TEGRA114_CLK_PLL_C3 208 -#define TEGRA114_CLK_PLL_M 209 -#define TEGRA114_CLK_PLL_M_OUT1 210 -#define TEGRA114_CLK_PLL_P 211 -#define TEGRA114_CLK_PLL_P_OUT1 212 -#define TEGRA114_CLK_PLL_P_OUT2 213 -#define TEGRA114_CLK_PLL_P_OUT3 214 -#define TEGRA114_CLK_PLL_P_OUT4 215 -#define TEGRA114_CLK_PLL_A 216 -#define TEGRA114_CLK_PLL_A_OUT0 217 -#define TEGRA114_CLK_PLL_D 218 -#define TEGRA114_CLK_PLL_D_OUT0 219 -#define TEGRA114_CLK_PLL_D2 220 -#define TEGRA114_CLK_PLL_D2_OUT0 221 -#define TEGRA114_CLK_PLL_U 222 -#define TEGRA114_CLK_PLL_U_480M 223 - -#define TEGRA114_CLK_PLL_U_60M 224 -#define TEGRA114_CLK_PLL_U_48M 225 -#define TEGRA114_CLK_PLL_U_12M 226 -#define TEGRA114_CLK_PLL_X 227 -#define TEGRA114_CLK_PLL_X_OUT0 228 -#define TEGRA114_CLK_PLL_RE_VCO 229 -#define TEGRA114_CLK_PLL_RE_OUT 230 -#define TEGRA114_CLK_PLL_E_OUT0 231 -#define TEGRA114_CLK_SPDIF_IN_SYNC 232 -#define TEGRA114_CLK_I2S0_SYNC 233 -#define TEGRA114_CLK_I2S1_SYNC 234 -#define TEGRA114_CLK_I2S2_SYNC 235 -#define TEGRA114_CLK_I2S3_SYNC 236 -#define TEGRA114_CLK_I2S4_SYNC 237 -#define TEGRA114_CLK_VIMCLK_SYNC 238 -#define TEGRA114_CLK_AUDIO0 239 -#define TEGRA114_CLK_AUDIO1 240 -#define TEGRA114_CLK_AUDIO2 241 -#define TEGRA114_CLK_AUDIO3 242 -#define TEGRA114_CLK_AUDIO4 243 -#define TEGRA114_CLK_SPDIF 244 -#define TEGRA114_CLK_CLK_OUT_1 245 -#define TEGRA114_CLK_CLK_OUT_2 246 -#define TEGRA114_CLK_CLK_OUT_3 247 -#define TEGRA114_CLK_BLINK 248 -/* 249 */ -/* 250 */ -/* 251 */ -#define TEGRA114_CLK_XUSB_HOST_SRC 252 -#define TEGRA114_CLK_XUSB_FALCON_SRC 253 -#define TEGRA114_CLK_XUSB_FS_SRC 254 -#define TEGRA114_CLK_XUSB_SS_SRC 255 - -#define TEGRA114_CLK_XUSB_DEV_SRC 256 -#define TEGRA114_CLK_XUSB_DEV 257 -#define TEGRA114_CLK_XUSB_HS_SRC 258 -#define TEGRA114_CLK_SCLK 259 -#define TEGRA114_CLK_HCLK 260 -#define TEGRA114_CLK_PCLK 261 -#define TEGRA114_CLK_CCLK_G 262 -#define TEGRA114_CLK_CCLK_LP 263 -#define TEGRA114_CLK_DFLL_REF 264 -#define TEGRA114_CLK_DFLL_SOC 265 -/* 266 */ -/* 267 */ -/* 268 */ -/* 269 */ -/* 270 */ -/* 271 */ -/* 272 */ -/* 273 */ -/* 274 */ -/* 275 */ -/* 276 */ -/* 277 */ -/* 278 */ -/* 279 */ -/* 280 */ -/* 281 */ -/* 282 */ -/* 283 */ -/* 284 */ -/* 285 */ -/* 286 */ -/* 287 */ - -/* 288 */ -/* 289 */ -/* 290 */ -/* 291 */ -/* 292 */ -/* 293 */ -/* 294 */ -/* 295 */ -/* 296 */ -/* 297 */ -/* 298 */ -/* 299 */ -#define TEGRA114_CLK_AUDIO0_MUX 300 -#define TEGRA114_CLK_AUDIO1_MUX 301 -#define TEGRA114_CLK_AUDIO2_MUX 302 -#define TEGRA114_CLK_AUDIO3_MUX 303 -#define TEGRA114_CLK_AUDIO4_MUX 304 -#define TEGRA114_CLK_SPDIF_MUX 305 -#define TEGRA114_CLK_CLK_OUT_1_MUX 306 -#define TEGRA114_CLK_CLK_OUT_2_MUX 307 -#define TEGRA114_CLK_CLK_OUT_3_MUX 308 -#define TEGRA114_CLK_DSIA_MUX 309 -#define TEGRA114_CLK_DSIB_MUX 310 -#define TEGRA114_CLK_XUSB_SS_DIV2 311 -#define TEGRA114_CLK_CLK_MAX 312 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ diff --git a/include/dt-bindings/clock/tegra124-car-common.h b/include/dt-bindings/clock/tegra124-car-common.h deleted file mode 100644 index a2156090563..00000000000 --- a/include/dt-bindings/clock/tegra124-car-common.h +++ /dev/null @@ -1,345 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra124-car or - * nvidia,tegra132-car. - * - * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 185 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 185 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H -#define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H - -/* 0 */ -/* 1 */ -/* 2 */ -#define TEGRA124_CLK_ISPB 3 -#define TEGRA124_CLK_RTC 4 -#define TEGRA124_CLK_TIMER 5 -#define TEGRA124_CLK_UARTA 6 -/* 7 (register bit affects uartb and vfir) */ -/* 8 */ -#define TEGRA124_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA124_CLK_I2S1 11 -#define TEGRA124_CLK_I2C1 12 -/* 13 */ -#define TEGRA124_CLK_SDMMC1 14 -#define TEGRA124_CLK_SDMMC4 15 -/* 16 */ -#define TEGRA124_CLK_PWM 17 -#define TEGRA124_CLK_I2S2 18 -/* 20 (register bit affects vi and vi_sensor) */ -/* 21 */ -#define TEGRA124_CLK_USBD 22 -#define TEGRA124_CLK_ISP 23 -/* 26 */ -/* 25 */ -#define TEGRA124_CLK_DISP2 26 -#define TEGRA124_CLK_DISP1 27 -#define TEGRA124_CLK_HOST1X 28 -#define TEGRA124_CLK_VCP 29 -#define TEGRA124_CLK_I2S0 30 -/* 31 */ - -#define TEGRA124_CLK_MC 32 -/* 33 */ -#define TEGRA124_CLK_APBDMA 34 -/* 35 */ -#define TEGRA124_CLK_KBC 36 -/* 37 */ -/* 38 */ -/* 39 (register bit affects fuse and fuse_burn) */ -#define TEGRA124_CLK_KFUSE 40 -#define TEGRA124_CLK_SBC1 41 -#define TEGRA124_CLK_NOR 42 -/* 43 */ -#define TEGRA124_CLK_SBC2 44 -/* 45 */ -#define TEGRA124_CLK_SBC3 46 -#define TEGRA124_CLK_I2C5 47 -#define TEGRA124_CLK_DSIA 48 -/* 49 */ -#define TEGRA124_CLK_MIPI 50 -#define TEGRA124_CLK_HDMI 51 -#define TEGRA124_CLK_CSI 52 -/* 53 */ -#define TEGRA124_CLK_I2C2 54 -#define TEGRA124_CLK_UARTC 55 -#define TEGRA124_CLK_MIPI_CAL 56 -#define TEGRA124_CLK_EMC 57 -#define TEGRA124_CLK_USB2 58 -#define TEGRA124_CLK_USB3 59 -/* 60 */ -#define TEGRA124_CLK_VDE 61 -#define TEGRA124_CLK_BSEA 62 -#define TEGRA124_CLK_BSEV 63 - -/* 64 */ -#define TEGRA124_CLK_UARTD 65 -/* 66 */ -#define TEGRA124_CLK_I2C3 67 -#define TEGRA124_CLK_SBC4 68 -#define TEGRA124_CLK_SDMMC3 69 -#define TEGRA124_CLK_PCIE 70 -#define TEGRA124_CLK_OWR 71 -#define TEGRA124_CLK_AFI 72 -#define TEGRA124_CLK_CSITE 73 -/* 74 */ -/* 75 */ -#define TEGRA124_CLK_LA 76 -#define TEGRA124_CLK_TRACE 77 -#define TEGRA124_CLK_SOC_THERM 78 -#define TEGRA124_CLK_DTV 79 -/* 80 */ -#define TEGRA124_CLK_I2CSLOW 81 -#define TEGRA124_CLK_DSIB 82 -#define TEGRA124_CLK_TSEC 83 -/* 84 */ -/* 85 */ -/* 86 */ -/* 87 */ -/* 88 */ -#define TEGRA124_CLK_XUSB_HOST 89 -/* 90 */ -#define TEGRA124_CLK_MSENC 91 -#define TEGRA124_CLK_CSUS 92 -/* 93 */ -/* 94 */ -/* 95 (bit affects xusb_dev and xusb_dev_src) */ - -/* 96 */ -/* 97 */ -/* 98 */ -#define TEGRA124_CLK_MSELECT 99 -#define TEGRA124_CLK_TSENSOR 100 -#define TEGRA124_CLK_I2S3 101 -#define TEGRA124_CLK_I2S4 102 -#define TEGRA124_CLK_I2C4 103 -#define TEGRA124_CLK_SBC5 104 -#define TEGRA124_CLK_SBC6 105 -#define TEGRA124_CLK_D_AUDIO 106 -#define TEGRA124_CLK_APBIF 107 -#define TEGRA124_CLK_DAM0 108 -#define TEGRA124_CLK_DAM1 109 -#define TEGRA124_CLK_DAM2 110 -#define TEGRA124_CLK_HDA2CODEC_2X 111 -/* 112 */ -#define TEGRA124_CLK_AUDIO0_2X 113 -#define TEGRA124_CLK_AUDIO1_2X 114 -#define TEGRA124_CLK_AUDIO2_2X 115 -#define TEGRA124_CLK_AUDIO3_2X 116 -#define TEGRA124_CLK_AUDIO4_2X 117 -#define TEGRA124_CLK_SPDIF_2X 118 -#define TEGRA124_CLK_ACTMON 119 -#define TEGRA124_CLK_EXTERN1 120 -#define TEGRA124_CLK_EXTERN2 121 -#define TEGRA124_CLK_EXTERN3 122 -#define TEGRA124_CLK_SATA_OOB 123 -#define TEGRA124_CLK_SATA 124 -#define TEGRA124_CLK_HDA 125 -/* 126 */ -#define TEGRA124_CLK_SE 127 - -#define TEGRA124_CLK_HDA2HDMI 128 -#define TEGRA124_CLK_SATA_COLD 129 -/* 130 */ -/* 131 */ -/* 132 */ -/* 133 */ -/* 134 */ -/* 135 */ -/* 136 */ -/* 137 */ -/* 138 */ -/* 139 */ -/* 140 */ -/* 141 */ -/* 142 */ -/* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ -/* xusb_host_src and xusb_ss_src) */ -#define TEGRA124_CLK_CILAB 144 -#define TEGRA124_CLK_CILCD 145 -#define TEGRA124_CLK_CILE 146 -#define TEGRA124_CLK_DSIALP 147 -#define TEGRA124_CLK_DSIBLP 148 -#define TEGRA124_CLK_ENTROPY 149 -#define TEGRA124_CLK_DDS 150 -/* 151 */ -#define TEGRA124_CLK_DP2 152 -#define TEGRA124_CLK_AMX 153 -#define TEGRA124_CLK_ADX 154 -/* 155 (bit affects dfll_ref and dfll_soc) */ -#define TEGRA124_CLK_XUSB_SS 156 -/* 157 */ -/* 158 */ -/* 159 */ - -/* 160 */ -/* 161 */ -/* 162 */ -/* 163 */ -/* 164 */ -/* 165 */ -#define TEGRA124_CLK_I2C6 166 -/* 167 */ -/* 168 */ -/* 169 */ -/* 170 */ -#define TEGRA124_CLK_VIM2_CLK 171 -/* 172 */ -/* 173 */ -/* 174 */ -/* 175 */ -#define TEGRA124_CLK_HDMI_AUDIO 176 -#define TEGRA124_CLK_CLK72MHZ 177 -#define TEGRA124_CLK_VIC03 178 -/* 179 */ -#define TEGRA124_CLK_ADX1 180 -#define TEGRA124_CLK_DPAUX 181 -#define TEGRA124_CLK_SOR0 182 -/* 183 */ -#define TEGRA124_CLK_GPU 184 -#define TEGRA124_CLK_AMX1 185 -/* 186 */ -/* 187 */ -/* 188 */ -/* 189 */ -/* 190 */ -/* 191 */ -#define TEGRA124_CLK_UARTB 192 -#define TEGRA124_CLK_VFIR 193 -#define TEGRA124_CLK_SPDIF_IN 194 -#define TEGRA124_CLK_SPDIF_OUT 195 -#define TEGRA124_CLK_VI 196 -#define TEGRA124_CLK_VI_SENSOR 197 -#define TEGRA124_CLK_FUSE 198 -#define TEGRA124_CLK_FUSE_BURN 199 -#define TEGRA124_CLK_CLK_32K 200 -#define TEGRA124_CLK_CLK_M 201 -#define TEGRA124_CLK_CLK_M_DIV2 202 -#define TEGRA124_CLK_CLK_M_DIV4 203 -#define TEGRA124_CLK_PLL_REF 204 -#define TEGRA124_CLK_PLL_C 205 -#define TEGRA124_CLK_PLL_C_OUT1 206 -#define TEGRA124_CLK_PLL_C2 207 -#define TEGRA124_CLK_PLL_C3 208 -#define TEGRA124_CLK_PLL_M 209 -#define TEGRA124_CLK_PLL_M_OUT1 210 -#define TEGRA124_CLK_PLL_P 211 -#define TEGRA124_CLK_PLL_P_OUT1 212 -#define TEGRA124_CLK_PLL_P_OUT2 213 -#define TEGRA124_CLK_PLL_P_OUT3 214 -#define TEGRA124_CLK_PLL_P_OUT4 215 -#define TEGRA124_CLK_PLL_A 216 -#define TEGRA124_CLK_PLL_A_OUT0 217 -#define TEGRA124_CLK_PLL_D 218 -#define TEGRA124_CLK_PLL_D_OUT0 219 -#define TEGRA124_CLK_PLL_D2 220 -#define TEGRA124_CLK_PLL_D2_OUT0 221 -#define TEGRA124_CLK_PLL_U 222 -#define TEGRA124_CLK_PLL_U_480M 223 - -#define TEGRA124_CLK_PLL_U_60M 224 -#define TEGRA124_CLK_PLL_U_48M 225 -#define TEGRA124_CLK_PLL_U_12M 226 -/* 227 */ -/* 228 */ -#define TEGRA124_CLK_PLL_RE_VCO 229 -#define TEGRA124_CLK_PLL_RE_OUT 230 -#define TEGRA124_CLK_PLL_E 231 -#define TEGRA124_CLK_SPDIF_IN_SYNC 232 -#define TEGRA124_CLK_I2S0_SYNC 233 -#define TEGRA124_CLK_I2S1_SYNC 234 -#define TEGRA124_CLK_I2S2_SYNC 235 -#define TEGRA124_CLK_I2S3_SYNC 236 -#define TEGRA124_CLK_I2S4_SYNC 237 -#define TEGRA124_CLK_VIMCLK_SYNC 238 -#define TEGRA124_CLK_AUDIO0 239 -#define TEGRA124_CLK_AUDIO1 240 -#define TEGRA124_CLK_AUDIO2 241 -#define TEGRA124_CLK_AUDIO3 242 -#define TEGRA124_CLK_AUDIO4 243 -#define TEGRA124_CLK_SPDIF 244 -#define TEGRA124_CLK_CLK_OUT_1 245 -#define TEGRA124_CLK_CLK_OUT_2 246 -#define TEGRA124_CLK_CLK_OUT_3 247 -#define TEGRA124_CLK_BLINK 248 -/* 249 */ -/* 250 */ -/* 251 */ -#define TEGRA124_CLK_XUSB_HOST_SRC 252 -#define TEGRA124_CLK_XUSB_FALCON_SRC 253 -#define TEGRA124_CLK_XUSB_FS_SRC 254 -#define TEGRA124_CLK_XUSB_SS_SRC 255 - -#define TEGRA124_CLK_XUSB_DEV_SRC 256 -#define TEGRA124_CLK_XUSB_DEV 257 -#define TEGRA124_CLK_XUSB_HS_SRC 258 -#define TEGRA124_CLK_SCLK 259 -#define TEGRA124_CLK_HCLK 260 -#define TEGRA124_CLK_PCLK 261 -/* 262 */ -/* 263 */ -#define TEGRA124_CLK_DFLL_REF 264 -#define TEGRA124_CLK_DFLL_SOC 265 -#define TEGRA124_CLK_VI_SENSOR2 266 -#define TEGRA124_CLK_PLL_P_OUT5 267 -#define TEGRA124_CLK_CML0 268 -#define TEGRA124_CLK_CML1 269 -#define TEGRA124_CLK_PLL_C4 270 -#define TEGRA124_CLK_PLL_DP 271 -#define TEGRA124_CLK_PLL_E_MUX 272 -#define TEGRA124_CLK_PLL_D_DSI_OUT 273 -/* 274 */ -/* 275 */ -/* 276 */ -/* 277 */ -/* 278 */ -/* 279 */ -/* 280 */ -/* 281 */ -/* 282 */ -/* 283 */ -/* 284 */ -/* 285 */ -/* 286 */ -/* 287 */ - -/* 288 */ -/* 289 */ -/* 290 */ -/* 291 */ -/* 292 */ -/* 293 */ -/* 294 */ -/* 295 */ -/* 296 */ -/* 297 */ -/* 298 */ -/* 299 */ -#define TEGRA124_CLK_AUDIO0_MUX 300 -#define TEGRA124_CLK_AUDIO1_MUX 301 -#define TEGRA124_CLK_AUDIO2_MUX 302 -#define TEGRA124_CLK_AUDIO3_MUX 303 -#define TEGRA124_CLK_AUDIO4_MUX 304 -#define TEGRA124_CLK_SPDIF_MUX 305 -#define TEGRA124_CLK_CLK_OUT_1_MUX 306 -#define TEGRA124_CLK_CLK_OUT_2_MUX 307 -#define TEGRA124_CLK_CLK_OUT_3_MUX 308 -/* 309 */ -/* 310 */ -#define TEGRA124_CLK_SOR0_LVDS 311 -#define TEGRA124_CLK_XUSB_SS_DIV2 312 - -#define TEGRA124_CLK_PLL_M_UD 313 -#define TEGRA124_CLK_PLL_C_UD 314 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */ diff --git a/include/dt-bindings/clock/tegra20-car.h b/include/dt-bindings/clock/tegra20-car.h deleted file mode 100644 index 04500b243a4..00000000000 --- a/include/dt-bindings/clock/tegra20-car.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra20-car. - * - * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 95 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 96 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H - -#define TEGRA20_CLK_CPU 0 -/* 1 */ -/* 2 */ -#define TEGRA20_CLK_AC97 3 -#define TEGRA20_CLK_RTC 4 -#define TEGRA20_CLK_TIMER 5 -#define TEGRA20_CLK_UARTA 6 -/* 7 (register bit affects uart2 and vfir) */ -#define TEGRA20_CLK_GPIO 8 -#define TEGRA20_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA20_CLK_I2S1 11 -#define TEGRA20_CLK_I2C1 12 -#define TEGRA20_CLK_NDFLASH 13 -#define TEGRA20_CLK_SDMMC1 14 -#define TEGRA20_CLK_SDMMC4 15 -#define TEGRA20_CLK_TWC 16 -#define TEGRA20_CLK_PWM 17 -#define TEGRA20_CLK_I2S2 18 -#define TEGRA20_CLK_EPP 19 -/* 20 (register bit affects vi and vi_sensor) */ -#define TEGRA20_CLK_GR2D 21 -#define TEGRA20_CLK_USBD 22 -#define TEGRA20_CLK_ISP 23 -#define TEGRA20_CLK_GR3D 24 -#define TEGRA20_CLK_IDE 25 -#define TEGRA20_CLK_DISP2 26 -#define TEGRA20_CLK_DISP1 27 -#define TEGRA20_CLK_HOST1X 28 -#define TEGRA20_CLK_VCP 29 -/* 30 */ -#define TEGRA20_CLK_CACHE2 31 - -#define TEGRA20_CLK_MC 32 -#define TEGRA20_CLK_AHBDMA 33 -#define TEGRA20_CLK_APBDMA 34 -/* 35 */ -#define TEGRA20_CLK_KBC 36 -#define TEGRA20_CLK_STAT_MON 37 -#define TEGRA20_CLK_PMC 38 -#define TEGRA20_CLK_FUSE 39 -#define TEGRA20_CLK_KFUSE 40 -#define TEGRA20_CLK_SBC1 41 -#define TEGRA20_CLK_NOR 42 -#define TEGRA20_CLK_SPI 43 -#define TEGRA20_CLK_SBC2 44 -#define TEGRA20_CLK_XIO 45 -#define TEGRA20_CLK_SBC3 46 -#define TEGRA20_CLK_DVC 47 -#define TEGRA20_CLK_DSI 48 -/* 49 (register bit affects tvo and cve) */ -#define TEGRA20_CLK_MIPI 50 -#define TEGRA20_CLK_HDMI 51 -#define TEGRA20_CLK_CSI 52 -#define TEGRA20_CLK_TVDAC 53 -#define TEGRA20_CLK_I2C2 54 -#define TEGRA20_CLK_UARTC 55 -/* 56 */ -#define TEGRA20_CLK_EMC 57 -#define TEGRA20_CLK_USB2 58 -#define TEGRA20_CLK_USB3 59 -#define TEGRA20_CLK_MPE 60 -#define TEGRA20_CLK_VDE 61 -#define TEGRA20_CLK_BSEA 62 -#define TEGRA20_CLK_BSEV 63 - -#define TEGRA20_CLK_SPEEDO 64 -#define TEGRA20_CLK_UARTD 65 -#define TEGRA20_CLK_UARTE 66 -#define TEGRA20_CLK_I2C3 67 -#define TEGRA20_CLK_SBC4 68 -#define TEGRA20_CLK_SDMMC3 69 -#define TEGRA20_CLK_PEX 70 -#define TEGRA20_CLK_OWR 71 -#define TEGRA20_CLK_AFI 72 -#define TEGRA20_CLK_CSITE 73 -/* 74 */ -#define TEGRA20_CLK_AVPUCQ 75 -#define TEGRA20_CLK_LA 76 -/* 77 */ -/* 78 */ -/* 79 */ -/* 80 */ -/* 81 */ -/* 82 */ -/* 83 */ -#define TEGRA20_CLK_IRAMA 84 -#define TEGRA20_CLK_IRAMB 85 -#define TEGRA20_CLK_IRAMC 86 -#define TEGRA20_CLK_IRAMD 87 -#define TEGRA20_CLK_CRAM2 88 -#define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */ -#define TEGRA20_CLK_CLK_D 90 -/* 91 */ -#define TEGRA20_CLK_CSUS 92 -#define TEGRA20_CLK_CDEV2 93 -#define TEGRA20_CLK_CDEV1 94 -/* 95 */ - -#define TEGRA20_CLK_UARTB 96 -#define TEGRA20_CLK_VFIR 97 -#define TEGRA20_CLK_SPDIF_IN 98 -#define TEGRA20_CLK_SPDIF_OUT 99 -#define TEGRA20_CLK_VI 100 -#define TEGRA20_CLK_VI_SENSOR 101 -#define TEGRA20_CLK_TVO 102 -#define TEGRA20_CLK_CVE 103 -#define TEGRA20_CLK_OSC 104 -#define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */ -#define TEGRA20_CLK_CLK_M 106 -#define TEGRA20_CLK_SCLK 107 -#define TEGRA20_CLK_CCLK 108 -#define TEGRA20_CLK_HCLK 109 -#define TEGRA20_CLK_PCLK 110 -#define TEGRA20_CLK_BLINK 111 -#define TEGRA20_CLK_PLL_A 112 -#define TEGRA20_CLK_PLL_A_OUT0 113 -#define TEGRA20_CLK_PLL_C 114 -#define TEGRA20_CLK_PLL_C_OUT1 115 -#define TEGRA20_CLK_PLL_D 116 -#define TEGRA20_CLK_PLL_D_OUT0 117 -#define TEGRA20_CLK_PLL_E 118 -#define TEGRA20_CLK_PLL_M 119 -#define TEGRA20_CLK_PLL_M_OUT1 120 -#define TEGRA20_CLK_PLL_P 121 -#define TEGRA20_CLK_PLL_P_OUT1 122 -#define TEGRA20_CLK_PLL_P_OUT2 123 -#define TEGRA20_CLK_PLL_P_OUT3 124 -#define TEGRA20_CLK_PLL_P_OUT4 125 -#define TEGRA20_CLK_PLL_S 126 -#define TEGRA20_CLK_PLL_U 127 - -#define TEGRA20_CLK_PLL_X 128 -#define TEGRA20_CLK_COP 129 /* a/k/a avp */ -#define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */ -#define TEGRA20_CLK_PLL_REF 131 -#define TEGRA20_CLK_TWD 132 -#define TEGRA20_CLK_CLK_MAX 133 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */ diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h deleted file mode 100644 index eddac16800d..00000000000 --- a/include/dt-bindings/clock/tegra210-car.h +++ /dev/null @@ -1,400 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra210-car. - * - * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 224 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 224 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H - -/* 0 */ -/* 1 */ -/* 2 */ -#define TEGRA210_CLK_ISPB 3 -#define TEGRA210_CLK_RTC 4 -#define TEGRA210_CLK_TIMER 5 -#define TEGRA210_CLK_UARTA 6 -/* 7 (register bit affects uartb and vfir) */ -#define TEGRA210_CLK_GPIO 8 -#define TEGRA210_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA210_CLK_I2S1 11 -#define TEGRA210_CLK_I2C1 12 -/* 13 */ -#define TEGRA210_CLK_SDMMC1 14 -#define TEGRA210_CLK_SDMMC4 15 -/* 16 */ -#define TEGRA210_CLK_PWM 17 -#define TEGRA210_CLK_I2S2 18 -/* 19 */ -/* 20 (register bit affects vi and vi_sensor) */ -/* 21 */ -#define TEGRA210_CLK_USBD 22 -#define TEGRA210_CLK_ISP 23 -/* 24 */ -/* 25 */ -#define TEGRA210_CLK_DISP2 26 -#define TEGRA210_CLK_DISP1 27 -#define TEGRA210_CLK_HOST1X 28 -/* 29 */ -#define TEGRA210_CLK_I2S0 30 -/* 31 */ - -#define TEGRA210_CLK_MC 32 -#define TEGRA210_CLK_AHBDMA 33 -#define TEGRA210_CLK_APBDMA 34 -/* 35 */ -/* 36 */ -/* 37 */ -#define TEGRA210_CLK_PMC 38 -/* 39 (register bit affects fuse and fuse_burn) */ -#define TEGRA210_CLK_KFUSE 40 -#define TEGRA210_CLK_SBC1 41 -/* 42 */ -/* 43 */ -#define TEGRA210_CLK_SBC2 44 -/* 45 */ -#define TEGRA210_CLK_SBC3 46 -#define TEGRA210_CLK_I2C5 47 -#define TEGRA210_CLK_DSIA 48 -/* 49 */ -/* 50 */ -/* 51 */ -#define TEGRA210_CLK_CSI 52 -/* 53 */ -#define TEGRA210_CLK_I2C2 54 -#define TEGRA210_CLK_UARTC 55 -#define TEGRA210_CLK_MIPI_CAL 56 -#define TEGRA210_CLK_EMC 57 -#define TEGRA210_CLK_USB2 58 -/* 59 */ -/* 60 */ -/* 61 */ -/* 62 */ -#define TEGRA210_CLK_BSEV 63 - -/* 64 */ -#define TEGRA210_CLK_UARTD 65 -/* 66 */ -#define TEGRA210_CLK_I2C3 67 -#define TEGRA210_CLK_SBC4 68 -#define TEGRA210_CLK_SDMMC3 69 -#define TEGRA210_CLK_PCIE 70 -#define TEGRA210_CLK_OWR 71 -#define TEGRA210_CLK_AFI 72 -#define TEGRA210_CLK_CSITE 73 -/* 74 */ -/* 75 */ -/* 76 */ -/* 77 */ -#define TEGRA210_CLK_SOC_THERM 78 -#define TEGRA210_CLK_DTV 79 -/* 80 */ -#define TEGRA210_CLK_I2CSLOW 81 -#define TEGRA210_CLK_DSIB 82 -#define TEGRA210_CLK_TSEC 83 -/* 84 */ -/* 85 */ -/* 86 */ -/* 87 */ -/* 88 */ -#define TEGRA210_CLK_XUSB_HOST 89 -/* 90 */ -/* 91 */ -#define TEGRA210_CLK_CSUS 92 -/* 93 */ -/* 94 */ -/* 95 (bit affects xusb_dev and xusb_dev_src) */ - -/* 96 */ -/* 97 */ -/* 98 */ -#define TEGRA210_CLK_MSELECT 99 -#define TEGRA210_CLK_TSENSOR 100 -#define TEGRA210_CLK_I2S3 101 -#define TEGRA210_CLK_I2S4 102 -#define TEGRA210_CLK_I2C4 103 -/* 104 */ -/* 105 */ -#define TEGRA210_CLK_D_AUDIO 106 -#define TEGRA210_CLK_APB2APE 107 -/* 108 */ -/* 109 */ -/* 110 */ -#define TEGRA210_CLK_HDA2CODEC_2X 111 -/* 112 */ -/* 113 */ -/* 114 */ -/* 115 */ -/* 116 */ -/* 117 */ -#define TEGRA210_CLK_SPDIF_2X 118 -#define TEGRA210_CLK_ACTMON 119 -#define TEGRA210_CLK_EXTERN1 120 -#define TEGRA210_CLK_EXTERN2 121 -#define TEGRA210_CLK_EXTERN3 122 -#define TEGRA210_CLK_SATA_OOB 123 -#define TEGRA210_CLK_SATA 124 -#define TEGRA210_CLK_HDA 125 -/* 126 */ -/* 127 */ - -#define TEGRA210_CLK_HDA2HDMI 128 -/* 129 */ -/* 130 */ -/* 131 */ -/* 132 */ -/* 133 */ -/* 134 */ -/* 135 */ -/* 136 */ -/* 137 */ -/* 138 */ -/* 139 */ -/* 140 */ -/* 141 */ -/* 142 */ -/* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */ -#define TEGRA210_CLK_XUSB_GATE 143 -#define TEGRA210_CLK_CILAB 144 -#define TEGRA210_CLK_CILCD 145 -#define TEGRA210_CLK_CILE 146 -#define TEGRA210_CLK_DSIALP 147 -#define TEGRA210_CLK_DSIBLP 148 -#define TEGRA210_CLK_ENTROPY 149 -/* 150 */ -/* 151 */ -/* 152 */ -/* 153 */ -/* 154 */ -/* 155 (bit affects dfll_ref and dfll_soc) */ -#define TEGRA210_CLK_XUSB_SS 156 -/* 157 */ -/* 158 */ -/* 159 */ - -/* 160 */ -#define TEGRA210_CLK_DMIC1 161 -#define TEGRA210_CLK_DMIC2 162 -/* 163 */ -/* 164 */ -/* 165 */ -#define TEGRA210_CLK_I2C6 166 -/* 167 */ -/* 168 */ -/* 169 */ -/* 170 */ -#define TEGRA210_CLK_VIM2_CLK 171 -/* 172 */ -#define TEGRA210_CLK_MIPIBIF 173 -/* 174 */ -/* 175 */ -/* 176 */ -#define TEGRA210_CLK_CLK72MHZ 177 -#define TEGRA210_CLK_VIC03 178 -/* 179 */ -/* 180 */ -#define TEGRA210_CLK_DPAUX 181 -#define TEGRA210_CLK_SOR0 182 -#define TEGRA210_CLK_SOR1 183 -#define TEGRA210_CLK_GPU 184 -#define TEGRA210_CLK_DBGAPB 185 -/* 186 */ -#define TEGRA210_CLK_PLL_P_OUT_ADSP 187 -/* 188 */ -#define TEGRA210_CLK_PLL_G_REF 189 -/* 190 */ -/* 191 */ - -/* 192 */ -#define TEGRA210_CLK_SDMMC_LEGACY 193 -#define TEGRA210_CLK_NVDEC 194 -#define TEGRA210_CLK_NVJPG 195 -/* 196 */ -#define TEGRA210_CLK_DMIC3 197 -#define TEGRA210_CLK_APE 198 -/* 199 */ -/* 200 */ -/* 201 */ -#define TEGRA210_CLK_MAUD 202 -/* 203 */ -/* 204 */ -/* 205 */ -#define TEGRA210_CLK_TSECB 206 -#define TEGRA210_CLK_DPAUX1 207 -#define TEGRA210_CLK_VI_I2C 208 -#define TEGRA210_CLK_HSIC_TRK 209 -#define TEGRA210_CLK_USB2_TRK 210 -#define TEGRA210_CLK_QSPI 211 -#define TEGRA210_CLK_UARTAPE 212 -/* 213 */ -/* 214 */ -/* 215 */ -/* 216 */ -/* 217 */ -/* 218 */ -#define TEGRA210_CLK_NVENC 219 -/* 220 */ -/* 221 */ -#define TEGRA210_CLK_SOR_SAFE 222 -#define TEGRA210_CLK_PLL_P_OUT_CPU 223 - -#define TEGRA210_CLK_UARTB 224 -#define TEGRA210_CLK_VFIR 225 -#define TEGRA210_CLK_SPDIF_IN 226 -#define TEGRA210_CLK_SPDIF_OUT 227 -#define TEGRA210_CLK_VI 228 -#define TEGRA210_CLK_VI_SENSOR 229 -#define TEGRA210_CLK_FUSE 230 -#define TEGRA210_CLK_FUSE_BURN 231 -#define TEGRA210_CLK_CLK_32K 232 -#define TEGRA210_CLK_CLK_M 233 -#define TEGRA210_CLK_CLK_M_DIV2 234 -#define TEGRA210_CLK_CLK_M_DIV4 235 -#define TEGRA210_CLK_PLL_REF 236 -#define TEGRA210_CLK_PLL_C 237 -#define TEGRA210_CLK_PLL_C_OUT1 238 -#define TEGRA210_CLK_PLL_C2 239 -#define TEGRA210_CLK_PLL_C3 240 -#define TEGRA210_CLK_PLL_M 241 -#define TEGRA210_CLK_PLL_M_OUT1 242 -#define TEGRA210_CLK_PLL_P 243 -#define TEGRA210_CLK_PLL_P_OUT1 244 -#define TEGRA210_CLK_PLL_P_OUT2 245 -#define TEGRA210_CLK_PLL_P_OUT3 246 -#define TEGRA210_CLK_PLL_P_OUT4 247 -#define TEGRA210_CLK_PLL_A 248 -#define TEGRA210_CLK_PLL_A_OUT0 249 -#define TEGRA210_CLK_PLL_D 250 -#define TEGRA210_CLK_PLL_D_OUT0 251 -#define TEGRA210_CLK_PLL_D2 252 -#define TEGRA210_CLK_PLL_D2_OUT0 253 -#define TEGRA210_CLK_PLL_U 254 -#define TEGRA210_CLK_PLL_U_480M 255 - -#define TEGRA210_CLK_PLL_U_60M 256 -#define TEGRA210_CLK_PLL_U_48M 257 -/* 258 */ -#define TEGRA210_CLK_PLL_X 259 -#define TEGRA210_CLK_PLL_X_OUT0 260 -#define TEGRA210_CLK_PLL_RE_VCO 261 -#define TEGRA210_CLK_PLL_RE_OUT 262 -#define TEGRA210_CLK_PLL_E 263 -#define TEGRA210_CLK_SPDIF_IN_SYNC 264 -#define TEGRA210_CLK_I2S0_SYNC 265 -#define TEGRA210_CLK_I2S1_SYNC 266 -#define TEGRA210_CLK_I2S2_SYNC 267 -#define TEGRA210_CLK_I2S3_SYNC 268 -#define TEGRA210_CLK_I2S4_SYNC 269 -#define TEGRA210_CLK_VIMCLK_SYNC 270 -#define TEGRA210_CLK_AUDIO0 271 -#define TEGRA210_CLK_AUDIO1 272 -#define TEGRA210_CLK_AUDIO2 273 -#define TEGRA210_CLK_AUDIO3 274 -#define TEGRA210_CLK_AUDIO4 275 -#define TEGRA210_CLK_SPDIF 276 -#define TEGRA210_CLK_CLK_OUT_1 277 -#define TEGRA210_CLK_CLK_OUT_2 278 -#define TEGRA210_CLK_CLK_OUT_3 279 -#define TEGRA210_CLK_BLINK 280 -/* 281 */ -/* 282 */ -/* 283 */ -#define TEGRA210_CLK_XUSB_HOST_SRC 284 -#define TEGRA210_CLK_XUSB_FALCON_SRC 285 -#define TEGRA210_CLK_XUSB_FS_SRC 286 -#define TEGRA210_CLK_XUSB_SS_SRC 287 - -#define TEGRA210_CLK_XUSB_DEV_SRC 288 -#define TEGRA210_CLK_XUSB_DEV 289 -#define TEGRA210_CLK_XUSB_HS_SRC 290 -#define TEGRA210_CLK_SCLK 291 -#define TEGRA210_CLK_HCLK 292 -#define TEGRA210_CLK_PCLK 293 -#define TEGRA210_CLK_CCLK_G 294 -#define TEGRA210_CLK_CCLK_LP 295 -#define TEGRA210_CLK_DFLL_REF 296 -#define TEGRA210_CLK_DFLL_SOC 297 -#define TEGRA210_CLK_VI_SENSOR2 298 -#define TEGRA210_CLK_PLL_P_OUT5 299 -#define TEGRA210_CLK_CML0 300 -#define TEGRA210_CLK_CML1 301 -#define TEGRA210_CLK_PLL_C4 302 -#define TEGRA210_CLK_PLL_DP 303 -#define TEGRA210_CLK_PLL_E_MUX 304 -#define TEGRA210_CLK_PLL_MB 305 -#define TEGRA210_CLK_PLL_A1 306 -#define TEGRA210_CLK_PLL_D_DSI_OUT 307 -#define TEGRA210_CLK_PLL_C4_OUT0 308 -#define TEGRA210_CLK_PLL_C4_OUT1 309 -#define TEGRA210_CLK_PLL_C4_OUT2 310 -#define TEGRA210_CLK_PLL_C4_OUT3 311 -#define TEGRA210_CLK_PLL_U_OUT 312 -#define TEGRA210_CLK_PLL_U_OUT1 313 -#define TEGRA210_CLK_PLL_U_OUT2 314 -#define TEGRA210_CLK_USB2_HSIC_TRK 315 -#define TEGRA210_CLK_PLL_P_OUT_HSIO 316 -#define TEGRA210_CLK_PLL_P_OUT_XUSB 317 -#define TEGRA210_CLK_XUSB_SSP_SRC 318 -#define TEGRA210_CLK_PLL_RE_OUT1 319 -/* 320 */ -/* 321 */ -/* 322 */ -/* 323 */ -/* 324 */ -/* 325 */ -/* 326 */ -/* 327 */ -/* 328 */ -/* 329 */ -/* 330 */ -/* 331 */ -/* 332 */ -/* 333 */ -/* 334 */ -/* 335 */ -/* 336 */ -/* 337 */ -/* 338 */ -/* 339 */ -/* 340 */ -/* 341 */ -/* 342 */ -/* 343 */ -/* 344 */ -/* 345 */ -/* 346 */ -/* 347 */ -/* 348 */ -/* 349 */ - -#define TEGRA210_CLK_AUDIO0_MUX 350 -#define TEGRA210_CLK_AUDIO1_MUX 351 -#define TEGRA210_CLK_AUDIO2_MUX 352 -#define TEGRA210_CLK_AUDIO3_MUX 353 -#define TEGRA210_CLK_AUDIO4_MUX 354 -#define TEGRA210_CLK_SPDIF_MUX 355 -#define TEGRA210_CLK_CLK_OUT_1_MUX 356 -#define TEGRA210_CLK_CLK_OUT_2_MUX 357 -#define TEGRA210_CLK_CLK_OUT_3_MUX 358 -#define TEGRA210_CLK_DSIA_MUX 359 -#define TEGRA210_CLK_DSIB_MUX 360 -#define TEGRA210_CLK_SOR0_LVDS 361 -#define TEGRA210_CLK_XUSB_SS_DIV2 362 - -#define TEGRA210_CLK_PLL_M_UD 363 -#define TEGRA210_CLK_PLL_C_UD 364 -#define TEGRA210_CLK_SCLK_MUX 365 - -#define TEGRA210_CLK_CLK_MAX 366 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/clock/tegra30-car.h deleted file mode 100644 index 889e49ba0aa..00000000000 --- a/include/dt-bindings/clock/tegra30-car.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * This header provides constants for binding nvidia,tegra30-car. - * - * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB - * registers. These IDs often match those in the CAR's RST_DEVICES registers, - * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In - * this case, those clocks are assigned IDs above 160 in order to highlight - * this issue. Implementations that interpret these clock IDs as bit values - * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to - * explicitly handle these special cases. - * - * The balance of the clocks controlled by the CAR are assigned IDs of 160 and - * above. - */ - -#ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H -#define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H - -#define TEGRA30_CLK_CPU 0 -/* 1 */ -/* 2 */ -/* 3 */ -#define TEGRA30_CLK_RTC 4 -#define TEGRA30_CLK_TIMER 5 -#define TEGRA30_CLK_UARTA 6 -/* 7 (register bit affects uartb and vfir) */ -#define TEGRA30_CLK_GPIO 8 -#define TEGRA30_CLK_SDMMC2 9 -/* 10 (register bit affects spdif_in and spdif_out) */ -#define TEGRA30_CLK_I2S1 11 -#define TEGRA30_CLK_I2C1 12 -#define TEGRA30_CLK_NDFLASH 13 -#define TEGRA30_CLK_SDMMC1 14 -#define TEGRA30_CLK_SDMMC4 15 -/* 16 */ -#define TEGRA30_CLK_PWM 17 -#define TEGRA30_CLK_I2S2 18 -#define TEGRA30_CLK_EPP 19 -/* 20 (register bit affects vi and vi_sensor) */ -#define TEGRA30_CLK_GR2D 21 -#define TEGRA30_CLK_USBD 22 -#define TEGRA30_CLK_ISP 23 -#define TEGRA30_CLK_GR3D 24 -/* 25 */ -#define TEGRA30_CLK_DISP2 26 -#define TEGRA30_CLK_DISP1 27 -#define TEGRA30_CLK_HOST1X 28 -#define TEGRA30_CLK_VCP 29 -#define TEGRA30_CLK_I2S0 30 -#define TEGRA30_CLK_COP_CACHE 31 - -#define TEGRA30_CLK_MC 32 -#define TEGRA30_CLK_AHBDMA 33 -#define TEGRA30_CLK_APBDMA 34 -/* 35 */ -#define TEGRA30_CLK_KBC 36 -#define TEGRA30_CLK_STATMON 37 -#define TEGRA30_CLK_PMC 38 -/* 39 (register bit affects fuse and fuse_burn) */ -#define TEGRA30_CLK_KFUSE 40 -#define TEGRA30_CLK_SBC1 41 -#define TEGRA30_CLK_NOR 42 -/* 43 */ -#define TEGRA30_CLK_SBC2 44 -/* 45 */ -#define TEGRA30_CLK_SBC3 46 -#define TEGRA30_CLK_I2C5 47 -#define TEGRA30_CLK_DSIA 48 -/* 49 (register bit affects cve and tvo) */ -#define TEGRA30_CLK_MIPI 50 -#define TEGRA30_CLK_HDMI 51 -#define TEGRA30_CLK_CSI 52 -#define TEGRA30_CLK_TVDAC 53 -#define TEGRA30_CLK_I2C2 54 -#define TEGRA30_CLK_UARTC 55 -/* 56 */ -#define TEGRA30_CLK_EMC 57 -#define TEGRA30_CLK_USB2 58 -#define TEGRA30_CLK_USB3 59 -#define TEGRA30_CLK_MPE 60 -#define TEGRA30_CLK_VDE 61 -#define TEGRA30_CLK_BSEA 62 -#define TEGRA30_CLK_BSEV 63 - -#define TEGRA30_CLK_SPEEDO 64 -#define TEGRA30_CLK_UARTD 65 -#define TEGRA30_CLK_UARTE 66 -#define TEGRA30_CLK_I2C3 67 -#define TEGRA30_CLK_SBC4 68 -#define TEGRA30_CLK_SDMMC3 69 -#define TEGRA30_CLK_PCIE 70 -#define TEGRA30_CLK_OWR 71 -#define TEGRA30_CLK_AFI 72 -#define TEGRA30_CLK_CSITE 73 -/* 74 */ -#define TEGRA30_CLK_AVPUCQ 75 -#define TEGRA30_CLK_LA 76 -/* 77 */ -/* 78 */ -#define TEGRA30_CLK_DTV 79 -#define TEGRA30_CLK_NDSPEED 80 -#define TEGRA30_CLK_I2CSLOW 81 -#define TEGRA30_CLK_DSIB 82 -/* 83 */ -#define TEGRA30_CLK_IRAMA 84 -#define TEGRA30_CLK_IRAMB 85 -#define TEGRA30_CLK_IRAMC 86 -#define TEGRA30_CLK_IRAMD 87 -#define TEGRA30_CLK_CRAM2 88 -/* 89 */ -#define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */ -/* 91 */ -#define TEGRA30_CLK_CSUS 92 -#define TEGRA30_CLK_CDEV2 93 -#define TEGRA30_CLK_CDEV1 94 -/* 95 */ - -#define TEGRA30_CLK_CPU_G 96 -#define TEGRA30_CLK_CPU_LP 97 -#define TEGRA30_CLK_GR3D2 98 -#define TEGRA30_CLK_MSELECT 99 -#define TEGRA30_CLK_TSENSOR 100 -#define TEGRA30_CLK_I2S3 101 -#define TEGRA30_CLK_I2S4 102 -#define TEGRA30_CLK_I2C4 103 -#define TEGRA30_CLK_SBC5 104 -#define TEGRA30_CLK_SBC6 105 -#define TEGRA30_CLK_D_AUDIO 106 -#define TEGRA30_CLK_APBIF 107 -#define TEGRA30_CLK_DAM0 108 -#define TEGRA30_CLK_DAM1 109 -#define TEGRA30_CLK_DAM2 110 -#define TEGRA30_CLK_HDA2CODEC_2X 111 -#define TEGRA30_CLK_ATOMICS 112 -#define TEGRA30_CLK_AUDIO0_2X 113 -#define TEGRA30_CLK_AUDIO1_2X 114 -#define TEGRA30_CLK_AUDIO2_2X 115 -#define TEGRA30_CLK_AUDIO3_2X 116 -#define TEGRA30_CLK_AUDIO4_2X 117 -#define TEGRA30_CLK_SPDIF_2X 118 -#define TEGRA30_CLK_ACTMON 119 -#define TEGRA30_CLK_EXTERN1 120 -#define TEGRA30_CLK_EXTERN2 121 -#define TEGRA30_CLK_EXTERN3 122 -#define TEGRA30_CLK_SATA_OOB 123 -#define TEGRA30_CLK_SATA 124 -#define TEGRA30_CLK_HDA 125 -/* 126 */ -#define TEGRA30_CLK_SE 127 - -#define TEGRA30_CLK_HDA2HDMI 128 -#define TEGRA30_CLK_SATA_COLD 129 -/* 130 */ -/* 131 */ -/* 132 */ -/* 133 */ -/* 134 */ -/* 135 */ -/* 136 */ -/* 137 */ -/* 138 */ -/* 139 */ -/* 140 */ -/* 141 */ -/* 142 */ -/* 143 */ -/* 144 */ -/* 145 */ -/* 146 */ -/* 147 */ -/* 148 */ -/* 149 */ -/* 150 */ -/* 151 */ -/* 152 */ -/* 153 */ -/* 154 */ -/* 155 */ -/* 156 */ -/* 157 */ -/* 158 */ -/* 159 */ - -#define TEGRA30_CLK_UARTB 160 -#define TEGRA30_CLK_VFIR 161 -#define TEGRA30_CLK_SPDIF_IN 162 -#define TEGRA30_CLK_SPDIF_OUT 163 -#define TEGRA30_CLK_VI 164 -#define TEGRA30_CLK_VI_SENSOR 165 -#define TEGRA30_CLK_FUSE 166 -#define TEGRA30_CLK_FUSE_BURN 167 -#define TEGRA30_CLK_CVE 168 -#define TEGRA30_CLK_TVO 169 -#define TEGRA30_CLK_CLK_32K 170 -#define TEGRA30_CLK_CLK_M 171 -#define TEGRA30_CLK_CLK_M_DIV2 172 -#define TEGRA30_CLK_CLK_M_DIV4 173 -#define TEGRA30_CLK_PLL_REF 174 -#define TEGRA30_CLK_PLL_C 175 -#define TEGRA30_CLK_PLL_C_OUT1 176 -#define TEGRA30_CLK_PLL_M 177 -#define TEGRA30_CLK_PLL_M_OUT1 178 -#define TEGRA30_CLK_PLL_P 179 -#define TEGRA30_CLK_PLL_P_OUT1 180 -#define TEGRA30_CLK_PLL_P_OUT2 181 -#define TEGRA30_CLK_PLL_P_OUT3 182 -#define TEGRA30_CLK_PLL_P_OUT4 183 -#define TEGRA30_CLK_PLL_A 184 -#define TEGRA30_CLK_PLL_A_OUT0 185 -#define TEGRA30_CLK_PLL_D 186 -#define TEGRA30_CLK_PLL_D_OUT0 187 -#define TEGRA30_CLK_PLL_D2 188 -#define TEGRA30_CLK_PLL_D2_OUT0 189 -#define TEGRA30_CLK_PLL_U 190 -#define TEGRA30_CLK_PLL_X 191 - -#define TEGRA30_CLK_PLL_X_OUT0 192 -#define TEGRA30_CLK_PLL_E 193 -#define TEGRA30_CLK_SPDIF_IN_SYNC 194 -#define TEGRA30_CLK_I2S0_SYNC 195 -#define TEGRA30_CLK_I2S1_SYNC 196 -#define TEGRA30_CLK_I2S2_SYNC 197 -#define TEGRA30_CLK_I2S3_SYNC 198 -#define TEGRA30_CLK_I2S4_SYNC 199 -#define TEGRA30_CLK_VIMCLK_SYNC 200 -#define TEGRA30_CLK_AUDIO0 201 -#define TEGRA30_CLK_AUDIO1 202 -#define TEGRA30_CLK_AUDIO2 203 -#define TEGRA30_CLK_AUDIO3 204 -#define TEGRA30_CLK_AUDIO4 205 -#define TEGRA30_CLK_SPDIF 206 -#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ -#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ -#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ -#define TEGRA30_CLK_SCLK 210 -#define TEGRA30_CLK_BLINK 211 -#define TEGRA30_CLK_CCLK_G 212 -#define TEGRA30_CLK_CCLK_LP 213 -#define TEGRA30_CLK_TWD 214 -#define TEGRA30_CLK_CML0 215 -#define TEGRA30_CLK_CML1 216 -#define TEGRA30_CLK_HCLK 217 -#define TEGRA30_CLK_PCLK 218 -/* 219 */ -/* 220 */ -/* 221 */ -/* 222 */ -/* 223 */ - -/* 288 */ -/* 289 */ -/* 290 */ -/* 291 */ -/* 292 */ -/* 293 */ -/* 294 */ -/* 295 */ -/* 296 */ -/* 297 */ -/* 298 */ -/* 299 */ -#define TEGRA30_CLK_CLK_OUT_1_MUX 300 -#define TEGRA30_CLK_CLK_OUT_2_MUX 301 -#define TEGRA30_CLK_CLK_OUT_3_MUX 302 -#define TEGRA30_CLK_AUDIO0_MUX 303 -#define TEGRA30_CLK_AUDIO1_MUX 304 -#define TEGRA30_CLK_AUDIO2_MUX 305 -#define TEGRA30_CLK_AUDIO3_MUX 306 -#define TEGRA30_CLK_AUDIO4_MUX 307 -#define TEGRA30_CLK_SPDIF_MUX 308 -#define TEGRA30_CLK_CLK_MAX 309 - -#endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ diff --git a/include/dt-bindings/pinctrl/am43xx.h b/include/dt-bindings/pinctrl/am43xx.h deleted file mode 100644 index 292c2ebf58d..00000000000 --- a/include/dt-bindings/pinctrl/am43xx.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This header provides constants specific to AM43XX pinctrl bindings. - */ - -#ifndef _DT_BINDINGS_PINCTRL_AM43XX_H -#define _DT_BINDINGS_PINCTRL_AM43XX_H - -#define MUX_MODE0 0 -#define MUX_MODE1 1 -#define MUX_MODE2 2 -#define MUX_MODE3 3 -#define MUX_MODE4 4 -#define MUX_MODE5 5 -#define MUX_MODE6 6 -#define MUX_MODE7 7 -#define MUX_MODE8 8 - -#define PULL_DISABLE (1 << 16) -#define PULL_UP (1 << 17) -#define INPUT_EN (1 << 18) -#define SLEWCTRL_SLOW (1 << 19) -#define SLEWCTRL_FAST 0 -#define DS0_PULL_UP_DOWN_EN (1 << 27) -#define WAKEUP_ENABLE (1 << 29) - -#define PIN_OUTPUT (PULL_DISABLE) -#define PIN_OUTPUT_PULLUP (PULL_UP) -#define PIN_OUTPUT_PULLDOWN 0 -#define PIN_INPUT (INPUT_EN | PULL_DISABLE) -#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) -#define PIN_INPUT_PULLDOWN (INPUT_EN) - -/* - * Macro to allow using the absolute physical address instead of the - * padconf registers instead of the offset from padconf base. - */ -#define AM4372_IOPAD(pa, val) (((pa) & 0xffff) - 0x0800) (val) - -#endif -- cgit v1.3.1 From ae7e0330ce22d580990cf40d648c809b5093b252 Mon Sep 17 00:00:00 2001 From: Valentin Caron Date: Tue, 27 May 2025 15:27:43 +0200 Subject: clk: scmi: add compatibility with clock protocol 2.0 Since clock protocol 2.0, SCMI specification add an option field "clock_enable_delay" to CLOCK_ATTRIBUTES command. scmi_read_resp_from_smt() will return an error ("Buffer too small") as the message length coming from the SCMI server is not the same as expected. So implement a condition to SCMI clock protocol version to change the length of the expected message. Signed-off-by: Valentin Caron Signed-off-by: Patrice Chotard Cc: Lukasz Majewski Cc: Sean Anderson Reviewed-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/clk/clk_scmi.c | 54 ++++++++++++++++++++++++++++++++++-------------- include/scmi_protocols.h | 15 ++++++++++++++ 2 files changed, 54 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c index af69850cdd8..e323a948780 100644 --- a/drivers/clk/clk_scmi.c +++ b/drivers/clk/clk_scmi.c @@ -84,26 +84,47 @@ static int scmi_clk_get_num_clock(struct udevice *dev, size_t *num_clocks) static int scmi_clk_get_attibute(struct udevice *dev, int clkid, char **name, u32 *attr) { + struct scmi_clock_priv *priv = dev_get_priv(dev); struct scmi_clk_attribute_in in = { .clock_id = clkid, }; - struct scmi_clk_attribute_out out; - struct scmi_msg msg = { - .protocol_id = SCMI_PROTOCOL_ID_CLOCK, - .message_id = SCMI_CLOCK_ATTRIBUTES, - .in_msg = (u8 *)&in, - .in_msg_sz = sizeof(in), - .out_msg = (u8 *)&out, - .out_msg_sz = sizeof(out), - }; int ret; - ret = devm_scmi_process_msg(dev, &msg); - if (ret) - return ret; - - *name = strdup(out.clock_name); - *attr = out.attributes; + if (priv->version >= 0x20000) { + struct scmi_clk_attribute_out_v2 out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_CLOCK, + .message_id = SCMI_CLOCK_ATTRIBUTES, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + + *name = strdup(out.clock_name); + *attr = out.attributes; + } else { + struct scmi_clk_attribute_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_CLOCK, + .message_id = SCMI_CLOCK_ATTRIBUTES, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + + *name = strdup(out.clock_name); + *attr = out.attributes; + } return 0; } @@ -257,6 +278,9 @@ static int scmi_clk_probe(struct udevice *dev) if (!CONFIG_IS_ENABLED(CLK_CCF)) return 0; + ret = scmi_generic_protocol_version(dev, SCMI_PROTOCOL_ID_CLOCK, + &priv->version); + /* register CCF children: CLK UCLASS, no probed again */ if (device_get_uclass_id(dev->parent) == UCLASS_CLK) return 0; diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index 9046de7e3e7..762a1032c37 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -782,6 +782,21 @@ struct scmi_clk_attribute_out { char clock_name[SCMI_CLOCK_NAME_LENGTH_MAX]; }; +/** + * struct scmi_clk_get_nb_out_v2 - Response payload for SCMI_CLOCK_ATTRIBUTES command + * Clock management Protocol 2.0 + * @status: SCMI command status + * @attributes: clock attributes + * @clock_name: name of the clock + * @clock_enable_delay: delay incurred by the platform to enable the clock + */ +struct scmi_clk_attribute_out_v2 { + s32 status; + u32 attributes; + char clock_name[SCMI_CLOCK_NAME_LENGTH_MAX]; + u32 clock_enable_delay; +}; + /** * struct scmi_clk_state_in - Message payload for CLOCK_CONFIG_SET command * @clock_id: SCMI clock ID -- cgit v1.3.1 From fc6c5e703f63d167f403781572d7437d48518d24 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Tue, 27 May 2025 15:27:44 +0200 Subject: clk: stm32mp25: Add clock driver support Add clock driver support for STM32MP25 SoCs. Signed-off-by: Gabriel Fernandez Signed-off-by: Valentin Caron Signed-off-by: Patrice Chotard Cc: Lukasz Majewski Cc: Sean Anderson Reviewed-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/clk/stm32/Kconfig | 9 + drivers/clk/stm32/Makefile | 1 + drivers/clk/stm32/clk-stm32mp25.c | 665 +++++++++++++++++++++++++++++++++++ include/stm32mp25_rcc.h | 712 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 1387 insertions(+) create mode 100644 drivers/clk/stm32/clk-stm32mp25.c create mode 100644 include/stm32mp25_rcc.h (limited to 'include') diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig index c05015efe8b..ea856be1662 100644 --- a/drivers/clk/stm32/Kconfig +++ b/drivers/clk/stm32/Kconfig @@ -36,3 +36,12 @@ config CLK_STM32MP13 help Enable the STM32 clock (RCC) driver. Enable support for manipulating STM32MP13's on-SoC clocks. + +config CLK_STM32MP25 + bool "Enable RCC clock driver for STM32MP25" + depends on ARCH_STM32MP && CLK + default y if STM32MP25X + select CLK_STM32_CORE + help + Enable the STM32 clock (RCC) driver. Enable support for + manipulating STM32MP25's on-SoC clocks. diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile index 20afbc3cfce..56adb8a4bbb 100644 --- a/drivers/clk/stm32/Makefile +++ b/drivers/clk/stm32/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_CLK_STM32F) += clk-stm32f.o obj-$(CONFIG_CLK_STM32H7) += clk-stm32h7.o obj-$(CONFIG_CLK_STM32MP1) += clk-stm32mp1.o obj-$(CONFIG_CLK_STM32MP13) += clk-stm32mp13.o +obj-$(CONFIG_CLK_STM32MP25) += clk-stm32mp25.o diff --git a/drivers/clk/stm32/clk-stm32mp25.c b/drivers/clk/stm32/clk-stm32mp25.c new file mode 100644 index 00000000000..043dd2273e1 --- /dev/null +++ b/drivers/clk/stm32/clk-stm32mp25.c @@ -0,0 +1,665 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include + +#include "clk-stm32-core.h" +#include "stm32mp25_rcc.h" + +/* Clock security definition */ +#define SECF_NONE -1 + +static const char * const adc12_src[] = { + "ck_flexgen_46", "ck_icn_ls_mcu" +}; + +static const char * const adc3_src[] = { + "ck_flexgen_47", "ck_icn_ls_mcu", "ck_flexgen_46" +}; + +static const char * const usb2phy1_src[] = { + "ck_flexgen_57", "hse_div2_ck" +}; + +static const char * const usb2phy2_src[] = { + "ck_flexgen_58", "hse_div2_ck" +}; + +static const char * const usb3pciphy_src[] = { + "ck_flexgen_34", "hse_div2_ck" +}; + +static const char * const dsiblane_src[] = { + "txbyteclk", "ck_ker_ltdc" +}; + +static const char * const dsiphy_src[] = { + "ck_flexgen_28", "hse_ck" +}; + +static const char * const lvdsphy_src[] = { + "ck_flexgen_32", "hse_ck" +}; + +static const char * const dts_src[] = { + "hsi_ck", "hse_ck", "msi_ck" +}; + +static const char * const mco1_src[] = { + "ck_flexgen_61", "ck_obs0" +}; + +static const char * const mco2_src[] = { + "ck_flexgen_62", "ck_obs1" +}; + +enum enum_mux_cfg { + MUX_MCO1, + MUX_MCO2, + MUX_ADC12, + MUX_ADC3, + MUX_USB2PHY1, + MUX_USB2PHY2, + MUX_USB3PCIEPHY, + MUX_DSIBLANE, + MUX_DSIPHY, + MUX_LVDSPHY, + MUX_DTS, + MUX_NB +}; + +#define MUX_CFG(id, src, _offset, _shift, _witdh)[id] = {\ + .num_parents = ARRAY_SIZE(src),\ + .parent_names = src,\ + .reg_off = (_offset),\ + .shift = (_shift),\ + .width = (_witdh),\ +} + +static const struct stm32_mux_cfg stm32mp25_muxes[MUX_NB] = { + MUX_CFG(MUX_ADC12, adc12_src, RCC_ADC12CFGR, 12, 1), + MUX_CFG(MUX_ADC3, adc3_src, RCC_ADC3CFGR, 12, 2), + MUX_CFG(MUX_DSIBLANE, dsiblane_src, RCC_DSICFGR, 12, 1), + MUX_CFG(MUX_DSIPHY, dsiphy_src, RCC_DSICFGR, 15, 1), + MUX_CFG(MUX_DTS, dts_src, RCC_DTSCFGR, 12, 2), + MUX_CFG(MUX_MCO1, mco1_src, RCC_MCO1CFGR, 0, 1), + MUX_CFG(MUX_MCO2, mco2_src, RCC_MCO2CFGR, 0, 1), + MUX_CFG(MUX_LVDSPHY, lvdsphy_src, RCC_LVDSCFGR, 15, 1), + MUX_CFG(MUX_USB2PHY1, usb2phy1_src, RCC_USB2PHY1CFGR, 15, 1), + MUX_CFG(MUX_USB2PHY2, usb2phy2_src, RCC_USB2PHY2CFGR, 15, 1), + MUX_CFG(MUX_USB3PCIEPHY, usb3pciphy_src, RCC_USB3PCIEPHYCFGR, 15, 1), +}; + +enum enum_gate_cfg { + GATE_ADC12, + GATE_ADC3, + GATE_ADF1, + GATE_CCI, + GATE_CRC, + GATE_CRYP1, + GATE_CRYP2, + GATE_CSI, + GATE_DBG, + GATE_DCMIPP, + GATE_DSI, + GATE_DTS, + GATE_ETH1, + GATE_ETH1MAC, + GATE_ETH1RX, + GATE_ETH1STP, + GATE_ETH1TX, + GATE_ETH2, + GATE_ETH2MAC, + GATE_ETH2RX, + GATE_ETH2STP, + GATE_ETH2TX, + GATE_ETHSW, + GATE_ETHSWMAC, + GATE_ETHSWREF, + GATE_ETR, + GATE_FDCAN, + GATE_GPU, + GATE_HASH, + GATE_HDP, + GATE_I2C1, + GATE_I2C2, + GATE_I2C3, + GATE_I2C4, + GATE_I2C5, + GATE_I2C6, + GATE_I2C7, + GATE_I2C8, + GATE_I3C1, + GATE_I3C2, + GATE_I3C3, + GATE_I3C4, + GATE_IS2M, + GATE_IWDG1, + GATE_IWDG2, + GATE_IWDG3, + GATE_IWDG4, + GATE_IWDG5, + GATE_LPTIM1, + GATE_LPTIM2, + GATE_LPTIM3, + GATE_LPTIM4, + GATE_LPTIM5, + GATE_LPUART1, + GATE_LTDC, + GATE_LVDS, + GATE_MCO1, + GATE_MCO2, + GATE_MDF1, + GATE_OSPI1, + GATE_OSPI2, + GATE_OSPIIOM, + GATE_PCIE, + GATE_PKA, + GATE_RNG, + GATE_SAES, + GATE_SAI1, + GATE_SAI2, + GATE_SAI3, + GATE_SAI4, + GATE_SDMMC1, + GATE_SDMMC2, + GATE_SDMMC3, + GATE_SERC, + GATE_SPDIFRX, + GATE_SPI1, + GATE_SPI2, + GATE_SPI3, + GATE_SPI4, + GATE_SPI5, + GATE_SPI6, + GATE_SPI7, + GATE_SPI8, + GATE_STGEN, + GATE_STM500, + GATE_TIM1, + GATE_TIM2, + GATE_TIM3, + GATE_TIM4, + GATE_TIM5, + GATE_TIM6, + GATE_TIM7, + GATE_TIM8, + GATE_TIM10, + GATE_TIM11, + GATE_TIM12, + GATE_TIM13, + GATE_TIM14, + GATE_TIM15, + GATE_TIM16, + GATE_TIM17, + GATE_TIM20, + GATE_TRACE, + GATE_UART4, + GATE_UART5, + GATE_UART7, + GATE_UART8, + GATE_UART9, + GATE_USART1, + GATE_USART2, + GATE_USART3, + GATE_USART6, + GATE_USBH, + GATE_USB2PHY1, + GATE_USB2PHY2, + GATE_USB3DR, + GATE_USB3PCIEPHY, + GATE_USBTC, + GATE_VDEC, + GATE_VENC, + GATE_VREF, + GATE_WWDG1, + GATE_WWDG2, + GATE_NB +}; + +#define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\ + .reg_off = (_offset),\ + .bit_idx = (_bit_idx),\ + .set_clr = (_offset_clr),\ +} + +static const struct stm32_gate_cfg stm32mp25_gates[GATE_NB] = { + GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 8, 0), + GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 8, 0), + GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0), + GATE_CFG(GATE_OSPI2, RCC_OSPI2CFGR, 1, 0), + GATE_CFG(GATE_DBG, RCC_DBGCFGR, 8, 0), + GATE_CFG(GATE_TRACE, RCC_DBGCFGR, 9, 0), + GATE_CFG(GATE_STM500, RCC_STM500CFGR, 1, 0), + GATE_CFG(GATE_ETR, RCC_ETRCFGR, 1, 0), + GATE_CFG(GATE_IS2M, RCC_IS2MCFGR, 1, 0), + GATE_CFG(GATE_TIM1, RCC_TIM1CFGR, 1, 0), + GATE_CFG(GATE_TIM2, RCC_TIM2CFGR, 1, 0), + GATE_CFG(GATE_TIM3, RCC_TIM3CFGR, 1, 0), + GATE_CFG(GATE_TIM4, RCC_TIM4CFGR, 1, 0), + GATE_CFG(GATE_TIM5, RCC_TIM5CFGR, 1, 0), + GATE_CFG(GATE_TIM6, RCC_TIM6CFGR, 1, 0), + GATE_CFG(GATE_TIM7, RCC_TIM7CFGR, 1, 0), + GATE_CFG(GATE_TIM8, RCC_TIM8CFGR, 1, 0), + GATE_CFG(GATE_TIM10, RCC_TIM10CFGR, 1, 0), + GATE_CFG(GATE_TIM11, RCC_TIM11CFGR, 1, 0), + GATE_CFG(GATE_TIM12, RCC_TIM12CFGR, 1, 0), + GATE_CFG(GATE_TIM13, RCC_TIM13CFGR, 1, 0), + GATE_CFG(GATE_TIM14, RCC_TIM14CFGR, 1, 0), + GATE_CFG(GATE_TIM15, RCC_TIM15CFGR, 1, 0), + GATE_CFG(GATE_TIM16, RCC_TIM16CFGR, 1, 0), + GATE_CFG(GATE_TIM17, RCC_TIM17CFGR, 1, 0), + GATE_CFG(GATE_TIM20, RCC_TIM20CFGR, 1, 0), + GATE_CFG(GATE_LPTIM1, RCC_LPTIM1CFGR, 1, 0), + GATE_CFG(GATE_LPTIM2, RCC_LPTIM2CFGR, 1, 0), + GATE_CFG(GATE_LPTIM3, RCC_LPTIM3CFGR, 1, 0), + GATE_CFG(GATE_LPTIM4, RCC_LPTIM4CFGR, 1, 0), + GATE_CFG(GATE_LPTIM5, RCC_LPTIM5CFGR, 1, 0), + GATE_CFG(GATE_SPI1, RCC_SPI1CFGR, 1, 0), + GATE_CFG(GATE_SPI2, RCC_SPI2CFGR, 1, 0), + GATE_CFG(GATE_SPI3, RCC_SPI3CFGR, 1, 0), + GATE_CFG(GATE_SPI4, RCC_SPI4CFGR, 1, 0), + GATE_CFG(GATE_SPI5, RCC_SPI5CFGR, 1, 0), + GATE_CFG(GATE_SPI6, RCC_SPI6CFGR, 1, 0), + GATE_CFG(GATE_SPI7, RCC_SPI7CFGR, 1, 0), + GATE_CFG(GATE_SPI8, RCC_SPI8CFGR, 1, 0), + GATE_CFG(GATE_SPDIFRX, RCC_SPDIFRXCFGR, 1, 0), + GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0), + GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0), + GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0), + GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0), + GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0), + GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0), + GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0), + GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0), + GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0), + GATE_CFG(GATE_LPUART1, RCC_LPUART1CFGR, 1, 0), + GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0), + GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0), + GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0), + GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0), + GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0), + GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0), + GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0), + GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0), + GATE_CFG(GATE_SAI1, RCC_SAI1CFGR, 1, 0), + GATE_CFG(GATE_SAI2, RCC_SAI2CFGR, 1, 0), + GATE_CFG(GATE_SAI3, RCC_SAI3CFGR, 1, 0), + GATE_CFG(GATE_SAI4, RCC_SAI4CFGR, 1, 0), + GATE_CFG(GATE_MDF1, RCC_MDF1CFGR, 1, 0), + GATE_CFG(GATE_ADF1, RCC_ADF1CFGR, 1, 0), + GATE_CFG(GATE_FDCAN, RCC_FDCANCFGR, 1, 0), + GATE_CFG(GATE_HDP, RCC_HDPCFGR, 1, 0), + GATE_CFG(GATE_ADC12, RCC_ADC12CFGR, 1, 0), + GATE_CFG(GATE_ADC3, RCC_ADC3CFGR, 1, 0), + GATE_CFG(GATE_ETH1MAC, RCC_ETH1CFGR, 1, 0), + GATE_CFG(GATE_ETH1STP, RCC_ETH1CFGR, 4, 0), + GATE_CFG(GATE_ETH1, RCC_ETH1CFGR, 5, 0), + GATE_CFG(GATE_ETH1TX, RCC_ETH1CFGR, 8, 0), + GATE_CFG(GATE_ETH1RX, RCC_ETH1CFGR, 10, 0), + GATE_CFG(GATE_ETH2MAC, RCC_ETH2CFGR, 1, 0), + GATE_CFG(GATE_ETH2STP, RCC_ETH2CFGR, 4, 0), + GATE_CFG(GATE_ETH2, RCC_ETH2CFGR, 5, 0), + GATE_CFG(GATE_ETH2TX, RCC_ETH2CFGR, 8, 0), + GATE_CFG(GATE_ETH2RX, RCC_ETH2CFGR, 10, 0), + GATE_CFG(GATE_USBH, RCC_USBHCFGR, 1, 0), + GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0), + GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0), + GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0), + GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0), + GATE_CFG(GATE_PCIE, RCC_PCIECFGR, 1, 0), + GATE_CFG(GATE_USBTC, RCC_UCPDCFGR, 1, 0), + GATE_CFG(GATE_ETHSWMAC, RCC_ETHSWCFGR, 1, 0), + GATE_CFG(GATE_ETHSW, RCC_ETHSWCFGR, 5, 0), + GATE_CFG(GATE_ETHSWREF, RCC_ETHSWCFGR, 21, 0), + GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0), + GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0), + GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0), + GATE_CFG(GATE_SDMMC3, RCC_SDMMC3CFGR, 1, 0), + GATE_CFG(GATE_GPU, RCC_GPUCFGR, 1, 0), + GATE_CFG(GATE_LTDC, RCC_LTDCCFGR, 1, 0), + GATE_CFG(GATE_DSI, RCC_DSICFGR, 1, 0), + GATE_CFG(GATE_LVDS, RCC_LVDSCFGR, 1, 0), + GATE_CFG(GATE_CSI, RCC_CSICFGR, 1, 0), + GATE_CFG(GATE_DCMIPP, RCC_DCMIPPCFGR, 1, 0), + GATE_CFG(GATE_CCI, RCC_CCICFGR, 1, 0), + GATE_CFG(GATE_VDEC, RCC_VDECCFGR, 1, 0), + GATE_CFG(GATE_VENC, RCC_VENCCFGR, 1, 0), + GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0), + GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0), + GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0), + GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0), + GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0), + GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0), + GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0), + GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0), + GATE_CFG(GATE_IWDG3, RCC_IWDG3CFGR, 1, 0), + GATE_CFG(GATE_IWDG4, RCC_IWDG4CFGR, 1, 0), + GATE_CFG(GATE_IWDG5, RCC_IWDG5CFGR, 1, 0), + GATE_CFG(GATE_WWDG1, RCC_WWDG1CFGR, 1, 0), + GATE_CFG(GATE_WWDG2, RCC_WWDG2CFGR, 1, 0), + GATE_CFG(GATE_VREF, RCC_VREFCFGR, 1, 0), + GATE_CFG(GATE_DTS, RCC_DTSCFGR, 1, 0), + GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0), + GATE_CFG(GATE_SERC, RCC_SERCCFGR, 1, 0), + GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0), + GATE_CFG(GATE_I3C1, RCC_I3C1CFGR, 1, 0), + GATE_CFG(GATE_I3C2, RCC_I3C2CFGR, 1, 0), + GATE_CFG(GATE_I3C3, RCC_I3C3CFGR, 1, 0), + GATE_CFG(GATE_I3C4, RCC_I3C4CFGR, 1, 0), +}; + +#define STM32_COMPOSITE_NODIV(_id, _name, _flags, _sec_id, _gate_id, _mux_id)\ + STM32_COMPOSITE(_id, _name, _flags, _sec_id, _gate_id, _mux_id, NO_STM32_DIV) + +static const struct clock_config stm32mp25_clock_cfg[] = { + /* ADC */ + STM32_GATE(CK_BUS_ADC12, "ck_icn_p_adc12", "ck_icn_ls_mcu", 0, GATE_ADC12, SECF_NONE), + STM32_COMPOSITE_NODIV(CK_KER_ADC12, "ck_ker_adc12", 0, SECF_NONE, GATE_ADC12, MUX_ADC12), + STM32_GATE(CK_BUS_ADC3, "ck_icn_p_adc3", "ck_icn_ls_mcu", 0, GATE_ADC3, SECF_NONE), + STM32_COMPOSITE_NODIV(CK_KER_ADC3, "ck_ker_adc3", 0, SECF_NONE, GATE_ADC3, MUX_ADC3), + + /* ADF */ + STM32_GATE(CK_BUS_ADF1, "ck_icn_p_adf1", "ck_icn_ls_mcu", 0, GATE_ADF1, SECF_NONE), + STM32_GATE(CK_KER_ADF1, "ck_ker_adf1", "ck_flexgen_42", 0, GATE_ADF1, SECF_NONE), + + /* Camera */ + /* DCMI */ + STM32_GATE(CK_BUS_CCI, "ck_icn_p_cci", "ck_icn_ls_mcu", 0, GATE_CCI, SECF_NONE), + + /* CSI-HOST */ + STM32_GATE(CK_BUS_CSI, "ck_icn_p_csi", "ck_icn_apb4", 0, GATE_CSI, SECF_NONE), + STM32_GATE(CK_KER_CSI, "ck_ker_csi", "ck_flexgen_29", 0, GATE_CSI, SECF_NONE), + STM32_GATE(CK_KER_CSITXESC, "ck_ker_csitxesc", "ck_flexgen_30", 0, GATE_CSI, SECF_NONE), + + /* CSI-PHY */ + STM32_GATE(CK_KER_CSIPHY, "ck_ker_csiphy", "ck_flexgen_31", 0, GATE_CSI, SECF_NONE), + + /* DCMIPP */ + STM32_GATE(CK_BUS_DCMIPP, "ck_icn_p_dcmipp", "ck_icn_apb4", 0, GATE_DCMIPP, SECF_NONE), + + /* CRC */ + STM32_GATE(CK_BUS_CRC, "ck_icn_p_crc", "ck_icn_ls_mcu", 0, GATE_CRC, SECF_NONE), + + /* CRYP */ + STM32_GATE(CK_BUS_CRYP1, "ck_icn_p_cryp1", "ck_icn_ls_mcu", 0, GATE_CRYP1, SECF_NONE), + STM32_GATE(CK_BUS_CRYP2, "ck_icn_p_cryp2", "ck_icn_ls_mcu", 0, GATE_CRYP2, SECF_NONE), + + /* DBG & TRACE*/ + STM32_GATE(CK_KER_TSDBG, "ck_ker_tsdbg", "ck_flexgen_43", 0, GATE_DBG, SECF_NONE), + STM32_GATE(CK_KER_TPIU, "ck_ker_tpiu", "ck_flexgen_44", 0, GATE_TRACE, SECF_NONE), + STM32_GATE(CK_BUS_SYSATB, "ck_sys_atb", "ck_flexgen_45", 0, GATE_DBG, SECF_NONE), + STM32_GATE(CK_BUS_ETR, "ck_icn_m_etr", "ck_flexgen_45", 0, GATE_ETR, SECF_NONE), + + /* Display subsystem */ + /* LTDC */ + STM32_GATE(CK_BUS_LTDC, "ck_icn_p_ltdc", "ck_icn_apb4", 0, GATE_LTDC, SECF_NONE), + STM32_GATE(CK_KER_LTDC, "ck_ker_ltdc", "ck_flexgen_27", CLK_SET_RATE_PARENT, + GATE_LTDC, SECF_NONE), + + /* DSI */ + STM32_GATE(CK_BUS_DSI, "ck_icn_p_dsi", "ck_icn_apb4", 0, GATE_DSI, SECF_NONE), + STM32_COMPOSITE_NODIV(CK_KER_DSIBLANE, "clk_lanebyte", 0, SECF_NONE, + GATE_DSI, MUX_DSIBLANE), + + /* LVDS */ + STM32_GATE(CK_BUS_LVDS, "ck_icn_p_lvds", "ck_icn_apb4", 0, GATE_LVDS, SECF_NONE), + + /* DSI PHY */ + STM32_COMPOSITE_NODIV(CK_KER_DSIPHY, "ck_ker_dsiphy", 0, SECF_NONE, GATE_DSI, MUX_DSIPHY), + + /* LVDS PHY */ + STM32_COMPOSITE_NODIV(CK_KER_LVDSPHY, "ck_ker_lvdsphy", 0, + SECF_NONE, GATE_LVDS, MUX_LVDSPHY), + + /* DTS */ + STM32_COMPOSITE_NODIV(CK_KER_DTS, "ck_ker_dts", 0, SECF_NONE, GATE_DTS, MUX_DTS), + + /* ETHERNET */ + STM32_GATE(CK_BUS_ETH1, "ck_icn_p_eth1", "ck_icn_ls_mcu", 0, GATE_ETH1, SECF_NONE), + STM32_GATE(CK_ETH1_STP, "ck_ker_eth1stp", "ck_icn_ls_mcu", 0, GATE_ETH1STP, SECF_NONE), + STM32_GATE(CK_KER_ETH1, "ck_ker_eth1", "ck_flexgen_54", 0, GATE_ETH1, SECF_NONE), + STM32_GATE(CK_KER_ETH1, "ck_ker_eth1ptp", "ck_flexgen_56", 0, GATE_ETH1, SECF_NONE), + STM32_GATE(CK_ETH1_MAC, "ck_ker_eth1mac", "ck_icn_ls_mcu", 0, GATE_ETH1MAC, SECF_NONE), + STM32_GATE(CK_ETH1_TX, "ck_ker_eth1tx", "ck_icn_ls_mcu", 0, GATE_ETH1TX, SECF_NONE), + STM32_GATE(CK_ETH1_RX, "ck_ker_eth1rx", "ck_icn_ls_mcu", 0, GATE_ETH1RX, SECF_NONE), + + STM32_GATE(CK_BUS_ETH2, "ck_icn_p_eth2", "ck_icn_ls_mcu", 0, GATE_ETH2, SECF_NONE), + STM32_GATE(CK_ETH2_STP, "ck_ker_eth2stp", "ck_icn_ls_mcu", 0, GATE_ETH2STP, SECF_NONE), + STM32_GATE(CK_KER_ETH2, "ck_ker_eth2", "ck_flexgen_54", 0, GATE_ETH2, SECF_NONE), + STM32_GATE(CK_KER_ETH2, "ck_ker_eth2ptp", "ck_flexgen_56", 0, GATE_ETH2, SECF_NONE), + STM32_GATE(CK_ETH2_MAC, "ck_ker_eth2mac", "ck_icn_ls_mcu", 0, GATE_ETH2MAC, SECF_NONE), + STM32_GATE(CK_ETH2_TX, "ck_ker_eth2tx", "ck_icn_ls_mcu", 0, GATE_ETH2TX, SECF_NONE), + STM32_GATE(CK_ETH2_RX, "ck_ker_eth2rx", "ck_icn_ls_mcu", 0, GATE_ETH2RX, SECF_NONE), + + STM32_GATE(CK_BUS_ETHSW, "ck_icn_p_ethsw", "ck_icn_ls_mcu", 0, GATE_ETHSWMAC, SECF_NONE), + STM32_GATE(CK_KER_ETHSW, "ck_ker_ethsw", "ck_flexgen_54", 0, GATE_ETHSW, SECF_NONE), + STM32_GATE(CK_KER_ETHSWREF, "ck_ker_ethswref", "ck_flexgen_60", 0, + GATE_ETHSWREF, SECF_NONE), + + /* FDCAN */ + STM32_GATE(CK_BUS_FDCAN, "ck_icn_p_fdcan", "ck_icn_apb2", 0, GATE_FDCAN, SECF_NONE), + STM32_GATE(CK_KER_FDCAN, "ck_ker_fdcan", "ck_flexgen_26", 0, GATE_FDCAN, SECF_NONE), + + /* GPU */ + STM32_GATE(CK_BUS_GPU, "ck_icn_m_gpu", "ck_flexgen_59", 0, GATE_GPU, SECF_NONE), + + /* HASH */ + STM32_GATE(CK_BUS_HASH, "ck_icn_p_hash", "ck_icn_ls_mcu", 0, GATE_HASH, SECF_NONE), + + /* HDP */ + STM32_GATE(CK_BUS_HDP, "ck_icn_p_hdp", "ck_icn_apb3", 0, GATE_HDP, SECF_NONE), + + /* I2C */ + STM32_GATE(CK_KER_I2C1, "ck_ker_i2c1", "ck_flexgen_12", 0, GATE_I2C1, SECF_NONE), + STM32_GATE(CK_KER_I2C2, "ck_ker_i2c2", "ck_flexgen_12", 0, GATE_I2C2, SECF_NONE), + STM32_GATE(CK_KER_I2C3, "ck_ker_i2c3", "ck_flexgen_13", 0, GATE_I2C3, SECF_NONE), + STM32_GATE(CK_KER_I2C5, "ck_ker_i2c5", "ck_flexgen_13", 0, GATE_I2C5, SECF_NONE), + STM32_GATE(CK_KER_I2C4, "ck_ker_i2c4", "ck_flexgen_14", 0, GATE_I2C4, SECF_NONE), + STM32_GATE(CK_KER_I2C6, "ck_ker_i2c6", "ck_flexgen_14", 0, GATE_I2C6, SECF_NONE), + STM32_GATE(CK_KER_I2C7, "ck_ker_i2c7", "ck_flexgen_15", 0, GATE_I2C7, SECF_NONE), + STM32_GATE(CK_KER_I2C8, "ck_ker_i2c8", "ck_flexgen_38", 0, GATE_I2C8, SECF_NONE), + + /* I3C */ + STM32_GATE(CK_KER_I3C1, "ck_ker_i3c1", "ck_flexgen_12", 0, GATE_I3C1, SECF_NONE), + STM32_GATE(CK_KER_I3C2, "ck_ker_i3c2", "ck_flexgen_12", 0, GATE_I3C2, SECF_NONE), + STM32_GATE(CK_KER_I3C3, "ck_ker_i3c3", "ck_flexgen_13", 0, GATE_I3C3, SECF_NONE), + STM32_GATE(CK_KER_I3C4, "ck_ker_i3c4", "ck_flexgen_36", 0, GATE_I3C4, SECF_NONE), + + /* I2S */ + STM32_GATE(CK_BUS_IS2M, "ck_icn_p_is2m", "ck_icn_apb3", 0, GATE_IS2M, SECF_NONE), + + /* IWDG */ + STM32_GATE(CK_BUS_IWDG1, "ck_icn_p_iwdg1", "ck_icn_apb3", 0, GATE_IWDG1, SECF_NONE), + STM32_GATE(CK_BUS_IWDG2, "ck_icn_p_iwdg2", "ck_icn_apb3", 0, GATE_IWDG2, SECF_NONE), + STM32_GATE(CK_BUS_IWDG3, "ck_icn_p_iwdg3", "ck_icn_apb3", 0, GATE_IWDG3, SECF_NONE), + STM32_GATE(CK_BUS_IWDG4, "ck_icn_p_iwdg4", "ck_icn_apb3", 0, GATE_IWDG4, SECF_NONE), + STM32_GATE(CK_BUS_IWDG5, "ck_icn_p_iwdg5", "ck_icn_ls_mcu", 0, GATE_IWDG5, SECF_NONE), + + /* LPTIM */ + STM32_GATE(CK_KER_LPTIM1, "ck_ker_lptim1", "ck_flexgen_07", 0, GATE_LPTIM1, SECF_NONE), + STM32_GATE(CK_KER_LPTIM2, "ck_ker_lptim2", "ck_flexgen_07", 0, GATE_LPTIM2, SECF_NONE), + STM32_GATE(CK_KER_LPTIM3, "ck_ker_lptim3", "ck_flexgen_40", 0, GATE_LPTIM3, SECF_NONE), + STM32_GATE(CK_KER_LPTIM4, "ck_ker_lptim4", "ck_flexgen_41", 0, GATE_LPTIM4, SECF_NONE), + STM32_GATE(CK_KER_LPTIM5, "ck_ker_lptim5", "ck_flexgen_41", 0, GATE_LPTIM5, SECF_NONE), + + /* LPUART */ + STM32_GATE(CK_KER_LPUART1, "ck_ker_lpuart1", "ck_flexgen_39", 0, GATE_LPUART1, SECF_NONE), + + /* MCO1 & MCO2 */ + STM32_COMPOSITE_NODIV(CK_MCO1, "ck_mco1", 0, SECF_NONE, GATE_MCO1, MUX_MCO1), + STM32_COMPOSITE_NODIV(CK_MCO2, "ck_mco2", 0, SECF_NONE, GATE_MCO2, MUX_MCO2), + + /* MDF */ + STM32_GATE(CK_KER_MDF1, "ck_ker_mdf1", "ck_flexgen_23", 0, GATE_MDF1, SECF_NONE), + + /* OCTOSPI */ + STM32_GATE(CK_BUS_OSPI1, "ck_icn_s_ospi1,", "ck_icn_hs_mcu", 0, GATE_OSPI1, SECF_NONE), + STM32_GATE(CK_BUS_OTFD1, "ck_icn_p_otfd1,", "ck_icn_hs_mcu", 0, GATE_OSPI1, SECF_NONE), + STM32_GATE(CK_KER_OSPI1, "ck_ker_ospi1", "ck_flexgen_48", 0, GATE_OSPI1, SECF_NONE), + STM32_GATE(CK_BUS_OSPI2, "ck_icn_s_ospi2,", "ck_icn_hs_mcu", 0, GATE_OSPI2, SECF_NONE), + STM32_GATE(CK_BUS_OTFD2, "ck_icn_p_otfd2,", "ck_icn_hs_mcu", 0, GATE_OSPI2, SECF_NONE), + STM32_GATE(CK_KER_OSPI2, "ck_ker_ospi2", "ck_flexgen_49", 0, GATE_OSPI2, SECF_NONE), + STM32_GATE(CK_BUS_OSPIIOM, "ck_icn_p_ospiiom", "ck_icn_ls_mcu", 0, GATE_OSPIIOM, SECF_NONE), + + /* PCIE */ + STM32_GATE(CK_BUS_PCIE, "ck_icn_p_pcie", "ck_icn_ls_mcu", 0, GATE_PCIE, SECF_NONE), + + /* PKA */ + STM32_GATE(CK_BUS_PKA, "ck_icn_p_pka", "ck_icn_ls_mcu", 0, GATE_PKA, SECF_NONE), + + /* RNG */ + STM32_GATE(CK_BUS_RNG, "ck_icn_p_rng", "ck_icn_ls_mcu", CLK_IGNORE_UNUSED, + GATE_RNG, SECF_NONE), + + /* SAES */ + STM32_GATE(CK_BUS_SAES, "ck_icn_p_saes", "ck_icn_ls_mcu", 0, GATE_SAES, SECF_NONE), + + /* SAI [1..4] */ + STM32_GATE(CK_BUS_SAI1, "ck_icn_p_sai1", "ck_icn_apb2", 0, GATE_SAI1, SECF_NONE), + STM32_GATE(CK_BUS_SAI2, "ck_icn_p_sai2", "ck_icn_apb2", 0, GATE_SAI2, SECF_NONE), + STM32_GATE(CK_BUS_SAI3, "ck_icn_p_sai3", "ck_icn_apb2", 0, GATE_SAI3, SECF_NONE), + STM32_GATE(CK_BUS_SAI4, "ck_icn_p_sai4", "ck_icn_apb2", 0, GATE_SAI4, SECF_NONE), + STM32_GATE(CK_KER_SAI1, "ck_ker_sai1", "ck_flexgen_23", 0, GATE_SAI1, SECF_NONE), + STM32_GATE(CK_KER_SAI2, "ck_ker_sai2", "ck_flexgen_24", 0, GATE_SAI2, SECF_NONE), + STM32_GATE(CK_KER_SAI3, "ck_ker_sai3", "ck_flexgen_25", 0, GATE_SAI3, SECF_NONE), + STM32_GATE(CK_KER_SAI4, "ck_ker_sai4", "ck_flexgen_25", 0, GATE_SAI4, SECF_NONE), + + /* SDMMC */ + STM32_GATE(CK_KER_SDMMC1, "ck_ker_sdmmc1", "ck_flexgen_51", 0, GATE_SDMMC1, SECF_NONE), + STM32_GATE(CK_KER_SDMMC2, "ck_ker_sdmmc2", "ck_flexgen_52", 0, GATE_SDMMC2, SECF_NONE), + STM32_GATE(CK_KER_SDMMC3, "ck_ker_sdmmc3", "ck_flexgen_53", 0, GATE_SDMMC3, SECF_NONE), + + /* SERC */ + STM32_GATE(CK_BUS_SERC, "ck_icn_p_serc", "ck_icn_apb3", 0, GATE_SERC, SECF_NONE), + + /* SPDIF */ + STM32_GATE(CK_KER_SPDIFRX, "ck_ker_spdifrx", "ck_flexgen_11", 0, GATE_SPDIFRX, SECF_NONE), + + /* SPI */ + STM32_GATE(CK_KER_SPI1, "ck_ker_spi1", "ck_flexgen_16", 0, GATE_SPI1, SECF_NONE), + STM32_GATE(CK_KER_SPI2, "ck_ker_spi2", "ck_flexgen_10", 0, GATE_SPI2, SECF_NONE), + STM32_GATE(CK_KER_SPI3, "ck_ker_spi3", "ck_flexgen_10", 0, GATE_SPI3, SECF_NONE), + STM32_GATE(CK_KER_SPI4, "ck_ker_spi4", "ck_flexgen_17", 0, GATE_SPI4, SECF_NONE), + STM32_GATE(CK_KER_SPI5, "ck_ker_spi5", "ck_flexgen_17", 0, GATE_SPI5, SECF_NONE), + STM32_GATE(CK_KER_SPI6, "ck_ker_spi6", "ck_flexgen_18", 0, GATE_SPI6, SECF_NONE), + STM32_GATE(CK_KER_SPI7, "ck_ker_spi7", "ck_flexgen_18", 0, GATE_SPI7, SECF_NONE), + STM32_GATE(CK_KER_SPI8, "ck_ker_spi8", "ck_flexgen_37", 0, GATE_SPI8, SECF_NONE), + + /* STGEN */ + STM32_GATE(CK_KER_STGEN, "ck_ker_stgen", "ck_flexgen_33", CLK_IGNORE_UNUSED, + GATE_STGEN, SECF_NONE), + + /* STM500 */ + STM32_GATE(CK_BUS_STM500, "ck_icn_s_stm500", "ck_icn_ls_mcu", 0, GATE_STM500, SECF_NONE), + + /* Timers */ + STM32_GATE(CK_KER_TIM2, "ck_ker_tim2", "timg1_ck", 0, GATE_TIM2, SECF_NONE), + STM32_GATE(CK_KER_TIM3, "ck_ker_tim3", "timg1_ck", 0, GATE_TIM3, SECF_NONE), + STM32_GATE(CK_KER_TIM4, "ck_ker_tim4", "timg1_ck", 0, GATE_TIM4, SECF_NONE), + STM32_GATE(CK_KER_TIM5, "ck_ker_tim5", "timg1_ck", 0, GATE_TIM5, SECF_NONE), + STM32_GATE(CK_KER_TIM6, "ck_ker_tim6", "timg1_ck", 0, GATE_TIM6, SECF_NONE), + STM32_GATE(CK_KER_TIM7, "ck_ker_tim7", "timg1_ck", 0, GATE_TIM7, SECF_NONE), + STM32_GATE(CK_KER_TIM10, "ck_ker_tim10", "timg1_ck", 0, GATE_TIM10, SECF_NONE), + STM32_GATE(CK_KER_TIM11, "ck_ker_tim11", "timg1_ck", 0, GATE_TIM11, SECF_NONE), + STM32_GATE(CK_KER_TIM12, "ck_ker_tim12", "timg1_ck", 0, GATE_TIM12, SECF_NONE), + STM32_GATE(CK_KER_TIM13, "ck_ker_tim13", "timg1_ck", 0, GATE_TIM13, SECF_NONE), + STM32_GATE(CK_KER_TIM14, "ck_ker_tim14", "timg1_ck", 0, GATE_TIM14, SECF_NONE), + + STM32_GATE(CK_KER_TIM1, "ck_ker_tim1", "timg2_ck", 0, GATE_TIM1, SECF_NONE), + STM32_GATE(CK_KER_TIM8, "ck_ker_tim8", "timg2_ck", 0, GATE_TIM8, SECF_NONE), + STM32_GATE(CK_KER_TIM15, "ck_ker_tim15", "timg2_ck", 0, GATE_TIM15, SECF_NONE), + STM32_GATE(CK_KER_TIM16, "ck_ker_tim16", "timg2_ck", 0, GATE_TIM16, SECF_NONE), + STM32_GATE(CK_KER_TIM17, "ck_ker_tim17", "timg2_ck", 0, GATE_TIM17, SECF_NONE), + STM32_GATE(CK_KER_TIM20, "ck_ker_tim20", "timg2_ck", 0, GATE_TIM20, SECF_NONE), + + /* UART/USART */ + STM32_GATE(CK_KER_USART2, "ck_ker_usart2", "ck_flexgen_08", 0, GATE_USART2, SECF_NONE), + STM32_GATE(CK_KER_UART4, "ck_ker_uart4", "ck_flexgen_08", 0, GATE_UART4, SECF_NONE), + STM32_GATE(CK_KER_USART3, "ck_ker_usart3", "ck_flexgen_09", 0, GATE_USART3, SECF_NONE), + STM32_GATE(CK_KER_UART5, "ck_ker_uart5", "ck_flexgen_09", 0, GATE_UART5, SECF_NONE), + STM32_GATE(CK_KER_USART1, "ck_ker_usart1", "ck_flexgen_19", 0, GATE_USART1, SECF_NONE), + STM32_GATE(CK_KER_USART6, "ck_ker_usart6", "ck_flexgen_20", 0, GATE_USART6, SECF_NONE), + STM32_GATE(CK_KER_UART7, "ck_ker_uart7", "ck_flexgen_21", 0, GATE_UART7, SECF_NONE), + STM32_GATE(CK_KER_UART8, "ck_ker_uart8", "ck_flexgen_21", 0, GATE_UART8, SECF_NONE), + STM32_GATE(CK_KER_UART9, "ck_ker_uart9", "ck_flexgen_22", 0, GATE_UART9, SECF_NONE), + + /* USB2PHY1 */ + STM32_COMPOSITE_NODIV(CK_KER_USB2PHY1, "ck_ker_usb2phy1", 0, + SECF_NONE, GATE_USB2PHY1, MUX_USB2PHY1), + + /* USBH */ + STM32_GATE(CK_BUS_USB2OHCI, "ck_icn_m_usb2ohci", "ck_icn_hsl", 0, GATE_USBH, SECF_NONE), + STM32_GATE(CK_BUS_USB2EHCI, "ck_icn_m_usb2ehci", "ck_icn_hsl", 0, GATE_USBH, SECF_NONE), + + /* USB2PHY2 */ + STM32_COMPOSITE_NODIV(CK_KER_USB2PHY2EN, "ck_ker_usb2phy2_en", 0, + SECF_NONE, GATE_USB2PHY2, MUX_USB2PHY2), + + /* USB3 PCIe COMBOPHY */ + STM32_GATE(CK_BUS_USB3PCIEPHY, "ck_icn_p_usb3pciephy", "ck_icn_apb4", 0, + GATE_USB3PCIEPHY, SECF_NONE), + + STM32_COMPOSITE_NODIV(CK_KER_USB3PCIEPHY, "ck_ker_usb3pciephy", 0, + SECF_NONE, GATE_USB3PCIEPHY, MUX_USB3PCIEPHY), + + /* USB3 DRD */ + STM32_GATE(CK_BUS_USB3DR, "ck_icn_m_usb3dr", "ck_icn_hsl", 0, GATE_USB3DR, SECF_NONE), + STM32_GATE(CK_KER_USB2PHY2, "ck_ker_usb2phy2", "ck_flexgen_58", 0, + GATE_USB3DR, SECF_NONE), + + /* UCPD */ + STM32_GATE(CK_BUS_USBTC, "ck_icn_p_usbtc", "ck_flexgen_35", 0, GATE_USBTC, SECF_NONE), + STM32_GATE(CK_KER_USBTC, "ck_ker_usbtc", "ck_flexgen_35", 0, GATE_USBTC, SECF_NONE), + + /* VDEC / VENC */ + STM32_GATE(CK_BUS_VDEC, "ck_icn_p_vdec", "ck_icn_apb4", 0, GATE_VDEC, SECF_NONE), + STM32_GATE(CK_BUS_VENC, "ck_icn_p_venc", "ck_icn_apb4", 0, GATE_VENC, SECF_NONE), + + /* VREF */ + STM32_GATE(CK_BUS_VREF, "ck_icn_p_vref", "ck_icn_apb3", 0, RCC_VREFCFGR, SECF_NONE), + + /* WWDG */ + STM32_GATE(CK_BUS_WWDG1, "ck_icn_p_wwdg1", "ck_icn_apb3", 0, GATE_WWDG1, SECF_NONE), + STM32_GATE(CK_BUS_WWDG2, "ck_icn_p_wwdg2", "ck_icn_ls_mcu", 0, GATE_WWDG2, SECF_NONE), +}; + +static const struct stm32_clock_match_data stm32mp25_data = { + .tab_clocks = stm32mp25_clock_cfg, + .num_clocks = ARRAY_SIZE(stm32mp25_clock_cfg), + .clock_data = &(const struct clk_stm32_clock_data) { + .num_gates = ARRAY_SIZE(stm32mp25_gates), + .gates = stm32mp25_gates, + .muxes = stm32mp25_muxes, + }, +}; + +static int stm32mp25_clk_probe(struct udevice *dev) +{ + fdt_addr_t base = dev_read_addr(dev->parent); + struct udevice *scmi; + + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + /* force SCMI probe to register all SCMI clocks */ + uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(scmi_clock), &scmi); + + stm32_rcc_init(dev, &stm32mp25_data); + + return 0; +} + +U_BOOT_DRIVER(stm32mp25_clock) = { + .name = "stm32mp25_clk", + .id = UCLASS_CLK, + .ops = &stm32_clk_ops, + .priv_auto = sizeof(struct stm32mp_rcc_priv), + .probe = stm32mp25_clk_probe, +}; diff --git a/include/stm32mp25_rcc.h b/include/stm32mp25_rcc.h new file mode 100644 index 00000000000..595e115c0c4 --- /dev/null +++ b/include/stm32mp25_rcc.h @@ -0,0 +1,712 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C STMicroelectronics 2019 - All Rights Reserved + * Author: Gabriel Fernandez for STMicroelectronics. + */ + +#ifndef STM32MP25_RCC_H +#define STM32MP25_RCC_H + +#define RCC_SECCFGR0 0x0 +#define RCC_SECCFGR1 0x4 +#define RCC_SECCFGR2 0x8 +#define RCC_SECCFGR3 0xC +#define RCC_PRIVCFGR0 0x10 +#define RCC_PRIVCFGR1 0x14 +#define RCC_PRIVCFGR2 0x18 +#define RCC_PRIVCFGR3 0x1C +#define RCC_RCFGLOCKR0 0x20 +#define RCC_RCFGLOCKR1 0x24 +#define RCC_RCFGLOCKR2 0x28 +#define RCC_RCFGLOCKR3 0x2C +#define RCC_R0CIDCFGR 0x30 +#define RCC_R0SEMCR 0x34 +#define RCC_R1CIDCFGR 0x38 +#define RCC_R1SEMCR 0x3C +#define RCC_R2CIDCFGR 0x40 +#define RCC_R2SEMCR 0x44 +#define RCC_R3CIDCFGR 0x48 +#define RCC_R3SEMCR 0x4C +#define RCC_R4CIDCFGR 0x50 +#define RCC_R4SEMCR 0x54 +#define RCC_R5CIDCFGR 0x58 +#define RCC_R5SEMCR 0x5C +#define RCC_R6CIDCFGR 0x60 +#define RCC_R6SEMCR 0x64 +#define RCC_R7CIDCFGR 0x68 +#define RCC_R7SEMCR 0x6C +#define RCC_R8CIDCFGR 0x70 +#define RCC_R8SEMCR 0x74 +#define RCC_R9CIDCFGR 0x78 +#define RCC_R9SEMCR 0x7C +#define RCC_R10CIDCFGR 0x80 +#define RCC_R10SEMCR 0x84 +#define RCC_R11CIDCFGR 0x88 +#define RCC_R11SEMCR 0x8C +#define RCC_R12CIDCFGR 0x90 +#define RCC_R12SEMCR 0x94 +#define RCC_R13CIDCFGR 0x98 +#define RCC_R13SEMCR 0x9C +#define RCC_R14CIDCFGR 0xA0 +#define RCC_R14SEMCR 0xA4 +#define RCC_R15CIDCFGR 0xA8 +#define RCC_R15SEMCR 0xAC +#define RCC_R16CIDCFGR 0xB0 +#define RCC_R16SEMCR 0xB4 +#define RCC_R17CIDCFGR 0xB8 +#define RCC_R17SEMCR 0xBC +#define RCC_R18CIDCFGR 0xC0 +#define RCC_R18SEMCR 0xC4 +#define RCC_R19CIDCFGR 0xC8 +#define RCC_R19SEMCR 0xCC +#define RCC_R20CIDCFGR 0xD0 +#define RCC_R20SEMCR 0xD4 +#define RCC_R21CIDCFGR 0xD8 +#define RCC_R21SEMCR 0xDC +#define RCC_R22CIDCFGR 0xE0 +#define RCC_R22SEMCR 0xE4 +#define RCC_R23CIDCFGR 0xE8 +#define RCC_R23SEMCR 0xEC +#define RCC_R24CIDCFGR 0xF0 +#define RCC_R24SEMCR 0xF4 +#define RCC_R25CIDCFGR 0xF8 +#define RCC_R25SEMCR 0xFC +#define RCC_R26CIDCFGR 0x100 +#define RCC_R26SEMCR 0x104 +#define RCC_R27CIDCFGR 0x108 +#define RCC_R27SEMCR 0x10C +#define RCC_R28CIDCFGR 0x110 +#define RCC_R28SEMCR 0x114 +#define RCC_R29CIDCFGR 0x118 +#define RCC_R29SEMCR 0x11C +#define RCC_R30CIDCFGR 0x120 +#define RCC_R30SEMCR 0x124 +#define RCC_R31CIDCFGR 0x128 +#define RCC_R31SEMCR 0x12C +#define RCC_R32CIDCFGR 0x130 +#define RCC_R32SEMCR 0x134 +#define RCC_R33CIDCFGR 0x138 +#define RCC_R33SEMCR 0x13C +#define RCC_R34CIDCFGR 0x140 +#define RCC_R34SEMCR 0x144 +#define RCC_R35CIDCFGR 0x148 +#define RCC_R35SEMCR 0x14C +#define RCC_R36CIDCFGR 0x150 +#define RCC_R36SEMCR 0x154 +#define RCC_R37CIDCFGR 0x158 +#define RCC_R37SEMCR 0x15C +#define RCC_R38CIDCFGR 0x160 +#define RCC_R38SEMCR 0x164 +#define RCC_R39CIDCFGR 0x168 +#define RCC_R39SEMCR 0x16C +#define RCC_R40CIDCFGR 0x170 +#define RCC_R40SEMCR 0x174 +#define RCC_R41CIDCFGR 0x178 +#define RCC_R41SEMCR 0x17C +#define RCC_R42CIDCFGR 0x180 +#define RCC_R42SEMCR 0x184 +#define RCC_R43CIDCFGR 0x188 +#define RCC_R43SEMCR 0x18C +#define RCC_R44CIDCFGR 0x190 +#define RCC_R44SEMCR 0x194 +#define RCC_R45CIDCFGR 0x198 +#define RCC_R45SEMCR 0x19C +#define RCC_R46CIDCFGR 0x1A0 +#define RCC_R46SEMCR 0x1A4 +#define RCC_R47CIDCFGR 0x1A8 +#define RCC_R47SEMCR 0x1AC +#define RCC_R48CIDCFGR 0x1B0 +#define RCC_R48SEMCR 0x1B4 +#define RCC_R49CIDCFGR 0x1B8 +#define RCC_R49SEMCR 0x1BC +#define RCC_R50CIDCFGR 0x1C0 +#define RCC_R50SEMCR 0x1C4 +#define RCC_R51CIDCFGR 0x1C8 +#define RCC_R51SEMCR 0x1CC +#define RCC_R52CIDCFGR 0x1D0 +#define RCC_R52SEMCR 0x1D4 +#define RCC_R53CIDCFGR 0x1D8 +#define RCC_R53SEMCR 0x1DC +#define RCC_R54CIDCFGR 0x1E0 +#define RCC_R54SEMCR 0x1E4 +#define RCC_R55CIDCFGR 0x1E8 +#define RCC_R55SEMCR 0x1EC +#define RCC_R56CIDCFGR 0x1F0 +#define RCC_R56SEMCR 0x1F4 +#define RCC_R57CIDCFGR 0x1F8 +#define RCC_R57SEMCR 0x1FC +#define RCC_R58CIDCFGR 0x200 +#define RCC_R58SEMCR 0x204 +#define RCC_R59CIDCFGR 0x208 +#define RCC_R59SEMCR 0x20C +#define RCC_R60CIDCFGR 0x210 +#define RCC_R60SEMCR 0x214 +#define RCC_R61CIDCFGR 0x218 +#define RCC_R61SEMCR 0x21C +#define RCC_R62CIDCFGR 0x220 +#define RCC_R62SEMCR 0x224 +#define RCC_R63CIDCFGR 0x228 +#define RCC_R63SEMCR 0x22C +#define RCC_R64CIDCFGR 0x230 +#define RCC_R64SEMCR 0x234 +#define RCC_R65CIDCFGR 0x238 +#define RCC_R65SEMCR 0x23C +#define RCC_R66CIDCFGR 0x240 +#define RCC_R66SEMCR 0x244 +#define RCC_R67CIDCFGR 0x248 +#define RCC_R67SEMCR 0x24C +#define RCC_R68CIDCFGR 0x250 +#define RCC_R68SEMCR 0x254 +#define RCC_R69CIDCFGR 0x258 +#define RCC_R69SEMCR 0x25C +#define RCC_R70CIDCFGR 0x260 +#define RCC_R70SEMCR 0x264 +#define RCC_R71CIDCFGR 0x268 +#define RCC_R71SEMCR 0x26C +#define RCC_R72CIDCFGR 0x270 +#define RCC_R72SEMCR 0x274 +#define RCC_R73CIDCFGR 0x278 +#define RCC_R73SEMCR 0x27C +#define RCC_R74CIDCFGR 0x280 +#define RCC_R74SEMCR 0x284 +#define RCC_R75CIDCFGR 0x288 +#define RCC_R75SEMCR 0x28C +#define RCC_R76CIDCFGR 0x290 +#define RCC_R76SEMCR 0x294 +#define RCC_R77CIDCFGR 0x298 +#define RCC_R77SEMCR 0x29C +#define RCC_R78CIDCFGR 0x2A0 +#define RCC_R78SEMCR 0x2A4 +#define RCC_R79CIDCFGR 0x2A8 +#define RCC_R79SEMCR 0x2AC +#define RCC_R80CIDCFGR 0x2B0 +#define RCC_R80SEMCR 0x2B4 +#define RCC_R81CIDCFGR 0x2B8 +#define RCC_R81SEMCR 0x2BC +#define RCC_R82CIDCFGR 0x2C0 +#define RCC_R82SEMCR 0x2C4 +#define RCC_R83CIDCFGR 0x2C8 +#define RCC_R83SEMCR 0x2CC +#define RCC_R84CIDCFGR 0x2D0 +#define RCC_R84SEMCR 0x2D4 +#define RCC_R85CIDCFGR 0x2D8 +#define RCC_R85SEMCR 0x2DC +#define RCC_R86CIDCFGR 0x2E0 +#define RCC_R86SEMCR 0x2E4 +#define RCC_R87CIDCFGR 0x2E8 +#define RCC_R87SEMCR 0x2EC +#define RCC_R88CIDCFGR 0x2F0 +#define RCC_R88SEMCR 0x2F4 +#define RCC_R89CIDCFGR 0x2F8 +#define RCC_R89SEMCR 0x2FC +#define RCC_R90CIDCFGR 0x300 +#define RCC_R90SEMCR 0x304 +#define RCC_R91CIDCFGR 0x308 +#define RCC_R91SEMCR 0x30C +#define RCC_R92CIDCFGR 0x310 +#define RCC_R92SEMCR 0x314 +#define RCC_R93CIDCFGR 0x318 +#define RCC_R93SEMCR 0x31C +#define RCC_R94CIDCFGR 0x320 +#define RCC_R94SEMCR 0x324 +#define RCC_R95CIDCFGR 0x328 +#define RCC_R95SEMCR 0x32C +#define RCC_R96CIDCFGR 0x330 +#define RCC_R96SEMCR 0x334 +#define RCC_R97CIDCFGR 0x338 +#define RCC_R97SEMCR 0x33C +#define RCC_R98CIDCFGR 0x340 +#define RCC_R98SEMCR 0x344 +#define RCC_R99CIDCFGR 0x348 +#define RCC_R99SEMCR 0x34C +#define RCC_R100CIDCFGR 0x350 +#define RCC_R100SEMCR 0x354 +#define RCC_R101CIDCFGR 0x358 +#define RCC_R101SEMCR 0x35C +#define RCC_R102CIDCFGR 0x360 +#define RCC_R102SEMCR 0x364 +#define RCC_R103CIDCFGR 0x368 +#define RCC_R103SEMCR 0x36C +#define RCC_R104CIDCFGR 0x370 +#define RCC_R104SEMCR 0x374 +#define RCC_R105CIDCFGR 0x378 +#define RCC_R105SEMCR 0x37C +#define RCC_R106CIDCFGR 0x380 +#define RCC_R106SEMCR 0x384 +#define RCC_R107CIDCFGR 0x388 +#define RCC_R107SEMCR 0x38C +#define RCC_R108CIDCFGR 0x390 +#define RCC_R108SEMCR 0x394 +#define RCC_R109CIDCFGR 0x398 +#define RCC_R109SEMCR 0x39C +#define RCC_R110CIDCFGR 0x3A0 +#define RCC_R110SEMCR 0x3A4 +#define RCC_R111CIDCFGR 0x3A8 +#define RCC_R111SEMCR 0x3AC +#define RCC_R112CIDCFGR 0x3B0 +#define RCC_R112SEMCR 0x3B4 +#define RCC_R113CIDCFGR 0x3B8 +#define RCC_R113SEMCR 0x3BC +#define RCC_GRSTCSETR 0x400 +#define RCC_C1RSTCSETR 0x404 +#define RCC_C1P1RSTCSETR 0x408 +#define RCC_C2RSTCSETR 0x40C +#define RCC_HWRSTSCLRR 0x410 +#define RCC_C1HWRSTSCLRR 0x414 +#define RCC_C2HWRSTSCLRR 0x418 +#define RCC_C1BOOTRSTSSETR 0x41C +#define RCC_C1BOOTRSTSCLRR 0x420 +#define RCC_C2BOOTRSTSSETR 0x424 +#define RCC_C2BOOTRSTSCLRR 0x428 +#define RCC_C1SREQSETR 0x42C +#define RCC_C1SREQCLRR 0x430 +#define RCC_CPUBOOTCR 0x434 +#define RCC_STBYBOOTCR 0x438 +#define RCC_LEGBOOTCR 0x43C +#define RCC_BDCR 0x440 +#define RCC_D3DCR 0x444 +#define RCC_D3DSR 0x448 +#define RCC_RDCR 0x44C +#define RCC_C1MSRDCR 0x450 +#define RCC_PWRLPDLYCR 0x454 +#define RCC_C1CIESETR 0x458 +#define RCC_C1CIFCLRR 0x45C +#define RCC_C2CIESETR 0x460 +#define RCC_C2CIFCLRR 0x464 +#define RCC_IWDGC1FZSETR 0x468 +#define RCC_IWDGC1FZCLRR 0x46C +#define RCC_IWDGC1CFGSETR 0x470 +#define RCC_IWDGC1CFGCLRR 0x474 +#define RCC_IWDGC2FZSETR 0x478 +#define RCC_IWDGC2FZCLRR 0x47C +#define RCC_IWDGC2CFGSETR 0x480 +#define RCC_IWDGC2CFGCLRR 0x484 +#define RCC_IWDGC3CFGSETR 0x488 +#define RCC_IWDGC3CFGCLRR 0x48C +#define RCC_C3CFGR 0x490 +#define RCC_MCO1CFGR 0x494 +#define RCC_MCO2CFGR 0x498 +#define RCC_OCENSETR 0x49C +#define RCC_OCENCLRR 0x4A0 +#define RCC_OCRDYR 0x4A4 +#define RCC_HSICFGR 0x4A8 +#define RCC_MSICFGR 0x4AC +#define RCC_RTCDIVR 0x4B0 +#define RCC_APB1DIVR 0x4B4 +#define RCC_APB2DIVR 0x4B8 +#define RCC_APB3DIVR 0x4BC +#define RCC_APB4DIVR 0x4C0 +#define RCC_APBDBGDIVR 0x4C4 +#define RCC_TIMG1PRER 0x4C8 +#define RCC_TIMG2PRER 0x4CC +#define RCC_LSMCUDIVR 0x4D0 +#define RCC_DDRCPCFGR 0x4D4 +#define RCC_DDRCAPBCFGR 0x4D8 +#define RCC_DDRPHYCAPBCFGR 0x4DC +#define RCC_DDRPHYCCFGR 0x4E0 +#define RCC_DDRCFGR 0x4E4 +#define RCC_DDRITFCFGR 0x4E8 +#define RCC_SYSRAMCFGR 0x4F0 +#define RCC_VDERAMCFGR 0x4F4 +#define RCC_SRAM1CFGR 0x4F8 +#define RCC_SRAM2CFGR 0x4FC +#define RCC_RETRAMCFGR 0x500 +#define RCC_BKPSRAMCFGR 0x504 +#define RCC_LPSRAM1CFGR 0x508 +#define RCC_LPSRAM2CFGR 0x50C +#define RCC_LPSRAM3CFGR 0x510 +#define RCC_OSPI1CFGR 0x514 +#define RCC_OSPI2CFGR 0x518 +#define RCC_FMCCFGR 0x51C +#define RCC_DBGCFGR 0x520 +#define RCC_STM500CFGR 0x524 +#define RCC_ETRCFGR 0x528 +#define RCC_GPIOACFGR 0x52C +#define RCC_GPIOBCFGR 0x530 +#define RCC_GPIOCCFGR 0x534 +#define RCC_GPIODCFGR 0x538 +#define RCC_GPIOECFGR 0x53C +#define RCC_GPIOFCFGR 0x540 +#define RCC_GPIOGCFGR 0x544 +#define RCC_GPIOHCFGR 0x548 +#define RCC_GPIOICFGR 0x54C +#define RCC_GPIOJCFGR 0x550 +#define RCC_GPIOKCFGR 0x554 +#define RCC_GPIOZCFGR 0x558 +#define RCC_HPDMA1CFGR 0x55C +#define RCC_HPDMA2CFGR 0x560 +#define RCC_HPDMA3CFGR 0x564 +#define RCC_LPDMACFGR 0x568 +#define RCC_HSEMCFGR 0x56C +#define RCC_IPCC1CFGR 0x570 +#define RCC_IPCC2CFGR 0x574 +#define RCC_RTCCFGR 0x578 +#define RCC_SYSCPU1CFGR 0x580 +#define RCC_BSECCFGR 0x584 +#define RCC_IS2MCFGR 0x58C +#define RCC_PLL2CFGR1 0x590 +#define RCC_PLL2CFGR2 0x594 +#define RCC_PLL2CFGR3 0x598 +#define RCC_PLL2CFGR4 0x59C +#define RCC_PLL2CFGR5 0x5A0 +#define RCC_PLL2CFGR6 0x5A8 +#define RCC_PLL2CFGR7 0x5AC +#define RCC_PLL3CFGR1 0x5B8 +#define RCC_PLL3CFGR2 0x5BC +#define RCC_PLL3CFGR3 0x5C0 +#define RCC_PLL3CFGR4 0x5C4 +#define RCC_PLL3CFGR5 0x5C8 +#define RCC_PLL3CFGR6 0x5D0 +#define RCC_PLL3CFGR7 0x5D4 +#define RCC_HSIFMONCR 0x5E0 +#define RCC_HSIFVALR 0x5E4 +#define RCC_TIM1CFGR 0x700 +#define RCC_TIM2CFGR 0x704 +#define RCC_TIM3CFGR 0x708 +#define RCC_TIM4CFGR 0x70C +#define RCC_TIM5CFGR 0x710 +#define RCC_TIM6CFGR 0x714 +#define RCC_TIM7CFGR 0x718 +#define RCC_TIM8CFGR 0x71C +#define RCC_TIM10CFGR 0x720 +#define RCC_TIM11CFGR 0x724 +#define RCC_TIM12CFGR 0x728 +#define RCC_TIM13CFGR 0x72C +#define RCC_TIM14CFGR 0x730 +#define RCC_TIM15CFGR 0x734 +#define RCC_TIM16CFGR 0x738 +#define RCC_TIM17CFGR 0x73C +#define RCC_TIM20CFGR 0x740 +#define RCC_LPTIM1CFGR 0x744 +#define RCC_LPTIM2CFGR 0x748 +#define RCC_LPTIM3CFGR 0x74C +#define RCC_LPTIM4CFGR 0x750 +#define RCC_LPTIM5CFGR 0x754 +#define RCC_SPI1CFGR 0x758 +#define RCC_SPI2CFGR 0x75C +#define RCC_SPI3CFGR 0x760 +#define RCC_SPI4CFGR 0x764 +#define RCC_SPI5CFGR 0x768 +#define RCC_SPI6CFGR 0x76C +#define RCC_SPI7CFGR 0x770 +#define RCC_SPI8CFGR 0x774 +#define RCC_SPDIFRXCFGR 0x778 +#define RCC_USART1CFGR 0x77C +#define RCC_USART2CFGR 0x780 +#define RCC_USART3CFGR 0x784 +#define RCC_UART4CFGR 0x788 +#define RCC_UART5CFGR 0x78C +#define RCC_USART6CFGR 0x790 +#define RCC_UART7CFGR 0x794 +#define RCC_UART8CFGR 0x798 +#define RCC_UART9CFGR 0x79C +#define RCC_LPUART1CFGR 0x7A0 +#define RCC_I2C1CFGR 0x7A4 +#define RCC_I2C2CFGR 0x7A8 +#define RCC_I2C3CFGR 0x7AC +#define RCC_I2C4CFGR 0x7B0 +#define RCC_I2C5CFGR 0x7B4 +#define RCC_I2C6CFGR 0x7B8 +#define RCC_I2C7CFGR 0x7BC +#define RCC_I2C8CFGR 0x7C0 +#define RCC_SAI1CFGR 0x7C4 +#define RCC_SAI2CFGR 0x7C8 +#define RCC_SAI3CFGR 0x7CC +#define RCC_SAI4CFGR 0x7D0 +#define RCC_MDF1CFGR 0x7D8 +#define RCC_ADF1CFGR 0x7DC +#define RCC_FDCANCFGR 0x7E0 +#define RCC_HDPCFGR 0x7E4 +#define RCC_ADC12CFGR 0x7E8 +#define RCC_ADC3CFGR 0x7EC +#define RCC_ETH1CFGR 0x7F0 +#define RCC_ETH2CFGR 0x7F4 +#define RCC_USBHCFGR 0x7FC +#define RCC_USB2PHY1CFGR 0x800 +#define RCC_USB2PHY2CFGR 0x804 +#define RCC_USB3DRCFGR 0x808 +#define RCC_USB3PCIEPHYCFGR 0x80C +#define RCC_PCIECFGR 0x810 +#define RCC_UCPDCFGR 0x814 +#define RCC_ETHSWCFGR 0x818 +#define RCC_ETHSWACMCFGR 0x81C +#define RCC_ETHSWACMMSGCFGR 0x820 +#define RCC_STGENCFGR 0x824 +#define RCC_SDMMC1CFGR 0x830 +#define RCC_SDMMC2CFGR 0x834 +#define RCC_SDMMC3CFGR 0x838 +#define RCC_GPUCFGR 0x83C +#define RCC_LTDCCFGR 0x840 +#define RCC_DSICFGR 0x844 +#define RCC_LVDSCFGR 0x850 +#define RCC_CSICFGR 0x858 +#define RCC_DCMIPPCFGR 0x85C +#define RCC_CCICFGR 0x860 +#define RCC_VDECCFGR 0x864 +#define RCC_VENCCFGR 0x868 +#define RCC_RNGCFGR 0x870 +#define RCC_PKACFGR 0x874 +#define RCC_SAESCFGR 0x878 +#define RCC_HASHCFGR 0x87C +#define RCC_CRYP1CFGR 0x880 +#define RCC_CRYP2CFGR 0x884 +#define RCC_IWDG1CFGR 0x888 +#define RCC_IWDG2CFGR 0x88C +#define RCC_IWDG3CFGR 0x890 +#define RCC_IWDG4CFGR 0x894 +#define RCC_IWDG5CFGR 0x898 +#define RCC_WWDG1CFGR 0x89C +#define RCC_WWDG2CFGR 0x8A0 +#define RCC_VREFCFGR 0x8A8 +#define RCC_DTSCFGR 0x8AC +#define RCC_CRCCFGR 0x8B4 +#define RCC_SERCCFGR 0x8B8 +#define RCC_OSPIIOMCFGR 0x8BC +#define RCC_GICV2MCFGR 0x8C0 +#define RCC_I3C1CFGR 0x8C8 +#define RCC_I3C2CFGR 0x8CC +#define RCC_I3C3CFGR 0x8D0 +#define RCC_I3C4CFGR 0x8D4 +#define RCC_MUXSELCFGR 0x1000 +#define RCC_XBAR0CFGR 0x1018 +#define RCC_XBAR1CFGR 0x101C +#define RCC_XBAR2CFGR 0x1020 +#define RCC_XBAR3CFGR 0x1024 +#define RCC_XBAR4CFGR 0x1028 +#define RCC_XBAR5CFGR 0x102C +#define RCC_XBAR6CFGR 0x1030 +#define RCC_XBAR7CFGR 0x1034 +#define RCC_XBAR8CFGR 0x1038 +#define RCC_XBAR9CFGR 0x103C +#define RCC_XBAR10CFGR 0x1040 +#define RCC_XBAR11CFGR 0x1044 +#define RCC_XBAR12CFGR 0x1048 +#define RCC_XBAR13CFGR 0x104C +#define RCC_XBAR14CFGR 0x1050 +#define RCC_XBAR15CFGR 0x1054 +#define RCC_XBAR16CFGR 0x1058 +#define RCC_XBAR17CFGR 0x105C +#define RCC_XBAR18CFGR 0x1060 +#define RCC_XBAR19CFGR 0x1064 +#define RCC_XBAR20CFGR 0x1068 +#define RCC_XBAR21CFGR 0x106C +#define RCC_XBAR22CFGR 0x1070 +#define RCC_XBAR23CFGR 0x1074 +#define RCC_XBAR24CFGR 0x1078 +#define RCC_XBAR25CFGR 0x107C +#define RCC_XBAR26CFGR 0x1080 +#define RCC_XBAR27CFGR 0x1084 +#define RCC_XBAR28CFGR 0x1088 +#define RCC_XBAR29CFGR 0x108C +#define RCC_XBAR30CFGR 0x1090 +#define RCC_XBAR31CFGR 0x1094 +#define RCC_XBAR32CFGR 0x1098 +#define RCC_XBAR33CFGR 0x109C +#define RCC_XBAR34CFGR 0x10A0 +#define RCC_XBAR35CFGR 0x10A4 +#define RCC_XBAR36CFGR 0x10A8 +#define RCC_XBAR37CFGR 0x10AC +#define RCC_XBAR38CFGR 0x10B0 +#define RCC_XBAR39CFGR 0x10B4 +#define RCC_XBAR40CFGR 0x10B8 +#define RCC_XBAR41CFGR 0x10BC +#define RCC_XBAR42CFGR 0x10C0 +#define RCC_XBAR43CFGR 0x10C4 +#define RCC_XBAR44CFGR 0x10C8 +#define RCC_XBAR45CFGR 0x10CC +#define RCC_XBAR46CFGR 0x10D0 +#define RCC_XBAR47CFGR 0x10D4 +#define RCC_XBAR48CFGR 0x10D8 +#define RCC_XBAR49CFGR 0x10DC +#define RCC_XBAR50CFGR 0x10E0 +#define RCC_XBAR51CFGR 0x10E4 +#define RCC_XBAR52CFGR 0x10E8 +#define RCC_XBAR53CFGR 0x10EC +#define RCC_XBAR54CFGR 0x10F0 +#define RCC_XBAR55CFGR 0x10F4 +#define RCC_XBAR56CFGR 0x10F8 +#define RCC_XBAR57CFGR 0x10FC +#define RCC_XBAR58CFGR 0x1100 +#define RCC_XBAR59CFGR 0x1104 +#define RCC_XBAR60CFGR 0x1108 +#define RCC_XBAR61CFGR 0x110C +#define RCC_XBAR62CFGR 0x1110 +#define RCC_XBAR63CFGR 0x1114 +#define RCC_PREDIV0CFGR 0x1118 +#define RCC_PREDIV1CFGR 0x111C +#define RCC_PREDIV2CFGR 0x1120 +#define RCC_PREDIV3CFGR 0x1124 +#define RCC_PREDIV4CFGR 0x1128 +#define RCC_PREDIV5CFGR 0x112C +#define RCC_PREDIV6CFGR 0x1130 +#define RCC_PREDIV7CFGR 0x1134 +#define RCC_PREDIV8CFGR 0x1138 +#define RCC_PREDIV9CFGR 0x113C +#define RCC_PREDIV10CFGR 0x1140 +#define RCC_PREDIV11CFGR 0x1144 +#define RCC_PREDIV12CFGR 0x1148 +#define RCC_PREDIV13CFGR 0x114C +#define RCC_PREDIV14CFGR 0x1150 +#define RCC_PREDIV15CFGR 0x1154 +#define RCC_PREDIV16CFGR 0x1158 +#define RCC_PREDIV17CFGR 0x115C +#define RCC_PREDIV18CFGR 0x1160 +#define RCC_PREDIV19CFGR 0x1164 +#define RCC_PREDIV20CFGR 0x1168 +#define RCC_PREDIV21CFGR 0x116C +#define RCC_PREDIV22CFGR 0x1170 +#define RCC_PREDIV23CFGR 0x1174 +#define RCC_PREDIV24CFGR 0x1178 +#define RCC_PREDIV25CFGR 0x117C +#define RCC_PREDIV26CFGR 0x1180 +#define RCC_PREDIV27CFGR 0x1184 +#define RCC_PREDIV28CFGR 0x1188 +#define RCC_PREDIV29CFGR 0x118C +#define RCC_PREDIV30CFGR 0x1190 +#define RCC_PREDIV31CFGR 0x1194 +#define RCC_PREDIV32CFGR 0x1198 +#define RCC_PREDIV33CFGR 0x119C +#define RCC_PREDIV34CFGR 0x11A0 +#define RCC_PREDIV35CFGR 0x11A4 +#define RCC_PREDIV36CFGR 0x11A8 +#define RCC_PREDIV37CFGR 0x11AC +#define RCC_PREDIV38CFGR 0x11B0 +#define RCC_PREDIV39CFGR 0x11B4 +#define RCC_PREDIV40CFGR 0x11B8 +#define RCC_PREDIV41CFGR 0x11BC +#define RCC_PREDIV42CFGR 0x11C0 +#define RCC_PREDIV43CFGR 0x11C4 +#define RCC_PREDIV44CFGR 0x11C8 +#define RCC_PREDIV45CFGR 0x11CC +#define RCC_PREDIV46CFGR 0x11D0 +#define RCC_PREDIV47CFGR 0x11D4 +#define RCC_PREDIV48CFGR 0x11D8 +#define RCC_PREDIV49CFGR 0x11DC +#define RCC_PREDIV50CFGR 0x11E0 +#define RCC_PREDIV51CFGR 0x11E4 +#define RCC_PREDIV52CFGR 0x11E8 +#define RCC_PREDIV53CFGR 0x11EC +#define RCC_PREDIV54CFGR 0x11F0 +#define RCC_PREDIV55CFGR 0x11F4 +#define RCC_PREDIV56CFGR 0x11F8 +#define RCC_PREDIV57CFGR 0x11FC +#define RCC_PREDIV58CFGR 0x1200 +#define RCC_PREDIV59CFGR 0x1204 +#define RCC_PREDIV60CFGR 0x1208 +#define RCC_PREDIV61CFGR 0x120C +#define RCC_PREDIV62CFGR 0x1210 +#define RCC_PREDIV63CFGR 0x1214 +#define RCC_PREDIVSR1 0x1218 +#define RCC_PREDIVSR2 0x121C +#define RCC_FINDIV0CFGR 0x1224 +#define RCC_FINDIV1CFGR 0x1228 +#define RCC_FINDIV2CFGR 0x122C +#define RCC_FINDIV3CFGR 0x1230 +#define RCC_FINDIV4CFGR 0x1234 +#define RCC_FINDIV5CFGR 0x1238 +#define RCC_FINDIV6CFGR 0x123C +#define RCC_FINDIV7CFGR 0x1240 +#define RCC_FINDIV8CFGR 0x1244 +#define RCC_FINDIV9CFGR 0x1248 +#define RCC_FINDIV10CFGR 0x124C +#define RCC_FINDIV11CFGR 0x1250 +#define RCC_FINDIV12CFGR 0x1254 +#define RCC_FINDIV13CFGR 0x1258 +#define RCC_FINDIV14CFGR 0x125C +#define RCC_FINDIV15CFGR 0x1260 +#define RCC_FINDIV16CFGR 0x1264 +#define RCC_FINDIV17CFGR 0x1268 +#define RCC_FINDIV18CFGR 0x126C +#define RCC_FINDIV19CFGR 0x1270 +#define RCC_FINDIV20CFGR 0x1274 +#define RCC_FINDIV21CFGR 0x1278 +#define RCC_FINDIV22CFGR 0x127C +#define RCC_FINDIV23CFGR 0x1280 +#define RCC_FINDIV24CFGR 0x1284 +#define RCC_FINDIV25CFGR 0x1288 +#define RCC_FINDIV26CFGR 0x128C +#define RCC_FINDIV27CFGR 0x1290 +#define RCC_FINDIV28CFGR 0x1294 +#define RCC_FINDIV29CFGR 0x1298 +#define RCC_FINDIV30CFGR 0x129C +#define RCC_FINDIV31CFGR 0x12A0 +#define RCC_FINDIV32CFGR 0x12A4 +#define RCC_FINDIV33CFGR 0x12A8 +#define RCC_FINDIV34CFGR 0x12AC +#define RCC_FINDIV35CFGR 0x12B0 +#define RCC_FINDIV36CFGR 0x12B4 +#define RCC_FINDIV37CFGR 0x12B8 +#define RCC_FINDIV38CFGR 0x12BC +#define RCC_FINDIV39CFGR 0x12C0 +#define RCC_FINDIV40CFGR 0x12C4 +#define RCC_FINDIV41CFGR 0x12C8 +#define RCC_FINDIV42CFGR 0x12CC +#define RCC_FINDIV43CFGR 0x12D0 +#define RCC_FINDIV44CFGR 0x12D4 +#define RCC_FINDIV45CFGR 0x12D8 +#define RCC_FINDIV46CFGR 0x12DC +#define RCC_FINDIV47CFGR 0x12E0 +#define RCC_FINDIV48CFGR 0x12E4 +#define RCC_FINDIV49CFGR 0x12E8 +#define RCC_FINDIV50CFGR 0x12EC +#define RCC_FINDIV51CFGR 0x12F0 +#define RCC_FINDIV52CFGR 0x12F4 +#define RCC_FINDIV53CFGR 0x12F8 +#define RCC_FINDIV54CFGR 0x12FC +#define RCC_FINDIV55CFGR 0x1300 +#define RCC_FINDIV56CFGR 0x1304 +#define RCC_FINDIV57CFGR 0x1308 +#define RCC_FINDIV58CFGR 0x130C +#define RCC_FINDIV59CFGR 0x1310 +#define RCC_FINDIV60CFGR 0x1314 +#define RCC_FINDIV61CFGR 0x1318 +#define RCC_FINDIV62CFGR 0x131C +#define RCC_FINDIV63CFGR 0x1320 +#define RCC_FINDIVSR1 0x1324 +#define RCC_FINDIVSR2 0x1328 +#define RCC_FCALCOBS0CFGR 0x1340 +#define RCC_FCALCOBS1CFGR 0x1344 +#define RCC_FCALCREFCFGR 0x1348 +#define RCC_FCALCCR1 0x134C +#define RCC_FCALCCR2 0x1354 +#define RCC_FCALCSR 0x1358 +#define RCC_PLL4CFGR1 0x1360 +#define RCC_PLL4CFGR2 0x1364 +#define RCC_PLL4CFGR3 0x1368 +#define RCC_PLL4CFGR4 0x136C +#define RCC_PLL4CFGR5 0x1370 +#define RCC_PLL4CFGR6 0x1378 +#define RCC_PLL4CFGR7 0x137C +#define RCC_PLL5CFGR1 0x1388 +#define RCC_PLL5CFGR2 0x138C +#define RCC_PLL5CFGR3 0x1390 +#define RCC_PLL5CFGR4 0x1394 +#define RCC_PLL5CFGR5 0x1398 +#define RCC_PLL5CFGR6 0x13A0 +#define RCC_PLL5CFGR7 0x13A4 +#define RCC_PLL6CFGR1 0x13B0 +#define RCC_PLL6CFGR2 0x13B4 +#define RCC_PLL6CFGR3 0x13B8 +#define RCC_PLL6CFGR4 0x13BC +#define RCC_PLL6CFGR5 0x13C0 +#define RCC_PLL6CFGR6 0x13C8 +#define RCC_PLL6CFGR7 0x13CC +#define RCC_PLL7CFGR1 0x13D8 +#define RCC_PLL7CFGR2 0x13DC +#define RCC_PLL7CFGR3 0x13E0 +#define RCC_PLL7CFGR4 0x13E4 +#define RCC_PLL7CFGR5 0x13E8 +#define RCC_PLL7CFGR6 0x13F0 +#define RCC_PLL7CFGR7 0x13F4 +#define RCC_PLL8CFGR1 0x1400 +#define RCC_PLL8CFGR2 0x1404 +#define RCC_PLL8CFGR3 0x1408 +#define RCC_PLL8CFGR4 0x140C +#define RCC_PLL8CFGR5 0x1410 +#define RCC_PLL8CFGR6 0x1418 +#define RCC_PLL8CFGR7 0x141C +#define RCC_VERR 0xFFF4 +#define RCC_IDR 0xFFF8 +#define RCC_SIDR 0xFFFC + +#endif /* STM32MP25_RCC_H */ -- cgit v1.3.1 From 0846bad0d08b53f6abaa4c8afe812dba93057424 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Tue, 27 May 2025 15:27:46 +0200 Subject: clk: add CONFIG_CLK_AUTO_ID Add a new config CONFIG_CLK_AUTO_ID to support a unique clk id for all the clock providers, managed by clk uclass, when the clock reference arg[0] is the same. When the CONFIG is activated, the clock id is limited to the lower CLK_ID_SZ = 24 bits in default clock xlate function and the sequence number + 1 of the clk provider device is added for the 8 higher bits. We use sequence number + 1 to avoid the "dummy" clock id = 0, used for invalid clock when CCF is activated. When this config is activated, the new function clk_get_id() should be used to get back the internal reference to clock for the each clock provider. Signed-off-by: Patrick Delaunay Signed-off-by: Patrice Chotard Cc: Lukasz Majewski Cc: Sean Anderson Reviewed-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- drivers/clk/Kconfig | 10 ++++++++++ drivers/clk/clk-uclass.c | 9 +++++++-- drivers/clk/stm32/clk-stm32-core.c | 3 ++- include/clk.h | 24 ++++++++++++++++++++++++ include/linux/clk-provider.h | 9 ++++++++- 5 files changed, 51 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 19aa2ffa539..8dbcc35335f 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -10,6 +10,16 @@ config CLK feed into other clocks in a tree structure, with multiplexers to choose the source for each clock. +config CLK_AUTO_ID + bool "Enable support of an unique clock id with several provider" + depends on CLK + help + Add the uclass sequence number of clock provider in the 8 higher bits + of the clk id to guaranty an unique clock identifier in clk uclass + when several clock providers are present on the device and when + default xlate are used. + This feature limit each identifier for each clock providers (24 bits). + config SPL_CLK bool "Enable clock support in SPL" depends on CLK && SPL && SPL_DM diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 2167cd5ad0f..7262e89b512 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -34,6 +34,11 @@ struct clk *dev_get_clk_ptr(struct udevice *dev) return (struct clk *)dev_get_uclass_priv(dev); } +ulong clk_get_id(const struct clk *clk) +{ + return (ulong)(clk->id & CLK_ID_MSK); +} + #if CONFIG_IS_ENABLED(OF_PLATDATA) int clk_get_by_phandle(struct udevice *dev, const struct phandle_1_arg *cells, struct clk *clk) @@ -43,7 +48,7 @@ int clk_get_by_phandle(struct udevice *dev, const struct phandle_1_arg *cells, ret = device_get_by_ofplat_idx(cells->idx, &clk->dev); if (ret) return ret; - clk->id = cells->arg[0]; + clk->id = CLK_ID(dev, cells->arg[0]); return 0; } @@ -61,7 +66,7 @@ static int clk_of_xlate_default(struct clk *clk, } if (args->args_count) - clk->id = args->args[0]; + clk->id = CLK_ID(clk->dev, args->args[0]); else clk->id = 0; diff --git a/drivers/clk/stm32/clk-stm32-core.c b/drivers/clk/stm32/clk-stm32-core.c index 358ee56682a..df3b35b1003 100644 --- a/drivers/clk/stm32/clk-stm32-core.c +++ b/drivers/clk/stm32/clk-stm32-core.c @@ -46,7 +46,8 @@ int stm32_rcc_init(struct udevice *dev, if (cfg->setup) { clk = cfg->setup(dev, cfg); - clk->id = cfg->id; + /* set identifier of clock provider*/ + dev_clk_dm(dev, cfg->id, clk); } else { dev_err(dev, "failed to register clock %s\n", cfg->name); return -ENOENT; diff --git a/include/clk.h b/include/clk.h index a6ef4e02692..f94135ff778 100644 --- a/include/clk.h +++ b/include/clk.h @@ -13,6 +13,15 @@ #include #include +#ifdef CONFIG_CLK_AUTO_ID +#define CLK_ID_SZ 24 +#define CLK_ID_MSK GENMASK(23, 0) +#define CLK_ID(dev, id) (((dev_seq(dev) + 1) << CLK_ID_SZ) | ((id) & CLK_ID_MSK)) +#else +#define CLK_ID_MSK (~0UL) +#define CLK_ID(dev, id) id +#endif + /** * DOC: Overview * @@ -570,6 +579,16 @@ int clk_get_by_id(ulong id, struct clk **clkp); */ bool clk_dev_binded(struct clk *clk); +/** + * clk_get_id - get clk id + * + * @clk: A clock struct + * + * Return: the clock identifier as it is defined by the clock provider in + * device tree or in platdata + */ +ulong clk_get_id(const struct clk *clk); + #else /* CONFIG_IS_ENABLED(CLK) */ static inline int clk_request(struct udevice *dev, struct clk *clk) @@ -641,6 +660,11 @@ static inline bool clk_dev_binded(struct clk *clk) { return false; } + +static inline ulong clk_get_id(const struct clk *clk) +{ + return 0; +} #endif /* CONFIG_IS_ENABLED(CLK) */ /** diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 267757939e0..2d754fa4287 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -15,10 +15,17 @@ struct udevice; +/* update clock ID for the dev = clock provider, compatible with CLK_AUTO_ID */ +static inline void dev_clk_dm(const struct udevice *dev, ulong id, struct clk *clk) +{ + if (!IS_ERR(clk)) + clk->id = CLK_ID(dev, id); +} + static inline void clk_dm(ulong id, struct clk *clk) { if (!IS_ERR(clk)) - clk->id = id; + clk->id = CLK_ID(clk->dev, id); } /* -- cgit v1.3.1 From 0994a627c27849f616b6d145508aed6bb8acc33d Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Tue, 27 May 2025 15:27:53 +0200 Subject: reset: stm32mp25: add stm32mp25 reset driver Implement STM32MP25 reset drivers using stm32-core-reset API. This reset stm32-reset-core API and will be able to use DT binding index started from 0. This patch also moves legacy reset into stm32 directory reset. Signed-off-by: Gabriel Fernandez Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay Reviewed-by: Patrice Chotard --- MAINTAINERS | 3 +- drivers/misc/stm32_rcc.c | 66 ++++++++------ drivers/reset/Kconfig | 9 +- drivers/reset/Makefile | 4 +- drivers/reset/stm32-reset.c | 97 -------------------- drivers/reset/stm32/Kconfig | 23 +++++ drivers/reset/stm32/Makefile | 9 ++ drivers/reset/stm32/stm32-reset-core.c | 92 +++++++++++++++++++ drivers/reset/stm32/stm32-reset-core.h | 31 +++++++ drivers/reset/stm32/stm32-reset-mp1.c | 55 ++++++++++++ drivers/reset/stm32/stm32-reset-mp25.c | 159 +++++++++++++++++++++++++++++++++ drivers/reset/stm32/stm32-reset.c | 43 +++++++++ include/stm32_rcc.h | 7 +- 13 files changed, 460 insertions(+), 138 deletions(-) delete mode 100644 drivers/reset/stm32-reset.c create mode 100644 drivers/reset/stm32/Kconfig create mode 100644 drivers/reset/stm32/Makefile create mode 100644 drivers/reset/stm32/stm32-reset-core.c create mode 100644 drivers/reset/stm32/stm32-reset-core.h create mode 100644 drivers/reset/stm32/stm32-reset-mp1.c create mode 100644 drivers/reset/stm32/stm32-reset-mp25.c create mode 100644 drivers/reset/stm32/stm32-reset.c (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 503b07149d2..5fda9b53499 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -718,7 +718,7 @@ F: drivers/power/regulator/stm32-vrefbuf.c F: drivers/power/regulator/stpmic1.c F: drivers/ram/stm32mp1/ F: drivers/remoteproc/stm32_copro.c -F: drivers/reset/stm32-reset.c +F: drivers/reset/stm32/ F: drivers/rng/optee_rng.c F: drivers/rng/stm32_rng.c F: drivers/rtc/stm32_rtc.c @@ -731,6 +731,7 @@ F: include/dt-bindings/clock/stm32fx-clock.h F: include/dt-bindings/clock/stm32mp* F: include/dt-bindings/pinctrl/stm32-pinfunc.h F: include/dt-bindings/reset/stm32mp* +F: include/stm32-reset-core.h F: include/stm32_rcc.h F: tools/logos/st.bmp F: tools/stm32image.c diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c index 5a6f979f91b..15bf69f7d57 100644 --- a/drivers/misc/stm32_rcc.c +++ b/drivers/misc/stm32_rcc.c @@ -14,47 +14,56 @@ #include #include -struct stm32_rcc_clk stm32_rcc_clk_f42x = { - .drv_name = "stm32fx_rcc_clock", +static const struct stm32_rcc stm32_rcc_f42x = { + .drv_name_clk = "stm32fx_rcc_clock", + .drv_name_rst = "stm32_rcc_reset", .soc = STM32F42X, }; -struct stm32_rcc_clk stm32_rcc_clk_f469 = { - .drv_name = "stm32fx_rcc_clock", +static const struct stm32_rcc stm32_rcc_f469 = { + .drv_name_clk = "stm32fx_rcc_clock", + .drv_name_rst = "stm32_rcc_reset", .soc = STM32F469, }; -struct stm32_rcc_clk stm32_rcc_clk_f7 = { - .drv_name = "stm32fx_rcc_clock", +static const struct stm32_rcc stm32_rcc_f7 = { + .drv_name_clk = "stm32fx_rcc_clock", + .drv_name_rst = "stm32_rcc_reset", .soc = STM32F7, }; -struct stm32_rcc_clk stm32_rcc_clk_h7 = { - .drv_name = "stm32h7_rcc_clock", +static const struct stm32_rcc stm32_rcc_h7 = { + .drv_name_clk = "stm32h7_rcc_clock", + .drv_name_rst = "stm32_rcc_reset", }; -struct stm32_rcc_clk stm32_rcc_clk_mp1 = { - .drv_name = "stm32mp1_clk", - .soc = STM32MP1, +static const struct stm32_rcc stm32_rcc_mp15 = { + .drv_name_clk = "stm32mp1_clk", + .drv_name_rst = "stm32mp1_reset", }; -struct stm32_rcc_clk stm32_rcc_clk_mp13 = { - .drv_name = "stm32mp13_clk", - .soc = STM32MP1, +static const struct stm32_rcc stm32_rcc_mp13 = { + .drv_name_clk = "stm32mp13_clk", + .drv_name_rst = "stm32mp1_reset", +}; + +static const struct stm32_rcc stm32_rcc_mp25 = { + .drv_name_clk = "stm32mp25_clk", + .drv_name_rst = "stm32mp25_reset", }; static int stm32_rcc_bind(struct udevice *dev) { struct udevice *child; struct driver *drv; - struct stm32_rcc_clk *rcc_clk = - (struct stm32_rcc_clk *)dev_get_driver_data(dev); + struct stm32_rcc *rcc_clk = + (struct stm32_rcc *)dev_get_driver_data(dev); int ret; dev_dbg(dev, "RCC bind\n"); - drv = lists_driver_lookup_name(rcc_clk->drv_name); + drv = lists_driver_lookup_name(rcc_clk->drv_name_clk); if (!drv) { - dev_err(dev, "Cannot find driver '%s'\n", rcc_clk->drv_name); + dev_err(dev, "Cannot find driver '%s'\n", rcc_clk->drv_name_clk); return -ENOENT; } @@ -65,25 +74,24 @@ static int stm32_rcc_bind(struct udevice *dev) if (ret) return ret; - drv = lists_driver_lookup_name("stm32_rcc_reset"); + drv = lists_driver_lookup_name(rcc_clk->drv_name_rst); if (!drv) { dev_err(dev, "Cannot find driver stm32_rcc_reset'\n"); return -ENOENT; } - return device_bind_with_driver_data(dev, drv, dev->name, - rcc_clk->soc, - dev_ofnode(dev), &child); + return device_bind(dev, drv, dev->name, NULL, dev_ofnode(dev), &child); } static const struct udevice_id stm32_rcc_ids[] = { - {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_clk_f42x }, - {.compatible = "st,stm32f469-rcc", .data = (ulong)&stm32_rcc_clk_f469 }, - {.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_clk_f7 }, - {.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_clk_h7 }, - {.compatible = "st,stm32mp1-rcc", .data = (ulong)&stm32_rcc_clk_mp1 }, - {.compatible = "st,stm32mp1-rcc-secure", .data = (ulong)&stm32_rcc_clk_mp1 }, - {.compatible = "st,stm32mp13-rcc", .data = (ulong)&stm32_rcc_clk_mp13 }, + {.compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32_rcc_f42x }, + {.compatible = "st,stm32f469-rcc", .data = (ulong)&stm32_rcc_f469 }, + {.compatible = "st,stm32f746-rcc", .data = (ulong)&stm32_rcc_f7 }, + {.compatible = "st,stm32h743-rcc", .data = (ulong)&stm32_rcc_h7 }, + {.compatible = "st,stm32mp1-rcc", .data = (ulong)&stm32_rcc_mp15 }, + {.compatible = "st,stm32mp1-rcc-secure", .data = (ulong)&stm32_rcc_mp15 }, + {.compatible = "st,stm32mp13-rcc", .data = (ulong)&stm32_rcc_mp13 }, + {.compatible = "st,stm32mp25-rcc", .data = (ulong)&stm32_rcc_mp25 }, { } }; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index a0d079c4555..e92bb8a7c39 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -28,13 +28,6 @@ config STI_RESET Say Y if you want to control reset signals provided by system config block. -config STM32_RESET - bool "Enable the STM32 reset" - depends on ARCH_STM32 || ARCH_STM32MP - help - Support for reset controllers on STMicroelectronics STM32 family SoCs. - This reset driver is compatible with STM32 F4/F7 and H7 SoCs. - config TEGRA_CAR_RESET bool "Enable Tegra CAR-based reset driver" depends on TEGRA_CAR @@ -258,4 +251,6 @@ config RESET_SPACEMIT_K1 help Support for SPACEMIT's K1 Reset system. Basic Assert/Deassert is supported. + +source "drivers/reset/stm32/Kconfig" endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 1dd3cd99a14..ee5b009d134 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -7,7 +7,6 @@ obj-$(CONFIG_DM_RESET) += reset-uclass.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o obj-$(CONFIG_STI_RESET) += sti-reset.o -obj-$(CONFIG_STM32_RESET) += stm32-reset.o obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o obj-$(CONFIG_RESET_AIROHA) += reset-airoha.o @@ -36,3 +35,6 @@ obj-$(CONFIG_RESET_AT91) += reset-at91.o obj-$(CONFIG_$(PHASE_)RESET_JH7110) += reset-jh7110.o obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o obj-$(CONFIG_RESET_SPACEMIT_K1) += reset-spacemit-k1.o + +obj-$(CONFIG_ARCH_STM32) += stm32/ +obj-$(CONFIG_ARCH_STM32MP) += stm32/ diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c deleted file mode 100644 index 9d4f361b251..00000000000 --- a/drivers/reset/stm32-reset.c +++ /dev/null @@ -1,97 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. - */ - -#define LOG_CATEGORY UCLASS_RESET - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* offset of register without set/clear management */ -#define RCC_MP_GCR_OFFSET 0x10C - -/* reset clear offset for STM32MP RCC */ -#define RCC_CL 0x4 - -struct stm32_reset_priv { - fdt_addr_t base; -}; - -static int stm32_reset_assert(struct reset_ctl *reset_ctl) -{ - struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev); - int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4; - int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE); - - dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n", - reset_ctl->id, bank, offset); - - if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) - if (bank != RCC_MP_GCR_OFFSET) - /* reset assert is done in rcc set register */ - writel(BIT(offset), priv->base + bank); - else - clrbits_le32(priv->base + bank, BIT(offset)); - else - setbits_le32(priv->base + bank, BIT(offset)); - - return 0; -} - -static int stm32_reset_deassert(struct reset_ctl *reset_ctl) -{ - struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev); - int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4; - int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE); - - dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n", - reset_ctl->id, bank, offset); - - if (dev_get_driver_data(reset_ctl->dev) == STM32MP1) - if (bank != RCC_MP_GCR_OFFSET) - /* reset deassert is done in rcc clr register */ - writel(BIT(offset), priv->base + bank + RCC_CL); - else - setbits_le32(priv->base + bank, BIT(offset)); - else - clrbits_le32(priv->base + bank, BIT(offset)); - - return 0; -} - -static const struct reset_ops stm32_reset_ops = { - .rst_assert = stm32_reset_assert, - .rst_deassert = stm32_reset_deassert, -}; - -static int stm32_reset_probe(struct udevice *dev) -{ - struct stm32_reset_priv *priv = dev_get_priv(dev); - - priv->base = dev_read_addr(dev); - if (priv->base == FDT_ADDR_T_NONE) { - /* for MFD, get address of parent */ - priv->base = dev_read_addr(dev->parent); - if (priv->base == FDT_ADDR_T_NONE) - return -EINVAL; - } - - return 0; -} - -U_BOOT_DRIVER(stm32_rcc_reset) = { - .name = "stm32_rcc_reset", - .id = UCLASS_RESET, - .probe = stm32_reset_probe, - .priv_auto = sizeof(struct stm32_reset_priv), - .ops = &stm32_reset_ops, -}; diff --git a/drivers/reset/stm32/Kconfig b/drivers/reset/stm32/Kconfig new file mode 100644 index 00000000000..39dcfa0a9ca --- /dev/null +++ b/drivers/reset/stm32/Kconfig @@ -0,0 +1,23 @@ +config RESET_STM32 + bool "Enable the STM32 reset" + depends on ARCH_STM32 + default y + help + Support for reset controllers on STMicroelectronics STM32 family SoCs. + This reset driver is compatible with STM32 F4/F7 and H7 SoCs. + +config RESET_STM32MP1 + bool "Enable the STM32MP1 reset" + depends on STM32MP13X || STM32MP15X + default y + help + Support for reset controllers on STMicroelectronics STM32MP1 family SoCs. + This reset driver is compatible with STM32MP13 and STM32MP15 SoCs. + +config RESET_STM32MP25 + bool "Enable the STM32MP25 reset" + depends on STM32MP25X + default y + help + Support for reset controllers on STMicroelectronics STM32MP2 family SoCs. + This reset driver is compatible with STM32MP25 SoCs. diff --git a/drivers/reset/stm32/Makefile b/drivers/reset/stm32/Makefile new file mode 100644 index 00000000000..c31ae524ba1 --- /dev/null +++ b/drivers/reset/stm32/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# +# Copyright (C) 2024, STMicroelectronics - All Rights Reserved + +obj-y += stm32-reset-core.o + +obj-$(CONFIG_RESET_STM32) += stm32-reset.o +obj-$(CONFIG_RESET_STM32MP1) += stm32-reset-mp1.o +obj-$(CONFIG_RESET_STM32MP25) += stm32-reset-mp25.o diff --git a/drivers/reset/stm32/stm32-reset-core.c b/drivers/reset/stm32/stm32-reset-core.c new file mode 100644 index 00000000000..7dd92e07e1a --- /dev/null +++ b/drivers/reset/stm32/stm32-reset-core.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2024, STMicroelectronics - All Rights Reserved + * Author(s): Gabriel Fernandez, for STMicroelectronics. + */ + +#include +#include +#include +#include +#include +#include + +static int stm32_reset_update(struct reset_ctl *reset_ctl, bool status) +{ + struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev); + const struct stm32_reset_data *data = priv->data; + const struct stm32_reset_cfg *ptr_line; + fdt_addr_t addr; + + assert(priv->data->get_reset_line); + + ptr_line = priv->data->get_reset_line(reset_ctl); + if (!ptr_line) + return -EPERM; + + addr = priv->base + ptr_line->offset; + + dev_dbg(reset_ctl->dev, "reset id=%ld offset=0x%x bit=%d status=%d\n", + reset_ctl->id, ptr_line->offset, ptr_line->bit_idx, status); + + status = ptr_line->inverted ^ status; + + if (ptr_line->set_clr) { + if (!status) + addr += data->clear_offset; + + writel(BIT(ptr_line->bit_idx), addr); + + } else { + if (status) + setbits_le32(addr, BIT(ptr_line->bit_idx)); + else + clrbits_le32(addr, BIT(ptr_line->bit_idx)); + } + + /* Check deassert */ + if (!status) { + u32 reg; + + return readl_poll_timeout(addr, reg, + !(reg & BIT(ptr_line->bit_idx)), + data->reset_us); + } + + return 0; +} + +static int stm32_reset_assert(struct reset_ctl *reset_ctl) +{ + return stm32_reset_update(reset_ctl, true); +} + +static int stm32_reset_deassert(struct reset_ctl *reset_ctl) +{ + return stm32_reset_update(reset_ctl, false); +} + +const struct reset_ops stm32_reset_ops = { + .rst_assert = stm32_reset_assert, + .rst_deassert = stm32_reset_deassert, +}; + +int stm32_reset_core_probe(struct udevice *dev, + const struct stm32_reset_data *data) +{ + struct stm32_reset_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) { + /* for MFD, get address of parent */ + priv->base = dev_read_addr(dev->parent); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + } + + priv->data = data; + + assert(priv->data); + + return 0; +} diff --git a/drivers/reset/stm32/stm32-reset-core.h b/drivers/reset/stm32/stm32-reset-core.h new file mode 100644 index 00000000000..25a1aa152cb --- /dev/null +++ b/drivers/reset/stm32/stm32-reset-core.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + * Author(s): Gabriel Fernandez, for STMicroelectronics. + */ + +#include + +struct stm32_reset_cfg { + u16 offset; + u8 bit_idx; + bool set_clr; + bool inverted; +}; + +struct stm32_reset_data { + const struct stm32_reset_cfg * (*get_reset_line)(struct reset_ctl *reset_ctl); + u32 clear_offset; + u32 reset_us; +}; + +struct stm32_reset_priv { + fdt_addr_t base; + struct stm32_reset_cfg reset_line; + const struct stm32_reset_data *data; +}; + +extern const struct reset_ops stm32_reset_ops; + +int stm32_reset_core_probe(struct udevice *dev, + const struct stm32_reset_data *data); diff --git a/drivers/reset/stm32/stm32-reset-mp1.c b/drivers/reset/stm32/stm32-reset-mp1.c new file mode 100644 index 00000000000..6863f6e64b7 --- /dev/null +++ b/drivers/reset/stm32/stm32-reset-mp1.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + */ + +#include +#include + +/* Reset clear offset for STM32MP RCC */ +#define RCC_CLR_OFFSET 0x4 + +/* Offset of register without set/clear management */ +#define RCC_MP_GCR_OFFSET 0x10C + +/* Timeout for deassert */ +#define STM32_DEASSERT_TIMEOUT_US 10000 + +static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_ctl *reset_ctl) +{ + struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev); + struct stm32_reset_cfg *ptr_line = &priv->reset_line; + int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4; + int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE); + + ptr_line->offset = bank; + ptr_line->bit_idx = offset; + ptr_line->set_clr = true; + + if (ptr_line->offset == RCC_MP_GCR_OFFSET) { + ptr_line->set_clr = false; + ptr_line->inverted = true; + } + + return ptr_line; +} + +static const struct stm32_reset_data stm32mp1_reset_data = { + .get_reset_line = stm32_get_reset_line, + .clear_offset = RCC_CLR_OFFSET, + .reset_us = STM32_DEASSERT_TIMEOUT_US, +}; + +static int stm32_reset_probe(struct udevice *dev) +{ + return stm32_reset_core_probe(dev, &stm32mp1_reset_data); +} + +U_BOOT_DRIVER(stm32mp25_rcc_reset) = { + .name = "stm32mp1_reset", + .id = UCLASS_RESET, + .probe = stm32_reset_probe, + .priv_auto = sizeof(struct stm32_reset_priv), + .ops = &stm32_reset_ops, +}; diff --git a/drivers/reset/stm32/stm32-reset-mp25.c b/drivers/reset/stm32/stm32-reset-mp25.c new file mode 100644 index 00000000000..91c0336bc58 --- /dev/null +++ b/drivers/reset/stm32/stm32-reset-mp25.c @@ -0,0 +1,159 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2024, STMicroelectronics - All Rights Reserved + * Author(s): Gabriel Fernandez, for STMicroelectronics. + */ + +#include +#include +#include +#include + +/* Reset clear offset for STM32MP RCC */ +#define RCC_CLR_OFFSET 0x4 + +/* Timeout for deassert */ +#define STM32_DEASSERT_TIMEOUT_US 10000 + +#define RESET(id, _offset, _bit_idx, _set_clr) \ + [id] = &(struct stm32_reset_cfg){ \ + .offset = (_offset), \ + .bit_idx = (_bit_idx), \ + .set_clr = (_set_clr), \ + } + +static const struct stm32_reset_cfg *stm32mp25_reset[STM32MP25_LAST_RESET] = { + RESET(TIM1_R, RCC_TIM1CFGR, 0, 0), + RESET(TIM2_R, RCC_TIM2CFGR, 0, 0), + RESET(TIM3_R, RCC_TIM3CFGR, 0, 0), + RESET(TIM4_R, RCC_TIM4CFGR, 0, 0), + RESET(TIM5_R, RCC_TIM5CFGR, 0, 0), + RESET(TIM6_R, RCC_TIM6CFGR, 0, 0), + RESET(TIM7_R, RCC_TIM7CFGR, 0, 0), + RESET(TIM8_R, RCC_TIM8CFGR, 0, 0), + RESET(TIM10_R, RCC_TIM10CFGR, 0, 0), + RESET(TIM11_R, RCC_TIM11CFGR, 0, 0), + RESET(TIM12_R, RCC_TIM12CFGR, 0, 0), + RESET(TIM13_R, RCC_TIM13CFGR, 0, 0), + RESET(TIM14_R, RCC_TIM14CFGR, 0, 0), + RESET(TIM15_R, RCC_TIM15CFGR, 0, 0), + RESET(TIM16_R, RCC_TIM16CFGR, 0, 0), + RESET(TIM17_R, RCC_TIM17CFGR, 0, 0), + RESET(TIM20_R, RCC_TIM20CFGR, 0, 0), + RESET(LPTIM1_R, RCC_LPTIM1CFGR, 0, 0), + RESET(LPTIM2_R, RCC_LPTIM2CFGR, 0, 0), + RESET(LPTIM3_R, RCC_LPTIM3CFGR, 0, 0), + RESET(LPTIM4_R, RCC_LPTIM4CFGR, 0, 0), + RESET(LPTIM5_R, RCC_LPTIM5CFGR, 0, 0), + RESET(SPI1_R, RCC_SPI1CFGR, 0, 0), + RESET(SPI2_R, RCC_SPI2CFGR, 0, 0), + RESET(SPI3_R, RCC_SPI3CFGR, 0, 0), + RESET(SPI4_R, RCC_SPI4CFGR, 0, 0), + RESET(SPI5_R, RCC_SPI5CFGR, 0, 0), + RESET(SPI6_R, RCC_SPI6CFGR, 0, 0), + RESET(SPI7_R, RCC_SPI7CFGR, 0, 0), + RESET(SPI8_R, RCC_SPI8CFGR, 0, 0), + RESET(SPDIFRX_R, RCC_SPDIFRXCFGR, 0, 0), + RESET(USART1_R, RCC_USART1CFGR, 0, 0), + RESET(USART2_R, RCC_USART2CFGR, 0, 0), + RESET(USART3_R, RCC_USART3CFGR, 0, 0), + RESET(UART4_R, RCC_UART4CFGR, 0, 0), + RESET(UART5_R, RCC_UART5CFGR, 0, 0), + RESET(USART6_R, RCC_USART6CFGR, 0, 0), + RESET(UART7_R, RCC_UART7CFGR, 0, 0), + RESET(UART8_R, RCC_UART8CFGR, 0, 0), + RESET(UART9_R, RCC_UART9CFGR, 0, 0), + RESET(LPUART1_R, RCC_LPUART1CFGR, 0, 0), + RESET(IS2M_R, RCC_IS2MCFGR, 0, 0), + RESET(I2C1_R, RCC_I2C1CFGR, 0, 0), + RESET(I2C2_R, RCC_I2C2CFGR, 0, 0), + RESET(I2C3_R, RCC_I2C3CFGR, 0, 0), + RESET(I2C4_R, RCC_I2C4CFGR, 0, 0), + RESET(I2C5_R, RCC_I2C5CFGR, 0, 0), + RESET(I2C6_R, RCC_I2C6CFGR, 0, 0), + RESET(I2C7_R, RCC_I2C7CFGR, 0, 0), + RESET(I2C8_R, RCC_I2C8CFGR, 0, 0), + RESET(SAI1_R, RCC_SAI1CFGR, 0, 0), + RESET(SAI2_R, RCC_SAI2CFGR, 0, 0), + RESET(SAI3_R, RCC_SAI3CFGR, 0, 0), + RESET(SAI4_R, RCC_SAI4CFGR, 0, 0), + RESET(MDF1_R, RCC_MDF1CFGR, 0, 0), + RESET(MDF2_R, RCC_ADF1CFGR, 0, 0), + RESET(FDCAN_R, RCC_FDCANCFGR, 0, 0), + RESET(HDP_R, RCC_HDPCFGR, 0, 0), + RESET(ADC12_R, RCC_ADC12CFGR, 0, 0), + RESET(ADC3_R, RCC_ADC3CFGR, 0, 0), + RESET(ETH1_R, RCC_ETH1CFGR, 0, 0), + RESET(ETH2_R, RCC_ETH2CFGR, 0, 0), + RESET(USBH_R, RCC_USBHCFGR, 0, 0), + RESET(USB2PHY1_R, RCC_USB2PHY1CFGR, 0, 0), + RESET(USB2PHY2_R, RCC_USB2PHY2CFGR, 0, 0), + RESET(USB3DR_R, RCC_USB3DRCFGR, 0, 0), + RESET(USB3PCIEPHY_R, RCC_USB3PCIEPHYCFGR, 0, 0), + RESET(USBTC_R, RCC_UCPDCFGR, 0, 0), + RESET(ETHSW_R, RCC_ETHSWCFGR, 0, 0), + RESET(SDMMC1_R, RCC_SDMMC1CFGR, 0, 0), + RESET(SDMMC1DLL_R, RCC_SDMMC1CFGR, 16, 0), + RESET(SDMMC2_R, RCC_SDMMC2CFGR, 0, 0), + RESET(SDMMC2DLL_R, RCC_SDMMC2CFGR, 16, 0), + RESET(SDMMC3_R, RCC_SDMMC3CFGR, 0, 0), + RESET(SDMMC3DLL_R, RCC_SDMMC3CFGR, 16, 0), + RESET(GPU_R, RCC_GPUCFGR, 0, 0), + RESET(LTDC_R, RCC_LTDCCFGR, 0, 0), + RESET(DSI_R, RCC_DSICFGR, 0, 0), + RESET(LVDS_R, RCC_LVDSCFGR, 0, 0), + RESET(CSI_R, RCC_CSICFGR, 0, 0), + RESET(DCMIPP_R, RCC_DCMIPPCFGR, 0, 0), + RESET(CCI_R, RCC_CCICFGR, 0, 0), + RESET(VDEC_R, RCC_VDECCFGR, 0, 0), + RESET(VENC_R, RCC_VENCCFGR, 0, 0), + RESET(WWDG1_R, RCC_WWDG1CFGR, 0, 0), + RESET(WWDG2_R, RCC_WWDG2CFGR, 0, 0), + RESET(VREF_R, RCC_VREFCFGR, 0, 0), + RESET(DTS_R, RCC_DTSCFGR, 0, 0), + RESET(CRC_R, RCC_CRCCFGR, 0, 0), + RESET(SERC_R, RCC_SERCCFGR, 0, 0), + RESET(OSPIIOM_R, RCC_OSPIIOMCFGR, 0, 0), + RESET(I3C1_R, RCC_I3C1CFGR, 0, 0), + RESET(I3C2_R, RCC_I3C2CFGR, 0, 0), + RESET(I3C3_R, RCC_I3C3CFGR, 0, 0), + RESET(I3C4_R, RCC_I3C4CFGR, 0, 0), + RESET(IWDG2_KER_R, RCC_IWDGC1CFGSETR, 18, 1), + RESET(IWDG4_KER_R, RCC_IWDGC2CFGSETR, 18, 1), + RESET(RNG_R, RCC_RNGCFGR, 0, 0), + RESET(PKA_R, RCC_PKACFGR, 0, 0), + RESET(SAES_R, RCC_SAESCFGR, 0, 0), + RESET(HASH_R, RCC_HASHCFGR, 0, 0), + RESET(CRYP1_R, RCC_CRYP1CFGR, 0, 0), + RESET(CRYP2_R, RCC_CRYP2CFGR, 0, 0), + RESET(PCIE_R, RCC_PCIECFGR, 0, 0), +}; + +static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_ctl *reset_ctl) +{ + unsigned long id = reset_ctl->id; + + if (id < STM32MP25_LAST_RESET) + return stm32mp25_reset[id]; + + return NULL; +} + +static const struct stm32_reset_data stm32mp25_reset_data = { + .get_reset_line = stm32_get_reset_line, + .clear_offset = RCC_CLR_OFFSET, + .reset_us = STM32_DEASSERT_TIMEOUT_US, +}; + +static int stm32_reset_probe(struct udevice *dev) +{ + return stm32_reset_core_probe(dev, &stm32mp25_reset_data); +} + +U_BOOT_DRIVER(stm32mp25_rcc_reset) = { + .name = "stm32mp25_reset", + .id = UCLASS_RESET, + .probe = stm32_reset_probe, + .priv_auto = sizeof(struct stm32_reset_priv), + .ops = &stm32_reset_ops, +}; diff --git a/drivers/reset/stm32/stm32-reset.c b/drivers/reset/stm32/stm32-reset.c new file mode 100644 index 00000000000..975f67f712a --- /dev/null +++ b/drivers/reset/stm32/stm32-reset.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, for STMicroelectronics. + */ + +#include +#include + +/* Timeout for deassert */ +#define STM32_DEASSERT_TIMEOUT_US 10000 + +static const struct stm32_reset_cfg *stm32_get_reset_line(struct reset_ctl *reset_ctl) +{ + struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev); + struct stm32_reset_cfg *ptr_line = &priv->reset_line; + int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4; + int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE); + + ptr_line->offset = bank; + ptr_line->bit_idx = offset; + ptr_line->set_clr = true; + + return ptr_line; +} + +static const struct stm32_reset_data stm32_reset_data = { + .get_reset_line = stm32_get_reset_line, + .reset_us = STM32_DEASSERT_TIMEOUT_US, +}; + +static int stm32_reset_probe(struct udevice *dev) +{ + return stm32_reset_core_probe(dev, &stm32_reset_data); +} + +U_BOOT_DRIVER(stm32_rcc_reset) = { + .name = "stm32_rcc_reset", + .id = UCLASS_RESET, + .probe = stm32_reset_probe, + .priv_auto = sizeof(struct stm32_reset_priv), + .ops = &stm32_reset_ops, +}; diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h index b559ea77281..447a555dcf5 100644 --- a/include/stm32_rcc.h +++ b/include/stm32_rcc.h @@ -39,11 +39,11 @@ struct stm32_clk_info { bool v2; }; +/* platdata used for clk-stm32f.c driver */ enum soc_family { STM32F42X, STM32F469, STM32F7, - STM32MP1, }; enum apb { @@ -51,8 +51,9 @@ enum apb { APB2, }; -struct stm32_rcc_clk { - char *drv_name; +struct stm32_rcc { + char *drv_name_clk; + char *drv_name_rst; enum soc_family soc; }; -- cgit v1.3.1 From 0298696b1efcbaf05317e5559bdc99cbac36293c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 12 May 2025 19:08:29 +0200 Subject: clk: stm32mp13: Add SPL support and clock tree init to STM32MP13 RCC driver Add SPL support and clock tree init to STM32MP13 RCC driver. This consists of two parts, make SCMI into an optional dependency and add clock tree initialization. The SCMI dependency is made optional first by registering the few core clock provided by SCMI clock as fixed clock, and second by letting the clock core parse out the clock configuration from SoC registers. The clock initialization code is derived from STM32MP15xx clock tree initialization code, which is almost identical, except for the use of new PLL2000 for PLL1 on STM32MP13xx . Signed-off-by: Marek Vasut --- drivers/clk/stm32/clk-stm32-core.h | 1 + drivers/clk/stm32/clk-stm32mp13.c | 1303 +++++++++++++++++++++++++- drivers/clk/stm32/stm32mp13_rcc.h | 93 ++ include/dt-bindings/clock/stm32mp13-clksrc.h | 399 ++++++++ 4 files changed, 1744 insertions(+), 52 deletions(-) create mode 100644 include/dt-bindings/clock/stm32mp13-clksrc.h (limited to 'include') diff --git a/drivers/clk/stm32/clk-stm32-core.h b/drivers/clk/stm32/clk-stm32-core.h index c13204260a9..baf2a996ef3 100644 --- a/drivers/clk/stm32/clk-stm32-core.h +++ b/drivers/clk/stm32/clk-stm32-core.h @@ -144,6 +144,7 @@ struct stm32mp_rcc_priv { void __iomem *base; u8 *gate_cpt; const struct clk_stm32_clock_data *data; + struct clk osc_clk[6]; }; int stm32_rcc_init(struct udevice *dev, diff --git a/drivers/clk/stm32/clk-stm32mp13.c b/drivers/clk/stm32/clk-stm32mp13.c index 50af69dba6a..b4d0890f902 100644 --- a/drivers/clk/stm32/clk-stm32mp13.c +++ b/drivers/clk/stm32/clk-stm32mp13.c @@ -3,7 +3,6 @@ * Copyright (C) 2022, STMicroelectronics - All Rights Reserved * Author: Gabriel Fernandez for STMicroelectronics. */ - #define LOG_CATEGORY UCLASS_CLK #include @@ -12,6 +11,22 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include "clk-stm32-core.h" #include "stm32mp13_rcc.h" @@ -130,46 +145,6 @@ static const char * const usbphy_src[] = { "ck_hse", "pll4_r", "clk-hse-div2" }; -enum enum_mux_cfg { - MUX_I2C12, - MUX_LPTIM45, - MUX_SPI23, - MUX_UART35, - MUX_UART78, - MUX_ADC1, - MUX_ADC2, - MUX_DCMIPP, - MUX_ETH1, - MUX_ETH2, - MUX_FDCAN, - MUX_FMC, - MUX_I2C3, - MUX_I2C4, - MUX_I2C5, - MUX_LPTIM1, - MUX_LPTIM2, - MUX_LPTIM3, - MUX_QSPI, - MUX_RNG1, - MUX_SAES, - MUX_SAI1, - MUX_SAI2, - MUX_SDMMC1, - MUX_SDMMC2, - MUX_SPDIF, - MUX_SPI1, - MUX_SPI4, - MUX_SPI5, - MUX_STGEN, - MUX_UART1, - MUX_UART2, - MUX_UART4, - MUX_UART6, - MUX_USBO, - MUX_USBPHY, - MUX_MCO1, - MUX_MCO2 -}; #define MUX_CFG(id, src, _offset, _shift, _witdh) \ [id] = { \ @@ -471,15 +446,6 @@ static const struct clk_div_table ck_trace_div_table[] = { { 0 }, }; -enum enum_div_cfg { - DIV_MCO1, - DIV_MCO2, - DIV_TRACE, - DIV_ETH1PTP, - DIV_ETH2PTP, - LAST_DIV -}; - #define DIV_CFG(id, _offset, _shift, _width, _flags, _table) \ [id] = { \ .reg_off = _offset, \ @@ -489,7 +455,7 @@ enum enum_div_cfg { .table = _table, \ } -static const struct stm32_div_cfg stm32mp13_dividers[LAST_DIV] = { +static const struct stm32_div_cfg stm32mp13_dividers[] = { DIV_CFG(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL), DIV_CFG(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL), DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table), @@ -566,6 +532,7 @@ enum securit_clk { .bit_idx = _bit_idx, \ } +#ifdef CONFIG_TFABOOT static const struct clk_stm32_security stm32mp13_security[] = { SECF(SECF_LPTIM2, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM2SECF), SECF(SECF_LPTIM3, RCC_APB3SECSR, RCC_APB3SECSR_LPTIM3SECF), @@ -622,6 +589,7 @@ static const struct clk_stm32_security stm32mp13_security[] = { SECF(SECF_MCO1, RCC_SECCFGR, RCC_SECCFGR_MCO1SECF), SECF(SECF_MCO2, RCC_SECCFGR, RCC_SECCFGR_MCO2SECF), }; +#endif #define PCLK(_id, _name, _parent, _flags, _gate_id, _sec_id) \ STM32_GATE(_id, _name, _parent, _flags, _gate_id, _sec_id) @@ -635,6 +603,7 @@ static const struct clk_stm32_security stm32mp13_security[] = { _gate_id, _mux_id, NO_STM32_DIV) static const struct clock_config stm32mp13_clock_cfg[] = { +#ifndef CONFIG_XPL_BUILD TIMER(TIM2_K, "tim2_k", "timg1_ck", 0, GATE_TIM2, SECF_NONE), TIMER(TIM3_K, "tim3_k", "timg1_ck", 0, GATE_TIM3, SECF_NONE), TIMER(TIM4_K, "tim4_k", "timg1_ck", 0, GATE_TIM4, SECF_NONE), @@ -649,23 +618,28 @@ static const struct clock_config stm32mp13_clock_cfg[] = { TIMER(TIM15_K, "tim15_k", "timg3_ck", 0, GATE_TIM15, SECF_TIM15), TIMER(TIM16_K, "tim16_k", "timg3_ck", 0, GATE_TIM16, SECF_TIM16), TIMER(TIM17_K, "tim17_k", "timg3_ck", 0, GATE_TIM17, SECF_TIM17), +#endif /* Peripheral clocks */ PCLK(SYSCFG, "syscfg", "pclk3", 0, GATE_SYSCFG, SECF_NONE), PCLK(VREF, "vref", "pclk3", 0, GATE_VREF, SECF_VREF), +#ifndef CONFIG_XPL_BUILD PCLK(PMBCTRL, "pmbctrl", "pclk3", 0, GATE_PMBCTRL, SECF_NONE), PCLK(HDP, "hdp", "pclk3", 0, GATE_HDP, SECF_NONE), +#endif PCLK(IWDG2, "iwdg2", "pclk4", 0, GATE_IWDG2APB, SECF_NONE), PCLK(STGENRO, "stgenro", "pclk4", 0, GATE_STGENRO, SECF_STGENRO), PCLK(TZPC, "tzpc", "pclk5", 0, GATE_TZC, SECF_TZC), PCLK(IWDG1, "iwdg1", "pclk5", 0, GATE_IWDG1APB, SECF_IWDG1), PCLK(BSEC, "bsec", "pclk5", 0, GATE_BSEC, SECF_BSEC), +#ifndef CONFIG_XPL_BUILD PCLK(DMA1, "dma1", "ck_mlahb", 0, GATE_DMA1, SECF_NONE), PCLK(DMA2, "dma2", "ck_mlahb", 0, GATE_DMA2, SECF_NONE), PCLK(DMAMUX1, "dmamux1", "ck_mlahb", 0, GATE_DMAMUX1, SECF_NONE), PCLK(DMAMUX2, "dmamux2", "ck_mlahb", 0, GATE_DMAMUX2, SECF_DMAMUX2), PCLK(ADC1, "adc1", "ck_mlahb", 0, GATE_ADC1, SECF_ADC1), PCLK(ADC2, "adc2", "ck_mlahb", 0, GATE_ADC2, SECF_ADC2), +#endif PCLK(GPIOA, "gpioa", "pclk4", 0, GATE_GPIOA, SECF_NONE), PCLK(GPIOB, "gpiob", "pclk4", 0, GATE_GPIOB, SECF_NONE), PCLK(GPIOC, "gpioc", "pclk4", 0, GATE_GPIOC, SECF_NONE), @@ -681,17 +655,23 @@ static const struct clock_config stm32mp13_clock_cfg[] = { PCLK(HASH1, "hash1", "ck_axi", 0, GATE_HASH1, SECF_HASH1), PCLK(BKPSRAM, "bkpsram", "ck_axi", 0, GATE_BKPSRAM, SECF_BKPSRAM), PCLK(MDMA, "mdma", "ck_axi", 0, GATE_MDMA, SECF_NONE), +#ifndef CONFIG_XPL_BUILD PCLK(ETH1TX, "eth1tx", "ck_axi", 0, GATE_ETH1TX, SECF_ETH1TX), PCLK(ETH1RX, "eth1rx", "ck_axi", 0, GATE_ETH1RX, SECF_ETH1RX), PCLK(ETH1MAC, "eth1mac", "ck_axi", 0, GATE_ETH1MAC, SECF_ETH1MAC), PCLK(ETH2TX, "eth2tx", "ck_axi", 0, GATE_ETH2TX, SECF_ETH2TX), PCLK(ETH2RX, "eth2rx", "ck_axi", 0, GATE_ETH2RX, SECF_ETH2RX), PCLK(ETH2MAC, "eth2mac", "ck_axi", 0, GATE_ETH2MAC, SECF_ETH2MAC), +#endif PCLK(CRC1, "crc1", "ck_axi", 0, GATE_CRC1, SECF_NONE), +#ifndef CONFIG_XPL_BUILD PCLK(USBH, "usbh", "ck_axi", 0, GATE_USBH, SECF_NONE), +#endif PCLK(DDRPERFM, "ddrperfm", "pclk4", 0, GATE_DDRPERFM, SECF_NONE), +#ifndef CONFIG_XPL_BUILD PCLK(ETH1STP, "eth1stp", "ck_axi", 0, GATE_ETH1STP, SECF_ETH1STP), PCLK(ETH2STP, "eth2stp", "ck_axi", 0, GATE_ETH2STP, SECF_ETH2STP), +#endif /* Kernel clocks */ KCLK(SDMMC1_K, "sdmmc1_k", 0, GATE_SDMMC1, MUX_SDMMC1, SECF_SDMMC1), @@ -702,8 +682,10 @@ static const struct clock_config stm32mp13_clock_cfg[] = { KCLK(SPI3_K, "spi3_k", 0, GATE_SPI3, MUX_SPI23, SECF_NONE), KCLK(I2C1_K, "i2c1_k", 0, GATE_I2C1, MUX_I2C12, SECF_NONE), KCLK(I2C2_K, "i2c2_k", 0, GATE_I2C2, MUX_I2C12, SECF_NONE), +#ifndef CONFIG_XPL_BUILD KCLK(LPTIM4_K, "lptim4_k", 0, GATE_LPTIM4, MUX_LPTIM45, SECF_NONE), KCLK(LPTIM5_K, "lptim5_k", 0, GATE_LPTIM5, MUX_LPTIM45, SECF_NONE), +#endif KCLK(USART3_K, "usart3_k", 0, GATE_USART3, MUX_UART35, SECF_NONE), KCLK(UART5_K, "uart5_k", 0, GATE_UART5, MUX_UART35, SECF_NONE), KCLK(UART7_K, "uart7_k", 0, GATE_UART7, MUX_UART78, SECF_NONE), @@ -711,20 +693,29 @@ static const struct clock_config stm32mp13_clock_cfg[] = { KCLK(RNG1_K, "rng1_k", 0, GATE_RNG1, MUX_RNG1, SECF_RNG1), KCLK(USBPHY_K, "usbphy_k", 0, GATE_USBPHY, MUX_USBPHY, SECF_USBPHY), KCLK(STGEN_K, "stgen_k", 0, GATE_STGENC, MUX_STGEN, SECF_STGENC), +#ifndef CONFIG_XPL_BUILD KCLK(SPDIF_K, "spdif_k", 0, GATE_SPDIF, MUX_SPDIF, SECF_NONE), +#endif KCLK(SPI1_K, "spi1_k", 0, GATE_SPI1, MUX_SPI1, SECF_NONE), KCLK(SPI4_K, "spi4_k", 0, GATE_SPI4, MUX_SPI4, SECF_SPI4), KCLK(SPI5_K, "spi5_k", 0, GATE_SPI5, MUX_SPI5, SECF_SPI5), +#ifdef CONFIG_TFABOOT KCLK(I2C3_K, "i2c3_k", 0, GATE_I2C3, MUX_I2C3, SECF_I2C3), +#else + KCLK(I2C3_K, "i2c3_k", 0, GATE_I2C3, MUX_I2C3, SECF_NONE), +#endif KCLK(I2C4_K, "i2c4_k", 0, GATE_I2C4, MUX_I2C4, SECF_I2C4), KCLK(I2C5_K, "i2c5_k", 0, GATE_I2C5, MUX_I2C5, SECF_I2C5), +#ifndef CONFIG_XPL_BUILD KCLK(LPTIM1_K, "lptim1_k", 0, GATE_LPTIM1, MUX_LPTIM1, SECF_NONE), KCLK(LPTIM2_K, "lptim2_k", 0, GATE_LPTIM2, MUX_LPTIM2, SECF_LPTIM2), KCLK(LPTIM3_K, "lptim3_k", 0, GATE_LPTIM3, MUX_LPTIM3, SECF_LPTIM3), +#endif KCLK(USART1_K, "usart1_k", 0, GATE_USART1, MUX_UART1, SECF_USART1), KCLK(USART2_K, "usart2_k", 0, GATE_USART2, MUX_UART2, SECF_USART2), KCLK(UART4_K, "uart4_k", 0, GATE_UART4, MUX_UART4, SECF_NONE), KCLK(USART6_K, "uart6_k", 0, GATE_USART6, MUX_UART6, SECF_NONE), +#ifndef CONFIG_XPL_BUILD KCLK(FDCAN_K, "fdcan_k", 0, GATE_FDCAN, MUX_FDCAN, SECF_NONE), KCLK(SAI1_K, "sai1_k", 0, GATE_SAI1, MUX_SAI1, SECF_NONE), KCLK(SAI2_K, "sai2_k", 0, GATE_SAI2, MUX_SAI2, SECF_NONE), @@ -732,7 +723,9 @@ static const struct clock_config stm32mp13_clock_cfg[] = { KCLK(ADC2_K, "adc2_k", 0, GATE_ADC2, MUX_ADC2, SECF_ADC2), KCLK(DCMIPP_K, "dcmipp_k", 0, GATE_DCMIPP, MUX_DCMIPP, SECF_DCMIPP), KCLK(ADFSDM_K, "adfsdm_k", 0, GATE_ADFSDM, MUX_SAI1, SECF_NONE), +#endif KCLK(USBO_K, "usbo_k", 0, GATE_USBO, MUX_USBO, SECF_USBO), +#ifndef CONFIG_XPL_BUILD KCLK(ETH1CK_K, "eth1ck_k", 0, GATE_ETH1CK, MUX_ETH1, SECF_ETH1CK), KCLK(ETH2CK_K, "eth2ck_k", 0, GATE_ETH2CK, MUX_ETH2, SECF_ETH2CK), KCLK(SAES_K, "saes_k", 0, GATE_SAES, MUX_SAES, SECF_SAES), @@ -742,6 +735,7 @@ static const struct clock_config stm32mp13_clock_cfg[] = { GATE_LTDC, SECF_NONE), STM32_GATE(DTS_K, "dts_k", "ck_lse", 0, GATE_DTS, SECF_NONE), +#endif STM32_COMPOSITE(ETH1PTP_K, "eth1ptp_k", CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT, SECF_ETH1CK, @@ -767,8 +761,22 @@ static const struct clock_config stm32mp13_clock_cfg[] = { STM32_COMPOSITE_NOMUX(CK_TRACE, "ck_trace", "ck_axi", CLK_OPS_PARENT_ENABLE, SECF_NONE, GATE_TRACECK, DIV_TRACE), + +#ifdef CONFIG_XPL_BUILD + STM32_GATE(AXIDCG, "axidcg", "ck_axi", CLK_IGNORE_UNUSED, + GATE_AXIDCG, SECF_NONE), + STM32_GATE(DDRC1, "ddrc1", "ck_axi", CLK_IGNORE_UNUSED, + GATE_DDRC1, SECF_NONE), + STM32_GATE(DDRPHYC, "ddrphyc", "pll2_r", CLK_IGNORE_UNUSED, + GATE_DDRPHYC, SECF_NONE), + STM32_GATE(DDRCAPB, "ddrcapb", "pclk4", CLK_IGNORE_UNUSED, + GATE_DDRCAPB, SECF_NONE), + STM32_GATE(DDRPHYCAPB, "ddrphycapb", "pclk4", CLK_IGNORE_UNUSED, + GATE_DDRPHYCAPB, SECF_NONE), +#endif }; +#ifdef CONFIG_TFABOOT static int stm32mp13_check_security(struct udevice *dev, void __iomem *base, const struct clock_config *cfg) { @@ -784,6 +792,7 @@ static int stm32mp13_check_security(struct udevice *dev, void __iomem *base, return secured; } +#endif static const struct stm32_clock_match_data stm32mp13_data = { .tab_clocks = stm32mp13_clock_cfg, @@ -794,16 +803,1204 @@ static const struct stm32_clock_match_data stm32mp13_data = { .muxes = stm32mp13_muxes, .dividers = stm32mp13_dividers, }, +#ifdef CONFIG_TFABOOT .check_security = stm32mp13_check_security, +#endif +}; + +#ifndef CONFIG_TFABOOT + +enum stm32mp1_parent_id { +/* + * _HSI, _HSE, _CSI, _LSI, _LSE should not be moved + * they are used as index in osc_clk[] as clock reference + */ + _HSI, + _HSE, + _CSI, + _LSI, + _LSE, + _I2S_CKIN, + NB_OSC, + +/* other parent source */ + _HSI_KER = NB_OSC, + _HSE_KER, + _HSE_KER_DIV2, + _CSI_KER, + _PLL1_P, + _PLL1_Q, + _PLL1_R, + _PLL2_P, + _PLL2_Q, + _PLL2_R, + _PLL3_P, + _PLL3_Q, + _PLL3_R, + _PLL4_P, + _PLL4_Q, + _PLL4_R, + _ACLK, + _PCLK1, + _PCLK2, + _PCLK3, + _PCLK4, + _PCLK5, + _HCLK6, + _HCLK2, + _CK_PER, + _CK_MPU, + _CK_MCU, + _DSI_PHY, + _USB_PHY_48, + _PARENT_NB, + _UNKNOWN_ID = 0xff, +}; + +#if defined(CONFIG_XPL_BUILD) + +#define MAX_HSI_HZ 64000000 + +/* TIMEOUT */ +#define TIMEOUT_200MS 200000 +#define TIMEOUT_1S 1000000 + +/* STGEN registers */ +#define STGENC_CNTCR 0x00 +#define STGENC_CNTSR 0x04 +#define STGENC_CNTCVL 0x08 +#define STGENC_CNTCVU 0x0C +#define STGENC_CNTFID0 0x20 + +#define STGENC_CNTCR_EN BIT(0) + +enum stm32mp1_clksrc_id { + CLKSRC_MPU, + CLKSRC_AXI, + CLKSRC_MLAHB, + CLKSRC_PLL12, + CLKSRC_PLL3, + CLKSRC_PLL4, + CLKSRC_RTC, + CLKSRC_MCO1, + CLKSRC_MCO2, + CLKSRC_NB +}; + +enum stm32mp1_clkdiv_id { + CLKDIV_AXI, + CLKDIV_MLAHB, + CLKDIV_APB1, + CLKDIV_APB2, + CLKDIV_APB3, + CLKDIV_APB4, + CLKDIV_APB5, + CLKDIV_APB6, + CLKDIV_RTC, + CLKDIV_NB +}; + +enum stm32mp1_pll_id { + _PLL1, + _PLL2, + _PLL3, + _PLL4, + _PLL_NB +}; + +enum stm32mp1_div_id { + _DIV_P, + _DIV_Q, + _DIV_R, + _DIV_NB, +}; + +/* define characteristic of PLL according type */ +#define DIVM_MIN 1 +#define DIVM_MAX 63 +#define DIVN_MIN 24 +#define DIVP_MIN 0 +#define DIVP_MAX 127 +#define FRAC_MAX 8192 + +#define PLL2000_VCO_MIN 992000000 +#define PLL2000_VCO_MAX 2000000000 + +enum stm32mp1_pllcfg { + PLLCFG_M, + PLLCFG_N, + PLLCFG_P, + PLLCFG_Q, + PLLCFG_R, + PLLCFG_O, + PLLCFG_NB +}; + +enum stm32mp1_pllcsg { + PLLCSG_MOD_PER, + PLLCSG_INC_STEP, + PLLCSG_SSCG_MODE, + PLLCSG_NB +}; + +enum stm32mp1_plltype { + PLL_800, + PLL_1600, + PLL_2000, + PLL_TYPE_NB +}; + +struct stm32mp1_pll { + u8 refclk_min; + u8 refclk_max; + u8 divn_max; +}; + +#define REFCLK_SIZE 4 +struct stm32mp1_clk_pll { + enum stm32mp1_plltype plltype; + u16 rckxselr; + u16 pllxcfgr1; + u16 pllxcfgr2; + u16 pllxfracr; + u16 pllxcr; + u16 pllxcsgr; + u8 refclk[REFCLK_SIZE]; +}; + +static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { + [PLL_800] = { + .refclk_min = 4, + .refclk_max = 16, + .divn_max = 99, + }, + [PLL_1600] = { + .refclk_min = 8, + .refclk_max = 16, + .divn_max = 199, + }, + [PLL_2000] = { + .refclk_min = 8, + .refclk_max = 16, + .divn_max = 99, + }, +}; + +#define STM32MP1_CLK_PLL(idx, type, off1, off2, off3, off4, off5, off6,\ + p1, p2, p3, p4) \ + [(idx)] = { \ + .plltype = (type), \ + .rckxselr = (off1), \ + .pllxcfgr1 = (off2), \ + .pllxcfgr2 = (off3), \ + .pllxfracr = (off4), \ + .pllxcr = (off5), \ + .pllxcsgr = (off6), \ + .refclk[0] = (p1), \ + .refclk[1] = (p2), \ + .refclk[2] = (p3), \ + .refclk[3] = (p4), \ + } + +static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { + STM32MP1_CLK_PLL(_PLL1, PLL_2000, + RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, + RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, + _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID), + STM32MP1_CLK_PLL(_PLL2, PLL_1600, + RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, + RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, + _HSI, _HSE, _UNKNOWN_ID, _UNKNOWN_ID), + STM32MP1_CLK_PLL(_PLL3, PLL_800, + RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, + RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, + _HSI, _HSE, _CSI, _UNKNOWN_ID), + STM32MP1_CLK_PLL(_PLL4, PLL_800, + RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, + RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, + _HSI, _HSE, _CSI, _I2S_CKIN), }; +static ulong stm32mp1_clk_get_fixed(struct stm32mp_rcc_priv *priv, int idx) +{ + if (idx >= NB_OSC) { + log_debug("clk id %d not found\n", idx); + return 0; + } + + return clk_get_rate(&priv->osc_clk[idx]); +} + +bool stm32mp1_supports_opp(u32 opp_id, u32 cpu_type) +{ + /* 650 MHz is always supported */ + if (opp_id == 1) + return true; + + /* + * 1000 MHz is supported on STM32MP13xDxx and STM32MP13xFxx, + * which all have bit 11 i.e. 0x800 set in CPU ID. + */ + if (opp_id == 2) + return !!(cpu_type & BIT(11)); + + /* Any other OPP is invalid. */ + return false; +} + +__weak void board_vddcore_init(u32 voltage_mv) +{ +} + +/* + * gets OPP parameters (frequency in KHz and voltage in mV) from + * an OPP table subnode. Platform HW support capabilities are also checked. + * Returns 0 on success and a negative FDT error code on failure. + */ +static int stm32mp1_get_opp(u32 cpu_type, ofnode subnode, + u32 *freq_khz, u32 *voltage_mv) +{ + u32 opp_hw; + u64 read_freq_64; + u32 read_voltage_32; + + *freq_khz = 0; + *voltage_mv = 0; + + opp_hw = ofnode_read_u32_default(subnode, "opp-supported-hw", 0); + if (opp_hw) + if (!stm32mp1_supports_opp(opp_hw, cpu_type)) + return -FDT_ERR_BADVALUE; + + read_freq_64 = ofnode_read_u64_default(subnode, "opp-hz", 0) / + 1000ULL; + read_voltage_32 = ofnode_read_u32_default(subnode, "opp-microvolt", 0) / + 1000U; + + if (!read_voltage_32 || !read_freq_64) + return -FDT_ERR_NOTFOUND; + + /* Frequency value expressed in KHz must fit on 32 bits */ + if (read_freq_64 > U32_MAX) + return -FDT_ERR_BADVALUE; + + /* Millivolt value must fit on 16 bits */ + if (read_voltage_32 > U16_MAX) + return -FDT_ERR_BADVALUE; + + *freq_khz = (u32)read_freq_64; + *voltage_mv = read_voltage_32; + + return 0; +} + +/* + * parses OPP table in DT and finds the parameters for the + * highest frequency supported by the HW platform. + * Returns 0 on success and a negative FDT error code on failure. + */ +int stm32mp1_get_max_opp_freq(struct stm32mp_rcc_priv *priv, u64 *freq_hz) +{ + ofnode node, subnode; + int ret; + u32 freq = 0U, voltage = 0U; + u32 cpu_type = get_cpu_type(); + + node = ofnode_by_compatible(ofnode_null(), "operating-points-v2"); + if (!ofnode_valid(node)) + return -FDT_ERR_NOTFOUND; + + ofnode_for_each_subnode(subnode, node) { + unsigned int read_freq; + unsigned int read_voltage; + + ret = stm32mp1_get_opp(cpu_type, subnode, + &read_freq, &read_voltage); + if (ret) + continue; + + if (read_freq > freq) { + freq = read_freq; + voltage = read_voltage; + } + } + + if (!freq || !voltage) + return -FDT_ERR_NOTFOUND; + + *freq_hz = (u64)1000U * freq; + board_vddcore_init(voltage); + + return 0; +} + +static int stm32mp1_pll1_opp(struct stm32mp_rcc_priv *priv, int clksrc, + u32 *pllcfg, u32 *fracv) +{ + u32 post_divm; + u32 input_freq; + u64 output_freq; + u64 freq; + u64 vco; + u32 divm, divn, divp, frac; + int i, ret; + u32 diff; + u32 best_diff = U32_MAX; + + /* PLL1 is 2000 */ + const u32 DIVN_MAX = stm32mp1_pll[PLL_2000].divn_max; + const u32 POST_DIVM_MIN = stm32mp1_pll[PLL_2000].refclk_min * 1000000U; + const u32 POST_DIVM_MAX = stm32mp1_pll[PLL_2000].refclk_max * 1000000U; + + ret = stm32mp1_get_max_opp_freq(priv, &output_freq); + if (ret) { + log_debug("PLL1 OPP configuration not found (%d).\n", ret); + return ret; + } + + switch (clksrc) { + case CLK_PLL12_HSI: + input_freq = stm32mp1_clk_get_fixed(priv, _HSI); + break; + case CLK_PLL12_HSE: + input_freq = stm32mp1_clk_get_fixed(priv, _HSE); + break; + default: + return -EINTR; + } + + /* Following parameters have always the same value */ + pllcfg[PLLCFG_Q] = 0; + pllcfg[PLLCFG_R] = 0; + pllcfg[PLLCFG_O] = PQR(1, 1, 1); + + for (divm = DIVM_MAX; divm >= DIVM_MIN; divm--) { + post_divm = (u32)(input_freq / (divm + 1)); + if (post_divm < POST_DIVM_MIN || post_divm > POST_DIVM_MAX) + continue; + + for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) { + freq = output_freq * (divm + 1) * (divp + 1); + divn = (u32)((freq / input_freq) - 1); + if (divn < DIVN_MIN || divn > DIVN_MAX) + continue; + + frac = (u32)(((freq * FRAC_MAX) / input_freq) - + ((divn + 1) * FRAC_MAX)); + /* 2 loops to refine the fractional part */ + for (i = 2; i != 0; i--) { + if (frac > FRAC_MAX) + break; + + vco = (post_divm * (divn + 1)) + + ((post_divm * (u64)frac) / + FRAC_MAX); + if (vco < (PLL2000_VCO_MIN / 2) || + vco > (PLL2000_VCO_MAX / 2)) { + frac++; + continue; + } + freq = vco / (divp + 1); + if (output_freq < freq) + diff = (u32)(freq - output_freq); + else + diff = (u32)(output_freq - freq); + if (diff < best_diff) { + pllcfg[PLLCFG_M] = divm; + pllcfg[PLLCFG_N] = divn; + pllcfg[PLLCFG_P] = divp; + *fracv = frac; + + if (diff == 0) { + return 0; + } + + best_diff = diff; + } + frac++; + } + } + } + + if (best_diff == U32_MAX) + return -1; + + return 0; +} + +static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset, + u32 mask_on) +{ + u32 address = rcc + offset; + + if (enable) + setbits_le32(address, mask_on); + else + clrbits_le32(address, mask_on); +} + +static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on) +{ + writel(mask_on, rcc + (enable ? RCC_OCENSETR : RCC_OCENCLRR)); +} + +static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset, + u32 mask_rdy) +{ + u32 mask_test = 0; + u32 address = rcc + offset; + u32 val; + int ret; + + if (enable) + mask_test = mask_rdy; + + ret = readl_poll_timeout(address, val, + (val & mask_rdy) == mask_test, + TIMEOUT_1S); + + if (ret) + log_err("OSC %x @ %x timeout for enable=%d : 0x%x\n", + mask_rdy, address, enable, readl(address)); + + return ret; +} + +static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int digbyp, + u32 lsedrv) +{ + u32 value; + + if (digbyp) + setbits_le32(rcc + RCC_BDCR, RCC_BDCR_DIGBYP); + + if (bypass || digbyp) + setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP); + + /* + * warning: not recommended to switch directly from "high drive" + * to "medium low drive", and vice-versa. + */ + value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) + >> RCC_BDCR_LSEDRV_SHIFT; + + while (value != lsedrv) { + if (value > lsedrv) + value--; + else + value++; + + clrsetbits_le32(rcc + RCC_BDCR, + RCC_BDCR_LSEDRV_MASK, + value << RCC_BDCR_LSEDRV_SHIFT); + } + + stm32mp1_ls_osc_set(1, rcc, RCC_BDCR, RCC_BDCR_LSEON); +} + +static void stm32mp1_lse_wait(fdt_addr_t rcc) +{ + stm32mp1_osc_wait(1, rcc, RCC_BDCR, RCC_BDCR_LSERDY); +} + +static void stm32mp1_lsi_set(fdt_addr_t rcc, int enable) +{ + stm32mp1_ls_osc_set(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSION); + stm32mp1_osc_wait(enable, rcc, RCC_RDLSICR, RCC_RDLSICR_LSIRDY); +} + +static void stm32mp1_hse_enable(fdt_addr_t rcc, int bypass, int digbyp, int css) +{ + if (digbyp) + writel(RCC_OCENR_DIGBYP, rcc + RCC_OCENSETR); + if (bypass || digbyp) + writel(RCC_OCENR_HSEBYP, rcc + RCC_OCENSETR); + + stm32mp1_hs_ocs_set(1, rcc, RCC_OCENR_HSEON); + stm32mp1_osc_wait(1, rcc, RCC_OCRDYR, RCC_OCRDYR_HSERDY); + + if (css) + writel(RCC_OCENR_HSECSSON, rcc + RCC_OCENSETR); +} + +static void stm32mp1_csi_set(fdt_addr_t rcc, int enable) +{ + stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_CSION); + stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_CSIRDY); +} + +static void stm32mp1_hsi_set(fdt_addr_t rcc, int enable) +{ + stm32mp1_hs_ocs_set(enable, rcc, RCC_OCENR_HSION); + stm32mp1_osc_wait(enable, rcc, RCC_OCRDYR, RCC_OCRDYR_HSIRDY); +} + +static int stm32mp1_set_hsidiv(fdt_addr_t rcc, u8 hsidiv) +{ + u32 address = rcc + RCC_OCRDYR; + u32 val; + int ret; + + clrsetbits_le32(rcc + RCC_HSICFGR, + RCC_HSICFGR_HSIDIV_MASK, + RCC_HSICFGR_HSIDIV_MASK & hsidiv); + + ret = readl_poll_timeout(address, val, + val & RCC_OCRDYR_HSIDIVRDY, + TIMEOUT_200MS); + if (ret) + log_err("HSIDIV failed @ 0x%x: 0x%x\n", + address, readl(address)); + + return ret; +} + +static int stm32mp1_hsidiv(fdt_addr_t rcc, ulong hsifreq) +{ + u8 hsidiv; + u32 hsidivfreq = MAX_HSI_HZ; + + for (hsidiv = 0; hsidiv < 4; hsidiv++, + hsidivfreq = hsidivfreq / 2) + if (hsidivfreq == hsifreq) + break; + + if (hsidiv == 4) { + log_err("hsi frequency invalid"); + return -1; + } + + if (hsidiv > 0) + return stm32mp1_set_hsidiv(rcc, hsidiv); + + return 0; +} + +static void pll_start(struct stm32mp_rcc_priv *priv, int pll_id) +{ + clrsetbits_le32((u32)(priv->base) + stm32mp1_clk_pll[pll_id].pllxcr, + RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | + RCC_PLLNCR_DIVREN, + RCC_PLLNCR_PLLON); +} + +static int pll_output(struct stm32mp_rcc_priv *priv, int pll_id, int output) +{ + u32 pllxcr = (u32)(priv->base) + stm32mp1_clk_pll[pll_id].pllxcr; + u32 val; + int ret; + + ret = readl_poll_timeout(pllxcr, val, val & RCC_PLLNCR_PLLRDY, + TIMEOUT_200MS); + + if (ret) { + log_err("PLL%d start failed @ 0x%x: 0x%x\n", + pll_id, pllxcr, readl(pllxcr)); + return ret; + } + + /* start the requested output */ + setbits_le32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); + + return 0; +} + +static int pll_stop(struct stm32mp_rcc_priv *priv, int pll_id) +{ + u32 pllxcr = (u32)(priv->base) + stm32mp1_clk_pll[pll_id].pllxcr; + u32 val; + + /* stop all output */ + clrbits_le32(pllxcr, + RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); + + /* stop PLL */ + clrbits_le32(pllxcr, RCC_PLLNCR_PLLON); + + /* wait PLL stopped */ + return readl_poll_timeout(pllxcr, val, (val & RCC_PLLNCR_PLLRDY) == 0, + TIMEOUT_200MS); +} + +static void pll_config_output(struct stm32mp_rcc_priv *priv, + int pll_id, u32 *pllcfg) +{ + fdt_addr_t rcc = (u32)(priv->base); + u32 value; + + value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) + & RCC_PLLNCFGR2_DIVP_MASK; + value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) + & RCC_PLLNCFGR2_DIVQ_MASK; + value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) + & RCC_PLLNCFGR2_DIVR_MASK; + writel(value, rcc + stm32mp1_clk_pll[pll_id].pllxcfgr2); +} + +static int pll_config(struct stm32mp_rcc_priv *priv, int pll_id, + u32 *pllcfg, u32 fracv) +{ + fdt_addr_t rcc = (u32)(priv->base); + enum stm32mp1_plltype type = stm32mp1_clk_pll[pll_id].plltype; + int src; + ulong refclk; + u8 ifrge = 0; + u32 value; + + src = readl((u32)(priv->base) + stm32mp1_clk_pll[pll_id].rckxselr) & RCC_SELR_SRC_MASK; + refclk = stm32mp1_clk_get_fixed(priv, stm32mp1_clk_pll[pll_id].refclk[src]) / + (pllcfg[PLLCFG_M] + 1); + + if (refclk < (stm32mp1_pll[type].refclk_min * 1000000) || + refclk > (stm32mp1_pll[type].refclk_max * 1000000)) { + log_err("invalid refclk = %x\n", (u32)refclk); + return -EINVAL; + } + + + if (type == PLL_800 && refclk >= 8000000) + ifrge = 1; + + value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) + & RCC_PLLNCFGR1_DIVN_MASK; + value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) + & RCC_PLLNCFGR1_DIVM_MASK; + value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) + & RCC_PLLNCFGR1_IFRGE_MASK; + writel(value, rcc + stm32mp1_clk_pll[pll_id].pllxcfgr1); + + /* fractional configuration: load sigma-delta modulator (SDM) */ + + /* Write into FRACV the new fractional value , and FRACLE to 0 */ + writel(fracv << RCC_PLLNFRACR_FRACV_SHIFT, + rcc + stm32mp1_clk_pll[pll_id].pllxfracr); + + /* Write FRACLE to 1 : FRACV value is loaded into the SDM */ + setbits_le32(rcc + stm32mp1_clk_pll[pll_id].pllxfracr, + RCC_PLLNFRACR_FRACLE); + + pll_config_output(priv, pll_id, pllcfg); + + return 0; +} + +static void pll_csg(struct stm32mp_rcc_priv *priv, int pll_id, u32 *csg) +{ + u32 pllxcsg; + + pllxcsg = ((csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & + RCC_PLLNCSGR_MOD_PER_MASK) | + ((csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & + RCC_PLLNCSGR_INC_STEP_MASK) | + ((csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & + RCC_PLLNCSGR_SSCG_MODE_MASK); + + writel(pllxcsg, (u32)(priv->base) + stm32mp1_clk_pll[pll_id].pllxcsgr); + + setbits_le32((u32)(priv->base) + stm32mp1_clk_pll[pll_id].pllxcr, RCC_PLLNCR_SSCG_CTRL); +} + +static ulong pll_get_fref_ck(struct stm32mp_rcc_priv *priv, + int pll_id) +{ + u32 selr; + int src; + + /* Get current refclk */ + selr = readl(priv->base + stm32mp1_clk_pll[pll_id].rckxselr); + src = selr & RCC_SELR_SRC_MASK; + + return stm32mp1_clk_get_fixed(priv, stm32mp1_clk_pll[pll_id].refclk[src]); +} + +static __maybe_unused int pll_set_rate(struct udevice *dev, + int pll_id, + int div_id, + unsigned long clk_rate) +{ + struct stm32mp_rcc_priv *priv = dev_get_priv(dev); + unsigned int pllcfg[PLLCFG_NB]; + ofnode plloff; + char name[12]; + enum stm32mp1_plltype type = stm32mp1_clk_pll[pll_id].plltype; + int divm, divn, divy; + int ret; + ulong fck_ref; + u32 fracv; + u64 value; + + if (div_id > _DIV_NB) + return -EINVAL; + + sprintf(name, "st,pll@%d", pll_id); + plloff = dev_read_subnode(dev, name); + if (!ofnode_valid(plloff)) + return -FDT_ERR_NOTFOUND; + + ret = ofnode_read_u32_array(plloff, "cfg", + pllcfg, PLLCFG_NB); + if (ret < 0) + return -FDT_ERR_NOTFOUND; + + fck_ref = pll_get_fref_ck(priv, pll_id); + + divm = pllcfg[PLLCFG_M]; + /* select output divider = 0: for _DIV_P, 1:_DIV_Q 2:_DIV_R */ + divy = pllcfg[PLLCFG_P + div_id]; + + /* For: PLL1 & PLL2 => VCO is * 2 but ck_pll_y is also / 2 + * So same final result than PLL2 et 4 + * with FRACV + * Fck_pll_y = Fck_ref * ((DIVN + 1) + FRACV / 2^13) + * / (DIVy + 1) * (DIVM + 1) + * value = (DIVN + 1) * 2^13 + FRACV / 2^13 + * = Fck_pll_y (DIVy + 1) * (DIVM + 1) * 2^13 / Fck_ref + */ + value = ((u64)clk_rate * (divy + 1) * (divm + 1)) << 13; + value = lldiv(value, fck_ref); + + divn = (value >> 13) - 1; + if (divn < DIVN_MIN || + divn > stm32mp1_pll[type].divn_max) { + dev_err(dev, "divn invalid = %d", divn); + return -EINVAL; + } + fracv = value - ((divn + 1) << 13); + pllcfg[PLLCFG_N] = divn; + + /* reconfigure PLL */ + pll_stop(priv, pll_id); + pll_config(priv, pll_id, pllcfg, fracv); + pll_start(priv, pll_id); + pll_output(priv, pll_id, pllcfg[PLLCFG_O]); + + return 0; +} + +static int set_clksrc(struct stm32mp_rcc_priv *priv, unsigned int clksrc) +{ + u32 address = (u32)(priv->base); + u32 mux = (clksrc & MUX_ID_MASK) >> MUX_ID_SHIFT; + u32 val; + int ret; + + /* List of relevant muxes to keep the size down */ + if (mux == MUX_PLL12) + address += RCC_RCK12SELR; + else if (mux == MUX_PLL3) + address += RCC_RCK3SELR; + else if (mux == MUX_PLL4) + address += RCC_RCK4SELR; + else if (mux == MUX_MPU) + address += RCC_MPCKSELR; + else if (mux == MUX_AXI) + address += RCC_ASSCKSELR; + else if (mux == MUX_MLAHB) + address += RCC_MSSCKSELR; + else if (mux == MUX_CKPER) + address += RCC_CPERCKSELR; + else + return -EINVAL; + + clrsetbits_le32(address, RCC_SELR_SRC_MASK, clksrc & RCC_SELR_SRC_MASK); + ret = readl_poll_timeout(address, val, val & RCC_SELR_SRCRDY, + TIMEOUT_200MS); + if (ret) + log_err("CLKSRC %x start failed @ 0x%x: 0x%x\n", + clksrc, address, readl(address)); + + return ret; +} + +static void stgen_config(struct stm32mp_rcc_priv *priv) +{ + u32 stgenc, cntfid0; + ulong rate = clk_get_rate(&priv->osc_clk[_HSI]); + stgenc = STM32_STGEN_BASE; + cntfid0 = readl(stgenc + STGENC_CNTFID0); + + if (cntfid0 != rate) { + u64 counter; + + log_debug("System Generic Counter (STGEN) update\n"); + clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); + counter = (u64)readl(stgenc + STGENC_CNTCVL); + counter |= ((u64)(readl(stgenc + STGENC_CNTCVU))) << 32; + counter = lldiv(counter * (u64)rate, cntfid0); + writel((u32)counter, stgenc + STGENC_CNTCVL); + writel((u32)(counter >> 32), stgenc + STGENC_CNTCVU); + writel(rate, stgenc + STGENC_CNTFID0); + setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); + + __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate)); + + /* need to update gd->arch.timer_rate_hz with new frequency */ + timer_init(); + } +} + +static int set_clkdiv(unsigned int clkdiv, u32 address) +{ + u32 val; + int ret; + + + clrsetbits_le32(address, RCC_DIVR_DIV_MASK, clkdiv & RCC_DIVR_DIV_MASK); + ret = readl_poll_timeout(address, val, val & RCC_DIVR_DIVRDY, + TIMEOUT_200MS); + if (ret) + log_err("CLKDIV %x start failed @ 0x%x: 0x%x\n", + clkdiv, address, readl(address)); + + return ret; +} + +static void set_rtcsrc(struct stm32mp_rcc_priv *priv, + unsigned int clksrc, + int lse_css) +{ + u32 address = (u32)(priv->base) + RCC_BDCR; + + if (readl(address) & RCC_BDCR_RTCCKEN) + goto skip_rtc; + + if (clksrc == CLK_RTC_DISABLED) + goto skip_rtc; + + clrsetbits_le32(address, + RCC_BDCR_RTCSRC_MASK, + clksrc << RCC_BDCR_RTCSRC_SHIFT); + + setbits_le32(address, RCC_BDCR_RTCCKEN); + +skip_rtc: + if (lse_css) + setbits_le32(address, RCC_BDCR_LSECSSON); +} + +static void pkcs_config(struct stm32mp_rcc_priv *priv, u32 pkcs) +{ + u32 mux = (pkcs & MUX_ID_MASK) >> MUX_ID_SHIFT; + u32 address = (u32)(priv->base) + stm32mp13_muxes[mux].reg_off; + u32 mask = (BIT(stm32mp13_muxes[mux].width) - 1) << stm32mp13_muxes[mux].shift; + u32 value = (pkcs << stm32mp13_muxes[mux].shift) & mask; + + clrsetbits_le32(address, mask, value); +} + +static int stm32mp1_clktree(struct udevice *dev) +{ + struct stm32mp_rcc_priv *priv = dev_get_priv(dev); + fdt_addr_t rcc = (u32)(priv->base); + unsigned int clksrc[CLKSRC_NB]; + unsigned int clkdiv[CLKDIV_NB]; + unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; + unsigned int pllfracv[_PLL_NB]; + unsigned int pllcsg[_PLL_NB][PLLCSG_NB]; + bool pllcfg_valid[_PLL_NB]; + bool pllcsg_set[_PLL_NB]; + int ret; + int i, len; + int lse_css = 0; + const u32 *pkcs_cell; + + /* check mandatory field */ + ret = dev_read_u32_array(dev, "st,clksrc", clksrc, CLKSRC_NB); + if (ret < 0) { + dev_dbg(dev, "field st,clksrc invalid: error %d\n", ret); + return -FDT_ERR_NOTFOUND; + } + + ret = dev_read_u32_array(dev, "st,clkdiv", clkdiv, CLKDIV_NB); + if (ret < 0) { + dev_dbg(dev, "field st,clkdiv invalid: error %d\n", ret); + return -FDT_ERR_NOTFOUND; + } + + /* check mandatory field in each pll */ + for (i = 0; i < _PLL_NB; i++) { + char name[12]; + ofnode node; + + sprintf(name, "st,pll@%d", i); + node = dev_read_subnode(dev, name); + pllcfg_valid[i] = ofnode_valid(node); + pllcsg_set[i] = false; + if (pllcfg_valid[i]) { + dev_dbg(dev, "DT for PLL %d @ %s\n", i, name); + ret = ofnode_read_u32_array(node, "cfg", + pllcfg[i], PLLCFG_NB); + if (ret < 0) { + dev_dbg(dev, "field cfg invalid: error %d\n", ret); + return -FDT_ERR_NOTFOUND; + } + pllfracv[i] = ofnode_read_u32_default(node, "frac", 0); + + ret = ofnode_read_u32_array(node, "csg", pllcsg[i], + PLLCSG_NB); + if (!ret) { + pllcsg_set[i] = true; + } else if (ret != -FDT_ERR_NOTFOUND) { + dev_dbg(dev, "invalid csg node for pll@%d res=%d\n", + i, ret); + return ret; + } + } else if (i == _PLL1) { + /* use OPP for PLL1 for A7 CPU */ + dev_dbg(dev, "DT for PLL %d with OPP\n", i); + ret = stm32mp1_pll1_opp(priv, + clksrc[CLKSRC_PLL12], + pllcfg[i], + &pllfracv[i]); + if (ret) { + dev_dbg(dev, "PLL %d with OPP error = %d\n", i, ret); + return ret; + } + pllcfg_valid[i] = true; + } + } + + dev_dbg(dev, "switch ON osillator\n"); + /* + * switch ON oscillator found in device-tree, + * HSI already ON after bootrom + */ + if (clk_valid(&priv->osc_clk[_LSI])) + stm32mp1_lsi_set(rcc, 1); + + if (clk_valid(&priv->osc_clk[_LSE])) { + int bypass, digbyp; + u32 lsedrv; + struct udevice *dev = priv->osc_clk[_LSE].dev; + + bypass = dev_read_bool(dev, "st,bypass"); + digbyp = dev_read_bool(dev, "st,digbypass"); + lse_css = dev_read_bool(dev, "st,css"); + lsedrv = dev_read_u32_default(dev, "st,drive", + LSEDRV_MEDIUM_HIGH); + + stm32mp1_lse_enable(rcc, bypass, digbyp, lsedrv); + } + + + if (clk_valid(&priv->osc_clk[_HSE])) { + int bypass, digbyp, css; + struct udevice *dev = priv->osc_clk[_HSE].dev; + + bypass = dev_read_bool(dev, "st,bypass"); + digbyp = dev_read_bool(dev, "st,digbypass"); + css = dev_read_bool(dev, "st,css"); + + stm32mp1_hse_enable(rcc, bypass, digbyp, css); + } + + /* CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) + * => switch on CSI even if node is not present in device tree + */ + stm32mp1_csi_set(rcc, 1); + + /* come back to HSI */ + dev_dbg(dev, "come back to HSI\n"); + set_clksrc(priv, CLK_MPU_HSI); + set_clksrc(priv, CLK_AXI_HSI); + set_clksrc(priv, CLK_MLAHBS_HSI); + + dev_dbg(dev, "pll stop\n"); + for (i = 0; i < _PLL_NB; i++) + pll_stop(priv, i); + + /* configure HSIDIV */ + dev_dbg(dev, "configure HSIDIV\n"); + if (clk_valid(&priv->osc_clk[_HSI])) { + stm32mp1_hsidiv(rcc, clk_get_rate(&priv->osc_clk[_HSI])); + stgen_config(priv); + } + + /* select DIV */ + dev_dbg(dev, "select DIV\n"); + /* no ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ + set_clkdiv(clkdiv[CLKDIV_AXI], rcc + RCC_AXIDIVR); + set_clkdiv(clkdiv[CLKDIV_APB4], rcc + RCC_APB4DIVR); + set_clkdiv(clkdiv[CLKDIV_APB5], rcc + RCC_APB5DIVR); + set_clkdiv(clkdiv[CLKDIV_APB6], rcc + RCC_APB6DIVR); + set_clkdiv(clkdiv[CLKDIV_APB1], rcc + RCC_APB1DIVR); + set_clkdiv(clkdiv[CLKDIV_APB2], rcc + RCC_APB2DIVR); + set_clkdiv(clkdiv[CLKDIV_APB3], rcc + RCC_APB3DIVR); + + /* no ready bit for RTC */ + writel(clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK, rcc + RCC_RTCDIVR); + + /* configure PLLs source */ + dev_dbg(dev, "configure PLLs source\n"); + set_clksrc(priv, clksrc[CLKSRC_PLL12]); + set_clksrc(priv, clksrc[CLKSRC_PLL3]); + set_clksrc(priv, clksrc[CLKSRC_PLL4]); + + /* configure and start PLLs */ + dev_dbg(dev, "configure PLLs\n"); + for (i = 0; i < _PLL_NB; i++) { + if (!pllcfg_valid[i]) + continue; + dev_dbg(dev, "configure PLL %d\n", i); + pll_config(priv, i, pllcfg[i], pllfracv[i]); + if (pllcsg_set[i]) + pll_csg(priv, i, pllcsg[i]); + pll_start(priv, i); + } + + /* wait and start PLLs ouptut when ready */ + for (i = 0; i < _PLL_NB; i++) { + if (!pllcfg_valid[i]) + continue; + dev_dbg(dev, "output PLL %d\n", i); + pll_output(priv, i, pllcfg[i][PLLCFG_O]); + } + + /* wait LSE ready before to use it */ + if (clk_valid(&priv->osc_clk[_LSE])) + stm32mp1_lse_wait(rcc); + + /* configure with expected clock source */ + dev_dbg(dev, "CLKSRC\n"); + set_clksrc(priv, clksrc[CLKSRC_MPU]); + set_clksrc(priv, clksrc[CLKSRC_AXI]); + set_clksrc(priv, clksrc[CLKSRC_MLAHB]); + set_rtcsrc(priv, clksrc[CLKSRC_RTC], lse_css); + + /* configure PKCK */ + dev_dbg(dev, "PKCK\n"); + pkcs_cell = dev_read_prop(dev, "st,pkcs", &len); + if (pkcs_cell) { + bool ckper_disabled = false; + + for (i = 0; i < len / sizeof(u32); i++) { + u32 pkcs = (u32)fdt32_to_cpu(pkcs_cell[i]); + + if (pkcs == CLK_CKPER_DISABLED) { + ckper_disabled = true; + continue; + } + pkcs_config(priv, pkcs); + } + /* CKPER is source for some peripheral clock + * (FMC-NAND / QPSI-NOR) and switching source is allowed + * only if previous clock is still ON + * => deactivated CKPER only after switching clock + */ + if (ckper_disabled) + pkcs_config(priv, CLK_CKPER_DISABLED); + } + + /* STGEN clock source can change with CLK_STGEN_XXX */ + stgen_config(priv); + + dev_dbg(dev, "oscillator off\n"); + /* switch OFF HSI if not found in device-tree */ + if (!clk_valid(&priv->osc_clk[_HSI])) + stm32mp1_hsi_set(rcc, 0); + + /* Software Self-Refresh mode (SSR) during DDR initilialization */ + clrsetbits_le32((u32)(priv->base) + RCC_DDRITFCR, + RCC_DDRITFCR_DDRCKMOD_MASK, + RCC_DDRITFCR_DDRCKMOD_SSR << + RCC_DDRITFCR_DDRCKMOD_SHIFT); + + return 0; +} +#endif + +static int stm32mp1_osc_init(struct udevice *dev) +{ + struct stm32mp_rcc_priv *priv = dev_get_priv(dev); + fdt_addr_t base = dev_read_addr(dev->parent); + struct clk *ck; + int i; + + const char *name[NB_OSC] = { + [_LSI] = "lsi", + [_LSE] = "lse", + [_HSI] = "hsi", + [_HSE] = "hse", + [_CSI] = "csi", + [_I2S_CKIN] = "i2s_ckin", + }; + + const struct { + const char *name; + const int rate; + } fixed_clk[] = { + { "bsec", 66625000 }, + { "ck_axi", 266500000 }, + { "ck_mlahb", 200000000 }, + { "ck_mpu", 1000000000 }, + { "ck_per", 24000000 }, + { "ck_rtc", 32768 }, + { "clk-hse-div2", 12000000 }, + { "pclk1", 100000000 }, + { "pclk2", 100000000 }, + { "pclk3", 100000000 }, + { "pclk4", 133250000 }, + { "pclk5", 66625000 }, + { "pclk6", 100000000 }, + { "pll2_q", 266500000 }, + { "pll2_r", 533000000 }, + { "pll3_p", 200000000 }, + { "pll3_q", 150000000 }, + { "pll3_r", 200000000 }, + { "pll4_p", 125000000 }, + { "pll4_q", 83333333 }, + { "pll4_r", 75000000 }, + { "rtcapb", 66625000 }, + { "timg1_ck", 200000000 }, + { "timg2_ck", 200000000 }, + { "timg3_ck", 200000000 }, + }; + + if (base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = (void __iomem *)base; + + for (i = 0; i < NB_OSC; i++) { + if (clk_get_by_name(dev, name[i], &priv->osc_clk[i])) + dev_dbg(dev, "No source clock \"%s\"\n", name[i]); + else + dev_dbg(dev, "%s clock rate: %luHz\n", + name[i], clk_get_rate(&priv->osc_clk[i])); + } + + for (i = 0; i < ARRAY_SIZE(fixed_clk); i++) { + ck = clk_register_fixed_rate(NULL, fixed_clk[i].name, fixed_clk[i].rate); + if (!ck) + dev_dbg(dev, "Cannot register fixed clock \"%s\"\n", fixed_clk[i].name); + } + + return 0; +} +#endif + static int stm32mp1_clk_probe(struct udevice *dev) { - struct udevice *scmi; int err; +#ifdef CONFIG_TFABOOT + struct udevice *scmi; + /* force SCMI probe to register all SCMI clocks */ uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(scmi_clock), &scmi); +#else + err = stm32mp1_osc_init(dev); + if (err) + return err; + +#if defined(CONFIG_XPL_BUILD) + /* clock tree init is done only one time, before relocation */ + if (!(gd->flags & GD_FLG_RELOC)) + err = stm32mp1_clktree(dev); + if (err) + dev_err(dev, "clock tree initialization failed (%d)\n", err); +#endif +#endif err = stm32_rcc_init(dev, &stm32mp13_data); if (err) @@ -815,6 +2012,7 @@ static int stm32mp1_clk_probe(struct udevice *dev) /* DDRPHYC father */ gd->mem_clk = clk_stm32_get_rate_by_name("pll2_r"); +#ifndef CONFIG_XPL_BUILD if (IS_ENABLED(CONFIG_DISPLAY_CPUINFO)) { if (gd->flags & GD_FLG_RELOC) { char buf[32]; @@ -827,6 +2025,7 @@ static int stm32mp1_clk_probe(struct udevice *dev) log_info("- DDR : %s MHz\n", strmhz(buf, gd->mem_clk)); } } +#endif return 0; } diff --git a/drivers/clk/stm32/stm32mp13_rcc.h b/drivers/clk/stm32/stm32mp13_rcc.h index e7191b428af..b9b44b213c3 100644 --- a/drivers/clk/stm32/stm32mp13_rcc.h +++ b/drivers/clk/stm32/stm32mp13_rcc.h @@ -285,4 +285,97 @@ #define RCC_AHB6SECSR_ETH2MACSECF 30 #define RCC_AHB6SECSR_ETH2STPSECF 31 +/* Fields of RCC_BDCR register */ +#define RCC_BDCR_LSEON BIT(0) +#define RCC_BDCR_LSEBYP BIT(1) +#define RCC_BDCR_LSERDY BIT(2) +#define RCC_BDCR_DIGBYP BIT(3) +#define RCC_BDCR_LSEDRV_MASK GENMASK(5, 4) +#define RCC_BDCR_LSEDRV_SHIFT 4 +#define RCC_BDCR_LSECSSON BIT(8) +#define RCC_BDCR_RTCCKEN BIT(20) +#define RCC_BDCR_RTCSRC_MASK GENMASK(17, 16) +#define RCC_BDCR_RTCSRC_SHIFT 16 + +/* Fields of RCC_RDLSICR register */ +#define RCC_RDLSICR_LSION BIT(0) +#define RCC_RDLSICR_LSIRDY BIT(1) + +/* used for ALL PLLNCR registers */ +#define RCC_PLLNCR_PLLON BIT(0) +#define RCC_PLLNCR_PLLRDY BIT(1) +#define RCC_PLLNCR_SSCG_CTRL BIT(2) +#define RCC_PLLNCR_DIVPEN BIT(4) +#define RCC_PLLNCR_DIVQEN BIT(5) +#define RCC_PLLNCR_DIVREN BIT(6) +#define RCC_PLLNCR_DIVEN_SHIFT 4 + +/* used for ALL PLLNCFGR1 registers */ +#define RCC_PLLNCFGR1_DIVM_SHIFT 16 +#define RCC_PLLNCFGR1_DIVM_MASK GENMASK(21, 16) +#define RCC_PLLNCFGR1_DIVN_SHIFT 0 +#define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) +/* only for PLL3 and PLL4 */ +#define RCC_PLLNCFGR1_IFRGE_SHIFT 24 +#define RCC_PLLNCFGR1_IFRGE_MASK GENMASK(25, 24) + +/* used for ALL PLLNCFGR2 registers , using stm32mp1_div_id */ +#define RCC_PLLNCFGR2_SHIFT(div_id) ((div_id) * 8) +#define RCC_PLLNCFGR2_DIVX_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVP_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_P) +#define RCC_PLLNCFGR2_DIVP_MASK GENMASK(6, 0) +#define RCC_PLLNCFGR2_DIVQ_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_Q) +#define RCC_PLLNCFGR2_DIVQ_MASK GENMASK(14, 8) +#define RCC_PLLNCFGR2_DIVR_SHIFT RCC_PLLNCFGR2_SHIFT(_DIV_R) +#define RCC_PLLNCFGR2_DIVR_MASK GENMASK(22, 16) + +/* used for ALL PLLNFRACR registers */ +#define RCC_PLLNFRACR_FRACV_SHIFT 3 +#define RCC_PLLNFRACR_FRACV_MASK GENMASK(15, 3) +#define RCC_PLLNFRACR_FRACLE BIT(16) + +/* used for ALL PLLNCSGR registers */ +#define RCC_PLLNCSGR_INC_STEP_SHIFT 16 +#define RCC_PLLNCSGR_INC_STEP_MASK GENMASK(30, 16) +#define RCC_PLLNCSGR_MOD_PER_SHIFT 0 +#define RCC_PLLNCSGR_MOD_PER_MASK GENMASK(12, 0) +#define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 +#define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) + +/* used for RCC_OCENSETR and RCC_OCENCLRR registers */ +#define RCC_OCENR_HSION BIT(0) +#define RCC_OCENR_CSION BIT(4) +#define RCC_OCENR_DIGBYP BIT(7) +#define RCC_OCENR_HSEON BIT(8) +#define RCC_OCENR_HSEBYP BIT(10) +#define RCC_OCENR_HSECSSON BIT(11) + +/* Fields of RCC_OCRDYR register */ +#define RCC_OCRDYR_HSIRDY BIT(0) +#define RCC_OCRDYR_HSIDIVRDY BIT(2) +#define RCC_OCRDYR_CSIRDY BIT(4) +#define RCC_OCRDYR_HSERDY BIT(8) + +/* Fields of DDRITFCR register */ +#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) +#define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 +#define RCC_DDRITFCR_DDRCKMOD_SSR 0 + +/* Fields of RCC_HSICFGR register */ +#define RCC_HSICFGR_HSIDIV_MASK GENMASK(1, 0) + +/* used for MCO related operations */ +#define RCC_MCOCFG_MCOON BIT(12) +#define RCC_MCOCFG_MCODIV_MASK GENMASK(7, 4) +#define RCC_MCOCFG_MCODIV_SHIFT 4 +#define RCC_MCOCFG_MCOSRC_MASK GENMASK(2, 0) + +/* used for most of SELR register */ +#define RCC_SELR_SRC_MASK GENMASK(2, 0) +#define RCC_SELR_SRCRDY BIT(31) + +/* used for most of DIVR register : max div for RTC */ +#define RCC_DIVR_DIV_MASK GENMASK(5, 0) +#define RCC_DIVR_DIVRDY BIT(31) + #endif /* STM32MP13_RCC_H */ diff --git a/include/dt-bindings/clock/stm32mp13-clksrc.h b/include/dt-bindings/clock/stm32mp13-clksrc.h new file mode 100644 index 00000000000..312a6054699 --- /dev/null +++ b/include/dt-bindings/clock/stm32mp13-clksrc.h @@ -0,0 +1,399 @@ +/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * + */ + +#ifndef _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ +#define _DT_BINDINGS_CLOCK_STM32MP13_CLKSRC_H_ + +/* PLL output is enable when x=1, with x=p,q or r */ +#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) + +/* st,clksrc: mandatory clock source */ + +#define CMD_DIV 0 +#define CMD_MUX 1 +#define CMD_CLK 2 +#define CMD_RESERVED1 3 + +#define CMD_SHIFT 26 +#define CMD_MASK 0xFC000000 +#define CMD_DATA_MASK 0x03FFFFFF + +#define DIV_ID_SHIFT 8 +#define DIV_ID_MASK 0x0000FF00 + +#define DIV_DIVN_SHIFT 0 +#define DIV_DIVN_MASK 0x000000FF + +#define MUX_ID_SHIFT 4 +#define MUX_ID_MASK 0x00000FF0 + +#define MUX_SEL_SHIFT 0 +#define MUX_SEL_MASK 0x0000000F + +#define CLK_ID_MASK GENMASK_32(19, 11) +#define CLK_ID_SHIFT 11 +#define CLK_ON_MASK 0x00000400 +#define CLK_ON_SHIFT 10 +#define CLK_DIV_MASK GENMASK_32(9, 4) +#define CLK_DIV_SHIFT 4 +#define CLK_SEL_MASK GENMASK_32(3, 0) +#define CLK_SEL_SHIFT 0 + +#define DIV_PLL1DIVP 0 +#define DIV_PLL2DIVP 1 +#define DIV_PLL2DIVQ 2 +#define DIV_PLL2DIVR 3 +#define DIV_PLL3DIVP 4 +#define DIV_PLL3DIVQ 5 +#define DIV_PLL3DIVR 6 +#define DIV_PLL4DIVP 7 +#define DIV_PLL4DIVQ 8 +#define DIV_PLL4DIVR 9 +#define DIV_MPU 10 +#define DIV_AXI 11 +#define DIV_MLAHB 12 +#define DIV_APB1 13 +#define DIV_APB2 14 +#define DIV_APB3 15 +#define DIV_APB4 16 +#define DIV_APB5 17 +#define DIV_APB6 18 +#define DIV_RTC 19 +#define DIV_MCO1 20 +#define DIV_MCO2 21 +#define DIV_HSI 22 +#define DIV_TRACE 23 +#define DIV_ETH1PTP 24 +#define DIV_ETH2PTP 25 +#define DIV_MAX 26 + +#define DIV(div_id, div) ((CMD_DIV << CMD_SHIFT) |\ + ((div_id) << DIV_ID_SHIFT |\ + (div))) + +#define CLKSRC(mux_id, sel) ((CMD_MUX << CMD_SHIFT) |\ + ((mux_id) << MUX_ID_SHIFT |\ + (sel))) + +/* MCO output is enable */ +#define MCO_SRC(mco_id, sel) ((CMD_CLK << CMD_SHIFT) |\ + (((mco_id) << CLK_ID_SHIFT) |\ + (sel)) | CLK_ON_MASK) + +#define MCO_DISABLED(mco_id) ((CMD_CLK << CMD_SHIFT) |\ + ((mco_id) << CLK_ID_SHIFT)) + +/* CLK output is enable */ +#define CLK_SRC(clk_id, sel) ((CMD_CLK << CMD_SHIFT) |\ + (((clk_id) << CLK_ID_SHIFT) |\ + (sel)) | CLK_ON_MASK) + +#define CLK_DISABLED(clk_id) ((CMD_CLK << CMD_SHIFT) |\ + ((clk_id) << CLK_ID_SHIFT)) + +#define MUX_MPU 0 +#define MUX_AXI 1 +#define MUX_MLAHB 2 +#define MUX_PLL12 3 +#define MUX_PLL3 4 +#define MUX_PLL4 5 +#define MUX_RTC 6 +#define MUX_MCO1 7 +#define MUX_MCO2 8 +#define MUX_CKPER 9 +#define MUX_KERNEL_BEGIN 10 +#define MUX_ADC1 10 +#define MUX_ADC2 11 +#define MUX_DCMIPP 12 +#define MUX_ETH1 13 +#define MUX_ETH2 14 +#define MUX_FDCAN 15 +#define MUX_FMC 16 +#define MUX_I2C12 17 +#define MUX_I2C3 18 +#define MUX_I2C4 19 +#define MUX_I2C5 20 +#define MUX_LPTIM1 21 +#define MUX_LPTIM2 22 +#define MUX_LPTIM3 23 +#define MUX_LPTIM45 24 +#define MUX_QSPI 25 +#define MUX_RNG1 26 +#define MUX_SAES 27 +#define MUX_SAI1 28 +#define MUX_SAI2 29 +#define MUX_SDMMC1 30 +#define MUX_SDMMC2 31 +#define MUX_SPDIF 32 +#define MUX_SPI1 33 +#define MUX_SPI23 34 +#define MUX_SPI4 35 +#define MUX_SPI5 36 +#define MUX_STGEN 37 +#define MUX_UART1 38 +#define MUX_UART2 39 +#define MUX_UART35 40 +#define MUX_UART4 41 +#define MUX_UART6 42 +#define MUX_UART78 43 +#define MUX_USBO 44 +#define MUX_USBPHY 45 +#define MUX_MAX 46 + +#define CLK_MPU_HSI CLKSRC(MUX_MPU, 0) +#define CLK_MPU_HSE CLKSRC(MUX_MPU, 1) +#define CLK_MPU_PLL1P CLKSRC(MUX_MPU, 2) +#define CLK_MPU_PLL1P_DIV CLKSRC(MUX_MPU, 3) + +#define CLK_AXI_HSI CLKSRC(MUX_AXI, 0) +#define CLK_AXI_HSE CLKSRC(MUX_AXI, 1) +#define CLK_AXI_PLL2P CLKSRC(MUX_AXI, 2) + +#define CLK_MLAHBS_HSI CLKSRC(MUX_MLAHB, 0) +#define CLK_MLAHBS_HSE CLKSRC(MUX_MLAHB, 1) +#define CLK_MLAHBS_CSI CLKSRC(MUX_MLAHB, 2) +#define CLK_MLAHBS_PLL3 CLKSRC(MUX_MLAHB, 3) + +#define CLK_PLL12_HSI CLKSRC(MUX_PLL12, 0) +#define CLK_PLL12_HSE CLKSRC(MUX_PLL12, 1) + +#define CLK_PLL3_HSI CLKSRC(MUX_PLL3, 0) +#define CLK_PLL3_HSE CLKSRC(MUX_PLL3, 1) +#define CLK_PLL3_CSI CLKSRC(MUX_PLL3, 2) + +#define CLK_PLL4_HSI CLKSRC(MUX_PLL4, 0) +#define CLK_PLL4_HSE CLKSRC(MUX_PLL4, 1) +#define CLK_PLL4_CSI CLKSRC(MUX_PLL4, 2) + +#define CLK_RTC_DISABLED CLK_DISABLED(RTC) +#define CLK_RTC_LSE CLK_SRC(RTC, 1) +#define CLK_RTC_LSI CLK_SRC(RTC, 2) +#define CLK_RTC_HSE CLK_SRC(RTC, 3) + +#define CLK_MCO1_HSI CLK_SRC(CK_MCO1, 0) +#define CLK_MCO1_HSE CLK_SRC(CK_MCO1, 1) +#define CLK_MCO1_CSI CLK_SRC(CK_MCO1, 2) +#define CLK_MCO1_LSI CLK_SRC(CK_MCO1, 3) +#define CLK_MCO1_LSE CLK_SRC(CK_MCO1, 4) +#define CLK_MCO1_DISABLED CLK_DISABLED(CK_MCO1) + +#define CLK_MCO2_MPU CLK_SRC(CK_MCO2, 0) +#define CLK_MCO2_AXI CLK_SRC(CK_MCO2, 1) +#define CLK_MCO2_MLAHB CLK_SRC(CK_MCO2, 2) +#define CLK_MCO2_PLL4 CLK_SRC(CK_MCO2, 3) +#define CLK_MCO2_HSE CLK_SRC(CK_MCO2, 4) +#define CLK_MCO2_HSI CLK_SRC(CK_MCO2, 5) +#define CLK_MCO2_DISABLED CLK_DISABLED(CK_MCO2) + +#define CLK_CKPER_HSI CLKSRC(MUX_CKPER, 0) +#define CLK_CKPER_CSI CLKSRC(MUX_CKPER, 1) +#define CLK_CKPER_HSE CLKSRC(MUX_CKPER, 2) +#define CLK_CKPER_DISABLED CLKSRC(MUX_CKPER, 3) + +#define CLK_I2C12_PCLK1 CLKSRC(MUX_I2C12, 0) +#define CLK_I2C12_PLL4R CLKSRC(MUX_I2C12, 1) +#define CLK_I2C12_HSI CLKSRC(MUX_I2C12, 2) +#define CLK_I2C12_CSI CLKSRC(MUX_I2C12, 3) + +#define CLK_I2C3_PCLK6 CLKSRC(MUX_I2C3, 0) +#define CLK_I2C3_PLL4R CLKSRC(MUX_I2C3, 1) +#define CLK_I2C3_HSI CLKSRC(MUX_I2C3, 2) +#define CLK_I2C3_CSI CLKSRC(MUX_I2C3, 3) + +#define CLK_I2C4_PCLK6 CLKSRC(MUX_I2C4, 0) +#define CLK_I2C4_PLL4R CLKSRC(MUX_I2C4, 1) +#define CLK_I2C4_HSI CLKSRC(MUX_I2C4, 2) +#define CLK_I2C4_CSI CLKSRC(MUX_I2C4, 3) + +#define CLK_I2C5_PCLK6 CLKSRC(MUX_I2C5, 0) +#define CLK_I2C5_PLL4R CLKSRC(MUX_I2C5, 1) +#define CLK_I2C5_HSI CLKSRC(MUX_I2C5, 2) +#define CLK_I2C5_CSI CLKSRC(MUX_I2C5, 3) + +#define CLK_SPI1_PLL4P CLKSRC(MUX_SPI1, 0) +#define CLK_SPI1_PLL3Q CLKSRC(MUX_SPI1, 1) +#define CLK_SPI1_I2SCKIN CLKSRC(MUX_SPI1, 2) +#define CLK_SPI1_CKPER CLKSRC(MUX_SPI1, 3) +#define CLK_SPI1_PLL3R CLKSRC(MUX_SPI1, 4) + +#define CLK_SPI23_PLL4P CLKSRC(MUX_SPI23, 0) +#define CLK_SPI23_PLL3Q CLKSRC(MUX_SPI23, 1) +#define CLK_SPI23_I2SCKIN CLKSRC(MUX_SPI23, 2) +#define CLK_SPI23_CKPER CLKSRC(MUX_SPI23, 3) +#define CLK_SPI23_PLL3R CLKSRC(MUX_SPI23, 4) + +#define CLK_SPI4_PCLK6 CLKSRC(MUX_SPI4, 0) +#define CLK_SPI4_PLL4Q CLKSRC(MUX_SPI4, 1) +#define CLK_SPI4_HSI CLKSRC(MUX_SPI4, 2) +#define CLK_SPI4_CSI CLKSRC(MUX_SPI4, 3) +#define CLK_SPI4_HSE CLKSRC(MUX_SPI4, 4) +#define CLK_SPI4_I2SCKIN CLKSRC(MUX_SPI4, 5) + +#define CLK_SPI5_PCLK6 CLKSRC(MUX_SPI5, 0) +#define CLK_SPI5_PLL4Q CLKSRC(MUX_SPI5, 1) +#define CLK_SPI5_HSI CLKSRC(MUX_SPI5, 2) +#define CLK_SPI5_CSI CLKSRC(MUX_SPI5, 3) +#define CLK_SPI5_HSE CLKSRC(MUX_SPI5, 4) + +#define CLK_UART1_PCLK6 CLKSRC(MUX_UART1, 0) +#define CLK_UART1_PLL3Q CLKSRC(MUX_UART1, 1) +#define CLK_UART1_HSI CLKSRC(MUX_UART1, 2) +#define CLK_UART1_CSI CLKSRC(MUX_UART1, 3) +#define CLK_UART1_PLL4Q CLKSRC(MUX_UART1, 4) +#define CLK_UART1_HSE CLKSRC(MUX_UART1, 5) + +#define CLK_UART2_PCLK6 CLKSRC(MUX_UART2, 0) +#define CLK_UART2_PLL3Q CLKSRC(MUX_UART2, 1) +#define CLK_UART2_HSI CLKSRC(MUX_UART2, 2) +#define CLK_UART2_CSI CLKSRC(MUX_UART2, 3) +#define CLK_UART2_PLL4Q CLKSRC(MUX_UART2, 4) +#define CLK_UART2_HSE CLKSRC(MUX_UART2, 5) + +#define CLK_UART35_PCLK1 CLKSRC(MUX_UART35, 0) +#define CLK_UART35_PLL4Q CLKSRC(MUX_UART35, 1) +#define CLK_UART35_HSI CLKSRC(MUX_UART35, 2) +#define CLK_UART35_CSI CLKSRC(MUX_UART35, 3) +#define CLK_UART35_HSE CLKSRC(MUX_UART35, 4) + +#define CLK_UART4_PCLK1 CLKSRC(MUX_UART4, 0) +#define CLK_UART4_PLL4Q CLKSRC(MUX_UART4, 1) +#define CLK_UART4_HSI CLKSRC(MUX_UART4, 2) +#define CLK_UART4_CSI CLKSRC(MUX_UART4, 3) +#define CLK_UART4_HSE CLKSRC(MUX_UART4, 4) + +#define CLK_UART6_PCLK2 CLKSRC(MUX_UART6, 0) +#define CLK_UART6_PLL4Q CLKSRC(MUX_UART6, 1) +#define CLK_UART6_HSI CLKSRC(MUX_UART6, 2) +#define CLK_UART6_CSI CLKSRC(MUX_UART6, 3) +#define CLK_UART6_HSE CLKSRC(MUX_UART6, 4) + +#define CLK_UART78_PCLK1 CLKSRC(MUX_UART78, 0) +#define CLK_UART78_PLL4Q CLKSRC(MUX_UART78, 1) +#define CLK_UART78_HSI CLKSRC(MUX_UART78, 2) +#define CLK_UART78_CSI CLKSRC(MUX_UART78, 3) +#define CLK_UART78_HSE CLKSRC(MUX_UART78, 4) + +#define CLK_LPTIM1_PCLK1 CLKSRC(MUX_LPTIM1, 0) +#define CLK_LPTIM1_PLL4P CLKSRC(MUX_LPTIM1, 1) +#define CLK_LPTIM1_PLL3Q CLKSRC(MUX_LPTIM1, 2) +#define CLK_LPTIM1_LSE CLKSRC(MUX_LPTIM1, 3) +#define CLK_LPTIM1_LSI CLKSRC(MUX_LPTIM1, 4) +#define CLK_LPTIM1_CKPER CLKSRC(MUX_LPTIM1, 5) + +#define CLK_LPTIM2_PCLK3 CLKSRC(MUX_LPTIM2, 0) +#define CLK_LPTIM2_PLL4Q CLKSRC(MUX_LPTIM2, 1) +#define CLK_LPTIM2_CKPER CLKSRC(MUX_LPTIM2, 2) +#define CLK_LPTIM2_LSE CLKSRC(MUX_LPTIM2, 3) +#define CLK_LPTIM2_LSI CLKSRC(MUX_LPTIM2, 4) + +#define CLK_LPTIM3_PCLK3 CLKSRC(MUX_LPTIM3, 0) +#define CLK_LPTIM3_PLL4Q CLKSRC(MUX_LPTIM3, 1) +#define CLK_LPTIM3_CKPER CLKSRC(MUX_LPTIM3, 2) +#define CLK_LPTIM3_LSE CLKSRC(MUX_LPTIM3, 3) +#define CLK_LPTIM3_LSI CLKSRC(MUX_LPTIM3, 4) + +#define CLK_LPTIM45_PCLK3 CLKSRC(MUX_LPTIM45, 0) +#define CLK_LPTIM45_PLL4P CLKSRC(MUX_LPTIM45, 1) +#define CLK_LPTIM45_PLL3Q CLKSRC(MUX_LPTIM45, 2) +#define CLK_LPTIM45_LSE CLKSRC(MUX_LPTIM45, 3) +#define CLK_LPTIM45_LSI CLKSRC(MUX_LPTIM45, 4) +#define CLK_LPTIM45_CKPER CLKSRC(MUX_LPTIM45, 5) + +#define CLK_SAI1_PLL4Q CLKSRC(MUX_SAI1, 0) +#define CLK_SAI1_PLL3Q CLKSRC(MUX_SAI1, 1) +#define CLK_SAI1_I2SCKIN CLKSRC(MUX_SAI1, 2) +#define CLK_SAI1_CKPER CLKSRC(MUX_SAI1, 3) +#define CLK_SAI1_PLL3R CLKSRC(MUX_SAI1, 4) + +#define CLK_SAI2_PLL4Q CLKSRC(MUX_SAI2, 0) +#define CLK_SAI2_PLL3Q CLKSRC(MUX_SAI2, 1) +#define CLK_SAI2_I2SCKIN CLKSRC(MUX_SAI2, 2) +#define CLK_SAI2_CKPER CLKSRC(MUX_SAI2, 3) +#define CLK_SAI2_SPDIF CLKSRC(MUX_SAI2, 4) +#define CLK_SAI2_PLL3R CLKSRC(MUX_SAI2, 5) + +#define CLK_FDCAN_HSE CLKSRC(MUX_FDCAN, 0) +#define CLK_FDCAN_PLL3Q CLKSRC(MUX_FDCAN, 1) +#define CLK_FDCAN_PLL4Q CLKSRC(MUX_FDCAN, 2) +#define CLK_FDCAN_PLL4R CLKSRC(MUX_FDCAN, 3) + +#define CLK_SPDIF_PLL4P CLKSRC(MUX_SPDIF, 0) +#define CLK_SPDIF_PLL3Q CLKSRC(MUX_SPDIF, 1) +#define CLK_SPDIF_HSI CLKSRC(MUX_SPDIF, 2) + +#define CLK_ADC1_PLL4R CLKSRC(MUX_ADC1, 0) +#define CLK_ADC1_CKPER CLKSRC(MUX_ADC1, 1) +#define CLK_ADC1_PLL3Q CLKSRC(MUX_ADC1, 2) + +#define CLK_ADC2_PLL4R CLKSRC(MUX_ADC2, 0) +#define CLK_ADC2_CKPER CLKSRC(MUX_ADC2, 1) +#define CLK_ADC2_PLL3Q CLKSRC(MUX_ADC2, 2) + +#define CLK_SDMMC1_HCLK6 CLKSRC(MUX_SDMMC1, 0) +#define CLK_SDMMC1_PLL3R CLKSRC(MUX_SDMMC1, 1) +#define CLK_SDMMC1_PLL4P CLKSRC(MUX_SDMMC1, 2) +#define CLK_SDMMC1_HSI CLKSRC(MUX_SDMMC1, 3) + +#define CLK_SDMMC2_HCLK6 CLKSRC(MUX_SDMMC2, 0) +#define CLK_SDMMC2_PLL3R CLKSRC(MUX_SDMMC2, 1) +#define CLK_SDMMC2_PLL4P CLKSRC(MUX_SDMMC2, 2) +#define CLK_SDMMC2_HSI CLKSRC(MUX_SDMMC2, 3) + +#define CLK_ETH1_PLL4P CLKSRC(MUX_ETH1, 0) +#define CLK_ETH1_PLL3Q CLKSRC(MUX_ETH1, 1) + +#define CLK_ETH2_PLL4P CLKSRC(MUX_ETH2, 0) +#define CLK_ETH2_PLL3Q CLKSRC(MUX_ETH2, 1) + +#define CLK_USBPHY_HSE CLKSRC(MUX_USBPHY, 0) +#define CLK_USBPHY_PLL4R CLKSRC(MUX_USBPHY, 1) +#define CLK_USBPHY_HSE_DIV2 CLKSRC(MUX_USBPHY, 2) + +#define CLK_USBO_PLL4R CLKSRC(MUX_USBO, 0) +#define CLK_USBO_USBPHY CLKSRC(MUX_USBO, 1) + +#define CLK_QSPI_ACLK CLKSRC(MUX_QSPI, 0) +#define CLK_QSPI_PLL3R CLKSRC(MUX_QSPI, 1) +#define CLK_QSPI_PLL4P CLKSRC(MUX_QSPI, 2) +#define CLK_QSPI_CKPER CLKSRC(MUX_QSPI, 3) + +#define CLK_FMC_ACLK CLKSRC(MUX_FMC, 0) +#define CLK_FMC_PLL3R CLKSRC(MUX_FMC, 1) +#define CLK_FMC_PLL4P CLKSRC(MUX_FMC, 2) +#define CLK_FMC_CKPER CLKSRC(MUX_FMC, 3) + +#define CLK_RNG1_CSI CLKSRC(MUX_RNG1, 0) +#define CLK_RNG1_PLL4R CLKSRC(MUX_RNG1, 1) +/* WARNING: POSITION 2 OF RNG1 MUX IS RESERVED */ +#define CLK_RNG1_LSI CLKSRC(MUX_RNG1, 3) + +#define CLK_STGEN_HSI CLKSRC(MUX_STGEN, 0) +#define CLK_STGEN_HSE CLKSRC(MUX_STGEN, 1) + +#define CLK_DCMIPP_ACLK CLKSRC(MUX_DCMIPP, 0) +#define CLK_DCMIPP_PLL2Q CLKSRC(MUX_DCMIPP, 1) +#define CLK_DCMIPP_PLL4P CLKSRC(MUX_DCMIPP, 2) +#define CLK_DCMIPP_CKPER CLKSRC(MUX_DCMIPP, 3) + +#define CLK_SAES_AXI CLKSRC(MUX_SAES, 0) +#define CLK_SAES_CKPER CLKSRC(MUX_SAES, 1) +#define CLK_SAES_PLL4R CLKSRC(MUX_SAES, 2) +#define CLK_SAES_LSI CLKSRC(MUX_SAES, 3) + +/* PLL output is enable when x=1, with x=p,q or r */ +#define PQR(p, q, r) (((p) & 1) | (((q) & 1) << 1) | (((r) & 1) << 2)) + +/* define for st,pll /csg */ +#define SSCG_MODE_CENTER_SPREAD 0 +#define SSCG_MODE_DOWN_SPREAD 1 + +/* define for st,drive */ +#define LSEDRV_LOWEST 0 +#define LSEDRV_MEDIUM_LOW 1 +#define LSEDRV_MEDIUM_HIGH 2 +#define LSEDRV_HIGHEST 3 + +#endif -- cgit v1.3.1 From 3f2eb09c2233904e973b94c08420358b7f0e3c31 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 12 May 2025 19:09:47 +0200 Subject: tools: stm32image: Add support for STM32 Image V2.0 Add support for generating STM32 Image V2.0, which is used by STM32MP13xx. The image header layout is similar to STM32MP15xx STM32 Image V1.0, but is different enough to justify duplicate functions to generate the v2 image. This code at least attempts to align the V1 and V2 image handling where possible. Signed-off-by: Marek Vasut --- boot/image.c | 1 + include/image.h | 1 + tools/stm32image.c | 215 +++++++++++++++++++++++++++++++++++++++-------------- 3 files changed, 163 insertions(+), 54 deletions(-) (limited to 'include') diff --git a/boot/image.c b/boot/image.c index 139c5bd035a..abac2c7034b 100644 --- a/boot/image.c +++ b/boot/image.c @@ -184,6 +184,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" }, { IH_TYPE_STARFIVE_SPL, "sfspl", "StarFive SPL Image" }, { IH_TYPE_TFA_BL31, "tfa-bl31", "TFA BL31 Image", }, + { IH_TYPE_STM32IMAGE_V2, "stm32imagev2", "STMicroelectronics STM32 Image V2.0" }, { -1, "", "", }, }; diff --git a/include/image.h b/include/image.h index f09862b636f..37506c81cdb 100644 --- a/include/image.h +++ b/include/image.h @@ -233,6 +233,7 @@ enum image_type_t { IH_TYPE_RENESAS_SPKG, /* Renesas SPKG image */ IH_TYPE_STARFIVE_SPL, /* StarFive SPL image */ IH_TYPE_TFA_BL31, /* TFA BL31 image */ + IH_TYPE_STM32IMAGE_V2, /* STMicroelectronics STM32 Image V2.0 */ IH_TYPE_COUNT, /* Number of image types */ }; diff --git a/tools/stm32image.c b/tools/stm32image.c index 5c6991f35de..2a31d37f9cf 100644 --- a/tools/stm32image.c +++ b/tools/stm32image.c @@ -8,58 +8,74 @@ /* magic ='S' 'T' 'M' 0x32 */ #define HEADER_MAGIC be32_to_cpu(0x53544D32) -#define VER_MAJOR_IDX 2 -#define VER_MINOR_IDX 1 -#define VER_VARIANT_IDX 0 +#define VER_MAJOR 2 +#define VER_MINOR 1 +#define VER_VARIANT 0 #define HEADER_VERSION_V1 0x1 +#define HEADER_VERSION_V2 0x2 /* default option : bit0 => no signature */ #define HEADER_DEFAULT_OPTION (cpu_to_le32(0x00000001)) /* default binary type for U-Boot */ #define HEADER_TYPE_UBOOT (cpu_to_le32(0x00000000)) +#define PADDING_HEADER_MAGIC (cpu_to_le32(0xFFFF5453)) +#define PADDING_HEADER_FLAG (1ULL << 31) +#define PADDING_HEADER_LENGTH 0x180 -struct stm32_header { +struct stm32_header_v1 { uint32_t magic_number; - uint32_t image_signature[64 / 4]; + uint8_t image_signature[64]; uint32_t image_checksum; - uint8_t header_version[4]; + uint8_t header_version[4]; uint32_t image_length; uint32_t image_entry_point; uint32_t reserved1; uint32_t load_address; uint32_t reserved2; uint32_t version_number; + /* V1.0 specific content */ uint32_t option_flags; uint32_t ecdsa_algorithm; - uint32_t ecdsa_public_key[64 / 4]; - uint32_t padding[83 / 4]; - uint32_t binary_type; + uint8_t ecdsa_public_key[64]; + uint8_t padding[83]; + uint8_t binary_type; }; -static struct stm32_header stm32image_header; +struct stm32_header_v2 { + uint32_t magic_number; + uint8_t image_signature[64]; + uint32_t image_checksum; + uint8_t header_version[4]; + uint32_t image_length; + uint32_t image_entry_point; + uint32_t reserved1; + uint32_t load_address; + uint32_t reserved2; + uint32_t version_number; + /* V2.0 specific content */ + uint32_t extension_flags; + uint32_t extension_headers_length; + uint32_t binary_type; + uint8_t padding[16]; + uint32_t extension_header_type; + uint32_t extension_header_length; + uint8_t extension_padding[376]; +}; -static void stm32image_default_header(struct stm32_header *ptr) -{ - if (!ptr) - return; - - ptr->magic_number = HEADER_MAGIC; - ptr->header_version[VER_MAJOR_IDX] = HEADER_VERSION_V1; - ptr->option_flags = HEADER_DEFAULT_OPTION; - ptr->ecdsa_algorithm = cpu_to_le32(1); - ptr->binary_type = HEADER_TYPE_UBOOT; -} +static struct stm32_header_v1 stm32image_header_v1; +static struct stm32_header_v2 stm32image_header_v2; -static uint32_t stm32image_checksum(void *start, uint32_t len) +static uint32_t stm32image_checksum(void *start, uint32_t len, + uint32_t header_size) { uint32_t csum = 0; - uint32_t hdr_len = sizeof(struct stm32_header); uint8_t *p; - if (len < hdr_len) + if (len < header_size) { return 0; + } - p = start + hdr_len; - len -= hdr_len; + p = (unsigned char *)start + header_size; + len -= header_size; while (len > 0) { csum += *p; @@ -70,24 +86,53 @@ static uint32_t stm32image_checksum(void *start, uint32_t len) return csum; } -static int stm32image_check_image_types(uint8_t type) +static int stm32image_check_image_types_v1(uint8_t type) { if (type == IH_TYPE_STM32IMAGE) return EXIT_SUCCESS; return EXIT_FAILURE; } -static int stm32image_verify_header(unsigned char *ptr, int image_size, - struct image_tool_params *params) +static int stm32image_check_image_types_v2(uint8_t type) +{ + if (type == IH_TYPE_STM32IMAGE_V2) + return EXIT_SUCCESS; + return EXIT_FAILURE; +} + +static int stm32image_verify_header_v1(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + struct stm32_header_v1 *stm32hdr = (struct stm32_header_v1 *)ptr; + int i; + + if (image_size < sizeof(struct stm32_header_v1)) + return -1; + if (stm32hdr->magic_number != HEADER_MAGIC) + return -1; + if (stm32hdr->header_version[VER_MAJOR] != HEADER_VERSION_V1) + return -1; + if (stm32hdr->reserved1 || stm32hdr->reserved2) + return -1; + for (i = 0; i < (sizeof(stm32hdr->padding) / 4); i++) { + if (stm32hdr->padding[i] != 0) + return -1; + } + + return 0; +} + +static int stm32image_verify_header_v2(unsigned char *ptr, int image_size, + struct image_tool_params *params) { - struct stm32_header *stm32hdr = (struct stm32_header *)ptr; + struct stm32_header_v2 *stm32hdr = (struct stm32_header_v2 *)ptr; int i; - if (image_size < sizeof(struct stm32_header)) + if (image_size < sizeof(struct stm32_header_v2)) return -1; if (stm32hdr->magic_number != HEADER_MAGIC) return -1; - if (stm32hdr->header_version[VER_MAJOR_IDX] != HEADER_VERSION_V1) + if (stm32hdr->header_version[VER_MAJOR] != HEADER_VERSION_V2) return -1; if (stm32hdr->reserved1 || stm32hdr->reserved2) return -1; @@ -101,38 +146,85 @@ static int stm32image_verify_header(unsigned char *ptr, int image_size, static void stm32image_print_header(const void *ptr, struct image_tool_params *params) { - struct stm32_header *stm32hdr = (struct stm32_header *)ptr; + struct stm32_header_v1 *stm32hdr_v1 = (struct stm32_header_v1 *)ptr; + struct stm32_header_v2 *stm32hdr_v2 = (struct stm32_header_v2 *)ptr; printf("Image Type : STMicroelectronics STM32 V%d.%d\n", - stm32hdr->header_version[VER_MAJOR_IDX], - stm32hdr->header_version[VER_MINOR_IDX]); + stm32hdr_v1->header_version[VER_MAJOR], + stm32hdr_v1->header_version[VER_MINOR]); printf("Image Size : %lu bytes\n", - (unsigned long)le32_to_cpu(stm32hdr->image_length)); + (unsigned long)le32_to_cpu(stm32hdr_v1->image_length)); printf("Image Load : 0x%08x\n", - le32_to_cpu(stm32hdr->load_address)); + le32_to_cpu(stm32hdr_v1->load_address)); printf("Entry Point : 0x%08x\n", - le32_to_cpu(stm32hdr->image_entry_point)); + le32_to_cpu(stm32hdr_v1->image_entry_point)); printf("Checksum : 0x%08x\n", - le32_to_cpu(stm32hdr->image_checksum)); - printf("Option : 0x%08x\n", - le32_to_cpu(stm32hdr->option_flags)); - printf("BinaryType : 0x%08x\n", - le32_to_cpu(stm32hdr->binary_type)); + le32_to_cpu(stm32hdr_v1->image_checksum)); + switch (stm32hdr_v1->header_version[VER_MAJOR]) { + case HEADER_VERSION_V1: + printf("Option : 0x%08x\n", + le32_to_cpu(stm32hdr_v1->option_flags)); + printf("BinaryType : 0x%08x\n", + le32_to_cpu(stm32hdr_v1->binary_type)); + break; + + case HEADER_VERSION_V2: + printf("Extension : 0x%08x\n", + le32_to_cpu(stm32hdr_v2->extension_flags)); + break; + + default: + printf("Incorrect header version\n"); + } } -static void stm32image_set_header(void *ptr, struct stat *sbuf, int ifd, - struct image_tool_params *params) +static void stm32image_set_header_v1(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) { - struct stm32_header *stm32hdr = (struct stm32_header *)ptr; + struct stm32_header_v1 *stm32hdr = (struct stm32_header_v1 *)ptr; - stm32image_default_header(stm32hdr); + stm32hdr->magic_number = HEADER_MAGIC; + stm32hdr->version_number = cpu_to_le32(0); + + stm32hdr->header_version[VER_MAJOR] = HEADER_VERSION_V1; + stm32hdr->option_flags = HEADER_DEFAULT_OPTION; + stm32hdr->ecdsa_algorithm = cpu_to_le32(1); + stm32hdr->binary_type = HEADER_TYPE_UBOOT; stm32hdr->load_address = cpu_to_le32(params->addr); stm32hdr->image_entry_point = cpu_to_le32(params->ep); stm32hdr->image_length = cpu_to_le32((uint32_t)sbuf->st_size - - sizeof(struct stm32_header)); + sizeof(*stm32hdr)); stm32hdr->image_checksum = - cpu_to_le32(stm32image_checksum(ptr, sbuf->st_size)); + cpu_to_le32(stm32image_checksum(ptr, sbuf->st_size, + sizeof(*stm32hdr))); +} + +static void stm32image_set_header_v2(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + struct stm32_header_v2 *stm32hdr = (struct stm32_header_v2 *)ptr; + + stm32hdr->magic_number = HEADER_MAGIC; + stm32hdr->version_number = cpu_to_le32(0); + + stm32hdr->header_version[VER_MAJOR] = HEADER_VERSION_V2; + stm32hdr->extension_flags = + cpu_to_le32(PADDING_HEADER_FLAG); + stm32hdr->extension_headers_length = + cpu_to_le32(PADDING_HEADER_LENGTH); + stm32hdr->extension_header_type = + cpu_to_le32(PADDING_HEADER_MAGIC); + stm32hdr->extension_header_length = + cpu_to_le32(PADDING_HEADER_LENGTH); + + stm32hdr->load_address = cpu_to_le32(params->addr); + stm32hdr->image_entry_point = cpu_to_le32(params->ep); + stm32hdr->image_length = cpu_to_le32((uint32_t)sbuf->st_size - + sizeof(*stm32hdr)); + stm32hdr->image_checksum = + cpu_to_le32(stm32image_checksum(ptr, sbuf->st_size, + sizeof(*stm32hdr))); } /* @@ -141,14 +233,29 @@ static void stm32image_set_header(void *ptr, struct stat *sbuf, int ifd, U_BOOT_IMAGE_TYPE( stm32image, "STMicroelectronics STM32MP Image support", - sizeof(struct stm32_header), - (void *)&stm32image_header, + sizeof(struct stm32_header_v1), + (void *)&stm32image_header_v1, + NULL, + stm32image_verify_header_v1, + stm32image_print_header, + stm32image_set_header_v1, + NULL, + stm32image_check_image_types_v1, + NULL, + NULL +); + +U_BOOT_IMAGE_TYPE( + stm32imagev2, + "STMicroelectronics STM32MP Image V2.0 support", + sizeof(struct stm32_header_v2), + (void *)&stm32image_header_v2, NULL, - stm32image_verify_header, + stm32image_verify_header_v2, stm32image_print_header, - stm32image_set_header, + stm32image_set_header_v2, NULL, - stm32image_check_image_types, + stm32image_check_image_types_v2, NULL, NULL ); -- cgit v1.3.1 From 7ab0ee3a59c01ca164a5b71e0c4c90555da5e806 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sat, 7 Jun 2025 11:37:17 +0200 Subject: board: stm32: add stm32h747-discovery board support The board includes an STM32H747XI SoC with the following resources: - 2 Mbytes Flash - 1 Mbyte SRAM - LCD-TFT controller - MIPI-DSI interface - FD-CAN - USB 2.0 high-speed/full-speed - Ethernet MAC - camera interface Detailed information can be found at: https://www.st.com/en/evaluation-tools/stm32h747i-disco.html Signed-off-by: Dario Binacchi Reviewed-by: Patrice Chotard --- arch/arm/mach-stm32/stm32h7/Kconfig | 4 +++ board/st/stm32h747-disco/Kconfig | 15 +++++++++++ board/st/stm32h747-disco/MAINTAINERS | 7 +++++ board/st/stm32h747-disco/Makefile | 6 +++++ board/st/stm32h747-disco/stm32h747-disco.c | 42 ++++++++++++++++++++++++++++++ configs/stm32h747-disco_defconfig | 35 +++++++++++++++++++++++++ drivers/clk/stm32/clk-stm32h7.c | 5 ++++ include/configs/stm32h747-disco.h | 32 +++++++++++++++++++++++ 8 files changed, 146 insertions(+) create mode 100644 board/st/stm32h747-disco/Kconfig create mode 100644 board/st/stm32h747-disco/MAINTAINERS create mode 100644 board/st/stm32h747-disco/Makefile create mode 100644 board/st/stm32h747-disco/stm32h747-disco.c create mode 100644 configs/stm32h747-disco_defconfig create mode 100644 include/configs/stm32h747-disco.h (limited to 'include') diff --git a/arch/arm/mach-stm32/stm32h7/Kconfig b/arch/arm/mach-stm32/stm32h7/Kconfig index 70233a4b23c..72f20c477d0 100644 --- a/arch/arm/mach-stm32/stm32h7/Kconfig +++ b/arch/arm/mach-stm32/stm32h7/Kconfig @@ -6,11 +6,15 @@ config TARGET_STM32H743_DISCO config TARGET_STM32H743_EVAL bool "STM32H743 Evaluation board" +config TARGET_STM32H747_DISCO + bool "STM32H747 Discovery board" + config TARGET_STM32H750_ART_PI bool "STM32H750 ART Pi board" source "board/st/stm32h743-eval/Kconfig" source "board/st/stm32h743-disco/Kconfig" +source "board/st/stm32h747-disco/Kconfig" source "board/st/stm32h750-art-pi/Kconfig" endif diff --git a/board/st/stm32h747-disco/Kconfig b/board/st/stm32h747-disco/Kconfig new file mode 100644 index 00000000000..a7b2c09a327 --- /dev/null +++ b/board/st/stm32h747-disco/Kconfig @@ -0,0 +1,15 @@ +if TARGET_STM32H747_DISCO + +config SYS_BOARD + default "stm32h747-disco" + +config SYS_VENDOR + default "st" + +config SYS_SOC + default "stm32h7" + +config SYS_CONFIG_NAME + default "stm32h747-disco" + +endif diff --git a/board/st/stm32h747-disco/MAINTAINERS b/board/st/stm32h747-disco/MAINTAINERS new file mode 100644 index 00000000000..d48649f773f --- /dev/null +++ b/board/st/stm32h747-disco/MAINTAINERS @@ -0,0 +1,7 @@ +STM32H747 DISCOVERY BOARD +M: Dario Binacchi +S: Maintained +F: board/st/stm32h747-disco +F: include/configs/stm32h747-disco.h +F: configs/stm32h747-disco_defconfig +F: arch/arm/dts/stm32h747* diff --git a/board/st/stm32h747-disco/Makefile b/board/st/stm32h747-disco/Makefile new file mode 100644 index 00000000000..e11f052cc88 --- /dev/null +++ b/board/st/stm32h747-disco/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2025 Dario Binacchi +# + +obj-y := stm32h747-disco.o diff --git a/board/st/stm32h747-disco/stm32h747-disco.c b/board/st/stm32h747-disco/stm32h747-disco.c new file mode 100644 index 00000000000..be0884bdeb4 --- /dev/null +++ b/board/st/stm32h747-disco/stm32h747-disco.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * stm32h747i-disco support + * + * Copyright (C) 2025 Dario Binacchi + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + struct udevice *dev; + int ret; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return ret; + } + + if (fdtdec_setup_mem_size_base() != 0) + ret = -EINVAL; + + return ret; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +int board_init(void) +{ + return 0; +} diff --git a/configs/stm32h747-disco_defconfig b/configs/stm32h747-disco_defconfig new file mode 100644 index 00000000000..8a0c72450d1 --- /dev/null +++ b/configs/stm32h747-disco_defconfig @@ -0,0 +1,35 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32=y +CONFIG_TEXT_BASE=0x08000000 +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x24040000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DEFAULT_DEVICE_TREE="st/stm32h747i-disco" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_LOAD_ADDR=0xd0400000 +CONFIG_STM32H7=y +CONFIG_TARGET_STM32H747_DISCO=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTDELAY=3 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" +CONFIG_AUTOBOOT_STOP_STR=" " +CONFIG_DEFAULT_FDT_FILE="stm32h747i-disco" +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NO_NET=y +CONFIG_STM32_SDMMC2=y +# CONFIG_PINCTRL_FULL is not set diff --git a/drivers/clk/stm32/clk-stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c index 6acf2ff0a8f..aa3be414a29 100644 --- a/drivers/clk/stm32/clk-stm32h7.c +++ b/drivers/clk/stm32/clk-stm32h7.c @@ -114,6 +114,7 @@ #define QSPISRC_PER_CK 3 #define PWR_CR3 0x0c +#define PWR_CR3_LDOEN BIT(1) #define PWR_CR3_SCUEN BIT(2) #define PWR_D3CR 0x18 #define PWR_D3CR_VOS_MASK GENMASK(15, 14) @@ -375,7 +376,11 @@ int configure_clocks(struct udevice *dev) clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK, VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT); /* Lock supply configuration update */ +#if IS_ENABLED(CONFIG_TARGET_STM32H747_DISCO) + clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_LDOEN); +#else clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN); +#endif while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY)) ; diff --git a/include/configs/stm32h747-disco.h b/include/configs/stm32h747-disco.h new file mode 100644 index 00000000000..393445a8ae1 --- /dev/null +++ b/include/configs/stm32h747-disco.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Dario Binacchi + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +/* For booting Linux, use the first 16MB of memory */ +#define CFG_SYS_BOOTMAPSZ SZ_16M + +#define CFG_SYS_FLASH_BASE 0x08000000 + +#define CFG_SYS_HZ_CLOCK 1000000 + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) + +#include +#define CFG_EXTRA_ENV_SETTINGS \ + "kernel_addr_r=0xD0008000\0" \ + "fdtfile=stm32h747i-disco.dtb\0" \ + "fdt_addr_r=0xD0408000\0" \ + "scriptaddr=0xD0418000\0" \ + "pxefile_addr_r=0xD0428000\0" \ + "ramdisk_addr_r=0xD0438000\0" \ + BOOTENV + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From b4b66e2f298e10d53749ce8d3ca086acbfc62f6a Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 28 May 2025 15:06:18 +0200 Subject: dm: core: use u32 instead of int for dev_read_u32_default dev_read_u32_default is for getting a u32 from a Device Tree property and allows to take a default value if that property is missing. Considering it calls ofnode_read_u32_default which takes a u32 and returns a u32, it should do the same instead of using an int, especially considering that int size is typically architecture-specific, as opposed to u32. This incidentally matches all other dev_read_*_default functions (except dev_read_s32_default which will be tackled in the next commit). Fixes: 47a0fd3bad38 ("dm: core: Implement live tree 'read' functions") Signed-off-by: Quentin Schulz Reviewed-by: Simon Glass --- drivers/core/read.c | 4 ++-- include/dm/read.h | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/drivers/core/read.c b/drivers/core/read.c index 55c19f335ae..981204bffe4 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -38,8 +38,8 @@ int dev_read_u32(const struct udevice *dev, const char *propname, u32 *outp) return ofnode_read_u32(dev_ofnode(dev), propname, outp); } -int dev_read_u32_default(const struct udevice *dev, const char *propname, - int def) +u32 dev_read_u32_default(const struct udevice *dev, const char *propname, + u32 def) { return ofnode_read_u32_default(dev_ofnode(dev), propname, def); } diff --git a/include/dm/read.h b/include/dm/read.h index 894bc698bb4..87017f07621 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -90,8 +90,8 @@ int dev_read_u32(const struct udevice *dev, const char *propname, u32 *outp); * @def: default value to return if the property has no value * Return: property value, or @def if not found */ -int dev_read_u32_default(const struct udevice *dev, const char *propname, - int def); +u32 dev_read_u32_default(const struct udevice *dev, const char *propname, + u32 def); /** * dev_read_u32_index() - read an indexed 32-bit integer from a device's DT @@ -896,7 +896,7 @@ static inline int dev_read_u32(const struct udevice *dev, } static inline int dev_read_u32_default(const struct udevice *dev, - const char *propname, int def) + const char *propname, u32 def) { return ofnode_read_u32_default(dev_ofnode(dev), propname, def); } -- cgit v1.3.1 From ad03050e26b1a61b3fe10a645a36da11652355e7 Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Wed, 28 May 2025 15:06:19 +0200 Subject: dm: core: use s32 instead of int for dev_read_s32_default dev_read_s32_default is for getting an s32 from a Device Tree property and allows to take a default value if that property is missing. Considering it calls ofnode_read_u32_default which takes a u32 and returns a u32, it should do the same instead of using an int, especially considering that int size is typically architecture-specific, as opposed to s32/u32. s32 and u32 being the same size, dev_read_s32* functions calling ofnode_read_u32_default shouldn't be an issue (at the type level at least) as the information will be stored appropriately in 4B regardless of the sign. This incidentally matches all other dev_read_*_default functions. Fixes: a1b17e4f4c82 ("dm: core: Add a function to read into a unsigned int") Signed-off-by: Quentin Schulz Reviewed-by: Simon Glass --- drivers/core/read.c | 4 ++-- include/dm/read.h | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/drivers/core/read.c b/drivers/core/read.c index 981204bffe4..c0d7a969db2 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -62,8 +62,8 @@ int dev_read_s32(const struct udevice *dev, const char *propname, s32 *outp) return ofnode_read_u32(dev_ofnode(dev), propname, (u32 *)outp); } -int dev_read_s32_default(const struct udevice *dev, const char *propname, - int def) +s32 dev_read_s32_default(const struct udevice *dev, const char *propname, + s32 def) { return ofnode_read_u32_default(dev_ofnode(dev), propname, def); } diff --git a/include/dm/read.h b/include/dm/read.h index 87017f07621..12dcde6645c 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -137,8 +137,8 @@ int dev_read_s32(const struct udevice *dev, const char *propname, s32 *outp); * @def: default value to return if the property has no value * Return: property value, or @def if not found */ -int dev_read_s32_default(const struct udevice *dev, const char *propname, - int def); +s32 dev_read_s32_default(const struct udevice *dev, const char *propname, + s32 def); /** * dev_read_u32u() - read a 32-bit integer from a device's DT property @@ -921,8 +921,8 @@ static inline int dev_read_s32(const struct udevice *dev, return ofnode_read_s32(dev_ofnode(dev), propname, outp); } -static inline int dev_read_s32_default(const struct udevice *dev, - const char *propname, int def) +static inline s32 dev_read_s32_default(const struct udevice *dev, + const char *propname, s32 def) { return ofnode_read_s32_default(dev_ofnode(dev), propname, def); } -- cgit v1.3.1 From 0805e4648686d5aa50b3990347b2b9f41dd42b3c Mon Sep 17 00:00:00 2001 From: Aristo Chen Date: Mon, 2 Jun 2025 02:18:02 +0000 Subject: bootstage: Fix typo Fix typo from heder to header Signed-off-by: Aristo Chen --- include/bootstage.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/bootstage.h b/include/bootstage.h index 3300ca0248a..528d0ca0614 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -73,7 +73,7 @@ enum bootstage_id { BOOTSTAGE_ID_CHECK_RAMDISK = 9, /* Checking ram disk */ BOOTSTAGE_ID_RD_MAGIC, /* Checking ram disk magic */ - BOOTSTAGE_ID_RD_HDR_CHECKSUM, /* Checking ram disk heder checksum */ + BOOTSTAGE_ID_RD_HDR_CHECKSUM, /* Checking ram disk header checksum */ BOOTSTAGE_ID_RD_CHECKSUM, /* Checking ram disk checksum */ BOOTSTAGE_ID_COPY_RAMDISK = 12, /* Copying ram disk into place */ BOOTSTAGE_ID_RAMDISK, /* Checking for valid ramdisk */ -- cgit v1.3.1 From a6e4fdfd77be4bd159cc73214bbf0a96df3aa551 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 28 May 2025 06:32:07 -0600 Subject: x86: Move Intel GNVS file into the common include directory Move this so we can include it from sandbox, needed since it is in a bloblist and must have a check. Signed-off-by: Simon Glass --- arch/x86/cpu/apollolake/acpi.c | 2 +- arch/x86/cpu/intel_common/acpi.c | 2 +- arch/x86/include/asm/arch-apollolake/global_nvs.h | 2 +- arch/x86/include/asm/intel_gnvs.h | 122 ---------------------- board/google/chromebook_coral/coral.c | 2 +- include/intel_gnvs.h | 122 ++++++++++++++++++++++ 6 files changed, 126 insertions(+), 126 deletions(-) delete mode 100644 arch/x86/include/asm/intel_gnvs.h create mode 100644 include/intel_gnvs.h (limited to 'include') diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c index 93040e7bb37..f32a10daedd 100644 --- a/arch/x86/cpu/apollolake/acpi.c +++ b/arch/x86/cpu/apollolake/acpi.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -20,7 +21,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/x86/cpu/intel_common/acpi.c b/arch/x86/cpu/intel_common/acpi.c index 982149b394e..8688232ec34 100644 --- a/arch/x86/cpu/intel_common/acpi.c +++ b/arch/x86/cpu/intel_common/acpi.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -23,7 +24,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/x86/include/asm/arch-apollolake/global_nvs.h b/arch/x86/include/asm/arch-apollolake/global_nvs.h index ef8eb228dbe..639d8f2de78 100644 --- a/arch/x86/include/asm/arch-apollolake/global_nvs.h +++ b/arch/x86/include/asm/arch-apollolake/global_nvs.h @@ -10,6 +10,6 @@ #ifndef _GLOBAL_NVS_H_ #define _GLOBAL_NVS_H_ -#include +#include #endif /* _GLOBAL_NVS_H_ */ diff --git a/arch/x86/include/asm/intel_gnvs.h b/arch/x86/include/asm/intel_gnvs.h deleted file mode 100644 index 0b69530edbf..00000000000 --- a/arch/x86/include/asm/intel_gnvs.h +++ /dev/null @@ -1,122 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2019 Intel Corporation. - * - * Taken from coreboot intelblocks/nvs.h - * Copyright 2019 Google LLC - */ - -#ifndef _INTEL_GNVS_H_ -#define _INTEL_GNVS_H_ - -#include -/* - * The chromeos_acpi portion of ACPI GNVS is assumed to live from offset - * 0x100 - 0x1000. When defining acpi_global_nvs, use check_member - * to ensure that it is properly aligned: - * - * check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); - */ -#define GNVS_CHROMEOS_ACPI_OFFSET 0x100 - -enum { - BOOT_REASON_OTHER = 0, - BOOT_REASON_S3DIAG = 9 -}; - -enum { - CHSW_RECOVERY_X86 = BIT(1), - CHSW_RECOVERY_EC = BIT(2), - CHSW_DEVELOPER_SWITCH = BIT(5), - CHSW_FIRMWARE_WP = BIT(9), -}; - -enum { - RECOVERY_REASON_NONE = 0, - RECOVERY_REASON_ME = 1 -}; - -enum { - ACTIVE_ECFW_RO = 0, - ACTIVE_ECFW_RW = 1 -}; - -enum { - BINF_RECOVERY = 0, - BINF_RW_A = 1, - BINF_RW_B = 2 -}; - -/** - * enum cros_fw_type_t - Used to indicate Chromium OS firmware type - * - * Chromium OS uses a region of the GNVS starting at offset 0x100 to store - * various bits of information, including the type of firmware being booted - */ -enum cros_fw_type_t { - FIRMWARE_TYPE_AUTO_DETECT = -1, - FIRMWARE_TYPE_RECOVERY = 0, - FIRMWARE_TYPE_NORMAL = 1, - FIRMWARE_TYPE_DEVELOPER = 2, - FIRMWARE_TYPE_NETBOOT = 3, - FIRMWARE_TYPE_LEGACY = 4, -}; - -struct __packed chromeos_acpi_gnvs { - /* ChromeOS-specific */ - u32 boot_reason; /* 00 boot reason */ - u32 active_main_fw; /* 04 (0=recovery, 1=A, 2=B) */ - u32 activeec_fw; /* 08 (0=RO, 1=RW) */ - u16 switches; /* 0c CHSW */ - u8 hwid[256]; /* 0e HWID */ - u8 fwid[64]; /* 10e FWID */ - u8 frid[64]; /* 14e FRID - 275 */ - u32 main_fw_type; /* 18e (2 = developer mode) */ - u32 recovery_reason; /* 192 recovery reason */ - u32 fmap_base; /* 196 fmap base address */ - u8 vdat[3072]; /* 19a VDAT space filled by verified boot */ - u32 fwid_ptr; /* d9a smbios bios version */ - u32 mehh[8]; /* d9e management engine hash */ - u32 ramoops_base; /* dbe ramoops base address */ - u32 ramoops_len; /* dc2 ramoops length */ - u32 vpd_ro_base; /* dc6 pointer to RO_VPD */ - u32 vpd_ro_size; /* dca size of RO_VPD */ - u32 vpd_rw_base; /* dce pointer to RW_VPD */ - u32 vpd_rw_size; /* dd2 size of RW_VPD */ - u8 pad[298]; /* dd6-eff */ -}; - -struct __packed acpi_global_nvs { - /* Miscellaneous */ - u8 pcnt; /* 0x00 - Processor Count */ - u8 ppcm; /* 0x01 - Max PPC State */ - u8 lids; /* 0x02 - LID State */ - u8 pwrs; /* 0x03 - AC Power State */ - u8 dpte; /* 0x04 - Enable DPTF */ - u32 cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ - u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ - u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */ - u64 nhla; /* 0x19 - 0x20 - NHLT Address */ - u32 nhll; /* 0x21 - 0x24 - NHLT Length */ - u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */ - u8 scdp; /* 0x29 - SD_CD GPIO portid */ - u8 scdo; /* 0x2a - GPIO pad offset relative to the community */ - u8 uior; /* 0x2b - UART debug controller init on S3 resume */ - u8 ecps; /* 0x2c - SGX Enabled status */ - u64 emna; /* 0x2d - 0x34 EPC base address */ - u64 elng; /* 0x35 - 0x3C EPC Length */ - u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */ -#ifdef CONFIG_CHROMEOS - /* ChromeOS-specific (0x100 - 0xfff) */ - struct chromeos_acpi_gnvs chromeos; -#else - u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */ -#endif -}; -#ifdef CONFIG_CHROMEOS -check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); -#else -check_member(acpi_global_nvs, unused2, GNVS_CHROMEOS_ACPI_OFFSET); -#endif - -#endif /* _INTEL_GNVS_H_ */ diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index db96534857c..b4053fa097d 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -11,13 +11,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include #include #include #include diff --git a/include/intel_gnvs.h b/include/intel_gnvs.h new file mode 100644 index 00000000000..0b69530edbf --- /dev/null +++ b/include/intel_gnvs.h @@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Intel Corporation. + * + * Taken from coreboot intelblocks/nvs.h + * Copyright 2019 Google LLC + */ + +#ifndef _INTEL_GNVS_H_ +#define _INTEL_GNVS_H_ + +#include +/* + * The chromeos_acpi portion of ACPI GNVS is assumed to live from offset + * 0x100 - 0x1000. When defining acpi_global_nvs, use check_member + * to ensure that it is properly aligned: + * + * check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); + */ +#define GNVS_CHROMEOS_ACPI_OFFSET 0x100 + +enum { + BOOT_REASON_OTHER = 0, + BOOT_REASON_S3DIAG = 9 +}; + +enum { + CHSW_RECOVERY_X86 = BIT(1), + CHSW_RECOVERY_EC = BIT(2), + CHSW_DEVELOPER_SWITCH = BIT(5), + CHSW_FIRMWARE_WP = BIT(9), +}; + +enum { + RECOVERY_REASON_NONE = 0, + RECOVERY_REASON_ME = 1 +}; + +enum { + ACTIVE_ECFW_RO = 0, + ACTIVE_ECFW_RW = 1 +}; + +enum { + BINF_RECOVERY = 0, + BINF_RW_A = 1, + BINF_RW_B = 2 +}; + +/** + * enum cros_fw_type_t - Used to indicate Chromium OS firmware type + * + * Chromium OS uses a region of the GNVS starting at offset 0x100 to store + * various bits of information, including the type of firmware being booted + */ +enum cros_fw_type_t { + FIRMWARE_TYPE_AUTO_DETECT = -1, + FIRMWARE_TYPE_RECOVERY = 0, + FIRMWARE_TYPE_NORMAL = 1, + FIRMWARE_TYPE_DEVELOPER = 2, + FIRMWARE_TYPE_NETBOOT = 3, + FIRMWARE_TYPE_LEGACY = 4, +}; + +struct __packed chromeos_acpi_gnvs { + /* ChromeOS-specific */ + u32 boot_reason; /* 00 boot reason */ + u32 active_main_fw; /* 04 (0=recovery, 1=A, 2=B) */ + u32 activeec_fw; /* 08 (0=RO, 1=RW) */ + u16 switches; /* 0c CHSW */ + u8 hwid[256]; /* 0e HWID */ + u8 fwid[64]; /* 10e FWID */ + u8 frid[64]; /* 14e FRID - 275 */ + u32 main_fw_type; /* 18e (2 = developer mode) */ + u32 recovery_reason; /* 192 recovery reason */ + u32 fmap_base; /* 196 fmap base address */ + u8 vdat[3072]; /* 19a VDAT space filled by verified boot */ + u32 fwid_ptr; /* d9a smbios bios version */ + u32 mehh[8]; /* d9e management engine hash */ + u32 ramoops_base; /* dbe ramoops base address */ + u32 ramoops_len; /* dc2 ramoops length */ + u32 vpd_ro_base; /* dc6 pointer to RO_VPD */ + u32 vpd_ro_size; /* dca size of RO_VPD */ + u32 vpd_rw_base; /* dce pointer to RW_VPD */ + u32 vpd_rw_size; /* dd2 size of RW_VPD */ + u8 pad[298]; /* dd6-eff */ +}; + +struct __packed acpi_global_nvs { + /* Miscellaneous */ + u8 pcnt; /* 0x00 - Processor Count */ + u8 ppcm; /* 0x01 - Max PPC State */ + u8 lids; /* 0x02 - LID State */ + u8 pwrs; /* 0x03 - AC Power State */ + u8 dpte; /* 0x04 - Enable DPTF */ + u32 cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ + u64 pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ + u64 gpei; /* 0x11 - 0x18 - GPE Wake Source */ + u64 nhla; /* 0x19 - 0x20 - NHLT Address */ + u32 nhll; /* 0x21 - 0x24 - NHLT Length */ + u32 prt0; /* 0x25 - 0x28 - PERST_0 Address */ + u8 scdp; /* 0x29 - SD_CD GPIO portid */ + u8 scdo; /* 0x2a - GPIO pad offset relative to the community */ + u8 uior; /* 0x2b - UART debug controller init on S3 resume */ + u8 ecps; /* 0x2c - SGX Enabled status */ + u64 emna; /* 0x2d - 0x34 EPC base address */ + u64 elng; /* 0x35 - 0x3C EPC Length */ + u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */ +#ifdef CONFIG_CHROMEOS + /* ChromeOS-specific (0x100 - 0xfff) */ + struct chromeos_acpi_gnvs chromeos; +#else + u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */ +#endif +}; +#ifdef CONFIG_CHROMEOS +check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET); +#else +check_member(acpi_global_nvs, unused2, GNVS_CHROMEOS_ACPI_OFFSET); +#endif + +#endif /* _INTEL_GNVS_H_ */ -- cgit v1.3.1 From f73450918d66565c5efacf2bb57227ba94bdaa40 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 28 May 2025 06:32:08 -0600 Subject: spl: Rename jump_to_image_no_args() This function is currently a misnomer at times as we have cases where it passes arguments to the image. In preparation for making that be a more common case rename this function to jump_to_image(...). In order to do this, rename jump_to_image in board_init_r(...) to jumper so that we do not have a conflict. Signed-off-by: Simon Glass [trini: Reword the commit message, adding missing cases of jump_to_image_no_args()] Signed-off-by: Tom Rini --- arch/arm/mach-imx/imx8ulp/soc.c | 2 +- arch/arm/mach-imx/spl.c | 2 +- arch/arm/mach-k3/r5/common.c | 2 +- arch/arm/mach-omap2/boot-common.c | 2 +- arch/arm/mach-stm32mp/stm32mp1/cpu.c | 2 +- arch/arm/mach-tegra/spl.c | 2 +- arch/mips/lib/spl.c | 2 +- arch/riscv/lib/spl.c | 2 +- arch/sandbox/cpu/spl.c | 6 +++--- arch/x86/lib/spl.c | 2 +- arch/x86/lib/tpl.c | 2 +- board/freescale/common/fsl_chain_of_trust.c | 2 +- board/renesas/common/rcar64-spl.c | 2 +- common/spl/spl.c | 16 ++++++++-------- drivers/usb/gadget/f_sdp.c | 2 +- include/spl.h | 2 +- 16 files changed, 25 insertions(+), 25 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index b5dc45296d1..2b042300103 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -806,7 +806,7 @@ int imx8ulp_dm_post_init(void) EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8ulp_dm_post_init); #if defined(CONFIG_XPL_BUILD) -__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +__weak void __noreturn jump_to_image(struct spl_image_info *spl_image) { debug("image entry point: 0x%lx\n", spl_image->entry_point); diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index bc291dcd129..518d9cb1262 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -276,7 +276,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) * +------------+ + CSF_PAD_SIZE */ -__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +__weak void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); uint32_t offset; diff --git a/arch/arm/mach-k3/r5/common.c b/arch/arm/mach-k3/r5/common.c index fa146549f13..6ac2973bd67 100644 --- a/arch/arm/mach-k3/r5/common.c +++ b/arch/arm/mach-k3/r5/common.c @@ -137,7 +137,7 @@ void release_resources_for_core_shutdown(void) } } -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); struct ti_sci_handle *ti_sci = get_ti_sci_handle(); diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index ddd7eeaf052..95b44c8b1e5 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -291,7 +291,7 @@ void spl_soc_init(void) spl_boot_ipu(); } -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(u32 *); image_entry_noargs_t image_entry = diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 9ab5a3ede52..8c09d91de05 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -349,7 +349,7 @@ uintptr_t get_stm32mp_bl2_dtb(void) } #ifdef CONFIG_XPL_BUILD -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_stm32_t)(u32 romapi); uintptr_t romapi = get_stm32mp_rom_api_table(); diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index 5df0eb28c96..b3a039217c2 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -43,7 +43,7 @@ u32 spl_boot_device(void) return BOOT_DEVICE_RAM; } -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { debug("image entry point: 0x%lX\n", spl_image->entry_point); diff --git a/arch/mips/lib/spl.c b/arch/mips/lib/spl.c index b4087546dd1..4949b17bd59 100644 --- a/arch/mips/lib/spl.c +++ b/arch/mips/lib/spl.c @@ -7,7 +7,7 @@ #include #include -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); image_entry_noargs_t image_entry = diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c index 9a7a4f6ac8d..38a5ab27dd8 100644 --- a/arch/riscv/lib/spl.c +++ b/arch/riscv/lib/spl.c @@ -36,7 +36,7 @@ __weak void board_init_f(ulong dummy) panic("spl_board_init_f() failed: %d\n", ret); } -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_riscv_t)(ulong hart, void *dtb); void *fdt_blob; diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c index ecc03785463..7ee4975523e 100644 --- a/arch/sandbox/cpu/spl.c +++ b/arch/sandbox/cpu/spl.c @@ -74,7 +74,7 @@ static int spl_board_load_file(struct spl_image_info *spl_image, } /* - * Set up spl_image to boot from jump_to_image_no_args(). Allocate this + * Set up spl_image to boot from jump_to_image(). Allocate this * outsdide the RAM buffer (i.e. don't use strdup()). */ spl_image->arg = os_malloc(strlen(fname) + 1); @@ -112,7 +112,7 @@ static int load_from_image(struct spl_image_info *spl_image, log_info("Reading from pos %lx size %lx\n", pos, size); /* - * Set up spl_image to boot from jump_to_image_no_args(). Allocate this + * Set up spl_image to boot from jump_to_image(). Allocate this * outside the RAM buffer (i.e. don't use strdup()). */ fname = state->prog_fname ? state->prog_fname : state->argv[0]; @@ -159,7 +159,7 @@ void spl_board_init(void) } } -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { switch (spl_image->flags) { case SPL_SANDBOXF_ARG_IS_FNAME: { diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index 6a6cad310bc..01ff034d665 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -277,7 +277,7 @@ int spl_spi_load_image(void) } #ifdef CONFIG_X86_RUN_64BIT -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { int ret; diff --git a/arch/x86/lib/tpl.c b/arch/x86/lib/tpl.c index f7df7e03621..06c9e4d02c1 100644 --- a/arch/x86/lib/tpl.c +++ b/arch/x86/lib/tpl.c @@ -101,7 +101,7 @@ int spl_spi_load_image(void) return -EPERM; } -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { debug("Jumping to %s at %lx\n", xpl_name(xpl_next_phase()), (ulong)spl_image->entry_point); diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 194a0907e72..3d44357caf7 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -134,7 +134,7 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) /* Override weak funtion defined in SPL framework to enable validation * of main u-boot image before jumping to u-boot image. */ -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); uint32_t hdr_addr; diff --git a/board/renesas/common/rcar64-spl.c b/board/renesas/common/rcar64-spl.c index 76f2bde924e..d8f05d2ffbe 100644 --- a/board/renesas/common/rcar64-spl.c +++ b/board/renesas/common/rcar64-spl.c @@ -6,7 +6,7 @@ #include #include -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +void __noreturn jump_to_image(struct spl_image_info *spl_image) { debug("image entry point: 0x%lx\n", spl_image->entry_point); if (spl_image->os == IH_OS_ARM_TRUSTED_FIRMWARE) { diff --git a/common/spl/spl.c b/common/spl/spl.c index 76fd56dfe4b..d8e26605d20 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -392,7 +392,7 @@ int spl_load(struct spl_image_info *spl_image, } #endif -__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +__weak void __noreturn jump_to_image(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); @@ -689,7 +689,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) BOOT_DEVICE_NONE, BOOT_DEVICE_NONE, }; - spl_jump_to_image_t jump_to_image = &jump_to_image_no_args; + spl_jump_to_image_t jumper = &jump_to_image; struct spl_image_info spl_image; int ret, os; @@ -783,20 +783,20 @@ void board_init_r(gd_t *dummy1, ulong dummy2) } else if (CONFIG_IS_ENABLED(ATF) && os == IH_OS_ARM_TRUSTED_FIRMWARE) { debug("Jumping to U-Boot via ARM Trusted Firmware\n"); spl_fixup_fdt(spl_image_fdt_addr(&spl_image)); - jump_to_image = &spl_invoke_atf; + jumper = &spl_invoke_atf; } else if (CONFIG_IS_ENABLED(OPTEE_IMAGE) && os == IH_OS_TEE) { debug("Jumping to U-Boot via OP-TEE\n"); spl_board_prepare_for_optee(spl_image_fdt_addr(&spl_image)); - jump_to_image = &jump_to_image_optee; + jumper = &jump_to_image_optee; } else if (CONFIG_IS_ENABLED(OPENSBI) && os == IH_OS_OPENSBI) { debug("Jumping to U-Boot via RISC-V OpenSBI\n"); - jump_to_image = &spl_invoke_opensbi; + jumper = &spl_invoke_opensbi; } else if (CONFIG_IS_ENABLED(OS_BOOT) && os == IH_OS_LINUX) { debug("Jumping to Linux\n"); if (IS_ENABLED(CONFIG_SPL_OS_BOOT)) spl_fixup_fdt((void *)SPL_PAYLOAD_ARGS_ADDR); spl_board_prepare_for_linux(); - jump_to_image = &jump_to_image_linux; + jumper = &jump_to_image_linux; } else { debug("Unsupported OS image.. Jumping nevertheless..\n"); } @@ -848,7 +848,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) if (CONFIG_IS_ENABLED(RELOC_LOADER)) { int ret; - ret = spl_reloc_jump(&spl_image, jump_to_image); + ret = spl_reloc_jump(&spl_image, jumper); if (ret) { if (xpl_phase() == PHASE_VPL) printf("jump failed %d\n", ret); @@ -856,7 +856,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2) } } - jump_to_image(&spl_image); + jumper(&spl_image); } /* diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index 36934b1bcf7..647001d8dd0 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -863,7 +863,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, struct spl_boot_device bootdev = {}; spl_parse_image_header(&spl_image, &bootdev, header); spl_board_prepare_for_boot(); - jump_to_image_no_args(&spl_image); + jump_to_image(&spl_image); #else /* In U-Boot, allow jumps to scripts */ cmd_source_script(sdp_func->jmp_address, NULL, NULL); diff --git a/include/spl.h b/include/spl.h index 850c64d4b19..7c10c7f792e 100644 --- a/include/spl.h +++ b/include/spl.h @@ -865,7 +865,7 @@ int spl_load_image_fat_os(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, struct blk_desc *block_dev, int partition); -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image); +void __noreturn jump_to_image(struct spl_image_info *spl_image); /* SPL EXT image functions */ int spl_load_image_ext(struct spl_image_info *spl_image, -- cgit v1.3.1 From 0230ad1c30a405c807dad5f78c95c57704234ffd Mon Sep 17 00:00:00 2001 From: E Shattow Date: Fri, 6 Jun 2025 15:45:02 -0700 Subject: include: use lowercase hex prefix style Use consistent lowercase hex prefix style in include/* Signed-off-by: E Shattow --- include/fsl_esdhc.h | 2 +- include/fsl_esdhc_imx.h | 2 +- include/mc13892.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 7ab1460abc6..d1f441e19b5 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -88,7 +88,7 @@ #define PRSSTAT_CINS (0x00010000) #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) -#define PRSSTAT_SDSTB (0X00000008) +#define PRSSTAT_SDSTB (0x00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) #define PRSSTAT_CIDHB (0x00000001) diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h index 8612b56609e..cd8ed833771 100644 --- a/include/fsl_esdhc_imx.h +++ b/include/fsl_esdhc_imx.h @@ -97,7 +97,7 @@ #define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BWEN (0x00000400) #define PRSSTAT_SDOFF (0x00000080) -#define PRSSTAT_SDSTB (0X00000008) +#define PRSSTAT_SDSTB (0x00000008) #define PRSSTAT_DLA (0x00000004) #define PRSSTAT_CICHB (0x00000002) #define PRSSTAT_CIDHB (0x00000001) diff --git a/include/mc13892.h b/include/mc13892.h index d9ef53b1e48..a044a4c606d 100644 --- a/include/mc13892.h +++ b/include/mc13892.h @@ -161,7 +161,7 @@ /* SWx Output Volts */ #define SWX_OUT_MASK 0x1F #define SWX_OUT_1_25 0x1A -#define SWX_OUT_1_30 0X1C +#define SWX_OUT_1_30 0x1C /* Buck Switchers (SW1,2,3,4) Output Voltage */ /* -- cgit v1.3.1 From 01cc7046ad2a1537791cda5175bce281f0a0acfc Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 7 Jun 2025 23:11:20 +0200 Subject: linux/bitfield.h: sync from Linux 6.15 Sync bitfield.h header with Linux 6.15 version. Mainly is to permit the introduction of FIELD_PREP_CONST. The bug.h header changed to build_bug.h doesn't cause any regression as we also ship split header similar to how it's done with in Linux. Signed-off-by: Christian Marangi --- include/linux/bitfield.h | 103 ++++++++++++++++++++++++++++++++++------------- 1 file changed, 75 insertions(+), 28 deletions(-) (limited to 'include') diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h index 7ad02f8cbb9..63928f17322 100644 --- a/include/linux/bitfield.h +++ b/include/linux/bitfield.h @@ -1,21 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2014 Felix Fietkau * Copyright (C) 2004 - 2009 Ivo van Doorn - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 - * as published by the Free Software Foundation - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #ifndef _LINUX_BITFIELD_H #define _LINUX_BITFIELD_H -#include +#include #include /* @@ -27,6 +19,9 @@ * * Example: * + * #include + * #include + * * #define REG_FIELD_A GENMASK(6, 0) * #define REG_FIELD_B BIT(7) * #define REG_FIELD_C GENMASK(15, 8) @@ -49,20 +44,51 @@ #define __bf_shf(x) (__builtin_ffsll(x) - 1) +#define __scalar_type_to_unsigned_cases(type) \ + unsigned type: (unsigned type)0, \ + signed type: (unsigned type)0 + +#define __unsigned_scalar_typeof(x) typeof( \ + _Generic((x), \ + char: (unsigned char)0, \ + __scalar_type_to_unsigned_cases(char), \ + __scalar_type_to_unsigned_cases(short), \ + __scalar_type_to_unsigned_cases(int), \ + __scalar_type_to_unsigned_cases(long), \ + __scalar_type_to_unsigned_cases(long long), \ + default: (x))) + +#define __bf_cast_unsigned(type, x) ((__unsigned_scalar_typeof(type))(x)) + #define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx) \ ({ \ BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \ _pfx "mask is not constant"); \ - BUILD_BUG_ON_MSG(!(_mask), _pfx "mask is zero"); \ + BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); \ BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \ - ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \ + ~((_mask) >> __bf_shf(_mask)) & \ + (0 + (_val)) : 0, \ _pfx "value too large for the field"); \ - BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \ + BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \ + __bf_cast_unsigned(_reg, ~0ull), \ _pfx "type of reg too small for mask"); \ __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \ (1ULL << __bf_shf(_mask))); \ }) +/** + * FIELD_MAX() - produce the maximum value representable by a field + * @_mask: shifted mask defining the field's length and position + * + * FIELD_MAX() returns the maximum value that can be held in the field + * specified by @_mask. + */ +#define FIELD_MAX(_mask) \ + ({ \ + __BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_MAX: "); \ + (typeof(_mask))((_mask) >> __bf_shf(_mask)); \ + }) + /** * FIELD_FIT() - check if value fits in the field * @_mask: shifted mask defining the field's length and position @@ -72,7 +98,7 @@ */ #define FIELD_FIT(_mask, _val) \ ({ \ - __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_FIT: "); \ + __BF_FIELD_CHECK(_mask, 0ULL, 0ULL, "FIELD_FIT: "); \ !((((typeof(_mask))_val) << __bf_shf(_mask)) & ~(_mask)); \ }) @@ -90,10 +116,36 @@ ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ }) +#define __BF_CHECK_POW2(n) BUILD_BUG_ON_ZERO(((n) & ((n) - 1)) != 0) + +/** + * FIELD_PREP_CONST() - prepare a constant bitfield element + * @_mask: shifted mask defining the field's length and position + * @_val: value to put in the field + * + * FIELD_PREP_CONST() masks and shifts up the value. The result should + * be combined with other fields of the bitfield using logical OR. + * + * Unlike FIELD_PREP() this is a constant expression and can therefore + * be used in initializers. Error checking is less comfortable for this + * version, and non-constant masks cannot be used. + */ +#define FIELD_PREP_CONST(_mask, _val) \ + ( \ + /* mask must be non-zero */ \ + BUILD_BUG_ON_ZERO((_mask) == 0) + \ + /* check if value fits */ \ + BUILD_BUG_ON_ZERO(~((_mask) >> __bf_shf(_mask)) & (_val)) + \ + /* check if mask is contiguous */ \ + __BF_CHECK_POW2((_mask) + (1ULL << __bf_shf(_mask))) + \ + /* and create the value */ \ + (((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask)) \ + ) + /** * FIELD_GET() - extract a bitfield element * @_mask: shifted mask defining the field's length and position - * @_reg: 32bit value of entire bitfield + * @_reg: value of entire bitfield * * FIELD_GET() extracts the field specified by @_mask from the * bitfield passed in as @_reg by masking and shifting it down. @@ -108,20 +160,18 @@ extern void __compiletime_error("value doesn't fit into mask") __field_overflow(void); extern void __compiletime_error("bad bitfield mask") __bad_mask(void); - static __always_inline u64 field_multiplier(u64 field) { if ((field | (field - 1)) & ((field | (field - 1)) + 1)) __bad_mask(); return field & -field; } - static __always_inline u64 field_mask(u64 field) { return field / field_multiplier(field); } - -#define ____MAKE_OP(type, base, to, from) \ +#define field_max(field) ((typeof(field))field_mask(field)) +#define ____MAKE_OP(type,base,to,from) \ static __always_inline __##type type##_encode_bits(base v, base field) \ { \ if (__builtin_constant_p(v) && (v & ~field_mask(field))) \ @@ -133,26 +183,23 @@ static __always_inline __##type type##_replace_bits(__##type old, \ { \ return (old & ~to(field)) | type##_encode_bits(val, field); \ } \ -static __always_inline void type##p_replace_bits(__##type * p, \ +static __always_inline void type##p_replace_bits(__##type *p, \ base val, base field) \ { \ *p = (*p & ~to(field)) | type##_encode_bits(val, field); \ } \ static __always_inline base type##_get_bits(__##type v, base field) \ { \ - return (from(v) & field) / field_multiplier(field); \ + return (from(v) & field)/field_multiplier(field); \ } - #define __MAKE_OP(size) \ - ____MAKE_OP(le##size, u##size, cpu_to_le##size, le##size##_to_cpu) \ - ____MAKE_OP(be##size, u##size, cpu_to_be##size, be##size##_to_cpu) \ - ____MAKE_OP(u##size, u##size, ,) - -____MAKE_OP(u8, u8, ,) + ____MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \ + ____MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \ + ____MAKE_OP(u##size,u##size,,) +____MAKE_OP(u8,u8,,) __MAKE_OP(16) __MAKE_OP(32) __MAKE_OP(64) - #undef __MAKE_OP #undef ____MAKE_OP -- cgit v1.3.1 From 9d7f90782d0a768af76718e0cbc17c954d6731e5 Mon Sep 17 00:00:00 2001 From: Lukasz Majewski Date: Fri, 6 Jun 2025 12:38:38 +0200 Subject: ARM: imx: mxs: Add support for imx287 based BTT devices The btt[c3] devices are based on imx287 SoC. U-Boot SPL 2025.04-01081-g07e086681d26 (Apr 16 2025 - 12:24:36 +0200) Trying to boot from MMC1 U-Boot 2025.04-01081-g07e086681d26 (Apr 16 2025 - 12:24:36 +0200) CPU: Freescale i.MX28 rev1.2 at 454 MHz BOOT: SSP SPI #3, master, 3V3 NOR Model: BTT3 Board: LWE BTT SoM HW rev 0 DRAM: 256 MiB Core: 86 devices, 15 uclasses, devicetree: separate MMC: MXS MMC: 0 Loading Environment from SPIFlash... SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 16 MiB OK In: serial@80074000 Out: serial@80074000 Err: serial@80074000 Net: eth0: ethernet@800f0000 Hit any key to stop autoboot: 0 Signed-off-by: Lukasz Majewski --- arch/arm/dts/imx28-btt3-0-u-boot.dtsi | 7 + arch/arm/dts/imx28-btt3-1-u-boot.dtsi | 7 + arch/arm/dts/imx28-btt3-2-u-boot.dtsi | 7 + arch/arm/dts/imx28-btt3-u-boot.dtsi | 90 +++++++ arch/arm/mach-imx/mxs/Kconfig | 6 + board/liebherr/btt/Kconfig | 24 ++ board/liebherr/btt/MAINTAINERS | 6 + board/liebherr/btt/Makefile | 9 + board/liebherr/btt/boot_img_scr.h | 27 ++ board/liebherr/btt/btt.c | 451 ++++++++++++++++++++++++++++++++++ board/liebherr/btt/btt.env | 139 +++++++++++ board/liebherr/btt/spl_btt.c | 347 ++++++++++++++++++++++++++ configs/imx28_btt3_defconfig | 140 +++++++++++ doc/board/index.rst | 1 + doc/board/liebherr/btt.rst | 34 +++ doc/board/liebherr/index.rst | 9 + include/configs/btt.h | 18 ++ 17 files changed, 1322 insertions(+) create mode 100644 arch/arm/dts/imx28-btt3-0-u-boot.dtsi create mode 100644 arch/arm/dts/imx28-btt3-1-u-boot.dtsi create mode 100644 arch/arm/dts/imx28-btt3-2-u-boot.dtsi create mode 100644 arch/arm/dts/imx28-btt3-u-boot.dtsi create mode 100644 board/liebherr/btt/Kconfig create mode 100644 board/liebherr/btt/MAINTAINERS create mode 100644 board/liebherr/btt/Makefile create mode 100644 board/liebherr/btt/boot_img_scr.h create mode 100644 board/liebherr/btt/btt.c create mode 100644 board/liebherr/btt/btt.env create mode 100644 board/liebherr/btt/spl_btt.c create mode 100644 configs/imx28_btt3_defconfig create mode 100644 doc/board/liebherr/btt.rst create mode 100644 doc/board/liebherr/index.rst create mode 100644 include/configs/btt.h (limited to 'include') diff --git a/arch/arm/dts/imx28-btt3-0-u-boot.dtsi b/arch/arm/dts/imx28-btt3-0-u-boot.dtsi new file mode 100644 index 00000000000..b128eef9e17 --- /dev/null +++ b/arch/arm/dts/imx28-btt3-0-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include "imx28-btt3-u-boot.dtsi" diff --git a/arch/arm/dts/imx28-btt3-1-u-boot.dtsi b/arch/arm/dts/imx28-btt3-1-u-boot.dtsi new file mode 100644 index 00000000000..b128eef9e17 --- /dev/null +++ b/arch/arm/dts/imx28-btt3-1-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include "imx28-btt3-u-boot.dtsi" diff --git a/arch/arm/dts/imx28-btt3-2-u-boot.dtsi b/arch/arm/dts/imx28-btt3-2-u-boot.dtsi new file mode 100644 index 00000000000..b128eef9e17 --- /dev/null +++ b/arch/arm/dts/imx28-btt3-2-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include "imx28-btt3-u-boot.dtsi" diff --git a/arch/arm/dts/imx28-btt3-u-boot.dtsi b/arch/arm/dts/imx28-btt3-u-boot.dtsi new file mode 100644 index 00000000000..3569d29a737 --- /dev/null +++ b/arch/arm/dts/imx28-btt3-u-boot.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +/* + * The minimal augmentation DTS U-Boot file to allow eMMC driver + * configuration in SPL for falcon boot. + */ +#include "imx28-u-boot.dtsi" +/ { + aliases { + /delete-property/ saif0; + /delete-property/ saif1; + /delete-property/ spi0; + /delete-property/ spi1; + /delete-property/ usbphy0; + /delete-property/ usbphy1; + }; + apb@80000000 { + bootph-pre-ram; + + apbh@80000000 { + bootph-pre-ram; + }; + + apbx@80040000 { + bootph-pre-ram; + }; + }; + + /delete-node/ keypad; + /delete-node/ panel; + /delete-node/ sdio-pwrseq; + /delete-node/ sound; +}; + +&clks { + bootph-pre-ram; + status = "disable"; +}; + +&duart { + /delete-property/ clocks; + bootph-pre-ram; + type = <1>; /* TYPE_PL011 */ +}; + +&gpio0 { + bootph-pre-ram; +}; + +&gpio3 { + bootph-pre-ram; +}; + +&gpio4 { + bootph-pre-ram; +}; + +&pinctrl { + /delete-property/ pinctrl-names; + /delete-property/ pinctrl-0; + bootph-pre-ram; +}; + +&ssp0 { + bootph-pre-ram; +}; + +&ssp3 { + num-cs = <2>; + spi-max-frequency = <40000000>; + bootph-pre-ram; +}; + +/delete-node/ &hog_pins_a; +/delete-node/ &keypad_pins_bttc; +/delete-node/ &lcdif; +/delete-node/ &lcdif_sync_pins_bttc; +/delete-node/ &pwm; +/delete-node/ &saif0; +/delete-node/ &saif1; +/delete-node/ &ssp1; +/delete-node/ &ssp2; +/delete-node/ &usb0; +/delete-node/ &usb1; +/delete-node/ &usbphy0; +/delete-node/ &usbphy1; diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig index d2e4205c5ce..b134d04b210 100644 --- a/arch/arm/mach-imx/mxs/Kconfig +++ b/arch/arm/mach-imx/mxs/Kconfig @@ -38,6 +38,11 @@ choice prompt "MX28 board select" optional +config TARGET_BTT + bool "Support BTT" + select PL01X_SERIAL + imply OF_UPSTREAM + config TARGET_MX28EVK bool "Support mx28evk" select PL01X_SERIAL @@ -70,6 +75,7 @@ config SPL_MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR from VDD5V) - so the VDD4P2 power source is operational. source "board/freescale/mx28evk/Kconfig" +source "board/liebherr/btt/Kconfig" source "board/liebherr/xea/Kconfig" endif diff --git a/board/liebherr/btt/Kconfig b/board/liebherr/btt/Kconfig new file mode 100644 index 00000000000..ff35dd04532 --- /dev/null +++ b/board/liebherr/btt/Kconfig @@ -0,0 +1,24 @@ +if TARGET_BTT + +config SYS_BOARD + default "btt" + +config SYS_VENDOR + default "liebherr" + +config SYS_SOC + default "mxs" + +config SYS_CONFIG_NAME + default "btt" + +config ENV_SIZE + default 0x2000 + +config ENV_SECT_SIZE + default 0x10000 if ENV_IS_IN_SPI_FLASH + +config ENV_OFFSET + default 0x80000 if ENV_IS_IN_SPI_FLASH + +endif diff --git a/board/liebherr/btt/MAINTAINERS b/board/liebherr/btt/MAINTAINERS new file mode 100644 index 00000000000..b4afed5aaeb --- /dev/null +++ b/board/liebherr/btt/MAINTAINERS @@ -0,0 +1,6 @@ +BTT BOARD +M: Lukasz Majewski +S: Maintained +F: board/liebherr/btt/ +F: include/configs/btt.h +F: configs/imx28_btt3_defconfig diff --git a/board/liebherr/btt/Makefile b/board/liebherr/btt/Makefile new file mode 100644 index 00000000000..a8ab657a9e0 --- /dev/null +++ b/board/liebherr/btt/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2025 +# Lukasz Majewski, DENX Software Engineering, lukma@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := btt.o +obj-$(CONFIG_XPL_BUILD) += spl_btt.o diff --git a/board/liebherr/btt/boot_img_scr.h b/board/liebherr/btt/boot_img_scr.h new file mode 100644 index 00000000000..baa3072b49c --- /dev/null +++ b/board/liebherr/btt/boot_img_scr.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Struct for boot image source description for placing in last + * two SPI NOR flash sectors on legcom. + */ + +struct boot_img_src { + u8 magic; /* Must be 'B' = 0x42 */ + u8 flags; /* flags to specify mmcblk[0|1] boot[0|1] */ + u8 crc8; /* CRC-8 over above two bytes */ +} __packed; + +/* + * Bit definition in boot_img_src.flags: + * Bit 0: mmcblk device 0 or 1 (1 - if this bit set) + * Bit 1: mmcblk boot partition 0 or 1. + * for eMMC: boot0 if this bit is cleared, boot1 - if set + * for SD-card the boot partition value will always be 0 + * (independent of the value of this bit) + * + */ +#define BOOT_SRC_MMC1 BIT(0) +#define BOOT_SRC_PART1 BIT(1) + +/* Offset of the first boot image source descriptor in SPI NOR */ +#define SPI_FLASH_BOOT_SRC_OFFS 0xFE0000 +#define SPI_FLASH_SECTOR_SIZE 0x10000 diff --git a/board/liebherr/btt/btt.c b/board/liebherr/btt/btt.c new file mode 100644 index 00000000000..e05e333ac7e --- /dev/null +++ b/board/liebherr/btt/btt.c @@ -0,0 +1,451 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * BTT[3C] iMX28 board + * + * Copyright (C) 2025 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "boot_img_scr.h" + +#include +#include + +#ifdef CONFIG_XPL_BUILD +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ + +static void init_clocks(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* SSP2 clock at 160MHz */ + mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); + /* SSP3 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK3, 96000, 0); +} + +#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) +void board_init_f(ulong arg) +{ + init_clocks(); + spl_early_init(); + preloader_console_init(); +} + +static struct boot_img_src img_src[2]; +static int spi_load_boot_info(void) +{ + struct spi_flash *flash; + int err; + + flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS, + CONFIG_SF_DEFAULT_CS, + CONFIG_SF_DEFAULT_SPEED, + CONFIG_SF_DEFAULT_MODE); + if (!flash) { + printf("%s: SPI probe err\n", __func__); + return -ENODEV; + } + + /* + * Load both boot info structs from SPI flash + */ + err = spi_flash_read(flash, SPI_FLASH_BOOT_SRC_OFFS, + sizeof(img_src[0]), + (void *)&img_src[0]); + if (err) { + debug("%s: First boot info NOR sector read error %d\n", + __func__, err); + return err; + } + + err = spi_flash_read(flash, + SPI_FLASH_BOOT_SRC_OFFS + SPI_FLASH_SECTOR_SIZE, + sizeof(img_src[0]), + (void *)&img_src[1]); + if (err) { + debug("%s: First boot info NOR sector read error %d\n", + __func__, err); + return err; + } + + debug("%s: BI0 0x%x 0x%x 0x%x\n", __func__, + img_src[0].magic, img_src[0].flags, img_src[0].crc8); + + debug("%s: BI1 0x%x 0x%x 0x%x\n", __func__, + img_src[1].magic, img_src[1].flags, img_src[1].crc8); + + return 0; +} + +#define BTT_MONITORING_DEVICE_TIMEOUT 100 +static int rescue_val; + +void spl_board_init(void) +{ + struct gpio_desc phy_rst, boot, rescue, wifi_en, bt_en; + int ret, i; + + /* + * On the new HW version of BTTC/3 (with LAN8720ai PHY) the !RST pin + * (15) is pulled LOW by external resistor. As a result it needs to be + * set HIGH as soon as possible to allow correct generation of RESET + * pulse. + * + * In the old BTTC (with TLK105 PHY) the RC circuit was used instead + * to set the RESET pin to HIGH after 100us, so there was no need to + * set it explicitly. + */ + ret = dm_gpio_lookup_name("GPIO4_12", &phy_rst); + if (ret) + printf("Cannot get GPIO4_12\n"); + + ret = dm_gpio_request(&phy_rst, "phy-rst"); + if (ret) + printf("Cannot request GPIO4_12\n"); + + dm_gpio_set_dir_flags(&phy_rst, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + /* + * Explicitly set GPIO, which controls WL_EN (wifi) to LOW. On the BTT3 + * it is directly connected to Jody module without any externa pull up + * down register. + */ + ret = dm_gpio_lookup_name("GPIO0_27", &wifi_en); + if (ret) + printf("Cannot get GPIO0_27\n"); + + ret = dm_gpio_request(&wifi_en, "wifi-en"); + if (ret) + printf("Cannot request GPIO0_27\n"); + + dm_gpio_set_dir_flags(&wifi_en, GPIOD_IS_OUT | GPIOD_ACTIVE_LOW | + GPIOD_IS_OUT_ACTIVE); + + /* + * Explicitly set GPIO, which controls BT_EN (Bluetooth) to LOW. On the + * BTT3 it is connected to Jody module via RC circuit (after some R*C + * time this pin is set to HIGH). However, the manual recommends setting + * it high from LOW state. + */ + ret = dm_gpio_lookup_name("GPIO3_27", &bt_en); + if (ret) + printf("Cannot get GPIO3_27\n"); + + ret = dm_gpio_request(&bt_en, "bt-en"); + if (ret) + printf("Cannot request GPIO3_27\n"); + + dm_gpio_set_dir_flags(&bt_en, GPIOD_IS_OUT | GPIOD_ACTIVE_LOW | + GPIOD_IS_OUT_ACTIVE); + + /* 'boot' and 'rescue' pins */ + ret = dm_gpio_lookup_name("GPIO4_9", &boot); + if (ret) + printf("Cannot get GPIO4_9\n"); + + ret = dm_gpio_request(&boot, "boot"); + if (ret) + printf("Cannot request GPIO4_9\n"); + + dm_gpio_set_dir_flags(&boot, GPIOD_IS_IN); + + ret = dm_gpio_lookup_name("GPIO4_11", &rescue); + if (ret) + printf("Cannot get GPIO4_11\n"); + + ret = dm_gpio_request(&rescue, "rescue"); + if (ret) + printf("Cannot request GPIO4_11\n"); + + dm_gpio_set_dir_flags(&rescue, GPIOD_IS_IN); + + /* Wait for ready signal from system "monitoring" device */ + for (i = 0; i < BTT_MONITORING_DEVICE_TIMEOUT; i++) { + if (dm_gpio_get_value(&boot)) + break; + mdelay(10); + } + + rescue_val = dm_gpio_get_value(&rescue); +} + +int spl_mmc_emmc_boot_partition(struct mmc *mmc) +{ + int i, src_idx = -1, ret; + + ret = spi_load_boot_info(); + if (ret) { + printf("%s: Cannot read BTT boot info! [%d]\n", __func__, ret); + /* To avoid bricking board - by default boot from boot0 eMMC */ + return 1; + } + + for (i = 0; i < 2; i++) { + if (img_src[i].magic == 'B' && + img_src[i].crc8 == crc8(0, &img_src[i].magic, 2)) { + src_idx = i; + break; + } + } + + debug("%s: src idx: %d\n", __func__, src_idx); + + if (src_idx < 0) + /* + * Always use eMMC (mmcblkX) boot0 if no + * valid image source description found + */ + return 1; + + if (img_src[src_idx].flags & BOOT_SRC_PART1) + return 2; + + return 1; +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = BOOT_DEVICE_MMC1; + spl_boot_list[1] = BOOT_DEVICE_SPI; + spl_boot_list[2] = BOOT_DEVICE_UART; +} + +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + debug("%s: rescue: %d\n", __func__, rescue_val); + return rescue_val; +} +#else + +/* + * Providing proper board name - i.e. 'bttc' vs 'btt3' + * The distinction is made on the size of DRAM memory - i.e. + * bttc has only 128 MiB, whereas btt3 has 256 MiB. + */ +#define STR_BTTC "bttc" +#define STR_BTT3 "btt3" + +static const char *get_board_name(void) +{ + if (gd->bd->bi_dram[0].size == SZ_128M) + return STR_BTTC; + + return STR_BTT3; +} + +/* + * Reading the HW ID number for BTT3 device + * + * GPIOs from Port 4: + * E0: GPIO4_10 + * E1: GPIO4_5 + * E2: GPIO4_14 + * E3: GPIO4_15 + * are used on BTT3 to store HW revision information. + * + * From rev 1+ the REV GPIOs are properly connected on the PCB, so PULL UPs + * shall be disabled (as they are by default on pins' SPL configuration) + *. + * Rev 0: - read all '1' (first production version without HW rev set) + * Rev 1: - read 0x1 (E0 set) + * Rev 2: - read 0x2 (E1 set) + * + */ +#define BTT3_HW_ID_GPIO_PORT (MXS_PINCTRL_BASE + (0x0900 + ((4) * 0x10))) +#define BTT3_HW_ID_E0 BIT(10) +#define BTT3_HW_ID_E1 BIT(5) +#define BTT3_HW_ID_E2 BIT(14) +#define BTT3_HW_ID_E3 BIT(15) + +static u8 get_som_rev(void) +{ + struct mxs_register_32 *reg = + (struct mxs_register_32 *)BTT3_HW_ID_GPIO_PORT; + u32 tmp = ~readl(®->reg); + u8 id = 0; + + if (tmp & BTT3_HW_ID_E0) + id += 1; + + if (tmp & BTT3_HW_ID_E1) + id += 2; + + if (tmp & BTT3_HW_ID_E2) + id += 4; + + if (tmp & BTT3_HW_ID_E3) + id += 8; + + /* + * Special case for first production BTT3 version, without HW + * revision support (so it reads 0x0s as pullups are disabled + * and hence 0xF is set for ID) + */ + if (id == 0xF) + id = 0; + + return id; +} + +int board_early_init_f(void) +{ + init_clocks(); + + return 0; +} + +int board_init(void) +{ + struct gpio_desc phy_rst; + int ret; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + cpu_eth_init(NULL); + + /* PHY INT#/PWDN# */ + ret = dm_gpio_lookup_name("GPIO4_13", &phy_rst); + if (ret) { + printf("Cannot get GPIO4_13\n"); + return ret; + } + + ret = dm_gpio_request(&phy_rst, "phy-rst"); + if (ret) { + printf("Cannot request GPIO4_13\n"); + return ret; + } + + dm_gpio_set_dir_flags(&phy_rst, GPIOD_IS_IN); + udelay(1000); + + return 0; +} + +#if defined(CONFIG_BOARD_LATE_INIT) +int board_late_init(void) +{ + int ret = env_set_ulong("board_som_rev", get_som_rev()); + + if (ret) + printf("Cannot set BTT's SoM revision env variable!\n"); + + ret = env_set("arch", get_board_name()); + if (ret) + printf("Cannot set SoM 'arch' env variable!\n"); + + return 0; +} +#endif + +#if defined(CONFIG_DISPLAY_BOARDINFO) +int checkboard(void) +{ + printf("Board: LWE BTT SoM HW rev %d\n", get_som_rev()); + + return 0; +} +#endif + +int dram_init(void) +{ + return mxs_dram_init(); +} + +#if defined(CONFIG_OF_BOARD) +int board_fdt_blob_setup(void **fdtp) +{ + /* + * The only purpose of this function is the specific BTT's DTB + * setup in u-boot proper. To be more specific - the SPL + * cannot support DTB selection due to size constraints + * (SPL < 50 KiB). + * + * Hence, the DTB selection is done in u-boot, which due to + * board's partition sizes (and backward compatibility) has also + * size constrain (~448 KiB). + * + * To support multiple DTBs appended, the compression has been used + * for them. Unfortunately, the initf_malloc() is called + * after the DTB needs to be selected. To fix this problem for this + * particular setup (i.e. BTT board) the initf_malloc() is called here. + */ + initf_malloc(); + + return -EEXIST; +} +#endif + +#if defined(CONFIG_MULTI_DTB_FIT) +int board_fit_config_name_match(const char *name) +{ + u8 rev_id = get_som_rev(); + char board[12]; + + sprintf(board, "imx28-btt3-%d", rev_id); + + if (!strncmp(name, board, sizeof(board))) + return 0; + + return -EINVAL; +} +#endif + +/* + * NOTE: + * + * IMX28 clock "stub" DM driver! + * + * Only used for SPL stage, which is NOT using DM; serial and + * eMMC configuration. + * + * It is required for SPL_OF_PLATDATA proper code generation as, + * this device has hard constrain on the size of the SPL binary + * (u-boot.sb). + */ +static const struct udevice_id imx28_clk_ids[] = { + { .compatible = "fsl,imx28-clkctrl", }, + { } +}; + +U_BOOT_DRIVER(fsl_imx28_clkctrl) = { + .name = "fsl_imx28_clkctrl", + .id = UCLASS_CLK, + .of_match = imx28_clk_ids, +}; +#endif /* CONFIG_XPL_BUILD */ diff --git a/board/liebherr/btt/btt.env b/board/liebherr/btt/btt.env new file mode 100644 index 00000000000..aaf0b8415d1 --- /dev/null +++ b/board/liebherr/btt/btt.env @@ -0,0 +1,139 @@ +bootmode=update +bootpri=mmc_mmc +bootsec=sf_swu +consdev=ttyAMA0 +baudrate=115200 +dtbfile=imx28-btt3-1.dtb +rootdev=/dev/mmcblk0p2 +netdev=eth0 +swufile=swupdate-image-btt3-upd.itb +sf_kernel_offset=0xA0000 +sf_swu_size=0xF40000 +ethact=FEC +arch=btt3 +lwe_env= + if dhcp ${loadaddr} ${hostname}/${lwe_uenv} ; then + source ${loadaddr}; + fi +lwe_uenv=env_uboot_btt3.bin +do_update_mmc= + if mmc rescan ; then + mmc dev 0 ${update_mmc_part} ; + if dhcp ${hostname}/${update_filename} ; then + setexpr fw_sz ${filesize} / 0x200 ; + setexpr fw_sz ${fw_sz} + 1 ; + mmc write ${loadaddr} ${update_offset} ${fw_sz} ; + fi ; + fi +do_update_sf= + if sf probe ; then + if dhcp ${hostname}/${update_filename} ; then + sf erase ${update_offset} +${filesize} ; + sf write ${loadaddr} ${update_offset} ${filesize} ; + fi ; + fi +factory_reset= + if sf probe ; then + run update_swu ; + setenv bootmode update ; + saveenv ; + fi +update_spl_filename=u-boot.sb +update_spl= + setenv update_filename ${update_spl_filename} ; + setenv update_offset 0 ; + run do_update_sf +update_uboot_filename=u-boot.img +update_uboot= + setenv update_filename ${update_uboot_filename} ; + setenv update_offset 0x10000 ; + run do_update_sf ; + setenv update_mmc_part 1 ; + setenv update_offset 0 ; + run do_update_mmc ; + setenv update_mmc_part 2 ; + run do_update_mmc +update_kernel_filename=uImage +update_kernel= + setenv update_mmc_part 1 ; + setenv update_filename ${update_kernel_filename} ; + setenv update_offset 0x800 ; + run do_update_mmc ; + setenv update_filename ${dtbfile} ; + setenv update_offset 0x400 ; + run do_update_mmc +update_swu= + setenv update_filename ${swufile} ; + setenv update_offset ${sf_kernel_offset} ; + run do_update_sf +addcons= + setenv bootargs ${bootargs} + console=${consdev},${baudrate} +addip= + setenv bootargs ${bootargs} + ip=${ipaddr}:${serverip}:${gatewayip}: + ${netmask}:${hostname}:${netdev}:off +addmisc= + setenv bootargs ${bootargs} ${miscargs} +addargs=run addcons addmisc +mmcload= + mmc rescan ; + mmc dev 0 1 ; + mmc read ${loadaddr} 0x800 0x2000 ; + mmc read ${dtbaddr} 0x400 0x80 +netload= + dhcp ${loadaddr} ${hostname}/${bootfile} ; + tftp ${dtbaddr} ${hostname}/${dtbfile} +usbload= + usb start ; + load usb 0:1 ${loadaddr} ${bootfile} +miscargs=panic=1 +mmcargs=setenv bootargs root=${rootdev} rw rootwait +nfsargs= + setenv bootargs root=/dev/nfs rw + nfsroot=${serverip}:${rootpath},v3,tcp +mmc_mmc= + if run mmcload mmcargs addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +mmc_nfs= + if run mmcload nfsargs addip addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +sf_mmc= + if run sfload mmcargs addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +sf_swu= + if sf probe ; then + sf read ${loadaddr} ${sf_kernel_offset} ${sf_swu_size} ; + setenv bootargs root=/dev/ram0 rw ; + run addargs ; + bootm ${loadaddr}#conf-imx28-${arch}-${board_som_rev}.dtb ; + fi +net_mmc= + if run netload mmcargs addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +net_nfs= + if run netload nfsargs addip addargs ; then + bootm ${loadaddr} - ${dtbaddr} ; + fi +prebootcmd= + if test ${envsaved} != y ; then ; + setenv envsaved y ; + saveenv ; + fi ; + if test ${bootmode} = normal ; then + setenv bootdelay 0 ; + setenv bootpri mmc_mmc ; + elif test ${bootmode} = devel ; then + setenv bootdelay 3 ; + setenv bootpri net_mmc ; + else + if test ${bootmode} != update ; then + echo Warning: unknown bootmode ${bootmode} ; + fi ; + setenv bootdelay 1 ; + setenv bootpri sf_swu ; + fi diff --git a/board/liebherr/btt/spl_btt.c b/board/liebherr/btt/spl_btt.c new file mode 100644 index 00000000000..da17e186b06 --- /dev/null +++ b/board/liebherr/btt/spl_btt.c @@ -0,0 +1,347 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * DENX M28 Boot setup + * + * Copyright (C) 2025 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ + +#include +#include +#include +#include +#include + +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_BOOT (MXS_PAD_3V3) +#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) + +/* HW_PINCTRL_EMI_DS_CTRL */ +#define EMI_DS_CTRL_CLR 0x3FFF +#define EMI_DS_CTRL_SLICE0_SHIFT 0 +#define EMI_DS_CTRL_SLICE1_SHIFT 2 +#define EMI_DS_CTRL_SLICE2_SHIFT 4 +#define EMI_DS_CTRL_SLICE3_SHIFT 6 +#define EMI_DS_CTRL_DUALPAD_SHIFT 8 +#define EMI_DS_CTRL_CONTROL_SHIFT 10 +#define EMI_DS_CTRL_ADDRESS_SHIFT 12 +#define EMI_DS_CTRL_MA_20 0x10 + +/* + * The BTT devide can be boot in several ways; U-Boot's 'falcon' mode, + * normal boot (through U-Boot proper) and also via recovery system. + * + * To fix some HW issues on the device, as well as providing all the + * above boot method's the same "start" state when kernel starts it + * has been decided to configure PINMUXes for all relevant IP blocks + * (and GPIOs during early SPI state). + * + * It also shall be mentioned, that during early SPL stage, the BTT + * device needs to cooperate with uC based co-processor - this + * requires correct pins configuration. + */ +static const iomux_cfg_t iomux_setup[] = { + /* AUART0 IRDA */ + MX28_PAD_AUART0_RX__AUART0_RX, + MX28_PAD_AUART0_TX__AUART0_TX, + + /* AUART 4 RS422 */ + MX28_PAD_AUART0_CTS__AUART4_RX, + MX28_PAD_AUART0_RTS__AUART4_TX, + + /* USB0 */ + MX28_PAD_AUART1_CTS__USB0_OVERCURRENT, + MX28_PAD_AUART1_RTS__USB0_ID, + MX28_PAD_LCD_VSYNC__GPIO_1_28, /* PRW_On */ + + /* USB1 */ + MX28_PAD_PWM2__USB1_OVERCURRENT, + + /* eMMC */ + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DETECT__GPIO_2_9, /* Reset for eMMC */ + MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0, + + /* DIG Keys */ + MX28_PAD_GPMI_D00__GPIO_0_0, + MX28_PAD_GPMI_D01__GPIO_0_1, + MX28_PAD_GPMI_D02__GPIO_0_2, + MX28_PAD_GPMI_D03__GPIO_0_3, + MX28_PAD_GPMI_D04__GPIO_0_4, + MX28_PAD_GPMI_D05__GPIO_0_5, + MX28_PAD_GPMI_D06__GPIO_0_6, + MX28_PAD_GPMI_D07__GPIO_0_7, + + /* ADR_0-2 */ + MX28_PAD_GPMI_CE1N__GPIO_0_17, + MX28_PAD_GPMI_CE2N__GPIO_0_18, + MX28_PAD_GPMI_CE3N__GPIO_0_19, + + /* Read Keys */ + MX28_PAD_GPMI_RDY0__GPIO_0_20, + + /* LATCH_EN */ + MX28_PAD_GPMI_RDY1__GPIO_0_21, + + /* Power off */ + MX28_PAD_GPMI_RDN__GPIO_0_24, + + /* WIFI EN */ + MX28_PAD_GPMI_CLE__GPIO_0_27, + + /* I2C1 Touch */ + MX28_PAD_AUART2_CTS__GPIO_3_10, + MX28_PAD_AUART2_RTS__GPIO_3_11, + MX28_PAD_GPMI_RDY2__GPIO_0_22, /* Touch Reset */ + MX28_PAD_GPMI_RDY3__GPIO_0_23, /* Touch INT */ + + /* TIVA */ + MX28_PAD_AUART1_RX__SSP2_CARD_DETECT, + MX28_PAD_SSP2_MISO__SSP2_D0, + MX28_PAD_SSP2_MOSI__SSP2_CMD, + MX28_PAD_SSP2_SCK__SSP2_SCK, + MX28_PAD_SSP2_SS0__SSP2_D3, + MX28_PAD_SSP2_SS1__GPIO_2_20, + MX28_PAD_SSP2_SS2__GPIO_2_21, + + /* SPI3 NOR-Flash */ + MX28_PAD_AUART1_TX__SSP3_CARD_DETECT, + MX28_PAD_AUART2_RX__SSP3_D1, + MX28_PAD_AUART2_TX__SSP3_D2, + MX28_PAD_SSP3_MISO__SSP3_D0, + MX28_PAD_SSP3_MOSI__SSP3_CMD, + MX28_PAD_SSP3_SCK__SSP3_SCK, + MX28_PAD_SSP3_SS0__SSP3_D3, + + /* NOR-Flash CMD */ + MX28_PAD_LCD_RS__GPIO_1_26, /* Hold */ + MX28_PAD_LCD_WR_RWN__GPIO_1_25, /* write protect */ + + /* I2C0 Codec */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* I2S Codec */ + MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK, + MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK, + MX28_PAD_SAIF0_MCLK__SAIF0_MCLK, + MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0, + MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0, + + /* BT_EN */ + MX28_PAD_SPDIF__GPIO_3_27, + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* Uart3 Bluetooth-Interface */ + MX28_PAD_AUART3_CTS__AUART3_CTS, + MX28_PAD_AUART3_RTS__AUART3_RTS, + MX28_PAD_AUART3_RX__AUART3_RX, + MX28_PAD_AUART3_TX__AUART3_TX, + + /* framebuffer */ + MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD, + MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD, + + /* DUART RS232 */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + + /* Backlight */ + MX28_PAD_PWM3__PWM_3, + + /* FEC Ethernet */ + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + MX28_PAD_ENET0_COL__ENET1_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_CRS__ENET1_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_CLK__GPIO_4_13, /* Phy Interrupt */ + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD3__ENET1_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_CLK__GPIO_4_5, /* n.c. */ + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD3__ENET1_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD3__GPIO_4_12, /* PHY reset */ + + /* boot/rescue pins */ + MX28_PAD_ENET0_RXD2__GPIO_4_9, + MX28_PAD_ENET0_TXD2__GPIO_4_11, + + /* HW revision setup pins - by default pullup DISABLED */ + MX28_PAD_ENET0_RXD3__GPIO_4_10, + MX28_PAD_ENET0_TX_CLK__GPIO_4_5, + MX28_PAD_ENET0_COL__GPIO_4_14, + MX28_PAD_ENET0_CRS__GPIO_4_15, +}; + +u32 mxs_dram_vals[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010101, 0x01010101, + 0x000f0f01, 0x0f02010a, 0x00000000, 0x00010101, + 0x00000100, 0x00000100, 0x00000000, 0x00000002, + 0x01010000, 0x07080403, 0x07005303, 0x0b0000c8, + 0x0200a0c1, 0x0002040c, 0x0038430a, 0x04290322, + 0x02040203, 0x00c8002b, 0x00000000, 0x00000000, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000612, 0x01000102, + 0x06120612, 0x00000200, 0x00020007, 0xf4004a27, + 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300, + 0x07400300, 0x07400300, 0x07400300, 0x00000005, + 0x00000000, 0x00000000, 0x01000000, 0x00000000, + 0x00000001, 0x000f1133, 0x00000000, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010000, 0x00030404, + 0x00000002, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x01010000, + 0x01000000, 0x03030000, 0x00010303, 0x01020202, + 0x00000000, 0x02040101, 0x21002103, 0x00061200, + 0x06120612, 0x00000642, 0x00000000, 0x00000004, + 0x00000000, 0x00000080, 0x00000000, 0x00000000, + 0x00000000, 0xffffffff +}; + +#ifndef CONFIG_SPL_FRAMEWORK +void board_init_ll(const u32 arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} +#else +void lowlevel_init(void) +{ + struct mxs_pinctrl_regs *pinctrl_regs = + (struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE; + + /* Set EMI drive strength - the HW_PINCTRL_EMI_DS_CTRL */ + writel(EMI_DS_CTRL_CLR, &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_clr); + writel(EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE0_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE1_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE2_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_SLICE3_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_DUALPAD_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_CONTROL_SHIFT | + EMI_DS_CTRL_MA_20 << EMI_DS_CTRL_ADDRESS_SHIFT, + &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set); + + mxs_common_spl_init(0, NULL, iomux_setup, ARRAY_SIZE(iomux_setup)); +} +#endif diff --git a/configs/imx28_btt3_defconfig b/configs/imx28_btt3_defconfig new file mode 100644 index 00000000000..a84327df922 --- /dev/null +++ b/configs/imx28_btt3_defconfig @@ -0,0 +1,140 @@ +CONFIG_ARM=y +CONFIG_SPL_SYS_THUMB_BUILD=y +CONFIG_ARCH_MX28=y +CONFIG_TEXT_BASE=0x40002000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_IMX_CONFIG="" +CONFIG_DM_GPIO=y +CONFIG_SPL_DM_SPI=y +CONFIG_DEFAULT_DEVICE_TREE="nxp/mxs/imx28-btt3-1" +CONFIG_TARGET_BTT=y +CONFIG_SPL_MXS_PMU_MINIMAL_VDD5V_CURRENT=y +CONFIG_SPL_MXS_PMU_DISABLE_BATT_CHARGE=y +# CONFIG_SPL_MXS_PMU_ENABLE_4P2_LINEAR_REGULATOR is not set +CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x80000 +CONFIG_MULTI_DTB_FIT_USER_DEF_ADDR=0x43000000 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK=0x20000 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_SPL_TEXT_BASE=0x1000 +CONFIG_SYS_LOAD_ADDR=0x42000000 +CONFIG_SF_DEFAULT_BUS=2 +CONFIG_SPL_SIZE_LIMIT=0xa000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x90000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI=y +CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_HAS_BOARD_SIZE_LIMIT=y +CONFIG_BOARD_SIZE_LIMIT=458752 +CONFIG_TIMESTAMP=y +CONFIG_FIT=y +# CONFIG_BOOTMETH_EXTLINUX is not set +# CONFIG_BOOTMETH_VBE is not set +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200n8" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ${bootpri} ; run ${bootsec}" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="run prebootcmd" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_NO_BSS_LIMIT=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x0 +CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG=y +CONFIG_SPL_DMA=y +CONFIG_SPL_MMC_TINY=y +CONFIG_SPL_DM_SPI_FLASH=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x44000000 +CONFIG_SPL_FALCON_BOOT_MMCSD=y +CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x800 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x400 +CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x40 +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x10000 +CONFIG_SYS_SPI_KERNEL_OFFS=0x100000 +CONFIG_SYS_SPI_ARGS_OFFS=0x80000 +CONFIG_SYS_SPI_ARGS_SIZE=0x8000 +CONFIG_SPL_YMODEM_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_SPL=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +# CONFIG_CMD_PINMUX is not set +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_DOS_PARTITION=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_BOARD=y +CONFIG_OF_LIST="nxp/mxs/imx28-btt3-0 nxp/mxs/imx28-btt3-1 nxp/mxs/imx28-btt3-2" +CONFIG_MULTI_DTB_FIT_GZIP=y +CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent interrupts" +CONFIG_SPL_OF_PLATDATA=y +# CONFIG_SPL_OF_PLATDATA_PARENT is not set +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_USE_BOOTFILE=y +CONFIG_BOOTFILE="uImage" +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="btt3" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_DEVRES=y +CONFIG_MXS_GPIO=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_MXS=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ADDR=1 +CONFIG_PHY_FIXED=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MXS=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXS_SPI=y +CONFIG_SPL_CRC8=y +# CONFIG_SPL_OF_LIBFDT is not set diff --git a/doc/board/index.rst b/doc/board/index.rst index 3c5a2c7d1cf..e084c7fb1df 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -38,6 +38,7 @@ Board-specific doc kontron/index lenovo/index lg/index + liebherr/index mediatek/index microchip/index microsoft/index diff --git a/doc/board/liebherr/btt.rst b/doc/board/liebherr/btt.rst new file mode 100644 index 00000000000..d22ffa205bd --- /dev/null +++ b/doc/board/liebherr/btt.rst @@ -0,0 +1,34 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Lukasz Majewski + +BTT devices +=========== + +Those devices are based on IMX's IMX287 SoC. The description regarding the +**btt** family of boards (i.e. `btt3` and `bttc`) is identical as the one for +the already supported **xea** board. + +Building +-------- + +Make sure that `CROSS_COMPILE` is set appropriately: + +.. code-block:: text + + $ make imx28_btt3_defconfig + $ make -j4 u-boot.sb u-boot.img + +Now you should see `u-boot.sb` and `u-boot.img` files in the build directory. + +For initial bringup - one can use `uuu` utulity to boot till u-boot prompt +(USB connection with the board is required). + +Flashing +-------- + +Via U-Boot: + +.. code-block:: text + + => run update_spl + => run update_uboot diff --git a/doc/board/liebherr/index.rst b/doc/board/liebherr/index.rst new file mode 100644 index 00000000000..d8db6bd188c --- /dev/null +++ b/doc/board/liebherr/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Liebherr +======== + +.. toctree:: + :maxdepth: 2 + + btt diff --git a/include/configs/btt.h b/include/configs/btt.h new file mode 100644 index 00000000000..dea87fa9b77 --- /dev/null +++ b/include/configs/btt.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 DENX Software Engineering + * Lukasz Majewski, DENX Software Engineering, lukma@denx.de + */ +#ifndef __CONFIGS_BTT_H__ +#define __CONFIGS_BTT_H__ + +#include +/* Memory configuration */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE SZ_256M /* Max 256 MB RAM */ +#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIGS_BTT_H__ */ -- cgit v1.3.1 From c1c2b5c6a4c09fe57933b70ec6289795f732ac83 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Wed, 7 May 2025 14:12:43 +0200 Subject: linux/list.h: drop use of prefetch() The use of prefetch() in these list helpers was dropped back in 2011 in linux (e66eed651fd1 ("list: remove prefetching from regular list iterators")). No arch in U-Boot defines any actual prefetch(), and as the referenced commit says, it's usually not a win anyway. Whole-sale sync of list.h is not really feasible, but we can synchronize the macros containing a prefetch() with their linux implementations as of v6.15-rc5, also importing the various helpers needed, e.g. list_is_head() and list_next_entry(). Signed-off-by: Rasmus Villemoes --- include/linux/list.h | 99 +++++++++++++++++++++++++++++++--------------------- 1 file changed, 59 insertions(+), 40 deletions(-) (limited to 'include') diff --git a/include/linux/list.h b/include/linux/list.h index 0f9d939b05f..e21ae03b208 100644 --- a/include/linux/list.h +++ b/include/linux/list.h @@ -169,6 +169,16 @@ static inline int list_is_last(const struct list_head *list, return list->next == head; } +/** + * list_is_head - tests whether @list is the list @head + * @list: the entry to test + * @head: the head of the list + */ +static inline int list_is_head(const struct list_head *list, const struct list_head *head) +{ + return list == head; +} + /** * list_empty - tests whether a list is empty * @head: the list to test. @@ -363,26 +373,28 @@ static inline void list_splice_tail_init(struct list_head *list, }) /** - * list_for_each - iterate over a list - * @pos: the &struct list_head to use as a loop cursor. - * @head: the head for your list. + * list_next_entry - get the next element in list + * @pos: the type * to cursor + * @member: the name of the list_head within the struct. */ -#define list_for_each(pos, head) \ - for (pos = (head)->next; prefetch(pos->next), pos != (head); \ - pos = pos->next) +#define list_next_entry(pos, member) \ + list_entry((pos)->member.next, typeof(*(pos)), member) + +/** + * list_prev_entry - get the prev element in list + * @pos: the type * to cursor + * @member: the name of the list_head within the struct. + */ +#define list_prev_entry(pos, member) \ + list_entry((pos)->member.prev, typeof(*(pos)), member) /** - * __list_for_each - iterate over a list + * list_for_each - iterate over a list * @pos: the &struct list_head to use as a loop cursor. * @head: the head for your list. - * - * This variant differs from list_for_each() in that it's the - * simplest possible list iteration code, no prefetching is done. - * Use this for code that knows the list to be very short (empty - * or 1 entry) most of the time. */ -#define __list_for_each(pos, head) \ - for (pos = (head)->next; pos != (head); pos = pos->next) +#define list_for_each(pos, head) \ + for (pos = (head)->next; !list_is_head(pos, (head)); pos = pos->next) /** * list_for_each_prev - iterate over a list backwards @@ -390,8 +402,7 @@ static inline void list_splice_tail_init(struct list_head *list, * @head: the head for your list. */ #define list_for_each_prev(pos, head) \ - for (pos = (head)->prev; prefetch(pos->prev), pos != (head); \ - pos = pos->prev) + for (pos = (head)->prev; !list_is_head(pos, (head)); pos = pos->prev) /** * list_for_each_safe - iterate over a list safe against removal of list entry @@ -411,30 +422,39 @@ static inline void list_splice_tail_init(struct list_head *list, */ #define list_for_each_prev_safe(pos, n, head) \ for (pos = (head)->prev, n = pos->prev; \ - prefetch(pos->prev), pos != (head); \ + !list_is_head(pos, (head)); \ pos = n, n = pos->prev) +/** + * list_entry_is_head - test if the entry points to the head of the list + * @pos: the type * to cursor + * @head: the head for your list. + * @member: the name of the list_head within the struct. + */ +#define list_entry_is_head(pos, head, member) \ + list_is_head(&pos->member, (head)) + /** * list_for_each_entry - iterate over list of given type * @pos: the type * to use as a loop cursor. * @head: the head for your list. - * @member: the name of the list_struct within the struct. + * @member: the name of the list_head within the struct. */ #define list_for_each_entry(pos, head, member) \ - for (pos = list_entry((head)->next, typeof(*pos), member); \ - prefetch(pos->member.next), &pos->member != (head); \ - pos = list_entry(pos->member.next, typeof(*pos), member)) + for (pos = list_first_entry(head, typeof(*pos), member); \ + !list_entry_is_head(pos, head, member); \ + pos = list_next_entry(pos, member)) /** * list_for_each_entry_reverse - iterate backwards over list of given type. * @pos: the type * to use as a loop cursor. * @head: the head for your list. - * @member: the name of the list_struct within the struct. + * @member: the name of the list_head within the struct. */ #define list_for_each_entry_reverse(pos, head, member) \ - for (pos = list_entry((head)->prev, typeof(*pos), member); \ - prefetch(pos->member.prev), &pos->member != (head); \ - pos = list_entry(pos->member.prev, typeof(*pos), member)) + for (pos = list_last_entry(head, typeof(*pos), member); \ + !list_entry_is_head(pos, head, member); \ + pos = list_prev_entry(pos, member)) /** * list_prepare_entry - prepare a pos entry for use in list_for_each_entry_continue() @@ -451,41 +471,41 @@ static inline void list_splice_tail_init(struct list_head *list, * list_for_each_entry_continue - continue iteration over list of given type * @pos: the type * to use as a loop cursor. * @head: the head for your list. - * @member: the name of the list_struct within the struct. + * @member: the name of the list_head within the struct. * * Continue to iterate over list of given type, continuing after * the current position. */ -#define list_for_each_entry_continue(pos, head, member) \ - for (pos = list_entry(pos->member.next, typeof(*pos), member); \ - prefetch(pos->member.next), &pos->member != (head); \ - pos = list_entry(pos->member.next, typeof(*pos), member)) +#define list_for_each_entry_continue(pos, head, member) \ + for (pos = list_next_entry(pos, member); \ + !list_entry_is_head(pos, head, member); \ + pos = list_next_entry(pos, member)) /** * list_for_each_entry_continue_reverse - iterate backwards from the given point * @pos: the type * to use as a loop cursor. * @head: the head for your list. - * @member: the name of the list_struct within the struct. + * @member: the name of the list_head within the struct. * * Start to iterate over list of given type backwards, continuing after * the current position. */ #define list_for_each_entry_continue_reverse(pos, head, member) \ - for (pos = list_entry(pos->member.prev, typeof(*pos), member); \ - prefetch(pos->member.prev), &pos->member != (head); \ - pos = list_entry(pos->member.prev, typeof(*pos), member)) + for (pos = list_prev_entry(pos, member); \ + !list_entry_is_head(pos, head, member); \ + pos = list_prev_entry(pos, member)) /** * list_for_each_entry_from - iterate over list of given type from the current point * @pos: the type * to use as a loop cursor. * @head: the head for your list. - * @member: the name of the list_struct within the struct. + * @member: the name of the list_head within the struct. * * Iterate over list of given type, continuing from current position. */ -#define list_for_each_entry_from(pos, head, member) \ - for (; prefetch(pos->member.next), &pos->member != (head); \ - pos = list_entry(pos->member.next, typeof(*pos), member)) +#define list_for_each_entry_from(pos, head, member) \ + for (; !list_entry_is_head(pos, head, member); \ + pos = list_next_entry(pos, member)) /** * list_for_each_entry_safe - iterate over list of given type safe against removal of list entry @@ -654,8 +674,7 @@ static inline void hlist_add_after(struct hlist_node *n, #define hlist_entry(ptr, type, member) container_of(ptr,type,member) #define hlist_for_each(pos, head) \ - for (pos = (head)->first; pos && ({ prefetch(pos->next); 1; }); \ - pos = pos->next) + for (pos = (head)->first; pos ; pos = pos->next) #define hlist_for_each_safe(pos, n, head) \ for (pos = (head)->first; pos && ({ n = pos->next; 1; }); \ -- cgit v1.3.1 From 1d19bbcb68280814952bdc18d7dec6d083b2c0ef Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Wed, 7 May 2025 14:12:46 +0200 Subject: linux/list.h: drop fallback definition of prefetch() None of the list helpers use prefetch() anymore, and no C code relies on getting this definition from list.h. In any case, such an arch/cpu specific thing does not belong in a header that just consists of cpp helper macros. Signed-off-by: Rasmus Villemoes --- include/linux/list.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include') diff --git a/include/linux/list.h b/include/linux/list.h index e21ae03b208..3dc38279716 100644 --- a/include/linux/list.h +++ b/include/linux/list.h @@ -4,11 +4,6 @@ #include #include -#ifndef ARCH_HAS_PREFETCH -#define ARCH_HAS_PREFETCH -static inline void prefetch(const void *x) {;} -#endif - /* * Simple doubly linked list implementation. * -- cgit v1.3.1 From 3bc174031d3cbcf176b22fc2869b486011fa194c Mon Sep 17 00:00:00 2001 From: Moteen Shah Date: Mon, 9 Jun 2025 13:44:29 +0530 Subject: ti_sci_*: Add utility to access tisci firmware and SOC capability Introduce response and request structs for receiving information regarding FW/SOC capability from DM. The received capability can further be used to call certain API's based on the feature supoorted by the DM firmware. Signed-off-by: Moteen Shah Reviewed-by: Neha Malcom Francis Reviewed-by: Dhruva Gole --- drivers/firmware/ti_sci.h | 13 +++++++++++++ include/linux/soc/ti/ti_sci_protocol.h | 13 +++++++++++++ 2 files changed, 26 insertions(+) (limited to 'include') diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h index bb8bc7beead..292f7cd578a 100644 --- a/drivers/firmware/ti_sci.h +++ b/drivers/firmware/ti_sci.h @@ -27,6 +27,7 @@ #define TI_SCI_MSG_BOARD_CONFIG_SECURITY 0x000d #define TI_SCI_MSG_BOARD_CONFIG_PM 0x000e #define TISCI_MSG_QUERY_MSMC 0x0020 +#define TI_SCI_MSG_QUERY_FW_CAPS 0x0022 /* Device requests */ #define TI_SCI_MSG_SET_DEVICE_STATE 0x0200 @@ -134,6 +135,18 @@ struct ti_sci_msg_resp_version { u8 abi_minor; } __packed; +/** + * struct ti_sci_query_fw_caps_resp - Response for a message + * @hdr: Generic header + * @fw_caps: 64-bit value representing the FW/SOC capabilities. + * + * Response to a message with message type TI_SCI_MSG_QUERY_FW_CAPS + */ +struct ti_sci_query_fw_caps_resp { + struct ti_sci_msg_hdr hdr; + u64 fw_caps; +} __packed; + /** * struct ti_sci_msg_req_reboot - Reboot the SoC * @hdr: Generic Header diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index aa4d105ee98..f967077b756 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -261,6 +261,18 @@ struct ti_sci_core_ops { u64 *msmc_start, u64 *msmc_end); }; +/** + * struct ti_sci_firmware_ops - DM firmware operations + * @query_dm_cap: Query the DM capabilities + * Return 0 for successful query else appropriate error value. + */ +struct ti_sci_firmware_ops { + int (*query_dm_cap)(struct ti_sci_handle *handle, + u64 *dm_cap); +}; + +#define TI_SCI_MSG_FLAG_FW_CAP_DM 0x100 + /** * struct ti_sci_proc_ops - Processor specific operations. * @@ -609,6 +621,7 @@ struct ti_sci_ops { struct ti_sci_dev_ops dev_ops; struct ti_sci_clk_ops clk_ops; struct ti_sci_core_ops core_ops; + struct ti_sci_firmware_ops fw_ops; struct ti_sci_proc_ops proc_ops; struct ti_sci_rm_core_ops rm_core_ops; struct ti_sci_rm_ringacc_ops rm_ring_ops; -- cgit v1.3.1 From 33fc7751b9adce0bc76989f399107078b2c21fd8 Mon Sep 17 00:00:00 2001 From: Moteen Shah Date: Mon, 9 Jun 2025 13:44:30 +0530 Subject: ti_sci_* : Add capability to access DM firmware's metadata Introduce response and request structs to receive and request information regarding DM version, etc from TI SCI. Signed-off-by: Moteen Shah Reviewed-by: Neha Malcom Francis Reviewed-by: Dhruva Gole --- drivers/firmware/ti_sci.h | 29 +++++++++++++++++++++++++++++ include/linux/soc/ti/ti_sci_protocol.h | 26 ++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) (limited to 'include') diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h index 292f7cd578a..ce50bf6800e 100644 --- a/drivers/firmware/ti_sci.h +++ b/drivers/firmware/ti_sci.h @@ -26,6 +26,7 @@ #define TI_SCI_MSG_BOARD_CONFIG_RM 0x000c #define TI_SCI_MSG_BOARD_CONFIG_SECURITY 0x000d #define TI_SCI_MSG_BOARD_CONFIG_PM 0x000e +#define TI_SCI_MSG_DM_VERSION 0x000f #define TISCI_MSG_QUERY_MSMC 0x0020 #define TI_SCI_MSG_QUERY_FW_CAPS 0x0022 @@ -135,6 +136,34 @@ struct ti_sci_msg_resp_version { u8 abi_minor; } __packed; +/** + * struct ti_sci_msg_dm_resp_version - Response for a message + * @hdr: Generic header + * @version: Version number of the firmware + * @sub_version: Sub-version number of the firmware + * @patch_version: Patch version number of the firmware + * @abi_major: Major version of the ABI that firmware supports + * @abi_minor: Minor version of the ABI that firmware supports + * @sci_server_version: String describing the SCI server version + * @rm_pm_hal_version: String describing the RM PM HAL version + * + * In general, ABI version changes follow the rule that minor version increments + * are backward compatible. Major revision changes in ABI may not be + * backward compatible. + * + * Response to a message with message type TI_SCI_MSG_DM_VERSION + */ +struct ti_sci_msg_dm_resp_version { + struct ti_sci_msg_hdr hdr; + u16 version; + u8 sub_version; + u8 patch_version; + u8 abi_major; + u8 abi_minor; + char rm_pm_hal_version[12]; + char sci_server_version[26]; +} __packed; + /** * struct ti_sci_query_fw_caps_resp - Response for a message * @hdr: Generic header diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h index f967077b756..52696763ecf 100644 --- a/include/linux/soc/ti/ti_sci_protocol.h +++ b/include/linux/soc/ti/ti_sci_protocol.h @@ -30,6 +30,28 @@ struct ti_sci_version_info { char firmware_description[32]; }; +/** + * struct ti_sci_dm_version_info - version information structure + * @abi_major: Major ABI version. Change here implies risk of backward + * compatibility break. + * @abi_minor: Minor ABI version. Change here implies new feature addition, + * or compatible change in ABI. + * @patch_ver: Patch version of the firmware. + * @sub_ver: Sub-version of the firmware. + * @dm_ver: DM version. + * @sci_server_version: Version string of the SCI server. + * @rm_pm_hal_version: Version string of the RM PM HAL. + */ +struct ti_sci_dm_version_info { + u8 abi_major; + u8 abi_minor; + u8 patch_ver; + u8 sub_ver; + u16 dm_ver; + char rm_pm_hal_version[12]; + char sci_server_version[26]; +}; + struct ti_sci_handle; /** @@ -265,10 +287,14 @@ struct ti_sci_core_ops { * struct ti_sci_firmware_ops - DM firmware operations * @query_dm_cap: Query the DM capabilities * Return 0 for successful query else appropriate error value. + * @get_dm_version: Get the DM version. + * Return 0 for successful request else appropriate error value. */ struct ti_sci_firmware_ops { int (*query_dm_cap)(struct ti_sci_handle *handle, u64 *dm_cap); + int (*get_dm_version)(struct ti_sci_handle *handle, + struct ti_sci_dm_version_info *get_dm_version); }; #define TI_SCI_MSG_FLAG_FW_CAP_DM 0x100 -- cgit v1.3.1 From f414dbcc13dd8709e03ac3f935f5e5c2eebfa5a0 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 7 May 2025 21:07:10 -0300 Subject: board: sama5d27_wlsom1_ek: Get RAM size and base from devicetree Instead of using defines for the RAM size and base address, retrieve these information from the devicetree. This aligns with the sama5d27_som1_ek board in commit 73c1589f025d9 ("board: sama5d27_som1_ek: Get dram size and base from device tree"). While at it, remove a spurious '/* SPL */' comment. Signed-off-by: Fabio Estevam --- board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 11 +++++++---- include/configs/sama5d27_wlsom1_ek.h | 6 ------ 2 files changed, 7 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 04de1257eca..897fab58eba 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -65,7 +65,7 @@ int board_early_init_f(void) int board_init(void) { /* address of boot parameters */ - gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; rgb_leds_init(); @@ -82,11 +82,14 @@ int misc_init_r(void) } #endif +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + int dram_init(void) { - gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, - CFG_SYS_SDRAM_SIZE); - return 0; + return fdtdec_setup_mem_size_base(); } /* SPL */ diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index 1979cb366e5..b54e3d5c710 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -15,10 +15,4 @@ #undef CFG_SYS_AT91_MAIN_CLOCK #define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ -/* SDRAM */ -#define CFG_SYS_SDRAM_BASE 0x20000000 -#define CFG_SYS_SDRAM_SIZE 0x10000000 - -/* SPL */ - #endif -- cgit v1.3.1 From ee6d7a5bf8a10e3fb487e7b936c9dd6aaf31dd9b Mon Sep 17 00:00:00 2001 From: Manikandan Muralidharan Date: Tue, 3 Jun 2025 10:35:55 +0530 Subject: board: sam9x75_curiosity: Add support for sam9x75 curiosity Add board specific functions for sam9x75 curiosity Signed-off-by: Manikandan Muralidharan Reviewed-by: Eugen Hristev --- arch/arm/mach-at91/Kconfig | 8 +++ board/atmel/sam9x75_curiosity/Kconfig | 15 ++++++ board/atmel/sam9x75_curiosity/MAINTAINERS | 6 +++ board/atmel/sam9x75_curiosity/Makefile | 7 +++ board/atmel/sam9x75_curiosity/sam9x75_curiosity.c | 66 +++++++++++++++++++++++ include/configs/sam9x75_curiosity.h | 23 ++++++++ 6 files changed, 125 insertions(+) create mode 100644 board/atmel/sam9x75_curiosity/Kconfig create mode 100644 board/atmel/sam9x75_curiosity/MAINTAINERS create mode 100644 board/atmel/sam9x75_curiosity/Makefile create mode 100644 board/atmel/sam9x75_curiosity/sam9x75_curiosity.c create mode 100644 include/configs/sam9x75_curiosity.h (limited to 'include') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 5429257875d..d21534ce883 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -158,6 +158,13 @@ config TARGET_SAM9X60_CURIOSITY select BOARD_EARLY_INIT_F select BOARD_LATE_INIT +config TARGET_SAM9X75_CURIOSITY + bool "SAM9X75 CURIOSITY board" + select SAM9X7 + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply OF_UPSTREAM + config TARGET_SAMA5D2_PTC_EK bool "SAMA5D2 PTC EK board" select BOARD_EARLY_INIT_F @@ -355,6 +362,7 @@ source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" source "board/atmel/sam9x60ek/Kconfig" source "board/atmel/sam9x60_curiosity/Kconfig" +source "board/atmel/sam9x75_curiosity/Kconfig" source "board/atmel/sama7g5ek/Kconfig" source "board/atmel/sama7g54_curiosity/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" diff --git a/board/atmel/sam9x75_curiosity/Kconfig b/board/atmel/sam9x75_curiosity/Kconfig new file mode 100644 index 00000000000..8ea93a21aa3 --- /dev/null +++ b/board/atmel/sam9x75_curiosity/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAM9X75_CURIOSITY + +config SYS_BOARD + default "sam9x75_curiosity" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sam9x75_curiosity" + +endif diff --git a/board/atmel/sam9x75_curiosity/MAINTAINERS b/board/atmel/sam9x75_curiosity/MAINTAINERS new file mode 100644 index 00000000000..a175053418f --- /dev/null +++ b/board/atmel/sam9x75_curiosity/MAINTAINERS @@ -0,0 +1,6 @@ +SAM9X75 CURIOSITY BOARD +M: Manikandan Muralidharan +S: Maintained +F: board/atmel/sam9x75_curiosity/ +F: include/configs/sam9x75_curiosity.h +F: arch/arm/dts/at91-sam9x75_curiosity-u-boot.dtsi diff --git a/board/atmel/sam9x75_curiosity/Makefile b/board/atmel/sam9x75_curiosity/Makefile new file mode 100644 index 00000000000..1f36d613229 --- /dev/null +++ b/board/atmel/sam9x75_curiosity/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries +# +# Author: Manikandan Muralidharan + +obj-y += sam9x75_curiosity.o diff --git a/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c new file mode 100644 index 00000000000..4e7c5667e21 --- /dev/null +++ b/board/atmel/sam9x75_curiosity/sam9x75_curiosity.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries + * + * Author: Manikandan Muralidharan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void at91_prepare_cpu_var(void); + +int board_late_init(void) +{ + at91_prepare_cpu_var(); + + return 0; +} + +#if (IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT)) +static void board_dbgu0_hw_init(void) +{ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 26, 1); /* DRXD */ + at91_pio3_set_a_periph(AT91_PIO_PORTA, 27, 1); /* DTXD */ + + at91_periph_clk_enable(ATMEL_ID_DBGU); +} + +void board_debug_uart_init(void) +{ + board_dbgu0_hw_init(); +} +#endif + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; + + return 0; +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} diff --git a/include/configs/sam9x75_curiosity.h b/include/configs/sam9x75_curiosity.h new file mode 100644 index 00000000000..62a855d9f01 --- /dev/null +++ b/include/configs/sam9x75_curiosity.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration settings for the SAM9X75 CURIOSITY board. + * + * Copyright (C) 2025 Microchip Technology Inc. and its subsidiaries + * + * Author: Manikandan Muralidharan + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +#define CFG_SYS_AT91_SLOW_CLOCK 32768 +#define CFG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ + +#define CFG_USART_BASE ATMEL_BASE_DBGU +#define CFG_USART_ID 0 /* ignored in arm */ + +/* SDRAM */ +#define CFG_SYS_SDRAM_BASE 0x20000000 +#define CFG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ + +#endif -- cgit v1.3.1 From 0fd9a3480a024a39da00b502af1406418378a27e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 9 Jun 2025 21:26:36 +0200 Subject: env: Rename OVERWRITE_ETHADDR_ONCE to ENV_OVERWRITE_ETHADDR_ONCE Rename the variable and add ENV_ prefix, so that all configuration options which are related to environment would have an CONFIG_ENV_ prefix. No functional change. Reviewed-by: Quentin Schulz Reviewed-by: Tom Rini Signed-off-by: Marek Vasut --- configs/M5253DEMO_defconfig | 2 +- configs/M5275EVB_defconfig | 2 +- configs/eb_cpu5282_defconfig | 2 +- configs/eb_cpu5282_internal_defconfig | 2 +- env/Kconfig | 2 +- include/env_flags.h | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index a1ce8ddf729..4f5e3183395 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -24,7 +24,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_MAC_PARTITION=y -CONFIG_OVERWRITE_ETHADDR_ONCE=y +CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="M5253DEMO" diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index 599eaf7b9ce..d09dbf21428 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -29,7 +29,7 @@ CONFIG_CMD_MII=y CONFIG_MII_INIT=y CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y -CONFIG_OVERWRITE_ETHADDR_ONCE=y +CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_RX_ETH_BUFFER=8 diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index 1c52322768e..00f24533021 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -30,7 +30,7 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_MII_INIT=y -CONFIG_OVERWRITE_ETHADDR_ONCE=y +CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_DM_I2C=y diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index a8c1b99bb05..c6cd3c74f08 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -28,7 +28,7 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_MII_INIT=y -CONFIG_OVERWRITE_ETHADDR_ONCE=y +CONFIG_ENV_OVERWRITE_ETHADDR_ONCE=y CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_DM_I2C=y diff --git a/env/Kconfig b/env/Kconfig index 8203ef73fce..ee47b565213 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -43,7 +43,7 @@ config ENV_OVERWRITE Use this to permit overriding of certain environmental variables like Ethernet and Serial -config OVERWRITE_ETHADDR_ONCE +config ENV_OVERWRITE_ETHADDR_ONCE bool "Enable overwriting ethaddr environment variables once" depends on !ENV_OVERWRITE help diff --git a/include/env_flags.h b/include/env_flags.h index 2476043b0e3..aac8b9ab53b 100644 --- a/include/env_flags.h +++ b/include/env_flags.h @@ -50,7 +50,7 @@ enum env_flags_varaccess { #ifdef CONFIG_ENV_OVERWRITE #define ETHADDR_FLAGS "eth" ETHADDR_WILDCARD "addr:ma," #else -#ifdef CONFIG_OVERWRITE_ETHADDR_ONCE +#ifdef CONFIG_ENV_OVERWRITE_ETHADDR_ONCE #define ETHADDR_FLAGS "eth" ETHADDR_WILDCARD "addr:mc," #else #define ETHADDR_FLAGS "eth" ETHADDR_WILDCARD "addr:mo," -- cgit v1.3.1 From 5fb88fa725d6d4f6d358e86613a14cde01426692 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 9 Jun 2025 21:26:37 +0200 Subject: env: Rename SYS_REDUNDAND_ENVIRONMENT to ENV_REDUNDANT Rename the variable and add ENV_ prefix, so that all configuration options which are related to environment would have an CONFIG_ENV_ prefix. No functional change. Signed-off-by: Marek Vasut --- configs/am335x_guardian_defconfig | 2 +- configs/am335x_igep003x_defconfig | 2 +- configs/am335x_shc_defconfig | 2 +- configs/am335x_shc_ict_defconfig | 2 +- configs/am335x_shc_netboot_defconfig | 2 +- configs/am335x_shc_sdboot_defconfig | 2 +- configs/am335x_sl50_defconfig | 2 +- configs/am43xx_evm_qspiboot_defconfig | 2 +- configs/am43xx_hs_evm_qspi_defconfig | 2 +- configs/am57xx_evm_defconfig | 2 +- configs/am57xx_hs_evm_defconfig | 2 +- configs/am57xx_hs_evm_usb_defconfig | 2 +- configs/am65x_evm_a53_defconfig | 2 +- configs/amd_versal2_virt_defconfig | 2 +- configs/aristainetos2c_defconfig | 2 +- configs/aristainetos2ccslb_defconfig | 2 +- configs/at91sam9260ek_nandflash_defconfig | 2 +- configs/at91sam9261ek_nandflash_defconfig | 2 +- configs/at91sam9263ek_nandflash_defconfig | 2 +- configs/at91sam9263ek_norflash_boot_defconfig | 2 +- configs/at91sam9263ek_norflash_defconfig | 2 +- configs/at91sam9g10ek_nandflash_defconfig | 2 +- configs/at91sam9g20ek_2mmc_nandflash_defconfig | 2 +- configs/at91sam9g20ek_nandflash_defconfig | 2 +- configs/at91sam9m10g45ek_nandflash_defconfig | 2 +- configs/at91sam9n12ek_nandflash_defconfig | 2 +- configs/at91sam9rlek_nandflash_defconfig | 2 +- configs/at91sam9x5ek_nandflash_defconfig | 2 +- configs/at91sam9xeek_nandflash_defconfig | 2 +- configs/axm_defconfig | 2 +- configs/bcm7260_defconfig | 2 +- configs/bcm7445_defconfig | 2 +- configs/bk4r1_defconfig | 2 +- configs/brcp150_defconfig | 2 +- configs/brcp170_defconfig | 2 +- configs/brcp1_1r_defconfig | 2 +- configs/brcp1_1r_switch_defconfig | 2 +- configs/brcp1_2r_defconfig | 2 +- configs/brppt1_mmc_defconfig | 2 +- configs/brsmarc1_defconfig | 2 +- configs/brsmarc2_defconfig | 2 +- configs/brxre1_defconfig | 2 +- configs/chiliboard_defconfig | 2 +- configs/corvus_defconfig | 2 +- configs/display5_defconfig | 2 +- configs/display5_factory_defconfig | 2 +- configs/dra7xx_evm_defconfig | 2 +- configs/dra7xx_hs_evm_defconfig | 2 +- configs/dra7xx_hs_evm_usb_defconfig | 2 +- configs/draco-etamin_defconfig | 2 +- configs/draco-rastaban_defconfig | 2 +- configs/draco-thuban_defconfig | 2 +- configs/e850-96_defconfig | 2 +- configs/edison_defconfig | 2 +- configs/gardena-smart-gateway-at91sam_defconfig | 2 +- configs/gardena-smart-gateway-mt7688_defconfig | 2 +- configs/gazerbeam_defconfig | 2 +- configs/gwventana_emmc_defconfig | 2 +- configs/gwventana_nand_defconfig | 2 +- configs/gxp_defconfig | 2 +- configs/igep00x0_defconfig | 2 +- configs/imx28_xea_defconfig | 2 +- configs/imx28_xea_sb_defconfig | 2 +- configs/imx6q_bosch_acc_defconfig | 2 +- configs/imx8m_data_modul.config | 2 +- configs/imx8mm-cl-iot-gate_defconfig | 2 +- configs/imx8mm-mx8menlo_defconfig | 2 +- configs/imx8mm-phygate-tauri-l_defconfig | 2 +- configs/imx8mm_phg_defconfig | 2 +- configs/imx8mm_venice_defconfig | 2 +- configs/imx8mn_venice_defconfig | 2 +- configs/imx8mp_venice_defconfig | 2 +- configs/imx8qxp_capricorn.config | 2 +- configs/imx93-phycore_defconfig | 2 +- configs/imx_dhsom.config | 2 +- configs/iot2050_defconfig | 2 +- configs/j7200_evm_a72_defconfig | 2 +- configs/j721e_beagleboneai64_a72_defconfig | 2 +- configs/j721e_evm_a72_defconfig | 2 +- configs/j721s2_evm_a72_defconfig | 2 +- configs/j784s4_evm_a72_defconfig | 2 +- configs/kmcent2_defconfig | 2 +- configs/kmcoge5ne_defconfig | 2 +- configs/kmeter1_defconfig | 2 +- configs/kmopti2_defconfig | 2 +- configs/kmsupx5_defconfig | 2 +- configs/kmtepr2_defconfig | 2 +- configs/kontron-sl-mx8mm_defconfig | 2 +- configs/kontron_sl28_defconfig | 2 +- configs/kp_imx53_defconfig | 2 +- configs/kp_imx6q_tpc_defconfig | 2 +- configs/lxr2_defconfig | 2 +- configs/m53menlo_defconfig | 2 +- configs/mccmon6_nor_defconfig | 2 +- configs/mccmon6_sd_defconfig | 2 +- configs/microblaze-generic_defconfig | 2 +- configs/msc_sm2s_imx8mp_defconfig | 2 +- configs/mscc_jr2_defconfig | 2 +- configs/mscc_luton_defconfig | 2 +- configs/mscc_ocelot_defconfig | 2 +- configs/mscc_serval_defconfig | 2 +- configs/mscc_servalt_defconfig | 2 +- configs/novena_defconfig | 2 +- configs/opos6uldev_defconfig | 2 +- configs/pcm052_defconfig | 2 +- configs/pcm058_defconfig | 2 +- configs/pg_wcom_expu1_defconfig | 2 +- configs/pg_wcom_expu1_update_defconfig | 2 +- configs/pg_wcom_seli8_defconfig | 2 +- configs/pg_wcom_seli8_update_defconfig | 2 +- configs/phycore-imx8mm_defconfig | 2 +- configs/phycore-imx8mp_defconfig | 2 +- configs/phycore_am62ax_a53_defconfig | 2 +- configs/phycore_am62x_a53_defconfig | 2 +- configs/phycore_am64x_a53_defconfig | 2 +- configs/pm9g45_defconfig | 2 +- configs/sam9x60ek_nandflash_defconfig | 2 +- configs/sama5d2_ptc_ek_nandflash_defconfig | 2 +- configs/sama5d36ek_cmp_nandflash_defconfig | 2 +- configs/sama5d3_xplained_nandflash_defconfig | 2 +- configs/sama5d3xek_nandflash_defconfig | 2 +- configs/sama5d4_xplained_nandflash_defconfig | 2 +- configs/sama5d4ek_nandflash_defconfig | 2 +- configs/smartweb_defconfig | 2 +- configs/smegw01_defconfig | 2 +- configs/socfpga_secu1_defconfig | 2 +- configs/socfpga_sr1500_defconfig | 2 +- configs/socfpga_vining_fpga_defconfig | 2 +- configs/socrates_defconfig | 2 +- configs/stm32mp13_defconfig | 2 +- configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig | 2 +- configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig | 2 +- .../stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig | 2 +- configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig | 2 +- configs/stm32mp15-odyssey_defconfig | 2 +- configs/stm32mp15_basic_defconfig | 2 +- configs/stm32mp15_defconfig | 2 +- configs/stm32mp15_trusted_defconfig | 2 +- configs/stm32mp25_defconfig | 2 +- configs/stm32mp_dhsom.config | 2 +- configs/taurus_defconfig | 2 +- .../theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig | 2 +- configs/theadorable-x86-conga-qa3-e3845_defconfig | 2 +- configs/theadorable-x86-dfi-bt700_defconfig | 2 +- configs/tqma6dl_mba6_spi_defconfig | 2 +- configs/tqma6q_mba6_spi_defconfig | 2 +- configs/tqma6s_mba6_spi_defconfig | 2 +- configs/tuge1_defconfig | 2 +- configs/tuxx1_defconfig | 2 +- configs/vining_2000_defconfig | 2 +- configs/work_92105_defconfig | 2 +- configs/xilinx_versal_net_virt_defconfig | 2 +- configs/xilinx_versal_virt_defconfig | 2 +- configs/xilinx_zynq_virt_defconfig | 2 +- configs/xilinx_zynqmp_kria_defconfig | 2 +- configs/xilinx_zynqmp_virt_defconfig | 2 +- env/Kconfig | 10 +++++----- env/common.c | 6 +++--- env/fat.c | 8 ++++---- env/mmc.c | 14 +++++++------- env/sf.c | 6 +++--- env/ubi.c | 16 ++++++++-------- include/env_default.h | 2 +- include/env_internal.h | 4 ++-- tools/envcrc.c | 2 +- 165 files changed, 190 insertions(+), 190 deletions(-) (limited to 'include') diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index c550e5e121e..7bfc39ed653 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -66,7 +66,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_ENV_IS_NOWHERE=y diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig index 19943881973..580b8fbb291 100644 --- a/configs/am335x_igep003x_defconfig +++ b/configs/am335x_igep003x_defconfig @@ -65,7 +65,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="config" CONFIG_ENV_UBI_VOLUME_REDUND="config_r" diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig index 2dfcd182cca..32790e852bc 100644 --- a/configs/am335x_shc_defconfig +++ b/configs/am335x_shc_defconfig @@ -58,7 +58,7 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig index 61527e2724a..82532c9e20b 100644 --- a/configs/am335x_shc_ict_defconfig +++ b/configs/am335x_shc_ict_defconfig @@ -56,7 +56,7 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig index da9c1b3d753..dc8582b9b18 100644 --- a/configs/am335x_shc_netboot_defconfig +++ b/configs/am335x_shc_netboot_defconfig @@ -60,7 +60,7 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig index 46e9e49a377..88b1a9fefb2 100644 --- a/configs/am335x_shc_sdboot_defconfig +++ b/configs/am335x_shc_sdboot_defconfig @@ -59,7 +59,7 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 1a48c05f06e..1e0e1fd66cc 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -55,7 +55,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_SYS_MMC_ENV_PART=2 diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig index d6c21869372..d735af9674b 100644 --- a/configs/am43xx_evm_qspiboot_defconfig +++ b/configs/am43xx_evm_qspiboot_defconfig @@ -35,7 +35,7 @@ CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig index f7ae7f51077..dd346d23946 100644 --- a/configs/am43xx_hs_evm_qspi_defconfig +++ b/configs/am43xx_hs_evm_qspi_defconfig @@ -36,7 +36,7 @@ CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig index ab45f5f7f10..8eb25f090a0 100644 --- a/configs/am57xx_evm_defconfig +++ b/configs/am57xx_evm_defconfig @@ -57,7 +57,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk" # CONFIG_ENV_IS_IN_FAT is not set -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig index e1fd680803f..2b10fb50698 100644 --- a/configs/am57xx_hs_evm_defconfig +++ b/configs/am57xx_hs_evm_defconfig @@ -50,7 +50,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk" # CONFIG_ENV_IS_IN_FAT is not set -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index d865b123b90..579e8d58734 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -54,7 +54,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index a41f67a43fe..4ee406b8347 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -72,7 +72,7 @@ CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/amd_versal2_virt_defconfig b/configs/amd_versal2_virt_defconfig index 6ec7dd317fd..88e8fbd1566 100644 --- a/configs/amd_versal2_virt_defconfig +++ b/configs/amd_versal2_virt_defconfig @@ -66,7 +66,7 @@ CONFIG_OF_BOARD=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index b6e259b490b..09cab1b3513 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -60,7 +60,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index 0ea13d46f31..61fa5011385 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -60,7 +60,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y diff --git a/configs/at91sam9260ek_nandflash_defconfig b/configs/at91sam9260ek_nandflash_defconfig index 4ee101ff641..bb5930cfbcd 100644 --- a/configs/at91sam9260ek_nandflash_defconfig +++ b/configs/at91sam9260ek_nandflash_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9261ek_nandflash_defconfig b/configs/at91sam9261ek_nandflash_defconfig index f53bf3c0450..07d7a792da5 100644 --- a/configs/at91sam9261ek_nandflash_defconfig +++ b/configs/at91sam9261ek_nandflash_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig index e51581848ac..284bf22c95e 100644 --- a/configs/at91sam9263ek_nandflash_defconfig +++ b/configs/at91sam9263ek_nandflash_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index 488c370581a..dcf6b417990 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x107D0000 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index d8c490d80de..337ba577fd9 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x107D0000 CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9g10ek_nandflash_defconfig b/configs/at91sam9g10ek_nandflash_defconfig index 580960e8181..3b53a17b693 100644 --- a/configs/at91sam9g10ek_nandflash_defconfig +++ b/configs/at91sam9g10ek_nandflash_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig index c4d12524282..58a75830bb0 100644 --- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig +++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9g20ek_nandflash_defconfig b/configs/at91sam9g20ek_nandflash_defconfig index e68f5036ca7..15378f5e128 100644 --- a/configs/at91sam9g20ek_nandflash_defconfig +++ b/configs/at91sam9g20ek_nandflash_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index e57bd2c8296..62f2a46425b 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index e7b4107f1e5..30470b5f450 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -40,7 +40,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=atmel_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,256k(env),256k(env_redundant),256k(spare),512k(dtb),6M(kernel)ro,-(rootfs)" CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig index c40e99817b9..7e31d11d0f2 100644 --- a/configs/at91sam9rlek_nandflash_defconfig +++ b/configs/at91sam9rlek_nandflash_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_NAND=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_CLK=y diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index 3f593953140..c6fa5a01359 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/at91sam9xeek_nandflash_defconfig b/configs/at91sam9xeek_nandflash_defconfig index 4ee101ff641..bb5930cfbcd 100644 --- a/configs/at91sam9xeek_nandflash_defconfig +++ b/configs/at91sam9xeek_nandflash_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index 6098e5caf5b..bc54795395e 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -75,7 +75,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_CLK=y diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig index ed026e58617..83008602004 100644 --- a/configs/bcm7260_defconfig +++ b/configs/bcm7260_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_DOS_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_MMC_SDHCI=y diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig index 07294451100..7f940e58339 100644 --- a/configs/bcm7445_defconfig +++ b/configs/bcm7445_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_DOS_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NO_NET=y CONFIG_MMC_SDHCI=y diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig index 2b72ec91632..511c86313c3 100644 --- a/configs/bk4r1_defconfig +++ b/configs/bk4r1_defconfig @@ -54,7 +54,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=500 CONFIG_NETCONSOLE=y diff --git a/configs/brcp150_defconfig b/configs/brcp150_defconfig index badde918f41..a3e7fc664b3 100644 --- a/configs/brcp150_defconfig +++ b/configs/brcp150_defconfig @@ -74,7 +74,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_NET_RETRY_COUNT=10 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_FPGA_XILINX=y diff --git a/configs/brcp170_defconfig b/configs/brcp170_defconfig index 209c4dfcec2..60b623bbdbe 100644 --- a/configs/brcp170_defconfig +++ b/configs/brcp170_defconfig @@ -73,7 +73,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_NET_RETRY_COUNT=10 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_FPGA_XILINX=y diff --git a/configs/brcp1_1r_defconfig b/configs/brcp1_1r_defconfig index f4a7071e8eb..023665566bb 100644 --- a/configs/brcp1_1r_defconfig +++ b/configs/brcp1_1r_defconfig @@ -73,7 +73,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_NET_RETRY_COUNT=10 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_FPGA_XILINX=y diff --git a/configs/brcp1_1r_switch_defconfig b/configs/brcp1_1r_switch_defconfig index c15033db9ee..2077b73c47e 100644 --- a/configs/brcp1_1r_switch_defconfig +++ b/configs/brcp1_1r_switch_defconfig @@ -73,7 +73,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_NET_RETRY_COUNT=10 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_FPGA_XILINX=y diff --git a/configs/brcp1_2r_defconfig b/configs/brcp1_2r_defconfig index ead2f1f5450..a881d5d4803 100644 --- a/configs/brcp1_2r_defconfig +++ b/configs/brcp1_2r_defconfig @@ -73,7 +73,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_NET_RETRY_COUNT=10 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_FPGA_XILINX=y diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index d96fdaa2887..743c3255e46 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -79,7 +79,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupt-controller interrupt-cells dma-names dmas " CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_SYS_MMC_ENV_PART=2 diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig index ee70220ebad..a31049d1f6b 100644 --- a/configs/brsmarc1_defconfig +++ b/configs/brsmarc1_defconfig @@ -83,7 +83,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/brsmarc2_defconfig b/configs/brsmarc2_defconfig index 5fdc669a12c..2bef76a3521 100644 --- a/configs/brsmarc2_defconfig +++ b/configs/brsmarc2_defconfig @@ -73,7 +73,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_NET_RETRY_COUNT=10 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_FPGA_XILINX=y diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index 245e4a582f2..030ce1a3158 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -73,7 +73,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_SYS_MMC_ENV_PART=2 diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index 8cb6b34ce76..3b4b04c9c88 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -46,7 +46,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nand:128k(NAND.SPL),128k(NAND.SPL.back CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index 85cd4623c48..729ebf7a6c8 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -67,7 +67,7 @@ CONFIG_CMD_MTDPARTS=y CONFIG_DOS_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y diff --git a/configs/display5_defconfig b/configs/display5_defconfig index a00a042ada6..950e4c5d84d 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -95,7 +95,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=02008000.spi.1:128k(SPL),1m(u-boot),64k(env1), CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOOTCOUNT_LIMIT=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 9965e00a1d0..3e545e5e12c 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -93,7 +93,7 @@ CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index f9cb732357c..ee4c91a2ed2 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -63,7 +63,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index f6f00454aaa..930abba1c84 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -55,7 +55,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y # CONFIG_ENV_IS_IN_FAT is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 850ccd934b7..9589d796464 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -51,7 +51,7 @@ CONFIG_SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x9000 CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/draco-etamin_defconfig b/configs/draco-etamin_defconfig index 6c175dd73b9..7fd2d87dfb9 100644 --- a/configs/draco-etamin_defconfig +++ b/configs/draco-etamin_defconfig @@ -69,7 +69,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x200000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/draco-rastaban_defconfig b/configs/draco-rastaban_defconfig index 521a090e376..9d8b5aff7a1 100644 --- a/configs/draco-rastaban_defconfig +++ b/configs/draco-rastaban_defconfig @@ -66,7 +66,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/draco-thuban_defconfig b/configs/draco-thuban_defconfig index 2c16db237f8..84fdd247c55 100644 --- a/configs/draco-thuban_defconfig +++ b/configs/draco-thuban_defconfig @@ -66,7 +66,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig index 5facd418260..5f2009ca1f2 100644 --- a/configs/e850-96_defconfig +++ b/configs/e850-96_defconfig @@ -33,7 +33,7 @@ CONFIG_CMD_RNG=y CONFIG_PARTITION_TYPE_GUID=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=2 CONFIG_NO_NET=y diff --git a/configs/edison_defconfig b/configs/edison_defconfig index 1294577ea8f..7e85a91898e 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -34,7 +34,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CPU=y CONFIG_DFU_TIMEOUT=y diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index fbcc84da9ae..e62e6ed397d 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -78,7 +78,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupts interrupt-parent interrupts-extended dmas dma-names" CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="ubi" CONFIG_ENV_UBI_VOLUME="uboot_env0" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_env1" diff --git a/configs/gardena-smart-gateway-mt7688_defconfig b/configs/gardena-smart-gateway-mt7688_defconfig index 109e7d0fc6c..d9ccf35afa3 100644 --- a/configs/gardena-smart-gateway-mt7688_defconfig +++ b/configs/gardena-smart-gateway-mt7688_defconfig @@ -71,7 +71,7 @@ CONFIG_MTDIDS_DEFAULT="spi-nand0=spi0.1,nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="spi0.0:640k(uboot),64k(uboot_env0),64k(uboot_env1),64k(factory),-(unused);spi0.1:-(nand)" CONFIG_CMD_UBI=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index 1fe7d2fc40b..a7a04bfa206 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -133,7 +133,7 @@ CONFIG_DOS_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xFE090000 CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 95d5b1172ff..cf1b3b6fa66 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -91,7 +91,7 @@ CONFIG_OF_LIST="imx6q-gw51xx imx6dl-gw51xx imx6q-gw52xx imx6dl-gw52xx imx6q-gw53 CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index 1d8af5ce103..2bc28f6203c 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -95,7 +95,7 @@ CONFIG_OF_LIST="imx6q-gw51xx imx6dl-gw51xx imx6q-gw52xx imx6dl-gw52xx imx6q-gw53 CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NETCONSOLE=y diff --git a/configs/gxp_defconfig b/configs/gxp_defconfig index ec05c2572e8..9578468bc48 100644 --- a/configs/gxp_defconfig +++ b/configs/gxp_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_GPT=y CONFIG_CMD_MISC=y CONFIG_CMD_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_NETCONSOLE=y CONFIG_MISC=y # CONFIG_MMC is not set diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index 0855081c9be..c2ece13e2a1 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -53,7 +53,7 @@ CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="config" CONFIG_ENV_UBI_VOLUME_REDUND="config_r" diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig index bf80a19bd96..8715893bbcc 100644 --- a/configs/imx28_xea_defconfig +++ b/configs/imx28_xea_defconfig @@ -94,7 +94,7 @@ CONFIG_SPL_OF_PLATDATA=y # CONFIG_SPL_OF_PLATDATA_PARENT is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_HOSTNAME=y diff --git a/configs/imx28_xea_sb_defconfig b/configs/imx28_xea_sb_defconfig index c7751b5dc93..d7b54baa749 100644 --- a/configs/imx28_xea_sb_defconfig +++ b/configs/imx28_xea_sb_defconfig @@ -62,7 +62,7 @@ CONFIG_SPL_OF_PLATDATA=y # CONFIG_SPL_OF_PLATDATA_PARENT is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_USE_HOSTNAME=y diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig index 017c27479d2..b6cbd9fbb66 100644 --- a/configs/imx6q_bosch_acc_defconfig +++ b/configs/imx6q_bosch_acc_defconfig @@ -76,7 +76,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y diff --git a/configs/imx8m_data_modul.config b/configs/imx8m_data_modul.config index 37e11e518a8..ab883259f09 100644 --- a/configs/imx8m_data_modul.config +++ b/configs/imx8m_data_modul.config @@ -202,7 +202,7 @@ CONFIG_SYS_MMC_ENV_PART=1 CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SYS_PBSIZE=2081 CONFIG_SYS_PROMPT="u-boot=> " -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_TEXT_BASE=0x40200000 CONFIG_TFTP_TSIZE=y diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index ea6a8789eea..064293c0f51 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -79,7 +79,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index 8a4bb896663..32063bc9280 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -91,7 +91,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig index 2b3c0969cfd..c57b63c1e75 100644 --- a/configs/imx8mm-phygate-tauri-l_defconfig +++ b/configs/imx8mm-phygate-tauri-l_defconfig @@ -73,7 +73,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig index 58dd8eb83f6..e6d0f41f418 100644 --- a/configs/imx8mm_phg_defconfig +++ b/configs/imx8mm_phg_defconfig @@ -62,7 +62,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index cc7dfcb1400..979c7b9d7f4 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -89,7 +89,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_LIST="freescale/imx8mm-venice-gw71xx-0x freescale/imx8mm-venice-gw72xx-0x freescale/imx8mm-venice-gw73xx-0x freescale/imx8mm-venice-gw7901 freescale/imx8mm-venice-gw7902 freescale/imx8mm-venice-gw7903 freescale/imx8mm-venice-gw7904 freescale/imx8mm-venice-gw75xx-0x" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index a7a838b61bb..2d9b716c862 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -88,7 +88,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 2e4cacf166d..bb43cf7ebfe 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -91,7 +91,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_OF_LIST="freescale/imx8mp-venice-gw71xx-2x freescale/imx8mp-venice-gw72xx-2x freescale/imx8mp-venice-gw73xx-2x freescale/imx8mp-venice-gw74xx freescale/imx8mp-venice-gw75xx-2x freescale/imx8mp-venice-gw82xx-2x" CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y diff --git a/configs/imx8qxp_capricorn.config b/configs/imx8qxp_capricorn.config index 463e584530f..7b034d5ff1e 100644 --- a/configs/imx8qxp_capricorn.config +++ b/configs/imx8qxp_capricorn.config @@ -10,7 +10,7 @@ CONFIG_NR_DRAM_BANKS=3 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_MMC_ENV_PART=2 CONFIG_DM_GPIO=y diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index 66a431244b0..fc6f4c77df2 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -85,7 +85,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_USE_ETHPRIME=y diff --git a/configs/imx_dhsom.config b/configs/imx_dhsom.config index d166b2cda2b..e293d61a488 100644 --- a/configs/imx_dhsom.config +++ b/configs/imx_dhsom.config @@ -25,7 +25,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SECT_SIZE_AUTO=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig index 5bb692ef3ad..55477c85807 100644 --- a/configs/iot2050_defconfig +++ b/configs/iot2050_defconfig @@ -83,7 +83,7 @@ CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_OF_LIST="ti/k3-am6528-iot2050-basic" CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SPL_REGMAP=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index a446074ad5d..2ae1743ac7b 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -78,7 +78,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/j721e_beagleboneai64_a72_defconfig b/configs/j721e_beagleboneai64_a72_defconfig index e3cd59343f0..25d2302bf1f 100644 --- a/configs/j721e_beagleboneai64_a72_defconfig +++ b/configs/j721e_beagleboneai64_a72_defconfig @@ -79,7 +79,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 99461cf6007..8aeeeb8bdc6 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -83,7 +83,7 @@ CONFIG_OF_LIST="ti/k3-j721e-common-proc-board" CONFIG_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 084deea28d0..1f216ffdf25 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -75,7 +75,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/j784s4_evm_a72_defconfig b/configs/j784s4_evm_a72_defconfig index 56af0230860..4589629c9ad 100644 --- a/configs/j784s4_evm_a72_defconfig +++ b/configs/j784s4_evm_a72_defconfig @@ -65,7 +65,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_UPSTREAM=y CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index 76e98c9b2a4..1668ce51883 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -55,7 +55,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xebf00000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="fm1-mac5" diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index cf50e2d27d8..69ef6cf3b9b 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -158,7 +158,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="UEC0" diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 7638fc2f5cf..267bbff81ae 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -137,7 +137,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="UEC0" diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 1c750455fc6..803eae06696 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -144,7 +144,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="UEC0" diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 5dd98175cd3..cd9bbc91e52 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -129,7 +129,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="UEC0" diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 2b240b3380d..f3bec1d569f 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -143,7 +143,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="UEC0" diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 9d37280138f..cdf8e406483 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -80,7 +80,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="imx8mm-kontron-bl imx8mm-kontron-bl-osm-s" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="kontron-mx8mm" diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index c5f145aadc1..6ddd21bd295 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -82,7 +82,7 @@ CONFIG_OF_UPSTREAM=y CONFIG_OF_LIST="freescale/fsl-ls1028a-kontron-sl28 freescale/fsl-ls1028a-kontron-sl28-var1 freescale/fsl-ls1028a-kontron-sl28-var2 freescale/fsl-ls1028a-kontron-sl28-var3 freescale/fsl-ls1028a-kontron-sl28-var4" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RX_ETH_BUFFER=8 CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SATA=y diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig index 25edee32462..54cfc855f1e 100644 --- a/configs/kp_imx53_defconfig +++ b/configs/kp_imx53_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ARP_TIMEOUT=200 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 7fd2bfb0efa..abc7f9fa3fe 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -47,7 +47,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents interrupts dmas dma-names" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ARP_TIMEOUT=200 diff --git a/configs/lxr2_defconfig b/configs/lxr2_defconfig index 0bc4ae0c7a5..a54f4ecbbef 100644 --- a/configs/lxr2_defconfig +++ b/configs/lxr2_defconfig @@ -71,7 +71,7 @@ CONFIG_EFI_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_ARP_TIMEOUT=200 diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index cc6ef49b1d0..a3333c2280c 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -70,7 +70,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="fitImage" diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig index 682ce3035b5..d9192617812 100644 --- a/configs/mccmon6_nor_defconfig +++ b/configs/mccmon6_nor_defconfig @@ -48,7 +48,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x8060000 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig index 665dc9ee45a..41ae748c97e 100644 --- a/configs/mccmon6_sd_defconfig +++ b/configs/mccmon6_sd_defconfig @@ -46,7 +46,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=8000000.nor:32m@0x0(mccmon6-image.nor),256k@0x CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x8060000 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 7497d20ee64..07612ef5e93 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_EMBED=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_USE_HOSTNAME=y CONFIG_HOSTNAME="microblaze-generic" CONFIG_NETCONSOLE=y diff --git a/configs/msc_sm2s_imx8mp_defconfig b/configs/msc_sm2s_imx8mp_defconfig index 6b2bb716293..9b0c529b3b2 100644 --- a/configs/msc_sm2s_imx8mp_defconfig +++ b/configs/msc_sm2s_imx8mp_defconfig @@ -65,7 +65,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y diff --git a/configs/mscc_jr2_defconfig b/configs/mscc_jr2_defconfig index 0577b12d17f..dc509426162 100644 --- a/configs/mscc_jr2_defconfig +++ b/configs/mscc_jr2_defconfig @@ -52,7 +52,7 @@ CONFIG_OF_LIST="jr2_pcb110 jr2_pcb111 serval2_pcb112" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig index dfd6bc08873..c4fe30c5255 100644 --- a/configs/mscc_luton_defconfig +++ b/configs/mscc_luton_defconfig @@ -55,7 +55,7 @@ CONFIG_OF_LIST="luton_pcb090 luton_pcb091" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig index 23aff7ea462..9c978201ee1 100644 --- a/configs/mscc_ocelot_defconfig +++ b/configs/mscc_ocelot_defconfig @@ -54,7 +54,7 @@ CONFIG_OF_LIST="ocelot_pcb120 ocelot_pcb123" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y diff --git a/configs/mscc_serval_defconfig b/configs/mscc_serval_defconfig index 6ddcbe1efee..c6835153066 100644 --- a/configs/mscc_serval_defconfig +++ b/configs/mscc_serval_defconfig @@ -49,7 +49,7 @@ CONFIG_OF_LIST="serval_pcb106 serval_pcb105" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y diff --git a/configs/mscc_servalt_defconfig b/configs/mscc_servalt_defconfig index 629b55561a1..0979143e4a3 100644 --- a/configs/mscc_servalt_defconfig +++ b/configs/mscc_servalt_defconfig @@ -47,7 +47,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:1m(UBoot),256k(Env),256k(Env.bk)" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index bf8fec5566f..dbd04b16786 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -54,7 +54,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="fitImage" diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index f7ed9e49359..1c96fd01eb8 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -73,7 +73,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_VERSION_VARIABLE=y diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig index d0d558ab11a..550e45b52ee 100644 --- a/configs/pcm052_defconfig +++ b/configs/pcm052_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VYBRID_GPIO=y CONFIG_DM_I2C=y diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig index 8ab2c1c069e..789c4c0f5ba 100644 --- a/configs/pcm058_defconfig +++ b/configs/pcm058_defconfig @@ -57,7 +57,7 @@ CONFIG_CMD_UBI=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index 4b82b077ea7..321e46e8c52 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -64,7 +64,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x60040000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index 53d54789687..b53af5be52c 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -62,7 +62,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x60200000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index 731ca435089..561df3ee009 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -64,7 +64,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x60040000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index 2598e477ed5..2a631176095 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -62,7 +62,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0x60200000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="ethernet@2d90000" diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 8f52ec2ab90..4558bf89c12 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -79,7 +79,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index ed2171540af..9c88d53b8e4 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -92,7 +92,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig index 11aaec67e2e..dd55893bddd 100644 --- a/configs/phycore_am62ax_a53_defconfig +++ b/configs/phycore_am62ax_a53_defconfig @@ -89,7 +89,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 5f91ca647fd..6a811ca4e7e 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -92,7 +92,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index 8b508d011e0..11482223247 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -92,7 +92,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig index fa8b53848b4..6d8ff63ba6c 100644 --- a/configs/pm9g45_defconfig +++ b/configs/pm9g45_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_CLK=y diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig index c1754e80dd1..2fab32b51d0 100644 --- a/configs/sam9x60ek_nandflash_defconfig +++ b/configs/sam9x60ek_nandflash_defconfig @@ -54,7 +54,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig index 0729cad701b..320be1be89f 100644 --- a/configs/sama5d2_ptc_ek_nandflash_defconfig +++ b/configs/sama5d2_ptc_ek_nandflash_defconfig @@ -47,7 +47,7 @@ CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_CLK=y CONFIG_CLK_AT91=y diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig index 595cb9cb17f..91fcd73f01e 100644 --- a/configs/sama5d36ek_cmp_nandflash_defconfig +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_CLK=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index 0e3eb7d7b01..831fccc485e 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -69,7 +69,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index 995c9de1c80..4eefe091c90 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -67,7 +67,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 5401f34adc6..43a40d370ad 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -65,7 +65,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_CLK=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index b22e0dd18a3..268e04676a5 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -64,7 +64,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas" CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 7253c997b24..cca9cb8f6e7 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -71,7 +71,7 @@ CONFIG_OF_EMBED=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_RANGE=0x80000 -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RETRY_COUNT=20 CONFIG_CLK=y diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig index ae6c9b60cd5..fe7cbc765b7 100644 --- a/configs/smegw01_defconfig +++ b/configs/smegw01_defconfig @@ -49,7 +49,7 @@ CONFIG_CMD_SQUASHFS=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_ENV_WRITEABLE_LIST=y diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index f7ae13c891b..5fe35fe6eb8 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -67,7 +67,7 @@ CONFIG_CMD_UBI=y # CONFIG_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="zImage" CONFIG_VERSION_VARIABLE=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 820b935b70a..39126d38d2b 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -54,7 +54,7 @@ CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_VERSION_VARIABLE=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index b4e303ed6dd..031a0f25086 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -61,7 +61,7 @@ CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="fitImage" diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 93d2736ba89..d17b86b344d 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -68,7 +68,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=fe000000.nor_flash:13312k(system1),13312k(syst # CONFIG_CMD_IRQ is not set CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xFFF00000 CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index 530f6aa6380..a327d792579 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_DEV=-1 CONFIG_ENV_MMC_USE_DT=y diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig index fc095ac0de1..ff7afa02789 100644 --- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig @@ -57,7 +57,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set CONFIG_USE_SERVERIP=y diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig index b243c45d690..0828e0cccb5 100644 --- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig +++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig @@ -57,7 +57,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set CONFIG_USE_SERVERIP=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig index e635c726459..da37b553367 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig @@ -57,7 +57,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set CONFIG_USE_SERVERIP=y diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig index 9e7849ff8f0..90962431ce4 100644 --- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig +++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig @@ -57,7 +57,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y # CONFIG_SPL_ENV_IS_NOWHERE is not set CONFIG_USE_SERVERIP=y diff --git a/configs/stm32mp15-odyssey_defconfig b/configs/stm32mp15-odyssey_defconfig index 74fd2fb8e63..6c7cbc82c67 100644 --- a/configs/stm32mp15-odyssey_defconfig +++ b/configs/stm32mp15-odyssey_defconfig @@ -59,7 +59,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index e3090ec2a50..89735f5f5c6 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -88,7 +88,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index 5ddec18b520..af5f30509a6 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -60,7 +60,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index f0e6b64ffde..56a76e226ff 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -61,7 +61,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig index 317a6d5ecd6..f87812fa080 100644 --- a/configs/stm32mp25_defconfig +++ b/configs/stm32mp25_defconfig @@ -43,7 +43,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_IS_IN_UBI=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" diff --git a/configs/stm32mp_dhsom.config b/configs/stm32mp_dhsom.config index 01d65cfd893..2e69a047ba9 100644 --- a/configs/stm32mp_dhsom.config +++ b/configs/stm32mp_dhsom.config @@ -83,7 +83,7 @@ CONFIG_SYS_DISABLE_AUTOLOAD=y CONFIG_SYS_I2C_STM32F7=y CONFIG_SYS_LOAD_ADDR=0xc2000000 CONFIG_SYS_PROMPT="STM32MP> " -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_TFTP_TSIZE=y CONFIG_USB=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index 29fa4ea42af..dab30ce295e 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -81,7 +81,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_SPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SPL_DM=y CONFIG_CLK=y diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig index fed54bc8207..393284fa5c4 100644 --- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig @@ -49,7 +49,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_ISO_PARTITION=y CONFIG_AMIGA_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig index af81e78ccf5..803152b0b59 100644 --- a/configs/theadorable-x86-conga-qa3-e3845_defconfig +++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig @@ -48,7 +48,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig index 0c9e6090617..9b64b6ef9d0 100644 --- a/configs/theadorable-x86-dfi-bt700_defconfig +++ b/configs/theadorable-x86-dfi-bt700_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig index 953ceba6626..c2bd47359ab 100644 --- a/configs/tqma6dl_mba6_spi_defconfig +++ b/configs/tqma6dl_mba6_spi_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig index 28b1bfc41f4..1a1248f2314 100644 --- a/configs/tqma6q_mba6_spi_defconfig +++ b/configs/tqma6q_mba6_spi_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig index 0af80d5c2e1..39d2d8ab5e1 100644 --- a/configs/tqma6s_mba6_spi_defconfig +++ b/configs/tqma6s_mba6_spi_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index ab0fd12bc48..dad17b39436 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -129,7 +129,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="UEC0" diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index e5a99b24dab..1ef7a472ace 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -143,7 +143,7 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=boot:768k(u-boot),128k(env),128k(envred),-(ubi CONFIG_CMD_UBI=y # CONFIG_CMD_UBIFS is not set CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_ADDR_REDUND=0xF00E0000 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="UEC0" diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 5842916fbdb..e6de7431788 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -62,7 +62,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 0b4989ca002..0091a897ab6 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_DOS_PARTITION=y CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="uImage" CONFIG_VERSION_VARIABLE=y diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig index a82ccdc9a0c..2dce60298ef 100644 --- a/configs/xilinx_versal_net_virt_defconfig +++ b/configs/xilinx_versal_net_virt_defconfig @@ -66,7 +66,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig index ba4519ce303..82e346f5ba4 100644 --- a/configs/xilinx_versal_virt_defconfig +++ b/configs/xilinx_versal_virt_defconfig @@ -70,7 +70,7 @@ CONFIG_OF_BOARD=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 6859e24b731..9a058d5bc15 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -93,7 +93,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/xilinx_zynqmp_kria_defconfig b/configs/xilinx_zynqmp_kria_defconfig index ae79f101701..3c9fcf59400 100644 --- a/configs/xilinx_zynqmp_kria_defconfig +++ b/configs/xilinx_zynqmp_kria_defconfig @@ -117,7 +117,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_FAT_DEVICE_AND_PART=":auto" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 29aa5891b23..f736f17466d 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -116,7 +116,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_IS_IN_NAND=y CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_REDUNDANT=y CONFIG_ENV_FAT_DEVICE_AND_PART=":auto" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_LWIP=y diff --git a/env/Kconfig b/env/Kconfig index ee47b565213..414db543b82 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -489,7 +489,7 @@ config ENV_IS_IN_UBI the environment in. This will enable redundant environments in UBI. It is assumed that both volumes are in the same MTD partition. -config SYS_REDUNDAND_ENVIRONMENT +config ENV_REDUNDANT bool "Enable redundant environment support" help Normally, the environemt is stored in a single location. By @@ -543,7 +543,7 @@ config ENV_FAT_FILE config ENV_FAT_FILE_REDUND string "Name of the FAT file to use for the environment" - depends on ENV_IS_IN_FAT && SYS_REDUNDAND_ENVIRONMENT + depends on ENV_IS_IN_FAT && ENV_REDUNDANT default "uboot-redund.env" help It's a string of the FAT file name. This file use to store the @@ -595,7 +595,7 @@ config ENV_ADDR config ENV_ADDR_REDUND hex "Redundant environment address" - depends on ENV_IS_IN_FLASH && SYS_REDUNDAND_ENVIRONMENT + depends on ENV_IS_IN_FLASH && ENV_REDUNDANT help Offset from the start of the device (or partition) of the redundant environment location. @@ -625,7 +625,7 @@ config ENV_OFFSET config ENV_OFFSET_REDUND hex "Redundant environment offset" depends on (ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \ - ENV_IS_IN_SPI_FLASH) && SYS_REDUNDAND_ENVIRONMENT + ENV_IS_IN_SPI_FLASH) && ENV_REDUNDANT default 0x10C0000 if MICROBLAZE default 0x0 help @@ -675,7 +675,7 @@ config ENV_UBI_VOLUME config ENV_UBI_VOLUME_REDUND string "UBI redundant volume name" - depends on ENV_IS_IN_UBI && SYS_REDUNDAND_ENVIRONMENT + depends on ENV_IS_IN_UBI && ENV_REDUNDANT help Name of the redundant volume that you want to store the environment in. diff --git a/env/common.c b/env/common.c index 86122582bc1..1e23c5de436 100644 --- a/env/common.c +++ b/env/common.c @@ -466,7 +466,7 @@ int env_import(const char *buf, int check, int flags) return -EIO; } -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +#ifdef CONFIG_ENV_REDUNDANT static unsigned char env_flags; int env_check_redund(const char *buf1, int buf1_read_fail, @@ -543,7 +543,7 @@ int env_import_redund(const char *buf1, int buf1_read_fail, return env_import((char *)ep, 0, flags); } -#endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */ +#endif /* CONFIG_ENV_REDUNDANT */ /* Export the environment and generate CRC for it. */ int env_export(env_t *env_out) @@ -560,7 +560,7 @@ int env_export(env_t *env_out) env_out->crc = crc32(0, env_out->data, ENV_SIZE); -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +#ifdef CONFIG_ENV_REDUNDANT env_out->flags = ++env_flags; /* increase the serial */ #endif diff --git a/env/fat.c b/env/fat.c index 1ad301eaaff..65ee1c8e086 100644 --- a/env/fat.c +++ b/env/fat.c @@ -86,7 +86,7 @@ static int env_fat_save(void) return 1; } -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +#ifdef CONFIG_ENV_REDUNDANT if (gd->env_valid == ENV_VALID) file = CONFIG_ENV_FAT_FILE_REDUND; #endif @@ -101,7 +101,7 @@ static int env_fat_save(void) return 1; } -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +#ifdef CONFIG_ENV_REDUNDANT gd->env_valid = (gd->env_valid == ENV_REDUND) ? ENV_VALID : ENV_REDUND; #endif @@ -112,7 +112,7 @@ static int env_fat_save(void) static int env_fat_load(void) { ALLOC_CACHE_ALIGN_BUFFER(char, buf1, CONFIG_ENV_SIZE); -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +#ifdef CONFIG_ENV_REDUNDANT ALLOC_CACHE_ALIGN_BUFFER(char, buf2, CONFIG_ENV_SIZE); int err2; #endif @@ -153,7 +153,7 @@ static int env_fat_load(void) } err1 = file_fat_read(CONFIG_ENV_FAT_FILE, buf1, CONFIG_ENV_SIZE); -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +#ifdef CONFIG_ENV_REDUNDANT err2 = file_fat_read(CONFIG_ENV_FAT_FILE_REDUND, buf2, CONFIG_ENV_SIZE); err1 = (err1 >= 0) ? 0 : -1; diff --git a/env/mmc.c b/env/mmc.c index 8848371eb4f..5451f914027 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -186,7 +186,7 @@ static inline s64 mmc_offset(struct mmc *mmc, int copy) defvalue = ENV_MMC_OFFSET; propname = dt_prop.offset; - if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT) && copy) { + if (IS_ENABLED(CONFIG_ENV_REDUNDANT) && copy) { defvalue = ENV_MMC_OFFSET_REDUND; propname = dt_prop.offset_redund; } @@ -198,7 +198,7 @@ static inline s64 mmc_offset(struct mmc *mmc, int copy) { s64 offset = ENV_MMC_OFFSET; - if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT) && copy) + if (IS_ENABLED(CONFIG_ENV_REDUNDANT) && copy) offset = ENV_MMC_OFFSET_REDUND; return offset; @@ -213,7 +213,7 @@ static bool mmc_env_is_redundant_in_both_boot_hwparts(struct mmc *mmc) * identical, store the environment and redundant environment in both * eMMC boot partitions, one copy in each. */ - if (!IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) + if (!IS_ENABLED(CONFIG_ENV_REDUNDANT)) return false; if (CONFIG_SYS_MMC_ENV_PART != 1) @@ -337,7 +337,7 @@ static int env_mmc_save(void) if (ret) goto fini; - if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) { + if (IS_ENABLED(CONFIG_ENV_REDUNDANT)) { if (gd->env_valid == ENV_VALID) copy = 1; @@ -362,7 +362,7 @@ static int env_mmc_save(void) ret = 0; - if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) + if (IS_ENABLED(CONFIG_ENV_REDUNDANT)) gd->env_valid = gd->env_valid == ENV_REDUND ? ENV_VALID : ENV_REDUND; fini: @@ -411,7 +411,7 @@ static int env_mmc_erase(void) printf("\n"); ret = erase_env(mmc, CONFIG_ENV_SIZE, offset); - if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) { + if (IS_ENABLED(CONFIG_ENV_REDUNDANT)) { copy = 1; if (mmc_env_is_redundant_in_both_boot_hwparts(mmc)) { @@ -555,7 +555,7 @@ static int env_mmc_load(void) { if (IS_ENABLED(ENV_IS_EMBEDDED)) return 0; - else if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) + else if (IS_ENABLED(CONFIG_ENV_REDUNDANT)) return env_mmc_load_redundant(); else return env_mmc_load_singular(); diff --git a/env/sf.c b/env/sf.c index eb4c8d5ec95..0b70e18b9af 100644 --- a/env/sf.c +++ b/env/sf.c @@ -380,7 +380,7 @@ static int env_sf_init_early(void) tmp_env1 = (env_t *)memalign(ARCH_DMA_MINALIGN, CONFIG_ENV_SIZE); - if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) + if (IS_ENABLED(CONFIG_ENV_REDUNDANT)) tmp_env2 = (env_t *)memalign(ARCH_DMA_MINALIGN, CONFIG_ENV_SIZE); @@ -394,7 +394,7 @@ static int env_sf_init_early(void) read1_fail = spi_flash_read(env_flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, tmp_env1); - if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) { + if (IS_ENABLED(CONFIG_ENV_REDUNDANT)) { read2_fail = spi_flash_read(env_flash, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE, tmp_env2); @@ -429,7 +429,7 @@ err_read: spi_flash_free(env_flash); free(tmp_env1); - if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) + if (IS_ENABLED(CONFIG_ENV_REDUNDANT)) free(tmp_env2); out: /* env is not valid. always return 0 */ diff --git a/env/ubi.c b/env/ubi.c index 2f4ca571edb..f424b1a16e8 100644 --- a/env/ubi.c +++ b/env/ubi.c @@ -27,14 +27,14 @@ DECLARE_GLOBAL_DATA_PTR; -#if CONFIG_SYS_REDUNDAND_ENVIRONMENT +#if CONFIG_ENV_REDUNDANT #define ENV_UBI_VOLUME_REDUND CONFIG_ENV_UBI_VOLUME_REDUND #else #define ENV_UBI_VOLUME_REDUND "invalid" #endif #ifdef CONFIG_CMD_SAVEENV -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +#ifdef CONFIG_ENV_REDUNDANT static int env_ubi_save(void) { ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); @@ -76,7 +76,7 @@ static int env_ubi_save(void) return 0; } -#else /* ! CONFIG_SYS_REDUNDAND_ENVIRONMENT */ +#else /* ! CONFIG_ENV_REDUNDANT */ static int env_ubi_save(void) { ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); @@ -102,10 +102,10 @@ static int env_ubi_save(void) puts("done\n"); return 0; } -#endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */ +#endif /* CONFIG_ENV_REDUNDANT */ #endif /* CONFIG_CMD_SAVEENV */ -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +#ifdef CONFIG_ENV_REDUNDANT static int env_ubi_load(void) { ALLOC_CACHE_ALIGN_BUFFER(char, env1_buf, CONFIG_ENV_SIZE); @@ -149,7 +149,7 @@ static int env_ubi_load(void) return env_import_redund((char *)tmp_env1, read1_fail, (char *)tmp_env2, read2_fail, H_EXTERNAL); } -#else /* ! CONFIG_SYS_REDUNDAND_ENVIRONMENT */ +#else /* ! CONFIG_ENV_REDUNDANT */ static int env_ubi_load(void) { ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE); @@ -180,7 +180,7 @@ static int env_ubi_load(void) return env_import(buf, 1, H_EXTERNAL); } -#endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */ +#endif /* CONFIG_ENV_REDUNDANT */ static int env_ubi_erase(void) { @@ -202,7 +202,7 @@ static int env_ubi_erase(void) CONFIG_ENV_UBI_VOLUME); ret = 1; } - if (IS_ENABLED(CONFIG_SYS_REDUNDAND_ENVIRONMENT)) { + if (IS_ENABLED(CONFIG_ENV_REDUNDANT)) { if (ubi_volume_write(ENV_UBI_VOLUME_REDUND, (void *)env_buf, 0, CONFIG_ENV_SIZE)) { printf("\n** Unable to erase env to %s:%s **\n", diff --git a/include/env_default.h b/include/env_default.h index 60c39f9853f..6e8f2ea90e7 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -16,7 +16,7 @@ #ifdef DEFAULT_ENV_INSTANCE_EMBEDDED env_t embedded_environment __UBOOT_ENV_SECTION__(environment) = { ENV_CRC, /* CRC Sum */ -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +#ifdef CONFIG_ENV_REDUNDANT 1, /* Flags: valid */ #endif { diff --git a/include/env_internal.h b/include/env_internal.h index 75b46d0bcb0..0589c435e84 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -53,7 +53,7 @@ extern unsigned long nand_env_oob_offset; #include "compiler.h" -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +#ifdef CONFIG_ENV_REDUNDANT # define ENV_HEADER_SIZE (sizeof(uint32_t) + 1) #else # define ENV_HEADER_SIZE (sizeof(uint32_t)) @@ -77,7 +77,7 @@ extern unsigned long nand_env_oob_offset; typedef struct environment_s { uint32_t crc; /* CRC32 over data bytes */ -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +#ifdef CONFIG_ENV_REDUNDANT unsigned char flags; /* active/obsolete flags ENVF_REDUND_ */ #endif unsigned char data[ENV_SIZE]; /* Environment data */ diff --git a/tools/envcrc.c b/tools/envcrc.c index 09051800364..7f680fb8a95 100644 --- a/tools/envcrc.c +++ b/tools/envcrc.c @@ -40,7 +40,7 @@ # endif #endif /* CONFIG_ENV_IS_IN_FLASH */ -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT +#ifdef CONFIG_ENV_REDUNDANT # define ENV_HEADER_SIZE (sizeof(uint32_t) + 1) #else # define ENV_HEADER_SIZE (sizeof(uint32_t)) -- cgit v1.3.1 From 0f44d5549ed814744b95b2450fbacfa14192587d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 9 Jun 2025 21:26:39 +0200 Subject: env: Rename SYS_MMC_ENV_DEV to ENV_MMC_DEVICE_INDEX Rename the variable and add ENV_ prefix, so that all configuration options which are related to environment would have an CONFIG_ENV_ prefix. No functional change. Use ENV_MMC_DEVICE_INDEX to clarify this is the SD/MMC device index, a number, as enumerated by U-Boot. Update the help text accordingly. Signed-off-by: Marek Vasut --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- arch/arm/mach-imx/imx8/cpu.c | 4 ++-- arch/arm/mach-imx/imx8ulp/soc.c | 4 ++-- arch/arm/mach-imx/imx9/scmi/soc.c | 4 ++-- arch/arm/mach-imx/imx9/soc.c | 4 ++-- arch/arm/mach-imx/mmc_env.c | 4 ++-- arch/arm/mach-imx/mx6/soc.c | 4 ++-- arch/arm/mach-imx/mx7ulp/soc.c | 4 ++-- arch/arm/mach-mvebu/armada8k/cpu.c | 2 +- arch/arm/mach-rockchip/board.c | 4 ++-- board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env | 2 +- board/freescale/imx8mm_evk/imx8mm_evk.env | 2 +- board/freescale/imx8mn_evk/imx8mn_evk.env | 2 +- board/freescale/imx8mp_evk/imx8mp_evk.env | 2 +- board/freescale/imx8mq_evk/imx8mq_evk.env | 2 +- board/freescale/imx91_evk/imx91_evk.env | 2 +- board/freescale/imx93_evk/imx93_evk.env | 2 +- board/freescale/imx93_qsb/imx93_qsb.env | 2 +- board/freescale/imx95_evk/imx95_19x19_evk.env | 2 +- board/grinn/liteboard/board.c | 2 +- board/phytec/common/k3/board.c | 2 +- board/phytec/phycore_imx8mm/phycore_imx8mm.env | 2 +- board/phytec/phycore_imx8mp/phycore_imx8mp.env | 2 +- board/phytec/phycore_imx93/phycore_imx93.env | 2 +- board/st/stm32mp1/stm32mp1.c | 2 +- board/st/stm32mp2/stm32mp2.c | 2 +- board/sunxi/board.c | 4 ++-- cmd/mvebu/bubt.c | 4 ++-- configs/am335x_shc_defconfig | 2 +- configs/am335x_shc_ict_defconfig | 2 +- configs/am335x_sl50_defconfig | 2 +- configs/am57xx_hs_evm_usb_defconfig | 2 +- configs/brppt1_mmc_defconfig | 2 +- configs/brxre1_defconfig | 2 +- configs/cgtqmx8_defconfig | 2 +- configs/dra7xx_evm_defconfig | 2 +- configs/dra7xx_hs_evm_defconfig | 2 +- configs/dra7xx_hs_evm_usb_defconfig | 2 +- configs/evb-rk3328_defconfig | 2 +- configs/ficus-rk3399_defconfig | 2 +- configs/hihope_rzg2_defconfig | 2 +- configs/imx6dl_mamoj_defconfig | 2 +- configs/imx8mm-cl-iot-gate-optee_defconfig | 2 +- configs/imx8mm-cl-iot-gate_defconfig | 2 +- configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 2 +- configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 2 +- configs/imx8mm-phygate-tauri-l_defconfig | 2 +- configs/imx8mm_beacon_defconfig | 2 +- configs/imx8mm_beacon_fspi_defconfig | 2 +- configs/imx8mm_evk_defconfig | 2 +- configs/imx8mm_evk_fspi_defconfig | 2 +- configs/imx8mm_venice_defconfig | 2 +- configs/imx8mn_beacon_2g_defconfig | 2 +- configs/imx8mn_beacon_defconfig | 2 +- configs/imx8mn_beacon_fspi_defconfig | 2 +- configs/imx8mn_ddr4_evk_defconfig | 2 +- configs/imx8mn_var_som_defconfig | 2 +- configs/imx8mn_venice_defconfig | 2 +- configs/imx8mp-icore-mx8mp-edimm2.2_defconfig | 2 +- configs/imx8mp_beacon_defconfig | 2 +- configs/imx8mp_debix_model_a_defconfig | 2 +- configs/imx8mp_evk_defconfig | 2 +- configs/imx8mp_navqp_defconfig | 2 +- configs/imx8mp_rsb3720a1_4G_defconfig | 2 +- configs/imx8mp_rsb3720a1_6G_defconfig | 2 +- configs/imx8mp_venice_defconfig | 2 +- configs/imx8mq_cm_defconfig | 2 +- configs/imx8mq_evk_defconfig | 2 +- configs/imx8mq_phanbell_defconfig | 2 +- configs/imx8mq_reform2_defconfig | 2 +- configs/imx8qm_dmsse20a1_defconfig | 2 +- configs/imx8qm_mek_defconfig | 2 +- configs/imx8qm_rom7720_a1_4G_defconfig | 2 +- configs/imx8qxp_mek_defconfig | 2 +- configs/imx91_11x11_evk_defconfig | 2 +- configs/imx91_11x11_evk_inline_ecc_defconfig | 2 +- configs/imx93-phycore_defconfig | 2 +- configs/imx93_11x11_evk_defconfig | 2 +- configs/imx93_9x9_qsb_defconfig | 2 +- configs/imx93_9x9_qsb_inline_ecc_defconfig | 2 +- configs/imx93_var_som_defconfig | 2 +- configs/imx95_19x19_evk_defconfig | 2 +- configs/khadas-vim3_android_ab_defconfig | 2 +- configs/khadas-vim3_android_defconfig | 2 +- configs/khadas-vim3l_android_ab_defconfig | 2 +- configs/khadas-vim3l_android_defconfig | 2 +- configs/kp_imx6q_tpc_defconfig | 2 +- configs/mvebu_crb_cn9130_defconfig | 2 +- configs/mvebu_db_cn9130_defconfig | 2 +- configs/mx6sabresd_defconfig | 2 +- configs/mx6sxsabresd_defconfig | 2 +- configs/mx6ul_14x14_evk_defconfig | 2 +- configs/mx6ul_9x9_evk_defconfig | 2 +- configs/mx6ull_14x14_evk_defconfig | 2 +- configs/mx6ull_14x14_evk_plugin_defconfig | 2 +- configs/mx6ulz_14x14_evk_defconfig | 2 +- configs/nanopi-r2c-plus-rk3328_defconfig | 2 +- configs/nanopi-r2c-rk3328_defconfig | 2 +- configs/nanopi-r2s-rk3328_defconfig | 2 +- configs/orangepi-r1-plus-lts-rk3328_defconfig | 2 +- configs/orangepi-r1-plus-rk3328_defconfig | 2 +- configs/phycore-imx8mm_defconfig | 2 +- configs/phycore-imx8mp_defconfig | 2 +- configs/phycore-rk3288_defconfig | 2 +- configs/phycore_am62ax_a53_defconfig | 2 +- configs/phycore_am62x_a53_defconfig | 2 +- configs/phycore_am64x_a53_defconfig | 2 +- configs/pico-imx8mq_defconfig | 2 +- configs/puma-rk3399_defconfig | 2 +- configs/riotboard_defconfig | 2 +- configs/roc-cc-rk3328_defconfig | 2 +- configs/rock-pi-e-rk3328_defconfig | 2 +- configs/rock-pi-e-v3-rk3328_defconfig | 2 +- configs/rock64-rk3328_defconfig | 2 +- configs/rock960-rk3399_defconfig | 2 +- configs/s5p4418_nanopi2_defconfig | 2 +- configs/sei510_defconfig | 2 +- configs/sei610_defconfig | 2 +- configs/smegw01_defconfig | 2 +- configs/somlabs_visionsom_6ull_defconfig | 2 +- configs/stm32mp13_defconfig | 2 +- configs/stm32mp13_dhcor_defconfig | 2 +- configs/stm32mp15-odyssey_defconfig | 2 +- configs/stm32mp15_basic_defconfig | 2 +- configs/stm32mp15_defconfig | 2 +- configs/stm32mp15_trusted_defconfig | 2 +- configs/stm32mp25_defconfig | 2 +- configs/tbs2910_defconfig | 2 +- configs/tinker-rk3288_defconfig | 2 +- configs/tinker-s-rk3288_defconfig | 2 +- configs/udoo_defconfig | 2 +- configs/udoo_neo_defconfig | 2 +- configs/verdin-imx8mp_defconfig | 2 +- configs/vyasa-rk3288_defconfig | 2 +- configs/x250_defconfig | 2 +- doc/device-tree-bindings/config.txt | 2 +- drivers/mmc/mmc.c | 4 ++-- drivers/net/fm/fm.c | 8 ++++---- drivers/net/phy/cortina.c | 8 ++++---- drivers/qe/qe.c | 8 ++++---- env/Kconfig | 10 ++++++---- env/mmc.c | 2 +- include/configs/cgtqmx8.h | 2 +- include/configs/imx7-cm.h | 2 +- include/configs/imx8mm-cl-iot-gate.h | 2 +- include/configs/imx8mp_rsb3720.h | 2 +- include/configs/imx8mq_phanbell.h | 2 +- include/configs/imx8qm_mek.h | 2 +- include/configs/imx8qm_rom7720.h | 2 +- include/configs/imx8qxp_mek.h | 2 +- include/configs/imx93_evk.h | 4 ++-- include/configs/liteboard.h | 2 +- include/configs/mx6cuboxi.h | 2 +- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6sllevk.h | 2 +- include/configs/mx6ul_14x14_evk.h | 2 +- include/configs/mx6ullevk.h | 2 +- include/configs/mx7ulp_com.h | 2 +- include/configs/mx7ulp_evk.h | 2 +- include/configs/pico-imx6.h | 2 +- include/configs/pico-imx8mq.h | 2 +- include/configs/tqma6.h | 2 +- include/configs/vf610twr.h | 2 +- include/configs/wandboard.h | 2 +- include/configs/warp7.h | 2 +- include/configs/xpress.h | 2 +- 166 files changed, 192 insertions(+), 190 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d2d3e346a36..cfbaa475701 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -802,7 +802,7 @@ enum boot_src get_boot_src(void) int mmc_get_env_dev(void) { enum boot_src src = get_boot_src(); - int dev = CONFIG_SYS_MMC_ENV_DEV; + int dev = CONFIG_ENV_MMC_DEVICE_INDEX; switch (src) { case BOOT_SOURCE_SD_MMC: diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c index 37a5473ac7c..0e112af661c 100644 --- a/arch/arm/mach-imx/imx8/cpu.c +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -451,7 +451,7 @@ void get_board_serial(struct tag_serialnr *serialnr) #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } int mmc_get_env_dev(void) @@ -473,7 +473,7 @@ int mmc_get_env_dev(void) break; default: /* If not boot from sd/mmc, use default value */ - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } return board_mmc_get_env_dev(devno); diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index b5dc45296d1..ab1e1bc12bd 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -56,7 +56,7 @@ int mmc_get_env_dev(void) if (ret != ROM_API_OKAY) { puts("ROMAPI: failure at query_boot_info\n"); - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } boot_type = boot >> 16; @@ -64,7 +64,7 @@ int mmc_get_env_dev(void) /* If not boot from sd/mmc, use default value */ if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC) - return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); + return env_get_ulong("mmcdev", 10, CONFIG_ENV_MMC_DEVICE_INDEX); return board_mmc_get_env_dev(boot_instance); } diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index d2b0455bff9..8338527d24f 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -84,7 +84,7 @@ int mmc_get_env_dev(void) ret = scmi_get_rom_data(rdata); if (ret != 0) { puts("SCMI: failure at rom_boot_info\n"); - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } } boot_type = rdata->boot_dev_type; @@ -95,7 +95,7 @@ int mmc_get_env_dev(void) /* If not boot from sd/mmc, use default value */ if (boot_type != BOOT_TYPE_SD && boot_type != BOOT_TYPE_MMC) - return env_get_ulong("mmcdev", 10, CONFIG_SYS_MMC_ENV_DEV); + return env_get_ulong("mmcdev", 10, CONFIG_ENV_MMC_DEVICE_INDEX); return board_mmc_get_env_dev(boot_instance); } diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index bb13ca742e3..02db7cc97ba 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -48,8 +48,8 @@ __weak int board_mmc_get_env_dev(int devno) return devno; } -#ifdef CONFIG_SYS_MMC_ENV_DEV -#define IMX9_MMC_ENV_DEV CONFIG_SYS_MMC_ENV_DEV +#ifdef CONFIG_ENV_MMC_DEVICE_INDEX +#define IMX9_MMC_ENV_DEV CONFIG_ENV_MMC_DEVICE_INDEX #else #define IMX9_MMC_ENV_DEV 0 #endif diff --git a/arch/arm/mach-imx/mmc_env.c b/arch/arm/mach-imx/mmc_env.c index 34a7d1706f3..2ec8ddf4d59 100644 --- a/arch/arm/mach-imx/mmc_env.c +++ b/arch/arm/mach-imx/mmc_env.c @@ -10,7 +10,7 @@ __weak int board_mmc_get_env_dev(int devno) { - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } int mmc_get_env_dev(void) @@ -22,7 +22,7 @@ int mmc_get_env_dev(void) /* If not boot from sd/mmc, use default value */ if ((boot_type != BOOT_TYPE_SD) && (boot_type != BOOT_TYPE_MMC)) - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; return board_mmc_get_env_dev(devno); } diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index d4a61731a67..90fe9e7c19b 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -502,7 +502,7 @@ int arch_cpu_init(void) #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } static int mmc_get_boot_dev(void) @@ -535,7 +535,7 @@ int mmc_get_env_dev(void) /* If not boot from sd/mmc, use default value */ if (devno < 0) - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; return board_mmc_get_env_dev(devno); } diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index 61d331e0181..5306e76223f 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -362,7 +362,7 @@ static char *get_reset_cause(char *ret) #ifdef CONFIG_ENV_IS_IN_MMC __weak int board_mmc_get_env_dev(int devno) { - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } int mmc_get_env_dev(void) @@ -372,7 +372,7 @@ int mmc_get_env_dev(void) /* If not boot from sd/mmc, use default value */ if (get_boot_mode() == LOW_POWER_BOOT) - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; bt1_cfg = readl(CMC1_RBASE + 0x40); devno = (bt1_cfg >> 9) & 0x7; diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c index 7908f75809c..3eb93c82387 100644 --- a/arch/arm/mach-mvebu/armada8k/cpu.c +++ b/arch/arm/mach-mvebu/armada8k/cpu.c @@ -109,5 +109,5 @@ int mmc_get_env_dev(void) return 1; } - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 75d6693e28a..2e6bb38b923 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -512,8 +512,8 @@ int mmc_get_env_dev(void) const char *boot_device; struct udevice *dev; -#ifdef CONFIG_SYS_MMC_ENV_DEV - devnum = CONFIG_SYS_MMC_ENV_DEV; +#ifdef CONFIG_ENV_MMC_DEVICE_INDEX + devnum = CONFIG_ENV_MMC_DEVICE_INDEX; #else devnum = 0; #endif diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env index 0c9f9c4178a..90861e622ed 100644 --- a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20-a1.env @@ -6,7 +6,7 @@ earlycon=lpuart32,0x5a060000 fdt_addr=0x83000000 boot_fdt=try fdt_file=imx8qm-dmsse20-a1.dtb -mmcdev= __stringify(CONFIG_SYS_MMC_ENV_DEV) +mmcdev= __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) mmcpart= __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.env b/board/freescale/imx8mm_evk/imx8mm_evk.env index 29690e75b15..299b8472c74 100644 --- a/board/freescale/imx8mm_evk/imx8mm_evk.env +++ b/board/freescale/imx8mm_evk/imx8mm_evk.env @@ -14,7 +14,7 @@ ip_dyn=yes kernel_addr_r=0x42000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw prepare_mcore=setenv mcore_clk clk-imx8mm.mcore_booted; diff --git a/board/freescale/imx8mn_evk/imx8mn_evk.env b/board/freescale/imx8mn_evk/imx8mn_evk.env index 16a6543ffc6..487893f9287 100644 --- a/board/freescale/imx8mn_evk/imx8mn_evk.env +++ b/board/freescale/imx8mn_evk/imx8mn_evk.env @@ -14,7 +14,7 @@ ip_dyn=yes kernel_addr_r=0x42000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw prepare_mcore=setenv mcore_clk clk-imx8mn.mcore_booted; diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.env b/board/freescale/imx8mp_evk/imx8mp_evk.env index f70e18fa9d9..18cdf3da056 100644 --- a/board/freescale/imx8mp_evk/imx8mp_evk.env +++ b/board/freescale/imx8mp_evk/imx8mp_evk.env @@ -10,7 +10,7 @@ fdt_addr=0x43000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image ip_dyn=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.env b/board/freescale/imx8mq_evk/imx8mq_evk.env index dcfe1c2f2d4..cab8c6b70bf 100644 --- a/board/freescale/imx8mq_evk/imx8mq_evk.env +++ b/board/freescale/imx8mq_evk/imx8mq_evk.env @@ -12,7 +12,7 @@ ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw prepare_mcore=setenv mcore_clk clk-imx8mq.mcore_booted; diff --git a/board/freescale/imx91_evk/imx91_evk.env b/board/freescale/imx91_evk/imx91_evk.env index c972d3eb251..6c10784cf61 100644 --- a/board/freescale/imx91_evk/imx91_evk.env +++ b/board/freescale/imx91_evk/imx91_evk.env @@ -10,7 +10,7 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx93_evk/imx93_evk.env b/board/freescale/imx93_evk/imx93_evk.env index 8c3aef6b557..d5ed216f54b 100644 --- a/board/freescale/imx93_evk/imx93_evk.env +++ b/board/freescale/imx93_evk/imx93_evk.env @@ -10,7 +10,7 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx93_qsb/imx93_qsb.env b/board/freescale/imx93_qsb/imx93_qsb.env index c972d3eb251..6c10784cf61 100644 --- a/board/freescale/imx93_qsb/imx93_qsb.env +++ b/board/freescale/imx93_qsb/imx93_qsb.env @@ -10,7 +10,7 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=CONFIG_DEFAULT_FDT_FILE image=Image -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes diff --git a/board/freescale/imx95_evk/imx95_19x19_evk.env b/board/freescale/imx95_evk/imx95_19x19_evk.env index a002767e874..a7309d734b0 100644 --- a/board/freescale/imx95_evk/imx95_19x19_evk.env +++ b/board/freescale/imx95_evk/imx95_19x19_evk.env @@ -14,7 +14,7 @@ cntr_file=os_cntr_signed.bin boot_fit=no fdtfile=CONFIG_DEFAULT_FDT_FILE bootm_size=0x10000000 -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcautodetect=yes mmcargs=setenv bootargs console=${console} root=${mmcroot} loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c index c2a44b4aa2d..492d1dc1d8c 100644 --- a/board/grinn/liteboard/board.c +++ b/board/grinn/liteboard/board.c @@ -84,7 +84,7 @@ static int mmc_get_env_devno(void) /* If not boot from sd/mmc, use default value */ if (bootsel != 1) - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; /* BOOT_CFG2[3] and BOOT_CFG2[4] */ dev_no = (soc_sbmr & 0x00001800) >> 11; diff --git a/board/phytec/common/k3/board.c b/board/phytec/common/k3/board.c index d9aec16b090..7f34d71d530 100644 --- a/board/phytec/common/k3/board.c +++ b/board/phytec/common/k3/board.c @@ -94,7 +94,7 @@ int mmc_get_env_dev(void) return 1; }; - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } #endif diff --git a/board/phytec/phycore_imx8mm/phycore_imx8mm.env b/board/phytec/phycore_imx8mm/phycore_imx8mm.env index a7d14e774a0..402d967ab7d 100644 --- a/board/phytec/phycore_imx8mm/phycore_imx8mm.env +++ b/board/phytec/phycore_imx8mm/phycore_imx8mm.env @@ -34,7 +34,7 @@ mmcboot= echo WARN: Cannot load the DT; fi; fi; -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=2 netargs= diff --git a/board/phytec/phycore_imx8mp/phycore_imx8mp.env b/board/phytec/phycore_imx8mp/phycore_imx8mp.env index 2c12fc65432..69690aa92e4 100644 --- a/board/phytec/phycore_imx8mp/phycore_imx8mp.env +++ b/board/phytec/phycore_imx8mp/phycore_imx8mp.env @@ -51,7 +51,7 @@ mmcboot= else echo WARN: Cannot load the DT; fi; -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=2 netargs= diff --git a/board/phytec/phycore_imx93/phycore_imx93.env b/board/phytec/phycore_imx93/phycore_imx93.env index 3b2f30118e7..7b0a90e6447 100644 --- a/board/phytec/phycore_imx93/phycore_imx93.env +++ b/board/phytec/phycore_imx93/phycore_imx93.env @@ -23,7 +23,7 @@ bootenv_addr_r=0x90500000 fdtfile=CONFIG_DEFAULT_FDT_FILE ip_dyn=yes prepare_mcore=setenv optargs "${optargs} clk-imx93.mcore_booted" -mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=2 mmcautodetect=yes diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 15fb9e4b062..ab7af69d472 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -828,7 +828,7 @@ const char *env_ext4_get_dev_part(void) int mmc_get_env_dev(void) { - const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_SYS_MMC_ENV_DEV), (-1)); + const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_ENV_MMC_DEVICE_INDEX), (-1)); if (mmc_env_dev >= 0) return mmc_env_dev; diff --git a/board/st/stm32mp2/stm32mp2.c b/board/st/stm32mp2/stm32mp2.c index 2547f2e4bb7..a72056e12d6 100644 --- a/board/st/stm32mp2/stm32mp2.c +++ b/board/st/stm32mp2/stm32mp2.c @@ -183,7 +183,7 @@ int mmc_get_boot(void) int mmc_get_env_dev(void) { - const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_SYS_MMC_ENV_DEV), (-1)); + const int mmc_env_dev = CONFIG_IS_ENABLED(ENV_IS_IN_MMC, (CONFIG_ENV_MMC_DEVICE_INDEX), (-1)); if (mmc_env_dev >= 0) return mmc_env_dev; diff --git a/board/sunxi/board.c b/board/sunxi/board.c index ac9cefc6eac..feec95658a2 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -516,7 +516,7 @@ int board_mmc_init(struct bd_info *bis) return 0; } -#ifdef CONFIG_SYS_MMC_ENV_DEV +#ifdef CONFIG_ENV_MMC_DEVICE_INDEX int mmc_get_env_dev(void) { switch (sunxi_get_boot_device()) { @@ -525,7 +525,7 @@ int mmc_get_env_dev(void) case BOOT_DEVICE_MMC2: return 1; default: - return CONFIG_SYS_MMC_ENV_DEV; + return CONFIG_ENV_MMC_DEVICE_INDEX; } } #endif diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c index 6b7d9ee061d..2755c26cdf7 100644 --- a/cmd/mvebu/bubt.c +++ b/cmd/mvebu/bubt.c @@ -185,7 +185,7 @@ static int mmc_burn_image(size_t image_size) lbaint_t blk_count; ulong blk_written; int err; - const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV; + const u8 mmc_dev_num = CONFIG_ENV_MMC_DEVICE_INDEX; #ifdef CONFIG_BLK struct blk_desc *blk_desc; #endif @@ -290,7 +290,7 @@ static size_t mmc_read_file(const char *file_name) loff_t act_read = 0; int rc; struct mmc *mmc; - const u8 mmc_dev_num = CONFIG_SYS_MMC_ENV_DEV; + const u8 mmc_dev_num = CONFIG_ENV_MMC_DEVICE_INDEX; mmc = find_mmc_device(mmc_dev_num); if (!mmc) { diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig index 94fe4d7df8d..0e1fef8b722 100644 --- a/configs/am335x_shc_defconfig +++ b/configs/am335x_shc_defconfig @@ -60,7 +60,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig index 02dd6a96623..65d17598a02 100644 --- a/configs/am335x_shc_ict_defconfig +++ b/configs/am335x_shc_ict_defconfig @@ -58,7 +58,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 906f02ee576..4887bf7b181 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -57,7 +57,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index e38929e940c..c3b6eb8c897 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -56,7 +56,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 2f336d3b64f..2bdd0f9c40b 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -81,7 +81,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index 9bbe6bf447c..fdb7b8b5db2 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -75,7 +75,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig index 93366dbc603..94020c8c1a7 100644 --- a/configs/cgtqmx8_defconfig +++ b/configs/cgtqmx8_defconfig @@ -68,7 +68,7 @@ CONFIG_CMD_FAT=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_CLK=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 6e5cfa92ef1..53e7a33af3a 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -65,7 +65,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index e4d5b117996..9b308548951 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -57,7 +57,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index d81e1fc7ad6..f80cfde75ab 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -53,7 +53,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 4f76c0fefdd..e1e59d38294 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -41,7 +41,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/ficus-rk3399_defconfig b/configs/ficus-rk3399_defconfig index d2f999b48e2..1bbc03ffb82 100644 --- a/configs/ficus-rk3399_defconfig +++ b/configs/ficus-rk3399_defconfig @@ -31,7 +31,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_SCSI_AHCI=y CONFIG_AHCI_PCI=y CONFIG_ROCKCHIP_GPIO=y diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index 5169b089687..88ce24c6572 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -24,7 +24,7 @@ CONFIG_MULTI_DTB_FIT_LZO=y CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_ENV_MMC_DEVICE_INDEX=0 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_GPIO_HOG=y CONFIG_DM_PCA953X=y diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index 255bd611d12..87e8d2ac5b3 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_BOUNCE_BUFFER=y CONFIG_DFU_MMC=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index b52341c1a49..5cb7ffd48c5 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -78,7 +78,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index ede02659a8f..be0add6c176 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -81,7 +81,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index bb90dee583a..544fcbf5d68 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -59,7 +59,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index d1540de3b84..c27bdaa15d1 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -59,7 +59,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig index 7a7ee935f03..7c8a2060b1a 100644 --- a/configs/imx8mm-phygate-tauri-l_defconfig +++ b/configs/imx8mm-phygate-tauri-l_defconfig @@ -75,7 +75,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_CLK_COMPOSITE_CCF=y diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index fda40e1269d..52c9f007892 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -75,7 +75,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig index 7d1772c5d09..77db48da38f 100644 --- a/configs/imx8mm_beacon_fspi_defconfig +++ b/configs/imx8mm_beacon_fspi_defconfig @@ -78,7 +78,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 02264e91b4e..0e0f764d2c7 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -61,7 +61,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig index a194eeb7dc5..f364e17bab2 100644 --- a/configs/imx8mm_evk_fspi_defconfig +++ b/configs/imx8mm_evk_fspi_defconfig @@ -63,7 +63,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 979c7b9d7f4..c7e630335f3 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -90,7 +90,7 @@ CONFIG_OF_LIVE=y CONFIG_OF_LIST="freescale/imx8mm-venice-gw71xx-0x freescale/imx8mm-venice-gw72xx-0x freescale/imx8mm-venice-gw73xx-0x freescale/imx8mm-venice-gw7901 freescale/imx8mm-venice-gw7902 freescale/imx8mm-venice-gw7903 freescale/imx8mm-venice-gw7904 freescale/imx8mm-venice-gw75xx-0x" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 0f9bf8586bd..0fd446c6e36 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -83,7 +83,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index bb3ef43fa3f..860d1a9bd27 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -84,7 +84,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig index f340cb1b7c5..4fb7cfded51 100644 --- a/configs/imx8mn_beacon_fspi_defconfig +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -83,7 +83,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 4edcda0dc85..f871bf1653d 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -66,7 +66,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_CLK_IMX8MN=y diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index cfa07c59901..3b41cdddddf 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -61,7 +61,7 @@ CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 2d9b716c862..3cdbcec1eed 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -89,7 +89,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig index 0679d041a6e..0649d746907 100644 --- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig +++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig @@ -67,7 +67,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig index 88cc025bd23..51b547c448f 100644 --- a/configs/imx8mp_beacon_defconfig +++ b/configs/imx8mp_beacon_defconfig @@ -82,7 +82,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx8mp_debix_model_a_defconfig b/configs/imx8mp_debix_model_a_defconfig index 9654a45d1db..2d3aca92e33 100644 --- a/configs/imx8mp_debix_model_a_defconfig +++ b/configs/imx8mp_debix_model_a_defconfig @@ -60,7 +60,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 4ddb4f2683e..d3b51134ee6 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -68,7 +68,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx8mp_navqp_defconfig b/configs/imx8mp_navqp_defconfig index f7ae8c0a5b0..552665d27ca 100644 --- a/configs/imx8mp_navqp_defconfig +++ b/configs/imx8mp_navqp_defconfig @@ -59,7 +59,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig index 000c536c9b7..b7a0b0533ba 100644 --- a/configs/imx8mp_rsb3720a1_4G_defconfig +++ b/configs/imx8mp_rsb3720a1_4G_defconfig @@ -96,7 +96,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig index c7623f23aa7..1e2fad98b7d 100644 --- a/configs/imx8mp_rsb3720a1_6G_defconfig +++ b/configs/imx8mp_rsb3720a1_6G_defconfig @@ -96,7 +96,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index bb43cf7ebfe..526a954aa85 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -92,7 +92,7 @@ CONFIG_OF_LIVE=y CONFIG_OF_LIST="freescale/imx8mp-venice-gw71xx-2x freescale/imx8mp-venice-gw72xx-2x freescale/imx8mp-venice-gw73xx-2x freescale/imx8mp-venice-gw74xx freescale/imx8mp-venice-gw75xx-2x freescale/imx8mp-venice-gw82xx-2x" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y CONFIG_PROT_TCP_SACK=y diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig index ac65565009e..8efbd61f9e3 100644 --- a/configs/imx8mq_cm_defconfig +++ b/configs/imx8mq_cm_defconfig @@ -57,7 +57,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 6be4b95148e..a9262833486 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -68,7 +68,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index ab53f90093e..42c9c8c3de7 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -71,7 +71,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig index 9cd1bb5e4e9..40e7bce9815 100644 --- a/configs/imx8mq_reform2_defconfig +++ b/configs/imx8mq_reform2_defconfig @@ -70,7 +70,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 diff --git a/configs/imx8qm_dmsse20a1_defconfig b/configs/imx8qm_dmsse20a1_defconfig index ddf6f0376a6..e066c2bcb58 100644 --- a/configs/imx8qm_dmsse20a1_defconfig +++ b/configs/imx8qm_dmsse20a1_defconfig @@ -64,7 +64,7 @@ CONFIG_CMD_FAT=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig index b73338299f7..113e0e0284a 100644 --- a/configs/imx8qm_mek_defconfig +++ b/configs/imx8qm_mek_defconfig @@ -74,7 +74,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_CLK=y diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig b/configs/imx8qm_rom7720_a1_4G_defconfig index 588c398dec4..d95d10a6080 100644 --- a/configs/imx8qm_rom7720_a1_4G_defconfig +++ b/configs/imx8qm_rom7720_a1_4G_defconfig @@ -56,7 +56,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig index 18fa27115fe..951d73fefd5 100644 --- a/configs/imx8qxp_mek_defconfig +++ b/configs/imx8qxp_mek_defconfig @@ -75,7 +75,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/imx91_11x11_evk_defconfig b/configs/imx91_11x11_evk_defconfig index 77681e547fd..e5168273197 100644 --- a/configs/imx91_11x11_evk_defconfig +++ b/configs/imx91_11x11_evk_defconfig @@ -81,7 +81,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx91_11x11_evk_inline_ecc_defconfig b/configs/imx91_11x11_evk_inline_ecc_defconfig index 29b0b54dbe8..9b1c5f8b0f1 100644 --- a/configs/imx91_11x11_evk_inline_ecc_defconfig +++ b/configs/imx91_11x11_evk_inline_ecc_defconfig @@ -81,7 +81,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index 1c7a0a4c954..6210be64672 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -87,7 +87,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index c1203508bc7..ba2da308705 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -77,7 +77,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/imx93_9x9_qsb_defconfig b/configs/imx93_9x9_qsb_defconfig index 632e2290cf3..99c349a9295 100644 --- a/configs/imx93_9x9_qsb_defconfig +++ b/configs/imx93_9x9_qsb_defconfig @@ -79,7 +79,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx93_9x9_qsb_inline_ecc_defconfig b/configs/imx93_9x9_qsb_inline_ecc_defconfig index 485452e7135..0966f166ec6 100644 --- a/configs/imx93_9x9_qsb_inline_ecc_defconfig +++ b/configs/imx93_9x9_qsb_inline_ecc_defconfig @@ -79,7 +79,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/imx93_var_som_defconfig b/configs/imx93_var_som_defconfig index 6811a6f58f5..1f7ff269487 100644 --- a/configs/imx93_var_som_defconfig +++ b/configs/imx93_var_som_defconfig @@ -88,7 +88,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/imx95_19x19_evk_defconfig b/configs/imx95_19x19_evk_defconfig index ad2e35b52c6..814570ee2ae 100644 --- a/configs/imx95_19x19_evk_defconfig +++ b/configs/imx95_19x19_evk_defconfig @@ -87,7 +87,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig index ef68e1cf1f5..e763f564ad1 100644 --- a/configs/khadas-vim3_android_ab_defconfig +++ b/configs/khadas-vim3_android_ab_defconfig @@ -57,7 +57,7 @@ CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig index 3ad82c9afff..af34a379e84 100644 --- a/configs/khadas-vim3_android_defconfig +++ b/configs/khadas-vim3_android_defconfig @@ -56,7 +56,7 @@ CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig index 8e439cad3c1..c95cd2831d6 100644 --- a/configs/khadas-vim3l_android_ab_defconfig +++ b/configs/khadas-vim3l_android_ab_defconfig @@ -57,7 +57,7 @@ CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig index 56b4086ee3f..d1141cd8cb9 100644 --- a/configs/khadas-vim3l_android_defconfig +++ b/configs/khadas-vim3l_android_defconfig @@ -56,7 +56,7 @@ CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 88063a37e32..84cef56706b 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -49,7 +49,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y # CONFIG_BLOCK_CACHE is not set diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig index 75b7f95be77..8a1e27287a3 100644 --- a/configs/mvebu_crb_cn9130_defconfig +++ b/configs/mvebu_crb_cn9130_defconfig @@ -43,7 +43,7 @@ CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_AHCI_GENERIC=y diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig index 000e5d3f3eb..81466f75cae 100644 --- a/configs/mvebu_db_cn9130_defconfig +++ b/configs/mvebu_db_cn9130_defconfig @@ -44,7 +44,7 @@ CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_AHCI_GENERIC=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index c29f38fa49e..e8109fbe6c0 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -69,7 +69,7 @@ CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index 0dc2e2595f1..d28880797dc 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 15709a1fcc7..0e35e5e6af5 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -57,7 +57,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 127a64f6af9..e1482081493 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -55,7 +55,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 17f46e06627..0422edeb53d 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -38,7 +38,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index 2a9f85c1313..36d1f96f25d 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -39,7 +39,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index a01bff6d8a8..9db0251a8a0 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -34,7 +34,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NO_NET=y CONFIG_BOUNCE_BUFFER=y diff --git a/configs/nanopi-r2c-plus-rk3328_defconfig b/configs/nanopi-r2c-plus-rk3328_defconfig index 16d22a0837e..5c6be8b85a7 100644 --- a/configs/nanopi-r2c-plus-rk3328_defconfig +++ b/configs/nanopi-r2c-plus-rk3328_defconfig @@ -43,7 +43,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/nanopi-r2c-rk3328_defconfig b/configs/nanopi-r2c-rk3328_defconfig index 4195979f8ea..fa2b348f2e5 100644 --- a/configs/nanopi-r2c-rk3328_defconfig +++ b/configs/nanopi-r2c-rk3328_defconfig @@ -43,7 +43,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig index a0530117e7d..bedcda2622c 100644 --- a/configs/nanopi-r2s-rk3328_defconfig +++ b/configs/nanopi-r2s-rk3328_defconfig @@ -43,7 +43,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/orangepi-r1-plus-lts-rk3328_defconfig b/configs/orangepi-r1-plus-lts-rk3328_defconfig index 7d562be867f..7e40d9d91f8 100644 --- a/configs/orangepi-r1-plus-lts-rk3328_defconfig +++ b/configs/orangepi-r1-plus-lts-rk3328_defconfig @@ -48,7 +48,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/orangepi-r1-plus-rk3328_defconfig b/configs/orangepi-r1-plus-rk3328_defconfig index c27b718bd63..36977865ad4 100644 --- a/configs/orangepi-r1-plus-rk3328_defconfig +++ b/configs/orangepi-r1-plus-rk3328_defconfig @@ -48,7 +48,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 6509471614a..96eacec1d23 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -81,7 +81,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_SPL_DM=y CONFIG_SPL_CLK_COMPOSITE_CCF=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 24afa93b4bb..cb38898a245 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -94,7 +94,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index bedcb960e3a..ee9cc2bd822 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -52,7 +52,7 @@ CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/phycore_am62ax_a53_defconfig b/configs/phycore_am62ax_a53_defconfig index dd55893bddd..35d693a17ed 100644 --- a/configs/phycore_am62ax_a53_defconfig +++ b/configs/phycore_am62ax_a53_defconfig @@ -90,7 +90,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_REDUNDANT=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index 6a811ca4e7e..5e89076774e 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -93,7 +93,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_REDUNDANT=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/phycore_am64x_a53_defconfig b/configs/phycore_am64x_a53_defconfig index 11482223247..a8bf7d7339b 100644 --- a/configs/phycore_am64x_a53_defconfig +++ b/configs/phycore_am64x_a53_defconfig @@ -93,7 +93,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_REDUNDANT=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig index 0e14944eed7..63feb839c17 100644 --- a/configs/pico-imx8mq_defconfig +++ b/configs/pico-imx8mq_defconfig @@ -71,7 +71,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 4e12900d279..90d8313723e 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -56,7 +56,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BUTTON=y CONFIG_BUTTON_GPIO=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index b3f6498d528..2ed3eb546c9 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -45,7 +45,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ARP_TIMEOUT=200 CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y diff --git a/configs/roc-cc-rk3328_defconfig b/configs/roc-cc-rk3328_defconfig index 812dd9f3ccc..fc79cfb6e15 100644 --- a/configs/roc-cc-rk3328_defconfig +++ b/configs/roc-cc-rk3328_defconfig @@ -41,7 +41,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/rock-pi-e-rk3328_defconfig b/configs/rock-pi-e-rk3328_defconfig index 67edcb35dc5..4b84223be33 100644 --- a/configs/rock-pi-e-rk3328_defconfig +++ b/configs/rock-pi-e-rk3328_defconfig @@ -39,7 +39,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/rock-pi-e-v3-rk3328_defconfig b/configs/rock-pi-e-v3-rk3328_defconfig index 053a964c667..39bbed8fdbe 100644 --- a/configs/rock-pi-e-v3-rk3328_defconfig +++ b/configs/rock-pi-e-v3-rk3328_defconfig @@ -40,7 +40,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig index d7cedbfc925..12cdf2e9e21 100644 --- a/configs/rock64-rk3328_defconfig +++ b/configs/rock64-rk3328_defconfig @@ -46,7 +46,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigne CONFIG_TPL_OF_PLATDATA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_TPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig index 298f4ee0df0..db121f03ae6 100644 --- a/configs/rock960-rk3399_defconfig +++ b/configs/rock960-rk3399_defconfig @@ -36,7 +36,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 # CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y diff --git a/configs/s5p4418_nanopi2_defconfig b/configs/s5p4418_nanopi2_defconfig index 548963c933f..0b265f104e4 100644 --- a/configs/s5p4418_nanopi2_defconfig +++ b/configs/s5p4418_nanopi2_defconfig @@ -48,7 +48,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_NO_NET=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_NEXELL=y diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig index b9bedcc4baf..65f7e8c212c 100644 --- a/configs/sei510_defconfig +++ b/configs/sei510_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=1 CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig index 770a487398f..90f7a6fbf27 100644 --- a/configs/sei610_defconfig +++ b/configs/sei610_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_AVB=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=1 CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/smegw01_defconfig b/configs/smegw01_defconfig index b3acec921df..529836e7bdd 100644 --- a/configs/smegw01_defconfig +++ b/configs/smegw01_defconfig @@ -51,7 +51,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_USE_BOOTFILE=y diff --git a/configs/somlabs_visionsom_6ull_defconfig b/configs/somlabs_visionsom_6ull_defconfig index d487a2e728e..852d7b984ba 100644 --- a/configs/somlabs_visionsom_6ull_defconfig +++ b/configs/somlabs_visionsom_6ull_defconfig @@ -39,7 +39,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index 2eab305cc5d..6ca6bd1261c 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -52,7 +52,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_ENV_MMC_DEVICE_INDEX=-1 CONFIG_ENV_MMC_USE_DT=y CONFIG_SYS_64BIT_LBA=y CONFIG_BUTTON=y diff --git a/configs/stm32mp13_dhcor_defconfig b/configs/stm32mp13_dhcor_defconfig index 2da9287ea7b..2357692c4c4 100644 --- a/configs/stm32mp13_dhcor_defconfig +++ b/configs/stm32mp13_dhcor_defconfig @@ -34,7 +34,7 @@ CONFIG_ENV_SPI_MAX_HZ=50000000 CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 -CONFIG_SYS_MMC_ENV_DEV=0 +CONFIG_ENV_MMC_DEVICE_INDEX=0 CONFIG_SYS_MMC_ENV_PART=1 CONFIG_PHY_REALTEK=y CONFIG_DM_REGULATOR_SCMI=y diff --git a/configs/stm32mp15-odyssey_defconfig b/configs/stm32mp15-odyssey_defconfig index 636a777f106..a317a6cae11 100644 --- a/configs/stm32mp15-odyssey_defconfig +++ b/configs/stm32mp15-odyssey_defconfig @@ -64,7 +64,7 @@ CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_ENV_MMC_DEVICE_INDEX=-1 CONFIG_ENV_MMC_USE_DT=y CONFIG_TFTP_TSIZE=y CONFIG_USE_SERVERIP=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 856311e076d..4c8ad87e72b 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -93,7 +93,7 @@ CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_ENV_MMC_DEVICE_INDEX=-1 CONFIG_ENV_MMC_USE_DT=y # CONFIG_SPL_ENV_IS_NOWHERE is not set # CONFIG_SPL_ENV_IS_IN_SPI_FLASH is not set diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index c99c5af3cd7..b3ec3898861 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -65,7 +65,7 @@ CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_ENV_MMC_DEVICE_INDEX=-1 CONFIG_ENV_MMC_USE_DT=y CONFIG_TFTP_TSIZE=y CONFIG_USE_SERVERIP=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 6788e932224..09383ed4824 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -66,7 +66,7 @@ CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_ENV_MMC_DEVICE_INDEX=-1 CONFIG_ENV_MMC_USE_DT=y CONFIG_TFTP_TSIZE=y CONFIG_USE_SERVERIP=y diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig index f87812fa080..ade9daf7474 100644 --- a/configs/stm32mp25_defconfig +++ b/configs/stm32mp25_defconfig @@ -47,7 +47,7 @@ CONFIG_ENV_REDUNDANT=y CONFIG_ENV_UBI_PART="UBI" CONFIG_ENV_UBI_VOLUME="uboot_config" CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r" -CONFIG_SYS_MMC_ENV_DEV=-1 +CONFIG_ENV_MMC_DEVICE_INDEX=-1 CONFIG_NO_NET=y CONFIG_SYS_64BIT_LBA=y CONFIG_BUTTON=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index 57d452f960c..efc3f195c1b 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -68,7 +68,7 @@ CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-ex CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=1 CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 77c9567a27a..afbb394228f 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -46,7 +46,7 @@ CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 1388212f18a..876086573d3 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -46,7 +46,7 @@ CONFIG_OF_UPSTREAM=y CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index cb9ae022c99..db0d9e2c789 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -39,7 +39,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 517313be9a5..d4fb271e03a 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_BOUNCE_BUFFER=y CONFIG_DM_I2C=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index abb64e8cd04..c2f78a9e90f 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -96,7 +96,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=2 +CONFIG_ENV_MMC_DEVICE_INDEX=2 CONFIG_SYS_MMC_ENV_PART=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index 00935608bbb..c9de6f8ad26 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -56,7 +56,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y diff --git a/configs/x250_defconfig b/configs/x250_defconfig index 628ce40fc91..35bef079fd1 100644 --- a/configs/x250_defconfig +++ b/configs/x250_defconfig @@ -46,7 +46,7 @@ CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_ENV_MMC_DEVICE_INDEX=1 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_IPV6=y diff --git a/doc/device-tree-bindings/config.txt b/doc/device-tree-bindings/config.txt index f50c68bbdc3..a617e7f84f8 100644 --- a/doc/device-tree-bindings/config.txt +++ b/doc/device-tree-bindings/config.txt @@ -70,7 +70,7 @@ u-boot,mmc-env-offset-redundant (int) u-boot,mmc-env-partition (int) if present, the environment shall be placed at the last CONFIG_ENV_SIZE blocks of the partition on the - CONFIG_SYS_MMC_ENV_DEV. + CONFIG_ENV_MMC_DEVICE_INDEX. if u-boot,mmc-env-offset* is present, this setting will take precedence. In that case, only if the partition is not found, diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 9421a846e45..2c1f4f9c336 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -3278,8 +3278,8 @@ int mmc_set_bkops_enable(struct mmc *mmc, bool autobkops, bool enable) __weak int mmc_get_env_dev(void) { -#ifdef CONFIG_SYS_MMC_ENV_DEV - return CONFIG_SYS_MMC_ENV_DEV; +#ifdef CONFIG_ENV_MMC_DEVICE_INDEX + return CONFIG_ENV_MMC_DEVICE_INDEX; #else return 0; #endif diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index a8caa0f0927..146f3f1fbd3 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -410,12 +410,12 @@ int fm_init_common(int index, struct ccsr_fman *reg, const char *firmware_name) spi_flash_free(ucode_flash); } } else if (src == BOOT_SOURCE_SD_MMC) { - int dev = CONFIG_SYS_MMC_ENV_DEV; + int dev = CONFIG_ENV_MMC_DEVICE_INDEX; addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512; - struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + struct mmc *mmc = find_mmc_device(CONFIG_ENV_MMC_DEVICE_INDEX); if (!mmc) { printf("\nMMC cannot find device for ucode\n"); @@ -514,11 +514,11 @@ int fm_init_common(int index, struct ccsr_fman *reg, const char *firmware_name) spi_flash_free(ucode_flash); } #elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC) - int dev = CONFIG_SYS_MMC_ENV_DEV; + int dev = CONFIG_ENV_MMC_DEVICE_INDEX; void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512; - struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + struct mmc *mmc = find_mmc_device(CONFIG_ENV_MMC_DEVICE_INDEX); if (!mmc) printf("\nMMC cannot find device for ucode\n"); diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index d043e859bad..be480ecef6c 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -170,10 +170,10 @@ void cs4340_upload_firmware(struct phy_device *phydev) spi_flash_free(ucode_flash); } } else if (src == BOOT_SOURCE_SD_MMC) { - int dev = CONFIG_SYS_MMC_ENV_DEV; + int dev = CONFIG_ENV_MMC_DEVICE_INDEX; u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512; u32 blk = cortina_fw_addr / 512; - struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + struct mmc *mmc = find_mmc_device(CONFIG_ENV_MMC_DEVICE_INDEX); if (!mmc) { puts("Failed to find MMC device for Cortina ucode\n"); @@ -223,10 +223,10 @@ void cs4340_upload_firmware(struct phy_device *phydev) spi_flash_free(ucode_flash); } #elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC) - int dev = CONFIG_SYS_MMC_ENV_DEV; + int dev = CONFIG_ENV_MMC_DEVICE_INDEX; u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512; u32 blk = cortina_fw_addr / 512; - struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + struct mmc *mmc = find_mmc_device(CONFIG_ENV_MMC_DEVICE_INDEX); if (!mmc) { puts("Failed to find MMC device for Cortina ucode\n"); diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 9631337b8d9..69b7de084e5 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -243,7 +243,7 @@ void u_qe_init(void) CFG_SYS_FSL_QSPI_BASE); if (src == BOOT_SOURCE_SD_MMC) { - int dev = CONFIG_SYS_MMC_ENV_DEV; + int dev = CONFIG_ENV_MMC_DEVICE_INDEX; u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; u32 blk = CONFIG_SYS_QE_FW_ADDR / 512; @@ -252,7 +252,7 @@ void u_qe_init(void) return; } addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); - struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + struct mmc *mmc = find_mmc_device(CONFIG_ENV_MMC_DEVICE_INDEX); if (!mmc) { free(addr); @@ -277,7 +277,7 @@ void u_qe_init(void) void *addr = (void *)CONFIG_SYS_QE_FW_ADDR; #ifdef CONFIG_SYS_QE_FMAN_FW_IN_MMC - int dev = CONFIG_SYS_MMC_ENV_DEV; + int dev = CONFIG_ENV_MMC_DEVICE_INDEX; u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512; u32 blk = CONFIG_SYS_QE_FW_ADDR / 512; @@ -286,7 +286,7 @@ void u_qe_init(void) return; } addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); - struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV); + struct mmc *mmc = find_mmc_device(CONFIG_ENV_MMC_DEVICE_INDEX); if (!mmc) { printf("\nMMC cannot find device for ucode\n"); diff --git a/env/Kconfig b/env/Kconfig index e551ffe45c3..1decdd89648 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -215,7 +215,7 @@ config ENV_IS_IN_MMC Define this if you have an MMC device which you want to use for the environment. - CONFIG_SYS_MMC_ENV_DEV: + CONFIG_ENV_MMC_DEVICE_INDEX: Specifies which MMC device the environment is stored in. @@ -698,13 +698,15 @@ config ENV_MTD_DEV help MTD device name on the platform where the environment is stored. -config SYS_MMC_ENV_DEV - int "mmc device number" +config ENV_MMC_DEVICE_INDEX + int "SD/MMC device index" depends on ENV_IS_IN_MMC || ENV_IS_IN_FAT || ENV_IS_IN_EXT4 || \ CMD_MVEBU_BUBT || FMAN_ENET || QE || PHY_CORTINA default 0 help - MMC device number on the platform where the environment is stored. + SD/MMC device index on the platform where the environment is stored. + The index is often derived from DT aliases mmcN node ordering, and + matches the 'mmc list' command output. config SYS_MMC_ENV_PART int "mmc partition number" diff --git a/env/mmc.c b/env/mmc.c index 5451f914027..dba99bd4d3d 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -164,7 +164,7 @@ static inline s64 mmc_offset(struct mmc *mmc, int copy) #if defined(CONFIG_ENV_MMC_PARTITION) str = CONFIG_ENV_MMC_PARTITION; #else - /* look for the partition in mmc CONFIG_SYS_MMC_ENV_DEV */ + /* look for the partition in mmc CONFIG_ENV_MMC_DEVICE_INDEX */ str = ofnode_conf_read_str(dt_prop.partition); #endif diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 0d338389cb9..c27b504a95d 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -64,7 +64,7 @@ "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "fdt_file=imx8qm-cgt-qmx8.dtb\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcdev=" __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) "\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index 36c4c5b8b50..d305c566239 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -28,7 +28,7 @@ "console=ttymxc0\0" \ "fdt_file=imx7-cm.dtb\0" \ "fdt_addr=0x83000000\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 6ed4a6fd3fc..d5cdfaeed8b 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -76,7 +76,7 @@ "fdtfile=sb-iotgimx8.dtb\0" \ "initrd_addr=0x43800000\0" \ "bootm_size=0x10000000\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcdev=" __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) "\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 8b96f7fd1e4..b0833171404 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -77,7 +77,7 @@ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "initrd_addr=0x43800000\0" \ "bootm_size=0x10000000\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcdev=" __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) "\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 3bc4b0034e8..a30d0da5050 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -39,7 +39,7 @@ "fdt_file=imx8mq-phanbell.dtb\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 842184bcae2..24e7aa96ec1 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -34,7 +34,7 @@ "fdt_file=undefined\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index df2cb8d9ced..cc94778bb65 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -58,7 +58,7 @@ "boot_fdt=try\0" \ "fdt_file=imx8qm-rom7720-a1.dtb\0" \ "initrd_addr=0x83800000\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk2p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index 1b6eb2b81cf..abc3603bacf 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -34,7 +34,7 @@ "fdt_file=undefined\0" \ "initrd_addr=0x83800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index eb40a69d20c..94355cf61e4 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -17,8 +17,8 @@ #define CFG_MALLOC_F_ADDR 0x204D0000 #endif -#ifdef CONFIG_SYS_MMC_ENV_DEV -#define IMX93_EVK_MMC_ENV_DEV CONFIG_SYS_MMC_ENV_DEV +#ifdef CONFIG_ENV_MMC_DEVICE_INDEX +#define IMX93_EVK_MMC_ENV_DEV CONFIG_ENV_MMC_DEVICE_INDEX #else #define IMX93_EVK_MMC_ENV_DEV 0 #endif diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index fc6bc6b28ba..2934c76a662 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -30,7 +30,7 @@ "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index 068b9e4d25f..711e2303c9c 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -33,7 +33,7 @@ "ip_dyn=yes\0" \ "console=ttymxc0\0" \ "bootm_size=0x10000000\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcdev=" __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) "\0" \ "finduuid=part uuid mmc 1:1 uuid\0" \ "update_sd_firmware=" \ "if test ${ip_dyn} = yes; then " \ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 9c61350a33b..c8e5757d0bb 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -50,7 +50,7 @@ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcdev=" __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) "\0" \ "mmcpart=1\0" \ "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ "update_sd_firmware=" \ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 0ba4054bbe4..1ffad5931c4 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -23,7 +23,7 @@ "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 3716dc75b96..203a037e342 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -42,7 +42,7 @@ "ip_dyn=yes\0" \ "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 910140ab4b7..353267dddec 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -34,7 +34,7 @@ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ diff --git a/include/configs/mx7ulp_com.h b/include/configs/mx7ulp_com.h index f8e3950fa32..139536547de 100644 --- a/include/configs/mx7ulp_com.h +++ b/include/configs/mx7ulp_com.h @@ -35,7 +35,7 @@ "initrd_high=0xffffffff\0" \ "fdt_file=imx7ulp-com.dtb\0" \ "fdt_addr=0x63000000\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index d1c1202d061..654537684ba 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -38,7 +38,7 @@ "boot_fdt=try\0" \ "earlycon=lpuart32,0x402D0010\0" \ "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index 500dd8c069a..f6a7ccfe87c 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -42,7 +42,7 @@ "initrd_high=0xffffffff\0" \ "fdt_addr_r=0x18000000\0" \ "fdt_addr=0x18000000\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcdev=" __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) "\0" \ CFG_DFU_ENV_SETTINGS \ "finduuid=part uuid mmc 0:1 uuid\0" \ "findfdt="\ diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 3012f64c0ae..f80773f2bc1 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -33,7 +33,7 @@ "fdt_file=imx8mq-pico-pi.dtb\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcdev=" __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) "\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index fd4d170456a..329fe3c86ed 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -54,7 +54,7 @@ "fdt_size="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ "kernel_size="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ "loadimage=mmc dev ${mmcdev}; " \ "mmc read ${loadaddr} ${kernel_start} ${kernel_size};\0" \ "loadfdt=mmc dev ${mmcdev}; " \ diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index d10b88f1575..072fdce7e90 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -52,7 +52,7 @@ "fdt_file=vf610-twr.dtb\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcdev=" __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) "\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "update_sd_firmware_filename=u-boot.imx\0" \ diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index b5b342b3538..7f764b90098 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -26,7 +26,7 @@ "fdt_addr_r=0x18000000\0" \ "fdt_addr=0x18000000\0" \ "ip_dyn=yes\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcdev=" __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) "\0" \ "finduuid=part uuid mmc 0:1 uuid\0" \ "update_sd_firmware_filename=u-boot.imx\0" \ "update_sd_firmware=" \ diff --git a/include/configs/warp7.h b/include/configs/warp7.h index a5278d1cb9b..c79c4e5bafe 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -42,7 +42,7 @@ "fdtovaddr=0x83100000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ "mmcpart=1\0" \ "rootpart=" __stringify(CONFIG_WARP7_ROOT_PART) "\0" \ "finduuid=part uuid mmc 0:${rootpart} uuid\0" \ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 8efebf77c3d..aa4dd3e9b8d 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -40,7 +40,7 @@ "fdt_addr=0x83000000\0" \ "boot_fdt=try\0" \ "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ + "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ "mmcpart=1\0" \ "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ "mmcautodetect=yes\0" \ -- cgit v1.3.1 From 31617b880ab7da6aade0cf3c07f0d02b42bb8f4c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 9 Jun 2025 21:26:40 +0200 Subject: env: Rename SYS_MMC_ENV_PART to ENV_MMC_EMMC_HW_PARTITION Rename the variable and add ENV_ prefix, so that all configuration options which are related to environment would have an CONFIG_ENV_ prefix. No functional change. Use ENV_MMC_EMMC_HW_PARTITION to clarify this is the eMMC hardware partition selector, not a software partition table entry selector. Retain the ENV_MMC_ prefix to make it easier to search for all the SD/MMC related ENV options. Update the help text accordingly. Signed-off-by: Marek Vasut --- arch/arm/mach-imx/mx6/soc.c | 6 +++--- configs/am335x_sl50_defconfig | 2 +- configs/am65x_evm_a53_defconfig | 2 +- configs/apalis-imx8_defconfig | 2 +- configs/apalis-tk1_defconfig | 2 +- configs/apalis_imx6_defconfig | 2 +- configs/apalis_t30_defconfig | 2 +- configs/beaver_defconfig | 2 +- configs/brppt1_mmc_defconfig | 2 +- configs/brxre1_defconfig | 2 +- configs/cardhu_defconfig | 2 +- configs/cei-tk1-som_defconfig | 2 +- configs/colibri-imx6ull-emmc_defconfig | 2 +- configs/colibri-imx8x_defconfig | 2 +- configs/colibri_imx6_defconfig | 2 +- configs/colibri_imx7_emmc_defconfig | 2 +- configs/colibri_t30_defconfig | 2 +- configs/dalmore_defconfig | 2 +- configs/dragonboard410c_defconfig | 2 +- configs/e850-96_defconfig | 2 +- configs/endeavoru_defconfig | 2 +- configs/grouper_defconfig | 2 +- configs/gwventana_emmc_defconfig | 2 +- configs/hihope_rzg2_defconfig | 2 +- configs/hikey_defconfig | 2 +- configs/hmibsc_defconfig | 2 +- configs/ideapad-yoga-11_defconfig | 2 +- configs/imx6q_bosch_acc_defconfig | 2 +- configs/imx8m_data_modul.config | 2 +- configs/imx8mm-mx8menlo_defconfig | 2 +- configs/imx8mm_beacon_defconfig | 2 +- configs/imx8mm_beacon_fspi_defconfig | 2 +- configs/imx8mn_beacon_2g_defconfig | 2 +- configs/imx8mn_beacon_defconfig | 2 +- configs/imx8mn_beacon_fspi_defconfig | 2 +- configs/imx8mn_var_som_defconfig | 2 +- configs/imx8mp_beacon_defconfig | 2 +- configs/imx8qxp_capricorn.config | 2 +- configs/j722s_evm_r5_defconfig | 2 +- configs/jetson-tk1_defconfig | 2 +- configs/khadas-vim3_android_ab_defconfig | 2 +- configs/khadas-vim3_android_defconfig | 2 +- configs/khadas-vim3l_android_ab_defconfig | 2 +- configs/khadas-vim3l_android_defconfig | 2 +- configs/mocha_defconfig | 2 +- configs/mot_defconfig | 2 +- configs/mt8183_pumpkin_defconfig | 2 +- configs/nyan-big_defconfig | 2 +- configs/opos6uldev_defconfig | 2 +- configs/ouya_defconfig | 2 +- configs/p2371-0000_defconfig | 2 +- configs/p2371-2180_defconfig | 2 +- configs/p2571_defconfig | 2 +- configs/p2771-0000-000_defconfig | 2 +- configs/p2771-0000-500_defconfig | 2 +- configs/paz00_defconfig | 2 +- configs/phycore_am62ax_r5_defconfig | 2 +- configs/picasso_defconfig | 2 +- configs/qc750_defconfig | 2 +- configs/r8a77990_ebisu_defconfig | 2 +- configs/r8a77995_draak_defconfig | 2 +- configs/r8a779g0_whitehawk_defconfig | 2 +- configs/r8a779h0_grayhawk_defconfig | 2 +- configs/rcar3_salvator-x_defconfig | 2 +- configs/rcar3_ulcb_defconfig | 2 +- configs/renesas_rzg2l_smarc_defconfig | 2 +- configs/rzg2_beacon_defconfig | 2 +- configs/seaboard_defconfig | 2 +- configs/sei510_defconfig | 2 +- configs/sei610_defconfig | 2 +- configs/star_defconfig | 2 +- configs/stm32mp13_dhcor_defconfig | 2 +- configs/surface-rt_defconfig | 2 +- configs/tbs2910_defconfig | 2 +- configs/tec-ng_defconfig | 2 +- configs/tegratab_defconfig | 2 +- configs/tf701t_defconfig | 2 +- configs/toradex-smarc-imx8mp_defconfig | 2 +- configs/transformer_t20_defconfig | 2 +- configs/transformer_t30_defconfig | 2 +- configs/turris_mox_defconfig | 2 +- configs/venice2_defconfig | 2 +- configs/ventana_defconfig | 2 +- configs/verdin-am62_a53_defconfig | 2 +- configs/verdin-am62p_a53_defconfig | 2 +- configs/verdin-imx8mm_defconfig | 2 +- configs/verdin-imx8mp_defconfig | 2 +- configs/vining_2000_defconfig | 2 +- configs/x3_t30_defconfig | 2 +- env/Kconfig | 8 ++++---- env/mmc.c | 8 ++++---- include/mmc.h | 2 +- 92 files changed, 100 insertions(+), 100 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c index 90fe9e7c19b..50521490b35 100644 --- a/arch/arm/mach-imx/mx6/soc.c +++ b/arch/arm/mach-imx/mx6/soc.c @@ -540,10 +540,10 @@ int mmc_get_env_dev(void) return board_mmc_get_env_dev(devno); } -#ifdef CONFIG_SYS_MMC_ENV_PART +#ifdef CONFIG_ENV_MMC_EMMC_HW_PARTITION __weak int board_mmc_get_env_part(int devno) { - return CONFIG_SYS_MMC_ENV_PART; + return CONFIG_ENV_MMC_EMMC_HW_PARTITION; } uint mmc_get_env_part(struct mmc *mmc) @@ -552,7 +552,7 @@ uint mmc_get_env_part(struct mmc *mmc) /* If not boot from sd/mmc, use default value */ if (devno < 0) - return CONFIG_SYS_MMC_ENV_PART; + return CONFIG_ENV_MMC_EMMC_HW_PARTITION; return board_mmc_get_env_part(devno); } diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 4887bf7b181..32c8e9bd39f 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -58,7 +58,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=1 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index fdee4d0bf07..86fa5d30373 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -74,7 +74,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig index 3872e8cd9b0..dfd586b1c14 100644 --- a/configs/apalis-imx8_defconfig +++ b/configs/apalis-imx8_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 539060c5282..de30fa1b961 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index fd08432e57a..7d54205938e 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -70,7 +70,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index 9937344cb6f..e9c9cfe940e 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig index 56f0362e201..caf2ae196f8 100644 --- a/configs/beaver_defconfig +++ b/configs/beaver_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig index 2bdd0f9c40b..58da63d11dd 100644 --- a/configs/brppt1_mmc_defconfig +++ b/configs/brppt1_mmc_defconfig @@ -82,7 +82,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=1 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig index fdb7b8b5db2..2af491b065d 100644 --- a/configs/brxre1_defconfig +++ b/configs/brxre1_defconfig @@ -76,7 +76,7 @@ CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=1 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig index ad220c19788..318fbaa529b 100644 --- a/configs/cardhu_defconfig +++ b/configs/cardhu_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_SYS_I2C_TEGRA=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_RTL8169=y diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index f9965bba23e..01c3117e364 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/colibri-imx6ull-emmc_defconfig b/configs/colibri-imx6ull-emmc_defconfig index 20469aa1973..f1c6373c31e 100644 --- a/configs/colibri-imx6ull-emmc_defconfig +++ b/configs/colibri-imx6ull-emmc_defconfig @@ -48,7 +48,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig index cf027bc1c75..431987d3f90 100644 --- a/configs/colibri-imx8x_defconfig +++ b/configs/colibri-imx8x_defconfig @@ -51,7 +51,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 7ce17b0bad9..1aea1d40c4e 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -69,7 +69,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_IP_DEFRAG=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index fa53b29eaac..e23cc993542 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -48,7 +48,7 @@ CONFIG_CMD_CACHE=y CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_IP_DEFRAG=y CONFIG_USE_IPADDR=y diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index 23ce3d9bbfd..8d7a6bf7060 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -44,7 +44,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_IP_DEFRAG=y CONFIG_TFTP_TSIZE=y CONFIG_NET_RANDOM_ETHADDR=y diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index 0aed9ebad58..c44980e9227 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -42,7 +42,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 20b2794b618..c01d22abe2b 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -36,7 +36,7 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_SYSBOOT=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_QCOM_APQ8016=y diff --git a/configs/e850-96_defconfig b/configs/e850-96_defconfig index 34bfc75ea31..e07e4cffd0a 100644 --- a/configs/e850-96_defconfig +++ b/configs/e850-96_defconfig @@ -35,7 +35,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_NO_NET=y CONFIG_CLK_EXYNOS850=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/endeavoru_defconfig b/configs/endeavoru_defconfig index 7aac11192fc..804b00697a1 100644 --- a/configs/endeavoru_defconfig +++ b/configs/endeavoru_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/grouper_defconfig b/configs/grouper_defconfig index 76ec9a39a7c..b9068e18b03 100644 --- a/configs/grouper_defconfig +++ b/configs/grouper_defconfig @@ -55,7 +55,7 @@ CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index 9aabd6be88a..807e48f50e4 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -93,7 +93,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NETCONSOLE=y CONFIG_USE_IPADDR=y diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index 88ce24c6572..f5bb28cb0c7 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -25,7 +25,7 @@ CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=0 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_GPIO_HOG=y CONFIG_DM_PCA953X=y CONFIG_SYS_I2C_RCAR_I2C=y diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig index c63e66cf383..59c2101110e 100644 --- a/configs/hikey_defconfig +++ b/configs/hikey_defconfig @@ -29,7 +29,7 @@ CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_CACHE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_HIKEY_GPIO=y CONFIG_MMC_DW=y CONFIG_MMC_DW_K3=y diff --git a/configs/hmibsc_defconfig b/configs/hmibsc_defconfig index 6832ed46077..b45245729a7 100644 --- a/configs/hmibsc_defconfig +++ b/configs/hmibsc_defconfig @@ -43,7 +43,7 @@ CONFIG_CMD_FS_GENERIC=y # CONFIG_OF_UPSTREAM is not set CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_BUTTON_QCOM_PMIC=y diff --git a/configs/ideapad-yoga-11_defconfig b/configs/ideapad-yoga-11_defconfig index 350dbcc4dcd..d5befae419d 100644 --- a/configs/ideapad-yoga-11_defconfig +++ b/configs/ideapad-yoga-11_defconfig @@ -51,7 +51,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig index b6cbd9fbb66..6f0ef2eaee3 100644 --- a/configs/imx6q_bosch_acc_defconfig +++ b/configs/imx6q_bosch_acc_defconfig @@ -77,7 +77,7 @@ CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_VERSION_VARIABLE=y diff --git a/configs/imx8m_data_modul.config b/configs/imx8m_data_modul.config index 0c9f85b7671..07390037c46 100644 --- a/configs/imx8m_data_modul.config +++ b/configs/imx8m_data_modul.config @@ -198,7 +198,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_MALLOC_LEN=0x1000000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SYS_PBSIZE=2081 CONFIG_SYS_PROMPT="u-boot=> " diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index d7be3f0c679..eb8e90a1251 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -93,7 +93,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 52c9f007892..06cc4bb7dde 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -76,7 +76,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig index 77db48da38f..5e60c9d3a08 100644 --- a/configs/imx8mm_beacon_fspi_defconfig +++ b/configs/imx8mm_beacon_fspi_defconfig @@ -79,7 +79,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 0fd446c6e36..b71cdbb2e4e 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -84,7 +84,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index 860d1a9bd27..bb483653db2 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -85,7 +85,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig index 4fb7cfded51..f163871bfaa 100644 --- a/configs/imx8mn_beacon_fspi_defconfig +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -84,7 +84,7 @@ CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index 3b41cdddddf..26b2a3be64d 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -62,7 +62,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig index 51b547c448f..1c2f7a8501a 100644 --- a/configs/imx8mp_beacon_defconfig +++ b/configs/imx8mp_beacon_defconfig @@ -83,7 +83,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth1" CONFIG_SPL_DM=y diff --git a/configs/imx8qxp_capricorn.config b/configs/imx8qxp_capricorn.config index 7b034d5ff1e..62babf2626f 100644 --- a/configs/imx8qxp_capricorn.config +++ b/configs/imx8qxp_capricorn.config @@ -11,7 +11,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_REDUNDANT=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DM_GPIO=y CONFIG_AHAB_BOOT=y diff --git a/configs/j722s_evm_r5_defconfig b/configs/j722s_evm_r5_defconfig index ab0d4ebb825..f4562bd0d68 100644 --- a/configs/j722s_evm_r5_defconfig +++ b/configs/j722s_evm_r5_defconfig @@ -69,7 +69,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_NO_NET=y CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index 9594c30dec6..13d43c02b9f 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -46,7 +46,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/khadas-vim3_android_ab_defconfig b/configs/khadas-vim3_android_ab_defconfig index e763f564ad1..765a154c150 100644 --- a/configs/khadas-vim3_android_ab_defconfig +++ b/configs/khadas-vim3_android_ab_defconfig @@ -58,7 +58,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/khadas-vim3_android_defconfig b/configs/khadas-vim3_android_defconfig index af34a379e84..d105c2b40b0 100644 --- a/configs/khadas-vim3_android_defconfig +++ b/configs/khadas-vim3_android_defconfig @@ -57,7 +57,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/khadas-vim3l_android_ab_defconfig b/configs/khadas-vim3l_android_ab_defconfig index c95cd2831d6..0625c101085 100644 --- a/configs/khadas-vim3l_android_ab_defconfig +++ b/configs/khadas-vim3l_android_ab_defconfig @@ -58,7 +58,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/khadas-vim3l_android_defconfig b/configs/khadas-vim3l_android_defconfig index d1141cd8cb9..be65d0feb12 100644 --- a/configs/khadas-vim3l_android_defconfig +++ b/configs/khadas-vim3l_android_defconfig @@ -57,7 +57,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ADC=y CONFIG_SARADC_MESON=y CONFIG_BUTTON=y diff --git a/configs/mocha_defconfig b/configs/mocha_defconfig index 8d352e49551..ab8cea69a02 100644 --- a/configs/mocha_defconfig +++ b/configs/mocha_defconfig @@ -54,7 +54,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/mot_defconfig b/configs/mot_defconfig index 8f0a52d719f..c5004c250fb 100644 --- a/configs/mot_defconfig +++ b/configs/mot_defconfig @@ -53,7 +53,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x11000000 diff --git a/configs/mt8183_pumpkin_defconfig b/configs/mt8183_pumpkin_defconfig index 9d0495f470c..4aceb73c34c 100644 --- a/configs/mt8183_pumpkin_defconfig +++ b/configs/mt8183_pumpkin_defconfig @@ -55,7 +55,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y # CONFIG_DOS_PARTITION is not set CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_DEVRES=y CONFIG_CLK=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 4294194ede6..6d2b1a17edf 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -57,7 +57,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index 0379b4bbfe9..e9184549601 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -75,7 +75,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_VERSION_VARIABLE=y CONFIG_USE_ROOTPATH=y CONFIG_ROOTPATH="/tftpboot/opos6ul-root" diff --git a/configs/ouya_defconfig b/configs/ouya_defconfig index d8f3f389b5e..60cc3796c5e 100644 --- a/configs/ouya_defconfig +++ b/configs/ouya_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index 422e3530e64..4d3bfaa6982 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -30,7 +30,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index 1815b24a4b7..fdbe87574d5 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index a8f80486791..4fd72ffbbf4 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -31,7 +31,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig index 21937a0decf..462bec3bae2 100644 --- a/configs/p2771-0000-000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -31,7 +31,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_SYS_I2C_TEGRA=y CONFIG_TEGRA186_BPMP_I2C=y CONFIG_DWC_ETH_QOS=y diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig index 4cd32e60a99..42043277e2d 100644 --- a/configs/p2771-0000-500_defconfig +++ b/configs/p2771-0000-500_defconfig @@ -30,7 +30,7 @@ CONFIG_BOOTP_PREFER_SERVERIP=y CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_SYS_I2C_TEGRA=y CONFIG_TEGRA186_BPMP_I2C=y CONFIG_DWC_ETH_QOS=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index 22afce410e8..492f1e29c8a 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -35,7 +35,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_SYS_I2C_TEGRA=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y diff --git a/configs/phycore_am62ax_r5_defconfig b/configs/phycore_am62ax_r5_defconfig index e37e3eca651..8ee6ed73adc 100644 --- a/configs/phycore_am62ax_r5_defconfig +++ b/configs/phycore_am62ax_r5_defconfig @@ -65,7 +65,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_SPL_DM=y CONFIG_SPL_DM_DEVICE_REMOVE=y CONFIG_SPL_DM_SEQ_ALIAS=y diff --git a/configs/picasso_defconfig b/configs/picasso_defconfig index e8a47f8cbf6..11cf01ee0ef 100644 --- a/configs/picasso_defconfig +++ b/configs/picasso_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x11000000 diff --git a/configs/qc750_defconfig b/configs/qc750_defconfig index 0088580513e..3f85890bdbd 100644 --- a/configs/qc750_defconfig +++ b/configs/qc750_defconfig @@ -53,7 +53,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index 7864fc50773..414bfdebab1 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -32,7 +32,7 @@ CONFIG_OF_DTB_PROPS_REMOVE=y CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_TFTP=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index b0da941e9ce..12d92067de5 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -31,7 +31,7 @@ CONFIG_OF_DTB_PROPS_REMOVE=y CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_TFTP=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/r8a779g0_whitehawk_defconfig b/configs/r8a779g0_whitehawk_defconfig index 8dcf8e35ee0..fefe356ed2b 100644 --- a/configs/r8a779g0_whitehawk_defconfig +++ b/configs/r8a779g0_whitehawk_defconfig @@ -19,7 +19,7 @@ CONFIG_CMD_REMOTEPROC=y CONFIG_REMOTEPROC_RENESAS_APMU=y CONFIG_SYS_CBSIZE=2048 CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BITBANGMII=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/r8a779h0_grayhawk_defconfig b/configs/r8a779h0_grayhawk_defconfig index 5b9ad93a596..33009429315 100644 --- a/configs/r8a779h0_grayhawk_defconfig +++ b/configs/r8a779h0_grayhawk_defconfig @@ -14,7 +14,7 @@ CONFIG_BOOTCOMMAND="tftp 0x48080000 Image && tftp 0x48000000 Image-r8a779h0-gray CONFIG_DEFAULT_FDT_FILE="r8a779h0-gray-hawk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BITBANGMII=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 61183be948a..15ec0a45901 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -38,7 +38,7 @@ CONFIG_OF_DTB_PROPS_REMOVE=y CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_TFTP=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index dab1c9a7353..41bdee19682 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -33,7 +33,7 @@ CONFIG_OF_DTB_PROPS_REMOVE=y CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_TFTP=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig index f9847de261d..e7c0a7e1eae 100644 --- a/configs/renesas_rzg2l_smarc_defconfig +++ b/configs/renesas_rzg2l_smarc_defconfig @@ -42,7 +42,7 @@ CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y diff --git a/configs/rzg2_beacon_defconfig b/configs/rzg2_beacon_defconfig index 5e19d365027..0b91337b17b 100644 --- a/configs/rzg2_beacon_defconfig +++ b/configs/rzg2_beacon_defconfig @@ -23,7 +23,7 @@ CONFIG_OF_LIST="renesas/r8a774a1-beacon-rzg2m-kit renesas/r8a774b1-beacon-rzg2n- CONFIG_MULTI_DTB_FIT_LZO=y CONFIG_MULTI_DTB_FIT_USER_DEFINED_AREA=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DM_PCA953X=y CONFIG_SYS_I2C_RCAR_I2C=y CONFIG_SYS_I2C_RCAR_IIC=y diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index 5e04090ef2b..d3611591e57 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -38,7 +38,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_SYS_I2C_TEGRA=y CONFIG_TEGRA_KEYBOARD=y CONFIG_MTD_RAW_NAND=y diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig index 65f7e8c212c..bebe6870da4 100644 --- a/configs/sei510_defconfig +++ b/configs/sei510_defconfig @@ -53,7 +53,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x6000000 diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig index 90f7a6fbf27..b7de10d71a9 100644 --- a/configs/sei610_defconfig +++ b/configs/sei610_defconfig @@ -53,7 +53,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_DFU_RAM=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x6000000 diff --git a/configs/star_defconfig b/configs/star_defconfig index 1ba3c00b063..a783fd86c74 100644 --- a/configs/star_defconfig +++ b/configs/star_defconfig @@ -54,7 +54,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x11000000 diff --git a/configs/stm32mp13_dhcor_defconfig b/configs/stm32mp13_dhcor_defconfig index 2357692c4c4..e5aaadd3920 100644 --- a/configs/stm32mp13_dhcor_defconfig +++ b/configs/stm32mp13_dhcor_defconfig @@ -35,7 +35,7 @@ CONFIG_CLK_SCMI=y CONFIG_SET_DFU_ALT_INFO=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_ENV_MMC_DEVICE_INDEX=0 -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_PHY_REALTEK=y CONFIG_DM_REGULATOR_SCMI=y CONFIG_RESET_SCMI=y diff --git a/configs/surface-rt_defconfig b/configs/surface-rt_defconfig index 71ee397d55a..4cd543ccb9c 100644 --- a/configs/surface-rt_defconfig +++ b/configs/surface-rt_defconfig @@ -50,7 +50,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index efc3f195c1b..070dce234d6 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -69,7 +69,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_LBA48=y diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig index fd8e96dfb09..39fb127ce35 100644 --- a/configs/tec-ng_defconfig +++ b/configs/tec-ng_defconfig @@ -39,7 +39,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_SYS_I2C_TEGRA=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SYS_NS16550=y diff --git a/configs/tegratab_defconfig b/configs/tegratab_defconfig index 93c9841e35f..00a0843d4d0 100644 --- a/configs/tegratab_defconfig +++ b/configs/tegratab_defconfig @@ -53,7 +53,7 @@ CONFIG_TEGRA_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/tf701t_defconfig b/configs/tf701t_defconfig index 620f8539273..a9976bf0388 100644 --- a/configs/tf701t_defconfig +++ b/configs/tf701t_defconfig @@ -53,7 +53,7 @@ CONFIG_TEGRA_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 diff --git a/configs/toradex-smarc-imx8mp_defconfig b/configs/toradex-smarc-imx8mp_defconfig index 0e7f1813dc1..dd6815d3465 100644 --- a/configs/toradex-smarc-imx8mp_defconfig +++ b/configs/toradex-smarc-imx8mp_defconfig @@ -89,7 +89,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/transformer_t20_defconfig b/configs/transformer_t20_defconfig index bbda38b2a3b..b4cc4130217 100644 --- a/configs/transformer_t20_defconfig +++ b/configs/transformer_t20_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x11000000 diff --git a/configs/transformer_t30_defconfig b/configs/transformer_t30_defconfig index b1ebd9b9012..eb3e41e68c5 100644 --- a/configs/transformer_t30_defconfig +++ b/configs/transformer_t30_defconfig @@ -56,7 +56,7 @@ CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_CLK_GPIO=y CONFIG_USB_FUNCTION_FASTBOOT=y diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig index 7792da7b90e..acfab5755ba 100644 --- a/configs/turris_mox_defconfig +++ b/configs/turris_mox_defconfig @@ -54,7 +54,7 @@ CONFIG_MAC_PARTITION=y CONFIG_OF_LIST="armada-3720-turris-mox armada-3720-ripe-atlas" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_ARP_TIMEOUT=200 CONFIG_NET_RETRY_COUNT=50 CONFIG_NETCONSOLE=y diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index 9e201bfbf41..810dc3f523f 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -41,7 +41,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DFU_MMC=y CONFIG_DFU_RAM=y CONFIG_DFU_SF=y diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index f94c6cf6623..5fa952f98a5 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -37,7 +37,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/verdin-am62_a53_defconfig b/configs/verdin-am62_a53_defconfig index 49431f503c6..4b8e7d9f490 100644 --- a/configs/verdin-am62_a53_defconfig +++ b/configs/verdin-am62_a53_defconfig @@ -89,7 +89,7 @@ CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/verdin-am62p_a53_defconfig b/configs/verdin-am62p_a53_defconfig index a9a18def354..e782ad4faca 100644 --- a/configs/verdin-am62p_a53_defconfig +++ b/configs/verdin-am62p_a53_defconfig @@ -92,7 +92,7 @@ CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 66c0d944208..7db6e81ee6d 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -84,7 +84,7 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index c2f78a9e90f..4cc69de041b 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -97,7 +97,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y CONFIG_ENV_MMC_DEVICE_INDEX=2 -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="eth0" diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 7a7e45c65de..e65d0fb9ef2 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -64,7 +64,7 @@ CONFIG_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_REDUNDANT=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_USE_ETHPRIME=y CONFIG_ETHPRIME="FEC" diff --git a/configs/x3_t30_defconfig b/configs/x3_t30_defconfig index e593a542239..3081d1203cf 100644 --- a/configs/x3_t30_defconfig +++ b/configs/x3_t30_defconfig @@ -52,7 +52,7 @@ CONFIG_CMD_EXT4_WRITE=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_ENV_OVERWRITE=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 CONFIG_BUTTON=y CONFIG_EXTCON=y CONFIG_EXTCON_MAX14526=y diff --git a/env/Kconfig b/env/Kconfig index 1decdd89648..3317f3c5603 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -219,7 +219,7 @@ config ENV_IS_IN_MMC Specifies which MMC device the environment is stored in. - CONFIG_SYS_MMC_ENV_PART (optional): + CONFIG_ENV_MMC_EMMC_HW_PARTITION (optional): Specifies which MMC partition the environment is stored in. If not set, defaults to partition 0, the user area. Common values might be @@ -252,7 +252,7 @@ config ENV_IS_IN_MMC This value may also be positive or negative; this is handled in the same way as CONFIG_ENV_OFFSET. - In case CONFIG_SYS_MMC_ENV_PART is 1 (i.e. environment in eMMC boot + In case CONFIG_ENV_MMC_EMMC_HW_PARTITION is 1 (i.e. environment in eMMC boot partition) then setting CONFIG_ENV_OFFSET_REDUND to the same value as CONFIG_ENV_OFFSET makes use of the second eMMC boot partition for the redundant environment copy. @@ -708,8 +708,8 @@ config ENV_MMC_DEVICE_INDEX The index is often derived from DT aliases mmcN node ordering, and matches the 'mmc list' command output. -config SYS_MMC_ENV_PART - int "mmc partition number" +config ENV_MMC_EMMC_HW_PARTITION + int "eMMC hardware partition number" depends on ENV_IS_IN_MMC || ENV_IS_IN_FAT default 0 help diff --git a/env/mmc.c b/env/mmc.c index dba99bd4d3d..5d1cb78e5ca 100644 --- a/env/mmc.c +++ b/env/mmc.c @@ -157,7 +157,7 @@ static inline s64 mmc_offset(struct mmc *mmc, int copy) int hwpart = 0; int err; -#if defined(CONFIG_SYS_MMC_ENV_PART) +#if defined(CONFIG_ENV_MMC_EMMC_HW_PARTITION) hwpart = mmc_get_env_part(mmc); #endif @@ -216,7 +216,7 @@ static bool mmc_env_is_redundant_in_both_boot_hwparts(struct mmc *mmc) if (!IS_ENABLED(CONFIG_ENV_REDUNDANT)) return false; - if (CONFIG_SYS_MMC_ENV_PART != 1) + if (CONFIG_ENV_MMC_EMMC_HW_PARTITION != 1) return false; return mmc_offset(mmc, 0) == mmc_offset(mmc, 1); @@ -239,10 +239,10 @@ __weak int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) return 0; } -#ifdef CONFIG_SYS_MMC_ENV_PART +#ifdef CONFIG_ENV_MMC_EMMC_HW_PARTITION __weak uint mmc_get_env_part(struct mmc *mmc) { - return CONFIG_SYS_MMC_ENV_PART; + return CONFIG_ENV_MMC_EMMC_HW_PARTITION; } static unsigned char env_mmc_orig_hwpart; diff --git a/include/mmc.h b/include/mmc.h index 87f7ef131b6..c6b2ab4a29f 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -996,7 +996,7 @@ void board_mmc_power_init(void); int board_mmc_init(struct bd_info *bis); int cpu_mmc_init(struct bd_info *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); -# ifdef CONFIG_SYS_MMC_ENV_PART +# ifdef CONFIG_ENV_MMC_EMMC_HW_PARTITION extern uint mmc_get_env_part(struct mmc *mmc); # endif int mmc_get_env_dev(void); -- cgit v1.3.1 From fb5235239aad43c41d528b2e6c8bd6c7b390cde1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 9 Jun 2025 21:26:42 +0200 Subject: env: Rename DEFAULT_ENV_FILE to ENV_DEFAULT_ENV_TEXT_FILE Rename the variable and add ENV_ prefix, so that all configuration options which are related to environment would have an CONFIG_ENV_ prefix. No functional change. Also rename USE_DEFAULT_ENV_FILE to USE_ENV_DEFAULT_ENV_TEXT_FILE . Signed-off-by: Marek Vasut --- Makefile | 4 ++-- board/qualcomm/qcom-phone.config | 2 +- boot/Kconfig | 6 +++--- configs/qcom_defconfig | 4 ++-- configs/qcom_ipq9574_mmc_defconfig | 4 ++-- doc/usage/environment.rst | 4 ++-- env/Kconfig | 6 +++--- include/env_default.h | 4 ++-- 8 files changed, 17 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/Makefile b/Makefile index c7b82299c19..c9c0d4646a9 100644 --- a/Makefile +++ b/Makefile @@ -1973,7 +1973,7 @@ ifeq ($(wildcard $(LDSCRIPT)),) @/bin/false endif -ifeq ($(CONFIG_USE_DEFAULT_ENV_FILE),y) +ifeq ($(CONFIG_ENV_USE_DEFAULT_ENV_TEXT_FILE),y) prepare1: $(defaultenv_h) envtools: $(defaultenv_h) @@ -2053,7 +2053,7 @@ $(timestamp_h): $(srctree)/Makefile FORCE $(dt_h): $(srctree)/Makefile FORCE $(call filechk,dt.h) -$(defaultenv_h): $(CONFIG_DEFAULT_ENV_FILE:"%"=%) FORCE +$(defaultenv_h): $(CONFIG_ENV_DEFAULT_ENV_TEXT_FILE:"%"=%) FORCE $(call filechk,defaultenv.h) # --------------------------------------------------------------------------- diff --git a/board/qualcomm/qcom-phone.config b/board/qualcomm/qcom-phone.config index 913c91757c1..d24094eefdd 100644 --- a/board/qualcomm/qcom-phone.config +++ b/board/qualcomm/qcom-phone.config @@ -1,5 +1,5 @@ # Settings for phones -CONFIG_DEFAULT_ENV_FILE="board/qualcomm/qcom-phone.env" +CONFIG_ENV_DEFAULT_ENV_TEXT_FILE="board/qualcomm/qcom-phone.env" # Hang on panic so the error message can be read CONFIG_PANIC_HANG=y # We use pause in various places to allow text to be read diff --git a/boot/Kconfig b/boot/Kconfig index 30eb5b328d7..01349e9096b 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -1845,7 +1845,7 @@ config USE_BOOTARGS config BOOTARGS string "Boot arguments" - depends on USE_BOOTARGS && !USE_DEFAULT_ENV_FILE + depends on USE_BOOTARGS && !ENV_USE_DEFAULT_ENV_TEXT_FILE help This can be used to pass arguments to the bootm command. The value of CONFIG_BOOTARGS goes into the environment value "bootargs". Note that @@ -1880,7 +1880,7 @@ config USE_BOOTCOMMAND config BOOTCOMMAND string "bootcmd value" - depends on USE_BOOTCOMMAND && !USE_DEFAULT_ENV_FILE + depends on USE_BOOTCOMMAND && !ENV_USE_DEFAULT_ENV_TEXT_FILE default "bootflow scan -lb" if BOOTSTD_DEFAULTS && CMD_BOOTFLOW_FULL default "bootflow scan" if BOOTSTD_DEFAULTS && !CMD_BOOTFLOW_FULL default "run distro_bootcmd" if !BOOTSTD_BOOTCOMMAND && DISTRO_DEFAULTS @@ -1903,7 +1903,7 @@ config USE_PREBOOT config PREBOOT string "preboot default value" - depends on USE_PREBOOT && !USE_DEFAULT_ENV_FILE + depends on USE_PREBOOT && !ENV_USE_DEFAULT_ENV_TEXT_FILE default "usb start" if USB_KEYBOARD default "" help diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index b8399701da0..5eb027ba27b 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -42,8 +42,8 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_LOG=y CONFIG_OF_LIVE=y CONFIG_OF_UPSTREAM_BUILD_VENDOR=y -CONFIG_USE_DEFAULT_ENV_FILE=y -CONFIG_DEFAULT_ENV_FILE="board/qualcomm/default.env" +CONFIG_ENV_USE_DEFAULT_ENV_TEXT_FILE=y +CONFIG_ENV_DEFAULT_ENV_TEXT_FILE="board/qualcomm/default.env" CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y CONFIG_CLK_STUB=y diff --git a/configs/qcom_ipq9574_mmc_defconfig b/configs/qcom_ipq9574_mmc_defconfig index 8d7d3d92c73..c7ce4f5c237 100644 --- a/configs/qcom_ipq9574_mmc_defconfig +++ b/configs/qcom_ipq9574_mmc_defconfig @@ -28,8 +28,8 @@ CONFIG_CMD_PART=y CONFIG_EFI_PARTITION=y CONFIG_OF_LIVE=y CONFIG_ENV_IS_IN_MMC=y -CONFIG_USE_DEFAULT_ENV_FILE=y -CONFIG_DEFAULT_ENV_FILE="board/qualcomm/default.env" +CONFIG_USE_ENV_DEFAULT_ENV_TEXT_FILE=y +CONFIG_ENV_DEFAULT_ENV_TEXT_FILE="board/qualcomm/default.env" CONFIG_CLK=y CONFIG_CLK_QCOM_IPQ9574=y CONFIG_MSM_GPIO=y diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index 7e2f2863d06..bb6c351b441 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -562,8 +562,8 @@ only effect after the next boot (yes, that's just like Windows). External environment file ------------------------- -The `CONFIG_USE_DEFAULT_ENV_FILE` option provides a way to bypass the -environment generation in U-Boot. If enabled, then `CONFIG_DEFAULT_ENV_FILE` +The `CONFIG_ENV_USE_DEFAULT_ENV_TEXT_FILE` option provides a way to bypass the +environment generation in U-Boot. If enabled, then `CONFIG_ENV_DEFAULT_ENV_TEXT_FILE` provides the name of a file which is converted into the environment, completely bypassing the standard environment variables in `env_default.h`. diff --git a/env/Kconfig b/env/Kconfig index 52f5cb86584..65ab8b6392d 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -749,7 +749,7 @@ config SCSI_ENV_PART_UUID help UUID of the SCSI partition that you want to store the environment in. -config USE_DEFAULT_ENV_FILE +config ENV_USE_DEFAULT_ENV_TEXT_FILE bool "Create default environment from file" help Normally, the default environment is automatically generated @@ -758,9 +758,9 @@ config USE_DEFAULT_ENV_FILE you can instead define the entire default environment in an external file. -config DEFAULT_ENV_FILE +config ENV_DEFAULT_ENV_TEXT_FILE string "Path to default environment file" - depends on USE_DEFAULT_ENV_FILE + depends on ENV_USE_DEFAULT_ENV_TEXT_FILE help The path containing the default environment. The format is the same as accepted by the mkenvimage tool: lines diff --git a/include/env_default.h b/include/env_default.h index 6e8f2ea90e7..9caf22cdd1d 100644 --- a/include/env_default.h +++ b/include/env_default.h @@ -27,7 +27,7 @@ char default_environment[] = { #else const char default_environment[] = { #endif -#ifndef CONFIG_USE_DEFAULT_ENV_FILE +#ifndef CONFIG_ENV_USE_DEFAULT_ENV_TEXT_FILE #ifdef CONFIG_ENV_CALLBACK_LIST_DEFAULT ENV_CALLBACK_VAR "=" CONFIG_ENV_CALLBACK_LIST_DEFAULT "\0" #endif @@ -136,7 +136,7 @@ const char default_environment[] = { "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0" #endif "\0" -#else /* CONFIG_USE_DEFAULT_ENV_FILE */ +#else /* CONFIG_ENV_USE_DEFAULT_ENV_TEXT_FILE */ #include "generated/defaultenv_autogenerated.h" #endif #ifdef DEFAULT_ENV_INSTANCE_EMBEDDED -- cgit v1.3.1 From 9d37a3d6e8b862071edfcb9ee95a0fbe45606918 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Tue, 17 Jun 2025 16:13:40 +0530 Subject: lmb: replace lmb_reserve() and lmb_alloc_addr() API's There currently are multiple allocation API's in the LMB module. There are a couple of API's for allocating memory(lmb_alloc() and lmb_alloc_base()), and then there are two for requesting a reservation for a particular memory region (lmb_reserve() and lmb_alloc_addr()). Introduce a single API lmb_alloc_mem() which will cater to all types of allocation requests and replace lmb_reserve() and lmb_alloc_addr() with the new API. Moreover, the lmb_reserve() API is pretty similar to the lmb_alloc_addr() API, with the one difference being that the lmb_reserve() API allows for reserving any address passed to it -- the address need not be part of the LMB memory map. The lmb_alloc_addr() does check that the address being requested is actually part of the LMB memory map. There is no need to support reserving memory regions which are outside the LMB memory map. Remove the lmb_reserve() API functionality and use the functionality provided by lmb_alloc_addr() instead. The lmb_alloc_addr() will check if the requested address is part of the LMB memory map and return an error if not. Signed-off-by: Sughosh Ganu Acked-by: Ilias Apalodimas --- arch/arm/mach-mediatek/tzcfg.c | 8 ++- arch/powerpc/cpu/mpc85xx/mp.c | 4 +- arch/powerpc/lib/misc.c | 5 +- boot/bootm.c | 15 ++++- boot/image-board.c | 11 +++- boot/image-fdt.c | 32 ++++++++-- cmd/booti.c | 10 +++- cmd/bootz.c | 10 +++- cmd/load.c | 9 ++- fs/fs.c | 5 +- include/lmb.h | 69 +++++++++++++--------- lib/efi_loader/efi_memory.c | 2 +- lib/lmb.c | 129 ++++++++++++++++++++++++----------------- test/lib/lmb.c | 27 ++++++--- 14 files changed, 223 insertions(+), 113 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-mediatek/tzcfg.c b/arch/arm/mach-mediatek/tzcfg.c index 71982ba4d20..c8fe8ac0e9b 100644 --- a/arch/arm/mach-mediatek/tzcfg.c +++ b/arch/arm/mach-mediatek/tzcfg.c @@ -173,6 +173,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) int arch_misc_init(void) { + phys_addr_t addr; struct arm_smccc_res res; /* @@ -180,11 +181,14 @@ int arch_misc_init(void) * there's no need to check the result */ arm_smccc_smc(MTK_SIP_GET_BL31_REGION, 0, 0, 0, 0, 0, 0, 0, &res); - lmb_reserve(res.a1, res.a2, LMB_NOMAP); + addr = (phys_addr_t)res.a1; + lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &addr, res.a2, LMB_NOMAP); arm_smccc_smc(MTK_SIP_GET_BL32_REGION, 0, 0, 0, 0, 0, 0, 0, &res); + addr = (phys_addr_t)res.a1; if (!res.a0 && res.a1 && res.a2) - lmb_reserve(res.a1, res.a2, LMB_NOMAP); + lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &addr, res.a2, + LMB_NOMAP); #if IS_ENABLED(CONFIG_CMD_PSTORE) char cmd[64]; diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 8918a401fac..bee6758dc9a 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -410,9 +410,9 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) void cpu_mp_lmb_reserve(void) { - u32 bootpg = determine_mp_bootpg(NULL); + phys_addr_t bootpg = determine_mp_bootpg(NULL); - lmb_reserve(bootpg, 4096, LMB_NONE); + lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &bootpg, 4096, LMB_NONE); } void setup_mp(void) diff --git a/arch/powerpc/lib/misc.c b/arch/powerpc/lib/misc.c index 7e303419624..fc10ae50cf8 100644 --- a/arch/powerpc/lib/misc.c +++ b/arch/powerpc/lib/misc.c @@ -36,11 +36,12 @@ int arch_misc_init(void) size = min(size, (ulong)CFG_SYS_LINUX_LOWMEM_MAX_SIZE); if (size < bootm_size) { - ulong base = bootmap_base + size; + phys_addr_t base = bootmap_base + size; printf("WARNING: adjusting available memory from 0x%lx to 0x%llx\n", size, (unsigned long long)bootm_size); - lmb_reserve(base, bootm_size - size, LMB_NONE); + lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &base, + bootm_size - size, LMB_NONE); } #ifdef CONFIG_MP diff --git a/boot/bootm.c b/boot/bootm.c index 108ca7fb472..3282bfc0b4b 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -698,9 +698,18 @@ static int bootm_load_os(struct bootm_headers *images, int boot_progress) images->os.end = relocated_addr + image_size; } - if (CONFIG_IS_ENABLED(LMB)) - lmb_reserve(images->os.load, (load_end - images->os.load), - LMB_NONE); + if (CONFIG_IS_ENABLED(LMB)) { + phys_addr_t load; + + load = (phys_addr_t)images->os.load; + err = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &load, + (load_end - images->os.load), LMB_NONE); + if (err) { + log_err("Unable to allocate memory %#lx for loading OS\n", + images->os.load); + return 1; + } + } return 0; } diff --git a/boot/image-board.c b/boot/image-board.c index 514f8e63f9c..b0fa028ceac 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -538,6 +538,7 @@ int boot_get_ramdisk(char const *select, struct bootm_headers *images, int boot_ramdisk_high(ulong rd_data, ulong rd_len, ulong *initrd_start, ulong *initrd_end) { + int err; char *s; phys_addr_t initrd_high; int initrd_copy_to_ram = 1; @@ -559,10 +560,18 @@ int boot_ramdisk_high(ulong rd_data, ulong rd_len, ulong *initrd_start, if (rd_data) { if (!initrd_copy_to_ram) { /* zero-copy ramdisk support */ + phys_addr_t initrd_addr; + debug(" in-place initrd\n"); *initrd_start = rd_data; *initrd_end = rd_data + rd_len; - lmb_reserve(rd_data, rd_len, LMB_NONE); + initrd_addr = (phys_addr_t)rd_data; + err = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, + &initrd_addr, rd_len, LMB_NONE); + if (err) { + puts("in-place initrd alloc failed\n"); + goto error; + } } else { if (initrd_high) *initrd_start = diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 8f718ad29f6..bd5a6231140 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -72,13 +72,15 @@ static const struct legacy_img_hdr *image_get_fdt(ulong fdt_addr) static void boot_fdt_reserve_region(u64 addr, u64 size, u32 flags) { long ret; + phys_addr_t rsv_addr; - ret = lmb_reserve(addr, size, flags); + rsv_addr = (phys_addr_t)addr; + ret = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &rsv_addr, size, flags); if (!ret) { debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n", (unsigned long long)addr, (unsigned long long)size, flags); - } else if (ret != -EEXIST) { + } else if (ret != -EEXIST && ret != -EINVAL) { puts("ERROR: reserving fdt memory region failed "); printf("(addr=%llx size=%llx flags=%x)\n", (unsigned long long)addr, @@ -155,7 +157,7 @@ void boot_fdt_add_mem_rsv_regions(void *fdt_blob) */ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) { - u64 start, size, usable, addr, low, mapsize; + u64 start, size, usable, low, mapsize; void *fdt_blob = *of_flat_tree; void *of_start = NULL; char *fdt_high; @@ -163,6 +165,7 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) int bank; int err; int disable_relocation = 0; + phys_addr_t addr; /* nothing to do */ if (*of_size == 0) @@ -185,7 +188,15 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) if (desired_addr == ~0UL) { /* All ones means use fdt in place */ of_start = fdt_blob; - lmb_reserve(map_to_sysmem(of_start), of_len, LMB_NONE); + addr = map_to_sysmem(fdt_blob); + err = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &addr, + of_len, LMB_NONE); + if (err) { + printf("Failed to reserve memory for fdt at %#llx\n", + (u64)addr); + goto error; + } + disable_relocation = 1; } else if (desired_addr) { addr = lmb_alloc_base(of_len, 0x1000, desired_addr, @@ -682,8 +693,17 @@ int image_setup_libfdt(struct bootm_headers *images, void *blob, bool lmb) of_size = ret; /* Create a new LMB reservation */ - if (CONFIG_IS_ENABLED(LMB) && lmb) - lmb_reserve(map_to_sysmem(blob), of_size, LMB_NONE); + if (CONFIG_IS_ENABLED(LMB) && lmb) { + phys_addr_t fdt_addr; + + fdt_addr = map_to_sysmem(blob); + ret = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &fdt_addr, + of_size, LMB_NONE); + if (ret) { + printf("Failed to reserve memory for the fdt at %#llx\n", + (u64)fdt_addr); + } + } #if defined(CONFIG_ARCH_KEYSTONE) if (IS_ENABLED(CONFIG_OF_BOARD_SETUP)) diff --git a/cmd/booti.c b/cmd/booti.c index 7e6d9426299..e6f67d6e136 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -30,6 +30,7 @@ static int booti_start(struct bootm_info *bmi) uint8_t *temp; ulong dest; ulong dest_end; + phys_addr_t ep_addr; unsigned long comp_len; unsigned long decomp_len; int ctype; @@ -88,7 +89,14 @@ static int booti_start(struct bootm_info *bmi) images->os.start = relocated_addr; images->os.end = relocated_addr + image_size; - lmb_reserve(images->ep, le32_to_cpu(image_size), LMB_NONE); + ep_addr = (phys_addr_t)images->ep; + ret = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &ep_addr, + le32_to_cpu(image_size), LMB_NONE); + if (ret) { + printf("Failed to allocate memory for the image at %#llx\n", + (unsigned long long)images->ep); + return 1; + } /* * Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not diff --git a/cmd/bootz.c b/cmd/bootz.c index 99318ff213f..44af7d012aa 100644 --- a/cmd/bootz.c +++ b/cmd/bootz.c @@ -28,6 +28,7 @@ static int bootz_start(struct cmd_tbl *cmdtp, int flag, int argc, { ulong zi_start, zi_end; struct bootm_info bmi; + phys_addr_t ep_addr; int ret; bootm_init(&bmi); @@ -56,7 +57,14 @@ static int bootz_start(struct cmd_tbl *cmdtp, int flag, int argc, if (ret != 0) return 1; - lmb_reserve(images->ep, zi_end - zi_start, LMB_NONE); + ep_addr = (phys_addr_t)images->ep; + ret = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &ep_addr, zi_end - zi_start, + LMB_NONE); + if (ret) { + printf("Failed to allocate memory for the image at %#llx\n", + (unsigned long long)images->ep); + return 1; + } /* * Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not diff --git a/cmd/load.c b/cmd/load.c index 899bb4f598e..a6e54fc668c 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -178,17 +178,20 @@ static ulong load_serial(long offset) #endif { void *dst; + phys_addr_t dst_addr; - ret = lmb_reserve(store_addr, binlen, LMB_NONE); + dst_addr = (phys_addr_t)store_addr; + ret = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &dst_addr, + binlen, LMB_NONE); if (ret) { printf("\nCannot overwrite reserved area (%08lx..%08lx)\n", store_addr, store_addr + binlen); return ret; } - dst = map_sysmem(store_addr, binlen); + dst = map_sysmem(dst_addr, binlen); memcpy(dst, binbuf, binlen); unmap_sysmem(dst); - lmb_free(store_addr, binlen); + lmb_free(dst_addr, binlen); } if ((store_addr) < start_addr) start_addr = store_addr; diff --git a/fs/fs.c b/fs/fs.c index 1f36872fb9a..2650328b358 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -580,6 +580,7 @@ static int fs_read_lmb_check(const char *filename, ulong addr, loff_t offset, int ret; loff_t size; loff_t read_len; + phys_addr_t read_addr; /* get the actual size of the file */ ret = info->size(filename, &size); @@ -597,7 +598,9 @@ static int fs_read_lmb_check(const char *filename, ulong addr, loff_t offset, lmb_dump_all(); - if (!lmb_alloc_addr(addr, read_len, LMB_NONE)) + read_addr = (phys_addr_t)addr; + if (!lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &read_addr, read_len, + LMB_NONE)) return 0; log_err("** Reading file would overwrite reserved memory **\n"); diff --git a/include/lmb.h b/include/lmb.h index 606a92cca48..8906b42181f 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -31,6 +31,14 @@ #define LMB_NOOVERWRITE BIT(2) #define LMB_NONOTIFY BIT(3) +/** + * enum lmb_mem_type - type of memory allocation request + * @LMB_MEM_ALLOC_ADDR: request for a particular region of memory + */ +enum lmb_mem_type { + LMB_MEM_ALLOC_ADDR = 1, +}; + /** * enum lmb_map_op - memory map operation */ @@ -67,6 +75,37 @@ struct lmb { bool test; }; +/** + * lmb_alloc_mem() - Request LMB memory + * @type: Type of memory allocation request + * @align: Alignment of the memory region requested(0 for none) + * @addr: Base address of the allocated memory region + * @size: Size in bytes of the allocation request + * @flags: Memory region attributes to be set + * + * Allocate a region of memory where the allocation is based on the parameters + * that have been passed to the function.The first parameter specifies the + * type of allocation that is being requested. The second parameter, @align + * is used to specify if the allocation is to be made with a particular + * alignment. Use 0 for no alignment requirements. + * + * The allocated address is returned through the @addr parameter when @type + * is @LMB_MEM_ALLOC_ANY or @LMB_MEM_ALLOC_MAX. If @type is + * @LMB_MEM_ALLOC_ADDR the @addr parameter would contain the address being + * requested. + * + * The flags parameter is used to specify the memory attributes of the + * requested region. + * + * Return: 0 on success, -ve value on failure + * + * When the allocation is of type @LMB_MEM_ALLOC_ADDR, the return value can + * be -EINVAL if the requested memory region is not part of the LMB memory + * map, and -EEXIST if the requested region is already allocated. + */ +int lmb_alloc_mem(enum lmb_mem_type type, u64 align, phys_addr_t *addr, + phys_size_t size, u32 flags); + /** * lmb_init() - Initialise the LMB module. * @@ -91,19 +130,6 @@ void lmb_add_memory(void); long lmb_add(phys_addr_t base, phys_size_t size); -/** - * lmb_reserve() - Reserve one region with a specific flags bitfield - * @base: Base address of the memory region - * @size: Size of the memory region - * @flags: Flags for the memory region - * - * Return: - * * %0 - Added successfully, or it's already added (only if LMB_NONE) - * * %-EEXIST - The region is already added, and flags != LMB_NONE - * * %-1 - Failure - */ -long lmb_reserve(phys_addr_t base, phys_size_t size, u32 flags); - phys_addr_t lmb_alloc(phys_size_t size, ulong align); phys_size_t lmb_get_free_size(phys_addr_t addr); @@ -124,21 +150,6 @@ phys_size_t lmb_get_free_size(phys_addr_t addr); phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr, uint flags); -/** - * lmb_alloc_addr() - Allocate specified memory address with specified attributes - * - * @base: Base Address requested - * @size: Size of the region requested - * @flags: Memory region attributes to be set - * - * Allocate a region of memory with the attributes specified through the - * parameter. The base parameter is used to specify the base address - * of the requested region. - * - * Return: 0 on success -1 on error - */ -int lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags); - /** * lmb_is_reserved_flags() - Test if address is in reserved region with flag * bits set @@ -175,7 +186,7 @@ void lmb_pop(struct lmb *store); static inline int lmb_read_check(phys_addr_t addr, phys_size_t len) { - return lmb_alloc_addr(addr, len, LMB_NONE); + return lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &addr, len, LMB_NONE); } /** diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 0abb1f6159a..77950a267cc 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -493,7 +493,7 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type, return EFI_NOT_FOUND; addr = map_to_sysmem((void *)(uintptr_t)*memory); - if (lmb_alloc_addr(addr, len, flags)) + if (lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &addr, len, flags)) return EFI_NOT_FOUND; break; default: diff --git a/lib/lmb.c b/lib/lmb.c index bb6f232f6bc..226cb6f1d9f 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -488,6 +488,54 @@ void lmb_dump_all(void) #endif } +/** + * lmb_can_reserve_region() - check if the region can be reserved + * @base: base address of region to be reserved + * @size: size of region to be reserved + * @flags: flag of the region to be reserved + * + * Go through all the reserved regions and ensure that the requested + * region does not overlap with any existing regions. An overlap is + * allowed only when the flag of the request region and the existing + * region is LMB_NONE. + * + * Return: true if region can be reserved, false otherwise + */ +static bool lmb_can_reserve_region(phys_addr_t base, phys_size_t size, + u32 flags) +{ + uint i; + struct lmb_region *lmb_reserved = lmb.used_mem.data; + + for (i = 0; i < lmb.used_mem.count; i++) { + u32 rgnflags = lmb_reserved[i].flags; + phys_addr_t rgnbase = lmb_reserved[i].base; + phys_size_t rgnsize = lmb_reserved[i].size; + + if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) { + if (flags != LMB_NONE || flags != rgnflags) + return false; + } + } + + return true; +} + +static long lmb_reserve(phys_addr_t base, phys_size_t size, u32 flags) +{ + long ret = 0; + struct alist *lmb_rgn_lst = &lmb.used_mem; + + if (!lmb_can_reserve_region(base, size, flags)) + return -EEXIST; + + ret = lmb_add_region_flags(lmb_rgn_lst, base, size, flags); + if (ret) + return ret; + + return lmb_map_update_notify(base, size, LMB_MAP_OP_RESERVE, flags); +} + static void lmb_reserve_uboot_region(void) { int bank; @@ -557,39 +605,6 @@ static __maybe_unused void lmb_reserve_common_spl(void) } } -/** - * lmb_can_reserve_region() - check if the region can be reserved - * @base: base address of region to be reserved - * @size: size of region to be reserved - * @flags: flag of the region to be reserved - * - * Go through all the reserved regions and ensure that the requested - * region does not overlap with any existing regions. An overlap is - * allowed only when the flag of the request region and the existing - * region is LMB_NONE. - * - * Return: true if region can be reserved, false otherwise - */ -static bool lmb_can_reserve_region(phys_addr_t base, phys_size_t size, - u32 flags) -{ - uint i; - struct lmb_region *lmb_reserved = lmb.used_mem.data; - - for (i = 0; i < lmb.used_mem.count; i++) { - u32 rgnflags = lmb_reserved[i].flags; - phys_addr_t rgnbase = lmb_reserved[i].base; - phys_size_t rgnsize = lmb_reserved[i].size; - - if (lmb_addrs_overlap(base, size, rgnbase, rgnsize)) { - if (flags != LMB_NONE || flags != rgnflags) - return false; - } - } - - return true; -} - void lmb_add_memory(void) { int i; @@ -657,21 +672,6 @@ long lmb_free(phys_addr_t base, phys_size_t size) return lmb_free_flags(base, size, LMB_NONE); } -long lmb_reserve(phys_addr_t base, phys_size_t size, u32 flags) -{ - long ret = 0; - struct alist *lmb_rgn_lst = &lmb.used_mem; - - if (!lmb_can_reserve_region(base, size, flags)) - return -EEXIST; - - ret = lmb_add_region_flags(lmb_rgn_lst, base, size, flags); - if (ret) - return ret; - - return lmb_map_update_notify(base, size, LMB_MAP_OP_RESERVE, flags); -} - static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr, u32 flags) { @@ -742,7 +742,7 @@ phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr, return _lmb_alloc_base(size, align, max_addr, flags); } -int lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags) +static int _lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags) { long rgn; struct lmb_region *lmb_memory = lmb.available_mem.data; @@ -756,14 +756,35 @@ int lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags) */ if (lmb_addrs_overlap(lmb_memory[rgn].base, lmb_memory[rgn].size, - base + size - 1, 1)) { + base + size - 1, 1)) /* ok, reserve the memory */ - if (!lmb_reserve(base, size, flags)) - return 0; - } + return lmb_reserve(base, size, flags); + } + + return -EINVAL; +} + +int lmb_alloc_mem(enum lmb_mem_type type, u64 align, phys_addr_t *addr, + phys_size_t size, u32 flags) +{ + int ret = -1; + + if (!size) + return 0; + + if (!addr) + return -EINVAL; + + switch (type) { + case LMB_MEM_ALLOC_ADDR: + ret = _lmb_alloc_addr(*addr, size, flags); + break; + default: + log_debug("%s: Invalid memory allocation type requested %d\n", + __func__, type); } - return -1; + return ret; } /* Return number of bytes from a given address that are free */ diff --git a/test/lib/lmb.c b/test/lib/lmb.c index 3bf558f7f4f..751909fc2cf 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -71,6 +71,19 @@ static int setup_lmb_test(struct unit_test_state *uts, struct lmb *store, return 0; } +static int lmb_reserve(phys_addr_t addr, phys_size_t size, u32 flags) +{ + int err; + + err = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &addr, size, flags); + if (err) + return err; + + return 0; +} + +#define lmb_alloc_addr(addr, size, flags) lmb_reserve(addr, size, flags) + static int test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram, const phys_size_t ram_size, const phys_addr_t ram0, const phys_size_t ram0_size, @@ -568,7 +581,7 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE); ut_asserteq(b, 0); b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); - ut_asserteq(b, -1); + ut_asserteq(b, -EEXIST); b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE); ut_asserteq(b, 0); b = lmb_alloc_addr(alloc_addr_a, 0x2000, LMB_NONE); @@ -578,9 +591,9 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); ut_asserteq(b, 0); b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NONE); - ut_asserteq(b, -1); + ut_asserteq(b, -EEXIST); b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); - ut_asserteq(b, -1); + ut_asserteq(b, -EEXIST); ret = lmb_free(alloc_addr_a, 0x1000); ut_asserteq(ret, 0); @@ -599,7 +612,7 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) alloc_addr_a + 0x4000, 0x1000, 0, 0); c = lmb_alloc_addr(alloc_addr_a + 0x1000, 0x5000, LMB_NONE); - ut_asserteq(c, -1); + ut_asserteq(c, -EEXIST); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000, alloc_addr_a + 0x4000, 0x1000, 0, 0); @@ -646,7 +659,7 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) alloc_addr_a + 0x4000, 0x1000, 0, 0); c = lmb_alloc_addr(alloc_addr_a + 0x1000, 0x5000, LMB_NOOVERWRITE); - ut_asserteq(c, -1); + ut_asserteq(c, -EEXIST); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000, alloc_addr_a + 0x4000, 0x1000, 0, 0); @@ -739,11 +752,11 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) /* check that allocating outside memory fails */ if (ram_end != 0) { ret = lmb_alloc_addr(ram_end, 1, LMB_NONE); - ut_asserteq(ret, -1); + ut_asserteq(ret, -EINVAL); } if (ram != 0) { ret = lmb_alloc_addr(ram - 1, 1, LMB_NONE); - ut_asserteq(ret, -1); + ut_asserteq(ret, -EINVAL); } lmb_pop(&store); -- cgit v1.3.1 From 6e4675b8e5d8d52d871042d6ac3429d6d1daf875 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Tue, 17 Jun 2025 16:13:41 +0530 Subject: lmb: replace the lmb_alloc() and lmb_alloc_base() API's There currently are two API's for requesting memory from the LMB module, lmb_alloc() and lmb_alloc_base(). The function which does the actual allocation is the same. Use the earlier introduced API lmb_alloc_mem() for both types of allocation requests. Signed-off-by: Sughosh Ganu Acked-by: Ilias Apalodimas --- arch/arm/mach-apple/board.c | 27 ++++++++++++++-------- arch/arm/mach-snapdragon/board.c | 30 +++++++++++++++--------- boot/bootm.c | 12 ++++++---- boot/image-board.c | 49 +++++++++++++++++++++------------------- boot/image-fdt.c | 35 ++++++++++++++++------------ include/lmb.h | 22 ++++-------------- lib/efi_loader/efi_memory.c | 14 +++++++----- lib/lmb.c | 28 ++++++++++------------- test/lib/lmb.c | 26 +++++++++++++++++++++ 9 files changed, 141 insertions(+), 102 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 2604c5a710e..4cd8979bdc2 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -773,22 +773,31 @@ u64 get_page_table_size(void) #define KERNEL_COMP_SIZE SZ_128M +#define lmb_alloc(size, addr) lmb_alloc_mem(LMB_MEM_ALLOC_ANY, SZ_2M, addr, size, LMB_NONE) + int board_late_init(void) { u32 status = 0; + phys_addr_t addr; /* somewhat based on the Linux Kernel boot requirements: * align by 2M and maximal FDT size 2M */ - status |= env_set_hex("loadaddr", lmb_alloc(SZ_1G, SZ_2M)); - status |= env_set_hex("fdt_addr_r", lmb_alloc(SZ_2M, SZ_2M)); - status |= env_set_hex("kernel_addr_r", lmb_alloc(SZ_128M, SZ_2M)); - status |= env_set_hex("ramdisk_addr_r", lmb_alloc(SZ_1G, SZ_2M)); - status |= env_set_hex("kernel_comp_addr_r", - lmb_alloc(KERNEL_COMP_SIZE, SZ_2M)); - status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE); - status |= env_set_hex("scriptaddr", lmb_alloc(SZ_4M, SZ_2M)); - status |= env_set_hex("pxefile_addr_r", lmb_alloc(SZ_4M, SZ_2M)); + status |= !lmb_alloc(SZ_1G, &addr) ? env_set_hex("loadaddr", addr) : 1; + status |= !lmb_alloc(SZ_2M, &addr) ? + env_set_hex("fdt_addr_r", addr) : 1; + status |= !lmb_alloc(SZ_128M, &addr) ? + env_set_hex("kernel_addr_r", addr) : 1; + status |= !lmb_alloc(SZ_1G, &addr) ? + env_set_hex("ramdisk_addr_r", addr) : 1; + status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ? + env_set_hex("kernel_comp_addr_r", addr) : 1; + status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ? + env_set_hex("kernel_comp_size", addr) : 1; + status |= !lmb_alloc(SZ_4M, &addr) ? + env_set_hex("scriptaddr", addr) : 1; + status |= !lmb_alloc(SZ_4M, &addr) ? + env_set_hex("pxefile_addr_r", addr) : 1; if (status) log_warning("late_init: Failed to set run time variables\n"); diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index 5547d6d054f..87a173e0acb 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -492,7 +492,7 @@ void __weak qcom_late_init(void) #define FASTBOOT_BUF_SIZE 0 #endif -#define addr_alloc(size) lmb_alloc(size, SZ_2M) +#define lmb_alloc(size, addr) lmb_alloc_mem(LMB_MEM_ALLOC_ANY, SZ_2M, addr, size, LMB_NONE) /* Stolen from arch/arm/mach-apple/board.c */ int board_late_init(void) @@ -502,18 +502,26 @@ int board_late_init(void) struct fdt_header *fdt_blob = (struct fdt_header *)gd->fdt_blob; /* We need to be fairly conservative here as we support boards with just 1G of TOTAL RAM */ - addr = addr_alloc(SZ_128M); + status |= !lmb_alloc(SZ_128M, &addr) ? + env_set_hex("loadaddr", addr) : 1; status |= env_set_hex("kernel_addr_r", addr); - status |= env_set_hex("loadaddr", addr); - status |= env_set_hex("ramdisk_addr_r", addr_alloc(SZ_128M)); - status |= env_set_hex("kernel_comp_addr_r", addr_alloc(KERNEL_COMP_SIZE)); - status |= env_set_hex("kernel_comp_size", KERNEL_COMP_SIZE); + status |= !lmb_alloc(SZ_128M, &addr) ? + env_set_hex("ramdisk_addr_r", addr) : 1; + status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ? + env_set_hex("kernel_comp_addr_r", addr) : 1; + status |= !lmb_alloc(KERNEL_COMP_SIZE, &addr) ? + env_set_hex("kernel_comp_size", addr) : 1; + status |= !lmb_alloc(SZ_4M, &addr) ? + env_set_hex("scriptaddr", addr) : 1; + status |= !lmb_alloc(SZ_4M, &addr) ? + env_set_hex("pxefile_addr_r", addr) : 1; + if (IS_ENABLED(CONFIG_FASTBOOT)) - status |= env_set_hex("fastboot_addr_r", addr_alloc(FASTBOOT_BUF_SIZE)); - status |= env_set_hex("scriptaddr", addr_alloc(SZ_4M)); - status |= env_set_hex("pxefile_addr_r", addr_alloc(SZ_4M)); - addr = addr_alloc(SZ_2M); - status |= env_set_hex("fdt_addr_r", addr); + status |= !lmb_alloc(FASTBOOT_BUF_SIZE, &addr) ? + env_set_hex("fastboot_addr_r", addr) : 1; + + status |= !lmb_alloc(SZ_2M, &addr) ? + env_set_hex("fdt_addr_r", addr) : 1; if (status) log_warning("%s: Failed to set run time variables\n", __func__); diff --git a/boot/bootm.c b/boot/bootm.c index 3282bfc0b4b..4bdca22ea8c 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -623,12 +623,16 @@ static int bootm_load_os(struct bootm_headers *images, int boot_progress) */ if (os.type == IH_TYPE_KERNEL_NOLOAD && os.comp != IH_COMP_NONE) { ulong req_size = ALIGN(image_len * 4, SZ_1M); + phys_addr_t addr; - load = lmb_alloc(req_size, SZ_2M); - if (!load) + err = lmb_alloc_mem(LMB_MEM_ALLOC_ANY, SZ_2M, &addr, + req_size, LMB_NONE); + if (err) return 1; - os.load = load; - images->ep = load; + + load = (ulong)addr; + os.load = (ulong)addr; + images->ep = (ulong)addr; debug("Allocated %lx bytes at %lx for kernel (size %lx) decompression\n", req_size, load, image_len); } diff --git a/boot/image-board.c b/boot/image-board.c index b0fa028ceac..005d60caf5c 100644 --- a/boot/image-board.c +++ b/boot/image-board.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -566,27 +567,24 @@ int boot_ramdisk_high(ulong rd_data, ulong rd_len, ulong *initrd_start, *initrd_start = rd_data; *initrd_end = rd_data + rd_len; initrd_addr = (phys_addr_t)rd_data; - err = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, - &initrd_addr, rd_len, LMB_NONE); + err = lmb_alloc_mem(LMB_MEM_ALLOC_ADDR, 0, &initrd_addr, + rd_len, LMB_NONE); if (err) { puts("in-place initrd alloc failed\n"); goto error; } } else { - if (initrd_high) - *initrd_start = - (ulong)lmb_alloc_base(rd_len, - 0x1000, - initrd_high, - LMB_NONE); - else - *initrd_start = (ulong)lmb_alloc(rd_len, - 0x1000); + enum lmb_mem_type type = initrd_high ? + LMB_MEM_ALLOC_MAX : LMB_MEM_ALLOC_ANY; - if (*initrd_start == 0) { + err = lmb_alloc_mem(type, 0x1000, &initrd_high, rd_len, + LMB_NONE); + if (err) { puts("ramdisk - allocation error\n"); goto error; } + + *initrd_start = (ulong)initrd_high; bootstage_mark(BOOTSTAGE_ID_COPY_RAMDISK); *initrd_end = *initrd_start + rd_len; @@ -837,9 +835,10 @@ int boot_get_loadable(struct bootm_headers *images) */ int boot_get_cmdline(ulong *cmd_start, ulong *cmd_end) { - int barg; + int barg, err; char *cmdline; char *s; + phys_addr_t addr; /* * Help the compiler detect that this function is only called when @@ -849,12 +848,14 @@ int boot_get_cmdline(ulong *cmd_start, ulong *cmd_end) return 0; barg = IF_ENABLED_INT(CONFIG_SYS_BOOT_GET_CMDLINE, CONFIG_SYS_BARGSIZE); - cmdline = (char *)(ulong)lmb_alloc_base(barg, 0xf, - env_get_bootm_mapsize() + env_get_bootm_low(), - LMB_NONE); - if (!cmdline) + addr = env_get_bootm_mapsize() + env_get_bootm_low(); + + err = lmb_alloc_mem(LMB_MEM_ALLOC_MAX, 0xf, &addr, barg, LMB_NONE); + if (err) return -1; + cmdline = (char *)(uintptr_t)addr; + s = env_get("bootargs"); if (!s) s = ""; @@ -883,14 +884,16 @@ int boot_get_cmdline(ulong *cmd_start, ulong *cmd_end) */ int boot_get_kbd(struct bd_info **kbd) { - *kbd = (struct bd_info *)(ulong)lmb_alloc_base(sizeof(struct bd_info), - 0xf, - env_get_bootm_mapsize() + - env_get_bootm_low(), - LMB_NONE); - if (!*kbd) + int err; + phys_addr_t addr; + + addr = env_get_bootm_mapsize() + env_get_bootm_low(); + err = lmb_alloc_mem(LMB_MEM_ALLOC_MAX, 0xf, &addr, + sizeof(struct bd_info), LMB_NONE); + if (err) return -1; + *kbd = (struct bd_info *)(uintptr_t)addr; **kbd = *gd->bd; debug("## kernel board info at 0x%08lx\n", (ulong)*kbd); diff --git a/boot/image-fdt.c b/boot/image-fdt.c index bd5a6231140..2720ce6f6f3 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -183,9 +183,9 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) /* If fdt_high is set use it to select the relocation address */ fdt_high = env_get("fdt_high"); if (fdt_high) { - ulong desired_addr = hextoul(fdt_high, NULL); + ulong high_addr = hextoul(fdt_high, NULL); - if (desired_addr == ~0UL) { + if (high_addr == ~0UL) { /* All ones means use fdt in place */ of_start = fdt_blob; addr = map_to_sysmem(fdt_blob); @@ -198,16 +198,17 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) } disable_relocation = 1; - } else if (desired_addr) { - addr = lmb_alloc_base(of_len, 0x1000, desired_addr, - LMB_NONE); - of_start = map_sysmem(addr, of_len); - if (of_start == NULL) { - puts("Failed using fdt_high value for Device Tree"); + } else { + enum lmb_mem_type type = high_addr ? + LMB_MEM_ALLOC_MAX : LMB_MEM_ALLOC_ANY; + + addr = high_addr; + err = lmb_alloc_mem(type, 0x1000, &addr, of_len, + LMB_NONE); + if (err) { + puts("Failed to allocate memory for Device Tree relocation\n"); goto error; } - } else { - addr = lmb_alloc(of_len, 0x1000); of_start = map_sysmem(addr, of_len); } } else { @@ -229,11 +230,15 @@ int boot_relocate_fdt(char **of_flat_tree, ulong *of_size) * for LMB allocation. */ usable = min(start + size, low + mapsize); - addr = lmb_alloc_base(of_len, 0x1000, usable, LMB_NONE); - of_start = map_sysmem(addr, of_len); - /* Allocation succeeded, use this block. */ - if (of_start != NULL) - break; + addr = usable; + err = lmb_alloc_mem(LMB_MEM_ALLOC_MAX, 0x1000, + &addr, of_len, LMB_NONE); + if (!err) { + of_start = map_sysmem(addr, of_len); + /* Allocation succeeded, use this block. */ + if (of_start) + break; + } /* * Reduce the mapping size in the next bank diff --git a/include/lmb.h b/include/lmb.h index 8906b42181f..34dbc25759d 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -34,9 +34,13 @@ /** * enum lmb_mem_type - type of memory allocation request * @LMB_MEM_ALLOC_ADDR: request for a particular region of memory + * @LMB_MEM_ALLOC_ANY: allocate any available memory region + * @LMB_MEM_ALLOC_MAX: allocate memory below a particular address */ enum lmb_mem_type { LMB_MEM_ALLOC_ADDR = 1, + LMB_MEM_ALLOC_ANY, + LMB_MEM_ALLOC_MAX, }; /** @@ -130,26 +134,8 @@ void lmb_add_memory(void); long lmb_add(phys_addr_t base, phys_size_t size); -phys_addr_t lmb_alloc(phys_size_t size, ulong align); phys_size_t lmb_get_free_size(phys_addr_t addr); -/** - * lmb_alloc_base() - Allocate specified memory region with specified - * attributes - * @size: Size of the region requested - * @align: Alignment of the memory region requested - * @max_addr: Maximum address of the requested region - * @flags: Memory region attributes to be set - * - * Allocate a region of memory with the attributes specified through the - * parameter. The max_addr parameter is used to specify the maximum address - * below which the requested region should be allocated. - * - * Return: Base address on success, 0 on error. - */ -phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr, - uint flags); - /** * lmb_is_reserved_flags() - Test if address is in reserved region with flag * bits set diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 77950a267cc..466f45c98b1 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -454,6 +454,7 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type, enum efi_memory_type memory_type, efi_uintn_t pages, uint64_t *memory) { + int err; u64 efi_addr, len; uint flags; efi_status_t ret; @@ -475,17 +476,18 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type, switch (type) { case EFI_ALLOCATE_ANY_PAGES: /* Any page */ - addr = (u64)lmb_alloc_base(len, EFI_PAGE_SIZE, - LMB_ALLOC_ANYWHERE, flags); - if (!addr) + err = lmb_alloc_mem(LMB_MEM_ALLOC_ANY, EFI_PAGE_SIZE, &addr, + len, flags); + if (err) return EFI_OUT_OF_RESOURCES; break; case EFI_ALLOCATE_MAX_ADDRESS: /* Max address */ addr = map_to_sysmem((void *)(uintptr_t)*memory); - addr = (u64)lmb_alloc_base(len, EFI_PAGE_SIZE, addr, - flags); - if (!addr) + + err = lmb_alloc_mem(LMB_MEM_ALLOC_MAX, EFI_PAGE_SIZE, &addr, + len, flags); + if (err) return EFI_OUT_OF_RESOURCES; break; case EFI_ALLOCATE_ADDRESS: diff --git a/lib/lmb.c b/lib/lmb.c index 226cb6f1d9f..a30ae64f8cd 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -672,16 +672,18 @@ long lmb_free(phys_addr_t base, phys_size_t size) return lmb_free_flags(base, size, LMB_NONE); } -static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, - phys_addr_t max_addr, u32 flags) +static int _lmb_alloc_base(phys_size_t size, ulong align, + phys_addr_t *addr, u32 flags) { int ret; long i, rgn; + phys_addr_t max_addr; phys_addr_t base = 0; phys_addr_t res_base; struct lmb_region *lmb_used = lmb.used_mem.data; struct lmb_region *lmb_memory = lmb.available_mem.data; + max_addr = *addr; for (i = lmb.available_mem.count - 1; i >= 0; i--) { phys_addr_t lmbbase = lmb_memory[i].base; phys_size_t lmbsize = lmb_memory[i].size; @@ -714,8 +716,8 @@ static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, flags); if (ret) return ret; - - return base; + *addr = base; + return 0; } res_base = lmb_used[rgn].base; @@ -728,18 +730,7 @@ static phys_addr_t _lmb_alloc_base(phys_size_t size, ulong align, log_debug("%s: Failed to allocate 0x%lx bytes below 0x%lx\n", __func__, (ulong)size, (ulong)max_addr); - return 0; -} - -phys_addr_t lmb_alloc(phys_size_t size, ulong align) -{ - return _lmb_alloc_base(size, align, LMB_ALLOC_ANYWHERE, LMB_NONE); -} - -phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t max_addr, - uint flags) -{ - return _lmb_alloc_base(size, align, max_addr, flags); + return -1; } static int _lmb_alloc_addr(phys_addr_t base, phys_size_t size, u32 flags) @@ -776,6 +767,11 @@ int lmb_alloc_mem(enum lmb_mem_type type, u64 align, phys_addr_t *addr, return -EINVAL; switch (type) { + case LMB_MEM_ALLOC_ANY: + *addr = LMB_ALLOC_ANYWHERE; + case LMB_MEM_ALLOC_MAX: + ret = _lmb_alloc_base(size, align, addr, flags); + break; case LMB_MEM_ALLOC_ADDR: ret = _lmb_alloc_addr(*addr, size, flags); break; diff --git a/test/lib/lmb.c b/test/lib/lmb.c index 751909fc2cf..d8eab96527a 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -82,6 +82,32 @@ static int lmb_reserve(phys_addr_t addr, phys_size_t size, u32 flags) return 0; } +static phys_addr_t lmb_alloc(phys_size_t size, ulong align) +{ + int err; + phys_addr_t addr; + + err = lmb_alloc_mem(LMB_MEM_ALLOC_ANY, align, &addr, size, LMB_NONE); + if (err) + return 0; + + return addr; +} + +static phys_addr_t lmb_alloc_base(phys_size_t size, ulong align, + phys_addr_t max_addr, u32 flags) +{ + int err; + phys_addr_t addr; + + addr = max_addr; + err = lmb_alloc_mem(LMB_MEM_ALLOC_MAX, align, &addr, size, flags); + if (err) + return 0; + + return addr; +} + #define lmb_alloc_addr(addr, size, flags) lmb_reserve(addr, size, flags) static int test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram, -- cgit v1.3.1 From 3faffba6f19834bdda12b7942e545ff4a4a6e18b Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Tue, 17 Jun 2025 16:13:42 +0530 Subject: lmb: staticise lmb_add_memory() lmb_add_memory() is only called from the lmb module. Mark the function as static. Signed-off-by: Sughosh Ganu Reviewed-by: Ilias Apalodimas --- include/lmb.h | 8 -------- lib/lmb.c | 2 +- 2 files changed, 1 insertion(+), 9 deletions(-) (limited to 'include') diff --git a/include/lmb.h b/include/lmb.h index 34dbc25759d..aead799d555 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -124,14 +124,6 @@ int lmb_alloc_mem(enum lmb_mem_type type, u64 align, phys_addr_t *addr, */ int lmb_init(void); -/** - * lmb_add_memory() - Add memory range for LMB allocations. - * - * Add the entire available memory range to the pool of memory that - * can be used by the LMB module for allocations. - */ -void lmb_add_memory(void); - long lmb_add(phys_addr_t base, phys_size_t size); phys_size_t lmb_get_free_size(phys_addr_t addr); diff --git a/lib/lmb.c b/lib/lmb.c index a30ae64f8cd..3265fad317d 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -605,7 +605,7 @@ static __maybe_unused void lmb_reserve_common_spl(void) } } -void lmb_add_memory(void) +static void lmb_add_memory(void) { int i; phys_addr_t bank_end; -- cgit v1.3.1 From 745f981f7083f70856b3db307b759774957a8082 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Tue, 17 Jun 2025 16:13:43 +0530 Subject: lmb: use a single function to free up memory There is no need to have two separate API's for freeing up memory. Use a single API lmb_free() to achieve this. Signed-off-by: Sughosh Ganu Reviewed-by: Ilias Apalodimas --- boot/image-fdt.c | 2 +- cmd/load.c | 2 +- include/lmb.h | 6 ++---- lib/efi_loader/efi_memory.c | 6 +++--- lib/lmb.c | 8 +------- test/lib/lmb.c | 49 +++++++++++++++++++++++---------------------- 6 files changed, 33 insertions(+), 40 deletions(-) (limited to 'include') diff --git a/boot/image-fdt.c b/boot/image-fdt.c index 2720ce6f6f3..97b6385ab7c 100644 --- a/boot/image-fdt.c +++ b/boot/image-fdt.c @@ -690,7 +690,7 @@ int image_setup_libfdt(struct bootm_headers *images, void *blob, bool lmb) /* Delete the old LMB reservation */ if (CONFIG_IS_ENABLED(LMB) && lmb) - lmb_free(map_to_sysmem(blob), fdt_totalsize(blob)); + lmb_free(map_to_sysmem(blob), fdt_totalsize(blob), LMB_NONE); ret = fdt_shrink_to_minimum(blob, 0); if (ret < 0) diff --git a/cmd/load.c b/cmd/load.c index a6e54fc668c..159767aa7f7 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -191,7 +191,7 @@ static ulong load_serial(long offset) dst = map_sysmem(dst_addr, binlen); memcpy(dst, binbuf, binlen); unmap_sysmem(dst); - lmb_free(dst_addr, binlen); + lmb_free(dst_addr, binlen, LMB_NONE); } if ((store_addr) < start_addr) start_addr = store_addr; diff --git a/include/lmb.h b/include/lmb.h index aead799d555..5d5f037ccb9 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -142,16 +142,14 @@ phys_size_t lmb_get_free_size(phys_addr_t addr); int lmb_is_reserved_flags(phys_addr_t addr, int flags); /** - * lmb_free_flags() - Free up a region of memory + * lmb_free() - Free up a region of memory * @base: Base Address of region to be freed * @size: Size of the region to be freed * @flags: Memory region attributes * * Return: 0 on success, negative error code on failure. */ -long lmb_free_flags(phys_addr_t base, phys_size_t size, uint flags); - -long lmb_free(phys_addr_t base, phys_size_t size); +long lmb_free(phys_addr_t base, phys_size_t size, u32 flags); void lmb_dump_all(void); void lmb_dump_all_force(void); diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 466f45c98b1..0828a47da61 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -508,7 +508,7 @@ efi_status_t efi_allocate_pages(enum efi_allocate_type type, ret = efi_update_memory_map(efi_addr, pages, memory_type, true, false); if (ret != EFI_SUCCESS) { /* Map would overlap, bail out */ - lmb_free_flags(addr, (u64)pages << EFI_PAGE_SHIFT, flags); + lmb_free(addr, (u64)pages << EFI_PAGE_SHIFT, flags); unmap_sysmem((void *)(uintptr_t)efi_addr); return EFI_OUT_OF_RESOURCES; } @@ -548,8 +548,8 @@ efi_status_t efi_free_pages(uint64_t memory, efi_uintn_t pages) * been mapped with map_sysmem() from efi_allocate_pages(). Convert * it back to an address LMB understands */ - status = lmb_free_flags(map_to_sysmem((void *)(uintptr_t)memory), len, - LMB_NOOVERWRITE); + status = lmb_free(map_to_sysmem((void *)(uintptr_t)memory), len, + LMB_NOOVERWRITE); if (status) return EFI_NOT_FOUND; diff --git a/lib/lmb.c b/lib/lmb.c index 3265fad317d..4af8dae4359 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -655,8 +655,7 @@ long lmb_add(phys_addr_t base, phys_size_t size) return lmb_map_update_notify(base, size, LMB_MAP_OP_ADD, LMB_NONE); } -long lmb_free_flags(phys_addr_t base, phys_size_t size, - uint flags) +long lmb_free(phys_addr_t base, phys_size_t size, u32 flags) { long ret; @@ -667,11 +666,6 @@ long lmb_free_flags(phys_addr_t base, phys_size_t size, return lmb_map_update_notify(base, size, LMB_MAP_OP_FREE, flags); } -long lmb_free(phys_addr_t base, phys_size_t size) -{ - return lmb_free_flags(base, size, LMB_NONE); -} - static int _lmb_alloc_base(phys_size_t size, ulong align, phys_addr_t *addr, u32 flags) { diff --git a/test/lib/lmb.c b/test/lib/lmb.c index d8eab96527a..b6259bef442 100644 --- a/test/lib/lmb.c +++ b/test/lib/lmb.c @@ -182,7 +182,7 @@ static int test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram, ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 8, 0, 0); - ret = lmb_free(a, 4); + ret = lmb_free(a, 4, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 4, 0, 0); @@ -191,12 +191,12 @@ static int test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram, ut_asserteq(a, a2); ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 8, 0, 0); - ret = lmb_free(a2, 4); + ret = lmb_free(a2, 4, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 4, 0, 0); - ret = lmb_free(b, 4); + ret = lmb_free(b, 4, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, 0, 0, 3, alloc_64k_addr - 8, 4, alloc_64k_addr, 0x10000, @@ -206,17 +206,17 @@ static int test_multi_alloc(struct unit_test_state *uts, const phys_addr_t ram, ut_asserteq(b, b2); ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 8, 0x10000 + 8, ram_end - 8, 4, 0, 0); - ret = lmb_free(b2, 4); + ret = lmb_free(b2, 4, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, 0, 0, 3, alloc_64k_addr - 8, 4, alloc_64k_addr, 0x10000, ram_end - 8, 4); - ret = lmb_free(c, 4); + ret = lmb_free(c, 4, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, 0, 0, 2, alloc_64k_addr - 8, 4, alloc_64k_addr, 0x10000, 0, 0); - ret = lmb_free(d, 4); + ret = lmb_free(d, 4, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, 0, 0, 1, alloc_64k_addr, 0x10000, 0, 0, 0, 0); @@ -320,7 +320,7 @@ static int test_bigblock(struct unit_test_state *uts, const phys_addr_t ram) ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, a, big_block_size + 0x10000, 0, 0, 0, 0); - ret = lmb_free(a, big_block_size); + ret = lmb_free(a, big_block_size, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, alloc_64k_addr, 0x10000, 0, 0, 0, 0); @@ -392,12 +392,12 @@ static int test_noreserved(struct unit_test_state *uts, const phys_addr_t ram, - alloc_size_aligned, alloc_size, 0, 0); } /* and free them */ - ret = lmb_free(b, alloc_size); + ret = lmb_free(b, alloc_size, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram + ram_size - alloc_size_aligned, alloc_size, 0, 0, 0, 0); - ret = lmb_free(a, alloc_size); + ret = lmb_free(a, alloc_size, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 0, 0, 0, 0, 0, 0, 0); @@ -408,7 +408,7 @@ static int test_noreserved(struct unit_test_state *uts, const phys_addr_t ram, ram + ram_size - alloc_size_aligned, alloc_size, 0, 0, 0, 0); /* and free it */ - ret = lmb_free(b, alloc_size); + ret = lmb_free(b, alloc_size, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 0, 0, 0, 0, 0, 0, 0); @@ -476,12 +476,12 @@ static int lib_test_lmb_at_0(struct unit_test_state *uts) ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, a, ram_size - 4, 0, 0, 0, 0); /* check that this was an error by freeing b */ - ret = lmb_free(b, 4); + ret = lmb_free(b, 4, LMB_NONE); ut_asserteq(ret, -1); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, a, ram_size - 4, 0, 0, 0, 0); - ret = lmb_free(a, ram_size - 4); + ret = lmb_free(a, ram_size - 4, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 0, 0, 0, 0, 0, 0, 0); @@ -612,7 +612,7 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ut_asserteq(b, 0); b = lmb_alloc_addr(alloc_addr_a, 0x2000, LMB_NONE); ut_asserteq(b, 0); - ret = lmb_free(alloc_addr_a, 0x2000); + ret = lmb_free(alloc_addr_a, 0x2000, LMB_NONE); ut_asserteq(ret, 0); b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); ut_asserteq(b, 0); @@ -620,7 +620,7 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ut_asserteq(b, -EEXIST); b = lmb_alloc_addr(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); ut_asserteq(b, -EEXIST); - ret = lmb_free(alloc_addr_a, 0x1000); + ret = lmb_free(alloc_addr_a, 0x1000, LMB_NONE); ut_asserteq(ret, 0); /* @@ -642,9 +642,9 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000, alloc_addr_a + 0x4000, 0x1000, 0, 0); - ret = lmb_free(alloc_addr_a, 0x1000); + ret = lmb_free(alloc_addr_a, 0x1000, LMB_NONE); ut_asserteq(ret, 0); - ret = lmb_free(alloc_addr_a + 0x4000, 0x1000); + ret = lmb_free(alloc_addr_a + 0x4000, 0x1000, LMB_NOOVERWRITE); ut_asserteq(ret, 0); /* @@ -667,7 +667,7 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, alloc_addr_a, 0x6000, 0, 0, 0, 0); - ret = lmb_free(alloc_addr_a, 0x6000); + ret = lmb_free(alloc_addr_a, 0x6000, LMB_NONE); ut_asserteq(ret, 0); /* @@ -689,9 +689,9 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, alloc_addr_a, 0x1000, alloc_addr_a + 0x4000, 0x1000, 0, 0); - ret = lmb_free(alloc_addr_a, 0x1000); + ret = lmb_free(alloc_addr_a, 0x1000, LMB_NOOVERWRITE); ut_asserteq(ret, 0); - ret = lmb_free(alloc_addr_a + 0x4000, 0x1000); + ret = lmb_free(alloc_addr_a + 0x4000, 0x1000, LMB_NOOVERWRITE); ut_asserteq(ret, 0); /* reserve 3 blocks */ @@ -732,7 +732,8 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) 0, 0, 0, 0); /* free thge allocation from d */ - ret = lmb_free(alloc_addr_c + 0x10000, ram_end - alloc_addr_c - 0x10000); + ret = lmb_free(alloc_addr_c + 0x10000, ram_end - alloc_addr_c - 0x10000, + LMB_NONE); ut_asserteq(ret, 0); /* allocate at 3 points in free range */ @@ -741,7 +742,7 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ut_asserteq(d, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x18010000, ram_end - 4, 4, 0, 0); - ret = lmb_free(ram_end - 4, 4); + ret = lmb_free(ram_end - 4, 4, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000, 0, 0, 0, 0); @@ -750,7 +751,7 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ut_asserteq(d, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 2, ram, 0x18010000, ram_end - 128, 4, 0, 0); - ret = lmb_free(ram_end - 128, 4); + ret = lmb_free(ram_end - 128, 4, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000, 0, 0, 0, 0); @@ -759,13 +760,13 @@ static int test_alloc_addr(struct unit_test_state *uts, const phys_addr_t ram) ut_asserteq(d, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010004, 0, 0, 0, 0); - ret = lmb_free(alloc_addr_c + 0x10000, 4); + ret = lmb_free(alloc_addr_c + 0x10000, 4, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram, 0x18010000, 0, 0, 0, 0); /* allocate at the bottom a was assigned to ram at the top */ - ret = lmb_free(ram, alloc_addr_a - ram); + ret = lmb_free(ram, alloc_addr_a - ram, LMB_NONE); ut_asserteq(ret, 0); ASSERT_LMB(mem_lst, used_lst, ram, ram_size, 1, ram + 0x8000000, 0x10010000, 0, 0, 0, 0); -- cgit v1.3.1 From 5c8de1bcfb0024993d902fb5dcfe87546116799b Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 8 Jun 2025 09:54:27 +0200 Subject: sandbox: align LMB memory To implement the EFI_SYSTEM_TABLE_POINTER we need 4 MiB aligned memory. On the sandbox LMB uses addresses relative to the start of a page aligned RAM buffer allocated with mmap(). This leads to a mismatch of alignment between EFI which uses pointers and LMB which uses phys_addr_t. Ensure that the RAM buffer used for LMB is 4 MiB aligned. Signed-off-by: Heinrich Schuchardt Reviewed-by: Tom Rini Reviewed-by: Ilias Apalodimas --- arch/sandbox/cpu/state.c | 6 ++++-- arch/sandbox/include/asm/state.h | 1 + include/configs/sandbox.h | 2 ++ 3 files changed, 7 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index 49236db99c2..6a15c8b0a18 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -480,7 +480,9 @@ int state_init(void) state = &main_state; state->ram_size = CFG_SYS_SDRAM_SIZE; - state->ram_buf = os_malloc(state->ram_size); + state->mmap_addr = os_malloc(state->ram_size + SB_SDRAM_ALIGN); + state->ram_buf = (uint8_t *)ALIGN((uintptr_t)state->mmap_addr, + SB_SDRAM_ALIGN); if (!state->ram_buf) { printf("Out of memory\n"); os_exit(1); @@ -533,7 +535,7 @@ int state_uninit(void) trace_set_enabled(0); os_free(state->state_fdt); - os_free(state->ram_buf); + os_free(state->mmap_addr); memset(state, '\0', sizeof(*state)); return 0; diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h index dc21a623106..9dea0980bfc 100644 --- a/arch/sandbox/include/asm/state.h +++ b/arch/sandbox/include/asm/state.h @@ -75,6 +75,7 @@ struct sandbox_state { char **argv; /* Command line arguments */ const char *jumped_fname; /* Jumped from previous U-Boot */ const char *prog_fname; /* U-Boot executable filename */ + uint8_t *mmap_addr; /* Memory allocated via mmap */ uint8_t *ram_buf; /* Emulated RAM buffer */ unsigned long ram_size; /* Size of RAM buffer */ const char *ram_buf_fname; /* Filename to use for RAM buffer */ diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index db2ac7f83bb..44d4960d487 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -14,6 +14,8 @@ #define CFG_SYS_SDRAM_BASE 0 #define CFG_SYS_SDRAM_SIZE \ (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20) +/** define SB_SDRAM_ALIGN - Alignment of emulated RAM */ +#define SB_SDRAM_ALIGN 0x400000 #define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} -- cgit v1.3.1 From e5d4733c2e1937eb7b622771bfea9f1fda0425c6 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 20 Jun 2025 10:21:47 -0600 Subject: m68k: Remove astro_mcf5373l board This board is currently unmaintained. Remove it. Acked-by: Angelo Dureghello Signed-off-by: Tom Rini --- arch/m68k/Kconfig | 5 - arch/m68k/dts/Makefile | 1 - arch/m68k/dts/astro_mcf5373l.dts | 27 --- board/astro/mcf5373l/Kconfig | 15 -- board/astro/mcf5373l/MAINTAINERS | 6 - board/astro/mcf5373l/Makefile | 6 - board/astro/mcf5373l/astro.h | 44 ----- board/astro/mcf5373l/fpga.c | 407 --------------------------------------- board/astro/mcf5373l/mcf5373l.c | 201 ------------------- configs/astro_mcf5373l_defconfig | 51 ----- include/configs/astro_mcf5373l.h | 187 ------------------ 11 files changed, 950 deletions(-) delete mode 100644 arch/m68k/dts/astro_mcf5373l.dts delete mode 100644 board/astro/mcf5373l/Kconfig delete mode 100644 board/astro/mcf5373l/MAINTAINERS delete mode 100644 board/astro/mcf5373l/Makefile delete mode 100644 board/astro/mcf5373l/astro.h delete mode 100644 board/astro/mcf5373l/fpga.c delete mode 100644 board/astro/mcf5373l/mcf5373l.c delete mode 100644 configs/astro_mcf5373l_defconfig delete mode 100644 include/configs/astro_mcf5373l.h (limited to 'include') diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index b288c65e7fd..8ade6f7b9d1 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -155,10 +155,6 @@ config TARGET_M5282EVB bool "Support M5282EVB" select M5282 -config TARGET_ASTRO_MCF5373L - bool "Support astro_mcf5373l" - select M5373 - config TARGET_M53017EVB bool "Support M53017EVB" select M53015 @@ -183,7 +179,6 @@ config TARGET_STMARK2 endchoice source "board/BuS/eb_cpu5282/Kconfig" -source "board/astro/mcf5373l/Kconfig" source "board/cobra5272/Kconfig" source "board/freescale/m5208evbe/Kconfig" source "board/freescale/m5235evb/Kconfig" diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile index 0f06109aa06..c89559be309 100644 --- a/arch/m68k/dts/Makefile +++ b/arch/m68k/dts/Makefile @@ -11,7 +11,6 @@ dtb-$(CONFIG_TARGET_M5253DEMO) += M5253DEMO.dtb dtb-$(CONFIG_TARGET_M5272C3) += M5272C3.dtb dtb-$(CONFIG_TARGET_M5275EVB) += M5275EVB.dtb dtb-$(CONFIG_TARGET_M5282EVB) += M5282EVB.dtb -dtb-$(CONFIG_TARGET_ASTRO_MCF5373L) += astro_mcf5373l.dtb dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb dtb-$(CONFIG_TARGET_M5329EVB) += M5329AFEE.dtb M5329BFEE.dtb dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb diff --git a/arch/m68k/dts/astro_mcf5373l.dts b/arch/m68k/dts/astro_mcf5373l.dts deleted file mode 100644 index 40f84dd64b6..00000000000 --- a/arch/m68k/dts/astro_mcf5373l.dts +++ /dev/null @@ -1,27 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Angelo Dureghello - */ - -/dts-v1/; -/include/ "mcf537x.dtsi" - -/ { - model = "Astro mcf5373l"; - compatible = "astro,mcf5373l"; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&uart0 { - bootph-all; - status = "okay"; -}; - -&i2c0 { - clock-frequency = <80000>; - u-boot,i2c-slave-addr = <0x7f>; - status = "okay"; -}; diff --git a/board/astro/mcf5373l/Kconfig b/board/astro/mcf5373l/Kconfig deleted file mode 100644 index a7c04cef83d..00000000000 --- a/board/astro/mcf5373l/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_ASTRO_MCF5373L - -config SYS_CPU - default "mcf532x" - -config SYS_BOARD - default "mcf5373l" - -config SYS_VENDOR - default "astro" - -config SYS_CONFIG_NAME - default "astro_mcf5373l" - -endif diff --git a/board/astro/mcf5373l/MAINTAINERS b/board/astro/mcf5373l/MAINTAINERS deleted file mode 100644 index 6c23da71968..00000000000 --- a/board/astro/mcf5373l/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -MCF5373L BOARD -M: Wolfgang Wegner -S: Maintained -F: board/astro/mcf5373l/ -F: include/configs/astro_mcf5373l.h -F: configs/astro_mcf5373l_defconfig diff --git a/board/astro/mcf5373l/Makefile b/board/astro/mcf5373l/Makefile deleted file mode 100644 index d3ea0d06a8d..00000000000 --- a/board/astro/mcf5373l/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. - -obj-y = mcf5373l.o fpga.o diff --git a/board/astro/mcf5373l/astro.h b/board/astro/mcf5373l/astro.h deleted file mode 100644 index b55a6f785ce..00000000000 --- a/board/astro/mcf5373l/astro.h +++ /dev/null @@ -1,44 +0,0 @@ -#ifndef __ASTRO_H__ -#define __ASTRO_H__ - -/* in mcf5373l.c */ -int rs_serial_init(int port, int baud); -void astro_put_char(char ch); -int astro_is_char(void); -int astro_get_char(void); - -/* in fpga.c */ -int astro5373l_altera_load(void); -int astro5373l_xilinx_load(void); - -/* data structures used for communication (update.c) */ -typedef struct card_id { - char card_type; - char hardware_version; - char software_version; - char software_subversion; /* " ","a".."z" */ - char fpga_version_altera; - char fpga_version_xilinx; -} card_id_t; - -typedef struct { - unsigned char mode; - unsigned char deviation; - unsigned short freq; -} __attribute__ ((packed)) output_params_t; - -typedef struct { - unsigned short satfreq; - unsigned char satdatallg; - unsigned short symbolrate; - unsigned char viterbirate; - unsigned char symbolrate_l; - output_params_t output_params; - unsigned char reserve; - unsigned char card_error; - unsigned short dummy_ts_id; - unsigned char dummy_pat_ver; - unsigned char dummy_sdt_ver; -} __attribute__ ((packed)) parameters_t; - -#endif /* __ASTRO_H__ */ diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c deleted file mode 100644 index 6e505c630d1..00000000000 --- a/board/astro/mcf5373l/fpga.c +++ /dev/null @@ -1,407 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2006 - * Wolfgang Wegner, ASTRO Strobel Kommunikationssysteme GmbH, - * w.wegner@astro-kom.de - * - * based on the files by - * Heiko Schocher, DENX Software Engineering, hs@denx.de - * and - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - */ - -/* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "fpga.h" - -int altera_pre_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char tmp_char; - unsigned short tmp_short; - - /* first, set the required pins to GPIO function */ - /* PAR_T0IN -> GPIO */ - tmp_char = readb(&gpiop->par_timer); - tmp_char &= 0xfc; - writeb(tmp_char, &gpiop->par_timer); - /* all QSPI pins -> GPIO */ - writew(0x0000, &gpiop->par_qspi); - /* U0RTS, U0CTS -> GPIO */ - tmp_short = __raw_readw(&gpiop->par_uart); - tmp_short &= 0xfff3; - __raw_writew(tmp_short, &gpiop->par_uart); - /* all PWM pins -> GPIO */ - writeb(0x00, &gpiop->par_pwm); - /* next, set data direction registers */ - writeb(0x01, &gpiop->pddr_timer); - writeb(0x25, &gpiop->pddr_qspi); - writeb(0x0c, &gpiop->pddr_uart); - writeb(0x04, &gpiop->pddr_pwm); - - /* ensure other SPI peripherals are deselected */ - writeb(0x08, &gpiop->ppd_uart); - writeb(0x38, &gpiop->ppd_qspi); - - /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */ - writeb(0xFB, &gpiop->pclrr_uart); - /* enable Altera configuration by clearing QSPI_CS2 and DT0IN */ - writeb(0xFE, &gpiop->pclrr_timer); - writeb(0xDF, &gpiop->pclrr_qspi); - return FPGA_SUCCESS; -} - -/* Set the state of CONFIG Pin */ -int altera_config_fn(int assert_config, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert_config) - writeb(0x04, &gpiop->ppd_uart); - else - writeb(0xFB, &gpiop->pclrr_uart); - return FPGA_SUCCESS; -} - -/* Returns the state of STATUS Pin */ -int altera_status_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (readb(&gpiop->ppd_pwm) & 0x08) - return FPGA_FAIL; - return FPGA_SUCCESS; -} - -/* Returns the state of CONF_DONE Pin */ -int altera_done_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (readb(&gpiop->ppd_pwm) & 0x20) - return FPGA_FAIL; - return FPGA_SUCCESS; -} - -/* - * writes the complete buffer to the FPGA - * writing the complete buffer in one function is much faster, - * then calling it for every bit - */ -int altera_write_fn(const void *buf, size_t len, int flush, int cookie) -{ - size_t bytecount = 0; - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char *data = (unsigned char *)buf; - unsigned char val = 0; - int i; - int len_40 = len / 40; - - while (bytecount < len) { - val = data[bytecount++]; - i = 8; - do { - writeb(0xFB, &gpiop->pclrr_qspi); - if (val & 0x01) - writeb(0x01, &gpiop->ppd_qspi); - else - writeb(0xFE, &gpiop->pclrr_qspi); - writeb(0x04, &gpiop->ppd_qspi); - val >>= 1; - i--; - } while (i > 0); - - if (bytecount % len_40 == 0) { -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) - schedule(); -#endif -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc('.'); /* let them know we are alive */ -#endif -#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc()) - return FPGA_FAIL; -#endif - } - } - return FPGA_SUCCESS; -} - -/* called, when programming is aborted */ -int altera_abort_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - writeb(0x20, &gpiop->ppd_qspi); - writeb(0x08, &gpiop->ppd_uart); - return FPGA_SUCCESS; -} - -/* called, when programming was succesful */ -int altera_post_fn(int cookie) -{ - return altera_abort_fn(cookie); -} - -/* - * Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - * FIXME: relocation not yet working for coldfire, see below! - */ -Altera_CYC2_Passive_Serial_fns altera_fns = { - altera_pre_fn, - altera_config_fn, - altera_status_fn, - altera_done_fn, - altera_write_fn, - altera_abort_fn, - altera_post_fn -}; - -#define FPGA_COUNT 1 -Altera_desc altera_fpga[FPGA_COUNT] = { - {Altera_CYC2, - passive_serial, - 85903, - (void *)&altera_fns, - NULL, - 0} -}; - -/* Initialize the fpga. Return 1 on success, 0 on failure. */ -int astro5373l_altera_load(void) -{ - int i; - - for (i = 0; i < FPGA_COUNT; i++) { - /* - * I did not yet manage to get relocation work properly, - * so set stuff here instead of static initialisation: - */ - altera_fns.pre = altera_pre_fn; - altera_fns.config = altera_config_fn; - altera_fns.status = altera_status_fn; - altera_fns.done = altera_done_fn; - altera_fns.write = altera_write_fn; - altera_fns.abort = altera_abort_fn; - altera_fns.post = altera_post_fn; - altera_fpga[i].iface_fns = (void *)&altera_fns; - fpga_add(fpga_altera, &altera_fpga[i]); - } - return 1; -} - -/* Set the FPGA's PROG_B line to the specified level */ -int xilinx_pgm_config_fn(int assert, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert) - writeb(0xFB, &gpiop->pclrr_uart); - else - writeb(0x04, &gpiop->ppd_uart); - return assert; -} - -/* - * Test the state of the active-low FPGA INIT line. Return 1 on INIT - * asserted (low). - */ -int xilinx_init_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - return (readb(&gpiop->ppd_pwm) & 0x08) == 0; -} - -/* Test the state of the active-high FPGA DONE pin */ -int xilinx_done_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - return (readb(&gpiop->ppd_pwm) & 0x20) >> 5; -} - -/* Abort an FPGA operation */ -int xilinx_abort_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - /* ensure all SPI peripherals and FPGAs are deselected */ - writeb(0x08, &gpiop->ppd_uart); - writeb(0x01, &gpiop->ppd_timer); - writeb(0x38, &gpiop->ppd_qspi); - return FPGA_FAIL; -} - -/* - * FPGA pre-configuration function. Just make sure that - * FPGA reset is asserted to keep the FPGA from starting up after - * configuration. - */ -int xilinx_pre_config_fn(int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char tmp_char; - unsigned short tmp_short; - - /* first, set the required pins to GPIO function */ - /* PAR_T0IN -> GPIO */ - tmp_char = readb(&gpiop->par_timer); - tmp_char &= 0xfc; - writeb(tmp_char, &gpiop->par_timer); - /* all QSPI pins -> GPIO */ - writew(0x0000, &gpiop->par_qspi); - /* U0RTS, U0CTS -> GPIO */ - tmp_short = __raw_readw(&gpiop->par_uart); - tmp_short &= 0xfff3; - __raw_writew(tmp_short, &gpiop->par_uart); - /* all PWM pins -> GPIO */ - writeb(0x00, &gpiop->par_pwm); - /* next, set data direction registers */ - writeb(0x01, &gpiop->pddr_timer); - writeb(0x25, &gpiop->pddr_qspi); - writeb(0x0c, &gpiop->pddr_uart); - writeb(0x04, &gpiop->pddr_pwm); - - /* ensure other SPI peripherals are deselected */ - writeb(0x08, &gpiop->ppd_uart); - writeb(0x38, &gpiop->ppd_qspi); - writeb(0x01, &gpiop->ppd_timer); - - /* CONFIG = 0, STATUS = 0 -> FPGA in reset state */ - writeb(0xFB, &gpiop->pclrr_uart); - /* enable Xilinx configuration by clearing QSPI_CS2 and U0CTS */ - writeb(0xF7, &gpiop->pclrr_uart); - writeb(0xDF, &gpiop->pclrr_qspi); - return 0; -} - -/* - * FPGA post configuration function. Should perform a test if FPGA is running. - */ -int xilinx_post_config_fn(int cookie) -{ - int rc = 0; - - /* - * no test yet - */ - return rc; -} - -int xilinx_clk_config_fn(int assert_clk, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert_clk) - writeb(0x04, &gpiop->ppd_qspi); - else - writeb(0xFB, &gpiop->pclrr_qspi); - return assert_clk; -} - -int xilinx_wr_config_fn(int assert_write, int flush, int cookie) -{ - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - - if (assert_write) - writeb(0x01, &gpiop->ppd_qspi); - else - writeb(0xFE, &gpiop->pclrr_qspi); - return assert_write; -} - -int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie) -{ - size_t bytecount = 0; - gpio_t *gpiop = (gpio_t *)MMAP_GPIO; - unsigned char *data = (unsigned char *)buf; - unsigned char val = 0; - int i; - int len_40 = len / 40; - - for (bytecount = 0; bytecount < len; bytecount++) { - val = *(data++); - for (i = 8; i > 0; i--) { - writeb(0xFB, &gpiop->pclrr_qspi); - if (val & 0x80) - writeb(0x01, &gpiop->ppd_qspi); - else - writeb(0xFE, &gpiop->pclrr_qspi); - writeb(0x04, &gpiop->ppd_qspi); - val <<= 1; - } - if (bytecount % len_40 == 0) { -#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG) - schedule(); -#endif -#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - putc('.'); /* let them know we are alive */ -#endif -#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC - if (ctrlc()) - return FPGA_FAIL; -#endif - } - } - return FPGA_SUCCESS; -} - -/* - * Note that these are pointers to code that is in Flash. They will be - * relocated at runtime. - * FIXME: relocation not yet working for coldfire, see below! - */ -xilinx_spartan3_slave_serial_fns xilinx_fns = { - xilinx_pre_config_fn, - xilinx_pgm_config_fn, - xilinx_clk_config_fn, - xilinx_init_config_fn, - xilinx_done_config_fn, - xilinx_wr_config_fn, - 0, - xilinx_fastwr_config_fn -}; - -xilinx_desc xilinx_fpga[FPGA_COUNT] = { - {xilinx_spartan3, - slave_serial, - XILINX_XC3S4000_SIZE, - (void *)&xilinx_fns, - 0, - &spartan3_op} -}; - -/* Initialize the fpga. Return 1 on success, 0 on failure. */ -int astro5373l_xilinx_load(void) -{ - int i; - - fpga_init(); - - for (i = 0; i < FPGA_COUNT; i++) { - /* - * I did not yet manage to get relocation work properly, - * so set stuff here instead of static initialisation: - */ - xilinx_fns.pre = xilinx_pre_config_fn; - xilinx_fns.pgm = xilinx_pgm_config_fn; - xilinx_fns.clk = xilinx_clk_config_fn; - xilinx_fns.init = xilinx_init_config_fn; - xilinx_fns.done = xilinx_done_config_fn; - xilinx_fns.wr = xilinx_wr_config_fn; - xilinx_fns.bwr = xilinx_fastwr_config_fn; - xilinx_fpga[i].iface_fns = (void *)&xilinx_fns; - fpga_add(fpga_xilinx, &xilinx_fpga[i]); - } - return 1; -} diff --git a/board/astro/mcf5373l/mcf5373l.c b/board/astro/mcf5373l/mcf5373l.c deleted file mode 100644 index 43fcbc65513..00000000000 --- a/board/astro/mcf5373l/mcf5373l.c +++ /dev/null @@ -1,201 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * modified by Wolfgang Wegner for ASTRO 5373l - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* needed for astro bus: */ -#include -#include "astro.h" - -DECLARE_GLOBAL_DATA_PTR; -extern void uart_port_conf(void); - -int checkboard(void) -{ - puts("Board: "); - puts("ASTRO MCF5373L (Urmel) Board\n"); - return 0; -} - -int dram_init(void) -{ -#if !defined(CONFIG_MONITOR_IS_IN_RAM) - sdram_t *sdp = (sdram_t *)(MMAP_SDRAM); - - /* - * GPIO configuration for bus should be set correctly from reset, - * so we do not care! First, set up address space: at this point, - * we should be running from internal SRAM; - * so use CFG_SYS_SDRAM_BASE as the base address for SDRAM, - * and do not care where it is - */ - __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018, - &sdp->cs0); - __raw_writel((CFG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000, - &sdp->cs1); - /* - * I am not sure from the data sheet, but it seems burst length - * has to be 8 for the 16 bit data bus we use; - * so these values are for BL = 8 - */ - __raw_writel(0x33211530, &sdp->cfg1); - __raw_writel(0x56570000, &sdp->cfg2); - /* send PrechargeALL, REF and IREF remain cleared! */ - __raw_writel(0xE1462C02, &sdp->ctrl); - udelay(1); - /* refresh SDRAM twice */ - __raw_writel(0xE1462C04, &sdp->ctrl); - udelay(1); - __raw_writel(0xE1462C04, &sdp->ctrl); - /* init MR */ - __raw_writel(0x008D0000, &sdp->mode); - /* initialize EMR */ - __raw_writel(0x80010000, &sdp->mode); - /* wait until DLL is locked */ - udelay(1); - /* - * enable automatic refresh, lock mode register, - * clear iref and ipall - */ - __raw_writel(0x71462C00, &sdp->ctrl); - /* Dummy write to start SDRAM */ - writel(0, CFG_SYS_SDRAM_BASE); -#endif - - /* - * for get_ram_size() to work, both CS areas have to be - * configured, i.e. CS1 has to be explicitely disabled, else - * probing for memory will cause the SDRAM bus to hang! - * (Do not rely on the SDCS register(s) being set to 0x00000000 - * during reset as stated in the data sheet.) - */ - gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, - 0x80000000 - CFG_SYS_SDRAM_BASE); - - return 0; -} - -#define UART_BASE MMAP_UART0 -int rs_serial_init(int port, int baud) -{ - uart_t *uart; - u32 counter; - - switch (port) { - case 0: - uart = (uart_t *)(MMAP_UART0); - break; - case 1: - uart = (uart_t *)(MMAP_UART1); - break; - case 2: - uart = (uart_t *)(MMAP_UART2); - break; - default: - uart = (uart_t *)(MMAP_UART0); - } - - uart_port_conf(); - - /* write to SICR: SIM2 = uart mode,dcd does not affect rx */ - writeb(UART_UCR_RESET_RX, &uart->ucr); - writeb(UART_UCR_RESET_TX, &uart->ucr); - writeb(UART_UCR_RESET_ERROR, &uart->ucr); - writeb(UART_UCR_RESET_MR, &uart->ucr); - __asm__ ("nop"); - - writeb(0, &uart->uimr); - - /* write to CSR: RX/TX baud rate from timers */ - writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr); - - writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr); - writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr); - - /* Setting up BaudRate */ - counter = (u32) (gd->bus_clk / (baud)); - counter >>= 5; - - /* write to CTUR: divide counter upper byte */ - writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1); - /* write to CTLR: divide counter lower byte */ - writeb((u8) (counter & 0x00ff), &uart->ubg2); - - writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); - - return 0; -} - -void astro_put_char(char ch) -{ - uart_t *uart; - unsigned long timer; - - uart = (uart_t *)(MMAP_UART0); - /* - * Wait for last character to go. Timeout of 6ms should - * be enough for our lowest baud rate of 2400. - */ - timer = get_timer(0); - while (get_timer(timer) < 6) { - if (readb(&uart->usr) & UART_USR_TXRDY) - break; - } - writeb(ch, &uart->utb); - - return; -} - -int astro_is_char(void) -{ - uart_t *uart; - - uart = (uart_t *)(MMAP_UART0); - return readb(&uart->usr) & UART_USR_RXRDY; -} - -int astro_get_char(void) -{ - uart_t *uart; - - uart = (uart_t *)(MMAP_UART0); - while (!(readb(&uart->usr) & UART_USR_RXRDY)) ; - return readb(&uart->urb); -} - -int misc_init_r(void) -{ - int retval = 0; - - puts("Configure Xilinx FPGA..."); - retval = astro5373l_xilinx_load(); - if (!retval) { - puts("failed!\n"); - return retval; - } - puts("done\n"); - - puts("Configure Altera FPGA..."); - retval = astro5373l_altera_load(); - if (!retval) { - puts("failed!\n"); - return retval; - } - puts("done\n"); - - return retval; -} diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig deleted file mode 100644 index 8dd369d68a1..00000000000 --- a/configs/astro_mcf5373l_defconfig +++ /dev/null @@ -1,51 +0,0 @@ -CONFIG_M68K=y -CONFIG_TEXT_BASE=0x00000000 -CONFIG_SYS_MALLOC_LEN=0x20000 -CONFIG_ENV_SIZE=0x8000 -CONFIG_ENV_SECT_SIZE=0x8000 -CONFIG_DEFAULT_DEVICE_TREE="astro_mcf5373l" -CONFIG_SYS_MONITOR_LEN=262144 -CONFIG_SYS_LOAD_ADDR=0x20000 -CONFIG_ENV_ADDR=0x1FF8000 -CONFIG_TARGET_ASTRO_MCF5373L=y -CONFIG_SYS_MONITOR_BASE=0x00000400 -CONFIG_BOOTDELAY=1 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS=" console=ttyS2,115200 rootfstype=romfs loaderversion=$loaderversion" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="protect off 0x80000 0x1ffffff;run env_check;run xilinxload&&run alteraload&&bootm 0x80000;update;reset" -CONFIG_SYS_PBSIZE=281 -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_MISC_INIT_R=y -CONFIG_SYS_MALLOC_BOOTPARAMS=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="URMEL > " -CONFIG_CMD_IMLS=y -CONFIG_CMD_FPGA_LOADMK=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_CACHE=y -CONFIG_CMD_JFFS2=y -CONFIG_NO_NET=y -CONFIG_FPGA_ALTERA=y -CONFIG_FPGA_CYCLON2=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_SPARTAN3=y -CONFIG_SYS_FPGA_PROG_FEEDBACK=y -CONFIG_DM_I2C=y -CONFIG_SYS_I2C_FSL=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_FLASH_SHOW_PROGRESS=0 -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_PROTECTION=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SYS_MAX_FLASH_SECT=259 -CONFIG_DM_RTC=y -CONFIG_MCFRTC=y -CONFIG_SYS_MCFRTC_BASE=0xFC0A8000 -CONFIG_MCFUART=y -CONFIG_WDT=y -CONFIG_WDT_MCF=y diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h deleted file mode 100644 index 65224324fbc..00000000000 --- a/include/configs/astro_mcf5373l.h +++ /dev/null @@ -1,187 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the Sentec Cobra Board. - * - * (C) Copyright 2003 Josef Baumgartner - */ - -/* - * configuration for ASTRO "Urmel" board. - * Originating from Cobra5272 configuration, messed up by - * Wolfgang Wegner - * Please do not bother the original author with bug reports - * concerning this file. - */ - -#ifndef _CONFIG_ASTRO_MCF5373L_H -#define _CONFIG_ASTRO_MCF5373L_H - -#include - -/* - * set the card type to actually compile for; either of - * the possibilities listed below has to be used! - */ -#define ASTRO_V532 1 - -#if ASTRO_V532 -#define ASTRO_ID 0xF8 -#elif ASTRO_V512 -#define ASTRO_ID 0xFA -#elif ASTRO_TWIN7S2 -#define ASTRO_ID 0xF9 -#elif ASTRO_V912 -#define ASTRO_ID 0xFC -#elif ASTRO_COFDMDUOS2 -#define ASTRO_ID 0xFB -#else -#error No card type defined! -#endif - -/* I2C */ - -/* - * Defines processor clock - important for correct timings concerning serial - * interface etc. - */ - -#define CFG_SYS_CLK 80000000 -#define CFG_SYS_CPU_CLK (CFG_SYS_CLK * 3) -#define CFG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ - -/* - * Define baudrate for UART1 (console output, tftp, ...) - * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud - * CFG_SYS_BAUDRATE_TABLE defines values that can be selected - * in u-boot command interface - */ - -#define CFG_SYS_UART_PORT (2) -#define CFG_SYS_UART2_ALT3_GPIO - -/* here we put our FPGA configuration... */ - -/* Define user parameters that have to be customized most likely */ - -/* AUTOBOOT settings - booting images automatically by u-boot after power on */ - -/* - * The following settings will be contained in the environment block ; if you - * want to use a neutral environment all those settings can be manually set in - * u-boot: 'set' command - */ - -#define CFG_EXTRA_ENV_SETTINGS \ - "loaderversion=11\0" \ - "card_id="__stringify(ASTRO_ID)"\0" \ - "alterafile=0\0" \ - "xilinxfile=0\0" \ - "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\ - "fpga load 0 0x41000000 $filesize\0" \ - "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\ - "fpga load 1 0x41000000 $filesize\0" \ - "env_default=1\0" \ - "env_check=if test $env_default -eq 1;"\ - " then setenv env_default 0;saveenv;fi\0" - -/* - * "update" is a non-standard command that has to be supplied - * by external update.c; This is not included in mainline because - * it needs non-blocking CFI routines. - */ - -#define CFG_SYS_FPGA_WAIT 1000 - -/* End of user parameters to be customized */ - -/* Defines memory range for test */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/* Base register address */ - -#define CFG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ - -/* System Conf. Reg. & System Protection Reg. */ - -#define CFG_SYS_SCR 0x0003; -#define CFG_SYS_SPR 0xffff; - -/* - * Definitions for initial stack pointer and data area (in internal SRAM) - */ -#define CFG_SYS_INIT_RAM_ADDR 0x80000000 -#define CFG_SYS_INIT_RAM_SIZE 0x8000 -#define CFG_SYS_INIT_RAM_CTRL 0x221 - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 - */ -#define CFG_SYS_SDRAM_BASE 0x40000000 - -/* - * Chipselect bank definitions - * - * CS0 - Flash 32MB (first 16MB) - * CS1 - Flash 32MB (second half) - * CS2 - FPGA - * CS3 - FPGA - * CS4 - unused - * CS5 - unused - */ -#define CFG_SYS_CS0_BASE 0 -#define CFG_SYS_CS0_MASK 0x00ff0001 -#define CFG_SYS_CS0_CTRL 0x00001fc0 - -#define CFG_SYS_CS1_BASE 0x01000000 -#define CFG_SYS_CS1_MASK 0x00ff0001 -#define CFG_SYS_CS1_CTRL 0x00001fc0 - -#define CFG_SYS_CS2_BASE 0x20000000 -#define CFG_SYS_CS2_MASK 0x00ff0001 -#define CFG_SYS_CS2_CTRL 0x0000fec0 - -#define CFG_SYS_CS3_BASE 0x21000000 -#define CFG_SYS_CS3_MASK 0x00ff0001 -#define CFG_SYS_CS3_CTRL 0x0000fec0 - -#define CFG_SYS_FLASH_BASE 0x00000000 - -/* Reserve 256 kB for Monitor */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + \ - (CFG_SYS_SDRAM_SIZE << 20)) - -/* FLASH organization */ - -#define CFG_SYS_FLASH_SIZE 0x2000000 - -#define LDS_BOARD_TEXT \ - . = DEFINED(env_offset) ? env_offset : .; \ - env/embedded.o(.text*) - -/* Cache Configuration */ - -#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ - CFG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \ - CFG_SYS_INIT_RAM_SIZE - 4) -#define CFG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CFG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ - CF_CACR_DCM_P) - -#endif /* _CONFIG_ASTRO_MCF5373L_H */ -- cgit v1.3.1 From b56c0632ad62415a40216d6f4de850e870163a6f Mon Sep 17 00:00:00 2001 From: Ilias Apalodimas Date: Wed, 18 Jun 2025 09:58:12 +0300 Subject: nxp: Prepare macros for KVM changes A following patch is replacing our IO accessors with do { ... } while(0) ones in order to make them usable with KVM. That leads to an error eventually looking like this: arch/arm/include/asm/io.h:62:9: error: expected expression before 'do' 62 | do { \ | ^~ arch/arm/include/asm/io.h:211:41: note: in expansion of macro '__raw_writel' 211 | #define out_arch(type,endian,a,v) __raw_write##type(cpu_to_##endian(v),a) | ^~~~~~~~~~~ arch/arm/include/asm/io.h:223:25: note: in expansion of macro 'out_arch' 223 | #define out_be32(a,v) out_arch(l,be32,a,v) | ^~~~~~~~ drivers/spi/fsl_dspi.c:127:17: note: in expansion of macro 'out_be32' 127 | out_be32(addr, val) : out_le32(addr, val); | ^~~~~~~~ So adjust the current macros and code to be compatible with the upcoming change. Signed-off-by: Ilias Apalodimas Reviewed-by: Tom Rini --- drivers/spi/fsl_dspi.c | 6 ++++-- include/fsl_ifc.h | 24 ++++++++++++------------ 2 files changed, 16 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index f2393c041f4..545561ad116 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -123,8 +123,10 @@ static uint dspi_read32(uint flags, uint *addr) static void dspi_write32(uint flags, uint *addr, uint val) { - flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? - out_be32(addr, val) : out_le32(addr, val); + if (flags & DSPI_FLAG_REGMAP_ENDIAN_BIG) + out_be32(addr, val); + else + out_le32(addr, val); } static void dspi_halt(struct fsl_dspi_priv *priv, u8 halt) diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index 3ac22687930..1c363115beb 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -803,29 +803,29 @@ void init_final_memctl_regs(void); ((struct fsl_ifc_fcm *)CFG_SYS_IFC_ADDR) #define get_ifc_cspr_ext(i) \ - (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext)) + ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext) #define get_ifc_cspr(i) \ - (ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr)) + ifc_in32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr) #define get_ifc_csor_ext(i) \ - (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext)) + ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext) #define get_ifc_csor(i) \ - (ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor)) + ifc_in32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor) #define get_ifc_amask(i) \ - (ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask)) + ifc_in32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask) #define get_ifc_ftim(i, j) \ - (ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j])) + ifc_in32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j]) #define set_ifc_cspr_ext(i, v) \ - (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v)) + ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr_ext, v) #define set_ifc_cspr(i, v) \ - (ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v)) + ifc_out32(&(IFC_FCM_BASE_ADDR)->cspr_cs[i].cspr, v) #define set_ifc_csor_ext(i, v) \ - (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v)) + ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor_ext, v) #define set_ifc_csor(i, v) \ - (ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v)) + ifc_out32(&(IFC_FCM_BASE_ADDR)->csor_cs[i].csor, v) #define set_ifc_amask(i, v) \ - (ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v)) + ifc_out32(&(IFC_FCM_BASE_ADDR)->amask_cs[i].amask, v) #define set_ifc_ftim(i, j, v) \ - (ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v)) + ifc_out32(&(IFC_FCM_BASE_ADDR)->ftim_cs[i].ftim[j], v) enum ifc_chip_sel { IFC_CS0, -- cgit v1.3.1 From 1fde88de1609a046285675ab76e8ecd3e7792b2b Mon Sep 17 00:00:00 2001 From: Andrew Goodbody Date: Mon, 30 Jun 2025 11:23:39 +0100 Subject: cmd: tpm: Fix attempt to return value not in enum The function tpm2_name_to_algorithm is defined as returning an enum for the algorithm specified but it also attempts to return an error on failure, but that error is not included in the enum. Add the error to the enum so that it can be returned. This issue was reported by Smatch. Signed-off-by: Andrew Goodbody Reviewed-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- include/tpm-v2.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/tpm-v2.h b/include/tpm-v2.h index ece422df0c7..f3eb2ef5643 100644 --- a/include/tpm-v2.h +++ b/include/tpm-v2.h @@ -20,6 +20,7 @@ #define __TPM_V2_H #include +#include struct udevice; @@ -266,6 +267,7 @@ enum tpm2_return_codes { * TPM2 algorithms. */ enum tpm2_algorithms { + TPM2_ALG_INVAL = -EINVAL, TPM2_ALG_SHA1 = 0x04, TPM2_ALG_XOR = 0x0A, TPM2_ALG_SHA256 = 0x0B, -- cgit v1.3.1 From f517d93842ad733d8df485d8255a3649c8ac517a Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 19 Jun 2025 10:34:00 +0200 Subject: disk: efi: expose the part_get_gpt_pte() helper function This function will be used by the EFI application disk support code to provide data required by the EFI_PARTITION_INFORMATION_PROTOCOL. Signed-off-by: Javier Martinez Canillas Reviewed-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- disk/part_efi.c | 2 +- include/part.h | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/disk/part_efi.c b/disk/part_efi.c index d0b1f96adff..fb1ed534f86 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -215,7 +215,7 @@ int get_disk_guid(struct blk_desc *desc, char *guid) return 0; } -static int part_get_gpt_pte(struct blk_desc *desc, int part, gpt_entry *gpt_e) +int part_get_gpt_pte(struct blk_desc *desc, int part, gpt_entry *gpt_e) { ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, desc->blksz); gpt_entry *gpt_pte = NULL; diff --git a/include/part.h b/include/part.h index 7075b2cb116..b3a3362b2af 100644 --- a/include/part.h +++ b/include/part.h @@ -647,6 +647,20 @@ int gpt_verify_partitions(struct blk_desc *desc, */ int get_disk_guid(struct blk_desc *desc, char *guid); +/** + * part_get_gpt_pte() - Get the GPT partition table entry of a partition + * + * This function reads the GPT partition table entry (PTE) for a given + * block device and partition number. + * + * @desc: block device descriptor + * @part: partition number for which to return the PTE + * @gpt_e: GPT partition table entry + * + * Return: 0 on success, otherwise error + */ +int part_get_gpt_pte(struct blk_desc *desc, int part, gpt_entry *gpt_e); + #endif #if CONFIG_IS_ENABLED(DOS_PARTITION) -- cgit v1.3.1 From 2fdfb802e30a1fbd65a830a283d7bd87631f08c0 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 19 Jun 2025 10:34:01 +0200 Subject: efi_loader: disk: add EFI_PARTITION_INFO_PROTOCOL support The UEFI 2.10 specification mentions that this protocol shall be installed along with EFI_BLOCK_IO_PROTOCOL. It provides cached partition information for MBR and GPT partition types. This patch just implements support for GPT partition types. The legacy MBR partition types is only needed for backward compatibility and can be added as a follow-up if needed, to make it fully compliant with the EFI spec. Signed-off-by: Javier Martinez Canillas Reviewed-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- include/part_efi.h | 20 ++++++++++++++++++++ lib/efi_loader/efi_disk.c | 39 +++++++++++++++++++++++++++++++++++++-- 2 files changed, 57 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/part_efi.h b/include/part_efi.h index 59b7895b8a2..fb402df6f13 100644 --- a/include/part_efi.h +++ b/include/part_efi.h @@ -138,4 +138,24 @@ typedef struct _legacy_mbr { __le16 signature; } __packed legacy_mbr; +#define EFI_PARTITION_INFO_PROTOCOL_GUID \ + EFI_GUID(0x8cf2f62c, 0xbc9b, 0x4821, 0x80, \ + 0x8d, 0xec, 0x9e, 0xc4, 0x21, 0xa1, 0xa0) + +#define EFI_PARTITION_INFO_PROTOCOL_REVISION 0x0001000 +#define PARTITION_TYPE_OTHER 0x00 +#define PARTITION_TYPE_MBR 0x01 +#define PARTITION_TYPE_GPT 0x02 + +struct efi_partition_info { + u32 revision; + u32 type; + u8 system; + u8 reserved[7]; + union { + struct partition mbr; + gpt_entry gpt; + } info; +} __packed; + #endif /* _DISK_PART_EFI_H */ diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c index 47b583cc5e1..130c4db9606 100644 --- a/lib/efi_loader/efi_disk.c +++ b/lib/efi_loader/efi_disk.c @@ -26,6 +26,7 @@ struct efi_system_partition efi_system_partition = { const efi_guid_t efi_block_io_guid = EFI_BLOCK_IO_PROTOCOL_GUID; const efi_guid_t efi_system_partition_guid = PARTITION_SYSTEM_GUID; +const efi_guid_t efi_partition_info_guid = EFI_PARTITION_INFO_PROTOCOL_GUID; /** * struct efi_disk_obj - EFI disk object @@ -35,6 +36,7 @@ const efi_guid_t efi_system_partition_guid = PARTITION_SYSTEM_GUID; * @media: block I/O media information * @dp: device path to the block device * @volume: simple file system protocol of the partition + * @info: EFI partition info protocol interface */ struct efi_disk_obj { struct efi_object header; @@ -42,6 +44,7 @@ struct efi_disk_obj { struct efi_block_io_media media; struct efi_device_path *dp; struct efi_simple_file_system_protocol *volume; + struct efi_partition_info info; }; /** @@ -426,6 +429,7 @@ static efi_status_t efi_disk_add_dev( /* Fill in object data */ if (part_info) { struct efi_device_path *node = efi_dp_part_node(desc, part); + struct efi_partition_info *info = &diskobj->info; struct efi_handler *handler; void *protocol_interface; @@ -454,18 +458,48 @@ static efi_status_t efi_disk_add_dev( goto error; } + info->revision = EFI_PARTITION_INFO_PROTOCOL_REVISION; + + switch (desc->part_type) { +#if CONFIG_IS_ENABLED(EFI_PARTITION) + case PART_TYPE_EFI: + info->type = PARTITION_TYPE_GPT; + ret = part_get_gpt_pte(desc, part, &info->info.gpt); + if (ret) { + log_debug("get PTE for part %d failed %ld\n", + part, ret); + goto error; + } + break; +#endif +#if CONFIG_IS_ENABLED(DOS_PARTITION) + case PART_TYPE_DOS: + info->type = PARTITION_TYPE_MBR; + + /* TODO: implement support for MBR partition types */ + log_debug("EFI_PARTITION_INFO_PROTOCOL doesn't support MBR\n"); + break; +#endif + default: + info->type = PARTITION_TYPE_OTHER; + break; + } + diskobj->dp = efi_dp_append_node(dp_parent, node); efi_free_pool(node); diskobj->media.last_block = part_info->size - 1; - if (part_info->bootable & PART_EFI_SYSTEM_PARTITION) + if (part_info->bootable & PART_EFI_SYSTEM_PARTITION) { esp_guid = &efi_system_partition_guid; + info->system = 1; + } + } else { diskobj->dp = efi_dp_from_part(desc, part); diskobj->media.last_block = desc->lba - 1; } /* - * Install the device path and the block IO protocol. + * Install the device path, the block IO and partition info protocols. * * InstallMultipleProtocolInterfaces() checks if the device path is * already installed on an other handle and returns EFI_ALREADY_STARTED @@ -476,6 +510,7 @@ static efi_status_t efi_disk_add_dev( &handle, &efi_guid_device_path, diskobj->dp, &efi_block_io_guid, &diskobj->ops, + &efi_partition_info_guid, &diskobj->info, /* * esp_guid must be last entry as it * can be NULL. Its interface is NULL. -- cgit v1.3.1 From ed004a260acdb196c8f36dffdb4c3b428f215616 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Thu, 3 Jul 2025 12:13:07 +0530 Subject: cmd: eficonfig: add support for URI device path based boot options The eficonfig command provides a menu based interface for maintenance of the EFI boot options. Add support for adding a URI based boot option. This boot option can then be used for HTTP boot. Signed-off-by: Sughosh Ganu Reviewed-by: Ilias Apalodimas Tested-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- cmd/eficonfig.c | 146 ++++++++++++++++++++++++++++++++++++++++++++++++--- include/efi_config.h | 2 + 2 files changed, 140 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c index 6e14d34a6bd..8ac0fb98e02 100644 --- a/cmd/eficonfig.c +++ b/cmd/eficonfig.c @@ -35,6 +35,7 @@ static int avail_row; #define EFICONFIG_DESCRIPTION_MAX 32 #define EFICONFIG_OPTIONAL_DATA_MAX 64 +#define EFICONFIG_URI_MAX 512 #define EFICONFIG_MENU_HEADER_ROW_NUM 3 #define EFICONFIG_MENU_DESC_ROW_NUM 5 @@ -538,6 +539,40 @@ struct efi_device_path *eficonfig_create_device_path(struct efi_device_path *dp_ return dp; } +/** + * eficonfig_create_uri_device_path() - Create an URI based device path + * @uri_str: URI string to be added to the device path + * + * Take the u16 string, convert it to a u8 string, and create a URI + * device path. This will be used for the EFI HTTP boot. + * + * Return: pointer to the URI device path on success, NULL on failure + */ +static struct efi_device_path *eficonfig_create_uri_device_path(u16 *uri_str) +{ + char *pos, *p; + u32 len = 0; + efi_uintn_t uridp_len; + struct efi_device_path_uri *uridp; + + len = utf16_utf8_strlen(uri_str); + + uridp_len = sizeof(struct efi_device_path) + len + 1; + uridp = efi_alloc(uridp_len + sizeof(EFI_DP_END)); + if (!uridp) + return NULL; + + uridp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE; + uridp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_URI; + uridp->dp.length = uridp_len; + p = (char *)&uridp->uri; + utf16_utf8_strcpy(&p, uri_str); + pos = (char *)uridp + uridp_len; + memcpy(pos, &EFI_DP_END, sizeof(EFI_DP_END)); + + return &uridp->dp; +} + /** * eficonfig_file_selected() - handler of file selection * @@ -983,6 +1018,22 @@ static efi_status_t eficonfig_boot_add_optional_data(void *data) " enter optional data:"); } +/** + * eficonfig_boot_add_uri() - handle user input for HTTP Boot URI + * + * @data: pointer to the internal boot option structure + * Return: status code + */ +static efi_status_t eficonfig_boot_add_uri(void *data) +{ + struct eficonfig_select_file_info *file_info = data; + + return handle_user_input(file_info->uri, EFICONFIG_URI_MAX, 24, + "\n ** Edit URI **\n" + "\n" + " enter HTTP Boot URI:"); +} + /** * eficonfig_boot_edit_save() - handler to save the boot option * @@ -998,7 +1049,8 @@ static efi_status_t eficonfig_boot_edit_save(void *data) bo->edit_completed = false; return EFI_NOT_READY; } - if (u16_strlen(bo->file_info.current_path) == 0) { + if (u16_strlen(bo->file_info.current_path) == 0 && + u16_strlen(bo->file_info.uri) == 0) { eficonfig_print_msg("File is not selected!"); bo->edit_completed = false; return EFI_NOT_READY; @@ -1024,9 +1076,19 @@ efi_status_t eficonfig_process_clear_file_selection(void *data) file_info->current_path[0] = u'\0'; file_info->dp_volume = NULL; + if (file_info->uri) + file_info->uri[0] = u'\0'; + return EFI_ABORTED; } +static struct eficonfig_item select_boot_file_menu_items[] = { + {"Select File", eficonfig_process_select_file}, + {"Enter URI", eficonfig_boot_add_uri}, + {"Clear", eficonfig_process_clear_file_selection}, + {"Quit", eficonfig_process_quit}, +}; + static struct eficonfig_item select_file_menu_items[] = { {"Select File", eficonfig_process_select_file}, {"Clear", eficonfig_process_clear_file_selection}, @@ -1042,16 +1104,30 @@ static struct eficonfig_item select_file_menu_items[] = { efi_status_t eficonfig_process_show_file_option(void *data) { efi_status_t ret; + unsigned int menu_count; struct efimenu *efi_menu; + struct eficonfig_item *menu_items; + struct eficonfig_select_file_info *file_info = data; + + menu_items = file_info->uri ? select_boot_file_menu_items : + select_file_menu_items; + + menu_count = file_info->uri ? + ARRAY_SIZE(select_boot_file_menu_items) : + ARRAY_SIZE(select_file_menu_items); + + menu_items[0].data = data; + menu_items[1].data = data; + menu_items[2].data = data; - select_file_menu_items[0].data = data; - select_file_menu_items[1].data = data; - efi_menu = eficonfig_create_fixed_menu(select_file_menu_items, - ARRAY_SIZE(select_file_menu_items)); + efi_menu = eficonfig_create_fixed_menu(menu_items, menu_count); if (!efi_menu) return EFI_OUT_OF_RESOURCES; - ret = eficonfig_process_common(efi_menu, " ** Update File **", + ret = eficonfig_process_common(efi_menu, + file_info->uri ? + " ** Update File/URI **" : + " ** Update File **", eficonfig_menu_desc, eficonfig_display_statusline, eficonfig_print_entry, @@ -1121,6 +1197,14 @@ out: file_info->current_path[len] = u'\0'; file_info->current_volume = tmp->current_volume; file_info->dp_volume = tmp->dp_volume; + + /* + * File being selected, set the URI string to + * null so that the file gets picked as the + * boot image. + */ + if (file_info->uri) + file_info->uri[0] = u'\0'; } list_for_each_safe(pos, n, &tmp->filepath_list) { @@ -1224,6 +1308,12 @@ static efi_status_t prepare_file_selection_entry(struct efimenu *efi_menu, char efi_handle_t handle; char *devname; + /* Check for URI based boot file */ + if (file_info->uri && utf16_utf8_strlen(file_info->uri)) + return create_boot_option_entry(efi_menu, title, file_info->uri, + eficonfig_process_show_file_option, + file_info); + devname = calloc(1, EFICONFIG_VOLUME_PATH_MAX + 1); if (!devname) return EFI_OUT_OF_RESOURCES; @@ -1340,6 +1430,27 @@ out: return ret; } +/** + * fill_dp_uri() - copy the URI string in the device path + * @dp: pointer to the URI device path + * @uri_str: URI string to be copied + * + * Copy the passed URI string to the URI device path. This + * requires utf8_utf16_strcpy() to copy the u16 string to + * the u8 array in the device path structure. + * + * Return: None + */ +static void fill_dp_uri(struct efi_device_path *dp, u16 **uri_str) +{ + u16 *p = *uri_str; + struct efi_device_path_uri *uridp; + + uridp = (struct efi_device_path_uri *)dp; + + utf8_utf16_strcpy(&p, uridp->uri); +} + /** * fill_file_info() - fill the file info from efi_device_path structure * @@ -1392,10 +1503,13 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo size_t len; efi_status_t ret; char *tmp = NULL, *p; + u16 *current_path = NULL; struct efi_load_option lo = {0}; efi_uintn_t dp_size; struct efi_device_path *dp = NULL; efi_uintn_t size = load_option_size; + struct efi_device_path *dp_volume = NULL; + struct efi_device_path *uri_dp = NULL; struct efi_device_path *device_dp = NULL; struct efi_device_path *initrd_dp = NULL; struct efi_device_path *fdt_dp = NULL; @@ -1464,6 +1578,12 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo goto out; } + bo->file_info.uri = calloc(1, EFICONFIG_URI_MAX * sizeof(u16)); + if (!bo->file_info.uri) { + ret = EFI_OUT_OF_RESOURCES; + goto out; + } + /* copy the preset value */ if (load_option) { ret = efi_deserialize_load_option(&lo, load_option, &size); @@ -1481,7 +1601,10 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo u16_strcpy(bo->description, lo.label); /* EFI image file path is a first instance */ - if (lo.file_path) + if (lo.file_path && EFI_DP_TYPE(lo.file_path, MESSAGING_DEVICE, + MSG_URI)) + fill_dp_uri(lo.file_path, &bo->file_info.uri); + else if (lo.file_path) fill_file_info(lo.file_path, &bo->file_info, device_dp); /* Initrd file path (optional) is placed at second instance. */ @@ -1512,6 +1635,9 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo goto out; } + if (utf16_utf8_strlen(bo->file_info.uri)) + uri_dp = eficonfig_create_uri_device_path(bo->file_info.uri); + if (bo->initrd_info.dp_volume) { dp = eficonfig_create_device_path(bo->initrd_info.dp_volume, bo->initrd_info.current_path); @@ -1536,7 +1662,10 @@ static efi_status_t eficonfig_edit_boot_option(u16 *varname, struct eficonfig_bo efi_free_pool(dp); } - dp = eficonfig_create_device_path(bo->file_info.dp_volume, bo->file_info.current_path); + dp_volume = bo->file_info.dp_volume; + current_path = bo->file_info.current_path; + dp = uri_dp ? + uri_dp : eficonfig_create_device_path(dp_volume, current_path); if (!dp) { ret = EFI_OUT_OF_RESOURCES; goto out; @@ -1560,6 +1689,7 @@ out: free(tmp); free(bo->optional_data); free(bo->description); + free(bo->file_info.uri); free(bo->file_info.current_path); free(bo->initrd_info.current_path); free(bo->fdt_info.current_path); diff --git a/include/efi_config.h b/include/efi_config.h index d7c1601137e..23211e799fc 100644 --- a/include/efi_config.h +++ b/include/efi_config.h @@ -82,6 +82,7 @@ struct eficonfig_item { * @current_volume: pointer to the efi_simple_file_system_protocol * @dp_volume: pointer to device path of the selected device * @current_path: pointer to the selected file path string + * @uri: URI for HTTP Boot * @filepath_list: list_head structure for file path list * @file_selectred: flag indicates file selecting status */ @@ -89,6 +90,7 @@ struct eficonfig_select_file_info { struct efi_simple_file_system_protocol *current_volume; struct efi_device_path *dp_volume; u16 *current_path; + u16 *uri; struct list_head filepath_list; bool file_selected; }; -- cgit v1.3.1 From aaf7be96c2c14aa190d39e50fa3606389eafda8e Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Thu, 3 Jul 2025 07:28:07 +0100 Subject: efi: add EFI_SYSTEM_TABLE_POINTER for debug Add EFI_SYSTEM_TABLE_POINTER structure for remote debugger to locate the address of EFI_SYSTEM_TABLE. This feature is described in UEFI SPEC version 2.10. Section 18.4.2. The implementation ensures support for hardware-assisted debugging and provides a standardized mechanism for debuggers to discover the EFI system table. Cc: Peter Robinson Cc: Simon Glass Signed-off-by: Ying-Chun Liu (PaulLiu) Reviewed-by: Ilias Apalodimas Tested-by: Heinrich Schuchardt Reviewed-by: Heinrich Schuchardt # change memset(systab_pointer, 0 ...) -> systab_pointer->crc32 = 0; Signed-off-by: Ilias Apalodimas --- include/efi_api.h | 16 +++++++++++++++ include/efi_loader.h | 2 ++ lib/efi_loader/Kconfig | 9 +++++++++ lib/efi_loader/Makefile | 1 + lib/efi_loader/efi_debug_support.c | 40 ++++++++++++++++++++++++++++++++++++++ lib/efi_loader/efi_setup.c | 7 +++++++ 6 files changed, 75 insertions(+) create mode 100644 lib/efi_loader/efi_debug_support.c (limited to 'include') diff --git a/include/efi_api.h b/include/efi_api.h index eb61eafa028..6c4c1a0cc7b 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -259,6 +259,22 @@ struct efi_capsule_result_variable_header { efi_status_t capsule_status; } __packed; +/** + * struct efi_system_table_pointer - struct to store the pointer of system + * table. + * @signature: The signature of this struct. + * @efi_system_table_base: The physical address of System Table. + * @crc32: CRC32 checksum + * + * This struct is design for hardware debugger to search through memory to + * get the address of EFI System Table. + */ +struct efi_system_table_pointer { + u64 signature; + efi_physical_addr_t efi_system_table_base; + u32 crc32; +}; + struct efi_memory_range { efi_physical_addr_t address; u64 length; diff --git a/include/efi_loader.h b/include/efi_loader.h index 8fd09aad2d0..ada29a5bad3 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -643,6 +643,8 @@ efi_status_t efi_tcg2_measure_dtb(void *dtb); efi_status_t efi_root_node_register(void); /* Called by bootefi to initialize runtime */ efi_status_t efi_initialize_system_table(void); +/* Called by bootefi to initialize debug */ +efi_status_t efi_initialize_system_table_pointer(void); /* efi_runtime_detach() - detach unimplemented runtime functions */ void efi_runtime_detach(void); /* efi_convert_pointer() - convert pointer to virtual address */ diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 3dadbc54b58..077466f01f0 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -71,6 +71,15 @@ config EFI_SECURE_BOOT config EFI_SIGNATURE_SUPPORT bool +config EFI_DEBUG_SUPPORT + bool "EFI Debug Support" + default y if !HAS_BOARD_SIZE_LIMIT + help + Select this option if you want to setup the EFI Debug Support + Table and the EFI_SYSTEM_TABLE_POINTER which is used by the debug + agent or an external debugger to determine loaded image information + in a quiescent manner. + menu "UEFI services" config EFI_GET_TIME diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index cf050e5385d..51ccf1cd87e 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -70,6 +70,7 @@ obj-$(CONFIG_EFI_RISCV_BOOT_PROTOCOL) += efi_riscv.o obj-$(CONFIG_EFI_LOAD_FILE2_INITRD) += efi_load_initrd.o obj-$(CONFIG_EFI_SIGNATURE_SUPPORT) += efi_signature.o obj-$(CONFIG_EFI_ECPT) += efi_conformance.o +obj-$(CONFIG_EFI_DEBUG_SUPPORT) += efi_debug_support.o EFI_VAR_SEED_FILE := $(subst $\",,$(CONFIG_EFI_VAR_SEED_FILE)) $(obj)/efi_var_seed.o: $(srctree)/$(EFI_VAR_SEED_FILE) diff --git a/lib/efi_loader/efi_debug_support.c b/lib/efi_loader/efi_debug_support.c new file mode 100644 index 00000000000..649d21ef829 --- /dev/null +++ b/lib/efi_loader/efi_debug_support.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * EFI debug support + * + * Copyright (c) 2025 Ying-Chun Liu, Linaro Ltd. + */ + +#include +#include +#include + +struct efi_system_table_pointer __efi_runtime_data * systab_pointer = NULL; + +/** + * efi_initialize_system_table_pointer() - Initialize system table pointer + * + * Return: status code + */ +efi_status_t efi_initialize_system_table_pointer(void) +{ + /* Allocate efi_system_table_pointer structure with 4MB alignment. */ + systab_pointer = efi_alloc_aligned_pages(sizeof(struct efi_system_table_pointer), + EFI_RUNTIME_SERVICES_DATA, + SZ_4M); + + if (!systab_pointer) { + log_err("Installing EFI system table pointer failed\n"); + return EFI_OUT_OF_RESOURCES; + } + + systab_pointer->crc32 = 0; + + systab_pointer->signature = EFI_SYSTEM_TABLE_SIGNATURE; + systab_pointer->efi_system_table_base = (uintptr_t)&systab; + systab_pointer->crc32 = crc32(0, + (const unsigned char *)systab_pointer, + sizeof(struct efi_system_table_pointer)); + + return EFI_SUCCESS; +} diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index 48f91da5df7..78c5059256a 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -278,6 +278,13 @@ efi_status_t efi_init_obj_list(void) if (ret != EFI_SUCCESS) goto out; + /* Initialize system table pointer */ + if (IS_ENABLED(CONFIG_EFI_DEBUG_SUPPORT)) { + ret = efi_initialize_system_table_pointer(); + if (ret != EFI_SUCCESS) + goto out; + } + if (IS_ENABLED(CONFIG_EFI_ECPT)) { ret = efi_ecpt_register(); if (ret != EFI_SUCCESS) -- cgit v1.3.1 From e7a85ec651ed5794eb9a837e1073f6b3146af501 Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Thu, 3 Jul 2025 07:28:08 +0100 Subject: efi: add EFI_DEBUG_IMAGE_INFO_TABLE for debug EFI_DEBUG_IMAGE_INFO_TABLE is used to store EFI_LOADED_IMAGE for debug purpose. This commit adds the table to the EFI_CONFIGURATION_TABLE. This feature is described in UEFI Spec version 2.10. Section 18.4. The implementation ensures support for hardware-assisted debugging and provides a standardized mechanism for debuggers to discover and interact with system-level debug resources. Cc: Heinrich Schuchardt Cc: Peter Robinson Cc: Simon Glass Signed-off-by: Ying-Chun Liu (PaulLiu) Reviewed-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- include/efi_api.h | 53 ++++++++++++++++++++++++++++++++++++++ include/efi_loader.h | 2 ++ lib/efi_loader/efi_debug_support.c | 6 +++++ lib/efi_loader/efi_setup.c | 11 ++++++++ 4 files changed, 72 insertions(+) (limited to 'include') diff --git a/include/efi_api.h b/include/efi_api.h index 6c4c1a0cc7b..8da0a350ce3 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -238,6 +238,10 @@ enum efi_reset_type { EFI_GUID(0xcce33c35, 0x74ac, 0x4087, 0xbc, 0xe7, \ 0x8b, 0x29, 0xb0, 0x2e, 0xeb, 0x27) +#define EFI_DEBUG_IMAGE_INFO_TABLE_GUID \ + EFI_GUID(0x49152e77, 0x1ada, 0x4764, 0xb7, 0xa2, \ + 0x7a, 0xfe, 0xfe, 0xd9, 0x5e, 0x8b) + struct efi_conformance_profiles_table { u16 version; u16 number_of_profiles; @@ -574,6 +578,55 @@ struct efi_loaded_image { efi_status_t (EFIAPI *unload)(efi_handle_t image_handle); }; +#define EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS 0x01 +#define EFI_DEBUG_IMAGE_INFO_TABLE_MODIFIED 0x02 + +/** + * struct efi_debug_image_info_normal - Store Debug Information for normal + * image. + * @image_info_type: the type of image info. + * @loaded_image_protocol_instance: the pointer to struct efi_loaded_image. + * @image_handle: the EFI handle of the image. + * + * This struct is created by efi_load_image() and store the information + * for debugging an normal image. + */ +struct efi_debug_image_info_normal { + u32 image_info_type; + struct efi_loaded_image *loaded_image_protocol_instance; + efi_handle_t image_handle; +}; + +/** + * union efi_debug_image_info - The union to store a pointer for EFI + * DEBUG IMAGE INFO. + * @image_info_type: the type of the image_info if it is not a normal image. + * @normal_image: The pointer to a normal image. + * + * This union is for a pointer that can point to the struct of normal_image. + * Or it points to an image_info_type. + */ +union efi_debug_image_info { + u32 *image_info_type; + struct efi_debug_image_info_normal *normal_image; +}; + +/** + * struct efi_debug_image_info_table_header - store the array of + * struct efi_debug_image_info. + * @update_status: Status to notify this struct is ready to use or not. + * @table_size: The number of elements of efi_debug_image_info_table. + * @efi_debug_image_info_table: The array of efi_debug_image_info. + * + * This struct stores the array of efi_debug_image_info. The + * number of elements is table_size. + */ +struct efi_debug_image_info_table_header { + volatile u32 update_status; + u32 table_size; + union efi_debug_image_info *efi_debug_image_info_table; +}; + #define EFI_DEVICE_PATH_PROTOCOL_GUID \ EFI_GUID(0x09576e91, 0x6d3f, 0x11d2, \ 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b) diff --git a/include/efi_loader.h b/include/efi_loader.h index ada29a5bad3..c02bc1b7ef4 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -312,6 +312,8 @@ extern const struct efi_hii_config_routing_protocol efi_hii_config_routing; extern const struct efi_hii_config_access_protocol efi_hii_config_access; extern const struct efi_hii_database_protocol efi_hii_database; extern const struct efi_hii_string_protocol efi_hii_string; +/* structure for EFI_DEBUG_SUPPORT_PROTOCOL */ +extern struct efi_debug_image_info_table_header efi_m_debug_info_table_header; uint16_t *efi_dp_str(struct efi_device_path *dp); diff --git a/lib/efi_loader/efi_debug_support.c b/lib/efi_loader/efi_debug_support.c index 649d21ef829..597592fbd1c 100644 --- a/lib/efi_loader/efi_debug_support.c +++ b/lib/efi_loader/efi_debug_support.c @@ -11,6 +11,12 @@ struct efi_system_table_pointer __efi_runtime_data * systab_pointer = NULL; +struct efi_debug_image_info_table_header efi_m_debug_info_table_header = { + 0, + 0, + NULL +}; + /** * efi_initialize_system_table_pointer() - Initialize system table pointer * diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c index 78c5059256a..f06cf49e443 100644 --- a/lib/efi_loader/efi_setup.c +++ b/lib/efi_loader/efi_setup.c @@ -18,6 +18,9 @@ efi_status_t efi_obj_list_initialized = OBJ_LIST_NOT_INITIALIZED; +const efi_guid_t efi_debug_image_info_table_guid = + EFI_DEBUG_IMAGE_INFO_TABLE_GUID; + /* * Allow unaligned memory access. * @@ -280,9 +283,17 @@ efi_status_t efi_init_obj_list(void) /* Initialize system table pointer */ if (IS_ENABLED(CONFIG_EFI_DEBUG_SUPPORT)) { + efi_guid_t debug_image_info_table_guid = + efi_debug_image_info_table_guid; + ret = efi_initialize_system_table_pointer(); if (ret != EFI_SUCCESS) goto out; + + ret = efi_install_configuration_table(&debug_image_info_table_guid, + &efi_m_debug_info_table_header); + if (ret != EFI_SUCCESS) + goto out; } if (IS_ENABLED(CONFIG_EFI_ECPT)) { -- cgit v1.3.1 From 3c08df58cc43c3ae8ec378ab0e32cfe548313c39 Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Thu, 3 Jul 2025 07:28:09 +0100 Subject: lib: efi_loader: efi_memory.c: add efi_realloc() for realloc memory Add efi_realloc() for realloc memory that previously alloc by efi_alloc(). Note that if realloced memory is explicitly allocated as BootServicesData. Cc: Heinrich Schuchardt Cc: Ilias Apalodimas Cc: Peter Robinson Cc: Simon Glass Signed-off-by: Ying-Chun Liu (PaulLiu) Reviewed-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- include/efi_loader.h | 10 ++++++++ lib/efi_loader/efi_memory.c | 58 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index c02bc1b7ef4..b60ea58d71f 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -875,6 +875,16 @@ efi_status_t efi_next_variable_name(efi_uintn_t *size, u16 **buf, #define efi_size_in_pages(size) (((size) + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT) /* Allocate boot service data pool memory */ void *efi_alloc(size_t len); +/** + * efi_realloc() - reallocate boot services data pool memory + * + * Reallocate memory from pool for a new size and copy the data from old one. + * + * @ptr: pointer to the buffer + * @size: number of bytes to allocate + * Return: EFI status to indicate success or not + */ +efi_status_t efi_realloc(void **ptr, size_t len); /* Allocate pages on the specified alignment */ void *efi_alloc_aligned_pages(u64 len, int memory_type, size_t align); /* More specific EFI memory allocator, called by EFI payloads */ diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c index 0828a47da61..6dfc698a247 100644 --- a/lib/efi_loader/efi_memory.c +++ b/lib/efi_loader/efi_memory.c @@ -668,6 +668,64 @@ void *efi_alloc(size_t size) return buf; } +/** + * efi_realloc() - reallocate boot services data pool memory + * + * Reallocate memory from pool for a new size and copy the data from old one. + * + * @ptr: pointer to old buffer + * @size: number of bytes to allocate + * Return: EFI status to indicate success or not + */ +efi_status_t efi_realloc(void **ptr, size_t size) +{ + efi_status_t ret; + void *new_ptr; + struct efi_pool_allocation *alloc; + u64 num_pages = efi_size_in_pages(size + + sizeof(struct efi_pool_allocation)); + size_t old_size; + + if (!*ptr) { + *ptr = efi_alloc(size); + if (*ptr) + return EFI_SUCCESS; + return EFI_OUT_OF_RESOURCES; + } + + ret = efi_check_allocated((uintptr_t)*ptr, true); + if (ret != EFI_SUCCESS) + return ret; + + alloc = container_of(*ptr, struct efi_pool_allocation, data); + + /* Check that this memory was allocated by efi_allocate_pool() */ + if (((uintptr_t)alloc & EFI_PAGE_MASK) || + alloc->checksum != checksum(alloc)) { + printf("%s: illegal realloc 0x%p\n", __func__, *ptr); + return EFI_INVALID_PARAMETER; + } + + /* Don't realloc. The actual size in pages is the same. */ + if (alloc->num_pages == num_pages) + return EFI_SUCCESS; + + old_size = alloc->num_pages * EFI_PAGE_SIZE - + sizeof(struct efi_pool_allocation); + + new_ptr = efi_alloc(size); + + /* copy old data to new alloced buffer */ + memcpy(new_ptr, *ptr, min(size, old_size)); + + /* free the old buffer */ + efi_free_pool(*ptr); + + *ptr = new_ptr; + + return EFI_SUCCESS; +} + /** * efi_free_pool() - free memory from pool * -- cgit v1.3.1 From 146546138af5966c97619797dc7f879c4857b00d Mon Sep 17 00:00:00 2001 From: "Ying-Chun Liu (PaulLiu)" Date: Thu, 3 Jul 2025 07:28:10 +0100 Subject: efi: add EFI_DEBUG_IMAGE_INFO for debug This commit adds the functionality of generate EFI_DEBUG_IMAGE_INFO while loading the image. This feature is described in UEFI Spec 2.10. Section 18.4.3. The implementation ensures support for hardware-assisted debugging and provides a standardized mechanism for debuggers to discover the load address of an EFI application. Cc: Ilias Apalodimas Cc: Peter Robinson Cc: Simon Glass Signed-off-by: Ying-Chun Liu (PaulLiu) Tested-by: Heinrich Schuchardt Acked-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- include/efi_api.h | 2 + include/efi_loader.h | 5 ++ lib/efi_loader/efi_boottime.c | 7 ++ lib/efi_loader/efi_debug_support.c | 137 +++++++++++++++++++++++++++++++++++++ 4 files changed, 151 insertions(+) (limited to 'include') diff --git a/include/efi_api.h b/include/efi_api.h index 8da0a350ce3..77a05f752e5 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -581,6 +581,8 @@ struct efi_loaded_image { #define EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS 0x01 #define EFI_DEBUG_IMAGE_INFO_TABLE_MODIFIED 0x02 +#define EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL 0x01 + /** * struct efi_debug_image_info_normal - Store Debug Information for normal * image. diff --git a/include/efi_loader.h b/include/efi_loader.h index b60ea58d71f..3e70ac07055 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -647,6 +647,11 @@ efi_status_t efi_root_node_register(void); efi_status_t efi_initialize_system_table(void); /* Called by bootefi to initialize debug */ efi_status_t efi_initialize_system_table_pointer(void); +/* Called by efi_load_image for register debug info */ +efi_status_t efi_core_new_debug_image_info_entry(u32 image_info_type, + struct efi_loaded_image *loaded_image, + efi_handle_t image_handle); +void efi_core_remove_debug_image_info_entry(efi_handle_t image_handle); /* efi_runtime_detach() - detach unimplemented runtime functions */ void efi_runtime_detach(void); /* efi_convert_pointer() - convert pointer to virtual address */ diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 754bc6a6519..ddc935d2240 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -2130,6 +2130,11 @@ efi_status_t EFIAPI efi_load_image(bool boot_policy, *image_handle = NULL; free(info); } + + if (IS_ENABLED(CONFIG_EFI_DEBUG_SUPPORT) && *image_handle) + efi_core_new_debug_image_info_entry(EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL, + info, + *image_handle); error: return EFI_EXIT(ret); } @@ -3360,6 +3365,8 @@ efi_status_t EFIAPI efi_unload_image(efi_handle_t image_handle) ret = EFI_INVALID_PARAMETER; goto out; } + if (IS_ENABLED(CONFIG_EFI_DEBUG_SUPPORT)) + efi_core_remove_debug_image_info_entry(image_handle); switch (efiobj->type) { case EFI_OBJECT_TYPE_STARTED_IMAGE: /* Call the unload function */ diff --git a/lib/efi_loader/efi_debug_support.c b/lib/efi_loader/efi_debug_support.c index 597592fbd1c..186bdbce750 100644 --- a/lib/efi_loader/efi_debug_support.c +++ b/lib/efi_loader/efi_debug_support.c @@ -17,6 +17,13 @@ struct efi_debug_image_info_table_header efi_m_debug_info_table_header = { NULL }; +/* efi_m_max_table_entries is the maximum entries allocated for + * the efi_m_debug_info_table_header.efi_debug_image_info_table. + */ +static u32 efi_m_max_table_entries; + +#define EFI_DEBUG_TABLE_ENTRY_SIZE (sizeof(union efi_debug_image_info *)) + /** * efi_initialize_system_table_pointer() - Initialize system table pointer * @@ -44,3 +51,133 @@ efi_status_t efi_initialize_system_table_pointer(void) return EFI_SUCCESS; } + +/** + * efi_core_new_debug_image_info_entry() - Add a new efi_loaded_image structure to the + * efi_debug_image_info table. + * + * @image_info_type: type of debug image information + * @loaded_image: pointer to the loaded image protocol for the image + * being loaded + * @image_handle: image handle for the image being loaded + * + * Re-Allocates the table if it's not large enough to accommodate another + * entry. + * + * Return: status code + **/ +efi_status_t efi_core_new_debug_image_info_entry(u32 image_info_type, + struct efi_loaded_image *loaded_image, + efi_handle_t image_handle) +{ + union efi_debug_image_info **table; + u32 index; + u32 table_size; + efi_status_t ret; + + /* Set the flag indicating that we're in the process of updating + * the table. + */ + efi_m_debug_info_table_header.update_status |= + EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS; + + table = &efi_m_debug_info_table_header.efi_debug_image_info_table; + + if (efi_m_debug_info_table_header.table_size >= efi_m_max_table_entries) { + /* table is full, re-allocate the buffer increasing the size + * by 4 KiB. + */ + table_size = efi_m_max_table_entries * EFI_DEBUG_TABLE_ENTRY_SIZE; + + ret = efi_realloc((void **)table, table_size + EFI_PAGE_SIZE); + + if (ret != EFI_SUCCESS) { + efi_m_debug_info_table_header.update_status &= + ~EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS; + return ret; + } + + /* Enlarge the max table entries and set the first empty + * entry index to be the original max table entries. + */ + efi_m_max_table_entries += + EFI_PAGE_SIZE / EFI_DEBUG_TABLE_ENTRY_SIZE; + } + + /* We always put the next entry at the end of the currently consumed + * table (i.e. first free entry) + */ + index = efi_m_debug_info_table_header.table_size; + + /* Allocate data for new entry. */ + ret = efi_allocate_pool(EFI_BOOT_SERVICES_DATA, + sizeof(union efi_debug_image_info), + (void **)(&(*table)[index].normal_image)); + if (ret == EFI_SUCCESS && (*table)[index].normal_image) { + /* Update the entry. */ + (*table)[index].normal_image->image_info_type = image_info_type; + (*table)[index].normal_image->loaded_image_protocol_instance = + loaded_image; + (*table)[index].normal_image->image_handle = image_handle; + + /* Increase the number of EFI_DEBUG_IMAGE_INFO elements and + * set the efi_m_debug_info_table_header in modified status. + */ + efi_m_debug_info_table_header.table_size++; + efi_m_debug_info_table_header.update_status |= + EFI_DEBUG_IMAGE_INFO_TABLE_MODIFIED; + } else { + log_err("Adding new efi_debug_image_info failed\n"); + return ret; + } + + efi_m_debug_info_table_header.update_status &= + ~EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS; + + return EFI_SUCCESS; +} + +/** + * efi_core_remove_debug_image_info_entry() - Remove an efi_debug_image_info entry. + * + * @image_handle: image handle for the image being removed + **/ +void efi_core_remove_debug_image_info_entry(efi_handle_t image_handle) +{ + union efi_debug_image_info *table; + u32 index; + + efi_m_debug_info_table_header.update_status |= + EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS; + + table = efi_m_debug_info_table_header.efi_debug_image_info_table; + + for (index = 0; index < efi_m_max_table_entries; index++) { + if (table[index].normal_image && + table[index].normal_image->image_handle == image_handle) { + /* Found a match. Free up the table entry. + * Move the tail of the table one slot to the front. + */ + efi_free_pool(table[index].normal_image); + + memmove(&table[index], + &table[index + 1], + (efi_m_debug_info_table_header.table_size - + index - 1) * EFI_DEBUG_TABLE_ENTRY_SIZE); + + /* Decrease the number of EFI_DEBUG_IMAGE_INFO + * elements and set the efi_m_debug_info_table_header + * in modified status. + */ + efi_m_debug_info_table_header.table_size--; + table[efi_m_debug_info_table_header.table_size].normal_image = + NULL; + efi_m_debug_info_table_header.update_status |= + EFI_DEBUG_IMAGE_INFO_TABLE_MODIFIED; + break; + } + } + + efi_m_debug_info_table_header.update_status &= + ~EFI_DEBUG_IMAGE_INFO_UPDATE_IN_PROGRESS; +} -- cgit v1.3.1