From a0a5c43193f62d427a7bd0b6b01fb5afbd8917e0 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Mon, 5 Jul 2021 13:29:02 +0100 Subject: usb: xhci-pci: Move reset logic out of XHCI core Resetting an XHCI controller inside xhci_register undoes any register setup performed by the platform driver. And at least on the Allwinner H6, resetting the XHCI controller also resets the PHY, which prevents the controller from working. That means the controller must be taken out of reset before initializing the PHY, which must be done before calling xhci_register. The logic in the XHCI core was added to support the Raspberry Pi 4 (although this was not mentioned in the commit log!), which uses the xhci-pci platform driver. Move the reset logic to the platform driver, where it belongs, and where it cannot interfere with other platform drivers. This also fixes a failure to call reset_free if xhci_register failed. Fixes: 0b80371b350e ("usb: xhci: Add reset controller support") Signed-off-by: Samuel Holland Reviewed-by: Bin Meng Signed-off-by: Andre Przywara --- include/usb/xhci.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 8d95e213b01..01e63cf0fce 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -17,7 +17,6 @@ #define HOST_XHCI_H_ #include -#include #include #include #include @@ -1200,7 +1199,6 @@ struct xhci_ctrl { #if CONFIG_IS_ENABLED(DM_USB) struct udevice *dev; #endif - struct reset_ctl reset; struct xhci_hccr *hccr; /* R/O registers, not need for volatile */ struct xhci_hcor *hcor; struct xhci_doorbell_array *dba; -- cgit v1.3.1 From daa632907e32c1ab348ffc0c88dbce064ab0c468 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 20 Sep 2021 15:37:22 +0200 Subject: usb: add support for ULPI/SERIAL/HSIC PHY modes Import usb_phy_interface enum values and DT match strings from the Linux kernel. Signed-off-by: Markus Niebel Signed-off-by: Matthias Schiffer --- drivers/usb/common/common.c | 3 +++ include/linux/usb/phy.h | 3 +++ 2 files changed, 6 insertions(+) (limited to 'include') diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c index 2a47f40bbab..43564c9fbaf 100644 --- a/drivers/usb/common/common.c +++ b/drivers/usb/common/common.c @@ -80,6 +80,9 @@ static const char *const usbphy_modes[] = { [USBPHY_INTERFACE_MODE_UNKNOWN] = "", [USBPHY_INTERFACE_MODE_UTMI] = "utmi", [USBPHY_INTERFACE_MODE_UTMIW] = "utmi_wide", + [USBPHY_INTERFACE_MODE_ULPI] = "ulpi", + [USBPHY_INTERFACE_MODE_SERIAL] = "serial", + [USBPHY_INTERFACE_MODE_HSIC] = "hsic", }; enum usb_phy_interface usb_get_phy_mode(ofnode node) diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h index 1e1217a9583..14b2c7eb2e6 100644 --- a/include/linux/usb/phy.h +++ b/include/linux/usb/phy.h @@ -16,6 +16,9 @@ enum usb_phy_interface { USBPHY_INTERFACE_MODE_UNKNOWN, USBPHY_INTERFACE_MODE_UTMI, USBPHY_INTERFACE_MODE_UTMIW, + USBPHY_INTERFACE_MODE_ULPI, + USBPHY_INTERFACE_MODE_SERIAL, + USBPHY_INTERFACE_MODE_HSIC, }; #if CONFIG_IS_ENABLED(DM_USB) -- cgit v1.3.1 From bc31f6a1b1c17763894ebd8075bcb4620b625317 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 20 Sep 2021 15:37:23 +0200 Subject: include/configs: replace MXC_EHCI_MODE_SERIAL with PORT_PTS_SERIAL The MXC_EHCI_MODE_ definitions are redundant. Replace MXC_EHCI_MODE_SERIAL with the equivalent PORT_PTS_SERIAL. Only the zmx25 platform is affected. Signed-off-by: Markus Niebel Signed-off-by: Matthias Schiffer --- include/configs/zmx25.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 88a885463d4..8b571da021a 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -57,7 +57,7 @@ #define CONFIG_USB_EHCI_MXC #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL +#define CONFIG_MXC_USB_PORTSC PORT_PTS_SERIAL #define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN) #define CONFIG_EHCI_IS_TDI #endif /* CONFIG_CMD_USB */ -- cgit v1.3.1 From 656bc27d502ca1f63846f6b8719e921621058594 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 20 Sep 2021 15:37:24 +0200 Subject: usb: ehci-ci: remove redundant PORTSC flag definitions These definitions are unused, all boards that define portsc flags use the equivalent PORT_* definitions instead. Signed-off-by: Markus Niebel Signed-off-by: Matthias Schiffer --- include/usb/ehci-ci.h | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'include') diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index efb2eec5ce7..bf5d26faa53 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -249,17 +249,6 @@ struct usb_ehci { * For MXC SOCs */ -/* values for portsc field */ -#define MXC_EHCI_PHY_LOW_POWER_SUSPEND (1 << 23) -#define MXC_EHCI_FORCE_FS (1 << 24) -#define MXC_EHCI_UTMI_8BIT (0 << 28) -#define MXC_EHCI_UTMI_16BIT (1 << 28) -#define MXC_EHCI_SERIAL (1 << 29) -#define MXC_EHCI_MODE_UTMI (0 << 30) -#define MXC_EHCI_MODE_PHILIPS (1 << 30) -#define MXC_EHCI_MODE_ULPI (2 << 30) -#define MXC_EHCI_MODE_SERIAL (3 << 30) - /* values for flags field */ #define MXC_EHCI_INTERFACE_DIFF_UNI (0 << 0) #define MXC_EHCI_INTERFACE_DIFF_BI (1 << 0) -- cgit v1.3.1 From e2a41bf63836e9336b4b301d26719445efb828c7 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Mon, 20 Sep 2021 15:37:25 +0200 Subject: usb: ehci-mx6: use phy_type from device tree Allow using different PHY interfaces for multiple USB controllers. When no value is set in DT, we fall back to CONFIG_MXC_USB_PORTSC for now to stay compatible with current board configurations. This also adds support for the HSIC mode of the i.MX7. Signed-off-by: Markus Niebel Signed-off-by: Matthias Schiffer --- drivers/usb/host/ehci-mx6.c | 25 +++++++++++++++++++++++-- include/usb/ehci-ci.h | 1 + 2 files changed, 24 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index c3e4170513e..1bd6147c76a 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "ehci.h" @@ -435,6 +436,7 @@ struct ehci_mx6_priv_data { struct clk clk; struct phy phy; enum usb_init_type init_type; + enum usb_phy_interface phy_type; #if !defined(CONFIG_PHY) int portnr; void __iomem *phy_addr; @@ -443,6 +445,24 @@ struct ehci_mx6_priv_data { #endif }; +static u32 mx6_portsc(enum usb_phy_interface phy_type) +{ + switch (phy_type) { + case USBPHY_INTERFACE_MODE_UTMI: + return PORT_PTS_UTMI; + case USBPHY_INTERFACE_MODE_UTMIW: + return PORT_PTS_UTMI | PORT_PTS_PTW; + case USBPHY_INTERFACE_MODE_ULPI: + return PORT_PTS_ULPI; + case USBPHY_INTERFACE_MODE_SERIAL: + return PORT_PTS_SERIAL; + case USBPHY_INTERFACE_MODE_HSIC: + return PORT_PTS_HSIC; + default: + return CONFIG_MXC_USB_PORTSC; + } +} + static int mx6_init_after_reset(struct ehci_ctrl *dev) { struct ehci_mx6_priv_data *priv = dev->priv; @@ -479,7 +499,7 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev) return 0; setbits_le32(&ehci->usbmode, CM_HOST); - writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + writel(mx6_portsc(priv->phy_type), &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); mdelay(10); @@ -641,6 +661,7 @@ static int ehci_usb_probe(struct udevice *dev) priv->ehci = ehci; priv->init_type = type; + priv->phy_type = usb_get_phy_mode(dev_ofnode(dev)); #if CONFIG_IS_ENABLED(CLK) ret = clk_get_by_index(dev, 0, &priv->clk); @@ -690,7 +711,7 @@ static int ehci_usb_probe(struct udevice *dev) if (priv->init_type == USB_INIT_HOST) { setbits_le32(&ehci->usbmode, CM_HOST); - writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + writel(mx6_portsc(priv->phy_type), &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); } diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index bf5d26faa53..2cdb3146e86 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -23,6 +23,7 @@ #define PORT_PTS_ULPI (2 << 30) #define PORT_PTS_SERIAL (3 << 30) #define PORT_PTS_PTW (1 << 28) +#define PORT_PTS_HSIC (1 << 25) #define PORT_PFSC (1 << 24) /* Defined on Page 39-44 of the mpc5151 ERM */ #define PORT_PTS_PHCD (1 << 23) #define PORT_PP (1 << 12) -- cgit v1.3.1 From 946af58f117d08921f8efc82eb728837df9be4ef Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 14 Sep 2021 05:25:29 +0200 Subject: arm: socfpga: vining: Drop meaningless comment The comment is no longer meaningful due to DT conversion, drop it. Signed-off-by: Marek Vasut Cc: Siew Chin Lim Cc: Simon Goldschmidt Cc: Tien Fong Chee --- include/configs/socfpga_vining_fpga.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h index 06976d804c7..38a77535893 100644 --- a/include/configs/socfpga_vining_fpga.h +++ b/include/configs/socfpga_vining_fpga.h @@ -17,8 +17,6 @@ #define CONFIG_LOADADDR 0x01000000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -/* Ethernet on SoC (EMAC) */ - /* Extra Environment */ #define CONFIG_HOSTNAME "socfpga_vining_fpga" -- cgit v1.3.1 From 4c3e84784849660f0c0d29e15d6c75b96c4f7f3d Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Wed, 22 Sep 2021 11:02:26 +0200 Subject: mtd: remove SPEAr flash driver st_smi Remove the driver st_smic.c used in SPEAr products and the associated config CONFIG_ST_SMI; this driver is no more used in U-Boot after the commit 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support"). Fixes: 570c3dcfc153 ("arm: Remove spear600 boards and the rest of SPEAr support") Signed-off-by: Patrick Delaunay Reviewed-by: Stefan Roese Reviewed-by: Tom Rini --- drivers/mtd/Makefile | 1 - drivers/mtd/st_smi.c | 565 ------------------------------------------- include/configs/bcmstb.h | 1 - include/linux/mtd/st_smi.h | 100 -------- scripts/config_whitelist.txt | 1 - 5 files changed, 668 deletions(-) delete mode 100644 drivers/mtd/st_smi.c delete mode 100644 include/linux/mtd/st_smi.h (limited to 'include') diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index 6d77ebfaa53..ce0451108eb 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -12,7 +12,6 @@ mtd-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o mtd-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o mtd-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o mtd-$(CONFIG_FLASH_PIC32) += pic32_flash.o -mtd-$(CONFIG_ST_SMI) += st_smi.o mtd-$(CONFIG_STM32_FLASH) += stm32_flash.o mtd-$(CONFIG_RENESAS_RPC_HF) += renesas_rpc_hf.o mtd-$(CONFIG_HBMC_AM654) += hbmc-am654.o diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c deleted file mode 100644 index 7c652e6c535..00000000000 --- a/drivers/mtd/st_smi.c +++ /dev/null @@ -1,565 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com. - */ - -#include -#include -#include -#include -#include - -#include -#include - -#if defined(CONFIG_MTD_NOR_FLASH) - -static struct smi_regs *const smicntl = - (struct smi_regs * const)CONFIG_SYS_SMI_BASE; -static ulong bank_base[CONFIG_SYS_MAX_FLASH_BANKS] = - CONFIG_SYS_FLASH_ADDR_BASE; -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/* data structure to maintain flash ids from different vendors */ -struct flash_device { - char *name; - u8 erase_cmd; - u32 device_id; - u32 pagesize; - unsigned long sectorsize; - unsigned long size_in_bytes; -}; - -#define FLASH_ID(n, es, id, psize, ssize, size) \ -{ \ - .name = n, \ - .erase_cmd = es, \ - .device_id = id, \ - .pagesize = psize, \ - .sectorsize = ssize, \ - .size_in_bytes = size \ -} - -/* - * List of supported flash devices. - * Currently the erase_cmd field is not used in this driver. - */ -static struct flash_device flash_devices[] = { - FLASH_ID("st m25p16" , 0xd8, 0x00152020, 0x100, 0x10000, 0x200000), - FLASH_ID("st m25p32" , 0xd8, 0x00162020, 0x100, 0x10000, 0x400000), - FLASH_ID("st m25p64" , 0xd8, 0x00172020, 0x100, 0x10000, 0x800000), - FLASH_ID("st m25p128" , 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000), - FLASH_ID("st m25p05" , 0xd8, 0x00102020, 0x80 , 0x8000 , 0x10000), - FLASH_ID("st m25p10" , 0xd8, 0x00112020, 0x80 , 0x8000 , 0x20000), - FLASH_ID("st m25p20" , 0xd8, 0x00122020, 0x100, 0x10000, 0x40000), - FLASH_ID("st m25p40" , 0xd8, 0x00132020, 0x100, 0x10000, 0x80000), - FLASH_ID("st m25p80" , 0xd8, 0x00142020, 0x100, 0x10000, 0x100000), - FLASH_ID("st m45pe10" , 0xd8, 0x00114020, 0x100, 0x10000, 0x20000), - FLASH_ID("st m45pe20" , 0xd8, 0x00124020, 0x100, 0x10000, 0x40000), - FLASH_ID("st m45pe40" , 0xd8, 0x00134020, 0x100, 0x10000, 0x80000), - FLASH_ID("st m45pe80" , 0xd8, 0x00144020, 0x100, 0x10000, 0x100000), - FLASH_ID("sp s25fl004" , 0xd8, 0x00120201, 0x100, 0x10000, 0x80000), - FLASH_ID("sp s25fl008" , 0xd8, 0x00130201, 0x100, 0x10000, 0x100000), - FLASH_ID("sp s25fl016" , 0xd8, 0x00140201, 0x100, 0x10000, 0x200000), - FLASH_ID("sp s25fl032" , 0xd8, 0x00150201, 0x100, 0x10000, 0x400000), - FLASH_ID("sp s25fl064" , 0xd8, 0x00160201, 0x100, 0x10000, 0x800000), - FLASH_ID("mac 25l512" , 0xd8, 0x001020C2, 0x010, 0x10000, 0x10000), - FLASH_ID("mac 25l1005" , 0xd8, 0x001120C2, 0x010, 0x10000, 0x20000), - FLASH_ID("mac 25l2005" , 0xd8, 0x001220C2, 0x010, 0x10000, 0x40000), - FLASH_ID("mac 25l4005" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000), - FLASH_ID("mac 25l4005a" , 0xd8, 0x001320C2, 0x010, 0x10000, 0x80000), - FLASH_ID("mac 25l8005" , 0xd8, 0x001420C2, 0x010, 0x10000, 0x100000), - FLASH_ID("mac 25l1605" , 0xd8, 0x001520C2, 0x100, 0x10000, 0x200000), - FLASH_ID("mac 25l1605a" , 0xd8, 0x001520C2, 0x010, 0x10000, 0x200000), - FLASH_ID("mac 25l3205" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000), - FLASH_ID("mac 25l3205a" , 0xd8, 0x001620C2, 0x100, 0x10000, 0x400000), - FLASH_ID("mac 25l6405" , 0xd8, 0x001720C2, 0x100, 0x10000, 0x800000), - FLASH_ID("wbd w25q128" , 0xd8, 0x001840EF, 0x100, 0x10000, 0x1000000), -}; - -/* - * smi_wait_xfer_finish - Wait until TFF is set in status register - * @timeout: timeout in milliseconds - * - * Wait until TFF is set in status register - */ -static int smi_wait_xfer_finish(int timeout) -{ - ulong start = get_timer(0); - - while (get_timer(start) < timeout) { - if (readl(&smicntl->smi_sr) & TFF) - return 0; - - /* Try after 10 ms */ - udelay(10); - }; - - return -1; -} - -/* - * smi_read_id - Read flash id - * @info: flash_info structure pointer - * @banknum: bank number - * - * Read the flash id present at bank #banknum - */ -static unsigned int smi_read_id(flash_info_t *info, int banknum) -{ - unsigned int value; - - writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); - writel(READ_ID, &smicntl->smi_tr); - writel((banknum << BANKSEL_SHIFT) | SEND | TX_LEN_1 | RX_LEN_3, - &smicntl->smi_cr2); - - if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) - return -EIO; - - value = (readl(&smicntl->smi_rr) & 0x00FFFFFF); - - writel(readl(&smicntl->smi_sr) & ~TFF, &smicntl->smi_sr); - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); - - return value; -} - -/* - * flash_get_size - Detect the SMI flash by reading the ID. - * @base: Base address of the flash area bank #banknum - * @banknum: Bank number - * - * Detect the SMI flash by reading the ID. Initializes the flash_info structure - * with size, sector count etc. - */ -static ulong flash_get_size(ulong base, int banknum) -{ - flash_info_t *info = &flash_info[banknum]; - int value; - int i; - - value = smi_read_id(info, banknum); - - if (value < 0) { - printf("Flash id could not be read\n"); - return 0; - } - - /* Matches chip-id to entire list of 'serial-nor flash' ids */ - for (i = 0; i < ARRAY_SIZE(flash_devices); i++) { - if (flash_devices[i].device_id == value) { - info->size = flash_devices[i].size_in_bytes; - info->flash_id = value; - info->start[0] = base; - info->sector_count = - info->size/flash_devices[i].sectorsize; - - return info->size; - } - } - - return 0; -} - -/* - * smi_read_sr - Read status register of SMI - * @bank: bank number - * - * This routine will get the status register of the flash chip present at the - * given bank - */ -static int smi_read_sr(int bank) -{ - u32 ctrlreg1, val; - - /* store the CTRL REG1 state */ - ctrlreg1 = readl(&smicntl->smi_cr1); - - /* Program SMI in HW Mode */ - writel(readl(&smicntl->smi_cr1) & ~(SW_MODE | WB_MODE), - &smicntl->smi_cr1); - - /* Performing a RSR instruction in HW mode */ - writel((bank << BANKSEL_SHIFT) | RD_STATUS_REG, &smicntl->smi_cr2); - - if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) - return -1; - - val = readl(&smicntl->smi_sr); - - /* Restore the CTRL REG1 state */ - writel(ctrlreg1, &smicntl->smi_cr1); - - return val; -} - -/* - * smi_wait_till_ready - Wait till last operation is over. - * @bank: bank number shifted. - * @timeout: timeout in milliseconds. - * - * This routine checks for WIP(write in progress)bit in Status register(SMSR-b0) - * The routine checks for #timeout loops, each at interval of 1 milli-second. - * If successful the routine returns 0. - */ -static int smi_wait_till_ready(int bank, int timeout) -{ - int sr; - ulong start = get_timer(0); - - /* One chip guarantees max 5 msec wait here after page writes, - but potentially three seconds (!) after page erase. */ - while (get_timer(start) < timeout) { - sr = smi_read_sr(bank); - if ((sr >= 0) && (!(sr & WIP_BIT))) - return 0; - - /* Try again after 10 usec */ - udelay(10); - } while (timeout--); - - printf("SMI controller is still in wait, timeout=%d\n", timeout); - return -EIO; -} - -/* - * smi_write_enable - Enable the flash to do write operation - * @bank: bank number - * - * Set write enable latch with Write Enable command. - * Returns negative if error occurred. - */ -static int smi_write_enable(int bank) -{ - u32 ctrlreg1; - u32 start; - int timeout = WMODE_TOUT; - int sr; - - /* Store the CTRL REG1 state */ - ctrlreg1 = readl(&smicntl->smi_cr1); - - /* Program SMI in H/W Mode */ - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); - - /* Give the Flash, Write Enable command */ - writel((bank << BANKSEL_SHIFT) | WE, &smicntl->smi_cr2); - - if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) - return -1; - - /* Restore the CTRL REG1 state */ - writel(ctrlreg1, &smicntl->smi_cr1); - - start = get_timer(0); - while (get_timer(start) < timeout) { - sr = smi_read_sr(bank); - if ((sr >= 0) && (sr & (1 << (bank + WM_SHIFT)))) - return 0; - - /* Try again after 10 usec */ - udelay(10); - }; - - return -1; -} - -/* - * smi_init - SMI initialization routine - * - * SMI initialization routine. Sets SMI control register1. - */ -void smi_init(void) -{ - /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */ - writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4, - &smicntl->smi_cr1); -} - -/* - * smi_sector_erase - Erase flash sector - * @info: flash_info structure pointer - * @sector: sector number - * - * Set write enable latch with Write Enable command. - * Returns negative if error occurred. - */ -static int smi_sector_erase(flash_info_t *info, unsigned int sector) -{ - int bank; - unsigned int sect_add; - unsigned int instruction; - - switch (info->start[0]) { - case SMIBANK0_BASE: - bank = BANK0; - break; - case SMIBANK1_BASE: - bank = BANK1; - break; - case SMIBANK2_BASE: - bank = BANK2; - break; - case SMIBANK3_BASE: - bank = BANK3; - break; - default: - return -1; - } - - sect_add = sector * (info->size / info->sector_count); - instruction = ((sect_add >> 8) & 0x0000FF00) | SECTOR_ERASE; - - writel(readl(&smicntl->smi_sr) & ~(ERF1 | ERF2), &smicntl->smi_sr); - - /* Wait until finished previous write command. */ - if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) - return -EBUSY; - - /* Send write enable, before erase commands. */ - if (smi_write_enable(bank)) - return -EIO; - - /* Put SMI in SW mode */ - writel(readl(&smicntl->smi_cr1) | SW_MODE, &smicntl->smi_cr1); - - /* Send Sector Erase command in SW Mode */ - writel(instruction, &smicntl->smi_tr); - writel((bank << BANKSEL_SHIFT) | SEND | TX_LEN_4, - &smicntl->smi_cr2); - if (smi_wait_xfer_finish(XFER_FINISH_TOUT)) - return -EIO; - - if (smi_wait_till_ready(bank, CONFIG_SYS_FLASH_ERASE_TOUT)) - return -EBUSY; - - /* Put SMI in HW mode */ - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, - &smicntl->smi_cr1); - - return 0; -} - -/* - * smi_write - Write to SMI flash - * @src_addr: source buffer - * @dst_addr: destination buffer - * @length: length to write in bytes - * @bank: bank base address - * - * Write to SMI flash - */ -static int smi_write(unsigned int *src_addr, unsigned int *dst_addr, - unsigned int length, ulong bank_addr) -{ - u8 *src_addr8 = (u8 *)src_addr; - u8 *dst_addr8 = (u8 *)dst_addr; - int banknum; - int i; - - switch (bank_addr) { - case SMIBANK0_BASE: - banknum = BANK0; - break; - case SMIBANK1_BASE: - banknum = BANK1; - break; - case SMIBANK2_BASE: - banknum = BANK2; - break; - case SMIBANK3_BASE: - banknum = BANK3; - break; - default: - return -1; - } - - if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) - return -EBUSY; - - /* Set SMI in Hardware Mode */ - writel(readl(&smicntl->smi_cr1) & ~SW_MODE, &smicntl->smi_cr1); - - if (smi_write_enable(banknum)) - return -EIO; - - /* Perform the write command */ - for (i = 0; i < length; i += 4) { - if (((ulong) (dst_addr) % SFLASH_PAGE_SIZE) == 0) { - if (smi_wait_till_ready(banknum, - CONFIG_SYS_FLASH_WRITE_TOUT)) - return -EBUSY; - - if (smi_write_enable(banknum)) - return -EIO; - } - - if (length < 4) { - int k; - - /* - * Handle special case, where length < 4 (redundant env) - */ - for (k = 0; k < length; k++) - *dst_addr8++ = *src_addr8++; - } else { - /* Normal 32bit write */ - *dst_addr++ = *src_addr++; - } - - if ((readl(&smicntl->smi_sr) & (ERF1 | ERF2))) - return -EIO; - } - - if (smi_wait_till_ready(banknum, CONFIG_SYS_FLASH_WRITE_TOUT)) - return -EBUSY; - - writel(readl(&smicntl->smi_sr) & ~(WCF), &smicntl->smi_sr); - - return 0; -} - -/* - * write_buff - Write to SMI flash - * @info: flash info structure - * @src: source buffer - * @dest_addr: destination buffer - * @length: length to write in words - * - * Write to SMI flash - */ -int write_buff(flash_info_t *info, uchar *src, ulong dest_addr, ulong length) -{ - return smi_write((unsigned int *)src, (unsigned int *)dest_addr, - length, info->start[0]); -} - -/* - * flash_init - SMI flash initialization - * - * SMI flash initialization - */ -unsigned long flash_init(void) -{ - unsigned long size = 0; - int i, j; - - smi_init(); - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - flash_info[i].flash_id = FLASH_UNKNOWN; - size += flash_info[i].size = flash_get_size(bank_base[i], i); - } - - for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) { - for (i = 1; i < flash_info[j].sector_count; i++) - flash_info[j].start[i] = - flash_info[j].start[i - 1] + - flash_info->size / flash_info->sector_count; - - } - - return size; -} - -/* - * flash_print_info - Print SMI flash information - * - * Print SMI flash information - */ -void flash_print_info(flash_info_t *info) -{ - int i; - if (info->flash_id == FLASH_UNKNOWN) { - puts("missing or unknown FLASH type\n"); - return; - } - - if (info->size >= 0x100000) - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - else - printf(" Size: %ld KB in %d Sectors\n", - info->size >> 10, info->sector_count); - - puts(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { -#ifdef CONFIG_SYS_FLASH_EMPTY_INFO - int size; - int erased; - u32 *flash; - - /* - * Check if whole sector is erased - */ - size = (info->size) / (info->sector_count); - flash = (u32 *) info->start[i]; - size = size / sizeof(int); - - while ((size--) && (*flash++ == ~0)) - ; - - size++; - if (size) - erased = 0; - else - erased = 1; - - if ((i % 5) == 0) - printf("\n"); - - printf(" %08lX%s%s", - info->start[i], - erased ? " E" : " ", info->protect[i] ? "RO " : " "); -#else - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], info->protect[i] ? " (RO) " : " "); -#endif - } - putc('\n'); - return; -} - -/* - * flash_erase - Erase SMI flash - * - * Erase SMI flash - */ -int flash_erase(flash_info_t *info, int s_first, int s_last) -{ - int rcode = 0; - int prot = 0; - flash_sect_t sect; - - if ((s_first < 0) || (s_first > s_last)) { - puts("- no sectors to erase\n"); - return 1; - } - - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) - prot++; - } - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - putc('\n'); - } - - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { - if (smi_sector_erase(info, sect)) - rcode = 1; - else - putc('.'); - } - } - puts(" done\n"); - return rcode; -} -#endif diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h index 2660d18f35a..d7f9e5bc063 100644 --- a/include/configs/bcmstb.h +++ b/include/configs/bcmstb.h @@ -130,7 +130,6 @@ extern phys_addr_t prior_stage_fdt_address; /* * Flash configuration. */ -#define CONFIG_ST_SMI #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_MACRONIX diff --git a/include/linux/mtd/st_smi.h b/include/linux/mtd/st_smi.h deleted file mode 100644 index 60589697870..00000000000 --- a/include/linux/mtd/st_smi.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. - */ - -#ifndef ST_SMI_H -#define ST_SMI_H - -/* 0xF800.0000 . 0xFBFF.FFFF 64MB SMI (Serial Flash Mem) */ -/* 0xFC00.0000 . 0xFC1F.FFFF 2MB SMI (Serial Flash Reg.) */ - -#define FLASH_START_ADDRESS CONFIG_SYS_FLASH_BASE -#define FLASH_BANK_SIZE CONFIG_SYS_FLASH_BANK_SIZE - -#define SMIBANK0_BASE (FLASH_START_ADDRESS) -#define SMIBANK1_BASE (SMIBANK0_BASE + FLASH_BANK_SIZE) -#define SMIBANK2_BASE (SMIBANK1_BASE + FLASH_BANK_SIZE) -#define SMIBANK3_BASE (SMIBANK2_BASE + FLASH_BANK_SIZE) - -#define BANK0 0 -#define BANK1 1 -#define BANK2 2 -#define BANK3 3 - -struct smi_regs { - u32 smi_cr1; - u32 smi_cr2; - u32 smi_sr; - u32 smi_tr; - u32 smi_rr; -}; - -/* CONTROL REG 1 */ -#define BANK_EN 0x0000000F /* enables all banks */ -#define DSEL_TIME 0x00000060 /* Deselect time */ -#define PRESCAL5 0x00000500 /* AHB_CK prescaling value */ -#define PRESCALA 0x00000A00 /* AHB_CK prescaling value */ -#define PRESCAL3 0x00000300 /* AHB_CK prescaling value */ -#define PRESCAL4 0x00000400 /* AHB_CK prescaling value */ -#define SW_MODE 0x10000000 /* enables SW Mode */ -#define WB_MODE 0x20000000 /* Write Burst Mode */ -#define FAST_MODE 0x00008000 /* Fast Mode */ -#define HOLD1 0x00010000 - -/* CONTROL REG 2 */ -#define RD_STATUS_REG 0x00000400 /* reads status reg */ -#define WE 0x00000800 /* Write Enable */ -#define BANK0_SEL 0x00000000 /* Select Banck0 */ -#define BANK1_SEL 0x00001000 /* Select Banck1 */ -#define BANK2_SEL 0x00002000 /* Select Banck2 */ -#define BANK3_SEL 0x00003000 /* Select Banck3 */ -#define BANKSEL_SHIFT 12 -#define SEND 0x00000080 /* Send data */ -#define TX_LEN_1 0x00000001 /* data length = 1 byte */ -#define TX_LEN_2 0x00000002 /* data length = 2 byte */ -#define TX_LEN_3 0x00000003 /* data length = 3 byte */ -#define TX_LEN_4 0x00000004 /* data length = 4 byte */ -#define RX_LEN_1 0x00000010 /* data length = 1 byte */ -#define RX_LEN_2 0x00000020 /* data length = 2 byte */ -#define RX_LEN_3 0x00000030 /* data length = 3 byte */ -#define RX_LEN_4 0x00000040 /* data length = 4 byte */ -#define TFIE 0x00000100 /* Tx Flag Interrupt Enable */ -#define WCIE 0x00000200 /* WCF Interrupt Enable */ - -/* STATUS_REG */ -#define INT_WCF_CLR 0xFFFFFDFF /* clear: WCF clear */ -#define INT_TFF_CLR 0xFFFFFEFF /* clear: TFF clear */ -#define WIP_BIT 0x00000001 /* WIP Bit of SPI SR */ -#define WEL_BIT 0x00000002 /* WEL Bit of SPI SR */ -#define RSR 0x00000005 /* Read Status regiser */ -#define TFF 0x00000100 /* Transfer Finished FLag */ -#define WCF 0x00000200 /* Transfer Finished FLag */ -#define ERF1 0x00000400 /* Error Flag 1 */ -#define ERF2 0x00000800 /* Error Flag 2 */ -#define WM0 0x00001000 /* WM Bank 0 */ -#define WM1 0x00002000 /* WM Bank 1 */ -#define WM2 0x00004000 /* WM Bank 2 */ -#define WM3 0x00008000 /* WM Bank 3 */ -#define WM_SHIFT 12 - -/* TR REG */ -#define READ_ID 0x0000009F /* Read Identification */ -#define BULK_ERASE 0x000000C7 /* BULK erase */ -#define SECTOR_ERASE 0x000000D8 /* SECTOR erase */ -#define WRITE_ENABLE 0x00000006 /* Wenable command to FLASH */ - -struct flash_dev { - u32 density; - ulong size; - ushort sector_count; -}; - -#define SFLASH_PAGE_SIZE 0x100 /* flash page size */ -#define XFER_FINISH_TOUT 15 /* xfer finish timeout(in ms) */ -#define WMODE_TOUT 15 /* write enable timeout(in ms) */ - -extern void smi_init(void); - -#endif diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index ff24ab18731..a9c2380d17e 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1427,7 +1427,6 @@ CONFIG_STM32_FLASH CONFIG_STV0991 CONFIG_STV0991_HZ CONFIG_STV0991_HZ_CLOCK -CONFIG_ST_SMI CONFIG_SXNI855T CONFIG_SYSFS CONFIG_SYSMGR_ISWGRP_HANDOFF -- cgit v1.3.1 From 019801863b64c69e98c7ce04ae6380af560affd0 Mon Sep 17 00:00:00 2001 From: Ruchika Gupta Date: Tue, 14 Sep 2021 12:14:31 +0530 Subject: efi_loader: Fix spec ID event creation TCG EFI Protocol Specification defines the number_of_algorithms field in spec ID event to be equal to the number of active algorithms supported by the TPM device. In current implementation, this field is populated with the count of all algorithms supported by the TPM which leads to incorrect spec ID event creation. Similarly, the algorithm array in spec ID event should be a variable length array with length being equal to the number_of_algorithms field. In current implementation this is defined as a fixed length array which has been fixed. Signed-off-by: Ruchika Gupta CC: Masahisa Kojima CC: Ilias Apalodimas CC: Heinrich Schuchardt Reviewed-by: Ilias Apalodimas --- include/efi_tcg2.h | 7 +------ lib/efi_loader/efi_tcg2.c | 40 +++++++++++++++++++++++----------------- 2 files changed, 24 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h index 5a1a36212e5..8f02d4fb0b2 100644 --- a/include/efi_tcg2.h +++ b/include/efi_tcg2.h @@ -165,8 +165,6 @@ struct tcg_efi_spec_id_event_algorithm_size { * @digest_sizes: array of number_of_algorithms pairs * 1st member defines the algorithm id * 2nd member defines the algorithm size - * @vendor_info_size: size in bytes for vendor specific info - * @vendor_info: vendor specific info */ struct tcg_efi_spec_id_event { u8 signature[16]; @@ -176,10 +174,7 @@ struct tcg_efi_spec_id_event { u8 spec_errata; u8 uintn_size; u32 number_of_algorithms; - struct tcg_efi_spec_id_event_algorithm_size digest_sizes[TPM2_NUM_PCR_BANKS]; - u8 vendor_info_size; - /* U-Boot does not provide any vendor info */ - u8 vendor_info[]; + struct tcg_efi_spec_id_event_algorithm_size digest_sizes[]; } __packed; /** diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c index cb48919223d..d3b8f93f148 100644 --- a/lib/efi_loader/efi_tcg2.c +++ b/lib/efi_loader/efi_tcg2.c @@ -575,9 +575,10 @@ static efi_status_t tcg2_create_digest(const u8 *input, u32 length, EFI_PRINT("Unsupported algorithm %x\n", hash_alg); return EFI_INVALID_PARAMETER; } + digest_list->digests[digest_list->count].hash_alg = hash_alg; + memcpy(&digest_list->digests[digest_list->count].digest, final, + (u32)alg_to_len(hash_alg)); digest_list->count++; - digest_list->digests[i].hash_alg = hash_alg; - memcpy(&digest_list->digests[i].digest, final, (u32)alg_to_len(hash_alg)); } return EFI_SUCCESS; @@ -798,8 +799,9 @@ static efi_status_t tcg2_hash_pe_image(void *efi, u64 efi_size, EFI_PRINT("Unsupported algorithm %x\n", hash_alg); return EFI_INVALID_PARAMETER; } - digest_list->digests[i].hash_alg = hash_alg; - memcpy(&digest_list->digests[i].digest, hash, (u32)alg_to_len(hash_alg)); + digest_list->digests[digest_list->count].hash_alg = hash_alg; + memcpy(&digest_list->digests[digest_list->count].digest, hash, + (u32)alg_to_len(hash_alg)); digest_list->count++; } @@ -1120,7 +1122,7 @@ static efi_status_t create_specid_event(struct udevice *dev, void *buffer, struct tcg_efi_spec_id_event *spec_event; size_t spec_event_size; efi_status_t ret = EFI_DEVICE_ERROR; - u32 active = 0, supported = 0; + u32 active = 0, supported = 0, pcr_count = 0, alg_count = 0; int err; size_t i; @@ -1142,25 +1144,29 @@ static efi_status_t create_specid_event(struct udevice *dev, void *buffer, TCG_EFI_SPEC_ID_EVENT_SPEC_VERSION_ERRATA_TPM2; spec_event->uintn_size = sizeof(efi_uintn_t) / sizeof(u32); - err = tpm2_get_pcr_info(dev, &supported, &active, - &spec_event->number_of_algorithms); + err = tpm2_get_pcr_info(dev, &supported, &active, &pcr_count); + if (err) goto out; - if (spec_event->number_of_algorithms > MAX_HASH_COUNT || - spec_event->number_of_algorithms < 1) - goto out; - for (i = 0; i < spec_event->number_of_algorithms; i++) { + for (i = 0; i < pcr_count; i++) { u16 hash_alg = hash_algo_list[i].hash_alg; u16 hash_len = hash_algo_list[i].hash_len; - if (active && alg_to_mask(hash_alg)) { + if (active & alg_to_mask(hash_alg)) { put_unaligned_le16(hash_alg, - &spec_event->digest_sizes[i].algorithm_id); + &spec_event->digest_sizes[alg_count].algorithm_id); put_unaligned_le16(hash_len, - &spec_event->digest_sizes[i].digest_size); + &spec_event->digest_sizes[alg_count].digest_size); + alg_count++; } } + + spec_event->number_of_algorithms = alg_count; + if (spec_event->number_of_algorithms > MAX_HASH_COUNT || + spec_event->number_of_algorithms < 1) + goto out; + /* * the size of the spec event and placement of vendor_info_size * depends on supported algoriths @@ -1169,9 +1175,9 @@ static efi_status_t create_specid_event(struct udevice *dev, void *buffer, offsetof(struct tcg_efi_spec_id_event, digest_sizes) + spec_event->number_of_algorithms * sizeof(spec_event->digest_sizes[0]); /* no vendor info for us */ - memset(buffer + spec_event_size, 0, - sizeof(spec_event->vendor_info_size)); - spec_event_size += sizeof(spec_event->vendor_info_size); + memset(buffer + spec_event_size, 0, 1); + /* add a byte for vendor_info_size in the spec event */ + spec_event_size += 1; *event_size = spec_event_size; return EFI_SUCCESS; -- cgit v1.3.1 From 4b46e8388549bd0e52ec742c7e5ed71e0edc1b9f Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Tue, 24 Aug 2021 15:00:41 +0300 Subject: net: dsa: introduce a .port_probe() method in struct dsa_ops Some drivers might want to execute code for each port at probe time, as opposed to executing code just-in-time for the port selected for networking. To cater to that use case, introduce a .port_probe() callback method into the DSA switch operations which is called for each available port, at the end of dsa_port_probe(). Signed-off-by: Vladimir Oltean Reviewed-by: Ramon Fried Tested-by: Michael Walle --- include/net/dsa.h | 5 ++++- net/dsa-uclass.c | 8 ++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/net/dsa.h b/include/net/dsa.h index 0f31a908c9d..ab2a9dfbea2 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -57,7 +57,8 @@ /** * struct dsa_ops - DSA operations * - * @port_enable: Initialize a switch port for I/O. + * @port_probe: Initialize a switch port. + * @port_enable: Enable I/O for a port. * @port_disable: Disable I/O for a port. * @xmit: Insert the DSA tag for transmission. * DSA drivers receive a copy of the packet with headroom and @@ -69,6 +70,8 @@ * master including any additional headers. */ struct dsa_ops { + int (*port_probe)(struct udevice *dev, int port, + struct phy_device *phy); int (*port_enable)(struct udevice *dev, int port, struct phy_device *phy); void (*port_disable)(struct udevice *dev, int port, diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c index dbd8558b648..9b8ae1e82b9 100644 --- a/net/dsa-uclass.c +++ b/net/dsa-uclass.c @@ -270,6 +270,7 @@ static void dsa_port_set_hwaddr(struct udevice *pdev, struct udevice *master) static int dsa_port_probe(struct udevice *pdev) { struct udevice *dev = dev_get_parent(pdev); + struct dsa_ops *ops = dsa_get_ops(dev); struct dsa_port_pdata *port_pdata; struct dsa_priv *dsa_priv; struct udevice *master; @@ -299,6 +300,13 @@ static int dsa_port_probe(struct udevice *pdev) dsa_port_set_hwaddr(pdev, master); + if (ops->port_probe) { + err = ops->port_probe(dev, port_pdata->index, + port_pdata->phy); + if (err) + return err; + } + return 0; } -- cgit v1.3.1 From 66fd01fe5935d4be5f556f67284efb1b67fa4143 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Fri, 17 Sep 2021 14:27:13 +0300 Subject: net: update NXP copyright text NXP Legal insists that the following are not fine: - Saying "NXP Semiconductors" instead of "NXP", since the company's registered name is "NXP" - Putting a "(c)" sign in the copyright string - Putting a comma in the copyright string The only accepted copyright string format is "Copyright NXP". This patch changes the copyright headers in the networking files that were sent by me, or derived from code sent by me. Signed-off-by: Vladimir Oltean Reviewed-by: Ramon Fried --- arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi | 2 +- arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi | 2 +- arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi | 2 +- arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi | 2 +- arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi | 2 +- arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi | 2 +- arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi | 2 +- arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi | 2 +- arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi | 2 +- arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi | 2 +- arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi | 2 +- arch/arm/dts/fsl-sch-24801.dtsi | 2 +- arch/arm/dts/fsl-sch-28021.dtsi | 2 +- arch/arm/dts/fsl-sch-30841.dtsi | 2 +- arch/arm/dts/fsl-sch-30842.dtsi | 2 +- arch/arm/dts/ls1021a-tsn.dts | 2 +- board/freescale/ls1021atsn/ls1021atsn.c | 2 +- drivers/net/dsa_sandbox.c | 2 +- drivers/net/mscc_eswitch/felix_switch.c | 2 +- include/configs/ls1021atsn.h | 2 +- include/net/dsa.h | 2 +- test/dm/dsa.c | 2 +- 22 files changed, 22 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi index 23816da8eeb..4063d9a114d 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 1xxx * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi index c6558ae2e07..6dcd15a6851 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 6xxx * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi index 5a0f060c16e..1607a32c1ee 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 7777 * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi index 39a83e10c4c..a00f58273dc 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 7xx7 * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ &slot1 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi index 7d4702e4ff2..94b5081d610 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 8xxx * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi index 021fe3fbc67..3b850268e6a 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 9999 * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi index b6704d8089a..eb632143e06 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 9999 * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP * */ diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi index 8c10897e565..ed86da6b26d 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW x3xx * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi index 1d800dacef8..c9de4ecc434 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW x5xx * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi index 1fb2cdf0c24..16a96c1fd51 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 7777 * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ &slot2 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi index 2333f74e5ae..0db9b70f219 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi @@ -2,7 +2,7 @@ /* * NXP LS1028A-QDS device tree fragment for RCW 7777 * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ &slot3 { diff --git a/arch/arm/dts/fsl-sch-24801.dtsi b/arch/arm/dts/fsl-sch-24801.dtsi index 304afdabc59..d1b43aa0020 100644 --- a/arch/arm/dts/fsl-sch-24801.dtsi +++ b/arch/arm/dts/fsl-sch-24801.dtsi @@ -2,7 +2,7 @@ /* * Device tree fragment for RCW SCH-24801 card * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-sch-28021.dtsi b/arch/arm/dts/fsl-sch-28021.dtsi index 584f3fa68cd..61245287b96 100644 --- a/arch/arm/dts/fsl-sch-28021.dtsi +++ b/arch/arm/dts/fsl-sch-28021.dtsi @@ -2,7 +2,7 @@ /* * Device tree fragment for RCW SCH-28021 card * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-sch-30841.dtsi b/arch/arm/dts/fsl-sch-30841.dtsi index ca437d17828..2f1e63a6ae7 100644 --- a/arch/arm/dts/fsl-sch-30841.dtsi +++ b/arch/arm/dts/fsl-sch-30841.dtsi @@ -2,7 +2,7 @@ /* * Device tree fragment for RCW SCH-30841 card * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/fsl-sch-30842.dtsi b/arch/arm/dts/fsl-sch-30842.dtsi index fa0f2cdb109..6a68b1849ef 100644 --- a/arch/arm/dts/fsl-sch-30842.dtsi +++ b/arch/arm/dts/fsl-sch-30842.dtsi @@ -2,7 +2,7 @@ /* * Device tree fragment for RCW SCH-30842 card * - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ /* diff --git a/arch/arm/dts/ls1021a-tsn.dts b/arch/arm/dts/ls1021a-tsn.dts index f633074099d..8e0f4eaf684 100644 --- a/arch/arm/dts/ls1021a-tsn.dts +++ b/arch/arm/dts/ls1021a-tsn.dts @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -/* Copyright 2016-2018 NXP Semiconductors +/* Copyright 2016-2018 NXP * Copyright 2019 Vladimir Oltean */ diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c index c1acd3040c4..f31e16c419a 100644 --- a/board/freescale/ls1021atsn/ls1021atsn.c +++ b/board/freescale/ls1021atsn/ls1021atsn.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0 -/* Copyright 2016-2019 NXP Semiconductors +/* Copyright 2016-2019 NXP */ #include #include diff --git a/drivers/net/dsa_sandbox.c b/drivers/net/dsa_sandbox.c index 4b62670e5d1..235f2f22d9a 100644 --- a/drivers/net/dsa_sandbox.c +++ b/drivers/net/dsa_sandbox.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ #include diff --git a/drivers/net/mscc_eswitch/felix_switch.c b/drivers/net/mscc_eswitch/felix_switch.c index 6aa79784460..859428f7cb9 100644 --- a/drivers/net/mscc_eswitch/felix_switch.c +++ b/drivers/net/mscc_eswitch/felix_switch.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause /* * Felix (VSC9959) Ethernet switch driver - * Copyright 2018-2021 NXP Semiconductors + * Copyright 2018-2021 NXP */ /* diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 58c2d97a327..0dd891b57ec 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0 - * Copyright 2016-2019 NXP Semiconductors + * Copyright 2016-2019 NXP * Copyright 2019 Vladimir Oltean */ diff --git a/include/net/dsa.h b/include/net/dsa.h index ab2a9dfbea2..a339a497303 100644 --- a/include/net/dsa.h +++ b/include/net/dsa.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019-2021 NXP Semiconductors + * Copyright 2019-2021 NXP */ #ifndef __DSA_H__ diff --git a/test/dm/dsa.c b/test/dm/dsa.c index 18c1776460d..c857106eaf4 100644 --- a/test/dm/dsa.c +++ b/test/dm/dsa.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2020-2021 NXP Semiconductors + * Copyright 2020-2021 NXP */ #include -- cgit v1.3.1 From 77b11f7604162886f46e56011e790b7700f8cadd Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Sat, 18 Sep 2021 15:32:34 +0300 Subject: net: replace the "xfi" phy-mode with "10gbase-r" As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean Reviewed-by: Ramon Fried --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc | 8 ++++---- arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 2 +- arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi | 4 ++-- arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi | 4 ++-- arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi | 16 ++++++++-------- arch/arm/dts/fsl-ls2088a-rdb-qspi.dts | 16 ++++++++-------- arch/arm/dts/fsl-sch-30841.dtsi | 2 +- arch/arm/dts/fsl-sch-30842.dtsi | 2 +- board/Marvell/octeon_ebb7304/board.c | 6 +++--- board/freescale/ls1043aqds/README | 2 +- board/freescale/ls1043aqds/eth.c | 4 ++-- board/freescale/ls1043ardb/README | 2 +- board/freescale/ls1043ardb/eth.c | 2 +- board/freescale/ls1046aqds/README | 2 +- board/freescale/ls1046aqds/eth.c | 4 ++-- board/freescale/ls1046ardb/README | 4 ++-- board/freescale/ls1046ardb/eth.c | 2 +- board/freescale/ls1088a/README | 4 ++-- board/freescale/ls1088a/eth_ls1088ardb.c | 6 +++--- board/freescale/ls2080aqds/README | 2 +- board/freescale/ls2080aqds/eth.c | 13 ++++++------- board/freescale/ls2080ardb/README | 2 +- board/freescale/t102xrdb/README | 2 +- board/freescale/t102xrdb/eth_t102xrdb.c | 2 +- board/freescale/t208xqds/README | 18 +++++++++--------- board/freescale/t208xqds/eth_t208xqds.c | 22 +++++++++++----------- board/freescale/t208xqds/t208xqds.c | 8 ++++---- board/freescale/t208xrdb/README | 4 ++-- board/freescale/t4rdb/eth.c | 2 +- doc/device-tree-bindings/net/ethernet.txt | 12 +++++++++++- drivers/net/fm/b4860.c | 2 +- drivers/net/fm/memac.c | 4 ++-- drivers/net/fsl_enetc.c | 4 ++-- drivers/net/mscc_eswitch/felix_switch.c | 2 +- drivers/net/phy/aquantia.c | 14 +++++++------- include/phy.h | 2 +- include/phy_interface.h | 4 ++-- 38 files changed, 111 insertions(+), 102 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index d0103fc8811..1a359d060e8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1147,7 +1147,7 @@ int arch_early_init_r(void) #endif #ifdef CONFIG_SYS_FSL_HAS_RGMII /* some dpmacs in armv8a based freescale layerscape SOCs can be - * configured via both serdes(sgmii, xfi, xlaui etc) bits and via + * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via * EC*_PMUX(rgmii) bits in RCW. * e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from * serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index f33d05d0539..f2efd4cc1d7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -31,7 +31,7 @@ The LS1043A SoC includes the following function and features: - Hardware buffer management for buffer allocation and de-allocation (BMan) - Cryptography acceleration (SEC) - Ethernet interfaces by FMan - - Up to 1 x XFI supporting 10G interface + - Up to 1 x 10GBase-R supporting 10G interface - Up to 1 x QSGMII - Up to 4 x SGMII supporting 1000Mbps - Up to 2 x SGMII supporting 2500Mbps @@ -190,7 +190,7 @@ The LS1046A SoC includes the following function and features: - Two PLLs per four-lane SerDes - Support for 10G operation - Ethernet interfaces by FMan - - Up to 2 x XFI supporting 10G interface (MAC 9, 10) + - Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10) - Up to 1 x QSGMII (MAC 5, 6, 10, 1) - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10) - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10) @@ -295,7 +295,7 @@ The LX2160A SoC includes the following function and features: Single WRIOP tile supporting 130Gbps using 18 MACs Support for 10G-SXGMII (aka USXGMII). Support for SGMII (and 1000Base-KX) - Support for XFI (and 10GBase-KR) + Support for 10GBase-R (and 10GBase-KR) Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G). Support for XLAUI (and 40GBase-KR4) for 40G. Support for two RGMII parallel interfaces. @@ -400,7 +400,7 @@ The LX2162A SoC includes the following function and features: Ethernet interfaces Support for 10G-SXGMII (aka USXGMII). Support for SGMII (and 1000Base-KX) - Support for XFI (and 10GBase-KR) + Support for 10GBase-R (and 10GBase-KR) Support for CAUI2 (50G) and 25G-AUI(25G). Support for XLAUI (and 40GBase-KR4) for 40G. Support for two RGMII parallel interfaces. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c index 280afbbf98f..26f8a498269 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c @@ -100,7 +100,7 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) return 0; /* - * LS1044A/1048A support only one XFI port + * LS1044A/1048A support only one 10GBase-R port * Disable MAC1 for LS1044A/1048A */ if (serdes == FSL_SRDS_1 && lane == 2) { diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi index e0a6c04835b..df39cca6961 100644 --- a/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi @@ -9,12 +9,12 @@ &dpmac1 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac2 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac4 { diff --git a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi index 65e95300ab5..99f74c2fc4d 100644 --- a/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi +++ b/arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi @@ -9,10 +9,10 @@ &dpmac1 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac2 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; diff --git a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi index ccbb5de1eae..72297f48ca6 100644 --- a/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi +++ b/arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi @@ -9,40 +9,40 @@ &dpmac1 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac2 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac3 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac4 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac5 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac6 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac7 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac8 { status = "okay"; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; diff --git a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts index 179ed19bf2c..9e68c147e60 100644 --- a/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts +++ b/arch/arm/dts/fsl-ls2088a-rdb-qspi.dts @@ -24,49 +24,49 @@ &dpmac1 { status = "okay"; phy-handle = <&mdio1_phy1>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac2 { status = "okay"; phy-handle = <&mdio1_phy2>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac3 { status = "okay"; phy-handle = <&mdio1_phy3>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac4 { status = "okay"; phy-handle = <&mdio1_phy4>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac5 { status = "okay"; phy-handle = <&mdio2_phy1>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac6 { status = "okay"; phy-handle = <&mdio2_phy2>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac7 { status = "okay"; phy-handle = <&mdio2_phy3>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &dpmac8 { status = "okay"; phy-handle = <&mdio2_phy4>; - phy-connection-type = "xfi"; + phy-connection-type = "10gbase-r"; }; &emdio1 { diff --git a/arch/arm/dts/fsl-sch-30841.dtsi b/arch/arm/dts/fsl-sch-30841.dtsi index 2f1e63a6ae7..3aa7fddc32f 100644 --- a/arch/arm/dts/fsl-sch-30841.dtsi +++ b/arch/arm/dts/fsl-sch-30841.dtsi @@ -9,7 +9,7 @@ * SCH-30841 is a 4 port add-on card used with various FSL QDS boards. * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed * together on a single lane or mapped 1:1 to serdes lanes. - * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI. + * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, 10GBase-R. * PHY addresses are 0x00 - 0x03. * On the card the first port is the bottom port (closest to PEX connector). */ diff --git a/arch/arm/dts/fsl-sch-30842.dtsi b/arch/arm/dts/fsl-sch-30842.dtsi index 6a68b1849ef..b3c0c2bc35d 100644 --- a/arch/arm/dts/fsl-sch-30842.dtsi +++ b/arch/arm/dts/fsl-sch-30842.dtsi @@ -8,7 +8,7 @@ /* * SCH-30842 is a single port add-on card used with various FSL QDS boards. * It integrates a AQR112 PHY, which supports several protocols - SGMII, - * SGMII-2500, USXGMII, XFI. + * SGMII-2500, USXGMII, 10GBase-R. * PHY address is 0x02. */ phy@02 { diff --git a/board/Marvell/octeon_ebb7304/board.c b/board/Marvell/octeon_ebb7304/board.c index 9aac5f0b09f..e8e2d547c1e 100644 --- a/board/Marvell/octeon_ebb7304/board.c +++ b/board/Marvell/octeon_ebb7304/board.c @@ -339,7 +339,7 @@ void __fixup_fdt(void) case CVMX_QLM_MODE_XFI: case CVMX_QLM_MODE_RGMII_XFI: case CVMX_QLM_MODE_RGMII_XFI_1X1: - type_str = "xfi"; + type_str = "10gbase-r"; break; case CVMX_QLM_MODE_10G_KR: case CVMX_QLM_MODE_RGMII_10G_KR: @@ -393,7 +393,7 @@ void __fixup_fdt(void) if (pmd_control.s.train_en) type_str = "10G_KR"; else - type_str = "xfi"; + type_str = "10gbase-r"; break; case 4: if (pmd_control.s.train_en) @@ -618,7 +618,7 @@ static void board_configure_qlms(void) speed[qlm] = 103125; } printf("QLM %d: XLAUI\n", qlm); - } else if (!strncmp(mode_str, "xfi", 3)) { + } else if (!strncmp(mode_str, "10gbase-r", 3)) { bool rgmii = false; speed[qlm] = 103125; diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README index 913537d4519..f5aa51da87e 100644 --- a/board/freescale/ls1043aqds/README +++ b/board/freescale/ls1043aqds/README @@ -18,7 +18,7 @@ SoC overview. - SGMII, SGMII 2.5 - QSGMII - SATA 3.0 - - XFI + - 10GBase-R - DDR Controller - 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s -IFC/Local Bus diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index c3efe8a0be6..81e18f6e82b 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -242,13 +242,13 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, "qsgmii"); } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII && port == FM1_10GEC1) { - /* XFI interface */ + /* 10GBase-R interface */ f_link.phy_id = cpu_to_fdt32(port); f_link.duplex = cpu_to_fdt32(1); f_link.link_speed = cpu_to_fdt32(10000); f_link.pause = 0; f_link.asym_pause = 0; - /* no PHY for XFI */ + /* no PHY for 10GBase-R */ fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii"); diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README index 709ddbbef31..66ee578e99d 100644 --- a/board/freescale/ls1043ardb/README +++ b/board/freescale/ls1043ardb/README @@ -17,7 +17,7 @@ SoC overview. - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and standard PCIe card - QSGMII with x4 RJ45 connector - - XFI with x1 RJ45 connector + - 10GBase-R with x1 RJ45 connector - DDR Controller - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s -IFC/Local Bus diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c index 1f01c155165..fa59116ce57 100644 --- a/board/freescale/ls1043ardb/eth.c +++ b/board/freescale/ls1043ardb/eth.c @@ -65,7 +65,7 @@ int board_eth_init(struct bd_info *bis) for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) fm_info_set_mdio(i, dev); - /* XFI on lane A, MAC 9 */ + /* 10GBase-R on lane A, MAC 9 */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(FM1_10GEC1, dev); diff --git a/board/freescale/ls1046aqds/README b/board/freescale/ls1046aqds/README index b8fa32652b0..d6469019bd2 100644 --- a/board/freescale/ls1046aqds/README +++ b/board/freescale/ls1046aqds/README @@ -18,7 +18,7 @@ SoC overview. - SGMII, SGMII 2.5 - QSGMII - SATA 3.0 - - XFI + - 10GBase-R - DDR Controller - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s -IFC/Local Bus diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index 33db552adb8..23528324662 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -217,13 +217,13 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, /* Backplane KR mode: skip fixups */ printf("Interface %d in backplane KR mode\n", port); } else { - /* XFI interface */ + /* 10GBase-R interface */ f_link.phy_id = cpu_to_fdt32(port); f_link.duplex = cpu_to_fdt32(1); f_link.link_speed = cpu_to_fdt32(10000); f_link.pause = 0; f_link.asym_pause = 0; - /* no PHY for XFI */ + /* no PHY for 10GBase-R */ fdt_delprop(fdt, offset, "phy-handle"); fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link)); diff --git a/board/freescale/ls1046ardb/README b/board/freescale/ls1046ardb/README index a38c9d48300..1660f7c7cf9 100644 --- a/board/freescale/ls1046ardb/README +++ b/board/freescale/ls1046ardb/README @@ -14,8 +14,8 @@ SoC overview. LS1046ARDB board Overview ----------------------- - SERDES1 Connections, 4 lanes supporting: - - Lane0: XFI with x1 RJ45 connector - - Lane1: XFI Cage + - Lane0: 10GBase-R with x1 RJ45 connector + - Lane1: 10GBase-R Cage - Lane2: SGMII.5 - Lane3: SGMII.6 - SERDES2 Connections, 4 lanes supporting: diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c index 4905302d8cd..a3e147a48b9 100644 --- a/board/freescale/ls1046ardb/eth.c +++ b/board/freescale/ls1046ardb/eth.c @@ -67,7 +67,7 @@ int board_eth_init(struct bd_info *bis) for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) fm_info_set_mdio(i, dev); - /* XFI on lane A, MAC 9 */ + /* 10GBase-R on lane A, MAC 9 */ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME); fm_info_set_mdio(FM1_10GEC1, dev); diff --git a/board/freescale/ls1088a/README b/board/freescale/ls1088a/README index aa0fb6ac676..5315909defc 100644 --- a/board/freescale/ls1088a/README +++ b/board/freescale/ls1088a/README @@ -42,7 +42,7 @@ Alternately you can use this command to switch from QSPI to SD - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 - SATA 3.0 - - XFI + - 10GBase-R - QSGMII - DDR Controller - One ports of 72-bits (8-bits ECC, 64-bits DATA) DDR4. Each port supports four @@ -106,7 +106,7 @@ SW12 1111 1111 - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 - SATA 3.0 - - 2 XFI + - 2 10GBase-R - QSGMII, SGMII with help for Riser card - 2 RGMII - 5 slot for Riser card or PCIe NIC diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c index a8e9ef15dc4..1ba5e94d0a0 100644 --- a/board/freescale/ls1088a/eth_ls1088ardb.c +++ b/board/freescale/ls1088a/eth_ls1088ardb.c @@ -52,9 +52,9 @@ int board_eth_init(struct bd_info *bis) switch (srds_s1) { case 0x1D: /* - * XFI does not need a PHY to work, but to avoid U-boot use - * default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to XFI + * 10GBase-R does not need a PHY to work, but to avoid U-boot + * use default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to 10GBase-R * MAC error. */ wriop_set_phy_address(WRIOP1_DPMAC1, 0, 0x0a); diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README index 8e31e9e41e3..04c1941b056 100644 --- a/board/freescale/ls2080aqds/README +++ b/board/freescale/ls2080aqds/README @@ -19,7 +19,7 @@ LS2088A SoC overview. - QSGMII - SATA 3.0 - XAUI - - XFI + - 10GBase-R - DDR Controller - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four chip-selects and two DIMM connectors. Support is up to 2133MT/s. diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 914cd0a9ab5..7db37898220 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -874,13 +874,12 @@ void ls2080a_handle_phy_interface_xsgmii(int i) case 0x4B: case 0x4C: /* - * XFI does not need a PHY to work, but to avoid U-Boot use - * default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to XFI - * MAC, and should not use a real XAUI PHY address, since - * MDIO can access it successfully, and then MDIO thinks - * the XAUI card is used for the XFI MAC, which will cause - * error. + * 10GBase-R does not need a PHY to work, but to avoid U-Boot + * use default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to 10GBase-R + * MAC, and should not use a real XAUI PHY address, since MDIO + * can access it successfully, and then MDIO thinks the XAUI + * card is used for the 10GBase-R MAC, which will cause error. */ wriop_set_phy_address(i, 0, i + 4); ls2080a_qds_enable_SFP_TX(SFP_TX); diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README index 205c45cb2af..75a633ccb4e 100644 --- a/board/freescale/ls2080ardb/README +++ b/board/freescale/ls2080ardb/README @@ -18,7 +18,7 @@ LS2081A, LS2088A SoC overview. - SERDES Connections, 16 lanes supporting: - PCI Express - 3.0 - SATA 3.0 - - XFI + - 10GBase-R - DDR Controller - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four chip-selects and two DIMM connectors. Support is up to 2133MT/s. diff --git a/board/freescale/t102xrdb/README b/board/freescale/t102xrdb/README index dde3f8ca37f..84deb9562a1 100644 --- a/board/freescale/t102xrdb/README +++ b/board/freescale/t102xrdb/README @@ -39,7 +39,7 @@ The T1024 SoC includes the following function and features: - One QSGMII interface - Four SGMII interface supporting 1000 Mbps - Three SGMII interfaces supporting up to 2500 Mbps - - 10GbE XFI or 10Base-KR interface + - 10GBase-R or 10Base-KR interface - Additional peripheral interfaces - Two USB 2.0 controllers with integrated PHY - SD/eSDHC/eMMC diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index 56e6109288f..b28c5457d67 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -64,7 +64,7 @@ int board_eth_init(struct bd_info *bis) /* set the on-board RGMII2 PHY */ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR); - /* set 10G XFI with Aquantia AQR105 PHY */ + /* set 10GBase-R with Aquantia AQR105 PHY */ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR); break; #endif diff --git a/board/freescale/t208xqds/README b/board/freescale/t208xqds/README index d690857f2e2..b52d9610e98 100755 --- a/board/freescale/t208xqds/README +++ b/board/freescale/t208xqds/README @@ -55,14 +55,14 @@ Memory: - Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support Ethernet interfaces: - Two 1Gbps RGMII on-board ports - - Four 10Gbps XFI on-board cages + - Four 10GBase-R on-board cages - 1Gbps/2.5Gbps SGMII Riser card - 10Gbps XAUI Riser card Accelerator: - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC SerDes: - 16 lanes up to 10.3125GHz - - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI + - Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, 10GBase-R and XAUI IFC: - 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA eSPI: @@ -85,14 +85,14 @@ System Logic: - QIXIS-II FPGA system controll Debug Features: - Support Legacy, COP/JTAG, Aurora, Event and EVT -XFI: - - XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to +10GBase-R: + - 10GBase-R is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to a on-board SFP+ cages, which to house optical module (fiber cable) or direct attach cable(copper), the copper cable is used to emulate 10GBASE-KR scenario. - So, for XFI usage, there are two scenarios, one will use fiber cable, + So, for 10GBase-R usage, there are two scenarios, one will use fiber cable, another will use copper cable. An hwconfig env "fsl_10gkr_copper" is - introduced to indicate a XFI port will use copper cable, and U-Boot + introduced to indicate a 10GBase-R port will use copper cable, and U-Boot will fixup the dtb accordingly. It's used as: fsl_10gkr_copper:<10g_mac_name> The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they @@ -100,10 +100,10 @@ XFI: "fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable will be used by default. for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in - hwconfig, then both four XFI ports will use copper cable. + hwconfig, then both four 10GBase-R ports will use copper cable. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two - XFI ports will use copper cable, the other two XFI ports will use fiber - cable. + 10GBase-R ports will use copper cable, the other two 10GBase-R ports will use + fiber cable. 1000BASE-KX(1G-KX): - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 705387af3c3..2d7fc8bdda2 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -310,16 +310,16 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) { switch (srds_s1) { - case 0x66: /* XFI interface */ + case 0x66: /* 10GBase-R interface */ case 0x6b: case 0x6c: case 0x6d: case 0x71: /* - * if the 10G is XFI, check hwconfig to see what is the - * media type, there are two types, fiber or copper, - * fix the dtb accordingly. - */ + * Check hwconfig to see what is the media type, there + * are two types, fiber or copper, fix the dtb + * accordingly. + */ switch (port) { case FM1_10GEC1: if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) { @@ -378,7 +378,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, printf("Interface %d in backplane KR mode\n", port); } else { - /* fixed-link for XFI fiber cable */ + /* fixed-link for 10GBase-R fiber cable */ f_link.phy_id = port; f_link.duplex = 1; f_link.link_speed = 10000; @@ -538,12 +538,12 @@ int board_eth_init(struct bd_info *bis) case 0x66: case 0x67: /* - * XFI does not need a PHY to work, but to avoid U-Boot use - * default PHY address which is zero to a MAC when it found - * a MAC has no PHY address, we give a PHY address to XFI + * 10GBase-R does not need a PHY to work, but to avoid U-Boot + * use default PHY address which is zero to a MAC when it found + * a MAC has no PHY address, we give a PHY address to 10GBase-R * MAC, and should not use a real XAUI PHY address, since * MDIO can access it successfully, and then MDIO thinks - * the XAUI card is used for the XFI MAC, which will cause + * the XAUI card is used for the 10GBase-R MAC, which will cause * error. */ fm_info_set_phy_address(FM1_10GEC1, 4); @@ -701,7 +701,7 @@ int board_eth_init(struct bd_info *bis) (srds_s1 == 0x6a) || (srds_s1 == 0x70) || (srds_s1 == 0x6c) || (srds_s1 == 0x6d) || (srds_s1 == 0x71)) { - /* As XFI is in cage intead of a slot, so + /* As 10GBase-R is in cage intead of a slot, so * ensure doesn't disable the corresponding port */ break; diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 715de106d69..e54672a80ba 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -136,14 +136,14 @@ int brd_mux_lane_to_slot(void) break; case 0x66: case 0x67: - /* SD1(A:D) => XFI cage + /* SD1(A:D) => 10GBase-R cage * SD1(E:H) => SLOT1 PCIe4 */ QIXIS_WRITE(brdcfg[12], 0xfe); break; case 0x6a: case 0x6b: - /* SD1(A:D) => XFI cage + /* SD1(A:D) => 10GBase-R cage * SD1(E) => SLOT1 PCIe4 * SD1(F:H) => SLOT2 SGMII */ @@ -151,14 +151,14 @@ int brd_mux_lane_to_slot(void) break; case 0x6c: case 0x6d: - /* SD1(A:B) => XFI cage + /* SD1(A:B) => 10GBase-R cage * SD1(C:D) => SLOT3 SGMII * SD1(E:H) => SLOT1 PCIe4 */ QIXIS_WRITE(brdcfg[12], 0xda); break; case 0x6e: - /* SD1(A:B) => SFP Module, XFI + /* SD1(A:B) => SFP Module, 10GBase-R * SD1(C:D) => SLOT3 SGMII * SD1(E:F) => SLOT1 PCIe4 x2 * SD1(G:H) => SLOT2 SGMII diff --git a/board/freescale/t208xrdb/README b/board/freescale/t208xrdb/README index ec47c96f2b1..c4bfd3b466f 100644 --- a/board/freescale/t208xrdb/README +++ b/board/freescale/t208xrdb/README @@ -54,7 +54,7 @@ Differences between T2080 and T2081 T2080PCIe-RDB board Overview ---------------------------- - SERDES Configuration - - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10) + - SerDes-1 Lane A-B: to two 10GBase-R fiber (MAC9 & MAC10) - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2) - SerDes-1 Lane E-H: to PCIe Goldfinger (PCIe4 x4, Gen3) - SerDes-2 Lane A-D: to PCIe Slot (PCIe1 x4, Gen2) @@ -62,7 +62,7 @@ T2080PCIe-RDB board Overview - SerDes-2 Lane G-H: to SATA1 & SATA2 - Ethernet - Two on-board 10M/100M/1G RGMII ethernet ports - - Two on-board 10Gbps XFI fiber ports + - Two on-board 10GBase-R fiber ports - Two on-board 10Gbps Base-T copper ports - DDR Memory - Supports 72bit 4GB DDR3-LP SODIMM diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index c815a3a4fa5..34ffaa6aeb5 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -106,7 +106,7 @@ int board_eth_init(struct bd_info *bis) #if (CONFIG_SYS_NUM_FMAN == 2) if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) { - /* SGMII && XFI */ + /* SGMII && 10GBase-R */ fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5); fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6); fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7); diff --git a/doc/device-tree-bindings/net/ethernet.txt b/doc/device-tree-bindings/net/ethernet.txt index cfc376bc977..648a1aee694 100644 --- a/doc/device-tree-bindings/net/ethernet.txt +++ b/doc/device-tree-bindings/net/ethernet.txt @@ -41,7 +41,17 @@ Documentation/devicetree/bindings/phy/phy-bindings.txt. * "2500base-x", * "rxaui" * "xaui" - * "10gbase-kr" (10GBASE-KR, XFI, SFI) + * "10gbase-r" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol + used with various different mediums. Please refer to the IEEE standard for + a definition of this. Note: 10GBASE-R is just one protocol that can be used + with XFI and SFI. XFI and SFI permit multiple protocols over a single + SERDES lane, and also defines the electrical characteristics of the signals + with a host compliance board plugged into the host XFP/SFP connector. + Therefore, XFI and SFI are not PHY interface types in their own right.) + * "10gbase-kr" (This is the IEEE 802.3 Clause 49 defined 10GBASE-R with + Clause 73 autonegotiation. Please refer to the IEEE standard for further + information. Note: due to legacy usage, some 10GBASE-R usage incorrectly + makes use of this definition). - phy-connection-type: the same as "phy-mode" property but described in the Devicetree Specification; - phy-handle: phandle, specifies a reference to a node representing a PHY diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c index 5be0ad2ab3d..6e3d008199a 100644 --- a/drivers/net/fm/b4860.c +++ b/drivers/net/fm/b4860.c @@ -100,7 +100,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) env_get_f("hwconfig", buffer, sizeof(buffer)); buf = buffer; - /* check if XFI interface enable in hwconfig for 10g */ + /* check if 10GBase-R interface enable in hwconfig for 10g */ if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2", "sfp_amc", "sfp", buf)) { if ((port == FM1_10GEC1 || diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index 36f50d27826..e1f812b688b 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -98,7 +98,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, if_mode &= ~IF_MODE_MASK; if_mode |= (IF_MODE_GMII); break; - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_XGMII: if_mode &= ~IF_MODE_MASK; if_mode |= IF_MODE_XGMII; @@ -107,7 +107,7 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, break; } /* Enable automatic speed selection for Non-XGMII */ - if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_XFI) + if (type != PHY_INTERFACE_MODE_XGMII && type != PHY_INTERFACE_MODE_10GBASER) if_mode |= IF_MODE_EN_AUTO; if (type == PHY_INTERFACE_MODE_RGMII || diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c index 566cdc7e546..12d9942b65d 100644 --- a/drivers/net/fsl_enetc.c +++ b/drivers/net/fsl_enetc.c @@ -228,7 +228,7 @@ static void enetc_setup_mac_iface(struct udevice *dev, break; case PHY_INTERFACE_MODE_XGMII: case PHY_INTERFACE_MODE_USXGMII: - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: /* set ifmode to (US)XGMII */ if_mode = enetc_read_port(priv, ENETC_PM_IF_MODE); if_mode &= ~ENETC_PM_IF_IFMODE_MASK; @@ -296,7 +296,7 @@ static void enetc_start_pcs(struct udevice *dev) break; case PHY_INTERFACE_MODE_XGMII: case PHY_INTERFACE_MODE_USXGMII: - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: enetc_init_sxgmii(dev); break; }; diff --git a/drivers/net/mscc_eswitch/felix_switch.c b/drivers/net/mscc_eswitch/felix_switch.c index 859428f7cb9..1413084595d 100644 --- a/drivers/net/mscc_eswitch/felix_switch.c +++ b/drivers/net/mscc_eswitch/felix_switch.c @@ -223,7 +223,7 @@ static void felix_start_pcs(struct udevice *dev, int port, felix_init_sgmii(imdio, port, autoneg); break; case PHY_INTERFACE_MODE_XGMII: - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: case PHY_INTERFACE_MODE_USXGMII: if (felix_init_sxgmii(imdio, port)) dev_err(dev, "PCS reset timeout on port %d\n", port); diff --git a/drivers/net/phy/aquantia.c b/drivers/net/phy/aquantia.c index d3d35a75d06..66d1d985682 100644 --- a/drivers/net/phy/aquantia.c +++ b/drivers/net/phy/aquantia.c @@ -310,7 +310,7 @@ struct { AQUANTIA_VND1_GSTART_RATE_1G}, [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G, AQUANTIA_VND1_GSTART_RATE_2_5G}, - [PHY_INTERFACE_MODE_XFI] = {0x100, AQUANTIA_VND1_GSYSCFG_10G, + [PHY_INTERFACE_MODE_10GBASER] = {0x100, AQUANTIA_VND1_GSYSCFG_10G, AQUANTIA_VND1_GSTART_RATE_10G}, [PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G, AQUANTIA_VND1_GSTART_RATE_10G}, @@ -443,18 +443,18 @@ int aquantia_config(struct phy_device *phydev) return ret; } /* - * for backward compatibility convert XGMII into either XFI or USX based - * on FW config + * for backward compatibility convert XGMII into either 10GBase-R or + * USXGMII based on FW config */ if (interface == PHY_INTERFACE_MODE_XGMII) { - debug("use XFI or USXGMII SI protos, XGMII is not valid\n"); + debug("use 10GBase-R or USXGMII SI protos, XGMII is not valid\n"); reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS, AQUANTIA_SYSTEM_INTERFACE_SR); if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII) interface = PHY_INTERFACE_MODE_USXGMII; else - interface = PHY_INTERFACE_MODE_XFI; + interface = PHY_INTERFACE_MODE_10GBASER; } /* @@ -494,7 +494,7 @@ int aquantia_config(struct phy_device *phydev) case PHY_INTERFACE_MODE_USXGMII: usx_an = 1; /* FALLTHROUGH */ - case PHY_INTERFACE_MODE_XFI: + case PHY_INTERFACE_MODE_10GBASER: /* 10GBASE-T mode */ phydev->advertising = SUPPORTED_10000baseT_Full; phydev->supported = phydev->advertising; @@ -515,7 +515,7 @@ int aquantia_config(struct phy_device *phydev) phydev->dev->name); } else { reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA; - debug("%s: system interface XFI\n", + debug("%s: system interface 10GBase-R\n", phydev->dev->name); } diff --git a/include/phy.h b/include/phy.h index 6b928636b6d..b9d8dc3a61e 100644 --- a/include/phy.h +++ b/include/phy.h @@ -368,7 +368,7 @@ static inline int is_10g_interface(phy_interface_t interface) { return interface == PHY_INTERFACE_MODE_XGMII || interface == PHY_INTERFACE_MODE_USXGMII || - interface == PHY_INTERFACE_MODE_XFI; + interface == PHY_INTERFACE_MODE_10GBASER; } #endif diff --git a/include/phy_interface.h b/include/phy_interface.h index ebb18ecd40c..f075abe9c9c 100644 --- a/include/phy_interface.h +++ b/include/phy_interface.h @@ -37,7 +37,7 @@ typedef enum { PHY_INTERFACE_MODE_CAUI2, PHY_INTERFACE_MODE_CAUI4, PHY_INTERFACE_MODE_NCSI, - PHY_INTERFACE_MODE_XFI, + PHY_INTERFACE_MODE_10GBASER, PHY_INTERFACE_MODE_USXGMII, PHY_INTERFACE_MODE_NONE, /* Must be last */ @@ -69,7 +69,7 @@ static const char * const phy_interface_strings[] = { [PHY_INTERFACE_MODE_CAUI2] = "caui2", [PHY_INTERFACE_MODE_CAUI4] = "caui4", [PHY_INTERFACE_MODE_NCSI] = "NC-SI", - [PHY_INTERFACE_MODE_XFI] = "xfi", + [PHY_INTERFACE_MODE_10GBASER] = "10gbase-r", [PHY_INTERFACE_MODE_USXGMII] = "usxgmii", [PHY_INTERFACE_MODE_NONE] = "", }; -- cgit v1.3.1