From 3cbb026f17332b70d352ae3659179ca2b51f418c Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Thu, 19 Nov 2020 21:26:20 +0200 Subject: linux/compat.h: Remove debug() from spin_lock_irqsave() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It seems nobody tested the debug() option in spin_lock_irqsave(). Currently, when #define DEBUG, it spoils the compiler with In file included from drivers/usb/dwc3/gadget.c:18: drivers/usb/dwc3/gadget.c: In function ‘dwc3_gadget_set_selfpowered’: include/log.h:235:4: warning: ‘flags’ is used uninitialized in this function [-Wuninitialized] 235 | printf(pr_fmt(fmt), ##args); \ | ^~~~~~ drivers/usb/dwc3/gadget.c:1347:17: note: ‘flags’ was declared here 1347 | unsigned long flags; | ^~~~~ and so on... Drop useless debug() call to make compiler happy. Fixes: 0c06db598367 ("lib, linux: move linux specific defines to linux/compat.h") Cc: Heiko Schocher Cc: Tom Rini Signed-off-by: Andy Shevchenko Reviewed-by: Oleksandr Andrushchenko Reviewed-by: Heiko Schocher --- include/linux/compat.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/linux/compat.h b/include/linux/compat.h index 38549baa251..3d0acbd582e 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -248,7 +248,7 @@ typedef int wait_queue_head_t; #define spin_lock_init(lock) do {} while (0) #define spin_lock(lock) do {} while (0) #define spin_unlock(lock) do {} while (0) -#define spin_lock_irqsave(lock, flags) do { debug("%lu\n", flags); } while (0) +#define spin_lock_irqsave(lock, flags) do {} while (0) #define spin_unlock_irqrestore(lock, flags) do { flags = 0; } while (0) #define DEFINE_MUTEX(...) -- cgit v1.3.1 From d61e784136f16e9142ccc56b34f706b6e5002c5e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 29 Nov 2020 17:07:04 -0700 Subject: log: Fix comment for LOGC_BOOT This comment is in the wrong format, so reports an error with 'make htmldocs'. Fix it. Fixes: b73d61a5565 ("x86: zimage: Add a little more logging") Signed-off-by: Simon Glass Reviewed-by: Heinrich Schuchardt --- include/log.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/log.h b/include/log.h index 29f18a82dcf..e53afa490e8 100644 --- a/include/log.h +++ b/include/log.h @@ -96,8 +96,8 @@ enum log_category_t { LOGC_DEVRES, /** @LOGC_ACPI: Advanced Configuration and Power Interface (ACPI) */ LOGC_ACPI, - LOGC_BOOT, /* Related to boot process / boot image processing */ - + /** @LOGC_BOOT: Related to boot process / boot image processing */ + LOGC_BOOT, /** @LOGC_COUNT: Number of log categories */ LOGC_COUNT, /** @LOGC_END: Sentinel value for lists of log categories */ -- cgit v1.3.1 From d211e0418fed8adf4ffa7c31f067e367fb26a081 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sun, 29 Nov 2020 17:07:05 -0700 Subject: global_data: Fix comment for dm_driver_rt This comment is in the wrong format, so reports an error with 'make htmldocs'. Fix it. Fixes: a294ead8d25 ("dm: Use an allocated array for run-time device info") Signed-off-by: Simon Glass Reviewed-by: Heinrich Schuchardt --- include/asm-generic/global_data.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h index 87d827d0f43..887b5c268de 100644 --- a/include/asm-generic/global_data.h +++ b/include/asm-generic/global_data.h @@ -196,7 +196,7 @@ struct global_data { */ struct list_head uclass_root; # if CONFIG_IS_ENABLED(OF_PLATDATA) - /** Dynamic info about the driver */ + /** @dm_driver_rt: Dynamic info about the driver */ struct driver_rt *dm_driver_rt; # endif #endif -- cgit v1.3.1 From 9e925d0c47871c5e38e70334d6485c504c0552e0 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 30 Nov 2020 09:04:48 +0100 Subject: log: typos in include/log.h Correct several typos. Signed-off-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- include/log.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/log.h b/include/log.h index e53afa490e8..6bce5606489 100644 --- a/include/log.h +++ b/include/log.h @@ -29,7 +29,7 @@ enum log_level_t { LOGL_CRIT, /** @LOGL_ERR: Error that prevents something from working */ LOGL_ERR, - /** @LOGL_WARNING: Warning may prevent optimial operation */ + /** @LOGL_WARNING: Warning may prevent optimal operation */ LOGL_WARNING, /** @LOGL_NOTICE: Normal but significant condition, printf() */ LOGL_NOTICE, @@ -322,7 +322,7 @@ void __assert_fail(const char *assertion, const char *file, unsigned int line, * * Members marked as 'not allocated' are stored as pointers and the caller is * responsible for making sure that the data pointed to is not overwritten. - * Memebers marked as 'allocated' are allocated (e.g. via strdup()) by the log + * Members marked as 'allocated' are allocated (e.g. via strdup()) by the log * system. * * TODO(sjg@chromium.org): Compress this struct down a bit to reduce space, e.g. @@ -379,7 +379,7 @@ struct log_driver { * the run-time aspects of drivers (currently just a list of filters to apply * to records send to this device). * - * @next_filter_num: Seqence number of next filter filter added (0=no filters + * @next_filter_num: Sequence number of next filter filter added (0=no filters * yet). This increments with each new filter on the device, but never * decrements * @flags: Flags for this filter (enum log_device_flags) @@ -412,7 +412,7 @@ enum log_filter_flags { }; /** - * struct log_filter - criterial to filter out log messages + * struct log_filter - criteria to filter out log messages * * If a message matches all criteria, then it is allowed. If LOGFF_DENY is set, * then it is denied instead. -- cgit v1.3.1 From 4cb8a10f7e6f50a8c71e41df1207264266bfa305 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Thu, 5 Nov 2020 10:15:37 +0100 Subject: remove obsolete option CONFIG_JFFS2_CMDLINE This option is obsolete since 2009 and can be removed globally. CC: Stefan Roese Signed-off-by: Holger Brunck Reviewed-by: Stefan Roese --- include/configs/ethernut5.h | 1 - include/configs/km/km-powerpc.h | 2 -- include/configs/kmp204x.h | 3 --- include/configs/pm9263.h | 1 - include/configs/stmark2.h | 1 - scripts/config_whitelist.txt | 1 - 6 files changed, 9 deletions(-) (limited to 'include') diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index b513b4bc68a..ca249d9d2b5 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -62,7 +62,6 @@ /* JFFS2 */ #ifdef CONFIG_CMD_JFFS2 -#define CONFIG_JFFS2_CMDLINE #define CONFIG_JFFS2_NAND #endif diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h index 7bfe12fecbb..3be926c1031 100644 --- a/include/configs/km/km-powerpc.h +++ b/include/configs/km/km-powerpc.h @@ -9,8 +9,6 @@ /* Do boardspecific init for all boards */ -#define CONFIG_JFFS2_CMDLINE - /* EEprom support 24C08, 24C16, 24C64 */ #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */ diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h index ec1254e747b..d1eb7b574b4 100644 --- a/include/configs/kmp204x.h +++ b/include/configs/kmp204x.h @@ -337,9 +337,6 @@ int get_scl(void); * additionnal command line configuration. */ -/* we don't need flash support */ -#undef CONFIG_JFFS2_CMDLINE - /* * For booting Linux, the board info and command line data * have to be in the first 64 MB of memory, since this is diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 0ed4b1aaa27..6c882b6ff94 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -190,7 +190,6 @@ #endif -#define CONFIG_JFFS2_CMDLINE 1 #define CONFIG_JFFS2_NAND 1 #define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index d9a2f75e738..da162cbb114 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -49,7 +49,6 @@ #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 /* spi not partitions */ -#define CONFIG_JFFS2_CMDLINE #define CONFIG_JFFS2_DEV "nor0" /* Timer */ diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 8b4fcba395a..c0339dcc00d 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -848,7 +848,6 @@ CONFIG_IRAM_STACK CONFIG_IRAM_TOP CONFIG_IRDA_BASE CONFIG_IS_ENABLED -CONFIG_JFFS2_CMDLINE CONFIG_JFFS2_DEV CONFIG_JFFS2_LZO CONFIG_JFFS2_NAND -- cgit v1.3.1 From a6cd384b9c37596ca9035f26922dd65991ddcb85 Mon Sep 17 00:00:00 2001 From: Holger Brunck Date: Thu, 5 Nov 2020 10:28:51 +0100 Subject: km/common: remove CONFIG_MTD_CONCAT This was used for a board which is not supproted anymore and can therefore be dropped. CC: Stefan Roese Signed-off-by: Holger Brunck Reviewed-by: Stefan Roese --- include/configs/km/keymile-common.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 851b13e063d..ad0041d8a94 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -32,9 +32,6 @@ */ #define CONFIG_BOOTP_BOOTFILESIZE -/* UBI Support for all Keymile boards */ -#define CONFIG_MTD_CONCAT - #ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS #define CONFIG_KM_DEF_ENV_BOOTPARAMS \ "actual_bank=0\0" -- cgit v1.3.1 From 8e487f38cc6408d0045194eec2271695da31b321 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 12 Sep 2019 11:12:55 +0200 Subject: apalis/colibri_t30: add note about colibri vs. nvidia uart mapping The following mapping is applicable for Apalis T30: Apalis UART1: NVIDIA UARTA Apalis UART2: NVIDIA UARTD Apalis UART3: NVIDIA UARTB Apalis UART4: NVIDIA UARTC The following mapping is applicable for Colibri T30: Colibri UART-A: NVIDIA UARTA Colibri UART-B: NVIDIA UARTD Colibri UART-C: NVIDIA UARTB Signed-off-by: Marcel Ziswiler Reviewed-by: Igor Opaniuk Signed-off-by: Tom Warren --- include/configs/apalis_t30.h | 9 ++++++++- include/configs/colibri_t30.h | 8 +++++++- 2 files changed, 15 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h index bf0aefda2ad..f0c003d2fe0 100644 --- a/include/configs/apalis_t30.h +++ b/include/configs/apalis_t30.h @@ -12,7 +12,14 @@ #include "tegra30-common.h" -/* Board-specific serial config */ +/* + * Board-specific serial config + * + * Apalis UART1: NVIDIA UARTA + * Apalis UART2: NVIDIA UARTD + * Apalis UART3: NVIDIA UARTB + * Apalis UART4: NVIDIA UARTC + */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h index fa0fa93b030..94802a66f7a 100644 --- a/include/configs/colibri_t30.h +++ b/include/configs/colibri_t30.h @@ -14,7 +14,13 @@ /* High-level configuration options */ -/* Board-specific serial config */ +/* + * Board-specific serial config + * + * Colibri UART-A: NVIDIA UARTA + * Colibri UART-B: NVIDIA UARTD + * Colibri UART-C: NVIDIA UARTB + */ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE -- cgit v1.3.1 From 632fb978a513e22e4cbc8410156a185716216649 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 2 Apr 2020 00:28:54 +0100 Subject: arm: tegra: define fdtfile option for distro boot For booting via UEFI we need to define the fdtfile option so bootefi has the option to load a fdtfile from disk. For arm64 the kernel dtb is located in a vendor directory so we define that as nvidia for that architecture. Signed-off-by: Peter Robinson Signed-off-by: Tom Warren --- include/configs/tegra-common.h | 6 ++++++ include/configs/tegra114-common.h | 1 + include/configs/tegra124-common.h | 1 + include/configs/tegra186-common.h | 1 + include/configs/tegra20-common.h | 1 + include/configs/tegra210-common.h | 1 + include/configs/tegra30-common.h | 1 + 7 files changed, 12 insertions(+) (limited to 'include') diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 2b968917d34..432eceaf351 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -49,6 +49,12 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +#ifdef CONFIG_ARM64 +#define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#else +#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" +#endif + /*----------------------------------------------------------------------- * Physical Memory Map */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index d3a70456976..9d751b67404 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -50,6 +50,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index 522993b958a..0eb8f928091 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -52,6 +52,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h index b4936cc731f..5c3ad35c766 100644 --- a/include/configs/tegra186-common.h +++ b/include/configs/tegra186-common.h @@ -49,6 +49,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 1e31d82574a..fdd89969554 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -51,6 +51,7 @@ "scriptaddr=0x10000000\0" \ "pxefile_addr_r=0x10100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x03000000\0" \ "ramdisk_addr_r=0x03100000\0" diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h index 1b8e94b60cc..2226effe16a 100644 --- a/include/configs/tegra210-common.h +++ b/include/configs/tegra210-common.h @@ -46,6 +46,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83200000\0" diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index 54bc6756abe..6c5dc24b266 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -47,6 +47,7 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x83000000\0" \ "ramdisk_addr_r=0x83100000\0" -- cgit v1.3.1 From fe669925cb4276b881a0b444e660378293585093 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Thu, 2 Apr 2020 00:28:55 +0100 Subject: arm: tegra: add options for BOOTENV_EFI_SET_FDTFILE_FALLBACK for tegra186 Upstream linux DT naming doesn't align with the U-Boot DT, which may not always be the case so this allows using BOOTENV_EFI_SET_FDTFILE_FALLBACK where it might be appropriate for some boards. Signed-off-by: Peter Robinson Signed-off-by: Tom Warren --- include/config_distro_bootcmd.h | 2 ++ include/configs/tegra186-common.h | 7 ++++++- 2 files changed, 8 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index ff29ef5a905..82a3a365c5b 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -118,8 +118,10 @@ "setenv efi_fdtfile ${soc}-${board}${boardver}.dtb; " \ "fi; " #else +#ifndef BOOTENV_EFI_SET_FDTFILE_FALLBACK #define BOOTENV_EFI_SET_FDTFILE_FALLBACK #endif +#endif #define BOOTENV_SHARED_EFI \ diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h index 5c3ad35c766..d5f21e09072 100644 --- a/include/configs/tegra186-common.h +++ b/include/configs/tegra186-common.h @@ -20,6 +20,12 @@ /* Generic Interrupt Controller */ #define CONFIG_GICV2 +#undef FDTFILE +#define BOOTENV_EFI_SET_FDTFILE_FALLBACK \ + "if test -z \"${fdtfile}\" -a -n \"${soc}\"; then " \ + "setenv efi_fdtfile ${vendor}/${soc}-${board}${boardver}.dtb; " \ + "fi; " + /* * Memory layout for where various images get loaded by boot scripts: * @@ -49,7 +55,6 @@ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdtfile=" FDTFILE "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" -- cgit v1.3.1 From 4f5128ff899d0cb13a7b010f6dbffd0aba71bb25 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 18 Jun 2020 09:41:34 +0200 Subject: configs: cei-tk1-som: remove CONFIG_ARMV7_PSCI in include file Activate ARCH_SUPPORT_PSCI as other TEGRA124 target and remove CONFIG_ARMV7_PSCI and CONFIG_ARMV7_PSCI_NR_CPUS in configs file as they are migrated in Kconfig. Select CONFIG_ARMV7_PSCI_0_1 (the first PSCI version), because CONFIG_ARMV7_PSCI_0_2 and CONFIG_ARMV7_PSCI_1_0 are not activated in this product. Hi, This patch depend on the previous serie [1]. I don't test this patch on real hardware but after this patch the size of the binary don't change. In .config we have: CONFIG_ARCH_SUPPORT_PSCI=y CONFIG_ARMV7_PSCI=y # CONFIG_ARMV7_PSCI_1_0 is not set # CONFIG_ARMV7_PSCI_0_2 is not set CONFIG_ARMV7_PSCI_0_1=y CONFIG_ARMV7_PSCI_NR_CPUS=4 In u-boot.cfg, this patch only add the 2 lines #define CONFIG_ARCH_SUPPORT_PSCI 1 #define CONFIG_ARMV7_PSCI_0_1 1 [1] "Convert CONFIG_ARMV7_PSCI_1_0 and CONFIG_ARMV7_PSCI_0_2 to Kconfig" http://patchwork.ozlabs.org/project/uboot/list/?series=184029 Regards Patrick END Signed-off-by: Patrick Delaunay Reviewed-by: Peter Chubb Signed-off-by: Tom Warren --- arch/arm/mach-tegra/tegra124/Kconfig | 1 + configs/cei-tk1-som_defconfig | 1 + include/configs/cei-tk1-som.h | 2 -- 3 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig index 6fa31ea0a16..fb016aa46c9 100644 --- a/arch/arm/mach-tegra/tegra124/Kconfig +++ b/arch/arm/mach-tegra/tegra124/Kconfig @@ -19,6 +19,7 @@ config TARGET_JETSON_TK1 config TARGET_CEI_TK1_SOM bool "Colorado Engineering Inc Tegra124 TK1-som board" + select ARCH_SUPPORT_PSCI select BOARD_LATE_INIT select CPU_V7_HAS_NONSEC if !SPL_BUILD select CPU_V7_HAS_VIRT if !SPL_BUILD diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index a1b494ec0f1..987e3ac8e95 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -7,6 +7,7 @@ CONFIG_ENV_OFFSET=0xFFFFE000 CONFIG_SPL_TEXT_BASE=0x80108000 CONFIG_TEGRA124=y CONFIG_TARGET_CEI_TK1_SOM=y +CONFIG_ARMV7_PSCI_0_1=y CONFIG_DEFAULT_DEVICE_TREE="tegra124-cei-tk1-som" CONFIG_OF_SYSTEM_SETUP=y CONFIG_CONSOLE_MUX=y diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h index dd3bdacc2c4..2c406d31866 100644 --- a/include/configs/cei-tk1-som.h +++ b/include/configs/cei-tk1-som.h @@ -28,8 +28,6 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" -#define CONFIG_ARMV7_PSCI 1 -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 /* Reserve top 1M for secure RAM */ #define CONFIG_ARMV7_SECURE_BASE 0xfff00000 #define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 -- cgit v1.3.1 From 3cf02f5ffa4f85c3934495cddae1f39bc61314b6 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 30 Nov 2020 20:46:02 +0100 Subject: imx6: remove not longer supported aristainetos boards Removed aristainetos2, 2b, 2b-csl. This boards have been recalled and destroyed. Adapt board code to remove stuff not needed anymore. Fix checkpatch warning, remove fdt_high and initrd_high from default environment. Signed-off-by: Heiko Schocher zu remove --- arch/arm/dts/Makefile | 7 - arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi | 13 - arch/arm/dts/imx6dl-aristainetos2_4.dts | 51 ---- arch/arm/dts/imx6dl-aristainetos2_4.dtsi | 84 ------ arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi | 19 -- arch/arm/dts/imx6dl-aristainetos2_7.dts | 16 - arch/arm/dts/imx6dl-aristainetos2_7.dtsi | 11 +- arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi | 13 - arch/arm/dts/imx6dl-aristainetos2b_4.dts | 50 ---- arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi | 19 -- arch/arm/dts/imx6dl-aristainetos2b_7.dts | 16 - .../dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi | 13 - arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts | 50 ---- .../dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi | 19 -- arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts | 16 - arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi | 13 - arch/arm/dts/imx6dl-aristainetos2c_4.dts | 50 ---- arch/arm/dts/imx6dl-aristainetos2c_7.dts | 2 +- arch/arm/dts/imx6qdl-aristainetos2-common.dtsi | 23 +- arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi | 22 -- arch/arm/dts/imx6qdl-aristainetos2.dtsi | 244 --------------- arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi | 77 ----- arch/arm/dts/imx6qdl-aristainetos2b.dtsi | 266 ----------------- .../arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi | 77 ----- arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi | 248 ---------------- arch/arm/dts/imx6qdl-aristainetos2c.dtsi | 12 +- arch/arm/mach-imx/mx6/Kconfig | 33 --- board/aristainetos/Kconfig | 36 --- board/aristainetos/MAINTAINERS | 29 +- board/aristainetos/aristainetos.c | 263 +++-------------- board/aristainetos/common/Kconfig | 5 +- configs/aristainetos2_defconfig | 121 -------- configs/aristainetos2b_defconfig | 115 -------- configs/aristainetos2bcsl_defconfig | 115 -------- configs/aristainetos2c_defconfig | 6 +- include/configs/aristainetos2.h | 326 ++++++++++----------- 36 files changed, 249 insertions(+), 2231 deletions(-) delete mode 100644 arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2_4.dts delete mode 100644 arch/arm/dts/imx6dl-aristainetos2_4.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2_7.dts delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_4.dts delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_7.dts delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts delete mode 100644 arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6dl-aristainetos2c_4.dts delete mode 100644 arch/arm/dts/imx6qdl-aristainetos2.dtsi delete mode 100644 arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6qdl-aristainetos2b.dtsi delete mode 100644 arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi delete mode 100644 arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi delete mode 100644 configs/aristainetos2_defconfig delete mode 100644 configs/aristainetos2b_defconfig delete mode 100644 configs/aristainetos2bcsl_defconfig (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e2e8a5fb7a6..457ccfe08ff 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -643,13 +643,6 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),) dtb-y += \ - imx6dl-aristainetos2_4.dtb \ - imx6dl-aristainetos2_7.dtb \ - imx6dl-aristainetos2b_4.dtb \ - imx6dl-aristainetos2b_7.dtb \ - imx6dl-aristainetos2b_csl_4.dtb \ - imx6dl-aristainetos2b_csl_7.dtb \ - imx6dl-aristainetos2c_4.dtb \ imx6dl-aristainetos2c_7.dtb \ imx6dl-brppt2.dtb \ imx6dl-cubox-i.dtb \ diff --git a/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi deleted file mode 100644 index ac7052c7b76..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -#include - -&lcd_panel { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_4.dts b/arch/arm/dts/imx6dl-aristainetos2_4.dts deleted file mode 100644 index 0157e244ae4..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_4.dts +++ /dev/null @@ -1,51 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * parts for 4.3 inch LG display on spi1 port0 - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -/dts-v1/; - -#include "imx6dl-aristainetos2_4.dtsi" -#include "imx6qdl-aristainetos2.dtsi" - -/ { - model = "aristainetos2 i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - -}; - -&ecspi1 { - lcd_panel: display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <0>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_4.dtsi b/arch/arm/dts/imx6dl-aristainetos2_4.dtsi deleted file mode 100644 index be4601b4b2b..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_4.dtsi +++ /dev/null @@ -1,84 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * parts for 4.3 inch LG display on the parallel port and atmel maxtouch - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -/dts-v1/; -#include "imx6dl.dtsi" - -/ { - display0: disp0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - - port@0 { - reg = <0>; - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; -}; - -&i2c3 { - touch: touch@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&iomuxc { - pinctrl_ipu_disp: ipudisp1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 - >; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi deleted file mode 100644 index 25bc562064b..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -#include -/ { - vdd_panel_reg: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "panel_regulator"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&panel0 { - power-supply = <&vdd_panel_reg>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7.dts b/arch/arm/dts/imx6dl-aristainetos2_7.dts deleted file mode 100644 index 0d1e83cb686..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2_7.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -/dts-v1/; -#include "imx6dl-aristainetos2_7.dtsi" -#include "imx6qdl-aristainetos2.dtsi" - -/ { - model = "aristainetos2 i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7.dtsi b/arch/arm/dts/imx6dl-aristainetos2_7.dtsi index 52d6a517a7f..ec633b8ed1c 100644 --- a/arch/arm/dts/imx6dl-aristainetos2_7.dtsi +++ b/arch/arm/dts/imx6dl-aristainetos2_7.dtsi @@ -1,7 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0) /* * support for the imx6 based aristainetos2 board - * parts for 7 inch LG display connected to the LVDS port and atmel maxtouch + * parts for 7 inch LG display connected to the LVDS port * * Copyright (C) 2019 Heiko Schocher * Copyright (C) 2015 Heiko Schocher @@ -26,15 +26,6 @@ }; }; -&i2c3 { - touch: touch@4d { - compatible = "atmel,maxtouch"; - reg = <0x4d>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - &ldb { status = "okay"; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi deleted file mode 100644 index ee02df39c15..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -#include - -&lcd_panel { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_4.dts b/arch/arm/dts/imx6dl-aristainetos2b_4.dts deleted file mode 100644 index a48a25c1195..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_4.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2b board - * parts for 4.3 inch LG display on spi1 port1 - * - * Copyright (C) 2019 Heiko Schocher - * - */ -/dts-v1/; - -#include "imx6dl-aristainetos2_4.dtsi" -#include "imx6qdl-aristainetos2b.dtsi" - -/ { - model = "aristainetos2b i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - -}; - -&ecspi1 { - lcd_panel: display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <1>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi deleted file mode 100644 index 0cb4f1974b9..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -#include -/ { - vdd_panel_reg: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "panel_regulator"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&panel0 { - power-supply = <&vdd_panel_reg>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_7.dts b/arch/arm/dts/imx6dl-aristainetos2b_7.dts deleted file mode 100644 index f1496cbfdd9..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_7.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -/dts-v1/; -#include "imx6dl-aristainetos2_7.dtsi" -#include "imx6qdl-aristainetos2b.dtsi" - -/ { - model = "aristainetos2b i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi deleted file mode 100644 index 654ac122a16..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -#include - -&lcd_panel { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts b/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts deleted file mode 100644 index bfbb799f20c..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2b csl board - * parts for 4.3 inch LG display on spi1 port1 - * - * Copyright (C) 2019 Heiko Schocher - * - */ -/dts-v1/; - -#include "imx6dl-aristainetos2_4.dtsi" -#include "imx6qdl-aristainetos2b_csl.dtsi" - -/ { - model = "aristainetos2b csl i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - -}; - -&ecspi1 { - lcd_panel: display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <1>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi deleted file mode 100644 index 70d195ecbfe..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi +++ /dev/null @@ -1,19 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -#include -/ { - vdd_panel_reg: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "panel_regulator"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -&panel0 { - power-supply = <&vdd_panel_reg>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts b/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts deleted file mode 100644 index ecf767da6ce..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -/dts-v1/; -#include "imx6dl-aristainetos2_7.dtsi" -#include "imx6qdl-aristainetos2b_csl.dtsi" - -/ { - model = "aristainetos2b csl i.MX6 Dual Lite Board 7"; - compatible = "fsl,imx6dl"; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi deleted file mode 100644 index 052d51852b9..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi +++ /dev/null @@ -1,13 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -#include - -&lcd_panel { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - backlight = <&backlight>; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_4.dts b/arch/arm/dts/imx6dl-aristainetos2c_4.dts deleted file mode 100644 index 142b108acec..00000000000 --- a/arch/arm/dts/imx6dl-aristainetos2c_4.dts +++ /dev/null @@ -1,50 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2c board - * parts for 4.3 inch LG display on spi1 port1 - * - * Copyright (C) 2019 Heiko Schocher - * - */ -/dts-v1/; - -#include "imx6dl-aristainetos2_4.dtsi" -#include "imx6qdl-aristainetos2c.dtsi" - -/ { - model = "aristainetos2c i.MX6 Dual Lite Board 4"; - compatible = "fsl,imx6dl"; - -}; - -&ecspi1 { - lcd_panel: display@0 { - compatible = "lg,lg4573"; - spi-max-frequency = <10000000>; - reg = <1>; - power-on-delay = <10>; - - display-timings { - 480x800p57 { - native-mode; - clock-frequency = <27000027>; - hactive = <480>; - vactive = <800>; - hfront-porch = <10>; - hback-porch = <59>; - hsync-len = <10>; - vback-porch = <15>; - vfront-porch = <15>; - vsync-len = <15>; - hsync-active = <1>; - vsync-active = <1>; - }; - }; - - port { - panel_in: endpoint { - remote-endpoint = <&display_out>; - }; - }; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_7.dts b/arch/arm/dts/imx6dl-aristainetos2c_7.dts index 35435e1c104..00eec82bf49 100644 --- a/arch/arm/dts/imx6dl-aristainetos2c_7.dts +++ b/arch/arm/dts/imx6dl-aristainetos2c_7.dts @@ -11,6 +11,6 @@ #include "imx6qdl-aristainetos2c.dtsi" / { - model = "aristainetos2c i.MX6 Dual Lite Board 7"; + model = "aristainetos2c+2d i.MX6 Dual Lite Boards 7"; compatible = "fsl,imx6dl"; }; diff --git a/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi b/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi index 2aa531b1ab7..570143694e8 100644 --- a/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi +++ b/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0) /* - * support for the imx6 based aristainetos2 board + * support for the imx6 based aristainetos2 boards * parts common to all versions * * Copyright (C) 2019 Heiko Schocher @@ -13,6 +13,8 @@ / { aliases { eeprom0 = &i2c_eeprom0; + eeprom1 = &i2c_eeprom1; + eeprom2 = &i2c_eeprom2; pmic0 = &i2c_pmic0; }; @@ -250,6 +252,12 @@ }; }; + i2c_eeprom2: eeprom@57{ + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; + rtc@68 { compatible = "st,m41t11"; reg = <0x68>; @@ -274,6 +282,19 @@ }; }; +&gpio2 { + tpm_pp { + gpio-hog; + output-low; + gpios = <17 GPIO_ACTIVE_HIGH>; + }; + tpm_reset { + gpio-hog; + output-high; + gpios = <18 GPIO_ACTIVE_HIGH>; + }; +}; + &gpio6 { spi_bus_ena { gpio-hog; diff --git a/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi index c713efd84c7..3063f01d700 100644 --- a/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi +++ b/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi @@ -50,28 +50,6 @@ }; }; -&iomuxc { - pinctrl-0 = <&pinctrl_gpio &pinctrl_gpio_fix>; - u-boot,dm-pre-reloc; - - pinctrl_gpio_fix: gpiofixgrp { - /* - * usdhc2 has a levelshifter on the carrier board Rev. DV1, - * that will automatically detect the driving direction. - * During initialisation this isn't working correctly, - * which causes DAT3 to be driven low towards the SD-card. - * This causes a SD-card enetring the SPI-Mode - * and therefore getting inaccessible until next power cycle. - * As workaround we drive the DAT3 line as GPIO and set it high. - * This makes usdhc2 unusable in u-boot, but works for the - * initialisation in Linux - */ - fsl,pins = < - MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x20000 - >; - }; -}; - &gpio1 { usdhc_fix { gpio-hog; diff --git a/arch/arm/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/dts/imx6qdl-aristainetos2.dtsi deleted file mode 100644 index 788e13edad0..00000000000 --- a/arch/arm/dts/imx6qdl-aristainetos2.dtsi +++ /dev/null @@ -1,244 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2 board - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -#include -#include - -#include "imx6qdl-aristainetos2-common.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - LED_blue { - label = "led_blue"; - gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; - }; - - LED_green { - label = "led_green"; - gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; - }; - - LED_red { - label = "led_red"; - gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; - }; - - LED_yellow { - label = "led_yellow"; - gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; - }; - - LED_ena { - label = "led_ena"; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH - &gpio4 10 GPIO_ACTIVE_HIGH - &gpio4 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; -}; - -&ecspi4 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; - pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - - flash: m25p80@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <1>; - }; -}; - -&gpio7 { - sd2_driver_ena { - gpio-hog; - output-high; - gpios = <8 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */ - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 /* WP pin */ - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - /* led enable */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 - /* LCD power enable */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 - /* led yellow */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 - /* led red */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 - /* led green */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 - /* led blue */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 - /* Profibus IRQ */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - /* FPGA IRQ currently unused*/ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 - /* Display reset because of clock failure */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 - /* spi bus #2 SS driver enable */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 - /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 - /* USB_OTG_ID = GPIO1_24*/ - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x4001b0b0 - /* Touchscreen IRQ */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - /* PCIe reset */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 - >; - }; - - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - /* SD1 card detect input */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 - /* SD1 write protect input */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 - /* SD2 level shifter output enable */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 - /* SD2 card detect input */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - /* SD2 write protect input */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi deleted file mode 100644 index 88826a2634c..00000000000 --- a/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -/ { - chosen { - u-boot,dm-pre-reloc; - stdout-path = &uart2; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdog1>; - }; -}; - -&uart2 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_gpio { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart2 { - u-boot,dm-pre-reloc; -}; - -&iomuxc { - u-boot,dm-pre-reloc; -}; - -&aips2 { - u-boot,dm-pre-reloc; -}; - -&backlight { - pwms = <&pwm1 0 300000>; - default-brightness-level = <2>; -}; - -/* - * allow switching write protect / reset pin by gpio, - * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot - */ -&gpio2 { - u-boot,dm-pre-reloc; - - wp_spi_nor { - gpio-hog; - output-high; - gpios = <15 GPIO_ACTIVE_HIGH>; - }; - - reset_spi_nor { - gpio-hog; - output-high; - gpios = <28 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpio4 { - u-boot,dm-pre-reloc; -}; - -&ecspi1 { - u-boot,dm-pre-reloc; -}; - -&flash { - u-boot,dm-pre-reloc; -}; - -&pinctrl_ecspi1 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b.dtsi deleted file mode 100644 index 7d92ea2af7e..00000000000 --- a/arch/arm/dts/imx6qdl-aristainetos2b.dtsi +++ /dev/null @@ -1,266 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2b board - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -#include -#include - -#include "imx6qdl-aristainetos2-common.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - LED_blue { - label = "led_blue"; - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - }; - - LED_green { - label = "led_green"; - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - }; - - LED_red { - label = "led_red"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; - }; - - LED_yellow { - label = "led_yellow"; - gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; - }; - - LED_ena { - label = "led_ena"; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH - &gpio4 10 GPIO_ACTIVE_HIGH - &gpio4 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; - pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&ecspi4 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; -}; - -&i2c1 { - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; -}; - -&gpio7 { - sd2_driver_ena { - gpio-hog; - output-high; - gpios = <8 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; - no-1-8-v; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - /* - * comment out this line to make the WiFi Eval-Module work in - * SD-Slot2, and add line: - * broken-cd; - * causes 6% CPU load if no WiFi module installed (polling) - */ - cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* SS0# */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 - /* SS1# */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 - /* SS2# */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 - /* WP pin NOR Flash */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 - /* Flash nReset */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - /* led enable */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 - /* LCD power enable */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 - /* led yellow */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 - /* led red */ - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 - /* led green */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 - /* led blue */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 - /* Profibus IRQ */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - /* FPGA IRQ currently unused*/ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 - /* Display reset because of clock failure */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 - /* spi bus #2 SS driver enable */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 - /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 - /* Touchscreen IRQ */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - /* PCIe reset */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 - /* make sure pin is GPIO and not ENET_REF_CLK */ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 - /* SD2 level shifter output enable / SD2 Reset# */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 - >; - }; - - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - /* SD1 card detect input */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 - /* SD1 write protect input */ - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 - /* SD2 card detect input */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 - /* SD2 write protect input */ - MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 - >; - }; -}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi deleted file mode 100644 index 8c2ed700751..00000000000 --- a/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ or X11 -/* - * Copyright (C) 2019 Heiko Schocher - */ - -/ { - chosen { - u-boot,dm-pre-reloc; - stdout-path = &uart1; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdog1>; - }; -}; - -&uart1 { - u-boot,dm-pre-reloc; -}; - -&pinctrl_gpio { - u-boot,dm-pre-reloc; -}; - -&pinctrl_uart1 { - u-boot,dm-pre-reloc; -}; - -&iomuxc { - u-boot,dm-pre-reloc; -}; - -&aips1 { - u-boot,dm-pre-reloc; -}; - -&backlight { - pwms = <&pwm1 0 300000>; - default-brightness-level = <2>; -}; - -/* - * allow switching write protect / reset pin by gpio, - * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot - */ -&gpio2 { - u-boot,dm-pre-reloc; - - wp_spi_nor { - gpio-hog; - output-high; - gpios = <15 GPIO_ACTIVE_HIGH>; - }; - - reset_spi_nor { - gpio-hog; - output-high; - gpios = <28 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpio4 { - u-boot,dm-pre-reloc; -}; - -&ecspi1 { - u-boot,dm-pre-reloc; -}; - -&flash { - u-boot,dm-pre-reloc; -}; - -&pinctrl_ecspi1 { - u-boot,dm-pre-reloc; -}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi deleted file mode 100644 index fa4dadefb65..00000000000 --- a/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0) -/* - * support for the imx6 based aristainetos2b-csl board - * - * Copyright (C) 2019 Heiko Schocher - * Copyright (C) 2015 Heiko Schocher - * - */ -#include -#include - -#include "imx6qdl-aristainetos2-common.dtsi" - -/ { - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - LED_blue { - label = "led_blue"; - gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; - }; - - LED_green { - label = "led_green"; - gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; - }; - - LED_red { - label = "led_red"; - gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; - }; - - LED_yellow { - label = "led_yellow"; - gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; - }; - - LED_blue_2 { - label = "led_blue2"; - gpios = <&expander 15 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - LED_green_2 { - label = "led_green2"; - gpios = <&expander 14 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - LED_red_2 { - label = "led_red2"; - gpios = <&expander 12 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - LED_yellow_2 { - label = "led_yellow2"; - gpios = <&expander 13 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; - - LED_ena { - label = "led_ena"; - gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&ecspi1 { - fsl,spi-num-chipselects = <3>; - cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH - &gpio4 10 GPIO_ACTIVE_HIGH - &gpio4 11 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi1>; - status = "okay"; - pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; - pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; - - flash: m25p80@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q128a11", "jedec,spi-nor"; - spi-max-frequency = <20000000>; - reg = <0>; - }; -}; - -&ecspi4 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi4>; - status = "okay"; -}; - -&i2c1 { - tpm@20 { - compatible = "infineon,slb9645tt"; - reg = <0x20>; - }; -}; - -&gpio7 { - wlan_reset { - gpio-hog; - output-high; - gpios = <8 GPIO_ACTIVE_HIGH>; - }; -}; - -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>; - no-1-8-v; - status = "okay"; -}; - -&iomuxc { - pinctrl_ecspi1: ecspi1grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 - MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 - MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 - /* SS0# */ - MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 - /* SS1# */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 - /* SS2# */ - MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 - /* WP pin NOR Flash */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 - /* Flash nReset */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 - >; - }; - - pinctrl_ecspi4: ecspi4grp { - fsl,pins = < - MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 - MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 - MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ - >; - }; - - pinctrl_gpio: gpiogrp { - fsl,pins = < - /* led enable */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 - /* LCD power enable */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 - /* led yellow */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 - /* led red */ - MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 - /* led green */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 - /* led blue */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 - /* Profibus IRQ */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - /* FPGA IRQ currently unused*/ - MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 - /* Display reset because of clock failure */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 - /* spi bus #2 SS driver enable */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 - /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 - /* Touchscreen IRQ */ - MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 - /* PCIe reset */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 - /* make sure pin is GPIO and not ENET_REF_CLK */ - MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 - /* WLAN Module Reset# */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 - >; - }; - - pinctrl_gpmi_nand: gpmi-nand { - fsl,pins = < - MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 - MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 - MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 - MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 - MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 - MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 - MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 - MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 - MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 - MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 - MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 - MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 - MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 - MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 - MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 - >; - }; - - pinctrl_usbotg: usbotggrp { - fsl,pins = < - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 - MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 - MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 - MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 - MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 - MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 - MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 - /* SD1 card detect input */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 - >; - }; -}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2c.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi index ba13d55f419..70c0177d295 100644 --- a/arch/arm/dts/imx6qdl-aristainetos2c.dtsi +++ b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0) /* - * support for the imx6 based aristainetos2c board + * support for the imx6 based aristainetos2c+2d boards * * Copyright (C) 2019 Heiko Schocher * Copyright (C) 2015 Heiko Schocher @@ -79,6 +79,14 @@ }; }; +&gpio7 { + eMMC_reset { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + }; +}; + &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; @@ -172,6 +180,8 @@ MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0 /* TPM Reset */ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 + /* eMMC Reset# */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 >; }; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 0646b7369c2..9d6c3440642 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -128,39 +128,6 @@ config TARGET_APALIS_IMX6 imply CMD_DM imply CMD_SATA -config TARGET_ARISTAINETOS2 - bool "aristainetos2" - depends on MX6DL - select BOARD_LATE_INIT - select SYS_I2C_MXC - select MXC_UART - select FEC_MXC - select DM - imply CMD_SATA - imply CMD_DM - -config TARGET_ARISTAINETOS2B - bool "Support aristainetos2-revB" - depends on MX6DL - select BOARD_LATE_INIT - select SYS_I2C_MXC - select MXC_UART - select FEC_MXC - select DM - imply CMD_SATA - imply CMD_DM - -config TARGET_ARISTAINETOS2BCSL - bool "Support aristainetos2-revB CSL" - depends on MX6DL - select BOARD_LATE_INIT - select SYS_I2C_MXC - select MXC_UART - select FEC_MXC - select DM - imply CMD_SATA - imply CMD_DM - config TARGET_ARISTAINETOS2C bool "Support aristainetos2-revC" depends on MX6DL diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 2ad3dbd56cb..d67002503dd 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -1,39 +1,3 @@ -if TARGET_ARISTAINETOS2 - -source "board/aristainetos/common/Kconfig" - -config SYS_BOARD - default "aristainetos" - -config SYS_BOARD_VERSION - default 2 - -endif - -if TARGET_ARISTAINETOS2B - -source "board/aristainetos/common/Kconfig" - -config SYS_BOARD - default "aristainetos" - -config SYS_BOARD_VERSION - default 3 - -endif - -if TARGET_ARISTAINETOS2BCSL - -source "board/aristainetos/common/Kconfig" - -config SYS_BOARD - default "aristainetos" - -config SYS_BOARD_VERSION - default 4 - -endif - if TARGET_ARISTAINETOS2C source "board/aristainetos/common/Kconfig" diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index b4ca7abb9c6..1c3fb3aeb14 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -3,34 +3,11 @@ M: Heiko Schocher S: Maintained F: board/aristainetos/ F: include/configs/aristainetos2.h -F: configs/aristainetos2_defconfig -F: configs/aristainetos2b_defconfig -F: configs/aristainetos2bcsl_defconfig F: configs/aristainetos2c_defconfig -F: arch/arm/dts/imx6qdl-aristainetos2.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2_7.dts -F: arch/arm/dts/imx6dl-aristainetos2_7.dtsi -F: arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2_4.dts -F: arch/arm/dts/imx6dl-aristainetos2_4.dtsi -F: arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2b_4.dts -F: arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2b_7.dts -F: arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2b.dtsi -F: arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts -F: arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts -F: arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi -F: arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi -F: arch/arm/dts/imx6dl-aristainetos2c_4.dts -F: arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi F: arch/arm/dts/imx6dl-aristainetos2c_7.dts F: arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2_7.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi F: arch/arm/dts/imx6qdl-aristainetos2c.dtsi F: arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 14931120f6f..6bfaaed666a 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -194,87 +194,6 @@ static void enable_lvds(struct display_info_t const *dev) writel(reg, &iomux->gpr[3]); } -static void enable_spi_display(struct display_info_t const *dev) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int reg; - s32 timeout = 100000; - -#if defined(CONFIG_VIDEO_BMP_LOGO) - rotate_logo(3); /* portrait display in landscape mode */ -#endif - - reg = readl(&ccm->cs2cdr); - - /* select pll 5 clock */ - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK - | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - writel(reg, &ccm->cs2cdr); - - /* set PLL5 to 197994996Hz */ - reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; - reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21); - reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; - reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); - writel(reg, &ccm->analog_pll_video); - - writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4), - &ccm->analog_pll_video_num); - writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240), - &ccm->analog_pll_video_denom); - - reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; - writel(reg, &ccm->analog_pll_video); - - while (timeout--) - if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) - break; - if (timeout < 0) - printf("Warning: video pll lock timeout!\n"); - - reg = readl(&ccm->analog_pll_video); - reg |= BM_ANADIG_PLL_VIDEO_ENABLE; - reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; - writel(reg, &ccm->analog_pll_video); - - /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ - reg = readl(&ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK - | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) - | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); - writel(reg, &ccm->cs2cdr); - - reg = readl(&ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; - writel(reg, &ccm->cscmr2); - - reg = readl(&ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK; - reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET); - reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK; - reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); - writel(reg, &ccm->chsccdr); - - reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES - | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH - | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH - | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG - | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT - | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED - | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; - writel(reg, &iomux->gpr[2]); - - reg = readl(&iomux->gpr[3]); - reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 - << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); - writel(reg, &iomux->gpr[3]); -} - static void setup_display(void) { enable_ipu_clock(); @@ -331,25 +250,36 @@ static void setup_board_gpio(void) setup_one_led("led_blue", LEDST_OFF); } -#define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \ - " rescueReason=%d " - static void aristainetos_run_rescue_command(int reason) { - char rescue_reason_command[80]; + char rescue_reason_command[20]; - sprintf(rescue_reason_command, ARI_RESC_FMT, reason); + sprintf(rescue_reason_command, "setenv rreason %d", reason); run_command(rescue_reason_command, 0); } -static int aristainetos_eeprom(void) +static int aristainetos_bootmode_settings(void) { + struct gpio_desc *desc; + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned int sbmr1 = readl(&psrc->sbmr1); + char *my_bootdelay; + char bootmode = 0; + int ret; struct udevice *dev; int off; - int ret; u8 data[0x10]; u8 rescue_reason; + /* jumper controlled reset of the environment */ + ret = gpio_hog_lookup_name("env_reset", &desc); + if (!ret) { + if (dm_gpio_get_value(desc)) { + printf("\nReset u-boot environment (jumper)\n"); + run_command("run default_env; saveenv; saveenv", 0); + } + } + off = fdt_path_offset(gd->fdt_blob, "eeprom0"); if (off < 0) { printf("%s: No eeprom0 path offset\n", __func__); @@ -366,37 +296,26 @@ static int aristainetos_eeprom(void) if (ret) return ret; - ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6); + ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, sizeof(data)); if (ret) { printf("%s: Could not read EEPROM\n", __func__); return ret; } - if (strncmp((char *)&data[3], "ReScUe", 6) == 0) { - rescue_reason = *(uint8_t *)&data[9]; - memset(&data[3], 0xff, 7); - i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7); - printf("\nBooting into Rescue System (EEPROM)\n"); - aristainetos_run_rescue_command(rescue_reason); - run_command("run rescue_load_fit rescueboot", 0); - } else if (strncmp((char *)data, "DeF", 3) == 0) { + /* software controlled reset of the environment (EEPROM magic) */ + if (strncmp((char *)data, "DeF", 3) == 0) { memset(data, 0xff, 3); i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3); - printf("\nClear u-boot environment (set back to defaults)\n"); + printf("\nReset u-boot environment (EEPROM)\n"); run_command("run default_env; saveenv; saveenv", 0); } - return 0; -}; - -static void aristainetos_bootmode_settings(void) -{ - struct gpio_desc *desc; - struct src *psrc = (struct src *)SRC_BASE_ADDR; - unsigned int sbmr1 = readl(&psrc->sbmr1); - char *my_bootdelay; - char bootmode = 0; - int ret; + if (sbmr1 & 0x40) { + env_set("bootmode", "1"); + printf("SD bootmode jumper set!\n"); + } else { + env_set("bootmode", "0"); + } /* * Check the boot-source. If booting from NOR Flash, @@ -420,28 +339,27 @@ static void aristainetos_bootmode_settings(void) env_set("bootdelay", "-2"); } - if (sbmr1 & 0x40) { - env_set("bootmode", "1"); - printf("SD bootmode jumper set!\n"); - } else { - env_set("bootmode", "0"); - } - - /* read out some jumper values*/ - ret = gpio_hog_lookup_name("env_reset", &desc); - if (!ret) { - if (dm_gpio_get_value(desc)) { - printf("\nClear env (set back to defaults)\n"); - run_command("run default_env; saveenv; saveenv", 0); - } - } + /* jumper controlled boot of the rescue system */ ret = gpio_hog_lookup_name("boot_rescue", &desc); if (!ret) { if (dm_gpio_get_value(desc)) { + printf("\nBooting into Rescue System (jumper)\n"); aristainetos_run_rescue_command(16); run_command("run rescue_xload_boot", 0); } } + + /* software controlled boot of the rescue system (EEPROM magic) */ + if (strncmp((char *)&data[3], "ReScUe", 6) == 0) { + rescue_reason = *(uint8_t *)&data[9]; + memset(&data[3], 0xff, 7); + i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7); + printf("\nBooting into Rescue System (EEPROM)\n"); + aristainetos_run_rescue_command(rescue_reason); + run_command("run rescue_xload_boot", 0); + } + + return 0; } #if defined(CONFIG_DM_PMIC_DA9063) @@ -497,15 +415,15 @@ static int setup_pmic_voltages(void) int board_late_init(void) { int x, y; + int ret; led_default_state(); splash_get_pos(&x, &y); bmp_display((ulong)&bmp_logo_bitmap[0], x, y); - aristainetos_bootmode_settings(); - - /* eeprom work */ - aristainetos_eeprom(); + ret = aristainetos_bootmode_settings(); + if (ret) + return ret; /* set board_type */ if (gd->board_type == BOARD_TYPE_4) @@ -549,97 +467,9 @@ struct display_info_t const displays[] = { .vmode = FB_VMODE_NONINTERLACED } } -#if ((CONFIG_SYS_BOARD_VERSION == 2) || \ - (CONFIG_SYS_BOARD_VERSION == 3) || \ - (CONFIG_SYS_BOARD_VERSION == 4) || \ - (CONFIG_SYS_BOARD_VERSION == 5)) - , { - .bus = -1, - .addr = 0, - .pixfmt = IPU_PIX_FMT_RGB24, - .detect = NULL, - .enable = enable_spi_display, - .mode = { - .name = "lg4573", - .refresh = 57, - .xres = 480, - .yres = 800, - .pixclock = 37037, - .left_margin = 59, - .right_margin = 10, - .upper_margin = 15, - .lower_margin = 15, - .hsync_len = 10, - .vsync_len = 15, - .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT | - FB_SYNC_VERT_HIGH_ACT, - .vmode = FB_VMODE_NONINTERLACED - } - } -#endif }; size_t display_count = ARRAY_SIZE(displays); -#if defined(CONFIG_MTD_RAW_NAND) -iomux_v3_cfg_t nfc_pads[] = { - MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static void setup_gpmi_nand(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - - /* config gpmi nand iomux */ - imx_iomux_v3_setup_multiple_pads(nfc_pads, - ARRAY_SIZE(nfc_pads)); - - /* gate ENFC_CLK_ROOT clock first,before clk source switch */ - clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); - - /* config gpmi and bch clock to 100 MHz */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | - MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); - - /* enable ENFC_CLK_ROOT clock */ - setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); - - /* enable gpmi and bch clock gating */ - setbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); - - /* enable apbh clock gating */ - setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); -} -#else -static void setup_gpmi_nand(void) -{ -} -#endif - int board_init(void) { struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -648,7 +478,6 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; setup_board_gpio(); - setup_gpmi_nand(); setup_display(); /* GPIO_1 for USB_OTG_ID */ diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index e26de5144d6..945a2c4df95 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -2,10 +2,7 @@ config SYS_BOARD_VERSION int "select version of aristainetos board" help version of aristainetos board version - 2 version 2 - 3 version 2b - 4 version 2bcsl - 5 version 2c + 5 version 2c and 2d config SYS_I2C_MXC_I2C1 default y diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig deleted file mode 100644 index 35e4b09715f..00000000000 --- a/configs/aristainetos2_defconfig +++ /dev/null @@ -1,121 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0xe000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_OFFSET=0xD0000 -CONFIG_MX6DL=y -CONFIG_TARGET_ARISTAINETOS2=y -CONFIG_DM_GPIO=y -CONFIG_ENV_OFFSET_REDUND=0xE0000 -CONFIG_IMX_HAB=y -# CONFIG_CMD_DEKBLOB is not set -# CONFIG_CMD_NANDBCB is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2_4" -CONFIG_FIT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_ENCRYPTION=y -CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run ari_boot" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_TYPES=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -# CONFIG_CMD_PINMUX is not set -# CONFIG_CMD_SATA is not set -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6dl-aristainetos2_4 imx6dl-aristainetos2_7" -CONFIG_DTB_RESELECT=y -CONFIG_MULTI_DTB_FIT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_EARLY=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_GPIO_HOG=y -CONFIG_DM_GPIO_LOOKUP_LABEL=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_DM_MMC=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_NAND_MXS=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=3 -CONFIG_SF_DEFAULT_CS=1 -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_DM_ETH=y -CONFIG_MII=y -CONFIG_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_DM_PMIC=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_PWM=y -CONFIG_PWM_IMX=y -CONFIG_DM_RTC=y -CONFIG_RTC_DS1307=y -CONFIG_DM_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_MXC_SPI=y -CONFIG_SYSRESET=y -CONFIG_SYSRESET_WATCHDOG=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_STORAGE=y -CONFIG_DM_VIDEO=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_DISPLAY=y -CONFIG_VIDEO_IPUV3=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_BMP_16BPP=y -CONFIG_IMX_WATCHDOG=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig deleted file mode 100644 index d47a074645b..00000000000 --- a/configs/aristainetos2b_defconfig +++ /dev/null @@ -1,115 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0xe000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_OFFSET=0xD0000 -CONFIG_MX6DL=y -CONFIG_TARGET_ARISTAINETOS2B=y -CONFIG_DM_GPIO=y -CONFIG_ENV_OFFSET_REDUND=0xE0000 -CONFIG_IMX_HAB=y -# CONFIG_CMD_DEKBLOB is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_4" -CONFIG_FIT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_ENCRYPTION=y -CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run ari_boot" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_TYPES=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_PINMUX is not set -# CONFIG_CMD_SATA is not set -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6dl-aristainetos2b_4 imx6dl-aristainetos2b_7" -CONFIG_DTB_RESELECT=y -CONFIG_MULTI_DTB_FIT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_EARLY=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_GPIO_HOG=y -CONFIG_DM_GPIO_LOOKUP_LABEL=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_DM_MMC=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_DM_ETH=y -CONFIG_MII=y -CONFIG_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_DM_PMIC=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_PWM=y -CONFIG_PWM_IMX=y -CONFIG_DM_RTC=y -CONFIG_RTC_DS1307=y -CONFIG_DM_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_MXC_SPI=y -CONFIG_SYSRESET=y -CONFIG_SYSRESET_WATCHDOG=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_STORAGE=y -CONFIG_DM_VIDEO=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_DISPLAY=y -CONFIG_VIDEO_IPUV3=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_BMP_16BPP=y -CONFIG_IMX_WATCHDOG=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/aristainetos2bcsl_defconfig b/configs/aristainetos2bcsl_defconfig deleted file mode 100644 index 30139621d83..00000000000 --- a/configs/aristainetos2bcsl_defconfig +++ /dev/null @@ -1,115 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0xe000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_OFFSET=0xD0000 -CONFIG_MX6DL=y -CONFIG_TARGET_ARISTAINETOS2BCSL=y -CONFIG_DM_GPIO=y -CONFIG_ENV_OFFSET_REDUND=0xE0000 -CONFIG_IMX_HAB=y -# CONFIG_CMD_DEKBLOB is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_csl_4" -CONFIG_FIT=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" -CONFIG_BOOTDELAY=3 -CONFIG_AUTOBOOT_KEYED=y -CONFIG_AUTOBOOT_ENCRYPTION=y -CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" -CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="run ari_boot" -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_BOARD_TYPES=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_BOOTM_NETBSD is not set -# CONFIG_BOOTM_PLAN9 is not set -# CONFIG_BOOTM_RTEMS is not set -# CONFIG_BOOTM_VXWORKS is not set -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -# CONFIG_CMD_PINMUX is not set -# CONFIG_CMD_SATA is not set -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6dl-aristainetos2b_csl_4 imx6dl-aristainetos2b_csl_7" -CONFIG_DTB_RESELECT=y -CONFIG_MULTI_DTB_FIT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_ENV_SPI_EARLY=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_GPIO_HOG=y -CONFIG_DM_GPIO_LOOKUP_LABEL=y -CONFIG_DM_PCA953X=y -CONFIG_DM_I2C=y -CONFIG_LED=y -CONFIG_LED_GPIO=y -CONFIG_MISC=y -CONFIG_I2C_EEPROM=y -CONFIG_DM_MMC=y -CONFIG_FSL_USDHC=y -CONFIG_MTD=y -CONFIG_DM_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_DM_ETH=y -CONFIG_MII=y -CONFIG_PHY=y -CONFIG_PINCTRL=y -CONFIG_PINCTRL_IMX6=y -CONFIG_DM_PMIC=y -CONFIG_DM_REGULATOR=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_PWM=y -CONFIG_PWM_IMX=y -CONFIG_DM_RTC=y -CONFIG_RTC_DS1307=y -CONFIG_DM_SERIAL=y -CONFIG_SPI=y -CONFIG_DM_SPI=y -CONFIG_MXC_SPI=y -CONFIG_SYSRESET=y -CONFIG_SYSRESET_WATCHDOG=y -CONFIG_USB=y -CONFIG_DM_USB=y -CONFIG_USB_STORAGE=y -CONFIG_DM_VIDEO=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_DISPLAY=y -CONFIG_VIDEO_IPUV3=y -CONFIG_SPLASH_SCREEN=y -CONFIG_SPLASH_SCREEN_ALIGN=y -CONFIG_VIDEO_BMP_RLE8=y -CONFIG_BMP_16BPP=y -CONFIG_IMX_WATCHDOG=y -# CONFIG_EFI_LOADER is not set diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 50cadb749af..f602b6eda1a 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -10,11 +10,10 @@ CONFIG_DM_GPIO=y CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_IMX_HAB=y # CONFIG_CMD_DEKBLOB is not set -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_4" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" -CONFIG_BOOTDELAY=3 +CONFIG_BOOTDELAY=-2 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_ENCRYPTION=y CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" @@ -51,7 +50,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_OF_LIST="imx6dl-aristainetos2c_4 imx6dl-aristainetos2c_7" +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_7" +CONFIG_OF_LIST="imx6dl-aristainetos2c_7" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 6e8595caad8..916bd5a59cb 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -13,14 +13,15 @@ #define CONFIG_HOSTNAME "aristainetos2" +#if (CONFIG_SYS_BOARD_VERSION == 5) #define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" +#endif #define CONFIG_FEC_XCV_TYPE RGMII /* Framebuffer */ #define CONFIG_SYS_LDB_CLOCK 28341000 -#define CONFIG_LG4573 #include "mx6_common.h" @@ -77,6 +78,8 @@ "enable_hab_check=1\0" #else #define HAB_EXTRA_SETTINGS \ + "hab_check_addr=echo HAB check addr always returns " \ + "true;true\0" \ "hab_check_file_fit=echo HAB check FIT file always returns " \ "true;true\0" \ "hab_check_flash_fit=echo HAB check flash FIT always returns " \ @@ -86,96 +89,12 @@ "enable_hab_check=0\0" #endif -#if (CONFIG_SYS_BOARD_VERSION == 3) -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "dead=led led_red on\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ - "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ - "mainboot=echo Booting from SD-card ...; " \ - "run mainargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ - "run boot_board_type;" \ - "bootm ${fit_addr_r}\0" \ - "mainargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ - "${fit_file}\0" \ - "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ - "${fit_addr_r} ${rescue_fit_file}\0" -#elif (CONFIG_SYS_BOARD_VERSION == 4) -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "dead=led led_red on;led led_red2 on;\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ - "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ - "mainboot=echo Booting from SD-card ...; " \ - "run mainargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ - "run boot_board_type;" \ - "bootm ${fit_addr_r}\0" \ - "mainargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ - "${fit_file}\0" \ - "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ - "${fit_addr_r} ${rescue_fit_file}\0" -#elif (CONFIG_SYS_BOARD_VERSION == 5) -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "emmcpart=1\0" \ - "emmc_rescue_part=3\0" \ - "emmcdev=1\0" \ - "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \ - "dead=led led_red on\0" \ - "mtdids=nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ - "bootmode=${bootmode} mmcpart=${mmcpart} " \ - "emmcpart=${emmcpart}\0" \ - "mainboot=echo Booting from eMMC ...; " \ - "run mainargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ - "run boot_board_type;" \ - "bootm ${fit_addr_r}\0" \ - "mainargs=setenv bootargs console=${console},${baudrate} " \ - "root=${emmcroot} rootfstype=ext4\0 " \ - "main_load_fit=ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \ - "${fit_file}; " \ - "imi ${fit_addr_r}\0 " \ - "rescue_load_fit=ext4load mmc ${emmcdev}:${emmc_rescue_part} " \ - "${fit_addr_r} ${rescue_fit_file};imi ${fit_addr_r}\0" -#else +#if (CONFIG_SYS_BOARD_VERSION == 5) #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "dead=led led_red on\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \ - "mtdparts=mtdparts=spi3.1:832k(u-boot),64k(env),64k(env-red)," \ - "-(ubi-nor);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ - "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ - "mainboot=echo Booting from SD-card ...; " \ - "run mainargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ - "run boot_board_type;" \ - "bootm ${fit_addr_r}\0" \ - "mainargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ - "${fit_file}\0" \ - "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ - "${fit_addr_r} ${rescue_fit_file}\0" + "dead=while true; do; " \ + "led led_red on; sleep 1;" \ + "led led_red off; sleep 1;" \ + "done\0" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -183,17 +102,24 @@ "usb_pgood_delay=2000\0" \ "nor_bootdelay=-2\0" \ "script=u-boot.scr\0" \ - "fit_file=/boot/system.itb\0" \ - "rescue_fit_file=/boot/rescue.itb\0" \ "loadaddr=0x12000000\0" \ "fit_addr_r=0x14000000\0" \ - "uboot=/boot/u-boot.imx\0" \ "uboot_sz=d0000\0" \ "panel=lb07wv8\0" \ "splashpos=m,m\0" \ "console=" CONSOLE_DEV "\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ + "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \ + "mtdids=nor0=spi0.0\0" \ + "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ + "-(ubi-nor)\0" \ + "mk_fitfile_path=setenv fit_file /${sysnum}/system.itb\0" \ + "mk_rescue_fitfile_path=setenv rescue_fit_file /${rescue_sysnum}/system.itb\0" \ + "mk_uboot_path=setenv uboot /${sysnum}/u-boot.imx\0" \ + "mk_pubkey_path=setenv pubkey /${sysnum}/PCR.pem\0" \ + "mk_rescue_pubkey_path=setenv pubkey /${rescue_sysnum}/PCR.pem\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ + "bootmode=${bootmode} rng_core.default_quality=1000 " \ + "mmcpart=${mmcpart} emmcpart=${emmcpart} sysnum=${sysnum}\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ "boot_board_type=bootm ${fit_addr_r}#${board_type}\0" \ "get_env=mw ${loadaddr} 0 0x20000;" \ @@ -205,7 +131,7 @@ "sf protect unlock 0 0x1000000;" \ "mw ${loadaddr} 0 0x20000;" \ "env export -t ${loadaddr} serial# ethaddr " \ - "board_type panel addmisc addmiscM addmiscC addmiscD;" \ + "board_type panel;" \ "env default -a;" \ "env import -t ${loadaddr}\0" \ "loadbootscript=" \ @@ -216,28 +142,62 @@ "loadbootscriptUSBf=" \ "fatload usb 0 ${loadaddr} ${script};\0" \ "bootscriptUSB=echo Running bootscript from usb-stick ...; " \ - "source\0" \ + "source \0" \ "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ + "source \0" \ "mmcpart=1\0" \ - "mmcrescuepart=3\0" \ "mmcdev=0\0" \ + "emmcpart=1\0" \ + "emmcdev=1\0" \ + "sysnum=1\0" \ + "rescue_sysnum=0\0" \ + "rreason=18\0" \ + "mainboot=echo Booting from eMMC ...; " \ + "run mainargs addmtd addmisc;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "mainargs=setenv bootargs console=${console},${baudrate} " \ + "root=${emmcroot} rootfstype=ext4\0 " \ + "main_load_fit=run mk_fitfile_path; " \ + "ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \ + "${fit_file}; " \ + "imi ${fit_addr_r}\0 " \ + "rescue_load_fit=run mk_rescue_fitfile_path; " \ + "ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \ + "${rescue_fit_file}; " \ + "imi ${fit_addr_r}\0" \ + "main_load_pubkey=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${emmcdev}:${emmcpart} ${loadaddr} " \ + "${pubkey}\0" \ + "rescue_load_pubkey=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${emmcdev}:${emmcpart} ${loadaddr} " \ + "${pubkey}\0" \ + "mainRargs=setenv bootargs console=${console},${baudrate} " \ + "rescue_sysnum=${rescue_sysnum} root=${emmcroot} rootfstype=ext4\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ + "mmcRargs=setenv bootargs console=${console},${baudrate} " \ + "rescue_sysnum=${rescue_sysnum} root=${mmcroot}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ "run boot_board_type;" \ "bootm ${fit_addr_r}\0" \ - "mmc_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "mmc_load_fit=run mk_fitfile_path; " \ + "ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ "${fit_file}\0" \ - "mmc_load_uboot=ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ - "${uboot}\0" \ - "mmc_rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ + "imi ${fit_addr_r}\0" \ + "mmc_rescue_load_fit=run mk_rescue_fitfile_path; " \ + "ext4load mmc ${mmcdev}:${mmcpart} " \ "${fit_addr_r} ${rescue_fit_file}\0" \ + "imi ${fit_addr_r}\0" \ + "mmc_load_uboot=run mk_uboot_path; " \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${uboot}\0" \ "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ "setexpr uboot_maxsize ${uboot_sz} - 400;" \ @@ -246,14 +206,19 @@ "sf write ${loadaddr} 400 ${filesize};" \ "sf read ${cmp_buf} 400 ${uboot_sz};" \ "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ - "rescueargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/ram rw\0 " \ + "mmc_load_pubkey=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${pubkey}\0" \ + "mmc_rescue_load_pubkey=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${pubkey}\0" \ "rescueboot=echo Booting rescue system ...; " \ - "run rescueargs addmtd addmisc;" \ + "run addmtd addmisc;" \ "if test -n ${rescue_reason}; then run rescue_reason;fi;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ "run boot_board_type;" \ "if bootm ${fit_addr_r}; then ; " \ "else " \ @@ -261,50 +226,73 @@ "fi; \0" \ "r_reason_syserr=setenv rescue_reason setenv bootargs " \ "\\\\${bootargs} " \ - "rescueReason=18\0 " \ - "usb_load_fit=ext4load usb 0 ${fit_addr_r} ${fit_file}\0" \ - "usb_load_fitf=fatload usb 0 ${fit_addr_r} ${fit_file}\0" \ - "usb_load_rescuefit=ext4load usb 0 ${fit_addr_r} " \ + "rescueReason=$rreason\0 " \ + "usb_load_fit=run mk_fitfile_path; " \ + "ext4load usb 0 ${fit_addr_r} ${fit_file}\0" \ + "usb_load_fitf=run mk_fitfile_path; " \ + "fatload usb 0 ${fit_addr_r} ${fit_file}\0" \ + "usb_load_rescuefit=run mk_rescue_fitfile_path; " \ + "ext4load usb 0 ${fit_addr_r} " \ "${rescue_fit_file}\0" \ - "usb_load_rescuefitf=fatload usb 0 ${fit_addr_r} " \ + "usb_load_rescuefitf=run mk_rescue_fitfile_path; " \ + "fatload usb 0 ${fit_addr_r} " \ "${rescue_fit_file}\0" \ + "usb_load_pubkey=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load usb 0 ${loadaddr} ${pubkey}\0" \ + "usb_rescue_load_pubkey=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "ext4load usb 0 ${loadaddr} ${pubkey}\0" \ + "usb_load_pubkeyf=run mk_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "fatload usb 0 ${loadaddr} ${pubkey}\0" \ + "usb_rescue_load_pubkeyf=run mk_rescue_pubkey_path; " \ + "setenv hab_check_filetype \"PCR.pem\";" \ + "env set check_addr ${loadaddr};" \ + "fatload usb 0 ${loadaddr} ${pubkey}\0" \ "usbroot=/dev/sda1 rootwait rw\0" \ "usbboot=echo Booting from usb-stick ...; " \ "run usbargs addmtd addmisc;" \ - "if test -n ${addmiscM}; then run addmiscM;fi;" \ - "if test -n ${addmiscC}; then run addmiscC;fi;" \ - "if test -n ${addmiscD}; then run addmiscD;fi;" \ "run boot_board_type;" \ "bootm ${fit_addr_r}\0" \ "usbargs=setenv bootargs console=${console},${baudrate} " \ "root=${usbroot}\0" \ + "usbRargs=setenv bootargs console=${console},${baudrate} " \ + "rescue_sysnum=${rescue_sysnum} root=${usbroot} rw\0 " \ "mmc_rescue_boot=" \ "run r_reason_syserr;" \ - "if run mmc_rescue_load_fit hab_check_file_fit; then " \ - "run rescueboot; " \ + "if run mmc_rescue_load_pubkey hab_check_addr " \ + "mmc_rescue_load_fit hab_check_file_fit; then " \ + "run mmcRargs; run rescueboot; " \ "else " \ - "run dead; " \ "echo RESCUE SYSTEM FROM SD-CARD BOOT FAILURE;" \ + "run dead; " \ "fi;\0" \ "main_rescue_boot=" \ - "if run main_load_fit hab_check_flash_fit; then " \ + "if run main_load_pubkey hab_check_addr " \ + "main_load_fit hab_check_flash_fit; then " \ "if run mainboot; then ; " \ "else " \ "run r_reason_syserr;" \ - "if run rescue_load_fit hab_check_file_fit;" \ - "then run rescueboot; " \ + "if run rescue_load_pubkey hab_check_addr " \ + "rescue_load_fit hab_check_file_fit; then " \ + "run mainRargs; run rescueboot; " \ "else " \ - "run dead; " \ "echo RESCUE SYSTEM BOOT FAILURE;" \ + "run dead; " \ "fi; " \ "fi; " \ "else " \ "run r_reason_syserr;" \ - "if run rescue_load_fit hab_check_file_fit; then " \ - "run rescueboot; " \ + "if run rescue_load_pubkey hab_check_addr " \ + "rescue_load_fit hab_check_file_fit; then " \ + "run mainRargs; run rescueboot; " \ "else " \ - "run dead; " \ "echo RESCUE SYSTEM BOOT FAILURE;" \ + "run dead; " \ "fi; " \ "fi;\0" \ "usb_mmc_rescue_boot=" \ @@ -318,17 +306,21 @@ "hab_check_file_bootscript;" \ "then run bootscriptUSB; " \ "fi; " \ - "if run usb_load_fit hab_check_file_fit; then " \ + "if run usb_load_pubkey hab_check_addr " \ + "usb_load_fit hab_check_file_fit; then " \ "run usbboot; " \ "fi; " \ - "if run usb_load_fitf hab_check_file_fit; then " \ + "if run usb_load_pubkeyf hab_check_addr " \ + "usb_load_fitf hab_check_file_fit; then " \ "run usbboot; " \ "fi; "\ - "if run usb_load_rescuefit hab_check_file_fit;" \ - "then run r_reason_syserr rescueboot;" \ + "if run usb_rescue_load_pubkey hab_check_addr " \ + "usb_load_rescuefit hab_check_file_fit; then " \ + "run r_reason_syserr usbRargs; run rescueboot;" \ "fi; " \ - "if run usb_load_rescuefitf hab_check_file_fit;" \ - "then run r_reason_syserr rescueboot;" \ + "if run usb_rescue_load_pubkeyf hab_check_addr " \ + "usb_load_rescuefitf hab_check_file_fit; then " \ + "run r_reason_syserr usbRargs; run rescueboot;" \ "fi; " \ "run mmc_rescue_boot;" \ "fi; "\ @@ -338,48 +330,57 @@ "if test ${bootmode} -ne 0 ; then " \ "mmc dev ${mmcdev};" \ "if mmc rescan; then " \ - "if run mmc_rescue_load_fit " \ - "hab_check_file_fit; then " \ - "run rescueboot; " \ + "if run mmc_rescue_load_pubkey " \ + "hab_check_addr " \ + "mmc_rescue_load_fit " \ + "hab_check_file_fit; then " \ + "run mmcRargs; run rescueboot; " \ "else " \ "usb start;" \ "if usb storage; then " \ - "if run usb_load_rescuefit " \ - "hab_check_file_fit;"\ - "then " \ - "run rescueboot;" \ + "if run usb_rescue_load_pubkey " \ + "hab_check_addr " \ + "usb_load_rescuefit " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ "fi; " \ - "if run usb_load_rescuefitf "\ - "hab_check_file_fit;"\ - "then " \ - "run rescueboot;" \ + "if run usb_rescue_load_pubkeyf " \ + "hab_check_addr " \ + "usb_load_rescuefitf " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ "fi; " \ "fi;" \ "fi;" \ - "run dead; " \ "echo RESCUE SYSTEM ON SD OR " \ "USB BOOT FAILURE;" \ + "run dead; " \ "else " \ "usb start;" \ "if usb storage; then " \ - "if run usb_load_rescuefit " \ - "hab_check_file_fit; then " \ - "run rescueboot;" \ + "if run usb_rescue_load_pubkey " \ + "hab_check_addr " \ + "usb_load_rescuefit " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ "fi; " \ - "if run usb_load_rescuefitf " \ - "hab_check_file_fit; then " \ - "run rescueboot;" \ + "if run usb_rescue_load_pubkeyf " \ + "hab_check_addr " \ + "usb_load_rescuefitf " \ + "hab_check_file_fit; then " \ + "run usbRargs; run rescueboot;" \ "fi; " \ "fi;" \ - "run dead; " \ "echo RESCUE SYSTEM ON USB BOOT FAILURE;" \ + "run dead; " \ "fi; " \ "else "\ - "if run rescue_load_fit hab_check_file_fit; then " \ - "run rescueboot; " \ + "if run rescue_load_pubkey hab_check_addr " \ + "rescue_load_fit hab_check_file_fit; then " \ + "run mainRargs; run rescueboot; " \ "else " \ - "run dead; " \ "echo RESCUE SYSTEM ON BOARD BOOT FAILURE;" \ + "run dead; " \ "fi; " \ "fi;\0" \ "ari_boot=if test ${bootmode} -ne 0 ; then " \ @@ -388,7 +389,8 @@ "if run loadbootscript hab_check_file_bootscript;" \ "then run bootscript; " \ "fi; " \ - "if run mmc_load_fit hab_check_file_fit; then " \ + "if run mmc_load_pubkey hab_check_addr " \ + "mmc_load_fit hab_check_file_fit; then " \ "if run mmcboot; then ; " \ "else " \ "run mmc_rescue_boot;" \ @@ -421,12 +423,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2 -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - /* DMA stuff, needed for GPMI/MXS NAND support */ /* USB Configs */ -- cgit v1.3.1 From 015c026f7a51dccae4040bc3912101e1e5a30b12 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 30 Nov 2020 20:46:03 +0100 Subject: imx6: add support for aristainetos2c_cslb board variant add support for aristainetos2c_cslb board variant. Signed-off-by: Heiko Schocher --- arch/arm/dts/Makefile | 1 + .../dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi | 19 ++ arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts | 16 ++ .../dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi | 77 +++++++ arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi | 232 +++++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 11 + board/aristainetos/Kconfig | 12 ++ board/aristainetos/MAINTAINERS | 5 + board/aristainetos/common/Kconfig | 1 + configs/aristainetos2c_defconfig | 3 +- configs/aristainetos2ccslb_defconfig | 118 +++++++++++ include/configs/aristainetos2.h | 9 + 12 files changed, 502 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts create mode 100644 arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi create mode 100644 configs/aristainetos2ccslb_defconfig (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 457ccfe08ff..089dfb73a38 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -644,6 +644,7 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \ ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),) dtb-y += \ imx6dl-aristainetos2c_7.dtb \ + imx6dl-aristainetos2c_cslb_7.dtb \ imx6dl-brppt2.dtb \ imx6dl-cubox-i.dtb \ imx6dl-cubox-i-emmc-som-v15.dtb \ diff --git a/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi new file mode 100644 index 00000000000..b069debc1e3 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +#include +/ { + vdd_panel_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&panel0 { + power-supply = <&vdd_panel_reg>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts new file mode 100644 index 00000000000..b40ddafeb97 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2c cslb board + * + * Copyright (C) 2019 Heiko Schocher + * Copyright (C) 2015 Heiko Schocher + * + */ +/dts-v1/; +#include "imx6dl-aristainetos2_7.dtsi" +#include "imx6qdl-aristainetos2c_cslb.dtsi" + +/ { + model = "aristainetos2c cslb i.MX6 Dual Lite Board 7"; + compatible = "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi new file mode 100644 index 00000000000..8c2ed700751 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart1; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_gpio { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-pre-reloc; +}; + +&backlight { + pwms = <&pwm1 0 300000>; + default-brightness-level = <2>; +}; + +/* + * allow switching write protect / reset pin by gpio, + * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot + */ +&gpio2 { + u-boot,dm-pre-reloc; + + wp_spi_nor { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + }; + + reset_spi_nor { + gpio-hog; + output-high; + gpios = <28 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio4 { + u-boot,dm-pre-reloc; +}; + +&ecspi1 { + u-boot,dm-pre-reloc; +}; + +&flash { + u-boot,dm-pre-reloc; +}; + +&pinctrl_ecspi1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi new file mode 100644 index 00000000000..c3724ec86fc --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2c-cslb board + * + * Copyright (C) 2019 Heiko Schocher + * Copyright (C) 2015 Heiko Schocher + * + */ +#include +#include + +#include "imx6qdl-aristainetos2-common.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + LED_blue { + label = "led_blue"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + }; + + LED_green { + label = "led_green"; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + }; + + LED_red { + label = "led_red"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + }; + + LED_yellow { + label = "led_yellow"; + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; + + LED_blue_2 { + label = "led_blue2"; + gpios = <&expander 15 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_green_2 { + label = "led_green2"; + gpios = <&expander 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_red_2 { + label = "led_red2"; + gpios = <&expander 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_yellow_2 { + label = "led_yellow2"; + gpios = <&expander 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_ena { + label = "led_ena"; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <3>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH + &gpio4 10 GPIO_ACTIVE_HIGH + &gpio4 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; +}; + +&i2c1 { + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; +}; + +&gpio7 { + eMMC_reset { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + }; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* SS0# */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 + /* SS1# */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 + /* SS2# */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 + /* WP pin NOR Flash */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 + /* Flash nReset */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + /* led enable */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 + /* LCD power enable */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 + /* led yellow */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 + /* led red */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 + /* led green */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 + /* led blue */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 + /* Profibus IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + /* FPGA IRQ currently unused*/ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + /* Display reset because of clock failure */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 + /* spi bus #2 SS driver enable */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 + /* RST_LOC# PHY reset input (has pull-down!)*/ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 + /* Touchscreen IRQ */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 + /* PCIe reset */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 + /* make sure pin is GPIO and not ENET_REF_CLK */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 + /* TPM PP */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0 + /* TPM Reset */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 + /* eMMC Reset# */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + /* SD1 card detect input */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 9d6c3440642..513d007ce75 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -139,6 +139,17 @@ config TARGET_ARISTAINETOS2C imply CMD_SATA imply CMD_DM +config TARGET_ARISTAINETOS2CCSLB + bool "Support aristainetos2-revC CSL" + depends on MX6DL + select BOARD_LATE_INIT + select SYS_I2C_MXC + select MXC_UART + select FEC_MXC + select DM + imply CMD_SATA + imply CMD_DM + config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" depends on MX6QDL diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index d67002503dd..cc603c1bc2d 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -9,3 +9,15 @@ config SYS_BOARD_VERSION default 5 endif + +if TARGET_ARISTAINETOS2CCSLB + +source "board/aristainetos/common/Kconfig" + +config SYS_BOARD + default "aristainetos" + +config SYS_BOARD_VERSION + default 6 + +endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index 1c3fb3aeb14..c81bef9cb7c 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -4,10 +4,15 @@ S: Maintained F: board/aristainetos/ F: include/configs/aristainetos2.h F: configs/aristainetos2c_defconfig +F: configs/aristainetos2ccslb_defconfig F: arch/arm/dts/imx6dl-aristainetos2c_7.dts F: arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts +F: arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi F: arch/arm/dts/imx6dl-aristainetos2_7.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi F: arch/arm/dts/imx6qdl-aristainetos2c.dtsi F: arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2c_cslb-u-boot.dtsi diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index 945a2c4df95..328243c2f9a 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -3,6 +3,7 @@ config SYS_BOARD_VERSION help version of aristainetos board version 5 version 2c and 2d + 6 version 2c-cslb config SYS_I2C_MXC_I2C1 default y diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index f602b6eda1a..773d7f67748 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -10,6 +10,7 @@ CONFIG_DM_GPIO=y CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_IMX_HAB=y # CONFIG_CMD_DEKBLOB is not set +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_7" CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" @@ -50,8 +51,6 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y CONFIG_OF_CONTROL=y -CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_7" -CONFIG_OF_LIST="imx6dl-aristainetos2c_7" CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig new file mode 100644 index 00000000000..16d3c88fe13 --- /dev/null +++ b/configs/aristainetos2ccslb_defconfig @@ -0,0 +1,118 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_OFFSET=0xD0000 +CONFIG_MX6DL=y +CONFIG_TARGET_ARISTAINETOS2CCSLB=y +CONFIG_DM_GPIO=y +CONFIG_ENV_OFFSET_REDUND=0xE0000 +CONFIG_IMX_HAB=y +# CONFIG_CMD_DEKBLOB is not set +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_cslb_7" +CONFIG_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" +CONFIG_BOOTDELAY=-2 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ari_boot" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_BOARD_TYPES=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_PINMUX is not set +# CONFIG_CMD_SATA is not set +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_APBH_DMA=y +CONFIG_APBH_DMA_BURST=y +CONFIG_APBH_DMA_BURST8=y +CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +# CONFIG_SPL_PMIC_CHILDREN is not set +CONFIG_DM_PMIC_DA9063=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_DA9063=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_IMX=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_IPUV3=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_IMX_WATCHDOG=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 916bd5a59cb..c1e8b4a10c3 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -16,6 +16,9 @@ #if (CONFIG_SYS_BOARD_VERSION == 5) #define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" +#elif (CONFIG_SYS_BOARD_VERSION == 6) +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONSOLE_DEV "ttymxc0" #endif #define CONFIG_FEC_XCV_TYPE RGMII @@ -95,6 +98,12 @@ "led led_red on; sleep 1;" \ "led led_red off; sleep 1;" \ "done\0" +#elif (CONFIG_SYS_BOARD_VERSION == 6) +#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ + "dead=while true; do; " \ + "led led_red on; led led_red2 on; sleep 1;" \ + "led led_red off; led led_red2 off;; sleep 1;" \ + "done\0" #endif #define CONFIG_EXTRA_ENV_SETTINGS \ -- cgit v1.3.1 From 7a8d18da4bb2a92246af1129337164e9a41a9abf Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 30 Nov 2020 20:46:05 +0100 Subject: imx: aristainetos: enable U-Boot Environment variables protection enable Environment protection with: CONFIG_ENV_APPEND=y CONFIG_ENV_WRITEABLE_LIST=y CONFIG_ENV_ACCESS_IGNORE_FORCE and add board specific env_get_location() function. Signed-off-by: Heiko Schocher --- board/aristainetos/aristainetos.c | 20 ++++++++++++++++++++ configs/aristainetos2c_defconfig | 8 +++++++- configs/aristainetos2ccslb_defconfig | 10 +++++++++- include/configs/aristainetos2.h | 3 +++ 4 files changed, 39 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 6bfaaed666a..07d2e3ec7bb 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -527,3 +528,22 @@ int embedded_dtb_select(void) return 0; } #endif + +enum env_location env_get_location(enum env_operation op, int prio) +{ + if (op == ENVOP_SAVE || op == ENVOP_ERASE) + return ENVL_SPI_FLASH; + + switch (prio) { + case 0: + return ENVL_NOWHERE; + + case 1: + return ENVL_SPI_FLASH; + + default: + return ENVL_UNKNOWN; + } + + return ENVL_UNKNOWN; +} diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index 773d7f67748..df0b26d6a0a 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_SYS_MALLOC_F_LEN=0x13000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0xD0000 CONFIG_MX6DL=y @@ -30,6 +30,8 @@ CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_NVEDIT_INFO=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -54,10 +56,14 @@ CONFIG_OF_CONTROL=y CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_APPEND=y +CONFIG_ENV_WRITEABLE_LIST=y +CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_VERSION_VARIABLE=y CONFIG_BOUNCE_BUFFER=y CONFIG_APBH_DMA=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index 16d3c88fe13..0156493934c 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_SYS_MALLOC_F_LEN=0x13000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_OFFSET=0xD0000 CONFIG_MX6DL=y @@ -30,6 +30,8 @@ CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_ENV_FLAGS=y +CONFIG_CMD_NVEDIT_INFO=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y @@ -54,10 +56,14 @@ CONFIG_OF_CONTROL=y CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_APPEND=y +CONFIG_ENV_WRITEABLE_LIST=y +CONFIG_ENV_ACCESS_IGNORE_FORCE=y CONFIG_VERSION_VARIABLE=y CONFIG_BOUNCE_BUFFER=y CONFIG_APBH_DMA=y @@ -114,5 +120,7 @@ CONFIG_DISPLAY=y CONFIG_VIDEO_IPUV3=y CONFIG_SPLASH_SCREEN=y CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y CONFIG_IMX_WATCHDOG=y # CONFIG_EFI_LOADER is not set diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index c1e8b4a10c3..78fa1a969e7 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -449,4 +449,7 @@ #define CONFIG_IMX6_PWM_PER_CLK 66000000 +#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mw,serial#:sw,board_type:sw," \ + "sysnum:dw,panel:sw,ipaddr:iw,serverip:iw" + #endif /* __ARISTAINETOS2_CONFIG_H */ -- cgit v1.3.1 From f2ac6f7796bbb8aae18998794fddf59198090c3f Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Wed, 4 Nov 2020 17:18:39 +0100 Subject: board: ge: bx50v3: correct CONFIG_CMD_NFS Fix typo in NFS command configuration check. Signed-off-by: Ian Ray Signed-off-by: Sebastian Reichel --- include/configs/ge_bx50v3.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index 4fdc2b65962..c328a12ce17 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -48,7 +48,7 @@ #define CONFIG_LOADADDR 0x12000000 -#ifdef CONFIG_NFS_CMD +#ifdef CONFIG_CMD_NFS #define NETWORKBOOT \ "setnetworkboot=" \ "setenv ipaddr 172.16.2.10; setenv serverip 172.16.2.20; " \ @@ -130,7 +130,7 @@ #define CONFIG_USBBOOTCOMMAND \ "echo Unsupported; " \ -#ifdef CONFIG_NFS_CMD +#ifdef CONFIG_CMD_NFS #define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND #elif CONFIG_CMD_USB #define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND -- cgit v1.3.1 From 4f1970f4373566190fc447bf7e27e9e95ec84cf8 Mon Sep 17 00:00:00 2001 From: Ian Ray Date: Wed, 4 Nov 2020 17:18:43 +0100 Subject: board: ge: bx50v3: check b850v3 power management watchdog Set `bootcause' from b850v3 power management watchdog status. Boot cause "REVERT" is no longer used, remove it. Signed-off-by: Ian Ray Signed-off-by: Sebastian Reichel --- board/ge/bx50v3/bx50v3.c | 17 +++++++++++++++++ include/configs/ge_bx50v3.h | 4 +--- 2 files changed, 18 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 8e7b90a10c7..4754647fb4a 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -384,6 +384,7 @@ static iomux_v3_cfg_t const misc_pads[] = { MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL), }; #define SUS_S3_OUT IMX_GPIO_NR(4, 11) +#define PWGIN_IN IMX_GPIO_NR(4, 14) #define WIFI_EN IMX_GPIO_NR(6, 14) int board_early_init_f(void) @@ -416,6 +417,9 @@ int board_init(void) gpio_request(SUS_S3_OUT, "sus_s3_out"); gpio_direction_output(SUS_S3_OUT, 1); + gpio_request(PWGIN_IN, "pwgin_in"); + gpio_direction_input(PWGIN_IN); + gpio_request(WIFI_EN, "wifi_en"); gpio_direction_output(WIFI_EN, 1); @@ -465,6 +469,17 @@ void pmic_init(void) } } +static void detect_boot_cause(void) +{ + const char *cause = "POR"; + + if (is_b850v3()) + if (!gpio_get_value(PWGIN_IN)) + cause = "PM_WDOG"; + + env_set("bootcause", cause); +} + int board_late_init(void) { process_vpd(&vpd); @@ -478,6 +493,8 @@ int board_late_init(void) else env_set("videoargs", "video=LVDS-1:1024x768@65"); + detect_boot_cause(); + /* board specific pmic init */ pmic_init(); diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index c328a12ce17..e5c580b3f91 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -56,7 +56,7 @@ "setenv netmask 255.255.255.0; setenv ethaddr ca:fe:de:ca:f0:11; " \ "setenv bootargs root=/dev/nfs nfsroot=${nfsserver}:/srv/nfs/,v3,tcp rw rootwait" \ "setenv bootargs $bootargs ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off " \ - "setenv bootargs $bootargs cma=128M bootcause=POR ${videoargs} " \ + "setenv bootargs $bootargs cma=128M bootcause=${bootcause} ${videoargs} " \ "setenv bootargs $bootargs systemd.mask=helix-network-defaults.service " \ "setenv bootargs $bootargs watchdog.handle_boot_enabled=1\0" \ "networkboot=" \ @@ -74,7 +74,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ NETWORKBOOT \ - "bootcause=POR\0" \ "image=/boot/fitImage\0" \ "dev=mmc\0" \ "devnum=2\0" \ @@ -104,7 +103,6 @@ "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ "run hasfirstboot || setenv partnum 0; " \ "if test ${partnum} != 0; then " \ - "setenv bootcause REVERT; " \ "run swappartitions loadimage doboot; " \ "fi; " \ "run failbootcmd\0" \ -- cgit v1.3.1 From a51fdba3fa1e18f5b3b294663949723f220576ba Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Thu, 22 Oct 2020 11:21:38 +0300 Subject: board: toradex: add apalis-imx8x 2gb wb it v1.1a module support This commit adds initial support for the Toradex Apalis iMX8X 2GB WB IT V1.1A System on Module support [1]. Boot log: U-Boot 2020.10-02940-g894aebb7e8-dirty (Oct 22 2020 - 09:43:57 +0300) CPU: NXP i.MX8QXP RevB A35 at 1200 MHz at 30C DRAM: 2 GiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 Loading Environment from MMC... OK In: serial@5a070000 Out: serial@5a070000 Err: serial@5a070000 Model: Toradex Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT V1.1A, Serial# 06617018 Net: eth0: ethernet@5b040000 [PRIME] Hit any key to stop autoboot: 0 Functionality wise the following is known to be working: - eMMC and MMC/SD card - Ethernet (*) - GPIOs - I2C Unfortunately, there is no USB functionality for the i.MX 8QXP as of yet. * With the SCU FW from the latest Toradex BSP 5.0.0 (SCU FW 1.5.1) ETH PHY encounters bring up problems after reset, this will be fixed soon on SCU FW side. [1] https://www.toradex.com/computer-on-modules/apalis-arm-family/nxp-imx-8x Signed-off-by: Igor Opaniuk Acked-by: Oleksandr Suvorov --- arch/arm/mach-imx/imx8/Kconfig | 6 + board/toradex/apalis-imx8x/Kconfig | 30 +++++ board/toradex/apalis-imx8x/MAINTAINERS | 10 ++ board/toradex/apalis-imx8x/Makefile | 6 + .../toradex/apalis-imx8x/apalis-imx8x-imximage.cfg | 24 ++++ board/toradex/apalis-imx8x/apalis-imx8x.c | 131 ++++++++++++++++++ configs/apalis-imx8x_defconfig | 77 +++++++++++ include/configs/apalis-imx8x.h | 149 +++++++++++++++++++++ 8 files changed, 433 insertions(+) create mode 100644 board/toradex/apalis-imx8x/Kconfig create mode 100644 board/toradex/apalis-imx8x/MAINTAINERS create mode 100644 board/toradex/apalis-imx8x/Makefile create mode 100644 board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg create mode 100644 board/toradex/apalis-imx8x/apalis-imx8x.c create mode 100644 configs/apalis-imx8x_defconfig create mode 100644 include/configs/apalis-imx8x.h (limited to 'include') diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 9d1f73dfc70..04b9729109e 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -65,6 +65,11 @@ config TARGET_COLIBRI_IMX8X select BOARD_LATE_INIT select IMX8QXP +config TARGET_APALIS_IMX8X + bool "Support Apalis iMX8X module" + select BOARD_LATE_INIT + select IMX8QXP + config TARGET_DENEB bool "Support i.MX8QXP Capricorn Deneb board" select BOARD_LATE_INIT @@ -98,6 +103,7 @@ source "board/freescale/imx8qxp_mek/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" +source "board/toradex/apalis-imx8x/Kconfig" source "board/siemens/capricorn/Kconfig" config IMX_SNVS_SEC_SC diff --git a/board/toradex/apalis-imx8x/Kconfig b/board/toradex/apalis-imx8x/Kconfig new file mode 100644 index 00000000000..ee61e09736f --- /dev/null +++ b/board/toradex/apalis-imx8x/Kconfig @@ -0,0 +1,30 @@ +if TARGET_APALIS_IMX8X + +config SYS_BOARD + default "apalis-imx8x" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "apalis-imx8x" + +config TDX_CFG_BLOCK + default y + +config TDX_HAVE_MMC + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +config TDX_CFG_BLOCK_PART + default "1" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/apalis-imx8x/MAINTAINERS b/board/toradex/apalis-imx8x/MAINTAINERS new file mode 100644 index 00000000000..fbf93799315 --- /dev/null +++ b/board/toradex/apalis-imx8x/MAINTAINERS @@ -0,0 +1,10 @@ +Apalis iMX8X +M: Igor Opaniuk +W: http://developer.toradex.com/software/linux/linux-software +S: Maintained +F: arch/arm/dts/fsl-imx8x-apalis.dts +F: arch/arm/dts/fsl-imx8x-apalis-u-boot.dtsi +F: board/toradex/apalis-imx8x/ +F: configs/apalis-imx8x_defconfig +F: doc/board/toradex/apalis-imx8x.rst +F: include/configs/apalis-imx8x.h diff --git a/board/toradex/apalis-imx8x/Makefile b/board/toradex/apalis-imx8x/Makefile new file mode 100644 index 00000000000..9d6e85b7429 --- /dev/null +++ b/board/toradex/apalis-imx8x/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright 2020 Toradex +# + +obj-y += apalis-imx8x.o diff --git a/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg new file mode 100644 index 00000000000..58c62d0a659 --- /dev/null +++ b/board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Toradex + * + * Refer doc/imx/mkimage/imx8image.txt for more details about how-to configure + * and create imx8image boot image + */ + +#define __ASSEMBLY__ + +/* Boot from SD, sector size 0x400 */ +BOOT_FROM EMMC_FASTBOOT 0x400 +/* SoC type IMX8QX */ +SOC_TYPE IMX8QX +/* Append seco container image */ +APPEND mx8qx-ahab-container.img +/* Create the 2nd container */ +CONTAINER +/* Add scfw image with exec attribute */ +IMAGE SCU mx8qx-apalis-scfw-tcm.bin +/* Add ATF image with exec attribute */ +IMAGE A35 bl31.bin 0x80000000 +/* Add U-Boot image with load attribute */ +DATA A35 u-boot-dtb.bin 0x80020000 diff --git a/board/toradex/apalis-imx8x/apalis-imx8x.c b/board/toradex/apalis-imx8x/apalis-imx8x.c new file mode 100644 index 00000000000..9f00f26cfe6 --- /dev/null +++ b/board/toradex/apalis-imx8x/apalis-imx8x.c @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Toradex + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/tdx-cfg-block.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT)) + +static iomux_cfg_t uart1_pads[] = { + SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +int board_early_init_f(void) +{ + sc_pm_clock_rate_t rate; + sc_err_t err = 0; + + /* + * This works around that having only UART3 up the baudrate is 1.2M + * instead of 115.2k. Set UART0 clock root to 80 MHz + */ + rate = 80000000; + err = sc_pm_set_clock_rate(-1, SC_R_UART_0, SC_PM_CLK_PER, &rate); + if (err != SC_ERR_NONE) + return 0; + + /* Set UART3 clock root to 80 MHz and enable it */ + rate = SC_80MHZ; + err = sc_pm_setup_uart(SC_R_UART_1, rate); + if (err != SC_ERR_NONE) + return 0; + + setup_iomux_uart(); + + return 0; +} + +#if IS_ENABLED(CONFIG_DM_GPIO) +static void board_gpio_init(void) +{ + /* TODO */ +} +#else +static inline void board_gpio_init(void) {} +#endif + +#if IS_ENABLED(CONFIG_FEC_MXC) +#include + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} +#endif + +int checkboard(void) +{ + puts("Model: Toradex Apalis iMX8X\n"); + + build_info(); + print_bootinfo(); + + return 0; +} + +int board_init(void) +{ + board_gpio_init(); + + return 0; +} + +/* + * Board specific reset that is system reset. + */ +void reset_cpu(ulong addr) +{ + /* TODO */ +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +/* TODO move to common */ + env_set("board_name", "Apalis iMX8X"); +#endif + + return 0; +} diff --git a/configs/apalis-imx8x_defconfig b/configs/apalis-imx8x_defconfig new file mode 100644 index 00000000000..e6aa5753805 --- /dev/null +++ b/configs/apalis-imx8x_defconfig @@ -0,0 +1,77 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8=y +CONFIG_SYS_TEXT_BASE=0x80020000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_TARGET_APALIS_IMX8X=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-apalis" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/apalis-imx8x/apalis-imx8x-imximage.cfg" +CONFIG_BOOTDELAY=1 +CONFIG_LOG=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_SYS_PROMPT="Apalis iMX8X # " +CONFIG_CMD_CPU=y +# CONFIG_BOOTM_NETBSD is not set +CONFIG_CMD_ASKENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x88000000 +CONFIG_SYS_MEMTEST_END=0x89000000 +CONFIG_CMD_CLK=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_UUID=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_PART=1 +CONFIG_VERSION_VARIABLE=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_IP_DEFRAG=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y +CONFIG_CLK_IMX8=y +CONFIG_CPU=y +CONFIG_MXC_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_FEC_MXC_SHARE_MDIO=y +CONFIG_FEC_MXC_MDIO_BASE=0x5B040000 +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_SCU_THERMAL=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h new file mode 100644 index 00000000000..db31c210f50 --- /dev/null +++ b/include/configs/apalis-imx8x.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 Toradex + */ + +#ifndef __APALIS_IMX8X_H +#define __APALIS_IMX8X_H + +#include +#include +#include + +#define CONFIG_REMAKE_ELF + +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define USDHC1_BASE_ADDR 0x5b010000 +#define USDHC2_BASE_ADDR 0x5b020000 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_TFTP_TSIZE + +#define CONFIG_IPADDR 192.168.10.2 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.10.1 + +#define FEC_ENET_ENABLE_TXC_DELAY +#define FEC_ENET_ENABLE_RXC_DELAY + +#define MEM_LAYOUT_ENV_SETTINGS \ + "kernel_addr_r=0x80280000\0" \ + "fdt_addr_r=0x83100000\0" \ + "ramdisk_addr_r=0x8a000000\0" \ + "scriptaddr=0x83200000\0" + +#ifdef CONFIG_AHAB_BOOT +#define AHAB_ENV "sec_boot=yes\0" +#else +#define AHAB_ENV "sec_boot=no\0" +#endif + +/* Boot M4 */ +#define M4_BOOT_ENV \ + "m4_0_image=m4_0.bin\0" \ + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${m4_0_image}\0" \ + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ + +#define MFG_NAND_PARTITION "" + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) +#include +#undef BOOTENV_RUN_NET_USB_START +#define BOOTENV_RUN_NET_USB_START "" + +#define CONFIG_MFG_ENV_SETTINGS \ + "mfgtool_args=setenv bootargs ${consoleargs} " \ + "rdinit=/linuxrc g_mass_storage.stall=0 " \ + "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \ + "g_mass_storage.idProduct=0x37FF " \ + "g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \ + "${vidargs} clk_ignore_unused\0" \ + "initrd_addr=0x83800000\0" \ + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \ + "${fdt_addr};\0" \ + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + AHAB_ENV \ + BOOTENV \ + CONFIG_MFG_ENV_SETTINGS \ + M4_BOOT_ENV \ + MEM_LAYOUT_ENV_SETTINGS \ + "boot_file=Image\0" \ + "consoleargs=console=ttyLP3,${baudrate} earlycon\0" \ + "fdt_file=imx8qxp-apalis-eval.dtb\0" \ + "fdtfile=imx8qxp-apalis-eval.dtb\0" \ + "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ + "image=Image\0" \ + "initrd_addr=0x83800000\0" \ + "mmcargs=setenv bootargs ${consoleargs} " \ + "root=PARTUUID=${uuid} rootwait " \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "netargs=setenv bootargs ${consoleargs} " \ + "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ + "${vidargs}\0" \ + "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ + "apalis-imx8x/${fdt_file}; booti ${loadaddr} - " \ + "${fdt_addr}\0" \ + "panel=NULL\0" \ + "script=boot.scr\0" \ + "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ + "if test \"$confirm\" = \"y\"; then " \ + "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ + "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ + "${blkcnt}; fi\0" \ + "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x89000000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 + +/* Environment in eMMC, before config block at the end of 1st "boot sector" */ + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +/* On Apalis iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_2 0x880000000 +#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ + +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE SZ_2K +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Generic Timer Definitions */ +#define COUNTER_FREQUENCY 8000000 /* 8MHz */ + +/* Networking */ +#define CONFIG_FEC_ENET_DEV 0 +#define IMX_FEC_BASE 0x5b040000 +#define CONFIG_FEC_MXC_PHYADDR 0x4 +#define CONFIG_ETHPRIME "eth0" +#define CONFIG_FEC_XCV_TYPE RGMII +#define FEC_QUIRK_ENET_MAC +#define PHY_ANEG_TIMEOUT 20000 + +#endif /* __APALIS_IMX8X_H */ -- cgit v1.3.1 From 8c5ea5361c1728c162dd5ce796654c5aef77420e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 29 Oct 2020 21:22:03 -0400 Subject: configs: migrate CONFIG_IMX_THERMAL to defconfigs Done via moveconfig.py Signed-off-by: Tom Rini --- configs/cgtqmx6eval_defconfig | 1 + configs/colibri-imx6ull_defconfig | 1 + configs/colibri_imx7_defconfig | 1 + configs/colibri_imx7_emmc_defconfig | 1 + configs/gwventana_emmc_defconfig | 2 ++ configs/gwventana_gw5904_defconfig | 2 ++ configs/gwventana_nand_defconfig | 2 ++ configs/liteboard_defconfig | 1 + configs/marsboard_defconfig | 1 + configs/mx6cuboxi_defconfig | 1 + configs/mx6sabreauto_defconfig | 1 + configs/mx6sabresd_defconfig | 1 + configs/mx6slevk_defconfig | 1 + configs/mx6slevk_spinor_defconfig | 1 + configs/mx6slevk_spl_defconfig | 1 + configs/mx6sllevk_defconfig | 1 + configs/mx6sllevk_plugin_defconfig | 1 + configs/mx6sxsabreauto_defconfig | 1 + configs/mx6sxsabresd_defconfig | 1 + configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + configs/mx6ull_14x14_evk_defconfig | 1 + configs/mx6ull_14x14_evk_plugin_defconfig | 1 + configs/mx6ulz_14x14_evk_defconfig | 1 + configs/mx7dsabresd_defconfig | 1 + configs/mx7dsabresd_qspi_defconfig | 1 + configs/myir_mys_6ulx_defconfig | 1 + configs/ot1200_defconfig | 1 + configs/ot1200_spl_defconfig | 1 + configs/pfla02_defconfig | 1 + configs/phycore_pcl063_defconfig | 1 + configs/phycore_pcl063_ull_defconfig | 1 + configs/pico-dwarf-imx7d_defconfig | 1 + configs/pico-hobbit-imx7d_defconfig | 1 + configs/pico-imx7d_bl33_defconfig | 1 + configs/pico-imx7d_defconfig | 1 + configs/pico-nymph-imx7d_defconfig | 1 + configs/pico-pi-imx7d_defconfig | 1 + configs/riotboard_defconfig | 1 + configs/riotboard_spl_defconfig | 1 + configs/sksimx6_defconfig | 1 + configs/somlabs_visionsom_6ull_defconfig | 1 + configs/tbs2910_defconfig | 1 + configs/udoo_neo_defconfig | 1 + configs/variscite_dart6ul_defconfig | 1 + configs/vining_2000_defconfig | 1 + configs/warp7_bl33_defconfig | 1 + configs/warp7_defconfig | 1 + configs/xpress_defconfig | 1 + configs/xpress_spl_defconfig | 1 + configs/zc5202_defconfig | 1 + configs/zc5601_defconfig | 1 + include/configs/cgtqmx6eval.h | 1 - include/configs/cl-som-imx7.h | 3 --- include/configs/colibri-imx6ull.h | 2 -- include/configs/colibri_imx7.h | 2 -- include/configs/dart_6ul.h | 2 -- include/configs/el6x_common.h | 2 -- include/configs/embestmx6boards.h | 2 -- include/configs/gw_ventana.h | 10 ---------- include/configs/liteboard.h | 2 -- include/configs/mx6cuboxi.h | 2 -- include/configs/mx6sabre_common.h | 2 -- include/configs/mx6slevk.h | 2 -- include/configs/mx6sllevk.h | 2 -- include/configs/mx6sxsabreauto.h | 2 -- include/configs/mx6sxsabresd.h | 2 -- include/configs/mx6ul_14x14_evk.h | 2 -- include/configs/mx6ullevk.h | 2 -- include/configs/mx7dsabresd.h | 2 -- include/configs/mys_6ulx.h | 2 -- include/configs/ot1200.h | 3 --- include/configs/pcl063.h | 2 -- include/configs/pcl063_ull.h | 2 -- include/configs/pfla02.h | 3 --- include/configs/pico-imx7d.h | 2 -- include/configs/sksimx6.h | 3 --- include/configs/somlabs_visionsom_6ull.h | 2 -- include/configs/tbs2910.h | 2 -- include/configs/udoo_neo.h | 4 ---- include/configs/vining_2000.h | 2 -- include/configs/warp7.h | 2 -- include/configs/xpress.h | 2 -- 83 files changed, 55 insertions(+), 75 deletions(-) (limited to 'include') diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig index c3f608264d3..26f74662f80 100644 --- a/configs/cgtqmx6eval_defconfig +++ b/configs/cgtqmx6eval_defconfig @@ -71,6 +71,7 @@ CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig index 273cb9d7a84..5e18f66d71b 100644 --- a/configs/colibri-imx6ull_defconfig +++ b/configs/colibri-imx6ull_defconfig @@ -84,6 +84,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig index 42a9d63383c..71e331ef71e 100644 --- a/configs/colibri_imx7_defconfig +++ b/configs/colibri_imx7_defconfig @@ -82,6 +82,7 @@ CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig index 81d83c72964..c5a6c4433d5 100644 --- a/configs/colibri_imx7_emmc_defconfig +++ b/configs/colibri_imx7_emmc_defconfig @@ -79,6 +79,7 @@ CONFIG_PINCTRL_IMX7=y CONFIG_DM_PMIC=y CONFIG_PMIC_RN5T567=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index fd47aad6482..41e190bf1e8 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -81,6 +81,8 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index 2a87353ca98..66b04419782 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -85,6 +85,8 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index d2fa6d70227..9022f350d13 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -85,6 +85,8 @@ CONFIG_MII=y CONFIG_PCI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig index 40b5f276ed6..b258880b947 100644 --- a/configs/liteboard_defconfig +++ b/configs/liteboard_defconfig @@ -56,6 +56,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig index 22578714b5c..d2bd9c46d25 100644 --- a/configs/marsboard_defconfig +++ b/configs/marsboard_defconfig @@ -38,6 +38,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 4cabe9076a3..a373d52c93d 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -66,6 +66,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_KEYBOARD=y diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 3241ef8e065..4faf49ef059 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -89,6 +89,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index baa304f7449..0016fbac20d 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -100,6 +100,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig index 171941a8f71..5fd78c3629a 100644 --- a/configs/mx6slevk_defconfig +++ b/configs/mx6slevk_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig index 925886cb403..9777166727e 100644 --- a/configs/mx6slevk_spinor_defconfig +++ b/configs/mx6slevk_spinor_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index b430955cb37..4e44bc2c79a 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -72,6 +72,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig index d145874a7f2..1e446a3e439 100644 --- a/configs/mx6sllevk_defconfig +++ b/configs/mx6sllevk_defconfig @@ -48,6 +48,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig index 49d76a08059..3e0e1006b96 100644 --- a/configs/mx6sllevk_plugin_defconfig +++ b/configs/mx6sllevk_plugin_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig index f645f751e26..0d8c07b57d8 100644 --- a/configs/mx6sxsabreauto_defconfig +++ b/configs/mx6sxsabreauto_defconfig @@ -61,6 +61,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index 0e672efb7b2..af5acc178f2 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -66,6 +66,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index f0a155aff34..878df78ccec 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -80,6 +80,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 40bb371a691..9587ff808f1 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -75,6 +75,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig index 4fdbb915d47..fdd44838178 100644 --- a/configs/mx6ull_14x14_evk_defconfig +++ b/configs/mx6ull_14x14_evk_defconfig @@ -58,3 +58,4 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig index f8f863411ea..a6c30b3fb68 100644 --- a/configs/mx6ull_14x14_evk_plugin_defconfig +++ b/configs/mx6ull_14x14_evk_plugin_defconfig @@ -57,3 +57,4 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig index fac63f38598..71801208adb 100644 --- a/configs/mx6ulz_14x14_evk_defconfig +++ b/configs/mx6ulz_14x14_evk_defconfig @@ -49,3 +49,4 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y +CONFIG_IMX_THERMAL=y diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig index e9e1f1ea475..3687a65283f 100644 --- a/configs/mx7dsabresd_defconfig +++ b/configs/mx7dsabresd_defconfig @@ -70,6 +70,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig index 6004128de95..c216b8c5be6 100644 --- a/configs/mx7dsabresd_qspi_defconfig +++ b/configs/mx7dsabresd_qspi_defconfig @@ -77,6 +77,7 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y CONFIG_SOFT_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig index ef90f5f66f7..e929216c832 100644 --- a/configs/myir_mys_6ulx_defconfig +++ b/configs/myir_mys_6ulx_defconfig @@ -66,6 +66,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig index a4fb70b5bfd..4f8a524c1dc 100644 --- a/configs/ot1200_defconfig +++ b/configs/ot1200_defconfig @@ -53,6 +53,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig index 81feb2ff2f4..ec3bf903069 100644 --- a/configs/ot1200_spl_defconfig +++ b/configs/ot1200_spl_defconfig @@ -64,6 +64,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig index dc7151b6107..fa8ed31e5be 100644 --- a/configs/pfla02_defconfig +++ b/configs/pfla02_defconfig @@ -71,4 +71,5 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index ab92e3f7e76..65239a049d5 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -59,6 +59,7 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index 9cc0892daba..c57ca29f3bc 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -48,6 +48,7 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 085913ef82d..dbfa2e0a8cf 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 6b3b100d20e..f33a72571c0 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 5bd56c65351..947dfcbf9eb 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -62,6 +62,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_CONS_INDEX=4 CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index e2e3a56437f..cc49e6f80ab 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 085913ef82d..dbfa2e0a8cf 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 4005f8d1afb..ab630cace7c 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -67,6 +67,7 @@ CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX7=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index 1c632770b3b..b652057d743 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -39,6 +39,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig index 42d737771c4..95549ff5b7f 100644 --- a/configs/riotboard_spl_defconfig +++ b/configs/riotboard_spl_defconfig @@ -49,6 +49,7 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y diff --git a/configs/sksimx6_defconfig b/configs/sksimx6_defconfig index 927f46f5db4..9b3706124ff 100644 --- a/configs/sksimx6_defconfig +++ b/configs/sksimx6_defconfig @@ -49,4 +49,5 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/configs/somlabs_visionsom_6ull_defconfig b/configs/somlabs_visionsom_6ull_defconfig index 739d4c9bab6..52e34e3b3f7 100644 --- a/configs/somlabs_visionsom_6ull_defconfig +++ b/configs/somlabs_visionsom_6ull_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig index e43fab208d3..239e9ed04ec 100644 --- a/configs/tbs2910_defconfig +++ b/configs/tbs2910_defconfig @@ -84,6 +84,7 @@ CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 89e9363dc56..ba1e6d31f8d 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -38,4 +38,5 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ8XXX=y CONFIG_MII=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index 37d9687c065..5f94cea5ddc 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -49,6 +49,7 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_GADGET=y diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index b0a9c652a98..31e6cfb4252 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -78,6 +78,7 @@ CONFIG_PINCTRL_IMX6=y CONFIG_PWM_IMX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig index 761fcd78219..4b45fcd50ab 100644 --- a/configs/warp7_bl33_defconfig +++ b/configs/warp7_bl33_defconfig @@ -52,6 +52,7 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_OPTEE=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig index 3fd21dd8533..3d11196080f 100644 --- a/configs/warp7_defconfig +++ b/configs/warp7_defconfig @@ -58,6 +58,7 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_OPTEE=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig index dd0b61c18f6..b77bf9a4709 100644 --- a/configs/xpress_defconfig +++ b/configs/xpress_defconfig @@ -40,6 +40,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_SMSC=y CONFIG_MII=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig index 935450efe03..aee059dea0c 100644 --- a/configs/xpress_spl_defconfig +++ b/configs/xpress_spl_defconfig @@ -51,6 +51,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_SMSC=y CONFIG_MII=y CONFIG_MXC_UART=y +CONFIG_IMX_THERMAL=y CONFIG_USB=y CONFIG_USB_STORAGE=y CONFIG_OF_LIBFDT=y diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig index 07cd0542a0a..321a9351d28 100644 --- a/configs/zc5202_defconfig +++ b/configs/zc5202_defconfig @@ -58,4 +58,5 @@ CONFIG_PCI=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig index 90736ec6ec1..ed6978e32cd 100644 --- a/configs/zc5601_defconfig +++ b/configs/zc5601_defconfig @@ -56,4 +56,5 @@ CONFIG_MII=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_MXC_SPI=y +CONFIG_IMX_THERMAL=y CONFIG_OF_LIBFDT=y diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 2ef6bfdba86..bdd5973cb71 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -35,7 +35,6 @@ #define CONFIG_SPI_FLASH_SST /* Thermal support */ -#define CONFIG_IMX_THERMAL /* I2C Configs */ #define CONFIG_SYS_I2C diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 07f1893d115..0ef55b77133 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -141,9 +141,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -/* Uncomment to enable iMX thermal driver support */ -/*#define CONFIG_IMX_THERMAL*/ - /* SPL */ #include "imx7_spl.h" diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index d373fda0168..2827c171c97 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -140,8 +140,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_IMX_THERMAL - #define CONFIG_USBD_HS /* USB Device Firmware Update support */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index b3601abe2cb..85dd8910553 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -208,8 +208,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_IMX_THERMAL - #define CONFIG_USBD_HS #if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index b27f7157983..4eb50f841e6 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -84,8 +84,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_IMX_THERMAL - #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index bd61f20a7a6..9ee7fee2d72 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -14,8 +14,6 @@ #include "mx6_common.h" -#define CONFIG_IMX_THERMAL - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index b18db76d2f1..ff3a849a144 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -17,8 +17,6 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) -#define CONFIG_IMX_THERMAL - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index a92157d52cb..7c8abda1d26 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -32,16 +32,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) -/* Init Functions */ - -/* Driver Model */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_DM_THERMAL -#endif - -/* Thermal */ -#define CONFIG_IMX_THERMAL - /* Serial */ #define CONFIG_MXC_UART_BASE UART2_BASE diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index db5e6fc133b..5adbe1ca391 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -141,6 +141,4 @@ #define CONFIG_ETHPRIME "FEC" #endif -#define CONFIG_IMX_THERMAL - #endif diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index cfab9a7fc02..55717c77ab3 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -13,8 +13,6 @@ #include "imx6_spl.h" -#define CONFIG_IMX_THERMAL - #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) /* MMC Configs */ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index c4e34e9cbc7..93d00a4dc3c 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -12,8 +12,6 @@ #include "mx6_common.h" -#define CONFIG_IMX_THERMAL - /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 44dadd681c0..ab32f4e151e 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -132,6 +132,4 @@ #define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_IMX_THERMAL - #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index 9533d307428..a38ce4d0977 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -123,8 +123,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_IMX_THERMAL - #define CONFIG_IOMUX_LPSR /* USB Configs */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 9ad29341c14..58cc3f0ee2b 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -138,8 +138,6 @@ #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif -#define CONFIG_IMX_THERMAL - #define CONFIG_SYS_FSL_USDHC_NUM 2 #endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 42feb140197..036881f6ea3 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -170,8 +170,6 @@ #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif -#define CONFIG_IMX_THERMAL - #ifndef CONFIG_SPL_BUILD #ifdef CONFIG_VIDEO #define CONFIG_VIDEO_MXS diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index fa6b303dd4a..7d36c1e4d90 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -177,8 +177,6 @@ #endif #endif -#define CONFIG_IMX_THERMAL - #ifndef CONFIG_SPL_BUILD #if defined(CONFIG_DM_VIDEO) #define CONFIG_VIDEO_MXS diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index ca2f2bd975d..23f6de9050c 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -150,8 +150,6 @@ /* environment organization */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -#define CONFIG_IMX_THERMAL - #define CONFIG_IOMUX_LPSR #define CONFIG_SOFT_SPI diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index 51a7a5f4a0e..5801da0cfac 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -134,8 +134,6 @@ /* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_IMX_THERMAL - #define CONFIG_USBD_HS #ifdef CONFIG_VIDEO diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 208779958f5..5ef16fb278e 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -50,8 +50,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_IMX_THERMAL - #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h index bf8f7b1e1b7..ea61f92bdbb 100644 --- a/include/configs/ot1200.h +++ b/include/configs/ot1200.h @@ -74,9 +74,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 #endif -/* Thermal support */ -#define CONFIG_IMX_THERMAL - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 2156da671b2..4f4d50131f5 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -62,8 +62,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_IMX_THERMAL - #define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc0,115200n8\0" \ "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index d7c6f8808e0..6009521c9f7 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -69,8 +69,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#define CONFIG_IMX_THERMAL - #define ENV_MMC \ "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h index 3227c4276e1..e96429083ed 100644 --- a/include/configs/pfla02.h +++ b/include/configs/pfla02.h @@ -13,9 +13,6 @@ #include "mx6_common.h" -/* Thermal */ -#define CONFIG_IMX_THERMAL - /* Serial */ #define CONFIG_MXC_UART_BASE UART4_BASE #define CONSOLE_DEV "ttymxc3" diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 51b7359cad9..80de1158ad1 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -168,6 +168,4 @@ #define CONFIG_MXC_USB_FLAGS 0 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_IMX_THERMAL - #endif diff --git a/include/configs/sksimx6.h b/include/configs/sksimx6.h index 511b1a440e8..7052d8049e4 100644 --- a/include/configs/sksimx6.h +++ b/include/configs/sksimx6.h @@ -10,9 +10,6 @@ #include "mx6_common.h" #include "imx6_spl.h" -/* Thermal */ -#define CONFIG_IMX_THERMAL - /* Serial */ #define CONFIG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index 204818b8eb7..945d0ecc737 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -104,6 +104,4 @@ #define CONFIG_ETHPRIME "eth0" #endif -#define CONFIG_IMX_THERMAL - #endif diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h index 01c1143e43c..a2e59ce6185 100644 --- a/include/configs/tbs2910.h +++ b/include/configs/tbs2910.h @@ -16,8 +16,6 @@ #define CONFIG_SYS_HZ 1000 -#define CONFIG_IMX_THERMAL - /* Physical Memory Map */ #define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index 34a95a0283f..4935a2b363e 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -70,10 +70,6 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) -/* Environment organization */ - -#define CONFIG_IMX_THERMAL - /* I2C configs */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index a851fb41a81..f97431f1354 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -73,8 +73,6 @@ #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) #endif -#define CONFIG_IMX_THERMAL - #define CONFIG_IMX6_PWM_PER_CLK 66000000 #ifdef CONFIG_ENV_IS_IN_MMC diff --git a/include/configs/warp7.h b/include/configs/warp7.h index 2d1ede3bc8d..8eb10602744 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -146,8 +146,6 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_IMX_THERMAL - #define CONFIG_USBD_HS /* USB Device Firmware Update support */ diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 399925a75bd..e7a26589d67 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -63,8 +63,6 @@ #define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_ETHPRIME "FEC" -#define CONFIG_IMX_THERMAL - #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_UBOOT_SECTOR_START 0x2 -- cgit v1.3.1 From 0f8106f8e0c03839b371eaee1d7459b810d569ec Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 2 Dec 2020 18:47:30 +0100 Subject: treewide: Update email address Patrick Delaunay and Patrice Chotard Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/include/asm/arch-stih410/sdhci.h | 2 +- arch/arm/include/asm/arch-stih410/sys_proto.h | 2 +- arch/arm/include/asm/arch-stm32/stm32f.h | 2 +- arch/arm/include/asm/arch-stm32f4/stm32_pwr.h | 2 +- arch/arm/include/asm/arch-stm32f7/stm32_pwr.h | 2 +- arch/arm/include/asm/arch-stm32h7/gpio.h | 2 +- arch/arm/include/asm/arch-stm32h7/stm32.h | 2 +- arch/arm/mach-stm32/soc.c | 2 +- board/st/stih410-b2260/board.c | 2 +- board/st/stm32f429-evaluation/stm32f429-evaluation.c | 2 +- board/st/stm32f469-discovery/stm32f469-discovery.c | 2 +- board/st/stm32h743-disco/stm32h743-disco.c | 2 +- board/st/stm32h743-eval/stm32h743-eval.c | 2 +- drivers/clk/clk_stm32h7.c | 2 +- drivers/misc/stm32_rcc.c | 2 +- drivers/mmc/sti_sdhci.c | 2 +- drivers/mmc/stm32_sdmmc2.c | 2 +- drivers/phy/sti_usb_phy.c | 2 +- drivers/pinctrl/pinctrl-sti.c | 2 +- drivers/reset/sti-reset.c | 2 +- drivers/reset/stm32-reset.c | 2 +- drivers/serial/serial_sti_asc.c | 2 +- drivers/sysreset/sysreset_sti.c | 2 +- drivers/timer/sti-timer.c | 2 +- drivers/timer/stm32_timer.c | 2 +- drivers/usb/host/dwc3-sti-glue.c | 2 +- drivers/video/backlight_gpio.c | 2 +- include/configs/stih410-b2260.h | 2 +- include/configs/stm32f429-evaluation.h | 2 +- include/configs/stm32f469-discovery.h | 2 +- include/configs/stm32h743-disco.h | 2 +- include/configs/stm32h743-eval.h | 2 +- include/dwc3-sti-glue.h | 2 +- include/stm32_rcc.h | 2 +- 34 files changed, 34 insertions(+), 34 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-stih410/sdhci.h b/arch/arm/include/asm/arch-stih410/sdhci.h index d5557b89fcb..1735c0e3918 100644 --- a/arch/arm/include/asm/arch-stih410/sdhci.h +++ b/arch/arm/include/asm/arch-stih410/sdhci.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __STI_SDHCI_H__ diff --git a/arch/arm/include/asm/arch-stih410/sys_proto.h b/arch/arm/include/asm/arch-stih410/sys_proto.h index f9e8d3704a8..30e7f398ebe 100644 --- a/arch/arm/include/asm/arch-stih410/sys_proto.h +++ b/arch/arm/include/asm/arch-stih410/sys_proto.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef _ASM_ARCH_SYS_PROTO_H diff --git a/arch/arm/include/asm/arch-stm32/stm32f.h b/arch/arm/include/asm/arch-stm32/stm32f.h index bd3f4fd30ae..a1ce81ecadd 100644 --- a/arch/arm/include/asm/arch-stm32/stm32f.h +++ b/arch/arm/include/asm/arch-stm32/stm32f.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef _ASM_ARCH_STM32F_H diff --git a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h index 8af6de220d8..fe6ca03d2df 100644 --- a/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h +++ b/arch/arm/include/asm/arch-stm32f4/stm32_pwr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __STM32_PWR_H_ diff --git a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h index 02faaeb663c..5cd6553d04d 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32_pwr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __STM32_PWR_H_ diff --git a/arch/arm/include/asm/arch-stm32h7/gpio.h b/arch/arm/include/asm/arch-stm32h7/gpio.h index 2dad52a4002..4f57f175ff6 100644 --- a/arch/arm/include/asm/arch-stm32h7/gpio.h +++ b/arch/arm/include/asm/arch-stm32h7/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef _STM32_GPIO_H_ diff --git a/arch/arm/include/asm/arch-stm32h7/stm32.h b/arch/arm/include/asm/arch-stm32h7/stm32.h index 458baca458b..2b0a6700080 100644 --- a/arch/arm/include/asm/arch-stm32h7/stm32.h +++ b/arch/arm/include/asm/arch-stm32h7/stm32.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef _ASM_ARCH_HARDWARE_H diff --git a/arch/arm/mach-stm32/soc.c b/arch/arm/mach-stm32/soc.c index 1f12da401c1..0bd8d7b22c4 100644 --- a/arch/arm/mach-stm32/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/board/st/stih410-b2260/board.c b/board/st/stih410-b2260/board.c index b1147f2e1a7..e06f05bfa48 100644 --- a/board/st/stih410-b2260/board.c +++ b/board/st/stih410-b2260/board.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c index 92e3d40a1b6..22a193d8fc3 100644 --- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c index 85988acb241..4ad4ee69c7c 100644 --- a/board/st/stm32f469-discovery/stm32f469-discovery.c +++ b/board/st/stm32f469-discovery/stm32f469-discovery.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) STMicroelectronics SA 2017 - * Author(s): Patrice CHOTARD, for STMicroelectronics. + * Author(s): Patrice CHOTARD, for STMicroelectronics. */ #include diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c index 0484c3c2504..0b5afa05ac7 100644 --- a/board/st/stm32h743-disco/stm32h743-disco.c +++ b/board/st/stm32h743-disco/stm32h743-disco.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c index 0484c3c2504..0b5afa05ac7 100644 --- a/board/st/stm32h743-eval/stm32h743-eval.c +++ b/board/st/stm32h743-eval/stm32h743-eval.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/clk_stm32h7.c index 5e6abca56fa..edf90ee00f3 100644 --- a/drivers/clk/clk_stm32h7.c +++ b/drivers/clk/clk_stm32h7.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/misc/stm32_rcc.c b/drivers/misc/stm32_rcc.c index b82fe54c600..86275454be0 100644 --- a/drivers/misc/stm32_rcc.c +++ b/drivers/misc/stm32_rcc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/mmc/sti_sdhci.c b/drivers/mmc/sti_sdhci.c index 5578feebef7..c3a1b344427 100644 --- a/drivers/mmc/sti_sdhci.c +++ b/drivers/mmc/sti_sdhci.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/mmc/stm32_sdmmc2.c b/drivers/mmc/stm32_sdmmc2.c index 77871d5afc9..1f1b6cf4fb5 100644 --- a/drivers/mmc/stm32_sdmmc2.c +++ b/drivers/mmc/stm32_sdmmc2.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/phy/sti_usb_phy.c b/drivers/phy/sti_usb_phy.c index 2a20f7601c0..51468b45732 100644 --- a/drivers/phy/sti_usb_phy.c +++ b/drivers/phy/sti_usb_phy.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/pinctrl/pinctrl-sti.c b/drivers/pinctrl/pinctrl-sti.c index 8e942a82802..2f3ee004532 100644 --- a/drivers/pinctrl/pinctrl-sti.c +++ b/drivers/pinctrl/pinctrl-sti.c @@ -3,7 +3,7 @@ * Pinctrl driver for STMicroelectronics STi SoCs * * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/reset/sti-reset.c b/drivers/reset/sti-reset.c index ac3a99f9bff..2cca67dc52a 100644 --- a/drivers/reset/sti-reset.c +++ b/drivers/reset/sti-reset.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c index 20c36a99eb3..d8902e9d9cc 100644 --- a/drivers/reset/stm32-reset.c +++ b/drivers/reset/stm32-reset.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/serial/serial_sti_asc.c b/drivers/serial/serial_sti_asc.c index 33ff396bff7..91e15746388 100644 --- a/drivers/serial/serial_sti_asc.c +++ b/drivers/serial/serial_sti_asc.c @@ -3,7 +3,7 @@ * Support for Serial I/O using STMicroelectronics' on-chip ASC. * * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/sysreset/sysreset_sti.c b/drivers/sysreset/sysreset_sti.c index 3482d2a0787..43e161c65dc 100644 --- a/drivers/sysreset/sysreset_sti.c +++ b/drivers/sysreset/sysreset_sti.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/timer/sti-timer.c b/drivers/timer/sti-timer.c index e6843ebb337..9d95f562fac 100644 --- a/drivers/timer/sti-timer.c +++ b/drivers/timer/sti-timer.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/timer/stm32_timer.c b/drivers/timer/stm32_timer.c index f517d5e61f2..2f5f8f43b96 100644 --- a/drivers/timer/stm32_timer.c +++ b/drivers/timer/stm32_timer.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/usb/host/dwc3-sti-glue.c b/drivers/usb/host/dwc3-sti-glue.c index 3e6c1429d66..9dec0877389 100644 --- a/drivers/usb/host/dwc3-sti-glue.c +++ b/drivers/usb/host/dwc3-sti-glue.c @@ -3,7 +3,7 @@ * STiH407 family DWC3 specific Glue layer * * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #include diff --git a/drivers/video/backlight_gpio.c b/drivers/video/backlight_gpio.c index 67fed7f224a..433d0979e88 100644 --- a/drivers/video/backlight_gpio.c +++ b/drivers/video/backlight_gpio.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author: Patrick Delaunay + * Author: Patrick Delaunay */ #include diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h index 169b9efeec8..33b34ee0cd3 100644 --- a/include/configs/stih410-b2260.h +++ b/include/configs/stih410-b2260.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h index 8390535af0a..fefdb2dd152 100644 --- a/include/configs/stm32f429-evaluation.h +++ b/include/configs/stm32f429-evaluation.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) STMicroelectronics SA 2017 - * Author(s): Patrice CHOTARD, for STMicroelectronics. + * Author(s): Patrice CHOTARD, for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index 57fb6b25afd..ba9f05a61b4 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) STMicroelectronics SA 2017 - * Author(s): Patrice CHOTARD, for STMicroelectronics. + * Author(s): Patrice CHOTARD, for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h index afc98ae791b..6e10dbdfe94 100644 --- a/include/configs/stm32h743-disco.h +++ b/include/configs/stm32h743-disco.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h index 66af8f50d90..268d39c7ad6 100644 --- a/include/configs/stm32h743-eval.h +++ b/include/configs/stm32h743-eval.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __CONFIG_H diff --git a/include/dwc3-sti-glue.h b/include/dwc3-sti-glue.h index 3989a9bb536..546ffbaf7b4 100644 --- a/include/dwc3-sti-glue.h +++ b/include/dwc3-sti-glue.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. + * Author(s): Patrice Chotard, for STMicroelectronics. */ #ifndef __DWC3_STI_UBOOT_H_ diff --git a/include/stm32_rcc.h b/include/stm32_rcc.h index a09a09ff955..b559ea77281 100644 --- a/include/stm32_rcc.h +++ b/include/stm32_rcc.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) STMicroelectronics SA 2017 - * Author(s): Patrice CHOTARD, for STMicroelectronics. + * Author(s): Patrice CHOTARD, for STMicroelectronics. */ #ifndef __STM32_RCC_H_ -- cgit v1.3.1 From 2a29a9a1b41200b228651a4dc13f88ff00301b62 Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Thu, 29 Oct 2020 19:16:15 +0530 Subject: drivers/net/phy: Add CORTINA_NO_FW_UPLOAD to Kconfig Move CORTINA_NO_FW_UPLOAD to Kconfig file so that it can be controlled via defconfig files. Signed-off-by: Meenakshi Aggarwal Reviewed-by: Priyanka Jain --- configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig | 1 + drivers/net/phy/Kconfig | 9 +++++++++ drivers/net/phy/cortina.c | 8 ++++---- include/configs/lx2160aqds.h | 1 - include/configs/lx2160ardb.h | 1 - 9 files changed, 18 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 9d60fe8a96f..cf4bf8a19a6 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -56,6 +56,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 391ea174fd0..f0e8dca8f92 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -63,6 +63,7 @@ CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_PHY_REALTEK=y CONFIG_PHY_VITESSE=y CONFIG_DM_ETH=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 22db7fbdd5b..0551ef07930 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -52,6 +52,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index a82f14ec1ca..52ac1264aee 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -61,6 +61,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index d3c76832c8b..d9c16740266 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -61,6 +61,7 @@ CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_PHY_ATHEROS=y CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y CONFIG_DM_ETH=y CONFIG_DM_MDIO=y CONFIG_E1000=y diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 4e1a93be221..51733dd1237 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -100,6 +100,15 @@ config PHY_BROADCOM config PHY_CORTINA bool "Cortina Ethernet PHYs support" +config SYS_CORTINA_NO_FW_UPLOAD + bool "Cortina firmware loading support" + default n + depends on PHY_CORTINA + help + Cortina phy has provision to store phy firmware in attached dedicated + EEPROM. And boards designed with such EEPROM does not require firmware + upload. + choice prompt "Location of the Cortina firmware" default SYS_CORTINA_FW_IN_NOR diff --git a/drivers/net/phy/cortina.c b/drivers/net/phy/cortina.c index dbc20b14051..b381a431fd9 100644 --- a/drivers/net/phy/cortina.c +++ b/drivers/net/phy/cortina.c @@ -3,7 +3,7 @@ * Cortina CS4315/CS4340 10G PHY drivers * * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2018 NXP + * Copyright 2018, 2020 NXP * */ @@ -29,7 +29,7 @@ #error The Cortina PHY needs 10G support #endif -#ifndef CORTINA_NO_FW_UPLOAD +#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD struct cortina_reg_config cortina_reg_cfg[] = { /* CS4315_enable_sr_mode */ {VILLA_GLOBAL_MSEQCLKCTRL, 0x8004}, @@ -227,7 +227,7 @@ void cs4340_upload_firmware(struct phy_device *phydev) int cs4340_phy_init(struct phy_device *phydev) { -#ifndef CORTINA_NO_FW_UPLOAD +#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD int timeout = 100; /* 100ms */ #endif int reg_value; @@ -238,7 +238,7 @@ int cs4340_phy_init(struct phy_device *phydev) * Boards designed with EEPROM attached to Cortina * does not require FW upload. */ -#ifndef CORTINA_NO_FW_UPLOAD +#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD /* step1: BIST test */ phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 1cc015c1c77..12884bcf2be 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -93,7 +93,6 @@ u8 qixis_esdhc_detect_quirk(void); #define AQ_PHY_ADDR3 0x02 #define AQ_PHY_ADDR4 0x03 -#define CORTINA_NO_FW_UPLOAD #define CORTINA_PHY_ADDR1 0x0 #define INPHI_PHY_ADDR1 0x0 diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index a51987e6b09..59c2305a34d 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -64,7 +64,6 @@ #define AQR107_PHY_ADDR2 0x05 #define AQR107_IRQ_MASK 0x0C -#define CORTINA_NO_FW_UPLOAD #define CORTINA_PHY_ADDR1 0x0 #define INPHI_PHY_ADDR1 0x0 -- cgit v1.3.1 From 9ed303dfa97b773c4f4743238ea32b68e340afa9 Mon Sep 17 00:00:00 2001 From: Meenakshi Aggarwal Date: Fri, 4 Dec 2020 20:17:28 +0530 Subject: armv8: lx2162aqds: Add support for LX2162AQDS platform This patch add base support for LX2162AQDS board. LX2162AQDS board supports LX2162A family SoCs. This patch add basic support of platform. Signed-off-by: Ioana Ciornei Signed-off-by: Zhao Qiang Signed-off-by: hui.song Signed-off-by: Manish Tomar Signed-off-by: Vikas Singh Signed-off-by: Meenakshi Aggarwal [Rebased] Signed-off-by: Priyanka Jain --- arch/arm/Kconfig | 12 + arch/arm/dts/Makefile | 6 +- arch/arm/dts/fsl-lx2160a-qds.dts | 3 - arch/arm/dts/fsl-lx2160a-qds.dtsi | 22 +- arch/arm/dts/fsl-lx2162a-qds-17-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-18-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-20-x.dts | 17 + arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi | 58 ++ arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi | 61 ++ arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi | 26 + arch/arm/dts/fsl-lx2162a-qds.dts | 34 + board/freescale/common/qixis.h | 25 + board/freescale/common/vid.h | 30 + board/freescale/lx2160a/Kconfig | 16 + board/freescale/lx2160a/MAINTAINERS | 26 + board/freescale/lx2160a/Makefile | 1 + board/freescale/lx2160a/README | 132 ++++ board/freescale/lx2160a/eth_lx2160ardb.c | 3 +- board/freescale/lx2160a/eth_lx2162aqds.c | 974 +++++++++++++++++++++++++ board/freescale/lx2160a/lx2160a.c | 43 +- board/freescale/lx2160a/lx2160a.h | 61 ++ configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 98 +++ configs/lx2162aqds_tfa_defconfig | 96 +++ configs/lx2162aqds_tfa_verified_boot_defconfig | 103 +++ include/configs/lx2160a_common.h | 2 + include/configs/lx2160aqds.h | 75 -- include/configs/lx2160ardb.h | 49 -- include/configs/lx2162aqds.h | 78 ++ 28 files changed, 1935 insertions(+), 150 deletions(-) create mode 100644 arch/arm/dts/fsl-lx2162a-qds-17-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-18-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-20-x.dts create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi create mode 100644 arch/arm/dts/fsl-lx2162a-qds.dts create mode 100644 board/freescale/lx2160a/eth_lx2162aqds.c create mode 100644 board/freescale/lx2160a/lx2160a.h create mode 100644 configs/lx2162aqds_tfa_SECURE_BOOT_defconfig create mode 100644 configs/lx2162aqds_tfa_defconfig create mode 100644 configs/lx2162aqds_tfa_verified_boot_defconfig create mode 100644 include/configs/lx2162aqds.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 5903c093705..fbe90875ae4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1326,6 +1326,18 @@ config TARGET_LX2160AQDS is a high-performance development platform that supports the QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor. +config TARGET_LX2162AQDS + bool "Support lx2162aqds" + select ARCH_LX2162A + select ARCH_MISC_INIT + select ARM64 + select ARMV8_MULTIENTRY + select ARCH_SUPPORT_TFABOOT + select BOARD_LATE_INIT + help + Support for NXP LX2162AQDS platform. + The lx2162aqds support is based on LX2160A Layerscape Architecture processor. + config TARGET_HIKEY bool "Support HiKey 96boards Consumer Edition Platform" select ARM64 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 02d04f5a8cd..fd47e408f82 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -414,7 +414,11 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-lx2160a-qds-19-x-x.dtb \ fsl-lx2160a-qds-19-11-x.dtb \ fsl-lx2160a-qds-20-x-x.dtb \ - fsl-lx2160a-qds-20-11-x.dtb + fsl-lx2160a-qds-20-11-x.dtb \ + fsl-lx2162a-qds.dtb\ + fsl-lx2162a-qds-17-x.dtb\ + fsl-lx2162a-qds-18-x.dtb\ + fsl-lx2162a-qds-20-x.dtb dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ fsl-ls1043a-qds-lpuart.dtb \ fsl-ls1043a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-lx2160a-qds.dts b/arch/arm/dts/fsl-lx2160a-qds.dts index e0f5d5e2d38..332c778d3a6 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dts +++ b/arch/arm/dts/fsl-lx2160a-qds.dts @@ -13,7 +13,4 @@ / { model = "NXP Layerscape LX2160AQDS Board"; compatible = "fsl,lx2160aqds", "fsl,lx2160a"; - aliases { - spi0 = &fspi; - }; }; diff --git a/arch/arm/dts/fsl-lx2160a-qds.dtsi b/arch/arm/dts/fsl-lx2160a-qds.dtsi index 96c980004bf..288607c0347 100644 --- a/arch/arm/dts/fsl-lx2160a-qds.dtsi +++ b/arch/arm/dts/fsl-lx2160a-qds.dtsi @@ -2,12 +2,18 @@ /* * NXP LX2160AQDS common device tree source * - * Copyright 2018-2019 NXP + * Copyright 2018-2020 NXP * */ #include "fsl-lx2160a.dtsi" +/ { + aliases { + spi0 = &fspi; + }; +}; + &dpmac17 { status = "okay"; phy-handle = <&rgmii_phy1>; @@ -251,6 +257,20 @@ }; }; +&fspi { + status = "okay"; + + mt35xu512aba0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <50000000>; + reg = <0>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; + }; +}; + &sata0 { status = "okay"; }; diff --git a/arch/arm/dts/fsl-lx2162a-qds-17-x.dts b/arch/arm/dts/fsl-lx2162a-qds-17-x.dts new file mode 100644 index 00000000000..8a8895f0238 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-17-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for SERDES protocol 17.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2162a-qds-sd1-17.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 17.x)"; + compatible = "fsl,lx2162aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-18-x.dts b/arch/arm/dts/fsl-lx2162a-qds-18-x.dts new file mode 100644 index 00000000000..c28e5e24972 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-18-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for SERDES protocol 18.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2162a-qds-sd1-18.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 18.x)"; + compatible = "fsl,lx2162aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-20-x.dts b/arch/arm/dts/fsl-lx2162a-qds-20-x.dts new file mode 100644 index 00000000000..7882c767e29 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-20-x.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for SERDES protocol 20.x + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2162a-qds-sd1-20.dtsi" + +/ { + model = "NXP Layerscape LX2160AQDS Board (DTS 20.x)"; + compatible = "fsl,lx2162aqds", "fsl,lx2160a"; + +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi new file mode 100644 index 00000000000..60f5a4ee435 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 17 + * + * Some assumptions are made: + * * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac3 { + status = "okay"; + phy-handle = <&inphi_phy0>; + phy-connection-type = "25g-aui"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&inphi_phy1>; + phy-connection-type = "25g-aui"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&inphi_phy2>; + phy-connection-type = "25g-aui"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&inphi_phy3>; + phy-connection-type = "25g-aui"; +}; + +&emdio1_slot1 { + inphi_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; + + inphi_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x1>; + }; + + inphi_phy2: ethernet-phy@2 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x2>; + }; + + inphi_phy3: ethernet-phy@3 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x3>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi new file mode 100644 index 00000000000..8e11b0680a9 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 18 + * + * Some assumptions are made: + * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4) + * * mezzanine card M13/M8 is connected to IO SLOT6 (25g-aui for DPMAC 5,6) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac3 { + status = "okay"; + phy-handle = <&aquantia_phy1>; + phy-connection-type = "usxgmii"; +}; + +&dpmac4 { + status = "okay"; + phy-handle = <&aquantia_phy2>; + phy-connection-type = "usxgmii"; +}; + +&dpmac5 { + status = "okay"; + phy-handle = <&inphi_phy0>; + phy-connection-type = "25g-aui"; +}; + +&dpmac6 { + status = "okay"; + phy-handle = <&inphi_phy1>; + phy-connection-type = "25g-aui"; +}; + +&emdio1_slot1 { + aquantia_phy1: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + aquantia_phy2: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; +}; + +&emdio1_slot6 { + inphi_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x0>; + }; + + inphi_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0210.7440"; + reg = <0x1>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi new file mode 100644 index 00000000000..faf4285eaba --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source for the SERDES block #1 - protocol 20 + * + * Some assumptions are made: + * * Mezzanine card M8 is connected to IO SLOT1 + * (xlaui4 for DPMAC 1) + * + * Copyright 2020 NXP + * + */ + +#include "fsl-lx2160a-qds.dtsi" + +&dpmac1 { + status = "okay"; + phy-handle = <&cortina_phy1_0>; + phy-connection-type = "xlaui4"; +}; + +&emdio1_slot1 { + cortina_phy1_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts new file mode 100644 index 00000000000..b16526503d9 --- /dev/null +++ b/arch/arm/dts/fsl-lx2162a-qds.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LX2162AQDS device tree source + * + * Copyright 2020 NXP + * + */ + +/dts-v1/; + +#include "fsl-lx2160a-qds.dtsi" + +/ { + model = "NXP Layerscape LX2162AQDS Board"; + compatible = "fsl,lx2162aqds", "fsl,lx2160a"; + + aliases { + pcie@3500000 { + status = "disabled"; + }; + + pcie@3800000 { + status = "disabled"; + }; + + pcie@3900000 { + status = "disabled"; + }; + }; +}; + +&usb1 { + status = "disabled"; +}; diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index 93638d24524..0860bd23126 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -141,4 +141,29 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_EVDD_BY_SDHC_VS 0x0c +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ +defined(CONFIG_TARGET_LX2160ARDB) +#define QIXIS_XMAP_MASK 0x07 +#define QIXIS_RST_CTL_RESET_EN 0x30 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x20 +#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_RCW_SRC_QSPI 0xff +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SD +#define QIXIS_LBMAP_EMMC +#define QIXIS_RCW_SRC_SD 0x08 +#define QIXIS_RCW_SRC_EMMC 0x09 +#define NON_EXTENDED_DUTCFG +#endif + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +#define QIXIS_SDID_MASK 0x07 +#define QIXIS_ESDHC_NO_ADAPTER 0x7 +#endif + #endif diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h index 65b348ee42f..5bbaecace4e 100644 --- a/board/freescale/common/vid.h +++ b/board/freescale/common/vid.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. + * Copyright 2020 NXP */ #ifndef __VID_H_ @@ -37,6 +38,35 @@ */ #define EN_WRITE_ALL_CMD (0) +#ifdef CONFIG_TARGET_LX2160ARDB +/* The lowest and highest voltage allowed*/ +#define VDD_MV_MIN 775 +#define VDD_MV_MAX 855 +#endif + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +/* The lowest and highest voltage allowed*/ +#define VDD_MV_MIN 775 +#define VDD_MV_MAX 925 +#endif + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) || \ +defined(CONFIG_TARGET_LX2160ARDB) +/* PM Bus commands code for LTC3882*/ +#define PWM_CHANNEL0 0x0 +#define PMBUS_CMD_PAGE 0x0 +#define PMBUS_CMD_READ_VOUT 0x8B +#define PMBUS_CMD_VOUT_COMMAND 0x21 +#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 + +/* Voltage monitor on channel 2*/ +#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 +#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 +#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 +#define I2C_VOL_MONITOR_ADDR 0x63 +#define I2C_MUX_CH_VOL_MONITOR 0xA +#endif + int adjust_vdd(ulong vdd_override); #endif /* __VID_H_ */ diff --git a/board/freescale/lx2160a/Kconfig b/board/freescale/lx2160a/Kconfig index 122a385100a..7556f7dd215 100644 --- a/board/freescale/lx2160a/Kconfig +++ b/board/freescale/lx2160a/Kconfig @@ -32,3 +32,19 @@ config SYS_CONFIG_NAME source "board/freescale/common/Kconfig" endif +if TARGET_LX2162AQDS + +config SYS_BOARD + default "lx2160a" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "lx2162aqds" + +source "board/freescale/common/Kconfig" +endif diff --git a/board/freescale/lx2160a/MAINTAINERS b/board/freescale/lx2160a/MAINTAINERS index 9fe79c0ef7a..c627417cf72 100644 --- a/board/freescale/lx2160a/MAINTAINERS +++ b/board/freescale/lx2160a/MAINTAINERS @@ -1,4 +1,5 @@ LX2160ARDB BOARD +M: Meenakshi Aggarwal M: Priyanka Jain S: Maintained F: board/freescale/lx2160a/ @@ -14,6 +15,7 @@ S: Maintained F: configs/lx2160ardb_tfa_SECURE_BOOT_defconfig LX2160AQDS BOARD +M: Meenakshi Aggarwal M: Pankaj Bansal S: Maintained F: board/freescale/lx2160a/eth_lx2160aqds.h @@ -25,3 +27,27 @@ LX2160AQDS_SECURE_BOOT BOARD M: Udit Agarwal S: Maintained F: configs/lx2160aqds_tfa_SECURE_BOOT_defconfig + +LX2162AQDS BOARD +M: Meenakshi Aggarwal +S: Maintained +F: board/freescale/lx2160a/eth_lx2162aqds.h +F: include/configs/lx2162aqds.h +F: configs/lx2162aqds_tfa_defconfig +F: arch/arm/dts/fsl-lx2162a-qds.dts +F: arch/arm/dts/fsl-lx2162a-qds-17-x.dts +F: arch/arm/dts/fsl-lx2162a-qds-18-x.dts +F: arch/arm/dts/fsl-lx2162a-qds-20-x.dts +F: arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi +F: arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi +F: arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi + +LX2162AQDS_SECURE_BOOT BOARD +M: Manish Tomar +S: Maintained +F: configs/lx2162aqds_tfa_SECURE_BOOT_defconfig + +LX2162AQDS_VERIFIED_BOOT BOARD +M: Manish Tomar +S: Maintained +F: configs/lx2162aqds_tfa_verified_boot_defconfig diff --git a/board/freescale/lx2160a/Makefile b/board/freescale/lx2160a/Makefile index d1a621b6821..c9561bfadea 100644 --- a/board/freescale/lx2160a/Makefile +++ b/board/freescale/lx2160a/Makefile @@ -8,3 +8,4 @@ obj-y += lx2160a.o obj-y += ddr.o obj-$(CONFIG_TARGET_LX2160ARDB) += eth_lx2160ardb.o obj-$(CONFIG_TARGET_LX2160AQDS) += eth_lx2160aqds.o +obj-$(CONFIG_TARGET_LX2162AQDS) += eth_lx2162aqds.o diff --git a/board/freescale/lx2160a/README b/board/freescale/lx2160a/README index 62fb9eab151..7bca98dd3d7 100644 --- a/board/freescale/lx2160a/README +++ b/board/freescale/lx2160a/README @@ -195,3 +195,135 @@ SERDES3 |CARDS |Connect I/O cable to IO_SLOT6(J125) ------------------------------------------------------------------------- +LX2162A SoC Overview +-------------------------------------- +For details, please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc + +LX2162AQDS board Overview +---------------------- +DDR Memory + One ports of 72-bits (8-bits ECC) DDR4. + Each port supports four chip-selects and two DIMM + connectors. Data rate upto 2.9 GT/s. + +SERDES ports + Two serdes controllers (12 lanes) + Serdes1: Supports two USXGMII connectors, each connected through + Aquantia AQR107 phy, two 25GbE SFP+ modules connected through an Inphi + IN112525 phy and one 40 GbE QSFP+ module connected through an Inphi + CS4223 phy. + + Serdes2: Supports two PCIe x4 (Gen3) and one PCIe x8 (Gen3) connector, + four SATA 3.0 connectors + +eSDHC + eSDHC1: Supports a SD connector for connecting SD cards + eSDHC2: Supports 128GB Micron MTFC128GAJAECE-IT eMMC + +Octal SPI (XSPI) + Supports two 64 MB onbpard octal SPI flash memories, one SPI emulator + for off-board emulation + +I2C All system devices on I2C1 multiplexed using PCA9547 multiplexer + Serial Ports + +USB 3.0 + One high speed USB 3.0 ports. First USB 3.0 port configured as Host + with Type-A connector, second USB 3.0 port configured as OTG with + micro-AB connector + +Serial Ports Two UART ports +Ethernet Two RGMII interfaces +Debug ARM JTAG support + +Booting Options +--------------- +a) Flexspi boot +b) SD boot +c) eMMC boot + +Memory map for Flexspi flash +---------------------------- +Image Flash Offset +bl2_flexspi_nor.pbl (RCW+PBI+bl2.pbl) 0x00000000 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00100000 +Boot firmware Environment 0x00500000 +DDR PHY Firmware (fip_ddr_all.bin) 0x00800000 +DPAA2 MC Firmware 0x00A00000 +DPAA2 DPL 0x00D00000 +DPAA2 DPC 0x00E00000 +Kernel.itb 0x01000000 + +Memory map for sd/eMMC card +---------------------------- +Image SD/eMMC card Offset +bl2_sd.pbl (RCW+PBI+bl2.pbl) 0x00008 +fip.bin (bl31 + bl33(u-boot) + + header for Secure-boot(secure-boot only)) 0x00800 +Boot firmware Environment 0x02800 +DDR PHY Firmware (fip_ddr_all.bin) 0x04000 +DPAA2 MC Firmware 0x05000 +DPAA2 DPL 0x06800 +DPAA2 DPC 0x07000 +Kernel.itb 0x08000 + +Various Mezzanine cards and their connection for different SERDES protocols is +as below: + +SERDES1 |CARDS +----------------------------------------------------------------------- +1 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +3 |Mezzanine:X-M11-USXGMII (29828) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +15 |Mezzanine:X-M8-50G (29734) + |Connect Hydra Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +17 |Mezzanine:X-M13-25G (32133) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J110) +------------------------------------------------------------------------ +18 |Mezzanine:X-M11-USXGMII (29828), X-M13-25G (32133) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT1 (J108) + |Connect M11 I/O cable to IO_SLOT1(J110), M13 I/O cable to IO_SLOT6(J125) +------------------------------------------------------------------------ +20 |Mezzanine:X-M7-40G (29738) + |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT1 (J108) + |Connect I/O cable to IO_SLOT1(J108) +------------------------------------------------------------------------ + + +SERDES2 |CARDS +----------------------------------------------------------------------- +2 |Mezzanine:X-M6-PCIE-X8 (29737) * + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect Straight Cable (HDR-198816-XX-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT3(J116) +------------------------------------------------------------------------ +3 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT3(J116) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT4(J119) +------------------------------------------------------------------------ +5 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT3(J116) + |Mezzanine:X-M5-SATA (29687) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT4(J119) +------------------------------------------------------------------------ +11 |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT3 (J114) + |Connect I/O cable to IO_SLOT7(J127) + |Mezzanine:X-M4-PCIE-SGMII (29733) + |Connect Hydra Cable (HDR-198564-01-ECUE) to SD_SLOT4 (J117) + |Connect I/O cable to IO_SLOT8(J131) +------------------------------------------------------------------------ diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c index b448883ee14..b3125b7748d 100644 --- a/board/freescale/lx2160a/eth_lx2160ardb.c +++ b/board/freescale/lx2160a/eth_lx2160ardb.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2018 NXP + * Copyright 2018, 2020 NXP * */ @@ -19,6 +19,7 @@ #include #include #include +#include "lx2160a.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/lx2160a/eth_lx2162aqds.c b/board/freescale/lx2160a/eth_lx2162aqds.c new file mode 100644 index 00000000000..4683f674f0e --- /dev/null +++ b/board/freescale/lx2160a/eth_lx2162aqds.c @@ -0,0 +1,974 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_DM_ETH +#define EMI_NONE 0 +#define EMI1 1 /* Mdio Bus 1 */ +#define EMI2 2 /* Mdio Bus 2 */ + +#if defined(CONFIG_FSL_MC_ENET) +enum io_slot { + IO_SLOT_NONE = 0, + IO_SLOT_1, + IO_SLOT_2, + IO_SLOT_3, + IO_SLOT_4, + IO_SLOT_5, + IO_SLOT_6, + IO_SLOT_7, + IO_SLOT_8, + EMI1_RGMII1, + EMI1_RGMII2, + IO_SLOT_MAX +}; + +struct lx2162a_qds_mdio { + enum io_slot ioslot : 4; + u8 realbusnum : 4; + struct mii_dev *realbus; +}; + +/* structure explaining the phy configuration on 8 lanes of a serdes*/ +struct serdes_phy_config { + u8 serdes; /* serdes protocol */ + struct phy_config { + u8 dpmacid; + /* -1 terminated array */ + int phy_address[WRIOP_MAX_PHY_NUM + 1]; + u8 mdio_bus; + enum io_slot ioslot; + } phy_config[SRDS_MAX_LANES]; +}; + +/* Table defining the phy configuration on 8 lanes of a serdes. + * Various assumptions have been made while defining this table. + * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII + * card is being used for dpmac 3-4. (X-M12-XFI could also have been used) + * And also that this card is connected to IO Slot 1 (could have been connected + * to any of the 8 IO slots (IO slot 1 - IO slot 8)). + * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card + * used in serdes1 protocol 19 (could have selected MDIO 2) + * To override these settings "dpmac" environment variable can be used after + * defining "dpmac_override" in hwconfig environment variable. + * This table has limited serdes protocol entries. It can be expanded as per + * requirement. + */ +/***************************************************************** + *| SERDES_1 PROTOCOL | IO_SLOT | CARD | + ****************************************************************** + *| 2 | IO_SLOT_1 | M4-PCIE-SGMII | + *| 3 | IO_SLOT_1 | M11-USXGMII | + *| 15 | IO_SLOT_1 | M13-25G | + *| 17 | IO_SLOT_1 | M13-25G | + *| 18 | IO_SLOT_1 | M11-USXGMII | + *| | IO_SLOT_6 | M13-25G | + *| 20 | IO_SLOT_1 | M7-40G | + ***************************************************************** + */ +static const struct serdes_phy_config serdes1_phy_config[] = { + {1, {} }, + {2, {{WRIOP1_DPMAC3, {SGMII_CARD_PORT1_PHY_ADDR, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC4, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC5, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC6, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_1} } }, + {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1}, + EMI1, IO_SLOT_1} } }, + {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1} } }, + {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1} } }, + {18, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1}, + EMI1, IO_SLOT_1}, + {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_6}, + {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1}, + EMI1, IO_SLOT_6} } }, + {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1}, + EMI1, IO_SLOT_1} } } +}; + +/***************************************************************** + *| SERDES_2 PROTOCOL | IO_SLOT | CARD | + ****************************************************************** + *| 2 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + *| 3 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + *| 5 | IO_SLOT_7 | M4-PCIE-SGMII | + *| 10 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + *| 11 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + *| 12 | IO_SLOT_7 | M4-PCIE-SGMII | + *| | IO_SLOT_8 | M4-PCIE-SGMII | + ****************************************************************** + */ +static const struct serdes_phy_config serdes2_phy_config[] = { + {2, {} }, + {3, {} }, + {5, {} }, + {10, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_7} } }, + {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_8}, + {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_8}, + {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_8} } }, + {12, {{WRIOP1_DPMAC11, {SGMII_CARD_PORT1_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1}, + EMI1, IO_SLOT_7}, + {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1}, + EMI1, IO_SLOT_7} } } +}; + +static inline +const struct phy_config *get_phy_config(u8 serdes, + const struct serdes_phy_config *table, + u8 table_size) +{ + int i; + + for (i = 0; i < table_size; i++) { + if (table[i].serdes == serdes) + return table[i].phy_config; + } + + return NULL; +} + +/* BRDCFG4 controls EMI routing for the board. + * Bits Function + * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V): + * EMI1 00= On-board PHY #1 + * 01= On-board PHY #2 + * 10= (reserved) + * 11= Slots 1..8 multiplexer and translator. + * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V): + * EMI1X 000= Slot #1 + * 001= Slot #2 + * 010= Slot #3 + * 011= Slot #4 + * 100= Slot #5 + * 101= Slot #6 + * 110= Slot #7 + * 111= Slot #8 + * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2): + * EMI2 000= Slot #1 (secondary EMI) + * 001= Slot #2 (secondary EMI) + * 010= Slot #3 (secondary EMI) + * 011= Slot #4 (secondary EMI) + * 100= Slot #5 (secondary EMI) + * 101= Slot #6 (secondary EMI) + * 110= Slot #7 (secondary EMI) + * 111= Slot #8 (secondary EMI) + */ +static int lx2162a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot) +{ + switch (realbusnum) { + case EMI1: + switch (ioslot) { + case EMI1_RGMII1: + return 0; + case EMI1_RGMII2: + return 0x40; + default: + return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0); + } + break; + case EMI2: + return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT); + default: + return -1; + } +} + +static void lx2162a_qds_mux_mdio(struct lx2162a_qds_mdio *priv) +{ + u8 brdcfg4, mux_val, reg; + + brdcfg4 = QIXIS_READ(brdcfg[4]); + reg = brdcfg4; + mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot); + + switch (priv->realbusnum) { + case EMI1: + brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK; + brdcfg4 |= mux_val; + break; + case EMI2: + brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK; + brdcfg4 |= mux_val; + break; + } + + if (brdcfg4 ^ reg) + QIXIS_WRITE(brdcfg[4], brdcfg4); +} + +static int lx2162a_qds_mdio_read(struct mii_dev *bus, int addr, + int devad, int regnum) +{ + struct lx2162a_qds_mdio *priv = bus->priv; + + lx2162a_qds_mux_mdio(priv); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int lx2162a_qds_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct lx2162a_qds_mdio *priv = bus->priv; + + lx2162a_qds_mux_mdio(priv); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int lx2162a_qds_mdio_reset(struct mii_dev *bus) +{ + struct lx2162a_qds_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static struct mii_dev *lx2162a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot) +{ + struct lx2162a_qds_mdio *pmdio; + struct mii_dev *bus; + /*should be within MDIO_NAME_LEN*/ + char dummy_mdio_name[] = "LX2162A_QDS_MDIO1_IOSLOT1"; + + if (realbusnum == EMI2) { + if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) { + printf("invalid ioslot %d\n", ioslot); + return NULL; + } + } else if (realbusnum == EMI1) { + if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) { + printf("invalid ioslot %d\n", ioslot); + return NULL; + } + } else { + printf("not supported real mdio bus %d\n", realbusnum); + return NULL; + } + + if (ioslot == EMI1_RGMII1) + strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII1"); + else if (ioslot == EMI1_RGMII2) + strcpy(dummy_mdio_name, "LX2162A_QDS_MDIO1_RGMII2"); + else + sprintf(dummy_mdio_name, "LX2162A_QDS_MDIO%d_IOSLOT%d", + realbusnum, ioslot); + bus = miiphy_get_dev_by_name(dummy_mdio_name); + + if (bus) + return bus; + + bus = mdio_alloc(); + if (!bus) { + printf("Failed to allocate %s bus\n", dummy_mdio_name); + return NULL; + } + + pmdio = malloc(sizeof(*pmdio)); + if (!pmdio) { + printf("Failed to allocate %s private data\n", dummy_mdio_name); + free(bus); + return NULL; + } + + switch (realbusnum) { + case EMI1: + pmdio->realbus = + miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME); + break; + case EMI2: + pmdio->realbus = + miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME); + break; + } + + if (!pmdio->realbus) { + printf("No real mdio bus num %d found\n", realbusnum); + free(bus); + free(pmdio); + return NULL; + } + + pmdio->realbusnum = realbusnum; + pmdio->ioslot = ioslot; + bus->read = lx2162a_qds_mdio_read; + bus->write = lx2162a_qds_mdio_write; + bus->reset = lx2162a_qds_mdio_reset; + strcpy(bus->name, dummy_mdio_name); + bus->priv = pmdio; + + if (!mdio_register(bus)) + return bus; + + printf("No bus with name %s\n", dummy_mdio_name); + free(bus); + free(pmdio); + return NULL; +} + +static inline void do_phy_config(const struct phy_config *phy_config) +{ + struct mii_dev *bus; + int i, phy_num, phy_address; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (!phy_config[i].dpmacid) + continue; + + for (phy_num = 0; + phy_num < ARRAY_SIZE(phy_config[i].phy_address); + phy_num++) { + phy_address = phy_config[i].phy_address[phy_num]; + if (phy_address == -1) + break; + wriop_set_phy_address(phy_config[i].dpmacid, + phy_num, phy_address); + } + /*Register the muxing front-ends to the MDIO buses*/ + bus = lx2162a_qds_mdio_init(phy_config[i].mdio_bus, + phy_config[i].ioslot); + if (!bus) + printf("could not get bus for mdio %d ioslot %d\n", + phy_config[i].mdio_bus, + phy_config[i].ioslot); + else + wriop_set_mdio(phy_config[i].dpmacid, bus); + } +} + +static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid, + char *env_dpmac) +{ + const char *ret; + size_t len; + u8 realbusnum, ioslot; + struct mii_dev *bus; + int phy_num; + char *phystr = "phy00"; + + /*search phy in dpmac arg*/ + for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) { + sprintf(phystr, "phy%d", phy_num + 1); + ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac); + if (!ret) { + /*look for phy instead of phy1*/ + if (!phy_num) + ret = hwconfig_subarg_f(arg_dpmacid, "phy", + &len, env_dpmac); + if (!ret) + continue; + } + + if (len != 4 || strncmp(ret, "0x", 2)) + printf("invalid phy format in %s variable.\n" + "specify phy%d for %s in hex format e.g. 0x12\n", + env_dpmac, phy_num + 1, arg_dpmacid); + else + wriop_set_phy_address(dpmac, phy_num, + simple_strtoul(ret, NULL, 16)); + } + + /*search mdio in dpmac arg*/ + ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac); + if (ret) + realbusnum = *ret - '0'; + else + realbusnum = EMI_NONE; + + if (realbusnum) { + /*search io in dpmac arg*/ + ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac); + if (ret) + ioslot = *ret - '0'; + else + ioslot = IO_SLOT_NONE; + /*Register the muxing front-ends to the MDIO buses*/ + bus = lx2162a_qds_mdio_init(realbusnum, ioslot); + if (!bus) + printf("could not get bus for mdio %d ioslot %d\n", + realbusnum, ioslot); + else + wriop_set_mdio(dpmac, bus); + } +} + +#endif +#endif /* !CONFIG_DM_ETH */ + +int board_eth_init(struct bd_info *bis) +{ +#ifndef CONFIG_DM_ETH +#if defined(CONFIG_FSL_MC_ENET) + struct memac_mdio_info mdio_info; + struct memac_mdio_controller *regs; + int i; + const char *ret; + char *env_dpmac; + char dpmacid[] = "dpmac00", srds[] = "00_00_00"; + size_t len; + struct mii_dev *bus; + const struct phy_config *phy_config; + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 srds_s1, srds_s2; + + srds_s1 = in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = in_le32(&gur->rcwsr[28]) & + FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + sprintf(srds, "%d_%d", srds_s1, srds_s2); + + regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; + mdio_info.regs = regs; + mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME; + + /*Register the EMI 1*/ + fm_memac_mdio_init(bis, &mdio_info); + + regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; + mdio_info.regs = regs; + mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME; + + /*Register the EMI 2*/ + fm_memac_mdio_init(bis, &mdio_info); + + /* "dpmac" environment variable can be used after + * defining "dpmac_override" in hwconfig environment variable. + */ + if (hwconfig("dpmac_override")) { + env_dpmac = env_get("dpmac"); + if (env_dpmac) { + ret = hwconfig_arg_f("srds", &len, env_dpmac); + if (ret) { + if (strncmp(ret, srds, strlen(srds))) { + printf("SERDES configuration changed.\n" + "previous: %.*s, current: %s.\n" + "update dpmac variable.\n", + (int)len, ret, srds); + } + } else { + printf("SERDES configuration not found.\n" + "Please add srds:%s in dpmac variable\n", + srds); + } + + for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) { + /* Look for dpmac1 to dpmac24(current max) arg + * in dpmac environment variable + */ + sprintf(dpmacid, "dpmac%d", i); + ret = hwconfig_arg_f(dpmacid, &len, env_dpmac); + if (ret) + do_dpmac_config(i, dpmacid, env_dpmac); + } + } else { + printf("Warning: environment dpmac not found.\n" + "DPAA network interfaces may not work\n"); + } + } else { + /*Look for phy config for serdes1 in phy config table*/ + phy_config = get_phy_config(srds_s1, serdes1_phy_config, + ARRAY_SIZE(serdes1_phy_config)); + if (!phy_config) { + printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n", + __func__, srds_s1); + } else { + do_phy_config(phy_config); + } + phy_config = get_phy_config(srds_s2, serdes2_phy_config, + ARRAY_SIZE(serdes2_phy_config)); + if (!phy_config) { + printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n", + __func__, srds_s2); + } else { + do_phy_config(phy_config); + } + } + + if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) { + wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1); + bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII1); + if (!bus) + printf("could not get bus for RGMII1\n"); + else + wriop_set_mdio(WRIOP1_DPMAC17, bus); + } + + if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) { + wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2); + bus = lx2162a_qds_mdio_init(EMI1, EMI1_RGMII2); + if (!bus) + printf("could not get bus for RGMII2\n"); + else + wriop_set_mdio(WRIOP1_DPMAC18, bus); + } + + cpu_eth_init(bis); +#endif /* CONFIG_FMAN_ENET */ +#endif /* !CONFIG_DM_ETH */ + +#ifdef CONFIG_PHY_AQUANTIA + /* + * Export functions to be used by AQ firmware + * upload application + */ + gd->jt->strcpy = strcpy; + gd->jt->mdelay = mdelay; + gd->jt->mdio_get_current_dev = mdio_get_current_dev; + gd->jt->phy_find_by_mask = phy_find_by_mask; + gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname; + gd->jt->miiphy_set_current_dev = miiphy_set_current_dev; +#endif + +#ifdef CONFIG_DM_ETH + return 0; +#else + return pci_eth_init(bis); +#endif +} + +#if defined(CONFIG_RESET_PHY_R) +void reset_phy(void) +{ +#if defined(CONFIG_FSL_MC_ENET) + mc_env_boot(); +#endif +} +#endif /* CONFIG_RESET_PHY_R */ + +#ifndef CONFIG_DM_ETH +#if defined(CONFIG_FSL_MC_ENET) +int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle) +{ + int offset; + int ret; + char dpmac_str[] = "dpmacs@00"; + const char *phy_string; + + offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs"); + + if (offset < 0) + offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs"); + + if (offset < 0) { + printf("dpmacs node not found in device tree\n"); + return offset; + } + + sprintf(dpmac_str, "dpmac@%x", dpmac_id); + debug("dpmac_str = %s\n", dpmac_str); + + offset = fdt_subnode_offset(fdt, offset, dpmac_str); + if (offset < 0) { + printf("%s node not found in device tree\n", dpmac_str); + return offset; + } + + phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL); + if (is_backplane_mode(phy_string)) { + /* Backplane KR mode: skip fixups */ + printf("Interface %d in backplane KR mode\n", dpmac_id); + return 0; + } + + ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle); + if (ret) + printf("%d@%s %d\n", __LINE__, __func__, ret); + + phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id)); + ret = fdt_setprop_string(fdt, offset, "phy-connection-type", + phy_string); + if (ret) + printf("%d@%s %d\n", __LINE__, __func__, ret); + + return ret; +} + +int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset) +{ + char mdio_ioslot_str[] = "mdio@00"; + struct lx2162a_qds_mdio *priv; + u64 reg; + u32 phandle; + int offset, mux_val; + + /*Test if the MDIO bus is real mdio bus or muxing front end ?*/ + if (strncmp(mii_dev->name, "LX2162A_QDS_MDIO", + strlen("LX2162A_QDS_MDIO"))) + return -1; + + /*Get the real MDIO bus num and ioslot info from bus's priv data*/ + priv = mii_dev->priv; + + debug("real_bus_num = %d, ioslot = %d\n", + priv->realbusnum, priv->ioslot); + + if (priv->realbusnum == EMI1) + reg = CONFIG_SYS_FSL_WRIOP1_MDIO1; + else + reg = CONFIG_SYS_FSL_WRIOP1_MDIO2; + + offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg); + if (offset < 0) { + printf("mdio@%llx node not found in device tree\n", reg); + return offset; + } + + phandle = fdt_get_phandle(fdt, offset); + phandle = cpu_to_fdt32(phandle); + offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus", + &phandle, 4); + if (offset < 0) { + printf("mdio-mux-%d node not found in device tree\n", + priv->realbusnum == EMI1 ? 1 : 2); + return offset; + } + + mux_val = lx2162a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot); + if (priv->realbusnum == EMI1) + mux_val >>= BRDCFG4_EMI1SEL_SHIFT; + else + mux_val >>= BRDCFG4_EMI2SEL_SHIFT; + sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val); + + offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str); + if (offset < 0) { + printf("%s node not found in device tree\n", mdio_ioslot_str); + return offset; + } + + return offset; +} + +int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset, + struct phy_device *phy_dev, int phandle) +{ + char phy_node_name[] = "ethernet-phy@00"; + char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,"; + int ret; + + sprintf(phy_node_name, "ethernet-phy@%x", phyaddr); + debug("phy_node_name = %s\n", phy_node_name); + + *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name); + if (*subnodeoffset <= 0) { + printf("Could not add subnode %s inside node %s err = %s\n", + phy_node_name, fdt_get_name(fdt, offset, NULL), + fdt_strerror(*subnodeoffset)); + return *subnodeoffset; + } + + sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,", + phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF); + debug("phy_id_compatible_str %s\n", phy_id_compatible_str); + + ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible", + phy_id_compatible_str); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + + if (phy_dev->is_c45) { + ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible", + "ethernet-phy-ieee802.3-c45"); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + } else { + ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible", + "ethernet-phy-ieee802.3-c22"); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + } + + ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + + ret = fdt_set_phandle(fdt, *subnodeoffset, phandle); + if (ret) { + printf("%d@%s %d\n", __LINE__, __func__, ret); + goto out; + } + +out: + if (ret) + fdt_del_node(fdt, *subnodeoffset); + + return ret; +} + +#define is_rgmii(dpmac_id) \ + wriop_get_enet_if((dpmac_id)) == PHY_INTERFACE_MODE_RGMII_ID + +int fdt_fixup_board_phy(void *fdt) +{ + int fpga_offset, offset, subnodeoffset; + struct mii_dev *mii_dev; + struct list_head *mii_devs, *entry; + int ret, dpmac_id, phandle, i; + struct phy_device *phy_dev; + char ethname[ETH_NAME_LEN]; + phy_interface_t phy_iface; + + ret = 0; + /* we know FPGA is connected to i2c0, therefore search path directly, + * instead of compatible property, as it saves time + */ + fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga"); + + if (fpga_offset < 0) + fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga"); + + if (fpga_offset < 0) { + printf("i2c@2000000/fpga node not found in device tree\n"); + return fpga_offset; + } + + phandle = fdt_alloc_phandle(fdt); + mii_devs = mdio_get_list_head(); + + list_for_each(entry, mii_devs) { + mii_dev = list_entry(entry, struct mii_dev, link); + debug("mii_dev name : %s\n", mii_dev->name); + offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset); + if (offset < 0) + continue; + + // Look for phy devices attached to MDIO bus muxing front end + // and create their entries with compatible being the device id + for (i = 0; i < PHY_MAX_ADDR; i++) { + phy_dev = mii_dev->phymap[i]; + if (!phy_dev) + continue; + + // TODO: use sscanf instead of loop + dpmac_id = WRIOP1_DPMAC1; + while (dpmac_id < NUM_WRIOP_PORTS) { + phy_iface = wriop_get_enet_if(dpmac_id); + snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s", + dpmac_id, + phy_string_for_interface(phy_iface)); + if (strcmp(ethname, phy_dev->dev->name) == 0) + break; + dpmac_id++; + } + if (dpmac_id == NUM_WRIOP_PORTS) + continue; + + if ((dpmac_id == 17 || dpmac_id == 18) && + is_rgmii(dpmac_id)) + continue; + + ret = fdt_create_phy_node(fdt, offset, i, + &subnodeoffset, + phy_dev, phandle); + if (ret) + break; + + ret = fdt_fixup_dpmac_phy_handle(fdt, + dpmac_id, phandle); + if (ret) { + fdt_del_node(fdt, subnodeoffset); + break; + } + /* calculate offset again as new node addition may have + * changed offset; + */ + offset = fdt_get_ioslot_offset(fdt, mii_dev, + fpga_offset); + phandle++; + } + + if (ret) + break; + } + + return ret; +} +#endif // CONFIG_FSL_MC_ENET +#endif + +#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT) + +/* Structure to hold SERDES protocols supported in case of + * CONFIG_DM_ETH enabled (network interfaces are described in the DTS). + * + * @serdes_block: the index of the SERDES block + * @serdes_protocol: the decimal value of the protocol supported + * @dts_needed: DTS notes describing the current configuration are needed + * + * When dts_needed is true, the board_fit_config_name_match() function + * will try to exactly match the current configuration of the block with a DTS + * name provided. + */ +static struct serdes_configuration { + u8 serdes_block; + u32 serdes_protocol; + bool dts_needed; +} supported_protocols[] = { + /* Serdes block #1 */ + {1, 2, true}, + {1, 3, true}, + {1, 15, true}, + {1, 17, true}, + {1, 18, true}, + {1, 20, true}, + + /* Serdes block #2 */ + {2, 2, false}, + {2, 3, false}, + {2, 5, false}, + {2, 10, false}, + {2, 11, true}, + {2, 12, true}, +}; + +#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols) + +static bool protocol_supported(u8 serdes_block, u32 protocol) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) + return true; + } + + return false; +} + +static void get_str_protocol(u8 serdes_block, u32 protocol, char *str) +{ + struct serdes_configuration serdes_conf; + int i; + + for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) { + serdes_conf = supported_protocols[i]; + if (serdes_conf.serdes_block == serdes_block && + serdes_conf.serdes_protocol == protocol) { + if (serdes_conf.dts_needed == true) + sprintf(str, "%u", protocol); + else + sprintf(str, "x"); + return; + } + } +} + +int board_fit_config_name_match(const char *name) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcw_status = in_le32(&gur->rcwsr[28]); + char srds_s1_str[2], srds_s2_str[2]; + u32 srds_s1, srds_s2; + char expected_dts[100]; + + srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; + srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; + + srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK; + srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT; + + /* Check for supported protocols. The default DTS will be used + * in this case + */ + if (!protocol_supported(1, srds_s1) || + !protocol_supported(2, srds_s2)) + return -1; + + get_str_protocol(1, srds_s1, srds_s1_str); + get_str_protocol(2, srds_s2, srds_s2_str); + + sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s", + srds_s1_str, srds_s2_str); + + if (!strcmp(name, expected_dts)) + return 0; + + return -1; +} +#endif diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 0ff987eeb4e..222906fdff9 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -32,12 +32,13 @@ #include "../common/vid.h" #include #include +#include "lx2160a.h" #ifdef CONFIG_EMC2305 #include "../common/emc2305.h" #endif -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value) #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f) #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value) @@ -47,7 +48,7 @@ #define SDHC1_BASE_PMUX_DSPI 2 #define SDHC2_BASE_PMUX_DSPI 2 #define IIC5_PMUX_SPI3 3 -#endif /* CONFIG_TARGET_LX2160AQDS */ +#endif /* CONFIG_TARGET_LX2160AQDS or CONFIG_TARGET_LX2162AQDS */ DECLARE_GLOBAL_DATA_PTR; @@ -191,7 +192,7 @@ int board_fix_fdt(void *fdt) } #endif -#if defined(CONFIG_TARGET_LX2160AQDS) +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) void esdhc_dspi_status_fixup(void *blob) { const char esdhc0_path[] = "/soc/esdhc@2140000"; @@ -259,7 +260,7 @@ void esdhc_dspi_status_fixup(void *blob) int esdhc_status_fixup(void *blob, const char *compat) { -#if defined(CONFIG_TARGET_LX2160AQDS) +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) /* Enable esdhc and dspi DT nodes based on RCW fields */ esdhc_dspi_status_fixup(blob); #else @@ -297,7 +298,7 @@ int checkboard(void) enum boot_src src = get_boot_src(); char buf[64]; u8 sw; -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) int clock; static const char *const freq[] = {"100", "125", "156.25", "161.13", "322.26", "", "", "", @@ -306,7 +307,7 @@ int checkboard(void) #endif cpu_name(buf); -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) printf("Board: %s-QDS, ", buf); #else printf("Board: %s-RDB, ", buf); @@ -339,7 +340,13 @@ int checkboard(void) break; } } -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160ARDB) + printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); + + puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); + puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); + puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); +#else printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver), qixis_read_tag(buf), (int)qixis_read_minor()); @@ -350,31 +357,27 @@ int checkboard(void) sw = QIXIS_READ(brdcfg[2]); clock = sw >> 4; printf("Clock1 = %sMHz ", freq[clock]); +#if defined(CONFIG_TARGET_LX2160AQDS) clock = sw & 0x0f; printf("Clock2 = %sMHz", freq[clock]); - +#endif sw = QIXIS_READ(brdcfg[3]); puts("\nSERDES2 Reference : "); clock = sw >> 4; printf("Clock1 = %sMHz ", freq[clock]); clock = sw & 0x0f; - printf("Clock2 = %sMHz", freq[clock]); - + printf("Clock2 = %sMHz\n", freq[clock]); +#if defined(CONFIG_TARGET_LX2160AQDS) sw = QIXIS_READ(brdcfg[12]); - puts("\nSERDES3 Reference : "); + puts("SERDES3 Reference : "); clock = sw >> 4; printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]); -#else - printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata)); - - puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n"); - puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); - puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n"); +#endif #endif return 0; } -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) /* * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro. */ @@ -562,7 +565,7 @@ int config_board_mux(void) unsigned long get_board_sys_clk(void) { -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) u8 sysclk_conf = QIXIS_READ(brdcfg[1]); switch (sysclk_conf & 0x03) { @@ -581,7 +584,7 @@ unsigned long get_board_sys_clk(void) unsigned long get_board_ddr_clk(void) { -#ifdef CONFIG_TARGET_LX2160AQDS +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); switch ((ddrclk_conf & 0x30) >> 4) { diff --git a/board/freescale/lx2160a/lx2160a.h b/board/freescale/lx2160a/lx2160a.h new file mode 100644 index 00000000000..52b020765dc --- /dev/null +++ b/board/freescale/lx2160a/lx2160a.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __LX2160_H +#define __LX2160_H + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +/* SYSCLK */ +#define QIXIS_SYSCLK_100 0x0 +#define QIXIS_SYSCLK_125 0x1 +#define QIXIS_SYSCLK_133 0x2 + +/* DDRCLK */ +#define QIXIS_DDRCLK_100 0x0 +#define QIXIS_DDRCLK_125 0x1 +#define QIXIS_DDRCLK_133 0x2 + +#define BRDCFG4_EMI1SEL_MASK 0xF8 +#define BRDCFG4_EMI1SEL_SHIFT 3 +#define BRDCFG4_EMI2SEL_MASK 0x07 +#define BRDCFG4_EMI2SEL_SHIFT 0 +#endif + +#define QIXIS_XMAP_SHIFT 5 + +/* RTC */ +#define I2C_MUX_CH_RTC 0xB + +/* MAC/PHY configuration */ +#if defined(CONFIG_FSL_MC_ENET) +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +#define AQ_PHY_ADDR1 0x00 +#define AQ_PHY_ADDR2 0x01 +#define AQ_PHY_ADDR3 0x02 +#define AQ_PHY_ADDR4 0x03 +#endif + +#ifdef CONFIG_TARGET_LX2160ARDB +#define AQR107_PHY_ADDR1 0x04 +#define AQR107_PHY_ADDR2 0x05 +#define AQR107_IRQ_MASK 0x0C +#endif + +#define CORTINA_PHY_ADDR1 0x0 +#define INPHI_PHY_ADDR1 0x0 + +#define RGMII_PHY_ADDR1 0x01 +#define RGMII_PHY_ADDR2 0x02 + +#if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) +#define INPHI_PHY_ADDR2 0x1 +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x1D +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x1F +#endif +#endif + +#endif /* __LX2160_H */ diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig new file mode 100644 index 00000000000..11fe33b0fa9 --- /dev/null +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -0,0 +1,98 @@ +CONFIG_ARM=y +CONFIG_TARGET_LX2162AQDS=y +CONFIG_TFABOOT=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_NXP_ESBC=y +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x500000 +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" +CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x" +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x20500000 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_E1000=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SBSA=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_GIC_V3_ITS=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_DM_RTC=y +CONFIG_DM_GPIO=y +CONFIG_CMD_DATE=y +CONFIG_RTC_PCF2127=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig new file mode 100644 index 00000000000..ca7479793d9 --- /dev/null +++ b/configs/lx2162aqds_tfa_defconfig @@ -0,0 +1,96 @@ +CONFIG_ARM=y +CONFIG_TARGET_LX2162AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x500000 +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" +CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x" +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x20500000 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_E1000=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SBSA=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_GIC_V3_ITS=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_DM_RTC=y +CONFIG_DM_GPIO=y +CONFIG_CMD_DATE=y +CONFIG_RTC_PCF2127=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig new file mode 100644 index 00000000000..1199b6c63dd --- /dev/null +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -0,0 +1,103 @@ +CONFIG_ARM=y +CONFIG_TARGET_LX2162AQDS=y +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x500000 +CONFIG_FSPI_AHB_EN_4BYTE=y +CONFIG_TFABOOT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y +CONFIG_AHCI=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_RSA=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_BOOTDELAY=10 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200 root=/dev/ram0 earlycon=pl011,mmio32,0x21c0000 ramdisk_size=0x2000000 default_hugepagesz=1024m hugepagesz=1024m hugepages=2 pci=pcie_bus_perf" +# CONFIG_USE_BOOTCOMMAND is not set +CONFIG_MISC_INIT_R=y +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_EEPROM=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_WDT=y +CONFIG_CMD_CACHE=y +CONFIG_MP=y +CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-lx2162a-qds" +CONFIG_OF_LIST="fsl-lx2162a-qds-17-x fsl-lx2162a-qds-18-x fsl-lx2162a-qds-20-x" +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_ADDR=0x20500000 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SATA_CEVA=y +CONFIG_FSL_CAAM=y +CONFIG_DM_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_CORTINA=y +CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_DM_MDIO=y +CONFIG_DM_MDIO_MUX=y +CONFIG_E1000=y +CONFIG_MDIO_MUX_I2CREG=y +CONFIG_FSL_LS_MDIO=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_LAYERSCAPE_RC=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_FSL_DSPI=y +CONFIG_NXP_FSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_WDT=y +CONFIG_WDT_SBSA=y +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y +CONFIG_GIC_V3_ITS=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_DEFAULT_BUS_NUMBER=0 +CONFIG_DM_RTC=y +CONFIG_DM_GPIO=y +CONFIG_CMD_DATE=y +CONFIG_RTC_PCF2127=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_CMD_OPTEE_RPMB=y +CONFIG_OPTEE_TA_AVB=y +CONFIG_SUPPORT_EMMC_RPMB=y diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 0017ac57734..837760fe46a 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -149,8 +149,10 @@ /* USB */ #ifdef CONFIG_USB #define CONFIG_HAS_FSL_XHCI_USB +#ifndef CONFIG_TARGET_LX2162AQDS #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #endif +#endif /* FlexSPI */ #ifdef CONFIG_NXP_FSPI diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h index 12884bcf2be..ea1b1635fe9 100644 --- a/include/configs/lx2160aqds.h +++ b/include/configs/lx2160aqds.h @@ -8,70 +8,14 @@ #include "lx2160a_common.h" -/* Qixis */ -#define QIXIS_XMAP_MASK 0x07 -#define QIXIS_XMAP_SHIFT 5 -#define QIXIS_RST_CTL_RESET_EN 0x30 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x20 -#define QIXIS_LBMAP_QSPI 0x00 -#define QIXIS_RCW_SRC_QSPI 0xff -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SD -#define QIXIS_LBMAP_EMMC -#define QIXIS_RCW_SRC_SD 0x08 -#define QIXIS_RCW_SRC_EMMC 0x09 -#define NON_EXTENDED_DUTCFG -#define QIXIS_SDID_MASK 0x07 -#define QIXIS_ESDHC_NO_ADAPTER 0x7 - -/* SYSCLK */ -#define QIXIS_SYSCLK_100 0x0 -#define QIXIS_SYSCLK_125 0x1 -#define QIXIS_SYSCLK_133 0x2 - -/* DDRCLK */ -#define QIXIS_DDRCLK_100 0x0 -#define QIXIS_DDRCLK_125 0x1 -#define QIXIS_DDRCLK_133 0x2 - -#define BRDCFG4_EMI1SEL_MASK 0xF8 -#define BRDCFG4_EMI1SEL_SHIFT 3 -#define BRDCFG4_EMI2SEL_MASK 0x07 -#define BRDCFG4_EMI2SEL_SHIFT 0 - /* VID */ - -#define I2C_MUX_CH_VOL_MONITOR 0xA -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x63 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 #define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv" #define CONFIG_VID - -/* The lowest and highest voltage allowed*/ -#define VDD_MV_MIN 775 -#define VDD_MV_MAX 925 - -/* PM Bus commands code for LTC3882*/ -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 -#define PMBUS_CMD_VOUT_COMMAND 0x21 -#define PWM_CHANNEL0 0x0 - #define CONFIG_VOL_MONITOR_LTC3882_SET #define CONFIG_VOL_MONITOR_LTC3882_READ /* RTC */ #define CONFIG_SYS_RTC_BUS_NUM 0 -#define I2C_MUX_CH_RTC 0xB /* * MMC @@ -87,25 +31,6 @@ u8 qixis_esdhc_detect_quirk(void); #if defined(CONFIG_FSL_MC_ENET) #define CONFIG_MII #define CONFIG_ETHPRIME "DPMAC17@rgmii-id" - -#define AQ_PHY_ADDR1 0x00 -#define AQ_PHY_ADDR2 0x01 -#define AQ_PHY_ADDR3 0x02 -#define AQ_PHY_ADDR4 0x03 - -#define CORTINA_PHY_ADDR1 0x0 - -#define INPHI_PHY_ADDR1 0x0 -#define INPHI_PHY_ADDR2 0x1 - -#define RGMII_PHY_ADDR1 0x01 -#define RGMII_PHY_ADDR2 0x02 - -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F - #endif /* EEPROM */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 59c2305a34d..097f1224c90 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -8,47 +8,9 @@ #include "lx2160a_common.h" -/* Qixis */ -#define QIXIS_XMAP_MASK 0x07 -#define QIXIS_XMAP_SHIFT 5 -#define QIXIS_RST_CTL_RESET_EN 0x30 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x20 -#define QIXIS_LBMAP_QSPI 0x00 -#define QIXIS_RCW_SRC_QSPI 0xff -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SD -#define QIXIS_LBMAP_EMMC -#define QIXIS_RCW_SRC_SD 0x08 -#define QIXIS_RCW_SRC_EMMC 0x09 -#define NON_EXTENDED_DUTCFG - /* VID */ - -#define I2C_MUX_CH_VOL_MONITOR 0xA -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x63 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 #define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv" #define CONFIG_VID - -/* The lowest and highest voltage allowed*/ -#define VDD_MV_MIN 775 -#define VDD_MV_MAX 855 - -/* PM Bus commands code for LTC3882*/ -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 -#define PMBUS_CMD_VOUT_COMMAND 0x21 -#define PWM_CHANNEL0 0x0 - #define CONFIG_VOL_MONITOR_LTC3882_SET #define CONFIG_VOL_MONITOR_LTC3882_READ @@ -59,17 +21,6 @@ #if defined(CONFIG_FSL_MC_ENET) #define CONFIG_MII #define CONFIG_ETHPRIME "DPMAC1@xgmii" - -#define AQR107_PHY_ADDR1 0x04 -#define AQR107_PHY_ADDR2 0x05 -#define AQR107_IRQ_MASK 0x0C - -#define CORTINA_PHY_ADDR1 0x0 -#define INPHI_PHY_ADDR1 0x0 - -#define RGMII_PHY_ADDR1 0x01 -#define RGMII_PHY_ADDR2 0x02 - #endif /* EMC2305 */ diff --git a/include/configs/lx2162aqds.h b/include/configs/lx2162aqds.h new file mode 100644 index 00000000000..847534c5505 --- /dev/null +++ b/include/configs/lx2162aqds.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2020 NXP + */ + +#ifndef __LX2162_QDS_H +#define __LX2162_QDS_H + +#include "lx2160a_common.h" + +/* USB */ +#undef CONFIG_USB_MAX_CONTROLLER_COUNT +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +/* Voltage monitor on channel 2*/ +#define CONFIG_VID_FLS_ENV "lx2162aqds_vdd_mv" +#define CONFIG_VID +#define CONFIG_VOL_MONITOR_LTC3882_SET +#define CONFIG_VOL_MONITOR_LTC3882_READ + +/* RTC */ +#define CONFIG_SYS_RTC_BUS_NUM 0 + +/* + * MMC + */ +#ifdef CONFIG_MMC +#ifndef __ASSEMBLY__ +u8 qixis_esdhc_detect_quirk(void); +#endif +#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() +#endif + +/* MAC/PHY configuration */ +#if defined(CONFIG_FSL_MC_ENET) +#define CONFIG_MII +#define CONFIG_ETHPRIME "DPMAC17@rgmii-id" +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXTRA_ENV_SETTINGS \ + "boot_scripts=lx2162aqds_boot.scr\0" \ + "boot_script_hdr=hdr_lx2162aqds_bs.out\0" \ + "BOARD=lx2162aqds\0" \ + "xspi_bootcmd=echo Trying load from flexspi..;" \ + "sf probe 0:0 && sf read $load_addr " \ + "$kernel_start $kernel_size ; env exists secureboot &&" \ + "sf read $kernelheader_addr_r $kernelheader_start " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ + " bootm $load_addr#$BOARD\0" \ + "sd_bootcmd=echo Trying load from sd card..;" \ + "mmc dev 0; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" \ + "emmc_bootcmd=echo Trying load from emmc card..;" \ + "mmc dev 1; mmcinfo; mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd ;" \ + "env exists secureboot && mmc read $kernelheader_addr_r "\ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$BOARD\0" + +#include + +#endif /* __LX2162_QDS_H */ -- cgit v1.3.1 From fc9a3d1b295cb15da06788fbb2f32d06b3888c57 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Mon, 26 Oct 2020 16:52:36 +0800 Subject: include/configs: ls1012aqds: add default environment variable This adds default environment variable for ls1012aqds Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- include/configs/ls1012aqds.h | 62 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) (limited to 'include') diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index df2a613eaf3..c4c9b7f5019 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -102,5 +102,67 @@ #define CONFIG_PCI_SCAN_SHOW +#undef CONFIG_EXTRA_ENV_SETTINGS +#define CONFIG_EXTRA_ENV_SETTINGS \ + "verify=no\0" \ + "fdt_addr=0x00f00000\0" \ + "kernel_addr=0x01000000\0" \ + "kernelheader_addr=0x600000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x96000000\0" \ + "fdt_addr_r=0x90000000\0" \ + "load_addr=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "kernelheader_size=0x40000\0" \ + "console=ttyS0,115200\0" \ + BOOTENV \ + "boot_scripts=ls1012aqds_boot.scr\0" \ + "boot_script_hdr=hdr_ls1012aqds_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "done;" \ + "\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ + "env exists secureboot " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=pfe stop; echo Trying load from qspi..;" \ + "sf probe 0:0 && sf read $load_addr " \ + "$kernel_addr $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" + +#undef CONFIG_BOOTCOMMAND +#ifdef CONFIG_TFABOOT +#undef QSPI_NOR_BOOTCOMMAND +#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#else +#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ + "env exists secureboot && esbc_halt;" +#endif + #include #endif /* __LS1012AQDS_H__ */ -- cgit v1.3.1 From 507103f8a93b51ece694a7662409408380bc828f Mon Sep 17 00:00:00 2001 From: Manish Tomar Date: Thu, 5 Nov 2020 14:08:55 +0530 Subject: ls1043a: Fix address for secure boot headers Update kernelheader_addr and kernelheader_addr variables with correct values for ls1043a. Signed-off-by: Manish Tomar Reviewed-by: Priyanka Jain --- include/configs/ls1043a_common.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 96fdd6417ed..6584e391993 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -247,12 +247,12 @@ "kernelheader_start=0x800000\0" \ "fdt_addr_r=0x90000000\0" \ "load_addr=0xa0000000\0" \ - "kernelheader_addr=0x60800000\0" \ + "kernelheader_addr=0x60600000\0" \ "kernel_size=0x2800000\0" \ "kernelheader_size=0x40000\0" \ "kernel_addr_sd=0x8000\0" \ "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_addr_sd=0x3000\0" \ "kernelhdr_size_sd=0x10\0" \ "console=ttyS0,115200\0" \ "boot_os=y\0" \ -- cgit v1.3.1 From 4ed00656a99aa3df82397e98c4a7b04d360f2e6b Mon Sep 17 00:00:00 2001 From: Manish Tomar Date: Thu, 5 Nov 2020 14:08:56 +0530 Subject: lx2160a: Fix address for secure boot headers Update kernel_size_sd variable with correct value for lx2160a. Signed-off-by: Manish Tomar Reviewed-by: Priyanka Jain --- include/configs/lx2160a_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 837760fe46a..4bd0ddbdad2 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -232,7 +232,7 @@ unsigned long get_board_ddr_clk(void); "kernel_size=0x2800000\0" \ "kernel_addr_sd=0x8000\0" \ "kernelhdr_addr_sd=0x3000\0" \ - "kernel_size_sd=0x1d000\0" \ + "kernel_size_sd=0x14000\0" \ "kernelhdr_size_sd=0x20\0" \ "console=ttyAMA0,38400n8\0" \ BOOTENV \ -- cgit v1.3.1 From bb1828f34537962cabe2f2e49f1e92d5cfee24aa Mon Sep 17 00:00:00 2001 From: Aleksandar Gerasimovski Date: Thu, 26 Nov 2020 10:45:16 +0000 Subject: drivers: ifc: add define for IFC_CSPRn TE bit To drive TE pin high is supported IFC configuration that can be used on some designs. Signed-off-by: Aleksandar Gerasimovski Reviewed-by: Priyanka Jain --- include/fsl_ifc.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index fd915335b2c..e1e6214b0f7 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -52,6 +52,8 @@ /* Machine Select */ #define CSPR_MSEL 0x00000006 #define CSPR_MSEL_SHIFT 1 +/* External Transceiver Enable */ +#define CSPR_TE 0x00000010 /* NOR */ #define CSPR_MSEL_NOR 0x00000000 /* NAND */ -- cgit v1.3.1 From b620363feb50ad9ec0623581567beb317e0d52d7 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 1 Dec 2020 17:30:26 +0100 Subject: riscv: qemu: enable distro boot from scsi Booting via distro boot fails for: qemu-system-riscv64 -drive if=none,file=sct-riscv64.img,format=raw,id=mydisk \ -device ich9-ahci,id=ahci -device ide-hd,drive=mydisk,bus=ahci.0 Enable distro booting from an attached SCSI disk. Signed-off-by: Heinrich Schuchardt Reviewed-by: Bin Meng --- include/configs/qemu-riscv.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index aed9a4ae990..a2f33587c24 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -35,6 +35,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(QEMU, qemu, na) \ func(VIRTIO, virtio, 0) \ + func(SCSI, scsi, 0) \ func(DHCP, dhcp, na) #include -- cgit v1.3.1 From c9cb6a6002fc91b045ac84b6d8fe0b34213dd320 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Thu, 29 Oct 2020 12:59:19 +0200 Subject: distro_bootcmd: set devtype for dhcp boot Set $devtype for DHCP boot, which can be handy for the boot.scr for detection of devtype used (for example, when the same boot.scr is used for both mmc/dhcp boot): if test ${devtype} = "dhcp"; then ... fi Signed-off-by: Igor Opaniuk Reviewed-by: Oleksandr Suvorov --- include/config_distro_bootcmd.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 82a3a365c5b..c9862260a38 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -369,6 +369,7 @@ #endif #define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \ "bootcmd_dhcp=" \ + "setenv devtype " #devtypel "; " \ BOOTENV_RUN_NET_USB_START \ BOOTENV_RUN_PCI_ENUM \ "if dhcp ${scriptaddr} ${boot_script_dhcp}; then " \ -- cgit v1.3.1 From 1b6314be50df11d9c07ba3c13618bac9df838d07 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 9 Nov 2020 07:12:25 -0700 Subject: x86: coral: Update the boot script Make use of the new bootargs substitution mechanism and zboot command syntax. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/configs/chromebook_coral.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/chromebook_coral.h b/include/configs/chromebook_coral.h index d4d32758e99..6e8e8ec1709 100644 --- a/include/configs/chromebook_coral.h +++ b/include/configs/chromebook_coral.h @@ -15,10 +15,13 @@ "read mmc 2:2 100000 0 80; setexpr loader *001004f0; " \ "setexpr size *00100518; setexpr blocks $size / 200; " \ "read mmc 2:2 100000 80 $blocks; setexpr setup $loader - 1000; " \ - "setexpr cmdline $loader - 2000; " \ - "part uuid mmc 2:2 uuid; setenv bootargs_U $uuid; " \ - "zboot start 100000 0 0 0 $setup $cmdline; " \ - "zboot load; zboot setup; zboot dump; zboot go" + "setexpr cmdline_ptr $loader - 2000; " \ + "setexpr.s cmdline *$cmdline_ptr; " \ + "setexpr cmdline gsub %U \\\\${uuid}; " \ + "if part uuid mmc 2:2 uuid; then " \ + "zboot start 100000 0 0 0 $setup cmdline; " \ + "zboot load; zboot setup; zboot dump; zboot go;" \ + "fi" #include #include -- cgit v1.3.1 From 538fe2f4eccb444ffab9305f45ec286c8e4e46ee Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2020 13:56:49 +0530 Subject: cm_fx6: Switch to full DM-aware Enable DM_SPI/DM_SPI_FLASH with a related config option. Build fine, but not tested. Cc: Nikita Kiryanov Signed-off-by: Jagan Teki --- configs/cm_fx6_defconfig | 3 +++ include/configs/cm_fx6.h | 7 ------- 2 files changed, 3 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 654a4fcc48e..86e4135b117 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -54,10 +54,12 @@ CONFIG_CMD_MTDPARTS=y CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:768k(uboot),256k(uboot-environment),-(reserved)" CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y # CONFIG_DWC_AHSATA_AHCI is not set @@ -85,6 +87,7 @@ CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y +CONFIG_SPECIFY_CONSOLE_INDEX=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 72eb19b581c..9892fb88170 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -150,13 +150,6 @@ /* APBH DMA is required for NAND support */ #endif -/* SPI Flash Configs */ -#if defined(CONFIG_SPL_BUILD) -#undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH -#undef CONFIG_SPI_FLASH_MTD -#endif - /* Ethernet */ #define CONFIG_FEC_MXC #define CONFIG_FEC_MXC_PHYADDR 0 -- cgit v1.3.1 From 03a673cf49e8d2b1a3314f0f51390198e27b6d71 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Fri, 23 Oct 2020 14:02:48 +0530 Subject: dh_imx6: Switch to full DM-aware Enable DM_SPI/DM_SPI_FLASH with a related config option. Build fine, but not tested. Cc: Ludwig Zenz Cc: Andreas Geisreiter Signed-off-by: Jagan Teki --- configs/dh_imx6_defconfig | 3 +++ include/configs/dh_imx6.h | 6 ------ 2 files changed, 3 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 0d1f0cfeac1..fbb8a3a0a5b 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -51,12 +51,14 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="imx6q-dhcom-pdk2 imx6dl-dhcom-pdk2" CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SPL_DM=y CONFIG_BOUNCE_BUFFER=y CONFIG_DWC_AHSATA=y CONFIG_BOOTCOUNT_LIMIT=y @@ -103,4 +105,5 @@ CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_IMX_WATCHDOG=y +# CONFIG_SPL_WDT is not set CONFIG_BZIP2=y diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 008a70a7c2e..4a469af5e60 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -52,12 +52,6 @@ /* SATA Configs */ #define CONFIG_LBA48 -/* SPI Flash Configs */ -#if defined(CONFIG_SPL_BUILD) -#undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH -#endif - /* UART */ #define CONFIG_MXC_UART_BASE UART1_BASE -- cgit v1.3.1 From 40fc33fae0bf72ddad8a0ed48130180acb74ffb2 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Fri, 7 Aug 2020 13:13:34 -0400 Subject: spi: Fix typo in header Spelling. Signed-off-by: Sean Anderson Reviewed-by: Jagan Teki --- include/spi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/spi.h b/include/spi.h index ef8c1f6692e..2d34e4af118 100644 --- a/include/spi.h +++ b/include/spi.h @@ -51,7 +51,7 @@ struct dm_spi_bus { * struct from a spi_slave, use dev_get_parent_platdata(dev) or * dev_get_parent_platdata(slave->dev). * - * This data is immuatable. Each time the device is probed, @max_hz and @mode + * This data is immutable. Each time the device is probed, @max_hz and @mode * will be copied to struct spi_slave. * * @cs: Chip select number (0..n-1) -- cgit v1.3.1 From 265ce19485ab8aae9964307e80e0c52f8105c589 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 20 Dec 2020 11:05:38 +0100 Subject: efi_loader: make variable store size customizable Currently the size of the buffer to keep UEFI variables in memory is fixed at 16384 bytes. This size has proven to be too small for some use cases. Make the size of the memory buffer for UEFI variables customizable. Reported-by: Paulo Alcantara (SUSE) Signed-off-by: Heinrich Schuchardt Acked-by: Ilias Apalodimas --- include/efi_variable.h | 2 +- lib/efi_loader/Kconfig | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/efi_variable.h b/include/efi_variable.h index 4704a3c16e6..bf5076233e4 100644 --- a/include/efi_variable.h +++ b/include/efi_variable.h @@ -91,7 +91,7 @@ efi_status_t efi_query_variable_info_int(u32 attributes, #define EFI_VAR_FILE_NAME "ubootefi.var" -#define EFI_VAR_BUF_SIZE 0x4000 +#define EFI_VAR_BUF_SIZE CONFIG_EFI_VAR_BUF_SIZE /* * This constant identifies the file format for storing UEFI variables in diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig index 7fd3a3c90c5..dd8b93bd3c5 100644 --- a/lib/efi_loader/Kconfig +++ b/lib/efi_loader/Kconfig @@ -77,6 +77,20 @@ config EFI_VAR_SEED_FILE endif +config EFI_VAR_BUF_SIZE + int "Memory size of the UEFI variable store" + default 16384 + range 4096 2147483647 + help + This defines the size in bytes of the memory area reserved for keeping + UEFI variables. + + When using StandAloneMM (CONFIG_EFI_MM_COMM_TEE=y) this value should + match the value of PcdFlashNvStorageVariableSize used to compile the + StandAloneMM module. + + Minimum 4096, default 16384. + config EFI_GET_TIME bool "GetTime() runtime service" depends on DM_RTC -- cgit v1.3.1 From e668bec96a5f8d9f6c1619038e8147816f040192 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 20 Dec 2020 22:35:13 +0100 Subject: board: kontron: sl28: reorder mmc devices Since linux commit 2e6cde96873253fd9eb0f20afd8ffd18278cff75 ("arm64: dts: ls1028a: make the eMMC and SD card controllers use fixed indices") mmc0 is the eMMC and mmc1 is the SD card. Also swap it in u-boot to avoid any confusion by the user and to be aligned with linux. Signed-off-by: Michael Walle --- arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 4 ++-- include/configs/kontron_sl28.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index 2375549c6ed..e63684c334b 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -4,8 +4,8 @@ / { aliases { - mmc0 = &esdhc0; - mmc1 = &esdhc1; + mmc0 = &esdhc1; + mmc1 = &esdhc0; i2c0 = &i2c0; i2c1 = &i2c3; i2c2 = &i2c4; diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index afe512a8c7b..442fb58b979 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -89,8 +89,8 @@ "ramdisk_addr_r=0x88080000\0" #define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ func(NVME, nvme, 0) \ func(USB, usb, 0) \ func(DHCP, dhcp, 0) \ -- cgit v1.3.1 From 6ef1b7508740dfce9b30f172839b385361e8bd50 Mon Sep 17 00:00:00 2001 From: Sughosh Ganu Date: Mon, 14 Dec 2020 11:52:44 +0530 Subject: fsp: Move and rename fsp_types.h file The fsp_types.h header file contains macros for building signatures of different widths. These signature macros are architecture agnostic, and can be used in all places which use signatures in a data structure. Move and rename the fsp_types.h under the common include header. Signed-off-by: Sughosh Ganu Reviewed-by: Simon Glass Reviewed-by: Bin Meng --- arch/x86/include/asm/fsp/fsp_support.h | 3 +- arch/x86/include/asm/fsp/fsp_types.h | 62 ---------------------------------- include/signatures.h | 62 ++++++++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 63 deletions(-) delete mode 100644 arch/x86/include/asm/fsp/fsp_types.h create mode 100644 include/signatures.h (limited to 'include') diff --git a/arch/x86/include/asm/fsp/fsp_support.h b/arch/x86/include/asm/fsp/fsp_support.h index 29e511415cd..3cd3e4fcf5b 100644 --- a/arch/x86/include/asm/fsp/fsp_support.h +++ b/arch/x86/include/asm/fsp/fsp_support.h @@ -7,11 +7,12 @@ #ifndef __FSP_SUPPORT_H__ #define __FSP_SUPPORT_H__ +#include + #include #include #include #include -#include #include #include diff --git a/arch/x86/include/asm/fsp/fsp_types.h b/arch/x86/include/asm/fsp/fsp_types.h deleted file mode 100644 index 3d5b17ecf11..00000000000 --- a/arch/x86/include/asm/fsp/fsp_types.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: Intel */ -/* - * Copyright (C) 2013, Intel Corporation - * Copyright (C) 2014, Bin Meng - */ - -#ifndef __FSP_TYPES_H__ -#define __FSP_TYPES_H__ - -/** - * Returns a 16-bit signature built from 2 ASCII characters. - * - * This macro returns a 16-bit value built from the two ASCII characters - * specified by A and B. - * - * @A: The first ASCII character. - * @B: The second ASCII character. - * - * @return: A 16-bit value built from the two ASCII characters specified by - * A and B. - */ -#define SIGNATURE_16(A, B) ((A) | (B << 8)) - -/** - * Returns a 32-bit signature built from 4 ASCII characters. - * - * This macro returns a 32-bit value built from the four ASCII characters - * specified by A, B, C, and D. - * - * @A: The first ASCII character. - * @B: The second ASCII character. - * @C: The third ASCII character. - * @D: The fourth ASCII character. - * - * @return: A 32-bit value built from the two ASCII characters specified by - * A, B, C and D. - */ -#define SIGNATURE_32(A, B, C, D) \ - (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16)) - -/** - * Returns a 64-bit signature built from 8 ASCII characters. - * - * This macro returns a 64-bit value built from the eight ASCII characters - * specified by A, B, C, D, E, F, G,and H. - * - * @A: The first ASCII character. - * @B: The second ASCII character. - * @C: The third ASCII character. - * @D: The fourth ASCII character. - * @E: The fifth ASCII character. - * @F: The sixth ASCII character. - * @G: The seventh ASCII character. - * @H: The eighth ASCII character. - * - * @return: A 64-bit value built from the two ASCII characters specified by - * A, B, C, D, E, F, G and H. - */ -#define SIGNATURE_64(A, B, C, D, E, F, G, H) \ - (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32)) - -#endif diff --git a/include/signatures.h b/include/signatures.h new file mode 100644 index 00000000000..4042db1e00b --- /dev/null +++ b/include/signatures.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: Intel */ +/* + * Copyright (C) 2013, Intel Corporation + * Copyright (C) 2014, Bin Meng + */ + +#ifndef __SIGNATURES_H__ +#define __SIGNATURES_H__ + +/** + * Returns a 16-bit signature built from 2 ASCII characters. + * + * This macro returns a 16-bit value built from the two ASCII characters + * specified by A and B. + * + * @A: The first ASCII character. + * @B: The second ASCII character. + * + * @return: A 16-bit value built from the two ASCII characters specified by + * A and B. + */ +#define SIGNATURE_16(A, B) ((A) | (B << 8)) + +/** + * Returns a 32-bit signature built from 4 ASCII characters. + * + * This macro returns a 32-bit value built from the four ASCII characters + * specified by A, B, C, and D. + * + * @A: The first ASCII character. + * @B: The second ASCII character. + * @C: The third ASCII character. + * @D: The fourth ASCII character. + * + * @return: A 32-bit value built from the two ASCII characters specified by + * A, B, C and D. + */ +#define SIGNATURE_32(A, B, C, D) \ + (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16)) + +/** + * Returns a 64-bit signature built from 8 ASCII characters. + * + * This macro returns a 64-bit value built from the eight ASCII characters + * specified by A, B, C, D, E, F, G,and H. + * + * @A: The first ASCII character. + * @B: The second ASCII character. + * @C: The third ASCII character. + * @D: The fourth ASCII character. + * @E: The fifth ASCII character. + * @F: The sixth ASCII character. + * @G: The seventh ASCII character. + * @H: The eighth ASCII character. + * + * @return: A 64-bit value built from the two ASCII characters specified by + * A, B, C, D, E, F, G and H. + */ +#define SIGNATURE_64(A, B, C, D, E, F, G, H) \ + (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32)) + +#endif /* __SIGNATURES_H__ */ -- cgit v1.3.1 From d72cecec7fc0b04d6d52df44ae1e7033ee7e4099 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Fri, 4 Dec 2020 17:27:45 -0600 Subject: imx: imx8mm: Update clock bindings header Import clock bindings header file from Linux 5.10-rc6 Signed-off-by: Adam Ford Acked-by: Peng Fan --- include/dt-bindings/clock/imx8mm-clock.h | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h index 07e6c686f3e..e63a5530aed 100644 --- a/include/dt-bindings/clock/imx8mm-clock.h +++ b/include/dt-bindings/clock/imx8mm-clock.h @@ -248,6 +248,32 @@ #define IMX8MM_CLK_SNVS_ROOT 228 #define IMX8MM_CLK_GIC 229 -#define IMX8MM_CLK_END 230 +#define IMX8MM_SYS_PLL1_40M_CG 230 +#define IMX8MM_SYS_PLL1_80M_CG 231 +#define IMX8MM_SYS_PLL1_100M_CG 232 +#define IMX8MM_SYS_PLL1_133M_CG 233 +#define IMX8MM_SYS_PLL1_160M_CG 234 +#define IMX8MM_SYS_PLL1_200M_CG 235 +#define IMX8MM_SYS_PLL1_266M_CG 236 +#define IMX8MM_SYS_PLL1_400M_CG 237 +#define IMX8MM_SYS_PLL2_50M_CG 238 +#define IMX8MM_SYS_PLL2_100M_CG 239 +#define IMX8MM_SYS_PLL2_125M_CG 240 +#define IMX8MM_SYS_PLL2_166M_CG 241 +#define IMX8MM_SYS_PLL2_200M_CG 242 +#define IMX8MM_SYS_PLL2_250M_CG 243 +#define IMX8MM_SYS_PLL2_333M_CG 244 +#define IMX8MM_SYS_PLL2_500M_CG 245 + +#define IMX8MM_CLK_M4_CORE 246 +#define IMX8MM_CLK_VPU_CORE 247 +#define IMX8MM_CLK_GPU3D_CORE 248 +#define IMX8MM_CLK_GPU2D_CORE 249 + +#define IMX8MM_CLK_CLKO2 250 + +#define IMX8MM_CLK_A53_CORE 251 + +#define IMX8MM_CLK_END 252 #endif -- cgit v1.3.1 From db43c0b72d1eb0dcf2778413743fcf355b5632a1 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 15 Dec 2020 00:41:53 +0100 Subject: compiler.h: add host_build() Add a host_build() function, so that it's possible to check for software being build with USE_HOSTCC without relying on preprocessor conditions. In other words #ifdef USE_HOSTCC host_only_code(); #endif can be written like this instead: if (host_build()) host_only_code(); This improves code readability and test coverage and compiler will eleminate this unreachable code. Signed-off-by: Sebastian Reichel Reviewed-by: Simon Glass --- include/compiler.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/compiler.h b/include/compiler.h index 90b7afae537..27b9843497a 100644 --- a/include/compiler.h +++ b/include/compiler.h @@ -6,6 +6,7 @@ #define __COMPILER_H__ #include +#include #ifdef USE_HOSTCC @@ -150,4 +151,12 @@ typedef unsigned long int uintptr_t; #define MEM_SUPPORT_64BIT_DATA 0 #endif +static inline bool host_build(void) { +#ifdef USE_HOSTCC + return true; +#else + return false; +#endif +} + #endif -- cgit v1.3.1 From c44d374bef118a07b44a5a5f596569891cfc6d21 Mon Sep 17 00:00:00 2001 From: Sebastian Reichel Date: Tue, 15 Dec 2020 00:41:56 +0100 Subject: board: ge: bx50v3: remove confidx magic numbers Instead of hardcoding index magic numbers in the board code, also rely on board_fit_config_name_match choosing the right config for the fitImage containing the kernel. Signed-off-by: Sebastian Reichel --- board/ge/bx50v3/bx50v3.c | 16 ++++++++++------ include/configs/ge_bx50v3.h | 4 ++-- 2 files changed, 12 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index 4754647fb4a..a3ae037a82e 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -356,15 +356,12 @@ static void process_vpd(struct vpd_cache *vpd) switch (vpd->product_id) { case VPD_PRODUCT_B450: - env_set("confidx", "1"); i210_index = 1; break; case VPD_PRODUCT_B650: - env_set("confidx", "2"); i210_index = 1; break; case VPD_PRODUCT_B850: - env_set("confidx", "3"); i210_index = 2; break; } @@ -554,16 +551,23 @@ int ft_board_setup(void *blob, struct bd_info *bd) int board_fit_config_name_match(const char *name) { + const char *machine = name; + if (!vpd.is_read) return strcmp(name, "imx6q-bx50v3"); + if (!strncmp(machine, "Boot ", 5)) + machine += 5; + if (!strncmp(machine, "imx6q-", 6)) + machine += 6; + switch (vpd.product_id) { case VPD_PRODUCT_B450: - return strcmp(name, "imx6q-b450v3"); + return strcasecmp(machine, "b450v3"); case VPD_PRODUCT_B650: - return strcmp(name, "imx6q-b650v3"); + return strcasecmp(machine, "b650v3"); case VPD_PRODUCT_B850: - return strcmp(name, "imx6q-b850v3"); + return strcasecmp(machine, "b850v3"); default: return -1; } diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index e5c580b3f91..2d854af9a06 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -62,7 +62,7 @@ "networkboot=" \ "run setnetworkboot; " \ "nfs ${loadaddr} /srv/nfs/fitImage; " \ - "bootm ${loadaddr}#conf@${confidx}\0" \ + "bootm ${loadaddr}\0" \ #define CONFIG_NETWORKBOOTCOMMAND \ "run networkboot; " \ @@ -111,7 +111,7 @@ "doboot=" \ "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ "run setargs; " \ - "bootm ${loadaddr}#conf@${confidx}\0" \ + "bootm ${loadaddr}\0" \ "tryboot=" \ "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ "run loadimage || run swappartitions && run loadimage || " \ -- cgit v1.3.1 From aeaf0e6d58093102aa35921c7bc6fcb0580504bd Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 28 Dec 2020 22:42:51 +0100 Subject: efi_loader: describe struct efi_loaded_image_obj Add the missing description of some fields of struct efi_loaded_image_obj. Signed-off-by: Heinrich Schuchardt --- include/efi_loader.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index 3c68b85b68e..dc3c6ac3049 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -297,8 +297,10 @@ enum efi_image_auth_status { * @exit_status: exit status passed to Exit() * @exit_data_size: exit data size passed to Exit() * @exit_data: exit data passed to Exit() - * @exit_jmp: long jump buffer for returning form started image + * @exit_jmp: long jump buffer for returning from started image * @entry: entry address of the relocated image + * @image_type: indicates if the image is an applicition or a driver + * @auth_status: indicates if the image is authenticated */ struct efi_loaded_image_obj { struct efi_object header; -- cgit v1.3.1 From be48b0f453a3903e924a4f1790f134b9b36e5fa8 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Mon, 28 Dec 2020 23:24:40 +0100 Subject: efi_loader: use after free in efi_exit() Do not use data from the loaded image object after deleting it. Fixes: 126a43f15b36 ("efi_loader: unload applications upon Exit()") Signed-off-by: Heinrich Schuchardt --- include/efi_loader.h | 4 ++-- lib/efi_loader/efi_boottime.c | 17 ++++++++++++----- 2 files changed, 14 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index dc3c6ac3049..0fc2255f3f0 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -304,10 +304,10 @@ enum efi_image_auth_status { */ struct efi_loaded_image_obj { struct efi_object header; - efi_status_t exit_status; + efi_status_t *exit_status; efi_uintn_t *exit_data_size; u16 **exit_data; - struct jmp_buf_data exit_jmp; + struct jmp_buf_data *exit_jmp; EFIAPI efi_status_t (*entry)(efi_handle_t image_handle, struct efi_system_table *st); u16 image_type; diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 417215a2109..a89bdb31402 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -2899,6 +2899,8 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, efi_status_t ret; void *info; efi_handle_t parent_image = current_image; + efi_status_t exit_status; + struct jmp_buf_data exit_jmp; EFI_ENTRY("%p, %p, %p", image_handle, exit_data_size, exit_data); @@ -2920,9 +2922,11 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, image_obj->exit_data_size = exit_data_size; image_obj->exit_data = exit_data; + image_obj->exit_status = &exit_status; + image_obj->exit_jmp = &exit_jmp; /* call the image! */ - if (setjmp(&image_obj->exit_jmp)) { + if (setjmp(&exit_jmp)) { /* * We called the entry point of the child image with EFI_CALL * in the lines below. The child image called the Exit() boot @@ -2944,10 +2948,10 @@ efi_status_t EFIAPI efi_start_image(efi_handle_t image_handle, */ assert(__efi_entry_check()); EFI_PRINT("%lu returned by started image\n", - (unsigned long)((uintptr_t)image_obj->exit_status & + (unsigned long)((uintptr_t)exit_status & ~EFI_ERROR_MASK)); current_image = parent_image; - return EFI_EXIT(image_obj->exit_status); + return EFI_EXIT(exit_status); } current_image = image_handle; @@ -3130,6 +3134,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle, struct efi_loaded_image *loaded_image_protocol; struct efi_loaded_image_obj *image_obj = (struct efi_loaded_image_obj *)image_handle; + struct jmp_buf_data *exit_jmp; EFI_ENTRY("%p, %ld, %zu, %p", image_handle, exit_status, exit_data_size, exit_data); @@ -3171,6 +3176,9 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle, if (ret != EFI_SUCCESS) EFI_PRINT("%s: out of memory\n", __func__); } + /* efi_delete_image() frees image_obj. Copy before the call. */ + exit_jmp = image_obj->exit_jmp; + *image_obj->exit_status = exit_status; if (image_obj->image_type == IMAGE_SUBSYSTEM_EFI_APPLICATION || exit_status != EFI_SUCCESS) efi_delete_image(image_obj, loaded_image_protocol); @@ -3184,8 +3192,7 @@ static efi_status_t EFIAPI efi_exit(efi_handle_t image_handle, */ efi_restore_gd(); - image_obj->exit_status = exit_status; - longjmp(&image_obj->exit_jmp, 1); + longjmp(exit_jmp, 1); panic("EFI application exited"); out: -- cgit v1.3.1