From cb4820725e9fc409c5cbc8e83054a6ed522d2111 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 18 Jan 2007 11:28:51 +0100 Subject: [PATCH] Fix: Compilerwarnings for SC3 board. The EBC Configuration Register is now by CFG_EBC_CFG definable Added JFFS2 support for the SC3 board. Signed-off-by: Heiko Schocher --- include/configs/sc3.h | 39 ++++++++++++++++++++++++++------------- 1 file changed, 26 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 2d0278290a2..a4a16054601 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -108,7 +108,8 @@ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nand_args=setenv bootargs root=/dev/mtdblock4 rw\0" \ + "nand_args=setenv bootargs root=/dev/mtdblock5 rw" \ + "rootfstype=jffs2\0" \ "addip=setenv bootargs ${bootargs} " \ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ @@ -164,18 +165,19 @@ #define CONFIG_COMMANDS \ (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_NET | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_NAND | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_CACHE | \ - CFG_CMD_ELF ) + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_NET | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_NAND | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_CACHE | \ + CFG_CMD_ELF ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -404,6 +406,15 @@ extern unsigned long offsetOfEnvironment; #define NAND_MAX_CHIPS 1 #define CFG_NAND_BASE 0x77D00000 + +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ + +/* No command line, one static partition Partition 3 contains jffs2 rootfs */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" +#define CONFIG_JFFS2_PART_SIZE 0x00400000 +#define CONFIG_JFFS2_PART_OFFSET 0x00c00000 + /*----------------------------------------------------------------------- * Cache Configuration * @@ -516,6 +527,8 @@ extern unsigned long offsetOfEnvironment; #undef CFG_EBC_PB7AP #undef CFG_EBC_PB7CR +#define CFG_EBC_CFG 0xb84ef000 + #define CONFIG_SDRAM_BANK0 /* use the standard SDRAM initialization */ #undef CONFIG_SPD_EEPROM -- cgit v1.3.1 From 34167a36c29ee946b727465db5c014746a08e978 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 18 Jan 2007 11:48:10 +0100 Subject: [PATCH] Add missing Taishan config file Signed-off-by: Stefan Roese --- include/configs/taishan.h | 333 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 333 insertions(+) create mode 100644 include/configs/taishan.h (limited to 'include') diff --git a/include/configs/taishan.h b/include/configs/taishan.h new file mode 100644 index 00000000000..7ace3971d74 --- /dev/null +++ b/include/configs/taishan.h @@ -0,0 +1,333 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * TAISHAN.h - configuration for AMCC 440GX Ref + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_TAISHAN 1 /* Board is taishan */ +#define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#undef CFG_DRAM_TEST /* Disable-takes long time! */ +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */ +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CFG_EBC0_FLASH_BASE CFG_FLASH_BASE +#define CFG_EBC1_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x01000000) +#define CFG_EBC2_LCM_BASE (CFG_PERIPHERAL_BASE + 0x02000000) +#define CFG_EBC3_CONN_BASE (CFG_PERIPHERAL_BASE + 0x08000000) + +#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700) + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM*/ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc*/ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#define CONFIG_UART1_CONSOLE 1 /* use of UART1 as console */ +#define CONFIG_SERIAL_MULTI 1 /* enable serial multi support */ +#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ +#define CONFIG_BAUDRATE 115200 + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * E2PROM bootstrap configure value + *----------------------------------------------------------------------*/ + +/* + * 800/133/66 + * IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00 + */ + +/* + * 800/160/80 + * IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00 + */ + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */ +#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */ +#define CFG_SDRAM0_TR0 0xC10A401A +#undef CONFIG_SDRAM_ECC /* enable ECC support */ + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#undef CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#define CFG_BOOTSTRAP_IIC_ADDR 0x50 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=taishan\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=/tftpboot/taishan/uImage\0" \ + "kernel_addr=fc000000\0" \ + "ramdisk_addr=fc180000\0" \ + "load=tftp 100000 /tftpboot/taishan/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b 100000 fffc0000 40000;" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "fixedip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ + "$(gatewayip):$(netmask):$(hostname):$(netdev):off panic=1\0" \ + "dhcp=setenv bootargs $(bootargs) ip=dhcp\0" \ + "kozio=bootm 0xffe00000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/*----------------------------------------------------------------------- + * Networking + *----------------------------------------------------------------------*/ +#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ +#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ +#define CONFIG_PHY2_ADDR 0x1 +#define CONFIG_PHY3_ADDR 0x3 +#define CONFIG_ET1011C_PHY 1 +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_HAS_ETH2 +#define CONFIG_HAS_ETH3 +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +/*----------------------------------------------------------------------- + * Console/Commands/Parser + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_DTT | \ + CFG_CMD_ELF | \ + CFG_CMD_EEPROM | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------- + */ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_EEPRO100 1 /* include PCI EEPRO100 */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT /* let board init pci target */ + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 0057d758e3e874cbe7f24745d0cce8c1cb6c207e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 18 Jan 2007 11:54:52 +0100 Subject: [PATCH] Update Prodrive P3Mx support Signed-off-by: Stefan Roese --- board/prodrive/p3mx/p3mx.c | 63 +++++++++++++++++++++++++++++++++++++--- board/prodrive/p3mx/sdram_init.c | 4 +-- include/configs/p3mx.h | 5 ++-- 3 files changed, 64 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/board/prodrive/p3mx/p3mx.c b/board/prodrive/p3mx/p3mx.c index 6cebd1aeb6d..d54ddaffc1e 100644 --- a/board/prodrive/p3mx/p3mx.c +++ b/board/prodrive/p3mx/p3mx.c @@ -45,6 +45,7 @@ #include "mpsc.h" #include "64460.h" #include "mv_regs.h" +#include "p3mx.h" DECLARE_GLOBAL_DATA_PTR; @@ -79,6 +80,7 @@ extern flash_info_t flash_info[]; void board_prebootm_init (void); unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS; int display_mem_map (void); +void set_led(int); /* ------------------------------------------------------------------------- */ @@ -246,7 +248,6 @@ int board_early_init_f (void) * that if it's not at the power-on location, it's where we put * it last time. (huber) */ - my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS); #ifdef CONFIG_PCI @@ -287,6 +288,8 @@ int board_early_init_f (void) GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL); + set_led(LED_RED); + return 0; } @@ -332,6 +335,7 @@ void after_reloc (ulong dest_addr, gd_t * gd) /* display_mem_map(); */ /* now, jump to the main U-Boot board init code */ + set_led(LED_GREEN); board_init_r (gd, dest_addr); /* NOTREACHED */ } @@ -356,15 +360,66 @@ int checkboard (void) return (0); } -/* utility functions */ -void debug_led (int led, int mode) +void set_led(int col) { + int tmp; + int on_pin; + int off_pin; + + /* Program Mpp[22] as Gpp[22] + * Program Mpp[23] as Gpp[23] + */ + tmp = GTREGREAD(MPP_CONTROL2); + tmp &= 0x00ffffff; + GT_REG_WRITE(MPP_CONTROL2,tmp); + + /* Program Gpp[22] and Gpp[23] as output + */ + tmp = GTREGREAD(GPP_IO_CONTROL); + tmp |= 0x00C00000; + GT_REG_WRITE(GPP_IO_CONTROL, tmp); + + /* Program Gpp[22] and Gpp[23] as active high + */ + tmp = GTREGREAD(GPP_LEVEL_CONTROL); + tmp &= 0xff3fffff; + GT_REG_WRITE(GPP_LEVEL_CONTROL, tmp); + + switch(col) { + default: + case LED_OFF : + on_pin = 0; + off_pin = ((1 << 23) | (1 << 22)); + break; + case LED_RED : + on_pin = (1 << 23); + off_pin = (1 << 22); + break; + case LED_GREEN : + on_pin = (1 << 22); + off_pin = (1 << 23); + break; + case LED_ORANGE : + on_pin = ((1 << 23) | (1 << 22)); + off_pin = 0; + break; + } + + /* Set output Gpp[22] and Gpp[23] + */ + tmp = GTREGREAD(GPP_VALUE); + tmp |= on_pin; + tmp &= ~off_pin; + GT_REG_WRITE(GPP_VALUE, tmp); } int display_mem_map (void) { - int i, j; + int i; unsigned int base, size, width; +#ifdef CONFIG_PCI + int j; +#endif /* SDRAM */ printf ("SD (DDR) RAM\n"); diff --git a/board/prodrive/p3mx/sdram_init.c b/board/prodrive/p3mx/sdram_init.c index 176252efee5..0464860424e 100644 --- a/board/prodrive/p3mx/sdram_init.c +++ b/board/prodrive/p3mx/sdram_init.c @@ -65,7 +65,7 @@ int mvDmaTransfer (int, ulong, ulong, ulong, ulong); int memory_map_bank (unsigned int bankNo, unsigned int bankBase, unsigned int bankLength) { -#ifdef MAP_PCI +#if defined (MAP_PCI) && defined (CONFIG_PCI) PCI_HOST host; #endif @@ -80,7 +80,7 @@ int memory_map_bank (unsigned int bankNo, memoryMapBank (bankNo, bankBase, bankLength); -#ifdef MAP_PCI +#if defined (MAP_PCI) && defined (CONFIG_PCI) for (host = PCI_HOST0; host <= PCI_HOST1; host++) { const int features = PREFETCH_ENABLE | diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index 262e9d6acfc..54462f007cd 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -168,10 +168,12 @@ #define PCI_HOST_FORCE 1 /* configure as pci host */ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ -#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI /* include pci support */ +#ifdef CONFIG_PCI #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ +#endif /* CONFIG_PCI */ /* PCI MEMORY MAP section */ #define CFG_PCI0_MEM_BASE 0x80000000 @@ -194,7 +196,6 @@ #define CFG_PCI1_IO_SPACE_PCI 0x00000000 #define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE) - #define CFG_PCI_IDSEL 0x30 #undef CONFIG_BOOTARGS -- cgit v1.3.1 From 9d8d5a5bfb64768f29a0cb47fc37cd6f4c40e276 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 18 Jan 2007 16:05:47 +0100 Subject: [PATCH] Add support for Prodrive SCPU (PDNB3 variant) board Signed-off-by: Stefan Roese --- MAINTAINERS | 1 + MAKEALL | 2 +- Makefile | 11 +++++++++-- board/prodrive/pdnb3/flash.c | 4 ++++ include/configs/pdnb3.h | 37 +++++++++++++++++++++++++++++++++++-- 5 files changed, 50 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 81c113d7b1a..e9203eb05f3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -465,6 +465,7 @@ Stefan Roese ixdpg425 xscale pdnb3 xscale + scpu xscale Robert Schwebel diff --git a/MAKEALL b/MAKEALL index b3e16bc6c5b..40a5c773e59 100755 --- a/MAKEALL +++ b/MAKEALL @@ -225,7 +225,7 @@ LIST_pxa=" \ xsengine zylonite \ " -LIST_ixp="ixdp425 ixdpg425 pdnb3" +LIST_ixp="ixdp425 ixdpg425 pdnb3 scpu" LIST_arm=" \ diff --git a/Makefile b/Makefile index af3300688f7..b1952edfe7f 100644 --- a/Makefile +++ b/Makefile @@ -2066,8 +2066,15 @@ pleb2_config : unconfig logodl_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa logodl -pdnb3_config : unconfig - @$(MKCONFIG) $(@:_config=) arm ixp pdnb3 prodrive +pdnb3_config \ +scpu_config: unconfig + @if [ "$(findstring scpu_,$@)" ] ; then \ + echo "#define CONFIG_SCPU" >>include/config.h ; \ + echo "... on SCPU board variant" ; \ + else \ + >include/config.h ; \ + fi + @$(MKCONFIG) -a pdnb3 arm ixp pdnb3 prodrive pxa255_idp_config: unconfig @$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c index d0e5fe703b9..518ea9c0314 100644 --- a/board/prodrive/pdnb3/flash.c +++ b/board/prodrive/pdnb3/flash.c @@ -24,6 +24,8 @@ #include #include +#if !defined(CFG_FLASH_CFI_DRIVER) + /* * include common flash code (for esd boards) */ @@ -83,3 +85,5 @@ unsigned long flash_init(void) return size; } + +#endif /* CFG_FLASH_CFI_DRIVER */ diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index ba6b113d8c2..2cc137ce6a8 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -71,12 +71,18 @@ #define CONFIG_BAUDRATE 115200 #define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ +#if defined(CONFIG_SCPU) +#define CMD_NAND_ADD 0 +#else +#define CMD_NAND_ADD CFG_CMD_NAND +#endif + #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_DHCP | \ CFG_CMD_DATE | \ CFG_CMD_NET | \ CFG_CMD_MII | \ - CFG_CMD_NAND | \ + CMD_NAND_ADD | \ CFG_CMD_I2C | \ CFG_CMD_ELF | \ CFG_CMD_PING) @@ -176,12 +182,20 @@ #define CFG_FLASH_BASE 0x50000000 #define CFG_MONITOR_BASE CFG_FLASH_BASE +#if defined(CONFIG_SCPU) +#define CFG_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */ +#else #define CFG_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */ +#endif /* * Expansion bus settings */ +#if defined(CONFIG_SCPU) +#define CFG_EXP_CS0 0x94d23C42 /* 8bit, max size */ +#else #define CFG_EXP_CS0 0x94913C43 /* 8bit, max size */ +#endif #define CFG_EXP_CS1 0x85000043 /* 8bit, 512bytes */ /* @@ -194,6 +208,12 @@ /* * FLASH and environment organization */ +#if defined(CONFIG_SCPU) +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ +#endif + #define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ @@ -217,20 +237,27 @@ #define CFG_ENV_IS_IN_FLASH 1 +#if defined(CONFIG_SCPU) +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ +#else #define CFG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */ -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ +#endif +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) /* Address and size of Redundant Environment Sector */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#if !defined(CONFIG_SCPU) /* * NAND-FLASH stuff */ #define CFG_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 #define CFG_NAND_BASE 0x51000000 /* NAND FLASH Base Address */ +#endif /* * GPIO settings @@ -284,9 +311,15 @@ /* * I2C RTC */ +#if 0 /* test-only */ +#define CONFIG_RTC_DS1340 1 +#define CFG_I2C_RTC_ADDR 0x68 +#else +/* M41T11 Serial Access Timekeeper(R) SRAM */ #define CONFIG_RTC_M41T11 1 #define CFG_I2C_RTC_ADDR 0x68 #define CFG_M41T11_BASE_YEAR 1900 /* play along with the linux driver */ +#endif /* * Spartan3 FPGA configuration support -- cgit v1.3.1 From d0b6e14087ddd8789f224a48e1d33f2a5df4d167 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 19 Jan 2007 18:05:26 +0100 Subject: [PATCH] CFI: define CFG_WRITE_SWAPPED_DATA for the CFI-Flash driver if you must swap the bytes between reading/writing. (Needed for the SC3 board) Signed-off-by: Heiko Schocher --- drivers/cfi_flash.c | 26 ++++++++++---------------- include/configs/sc3.h | 3 +++ 2 files changed, 13 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index 665d8e7649c..696f9a47ada 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -40,10 +40,6 @@ #include #ifdef CFG_FLASH_CFI_DRIVER -#if defined(CONFIG_SOLIDCARD3) -#define __LITTLE_ENDIAN -#endif - /* * This file implements a Common Flash Interface (CFI) driver for U-Boot. * The width of the port and the width of the chips are determined at initialization. @@ -58,6 +54,8 @@ * AMD/Spansion Application Note: Migration from Single-byte to Three-byte * Device IDs, Publication Number 25538 Revision A, November 8, 2001 * + * define CFG_WRITE_SWAPPED_DATA, if you have to swap the Bytes between + * reading and writing ... (yes there is such a Hardware). */ #ifndef CFG_FLASH_BANKS_LIST @@ -260,7 +258,7 @@ inline uchar flash_read_uchar (flash_info_t * info, uint offset) uchar *cp; cp = flash_make_addr (info, 0, offset); -#if defined(__LITTLE_ENDIAN) +#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) return (cp[0]); #else return (cp[info->portwidth - 1]); @@ -287,7 +285,7 @@ ushort flash_read_ushort (flash_info_t * info, flash_sect_t sect, uint offset) debug ("addr[%x] = 0x%x\n", x, addr[x]); } #endif -#if defined(__LITTLE_ENDIAN) +#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) retval = ((addr[(info->portwidth)] << 8) | addr[0]); #else retval = ((addr[(2 * info->portwidth) - 1] << 8) | @@ -319,7 +317,7 @@ ulong flash_read_long (flash_info_t * info, flash_sect_t sect, uint offset) debug ("addr[%x] = 0x%x\n", x, addr[x]); } #endif -#if defined(__LITTLE_ENDIAN) +#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) retval = (addr[0] << 16) | (addr[(info->portwidth)] << 24) | (addr[(2 * info->portwidth)]) | (addr[(3 * info->portwidth)] << 8); #else @@ -860,7 +858,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, */ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) { -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SOLIDCARD3) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) unsigned short w; unsigned int l; unsigned long long ll; @@ -871,7 +869,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) cword->c = c; break; case FLASH_CFI_16BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SOLIDCARD3) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) w = c; w <<= 8; cword->w = (cword->w >> 8) | w; @@ -880,7 +878,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) #endif break; case FLASH_CFI_32BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SOLIDCARD3) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) l = c; l <<= 24; cword->l = (cword->l >> 8) | l; @@ -889,7 +887,7 @@ static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c) #endif break; case FLASH_CFI_64BIT: -#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SOLIDCARD3) +#if defined(__LITTLE_ENDIAN) && !defined(CFG_WRITE_SWAPPED_DATA) ll = c; ll <<= 56; cword->ll = (cword->ll >> 8) | ll; @@ -909,7 +907,7 @@ static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf) int i; uchar *cp = (uchar *) cmdbuf; -#if defined(__LITTLE_ENDIAN) +#if defined(__LITTLE_ENDIAN) || defined(CFG_WRITE_SWAPPED_DATA) for (i = info->portwidth; i > 0; i--) #else for (i = 1; i <= info->portwidth; i++) @@ -1535,8 +1533,4 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp, } #endif /* CFG_FLASH_USE_BUFFER_WRITE */ -#if defined(CONFIG_SOLIDCARD3) -#undef __LITTLE_ENDIAN -#endif - #endif /* CFG_FLASH_CFI */ diff --git a/include/configs/sc3.h b/include/configs/sc3.h index a4a16054601..bf2af9923cc 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -119,6 +119,8 @@ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=/tftpboot/sc3/uImage\0" \ + "u-boot=/tftpboot/sc3/u-boot.bin\0" \ + "setup=tftp 200000 /tftpboot/sc3/setup.img;autoscr 200000\0" \ "kernel_addr=FFE08000\0" \ "" #undef CONFIG_BOOTCOMMAND @@ -384,6 +386,7 @@ extern unsigned long offsetOfEnvironment; #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_WRITE_SWAPPED_DATA /* swap Databytes between reading/writing */ #define CFG_ENV_IS_IN_FLASH 1 #if CFG_ENV_IS_IN_FLASH -- cgit v1.3.1 From f539b7ba7d7ef6dd187c8209609001cb1cd95e39 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 19 Jan 2007 19:57:10 +0100 Subject: [PATCH] SC3 board: added CFG_CMD_AUTOSCRIPT. Signed-off-by: Heiko Schocher --- include/configs/sc3.h | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/configs/sc3.h b/include/configs/sc3.h index bf2af9923cc..b767449759d 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -167,18 +167,19 @@ #define CONFIG_COMMANDS \ (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_NET | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_NAND | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_CACHE | \ + CFG_CMD_AUTOSCRIPT | \ + CFG_CMD_PCI | \ + CFG_CMD_IRQ | \ + CFG_CMD_NET | \ + CFG_CMD_MII | \ + CFG_CMD_PING | \ + CFG_CMD_NAND | \ + CFG_CMD_JFFS2 | \ + CFG_CMD_I2C | \ + CFG_CMD_IDE | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_CACHE | \ CFG_CMD_ELF ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -- cgit v1.3.1 From 363d1d8f9c99b63daef81f5985cab3fc00edde5c Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Tue, 23 Jan 2007 13:25:22 +0100 Subject: [ColdFire MCF5271 family] Add CPU detection based on the value of Chip Identification Register (CIR). --- cpu/mcf52x2/cpu.c | 34 +++++++++++++++++++++++++++++++++- include/asm-m68k/m5271.h | 6 ++++++ 2 files changed, 39 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/cpu/mcf52x2/cpu.c b/cpu/mcf52x2/cpu.c index aa6b2bd670c..ce59d39cfab 100644 --- a/cpu/mcf52x2/cpu.c +++ b/cpu/mcf52x2/cpu.c @@ -49,11 +49,43 @@ #endif #ifdef CONFIG_M5271 +/* + * Both MCF5270 and MCF5271 are members of the MPC5271 family. Try to + * determine which one we are running on, based on the Chip Identification + * Register (CIR). + */ int checkcpu (void) { char buf[32]; + unsigned short cir; /* Chip Identification Register */ + unsigned short pin; /* Part identification number */ + unsigned char prn; /* Part revision number */ + char *cpu_model; + + cir = mbar_readShort(MCF_CCM_CIR); + pin = cir >> MCF_CCM_CIR_PIN_LEN; + prn = cir & MCF_CCM_CIR_PRN_MASK; + + switch (pin) { + case MCF_CCM_CIR_PIN_MCF5270: + cpu_model = "5270"; + break; + case MCF_CCM_CIR_PIN_MCF5271: + cpu_model = "5271"; + break; + default: + cpu_model = NULL; + break; + } + + if (cpu_model) + printf("CPU: Freescale ColdFire MCF%s rev. %hu, at %s MHz\n", + cpu_model, prn, strmhz(buf, CFG_CLK)); + else + printf("CPU: Unknown - Freescale ColdFire MCF5271 family" + " (PIN: 0x%x) rev. %hu, at %s MHz\n", + pin, prn, strmhz(buf, CFG_CLK)); - printf ("CPU: Freescale Coldfire MCF5271 at %s MHz\n", strmhz(buf, CFG_CLK)); return 0; } diff --git a/include/asm-m68k/m5271.h b/include/asm-m68k/m5271.h index 765414fdc32..e0f02cf7fdf 100644 --- a/include/asm-m68k/m5271.h +++ b/include/asm-m68k/m5271.h @@ -57,6 +57,12 @@ #define MCF_GPIO_PAR_FECI2C 0x100047 #define MCF_GPIO_PAR_UART 0x100048 +#define MCF_CCM_CIR 0x11000A +#define MCF_CCM_CIR_PRN_MASK 0x3F +#define MCF_CCM_CIR_PIN_LEN 6 +#define MCF_CCM_CIR_PIN_MCF5270 0x2e +#define MCF_CCM_CIR_PIN_MCF5271 0x80 + #define MCF_GPIO_AD_ADDR23 0x80 #define MCF_GPIO_AD_ADDR22 0x40 #define MCF_GPIO_AD_ADDR21 0x20 -- cgit v1.3.1 From 0ed47bb119cd2c4c16edb2548789148f9e6dc9de Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Tue, 23 Jan 2007 14:11:22 +0100 Subject: [iDMR] Using MII-related commands on iDRM board doesn't work now (e.g., "mii device" results in "Unexpected exception"). Fixing this properly requires some clean-up in the FEC drivers infrastructure for ColdFire, so this commit disables MII commads for now. --- include/configs/idmr.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 48915b32e36..8143f0d3feb 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -83,8 +83,7 @@ */ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ CFG_CMD_PING | \ - CFG_CMD_NET | \ - CFG_CMD_MII) & \ + CFG_CMD_NET) & \ ~(CFG_CMD_LOADS | \ CFG_CMD_LOADB)) @@ -194,4 +193,9 @@ /* Port configuration */ #define CFG_FECI2C 0xF0 + +#if (CONFIG_COMMANDS & CFG_CMD_MII) +#error MII commands don't work on iDMR board and sholud not be enabled. +#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */ + #endif /* _IDMR_H */ -- cgit v1.3.1 From 2daf046ba627f85f44195815778140039636244e Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Tue, 23 Jan 2007 17:22:06 +0100 Subject: [iDMR] Add MTD and JFFS2 support, also add default partition definition. --- include/configs/idmr.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include') diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 8143f0d3feb..b1dbe2ccb94 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -83,6 +83,7 @@ */ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ CFG_CMD_PING | \ + CFG_CMD_JFFS2 | \ CFG_CMD_NET) & \ ~(CFG_CMD_LOADS | \ CFG_CMD_LOADB)) @@ -194,6 +195,17 @@ /* Port configuration */ #define CFG_FECI2C 0xF0 + +/* Dynamic MTD partition support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=idmr-0" + +#define MTDPARTS_DEFAULT "mtdparts=idmr-0:128k(u-boot)," \ + "64k(env)," \ + "640k(kernel)," \ + "2m(rootfs)," \ + "-(user)"; + #if (CONFIG_COMMANDS & CFG_CMD_MII) #error MII commands don't work on iDMR board and sholud not be enabled. #endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */ -- cgit v1.3.1