From a9f04d49e519383f98689d603facdee227a2f94d Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 10 Nov 2014 18:00:19 -0700
Subject: fdt: Add a function to decode a variable-sized u32 array

Sometimes an array can be of variable size up to a maximum. Add a helper
function to decode this.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 include/fdtdec.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'include')

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 4ae77be9ba7..6b4000623d8 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -444,6 +444,22 @@ int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name);
 int fdtdec_get_int_array(const void *blob, int node, const char *prop_name,
 		u32 *array, int count);
 
+/**
+ * Look up a property in a node and return its contents in an integer
+ * array of given length. The property must exist but may have less data that
+ * expected (4*count bytes). It may have more, but this will be ignored.
+ *
+ * @param blob		FDT blob
+ * @param node		node to examine
+ * @param prop_name	name of property to find
+ * @param array		array to fill with data
+ * @param count		number of array elements
+ * @return number of array elements if ok, or -FDT_ERR_NOTFOUND if the
+ *		property is not found
+ */
+int fdtdec_get_int_array_count(const void *blob, int node,
+			       const char *prop_name, u32 *array, int count);
+
 /**
  * Look up a property in a node and return a pointer to its contents as a
  * unsigned int array of given length. The property must have at least enough
-- 
cgit v1.3.1


From 469a579df2907a421afec06e37d50e61b7d80227 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 10 Nov 2014 18:00:20 -0700
Subject: dm: serial: Move current serial port pointer to global_data

In general we can't store things in the data section until we have inited
SDRAM. Some platforms allow this (e.g. those with SPL) but some don't. Move
the pointer to global_data so that it will work on all platforms.

Without this fix the serial port will not work prior to relocation with
driver model on some platforms.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 drivers/serial/serial-uclass.c    | 35 +++++++++++++++++++----------------
 include/asm-generic/global_data.h |  1 +
 2 files changed, 20 insertions(+), 16 deletions(-)

(limited to 'include')

diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c
index 71f1a5cb910..0f019c8f505 100644
--- a/drivers/serial/serial-uclass.c
+++ b/drivers/serial/serial-uclass.c
@@ -19,15 +19,14 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* The currently-selected console serial device */
-struct udevice *cur_dev __attribute__ ((section(".data")));
-
 #ifndef CONFIG_SYS_MALLOC_F_LEN
 #error "Serial is required before relocation - define CONFIG_SYS_MALLOC_F_LEN to make this work"
 #endif
 
 static void serial_find_console_or_panic(void)
 {
+	struct udevice *dev;
+
 #ifdef CONFIG_OF_CONTROL
 	int node;
 
@@ -35,18 +34,21 @@ static void serial_find_console_or_panic(void)
 	node = fdtdec_get_chosen_node(gd->fdt_blob, "stdout-path");
 	if (node < 0)
 		node = fdtdec_get_alias_node(gd->fdt_blob, "console");
-	if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &cur_dev))
+	if (!uclass_get_device_by_of_offset(UCLASS_SERIAL, node, &dev)) {
+		gd->cur_serial_dev = dev;
 		return;
+	}
 
 	/*
 	 * If the console is not marked to be bound before relocation, bind
 	 * it anyway.
 	 */
 	if (node > 0 &&
-	    !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &cur_dev)) {
-		if (!device_probe(cur_dev))
+	    !lists_bind_fdt(gd->dm_root, gd->fdt_blob, node, &dev)) {
+		if (!device_probe(dev)) {
+			gd->cur_serial_dev = dev;
 			return;
-		cur_dev = NULL;
+		}
 	}
 #endif
 	/*
@@ -61,11 +63,12 @@ static void serial_find_console_or_panic(void)
 #else
 #define INDEX 0
 #endif
-	if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &cur_dev) &&
-	    uclass_get_device(UCLASS_SERIAL, INDEX, &cur_dev) &&
-	    (uclass_first_device(UCLASS_SERIAL, &cur_dev) || !cur_dev))
+	if (uclass_get_device_by_seq(UCLASS_SERIAL, INDEX, &dev) &&
+	    uclass_get_device(UCLASS_SERIAL, INDEX, &dev) &&
+	    (uclass_first_device(UCLASS_SERIAL, &dev) || !dev))
 		panic("No serial driver found");
 #undef INDEX
+	gd->cur_serial_dev = dev;
 }
 
 /* Called prior to relocation */
@@ -127,30 +130,30 @@ static int _serial_tstc(struct udevice *dev)
 
 void serial_putc(char ch)
 {
-	_serial_putc(cur_dev, ch);
+	_serial_putc(gd->cur_serial_dev, ch);
 }
 
 void serial_puts(const char *str)
 {
-	_serial_puts(cur_dev, str);
+	_serial_puts(gd->cur_serial_dev, str);
 }
 
 int serial_getc(void)
 {
-	return _serial_getc(cur_dev);
+	return _serial_getc(gd->cur_serial_dev);
 }
 
 int serial_tstc(void)
 {
-	return _serial_tstc(cur_dev);
+	return _serial_tstc(gd->cur_serial_dev);
 }
 
 void serial_setbrg(void)
 {
-	struct dm_serial_ops *ops = serial_get_ops(cur_dev);
+	struct dm_serial_ops *ops = serial_get_ops(gd->cur_serial_dev);
 
 	if (ops->setbrg)
-		ops->setbrg(cur_dev, gd->baudrate);
+		ops->setbrg(gd->cur_serial_dev, gd->baudrate);
 }
 
 void serial_stdio_init(void)
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index 74df2100336..f61acbc4fc1 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -91,6 +91,7 @@ typedef struct global_data {
 	unsigned long malloc_limit;	/* limit address */
 	unsigned long malloc_ptr;	/* current address */
 #endif
+	struct udevice *cur_serial_dev;	/* current serial device */
 	struct arch_global_data arch;	/* architecture-specific data */
 } gd_t;
 #endif
-- 
cgit v1.3.1


From e5901c94e32b3533c35511d1acfb7f1587e324ee Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 10 Nov 2014 18:00:21 -0700
Subject: dm: gpio: Add a function to read an ID from a list of GPIOs

For board IDs a common approach is to set aside several GPIOs for use in
determining the board ID. This can provide information about board features
and the revision.

Add a function that turns a list of GPIOs into an integer by assigning
each GPIO to a single bit.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 drivers/gpio/gpio-uclass.c | 19 +++++++++++++++++++
 include/asm-generic/gpio.h | 11 ++++++++++-
 2 files changed, 29 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 45e9a5ad227..255700ab18d 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -390,6 +390,25 @@ int gpio_get_status(struct udevice *dev, int offset, char *buf, int buffsize)
 	return 0;
 }
 
+/*
+ * get a number comprised of multiple GPIO values. gpio_num_array points to
+ * the array of gpio pin numbers to scan, terminated by -1.
+ */
+unsigned gpio_get_values_as_int(const int *gpio_num_array)
+{
+	int gpio;
+	unsigned bitmask = 1;
+	unsigned vector = 0;
+
+	while (bitmask &&
+	       ((gpio = *gpio_num_array++) != -1)) {
+		if (gpio_get_value(gpio))
+			vector |= bitmask;
+		bitmask <<= 1;
+	}
+	return vector;
+}
+
 /* We need to renumber the GPIOs when any driver is probed/removed */
 static int gpio_renumber(struct udevice *removed_dev)
 {
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index f81b51aa301..36a36c64b8a 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -257,6 +257,15 @@ const char *gpio_get_bank_info(struct udevice *dev, int *offset_count);
 int gpio_lookup_name(const char *name, struct udevice **devp,
 		     unsigned int *offsetp, unsigned int *gpiop);
 
-int name_to_gpio(const char *name);
+/**
+ * get_gpios() - Turn the values of a list of GPIOs into an integer
+ *
+ * This puts the value of the first GPIO into bit 0, the second into bit 1,
+ * etc. then returns the resulting integer.
+ *
+ * @gpio_list: List of GPIOs to collect
+ * @return resulting integer value
+ */
+unsigned gpio_get_values_as_int(const int *gpio_list);
 
 #endif	/* _ASM_GENERIC_GPIO_H_ */
-- 
cgit v1.3.1


From 880a3cc4381ac0e2e39ce3313e267fb3e297bc3f Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Mon, 10 Nov 2014 18:00:23 -0700
Subject: x86: config: Move common x86 configs to a common file

Many of the x86 CONFIG options will be common across different boards. Move
them to a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
---
 include/configs/coreboot.h   | 265 ++-----------------------------------------
 include/configs/x86-common.h | 251 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 260 insertions(+), 256 deletions(-)
 create mode 100644 include/configs/x86-common.h

(limited to 'include')

diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index fef267f70b2..25813804834 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -6,7 +6,6 @@
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
-#include <asm/ibmpc.h>
 /*
  * board/config.h - configuration options, board specific
  */
@@ -14,27 +13,23 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <configs/x86-common.h>
+
 /*
  * High Level Configuration Options
  * (easy to change)
  */
 #define CONFIG_SYS_COREBOOT
-#define CONFIG_SHOW_BOOT_PROGRESS
 #define CONFIG_LAST_STAGE_INIT
-#define CONFIG_SYS_VSNPRINTF
-#define CONFIG_ZBOOT_32
-#define CONFIG_PHYSMEM
 #define CONFIG_SYS_EARLY_PCI_INIT
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-#define CONFIG_DISPLAY_CPUINFO
 
-#define CONFIG_DM
-#define CONFIG_CMD_DM
-#define CONFIG_DM_GPIO
-#define CONFIG_DM_SERIAL
+#define CONFIG_SYS_CAR_ADDR			0x19200000
+#define CONFIG_SYS_CAR_SIZE			(16 * 1024)
+#define CONFIG_SYS_MONITOR_LEN			(256 * 1024)
 
-#define CONFIG_LMB
-#define CONFIG_OF_LIBFDT
+#define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
+#define CONFIG_TRACE_EARLY
+#define CONFIG_TRACE_EARLY_ADDR		0x01400000
 
 #define CONFIG_BOOTSTAGE
 #define CONFIG_BOOTSTAGE_REPORT
@@ -45,26 +40,6 @@
 #define CONFIG_BOOTSTAGE_STASH_SIZE	0x7fc
 #define CONFIG_BOOTSTAGE_USER_COUNT	60
 
-#define CONFIG_LZO
-#define CONFIG_FIT
-#undef CONFIG_ZLIB
-#undef CONFIG_GZIP
-#define CONFIG_SYS_BOOTM_LEN		(16 << 20)
-
-/*-----------------------------------------------------------------------
- * Watchdog Configuration
- */
-#undef CONFIG_WATCHDOG
-#undef CONFIG_HW_WATCHDOG
-
-/* SATA AHCI storage */
-
-#define CONFIG_SCSI_AHCI
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_LIBATA
-#define CONFIG_SYS_64BIT_LBA
-#define CONFIG_SATA_INTEL		1
 #define CONFIG_SCSI_DEV_LIST		{PCI_VENDOR_ID_INTEL, \
 			PCI_DEVICE_ID_INTEL_NM10_AHCI},	      \
 	{PCI_VENDOR_ID_INTEL,		\
@@ -74,249 +49,27 @@
 	{PCI_VENDOR_ID_INTEL,		\
 			PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
 
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	2
-#define CONFIG_SYS_SCSI_MAX_LUN		1
-#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
-					 CONFIG_SYS_SCSI_MAX_LUN)
-#endif
-
-/* Generic TPM interfaced through LPC bus */
-#define CONFIG_TPM
-#define CONFIG_TPM_TIS_LPC
-#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
-
-/*-----------------------------------------------------------------------
- * Real Time Clock Configuration
- */
-#define CONFIG_RTC_MC146818
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0
-#define CONFIG_SYS_ISA_IO      CONFIG_SYS_ISA_IO_BASE_ADDRESS
-
-/*-----------------------------------------------------------------------
- * Serial Configuration
- */
 #define CONFIG_COREBOOT_SERIAL
-#define CONFIG_SYS_NS16550
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{300, 600, 1200, 2400, 4800, \
-					 9600, 19200, 38400, 115200}
-#define CONFIG_SYS_NS16550_PORT_MAPPED
 
 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
 					"stdout=vga,serial,cbmem\0" \
 					"stderr=vga,serial,cbmem\0"
 
-#define CONFIG_CONSOLE_MUX
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define CONFIG_SYS_STDIO_DEREGISTER
 #define CONFIG_CBMEM_CONSOLE
 
-#define CONFIG_CMDLINE_EDITING
-#define CONFIG_COMMAND_HISTORY
-#define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
-
-#define CONFIG_SUPPORT_VFAT
-/************************************************************
- * ATAPI support (experimental)
- ************************************************************/
-#define CONFIG_ATAPI
-
-/************************************************************
- * DISK Partition support
- ************************************************************/
-#define CONFIG_EFI_PARTITION
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION		/* Experimental */
-
-#define CONFIG_CMD_PART
-#define CONFIG_CMD_CBFS
-#define CONFIG_CMD_EXT4
-#define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_PARTITION_UUIDS
-
-/*-----------------------------------------------------------------------
- * Video Configuration
- */
-#define CONFIG_VIDEO
 #define CONFIG_VIDEO_COREBOOT
-#define CONFIG_VIDEO_SW_CURSOR
-#define VIDEO_FB_16BPP_WORD_SWAP
-#define CONFIG_I8042_KBD
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
 
-/* x86 GPIOs are accessed through a PCI device */
-#define CONFIG_INTEL_ICH6_GPIO
-
-/*-----------------------------------------------------------------------
- * Command line configuration.
- */
-#include <config_cmd_default.h>
+#define CONFIG_NR_DRAM_BANKS			4
 
 #define CONFIG_TRACE
 #define CONFIG_CMD_TRACE
 #define CONFIG_TRACE_BUFFER_SIZE	(16 << 20)
-#define CONFIG_TRACE_EARLY_SIZE		(8 << 20)
-#define CONFIG_TRACE_EARLY
-#define CONFIG_TRACE_EARLY_ADDR		0x01400000
-
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_BOOTD
-#define CONFIG_CMD_CONSOLE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ECHO
-#undef CONFIG_CMD_FLASH
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_GPIO
-#define CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#define CONFIG_CMD_IO
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ITEST
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SETGETDCR
-#define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_TIME
-#define CONFIG_CMD_GETTIME
-#define CONFIG_CMD_XIMG
-#define CONFIG_CMD_SCSI
-
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_EXT2
-
-#define CONFIG_CMD_ZBOOT
-#define CONFIG_CMD_ELF
 
 #define CONFIG_BOOTDELAY	2
-#define CONFIG_BOOTARGS		\
-	"root=/dev/sdb3 init=/sbin/init rootwait ro"
-#define CONFIG_BOOTCOMMAND	\
-	"ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
-
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE			115200
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE			512
-#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
-						 sizeof(CONFIG_SYS_PROMPT) + \
-						 16)
-#define CONFIG_SYS_MAXARGS			16
-#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START		0x00100000
-#define CONFIG_SYS_MEMTEST_END			0x01000000
-#define CONFIG_SYS_LOAD_ADDR			0x20000000
-
-/*-----------------------------------------------------------------------
- * SDRAM Configuration
- */
-#define CONFIG_NR_DRAM_BANKS			4
-
-/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
-#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
-#undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
-#undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
-#undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
-
-/*-----------------------------------------------------------------------
- * CPU Features
- */
-
-#define CONFIG_SYS_X86_TSC_TIMER
-#define CONFIG_SYS_PCAT_INTERRUPTS
-#define CONFIG_SYS_PCAT_TIMER
-#define CONFIG_SYS_NUM_IRQS			16
-
-/*-----------------------------------------------------------------------
- * Memory organization:
- * 32kB Stack
- * 16kB Cache-As-RAM @ 0x19200000
- * 256kB Monitor
- * (128kB + Environment Sector Size) malloc pool
- */
-#define CONFIG_SYS_STACK_SIZE			(32 * 1024)
-#define CONFIG_SYS_CAR_ADDR			0x19200000
-#define CONFIG_SYS_CAR_SIZE			(16 * 1024)
-#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN			(256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN			(0x20000 + 128 * 1024)
-#define CONFIG_SYS_MALLOC_F_LEN			(1 << 10)
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*-----------------------------------------------------------------------
- * FLASH configuration
- */
-#define CONFIG_ICH_SPI
-#define CONFIG_SPI_FLASH
-#define CONFIG_SPI_FLASH_MACRONIX
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SPI_FLASH_GIGADEVICE
-#define CONFIG_SYS_NO_FLASH
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SF_TEST
-#define CONFIG_CMD_SPI
-#define CONFIG_SPI
-
-/*-----------------------------------------------------------------------
- * Environment configuration
- */
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_SIZE			0x01000
-
-/*-----------------------------------------------------------------------
- * PCI configuration
- */
-#define CONFIG_PCI
 
 #define CONFIG_CROS_EC
 #define CONFIG_CROS_EC_LPC
 #define CONFIG_CMD_CROS_EC
 #define CONFIG_ARCH_EARLY_INIT_R
 
-/*-----------------------------------------------------------------------
- * USB configuration
- */
-#define CONFIG_USB_EHCI
-#define CONFIG_USB_EHCI_PCI
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS     12
-#define CONFIG_USB_MAX_CONTROLLER_COUNT        2
-#define CONFIG_USB_STORAGE
-#define CONFIG_USB_KEYBOARD
-#define CONFIG_SYS_USB_EVENT_POLL
-
-#define CONFIG_USB_HOST_ETHER
-#define CONFIG_USB_ETHER_ASIX
-#define CONFIG_USB_ETHER_SMSC95XX
-#define CONFIG_TFTP_TSIZE
-#define CONFIG_CMD_DHCP
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-#define CONFIG_CMD_USB
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	CONFIG_STD_DEVICES_SETTINGS
-
 #endif	/* __CONFIG_H */
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
new file mode 100644
index 00000000000..825e9f78426
--- /dev/null
+++ b/include/configs/x86-common.h
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/ibmpc.h>
+
+#ifndef __CONFIG_X86_COMMON_H
+#define __CONFIG_X86_COMMON_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_SYS_VSNPRINTF
+#define CONFIG_ZBOOT_32
+#define CONFIG_PHYSMEM
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+#define CONFIG_DM_GPIO
+#define CONFIG_DM_SERIAL
+
+#define CONFIG_LMB
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_LZO
+#define CONFIG_FIT
+#undef CONFIG_ZLIB
+#undef CONFIG_GZIP
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20)
+
+/* SATA AHCI storage */
+
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SATA_INTEL
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_LIBATA
+#define CONFIG_SYS_64BIT_LBA
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	2
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+					 CONFIG_SYS_SCSI_MAX_LUN)
+#endif
+
+/* Generic TPM interfaced through LPC bus */
+#define CONFIG_TPM
+#define CONFIG_TPM_TIS_LPC
+#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
+
+/*-----------------------------------------------------------------------
+ * Real Time Clock Configuration
+ */
+#define CONFIG_RTC_MC146818
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0
+#define CONFIG_SYS_ISA_IO      CONFIG_SYS_ISA_IO_BASE_ADDRESS
+
+/*-----------------------------------------------------------------------
+ * Serial Configuration
+ */
+#define CONFIG_SYS_NS16550
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{300, 600, 1200, 2400, 4800, \
+					 9600, 19200, 38400, 115200}
+#define CONFIG_SYS_NS16550_PORT_MAPPED
+
+#define CONFIG_CONSOLE_MUX
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_STDIO_DEREGISTER
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_SUPPORT_VFAT
+/************************************************************
+ * ATAPI support (experimental)
+ ************************************************************/
+#define CONFIG_ATAPI
+
+/************************************************************
+ * DISK Partition support
+ ************************************************************/
+#define CONFIG_EFI_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION		/* Experimental */
+
+#define CONFIG_CMD_PART
+#define CONFIG_CMD_CBFS
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_PARTITION_UUIDS
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+
+/* x86 GPIOs are accessed through a PCI device */
+#define CONFIG_INTEL_ICH6_GPIO
+
+/*-----------------------------------------------------------------------
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BDI
+#define CONFIG_CMD_BOOTD
+#define CONFIG_CMD_CONSOLE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_ECHO
+#undef CONFIG_CMD_FLASH
+#define CONFIG_CMD_FPGA
+#define CONFIG_CMD_FPGA_LOADMK
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_IO
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_ITEST
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_MISC
+#define CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_SETGETDCR
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_TIME
+#define CONFIG_CMD_GETTIME
+#define CONFIG_CMD_XIMG
+#define CONFIG_CMD_SCSI
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+
+#define CONFIG_CMD_ZBOOT
+#define CONFIG_CMD_ELF
+
+#define CONFIG_BOOTARGS		\
+	"root=/dev/sdb3 init=/sbin/init rootwait ro"
+#define CONFIG_BOOTCOMMAND	\
+	"ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000"
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE			115200
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE			512
+#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE + \
+						 sizeof(CONFIG_SYS_PROMPT) + \
+						 16)
+#define CONFIG_SYS_MAXARGS			16
+#define CONFIG_SYS_BARGSIZE			CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START		0x00100000
+#define CONFIG_SYS_MEMTEST_END			0x01000000
+#define CONFIG_SYS_LOAD_ADDR			0x20000000
+
+/*-----------------------------------------------------------------------
+ * Video Configuration
+ */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_SW_CURSOR
+#define VIDEO_FB_16BPP_WORD_SWAP
+#define CONFIG_I8042_KBD
+#define CONFIG_CFB_CONSOLE
+
+/*-----------------------------------------------------------------------
+ * CPU Features
+ */
+
+#define CONFIG_SYS_X86_TSC_TIMER
+#define CONFIG_SYS_PCAT_INTERRUPTS
+#define CONFIG_SYS_PCAT_TIMER
+#define CONFIG_SYS_NUM_IRQS			16
+
+#define CONFIG_SYS_STACK_SIZE			(32 * 1024)
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MALLOC_LEN			0x200000
+#define CONFIG_SYS_MALLOC_F_LEN			(1 << 10)
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/*-----------------------------------------------------------------------
+ * FLASH configuration
+ */
+#define CONFIG_ICH_SPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_MACRONIX
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SPI_FLASH_GIGADEVICE
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SF_TEST
+#define CONFIG_CMD_SPI
+#define CONFIG_SPI
+
+/*-----------------------------------------------------------------------
+ * Environment configuration
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			0x01000
+
+/*-----------------------------------------------------------------------
+ * PCI configuration
+ */
+#define CONFIG_PCI
+
+/*-----------------------------------------------------------------------
+ * USB configuration
+ */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_PCI
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS     12
+#define CONFIG_USB_MAX_CONTROLLER_COUNT        2
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_KEYBOARD
+#define CONFIG_SYS_USB_EVENT_POLL
+
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_TFTP_TSIZE
+#define CONFIG_CMD_DHCP
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+#define CONFIG_CMD_USB
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_STD_DEVICES_SETTINGS
+
+#endif	/* __CONFIG_H */
-- 
cgit v1.3.1


From 8ef07571a0300e6ae84931c63d5eb3b2310c8aba Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 12 Nov 2014 22:42:07 -0700
Subject: x86: Add chromebook_link board

This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.

This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/x86/Kconfig                           |  23 ++++
 arch/x86/cpu/coreboot/coreboot.c           |   1 +
 arch/x86/cpu/ivybridge/Kconfig             | 171 +++++++++++++++++++++++++++++
 arch/x86/cpu/ivybridge/Makefile            |   9 ++
 arch/x86/cpu/ivybridge/car.S               |  20 ++++
 arch/x86/cpu/ivybridge/cpu.c               |  42 +++++++
 arch/x86/cpu/ivybridge/sdram.c             |  20 ++++
 arch/x86/dts/Makefile                      |   1 +
 arch/x86/dts/chromebook_link.dts           |   1 +
 arch/x86/include/asm/arch-ivybridge/gpio.h |  10 ++
 board/google/chromebook_link/Kconfig       |  15 +++
 board/google/chromebook_link/MAINTAINERS   |   6 +
 board/google/chromebook_link/Makefile      |  15 +++
 board/google/chromebook_link/link.c        |  17 +++
 board/google/common/Makefile               |   7 ++
 board/google/common/early_init.S           |  10 ++
 configs/chromebook_link_defconfig          |  10 ++
 include/configs/chromebook_link.h          |  60 ++++++++++
 18 files changed, 438 insertions(+)
 create mode 100644 arch/x86/cpu/ivybridge/Kconfig
 create mode 100644 arch/x86/cpu/ivybridge/Makefile
 create mode 100644 arch/x86/cpu/ivybridge/car.S
 create mode 100644 arch/x86/cpu/ivybridge/cpu.c
 create mode 100644 arch/x86/cpu/ivybridge/sdram.c
 create mode 120000 arch/x86/dts/chromebook_link.dts
 create mode 100644 arch/x86/include/asm/arch-ivybridge/gpio.h
 create mode 100644 board/google/chromebook_link/Kconfig
 create mode 100644 board/google/chromebook_link/MAINTAINERS
 create mode 100644 board/google/chromebook_link/Makefile
 create mode 100644 board/google/chromebook_link/link.c
 create mode 100644 board/google/common/Makefile
 create mode 100644 board/google/common/early_init.S
 create mode 100644 configs/chromebook_link_defconfig
 create mode 100644 include/configs/chromebook_link.h

(limited to 'include')

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 0dba8acbb2b..a5f24d00a69 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -12,9 +12,32 @@ choice
 
 config TARGET_COREBOOT
 	bool "Support coreboot"
+	help
+	  This target is used for running U-Boot on top of Coreboot. In
+	  this case Coreboot does the early inititalisation, and U-Boot
+	  takes over once the RAM, video and CPU are fully running.
+	  U-Boot is loaded as a fallback payload from Coreboot, in
+	  Coreboot terminology. This method was used for the Chromebook
+	  Pixel when launched.
+
+config TARGET_CHROMEBOOK_LINK
+	bool "Support Chromebook link"
+	help
+	  This is the Chromebook Pixel released in 2013. It uses an Intel
+	  i5 Ivybridge which is a die-shrink of Sandybridge, with 4GB of
+	  SDRAM. It has a Panther Point platform controller hub, PCIe
+	  WiFi and Bluetooth. It also includes a 720p webcam, USB SD
+	  reader, microphone and speakers, display port and 32GB SATA
+	  solid state drive. There is a Chrome OS EC connected on LPC,
+	  and it provides a 2560x1700 high resolution touch-enabled LCD
+	  display.
 
 endchoice
 
+source "arch/x86/cpu/ivybridge/Kconfig"
+
 source "board/chromebook-x86/coreboot/Kconfig"
 
+source "board/google/chromebook_link/Kconfig"
+
 endmenu
diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index c9f83b0e605..85017165c0a 100644
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -13,6 +13,7 @@
 #include <ns16550.h>
 #include <asm/msr.h>
 #include <asm/cache.h>
+#include <asm/cpu.h>
 #include <asm/io.h>
 #include <asm/arch-coreboot/tables.h>
 #include <asm/arch-coreboot/sysinfo.h>
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
new file mode 100644
index 00000000000..177247edc65
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -0,0 +1,171 @@
+#
+# From Coreboot src/northbridge/intel/sandybridge/Kconfig
+#
+# Copyright (C) 2010 Google Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0
+
+
+config NORTHBRIDGE_INTEL_SANDYBRIDGE
+	bool
+	select CACHE_MRC_BIN
+	select CPU_INTEL_MODEL_206AX
+
+config NORTHBRIDGE_INTEL_IVYBRIDGE
+	bool
+	select CACHE_MRC_BIN
+	select CPU_INTEL_MODEL_306AX
+
+if NORTHBRIDGE_INTEL_SANDYBRIDGE
+
+config VGA_BIOS_ID
+	string
+	default "8086,0106"
+
+config CACHE_MRC_SIZE_KB
+	int
+	default 256
+
+config MRC_CACHE_BASE
+	hex
+	default 0xff800000
+
+config MRC_CACHE_LOCATION
+	hex
+	depends on !CHROMEOS
+	default 0x1ec000
+
+config MRC_CACHE_SIZE
+	hex
+	depends on !CHROMEOS
+	default 0x10000
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xff7f0000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x10000
+
+endif
+
+if NORTHBRIDGE_INTEL_IVYBRIDGE
+
+config VGA_BIOS_ID
+	string
+	default "8086,0166"
+
+config EXTERNAL_MRC_BLOB
+	bool
+	default n
+
+config CACHE_MRC_SIZE_KB
+	int
+	default 512
+
+config MRC_CACHE_BASE
+	hex
+	default 0xff800000
+
+config MRC_CACHE_LOCATION
+	hex
+	depends on !CHROMEOS
+	default 0x370000
+
+config MRC_CACHE_SIZE
+	hex
+	depends on !CHROMEOS
+	default 0x10000
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xff7e0000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x20000
+
+endif
+
+if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE
+
+config HAVE_MRC
+        bool "Add a System Agent binary"
+        help
+          Select this option to add a System Agent binary to
+          the resulting U-Boot image. MRC stands for Memory Reference Code.
+          It is a binary blob which U-Boot uses to set up SDRAM.
+
+          Note: Without this binary U-Boot will not be able to set up its
+          SDRAM so will not boot.
+
+config DCACHE_RAM_MRC_VAR_SIZE
+	hex
+	default 0x4000
+	help
+	  This is the amount of CAR (Cache as RAM) reserved for use by the
+	  memory reference code. This should be set to 16KB (0x4000 hex)
+	  so that MRC has enough space to run.
+
+config MRC_FILE
+	string "Intel System Agent path and filename"
+	depends on HAVE_MRC
+	default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE
+	default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE
+	help
+	  The path and filename of the file to use as System Agent
+	  binary.
+
+config CPU_SPECIFIC_OPTIONS
+	def_bool y
+	select SMM_TSEG
+	select ARCH_BOOTBLOCK_X86_32
+	select ARCH_ROMSTAGE_X86_32
+	select ARCH_RAMSTAGE_X86_32
+	select SMP
+	select SSE2
+	select UDELAY_LAPIC
+	select CPU_MICROCODE_IN_CBFS
+	select TSC_SYNC_MFENCE
+	select HAVE_INTEL_ME
+
+config SMM_TSEG_SIZE
+	hex
+	default 0x800000
+
+config ENABLE_VMX
+	bool "Enable VMX for virtualization"
+	default n
+	help
+	  Virtual Machine Extensions are provided in many x86 CPUs. These
+	  provide various facilities for allowing a host OS to provide an
+	  environment where potentially several guest OSes have only
+	  limited access to the underlying hardware. This is achieved
+	  without resorting to software trapping and/or instruction set
+	  emulation (which would be very slow).
+
+	  Intel's implementation of this is called VT-x. This option enables
+	  VT-x this so that the OS that is booted by U-Boot can make use of
+	  these facilities. If this option is not enabled, then the host OS
+	  will be unable to support virtualisation, or it will run very
+	  slowly.
+
+endif
+
+config CPU_INTEL_SOCKET_RPGA989
+	bool
+
+if CPU_INTEL_SOCKET_RPGA989
+
+config SOCKET_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select MMX
+	select SSE
+	select CACHE_AS_RAM
+
+config CACHE_MRC_BIN
+	bool
+	default n
+
+endif
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
new file mode 100644
index 00000000000..dbcd4bdb3ae
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2014 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += car.o
+obj-y += cpu.o
+obj-y += sdram.o
diff --git a/arch/x86/cpu/ivybridge/car.S b/arch/x86/cpu/ivybridge/car.S
new file mode 100644
index 00000000000..0480813b743
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/car.S
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot file cpu/intel/model_206ax/cache_as_ram.inc
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2005 Tyan (written by Yinghai Lu for Tyan)
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2012 Kyösti Mälkki <kyosti.malkki@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+
+	/* Note: ebp must not be touched in this code */
+.globl car_init
+car_init:
+	/* TODO: Add cache-as-RAM init here */
+	jmp	car_init_ret
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
new file mode 100644
index 00000000000..1cbdaaffe63
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * Some portions from coreboot src/mainboard/google/link/romstage.c
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/cpu.h>
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int arch_cpu_init(void)
+{
+	int ret;
+
+	timer_set_base(rdtsc());
+
+	ret = x86_cpu_init_f();
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+int print_cpuinfo(void)
+{
+	char processor_name[CPU_MAX_NAME_LEN];
+	const char *name;
+
+	/* Print processor name */
+	name = cpu_get_name(processor_name);
+	printf("CPU:   %s\n", name);
+
+	return 0;
+}
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
new file mode 100644
index 00000000000..5f9ae5ecdbc
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2010,2011
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * Portions from Coreboot mainboard/google/link/romstage.c
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+
+int dram_init(void)
+{
+	/* TODO: Set up DRAM */
+
+	return 0;
+}
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 48265ef6dd4..bb3b116533e 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -1,4 +1,5 @@
 dtb-y += link.dtb \
+	chromebook_link.dtb \
 	alex.dtb
 
 targets += $(dtb-y)
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
new file mode 120000
index 00000000000..6f8c5cdba79
--- /dev/null
+++ b/arch/x86/dts/chromebook_link.dts
@@ -0,0 +1 @@
+link.dts
\ No newline at end of file
diff --git a/arch/x86/include/asm/arch-ivybridge/gpio.h b/arch/x86/include/asm/arch-ivybridge/gpio.h
new file mode 100644
index 00000000000..4951a8c9574
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/gpio.h
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2014, Google Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _X86_ARCH_GPIO_H_
+#define _X86_ARCH_GPIO_H_
+
+#endif /* _X86_ARCH_GPIO_H_ */
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
new file mode 100644
index 00000000000..975d557e1c5
--- /dev/null
+++ b/board/google/chromebook_link/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_CHROMEBOOK_LINK
+
+config SYS_BOARD
+	default "chromebook_link"
+
+config SYS_VENDOR
+	default "google"
+
+config SYS_SOC
+	default "ivybridge"
+
+config SYS_CONFIG_NAME
+	default "chromebook_link"
+
+endif
diff --git a/board/google/chromebook_link/MAINTAINERS b/board/google/chromebook_link/MAINTAINERS
new file mode 100644
index 00000000000..bc253a2ba7b
--- /dev/null
+++ b/board/google/chromebook_link/MAINTAINERS
@@ -0,0 +1,6 @@
+CHROMEBOOK LINK BOARD
+M:	Simon Glass <sjg@chromium.org>
+S:	Maintained
+F:	board/google/chromebook_link/
+F:	include/configs/chromebook_link.h
+F:	configs/chromebook_link_defconfig
diff --git a/board/google/chromebook_link/Makefile b/board/google/chromebook_link/Makefile
new file mode 100644
index 00000000000..a133c2e894b
--- /dev/null
+++ b/board/google/chromebook_link/Makefile
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+# (C) Copyright 2008
+# Graeme Russ, graeme.russ@gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= link.o
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
new file mode 100644
index 00000000000..ffa9d60c5a0
--- /dev/null
+++ b/board/google/chromebook_link/link.c
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+int arch_early_init_r(void)
+{
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	return 0;
+}
diff --git a/board/google/common/Makefile b/board/google/common/Makefile
new file mode 100644
index 00000000000..b38bc14ff66
--- /dev/null
+++ b/board/google/common/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2014 Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += early_init.o
diff --git a/board/google/common/early_init.S b/board/google/common/early_init.S
new file mode 100644
index 00000000000..cf70ae40c65
--- /dev/null
+++ b/board/google/common/early_init.S
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+	/* No 32-bit board specific initialisation */
+	jmp	early_board_init_ret
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
new file mode 100644
index 00000000000..b83803e1d2c
--- /dev/null
+++ b/configs/chromebook_link_defconfig
@@ -0,0 +1,10 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000"
+CONFIG_X86=y
+CONFIG_TARGET_CHROMEBOOK_LINK=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_SEPARATE=y
+CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
+CONFIG_HAVE_MRC=y
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
new file mode 100644
index 00000000000..394e27ba9d1
--- /dev/null
+++ b/include/configs/chromebook_link.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_CAR_ADDR			0xff7e0000
+#define CONFIG_SYS_CAR_SIZE			(128 * 1024)
+#define CONFIG_SYS_MONITOR_LEN			(1 << 20)
+#define CONFIG_BOARD_EARLY_INIT_R
+
+#define CONFIG_NR_DRAM_BANKS			8
+
+#define CONFIG_COREBOOT_SERIAL
+
+#define CONFIG_SCSI_DEV_LIST		{PCI_VENDOR_ID_INTEL, \
+			PCI_DEVICE_ID_INTEL_NM10_AHCI},	      \
+	{PCI_VENDOR_ID_INTEL,		\
+			PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
+	{PCI_VENDOR_ID_INTEL, \
+			PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
+	{PCI_VENDOR_ID_INTEL,		\
+			PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
+
+/*
+ * These common x86 features are not yet supported, but are added in
+ * follow-on patches in this series. Add undefs here to avoid every patch
+ * having to put things back into x86-common.h
+ */
+#undef CONFIG_INTEL_ICH6_GPIO
+#undef CONFIG_DM_GPIO
+#undef CONFIG_CMD_GPIO
+#undef CONFIG_VIDEO
+#undef CONFIG_CFB_CONSOLE
+#undef CONFIG_SYS_EARLY_PCI_INIT
+#undef CONFIG_PCI
+#undef CONFIG_ICH_SPI
+#undef CONFIG_SPI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_SF
+#undef CONFIG_USB_EHCI
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_SCSI
+
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
+					"stdout=vga,serial\0" \
+					"stderr=vga,serial\0"
+
+#endif	/* __CONFIG_H */
-- 
cgit v1.3.1


From fce7b2768364366bd4c4af9188186f6b3f9c2fe8 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 12 Nov 2014 22:42:08 -0700
Subject: x86: Build a .rom file which can be flashed to an x86 machine

On x86 machines U-Boot needs to be added to a large ROM image which is
then flashed onto the target board. The ROM has a particular format so it
makes sense for U-Boot to build this image automatically. Unfortunately
it relies on binary blobs so we cannot require this for the default
build as yet.

Create a u-boot.rom output file for this purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 Makefile                          | 36 +++++++++++++++++++++++++++++++++++-
 arch/x86/Kconfig                  | 13 +++++++++++++
 include/configs/chromebook_link.h |  2 ++
 3 files changed, 50 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/Makefile b/Makefile
index ddea53485a1..23590d91da8 100644
--- a/Makefile
+++ b/Makefile
@@ -749,6 +749,9 @@ ALL-$(CONFIG_SPL) += $(CONFIG_SPL_TARGET:"%"=%)
 endif
 ALL-$(CONFIG_REMAKE_ELF) += u-boot.elf
 
+# We can't do this yet due to the need for binary blobs
+# ALL-$(CONFIG_X86_RESET_VECTOR) += u-boot.rom
+
 # enable combined SPL/u-boot/dtb rules for tegra
 ifneq ($(CONFIG_TEGRA),)
 ifeq ($(CONFIG_SPL),y)
@@ -817,7 +820,8 @@ OBJCOPYFLAGS_u-boot.srec := -O srec
 u-boot.hex u-boot.srec: u-boot FORCE
 	$(call if_changed,objcopy)
 
-OBJCOPYFLAGS_u-boot.bin := -O binary
+OBJCOPYFLAGS_u-boot.bin := -O binary \
+		$(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec)
 
 binary_size_check: u-boot.bin FORCE
 	@file_size=$(shell wc -c u-boot.bin | awk '{print $$1}') ; \
@@ -956,6 +960,36 @@ u-boot-nand.gph: u-boot.bin FORCE
 	$(call if_changed,mkimage)
 	@dd if=/dev/zero bs=8 count=1 2>/dev/null >> $@
 
+# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
+# reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
+# the middle.
+ifneq ($(CONFIG_X86_RESET_VECTOR),)
+rom: u-boot.rom FORCE
+
+u-boot.rom: u-boot-x86-16bit.bin u-boot-dtb.bin \
+		$(srctree)/board/$(BOARDDIR)/mrc.bin
+	$(objtree)/tools/ifdtool -c -r $(CONFIG_ROM_SIZE) u-boot.tmp
+	if [ -n "$(CONFIG_HAVE_INTEL_ME)" ]; then \
+		$(objtree)/tools/ifdtool -D \
+			$(srctree)/board/$(BOARDDIR)/descriptor.bin u-boot.tmp; \
+		$(objtree)/tools/ifdtool \
+			-i ME:$(srctree)/board/$(BOARDDIR)/me.bin u-boot.tmp; \
+	fi
+	$(objtree)/tools/ifdtool -w \
+		$(CONFIG_SYS_TEXT_BASE):$(objtree)/u-boot-dtb.bin u-boot.tmp
+	$(objtree)/tools/ifdtool -w \
+		$(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin \
+		u-boot.tmp
+	$(objtree)/tools/ifdtool -w \
+		$(CONFIG_SYS_X86_START16):$(objtree)/u-boot-x86-16bit.bin \
+		u-boot.tmp
+	mv u-boot.tmp $@
+
+OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec
+u-boot-x86-16bit.bin: u-boot FORCE
+	$(call if_changed,objcopy)
+endif
+
 ifneq ($(CONFIG_SUNXI),)
 OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
 				   --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index a5f24d00a69..aa7cf779910 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -34,6 +34,19 @@ config TARGET_CHROMEBOOK_LINK
 
 endchoice
 
+config ROM_SIZE
+	hex
+	default 0x800000
+
+config HAVE_INTEL_ME
+	bool "Platform requires Intel Management Engine"
+	help
+	  Newer higher-end devices have an Intel Management Engine (ME)
+	  which is a very large binary blob (typically 1.5MB) which is
+	  required for the platform to work. This enforces a particular
+	  SPI flash format. You will need to supply the me.bin file in
+	  your board directory.
+
 source "arch/x86/cpu/ivybridge/Kconfig"
 
 source "board/chromebook-x86/coreboot/Kconfig"
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index 394e27ba9d1..3137ef08b81 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -18,8 +18,10 @@
 #define CONFIG_SYS_CAR_ADDR			0xff7e0000
 #define CONFIG_SYS_CAR_SIZE			(128 * 1024)
 #define CONFIG_SYS_MONITOR_LEN			(1 << 20)
+#define CONFIG_SYS_X86_START16			0xfffff800
 #define CONFIG_BOARD_EARLY_INIT_R
 
+#define CONFIG_X86_RESET_VECTOR
 #define CONFIG_NR_DRAM_BANKS			8
 
 #define CONFIG_COREBOOT_SERIAL
-- 
cgit v1.3.1


From 6e5b12b6144acd83dcfb4a79ea0beff787f3f545 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 12 Nov 2014 22:42:13 -0700
Subject: x86: ivybridge: Enable PCI in early init

Enable PCI so we can access devices that need to be set up before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/x86/cpu/ivybridge/Makefile   |  1 +
 arch/x86/cpu/ivybridge/cpu.c      |  6 ++++
 arch/x86/cpu/ivybridge/pci.c      | 60 +++++++++++++++++++++++++++++++++++++++
 include/configs/chromebook_link.h | 14 +++++++--
 4 files changed, 79 insertions(+), 2 deletions(-)
 create mode 100644 arch/x86/cpu/ivybridge/pci.c

(limited to 'include')

diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index dbcd4bdb3ae..6d0a78d25d2 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -6,4 +6,5 @@
 
 obj-y += car.o
 obj-y += cpu.o
+obj-y += pci.o
 obj-y += sdram.o
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 5863811b8c0..ff6b7b3e7ac 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -12,6 +12,7 @@
 
 #include <common.h>
 #include <asm/cpu.h>
+#include <asm/pci.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 
@@ -19,6 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int arch_cpu_init(void)
 {
+	struct pci_controller *hose;
 	int ret;
 
 	post_code(POST_CPU_INIT);
@@ -28,6 +30,10 @@ int arch_cpu_init(void)
 	if (ret)
 		return ret;
 
+	ret = pci_early_init_hose(&hose);
+	if (ret)
+		return ret;
+
 	return 0;
 }
 
diff --git a/arch/x86/cpu/ivybridge/pci.c b/arch/x86/cpu/ivybridge/pci.c
new file mode 100644
index 00000000000..c1ae658d3f3
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/pci.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008,2009
+ * Graeme Russ, <graeme.russ@gmail.com>
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+
+static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
+			      struct pci_config_table *table)
+{
+	u8 secondary;
+
+	hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
+	if (secondary != 0)
+		pci_hose_scan_bus(hose, secondary);
+}
+
+static struct pci_config_table pci_ivybridge_config_table[] = {
+	/* vendor, device, class, bus, dev, func */
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
+		PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
+	{}
+};
+
+void board_pci_setup_hose(struct pci_controller *hose)
+{
+	hose->config_table = pci_ivybridge_config_table;
+	hose->first_busno = 0;
+	hose->last_busno = 0;
+
+	/* PCI memory space */
+	pci_set_region(hose->regions + 0,
+		       CONFIG_PCI_MEM_BUS,
+		       CONFIG_PCI_MEM_PHYS,
+		       CONFIG_PCI_MEM_SIZE,
+		       PCI_REGION_MEM);
+
+	/* PCI IO space */
+	pci_set_region(hose->regions + 1,
+		       CONFIG_PCI_IO_BUS,
+		       CONFIG_PCI_IO_PHYS,
+		       CONFIG_PCI_IO_SIZE,
+		       PCI_REGION_IO);
+
+	pci_set_region(hose->regions + 2,
+		       CONFIG_PCI_PREF_BUS,
+		       CONFIG_PCI_PREF_PHYS,
+		       CONFIG_PCI_PREF_SIZE,
+		       PCI_REGION_PREFETCH);
+
+	hose->region_count = 3;
+}
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index 3137ef08b81..0b8c0678c79 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -45,8 +45,6 @@
 #undef CONFIG_CMD_GPIO
 #undef CONFIG_VIDEO
 #undef CONFIG_CFB_CONSOLE
-#undef CONFIG_SYS_EARLY_PCI_INIT
-#undef CONFIG_PCI
 #undef CONFIG_ICH_SPI
 #undef CONFIG_SPI
 #undef CONFIG_CMD_SPI
@@ -55,6 +53,18 @@
 #undef CONFIG_CMD_USB
 #undef CONFIG_CMD_SCSI
 
+#define CONFIG_PCI_MEM_BUS	0xe0000000
+#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
+#define CONFIG_PCI_MEM_SIZE	0x10000000
+
+#define CONFIG_PCI_PREF_BUS	0xd0000000
+#define CONFIG_PCI_PREF_PHYS	CONFIG_PCI_PREF_BUS
+#define CONFIG_PCI_PREF_SIZE	0x10000000
+
+#define CONFIG_PCI_IO_BUS	0x1000
+#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
+#define CONFIG_PCI_IO_SIZE	0xefff
+
 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
 					"stdout=vga,serial\0" \
 					"stderr=vga,serial\0"
-- 
cgit v1.3.1


From 77f9b1fb6244878ab4aab342a814880d17253b75 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 12 Nov 2014 22:42:21 -0700
Subject: x86: ivybridge: Perform Intel microcode update on boot

Microcode updates are stored in the device tree. Work through these and
apply any that are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/x86/cpu/ivybridge/Makefile                 |   1 +
 arch/x86/cpu/ivybridge/cpu.c                    |   5 +
 arch/x86/cpu/ivybridge/microcode_intel.c        | 151 ++++++++++++++++++++++++
 arch/x86/include/asm/arch-ivybridge/microcode.h |  20 ++++
 include/fdtdec.h                                |   1 +
 lib/fdtdec.c                                    |   1 +
 6 files changed, 179 insertions(+)
 create mode 100644 arch/x86/cpu/ivybridge/microcode_intel.c
 create mode 100644 arch/x86/include/asm/arch-ivybridge/microcode.h

(limited to 'include')

diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index 4b77c9cd835..74f01e87bd3 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -7,5 +7,6 @@
 obj-y += car.o
 obj-y += cpu.o
 obj-y += lpc.o
+obj-y += microcode_intel.o
 obj-y += pci.o
 obj-y += sdram.o
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 6a242d7c8bf..0aca2f02a7f 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -21,6 +21,7 @@
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/arch/model_206ax.h>
+#include <asm/arch/microcode.h>
 #include <asm/arch/pch.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -200,6 +201,10 @@ int print_cpuinfo(void)
 	if (ret)
 		return ret;
 
+	ret = microcode_update_intel();
+	if (ret && ret != -ENOENT && ret != -EEXIST)
+		return ret;
+
 	/* Print processor name */
 	name = cpu_get_name(processor_name);
 	printf("CPU:   %s\n", name);
diff --git a/arch/x86/cpu/ivybridge/microcode_intel.c b/arch/x86/cpu/ivybridge/microcode_intel.c
new file mode 100644
index 00000000000..8c11a6351f3
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/microcode_intel.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ * Copyright (C) 2000 Ronald G. Minnich
+ *
+ * Microcode update for Intel PIII and later CPUs
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <libfdt.h>
+#include <asm/cpu.h>
+#include <asm/msr.h>
+#include <asm/processor.h>
+
+/**
+ * struct microcode_update - standard microcode header from Intel
+ *
+ * We read this information out of the device tree and use it to determine
+ * whether the update is applicable or not. We also use the same structure
+ * to read information from the CPU.
+ */
+struct microcode_update {
+	uint header_version;
+	uint update_revision;
+	uint date_code;
+	uint processor_signature;
+	uint checksum;
+	uint loader_revision;
+	uint processor_flags;
+	const void *data;
+	int size;
+};
+
+static int microcode_decode_node(const void *blob, int node,
+				 struct microcode_update *update)
+{
+	update->data = fdt_getprop(blob, node, "data", &update->size);
+	if (!update->data)
+		return -EINVAL;
+
+	update->header_version = fdtdec_get_int(blob, node,
+						"intel,header-version", 0);
+	update->update_revision = fdtdec_get_int(blob, node,
+						 "intel,update-revision", 0);
+	update->date_code = fdtdec_get_int(blob, node,
+					   "intel,date-code", 0);
+	update->processor_signature = fdtdec_get_int(blob, node,
+					"intel.processor-signature", 0);
+	update->checksum = fdtdec_get_int(blob, node, "intel,checksum", 0);
+	update->loader_revision = fdtdec_get_int(blob, node,
+						 "loader-revision", 0);
+	update->processor_flags = fdtdec_get_int(blob, node,
+						 "processor-flags", 0);
+
+	return 0;
+}
+
+static uint32_t microcode_read_rev(void)
+{
+	/*
+	 * Some Intel CPUs can be very finicky about the CPUID sequence used.
+	 * So this is implemented in assembly so that it works reliably.
+	 */
+	uint32_t low, high;
+
+	asm volatile (
+		"xorl %%eax, %%eax\n"
+		"xorl %%edx, %%edx\n"
+		"movl $0x8b, %%ecx\n"
+		"wrmsr\n"
+		"movl $0x01, %%eax\n"
+		"cpuid\n"
+		"movl $0x8b, %%ecx\n"
+		"rdmsr\n"
+		: /* outputs */
+		"=a" (low), "=d" (high)
+		: /* inputs */
+		: /* clobbers */
+		 "ebx", "ecx"
+	);
+
+	return high;
+}
+
+static void microcode_read_cpu(struct microcode_update *cpu)
+{
+	/* CPUID sets MSR 0x8B iff a microcode update has been loaded. */
+	unsigned int x86_model, x86_family;
+	struct cpuid_result result;
+	uint32_t low, high;
+
+	wrmsr(0x8b, 0, 0);
+	result = cpuid(1);
+	rdmsr(0x8b, low, cpu->update_revision);
+	x86_model = (result.eax >> 4) & 0x0f;
+	x86_family = (result.eax >> 8) & 0x0f;
+	cpu->processor_signature = result.eax;
+
+	cpu->processor_flags = 0;
+	if ((x86_model >= 5) || (x86_family > 6)) {
+		rdmsr(0x17, low, high);
+		cpu->processor_flags = 1 << ((high >> 18) & 7);
+	}
+	debug("microcode: sig=%#x pf=%#x revision=%#x\n",
+	      cpu->processor_signature, cpu->processor_flags,
+	      cpu->update_revision);
+}
+
+/* Get a microcode update from the device tree and apply it */
+int microcode_update_intel(void)
+{
+	struct microcode_update cpu, update;
+	const void *blob = gd->fdt_blob;
+	int count;
+	int node;
+	int ret;
+
+	microcode_read_cpu(&cpu);
+	node = 0;
+	count = 0;
+	do {
+		node = fdtdec_next_compatible(blob, node,
+					      COMPAT_INTEL_MICROCODE);
+		if (node < 0) {
+			debug("%s: Found %d updates\n", __func__, count);
+			return count ? 0 : -ENOENT;
+		}
+
+		ret = microcode_decode_node(blob, node, &update);
+		if (ret) {
+			debug("%s: Unable to decode update: %d\n", __func__,
+			      ret);
+			return ret;
+		}
+		if (update.processor_signature == cpu.processor_signature &&
+		    (update.processor_flags & cpu.processor_flags)) {
+			debug("%s: Update already exists\n", __func__);
+			return -EEXIST;
+		}
+
+		wrmsr(0x79, (ulong)update.data, 0);
+		debug("microcode: updated to revision 0x%x date=%04x-%02x-%02x\n",
+		      microcode_read_rev(), update.date_code & 0xffff,
+		      (update.date_code >> 24) & 0xff,
+		      (update.date_code >> 16) & 0xff);
+		count++;
+	} while (1);
+}
diff --git a/arch/x86/include/asm/arch-ivybridge/microcode.h b/arch/x86/include/asm/arch-ivybridge/microcode.h
new file mode 100644
index 00000000000..bc9b87c44c4
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/microcode.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_MICROCODE_H
+#define __ASM_ARCH_MICROCODE_H
+
+/**
+ * microcode_update_intel() - Apply microcode updates
+ *
+ * Applies any microcode updates in the device tree.
+ *
+ * @return 0 if OK, -EEXIST if the updates were already applied, -ENOENT if
+ * not updates were found, -EINVAL if an update was invalid
+ */
+int microcode_update_intel(void);
+
+#endif
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 6b4000623d8..3bd60b7f122 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -118,6 +118,7 @@ enum fdt_compat_id {
 	COMPAT_SAMSUNG_EXYNOS_SYSMMU,	/* Exynos sysmmu */
 	COMPAT_PARADE_PS8625,		/* Parade PS8622 EDP->LVDS bridge */
 	COMPAT_INTEL_LPC,		/* Intel Low Pin Count I/F */
+	COMPAT_INTEL_MICROCODE,		/* Intel microcode update */
 
 	COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 4aa227a0c38..9a68f9ca154 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -73,6 +73,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(SAMSUNG_EXYNOS_SYSMMU, "samsung,sysmmu-v3.3"),
 	COMPAT(PARADE_PS8625, "parade,ps8625"),
 	COMPAT(COMPAT_INTEL_LPC, "intel,lpc"),
+	COMPAT(INTEL_MICROCODE, "intel,microcode"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
cgit v1.3.1


From 437c2b7cd04f017cf79dcde63e7d9035f8cd99e5 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 12 Nov 2014 22:42:25 -0700
Subject: x86: chromebook_link: Enable GPIO support

Enable GPIO support and provide the required GPIO setup information to
the driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/x86/dts/link.dts               |   3 +
 board/google/chromebook_link/link.c | 107 ++++++++++++++++++++++++++++++++++++
 include/configs/chromebook_link.h   |   4 +-
 3 files changed, 111 insertions(+), 3 deletions(-)

(limited to 'include')

diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index f1b7bf09417..74b21985f58 100644
--- a/arch/x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
@@ -14,18 +14,21 @@
 
 	gpioa {
 		compatible = "intel,ich6-gpio";
+		u-boot,dm-pre-reloc;
 		reg = <0 0x10>;
 		bank-name = "A";
 	};
 
 	gpiob {
 		compatible = "intel,ich6-gpio";
+		u-boot,dm-pre-reloc;
 		reg = <0x30 0x10>;
 		bank-name = "B";
 	};
 
 	gpioc {
 		compatible = "intel,ich6-gpio";
+		u-boot,dm-pre-reloc;
 		reg = <0x40 0x10>;
 		bank-name = "C";
 	};
diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c
index ffa9d60c5a0..88cee052415 100644
--- a/board/google/chromebook_link/link.c
+++ b/board/google/chromebook_link/link.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <asm/gpio.h>
 
 int arch_early_init_r(void)
 {
@@ -15,3 +16,109 @@ int board_early_init_r(void)
 {
 	return 0;
 }
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,  /* NMI_DBG# */
+	.gpio3 = GPIO_MODE_GPIO,  /* ALS_INT# */
+	.gpio5 = GPIO_MODE_GPIO,  /* SIM_DET */
+	.gpio7 = GPIO_MODE_GPIO,  /* EC_SCI# */
+	.gpio8 = GPIO_MODE_GPIO,  /* EC_SMI# */
+	.gpio9 = GPIO_MODE_GPIO,  /* RECOVERY# */
+	.gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
+	.gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
+	.gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
+	.gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
+	.gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
+	.gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
+	.gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
+	.gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio9 = GPIO_DIR_INPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio1 = GPIO_LEVEL_HIGH,
+	.gpio6 = GPIO_LEVEL_HIGH,
+	.gpio24 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio7 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio12 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+	.gpio15 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
+	.gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
+	.gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
+	.gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
+	.gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
+	.gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio36 = GPIO_DIR_OUTPUT,
+	.gpio41 = GPIO_DIR_INPUT,
+	.gpio42 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio36 = GPIO_LEVEL_HIGH,
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_map link_gpio_map = {
+	.set1 = {
+		.mode      = &pch_gpio_set1_mode,
+		.direction = &pch_gpio_set1_direction,
+		.level     = &pch_gpio_set1_level,
+		.invert    = &pch_gpio_set1_invert,
+	},
+	.set2 = {
+		.mode      = &pch_gpio_set2_mode,
+		.direction = &pch_gpio_set2_direction,
+		.level     = &pch_gpio_set2_level,
+	},
+	.set3 = {
+		.mode      = &pch_gpio_set3_mode,
+		.direction = &pch_gpio_set3_direction,
+		.level     = &pch_gpio_set3_level,
+	},
+};
+
+int board_early_init_f(void)
+{
+	ich_gpio_set_gpio_map(&link_gpio_map);
+
+	return 0;
+}
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index 0b8c0678c79..3063bd9a0f6 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -19,6 +19,7 @@
 #define CONFIG_SYS_CAR_SIZE			(128 * 1024)
 #define CONFIG_SYS_MONITOR_LEN			(1 << 20)
 #define CONFIG_SYS_X86_START16			0xfffff800
+#define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 
 #define CONFIG_X86_RESET_VECTOR
@@ -40,9 +41,6 @@
  * follow-on patches in this series. Add undefs here to avoid every patch
  * having to put things back into x86-common.h
  */
-#undef CONFIG_INTEL_ICH6_GPIO
-#undef CONFIG_DM_GPIO
-#undef CONFIG_CMD_GPIO
 #undef CONFIG_VIDEO
 #undef CONFIG_CFB_CONSOLE
 #undef CONFIG_ICH_SPI
-- 
cgit v1.3.1


From 65dd74a674d636afcc14594c8308ff516e95a445 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Wed, 12 Nov 2014 22:42:28 -0700
Subject: x86: ivybridge: Implement SDRAM init

Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in
the board directory and the SDRAM SPD information in the device tree. This
also needs the Intel Management Engine (me.bin) to work. Binary blobs
everywhere: so far we have MRC, ME and microcode.

SDRAM init works by setting up various parameters and calling the MRC. This
in turn does some sort of magic to work out how much memory there is and
the timing parameters to use. It also sets up the DRAM controllers. When
the MRC returns, we use the information it provides to map out the
available memory in U-Boot.

U-Boot normally moves itself to the top of RAM. On x86 the RAM is not
generally contiguous, and anyway some RAM may be above 4GB which doesn't
work in 32-bit mode. So we relocate to the top of the largest block of
RAM we can find below 4GB. Memory above 4GB is accessible with special
functions (see physmem).

It would be possible to build U-Boot in 64-bit mode but this wouldn't
necessarily provide any more memory, since the largest block is often below
4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large
ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit
kernels directly so this does not pose a limitation in that area. Also there
are probably parts of U-Boot that will not work correctly in 64-bit mode.
The MRC is one.

There is some work remaining in this area. Since memory init is very slow
(over 500ms) it is possible to save the parameters in SPI flash to speed it
up next time. Suspend/resume support is not fully implemented, or at least
it is not efficient.

With this patch, link boots to a prompt.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/x86/Kconfig                                  |  20 +
 arch/x86/cpu/ivybridge/Kconfig                    |   1 +
 arch/x86/cpu/ivybridge/Makefile                   |   3 +
 arch/x86/cpu/ivybridge/early_me.c                 | 191 ++++++++
 arch/x86/cpu/ivybridge/me_status.c                | 195 ++++++++
 arch/x86/cpu/ivybridge/report_platform.c          |  89 ++++
 arch/x86/cpu/ivybridge/sdram.c                    | 553 +++++++++++++++++++++-
 arch/x86/cpu/start.S                              |  10 +-
 arch/x86/dts/link.dts                             | 111 +++++
 arch/x86/include/asm/arch-ivybridge/me.h          | 356 ++++++++++++++
 arch/x86/include/asm/arch-ivybridge/pch.h         | 113 +++++
 arch/x86/include/asm/arch-ivybridge/pei_data.h    | 121 +++++
 arch/x86/include/asm/arch-ivybridge/sandybridge.h |   2 +
 arch/x86/include/asm/config.h                     |   1 +
 arch/x86/include/asm/global_data.h                |  13 +
 arch/x86/include/asm/post.h                       |   5 +
 arch/x86/include/asm/u-boot-x86.h                 |   2 +
 arch/x86/lib/Makefile                             |   1 +
 arch/x86/lib/ramtest.c                            |  79 ++++
 include/configs/chromebook_link.h                 |   4 +
 include/configs/x86-common.h                      |   2 +-
 include/fdtdec.h                                  |   1 +
 lib/fdtdec.c                                      |   1 +
 23 files changed, 1868 insertions(+), 6 deletions(-)
 create mode 100644 arch/x86/cpu/ivybridge/early_me.c
 create mode 100644 arch/x86/cpu/ivybridge/me_status.c
 create mode 100644 arch/x86/cpu/ivybridge/report_platform.c
 create mode 100644 arch/x86/include/asm/arch-ivybridge/me.h
 create mode 100644 arch/x86/include/asm/arch-ivybridge/pei_data.h
 create mode 100644 arch/x86/lib/ramtest.c

(limited to 'include')

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index f27d731bfd8..43c22ff7a5c 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -50,6 +50,17 @@ config CPU_ADDR_BITS
 	int
 	default 36
 
+config HPET_ADDRESS
+	hex
+	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
+
+config SMM_TSEG
+	bool
+	default n
+
+config SMM_TSEG_SIZE
+	hex
+
 config ROM_SIZE
 	hex
 	default 0x800000
@@ -63,6 +74,15 @@ config HAVE_INTEL_ME
 	  SPI flash format. You will need to supply the me.bin file in
 	  your board directory.
 
+config X86_RAMTEST
+	bool "Perform a simple RAM test after SDRAM initialisation"
+	help
+	  If there is something wrong with SDRAM then the platform will
+	  often crash within U-Boot or the kernel. This option enables a
+	  very simple RAM test that quickly checks whether the SDRAM seems
+	  to work correctly. It is not exhaustive but can save time by
+	  detecting obvious failures.
+
 source "arch/x86/cpu/ivybridge/Kconfig"
 
 source "board/chromebook-x86/coreboot/Kconfig"
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index 177247edc65..afca9579da2 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -129,6 +129,7 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_MICROCODE_IN_CBFS
 	select TSC_SYNC_MFENCE
 	select HAVE_INTEL_ME
+	select X86_RAMTEST
 
 config SMM_TSEG_SIZE
 	hex
diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile
index e5c0751e659..721b37e628c 100644
--- a/arch/x86/cpu/ivybridge/Makefile
+++ b/arch/x86/cpu/ivybridge/Makefile
@@ -7,7 +7,10 @@
 obj-y += car.o
 obj-y += cpu.o
 obj-y += early_init.o
+obj-y += early_me.o
 obj-y += lpc.o
+obj-y += me_status.o
 obj-y += microcode_intel.o
 obj-y += pci.o
+obj-y += report_platform.o
 obj-y += sdram.o
diff --git a/arch/x86/cpu/ivybridge/early_me.c b/arch/x86/cpu/ivybridge/early_me.c
new file mode 100644
index 00000000000..b24dea10b1e
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/early_me.c
@@ -0,0 +1,191 @@
+/*
+ * From Coreboot src/southbridge/intel/bd82x6x/early_me.c
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/pci.h>
+#include <asm/processor.h>
+#include <asm/arch/me.h>
+#include <asm/arch/pch.h>
+#include <asm/io.h>
+
+static const char *const me_ack_values[] = {
+	[ME_HFS_ACK_NO_DID]	= "No DID Ack received",
+	[ME_HFS_ACK_RESET]	= "Non-power cycle reset",
+	[ME_HFS_ACK_PWR_CYCLE]	= "Power cycle reset",
+	[ME_HFS_ACK_S3]		= "Go to S3",
+	[ME_HFS_ACK_S4]		= "Go to S4",
+	[ME_HFS_ACK_S5]		= "Go to S5",
+	[ME_HFS_ACK_GBL_RESET]	= "Global Reset",
+	[ME_HFS_ACK_CONTINUE]	= "Continue to boot"
+};
+
+static inline void pci_read_dword_ptr(void *ptr, int offset)
+{
+	u32 dword;
+
+	dword = pci_read_config32(PCH_ME_DEV, offset);
+	memcpy(ptr, &dword, sizeof(dword));
+}
+
+static inline void pci_write_dword_ptr(void *ptr, int offset)
+{
+	u32 dword = 0;
+	memcpy(&dword, ptr, sizeof(dword));
+	pci_write_config32(PCH_ME_DEV, offset, dword);
+}
+
+void intel_early_me_status(void)
+{
+	struct me_hfs hfs;
+	struct me_gmes gmes;
+
+	pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+	pci_read_dword_ptr(&gmes, PCI_ME_GMES);
+
+	intel_me_status(&hfs, &gmes);
+}
+
+int intel_early_me_init(void)
+{
+	int count;
+	struct me_uma uma;
+	struct me_hfs hfs;
+
+	debug("Intel ME early init\n");
+
+	/* Wait for ME UMA SIZE VALID bit to be set */
+	for (count = ME_RETRY; count > 0; --count) {
+		pci_read_dword_ptr(&uma, PCI_ME_UMA);
+		if (uma.valid)
+			break;
+		udelay(ME_DELAY);
+	}
+	if (!count) {
+		printf("ERROR: ME is not ready!\n");
+		return -EBUSY;
+	}
+
+	/* Check for valid firmware */
+	pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+	if (hfs.fpt_bad) {
+		printf("WARNING: ME has bad firmware\n");
+		return -EBADF;
+	}
+
+	debug("Intel ME firmware is ready\n");
+
+	return 0;
+}
+
+int intel_early_me_uma_size(void)
+{
+	struct me_uma uma;
+
+	pci_read_dword_ptr(&uma, PCI_ME_UMA);
+	if (uma.valid) {
+		debug("ME: Requested %uMB UMA\n", uma.size);
+		return uma.size;
+	}
+
+	debug("ME: Invalid UMA size\n");
+	return -EINVAL;
+}
+
+static inline void set_global_reset(int enable)
+{
+	u32 etr3;
+
+	etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
+
+	/* Clear CF9 Without Resume Well Reset Enable */
+	etr3 &= ~ETR3_CWORWRE;
+
+	/* CF9GR indicates a Global Reset */
+	if (enable)
+		etr3 |= ETR3_CF9GR;
+	else
+		etr3 &= ~ETR3_CF9GR;
+
+	pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
+}
+
+int intel_early_me_init_done(u8 status)
+{
+	u8 reset;
+	int count;
+	u32 mebase_l, mebase_h;
+	struct me_hfs hfs;
+	struct me_did did = {
+		.init_done = ME_INIT_DONE,
+		.status = status
+	};
+
+	/* MEBASE from MESEG_BASE[35:20] */
+	mebase_l = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L);
+	mebase_h = pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H);
+	mebase_h &= 0xf;
+	did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
+
+	/* Send message to ME */
+	debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n",
+	      status, did.uma_base);
+
+	pci_write_dword_ptr(&did, PCI_ME_H_GS);
+
+	/* Must wait for ME acknowledgement */
+	for (count = ME_RETRY; count > 0; --count) {
+		pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+		if (hfs.bios_msg_ack)
+			break;
+		udelay(ME_DELAY);
+	}
+	if (!count) {
+		printf("ERROR: ME failed to respond\n");
+		return -1;
+	}
+
+	/* Return the requested BIOS action */
+	debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]);
+
+	/* Check status after acknowledgement */
+	intel_early_me_status();
+
+	reset = 0;
+	switch (hfs.ack_data) {
+	case ME_HFS_ACK_CONTINUE:
+		/* Continue to boot */
+		return 0;
+	case ME_HFS_ACK_RESET:
+		/* Non-power cycle reset */
+		set_global_reset(0);
+		reset = 0x06;
+		break;
+	case ME_HFS_ACK_PWR_CYCLE:
+		/* Power cycle reset */
+		set_global_reset(0);
+		reset = 0x0e;
+		break;
+	case ME_HFS_ACK_GBL_RESET:
+		/* Global reset */
+		set_global_reset(1);
+		reset = 0x0e;
+		break;
+	case ME_HFS_ACK_S3:
+	case ME_HFS_ACK_S4:
+	case ME_HFS_ACK_S5:
+		break;
+	}
+
+	/* Perform the requested reset */
+	if (reset) {
+		outb(reset, 0xcf9);
+		cpu_hlt();
+	}
+	return -1;
+}
diff --git a/arch/x86/cpu/ivybridge/me_status.c b/arch/x86/cpu/ivybridge/me_status.c
new file mode 100644
index 00000000000..15cf69f40e3
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/me_status.c
@@ -0,0 +1,195 @@
+/*
+ * From Coreboot src/southbridge/intel/bd82x6x/me_status.c
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/arch/me.h>
+
+/* HFS1[3:0] Current Working State Values */
+static const char *const me_cws_values[] = {
+	[ME_HFS_CWS_RESET]	= "Reset",
+	[ME_HFS_CWS_INIT]	= "Initializing",
+	[ME_HFS_CWS_REC]	= "Recovery",
+	[ME_HFS_CWS_NORMAL]	= "Normal",
+	[ME_HFS_CWS_WAIT]	= "Platform Disable Wait",
+	[ME_HFS_CWS_TRANS]	= "OP State Transition",
+	[ME_HFS_CWS_INVALID]	= "Invalid CPU Plugged In"
+};
+
+/* HFS1[8:6] Current Operation State Values */
+static const char *const me_opstate_values[] = {
+	[ME_HFS_STATE_PREBOOT]	= "Preboot",
+	[ME_HFS_STATE_M0_UMA]	= "M0 with UMA",
+	[ME_HFS_STATE_M3]	= "M3 without UMA",
+	[ME_HFS_STATE_M0]	= "M0 without UMA",
+	[ME_HFS_STATE_BRINGUP]	= "Bring up",
+	[ME_HFS_STATE_ERROR]	= "M0 without UMA but with error"
+};
+
+/* HFS[19:16] Current Operation Mode Values */
+static const char *const me_opmode_values[] = {
+	[ME_HFS_MODE_NORMAL]	= "Normal",
+	[ME_HFS_MODE_DEBUG]	= "Debug",
+	[ME_HFS_MODE_DIS]	= "Soft Temporary Disable",
+	[ME_HFS_MODE_OVER_JMPR]	= "Security Override via Jumper",
+	[ME_HFS_MODE_OVER_MEI]	= "Security Override via MEI Message"
+};
+
+/* HFS[15:12] Error Code Values */
+static const char *const me_error_values[] = {
+	[ME_HFS_ERROR_NONE]	= "No Error",
+	[ME_HFS_ERROR_UNCAT]	= "Uncategorized Failure",
+	[ME_HFS_ERROR_IMAGE]	= "Image Failure",
+	[ME_HFS_ERROR_DEBUG]	= "Debug Failure"
+};
+
+/* GMES[31:28] ME Progress Code */
+static const char *const me_progress_values[] = {
+	[ME_GMES_PHASE_ROM]	= "ROM Phase",
+	[ME_GMES_PHASE_BUP]	= "BUP Phase",
+	[ME_GMES_PHASE_UKERNEL]	= "uKernel Phase",
+	[ME_GMES_PHASE_POLICY]	= "Policy Module",
+	[ME_GMES_PHASE_MODULE]	= "Module Loading",
+	[ME_GMES_PHASE_UNKNOWN]	= "Unknown",
+	[ME_GMES_PHASE_HOST]	= "Host Communication"
+};
+
+/* GMES[27:24] Power Management Event */
+static const char *const me_pmevent_values[] = {
+	[0x00] = "Clean Moff->Mx wake",
+	[0x01] = "Moff->Mx wake after an error",
+	[0x02] = "Clean global reset",
+	[0x03] = "Global reset after an error",
+	[0x04] = "Clean Intel ME reset",
+	[0x05] = "Intel ME reset due to exception",
+	[0x06] = "Pseudo-global reset",
+	[0x07] = "S0/M0->Sx/M3",
+	[0x08] = "Sx/M3->S0/M0",
+	[0x09] = "Non-power cycle reset",
+	[0x0a] = "Power cycle reset through M3",
+	[0x0b] = "Power cycle reset through Moff",
+	[0x0c] = "Sx/Mx->Sx/Moff"
+};
+
+/* Progress Code 0 states */
+static const char *const me_progress_rom_values[] = {
+	[0x00] = "BEGIN",
+	[0x06] = "DISABLE"
+};
+
+/* Progress Code 1 states */
+static const char *const me_progress_bup_values[] = {
+	[0x00] = "Initialization starts",
+	[0x01] = "Disable the host wake event",
+	[0x04] = "Flow determination start process",
+	[0x08] = "Error reading/matching the VSCC table in the descriptor",
+	[0x0a] = "Check to see if straps say ME DISABLED",
+	[0x0b] = "Timeout waiting for PWROK",
+	[0x0d] = "Possibly handle BUP manufacturing override strap",
+	[0x11] = "Bringup in M3",
+	[0x12] = "Bringup in M0",
+	[0x13] = "Flow detection error",
+	[0x15] = "M3 clock switching error",
+	[0x18] = "M3 kernel load",
+	[0x1c] = "T34 missing - cannot program ICC",
+	[0x1f] = "Waiting for DID BIOS message",
+	[0x20] = "Waiting for DID BIOS message failure",
+	[0x21] = "DID reported an error",
+	[0x22] = "Enabling UMA",
+	[0x23] = "Enabling UMA error",
+	[0x24] = "Sending DID Ack to BIOS",
+	[0x25] = "Sending DID Ack to BIOS error",
+	[0x26] = "Switching clocks in M0",
+	[0x27] = "Switching clocks in M0 error",
+	[0x28] = "ME in temp disable",
+	[0x32] = "M0 kernel load",
+};
+
+/* Progress Code 3 states */
+static const char *const me_progress_policy_values[] = {
+	[0x00] = "Entery into Policy Module",
+	[0x03] = "Received S3 entry",
+	[0x04] = "Received S4 entry",
+	[0x05] = "Received S5 entry",
+	[0x06] = "Received UPD entry",
+	[0x07] = "Received PCR entry",
+	[0x08] = "Received NPCR entry",
+	[0x09] = "Received host wake",
+	[0x0a] = "Received AC<>DC switch",
+	[0x0b] = "Received DRAM Init Done",
+	[0x0c] = "VSCC Data not found for flash device",
+	[0x0d] = "VSCC Table is not valid",
+	[0x0e] = "Flash Partition Boundary is outside address space",
+	[0x0f] = "ME cannot access the chipset descriptor region",
+	[0x10] = "Required VSCC values for flash parts do not match",
+};
+
+void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
+{
+	/* Check Current States */
+	debug("ME: FW Partition Table      : %s\n",
+	      hfs->fpt_bad ? "BAD" : "OK");
+	debug("ME: Bringup Loader Failure  : %s\n",
+	      hfs->ft_bup_ld_flr ? "YES" : "NO");
+	debug("ME: Firmware Init Complete  : %s\n",
+	      hfs->fw_init_complete ? "YES" : "NO");
+	debug("ME: Manufacturing Mode      : %s\n",
+	      hfs->mfg_mode ? "YES" : "NO");
+	debug("ME: Boot Options Present    : %s\n",
+	      hfs->boot_options_present ? "YES" : "NO");
+	debug("ME: Update In Progress      : %s\n",
+	      hfs->update_in_progress ? "YES" : "NO");
+	debug("ME: Current Working State   : %s\n",
+	      me_cws_values[hfs->working_state]);
+	debug("ME: Current Operation State : %s\n",
+	      me_opstate_values[hfs->operation_state]);
+	debug("ME: Current Operation Mode  : %s\n",
+	      me_opmode_values[hfs->operation_mode]);
+	debug("ME: Error Code              : %s\n",
+	      me_error_values[hfs->error_code]);
+	debug("ME: Progress Phase          : %s\n",
+	      me_progress_values[gmes->progress_code]);
+	debug("ME: Power Management Event  : %s\n",
+	      me_pmevent_values[gmes->current_pmevent]);
+
+	debug("ME: Progress Phase State    : ");
+	switch (gmes->progress_code) {
+	case ME_GMES_PHASE_ROM:		/* ROM Phase */
+		debug("%s", me_progress_rom_values[gmes->current_state]);
+		break;
+
+	case ME_GMES_PHASE_BUP:		/* Bringup Phase */
+		if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values) &&
+		    me_progress_bup_values[gmes->current_state])
+			debug("%s",
+			      me_progress_bup_values[gmes->current_state]);
+		else
+			debug("0x%02x", gmes->current_state);
+		break;
+
+	case ME_GMES_PHASE_POLICY:	/* Policy Module Phase */
+		if (gmes->current_state <
+				ARRAY_SIZE(me_progress_policy_values) &&
+		    me_progress_policy_values[gmes->current_state])
+			debug("%s",
+			      me_progress_policy_values[gmes->current_state]);
+		else
+			debug("0x%02x", gmes->current_state);
+		break;
+
+	case ME_GMES_PHASE_HOST:	/* Host Communication Phase */
+		if (!gmes->current_state)
+			debug("Host communication established");
+		else
+			debug("0x%02x", gmes->current_state);
+		break;
+
+	default:
+		debug("Unknown 0x%02x", gmes->current_state);
+	}
+	debug("\n");
+}
diff --git a/arch/x86/cpu/ivybridge/report_platform.c b/arch/x86/cpu/ivybridge/report_platform.c
new file mode 100644
index 00000000000..69e31b3ca29
--- /dev/null
+++ b/arch/x86/cpu/ivybridge/report_platform.c
@@ -0,0 +1,89 @@
+/*
+ * From Coreboot src/northbridge/intel/sandybridge/report_platform.c
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/cpu.h>
+#include <asm/pci.h>
+#include <asm/arch/pch.h>
+
+static void report_cpu_info(void)
+{
+	char cpu_string[CPU_MAX_NAME_LEN], *cpu_name;
+	const char *mode[] = {"NOT ", ""};
+	struct cpuid_result cpuidr;
+	int vt, txt, aes;
+	u32 index;
+
+	index = 0x80000000;
+	cpuidr = cpuid(index);
+	if (cpuidr.eax < 0x80000004) {
+		strcpy(cpu_string, "Platform info not available");
+		cpu_name = cpu_string;
+	} else {
+		cpu_name = cpu_get_name(cpu_string);
+	}
+
+	cpuidr = cpuid(1);
+	debug("CPU id(%x): %s\n", cpuidr.eax, cpu_name);
+	aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
+	txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
+	vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
+	debug("AES %ssupported, TXT %ssupported, VT %ssupported\n",
+	      mode[aes], mode[txt], mode[vt]);
+}
+
+/* The PCI id name match comes from Intel document 472178 */
+static struct {
+	u16 dev_id;
+	const char *dev_name;
+} pch_table[] = {
+	{0x1E41, "Desktop Sample"},
+	{0x1E42, "Mobile Sample"},
+	{0x1E43, "SFF Sample"},
+	{0x1E44, "Z77"},
+	{0x1E45, "H71"},
+	{0x1E46, "Z75"},
+	{0x1E47, "Q77"},
+	{0x1E48, "Q75"},
+	{0x1E49, "B75"},
+	{0x1E4A, "H77"},
+	{0x1E53, "C216"},
+	{0x1E55, "QM77"},
+	{0x1E56, "QS77"},
+	{0x1E58, "UM77"},
+	{0x1E57, "HM77"},
+	{0x1E59, "HM76"},
+	{0x1E5D, "HM75"},
+	{0x1E5E, "HM70"},
+	{0x1E5F, "NM70"},
+};
+
+static void report_pch_info(void)
+{
+	const char *pch_type = "Unknown";
+	int i;
+	u16 dev_id;
+	uint8_t rev_id;
+
+	dev_id = pci_read_config16(PCH_LPC_DEV, 2);
+	for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
+		if (pch_table[i].dev_id == dev_id) {
+			pch_type = pch_table[i].dev_name;
+			break;
+		}
+	}
+	rev_id = pci_read_config8(PCH_LPC_DEV, 8);
+	debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
+	      rev_id);
+}
+
+void report_platform_info(void)
+{
+	report_cpu_info();
+	report_pch_info();
+}
diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c
index 5f9ae5ecdbc..df2b9901fc0 100644
--- a/arch/x86/cpu/ivybridge/sdram.c
+++ b/arch/x86/cpu/ivybridge/sdram.c
@@ -11,10 +11,561 @@
  */
 
 #include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/gpio.h>
+#include <asm/global_data.h>
+#include <asm/pci.h>
+#include <asm/arch/me.h>
+#include <asm/arch/pei_data.h>
+#include <asm/arch/pch.h>
+#include <asm/post.h>
+#include <asm/arch/sandybridge.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * This function looks for the highest region of memory lower than 4GB which
+ * has enough space for U-Boot where U-Boot is aligned on a page boundary.
+ * It overrides the default implementation found elsewhere which simply
+ * picks the end of ram, wherever that may be. The location of the stack,
+ * the relocation address, and how far U-Boot is moved by relocation are
+ * set in the global data structure.
+ */
+ulong board_get_usable_ram_top(ulong total_size)
+{
+	struct memory_info *info = &gd->arch.meminfo;
+	uintptr_t dest_addr = 0;
+	struct memory_area *largest = NULL;
+	int i;
+
+	/* Find largest area of memory below 4GB */
+
+	for (i = 0; i < info->num_areas; i++) {
+		struct memory_area *area = &info->area[i];
+
+		if (area->start >= 1ULL << 32)
+			continue;
+		if (!largest || area->size > largest->size)
+			largest = area;
+	}
+
+	/* If no suitable area was found, return an error. */
+	assert(largest);
+	if (!largest || largest->size < (2 << 20))
+		panic("No available memory found for relocation");
+
+	dest_addr = largest->start + largest->size;
+
+	return (ulong)dest_addr;
+}
+
+void dram_init_banksize(void)
+{
+	struct memory_info *info = &gd->arch.meminfo;
+	int num_banks;
+	int i;
+
+	for (i = 0, num_banks = 0; i < info->num_areas; i++) {
+		struct memory_area *area = &info->area[i];
+
+		if (area->start >= 1ULL << 32)
+			continue;
+		gd->bd->bi_dram[num_banks].start = area->start;
+		gd->bd->bi_dram[num_banks].size = area->size;
+		num_banks++;
+	}
+}
+
+static const char *const ecc_decoder[] = {
+	"inactive",
+	"active on IO",
+	"disabled on IO",
+	"active"
+};
+
+/*
+ * Dump in the log memory controller configuration as read from the memory
+ * controller registers.
+ */
+static void report_memory_config(void)
+{
+	u32 addr_decoder_common, addr_decode_ch[2];
+	int i;
+
+	addr_decoder_common = readl(MCHBAR_REG(0x5000));
+	addr_decode_ch[0] = readl(MCHBAR_REG(0x5004));
+	addr_decode_ch[1] = readl(MCHBAR_REG(0x5008));
+
+	debug("memcfg DDR3 clock %d MHz\n",
+	      (readl(MCHBAR_REG(0x5e04)) * 13333 * 2 + 50) / 100);
+	debug("memcfg channel assignment: A: %d, B % d, C % d\n",
+	      addr_decoder_common & 3,
+	      (addr_decoder_common >> 2) & 3,
+	      (addr_decoder_common >> 4) & 3);
+
+	for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) {
+		u32 ch_conf = addr_decode_ch[i];
+		debug("memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
+		debug("   ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
+		debug("   enhanced interleave mode %s\n",
+		      ((ch_conf >> 22) & 1) ? "on" : "off");
+		debug("   rank interleave %s\n",
+		      ((ch_conf >> 21) & 1) ? "on" : "off");
+		debug("   DIMMA %d MB width x%d %s rank%s\n",
+		      ((ch_conf >> 0) & 0xff) * 256,
+		      ((ch_conf >> 19) & 1) ? 16 : 8,
+		      ((ch_conf >> 17) & 1) ? "dual" : "single",
+		      ((ch_conf >> 16) & 1) ? "" : ", selected");
+		debug("   DIMMB %d MB width x%d %s rank%s\n",
+		      ((ch_conf >> 8) & 0xff) * 256,
+		      ((ch_conf >> 20) & 1) ? 16 : 8,
+		      ((ch_conf >> 18) & 1) ? "dual" : "single",
+		      ((ch_conf >> 16) & 1) ? ", selected" : "");
+	}
+}
+
+static void post_system_agent_init(struct pei_data *pei_data)
+{
+	/* If PCIe init is skipped, set the PEG clock gating */
+	if (!pei_data->pcie_init)
+		setbits_le32(MCHBAR_REG(0x7010), 1);
+}
+
+static asmlinkage void console_tx_byte(unsigned char byte)
+{
+#ifdef DEBUG
+	putc(byte);
+#endif
+}
+
+/**
+ * Find the PEI executable in the ROM and execute it.
+ *
+ * @param pei_data: configuration data for UEFI PEI reference code
+ */
+int sdram_initialise(struct pei_data *pei_data)
+{
+	unsigned version;
+	const char *data;
+	uint16_t done;
+	int ret;
+
+	report_platform_info();
+
+	/* Wait for ME to be ready */
+	ret = intel_early_me_init();
+	if (ret)
+		return ret;
+	ret = intel_early_me_uma_size();
+	if (ret < 0)
+		return ret;
+
+	debug("Starting UEFI PEI System Agent\n");
+
+	/* If MRC data is not found we cannot continue S3 resume. */
+	if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
+		debug("Giving up in sdram_initialize: No MRC data\n");
+		outb(0x6, PORT_RESET);
+		cpu_hlt();
+	}
+
+	/* Pass console handler in pei_data */
+	pei_data->tx_byte = console_tx_byte;
+
+	debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
+
+	data = (char *)CONFIG_X86_MRC_START;
+	if (data) {
+		int rv;
+		int (*func)(struct pei_data *);
+
+		debug("Calling MRC at %p\n", data);
+		post_code(POST_PRE_MRC);
+		func = (int (*)(struct pei_data *))data;
+		rv = func(pei_data);
+		post_code(POST_MRC);
+		if (rv) {
+			switch (rv) {
+			case -1:
+				printf("PEI version mismatch.\n");
+				break;
+			case -2:
+				printf("Invalid memory frequency.\n");
+				break;
+			default:
+				printf("MRC returned %x.\n", rv);
+			}
+			printf("Nonzero MRC return value.\n");
+			return -EFAULT;
+		}
+	} else {
+		printf("UEFI PEI System Agent not found.\n");
+		return -ENOSYS;
+	}
+
+#if CONFIG_USBDEBUG
+	/* mrc.bin reconfigures USB, so reinit it to have debug */
+	early_usbdebug_init();
+#endif
+
+	version = readl(MCHBAR_REG(0x5034));
+	debug("System Agent Version %d.%d.%d Build %d\n",
+	      version >> 24 , (version >> 16) & 0xff,
+	      (version >> 8) & 0xff, version & 0xff);
+
+	/*
+	 * Send ME init done for SandyBridge here.  This is done inside the
+	 * SystemAgent binary on IvyBridge
+	 */
+	done = pci_read_config32(PCH_DEV, PCI_DEVICE_ID);
+	done &= BASE_REV_MASK;
+	if (BASE_REV_SNB == done)
+		intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
+	else
+		intel_early_me_status();
+
+	post_system_agent_init(pei_data);
+	report_memory_config();
+
+	return 0;
+}
+
+static int copy_spd(struct pei_data *peid)
+{
+	const int gpio_vector[] = {41, 42, 43, 10, -1};
+	int spd_index;
+	const void *blob = gd->fdt_blob;
+	int node, spd_node;
+	int ret, i;
+
+	for (i = 0; ; i++) {
+		if (gpio_vector[i] == -1)
+			break;
+		ret = gpio_requestf(gpio_vector[i], "spd_id%d", i);
+		if (ret) {
+			debug("%s: Could not request gpio %d\n", __func__,
+			      gpio_vector[i]);
+			return ret;
+		}
+	}
+	spd_index = gpio_get_values_as_int(gpio_vector);
+	debug("spd index %d\n", spd_index);
+	node = fdtdec_next_compatible(blob, 0, COMPAT_MEMORY_SPD);
+	if (node < 0) {
+		printf("SPD data not found.\n");
+		return -ENOENT;
+	}
+
+	for (spd_node = fdt_first_subnode(blob, node);
+	     spd_node > 0;
+	     spd_node = fdt_next_subnode(blob, spd_node)) {
+		const char *data;
+		int len;
+
+		if (fdtdec_get_int(blob, spd_node, "reg", -1) != spd_index)
+			continue;
+		data = fdt_getprop(blob, spd_node, "data", &len);
+		if (len < sizeof(peid->spd_data[0])) {
+			printf("Missing SPD data\n");
+			return -EINVAL;
+		}
+
+		debug("Using SDRAM SPD data for '%s'\n",
+		      fdt_get_name(blob, spd_node, NULL));
+		memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
+		break;
+	}
+
+	if (spd_node < 0) {
+		printf("No SPD data found for index %d\n", spd_index);
+		return -ENOENT;
+	}
+
+	return 0;
+}
+
+/**
+ * add_memory_area() - Add a new usable memory area to our list
+ *
+ * Note: @start and @end must not span the first 4GB boundary
+ *
+ * @info:	Place to store memory info
+ * @start:	Start of this memory area
+ * @end:	End of this memory area + 1
+ */
+static int add_memory_area(struct memory_info *info,
+			   uint64_t start, uint64_t end)
+{
+	struct memory_area *ptr;
+
+	if (info->num_areas == CONFIG_NR_DRAM_BANKS)
+		return -ENOSPC;
+
+	ptr = &info->area[info->num_areas];
+	ptr->start = start;
+	ptr->size = end - start;
+	info->total_memory += ptr->size;
+	if (ptr->start < (1ULL << 32))
+		info->total_32bit_memory += ptr->size;
+	debug("%d: memory %llx size %llx, total now %llx / %llx\n",
+	      info->num_areas, ptr->start, ptr->size,
+	      info->total_32bit_memory, info->total_memory);
+	info->num_areas++;
+
+	return 0;
+}
+
+/**
+ * sdram_find() - Find available memory
+ *
+ * This is a bit complicated since on x86 there are system memory holes all
+ * over the place. We create a list of available memory blocks
+ */
+static int sdram_find(pci_dev_t dev)
+{
+	struct memory_info *info = &gd->arch.meminfo;
+	uint32_t tseg_base, uma_size, tolud;
+	uint64_t tom, me_base, touud;
+	uint64_t uma_memory_base = 0;
+	uint64_t uma_memory_size;
+	unsigned long long tomk;
+	uint16_t ggc;
+
+	/* Total Memory 2GB example:
+	 *
+	 *  00000000  0000MB-1992MB  1992MB  RAM     (writeback)
+	 *  7c800000  1992MB-2000MB     8MB  TSEG    (SMRR)
+	 *  7d000000  2000MB-2002MB     2MB  GFX GTT (uncached)
+	 *  7d200000  2002MB-2034MB    32MB  GFX UMA (uncached)
+	 *  7f200000   2034MB TOLUD
+	 *  7f800000   2040MB MEBASE
+	 *  7f800000  2040MB-2048MB     8MB  ME UMA  (uncached)
+	 *  80000000   2048MB TOM
+	 * 100000000  4096MB-4102MB     6MB  RAM     (writeback)
+	 *
+	 * Total Memory 4GB example:
+	 *
+	 *  00000000  0000MB-2768MB  2768MB  RAM     (writeback)
+	 *  ad000000  2768MB-2776MB     8MB  TSEG    (SMRR)
+	 *  ad800000  2776MB-2778MB     2MB  GFX GTT (uncached)
+	 *  ada00000  2778MB-2810MB    32MB  GFX UMA (uncached)
+	 *  afa00000   2810MB TOLUD
+	 *  ff800000   4088MB MEBASE
+	 *  ff800000  4088MB-4096MB     8MB  ME UMA  (uncached)
+	 * 100000000   4096MB TOM
+	 * 100000000  4096MB-5374MB  1278MB  RAM     (writeback)
+	 * 14fe00000   5368MB TOUUD
+	 */
+
+	/* Top of Upper Usable DRAM, including remap */
+	touud = pci_read_config32(dev, TOUUD+4);
+	touud <<= 32;
+	touud |= pci_read_config32(dev, TOUUD);
+
+	/* Top of Lower Usable DRAM */
+	tolud = pci_read_config32(dev, TOLUD);
+
+	/* Top of Memory - does not account for any UMA */
+	tom = pci_read_config32(dev, 0xa4);
+	tom <<= 32;
+	tom |= pci_read_config32(dev, 0xa0);
+
+	debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
+
+	/* ME UMA needs excluding if total memory <4GB */
+	me_base = pci_read_config32(dev, 0x74);
+	me_base <<= 32;
+	me_base |= pci_read_config32(dev, 0x70);
+
+	debug("MEBASE %llx\n", me_base);
+
+	/* TODO: Get rid of all this shifting by 10 bits */
+	tomk = tolud >> 10;
+	if (me_base == tolud) {
+		/* ME is from MEBASE-TOM */
+		uma_size = (tom - me_base) >> 10;
+		/* Increment TOLUD to account for ME as RAM */
+		tolud += uma_size << 10;
+		/* UMA starts at old TOLUD */
+		uma_memory_base = tomk * 1024ULL;
+		uma_memory_size = uma_size * 1024ULL;
+		debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
+	}
+
+	/* Graphics memory comes next */
+	ggc = pci_read_config16(dev, GGC);
+	if (!(ggc & 2)) {
+		debug("IGD decoded, subtracting ");
+
+		/* Graphics memory */
+		uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
+		debug("%uM UMA", uma_size >> 10);
+		tomk -= uma_size;
+		uma_memory_base = tomk * 1024ULL;
+		uma_memory_size += uma_size * 1024ULL;
+
+		/* GTT Graphics Stolen Memory Size (GGMS) */
+		uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
+		tomk -= uma_size;
+		uma_memory_base = tomk * 1024ULL;
+		uma_memory_size += uma_size * 1024ULL;
+		debug(" and %uM GTT\n", uma_size >> 10);
+	}
+
+	/* Calculate TSEG size from its base which must be below GTT */
+	tseg_base = pci_read_config32(dev, 0xb8);
+	uma_size = (uma_memory_base - tseg_base) >> 10;
+	tomk -= uma_size;
+	uma_memory_base = tomk * 1024ULL;
+	uma_memory_size += uma_size * 1024ULL;
+	debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
+
+	debug("Available memory below 4GB: %lluM\n", tomk >> 10);
+
+	/* Report the memory regions */
+	add_memory_area(info, 1 << 20, 2 << 28);
+	add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
+	add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
+	add_memory_area(info, 1ULL << 32, touud);
+	/*
+	 * If >= 4GB installed then memory from TOLUD to 4GB
+	 * is remapped above TOM, TOUUD will account for both
+	 */
+	if (touud > (1ULL << 32ULL)) {
+		debug("Available memory above 4GB: %lluM\n",
+		      (touud >> 20) - 4096);
+	}
+
+	return 0;
+}
+
+static void rcba_config(void)
+{
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P3IP  WLAN   INTA -> PIRQB
+	 * D29IP_E1P   EHCI1  INTA -> PIRQD
+	 * D26IP_E2P   EHCI2  INTA -> PIRQF
+	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
+	 * D31IP_SMIP  SMBUS  INTB -> PIRQH
+	 * D31IP_TTIP  THRT   INTC -> PIRQA
+	 * D27IP_ZIP   HDA    INTA -> PIRQA (MSI)
+	 *
+	 * TRACKPAD                -> PIRQE (Edge Triggered)
+	 * TOUCHSCREEN             -> PIRQG (Edge Triggered)
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+	       (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP));
+	writel(NOINT << D30IP_PIP, RCB_REG(D30IP));
+	writel(INTA << D29IP_E1P, RCB_REG(D29IP));
+	writel(INTA << D28IP_P3IP, RCB_REG(D28IP));
+	writel(INTA << D27IP_ZIP, RCB_REG(D27IP));
+	writel(INTA << D26IP_E2P, RCB_REG(D26IP));
+	writel(NOINT << D25IP_LIP, RCB_REG(D25IP));
+	writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP));
+
+	/* Device interrupt route registers */
+	writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR));
+	writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR));
+	writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR));
+	writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR));
+	writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR));
+	writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR));
+	writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR));
+
+	/* Enable IOAPIC (generic) */
+	writew(0x0100, RCB_REG(OIC));
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void)readw(RCB_REG(OIC));
+
+	/* Disable unused devices (board specific) */
+	setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
+}
 
 int dram_init(void)
 {
-	/* TODO: Set up DRAM */
+	struct pei_data pei_data __aligned(8) = {
+		.pei_version = PEI_VERSION,
+		.mchbar = DEFAULT_MCHBAR,
+		.dmibar = DEFAULT_DMIBAR,
+		.epbar = DEFAULT_EPBAR,
+		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+		.smbusbar = SMBUS_IO_BASE,
+		.wdbbar = 0x4000000,
+		.wdbsize = 0x1000,
+		.hpet_address = CONFIG_HPET_ADDRESS,
+		.rcba = DEFAULT_RCBABASE,
+		.pmbase = DEFAULT_PMBASE,
+		.gpiobase = DEFAULT_GPIOBASE,
+		.thermalbase = 0xfed08000,
+		.system_type = 0, /* 0 Mobile, 1 Desktop/Server */
+		.tseg_size = CONFIG_SMM_TSEG_SIZE,
+		.ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+		.ec_present = 1,
+		.ddr3lv_support = 1,
+		/*
+		 * 0 = leave channel enabled
+		 * 1 = disable dimm 0 on channel
+		 * 2 = disable dimm 1 on channel
+		 * 3 = disable dimm 0+1 on channel
+		 */
+		.dimm_channel0_disabled = 2,
+		.dimm_channel1_disabled = 2,
+		.max_ddr3_freq = 1600,
+		.usb_port_config = {
+			/*
+			 * Empty and onboard Ports 0-7, set to un-used pin
+			 * OC3
+			 */
+			{ 0, 3, 0x0000 }, /* P0= Empty */
+			{ 1, 0, 0x0040 }, /* P1= Left USB 1  (OC0) */
+			{ 1, 1, 0x0040 }, /* P2= Left USB 2  (OC1) */
+			{ 1, 3, 0x0040 }, /* P3= SDCARD      (no OC) */
+			{ 0, 3, 0x0000 }, /* P4= Empty */
+			{ 1, 3, 0x0040 }, /* P5= WWAN        (no OC) */
+			{ 0, 3, 0x0000 }, /* P6= Empty */
+			{ 0, 3, 0x0000 }, /* P7= Empty */
+			/*
+			 * Empty and onboard Ports 8-13, set to un-used pin
+			 * OC4
+			 */
+			{ 1, 4, 0x0040 }, /* P8= Camera      (no OC) */
+			{ 1, 4, 0x0040 }, /* P9= Bluetooth   (no OC) */
+			{ 0, 4, 0x0000 }, /* P10= Empty */
+			{ 0, 4, 0x0000 }, /* P11= Empty */
+			{ 0, 4, 0x0000 }, /* P12= Empty */
+			{ 0, 4, 0x0000 }, /* P13= Empty */
+		},
+	};
+	pci_dev_t dev = PCI_BDF(0, 0, 0);
+	int ret;
+
+	debug("Boot mode %d\n", gd->arch.pei_boot_mode);
+	debug("mcr_input %p\n", pei_data.mrc_input);
+	pei_data.boot_mode = gd->arch.pei_boot_mode;
+	ret = copy_spd(&pei_data);
+	if (!ret)
+		ret = sdram_initialise(&pei_data);
+	if (ret)
+		return ret;
+
+	rcba_config();
+	quick_ram_check();
+
+	writew(0xCAFE, MCHBAR_REG(SSKPD));
+
+	post_code(POST_DRAM);
+
+	ret = sdram_find(dev);
+	if (ret)
+		return ret;
+
+	gd->ram_size = gd->arch.meminfo.total_32bit_memory;
 
 	return 0;
 }
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 1b738f99167..b0d0ac0610b 100644
--- a/arch/x86/cpu/start.S
+++ b/arch/x86/cpu/start.S
@@ -78,20 +78,22 @@ car_init_ret:
 	 * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM,
 	 * or fully initialised SDRAM - we really don't care which)
 	 * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack
-	 * and early malloc area.
+	 * and early malloc area. The MRC requires some space at the top.
 	 *
 	 * Stack grows down from top of CAR. We have:
 	 *
 	 * top-> CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE
+	 *	MRC area
 	 *	global_data
 	 *	x86 global descriptor table
 	 *	early malloc area
 	 *	stack
 	 * bottom-> CONFIG_SYS_CAR_ADDR
 	 */
-
-	/* Stack grows down from top of CAR */
-	movl	$(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE), %esp
+	movl	$(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp
+#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE
+	subl	$CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp
+#endif
 
 	/* Reserve space on stack for global data */
 	subl	$GENERATED_GBL_DATA_SIZE, %esp
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index 74b21985f58..932991604f7 100644
--- a/arch/x86/dts/link.dts
+++ b/arch/x86/dts/link.dts
@@ -41,6 +41,117 @@
 	chosen { };
 	memory { device_type = "memory"; reg = <0 0>; };
 
+	spd {
+		compatible = "memory-spd";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		elpida_4Gb_1600_x16 {
+			reg = <0>;
+			data = [92 10 0b 03 04 19 02 02
+				03 52 01 08 0a 00 fe 00
+				69 78 69 3c 69 11 18 81
+				20 08 3c 3c 01 40 83 81
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 0f 11 42 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 02 fe 00
+				11 52 00 00 00 07 7f 37
+				45 42 4a 32 30 55 47 36
+				45 42 55 30 2d 47 4e 2d
+				46 20 30 20 02 fe 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00];
+		};
+		samsung_4Gb_1600_1.35v_x16 {
+			reg = <1>;
+			data = [92 11 0b 03 04 19 02 02
+				03 11 01 08 0a 00 fe 00
+				69 78 69 3c 69 11 18 81
+				f0 0a 3c 3c 01 40 83 01
+				00 80 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 0f 11 02 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 80 ce 01
+				00 00 00 00 00 00 6a 04
+				4d 34 37 31 42 35 36 37
+				34 42 48 30 2d 59 4b 30
+				20 20 00 00 80 ce 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00];
+			};
+		micron_4Gb_1600_1.35v_x16 {
+			reg = <2>;
+			data = [92 11 0b 03 04 19 02 02
+				03 11 01 08 0a 00 fe 00
+				69 78 69 3c 69 11 18 81
+				20 08 3c 3c 01 40 83 05
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 0f 01 02 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 80 2c 00
+				00 00 00 00 00 00 ad 75
+				34 4b 54 46 32 35 36 36
+				34 48 5a 2d 31 47 36 45
+				31 20 45 31 80 2c 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				00 00 00 00 00 00 00 00
+				ff ff ff ff ff ff ff ff
+				ff ff ff ff ff ff ff ff
+				ff ff ff ff ff ff ff ff
+				ff ff ff ff ff ff ff ff
+				ff ff ff ff ff ff ff ff
+				ff ff ff ff ff ff ff ff
+				ff ff ff ff ff ff ff ff
+				ff ff ff ff ff ff ff ff
+				ff ff ff ff ff ff ff ff
+				ff ff ff ff ff ff ff ff];
+		};
+	};
+
 	spi {
 		#address-cells = <1>;
 		#size-cells = <0>;
diff --git a/arch/x86/include/asm/arch-ivybridge/me.h b/arch/x86/include/asm/arch-ivybridge/me.h
new file mode 100644
index 00000000000..3a0809d6ece
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/me.h
@@ -0,0 +1,356 @@
+/*
+ * From Coreboot src/southbridge/intel/bd82x6x/me.h
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _ASM_INTEL_ME_H
+#define _ASM_INTEL_ME_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#define ME_RETRY		100000	/* 1 second */
+#define ME_DELAY		10	/* 10 us */
+
+/*
+ * Management Engine PCI registers
+ */
+
+#define PCI_CPU_MEBASE_L	0x70	/* Set by MRC */
+#define PCI_CPU_MEBASE_H	0x74	/* Set by MRC */
+
+#define PCI_ME_HFS		0x40
+#define  ME_HFS_CWS_RESET	0
+#define  ME_HFS_CWS_INIT	1
+#define  ME_HFS_CWS_REC		2
+#define  ME_HFS_CWS_NORMAL	5
+#define  ME_HFS_CWS_WAIT	6
+#define  ME_HFS_CWS_TRANS	7
+#define  ME_HFS_CWS_INVALID	8
+#define  ME_HFS_STATE_PREBOOT	0
+#define  ME_HFS_STATE_M0_UMA	1
+#define  ME_HFS_STATE_M3	4
+#define  ME_HFS_STATE_M0	5
+#define  ME_HFS_STATE_BRINGUP	6
+#define  ME_HFS_STATE_ERROR	7
+#define  ME_HFS_ERROR_NONE	0
+#define  ME_HFS_ERROR_UNCAT	1
+#define  ME_HFS_ERROR_IMAGE	3
+#define  ME_HFS_ERROR_DEBUG	4
+#define  ME_HFS_MODE_NORMAL	0
+#define  ME_HFS_MODE_DEBUG	2
+#define  ME_HFS_MODE_DIS	3
+#define  ME_HFS_MODE_OVER_JMPR	4
+#define  ME_HFS_MODE_OVER_MEI	5
+#define  ME_HFS_BIOS_DRAM_ACK	1
+#define  ME_HFS_ACK_NO_DID	0
+#define  ME_HFS_ACK_RESET	1
+#define  ME_HFS_ACK_PWR_CYCLE	2
+#define  ME_HFS_ACK_S3		3
+#define  ME_HFS_ACK_S4		4
+#define  ME_HFS_ACK_S5		5
+#define  ME_HFS_ACK_GBL_RESET	6
+#define  ME_HFS_ACK_CONTINUE	7
+
+struct me_hfs {
+	u32 working_state:4;
+	u32 mfg_mode:1;
+	u32 fpt_bad:1;
+	u32 operation_state:3;
+	u32 fw_init_complete:1;
+	u32 ft_bup_ld_flr:1;
+	u32 update_in_progress:1;
+	u32 error_code:4;
+	u32 operation_mode:4;
+	u32 reserved:4;
+	u32 boot_options_present:1;
+	u32 ack_data:3;
+	u32 bios_msg_ack:4;
+} __packed;
+
+#define PCI_ME_UMA		0x44
+
+struct me_uma {
+	u32 size:6;
+	u32 reserved_1:10;
+	u32 valid:1;
+	u32 reserved_0:14;
+	u32 set_to_one:1;
+} __packed;
+
+#define PCI_ME_H_GS		0x4c
+#define  ME_INIT_DONE		1
+#define  ME_INIT_STATUS_SUCCESS	0
+#define  ME_INIT_STATUS_NOMEM	1
+#define  ME_INIT_STATUS_ERROR	2
+
+struct me_did {
+	u32 uma_base:16;
+	u32 reserved:8;
+	u32 status:4;
+	u32 init_done:4;
+} __packed;
+
+#define PCI_ME_GMES		0x48
+#define  ME_GMES_PHASE_ROM	0
+#define  ME_GMES_PHASE_BUP	1
+#define  ME_GMES_PHASE_UKERNEL	2
+#define  ME_GMES_PHASE_POLICY	3
+#define  ME_GMES_PHASE_MODULE	4
+#define  ME_GMES_PHASE_UNKNOWN	5
+#define  ME_GMES_PHASE_HOST	6
+
+struct me_gmes {
+	u32 bist_in_prog:1;
+	u32 icc_prog_sts:2;
+	u32 invoke_mebx:1;
+	u32 cpu_replaced_sts:1;
+	u32 mbp_rdy:1;
+	u32 mfs_failure:1;
+	u32 warm_rst_req_for_df:1;
+	u32 cpu_replaced_valid:1;
+	u32 reserved_1:2;
+	u32 fw_upd_ipu:1;
+	u32 reserved_2:4;
+	u32 current_state:8;
+	u32 current_pmevent:4;
+	u32 progress_code:4;
+} __packed;
+
+#define PCI_ME_HERES		0xbc
+#define  PCI_ME_EXT_SHA1	0x00
+#define  PCI_ME_EXT_SHA256	0x02
+#define PCI_ME_HER(x)		(0xc0+(4*(x)))
+
+struct me_heres {
+	u32 extend_reg_algorithm:4;
+	u32 reserved:26;
+	u32 extend_feature_present:1;
+	u32 extend_reg_valid:1;
+} __packed;
+
+/*
+ * Management Engine MEI registers
+ */
+
+#define MEI_H_CB_WW		0x00
+#define MEI_H_CSR		0x04
+#define MEI_ME_CB_RW		0x08
+#define MEI_ME_CSR_HA		0x0c
+
+struct mei_csr {
+	u32 interrupt_enable:1;
+	u32 interrupt_status:1;
+	u32 interrupt_generate:1;
+	u32 ready:1;
+	u32 reset:1;
+	u32 reserved:3;
+	u32 buffer_read_ptr:8;
+	u32 buffer_write_ptr:8;
+	u32 buffer_depth:8;
+} __packed;
+
+#define MEI_ADDRESS_CORE	0x01
+#define MEI_ADDRESS_AMT		0x02
+#define MEI_ADDRESS_RESERVED	0x03
+#define MEI_ADDRESS_WDT		0x04
+#define MEI_ADDRESS_MKHI	0x07
+#define MEI_ADDRESS_ICC		0x08
+#define MEI_ADDRESS_THERMAL	0x09
+
+#define MEI_HOST_ADDRESS	0
+
+struct mei_header {
+	u32 client_address:8;
+	u32 host_address:8;
+	u32 length:9;
+	u32 reserved:6;
+	u32 is_complete:1;
+} __packed;
+
+#define MKHI_GROUP_ID_CBM	0x00
+#define MKHI_GROUP_ID_FWCAPS	0x03
+#define MKHI_GROUP_ID_MDES	0x08
+#define MKHI_GROUP_ID_GEN	0xff
+
+#define MKHI_GLOBAL_RESET	0x0b
+
+#define MKHI_FWCAPS_GET_RULE	0x02
+
+#define MKHI_MDES_ENABLE	0x09
+
+#define MKHI_GET_FW_VERSION	0x02
+#define MKHI_END_OF_POST	0x0c
+#define MKHI_FEATURE_OVERRIDE	0x14
+
+struct mkhi_header {
+	u32 group_id:8;
+	u32 command:7;
+	u32 is_response:1;
+	u32 reserved:8;
+	u32 result:8;
+} __packed;
+
+struct me_fw_version {
+	u16 code_minor;
+	u16 code_major;
+	u16 code_build_number;
+	u16 code_hot_fix;
+	u16 recovery_minor;
+	u16 recovery_major;
+	u16 recovery_build_number;
+	u16 recovery_hot_fix;
+} __packed;
+
+
+#define HECI_EOP_STATUS_SUCCESS       0x0
+#define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
+
+#define CBM_RR_GLOBAL_RESET	0x01
+
+#define GLOBAL_RESET_BIOS_MRC	0x01
+#define GLOBAL_RESET_BIOS_POST	0x02
+#define GLOBAL_RESET_MEBX	0x03
+
+struct me_global_reset {
+	u8 request_origin;
+	u8 reset_type;
+} __packed;
+
+enum me_bios_path {
+	ME_NORMAL_BIOS_PATH,
+	ME_S3WAKE_BIOS_PATH,
+	ME_ERROR_BIOS_PATH,
+	ME_RECOVERY_BIOS_PATH,
+	ME_DISABLE_BIOS_PATH,
+	ME_FIRMWARE_UPDATE_BIOS_PATH,
+};
+
+struct __packed mbp_fw_version_name {
+	u32 major_version:16;
+	u32 minor_version:16;
+	u32 hotfix_version:16;
+	u32 build_version:16;
+};
+
+struct __packed mbp_icc_profile {
+	u8 num_icc_profiles;
+	u8 icc_profile_soft_strap;
+	u8 icc_profile_index;
+	u8 reserved;
+	u32 register_lock_mask[3];
+};
+
+struct __packed mefwcaps_sku {
+	u32 full_net:1;
+	u32 std_net:1;
+	u32 manageability:1;
+	u32 small_business:1;
+	u32 l3manageability:1;
+	u32 intel_at:1;
+	u32 intel_cls:1;
+	u32 reserved:3;
+	u32 intel_mpc:1;
+	u32 icc_over_clocking:1;
+	u32 pavp:1;
+	u32 reserved_1:4;
+	u32 ipv6:1;
+	u32 kvm:1;
+	u32 och:1;
+	u32 vlan:1;
+	u32 tls:1;
+	u32 reserved_4:1;
+	u32 wlan:1;
+	u32 reserved_5:8;
+};
+
+struct __packed tdt_state_flag {
+	u16 lock_state:1;
+	u16 authenticate_module:1;
+	u16 s3authentication:1;
+	u16 flash_wear_out:1;
+	u16 flash_variable_security:1;
+	u16 wwan3gpresent:1;
+	u16 wwan3goob:1;
+	u16 reserved:9;
+};
+
+struct __packed tdt_state_info {
+	u8 state;
+	u8 last_theft_trigger;
+	struct tdt_state_flag flags;
+};
+
+struct __packed platform_type_rule_data {
+	u32 platform_target_usage_type:4;
+	u32 platform_target_market_type:2;
+	u32 super_sku:1;
+	u32 reserved:1;
+	u32 intel_me_fw_image_type:4;
+	u32 platform_brand:4;
+	u32 reserved_1:16;
+};
+
+struct __packed mbp_fw_caps {
+	struct mefwcaps_sku fw_capabilities;
+	u8 available;
+};
+
+struct __packed mbp_rom_bist_data {
+	u16 device_id;
+	u16 fuse_test_flags;
+	u32 umchid[4];
+};
+
+struct __packed mbp_platform_key {
+	u32 key[8];
+};
+
+struct __packed mbp_plat_type {
+	struct platform_type_rule_data rule_data;
+	u8 available;
+};
+
+struct __packed me_bios_payload {
+	struct mbp_fw_version_name fw_version_name;
+	struct mbp_fw_caps fw_caps_sku;
+	struct mbp_rom_bist_data rom_bist_data;
+	struct mbp_platform_key platform_key;
+	struct mbp_plat_type fw_plat_type;
+	struct mbp_icc_profile icc_profile;
+	struct tdt_state_info at_state;
+	u32 mfsintegrity;
+};
+
+struct __packed mbp_header {
+	u32 mbp_size:8;
+	u32 num_entries:8;
+	u32 rsvd:16;
+};
+
+struct __packed mbp_item_header {
+	u32 app_id:8;
+	u32 item_id:8;
+	u32 length:8;
+	u32 rsvd:8;
+};
+
+struct __packed me_fwcaps {
+	u32 id;
+	u8 length;
+	struct mefwcaps_sku caps_sku;
+	u8 reserved[3];
+};
+
+/* Defined in me_status.c for both romstage and ramstage */
+void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
+
+void intel_early_me_status(void);
+int intel_early_me_init(void);
+int intel_early_me_uma_size(void);
+int intel_early_me_init_done(u8 status);
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index ae338e3d92a..c6efdb85659 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -31,6 +31,13 @@
 /* PCI Configuration Space (D31:F0): LPC */
 #define PCH_LPC_DEV		PCI_BDF(0, 0x1f, 0)
 
+#define GEN_PMCON_1		0xa0
+#define GEN_PMCON_2		0xa2
+#define GEN_PMCON_3		0xa4
+#define ETR3			0xac
+#define  ETR3_CWORWRE		(1 << 18)
+#define  ETR3_CF9GR		(1 << 20)
+
 #define PMBASE			0x40
 #define ACPI_CNTL		0x44
 #define BIOS_CNTL		0xDC
@@ -126,12 +133,97 @@
 #define RPC		0x0400	/* 32bit */
 #define RPFN		0x0404	/* 32bit */
 
+#define TRSR		0x1e00	/*  8bit */
+#define TRCR		0x1e10	/* 64bit */
+#define TWDR		0x1e18	/* 64bit */
+
+#define IOTR0		0x1e80	/* 64bit */
+#define IOTR1		0x1e88	/* 64bit */
+#define IOTR2		0x1e90	/* 64bit */
+#define IOTR3		0x1e98	/* 64bit */
+
+#define TCTL		0x3000	/*  8bit */
+
+#define NOINT		0
+#define INTA		1
+#define INTB		2
+#define INTC		3
+#define INTD		4
+
+#define DIR_IDR		12	/* Interrupt D Pin Offset */
+#define DIR_ICR		8	/* Interrupt C Pin Offset */
+#define DIR_IBR		4	/* Interrupt B Pin Offset */
+#define DIR_IAR		0	/* Interrupt A Pin Offset */
+
+#define PIRQA		0
+#define PIRQB		1
+#define PIRQC		2
+#define PIRQD		3
+#define PIRQE		4
+#define PIRQF		5
+#define PIRQG		6
+#define PIRQH		7
+
+/* IO Buffer Programming */
+#define IOBPIRI		0x2330
+#define IOBPD		0x2334
+#define IOBPS		0x2338
+#define  IOBPS_RW_BX    ((1 << 9)|(1 << 10))
+#define  IOBPS_WRITE_AX	((1 << 9)|(1 << 10))
+#define  IOBPS_READ_AX	((1 << 8)|(1 << 9)|(1 << 10))
+
+#define D31IP		0x3100	/* 32bit */
+#define D31IP_TTIP	24	/* Thermal Throttle Pin */
+#define D31IP_SIP2	20	/* SATA Pin 2 */
+#define D31IP_SMIP	12	/* SMBUS Pin */
+#define D31IP_SIP	8	/* SATA Pin */
+#define D30IP		0x3104	/* 32bit */
+#define D30IP_PIP	0	/* PCI Bridge Pin */
+#define D29IP		0x3108	/* 32bit */
+#define D29IP_E1P	0	/* EHCI #1 Pin */
+#define D28IP		0x310c	/* 32bit */
+#define D28IP_P8IP	28	/* PCI Express Port 8 */
+#define D28IP_P7IP	24	/* PCI Express Port 7 */
+#define D28IP_P6IP	20	/* PCI Express Port 6 */
+#define D28IP_P5IP	16	/* PCI Express Port 5 */
+#define D28IP_P4IP	12	/* PCI Express Port 4 */
+#define D28IP_P3IP	8	/* PCI Express Port 3 */
+#define D28IP_P2IP	4	/* PCI Express Port 2 */
+#define D28IP_P1IP	0	/* PCI Express Port 1 */
+#define D27IP		0x3110	/* 32bit */
+#define D27IP_ZIP	0	/* HD Audio Pin */
+#define D26IP		0x3114	/* 32bit */
+#define D26IP_E2P	0	/* EHCI #2 Pin */
+#define D25IP		0x3118	/* 32bit */
+#define D25IP_LIP	0	/* GbE LAN Pin */
+#define D22IP		0x3124	/* 32bit */
+#define D22IP_KTIP	12	/* KT Pin */
+#define D22IP_IDERIP	8	/* IDE-R Pin */
+#define D22IP_MEI2IP	4	/* MEI #2 Pin */
+#define D22IP_MEI1IP	0	/* MEI #1 Pin */
+#define D20IP		0x3128  /* 32bit */
+#define D20IP_XHCIIP	0
+#define D31IR		0x3140	/* 16bit */
+#define D30IR		0x3142	/* 16bit */
+#define D29IR		0x3144	/* 16bit */
+#define D28IR		0x3146	/* 16bit */
+#define D27IR		0x3148	/* 16bit */
+#define D26IR		0x314c	/* 16bit */
+#define D25IR		0x3150	/* 16bit */
+#define D22IR		0x315c	/* 16bit */
+#define D20IR		0x3160	/* 16bit */
+#define OIC		0x31fe	/* 16bit */
+
 #define SPI_FREQ_SWSEQ	0x3893
 #define SPI_DESC_COMP0	0x38b0
 #define SPI_FREQ_WR_ERA	0x38b4
 #define SOFT_RESET_CTRL 0x38f4
 #define SOFT_RESET_DATA 0x38f8
 
+#define DIR_ROUTE(a, b, c, d) \
+		(((d) << DIR_IDR) | ((c) << DIR_ICR) | \
+			((b) << DIR_IBR) | ((a) << DIR_IAR))
+
 #define RC		0x3400	/* 32bit */
 #define HPTC		0x3404	/* 32bit */
 #define GCS		0x3410	/* 32bit */
@@ -142,6 +234,27 @@
 #define FD2		0x3428	/* 32bit */
 #define CG		0x341c	/* 32bit */
 
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS	((1 << 0)|(1 << 26))
+#define PCH_DISABLE_P2P		(1 << 1)
+#define PCH_DISABLE_SATA1	(1 << 2)
+#define PCH_DISABLE_SMBUS	(1 << 3)
+#define PCH_DISABLE_HD_AUDIO	(1 << 4)
+#define PCH_DISABLE_EHCI2	(1 << 13)
+#define PCH_DISABLE_LPC		(1 << 14)
+#define PCH_DISABLE_EHCI1	(1 << 15)
+#define PCH_DISABLE_PCIE(x)	(1 << (16 + x))
+#define PCH_DISABLE_THERMAL	(1 << 24)
+#define PCH_DISABLE_SATA2	(1 << 25)
+#define PCH_DISABLE_XHCI	(1 << 27)
+
+/* Function Disable 2 RCBA 0x3428 */
+#define PCH_DISABLE_KT		(1 << 4)
+#define PCH_DISABLE_IDER	(1 << 3)
+#define PCH_DISABLE_MEI2	(1 << 2)
+#define PCH_DISABLE_MEI1	(1 << 1)
+#define PCH_ENABLE_DBDF		(1 << 0)
+
 /* ICH7 GPIOBASE */
 #define GPIO_USE_SEL	0x00
 #define GP_IO_SEL	0x04
diff --git a/arch/x86/include/asm/arch-ivybridge/pei_data.h b/arch/x86/include/asm/arch-ivybridge/pei_data.h
new file mode 100644
index 00000000000..5026c8bab31
--- /dev/null
+++ b/arch/x86/include/asm/arch-ivybridge/pei_data.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2011, Google Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef ASM_ARCH_PEI_DATA_H
+#define ASM_ARCH_PEI_DATA_H
+
+struct pch_usb3_controller_settings {
+	/* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */
+	uint16_t mode;
+	/* 4 bit mask, 1: switchable, 0: not switchable */
+	uint16_t hs_port_switch_mask;
+	/* 0: No xHCI preOS driver, 1: xHCI preOS driver */
+	uint16_t preboot_support;
+	/* 0: Disable, 1: Enable */
+	uint16_t xhci_streams;
+};
+
+typedef asmlinkage void (*tx_byte_func)(unsigned char byte);
+
+#define PEI_VERSION 6
+
+struct __packed pei_data {
+	uint32_t pei_version;
+	uint32_t mchbar;
+	uint32_t dmibar;
+	uint32_t epbar;
+	uint32_t pciexbar;
+	uint16_t smbusbar;
+	uint32_t wdbbar;
+	uint32_t wdbsize;
+	uint32_t hpet_address;
+	uint32_t rcba;
+	uint32_t pmbase;
+	uint32_t gpiobase;
+	uint32_t thermalbase;
+	uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */
+	uint32_t tseg_size;
+	uint8_t spd_addresses[4];
+	uint8_t ts_addresses[4];
+	int boot_mode;
+	int ec_present;
+	int gbe_enable;
+	/*
+	 * 0 = leave channel enabled
+	 * 1 = disable dimm 0 on channel
+	 * 2 = disable dimm 1 on channel
+	 * 3 = disable dimm 0+1 on channel
+	 */
+	int dimm_channel0_disabled;
+	int dimm_channel1_disabled;
+	/* Seed values saved in CMOS */
+	uint32_t scrambler_seed;
+	uint32_t scrambler_seed_s3;
+	/* Data read from flash and passed into MRC */
+	unsigned char *mrc_input;
+	unsigned int mrc_input_len;
+	/* Data from MRC that should be saved to flash */
+	unsigned char *mrc_output;
+	unsigned int mrc_output_len;
+	/*
+	 * Max frequency DDR3 could be ran at. Could be one of four values:
+	 * 800, 1067, 1333, 1600
+	 */
+	uint32_t max_ddr3_freq;
+	/*
+	 * USB Port Configuration:
+	 *  [0] = enable
+	 *  [1] = overcurrent pin
+	 *  [2] = length
+	 *
+	 * Ports 0-7 can be mapped to OC0-OC3
+	 * Ports 8-13 can be mapped to OC4-OC7
+	 *
+	 * Port Length
+	 *  MOBILE:
+	 *   < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude)
+	 *   < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude)
+	 *  DESKTOP:
+	 *   < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude)
+	 *   < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude)
+	 *   < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude)
+	 */
+	uint16_t usb_port_config[16][3];
+	/* See the usb3 struct above for details */
+	struct pch_usb3_controller_settings usb3;
+	/*
+	 * SPD data array for onboard RAM. Specify address 0xf0,
+	 * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in
+	 * spd_address for a given "DIMM".
+	 */
+	uint8_t spd_data[4][256];
+	tx_byte_func tx_byte;
+	int ddr3lv_support;
+	/*
+	 * pcie_init needs to be set to 1 to have the system agent initialise
+	 * PCIe. Note: This should only be required if your system has Gen3
+	 * devices and it will increase your boot time by at least 100ms.
+	 */
+	int pcie_init;
+	/*
+	 * N mode functionality. Leave this setting at 0.
+	 * 0 Auto
+	 * 1 1N
+	 * 2 2N
+	 */
+	int nmode;
+	/*
+	 * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows
+	 * for DIMM SPD data to specify whether double-rate is required for
+	 * extended operating temperature range.
+	 * 0 Enable double rate based upon temperature thresholds
+	 * 1 Normal rate
+	 * 2 Always enable double rate
+	 */
+	int ddr_refresh_rate_config;
+};
+
+#endif
diff --git a/arch/x86/include/asm/arch-ivybridge/sandybridge.h b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
index a1072f21e87..114ee19e241 100644
--- a/arch/x86/include/asm/arch-ivybridge/sandybridge.h
+++ b/arch/x86/include/asm/arch-ivybridge/sandybridge.h
@@ -102,6 +102,8 @@
 #define SSKPD		0x5d14	/* 16bit (scratchpad) */
 #define BIOS_RESET_CPL	0x5da8	/* 8bit */
 
+void report_platform_info(void);
+
 void sandybridge_early_init(int chipset_type);
 
 #endif
diff --git a/arch/x86/include/asm/config.h b/arch/x86/include/asm/config.h
index ff15828a713..c97d988f3be 100644
--- a/arch/x86/include/asm/config.h
+++ b/arch/x86/include/asm/config.h
@@ -10,5 +10,6 @@
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_LMB
 #define CONFIG_SYS_BOOT_RAMDISK_HIGH
+#define asmlinkage __attribute__((regparm(0)))
 
 #endif
diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h
index 4ea46d79eb2..48bbd1ae43e 100644
--- a/arch/x86/include/asm/global_data.h
+++ b/arch/x86/include/asm/global_data.h
@@ -17,6 +17,18 @@ enum pei_boot_mode_t {
 
 };
 
+struct memory_area {
+	uint64_t start;
+	uint64_t size;
+};
+
+struct memory_info {
+	int num_areas;
+	uint64_t total_memory;
+	uint64_t total_32bit_memory;
+	struct memory_area area[CONFIG_NR_DRAM_BANKS];
+};
+
 /* Architecture-specific global data */
 struct arch_global_data {
 	struct global_data *gd_addr;		/* Location of Global Data */
@@ -34,6 +46,7 @@ struct arch_global_data {
 	struct pci_controller *hose;	/* PCI hose for early use */
 	enum pei_boot_mode_t pei_boot_mode;
 	const struct pch_gpio_map *gpio_map;	/* board GPIO map */
+	struct memory_info meminfo;	/* Memory information */
 };
 
 #endif
diff --git a/arch/x86/include/asm/post.h b/arch/x86/include/asm/post.h
index 61dcda190a4..ce68839deca 100644
--- a/arch/x86/include/asm/post.h
+++ b/arch/x86/include/asm/post.h
@@ -27,6 +27,11 @@
 #define POST_CPU_INIT		0x2b
 #define POST_EARLY_INIT		0x2c
 #define POST_CPU_INFO		0x2d
+#define POST_PRE_MRC		0x2e
+#define POST_MRC		0x2f
+#define POST_DRAM		0x2f
+
+#define POST_RAM_FAILURE	0xea
 
 /* Output a post code using al - value must be 0 to 0xff */
 #ifdef __ASSEMBLY__
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 0399417e409..98217dd615f 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -70,4 +70,6 @@ static inline __attribute__((no_instrument_function)) uint64_t rdtsc(void)
 void timer_set_tsc_base(uint64_t new_base);
 uint64_t timer_get_tsc(void);
 
+void quick_ram_check(void);
+
 #endif	/* _U_BOOT_I386_H_ */
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 25b672a0c13..e146e646cdb 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o
 obj-$(CONFIG_PCI) += pci_type1.o
 obj-y	+= relocate.o
 obj-y += physmem.o
+obj-$(CONFIG_X86_RAMTEST) += ramtest.o
 obj-y	+= string.o
 obj-$(CONFIG_SYS_X86_TSC_TIMER)	+= tsc_timer.o
 obj-$(CONFIG_VIDEO_VGA)	+= video.o
diff --git a/arch/x86/lib/ramtest.c b/arch/x86/lib/ramtest.c
new file mode 100644
index 00000000000..c21be038486
--- /dev/null
+++ b/arch/x86/lib/ramtest.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * From Coreboot src/lib/ramtest.c
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/post.h>
+
+static void write_phys(unsigned long addr, u32 value)
+{
+#if CONFIG_SSE2
+	asm volatile(
+		"movnti %1, (%0)"
+		: /* outputs */
+		: "r" (addr), "r" (value) /* inputs */
+		: /* clobbers */
+		);
+#else
+	writel(value, addr);
+#endif
+}
+
+static u32 read_phys(unsigned long addr)
+{
+	return readl(addr);
+}
+
+static void phys_memory_barrier(void)
+{
+#if CONFIG_SSE2
+	/* Needed for movnti */
+	asm volatile(
+		"sfence"
+		:
+		:
+		: "memory"
+	);
+#else
+	asm volatile(""
+		:
+		:
+		: "memory");
+#endif
+}
+
+void quick_ram_check(void)
+{
+	int fail = 0;
+	u32 backup;
+
+	backup = read_phys(CONFIG_RAMBASE);
+	write_phys(CONFIG_RAMBASE, 0x55555555);
+	phys_memory_barrier();
+	if (read_phys(CONFIG_RAMBASE) != 0x55555555)
+		fail = 1;
+	write_phys(CONFIG_RAMBASE, 0xaaaaaaaa);
+	phys_memory_barrier();
+	if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa)
+		fail = 1;
+	write_phys(CONFIG_RAMBASE, 0x00000000);
+	phys_memory_barrier();
+	if (read_phys(CONFIG_RAMBASE) != 0x00000000)
+		fail = 1;
+	write_phys(CONFIG_RAMBASE, 0xffffffff);
+	phys_memory_barrier();
+	if (read_phys(CONFIG_RAMBASE) != 0xffffffff)
+		fail = 1;
+
+	write_phys(CONFIG_RAMBASE, backup);
+	if (fail) {
+		post_code(POST_RAM_FAILURE);
+		panic("RAM INIT FAILURE!\n");
+	}
+	phys_memory_barrier();
+}
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h
index 3063bd9a0f6..8caeca64307 100644
--- a/include/configs/chromebook_link.h
+++ b/include/configs/chromebook_link.h
@@ -18,12 +18,16 @@
 #define CONFIG_SYS_CAR_ADDR			0xff7e0000
 #define CONFIG_SYS_CAR_SIZE			(128 * 1024)
 #define CONFIG_SYS_MONITOR_LEN			(1 << 20)
+#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE		0x4000
 #define CONFIG_SYS_X86_START16			0xfffff800
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_DISPLAY_CPUINFO
 
 #define CONFIG_X86_RESET_VECTOR
 #define CONFIG_NR_DRAM_BANKS			8
+#define CONFIG_X86_MRC_START			0xfffa0000
+#define CONFIG_CACHE_MRC_SIZE_KB		512
 
 #define CONFIG_COREBOOT_SERIAL
 
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index 825e9f78426..f16ae329132 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -192,7 +192,7 @@
 #define CONFIG_SYS_STACK_SIZE			(32 * 1024)
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MALLOC_LEN			0x200000
-#define CONFIG_SYS_MALLOC_F_LEN			(1 << 10)
+#define CONFIG_SYS_MALLOC_F_LEN			(2 << 10)
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 3bd60b7f122..abfd678424b 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -119,6 +119,7 @@ enum fdt_compat_id {
 	COMPAT_PARADE_PS8625,		/* Parade PS8622 EDP->LVDS bridge */
 	COMPAT_INTEL_LPC,		/* Intel Low Pin Count I/F */
 	COMPAT_INTEL_MICROCODE,		/* Intel microcode update */
+	COMPAT_MEMORY_SPD,		/* Memory SPD information */
 
 	COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 9a68f9ca154..aafc4f93150 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -74,6 +74,7 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(PARADE_PS8625, "parade,ps8625"),
 	COMPAT(COMPAT_INTEL_LPC, "intel,lpc"),
 	COMPAT(INTEL_MICROCODE, "intel,microcode"),
+	COMPAT(MEMORY_SPD, "memory-spd"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
cgit v1.3.1