From 864aa6a6a466fcb92bf32b1d7dba79cd709b52c9 Mon Sep 17 00:00:00 2001 From: Grzegorz Wianecki Date: Sun, 29 Apr 2007 14:01:54 +0200 Subject: [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up message. Use PVR to distinguish between the two variants, and print proper CPU information. Signed-off-by: Grzegorz Wianecki Signed-off-by: Bartlomiej Sieka Signed-off-by: Grant Likely --- include/asm-ppc/processor.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 058596275f4..7c11c9e0231 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -701,8 +701,6 @@ #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ -/* System-On-Chip Version Numbers (version field only) */ -#define SVR_MPC5200 0x8011 /* Processor Version Register */ @@ -813,6 +811,12 @@ #define PVR_8260_HIP7R1 0x80822013 #define PVR_8260_HIP7RA 0x80822014 +/* + * MPC 52xx + */ +#define PVR_5200 0x80822011 +#define PVR_5200B 0x80822014 + /* * System Version Register -- cgit v1.3.1 From b0d8f5bf0d215adc9424cb228b2484dbf07f7761 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Wed, 9 May 2007 11:37:56 +0100 Subject: New board SMN42 branch --- MAKEALL | 2 +- Makefile | 5 +- board/lpc2292sodimm/Makefile | 35 ++--- board/lpc2292sodimm/flash.c | 240 ++------------------------------ common/soft_i2c.c | 3 + disk/part.c | 1 + drivers/Makefile | 2 +- fs/fat/fat.c | 7 +- include/asm-arm/arch-arm720t/hardware.h | 2 - include/configs/lpc2292sodimm.h | 14 +- 10 files changed, 43 insertions(+), 268 deletions(-) (limited to 'include') diff --git a/MAKEALL b/MAKEALL index d7cd8d74203..17ea97ea22b 100755 --- a/MAKEALL +++ b/MAKEALL @@ -185,7 +185,7 @@ LIST_SA="assabet dnp1110 gcplus lart shannon" LIST_ARM7=" \ armadillo B2 ep7312 evb4510 \ impa7 integratorap ap7 ap720t \ - lpc2292sodimm modnet50 \ + lpc2292sodimm modnet50 SMN42 \ " ######################################################################### diff --git a/Makefile b/Makefile index ceee2c7bed3..3e547fdb306 100755 --- a/Makefile +++ b/Makefile @@ -2100,7 +2100,10 @@ evb4510_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm720t evb4510 lpc2292sodimm_config: unconfig - @$(MKCONFIG) $(@:_config=) arm arm720t lpc2292sodimm + @$(MKCONFIG) $(@:_config=) arm arm720t lpc2292sodimm NULL lpc2292 + +SMN42_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm720t SMN42 siemens lpc2292 ######################################################################### ## XScale Systems diff --git a/board/lpc2292sodimm/Makefile b/board/lpc2292sodimm/Makefile index 5a30198e21a..18a95d7f9b8 100644 --- a/board/lpc2292sodimm/Makefile +++ b/board/lpc2292sodimm/Makefile @@ -1,7 +1,6 @@ # -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH -# Marius Groeger +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this # project. @@ -24,35 +23,29 @@ include $(TOPDIR)/config.mk -LIB = lib$(BOARD).a +LIB = $(obj)lib$(BOARD).a -OBJS := lpc2292sodimm.o flash.o mmc.o spi.o mmc_hw.o eth.o -SOBJS := lowlevel_init.o iap_entry.o +COBJS := flash.o lpc2292sodimm.o +SOBJTS := lowlevel_init.o -$(LIB): $(OBJS) $(SOBJS) - $(AR) crv $@ $(OBJS) $(SOBJS) +SRCS := $(SOBJTS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJTS)) -# this MUST be compiled as thumb code! -iap_entry.o: - arm-linux-gcc -D__ASSEMBLY__ -g -Os -fno-strict-aliasing \ - -fno-common -ffixed-r8 -msoft-float -D__KERNEL__ \ - -DTEXT_BASE=0x81500000 -I/home/garyj/proj/LPC/u-boot/include \ - -fno-builtin -ffreestanding -nostdinc -isystem \ - /opt/eldk/arm/usr/bin/../lib/gcc/arm-linux/4.0.0/include -pipe \ - -DCONFIG_ARM -D__ARM__ -march=armv4t -mtune=arm7tdmi -mabi=apcs-gnu \ - -c -o iap_entry.o iap_entry.S +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) clean: rm -f $(SOBJS) $(OBJS) distclean: clean - rm -f $(LIB) core *.bak .depend + rm -f $(LIB) core *.bak $(obj).depend ######################################################################### -.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) - $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ +# defines $(obj).depend target +include $(SRCTREE)/rules.mk --include .depend +sinclude $(obj).depend ######################################################################### diff --git a/board/lpc2292sodimm/flash.c b/board/lpc2292sodimm/flash.c index 55aaabfe6f6..0fb08430c53 100644 --- a/board/lpc2292sodimm/flash.c +++ b/board/lpc2292sodimm/flash.c @@ -1,6 +1,9 @@ /* * (C) Copyright 2006 Embedded Artists AB * + * Modified to use the routines in cpu/arm720t/lpc2292/flash.c by + * Gary Jennejohn + * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of @@ -20,84 +23,16 @@ #include #include -/* IAP commands use 32 bytes at the top of CPU internal sram, we - use 512 bytes below that */ -#define COPY_BUFFER_LOCATION 0x40003de0 - -#define IAP_LOCATION 0x7ffffff1 -#define IAP_CMD_PREPARE 50 -#define IAP_CMD_COPY 51 -#define IAP_CMD_ERASE 52 -#define IAP_CMD_CHECK 53 -#define IAP_CMD_ID 54 -#define IAP_CMD_VERSION 55 -#define IAP_CMD_COMPARE 56 - -#define IAP_RET_CMD_SUCCESS 0 - #define SST_BASEADDR 0x80000000 #define SST_ADDR1 ((volatile ushort*)(SST_BASEADDR + (0x5555 << 1))) #define SST_ADDR2 ((volatile ushort*)(SST_BASEADDR + (0x2AAA << 1))) -static unsigned long command[5]; -static unsigned long result[2]; - flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; -extern void iap_entry(unsigned long * command, unsigned long * result); - -/*----------------------------------------------------------------------- - * - */ -int get_flash_sector(flash_info_t * info, ulong flash_addr) -{ - int i; - - for(i=1; i < (info->sector_count); i++) { - if (flash_addr < (info->start[i])) - break; - } - - return (i-1); -} - -/*----------------------------------------------------------------------- - * This function assumes that flash_addr is aligned on 512 bytes boundary - * in flash. This function also assumes that prepare have been called - * for the sector in question. - */ -int copy_buffer_to_flash(flash_info_t * info, ulong flash_addr) -{ - int first_sector; - int last_sector; - - first_sector = get_flash_sector(info, flash_addr); - last_sector = get_flash_sector(info, flash_addr + 512 - 1); - - /* prepare sectors for write */ - command[0] = IAP_CMD_PREPARE; - command[1] = first_sector; - command[2] = last_sector; - iap_entry(command, result); - if (result[0] != IAP_RET_CMD_SUCCESS) { - printf("IAP prepare failed\n"); - return ERR_PROG_ERROR; - } - - command[0] = IAP_CMD_COPY; - command[1] = flash_addr; - command[2] = COPY_BUFFER_LOCATION; - command[3] = 512; - command[4] = CFG_SYS_CLK_FREQ >> 10; - iap_entry(command, result); - if (result[0] != IAP_RET_CMD_SUCCESS) { - printf("IAP copy failed\n"); - return 1; - } - - return 0; -} +extern int lpc2292_copy_buffer_to_flash(flash_info_t *, ulong); +extern int lpc2292_flash_erase(flash_info_t *, int, int); +extern int lpc2292_write_buff (flash_info_t *, uchar *, ulong, ulong); /*----------------------------------------------------------------------- * @@ -220,56 +155,6 @@ void flash_print_info (flash_info_t * info) printf ("\n"); } -/*----------------------------------------------------------------------- - */ - -int flash_erase_philips (flash_info_t * info, int s_first, int s_last) -{ - int flag; - int prot; - int sect; - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - - flag = disable_interrupts(); - - printf ("Erasing %d sectors starting at sector %2d.\n" - "This make take some time ... ", - s_last - s_first + 1, s_first); - - command[0] = IAP_CMD_PREPARE; - command[1] = s_first; - command[2] = s_last; - iap_entry(command, result); - if (result[0] != IAP_RET_CMD_SUCCESS) { - printf("IAP prepare failed\n"); - return ERR_PROTECTED; - } - - command[0] = IAP_CMD_ERASE; - command[1] = s_first; - command[2] = s_last; - command[3] = CFG_SYS_CLK_FREQ >> 10; - iap_entry(command, result); - if (result[0] != IAP_RET_CMD_SUCCESS) { - printf("IAP erase failed\n"); - return ERR_PROTECTED; - } - - if (flag) - enable_interrupts(); - - return ERR_OK; -} - int flash_erase_sst (flash_info_t * info, int s_first, int s_last) { int i; @@ -294,7 +179,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last) case (SST_MANUFACT & FLASH_VENDMASK): return flash_erase_sst(info, s_first, s_last); case (PHILIPS_LPC2292 & FLASH_VENDMASK): - return flash_erase_philips(info, s_first, s_last); + return lpc2292_flash_erase(info, s_first, s_last); default: return ERR_PROTECTED; } @@ -353,122 +238,13 @@ int write_buff_sst (flash_info_t * info, uchar * src, ulong addr, ulong cnt) return ret; } -int write_buff_philips (flash_info_t * info, - uchar * src, - ulong addr, - ulong cnt) -{ - int first_copy_size; - int last_copy_size; - int first_block; - int last_block; - int nbr_mid_blocks; - uchar memmap_value; - ulong i; - uchar* src_org; - uchar* dst_org; - int ret = ERR_OK; - - src_org = src; - dst_org = (uchar*)addr; - - first_block = addr / 512; - last_block = (addr + cnt) / 512; - nbr_mid_blocks = last_block - first_block - 1; - - first_copy_size = 512 - (addr % 512); - last_copy_size = (addr + cnt) % 512; - -#if 0 - printf("\ncopy first block: (1) %lX -> %lX 0x200 bytes, " - "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n", - (ulong)(first_block * 512), - (ulong)COPY_BUFFER_LOCATION, - (ulong)src, - (ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size), - first_copy_size, - (ulong)COPY_BUFFER_LOCATION, - (ulong)(first_block * 512)); -#endif - - /* copy first block */ - memcpy((void*)COPY_BUFFER_LOCATION, - (void*)(first_block * 512), 512); - memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size), - src, first_copy_size); - copy_buffer_to_flash(info, first_block * 512); - src += first_copy_size; - addr += first_copy_size; - - /* copy middle blocks */ - for (i = 0; i < nbr_mid_blocks; i++) { -#if 0 - printf("copy middle block: %lX -> %lX 512 bytes, " - "%lX -> %lX 512 bytes\n", - (ulong)src, - (ulong)COPY_BUFFER_LOCATION, - (ulong)COPY_BUFFER_LOCATION, - (ulong)addr); -#endif - memcpy((void*)COPY_BUFFER_LOCATION, src, 512); - copy_buffer_to_flash(info, addr); - src += 512; - addr += 512; - } - - - if (last_copy_size > 0) { -#if 0 - printf("copy last block: (1) %lX -> %lX 0x200 bytes, " - "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n", - (ulong)(last_block * 512), - (ulong)COPY_BUFFER_LOCATION, - (ulong)src, - (ulong)(COPY_BUFFER_LOCATION), - last_copy_size, - (ulong)COPY_BUFFER_LOCATION, - (ulong)addr); -#endif - /* copy last block */ - memcpy((void*)COPY_BUFFER_LOCATION, - (void*)(last_block * 512), 512); - memcpy((void*)COPY_BUFFER_LOCATION, - src, last_copy_size); - copy_buffer_to_flash(info, addr); - } - - /* verify write */ - memmap_value = GET8(MEMMAP); - - disable_interrupts(); - - PUT8(MEMMAP, 01); /* we must make sure that initial 64 - bytes are taken from flash when we - do the compare */ - - for (i = 0; i < cnt; i++) { - if (*dst_org != *src_org){ - printf("Write failed. Byte %lX differs\n", i); - ret = ERR_PROG_ERROR; - break; - } - dst_org++; - src_org++; - } - - PUT8(MEMMAP, memmap_value); - enable_interrupts(); - - return ret; -} - int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) { switch (info->flash_id & FLASH_VENDMASK) { case (SST_MANUFACT & FLASH_VENDMASK): return write_buff_sst(info, src, addr, cnt); case (PHILIPS_LPC2292 & FLASH_VENDMASK): - return write_buff_philips(info, src, addr, cnt); + return lpc2292_write_buff(info, src, addr, cnt); default: return ERR_PROG_ERROR; } diff --git a/common/soft_i2c.c b/common/soft_i2c.c index edad51bc418..0f6e3a938d2 100644 --- a/common/soft_i2c.c +++ b/common/soft_i2c.c @@ -36,6 +36,9 @@ #ifdef CONFIG_IXP425 /* only valid for IXP425 */ #include #endif +#ifdef CONFIG_LPC2292 +#include +#endif #include #if defined(CONFIG_SOFT_I2C) diff --git a/disk/part.c b/disk/part.c index acc1a748e44..54de737c3ba 100644 --- a/disk/part.c +++ b/disk/part.c @@ -180,6 +180,7 @@ void dev_print (block_dev_desc_t *dev_desc) (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ (CONFIG_COMMANDS & CFG_CMD_USB) || \ defined(CONFIG_MMC) || \ + (defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \ defined(CONFIG_SYSTEMACE) ) #if defined(CONFIG_MAC_PARTITION) || \ diff --git a/drivers/Makefile b/drivers/Makefile index d68cba682be..c7fcc3f23e5 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -30,7 +30,7 @@ LIB = $(obj)libdrivers.a COBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \ bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \ cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ - e1000.o eepro100.o \ + e1000.o eepro100.o enc28j60.o \ i8042.o inca-ip_sw.o keyboard.o \ lan91c96.o macb.o \ natsemi.o ne2000.o netarm_eth.o netconsole.o \ diff --git a/fs/fat/fat.c b/fs/fat/fat.c index a823b5aba40..084ee44459e 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -89,8 +89,11 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no) part_offset=0; } else { -#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ - (CONFIG_COMMANDS & CFG_CMD_USB) || defined(CONFIG_SYSTEMACE) +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ + (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ + (CONFIG_COMMANDS & CFG_CMD_USB) || \ + (defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \ + defined(CONFIG_SYSTEMACE) ) disk_partition_t info; if(!get_partition_info(dev_desc, part_no, &info)) { part_offset = info.start; diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h index 1e9cd41169d..3056ca7f673 100644 --- a/include/asm-arm/arch-arm720t/hardware.h +++ b/include/asm-arm/arch-arm720t/hardware.h @@ -36,8 +36,6 @@ /* include armadillo specific hardware file if there was one */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* include IntegratorCP/CM720T specific hardware file if there was one */ -#elif defined(CONFIG_LPC2292) -#include #else #error No hardware file defined for this configuration #endif diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h index 7e515230a33..d817ea8d736 100644 --- a/include/configs/lpc2292sodimm.h +++ b/include/configs/lpc2292sodimm.h @@ -1,12 +1,8 @@ /* - * (C) Copyright 2000 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Configuation settings for the EP7312 board. - * - * Modified to work on Armadillo HT1070 ARM720T board - * (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com + * Configuation settings for the LPC2292SODIMM board from Embedded Artists. * * See file CREDITS for list of people who contributed to this * project. @@ -31,7 +27,7 @@ #define __CONFIG_H /* - * If we are developing, we might want to start armboot from ram + * If we are developing, we might want to start u-boot from ram * so we MUST NOT initialize critical regs like mem-timing ... */ #undef CONFIG_INIT_CRITICAL /* undef for developing */ @@ -154,5 +150,7 @@ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG #define CONFIG_MMC 1 +/* we use this ethernet chip */ +#define CONFIG_ENC28J60 #endif /* __CONFIG_H */ -- cgit v1.3.1 From 5c6d2b5a500f8c49670de8910150b78a41f781fc Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Wed, 9 May 2007 11:40:34 +0100 Subject: Remove the deleted files for the SMN42 patch --- board/lpc2292sodimm/eth.c | 885 ----------------------- board/lpc2292sodimm/iap_entry.S | 7 - board/lpc2292sodimm/mmc.c | 154 ---- board/lpc2292sodimm/mmc_hw.c | 233 ------ board/lpc2292sodimm/mmc_hw.h | 29 - board/lpc2292sodimm/spi.c | 40 - board/lpc2292sodimm/spi.h | 82 --- include/asm-arm/arch-arm720t/lpc2292_registers.h | 225 ------ include/asm-arm/arch-arm720t/mmc.h | 22 - 9 files changed, 1677 deletions(-) delete mode 100644 board/lpc2292sodimm/eth.c delete mode 100644 board/lpc2292sodimm/iap_entry.S delete mode 100644 board/lpc2292sodimm/mmc.c delete mode 100644 board/lpc2292sodimm/mmc_hw.c delete mode 100644 board/lpc2292sodimm/mmc_hw.h delete mode 100644 board/lpc2292sodimm/spi.c delete mode 100644 board/lpc2292sodimm/spi.h delete mode 100644 include/asm-arm/arch-arm720t/lpc2292_registers.h delete mode 100644 include/asm-arm/arch-arm720t/mmc.h (limited to 'include') diff --git a/board/lpc2292sodimm/eth.c b/board/lpc2292sodimm/eth.c deleted file mode 100644 index 249ab043934..00000000000 --- a/board/lpc2292sodimm/eth.c +++ /dev/null @@ -1,885 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include "spi.h" - -/* - * Control Registers in Bank 0 - */ - -#define CTL_REG_ERDPTL 0x00 -#define CTL_REG_ERDPTH 0x01 -#define CTL_REG_EWRPTL 0x02 -#define CTL_REG_EWRPTH 0x03 -#define CTL_REG_ETXSTL 0x04 -#define CTL_REG_ETXSTH 0x05 -#define CTL_REG_ETXNDL 0x06 -#define CTL_REG_ETXNDH 0x07 -#define CTL_REG_ERXSTL 0x08 -#define CTL_REG_ERXSTH 0x09 -#define CTL_REG_ERXNDL 0x0A -#define CTL_REG_ERXNDA 0x0B -#define CTL_REG_ERXRDPTL 0x0C -#define CTL_REG_ERXRDPTH 0x0D -#define CTL_REG_ERXWRPTL 0x0E -#define CTL_REG_ERXWRPTH 0x0F -#define CTL_REG_EDMASTL 0x10 -#define CTL_REG_EDMASTH 0x11 -#define CTL_REG_EDMANDL 0x12 -#define CTL_REG_EDMANDH 0x13 -#define CTL_REG_EDMADSTL 0x14 -#define CTL_REG_EDMADSTH 0x15 -#define CTL_REG_EDMACSL 0x16 -#define CTL_REG_EDMACSH 0x17 -/* these are common in all banks */ -#define CTL_REG_EIE 0x1B -#define CTL_REG_EIR 0x1C -#define CTL_REG_ESTAT 0x1D -#define CTL_REG_ECON2 0x1E -#define CTL_REG_ECON1 0x1F - -/* - * Control Registers in Bank 1 - */ - -#define CTL_REG_EHT0 0x00 -#define CTL_REG_EHT1 0x01 -#define CTL_REG_EHT2 0x02 -#define CTL_REG_EHT3 0x03 -#define CTL_REG_EHT4 0x04 -#define CTL_REG_EHT5 0x05 -#define CTL_REG_EHT6 0x06 -#define CTL_REG_EHT7 0x07 -#define CTL_REG_EPMM0 0x08 -#define CTL_REG_EPMM1 0x09 -#define CTL_REG_EPMM2 0x0A -#define CTL_REG_EPMM3 0x0B -#define CTL_REG_EPMM4 0x0C -#define CTL_REG_EPMM5 0x0D -#define CTL_REG_EPMM6 0x0E -#define CTL_REG_EPMM7 0x0F -#define CTL_REG_EPMCSL 0x10 -#define CTL_REG_EPMCSH 0x11 -#define CTL_REG_EPMOL 0x14 -#define CTL_REG_EPMOH 0x15 -#define CTL_REG_EWOLIE 0x16 -#define CTL_REG_EWOLIR 0x17 -#define CTL_REG_ERXFCON 0x18 -#define CTL_REG_EPKTCNT 0x19 - -/* - * Control Registers in Bank 2 - */ - -#define CTL_REG_MACON1 0x00 -#define CTL_REG_MACON2 0x01 -#define CTL_REG_MACON3 0x02 -#define CTL_REG_MACON4 0x03 -#define CTL_REG_MABBIPG 0x04 -#define CTL_REG_MAIPGL 0x06 -#define CTL_REG_MAIPGH 0x07 -#define CTL_REG_MACLCON1 0x08 -#define CTL_REG_MACLCON2 0x09 -#define CTL_REG_MAMXFLL 0x0A -#define CTL_REG_MAMXFLH 0x0B -#define CTL_REG_MAPHSUP 0x0D -#define CTL_REG_MICON 0x11 -#define CTL_REG_MICMD 0x12 -#define CTL_REG_MIREGADR 0x14 -#define CTL_REG_MIWRL 0x16 -#define CTL_REG_MIWRH 0x17 -#define CTL_REG_MIRDL 0x18 -#define CTL_REG_MIRDH 0x19 - -/* - * Control Registers in Bank 3 - */ - -#define CTL_REG_MAADR1 0x00 -#define CTL_REG_MAADR0 0x01 -#define CTL_REG_MAADR3 0x02 -#define CTL_REG_MAADR2 0x03 -#define CTL_REG_MAADR5 0x04 -#define CTL_REG_MAADR4 0x05 -#define CTL_REG_EBSTSD 0x06 -#define CTL_REG_EBSTCON 0x07 -#define CTL_REG_EBSTCSL 0x08 -#define CTL_REG_EBSTCSH 0x09 -#define CTL_REG_MISTAT 0x0A -#define CTL_REG_EREVID 0x12 -#define CTL_REG_ECOCON 0x15 -#define CTL_REG_EFLOCON 0x17 -#define CTL_REG_EPAUSL 0x18 -#define CTL_REG_EPAUSH 0x19 - - -/* - * PHY Register - */ - -#define PHY_REG_PHID1 0x02 -#define PHY_REG_PHID2 0x03 - - -/* - * Receive Filter Register (ERXFCON) bits - */ - -#define ENC_RFR_UCEN 0x80 -#define ENC_RFR_ANDOR 0x40 -#define ENC_RFR_CRCEN 0x20 -#define ENC_RFR_PMEN 0x10 -#define ENC_RFR_MPEN 0x08 -#define ENC_RFR_HTEN 0x04 -#define ENC_RFR_MCEN 0x02 -#define ENC_RFR_BCEN 0x01 - -/* - * ECON1 Register Bits - */ - -#define ENC_ECON1_TXRST 0x80 -#define ENC_ECON1_RXRST 0x40 -#define ENC_ECON1_DMAST 0x20 -#define ENC_ECON1_CSUMEN 0x10 -#define ENC_ECON1_TXRTS 0x08 -#define ENC_ECON1_RXEN 0x04 -#define ENC_ECON1_BSEL1 0x02 -#define ENC_ECON1_BSEL0 0x01 - -/* - * ECON2 Register Bits - */ -#define ENC_ECON2_AUTOINC 0x80 -#define ENC_ECON2_PKTDEC 0x40 -#define ENC_ECON2_PWRSV 0x20 -#define ENC_ECON2_VRPS 0x08 - -/* - * EIR Register Bits - */ -#define ENC_EIR_PKTIF 0x40 -#define ENC_EIR_DMAIF 0x20 -#define ENC_EIR_LINKIF 0x10 -#define ENC_EIR_TXIF 0x08 -#define ENC_EIR_WOLIF 0x04 -#define ENC_EIR_TXERIF 0x02 -#define ENC_EIR_RXERIF 0x01 - -/* - * ESTAT Register Bits - */ - -#define ENC_ESTAT_INT 0x80 -#define ENC_ESTAT_LATECOL 0x10 -#define ENC_ESTAT_RXBUSY 0x04 -#define ENC_ESTAT_TXABRT 0x02 -#define ENC_ESTAT_CLKRDY 0x01 - -/* - * EIE Register Bits - */ - -#define ENC_EIE_INTIE 0x80 -#define ENC_EIE_PKTIE 0x40 -#define ENC_EIE_DMAIE 0x20 -#define ENC_EIE_LINKIE 0x10 -#define ENC_EIE_TXIE 0x08 -#define ENC_EIE_WOLIE 0x04 -#define ENC_EIE_TXERIE 0x02 -#define ENC_EIE_RXERIE 0x01 - -/* - * MACON1 Register Bits - */ -#define ENC_MACON1_LOOPBK 0x10 -#define ENC_MACON1_TXPAUS 0x08 -#define ENC_MACON1_RXPAUS 0x04 -#define ENC_MACON1_PASSALL 0x02 -#define ENC_MACON1_MARXEN 0x01 - - -/* - * MACON2 Register Bits - */ -#define ENC_MACON2_MARST 0x80 -#define ENC_MACON2_RNDRST 0x40 -#define ENC_MACON2_MARXRST 0x08 -#define ENC_MACON2_RFUNRST 0x04 -#define ENC_MACON2_MATXRST 0x02 -#define ENC_MACON2_TFUNRST 0x01 - -/* - * MACON3 Register Bits - */ -#define ENC_MACON3_PADCFG2 0x80 -#define ENC_MACON3_PADCFG1 0x40 -#define ENC_MACON3_PADCFG0 0x20 -#define ENC_MACON3_TXCRCEN 0x10 -#define ENC_MACON3_PHDRLEN 0x08 -#define ENC_MACON3_HFRMEN 0x04 -#define ENC_MACON3_FRMLNEN 0x02 -#define ENC_MACON3_FULDPX 0x01 - -/* - * MICMD Register Bits - */ -#define ENC_MICMD_MIISCAN 0x02 -#define ENC_MICMD_MIIRD 0x01 - -/* - * MISTAT Register Bits - */ -#define ENC_MISTAT_NVALID 0x04 -#define ENC_MISTAT_SCAN 0x02 -#define ENC_MISTAT_BUSY 0x01 - -/* - * PHID1 and PHID2 values - */ -#define ENC_PHID1_VALUE 0x0083 -#define ENC_PHID2_VALUE 0x1400 -#define ENC_PHID2_MASK 0xFC00 - - -#define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */ -#define ENC_RESET 0x00020000 /* pin P1.17 */ - -#define FAILSAFE_VALUE 5000 - -/* - * Controller memory layout: - * - * 0x0000 - 0x17ff 6k bytes receive buffer - * 0x1800 - 0x1fff 2k bytes transmit buffer - */ -/* Use the lower memory for receiver buffer. See errata pt. 5 */ -#define ENC_RX_BUF_START 0x0000 -#define ENC_TX_BUF_START 0x1800 - -/* maximum frame length */ -#define ENC_MAX_FRM_LEN 1518 - -#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS) -#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS) -#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8); - - -static unsigned char encReadReg (unsigned char regNo); -static void encWriteReg (unsigned char regNo, unsigned char data); -static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c); -static void encReadBuff (unsigned short length, unsigned char *pBuff); -static void encWriteBuff (unsigned short length, unsigned char *pBuff); -static void encBitSet (unsigned char regNo, unsigned char data); -static void encBitClr (unsigned char regNo, unsigned char data); -static void encReset (void); -static void encInit (unsigned char *pEthAddr); -static unsigned short phyRead (unsigned char addr); -static void encPoll (void); -static void encRx (void); - -#define m_nic_read(reg) encReadReg(reg) -#define m_nic_write(reg, data) encWriteReg(reg, data) -#define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count) -#define m_nic_read_data(len, buf) encReadBuff((len), (buf)) -#define m_nic_write_data(len, buf) encWriteBuff((len), (buf)) - -/* bit field set */ -#define m_nic_bfs(reg, data) encBitSet(reg, data) - -/* bit field clear */ -#define m_nic_bfc(reg, data) encBitClr(reg, data) - -static unsigned char bank = 0; /* current bank in enc28j60 */ -static unsigned char next_pointer_lsb; -static unsigned char next_pointer_msb; - -static unsigned char buffer[ENC_MAX_FRM_LEN]; -static int rxResetCounter = 0; - -#define RX_RESET_COUNTER 1000; - -/*----------------------------------------------------------------------------- - * Returns 0 when failes otherwize 1 - */ -int eth_init (bd_t * bis) -{ - /* configure GPIO */ - (*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS; - (*((volatile unsigned long *) IO1DIR)) |= ENC_RESET; - - /* CS and RESET active low */ - PUT32 (IO1SET, ENC_SPI_SLAVE_CS); - PUT32 (IO1SET, ENC_RESET); - - spi_init (); - - /* initialize controller */ - encReset (); - encInit (bis->bi_enetaddr); - - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */ - - return 0; -} - -int eth_send (volatile void *packet, int length) -{ - /* check frame length, etc. */ - /* TODO: */ - - /* switch to bank 0 */ - m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); - - /* set EWRPT */ - m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff)); - m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8)); - - /* set ETXST */ - m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF); - m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8); - - /* write packet */ - m_nic_write_data (length, (unsigned char *) packet); - - /* set ETXND */ - m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF); - m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8); - - /* set ECON1.TXRTS */ - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS); - - return 0; -} - - -/***************************************************************************** - * This function resets the receiver only. This function may be called from - * interrupt-context. - */ -static void encReceiverReset (void) -{ - unsigned char econ1; - - econ1 = m_nic_read (CTL_REG_ECON1); - if ((econ1 & ENC_ECON1_RXRST) == 0) { - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST); - rxResetCounter = RX_RESET_COUNTER; - } -} - -/***************************************************************************** - * receiver reset timer - */ -static void encReceiverResetCallback (void) -{ - m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST); - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */ -} - -/*----------------------------------------------------------------------------- - * Check for received packets. Call NetReceive for each packet. The return - * value is ignored by the caller. - */ -int eth_rx (void) -{ - if (rxResetCounter > 0 && --rxResetCounter == 0) { - encReceiverResetCallback (); - } - - encPoll (); - - return 0; -} - -void eth_halt (void) -{ - m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */ -} - -/*****************************************************************************/ - -static void encPoll (void) -{ - unsigned char eir_reg; - volatile unsigned char estat_reg; - unsigned char pkt_cnt; - - /* clear global interrupt enable bit in enc28j60 */ - m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE); - estat_reg = m_nic_read (CTL_REG_ESTAT); - - eir_reg = m_nic_read (CTL_REG_EIR); - - if (eir_reg & ENC_EIR_TXIF) { - /* clear TXIF bit in EIR */ - m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF); - } - - /* We have to use pktcnt and not pktif bit, see errata pt. 6 */ - - /* move to bank 1 */ - m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1); - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0); - - /* read pktcnt */ - pkt_cnt = m_nic_read (CTL_REG_EPKTCNT); - - if (pkt_cnt > 0) { - if ((eir_reg & ENC_EIR_PKTIF) == 0) { - /*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */ - } - encRx (); - /* clear PKTIF bit in EIR, this should not need to be done but it - seems like we get problems if we do not */ - m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF); - } - - if (eir_reg & ENC_EIR_RXERIF) { - printf ("encPoll: rx error\n"); - m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF); - } - if (eir_reg & ENC_EIR_TXERIF) { - printf ("encPoll: tx error\n"); - m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF); - } - - /* set global interrupt enable bit in enc28j60 */ - m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE); -} - -static void encRx (void) -{ - unsigned short pkt_len; - unsigned short copy_len; - unsigned short status; - unsigned char eir_reg; - unsigned char pkt_cnt = 0; - - /* switch to bank 0 */ - m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); - - m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb); - m_nic_write (CTL_REG_ERDPTH, next_pointer_msb); - - do { - m_nic_read_data (6, buffer); - next_pointer_lsb = buffer[0]; - next_pointer_msb = buffer[1]; - pkt_len = buffer[2]; - pkt_len |= (unsigned short) buffer[3] << 8; - status = buffer[4]; - status |= (unsigned short) buffer[5] << 8; - - if (pkt_len <= ENC_MAX_FRM_LEN) { - copy_len = pkt_len; - } else { - copy_len = 0; - /* p_priv->stats.rx_dropped++; */ - /* we will drop this packet */ - } - - if ((status & (1L << 7)) == 0) { /* check Received Ok bit */ - copy_len = 0; - /* p_priv->stats.rx_errors++; */ - } - - if (copy_len > 0) { - m_nic_read_data (copy_len, buffer); - } - - /* advance read pointer to next pointer */ - m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb); - m_nic_write (CTL_REG_ERDPTH, next_pointer_msb); - - /* decrease packet counter */ - m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC); - - /* move to bank 1 */ - m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1); - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0); - - /* read pktcnt */ - pkt_cnt = m_nic_read (CTL_REG_EPKTCNT); - - /* switch to bank 0 */ - m_nic_bfc (CTL_REG_ECON1, - (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); - - if (copy_len == 0) { - eir_reg = m_nic_read (CTL_REG_EIR); - encReceiverReset (); - printf ("eth_rx: copy_len=0\n"); - continue; - } - - NetReceive ((unsigned char *) buffer, pkt_len); - - eir_reg = m_nic_read (CTL_REG_EIR); - } while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */ - m_nic_write (CTL_REG_ERXRDPTL, next_pointer_lsb); - m_nic_write (CTL_REG_ERXRDPTH, next_pointer_msb); -} - -static void encWriteReg (unsigned char regNo, unsigned char data) -{ - spi_lock (); - enc_cfg_spi (); - enc_enable (); - - spi_write (0x40 | regNo); /* write in regNo */ - spi_write (data); - - enc_disable (); - enc_enable (); - - spi_write (0x1f); /* write reg 0x1f */ - - enc_disable (); - spi_unlock (); -} - -static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c) -{ - unsigned char readback; - int i; - - spi_lock (); - - for (i = 0; i < c; i++) { - enc_cfg_spi (); - enc_enable (); - - spi_write (0x40 | regNo); /* write in regNo */ - spi_write (data); - - enc_disable (); - enc_enable (); - - spi_write (0x1f); /* write reg 0x1f */ - - enc_disable (); - - spi_unlock (); /* we must unlock spi first */ - - readback = encReadReg (regNo); - - spi_lock (); - - if (readback == data) - break; - } - spi_unlock (); - - if (i == c) { - printf ("enc28j60: write reg %d failed\n", regNo); - } -} - -static unsigned char encReadReg (unsigned char regNo) -{ - unsigned char rxByte; - - spi_lock (); - enc_cfg_spi (); - enc_enable (); - - spi_write (0x1f); /* read reg 0x1f */ - - bank = spi_read () & 0x3; - - enc_disable (); - enc_enable (); - - spi_write (regNo); - rxByte = spi_read (); - - /* check if MAC or MII register */ - if (((bank == 2) && (regNo <= 0x1a)) || - ((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) { - /* ignore first byte and read another byte */ - rxByte = spi_read (); - } - - enc_disable (); - spi_unlock (); - - return rxByte; -} - -static void encReadBuff (unsigned short length, unsigned char *pBuff) -{ - spi_lock (); - enc_cfg_spi (); - enc_enable (); - - spi_write (0x20 | 0x1a); /* read buffer memory */ - - while (length--) { - if (pBuff != NULL) - *pBuff++ = spi_read (); - else - spi_write (0); - } - - enc_disable (); - spi_unlock (); -} - -static void encWriteBuff (unsigned short length, unsigned char *pBuff) -{ - spi_lock (); - enc_cfg_spi (); - enc_enable (); - - spi_write (0x60 | 0x1a); /* write buffer memory */ - - spi_write (0x00); /* control byte */ - - while (length--) - spi_write (*pBuff++); - - enc_disable (); - spi_unlock (); -} - -static void encBitSet (unsigned char regNo, unsigned char data) -{ - spi_lock (); - enc_cfg_spi (); - enc_enable (); - - spi_write (0x80 | regNo); /* bit field set */ - spi_write (data); - - enc_disable (); - spi_unlock (); -} - -static void encBitClr (unsigned char regNo, unsigned char data) -{ - spi_lock (); - enc_cfg_spi (); - enc_enable (); - - spi_write (0xA0 | regNo); /* bit field clear */ - spi_write (data); - - enc_disable (); - spi_unlock (); -} - -static void encReset (void) -{ - spi_lock (); - enc_cfg_spi (); - enc_enable (); - - spi_write (0xff); /* soft reset */ - - enc_disable (); - spi_unlock (); - - /* sleep 1 ms. See errata pt. 2 */ - udelay (1000); - -#if 0 - (*((volatile unsigned long *) IO1CLR)) &= ENC_RESET; - mdelay (5); - (*((volatile unsigned long *) IO1SET)) &= ENC_RESET; -#endif -} - -static void encInit (unsigned char *pEthAddr) -{ - unsigned short phid1 = 0; - unsigned short phid2 = 0; - - /* switch to bank 0 */ - m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); - - /* - * Setup the buffer space. The reset values are valid for the - * other pointers. - */ -#if 0 - /* We shall not write to ERXST, see errata pt. 5. Instead we - have to make sure that ENC_RX_BUS_START is 0. */ - m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1); - m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1); -#endif - m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1); - m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1); - - next_pointer_lsb = (ENC_RX_BUF_START & 0xFF); - next_pointer_msb = (ENC_RX_BUF_START >> 8); - - /* - * For tracking purposes, the ERXRDPT registers should be programmed with - * the same value. This is the read pointer. - */ - m_nic_write (CTL_REG_ERXRDPTL, (ENC_RX_BUF_START & 0xFF)); - m_nic_write_retry (CTL_REG_ERXRDPTH, (ENC_RX_BUF_START >> 8), 1); - - /* Setup receive filters. */ - - /* move to bank 1 */ - m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1); - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0); - - /* OR-filtering, Unicast, CRC-check and broadcast */ - m_nic_write_retry (CTL_REG_ERXFCON, - (ENC_RFR_UCEN | ENC_RFR_CRCEN | ENC_RFR_BCEN), 1); - - /* Wait for Oscillator Start-up Timer (OST). */ - while ((m_nic_read (CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) == 0) { - static int cnt = 0; - - if (cnt++ >= 1000) { - cnt = 0; - } - } - - /* verify identification */ - phid1 = phyRead (PHY_REG_PHID1); - phid2 = phyRead (PHY_REG_PHID2); - - if (phid1 != ENC_PHID1_VALUE - || (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) { - printf ("ERROR: failed to identify controller\n"); - printf ("phid1 = %x, phid2 = %x\n", - phid1, (phid2 & ENC_PHID2_MASK)); - printf ("should be phid1 = %x, phid2 = %x\n", - ENC_PHID1_VALUE, ENC_PHID2_VALUE); - } - - /* - * --- MAC Initialization --- - */ - - /* Pull MAC out of Reset */ - - /* switch to bank 2 */ - m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0); - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1); - /* clear MAC reset bits */ - m_nic_write_retry (CTL_REG_MACON2, 0, 1); - - /* enable MAC to receive frames */ - m_nic_write_retry (CTL_REG_MACON1, ENC_MACON1_MARXEN, 10); - - /* configure pad, tx-crc and duplex */ - /* TODO maybe enable FRMLNEN */ - m_nic_write_retry (CTL_REG_MACON3, - (ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN), 10); - - /* set maximum frame length */ - m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10); - m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10); - - /* - * Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex - * and 0x15 for full duplex. - */ - m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10); - - /* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */ - m_nic_write_retry (CTL_REG_MAIPGL, 0x12, 10); - - /* - * Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended - * 0x0c for half-duplex. Nothing for full-duplex - */ - m_nic_write_retry (CTL_REG_MAIPGH, 0x0C, 10); - - /* set MAC address */ - - /* switch to bank 3 */ - m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1)); - - m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1); - m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1); - m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1); - m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1); - m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1); - m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1); - - /* - * Receive settings - */ - - /* auto-increment RX-pointer when reading a received packet */ - m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_AUTOINC); - - /* enable interrupts */ - m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE); - m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE); - m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE); - m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE); - m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE); -} - -/***************************************************************************** - * - * Description: - * Read PHY registers. - * - * NOTE! This function will change to Bank 2. - * - * Params: - * [in] addr address of the register to read - * - * Returns: - * The value in the register - */ -static unsigned short phyRead (unsigned char addr) -{ - unsigned short ret = 0; - - /* move to bank 2 */ - m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0); - m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1); - - /* write address to MIREGADR */ - m_nic_write (CTL_REG_MIREGADR, addr); - - /* set MICMD.MIIRD */ - m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD); - - /* poll MISTAT.BUSY bit until operation is complete */ - while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) { - static int cnt = 0; - - if (cnt++ >= 1000) { - /* GJ - this seems extremely dangerous! */ - /* printf("#"); */ - cnt = 0; - } - } - - /* clear MICMD.MIIRD */ - m_nic_write (CTL_REG_MICMD, 0); - - ret = (m_nic_read (CTL_REG_MIRDH) << 8); - ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF); - - return ret; -} diff --git a/board/lpc2292sodimm/iap_entry.S b/board/lpc2292sodimm/iap_entry.S deleted file mode 100644 index c31d5190bd7..00000000000 --- a/board/lpc2292sodimm/iap_entry.S +++ /dev/null @@ -1,7 +0,0 @@ -IAP_ADDRESS: .word 0x7FFFFFF1 - -.globl iap_entry -iap_entry: - ldr r2, IAP_ADDRESS - bx r2 - mov pc, lr diff --git a/board/lpc2292sodimm/mmc.c b/board/lpc2292sodimm/mmc.c deleted file mode 100644 index 1c0922f2405..00000000000 --- a/board/lpc2292sodimm/mmc.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include "mmc_hw.h" -#include "spi.h" - -#ifdef CONFIG_MMC - -#undef MMC_DEBUG - -static block_dev_desc_t mmc_dev; - -/* these are filled out by a call to mmc_hw_get_parameters */ -static int hw_size; /* in kbytes */ -static int hw_nr_sects; -static int hw_sect_size; /* in bytes */ - -block_dev_desc_t * mmc_get_dev(int dev) -{ - return (block_dev_desc_t *)(&mmc_dev); -} - -unsigned long mmc_block_read(int dev, - unsigned long start, - lbaint_t blkcnt, - unsigned long *buffer) -{ - unsigned long rc = 0; - unsigned char *p = (unsigned char *)buffer; - unsigned long i; - unsigned long addr = start; - -#ifdef MMC_DEBUG - printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start, - (unsigned long)blkcnt); -#endif - - for(i = 0; i < (unsigned long)blkcnt; i++) { -#ifdef MMC_DEBUG - printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p); -#endif - (void)mmc_read_sector(addr, p); - rc++; - addr++; - p += hw_sect_size; - } - - return rc; -} - -/*----------------------------------------------------------------------------- - * Read hardware paramterers (sector size, size, number of sectors) - */ -static int mmc_hw_get_parameters(void) -{ - unsigned char csddata[16]; - unsigned int sizemult; - unsigned int size; - - mmc_read_csd(csddata); - hw_sect_size = 1<<(csddata[5] & 0x0f); - size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0); - sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1); - hw_nr_sects = (size+1)*(1<<(sizemult+2)); - hw_size = hw_nr_sects*hw_sect_size/1024; - -#ifdef MMC_DEBUG - printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, " - "hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size); -#endif - - return 0; -} - -int mmc_init(int verbose) -{ - int ret = -ENODEV; - - if (verbose) - printf("mmc_init\n"); - - spi_init(); - mmc_hw_init(); - - mmc_hw_get_parameters(); - - mmc_dev.if_type = IF_TYPE_MMC; - mmc_dev.part_type = PART_TYPE_DOS; - mmc_dev.dev = 0; - mmc_dev.lun = 0; - mmc_dev.type = 0; - mmc_dev.blksz = hw_sect_size; - mmc_dev.lba = hw_nr_sects; - sprintf((char*)mmc_dev.vendor, "Unknown vendor"); - sprintf((char*)mmc_dev.product, "Unknown product"); - sprintf((char*)mmc_dev.revision, "N/A"); - mmc_dev.removable = 0; /* should be true??? */ - mmc_dev.block_read = mmc_block_read; - - fat_register_device(&mmc_dev, 1); - - ret = 0; - - return ret; -} - -int mmc_write(uchar * src, ulong dst, int size) -{ -#ifdef MMC_DEBUG - printf("mmc_write: src=%p, dst=%lu, size=%u\n", src, dst, size); -#endif - /* Since mmc2info always returns 0 this function will never be called */ - return 0; -} - -int mmc_read(ulong src, uchar * dst, int size) -{ -#ifdef MMC_DEBUG - printf("mmc_read: src=%lu, dst=%p, size=%u\n", src, dst, size); -#endif - /* Since mmc2info always returns 0 this function will never be called */ - return 0; -} - -int mmc2info(ulong addr) -{ - /* This function is used by cmd_cp to determine if source or destination - address resides on MMC-card or not. We do not support copy to and from - MMC-card so we always return 0. */ - return 0; -} - -#endif /* CONFIG_MMC */ diff --git a/board/lpc2292sodimm/mmc_hw.c b/board/lpc2292sodimm/mmc_hw.c deleted file mode 100644 index 31f2a7988da..00000000000 --- a/board/lpc2292sodimm/mmc_hw.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - This code was original written by Ulrich Radig and modified by - Embedded Artists AB (www.embeddedartists.com). - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include -#include -#include -#include "spi.h" - -#define MMC_Enable() PUT32(IO1CLR, 1l << 22) -#define MMC_Disable() PUT32(IO1SET, 1l << 22) -#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0); - -static unsigned char Write_Command_MMC (unsigned char *CMD); -static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, - unsigned short int Bytes); - -/* initialize the hardware */ -int mmc_hw_init(void) -{ - unsigned long a; - unsigned short int Timeout = 0; - unsigned char b; - unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95}; - - /* set-up GPIO and SPI */ - (*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */ - (*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */ - - MMC_Disable(); - - spi_lock(); - spi_set_clock(248); - spi_set_cfg(0, 1, 0); - MMC_Enable(); - - /* waste some time */ - for(a=0; a < 20000; a++) - asm("nop"); - - /* Put the MMC/SD-card into SPI-mode */ - for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */ - spi_write(0xff); - - /* Sends command CMD0 to MMC/SD-card */ - while (Write_Command_MMC(CMD) != 1) { - if (Timeout++ > 200) { - MMC_Disable(); - spi_unlock(); - return(1); /* Abort with command 1 (return 1) */ - } - } - /* Sends Command CMD1 an MMC/SD-card */ - Timeout = 0; - CMD[0] = 0x41;/* Command 1 */ - CMD[5] = 0xFF; - - while (Write_Command_MMC(CMD) != 0) { - if (Timeout++ > 200) { - MMC_Disable(); - spi_unlock(); - return (2); /* Abort with command 2 (return 2) */ - } - } - - MMC_Disable(); - spi_unlock(); - - return 0; -} - -/* ############################################################################ - Sends a command to the MMC/SD-card - ######################################################################### */ -static unsigned char Write_Command_MMC (unsigned char *CMD) -{ - unsigned char a, tmp = 0xff; - unsigned short int Timeout = 0; - - MMC_Disable(); - spi_write(0xFF); - MMC_Enable(); - - for (a = 0; a < 0x06; a++) - spi_write(*CMD++); - - while (tmp == 0xff) { - tmp = spi_read(); - if (Timeout++ > 5000) - break; - } - - return (tmp); -} - -/* ############################################################################ - Routine to read the CID register from the MMC/SD-card (16 bytes) - ######################################################################### */ -void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short - int Bytes) -{ - unsigned short int a; - - spi_lock(); - mmc_spi_cfg(); - MMC_Enable(); - - if (Write_Command_MMC(CMD) != 0) { - MMC_Disable(); - spi_unlock(); - return; - } - - while (spi_read() != 0xfe) {}; - for (a = 0; a < Bytes; a++) - *Buffer++ = spi_read(); - - /* Read the CRC-byte */ - spi_read(); /* CRC - byte is discarded */ - spi_read(); /* CRC - byte is discarded */ - /* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */ - MMC_Disable(); - spi_unlock(); - - return; -} - -/* ############################################################################ - Routine to read a block (512 bytes) from the MMC/SD-card - ######################################################################### */ -unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer) -{ - /* Command 16 to read aBlocks from the MMC/SD - caed */ - unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF}; - - /* The addres on the MMC/SD-card is in bytes, - addr is transformed from blocks to bytes and the result is - placed into the command */ - - addr = addr << 9; /* addr = addr * 512 */ - - CMD[1] = ((addr & 0xFF000000) >> 24); - CMD[2] = ((addr & 0x00FF0000) >> 16); - CMD[3] = ((addr & 0x0000FF00) >> 8 ); - - MMC_Read_Block(CMD, Buffer, 512); - - return (0); -} - -/* ############################################################################ - Routine to write a block (512 byte) to the MMC/SD-card - ######################################################################### */ -unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer) -{ - unsigned char tmp, a; - unsigned short int b; - /* Command 24 to write a block to the MMC/SD - card */ - unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF}; - - /* The addres on the MMC/SD-card is in bytes, - addr is transformed from blocks to bytes and the result is - placed into the command */ - - addr = addr << 9; /* addr = addr * 512 */ - - CMD[1] = ((addr & 0xFF000000) >> 24); - CMD[2] = ((addr & 0x00FF0000) >> 16); - CMD[3] = ((addr & 0x0000FF00) >> 8 ); - - spi_lock(); - mmc_spi_cfg(); - MMC_Enable(); - - /* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */ - tmp = Write_Command_MMC(CMD); - if (tmp != 0) { - MMC_Disable(); - spi_unlock(); - return(tmp); - } - - /* Do a short delay and send a clock-pulse to the MMC/SD-card */ - for (a = 0; a < 100; a++) - spi_read(); - - /* Send a start byte to the MMC/SD-card */ - spi_write(0xFE); - - /* Write the block (512 bytes) to the MMC/SD-card */ - for (b = 0; b < 512; b++) - spi_write(*Buffer++); - - /* write the CRC-Byte */ - spi_write(0xFF); /* write a dummy CRC */ - spi_write(0xFF); /* CRC code is not used */ - - /* Wait for MMC/SD-card busy */ - while (spi_read() != 0xff) {}; - - /* set MMC_Chip_Select to high (MMC/SD-card inactive) */ - MMC_Disable(); - spi_unlock(); - return (0); -} - -/* ######################################################################### - Routine to read the CSD register from the MMC/SD-card (16 bytes) - ######################################################################### */ -unsigned char mmc_read_csd (unsigned char *Buffer) -{ - /* Command to read the CSD register */ - unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF}; - - MMC_Read_Block(CMD, Buffer, 16); - - return (0); -} diff --git a/board/lpc2292sodimm/mmc_hw.h b/board/lpc2292sodimm/mmc_hw.h deleted file mode 100644 index 3687dbf6969..00000000000 --- a/board/lpc2292sodimm/mmc_hw.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - This module implements a linux character device driver for the 24c256 chip. - Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#ifndef _MMC_HW_ -#define _MMC_HW_ - -unsigned char mmc_read_csd(unsigned char *Buffer); -unsigned char mmc_read_sector (unsigned long addr, - unsigned char *Buffer); -unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer); -int mmc_hw_init(void); - -#endif /* _MMC_HW_ */ diff --git a/board/lpc2292sodimm/spi.c b/board/lpc2292sodimm/spi.c deleted file mode 100644 index 4ba1468f39e..00000000000 --- a/board/lpc2292sodimm/spi.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - This module implements an interface to the SPI on the lpc22xx. - Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#include -#include -#include -#include -#include "spi.h" - -unsigned long spi_flags; -unsigned char spi_idle = 0x00; - -int spi_init(void) -{ - unsigned long pinsel0_value; - - /* activate spi pins */ - pinsel0_value = GET32(PINSEL0); - pinsel0_value &= ~(0xFFl << 8); - pinsel0_value |= (0x55l << 8); - PUT32(PINSEL0, pinsel0_value); - - return 0; -} diff --git a/board/lpc2292sodimm/spi.h b/board/lpc2292sodimm/spi.h deleted file mode 100644 index 6ae66e8ba74..00000000000 --- a/board/lpc2292sodimm/spi.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - This file defines the interface to the lpc22xx SPI module. - Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) - - This file may be included in software not adhering to the GPL. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -*/ - -#ifndef SPI_H -#define SPI_H - -#include -#include -#include -#include - -#define SPIF 0x80 - -#define spi_lock() disable_interrupts(); -#define spi_unlock() enable_interrupts(); - -extern unsigned long spi_flags; -extern unsigned char spi_idle; - -int spi_init(void); - -static inline unsigned char spi_read(void) -{ - unsigned char b; - - PUT8(S0SPDR, spi_idle); - while (!(GET8(S0SPSR) & SPIF)); - b = GET8(S0SPDR); - - return b; -} - -static inline void spi_write(unsigned char b) -{ - PUT8(S0SPDR, b); - while (!(GET8(S0SPSR) & SPIF)); - GET8(S0SPDR); /* this will clear the SPIF bit */ -} - -static inline void spi_set_clock(unsigned char clk_value) -{ - PUT8(S0SPCCR, clk_value); -} - -static inline void spi_set_cfg(unsigned char phase, - unsigned char polarity, - unsigned char lsbf) -{ - unsigned char v = 0x20; /* master bit set */ - - if (phase) - v |= 0x08; /* set phase bit */ - if (polarity) { - v |= 0x10; /* set polarity bit */ - spi_idle = 0xFF; - } else { - spi_idle = 0x00; - } - if (lsbf) - v |= 0x40; /* set lsbf bit */ - - PUT8(S0SPCR, v); -} -#endif /* SPI_H */ diff --git a/include/asm-arm/arch-arm720t/lpc2292_registers.h b/include/asm-arm/arch-arm720t/lpc2292_registers.h deleted file mode 100644 index 5715f3ef745..00000000000 --- a/include/asm-arm/arch-arm720t/lpc2292_registers.h +++ /dev/null @@ -1,225 +0,0 @@ -#ifndef __LPC2292_REGISTERS_H -#define __LPC2292_REGISTERS_H - -#include - -/* Macros for reading/writing registers */ -#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value)) -#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value)) -#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value)) -#define GET8(reg) (*(volatile unsigned char*)(reg)) -#define GET16(reg) (*(volatile unsigned short*)(reg)) -#define GET32(reg) (*(volatile unsigned int*)(reg)) - -/* External Memory Controller */ - -#define BCFG0 0xFFE00000 /* 32-bits */ -#define BCFG1 0xFFE00004 /* 32-bits */ -#define BCFG2 0xFFE00008 /* 32-bits */ -#define BCFG3 0xFFE0000c /* 32-bits */ - -/* System Control Block */ - -#define EXTINT 0xE01FC140 -#define EXTWAKE 0xE01FC144 -#define EXTMODE 0xE01FC148 -#define EXTPOLAR 0xE01FC14C -#define MEMMAP 0xE01FC040 -#define PLLCON 0xE01FC080 -#define PLLCFG 0xE01FC084 -#define PLLSTAT 0xE01FC088 -#define PLLFEED 0xE01FC08C -#define PCON 0xE01FC0C0 -#define PCONP 0xE01FC0C4 -#define VPBDIV 0xE01FC100 - -/* Memory Acceleration Module */ - -#define MAMCR 0xE01FC000 -#define MAMTIM 0xE01FC004 - -/* Vectored Interrupt Controller */ - -#define VICIRQStatus 0xFFFFF000 -#define VICFIQStatus 0xFFFFF004 -#define VICRawIntr 0xFFFFF008 -#define VICIntSelect 0xFFFFF00C -#define VICIntEnable 0xFFFFF010 -#define VICIntEnClr 0xFFFFF014 -#define VICSoftInt 0xFFFFF018 -#define VICSoftIntClear 0xFFFFF01C -#define VICProtection 0xFFFFF020 -#define VICVectAddr 0xFFFFF030 -#define VICDefVectAddr 0xFFFFF034 -#define VICVectAddr0 0xFFFFF100 -#define VICVectAddr1 0xFFFFF104 -#define VICVectAddr2 0xFFFFF108 -#define VICVectAddr3 0xFFFFF10C -#define VICVectAddr4 0xFFFFF110 -#define VICVectAddr5 0xFFFFF114 -#define VICVectAddr6 0xFFFFF118 -#define VICVectAddr7 0xFFFFF11C -#define VICVectAddr8 0xFFFFF120 -#define VICVectAddr9 0xFFFFF124 -#define VICVectAddr10 0xFFFFF128 -#define VICVectAddr11 0xFFFFF12C -#define VICVectAddr12 0xFFFFF130 -#define VICVectAddr13 0xFFFFF134 -#define VICVectAddr14 0xFFFFF138 -#define VICVectAddr15 0xFFFFF13C -#define VICVectCntl0 0xFFFFF200 -#define VICVectCntl1 0xFFFFF204 -#define VICVectCntl2 0xFFFFF208 -#define VICVectCntl3 0xFFFFF20C -#define VICVectCntl4 0xFFFFF210 -#define VICVectCntl5 0xFFFFF214 -#define VICVectCntl6 0xFFFFF218 -#define VICVectCntl7 0xFFFFF21C -#define VICVectCntl8 0xFFFFF220 -#define VICVectCntl9 0xFFFFF224 -#define VICVectCntl10 0xFFFFF228 -#define VICVectCntl11 0xFFFFF22C -#define VICVectCntl12 0xFFFFF230 -#define VICVectCntl13 0xFFFFF234 -#define VICVectCntl14 0xFFFFF238 -#define VICVectCntl15 0xFFFFF23C - -/* Pin connect block */ - -#define PINSEL0 0xE002C000 /* 32 bits */ -#define PINSEL1 0xE002C004 /* 32 bits */ -#define PINSEL2 0xE002C014 /* 32 bits */ - -/* GPIO */ - -#define IO0PIN 0xE0028000 -#define IO0SET 0xE0028004 -#define IO0DIR 0xE0028008 -#define IO0CLR 0xE002800C -#define IO1PIN 0xE0028010 -#define IO1SET 0xE0028014 -#define IO1DIR 0xE0028018 -#define IO1CLR 0xE002801C -#define IO2PIN 0xE0028020 -#define IO2SET 0xE0028024 -#define IO2DIR 0xE0028028 -#define IO2CLR 0xE002802C -#define IO3PIN 0xE0028030 -#define IO3SET 0xE0028034 -#define IO3DIR 0xE0028038 -#define IO3CLR 0xE002803C - -/* Uarts */ - -#define U0RBR 0xE000C000 -#define U0THR 0xE000C000 -#define U0IER 0xE000C004 -#define U0IIR 0xE000C008 -#define U0FCR 0xE000C008 -#define U0LCR 0xE000C00C -#define U0LSR 0xE000C014 -#define U0SCR 0xE000C01C -#define U0DLL 0xE000C000 -#define U0DLM 0xE000C004 - -#define U1RBR 0xE0010000 -#define U1THR 0xE0010000 -#define U1IER 0xE0010004 -#define U1IIR 0xE0010008 -#define U1FCR 0xE0010008 -#define U1LCR 0xE001000C -#define U1MCR 0xE0010010 -#define U1LSR 0xE0010014 -#define U1MSR 0xE0010018 -#define U1SCR 0xE001001C -#define U1DLL 0xE0010000 -#define U1DLM 0xE0010004 - -/* I2C */ - -#define I2CONSET 0xE001C000 -#define I2STAT 0xE001C004 -#define I2DAT 0xE001C008 -#define I2ADR 0xE001C00C -#define I2SCLH 0xE001C010 -#define I2SCLL 0xE001C014 -#define I2CONCLR 0xE001C018 - -/* SPI */ - -#define S0SPCR 0xE0020000 -#define S0SPSR 0xE0020004 -#define S0SPDR 0xE0020008 -#define S0SPCCR 0xE002000C -#define S0SPINT 0xE002001C - -#define S1SPCR 0xE0030000 -#define S1SPSR 0xE0030004 -#define S1SPDR 0xE0030008 -#define S1SPCCR 0xE003000C -#define S1SPINT 0xE003001C - -/* CAN controller */ - -/* skip for now */ - -/* Timers */ - -#define T0IR 0xE0004000 -#define T0TCR 0xE0004004 -#define T0TC 0xE0004008 -#define T0PR 0xE000400C -#define T0PC 0xE0004010 -#define T0MCR 0xE0004014 -#define T0MR0 0xE0004018 -#define T0MR1 0xE000401C -#define T0MR2 0xE0004020 -#define T0MR3 0xE0004024 -#define T0CCR 0xE0004028 -#define T0CR0 0xE000402C -#define T0CR1 0xE0004030 -#define T0CR2 0xE0004034 -#define T0CR3 0xE0004038 -#define T0EMR 0xE000403C - -#define T1IR 0xE0008000 -#define T1TCR 0xE0008004 -#define T1TC 0xE0008008 -#define T1PR 0xE000800C -#define T1PC 0xE0008010 -#define T1MCR 0xE0008014 -#define T1MR0 0xE0008018 -#define T1MR1 0xE000801C -#define T1MR2 0xE0008020 -#define T1MR3 0xE0008024 -#define T1CCR 0xE0008028 -#define T1CR0 0xE000802C -#define T1CR1 0xE0008030 -#define T1CR2 0xE0008034 -#define T1CR3 0xE0008038 -#define T1EMR 0xE000803C - -/* PWM */ - -/* skip for now */ - -/* A/D converter */ - -/* skip for now */ - -/* Real Time Clock */ - -/* skip for now */ - -/* Watchdog */ - -#define WDMOD 0xE0000000 -#define WDTC 0xE0000004 -#define WDFEED 0xE0000008 -#define WDTV 0xE000000C - -/* EmbeddedICE LOGIC */ - -/* skip for now */ - -#endif diff --git a/include/asm-arm/arch-arm720t/mmc.h b/include/asm-arm/arch-arm720t/mmc.h deleted file mode 100644 index e664a5f6789..00000000000 --- a/include/asm-arm/arch-arm720t/mmc.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * A dummy header file for use with the LPC2292 port to keep the - * compiler happy. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _MMC_ARM_TDM_H_ -#define _MMC_ARM_TDM_H_ -#endif /* _MMC_ARM_TDM_H_ */ -- cgit v1.3.1 From 160131bf965785419626df6c388729fe0b597992 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Wed, 9 May 2007 11:41:58 +0100 Subject: Add the files for the SMN42 board --- cpu/arm720t/lpc2292/Makefile | 50 ++ cpu/arm720t/lpc2292/flash.c | 249 ++++++ cpu/arm720t/lpc2292/iap_entry.S | 7 + cpu/arm720t/lpc2292/mmc.c | 157 ++++ cpu/arm720t/lpc2292/mmc_hw.c | 233 ++++++ cpu/arm720t/lpc2292/mmc_hw.h | 29 + cpu/arm720t/lpc2292/spi.c | 40 + drivers/enc28j60.c | 978 +++++++++++++++++++++++ include/asm-arm/arch-lpc2292/hardware.h | 33 + include/asm-arm/arch-lpc2292/lpc2292_registers.h | 225 ++++++ include/asm-arm/arch-lpc2292/mmc.h | 22 + include/asm-arm/arch-lpc2292/spi.h | 82 ++ include/configs/SMN42.h | 198 +++++ 13 files changed, 2303 insertions(+) create mode 100644 cpu/arm720t/lpc2292/Makefile create mode 100644 cpu/arm720t/lpc2292/flash.c create mode 100644 cpu/arm720t/lpc2292/iap_entry.S create mode 100644 cpu/arm720t/lpc2292/mmc.c create mode 100644 cpu/arm720t/lpc2292/mmc_hw.c create mode 100644 cpu/arm720t/lpc2292/mmc_hw.h create mode 100644 cpu/arm720t/lpc2292/spi.c create mode 100644 drivers/enc28j60.c create mode 100644 include/asm-arm/arch-lpc2292/hardware.h create mode 100644 include/asm-arm/arch-lpc2292/lpc2292_registers.h create mode 100644 include/asm-arm/arch-lpc2292/mmc.h create mode 100644 include/asm-arm/arch-lpc2292/spi.h create mode 100644 include/configs/SMN42.h (limited to 'include') diff --git a/cpu/arm720t/lpc2292/Makefile b/cpu/arm720t/lpc2292/Makefile new file mode 100644 index 00000000000..240f1e3b3b5 --- /dev/null +++ b/cpu/arm720t/lpc2292/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = flash.o mmc.o mmc_hw.o spi.o +SOBJS = $(obj)iap_entry.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +# this MUST be compiled as thumb code! +$(SOBJS): + $(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm720t/lpc2292/flash.c b/cpu/arm720t/lpc2292/flash.c new file mode 100644 index 00000000000..e5c869722dc --- /dev/null +++ b/cpu/arm720t/lpc2292/flash.c @@ -0,0 +1,249 @@ +/* + * (C) Copyright 2006 Embedded Artists AB + * + * Modified to remove all but the IAP-command related code by + * Gary Jennejohn + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +/* IAP commands use 32 bytes at the top of CPU internal sram, we + use 512 bytes below that */ +#define COPY_BUFFER_LOCATION 0x40003de0 + +#define IAP_LOCATION 0x7ffffff1 +#define IAP_CMD_PREPARE 50 +#define IAP_CMD_COPY 51 +#define IAP_CMD_ERASE 52 +#define IAP_CMD_CHECK 53 +#define IAP_CMD_ID 54 +#define IAP_CMD_VERSION 55 +#define IAP_CMD_COMPARE 56 + +#define IAP_RET_CMD_SUCCESS 0 + +static unsigned long command[5]; +static unsigned long result[2]; + +extern void iap_entry(unsigned long * command, unsigned long * result); + +/*----------------------------------------------------------------------- + * + */ +static int get_flash_sector(flash_info_t * info, ulong flash_addr) +{ + int i; + + for(i = 1; i < (info->sector_count); i++) { + if (flash_addr < (info->start[i])) + break; + } + + return (i-1); +} + +/*----------------------------------------------------------------------- + * This function assumes that flash_addr is aligned on 512 bytes boundary + * in flash. This function also assumes that prepare have been called + * for the sector in question. + */ +int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr) +{ + int first_sector; + int last_sector; + + first_sector = get_flash_sector(info, flash_addr); + last_sector = get_flash_sector(info, flash_addr + 512 - 1); + + /* prepare sectors for write */ + command[0] = IAP_CMD_PREPARE; + command[1] = first_sector; + command[2] = last_sector; + iap_entry(command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf("IAP prepare failed\n"); + return ERR_PROG_ERROR; + } + + command[0] = IAP_CMD_COPY; + command[1] = flash_addr; + command[2] = COPY_BUFFER_LOCATION; + command[3] = 512; + command[4] = CFG_SYS_CLK_FREQ >> 10; + iap_entry(command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf("IAP copy failed\n"); + return 1; + } + + return 0; +} + +/*----------------------------------------------------------------------- + */ + +int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag; + int prot; + int sect; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + + flag = disable_interrupts(); + + printf ("Erasing %d sectors starting at sector %2d.\n" + "This make take some time ... ", + s_last - s_first + 1, s_first); + + command[0] = IAP_CMD_PREPARE; + command[1] = s_first; + command[2] = s_last; + iap_entry(command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf("IAP prepare failed\n"); + return ERR_PROTECTED; + } + + command[0] = IAP_CMD_ERASE; + command[1] = s_first; + command[2] = s_last; + command[3] = CFG_SYS_CLK_FREQ >> 10; + iap_entry(command, result); + if (result[0] != IAP_RET_CMD_SUCCESS) { + printf("IAP erase failed\n"); + return ERR_PROTECTED; + } + + if (flag) + enable_interrupts(); + + return ERR_OK; +} + +int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr, + ulong cnt) +{ + int first_copy_size; + int last_copy_size; + int first_block; + int last_block; + int nbr_mid_blocks; + uchar memmap_value; + ulong i; + uchar* src_org; + uchar* dst_org; + int ret = ERR_OK; + + src_org = src; + dst_org = (uchar*)addr; + + first_block = addr / 512; + last_block = (addr + cnt) / 512; + nbr_mid_blocks = last_block - first_block - 1; + + first_copy_size = 512 - (addr % 512); + last_copy_size = (addr + cnt) % 512; + + debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, " + "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n", + (ulong)(first_block * 512), + (ulong)COPY_BUFFER_LOCATION, + (ulong)src, + (ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size), + first_copy_size, + (ulong)COPY_BUFFER_LOCATION, + (ulong)(first_block * 512)); + + /* copy first block */ + memcpy((void*)COPY_BUFFER_LOCATION, + (void*)(first_block * 512), 512); + memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size), + src, first_copy_size); + lpc2292_copy_buffer_to_flash(info, first_block * 512); + src += first_copy_size; + addr += first_copy_size; + + /* copy middle blocks */ + for (i = 0; i < nbr_mid_blocks; i++) { + debug("copy middle block: %lX -> %lX 512 bytes, " + "%lX -> %lX 512 bytes\n", + (ulong)src, + (ulong)COPY_BUFFER_LOCATION, + (ulong)COPY_BUFFER_LOCATION, + (ulong)addr); + + memcpy((void*)COPY_BUFFER_LOCATION, src, 512); + lpc2292_copy_buffer_to_flash(info, addr); + src += 512; + addr += 512; + } + + + if (last_copy_size > 0) { + debug("copy last block: (1) %lX -> %lX 0x200 bytes, " + "(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n", + (ulong)(last_block * 512), + (ulong)COPY_BUFFER_LOCATION, + (ulong)src, + (ulong)(COPY_BUFFER_LOCATION), + last_copy_size, + (ulong)COPY_BUFFER_LOCATION, + (ulong)addr); + + /* copy last block */ + memcpy((void*)COPY_BUFFER_LOCATION, + (void*)(last_block * 512), 512); + memcpy((void*)COPY_BUFFER_LOCATION, + src, last_copy_size); + lpc2292_copy_buffer_to_flash(info, addr); + } + + /* verify write */ + memmap_value = GET8(MEMMAP); + + disable_interrupts(); + + PUT8(MEMMAP, 01); /* we must make sure that initial 64 + bytes are taken from flash when we + do the compare */ + + for (i = 0; i < cnt; i++) { + if (*dst_org != *src_org){ + printf("Write failed. Byte %lX differs\n", i); + ret = ERR_PROG_ERROR; + break; + } + dst_org++; + src_org++; + } + + PUT8(MEMMAP, memmap_value); + enable_interrupts(); + + return ret; +} diff --git a/cpu/arm720t/lpc2292/iap_entry.S b/cpu/arm720t/lpc2292/iap_entry.S new file mode 100644 index 00000000000..c31d5190bd7 --- /dev/null +++ b/cpu/arm720t/lpc2292/iap_entry.S @@ -0,0 +1,7 @@ +IAP_ADDRESS: .word 0x7FFFFFF1 + +.globl iap_entry +iap_entry: + ldr r2, IAP_ADDRESS + bx r2 + mov pc, lr diff --git a/cpu/arm720t/lpc2292/mmc.c b/cpu/arm720t/lpc2292/mmc.c new file mode 100644 index 00000000000..fd7f149b66c --- /dev/null +++ b/cpu/arm720t/lpc2292/mmc.c @@ -0,0 +1,157 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "mmc_hw.h" +#include + +#ifdef CONFIG_MMC + +#undef MMC_DEBUG + +static block_dev_desc_t mmc_dev; + +/* these are filled out by a call to mmc_hw_get_parameters */ +static int hw_size; /* in kbytes */ +static int hw_nr_sects; +static int hw_sect_size; /* in bytes */ + +block_dev_desc_t * mmc_get_dev(int dev) +{ + return (block_dev_desc_t *)(&mmc_dev); +} + +unsigned long mmc_block_read(int dev, + unsigned long start, + lbaint_t blkcnt, + void *buffer) +{ + unsigned long rc = 0; + unsigned char *p = (unsigned char *)buffer; + unsigned long i; + unsigned long addr = start; + +#ifdef MMC_DEBUG + printf("mmc_block_read: start=%lu, blkcnt=%lu\n", start, + (unsigned long)blkcnt); +#endif + + for(i = 0; i < (unsigned long)blkcnt; i++) { +#ifdef MMC_DEBUG + printf("mmc_read_sector: addr=%lu, buffer=%p\n", addr, p); +#endif + (void)mmc_read_sector(addr, p); + rc++; + addr++; + p += hw_sect_size; + } + + return rc; +} + +/*----------------------------------------------------------------------------- + * Read hardware paramterers (sector size, size, number of sectors) + */ +static int mmc_hw_get_parameters(void) +{ + unsigned char csddata[16]; + unsigned int sizemult; + unsigned int size; + + mmc_read_csd(csddata); + hw_sect_size = 1<<(csddata[5] & 0x0f); + size = ((csddata[6]&0x03)<<10)+(csddata[7]<<2)+(csddata[8]&0xc0); + sizemult = ((csddata[10] & 0x80)>>7)+((csddata[9] & 0x03)<<1); + hw_nr_sects = (size+1)*(1<<(sizemult+2)); + hw_size = hw_nr_sects*hw_sect_size/1024; + +#ifdef MMC_DEBUG + printf("mmc_hw_get_parameters: hw_sect_size=%d, hw_nr_sects=%d, " + "hw_size=%d\n", hw_sect_size, hw_nr_sects, hw_size); +#endif + + return 0; +} + +int mmc_init(int verbose) +{ + int ret = -ENODEV; + + if (verbose) + printf("mmc_init\n"); + + spi_init(); + /* this meeds to be done twice */ + mmc_hw_init(); + udelay(1000); + mmc_hw_init(); + + mmc_hw_get_parameters(); + + mmc_dev.if_type = IF_TYPE_MMC; + mmc_dev.part_type = PART_TYPE_DOS; + mmc_dev.dev = 0; + mmc_dev.lun = 0; + mmc_dev.type = 0; + mmc_dev.blksz = hw_sect_size; + mmc_dev.lba = hw_nr_sects; + sprintf((char*)mmc_dev.vendor, "Unknown vendor"); + sprintf((char*)mmc_dev.product, "Unknown product"); + sprintf((char*)mmc_dev.revision, "N/A"); + mmc_dev.removable = 0; /* should be true??? */ + mmc_dev.block_read = mmc_block_read; + + fat_register_device(&mmc_dev, 1); + + ret = 0; + + return ret; +} + +int mmc_write(uchar * src, ulong dst, int size) +{ +#ifdef MMC_DEBUG + printf("mmc_write: src=%p, dst=%lu, size=%u\n", src, dst, size); +#endif + /* Since mmc2info always returns 0 this function will never be called */ + return 0; +} + +int mmc_read(ulong src, uchar * dst, int size) +{ +#ifdef MMC_DEBUG + printf("mmc_read: src=%lu, dst=%p, size=%u\n", src, dst, size); +#endif + /* Since mmc2info always returns 0 this function will never be called */ + return 0; +} + +int mmc2info(ulong addr) +{ + /* This function is used by cmd_cp to determine if source or destination + address resides on MMC-card or not. We do not support copy to and from + MMC-card so we always return 0. */ + return 0; +} + +#endif /* CONFIG_MMC */ diff --git a/cpu/arm720t/lpc2292/mmc_hw.c b/cpu/arm720t/lpc2292/mmc_hw.c new file mode 100644 index 00000000000..b4dc4a6e2f1 --- /dev/null +++ b/cpu/arm720t/lpc2292/mmc_hw.c @@ -0,0 +1,233 @@ +/* + This code was original written by Ulrich Radig and modified by + Embedded Artists AB (www.embeddedartists.com). + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include +#include +#include +#include + +#define MMC_Enable() PUT32(IO1CLR, 1l << 22) +#define MMC_Disable() PUT32(IO1SET, 1l << 22) +#define mmc_spi_cfg() spi_set_clock(8); spi_set_cfg(0, 1, 0); + +static unsigned char Write_Command_MMC (unsigned char *CMD); +static void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, + unsigned short int Bytes); + +/* initialize the hardware */ +int mmc_hw_init(void) +{ + unsigned long a; + unsigned short int Timeout = 0; + unsigned char b; + unsigned char CMD[] = {0x40, 0x00, 0x00, 0x00, 0x00, 0x95}; + + /* set-up GPIO and SPI */ + (*((volatile unsigned long *)PINSEL2)) &= ~(1l << 3); /* clear bit 3 */ + (*((volatile unsigned long *)IO1DIR)) |= (1l << 22); /* set bit 22 (output) */ + + MMC_Disable(); + + spi_lock(); + spi_set_clock(248); + spi_set_cfg(0, 1, 0); + MMC_Enable(); + + /* waste some time */ + for(a=0; a < 20000; a++) + asm("nop"); + + /* Put the MMC/SD-card into SPI-mode */ + for (b = 0; b < 10; b++) /* Sends min 74+ clocks to the MMC/SD-card */ + spi_write(0xff); + + /* Sends command CMD0 to MMC/SD-card */ + while (Write_Command_MMC(CMD) != 1) { + if (Timeout++ > 200) { + MMC_Disable(); + spi_unlock(); + return(1); /* Abort with command 1 (return 1) */ + } + } + /* Sends Command CMD1 an MMC/SD-card */ + Timeout = 0; + CMD[0] = 0x41;/* Command 1 */ + CMD[5] = 0xFF; + + while (Write_Command_MMC(CMD) != 0) { + if (Timeout++ > 200) { + MMC_Disable(); + spi_unlock(); + return (2); /* Abort with command 2 (return 2) */ + } + } + + MMC_Disable(); + spi_unlock(); + + return 0; +} + +/* ############################################################################ + Sends a command to the MMC/SD-card + ######################################################################### */ +static unsigned char Write_Command_MMC (unsigned char *CMD) +{ + unsigned char a, tmp = 0xff; + unsigned short int Timeout = 0; + + MMC_Disable(); + spi_write(0xFF); + MMC_Enable(); + + for (a = 0; a < 0x06; a++) + spi_write(*CMD++); + + while (tmp == 0xff) { + tmp = spi_read(); + if (Timeout++ > 5000) + break; + } + + return (tmp); +} + +/* ############################################################################ + Routine to read the CID register from the MMC/SD-card (16 bytes) + ######################################################################### */ +void MMC_Read_Block(unsigned char *CMD, unsigned char *Buffer, unsigned short + int Bytes) +{ + unsigned short int a; + + spi_lock(); + mmc_spi_cfg(); + MMC_Enable(); + + if (Write_Command_MMC(CMD) != 0) { + MMC_Disable(); + spi_unlock(); + return; + } + + while (spi_read() != 0xfe) {}; + for (a = 0; a < Bytes; a++) + *Buffer++ = spi_read(); + + /* Read the CRC-byte */ + spi_read(); /* CRC - byte is discarded */ + spi_read(); /* CRC - byte is discarded */ + /* set MMC_Chip_Select to high (MMC/SD-card Inaktiv) */ + MMC_Disable(); + spi_unlock(); + + return; +} + +/* ############################################################################ + Routine to read a block (512 bytes) from the MMC/SD-card + ######################################################################### */ +unsigned char mmc_read_sector (unsigned long addr,unsigned char *Buffer) +{ + /* Command 16 to read aBlocks from the MMC/SD - caed */ + unsigned char CMD[] = {0x51,0x00,0x00,0x00,0x00,0xFF}; + + /* The addres on the MMC/SD-card is in bytes, + addr is transformed from blocks to bytes and the result is + placed into the command */ + + addr = addr << 9; /* addr = addr * 512 */ + + CMD[1] = ((addr & 0xFF000000) >> 24); + CMD[2] = ((addr & 0x00FF0000) >> 16); + CMD[3] = ((addr & 0x0000FF00) >> 8 ); + + MMC_Read_Block(CMD, Buffer, 512); + + return (0); +} + +/* ############################################################################ + Routine to write a block (512 byte) to the MMC/SD-card + ######################################################################### */ +unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer) +{ + unsigned char tmp, a; + unsigned short int b; + /* Command 24 to write a block to the MMC/SD - card */ + unsigned char CMD[] = {0x58, 0x00, 0x00, 0x00, 0x00, 0xFF}; + + /* The addres on the MMC/SD-card is in bytes, + addr is transformed from blocks to bytes and the result is + placed into the command */ + + addr = addr << 9; /* addr = addr * 512 */ + + CMD[1] = ((addr & 0xFF000000) >> 24); + CMD[2] = ((addr & 0x00FF0000) >> 16); + CMD[3] = ((addr & 0x0000FF00) >> 8 ); + + spi_lock(); + mmc_spi_cfg(); + MMC_Enable(); + + /* Send command CMD24 to the MMC/SD-card (Write 1 Block/512 Bytes) */ + tmp = Write_Command_MMC(CMD); + if (tmp != 0) { + MMC_Disable(); + spi_unlock(); + return(tmp); + } + + /* Do a short delay and send a clock-pulse to the MMC/SD-card */ + for (a = 0; a < 100; a++) + spi_read(); + + /* Send a start byte to the MMC/SD-card */ + spi_write(0xFE); + + /* Write the block (512 bytes) to the MMC/SD-card */ + for (b = 0; b < 512; b++) + spi_write(*Buffer++); + + /* write the CRC-Byte */ + spi_write(0xFF); /* write a dummy CRC */ + spi_write(0xFF); /* CRC code is not used */ + + /* Wait for MMC/SD-card busy */ + while (spi_read() != 0xff) {}; + + /* set MMC_Chip_Select to high (MMC/SD-card inactive) */ + MMC_Disable(); + spi_unlock(); + return (0); +} + +/* ######################################################################### + Routine to read the CSD register from the MMC/SD-card (16 bytes) + ######################################################################### */ +unsigned char mmc_read_csd (unsigned char *Buffer) +{ + /* Command to read the CSD register */ + unsigned char CMD[] = {0x49, 0x00, 0x00, 0x00, 0x00, 0xFF}; + + MMC_Read_Block(CMD, Buffer, 16); + + return (0); +} diff --git a/cpu/arm720t/lpc2292/mmc_hw.h b/cpu/arm720t/lpc2292/mmc_hw.h new file mode 100644 index 00000000000..3687dbf6969 --- /dev/null +++ b/cpu/arm720t/lpc2292/mmc_hw.h @@ -0,0 +1,29 @@ +/* + This module implements a linux character device driver for the 24c256 chip. + Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#ifndef _MMC_HW_ +#define _MMC_HW_ + +unsigned char mmc_read_csd(unsigned char *Buffer); +unsigned char mmc_read_sector (unsigned long addr, + unsigned char *Buffer); +unsigned char mmc_write_sector (unsigned long addr,unsigned char *Buffer); +int mmc_hw_init(void); + +#endif /* _MMC_HW_ */ diff --git a/cpu/arm720t/lpc2292/spi.c b/cpu/arm720t/lpc2292/spi.c new file mode 100644 index 00000000000..d296bdac686 --- /dev/null +++ b/cpu/arm720t/lpc2292/spi.c @@ -0,0 +1,40 @@ +/* + This module implements an interface to the SPI on the lpc22xx. + Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#include +#include +#include +#include +#include + +unsigned long spi_flags; +unsigned char spi_idle = 0x00; + +int spi_init(void) +{ + unsigned long pinsel0_value; + + /* activate spi pins */ + pinsel0_value = GET32(PINSEL0); + pinsel0_value &= ~(0xFFl << 8); + pinsel0_value |= (0x55l << 8); + PUT32(PINSEL0, pinsel0_value); + + return 0; +} diff --git a/drivers/enc28j60.c b/drivers/enc28j60.c new file mode 100644 index 00000000000..c2ed48573ad --- /dev/null +++ b/drivers/enc28j60.c @@ -0,0 +1,978 @@ +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#ifdef CONFIG_ENC28J60 +#include +#include +#include + +/* + * Control Registers in Bank 0 + */ + +#define CTL_REG_ERDPTL 0x00 +#define CTL_REG_ERDPTH 0x01 +#define CTL_REG_EWRPTL 0x02 +#define CTL_REG_EWRPTH 0x03 +#define CTL_REG_ETXSTL 0x04 +#define CTL_REG_ETXSTH 0x05 +#define CTL_REG_ETXNDL 0x06 +#define CTL_REG_ETXNDH 0x07 +#define CTL_REG_ERXSTL 0x08 +#define CTL_REG_ERXSTH 0x09 +#define CTL_REG_ERXNDL 0x0A +#define CTL_REG_ERXNDH 0x0B +#define CTL_REG_ERXRDPTL 0x0C +#define CTL_REG_ERXRDPTH 0x0D +#define CTL_REG_ERXWRPTL 0x0E +#define CTL_REG_ERXWRPTH 0x0F +#define CTL_REG_EDMASTL 0x10 +#define CTL_REG_EDMASTH 0x11 +#define CTL_REG_EDMANDL 0x12 +#define CTL_REG_EDMANDH 0x13 +#define CTL_REG_EDMADSTL 0x14 +#define CTL_REG_EDMADSTH 0x15 +#define CTL_REG_EDMACSL 0x16 +#define CTL_REG_EDMACSH 0x17 +/* these are common in all banks */ +#define CTL_REG_EIE 0x1B +#define CTL_REG_EIR 0x1C +#define CTL_REG_ESTAT 0x1D +#define CTL_REG_ECON2 0x1E +#define CTL_REG_ECON1 0x1F + +/* + * Control Registers in Bank 1 + */ + +#define CTL_REG_EHT0 0x00 +#define CTL_REG_EHT1 0x01 +#define CTL_REG_EHT2 0x02 +#define CTL_REG_EHT3 0x03 +#define CTL_REG_EHT4 0x04 +#define CTL_REG_EHT5 0x05 +#define CTL_REG_EHT6 0x06 +#define CTL_REG_EHT7 0x07 +#define CTL_REG_EPMM0 0x08 +#define CTL_REG_EPMM1 0x09 +#define CTL_REG_EPMM2 0x0A +#define CTL_REG_EPMM3 0x0B +#define CTL_REG_EPMM4 0x0C +#define CTL_REG_EPMM5 0x0D +#define CTL_REG_EPMM6 0x0E +#define CTL_REG_EPMM7 0x0F +#define CTL_REG_EPMCSL 0x10 +#define CTL_REG_EPMCSH 0x11 +#define CTL_REG_EPMOL 0x14 +#define CTL_REG_EPMOH 0x15 +#define CTL_REG_EWOLIE 0x16 +#define CTL_REG_EWOLIR 0x17 +#define CTL_REG_ERXFCON 0x18 +#define CTL_REG_EPKTCNT 0x19 + +/* + * Control Registers in Bank 2 + */ + +#define CTL_REG_MACON1 0x00 +#define CTL_REG_MACON2 0x01 +#define CTL_REG_MACON3 0x02 +#define CTL_REG_MACON4 0x03 +#define CTL_REG_MABBIPG 0x04 +#define CTL_REG_MAIPGL 0x06 +#define CTL_REG_MAIPGH 0x07 +#define CTL_REG_MACLCON1 0x08 +#define CTL_REG_MACLCON2 0x09 +#define CTL_REG_MAMXFLL 0x0A +#define CTL_REG_MAMXFLH 0x0B +#define CTL_REG_MAPHSUP 0x0D +#define CTL_REG_MICON 0x11 +#define CTL_REG_MICMD 0x12 +#define CTL_REG_MIREGADR 0x14 +#define CTL_REG_MIWRL 0x16 +#define CTL_REG_MIWRH 0x17 +#define CTL_REG_MIRDL 0x18 +#define CTL_REG_MIRDH 0x19 + +/* + * Control Registers in Bank 3 + */ + +#define CTL_REG_MAADR1 0x00 +#define CTL_REG_MAADR0 0x01 +#define CTL_REG_MAADR3 0x02 +#define CTL_REG_MAADR2 0x03 +#define CTL_REG_MAADR5 0x04 +#define CTL_REG_MAADR4 0x05 +#define CTL_REG_EBSTSD 0x06 +#define CTL_REG_EBSTCON 0x07 +#define CTL_REG_EBSTCSL 0x08 +#define CTL_REG_EBSTCSH 0x09 +#define CTL_REG_MISTAT 0x0A +#define CTL_REG_EREVID 0x12 +#define CTL_REG_ECOCON 0x15 +#define CTL_REG_EFLOCON 0x17 +#define CTL_REG_EPAUSL 0x18 +#define CTL_REG_EPAUSH 0x19 + + +/* + * PHY Register + */ + +#define PHY_REG_PHID1 0x02 +#define PHY_REG_PHID2 0x03 +/* taken from the Linux driver */ +#define PHY_REG_PHCON1 0x00 +#define PHY_REG_PHCON2 0x10 +#define PHY_REG_PHLCON 0x14 + +/* + * Receive Filter Register (ERXFCON) bits + */ + +#define ENC_RFR_UCEN 0x80 +#define ENC_RFR_ANDOR 0x40 +#define ENC_RFR_CRCEN 0x20 +#define ENC_RFR_PMEN 0x10 +#define ENC_RFR_MPEN 0x08 +#define ENC_RFR_HTEN 0x04 +#define ENC_RFR_MCEN 0x02 +#define ENC_RFR_BCEN 0x01 + +/* + * ECON1 Register Bits + */ + +#define ENC_ECON1_TXRST 0x80 +#define ENC_ECON1_RXRST 0x40 +#define ENC_ECON1_DMAST 0x20 +#define ENC_ECON1_CSUMEN 0x10 +#define ENC_ECON1_TXRTS 0x08 +#define ENC_ECON1_RXEN 0x04 +#define ENC_ECON1_BSEL1 0x02 +#define ENC_ECON1_BSEL0 0x01 + +/* + * ECON2 Register Bits + */ +#define ENC_ECON2_AUTOINC 0x80 +#define ENC_ECON2_PKTDEC 0x40 +#define ENC_ECON2_PWRSV 0x20 +#define ENC_ECON2_VRPS 0x08 + +/* + * EIR Register Bits + */ +#define ENC_EIR_PKTIF 0x40 +#define ENC_EIR_DMAIF 0x20 +#define ENC_EIR_LINKIF 0x10 +#define ENC_EIR_TXIF 0x08 +#define ENC_EIR_WOLIF 0x04 +#define ENC_EIR_TXERIF 0x02 +#define ENC_EIR_RXERIF 0x01 + +/* + * ESTAT Register Bits + */ + +#define ENC_ESTAT_INT 0x80 +#define ENC_ESTAT_LATECOL 0x10 +#define ENC_ESTAT_RXBUSY 0x04 +#define ENC_ESTAT_TXABRT 0x02 +#define ENC_ESTAT_CLKRDY 0x01 + +/* + * EIE Register Bits + */ + +#define ENC_EIE_INTIE 0x80 +#define ENC_EIE_PKTIE 0x40 +#define ENC_EIE_DMAIE 0x20 +#define ENC_EIE_LINKIE 0x10 +#define ENC_EIE_TXIE 0x08 +#define ENC_EIE_WOLIE 0x04 +#define ENC_EIE_TXERIE 0x02 +#define ENC_EIE_RXERIE 0x01 + +/* + * MACON1 Register Bits + */ +#define ENC_MACON1_LOOPBK 0x10 +#define ENC_MACON1_TXPAUS 0x08 +#define ENC_MACON1_RXPAUS 0x04 +#define ENC_MACON1_PASSALL 0x02 +#define ENC_MACON1_MARXEN 0x01 + + +/* + * MACON2 Register Bits + */ +#define ENC_MACON2_MARST 0x80 +#define ENC_MACON2_RNDRST 0x40 +#define ENC_MACON2_MARXRST 0x08 +#define ENC_MACON2_RFUNRST 0x04 +#define ENC_MACON2_MATXRST 0x02 +#define ENC_MACON2_TFUNRST 0x01 + +/* + * MACON3 Register Bits + */ +#define ENC_MACON3_PADCFG2 0x80 +#define ENC_MACON3_PADCFG1 0x40 +#define ENC_MACON3_PADCFG0 0x20 +#define ENC_MACON3_TXCRCEN 0x10 +#define ENC_MACON3_PHDRLEN 0x08 +#define ENC_MACON3_HFRMEN 0x04 +#define ENC_MACON3_FRMLNEN 0x02 +#define ENC_MACON3_FULDPX 0x01 + +/* + * MICMD Register Bits + */ +#define ENC_MICMD_MIISCAN 0x02 +#define ENC_MICMD_MIIRD 0x01 + +/* + * MISTAT Register Bits + */ +#define ENC_MISTAT_NVALID 0x04 +#define ENC_MISTAT_SCAN 0x02 +#define ENC_MISTAT_BUSY 0x01 + +/* + * PHID1 and PHID2 values + */ +#define ENC_PHID1_VALUE 0x0083 +#define ENC_PHID2_VALUE 0x1400 +#define ENC_PHID2_MASK 0xFC00 + + +#define ENC_SPI_SLAVE_CS 0x00010000 /* pin P1.16 */ +#define ENC_RESET 0x00020000 /* pin P1.17 */ + +#define FAILSAFE_VALUE 5000 + +/* + * Controller memory layout: + * + * 0x0000 - 0x17ff 6k bytes receive buffer + * 0x1800 - 0x1fff 2k bytes transmit buffer + */ +/* Use the lower memory for receiver buffer. See errata pt. 5 */ +#define ENC_RX_BUF_START 0x0000 +#define ENC_TX_BUF_START 0x1800 +/* taken from the Linux driver */ +#define ENC_RX_BUF_END 0x17ff +#define ENC_TX_BUF_END 0x1fff + +/* maximum frame length */ +#define ENC_MAX_FRM_LEN 1518 + +#define enc_enable() PUT32(IO1CLR, ENC_SPI_SLAVE_CS) +#define enc_disable() PUT32(IO1SET, ENC_SPI_SLAVE_CS) +#define enc_cfg_spi() spi_set_cfg(0, 0, 0); spi_set_clock(8); + + +static unsigned char encReadReg (unsigned char regNo); +static void encWriteReg (unsigned char regNo, unsigned char data); +static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c); +static void encReadBuff (unsigned short length, unsigned char *pBuff); +static void encWriteBuff (unsigned short length, unsigned char *pBuff); +static void encBitSet (unsigned char regNo, unsigned char data); +static void encBitClr (unsigned char regNo, unsigned char data); +static void encReset (void); +static void encInit (unsigned char *pEthAddr); +static unsigned short phyRead (unsigned char addr); +static void phyWrite(unsigned char, unsigned short); +static void encPoll (void); +static void encRx (void); + +#define m_nic_read(reg) encReadReg(reg) +#define m_nic_write(reg, data) encWriteReg(reg, data) +#define m_nic_write_retry(reg, data, count) encWriteRegRetry(reg, data, count) +#define m_nic_read_data(len, buf) encReadBuff((len), (buf)) +#define m_nic_write_data(len, buf) encWriteBuff((len), (buf)) + +/* bit field set */ +#define m_nic_bfs(reg, data) encBitSet(reg, data) + +/* bit field clear */ +#define m_nic_bfc(reg, data) encBitClr(reg, data) + +static unsigned char bank = 0; /* current bank in enc28j60 */ +static unsigned char next_pointer_lsb; +static unsigned char next_pointer_msb; + +static unsigned char buffer[ENC_MAX_FRM_LEN]; +static int rxResetCounter = 0; + +#define RX_RESET_COUNTER 1000; + +/*----------------------------------------------------------------------------- + * Always returns 0 + */ +int eth_init (bd_t * bis) +{ + unsigned char estatVal; + + /* configure GPIO */ + (*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS; + (*((volatile unsigned long *) IO1DIR)) |= ENC_RESET; + + /* CS and RESET active low */ + PUT32 (IO1SET, ENC_SPI_SLAVE_CS); + PUT32 (IO1SET, ENC_RESET); + + spi_init (); + + /* taken from the Linux driver - dangerous stuff here! */ + /* Wait for CLKRDY to become set (i.e., check that we can communicate with + the ENC) */ + do + { + estatVal = m_nic_read(CTL_REG_ESTAT); + } while ((estatVal & 0x08) || (~estatVal & ENC_ESTAT_CLKRDY)); + + /* initialize controller */ + encReset (); + encInit (bis->bi_enetaddr); + + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */ + + return 0; +} + +int eth_send (volatile void *packet, int length) +{ + /* check frame length, etc. */ + /* TODO: */ + + /* switch to bank 0 */ + m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); + + /* set EWRPT */ + m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff)); + m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8)); + + /* set ETXND */ + m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF); + m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8); + + /* set ETXST */ + m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF); + m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8); + + /* write packet */ + m_nic_write_data (length, (unsigned char *) packet); + + /* taken from the Linux driver */ + /* Verify that the internal transmit logic has not been altered by excessive + collisions. See Errata B4 12 and 14. + */ + if (m_nic_read(CTL_REG_EIR) & ENC_EIR_TXERIF) { + m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_TXRST); + m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_TXRST); + } + m_nic_bfc(CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF)); + + /* set ECON1.TXRTS */ + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS); + + return 0; +} + + +/***************************************************************************** + * This function resets the receiver only. This function may be called from + * interrupt-context. + */ +static void encReceiverReset (void) +{ + unsigned char econ1; + + econ1 = m_nic_read (CTL_REG_ECON1); + if ((econ1 & ENC_ECON1_RXRST) == 0) { + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXRST); + rxResetCounter = RX_RESET_COUNTER; + } +} + +/***************************************************************************** + * receiver reset timer + */ +static void encReceiverResetCallback (void) +{ + m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXRST); + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_RXEN); /* enable receive */ +} + +/*----------------------------------------------------------------------------- + * Check for received packets. Call NetReceive for each packet. The return + * value is ignored by the caller. + */ +int eth_rx (void) +{ + if (rxResetCounter > 0 && --rxResetCounter == 0) { + encReceiverResetCallback (); + } + + encPoll (); + + return 0; +} + +void eth_halt (void) +{ + m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_RXEN); /* disable receive */ +} + +/*****************************************************************************/ + +static void encPoll (void) +{ + unsigned char eir_reg; + volatile unsigned char estat_reg; + unsigned char pkt_cnt; + +#ifdef CONFIG_USE_IRQ + /* clear global interrupt enable bit in enc28j60 */ + m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE); +#endif + estat_reg = m_nic_read (CTL_REG_ESTAT); + + eir_reg = m_nic_read (CTL_REG_EIR); + + if (eir_reg & ENC_EIR_TXIF) { + /* clear TXIF bit in EIR */ + m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXIF); + } + + /* We have to use pktcnt and not pktif bit, see errata pt. 6 */ + + /* move to bank 1 */ + m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1); + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0); + + /* read pktcnt */ + pkt_cnt = m_nic_read (CTL_REG_EPKTCNT); + + if (pkt_cnt > 0) { + if ((eir_reg & ENC_EIR_PKTIF) == 0) { + /*printf("encPoll: pkt cnt > 0, but pktif not set\n"); */ + } + encRx (); + /* clear PKTIF bit in EIR, this should not need to be done but it + seems like we get problems if we do not */ + m_nic_bfc (CTL_REG_EIR, ENC_EIR_PKTIF); + } + + if (eir_reg & ENC_EIR_RXERIF) { + printf ("encPoll: rx error\n"); + m_nic_bfc (CTL_REG_EIR, ENC_EIR_RXERIF); + } + if (eir_reg & ENC_EIR_TXERIF) { + printf ("encPoll: tx error\n"); + m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF); + } + +#ifdef CONFIG_USE_IRQ + /* set global interrupt enable bit in enc28j60 */ + m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE); +#endif +} + +static void encRx (void) +{ + unsigned short pkt_len; + unsigned short copy_len; + unsigned short status; + unsigned char eir_reg; + unsigned char pkt_cnt = 0; + unsigned short rxbuf_rdpt; + + /* switch to bank 0 */ + m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); + + m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb); + m_nic_write (CTL_REG_ERDPTH, next_pointer_msb); + + do { + m_nic_read_data (6, buffer); + next_pointer_lsb = buffer[0]; + next_pointer_msb = buffer[1]; + pkt_len = buffer[2]; + pkt_len |= (unsigned short) buffer[3] << 8; + status = buffer[4]; + status |= (unsigned short) buffer[5] << 8; + + if (pkt_len <= ENC_MAX_FRM_LEN) + copy_len = pkt_len; + else + copy_len = 0; + + if ((status & (1L << 7)) == 0) /* check Received Ok bit */ + copy_len = 0; + + /* taken from the Linux driver */ + /* check if next pointer is resonable */ + if ((((unsigned int)next_pointer_msb << 8) | + (unsigned int)next_pointer_lsb) >= ENC_TX_BUF_START) + copy_len = 0; + + if (copy_len > 0) { + m_nic_read_data (copy_len, buffer); + } + + /* advance read pointer to next pointer */ + m_nic_write (CTL_REG_ERDPTL, next_pointer_lsb); + m_nic_write (CTL_REG_ERDPTH, next_pointer_msb); + + /* decrease packet counter */ + m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC); + + /* taken from the Linux driver */ + /* Only odd values should be written to ERXRDPTL, see errata B4 pt.13 */ rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1; + if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 | + m_nic_read(CTL_REG_ERXSTL))) || (rxbuf_rdpt > + (m_nic_read(CTL_REG_ERXNDH) << 8 | + m_nic_read(CTL_REG_ERXNDL)))) { + m_nic_write(CTL_REG_ERXRDPTL, m_nic_read(CTL_REG_ERXNDL)); + m_nic_write(CTL_REG_ERXRDPTH, m_nic_read(CTL_REG_ERXNDH)); + } else { + m_nic_write(CTL_REG_ERXRDPTL, rxbuf_rdpt & 0xFF); + m_nic_write(CTL_REG_ERXRDPTH, rxbuf_rdpt >> 8); + } + + /* move to bank 1 */ + m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1); + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0); + + /* read pktcnt */ + pkt_cnt = m_nic_read (CTL_REG_EPKTCNT); + + /* switch to bank 0 */ + m_nic_bfc (CTL_REG_ECON1, + (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); + + if (copy_len == 0) { + eir_reg = m_nic_read (CTL_REG_EIR); + encReceiverReset (); + printf ("eth_rx: copy_len=0\n"); + continue; + } + + NetReceive ((unsigned char *) buffer, pkt_len); + + eir_reg = m_nic_read (CTL_REG_EIR); + } while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */ +} + +static void encWriteReg (unsigned char regNo, unsigned char data) +{ + spi_lock (); + enc_cfg_spi (); + enc_enable (); + + spi_write (0x40 | regNo); /* write in regNo */ + spi_write (data); + + enc_disable (); + enc_enable (); + + spi_write (0x1f); /* write reg 0x1f */ + + enc_disable (); + spi_unlock (); +} + +static void encWriteRegRetry (unsigned char regNo, unsigned char data, int c) +{ + unsigned char readback; + int i; + + spi_lock (); + + for (i = 0; i < c; i++) { + enc_cfg_spi (); + enc_enable (); + + spi_write (0x40 | regNo); /* write in regNo */ + spi_write (data); + + enc_disable (); + enc_enable (); + + spi_write (0x1f); /* write reg 0x1f */ + + enc_disable (); + + spi_unlock (); /* we must unlock spi first */ + + readback = encReadReg (regNo); + + spi_lock (); + + if (readback == data) + break; + } + spi_unlock (); + + if (i == c) { + printf ("enc28j60: write reg %d failed\n", regNo); + } +} + +static unsigned char encReadReg (unsigned char regNo) +{ + unsigned char rxByte; + + spi_lock (); + enc_cfg_spi (); + enc_enable (); + + spi_write (0x1f); /* read reg 0x1f */ + + bank = spi_read () & 0x3; + + enc_disable (); + enc_enable (); + + spi_write (regNo); + rxByte = spi_read (); + + /* check if MAC or MII register */ + if (((bank == 2) && (regNo <= 0x1a)) || + ((bank == 3) && (regNo <= 0x05 || regNo == 0x0a))) { + /* ignore first byte and read another byte */ + rxByte = spi_read (); + } + + enc_disable (); + spi_unlock (); + + return rxByte; +} + +static void encReadBuff (unsigned short length, unsigned char *pBuff) +{ + spi_lock (); + enc_cfg_spi (); + enc_enable (); + + spi_write (0x20 | 0x1a); /* read buffer memory */ + + while (length--) { + if (pBuff != NULL) + *pBuff++ = spi_read (); + else + spi_write (0); + } + + enc_disable (); + spi_unlock (); +} + +static void encWriteBuff (unsigned short length, unsigned char *pBuff) +{ + spi_lock (); + enc_cfg_spi (); + enc_enable (); + + spi_write (0x60 | 0x1a); /* write buffer memory */ + + spi_write (0x00); /* control byte */ + + while (length--) + spi_write (*pBuff++); + + enc_disable (); + spi_unlock (); +} + +static void encBitSet (unsigned char regNo, unsigned char data) +{ + spi_lock (); + enc_cfg_spi (); + enc_enable (); + + spi_write (0x80 | regNo); /* bit field set */ + spi_write (data); + + enc_disable (); + spi_unlock (); +} + +static void encBitClr (unsigned char regNo, unsigned char data) +{ + spi_lock (); + enc_cfg_spi (); + enc_enable (); + + spi_write (0xA0 | regNo); /* bit field clear */ + spi_write (data); + + enc_disable (); + spi_unlock (); +} + +static void encReset (void) +{ + spi_lock (); + enc_cfg_spi (); + enc_enable (); + + spi_write (0xff); /* soft reset */ + + enc_disable (); + spi_unlock (); + + /* sleep 1 ms. See errata pt. 2 */ + udelay (1000); +} + +static void encInit (unsigned char *pEthAddr) +{ + unsigned short phid1 = 0; + unsigned short phid2 = 0; + + /* switch to bank 0 */ + m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0)); + + /* + * Setup the buffer space. The reset values are valid for the + * other pointers. + */ + /* We shall not write to ERXST, see errata pt. 5. Instead we + have to make sure that ENC_RX_BUS_START is 0. */ + m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1); + m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1); + + /* taken from the Linux driver */ + m_nic_write_retry (CTL_REG_ERXNDL, (ENC_RX_BUF_END & 0xFF), 1); + m_nic_write_retry (CTL_REG_ERXNDH, (ENC_RX_BUF_END >> 8), 1); + + m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1); + m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1); + + next_pointer_lsb = (ENC_RX_BUF_START & 0xFF); + next_pointer_msb = (ENC_RX_BUF_START >> 8); + + /* verify identification */ + phid1 = phyRead (PHY_REG_PHID1); + phid2 = phyRead (PHY_REG_PHID2); + + if (phid1 != ENC_PHID1_VALUE + || (phid2 & ENC_PHID2_MASK) != ENC_PHID2_VALUE) { + printf ("ERROR: failed to identify controller\n"); + printf ("phid1 = %x, phid2 = %x\n", + phid1, (phid2 & ENC_PHID2_MASK)); + printf ("should be phid1 = %x, phid2 = %x\n", + ENC_PHID1_VALUE, ENC_PHID2_VALUE); + } + + /* + * --- MAC Initialization --- + */ + + /* Pull MAC out of Reset */ + + /* switch to bank 2 */ + m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0); + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1); + + /* enable MAC to receive frames */ + /* added some bits from the Linux driver */ + m_nic_write_retry (CTL_REG_MACON1, (ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS), 10); + + /* configure pad, tx-crc and duplex */ + /* added a bit from the Linux driver */ + m_nic_write_retry (CTL_REG_MACON3, + (ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN), + 10); + + /* added 4 new lines from the Linux driver */ + /* Allow infinite deferals if the medium is continously busy */ + m_nic_write_retry(CTL_REG_MACON4, (1<<6) /*ENC_MACON4_DEFER*/, 10); + + /* Late collisions occur beyond 63 bytes */ + m_nic_write_retry(CTL_REG_MACLCON2, 63, 10); + + /* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */ + m_nic_write_retry(CTL_REG_MAIPGL, 0x12, 10); + + /* + * Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended + * 0x0c for half-duplex. Nothing for full-duplex + */ + m_nic_write_retry(CTL_REG_MAIPGH, 0x0C, 10); + + /* set maximum frame length */ + m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10); + m_nic_write_retry (CTL_REG_MAMXFLH, (ENC_MAX_FRM_LEN >> 8), 10); + + /* + * Set MAC back-to-back inter-packet gap. Recommended 0x12 for half duplex + * and 0x15 for full duplex. + */ + m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10); + + /* set MAC address */ + + /* switch to bank 3 */ + m_nic_bfs (CTL_REG_ECON1, (ENC_ECON1_BSEL0 | ENC_ECON1_BSEL1)); + + m_nic_write_retry (CTL_REG_MAADR0, pEthAddr[5], 1); + m_nic_write_retry (CTL_REG_MAADR1, pEthAddr[4], 1); + m_nic_write_retry (CTL_REG_MAADR2, pEthAddr[3], 1); + m_nic_write_retry (CTL_REG_MAADR3, pEthAddr[2], 1); + m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1); + m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1); + + /* + * PHY Initialization taken from the Linux driver + */ + + /* Prevent automatic loopback of data beeing transmitted by setting + ENC_PHCON2_HDLDIS */ + phyWrite(PHY_REG_PHCON2, (1<<8)); + + /* LEDs configuration + * LEDA: LACFG = 0100 -> display link status + * LEDB: LBCFG = 0111 -> display TX & RX activity + * STRCH = 1 -> LED pulses + */ + phyWrite(PHY_REG_PHLCON, 0x0472); + + /* Reset PDPXMD-bit => half duplex */ + phyWrite(PHY_REG_PHCON1, 0); + + /* + * Receive settings + */ + +#ifdef CONFIG_USE_IRQ + /* enable interrupts */ + m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE); + m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE); + m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE); + m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE); + m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE); +#endif +} + +/***************************************************************************** + * + * Description: + * Read PHY registers. + * + * NOTE! This function will change to Bank 2. + * + * Params: + * [in] addr address of the register to read + * + * Returns: + * The value in the register + */ +static unsigned short phyRead (unsigned char addr) +{ + unsigned short ret = 0; + + /* move to bank 2 */ + m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0); + m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1); + + /* write address to MIREGADR */ + m_nic_write (CTL_REG_MIREGADR, addr); + + /* set MICMD.MIIRD */ + m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD); + + /* taken from the Linux driver */ + /* move to bank 3 */ + m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0); + m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); + + /* poll MISTAT.BUSY bit until operation is complete */ + while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) { + static int cnt = 0; + + if (cnt++ >= 1000) { + /* GJ - this seems extremely dangerous! */ + /* printf("#"); */ + cnt = 0; + } + } + + /* taken from the Linux driver */ + /* move to bank 2 */ + m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0); + m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); + + /* clear MICMD.MIIRD */ + m_nic_write (CTL_REG_MICMD, 0); + + ret = (m_nic_read (CTL_REG_MIRDH) << 8); + ret |= (m_nic_read (CTL_REG_MIRDL) & 0xFF); + + return ret; +} + +/***************************************************************************** + * + * Taken from the Linux driver. + * Description: + * Write PHY registers. + * + * NOTE! This function will change to Bank 3. + * + * Params: + * [in] addr address of the register to write to + * [in] data to be written + * + * Returns: + * None + */ +static void phyWrite(unsigned char addr, unsigned short data) +{ + /* move to bank 2 */ + m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0); + m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); + + /* write address to MIREGADR */ + m_nic_write(CTL_REG_MIREGADR, addr); + + m_nic_write(CTL_REG_MIWRL, data & 0xff); + m_nic_write(CTL_REG_MIWRH, data >> 8); + + /* move to bank 3 */ + m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0); + m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1); + + /* poll MISTAT.BUSY bit until operation is complete */ + while((m_nic_read(CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) { + static int cnt = 0; + + if(cnt++ >= 1000) { + cnt = 0; + } + } +} + +#endif /* CONFIG_ENC28J60 */ diff --git a/include/asm-arm/arch-lpc2292/hardware.h b/include/asm-arm/arch-lpc2292/hardware.h new file mode 100644 index 00000000000..fd2b464e37b --- /dev/null +++ b/include/asm-arm/arch-lpc2292/hardware.h @@ -0,0 +1,33 @@ +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* + * Copyright (c) 2004 Cucy Systems (http://www.cucy.com) + * Curt Brune + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#if defined(CONFIG_LPC2292) +#include +#else +#error No hardware file defined for this configuration +#endif + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-lpc2292/lpc2292_registers.h b/include/asm-arm/arch-lpc2292/lpc2292_registers.h new file mode 100644 index 00000000000..5715f3ef745 --- /dev/null +++ b/include/asm-arm/arch-lpc2292/lpc2292_registers.h @@ -0,0 +1,225 @@ +#ifndef __LPC2292_REGISTERS_H +#define __LPC2292_REGISTERS_H + +#include + +/* Macros for reading/writing registers */ +#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value)) +#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value)) +#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value)) +#define GET8(reg) (*(volatile unsigned char*)(reg)) +#define GET16(reg) (*(volatile unsigned short*)(reg)) +#define GET32(reg) (*(volatile unsigned int*)(reg)) + +/* External Memory Controller */ + +#define BCFG0 0xFFE00000 /* 32-bits */ +#define BCFG1 0xFFE00004 /* 32-bits */ +#define BCFG2 0xFFE00008 /* 32-bits */ +#define BCFG3 0xFFE0000c /* 32-bits */ + +/* System Control Block */ + +#define EXTINT 0xE01FC140 +#define EXTWAKE 0xE01FC144 +#define EXTMODE 0xE01FC148 +#define EXTPOLAR 0xE01FC14C +#define MEMMAP 0xE01FC040 +#define PLLCON 0xE01FC080 +#define PLLCFG 0xE01FC084 +#define PLLSTAT 0xE01FC088 +#define PLLFEED 0xE01FC08C +#define PCON 0xE01FC0C0 +#define PCONP 0xE01FC0C4 +#define VPBDIV 0xE01FC100 + +/* Memory Acceleration Module */ + +#define MAMCR 0xE01FC000 +#define MAMTIM 0xE01FC004 + +/* Vectored Interrupt Controller */ + +#define VICIRQStatus 0xFFFFF000 +#define VICFIQStatus 0xFFFFF004 +#define VICRawIntr 0xFFFFF008 +#define VICIntSelect 0xFFFFF00C +#define VICIntEnable 0xFFFFF010 +#define VICIntEnClr 0xFFFFF014 +#define VICSoftInt 0xFFFFF018 +#define VICSoftIntClear 0xFFFFF01C +#define VICProtection 0xFFFFF020 +#define VICVectAddr 0xFFFFF030 +#define VICDefVectAddr 0xFFFFF034 +#define VICVectAddr0 0xFFFFF100 +#define VICVectAddr1 0xFFFFF104 +#define VICVectAddr2 0xFFFFF108 +#define VICVectAddr3 0xFFFFF10C +#define VICVectAddr4 0xFFFFF110 +#define VICVectAddr5 0xFFFFF114 +#define VICVectAddr6 0xFFFFF118 +#define VICVectAddr7 0xFFFFF11C +#define VICVectAddr8 0xFFFFF120 +#define VICVectAddr9 0xFFFFF124 +#define VICVectAddr10 0xFFFFF128 +#define VICVectAddr11 0xFFFFF12C +#define VICVectAddr12 0xFFFFF130 +#define VICVectAddr13 0xFFFFF134 +#define VICVectAddr14 0xFFFFF138 +#define VICVectAddr15 0xFFFFF13C +#define VICVectCntl0 0xFFFFF200 +#define VICVectCntl1 0xFFFFF204 +#define VICVectCntl2 0xFFFFF208 +#define VICVectCntl3 0xFFFFF20C +#define VICVectCntl4 0xFFFFF210 +#define VICVectCntl5 0xFFFFF214 +#define VICVectCntl6 0xFFFFF218 +#define VICVectCntl7 0xFFFFF21C +#define VICVectCntl8 0xFFFFF220 +#define VICVectCntl9 0xFFFFF224 +#define VICVectCntl10 0xFFFFF228 +#define VICVectCntl11 0xFFFFF22C +#define VICVectCntl12 0xFFFFF230 +#define VICVectCntl13 0xFFFFF234 +#define VICVectCntl14 0xFFFFF238 +#define VICVectCntl15 0xFFFFF23C + +/* Pin connect block */ + +#define PINSEL0 0xE002C000 /* 32 bits */ +#define PINSEL1 0xE002C004 /* 32 bits */ +#define PINSEL2 0xE002C014 /* 32 bits */ + +/* GPIO */ + +#define IO0PIN 0xE0028000 +#define IO0SET 0xE0028004 +#define IO0DIR 0xE0028008 +#define IO0CLR 0xE002800C +#define IO1PIN 0xE0028010 +#define IO1SET 0xE0028014 +#define IO1DIR 0xE0028018 +#define IO1CLR 0xE002801C +#define IO2PIN 0xE0028020 +#define IO2SET 0xE0028024 +#define IO2DIR 0xE0028028 +#define IO2CLR 0xE002802C +#define IO3PIN 0xE0028030 +#define IO3SET 0xE0028034 +#define IO3DIR 0xE0028038 +#define IO3CLR 0xE002803C + +/* Uarts */ + +#define U0RBR 0xE000C000 +#define U0THR 0xE000C000 +#define U0IER 0xE000C004 +#define U0IIR 0xE000C008 +#define U0FCR 0xE000C008 +#define U0LCR 0xE000C00C +#define U0LSR 0xE000C014 +#define U0SCR 0xE000C01C +#define U0DLL 0xE000C000 +#define U0DLM 0xE000C004 + +#define U1RBR 0xE0010000 +#define U1THR 0xE0010000 +#define U1IER 0xE0010004 +#define U1IIR 0xE0010008 +#define U1FCR 0xE0010008 +#define U1LCR 0xE001000C +#define U1MCR 0xE0010010 +#define U1LSR 0xE0010014 +#define U1MSR 0xE0010018 +#define U1SCR 0xE001001C +#define U1DLL 0xE0010000 +#define U1DLM 0xE0010004 + +/* I2C */ + +#define I2CONSET 0xE001C000 +#define I2STAT 0xE001C004 +#define I2DAT 0xE001C008 +#define I2ADR 0xE001C00C +#define I2SCLH 0xE001C010 +#define I2SCLL 0xE001C014 +#define I2CONCLR 0xE001C018 + +/* SPI */ + +#define S0SPCR 0xE0020000 +#define S0SPSR 0xE0020004 +#define S0SPDR 0xE0020008 +#define S0SPCCR 0xE002000C +#define S0SPINT 0xE002001C + +#define S1SPCR 0xE0030000 +#define S1SPSR 0xE0030004 +#define S1SPDR 0xE0030008 +#define S1SPCCR 0xE003000C +#define S1SPINT 0xE003001C + +/* CAN controller */ + +/* skip for now */ + +/* Timers */ + +#define T0IR 0xE0004000 +#define T0TCR 0xE0004004 +#define T0TC 0xE0004008 +#define T0PR 0xE000400C +#define T0PC 0xE0004010 +#define T0MCR 0xE0004014 +#define T0MR0 0xE0004018 +#define T0MR1 0xE000401C +#define T0MR2 0xE0004020 +#define T0MR3 0xE0004024 +#define T0CCR 0xE0004028 +#define T0CR0 0xE000402C +#define T0CR1 0xE0004030 +#define T0CR2 0xE0004034 +#define T0CR3 0xE0004038 +#define T0EMR 0xE000403C + +#define T1IR 0xE0008000 +#define T1TCR 0xE0008004 +#define T1TC 0xE0008008 +#define T1PR 0xE000800C +#define T1PC 0xE0008010 +#define T1MCR 0xE0008014 +#define T1MR0 0xE0008018 +#define T1MR1 0xE000801C +#define T1MR2 0xE0008020 +#define T1MR3 0xE0008024 +#define T1CCR 0xE0008028 +#define T1CR0 0xE000802C +#define T1CR1 0xE0008030 +#define T1CR2 0xE0008034 +#define T1CR3 0xE0008038 +#define T1EMR 0xE000803C + +/* PWM */ + +/* skip for now */ + +/* A/D converter */ + +/* skip for now */ + +/* Real Time Clock */ + +/* skip for now */ + +/* Watchdog */ + +#define WDMOD 0xE0000000 +#define WDTC 0xE0000004 +#define WDFEED 0xE0000008 +#define WDTV 0xE000000C + +/* EmbeddedICE LOGIC */ + +/* skip for now */ + +#endif diff --git a/include/asm-arm/arch-lpc2292/mmc.h b/include/asm-arm/arch-lpc2292/mmc.h new file mode 100644 index 00000000000..e664a5f6789 --- /dev/null +++ b/include/asm-arm/arch-lpc2292/mmc.h @@ -0,0 +1,22 @@ +/* + * A dummy header file for use with the LPC2292 port to keep the + * compiler happy. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _MMC_ARM_TDM_H_ +#define _MMC_ARM_TDM_H_ +#endif /* _MMC_ARM_TDM_H_ */ diff --git a/include/asm-arm/arch-lpc2292/spi.h b/include/asm-arm/arch-lpc2292/spi.h new file mode 100644 index 00000000000..6ae66e8ba74 --- /dev/null +++ b/include/asm-arm/arch-lpc2292/spi.h @@ -0,0 +1,82 @@ +/* + This file defines the interface to the lpc22xx SPI module. + Copyright (C) 2006 Embedded Artists AB (www.embeddedartists.com) + + This file may be included in software not adhering to the GPL. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +*/ + +#ifndef SPI_H +#define SPI_H + +#include +#include +#include +#include + +#define SPIF 0x80 + +#define spi_lock() disable_interrupts(); +#define spi_unlock() enable_interrupts(); + +extern unsigned long spi_flags; +extern unsigned char spi_idle; + +int spi_init(void); + +static inline unsigned char spi_read(void) +{ + unsigned char b; + + PUT8(S0SPDR, spi_idle); + while (!(GET8(S0SPSR) & SPIF)); + b = GET8(S0SPDR); + + return b; +} + +static inline void spi_write(unsigned char b) +{ + PUT8(S0SPDR, b); + while (!(GET8(S0SPSR) & SPIF)); + GET8(S0SPDR); /* this will clear the SPIF bit */ +} + +static inline void spi_set_clock(unsigned char clk_value) +{ + PUT8(S0SPCCR, clk_value); +} + +static inline void spi_set_cfg(unsigned char phase, + unsigned char polarity, + unsigned char lsbf) +{ + unsigned char v = 0x20; /* master bit set */ + + if (phase) + v |= 0x08; /* set phase bit */ + if (polarity) { + v |= 0x10; /* set polarity bit */ + spi_idle = 0xFF; + } else { + spi_idle = 0x00; + } + if (lsbf) + v |= 0x40; /* set lsbf bit */ + + PUT8(S0SPCR, v); +} +#endif /* SPI_H */ diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h new file mode 100644 index 00000000000..41330e9dbee --- /dev/null +++ b/include/configs/SMN42.h @@ -0,0 +1,198 @@ +/* + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Configuation settings for the SMN42 board from Siemens. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * If we are developing, we might want to start u-boot from ram + * so we MUST NOT initialize critical regs like mem-timing ... + */ +#undef CONFIG_INIT_CRITICAL /* undef for developing */ + +#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_ARM7 1 /* This is a ARM7 CPU */ +#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ +#define CONFIG_LPC2292 +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ + +#undef CONFIG_USE_IRQ /* don't need them anymore */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_SERIAL1 1 /* we use Serial line 1 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +/* this would be 0xAE if E0, E1 and E2 were pulled high */ +#define CFG_I2C_SLAVE 0xA0 +#define CFG_I2C_EEPROM_ADDR (0xA0 >> 1) +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit address */ +#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes per write */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +/* not used but required by devices.c */ +#define CFG_I2C_SPEED 10000 + +#ifdef CONFIG_SOFT_I2C +/* + * Software (bit-bang) I2C driver configuration + */ +#define SCL 0x00000004 /* P0.2 */ +#define SDA 0x00000008 /* P0.3 */ + +#define I2C_READ ((GET32(IO0PIN) & SDA) ? 1 : 0) +#define I2C_SDA(x) { if (x) PUT32(IO0SET, SDA); else PUT32(IO0CLR, SDA); } +#define I2C_SCL(x) { if (x) PUT32(IO0SET, SCL); else PUT32(IO0CLR, SCL); } +#define I2C_DELAY { udelay(100); } +#define I2C_ACTIVE { unsigned int i2ctmp; \ + i2ctmp = GET32(IO0DIR); \ + i2ctmp |= SDA; \ + PUT32(IO0DIR, i2ctmp); } +#define I2C_TRISTATE { unsigned int i2ctmp; \ + i2ctmp = GET32(IO0DIR); \ + i2ctmp &= ~SDA; \ + PUT32(IO0DIR, i2ctmp); } +#endif /* CONFIG_SOFT_I2C */ + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_DHCP | \ + CFG_CMD_FAT | \ + CFG_CMD_MMC | \ + CFG_CMD_NET | \ + CFG_CMD_EEPROM | \ + CFG_CMD_PING) + +#define CONFIG_DOS_PARTITION + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 5 + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "SMN42 # " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x81800000 /* memtest works on */ +#define CFG_MEMTEST_END 0x83000000 /* 24 MB in SRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x81000000 /* default load address for uClinux img is here*/ + +#define CFG_SYS_CLK_FREQ 58982400 /* Hz */ +#define CFG_HZ 2048 /* decrementer freq in Hz */ + + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SRAM */ +#define PHYS_SDRAM_1 0x81000000 /* SRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB SRAM */ + +/* This is the external flash */ +#define PHYS_FLASH_1 0x80000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* + * The first entry in CFG_FLASH_BANKS_LIST is a dummy, but it must be present. + */ +#define CFG_FLASH_BANKS_LIST { 0, PHYS_FLASH_1 } +#define CFG_FLASH_ADDR0 0x555 +#define CFG_FLASH_ADDR1 0x2AA +#define CFG_FLASH_ERASE_TOUT 16384 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ + +#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ + +#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ + +#define CFG_ENV_IS_IN_FLASH 1 +/* The Environment Sector is in the CPU-internal flash */ +#define CFG_FLASH_BASE 0 +#define CFG_ENV_OFFSET 0x3C000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_MMC 1 +/* we use this ethernet chip */ +#define CONFIG_ENC28J60 + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 56fd7162985c412317bbf763a225fba23c64fd31 Mon Sep 17 00:00:00 2001 From: Stephen Williams Date: Tue, 15 May 2007 07:55:42 -0700 Subject: Fix for compile of JSE target The attached patch fixes the compile of the JSE board in the denx git as of 14 may 2007. It is an extremely simple patch, it just adds the missing define of CFG_SYSTEMACE_WIDTH. Fix to compile JSE against 20070514 git of u-boot --- include/configs/JSE.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/JSE.h b/include/configs/JSE.h index ccd1f19903b..7fa9ed2d42a 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -49,6 +49,7 @@ /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */ #define CONFIG_SYSTEMACE 1 #define CFG_SYSTEMACE_BASE 0xf0000000 +#define CFG_SYSTEMACE_WIDTH 8 #define CONFIG_DOS_PARTITION 1 /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ -- cgit v1.3.1 From 66d9dbec1cc27d6398ee6cf84639dbe14971251e Mon Sep 17 00:00:00 2001 From: mushtaq khan Date: Fri, 20 Apr 2007 14:23:02 +0530 Subject: Add driver for S-ATA-controller on Intel processors with South Bridge, ICH-5, ICH-6 and ICH-7. Implementation: 1. Code is divided in to two files. All functions, which are controller specific are kept in "drivers/ata_piix.c" file and functions, which are not controller specific, are kept in "common/cmd_sata.c" file. 2. Reading and Writing from the S-ATA drive is done using PIO method. 3. Driver can be configured for 48-bit addressing by defining macro CONFIG_LBA48, if this macro is not defined driver uses the 28-bit addressing. 4. S-ATA read function is hooked to the File system, commands like ext2ls and ext2load file can be used. This has been tested. 5. U-Boot command "SATA_init" is added, which initializes the S-ATA controller and identifies the S-ATA drives connected to it. 6. U-Boot command "sata" is added, which is used to read/write, print partition table and get info about the drives present. This I have implemented in same way as "ide" command is implemented in U-Boot. 7. This driver is for S-ATA in native mode. 8. This driver does not support the Native command queuing and Hot-plugging. Signed-off-by: Mushtaq Khan --- common/Makefile | 4 +- common/cmd_sata.c | 710 ++++++++++++++++++++++++++++++++++++++++++++ drivers/Makefile | 2 +- drivers/ata_piix.c | 216 ++++++++++++++ include/ata.h | 60 ++++ include/configs/sc520_cdp.h | 9 + include/sata.h | 108 +++++++ 7 files changed, 1106 insertions(+), 3 deletions(-) create mode 100644 common/cmd_sata.c create mode 100644 drivers/ata_piix.c create mode 100644 include/sata.h (limited to 'include') diff --git a/common/Makefile b/common/Makefile index 5dfd3a84a24..1e4ce312cd2 100644 --- a/common/Makefile +++ b/common/Makefile @@ -38,8 +38,8 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \ cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \ cmd_nand.o cmd_net.o cmd_nvedit.o \ cmd_pci.o cmd_pcmcia.o cmd_portio.o \ - cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \ - cmd_usb.o cmd_vfd.o \ + cmd_reginfo.o cmd_reiser.o cmd_sata.o cmd_scsi.o cmd_spi.o \ + cmd_universe.o cmd_usb.o cmd_vfd.o \ command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \ environment.o env_common.o \ env_nand.o env_dataflash.o env_flash.o env_eeprom.o \ diff --git a/common/cmd_sata.c b/common/cmd_sata.c new file mode 100644 index 00000000000..1c71b6471d9 --- /dev/null +++ b/common/cmd_sata.c @@ -0,0 +1,710 @@ +/* + * Copyright (C) Procsys. All rights reserved. + * Author: Mushtaq Khan + + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference to libata in kernel 2.4.32 + * +*/ + +/*File contains SATA read-write and other utility functions.*/ +#include +#include +#include +#include +#include +#include +#include + +#ifdef CFG_SATA_SUPPORTED +/*For debug prints set macro DEBUG_SATA to 1 */ +#define DEBUG_SATA 0 +/*Macro for SATA library specific declarations */ +#define SATA_DECL +#include +#undef SATA_DECL + +static u8 __inline__ +sata_inb (unsigned long ioaddr) +{ + return inb (ioaddr); +} + +static void __inline__ +sata_outb (unsigned char val, unsigned long ioaddr) +{ + outb (val, ioaddr); +} + +static void +output_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words) +{ + outsw (ioaddr->data_addr, sect_buf, words << 1); +} + +static int +input_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words) +{ + insw (ioaddr->data_addr, sect_buf, words << 1); + return 0; +} + +static void +sata_cpy (unsigned char *dst, unsigned char *src, unsigned int len) +{ + unsigned char *end, *last; + + last = dst; + end = src + len - 1; + + /* reserve space for '\0' */ + if (len < 2) + goto OUT; + + /* skip leading white space */ + while ((*src) && (src < end) && (*src == ' ')) + ++src; + + /* copy string, omitting trailing white space */ + while ((*src) && (src < end)) { + *dst++ = *src; + if (*src++ != ' ') + last = dst; + } + OUT: + *last = '\0'; +} + +int +sata_bus_softreset (int num) +{ + u8 dev = 0, status = 0, i; + + port[num].dev_mask = 0; + + for (i = 0; i < CFG_SATA_DEVS_PER_BUS; i++) { + if (!(sata_devchk (&port[num].ioaddr, i))) { + PRINTF ("dev_chk failed for dev#%d\n", i); + } else { + port[num].dev_mask |= (1 << i); + PRINTF ("dev_chk passed for dev#%d\n", i); + } + } + + if (!(port[num].dev_mask)) { + printf ("no devices on port%d\n", num); + return 1; + } + + dev_select (&port[num].ioaddr, dev); + + port[num].ctl_reg = 0x08; /*Default value of control reg */ + sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); + udelay (10); + sata_outb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr); + udelay (10); + sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr); + + /* spec mandates ">= 2ms" before checking status. + * We wait 150ms, because that was the magic delay used for + * ATAPI devices in Hale Landis's ATADRVR, for the period of time + * between when the ATA command register is written, and then + * status is checked. Because waiting for "a while" before + * checking status is fine, post SRST, we perform this magic + * delay here as well. + */ + msleep (150); + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300); + while ((status & ATA_BUSY)) { + msleep (100); + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3); + } + + if (status & ATA_BUSY) + printf ("ata%u is slow to respond,plz be patient\n", port); + + while ((status & ATA_BUSY)) { + msleep (100); + status = sata_chk_status (&port[num].ioaddr); + } + + if (status & ATA_BUSY) { + printf ("ata%u failed to respond : ", port); + printf ("bus reset failed\n"); + return 1; + } + return 0; +} + +void +sata_identify (int num, int dev) +{ + u8 cmd = 0, status = 0, devno = num * CFG_SATA_DEVS_PER_BUS + dev; + u16 iobuf[ATA_SECT_SIZE]; + u64 n_sectors = 0; + u8 mask = 0; + + memset (iobuf, 0, sizeof (iobuf)); + hd_driveid_t *iop = (hd_driveid_t *) iobuf; + + if (dev == 0) + mask = 0x01; + else + mask = 0x02; + + if (!(port[num].dev_mask & mask)) { + printf ("dev%d is not present on port#%d\n", dev, num); + return; + } + + printf ("port=%d dev=%d\n", num, dev); + + dev_select (&port[num].ioaddr, dev); + + status = 0; + cmd = ATA_CMD_IDENT; /*Device Identify Command */ + sata_outb (cmd, port[num].ioaddr.command_addr); + sata_inb (port[num].ioaddr.altstatus_addr); + udelay (10); + + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000); + if (status & ATA_ERR) { + printf ("\ndevice not responding\n"); + port[num].dev_mask &= ~mask; + return; + } + + input_data (&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS); + + PRINTF ("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x" + "86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49], + iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86], + iobuf[87], iobuf[88]); + + /* we require LBA and DMA support (bits 8 & 9 of word 49) */ + if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) { + PRINTF ("ata%u: no dma/lba\n", num); + } + ata_dump_id (iobuf); + + if (ata_id_has_lba48 (iobuf)) { + n_sectors = ata_id_u64 (iobuf, 100); + } else { + n_sectors = ata_id_u32 (iobuf, 60); + } + PRINTF ("no. of sectors %u\n", ata_id_u64 (iobuf, 100)); + PRINTF ("no. of sectors %u\n", ata_id_u32 (iobuf, 60)); + + if (n_sectors == 0) { + port[num].dev_mask &= ~mask; + return; + } + + sata_cpy (sata_dev_desc[devno].revision, iop->fw_rev, + sizeof (sata_dev_desc[devno].revision)); + sata_cpy (sata_dev_desc[devno].vendor, iop->model, + sizeof (sata_dev_desc[devno].vendor)); + sata_cpy (sata_dev_desc[devno].product, iop->serial_no, + sizeof (sata_dev_desc[devno].product)); + strswab (sata_dev_desc[devno].revision); + strswab (sata_dev_desc[devno].vendor); + + if ((iop->config & 0x0080) == 0x0080) { + sata_dev_desc[devno].removable = 1; + } else { + sata_dev_desc[devno].removable = 0; + } + + sata_dev_desc[devno].lba = iop->lba_capacity; + PRINTF ("lba=0x%x", sata_dev_desc[devno].lba); + +#ifdef CONFIG_LBA48 + if (iop->command_set_2 & 0x0400) { + sata_dev_desc[devno].lba48 = 1; + lba = (unsigned long long) iop->lba48_capacity[0] | + ((unsigned long long) iop->lba48_capacity[1] << 16) | + ((unsigned long long) iop->lba48_capacity[2] << 32) | + ((unsigned long long) iop->lba48_capacity[3] << 48); + } else { + sata_dev_desc[devno].lba48 = 0; + } +#endif + + /* assuming HD */ + sata_dev_desc[devno].type = DEV_TYPE_HARDDISK; + sata_dev_desc[devno].blksz = ATA_BLOCKSIZE; + sata_dev_desc[devno].lun = 0; /* just to fill something in... */ +} + +void +set_Feature_cmd (int num, int dev) +{ + u8 mask = 0x00, status = 0; + + if (dev == 0) + mask = 0x01; + else + mask = 0x02; + + if (!(port[num].dev_mask & mask)) { + PRINTF ("dev%d is not present on port#%d\n", dev, num); + return; + } + + dev_select (&port[num].ioaddr, dev); + + sata_outb (SETFEATURES_XFER, port[num].ioaddr.feature_addr); + sata_outb (XFER_PIO_4, port[num].ioaddr.nsect_addr); + sata_outb (0, port[num].ioaddr.lbal_addr); + sata_outb (0, port[num].ioaddr.lbam_addr); + sata_outb (0, port[num].ioaddr.lbah_addr); + + sata_outb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr); + sata_outb (ATA_CMD_SETF, port[num].ioaddr.command_addr); + + udelay (50); + msleep (150); + + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000); + if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) { + printf ("Error : status 0x%02x\n", status); + port[num].dev_mask &= ~mask; + } +} + +void +sata_port (struct sata_ioports *ioport) +{ + ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA; + ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR; + ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE; + ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT; + ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL; + ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM; + ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH; + ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE; + ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS; + ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD; +} + +int +sata_devchk (struct sata_ioports *ioaddr, int dev) +{ + u8 nsect, lbal; + + dev_select (ioaddr, dev); + + sata_outb (0x55, ioaddr->nsect_addr); + sata_outb (0xaa, ioaddr->lbal_addr); + + sata_outb (0xaa, ioaddr->nsect_addr); + sata_outb (0x55, ioaddr->lbal_addr); + + sata_outb (0x55, ioaddr->nsect_addr); + sata_outb (0xaa, ioaddr->lbal_addr); + + nsect = sata_inb (ioaddr->nsect_addr); + lbal = sata_inb (ioaddr->lbal_addr); + + if ((nsect == 0x55) && (lbal == 0xaa)) + return 1; /* we found a device */ + else + return 0; /* nothing found */ +} + +void +dev_select (struct sata_ioports *ioaddr, int dev) +{ + u8 tmp = 0; + + if (dev == 0) + tmp = ATA_DEVICE_OBS; + else + tmp = ATA_DEVICE_OBS | ATA_DEV1; + + sata_outb (tmp, ioaddr->device_addr); + sata_inb (ioaddr->altstatus_addr); + udelay (5); +} + +u8 +sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max) +{ + u8 status; + + do { + udelay (1000); + status = sata_chk_status (ioaddr); + max--; + } while ((status & bits) && (max > 0)); + + return status; +} + +u8 +sata_chk_status (struct sata_ioports * ioaddr) +{ + return sata_inb (ioaddr->status_addr); +} + +void +msleep (int count) +{ + int i; + + for (i = 0; i < count; i++) + udelay (1000); +} + +ulong +sata_read (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer) +{ + ulong n = 0; + u8 dev = 0, num = 0, mask = 0, status = 0; + +#ifdef CONFIG_LBA48 + unsigned char lba48 = 0; + + if (blknr & 0x0000fffff0000000) { + if (!sata_dev_desc[devno].lba48) { + printf ("Drive doesn't support 48-bit addressing\n"); + return 0; + } + /* more than 28 bits used, use 48bit mode */ + lba48 = 1; + } +#endif + /*Port Number */ + num = device / CFG_SATA_DEVS_PER_BUS; + /*dev on the port */ + if (device >= CFG_SATA_DEVS_PER_BUS) + dev = device - CFG_SATA_DEVS_PER_BUS; + else + dev = device; + + if (dev == 0) + mask = 0x01; + else + mask = 0x02; + + if (!(port[num].dev_mask & mask)) { + printf ("dev%d is not present on port#%d\n", dev, num); + return 0; + } + + /* Select device */ + dev_select (&port[num].ioaddr, dev); + + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500); + if (status & ATA_BUSY) { + printf ("ata%u failed to respond\n", port[num].port_no); + return n; + } + while (blkcnt-- > 0) { + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500); + if (status & ATA_BUSY) { + printf ("ata%u failed to respond\n", 0); + return n; + } +#ifdef CONFIG_LBA48 + if (lba48) { + /* write high bits */ + sata_outb (0, port[num].ioaddr.nsect_addr); + sata_outb ((blknr >> 24) & 0xFF, + port[num].ioaddr.lbal_addr); + sata_outb ((blknr >> 32) & 0xFF, + port[num].ioaddr.lbam_addr); + sata_outb ((blknr >> 40) & 0xFF, + port[num].ioaddr.lbah_addr); + } +#endif + sata_outb (1, port[num].ioaddr.nsect_addr); + sata_outb (((blknr) >> 0) & 0xFF, + port[num].ioaddr.lbal_addr); + sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr); + sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr); + +#ifdef CONFIG_LBA48 + if (lba48) { + sata_outb (ATA_LBA, port[num].ioaddr.device_addr); + sata_outb (ATA_CMD_READ_EXT, + port[num].ioaddr.command_addr); + } else +#endif + { + sata_outb (ATA_LBA | ((blknr >> 24) & 0xF), + port[num].ioaddr.device_addr); + sata_outb (ATA_CMD_READ, + port[num].ioaddr.command_addr); + } + + msleep (50); + /*may take up to 4 sec */ + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000); + + if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) + != ATA_STAT_DRQ) { + u8 err = 0; + + printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n", + device, (ulong) blknr, status); + err = sata_inb (port[num].ioaddr.error_addr); + printf ("Error reg = 0x%x\n", err); + return (n); + } + input_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS); + sata_inb (port[num].ioaddr.altstatus_addr); + udelay (50); + + ++n; + ++blknr; + buffer += ATA_SECTORWORDS; + } + return n; +} + +ulong +sata_write (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer) +{ + ulong n = 0; + unsigned char status = 0, num = 0, dev = 0, mask = 0; + +#ifdef CONFIG_LBA48 + unsigned char lba48 = 0; + + if (blknr & 0x0000fffff0000000) { + if (!sata_dev_desc[devno].lba48) { + printf ("Drive doesn't support 48-bit addressing\n"); + return 0; + } + /* more than 28 bits used, use 48bit mode */ + lba48 = 1; + } +#endif + /*Port Number */ + num = device / CFG_SATA_DEVS_PER_BUS; + /*dev on the Port */ + if (device >= CFG_SATA_DEVS_PER_BUS) + dev = device - CFG_SATA_DEVS_PER_BUS; + else + dev = device; + + if (dev == 0) + mask = 0x01; + else + mask = 0x02; + + /* Select device */ + dev_select (&port[num].ioaddr, dev); + + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500); + if (status & ATA_BUSY) { + printf ("ata%u failed to respond\n", port[num].port_no); + return n; + } + + while (blkcnt-- > 0) { + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500); + if (status & ATA_BUSY) { + printf ("ata%u failed to respond\n", + port[num].port_no); + return n; + } +#ifdef CONFIG_LBA48 + if (lba48) { + /* write high bits */ + sata_outb (0, port[num].ioaddr.nsect_addr); + sata_outb ((blknr >> 24) & 0xFF, + port[num].ioaddr.lbal_addr); + sata_outb ((blknr >> 32) & 0xFF, + port[num].ioaddr.lbam_addr); + sata_outb ((blknr >> 40) & 0xFF, + port[num].ioaddr.lbah_addr); + } +#endif + sata_outb (1, port[num].ioaddr.nsect_addr); + sata_outb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr); + sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr); + sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr); +#ifdef CONFIG_LBA48 + if (lba48) { + sata_outb (ATA_LBA, port[num].ioaddr.device_addr); + sata_outb (ATA_CMD_WRITE_EXT, + port[num].ioaddr.command_addr); + } else +#endif + { + sata_outb (ATA_LBA | ((blknr >> 24) & 0xF), + port[num].ioaddr.device_addr); + sata_outb (ATA_CMD_WRITE, + port[num].ioaddr.command_addr); + } + + msleep (50); + /*may take up to 4 sec */ + status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000); + if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) + != ATA_STAT_DRQ) { + printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n", + device, (ulong) blknr, status); + return (n); + } + + output_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS); + sata_inb (port[num].ioaddr.altstatus_addr); + udelay (50); + + ++n; + ++blknr; + buffer += ATA_SECTORWORDS; + } + return n; +} + +block_dev_desc_t *sata_get_dev (int dev); + +block_dev_desc_t * +sata_get_dev (int dev) +{ + return ((block_dev_desc_t *) & sata_dev_desc[dev]); +} + +int +do_sata (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + + switch (argc) { + case 0: + case 1: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 2: + if (strncmp (argv[1], "init", 4) == 0) { + int rcode = 0; + + rcode = init_sata (); + if (rcode) + printf ("Sata initialization Failed\n"); + return rcode; + } else if (strncmp (argv[1], "inf", 3) == 0) { + int i; + + putc ('\n'); + for (i = 0; i < CFG_SATA_MAXDEVICES; ++i) { + /*List only known devices */ + if (sata_dev_desc[i].type == + DEV_TYPE_UNKNOWN) + continue; + printf ("sata dev %d: ", i); + dev_print (&sata_dev_desc[i]); + } + return 0; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + case 3: + if (strcmp (argv[1], "dev") == 0) { + int dev = (int) simple_strtoul (argv[2], NULL, 10); + + if (dev >= CFG_SATA_MAXDEVICES) { + printf ("\nSata dev %d not available\n", + dev); + return 1; + } + printf ("\nSATA dev %d: ", dev); + dev_print (&sata_dev_desc[dev]); + if (sata_dev_desc[dev].type == DEV_TYPE_UNKNOWN) + return 1; + curr_dev = dev; + return 0; + } else if (strcmp (argv[1], "part") == 0) { + int dev = (int) simple_strtoul (argv[2], NULL, 10); + + if (dev >= CFG_SATA_MAXDEVICES) { + printf ("\nSata dev %d not available\n", + dev); + return 1; + } + PRINTF ("\nSATA dev %d: ", dev); + if (sata_dev_desc[dev].part_type != + PART_TYPE_UNKNOWN) { + print_part (&sata_dev_desc[dev]); + } else { + printf ("\nSata dev %d partition type " + "unknown\n", dev); + return 1; + } + return 0; + } + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + default: + if (argc < 5) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + if (strcmp (argv[1], "read") == 0) { + ulong addr = simple_strtoul (argv[2], NULL, 16); + ulong cnt = simple_strtoul (argv[4], NULL, 16); + ulong n; + lbaint_t blk = simple_strtoul (argv[3], NULL, 16); + + memset ((int *) addr, 0, cnt * 512); + printf ("\nSATA read: dev %d blk # %ld," + "count %ld ... ", curr_dev, blk, cnt); + n = sata_read (curr_dev, blk, cnt, (ulong *) addr); + /* flush cache after read */ + flush_cache (addr, cnt * 512); + printf ("%ld blocks read: %s\n", n, + (n == cnt) ? "OK" : "ERR"); + if (n == cnt) + return 1; + else + return 0; + } else if (strcmp (argv[1], "write") == 0) { + ulong addr = simple_strtoul (argv[2], NULL, 16); + ulong cnt = simple_strtoul (argv[4], NULL, 16); + ulong n; + lbaint_t blk = simple_strtoul (argv[3], NULL, 16); + + printf ("\nSata write: dev %d blk # %ld," + "count %ld ... ", curr_dev, blk, cnt); + n = sata_write (curr_dev, blk, cnt, (ulong *) addr); + printf ("%ld blocks written: %s\n", n, + (n == cnt) ? "OK" : "ERR"); + if (n == cnt) + return 1; + else + return 0; + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + } /*End OF SWITCH */ +} + +U_BOOT_CMD (sata, 5, 1, do_sata, + "sata init\n" + "sata info\n" + "sata part device\n" + "sata dev device\n" + "sata read addr blk# cnt\n" + "sata write addr blk# cnt\n", "cmd for init,rw and dev-info\n"); + +#endif diff --git a/drivers/Makefile b/drivers/Makefile index d68cba682be..8ad530fb2ae 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)libdrivers.a -COBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \ +COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \ bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \ cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \ e1000.o eepro100.o \ diff --git a/drivers/ata_piix.c b/drivers/ata_piix.c new file mode 100644 index 00000000000..7e611633bee --- /dev/null +++ b/drivers/ata_piix.c @@ -0,0 +1,216 @@ +/* + * Copyright (C) Procsys. All rights reserved. + * Author: Mushtaq Khan + + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference to ata_piix driver in kernel 2.4.32 +*/ + +/* +This file contains SATA controller and SATA drive initialization functions +*/ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CFG_ATA_PIIX /*ata_piix driver */ + +#define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */ + +#define DRV_DECL /*For file specific declarations */ +#include +#undef DRV_DECL + +/*Macros realted to PCI*/ +#define PCI_SATA_BUS 0x00 +#define PCI_SATA_DEV 0x1f +#define PCI_SATA_FUNC 0x02 + +#define PCI_SATA_BASE1 0x10 +#define PCI_SATA_BASE2 0x14 +#define PCI_SATA_BASE3 0x18 +#define PCI_SATA_BASE4 0x1c +#define PCI_SATA_BASE5 0x20 +#define PCI_PMR 0x90 +#define PCI_PI 0x09 +#define PCI_PCS 0x92 +#define PCI_DMA_CTL 0x48 + +#define PORT_PRESENT (1<<0) +#define PORT_ENABLED (1<<4) + +u32 bdf; +u32 iobase1 = 0; /*Primary cmd block */ +u32 iobase2 = 0; /*Primary ctl block */ +u32 iobase3 = 0; /*Sec cmd block */ +u32 iobase4 = 0; /*sec ctl block */ +u32 iobase5 = 0; /*BMDMA*/ +int +pci_sata_init (void) +{ + u32 bus = PCI_SATA_BUS; + u32 dev = PCI_SATA_DEV; + u32 fun = PCI_SATA_FUNC; + u16 cmd = 0; + u8 lat = 0, pcibios_max_latency = 0xff; + u8 pmr; /*Port mapping reg */ + u8 pi; /*Prgming Interface reg */ + + bdf = PCI_BDF (bus, dev, fun); + pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1); + pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2); + pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3); + pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4); + pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5); + + if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) || + (iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) || + (iobase5 == 0xFFFFFFFF)) { + printf ("error no base addr for SATA controller\n"); + return 1; + /*ERROR*/} + + iobase1 &= 0xFFFFFFFE; + iobase2 &= 0xFFFFFFFE; + iobase3 &= 0xFFFFFFFE; + iobase4 &= 0xFFFFFFFE; + iobase5 &= 0xFFFFFFFE; + + /*check for mode */ + pci_read_config_byte (bdf, PCI_PMR, &pmr); + if (pmr > 1) { + printf ("combined mode not supported\n"); + return 1; + } + + pci_read_config_byte (bdf, PCI_PI, &pi); + if ((pi & 0x05) != 0x05) { + printf ("Sata is in Legacy mode\n"); + return 1; + } else { + printf ("sata is in Native mode\n"); + } + + /*MASTER CFG AND IO CFG */ + pci_read_config_word (bdf, PCI_COMMAND, &cmd); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_word (bdf, PCI_COMMAND, cmd); + pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat); + + if (lat < 16) + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; + else if (lat > pcibios_max_latency) + lat = pcibios_max_latency; + pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat); + + return 0; +} + +int +sata_bus_probe (int port_no) +{ + int orig_mask, mask; + u16 pcs; + + mask = (PORT_PRESENT << port_no); + pci_read_config_word (bdf, PCI_PCS, &pcs); + orig_mask = (int) pcs & 0xff; + if ((orig_mask & mask) != mask) + return 0; + else + return 1; +} + +int +init_sata (void) +{ + u8 i, rv = 0; + + for (i = 0; i < CFG_SATA_MAXDEVICES; i++) { + sata_dev_desc[i].type = DEV_TYPE_UNKNOWN; + sata_dev_desc[i].if_type = IF_TYPE_IDE; + sata_dev_desc[i].dev = i; + sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN; + sata_dev_desc[i].blksz = 0; + sata_dev_desc[i].lba = 0; + sata_dev_desc[i].block_read = sata_read; + } + + rv = pci_sata_init (); + if (rv == 1) { + printf ("pci initialization failed\n"); + return 1; + } + + port[0].port_no = 0; + port[0].ioaddr.cmd_addr = iobase1; + port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr = + iobase2 | ATA_PCI_CTL_OFS; + port[0].ioaddr.bmdma_addr = iobase5; + + port[1].port_no = 1; + port[1].ioaddr.cmd_addr = iobase3; + port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr = + iobase4 | ATA_PCI_CTL_OFS; + port[1].ioaddr.bmdma_addr = iobase5 + 0x8; + + for (i = 0; i < CFG_SATA_MAXBUS; i++) + sata_port (&port[i].ioaddr); + + for (i = 0; i < CFG_SATA_MAXBUS; i++) { + if (!(sata_bus_probe (i))) { + port[i].port_state = 0; + printf ("SATA#%d port is not present \n", i); + } else { + printf ("SATA#%d port is present\n", i); + if (sata_bus_softreset (i)) { + port[i].port_state = 0; + } else { + port[i].port_state = 1; + } + } + } + + for (i = 0; i < CFG_SATA_MAXBUS; i++) { + u8 j, devno; + + if (port[i].port_state == 0) + continue; + for (j = 0; j < CFG_SATA_DEVS_PER_BUS; j++) { + sata_identify (i, j); + set_Feature_cmd (i, j); + devno = i * CFG_SATA_DEVS_PER_BUS + j; + if ((sata_dev_desc[devno].lba > 0) && + (sata_dev_desc[devno].blksz > 0)) { + dev_print (&sata_dev_desc[devno]); + /* initialize partition type */ + init_part (&sata_dev_desc[devno]); + if (curr_dev < 0) + curr_dev = + i * CFG_SATA_DEVS_PER_BUS + j; + } + } + } + return 0; +} +#endif diff --git a/include/ata.h b/include/ata.h index 8584226eb07..d36bdf6cd1c 100644 --- a/include/ata.h +++ b/include/ata.h @@ -83,6 +83,66 @@ #define ATA_DEVICE(x) ((x & 1)<<4) #define ATA_LBA 0xE0 +enum { + ATA_MAX_DEVICES = 1, /* per bus/port */ + ATA_MAX_PRD = 256, /* we could make these 256/256 */ + ATA_SECT_SIZE = 256, /*256 words per sector */ + + /* bits in ATA command block registers */ + ATA_HOB = (1 << 7), /* LBA48 selector */ + ATA_NIEN = (1 << 1), /* disable-irq flag */ + /*ATA_LBA = (1 << 6), *//* LBA28 selector */ + ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */ + ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */ + ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */ + ATA_BUSY = (1 << 7), /* BSY status bit */ + ATA_DRDY = (1 << 6), /* device ready */ + ATA_DF = (1 << 5), /* device fault */ + ATA_DRQ = (1 << 3), /* data request i/o */ + ATA_ERR = (1 << 0), /* have an error */ + ATA_SRST = (1 << 2), /* software reset */ + ATA_ABORTED = (1 << 2), /* command aborted */ + /* ATA command block registers */ + ATA_REG_DATA = 0x00, + ATA_REG_ERR = 0x01, + ATA_REG_NSECT = 0x02, + ATA_REG_LBAL = 0x03, + ATA_REG_LBAM = 0x04, + ATA_REG_LBAH = 0x05, + ATA_REG_DEVICE = 0x06, + ATA_REG_STATUS = 0x07, + ATA_PCI_CTL_OFS = 0x02, + /* and their aliases */ + ATA_REG_FEATURE = ATA_REG_ERR, + ATA_REG_CMD = ATA_REG_STATUS, + ATA_REG_BYTEL = ATA_REG_LBAM, + ATA_REG_BYTEH = ATA_REG_LBAH, + ATA_REG_DEVSEL = ATA_REG_DEVICE, + ATA_REG_IRQ = ATA_REG_NSECT, + + /* SETFEATURES stuff */ + SETFEATURES_XFER = 0x03, + XFER_UDMA_7 = 0x47, + XFER_UDMA_6 = 0x46, + XFER_UDMA_5 = 0x45, + XFER_UDMA_4 = 0x44, + XFER_UDMA_3 = 0x43, + XFER_UDMA_2 = 0x42, + XFER_UDMA_1 = 0x41, + XFER_UDMA_0 = 0x40, + XFER_MW_DMA_2 = 0x22, + XFER_MW_DMA_1 = 0x21, + XFER_MW_DMA_0 = 0x20, + XFER_PIO_4 = 0x0C, + XFER_PIO_3 = 0x0B, + XFER_PIO_2 = 0x0A, + XFER_PIO_1 = 0x09, + XFER_PIO_0 = 0x08, + XFER_SW_DMA_2 = 0x12, + XFER_SW_DMA_1 = 0x11, + XFER_SW_DMA_0 = 0x10, + XFER_PIO_SLOW = 0x00 +}; /* * ATA Commands (only mandatory commands listed here) */ diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index d7d07a62fc9..8b2ec077bd9 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -181,6 +181,15 @@ #undef CONFIG_IDE_RESET /* reset for ide unsupported... */ #undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */ +/************************************************************ +*SATA/Native Stuff +************************************************************/ +#define CFG_SATA_SUPPORTED 1 +#define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */ +#define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */ +#define CFG_SATA_MAXDEVICES (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS) +#define CFG_ATA_PIIX 1 /*Supports ata_piix driver */ + /************************************************************ * ATAPI support (experimental) ************************************************************/ diff --git a/include/sata.h b/include/sata.h new file mode 100644 index 00000000000..c6fa2ab5bcd --- /dev/null +++ b/include/sata.h @@ -0,0 +1,108 @@ + +#if (DEBUG_SATA) +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +struct sata_ioports { + unsigned long cmd_addr; + unsigned long data_addr; + unsigned long error_addr; + unsigned long feature_addr; + unsigned long nsect_addr; + unsigned long lbal_addr; + unsigned long lbam_addr; + unsigned long lbah_addr; + unsigned long device_addr; + unsigned long status_addr; + unsigned long command_addr; + unsigned long altstatus_addr; + unsigned long ctl_addr; + unsigned long bmdma_addr; + unsigned long scr_addr; +}; + +struct sata_port { + unsigned char port_no; /*primary-0, secondary=1 */ + struct sata_ioports ioaddr; /*ATA cmd/ctl/dma reg blks */ + unsigned char ctl_reg; + unsigned char last_ctl; + unsigned char port_state; /*1-port is present and + 0-port is not available */ + unsigned char dev_mask; +}; + +/***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/ +#ifdef SATA_DECL /*SATA library specific declarations */ +#define ata_id_has_lba48(id) ((id)[83] & (1 << 10)) +#define ata_id_has_lba(id) ((id)[49] & (1 << 9)) +#define ata_id_has_dma(id) ((id)[49] & (1 << 8)) +#define ata_id_u32(id,n) \ + (((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)])) +#define ata_id_u64(id,n) \ + (((u64) (id)[(n) + 3] << 48) | \ + ((u64) (id)[(n) + 2] << 32) | \ + ((u64) (id)[(n) + 1] << 16) | \ + ((u64) (id)[(n) + 0]) ) +#endif + +#ifdef SATA_DECL /*SATA library specific declarations */ +static inline void +ata_dump_id (u16 * id) +{ + PRINTF ("49==0x%04x " + "53==0x%04x " + "63==0x%04x " + "64==0x%04x " + "75==0x%04x \n", id[49], id[53], id[63], id[64], id[75]); + PRINTF ("80==0x%04x " + "81==0x%04x " + "82==0x%04x " + "83==0x%04x " + "84==0x%04x \n", id[80], id[81], id[82], id[83], id[84]); + PRINTF ("88==0x%04x " "93==0x%04x\n", id[88], id[93]); +} +#endif + +#ifdef SATA_DECL /*SATA library specific declarations */ +int sata_bus_softreset (int num); +void sata_identify (int num, int dev); +void sata_port (struct sata_ioports *ioport); +void set_Feature_cmd (int num, int dev); +int sata_devchk (struct sata_ioports *ioaddr, int dev); +void dev_select (struct sata_ioports *ioaddr, int dev); +u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max); +u8 sata_chk_status (struct sata_ioports *ioaddr); +ulong sata_read (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer); +ulong sata_write (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer); +void msleep (int count); +#else +extern int sata_bus_softreset (int num); +extern void sata_identify (int num, int dev); +extern void sata_port (struct sata_ioports *ioport); +extern void set_Feature_cmd (int num, int dev); +extern ulong sata_read (int device, lbaint_t blknr, + ulong blkcnt, ulong * buffer); +extern ulong sata_write (int device, lbaint_t blknr, + ulong blkcnt, ulong * buffer); +extern void msleep (int count); +#endif + +/************DRIVER SPECIFIC DEFINITIONS AND DECLARATIONS**************/ + +#ifdef DRV_DECL /*Driver specific declaration */ +int init_sata (void); +#else +extern int init_sata (void); +#endif + +#ifdef DRV_DECL /*Defines Driver Specific variables */ +struct sata_port port[CFG_SATA_MAXBUS]; +block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES]; +int curr_dev = -1; +#else +extern struct sata_port port[CFG_SATA_MAXBUS]; +extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES]; +extern int curr_dev; +#endif -- cgit v1.3.1 From 3162eb836903c8b247fdc7470dd39bfa6996f495 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 15 May 2007 23:38:05 +0200 Subject: Minor coding style cleanup. --- common/cmd_sata.c | 52 +++++++++++++++++++++++++++------------------------- drivers/ata_piix.c | 46 +++++++++++++++++++++++----------------------- include/ata.h | 2 +- include/sata.h | 8 ++++---- 4 files changed, 55 insertions(+), 53 deletions(-) (limited to 'include') diff --git a/common/cmd_sata.c b/common/cmd_sata.c index 1c71b6471d9..2e601a7d809 100644 --- a/common/cmd_sata.c +++ b/common/cmd_sata.c @@ -1,29 +1,31 @@ /* - * Copyright (C) Procsys. All rights reserved. - * Author: Mushtaq Khan - - * - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * with the reference to libata in kernel 2.4.32 - * -*/ - -/*File contains SATA read-write and other utility functions.*/ + * Copyright (C) Procsys. All rights reserved. + * Author: Mushtaq Khan + * + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference to libata in kernel 2.4.32 + * + */ + +/* + * File contains SATA read-write and other utility functions. + */ #include #include #include diff --git a/drivers/ata_piix.c b/drivers/ata_piix.c index 7e611633bee..42456d7be33 100644 --- a/drivers/ata_piix.c +++ b/drivers/ata_piix.c @@ -1,29 +1,29 @@ /* - * Copyright (C) Procsys. All rights reserved. - * Author: Mushtaq Khan - - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * with the reference to ata_piix driver in kernel 2.4.32 -*/ + * Copyright (C) Procsys. All rights reserved. + * Author: Mushtaq Khan + * + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * with the reference to ata_piix driver in kernel 2.4.32 + */ /* -This file contains SATA controller and SATA drive initialization functions -*/ + * This file contains SATA controller and SATA drive initialization functions + */ #include #include diff --git a/include/ata.h b/include/ata.h index d36bdf6cd1c..aa6e90d4702 100644 --- a/include/ata.h +++ b/include/ata.h @@ -91,7 +91,7 @@ enum { /* bits in ATA command block registers */ ATA_HOB = (1 << 7), /* LBA48 selector */ ATA_NIEN = (1 << 1), /* disable-irq flag */ - /*ATA_LBA = (1 << 6), *//* LBA28 selector */ + /*ATA_LBA = (1 << 6), */ /* LBA28 selector */ ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */ ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */ ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */ diff --git a/include/sata.h b/include/sata.h index c6fa2ab5bcd..a8713f817e9 100644 --- a/include/sata.h +++ b/include/sata.h @@ -24,12 +24,12 @@ struct sata_ioports { }; struct sata_port { - unsigned char port_no; /*primary-0, secondary=1 */ - struct sata_ioports ioaddr; /*ATA cmd/ctl/dma reg blks */ + unsigned char port_no; /* primary=0, secondary=1 */ + struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */ unsigned char ctl_reg; unsigned char last_ctl; - unsigned char port_state; /*1-port is present and - 0-port is not available */ + unsigned char port_state; /* 1-port is present and */ + 0-port is not available */ unsigned char dev_mask; }; -- cgit v1.3.1 From 255a3577c848706441daee0174543efe205a77f8 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 16 May 2007 16:52:19 -0500 Subject: Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx For all practical u-boot purposes, TSECs don't differ throughout the mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx. Signed-off-by: Kim Phillips --- board/cds/mpc8548cds/mpc8548cds.c | 10 +++++----- cpu/mpc83xx/cpu.c | 8 ++++---- cpu/mpc85xx/cpu.c | 2 +- cpu/mpc86xx/cpu.c | 8 ++++---- drivers/tsec.c | 18 ++++++++---------- include/configs/MPC8313ERDB.h | 8 ++++---- include/configs/MPC8349EMDS.h | 8 ++++---- include/configs/MPC8349ITX.h | 14 +++++++------- include/configs/MPC8540ADS.h | 8 ++++---- include/configs/MPC8540EVAL.h | 8 ++++---- include/configs/MPC8541CDS.h | 8 ++++---- include/configs/MPC8544DS.h | 8 ++++---- include/configs/MPC8548CDS.h | 16 ++++++++-------- include/configs/MPC8555CDS.h | 8 ++++---- include/configs/MPC8560ADS.h | 8 ++++---- include/configs/MPC8568MDS.h | 12 ++++++------ include/configs/MPC8641HPCN.h | 16 ++++++++-------- include/configs/PM854.h | 8 ++++---- include/configs/PM856.h | 8 ++++---- include/configs/TQM834x.h | 8 ++++---- include/configs/TQM85xx.h | 8 ++++---- include/configs/sbc8349.h | 8 ++++---- include/configs/stxgp3.h | 8 ++++---- include/configs/stxssa.h | 8 ++++---- net/eth.c | 39 ++++++++------------------------------- 25 files changed, 119 insertions(+), 144 deletions(-) (limited to 'include') diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c index 929ff2e6629..b7236417e8b 100644 --- a/board/cds/mpc8548cds/mpc8548cds.c +++ b/board/cds/mpc8548cds/mpc8548cds.c @@ -345,23 +345,23 @@ int last_stage_init(void) /* This is needed to get the RGMII working for the 1.3+ * CDS cards */ if (get_board_version() == 0x13) { - miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + miiphy_write(CONFIG_TSEC1_NAME, TSEC1_PHY_ADDR, 29, 18); - miiphy_read(CONFIG_MPC85XX_TSEC1_NAME, + miiphy_read(CONFIG_TSEC1_NAME, TSEC1_PHY_ADDR, 30, &temp); temp = (temp & 0xf03f); temp |= 2 << 9; /* 36 ohm */ temp |= 2 << 6; /* 39 ohm */ - miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + miiphy_write(CONFIG_TSEC1_NAME, TSEC1_PHY_ADDR, 30, temp); - miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + miiphy_write(CONFIG_TSEC1_NAME, TSEC1_PHY_ADDR, 29, 3); - miiphy_write(CONFIG_MPC85XX_TSEC1_NAME, + miiphy_write(CONFIG_TSEC1_NAME, TSEC1_PHY_ADDR, 30, 0x8000); } diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index e078f27a23d..841fe82428d 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -415,7 +415,7 @@ static const struct { "clock-frequency", fdt_set_busfreq }, -#ifdef CONFIG_MPC83XX_TSEC1 +#ifdef CONFIG_TSEC1 { "/" OF_SOC "/ethernet@24000, "mac-address", fdt_set_eth0 @@ -425,7 +425,7 @@ static const struct { fdt_set_eth0 }, #endif -#ifdef CONFIG_MPC83XX_TSEC2 +#ifdef CONFIG_TSEC2 { "/" OF_SOC "/ethernet@25000, "mac-address", fdt_set_eth1 @@ -525,7 +525,7 @@ ft_cpu_setup(void *blob, bd_t *bd) if (p != NULL) *p = cpu_to_be32(clock); -#ifdef CONFIG_MPC83XX_TSEC1 +#ifdef CONFIG_TSEC1 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enetaddr, 6); @@ -535,7 +535,7 @@ ft_cpu_setup(void *blob, bd_t *bd) memcpy(p, bd->bi_enetaddr, 6); #endif -#ifdef CONFIG_MPC83XX_TSEC2 +#ifdef CONFIG_TSEC2 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enet1addr, 6); diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 7735a52ccf1..1d791c9b9b3 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -280,7 +280,7 @@ ft_cpu_setup(void *blob, bd_t *bd) if (p != NULL) *p = cpu_to_be32(clock); -#if defined(CONFIG_MPC85XX_TSEC1) +#if defined(CONFIG_TSEC1) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); if (p) memcpy(p, bd->bi_enetaddr, 6); diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index a33acfec4d3..9456471e84e 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -278,7 +278,7 @@ ft_cpu_setup(void *blob, bd_t *bd) if (p != NULL) *p = cpu_to_be32(clock); -#if defined(CONFIG_MPC86XX_TSEC1) +#if defined(CONFIG_TSEC1) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enetaddr, 6); @@ -287,7 +287,7 @@ ft_cpu_setup(void *blob, bd_t *bd) memcpy(p, bd->bi_enetaddr, 6); #endif -#if defined(CONFIG_MPC86XX_TSEC2) +#if defined(CONFIG_TSEC2) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enet1addr, 6); @@ -296,7 +296,7 @@ ft_cpu_setup(void *blob, bd_t *bd) memcpy(p, bd->bi_enet1addr, 6); #endif -#if defined(CONFIG_MPC86XX_TSEC3) +#if defined(CONFIG_TSEC3) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enet2addr, 6); @@ -305,7 +305,7 @@ ft_cpu_setup(void *blob, bd_t *bd) memcpy(p, bd->bi_enet2addr, 6); #endif -#if defined(CONFIG_MPC86XX_TSEC4) +#if defined(CONFIG_TSEC4) p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len); if (p != NULL) memcpy(p, bd->bi_enet3addr, 6); diff --git a/drivers/tsec.c b/drivers/tsec.c index 790ba47c781..1298478704f 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -65,33 +65,31 @@ struct tsec_info_struct { * FEC_PHYIDX */ static struct tsec_info_struct tsec_info[] = { -#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1) -#if defined(CONFIG_MPC8544DS) +#if defined(CONFIG_TSEC1) +#if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN) {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, #else {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX}, #endif -#elif defined(CONFIG_MPC86XX_TSEC1) - {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX}, -#else {0, 0, 0}, #endif -#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2) - {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, -#elif defined(CONFIG_MPC86XX_TSEC2) +#if defined(CONFIG_TSEC2) +#if defined(CONFIG_MPC8641HPCN) {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX}, #else + {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX}, +#endif {0, 0, 0}, #endif #ifdef CONFIG_MPC85XX_FEC {FEC_PHY_ADDR, 0, FEC_PHYIDX}, #else -#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3) +#if defined(CONFIG_TSEC3) {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX}, #else {0, 0, 0}, #endif -#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4) +#if defined(CONFIG_TSEC4) {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX}, #else {0, 0, 0}, diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 697631345f6..7e1005c1ae9 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -303,11 +303,11 @@ #endif #define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_MPC83XX_TSEC1 1 +#define CONFIG_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0x1c #define TSEC2_PHY_ADDR 4 #define TSEC1_PHYIDX 0 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 0460be9e569..20c6d5a365e 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -432,10 +432,10 @@ #endif #define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_MPC83XX_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 906339e9d88..834934d0b6a 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -374,18 +374,18 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_MII #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ -#define CONFIG_MPC83XX_TSEC1 +#define CONFIG_TSEC1 -#ifdef CONFIG_MPC83XX_TSEC1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#ifdef CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "TSEC0" #define CFG_TSEC1_OFFSET 0x24000 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ #define TSEC1_PHYIDX 0 #endif -#ifdef CONFIG_MPC83XX_TSEC2 +#ifdef CONFIG_TSEC2 #define CONFIG_HAS_ETH1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC2_NAME "TSEC1" #define CFG_TSEC2_OFFSET 0x25000 #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ #define TSEC2_PHY_ADDR 4 @@ -628,11 +628,11 @@ boards, we say we have two, but don't display a message if we find only one. */ */ #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_MPC83XX_TSEC1 +#ifdef CONFIG_TSEC1 #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 #endif -#ifdef CONFIG_MPC83XX_TSEC2 +#ifdef CONFIG_TSEC2 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 #endif diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5aeea586800..9176be388e6 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -366,10 +366,10 @@ #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 418a3a38e68..b568cb4df75 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -212,10 +212,10 @@ #elif defined(CONFIG_TSEC_ENET) #define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define CONFIG_MPC85XX_FEC 1 #define CONFIG_MPC85XX_FEC_NAME "FEC" #define TSEC1_PHY_ADDR 7 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index fb360d282cd..e047e259a5b 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 4c3430897da..7cd62e95a91 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -359,10 +359,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC1" -#define CONFIG_MPC85XX_TSEC3 1 -#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC3" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 680009d6006..a0d291eef48 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -391,14 +391,14 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" -#define CONFIG_MPC85XX_TSEC3 1 -#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#undef CONFIG_MPC85XX_TSEC4 -#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC2" +#undef CONFIG_TSEC4 +#define CONFIG_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 4c8b4e73f3b..b7e703ca183 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 21e66376805..043397fc21b 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -356,10 +356,10 @@ #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 3f65644fdd4..0ff0416138d 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -353,12 +353,12 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" -#undef CONFIG_MPC85XX_TSEC3 -#undef CONFIG_MPC85XX_TSEC4 +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#undef CONFIG_TSEC3 +#undef CONFIG_TSEC4 #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 2 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index bbe35053dd7..43a9d6ff288 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -359,14 +359,14 @@ #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC86XX_TSEC1 1 -#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" -#define CONFIG_MPC86XX_TSEC2 1 -#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" -#define CONFIG_MPC86XX_TSEC3 1 -#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" -#define CONFIG_MPC86XX_TSEC4 1 -#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC4" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 4fb54402b1b..8f130f5ccd8 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -262,10 +262,10 @@ #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 87ab9348735..0286b53e017 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -258,10 +258,10 @@ #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index ed0357791b4..4a5f8b67578 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -248,10 +248,10 @@ extern int tqm834x_num_flash_banks; #define CONFIG_NET_MULTI #endif -#define CONFIG_MPC83XX_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index f45f3a2f5ac..b0b9dd3ab89 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -258,10 +258,10 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 65aac5cefd3..e6e3866a07e 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -401,10 +401,10 @@ #define CONFIG_NET_MULTI 1 #endif -#define CONFIG_MPC83XX_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define CONFIG_PHY_BCM5421S 1 #define TSEC1_PHY_ADDR 0x19 #define TSEC2_PHY_ADDR 0x1a diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 625cf20144f..21065b9d05c 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -230,10 +230,10 @@ #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 8624f4b74b8..2a341855401 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -252,10 +252,10 @@ #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 diff --git a/net/eth.c b/net/eth.c index 0fc22115dc2..ab56dcf6d52 100644 --- a/net/eth.c +++ b/net/eth.c @@ -173,28 +173,20 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_SK98) skge_initialize(bis); #endif -#if defined(CONFIG_MPC85XX_TSEC1) - tsec_initialize(bis, 0, CONFIG_MPC85XX_TSEC1_NAME); -#elif defined(CONFIG_MPC83XX_TSEC1) - tsec_initialize(bis, 0, CONFIG_MPC83XX_TSEC1_NAME); +#if defined(CONFIG_TSEC1) + tsec_initialize(bis, 0, CONFIG_TSEC1_NAME); #endif -#if defined(CONFIG_MPC85XX_TSEC2) - tsec_initialize(bis, 1, CONFIG_MPC85XX_TSEC2_NAME); -#elif defined(CONFIG_MPC83XX_TSEC2) - tsec_initialize(bis, 1, CONFIG_MPC83XX_TSEC2_NAME); +#if defined(CONFIG_TSEC2) + tsec_initialize(bis, 1, CONFIG_TSEC2_NAME); #endif #if defined(CONFIG_MPC85XX_FEC) tsec_initialize(bis, 2, CONFIG_MPC85XX_FEC_NAME); #else -# if defined(CONFIG_MPC85XX_TSEC3) - tsec_initialize(bis, 2, CONFIG_MPC85XX_TSEC3_NAME); -# elif defined(CONFIG_MPC83XX_TSEC3) - tsec_initialize(bis, 2, CONFIG_MPC83XX_TSEC3_NAME); +# if defined(CONFIG_TSEC3) + tsec_initialize(bis, 2, CONFIG_TSEC3_NAME); # endif -# if defined(CONFIG_MPC85XX_TSEC4) - tsec_initialize(bis, 3, CONFIG_MPC85XX_TSEC4_NAME); -# elif defined(CONFIG_MPC83XX_TSEC4) - tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME); +# if defined(CONFIG_TSEC4) + tsec_initialize(bis, 3, CONFIG_TSEC4_NAME); # endif #endif #if defined(CONFIG_UEC_ETH1) @@ -203,21 +195,6 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_UEC_ETH2) uec_initialize(1); #endif -#if defined(CONFIG_MPC86XX_TSEC1) - tsec_initialize(bis, 0, CONFIG_MPC86XX_TSEC1_NAME); -#endif - -#if defined(CONFIG_MPC86XX_TSEC2) - tsec_initialize(bis, 1, CONFIG_MPC86XX_TSEC2_NAME); -#endif - -#if defined(CONFIG_MPC86XX_TSEC3) - tsec_initialize(bis, 2, CONFIG_MPC86XX_TSEC3_NAME); -#endif - -#if defined(CONFIG_MPC86XX_TSEC4) - tsec_initialize(bis, 3, CONFIG_MPC86XX_TSEC4_NAME); -#endif #if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC) fec_initialize(bis); -- cgit v1.3.1 From 3e3b956906eba9e4ad7931581ecedaad10eccce8 Mon Sep 17 00:00:00 2001 From: Peter Pearse Date: Fri, 18 May 2007 16:47:03 +0100 Subject: Reduce line lengths to 80 characters max. --- board/siemens/SMN42/flash.c | 3 ++- disk/part.c | 6 ++++-- drivers/enc28j60.c | 15 ++++++++++----- fs/fat/fat.c | 6 ++++-- include/configs/SMN42.h | 3 ++- include/configs/lpc2292sodimm.h | 4 +++- 6 files changed, 25 insertions(+), 12 deletions(-) mode change 100644 => 100755 board/siemens/SMN42/flash.c mode change 100644 => 100755 disk/part.c mode change 100644 => 100755 drivers/enc28j60.c mode change 100644 => 100755 fs/fat/fat.c mode change 100644 => 100755 include/configs/SMN42.h mode change 100644 => 100755 include/configs/lpc2292sodimm.h (limited to 'include') diff --git a/board/siemens/SMN42/flash.c b/board/siemens/SMN42/flash.c old mode 100644 new mode 100755 index 7d4977e0262..e80df0bcf4b --- a/board/siemens/SMN42/flash.c +++ b/board/siemens/SMN42/flash.c @@ -25,7 +25,8 @@ #include #include -static unsigned long flash_addr_table[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; +static unsigned long flash_addr_table[CFG_MAX_FLASH_BANKS] + = CFG_FLASH_BANKS_LIST; flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; extern int lpc2292_copy_buffer_to_flash(flash_info_t *, ulong); diff --git a/disk/part.c b/disk/part.c old mode 100644 new mode 100755 index 54de737c3ba..61e6579d459 --- a/disk/part.c +++ b/disk/part.c @@ -220,7 +220,8 @@ void init_part (block_dev_desc_t * dev_desc) } -int get_partition_info (block_dev_desc_t *dev_desc, int part, disk_partition_t *info) +int get_partition_info (block_dev_desc_t *dev_desc, int part + , disk_partition_t *info) { switch (dev_desc->part_type) { #ifdef CONFIG_MAC_PARTITION @@ -326,7 +327,8 @@ void print_part (block_dev_desc_t * dev_desc) #else /* neither MAC nor DOS nor ISO partition configured */ -# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION nor CONFIG_ISO_PARTITION configured! +# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION +# error nor CONFIG_ISO_PARTITION configured! #endif #endif /* (CONFIG_COMMANDS & CFG_CMD_IDE) || CONFIG_COMMANDS & CFG_CMD_SCSI) */ diff --git a/drivers/enc28j60.c b/drivers/enc28j60.c old mode 100644 new mode 100755 index c2ed48573ad..36b084c1916 --- a/drivers/enc28j60.c +++ b/drivers/enc28j60.c @@ -548,7 +548,10 @@ static void encRx (void) m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC); /* taken from the Linux driver */ - /* Only odd values should be written to ERXRDPTL, see errata B4 pt.13 */ rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1; + /* Only odd values should be written to ERXRDPTL, + * see errata B4 pt.13 + */ + rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1; if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 | m_nic_read(CTL_REG_ERXSTL))) || (rxbuf_rdpt > (m_nic_read(CTL_REG_ERXNDH) << 8 | @@ -799,13 +802,15 @@ static void encInit (unsigned char *pEthAddr) /* enable MAC to receive frames */ /* added some bits from the Linux driver */ - m_nic_write_retry (CTL_REG_MACON1, (ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS), 10); + m_nic_write_retry (CTL_REG_MACON1 + ,(ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS) + ,10); /* configure pad, tx-crc and duplex */ /* added a bit from the Linux driver */ - m_nic_write_retry (CTL_REG_MACON3, - (ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN), - 10); + m_nic_write_retry (CTL_REG_MACON3 + ,(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN) + ,10); /* added 4 new lines from the Linux driver */ /* Allow infinite deferals if the medium is continously busy */ diff --git a/fs/fat/fat.c b/fs/fat/fat.c old mode 100644 new mode 100755 index 084ee44459e..3007608360a --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -59,7 +59,8 @@ int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr) if (cur_dev == NULL) return -1; if (cur_dev->block_read) { - return cur_dev->block_read (cur_dev->dev, startblock, getsize, (unsigned long *)bufptr); + return cur_dev->block_read (cur_dev->dev + , startblock, getsize, (unsigned long *)bufptr); } return -1; } @@ -996,7 +997,8 @@ file_fat_detectfs(void) memcpy (vol_label, volinfo.volume_label, 11); vol_label[11] = '\0'; volinfo.fs_type[5]='\0'; - printf("Partition %d: Filesystem: %s \"%s\"\n",cur_part,volinfo.fs_type,vol_label); + printf("Partition %d: Filesystem: %s \"%s\"\n" + ,cur_part,volinfo.fs_type,vol_label); return 0; } diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h old mode 100644 new mode 100755 index 41330e9dbee..1d2f28d9462 --- a/include/configs/SMN42.h +++ b/include/configs/SMN42.h @@ -134,7 +134,8 @@ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR 0x81000000 /* default load address for uClinux img is here*/ +#define CFG_LOAD_ADDR 0x81000000 /* default load address + * for uClinux img is here*/ #define CFG_SYS_CLK_FREQ 58982400 /* Hz */ #define CFG_HZ 2048 /* decrementer freq in Hz */ diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h old mode 100644 new mode 100755 index d817ea8d736..30e0b10f797 --- a/include/configs/lpc2292sodimm.h +++ b/include/configs/lpc2292sodimm.h @@ -101,7 +101,9 @@ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR 0x00040000 /* default load address for armadillo: kernel img is here*/ +#define CFG_LOAD_ADDR 0x00040000 /* default load address for + * armadillo: kernel img is here + */ #define CFG_SYS_CLK_FREQ 58982400 /* Hz */ #define CFG_HZ 2048 /* decrementer freq in Hz */ -- cgit v1.3.1 From 32922cdc470fdfd39bea0c1c4f582d3fb340421e Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Tue, 5 Jun 2007 12:30:52 -0500 Subject: mpc8641 image size cleanup e600 does not have a bootpg restriction. Move the version string to beginning of image at fff00000. Resetvec.S is not needed. Update flash copy instructions. Add tftpflash env variable Signed-off-by: Ed Swarthout Signed-off-by: Jon Loeliger --- Makefile | 3 --- board/mpc8641hpcn/config.mk | 2 +- board/mpc8641hpcn/u-boot.lds | 22 ++++------------------ cpu/mpc86xx/resetvec.S | 2 -- doc/README.mpc8641hpcn | 11 +++++++---- include/configs/MPC8641HPCN.h | 10 +++++++++- 6 files changed, 21 insertions(+), 29 deletions(-) delete mode 100644 cpu/mpc86xx/resetvec.S (limited to 'include') diff --git a/Makefile b/Makefile index 94cda54c731..df8c3cd66f4 100644 --- a/Makefile +++ b/Makefile @@ -173,9 +173,6 @@ endif ifeq ($(CPU),mpc85xx) OBJS += cpu/$(CPU)/resetvec.o endif -ifeq ($(CPU),mpc86xx) -OBJS += cpu/$(CPU)/resetvec.o -endif ifeq ($(CPU),bf533) OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o diff --git a/board/mpc8641hpcn/config.mk b/board/mpc8641hpcn/config.mk index 989a40b015e..f778dcbe0c5 100644 --- a/board/mpc8641hpcn/config.mk +++ b/board/mpc8641hpcn/config.mk @@ -25,7 +25,7 @@ # default CCSRBAR is at 0xff700000 # assume U-Boot is less than 0.5MB # -TEXT_BASE = 0xfff01000 +TEXT_BASE = 0xfff00000 PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds index 13c1acf803a..34b50e4be20 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/mpc8641hpcn/u-boot.lds @@ -1,7 +1,5 @@ /* - * (C) Copyright 2004, Freescale, Inc. - * (C) Copyright 2002,2003, Motorola,Inc. - * Jeff Brown + * Copyright 2006, 2007 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -23,24 +21,11 @@ */ OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -/* Do we need any of these for elf? - __DYNAMIC = 0; */ + SECTIONS { - .resetvec 0xFFF00100 : - { - *(.resetvec) - } = 0xffff - - .bootpg 0xFFF70000 : - { - cpu/mpc86xx/start.o (.bootpg) - board/mpc8641hpcn/init.o (.bootpg) - } = 0xffff /* Read-only sections, merged into text segment: */ - . = + 1024; .interp : { *(.interp) } .hash : { *(.hash) } .dynsym : { *(.dynsym) } @@ -66,7 +51,7 @@ SECTIONS .text : { cpu/mpc86xx/start.o (.text) - board/mpc8641hpcn/init.o (.text) + board/mpc8641hpcn/init.o (.bootpg) cpu/mpc86xx/traps.o (.text) cpu/mpc86xx/interrupts.o (.text) cpu/mpc86xx/cpu_init.o (.text) @@ -88,6 +73,7 @@ SECTIONS *(.rodata) *(.rodata1) *(.rodata.str1.4) + *(.eh_frame) } .fini : { *(.fini) } =0 .ctors : { *(.ctors) } diff --git a/cpu/mpc86xx/resetvec.S b/cpu/mpc86xx/resetvec.S deleted file mode 100644 index 9a552f6624e..00000000000 --- a/cpu/mpc86xx/resetvec.S +++ /dev/null @@ -1,2 +0,0 @@ - .section .resetvec,"ax" - b _start diff --git a/doc/README.mpc8641hpcn b/doc/README.mpc8641hpcn index 3b88f8bc728..ac56ccaf23b 100644 --- a/doc/README.mpc8641hpcn +++ b/doc/README.mpc8641hpcn @@ -96,14 +96,17 @@ To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF): tftp 1000000 u-boot.bin protect off all - erase fff00000 ffffffff - cp.b 1000000 fff00100 80000 + erase fff00000 +$filesize + cp.b 1000000 fff00000 $filesize + +or use tftpflash command: + run tftpflash To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF): tftp 1000000 u-boot.bin - erase ffb00000 ffbfffff - cp.b 1000000 ffb00100 80000 + erase ffb00000 +$filesize + cp.b 1000000 ffb00000 $filesize 4. Memory Map diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index bbe35053dd7..41daa2bfeaa 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -577,6 +577,7 @@ #define CONFIG_HOSTNAME unknown #define CONFIG_ROOTPATH /opt/nfsroot #define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1 @@ -592,10 +593,17 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ - "dtbaddr=400000\0" \ + "dtbaddr=c00000\0" \ "dtbfile=mpc8641_hpcn.dtb\0" \ "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ -- cgit v1.3.1 From c440bfe6d6d92d66478a7e84402b31f48413617b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 6 Jun 2007 11:42:13 +0200 Subject: ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese --- MAKEALL | 33 ++++---- Makefile | 9 ++ board/amcc/acadia/Makefile | 2 +- board/amcc/acadia/acadia.c | 10 ++- board/amcc/acadia/cmd_acadia.c | 101 ++++++++++++++++++++++ board/amcc/acadia/config.mk | 6 ++ board/amcc/acadia/memory.c | 11 ++- board/amcc/acadia/u-boot-nand.lds | 137 ++++++++++++++++++++++++++++++ cpu/ppc4xx/start.S | 72 ++++++++++++---- include/configs/acadia.h | 152 ++++++++++++++++++++++++++-------- include/ppc405.h | 8 ++ nand_spl/board/amcc/acadia/Makefile | 104 +++++++++++++++++++++++ nand_spl/board/amcc/acadia/config.mk | 47 +++++++++++ nand_spl/board/amcc/acadia/u-boot.lds | 63 ++++++++++++++ 14 files changed, 685 insertions(+), 70 deletions(-) create mode 100644 board/amcc/acadia/cmd_acadia.c create mode 100644 board/amcc/acadia/u-boot-nand.lds create mode 100644 nand_spl/board/amcc/acadia/Makefile create mode 100644 nand_spl/board/amcc/acadia/config.mk create mode 100644 nand_spl/board/amcc/acadia/u-boot.lds (limited to 'include') diff --git a/MAKEALL b/MAKEALL index 81f5dfcb058..67d39a716fb 100755 --- a/MAKEALL +++ b/MAKEALL @@ -75,22 +75,23 @@ LIST_8xx=" \ ######################################################################### LIST_4xx=" \ - acadia ADCIOP alpr AP1000 \ - AR405 ASH405 bamboo bamboo_nand \ - bubinga CANBT CMS700 CPCI2DP \ - CPCI405 CPCI4052 CPCI405AB CPCI405DT \ - CPCI440 CPCIISER4 CRAYL1 csb272 \ - csb472 DASA_SIM DP405 DU405 \ - ebony ERIC EXBITGEN G2000 \ - HH405 HUB405 JSE KAREF \ - katmai luan METROBOX MIP405 \ - MIP405T ML2 ml300 ocotea \ - OCRTC ORSG p3p440 PCI405 \ - pcs440ep PIP405 PLU405 PMC405 \ - PPChameleonEVB sbc405 sc3 sequoia \ - sequoia_nand taishan VOH405 VOM405 \ - W7OLMC W7OLMG walnut WUH405 \ - XPEDITE1K yellowstone yosemite yucca \ + acadia acadia_nand ADCIOP alpr \ + AP1000 AR405 ASH405 bamboo \ + bamboo_nand bubinga CANBT CMS700 \ + CPCI2DP CPCI405 CPCI4052 CPCI405AB \ + CPCI405DT CPCI440 CPCIISER4 CRAYL1 \ + csb272 csb472 DASA_SIM DP405 \ + DU405 ebony ERIC EXBITGEN \ + G2000 HH405 HUB405 JSE \ + KAREF katmai luan METROBOX \ + MIP405 MIP405T ML2 ml300 \ + ocotea OCRTC ORSG p3p440 \ + PCI405 pcs440ep PIP405 PLU405 \ + PMC405 PPChameleonEVB sbc405 sc3 \ + sequoia sequoia_nand taishan VOH405 \ + VOM405 W7OLMC W7OLMG walnut \ + WUH405 XPEDITE1K yellowstone yosemite \ + yucca \ " ######################################################################### diff --git a/Makefile b/Makefile index 463757c43b2..6b70dd53b26 100644 --- a/Makefile +++ b/Makefile @@ -1017,6 +1017,15 @@ xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$( acadia_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx acadia amcc +acadia_nand_config: unconfig + @mkdir -p $(obj)include + @mkdir -p $(obj)nand_spl + @mkdir -p $(obj)board/amcc/acadia + @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h + @$(MKCONFIG) -n $@ -a acadia ppc ppc4xx acadia amcc + @echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/acadia/config.tmp + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + ADCIOP_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile index abcbf3e439c..ddbcb8091f7 100644 --- a/board/amcc/acadia/Makefile +++ b/board/amcc/acadia/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cpr.o memory.o +COBJS = $(BOARD).o cmd_acadia.o cpr.o memory.o SOBJS = SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 3b63c8a741d..46d63e6308b 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -63,8 +63,14 @@ int board_early_init_f(void) acadia_gpio_init(); /* Configure 405EZ for NAND usage */ - mtsdr(sdrnand0, 0x80c00000); - mtsdr(sdrultra0, 0x8d110000); + mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN); + mfsdr(sdrultra0, reg); + reg &= ~SDR_ULTRA0_CSN_MASK; + reg |= (SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS) | + SDR_ULTRA0_NDGPIOBP | + SDR_ULTRA0_EBCRDYEN | + SDR_ULTRA0_NFSRSTEN; + mtsdr(sdrultra0, reg); /* USB Host core needs this bit set */ mfsdr(sdrultra1, reg); diff --git a/board/amcc/acadia/cmd_acadia.c b/board/amcc/acadia/cmd_acadia.c new file mode 100644 index 00000000000..fb7ea359545 --- /dev/null +++ b/board/amcc/acadia/cmd_acadia.c @@ -0,0 +1,101 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include + +static u8 boot_267_nor[] = { + 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00, + 0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static u8 boot_267_nand[] = { + 0xd0, 0x38, 0xc3, 0x50, 0x13, 0x88, 0x8e, 0x00, + 0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u8 chip; + u8 *buf; + int cpu_freq; + + if (argc < 3) { + printf("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + cpu_freq = simple_strtol(argv[1], NULL, 10); + if (cpu_freq != 267) { + printf("Unsupported cpu-frequency - only 267 supported\n"); + return 1; + } + + /* use 0x50 as I2C EEPROM address for now */ + chip = 0x50; + + if ((strcmp(argv[2], "nor") != 0) && + (strcmp(argv[2], "nand") != 0)) { + printf("Unsupported boot-device - only nor|nand support\n"); + return 1; + } + + if (strcmp(argv[2], "nand") == 0) { + switch (cpu_freq) { + case 267: + buf = boot_267_nand; + break; + default: + break; + } + } else { + switch (cpu_freq) { + case 267: + buf = boot_267_nor; + break; + default: + break; + } + } + + if (i2c_write(chip, 0, 1, buf, 16) != 0) + printf("Error writing to EEPROM at address 0x%x\n", chip); + udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); + if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0) + printf("Error2 writing to EEPROM at address 0x%x\n", chip); + + printf("Done\n"); + printf("Please power-cycle the board for the changes to take effect\n"); + + return 0; +} + +U_BOOT_CMD( + bootstrap, 3, 0, do_bootstrap, + "bootstrap - program the I2C bootstrap EEPROM\n", + " - program the I2C bootstrap EEPROM\n" + ); diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk index c8566ecc7b6..af5a46c2a5d 100644 --- a/board/amcc/acadia/config.mk +++ b/board/amcc/acadia/config.mk @@ -21,6 +21,12 @@ # MA 02111-1307 USA # +# +# AMCC 405EZ Reference Platform (Acadia) board +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + ifndef TEXT_BASE TEXT_BASE = 0xFFFC0000 endif diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 5375d36c9b5..25904d3b94a 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -39,6 +39,7 @@ void sdram_init(void) return; } +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) static void cram_bcr_write(u32 wr_val) { wr_val <<= 2; @@ -62,9 +63,12 @@ static void cram_bcr_write(u32 wr_val) return; } +#endif long int initdram(int board_type) { +#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) + int i; u32 val; /* 1. EBC need to program READY, CLK, ADV for ASync mode */ @@ -92,7 +96,12 @@ long int initdram(int board_type) /* Config EBC to use RDY */ mfsdr(sdrultra0, val); - mtsdr(sdrultra0, val | 0x04000000); + mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN); + + /* Wait a short while, since for NAND booting this is too fast */ + for (i=0; i<200000; i++) + ; +#endif return (CFG_MBYTES_RAM << 20); } diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds new file mode 100644 index 00000000000..a5dae0e98cc --- /dev/null +++ b/board/amcc/acadia/u-boot-nand.lds @@ -0,0 +1,137 @@ +/* + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + + /* Align to next NAND block */ + . = ALIGN(0x4000); + common/environment.o (.ppcenv) + /* Keep some space here for redundant env and potential bad env blocks */ + . = ALIGN(0x10000); + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 78de30031d7..78d0042cc76 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -155,7 +155,9 @@ * NAND U-Boot image is started from offset 0 */ .text +#if defined(CONFIG_440) bl reconfig_tlb0 +#endif GET_GOT bl cpu_init_f /* run low-level CPU init code (from Flash) */ bl board_init_f @@ -857,6 +859,38 @@ _start: #endif /* CONFIG_405EZ */ #endif +#ifdef CONFIG_NAND_SPL + /* + * Copy SPL from cache into internal SRAM + */ + li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1 + mtctr r4 + lis r2,CFG_NAND_BOOT_SPL_SRC@h + ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l + lis r3,CFG_NAND_BOOT_SPL_DST@h + ori r3,r3,CFG_NAND_BOOT_SPL_DST@l +spl_loop: + lwzu r4,4(r2) + stwu r4,4(r3) + bdnz spl_loop + + /* + * Jump to code in RAM + */ + bl 00f +00: mflr r10 + lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h + ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l + sub r10,r10,r3 + addi r10,r10,28 + mtlr r10 + blr + +start_ram: + sync + isync +#endif /* CONFIG_NAND_SPL */ + /*----------------------------------------------------------------------- */ /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ /*----------------------------------------------------------------------- */ @@ -967,12 +1001,16 @@ _start: stw r0, +12(r1) /* Save return addr (underflow vect) */ #endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */ +#ifdef CONFIG_NAND_SPL + bl nand_boot /* will not return */ +#else GET_GOT /* initialize GOT access */ bl cpu_init_f /* run low-level CPU init code (from Flash) */ /* NEVER RETURNS! */ bl board_init_f /* run first part of init code (from Flash) */ +#endif /* CONFIG_NAND_SPL */ #endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */ /*----------------------------------------------------------------------- */ @@ -1187,23 +1225,6 @@ crit_return: /* Cache functions. */ -invalidate_icache: - iccci r0,r0 /* for 405, iccci invalidates the */ - blr /* entire I cache */ - -invalidate_dcache: - addi r6,0,0x0000 /* clear GPR 6 */ - /* Do loop for # of dcache congruence classes. */ - lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */ - ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l - /* NOTE: dccci invalidates both */ - mtctr r7 /* ways in the D cache */ -..dcloop: - dccci 0,r6 /* invalidate line */ - addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */ - bdnz ..dcloop - blr - flush_dcache: addis r9,r0,0x0002 /* set mask for EE and CE msr bits */ ori r9,r9,0x8000 @@ -1734,6 +1755,23 @@ in32: lwz 3,0x0000(3) blr +invalidate_icache: + iccci r0,r0 /* for 405, iccci invalidates the */ + blr /* entire I cache */ + +invalidate_dcache: + addi r6,0,0x0000 /* clear GPR 6 */ + /* Do loop for # of dcache congruence classes. */ + lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */ + ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l + /* NOTE: dccci invalidates both */ + mtctr r7 /* ways in the D cache */ +..dcloop: + dccci 0,r6 /* invalidate line */ + addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */ + bdnz ..dcloop + blr + /**************************************************************************/ /* PPC405EP specific stuff */ /**************************************************************************/ diff --git a/include/configs/acadia.h b/include/configs/acadia.h index c72d9339e6b..0f447b004a0 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -109,6 +109,7 @@ /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CFG_FLASH_CFI /* The flash is CFI compatible */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ @@ -122,6 +123,12 @@ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define _CFG_CMD_INCLUDE (CFG_CMD_ALL) +#else +#define CFG_NO_FLASH 1 /* No NOR on Acadia when NAND-booting */ +#define _CFG_CMD_INCLUDE ((CFG_CMD_ALL) & ~(CFG_CMD_FLASH | CFG_CMD_IMLS)) +#endif + #ifdef CFG_ENV_IS_IN_FLASH #define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) @@ -132,6 +139,63 @@ #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #endif +/* + * IPL (Initial Program Loader, integrated inside CPU) + * Will load first 4k from NAND (SPL) into cache and execute it from there. + * + * SPL (Secondary Program Loader) + * Will load special U-Boot version (NUB) from NAND and execute it. This SPL + * has to fit into 4kByte. It sets up the CPU and configures the SDRAM + * controller and the NAND controller so that the special U-Boot image can be + * loaded from NAND to SDRAM. + * + * NUB (NAND U-Boot) + * This NAND U-Boot (NUB) is a special U-Boot version which can be started + * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. + * + * On 440EPx the SPL is copied to SDRAM before the NAND controller is + * set up. While still running from cache, I experienced problems accessing + * the NAND controller. sr - 2006-08-25 + */ +#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ +#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ +#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (12 << 10)) /* Copy SPL here*/ +#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ +#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) + +/* + * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) + */ +#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ +#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ + +/* + * Now the NAND chip has to be defined (no autodetection used!) + */ +#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */ +#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ +#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */ +#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ +#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */ + +#define CFG_NAND_ECCSIZE 256 +#define CFG_NAND_ECCBYTES 3 +#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE) +#define CFG_NAND_OOBSIZE 16 +#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS) +#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7} + +#ifdef CFG_ENV_IS_IN_NAND +/* + * For NAND booting the environment is embedded in the U-Boot image. Please take + * look at the file board/amcc/sequoia/u-boot-nand.lds for details. + */ +#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE +#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE) +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE) +#endif + /*----------------------------------------------------------------------- * RAM (CRAM) *----------------------------------------------------------------------*/ @@ -209,7 +273,11 @@ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b ${fileaddr} fffc0000 ${filesize};" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ + "nload=tftp 200000 acadia/u-boot-nand.bin\0" \ + "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \ + "setenv filesize;saveenv\0" \ + "nupd=run nload nupdate\0" \ "kozio=bootm ffc60000\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -233,24 +301,24 @@ #define CONFIG_SUPPORT_VFAT -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DTT | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_USB) +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & _CFG_CMD_INCLUDE) | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DTT | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NAND | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_USB) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -312,12 +380,16 @@ /*----------------------------------------------------------------------- * External Bus Controller (EBC) Setup *----------------------------------------------------------------------*/ -#define CFG_NAND_CS 3 /* NAND chip connected to CSx */ - +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CFG_NAND_CS 3 /* Memory Bank 0 (Flash) initialization */ #define CFG_EBC_PB0AP 0x03337200 #define CFG_EBC_PB0CR 0xfe0bc000 +/* Memory Bank 3 (NAND-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x018003c0 +#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000) + /* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/ /* Memory Bank 1 (CRAM) initialization */ #define CFG_EBC_PB1AP 0x030400c0 @@ -326,10 +398,24 @@ /* Memory Bank 2 (CRAM) initialization */ #define CFG_EBC_PB2AP 0x030400c0 #define CFG_EBC_PB2CR 0x020bc000 +#else +#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ +/* Memory Bank 0 (NAND-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x018003c0 +#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000) -/* Memory Bank 3 (NAND-FLASH) initialization */ -#define CFG_EBC_PB3AP 0x018003c0 -#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000) +/* + * When NAND-booting the CRAM EBC setup must be done in sync mode, since the + * NAND-SPL already initialized the CRAM and EBC to sync mode. + */ +/* Memory Bank 1 (CRAM) initialization */ +#define CFG_EBC_PB1AP 0x9C0201C0 +#define CFG_EBC_PB1CR 0x000bc000 + +/* Memory Bank 2 (CRAM) initialization */ +#define CFG_EBC_PB2AP 0x9C0201C0 +#define CFG_EBC_PB2CR 0x020bc000 +#endif /* Memory Bank 4 (CPLD) initialization */ #define CFG_EBC_PB4AP 0x04006000 @@ -341,9 +427,9 @@ * GPIO Setup *----------------------------------------------------------------------*/ #define CFG_GPIO_CRAM_CLK 8 -#define CFG_GPIO_CRAM_WAIT 9 +#define CFG_GPIO_CRAM_WAIT 9 /* GPIO-In */ #define CFG_GPIO_CRAM_ADV 10 -#define CFG_GPIO_CRAM_CRE (32 + 21) +#define CFG_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */ /*----------------------------------------------------------------------- * Definitions for GPIO_0 setup (PPC405EZ specific) @@ -365,10 +451,10 @@ * GPIO0[28-30] - Trace Outputs / PWM Inputs * GPIO0[31] - PWM_8 I/O */ -#define CFG_GPIO0_TCR 0xC0000000 -#define CFG_GPIO0_OSRL 0x50000000 +#define CFG_GPIO0_TCR 0xC0A00000 +#define CFG_GPIO0_OSRL 0x50004400 #define CFG_GPIO0_OSRH 0x02000055 -#define CFG_GPIO0_ISR1L 0x00000000 +#define CFG_GPIO0_ISR1L 0x00001000 #define CFG_GPIO0_ISR1H 0x00000055 #define CFG_GPIO0_TSRL 0x02000000 #define CFG_GPIO0_TSRH 0x00000055 @@ -387,13 +473,13 @@ * GPIO1[16] - SPI_SS_1_N Output * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs */ -#define CFG_GPIO1_OSRH 0x55455555 +#define CFG_GPIO1_TCR 0xFFFF8414 #define CFG_GPIO1_OSRL 0x40000110 -#define CFG_GPIO1_ISR1H 0x00000000 +#define CFG_GPIO1_OSRH 0x55455555 #define CFG_GPIO1_ISR1L 0x15555445 -#define CFG_GPIO1_TSRH 0x00000000 +#define CFG_GPIO1_ISR1H 0x00000000 #define CFG_GPIO1_TSRL 0x00000000 -#define CFG_GPIO1_TCR 0xFFFF8014 +#define CFG_GPIO1_TSRH 0x00000000 /* * Internal Definitions diff --git a/include/ppc405.h b/include/ppc405.h index fffae4dd16a..71ad12e5159 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -556,6 +556,11 @@ #define sdricintstat 0x4510 #define SDR_NAND0_NDEN 0x80000000 +#define SDR_NAND0_NDBTEN 0x40000000 +#define SDR_NAND0_NDBADR_MASK 0x30000000 +#define SDR_NAND0_NDBPG_MASK 0x0f000000 +#define SDR_NAND0_NDAREN 0x00800000 +#define SDR_NAND0_NDRBEN 0x00400000 #define SDR_ULTRA0_NDGPIOBP 0x80000000 #define SDR_ULTRA0_CSN_MASK 0x78000000 @@ -563,6 +568,9 @@ #define SDR_ULTRA0_CSNSEL1 0x20000000 #define SDR_ULTRA0_CSNSEL2 0x10000000 #define SDR_ULTRA0_CSNSEL3 0x08000000 +#define SDR_ULTRA0_EBCRDYEN 0x04000000 +#define SDR_ULTRA0_SPISSINEN 0x02000000 +#define SDR_ULTRA0_NFSRSTEN 0x01000000 #define SDR_ULTRA1_LEDNENABLE 0x40000000 diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile new file mode 100644 index 00000000000..0d6828a76fb --- /dev/null +++ b/nand_spl/board/amcc/acadia/Makefile @@ -0,0 +1,104 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o resetvec.o +COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +# from cpu directory +$(obj)gpio.c: + @rm -f $(obj)gpio.c + ln -s $(SRCTREE)/cpu/ppc4xx/gpio.c $(obj)gpio.c + +$(obj)ndfc.c: + @rm -f $(obj)ndfc.c + ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c + +$(obj)resetvec.S: + @rm -f $(obj)resetvec.S + ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S + +$(obj)start.S: + @rm -f $(obj)start.S + ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S + +# from board directory +$(obj)memory.c: + @rm -f $(obj)memory.c + ln -s $(SRCTREE)/board/amcc/acadia/memory.c $(obj)memory.c + +# from nand_spl directory +$(obj)nand_boot.c: + @rm -f $(obj)nand_boot.c + ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c + +# from drivers/nand directory +$(obj)nand_ecc.c: + @rm -f $(obj)nand_ecc.c + ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/amcc/acadia/config.mk b/nand_spl/board/amcc/acadia/config.mk new file mode 100644 index 00000000000..55069b4dfea --- /dev/null +++ b/nand_spl/board/amcc/acadia/config.mk @@ -0,0 +1,47 @@ +# +# (C) Copyright 2007 +# Stefan Roese, DENX Software Engineering, sr@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# AMCC 405EZ Reference Platform (Acadia) board +# + +# +# TEXT_BASE for SPL: +# +# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff, +# in the last 4kBytes of memory space in cache. +# We will copy this SPL into internal SRAM in start.S. So we set +# TEXT_BASE to starting address in internal SRAM here. +# +TEXT_BASE = 0xF8003000 + +# PAD_TO used to generate a 16kByte binary needed for the combined image +# -> PAD_TO = TEXT_BASE + 0x4000 +PAD_TO = 0xF8007000 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/nand_spl/board/amcc/acadia/u-boot.lds b/nand_spl/board/amcc/acadia/u-boot.lds new file mode 100644 index 00000000000..018def1faba --- /dev/null +++ b/nand_spl/board/amcc/acadia/u-boot.lds @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc:common) +SECTIONS +{ + .resetvec 0xF8003FFC : + { + *(.resetvec) + } = 0xffff + + .text : + { + start.o (.text) + nand_boot.o (.text) + ndfc.o (.text) + + *(.text) + *(.fixup) + } + _etext = .; + + .data : + { + *(.rodata*) + *(.data*) + *(.sdata*) + __got2_start = .; + *(.got2) + __got2_end = .; + } + + _edata = .; + + __bss_start = .; + .bss : + { + *(.sbss) + *(.bss) + } + + _end = . ; +} -- cgit v1.3.1 From 725671ccd2cd04c9ebc50c9e5a94dd8cbade66b7 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 6 Jun 2007 16:26:56 +0200 Subject: Coding Style cleanup; generate new CHANGELOG file. Signed-off-by: Wolfgang Denk --- CHANGELOG | 483 ++++++++++++++++++++++++++++++++++++++++ board/siemens/SMN42/flash.c | 3 +- disk/part.c | 2 +- drivers/enc28j60.c | 4 +- include/configs/SMN42.h | 18 +- include/configs/TB5200.h | 2 +- include/configs/aev.h | 2 +- include/configs/lpc2292sodimm.h | 13 +- include/configs/spieval.h | 2 +- 9 files changed, 505 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 24d805eb389..b77eec71ba6 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,9 +1,438 @@ +commit c440bfe6d6d92d66478a7e84402b31f48413617b +Author: Stefan Roese +Date: Wed Jun 6 11:42:13 2007 +0200 + + ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board + + This patch adds NAND booting support for the AMCC Acadia eval board. + + Please make sure to configure jumper J7 to position 2-3 when booting + from NOR, and to position 1-2 when booting for NAND. + + I also added a board command to configure the I2C bootstrap EEPROM + values. Right now only 267MHz is support for booting either via NOR + or NAND FLASH. Here the usage: + + => bootstrap 267 nor ;to configure the board for 267MHz NOR booting + => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting + + Signed-off-by: Stefan Roese + +commit 32922cdc470fdfd39bea0c1c4f582d3fb340421e +Author: Ed Swarthout +Date: Tue Jun 5 12:30:52 2007 -0500 + + mpc8641 image size cleanup + + e600 does not have a bootpg restriction. + Move the version string to beginning of image at fff00000. + Resetvec.S is not needed. + Update flash copy instructions. + Add tftpflash env variable + + Signed-off-by: Ed Swarthout + Signed-off-by: Jon Loeliger + +commit e3cbe1f93c5722f8ebbad468e30c069a2b511097 +Author: Benoît Monin +Date: Mon Jun 4 08:36:05 2007 +0200 + + [PATCH] Fix ppc4xx bootstrap letter displayed on startup + + The attached patch is mainly cosmetic, allowing u-boot to + display the correct bootstrap option letter according to the + datasheets. + + The original patch was extended with 405EZ support by Stefan + Roese. + + Signed-off-by: Benoit Monin + Signed-off-by: Stefan Roese + +commit 18d156eb37c90fadc8ec7a81a3b89176161f85b7 +Author: Stefan Roese +Date: Fri Jun 1 16:18:17 2007 +0200 + + ppc4xx: Add missing file for Bamboo NAND booting support + + Signed-off-by: Stefan Roese + +commit 155a96478a0881e6da96cbbbcf34952d6a3b1b4b +Author: Stefan Roese +Date: Fri Jun 1 15:58:19 2007 +0200 + + ppc4xx: Undo Sequoia patch for dynamic EBC speed support of 83MHz + + This patch undoes the patch by Jeff Mann with commit-id ada4697d. As + suggested by AMCC it is not recommended to dynamically change the EBC + speed after bootup. So we undo this change to be on the safe side. + + Signed-off-by: Stefan Roese + +commit 9d9096043e8f713d4bf1743d32e1459e6a11644b +Author: Stefan Roese +Date: Fri Jun 1 15:29:04 2007 +0200 + + ppc4xx: Update Sequoia NAND booting support with ECC + + Signed-off-by: Stefan Roese + +commit cf959c7d6687567c308e366e9581e1a5aff5cc5b +Author: Stefan Roese +Date: Fri Jun 1 15:27:11 2007 +0200 + + ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval board + + This patch adds NAND booting support for the AMCC Bamboo eval board. + Since the NAND-SPL boot image is limited to 4kbytes, this version + only supports the onboard 64MBytes of DDR. The DIMM modules can't be + supported, since the setup code for I2C DIMM autodetection and + configuration is too big for this NAND bootloader. + + Signed-off-by: Stefan Roese + +commit 42be56f53c8b107868e6125c8524ae84293e95a7 +Author: Stefan Roese +Date: Fri Jun 1 15:23:04 2007 +0200 + + NAND: Add ECC support to NAND booting support in nand_spl/nand_boot.c + + The U-Boot NAND booting support is now extended to support ECC + upon loading of the NAND U-Boot image. + + Tested on AMCC Sequoia (440EPx) and Bamboo (440EP). + + Signed-off-by: Stefan Roese + +commit a471db07fbb65a841ffc9f4f112562b945230f98 +Author: Stefan Roese +Date: Fri Jun 1 15:19:29 2007 +0200 + + ppc4xx: Prepare Bamboo port for NAND booting support + + This patch updates the "normal" Bamboo NOR booting port, so + that it is compatible with the coming soon NAND booting + Bamboo port. + + It also enables the 2nd NAND flash on the Bamboo. + + Signed-off-by: Stefan Roese + +commit 53ad02103fb8be4138a9937a8ab91fcdff7b4987 +Author: Stefan Roese +Date: Fri Jun 1 15:16:58 2007 +0200 + + ppc4xx: Update in_be32() functions and friends to latest Linux version + + Signed-off-by: Stefan Roese + +commit 91da09cfbce0c1de05d6d84aa8363d666fa7ea3c +Author: Stefan Roese +Date: Fri Jun 1 15:15:12 2007 +0200 + + NAND: Add hardware ECC support to the PPC4xx NAND driver ndfc.c + + This patch adds hardware ECC support to the NDFC driver. It also + changes the register access from using the "simple" in32/out32 + functions to the in_be32/out_be32 functions, which make sure + that the access is correctly synced. This is the only recommended + access to SoC registers in the current Linux kernel. + + Signed-off-by: Stefan Roese + +commit 17b5e862287cca76f19dcf8b741e61a7d06617f2 +Author: Stefan Roese +Date: Fri Jun 1 15:12:15 2007 +0200 + + NAND: Update nand_ecc.c to latest Linux version + + This patch updates the nand_ecc code to the latest Linux version. + The main reason for this is the more compact code. This makes + it possible to include the ECC code into the NAND bootloader + image (NAND_SPL) for PPC4xx. + + Signed-off-by: Stefan Roese + +commit d2d432760d2199d0e8558fdd9d1789b8131abcf7 +Author: Stefan Roese +Date: Fri Jun 1 15:09:50 2007 +0200 + + ppc4xx: 44x DDR driver code cleanup and small fix for Bamboo + + Signed-off-by: Stefan Roese + +commit e4bbed2803a2ad0521c7362f5d3e065f99abaedc +Author: Stefan Roese +Date: Fri Jun 1 13:45:24 2007 +0200 + + ppc4xx: Change Luan config file to support ECC + + With the updated 44x DDR2 driver the Luan board now supports + ECC generation and checking. + + Signed-off-by: Stefan Roese + +commit 7187db73491c8de0fb56efb5e5134ba5ec443089 +Author: Stefan Roese +Date: Fri Jun 1 13:45:00 2007 +0200 + + ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe) + + Add config option for 180 degree advance clock control as needed + for the AMCC Luan eval board. + + Signed-off-by: Stefan Roese + +commit ee1529838abbfaa35f14e3ffbeaaba693159475f +Author: Wolfgang Denk +Date: Thu May 31 17:20:09 2007 +0200 + + Add support for STX GP3SSA (stxssa) Board with 4 MiB flash. + + Signed-off-by: Wolfgang Denk + +commit 7049288fb1f16f1b317140226cdebd07bd416395 +Author: Bartlomiej Sieka +Date: Sun May 27 17:26:46 2007 +0200 + + Motion-PRO: Code cleanup, fix of a typo in OF_STDOUT_PATH. + + Signed-off-by: Bartlomiej Sieka + +commit 4520fd4d2c450da49637216aa0e53739b61c60ac +Author: Bartlomiej Sieka +Date: Sun May 27 17:06:36 2007 +0200 + + Motion-PRO: Add support for redundant environment. + + Enable redundant environment, add a MTD partition for it; also add env. + variable command for passing MTD partitions to the kernel command line. + + Signed-off-by: Piotr Kruszynski + Acked-by: Bartlomiej Sieka + +commit a26eabeec31746f06d309103690892805696e344 +Author: Bartlomiej Sieka +Date: Sun May 27 17:05:11 2007 +0200 + + Motion-PRO: Change maximum console buffer size from 256 to 1024 bytes. + + Allow passing longer command line to the kernel - useful especially + for passing MTD partition layout. + + Signed-off-by: Piotr Kruszynski + Acked-by: Bartlomiej Sieka + +commit 9160b96f71483a116de81c68985e8ee306d36764 +Author: Bartlomiej Sieka +Date: Sun May 27 17:04:18 2007 +0200 + + Fix: Add missing NULL termination in strings expanded by macros parser. + + Signed-off-by: Piotr Kruszynski + Acked-by: Bartlomiej Sieka + +commit 630ec84aef7228fc1dbfb38dec78541403a786cd +Author: Bartlomiej Sieka +Date: Sun May 27 17:03:37 2007 +0200 + + Motion-PRO: Update EEPROM's page write bits and write delay. + + Change EEPROM configuration according to the datasheet: "The 24C01A and 24C02A + have a page write capability of two bytes", and "This device offers fast (1ms) + byte write". Add 3ms of extra delay. + + Signed-off-by: Piotr Kruszynski + Acked-by: Bartlomiej Sieka + +commit c00125e07c1ebc125bab40e1e18bceed8be0c162 +Author: Bartlomiej Sieka +Date: Sun May 27 16:58:45 2007 +0200 + + MPC5XXX, Motion-PRO: Fix PHY initialization problem. + + After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which + networking does not function. This commit switches PHY to TX mode by clearing + the FX_SEL bit of Mode Control Register. It also reverses commit + 008861a2f3ef2c062744d733787c7e530a1b8761, i.e., a temporary workaround. + + Signed-off-by: Grzegorz Bernacki + Acked-by: Bartlomiej Sieka + +commit 93b78f534a6e708b4cf1a4ffb4d8438c67a007db +Author: Bartlomiej Sieka +Date: Sun May 27 16:57:15 2007 +0200 + + Motion-PRO: Add support for the temperature sensor. + + Signed-off-by: Piotr Kruszynski + Acked-by: Bartlomiej Sieka + +commit c75e639630cc132dc19cd1ecda5922c0db0bfbba +Author: Bartlomiej Sieka +Date: Sun May 27 16:55:23 2007 +0200 + + Motion-PRO: Add displaying of CPLD revision information during boot. + + Signed-off-by: Jan Wrobel + Acked-by: Bartlomiej Sieka + +commit c99512d6bd3973f01ca2fc4896d829b46e68f150 +Author: Bartlomiej Sieka +Date: Sun May 27 16:53:43 2007 +0200 + + MPC5xxx: Change names of defines related to IPB and PCI clocks. + + Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining + them does not cause PCI or IPB clocks to run at the specified speed. + Instead, they configure divisors used to calculate said clocks. This + patch renames the defines according to their real function. + + Signed-off-by: Grzegorz Bernacki + Acked-by: Bartlomiej Sieka + +commit a11c0b85dc3664bb3c1e781137118730c8f619ab +Author: Bartlomiej Sieka +Date: Sun May 27 16:51:48 2007 +0200 + + Motion-PRO: Add LED support. + + Signed-off-by: Jan Wrobel + Signed-off-by: Marian Balakowicz + Acked-by: Bartlomiej Sieka + +commit d756894722c888d09a9fa1df8323753772d3dcce +Author: Stefan Roese +Date: Thu May 24 09:49:00 2007 +0200 + + ppc4xx: Fix small 405EZ OCM initilization bug in start.S + + As pointed out by Bruce Adler this patch + fixes a small bug in the 405EZ OCM initialization. Thanks for + spotting. + + Signed-off-by: Stefan Roese + +commit 5d4a179013d59a76446462e1eb0a969fba63eb81 +Author: Stefan Roese +Date: Thu May 24 08:22:09 2007 +0200 + + ppc4xx: Update AMCC Acadia support for board revision 1.1 + + This patch updates the Acadia (405EZ) support for the new 1.1 board + revision. It also adds support for NAND FLASH via the 4xx NDFC. + + Please note that the jumper J7 must be in position 2-3 for this + NAND support. Position 1-2 is for NAND booting only. NAND booting + support will follow later. + + Signed-off-by: Stefan Roese + +commit 9f0077abd69f7a7c756a915b961037302be3e6f2 +Author: Stefan Roese +Date: Tue May 22 12:48:09 2007 +0200 + + ppc4xx: Use do { ... } while (0) for CPR & SDR access macros + + Signed-off-by: Stefan Roese + +commit 6f3dfc139a838b0841c151efe00ad47db2366e79 +Author: Stefan Roese +Date: Tue May 22 12:46:10 2007 +0200 + + ppc4xx: Add 405 support to 4xx NAND driver ndfc.c + + This patch adds support for 405 PPC's to the 4xx NAND driver + ndfc.c. This is in preparation for the new AMCC 405EZ. + + Signed-off-by: Stefan Roese + +commit 10603d76767426be803dadd4fb688b97eb69481c +Author: Stefan Roese +Date: Mon May 21 07:41:22 2007 +0200 + + ppc4xx: Fix problem in 405EZ OCM initialization + + As spotted by Bruce Adler this patch fixes an initialization problem + for the 405EZ OCM. + + Signed-off-by: Stefan Roese + +commit 3e3b956906eba9e4ad7931581ecedaad10eccce8 +Author: Peter Pearse +Date: Fri May 18 16:47:03 2007 +0100 + + Reduce line lengths to 80 characters max. + +commit 93ef45c9ddfdd9fc17c4e74bd8e2f2456580eb72 +Author: Peter Pearse +Date: Fri May 18 14:34:07 2007 +0100 + + Makefile permissions + +commit 1443a31457d68f7e8f0b9403e9832ec1e79dc59d +Author: Peter Pearse +Date: Fri May 18 14:33:11 2007 +0100 + + Makefile permissions + +commit 70124c2602ae2d4c5d3dba05b482d91548242de8 +Author: Stefano Babic +Date: Wed May 16 14:49:12 2007 +0200 + + Fix compile problem cause my Microblaze merge + + Signed-off-by: Stefano Babic + +commit ada4697d0230d6da552867777f98a67ec3ba2579 +Author: Jeffrey Mann +Date: Wed May 16 13:23:10 2007 +0200 + + [PATCH] Run new sequoia boards with an EBC speed of 83MHz + + Because the Sequoia board does not boot with an EBC faster than 66MHz, + the clock divider are changed after the initial boot process. + + This allows for maximum clocking speeds to be achieved on newer boards. + Sequoia boards with 666.66 MHz processors require that the EBC divider + be set to 3 in order to start the initial boot process at a slower EBC + speed. After the initial boot process, the divider can be set back to 2, + which will cause the boards to run at 83.333MHz. This is backward + compatible with boards with 533.33 MHz processors, as these boards will + already be set with an EBC divider of 2. + + Signed-off-by: Jeffrey Mann + +commit a7676ea7732f3c596805079fed7e5c9fac652cfc +Author: Wolfgang Denk +Date: Wed May 16 01:16:53 2007 +0200 + + Minor Coding Style cleanup, update CHANGELOG. + + Signed-off-by: Wolfgang Denk + commit d62f64cc23a940eafe712c776b3249e4160753d1 Author: Wolfgang Denk Date: Wed May 16 00:13:33 2007 +0200 Coding Style Cleanup, new CHANGELOG +commit 61936667e86a250ae12fd2dc189d3588f0a59e0b +Author: Stefan Roese +Date: Fri May 11 12:01:49 2007 +0200 + + ppc4xx: Add mtcpr/mfcpr access macros + + Signed-off-by: Stefan Roese + +commit 343c48bd84606c4025c8a7c7263fda465d6e284c +Author: Stefan Roese +Date: Fri May 11 12:01:06 2007 +0200 + + ppc4xx: Set bd->bi_pci_busfreq on 440EPx/GRx too + + Signed-off-by: Stefan Roese + commit 7d98ba770a7eaefa29ce927f31a0956df85bf650 Author: Piotr Kruszynski Date: Thu May 10 16:55:52 2007 +0200 @@ -11,6 +440,48 @@ Date: Thu May 10 16:55:52 2007 +0200 [Motion-PRO] Add MTD and JFFS2 support, also add default partition definition. +commit 65fb6a676e821f9570a2a376dc204bf611ce5f81 +Author: Peter Pearse +Date: Wed May 9 11:42:44 2007 +0100 + + Add the board directory for SMN42 + +commit 160131bf965785419626df6c388729fe0b597992 +Author: Peter Pearse +Date: Wed May 9 11:41:58 2007 +0100 + + Add the files for the SMN42 board + +commit 5c6d2b5a500f8c49670de8910150b78a41f781fc +Author: Peter Pearse +Date: Wed May 9 11:40:34 2007 +0100 + + Remove the deleted files for the SMN42 patch + +commit b0d8f5bf0d215adc9424cb228b2484dbf07f7761 +Author: Peter Pearse +Date: Wed May 9 11:37:56 2007 +0100 + + New board SMN42 branch + +commit 29f3be0caf0799ca6b89dfd9824c15619a50000f +Author: Peter Pearse +Date: Wed May 9 10:24:38 2007 +0100 + + Makefile permissions + +commit b84289b595731e8851df46e893845cc1322c9b9b +Author: Ed Swarthout +Date: Tue May 8 14:17:07 2007 -0500 + + 8641hpcn: Fix Makefile after moving pixis to board/freescale. + + The OBJTREE != SRCTREE build scenario was broken. + This fixes it. + + Signed-off-by: Ed Swarthout + Signed-off-by: Jon Loeliger + commit e69f66c6ebe82bbbd1da766bc4eda40ec7ee5af1 Author: Michal Simek Date: Tue May 8 15:57:43 2007 +0200 @@ -93,6 +564,18 @@ Date: Mon May 7 19:43:10 2007 +0200 fix: read and write MSR - repair number of parameters +commit 193b4a3bb3acaddf798da8de0da05d94ba8774ee +Author: Jeffrey Mann +Date: Mon May 7 19:42:49 2007 +0200 + + [PATCH] ppc4xx: Fix CONFIG_SYS_CLK_FREQ definition in Sequoia config file + + A '3' got cut off in the formatting of the last patch to automatically + change the clock speed of the system clock on sequoia board. + + Signed-off-by: Jeffrey Mann + Signed-off-by: Stefan Roese + commit 19bf1fbad7f19d5a120be9b1daf136e052fcab39 Author: Michal Simek Date: Mon May 7 19:33:51 2007 +0200 diff --git a/board/siemens/SMN42/flash.c b/board/siemens/SMN42/flash.c index e80df0bcf4b..7d4977e0262 100755 --- a/board/siemens/SMN42/flash.c +++ b/board/siemens/SMN42/flash.c @@ -25,8 +25,7 @@ #include #include -static unsigned long flash_addr_table[CFG_MAX_FLASH_BANKS] - = CFG_FLASH_BANKS_LIST; +static unsigned long flash_addr_table[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST; flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; extern int lpc2292_copy_buffer_to_flash(flash_info_t *, ulong); diff --git a/disk/part.c b/disk/part.c index 61e6579d459..255b1406982 100755 --- a/disk/part.c +++ b/disk/part.c @@ -327,7 +327,7 @@ void print_part (block_dev_desc_t * dev_desc) #else /* neither MAC nor DOS nor ISO partition configured */ -# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION +# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION # error nor CONFIG_ISO_PARTITION configured! #endif diff --git a/drivers/enc28j60.c b/drivers/enc28j60.c index 36b084c1916..98303aceee9 100755 --- a/drivers/enc28j60.c +++ b/drivers/enc28j60.c @@ -548,8 +548,8 @@ static void encRx (void) m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC); /* taken from the Linux driver */ - /* Only odd values should be written to ERXRDPTL, - * see errata B4 pt.13 + /* Only odd values should be written to ERXRDPTL, + * see errata B4 pt.13 */ rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1; if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 | diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h index 1d2f28d9462..d588818fc2e 100755 --- a/include/configs/SMN42.h +++ b/include/configs/SMN42.h @@ -42,7 +42,7 @@ #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ #define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ #define CONFIG_LPC2292 -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ #undef CONFIG_USE_IRQ /* don't need them anymore */ @@ -66,10 +66,10 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) /* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ /* this would be 0xAE if E0, E1 and E2 were pulled high */ #define CFG_I2C_SLAVE 0xA0 @@ -92,11 +92,11 @@ #define I2C_SCL(x) { if (x) PUT32(IO0SET, SCL); else PUT32(IO0CLR, SCL); } #define I2C_DELAY { udelay(100); } #define I2C_ACTIVE { unsigned int i2ctmp; \ - i2ctmp = GET32(IO0DIR); \ + i2ctmp = GET32(IO0DIR); \ i2ctmp |= SDA; \ PUT32(IO0DIR, i2ctmp); } #define I2C_TRISTATE { unsigned int i2ctmp; \ - i2ctmp = GET32(IO0DIR); \ + i2ctmp = GET32(IO0DIR); \ i2ctmp &= ~SDA; \ PUT32(IO0DIR, i2ctmp); } #endif /* CONFIG_SOFT_I2C */ @@ -132,12 +132,12 @@ #define CFG_MEMTEST_START 0x81800000 /* memtest works on */ #define CFG_MEMTEST_END 0x83000000 /* 24 MB in SRAM */ -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR 0x81000000 /* default load address - * for uClinux img is here*/ +#define CFG_LOAD_ADDR 0x81000000 /* default load address */ + /* for uClinux img is here*/ -#define CFG_SYS_CLK_FREQ 58982400 /* Hz */ +#define CFG_SYS_CLK_FREQ 58982400 /* Hz */ #define CFG_HZ 2048 /* decrementer freq in Hz */ /* valid baudrates */ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index b42cfb6e1fb..712668ab8a2 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -207,7 +207,7 @@ * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock + * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. */ #define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ diff --git a/include/configs/aev.h b/include/configs/aev.h index 6c2a3603787..f6f530cedbd 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -173,7 +173,7 @@ * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock + * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. */ #define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h index 30e0b10f797..7b6c6953e14 100755 --- a/include/configs/lpc2292sodimm.h +++ b/include/configs/lpc2292sodimm.h @@ -42,7 +42,7 @@ #define CONFIG_ARM7 1 /* This is a ARM7 CPU */ #define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */ #define CONFIG_LPC2292 -#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ +#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */ #undef CONFIG_USE_IRQ /* don't need them anymore */ @@ -66,7 +66,7 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) /* * Supported commands @@ -99,13 +99,12 @@ #define CFG_MEMTEST_START 0x40000000 /* memtest works on */ #define CFG_MEMTEST_END 0x40000000 /* 4 ... 8 MB in DRAM */ -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR 0x00040000 /* default load address for - * armadillo: kernel img is here - */ +#define CFG_LOAD_ADDR 0x00040000 /* default load address for */ + /* armadillo: kernel img is here*/ -#define CFG_SYS_CLK_FREQ 58982400 /* Hz */ +#define CFG_SYS_CLK_FREQ 58982400 /* Hz */ #define CFG_HZ 2048 /* decrementer freq in Hz */ /* valid baudrates */ diff --git a/include/configs/spieval.h b/include/configs/spieval.h index fd138a5d17a..9888d111086 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -226,7 +226,7 @@ * PCI Bus clocking configuration * * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock + * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. */ #define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ -- cgit v1.3.1 From 9045f33c023f698660a2e45d1b2194c0711abebc Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 8 Jun 2007 10:24:58 +0200 Subject: Fix config problems on SC3 board; make ide_reset_timeout work. --- common/cmd_ide.c | 4 ++-- cpu/ppc4xx/405gp_pci.c | 2 +- include/configs/sc3.h | 5 +++-- lib_ppc/board.c | 6 +++--- 4 files changed, 9 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/common/cmd_ide.c b/common/cmd_ide.c index ce99a41ab7d..e308474af71 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -514,11 +514,11 @@ void ide_init (void) unsigned char c; int i, bus; #if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_SC3) - unsigned int ata_reset_time; + unsigned int ata_reset_time = ATA_RESET_TIME; + char *s; #endif #ifdef CONFIG_AMIGAONEG3SE unsigned int max_bus_scan; - char *s; #endif #ifdef CONFIG_IDE_8xx_PCCARD extern int pcmcia_on (void); diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index 7134355635e..8bf03e1b2f1 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c @@ -380,7 +380,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); } -#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SOLIDCARD3)) +#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3)) /* *As is these functs get called out of flash Not a horrible diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 6b6acfa8758..e4357b08854 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -58,7 +58,7 @@ * 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB) */ -#define CONFIG_SOLIDCARD3 1 +#define CONFIG_SC3 1 #define CONFIG_4xx 1 #define CONFIG_405GP 1 @@ -134,7 +134,8 @@ #if 1 /* feel free to disable for development */ #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ #define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with ENTER\n" -#define CONFIG_AUTOBOOT_DELAY_STR "\n" /* 1st "password" */ +#define CONFIG_AUTOBOOT_DELAY_STR "\r" /* 1st "password" */ +#define CONFIG_AUTOBOOT_DELAY_STR2 "\n" /* 1st "password" */ #endif /* diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 9e85cdddc4a..c4fc5805ab6 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -76,7 +76,7 @@ extern int update_flash_size (int flash_size); #endif -#if defined(CONFIG_SOLIDCARD3) +#if defined(CONFIG_SC3) extern void sc3_read_eeprom(void); #endif @@ -820,7 +820,7 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif /* CONFIG_405GP, CONFIG_405EP */ #endif /* CFG_EXTBDINFO */ -#if defined(CONFIG_SOLIDCARD3) +#if defined(CONFIG_SC3) sc3_read_eeprom(); #endif s = getenv ("ethaddr"); @@ -929,7 +929,7 @@ void board_init_r (gd_t *id, ulong dest_addr) defined(CONFIG_KUP4X) || \ defined(CONFIG_LWMON) || \ defined(CONFIG_PCU_E) || \ - defined(CONFIG_SOLIDCARD3) || \ + defined(CONFIG_SC3) || \ defined(CONFIG_W7O) || \ defined(CONFIG_MISC_INIT_R) /* miscellaneous platform dependent initialisations */ -- cgit v1.3.1 From 8f8416fada9faf94b9a92f21fe6000643cb521d5 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Fri, 8 Jun 2007 14:52:22 +0200 Subject: TQM5200: Add Flat Device Tree support, update default env. accordingly. Signed-off-by: Jan Wrobel Acked-by: Bartlomiej Sieka --- board/tqm5200/tqm5200.c | 11 +++++++++++ include/configs/TQM5200.h | 30 +++++++++++++++++++++++++++--- 2 files changed, 38 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/tqm5200/tqm5200.c b/board/tqm5200/tqm5200.c index a4322b6661a..cf97603afc5 100644 --- a/board/tqm5200/tqm5200.c +++ b/board/tqm5200/tqm5200.c @@ -32,6 +32,10 @@ #include #include +#if defined(CONFIG_OF_FLAT_TREE) +#include +#endif + #ifdef CONFIG_VIDEO_SM501 #include #endif @@ -775,3 +779,10 @@ int board_get_height (void) } #endif /* CONFIG_VIDEO_SM501 */ + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 7935593febe..9da1d884b14 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -234,6 +234,8 @@ #ifndef CONFIG_CAM5200 #define CUSTOM_ENV_SETTINGS \ "bootfile=/tftpboot/tqm5200/uImage\0" \ + "bootfile_fdt=/tftpboot/tqm5200/uImage_fdt\0" \ + "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \ "u-boot=/tftpboot/tqm5200/u-boot.bin\0" #else #define CUSTOM_ENV_SETTINGS \ @@ -243,6 +245,10 @@ #endif #define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttyS0\0" \ + "kernel_addr=200000\0" \ + "fdt_addr=400000\0" \ + "hostname=tqm5200\0" \ "netdev=eth0\0" \ "rootpath=/opt/eldk/ppc_6xx\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -252,13 +258,17 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ ":${hostname}:${netdev}:off panic=1\0" \ "addcons=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate}\0" \ + "console=${console},${baudrate}\0" \ "flash_self=run ramargs addip addcons;" \ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "flash_nfs=run nfsargs addip addcons;" \ "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \ - "bootm\0" \ + "net_nfs=tftp ${kernel_addr} ${bootfile};" \ + "run nfsargs addip addcons;bootm\0" \ + "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt};" \ + "tftp ${fdt_addr} ${fdt_file};setenv console ttyPSC0;" \ + "run nfsargs addip addcons;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ CUSTOM_ENV_SETTINGS \ "load=tftp 200000 ${u-boot}\0" \ ENV_UPDT \ @@ -676,4 +686,18 @@ /* Interval between registers */ #define CFG_ATA_STRIDE 4 +/*----------------------------------------------------------------------- + * Open firmware flat tree support + *----------------------------------------------------------------------- + */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 + +/* maximum size of the flat tree (8K) */ +#define OF_FLAT_TREE_MAX_SIZE 8192 +#define OF_CPU "PowerPC,5200@0" +#define OF_SOC "soc5200@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" + #endif /* __CONFIG_H */ -- cgit v1.3.1 From 85f737376d5ff3d5f0d45a8b657686326d175307 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 15 Jun 2007 07:39:43 +0200 Subject: [ppc4xx] Extend 44x GPIO setup with default output state The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup is extended with the default GPIO output state (level). Signed-off-by: Stefan Roese --- cpu/ppc4xx/gpio.c | 38 +++++++++++++ include/asm-ppc/gpio.h | 8 +-- include/configs/pcs440ep.h | 130 ++++++++++++++++++++++----------------------- 3 files changed, 108 insertions(+), 68 deletions(-) (limited to 'include') diff --git a/cpu/ppc4xx/gpio.c b/cpu/ppc4xx/gpio.c index fb0f575eafc..5235203ea28 100644 --- a/cpu/ppc4xx/gpio.c +++ b/cpu/ppc4xx/gpio.c @@ -103,6 +103,18 @@ void gpio_write_bit(int pin, int val) out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin)); } +int gpio_read_out_bit(int pin) +{ + u32 offs = 0; + + if (pin >= GPIO_MAX) { + offs = 0x100; + pin -= GPIO_MAX; + } + + return (in32(GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0); +} + #if defined(CFG_440_GPIO_TABLE) void gpio_set_chip_configuration(void) { @@ -157,11 +169,37 @@ void gpio_set_chip_configuration(void) switch (gpio_tab[gpio_core][i].alt_nb) { case GPIO_SEL: if (gpio_core == GPIO0) { + /* + * Setup output value + * 1 -> high level + * 0 -> low level + * else -> don't touch + */ + reg = in32(GPIO0_OR); + if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) + reg |= (0x80000000 >> (i)); + else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0) + reg &= ~(0x80000000 >> (i)); + out32(GPIO0_OR, reg); + reg = in32(GPIO0_TCR) | (0x80000000 >> (i)); out32(GPIO0_TCR, reg); } if (gpio_core == GPIO1) { + /* + * Setup output value + * 1 -> high level + * 0 -> low level + * else -> don't touch + */ + reg = in32(GPIO0_OR); + if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1) + reg |= (0x80000000 >> (i)); + else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0) + reg &= ~(0x80000000 >> (i)); + out32(GPIO0_OR, reg); + reg = in32(GPIO1_TCR) | (0x80000000 >> (i)); out32(GPIO1_TCR, reg); } diff --git a/include/asm-ppc/gpio.h b/include/asm-ppc/gpio.h index 114dc92db9e..c9b6a36b4f9 100644 --- a/include/asm-ppc/gpio.h +++ b/include/asm-ppc/gpio.h @@ -45,12 +45,14 @@ typedef enum gpio_driver { GPIO_DIS, GPIO_IN, GPIO_OUT, GPIO_BI } gpio_driver_t; typedef enum gpio_out { GPIO_OUT_0, GPIO_OUT_1, GPIO_OUT_NO_CHG } gpio_out_t; typedef struct { - unsigned long add; /* gpio core base address */ - gpio_driver_t in_out; /* Driver Setting */ - gpio_select_t alt_nb; /* Selected Alternate */ + unsigned long add; /* gpio core base address */ + gpio_driver_t in_out; /* Driver Setting */ + gpio_select_t alt_nb; /* Selected Alternate */ + gpio_out_t out_val;/* Default Output Value */ } gpio_param_s; #endif void gpio_config(int pin, int in_out, int gpio_alt, int out_val); void gpio_write_bit(int pin, int val); +int gpio_read_out_bit(int pin); void gpio_set_chip_configuration(void); diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 23bdfc8dfb9..9e41773f570 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -315,76 +315,76 @@ /*----------------------------------------------------------------------- * PPC440 GPIO Configuration */ -#define CFG_440_GPIO_TABLE { /* GPIO Alternate1 Alternate2 Alternate3 */ \ +#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ { \ /* GPIO Core 0 */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO6 EBC_CS_N(1) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO7 EBC_CS_N(2) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO8 EBC_CS_N(3) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO9 EBC_CS_N(4) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO10 EBC_CS_N(5) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_SEL }, /* GPIO11 EBC_BUS_ERR */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO12 ZII_p0Rxd(0) */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO13 ZII_p0Rxd(1) */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO14 ZII_p0Rxd(2) */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO15 ZII_p0Rxd(3) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO16 ZII_p0Txd(0) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO17 ZII_p0Txd(1) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO18 ZII_p0Txd(2) */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO19 ZII_p0Txd(3) */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO20 ZII_p0Rx_er */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO21 ZII_p0Rx_dv */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO22 ZII_p0RxCrs */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO23 ZII_p0Tx_er */ \ -{ GPIO0_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO24 ZII_p0Tx_en */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO25 ZII_p0Col */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO26 USB2D_RXVALID */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO28 USB2D_TXVALID */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ -{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ -{ GPIO0_BASE, GPIO_IN, GPIO_SEL }, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO6 EBC_CS_N(1) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO7 EBC_CS_N(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO8 EBC_CS_N(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO9 EBC_CS_N(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO10 EBC_CS_N(5) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO11 EBC_BUS_ERR */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO12 ZII_p0Rxd(0) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO13 ZII_p0Rxd(1) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO14 ZII_p0Rxd(2) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO15 ZII_p0Rxd(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO16 ZII_p0Txd(0) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO17 ZII_p0Txd(1) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO18 ZII_p0Txd(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO19 ZII_p0Txd(3) */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO20 ZII_p0Rx_er */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO21 ZII_p0Rx_dv */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO22 ZII_p0RxCrs */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO23 ZII_p0Tx_er */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO24 ZII_p0Tx_en */ \ +{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO25 ZII_p0Col */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO26 USB2D_RXVALID */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO28 USB2D_TXVALID */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ +{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ }, \ { \ /* GPIO Core 1 */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO32 USB2D_OPMODE0 */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO33 USB2D_OPMODE1 */ \ -{ GPIO1_BASE, GPIO_OUT, GPIO_ALT3 }, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT3 }, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \ -{ GPIO1_BASE, GPIO_OUT, GPIO_ALT1 }, /* GPIO37 UART0_RTS_N */ \ -{ GPIO1_BASE, GPIO_OUT, GPIO_ALT2 }, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT2 }, /* GPIO39 UART0_RI_N UART1_SIN */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO40 UIC_IRQ(0) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO41 UIC_IRQ(1) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO42 UIC_IRQ(2) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO43 UIC_IRQ(3) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_ALT1 }, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ -{ GPIO1_BASE, GPIO_BI, GPIO_SEL }, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO49 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO50 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO51 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO52 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO53 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO54 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO55 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO56 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO57 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO58 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO59 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO60 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO61 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO62 Unselect via TraceSelect Bit */ \ -{ GPIO1_BASE, GPIO_IN, GPIO_SEL }, /* GPIO63 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO32 USB2D_OPMODE0 */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO33 USB2D_OPMODE1 */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_NO_CHG}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO36 UART0_8PIN_CTS_N UART3_SIN*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO37 UART0_RTS_N */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_NO_CHG}, /* GPIO39 UART0_RI_N UART1_SIN */ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO40 UIC_IRQ(0) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO41 UIC_IRQ(1) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO42 UIC_IRQ(2) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO43 UIC_IRQ(3) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ +{GPIO1_BASE, GPIO_BI, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO50 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO51 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO52 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO53 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO54 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO55 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO56 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO57 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO58 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO59 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO60 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO61 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO62 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO63 Unselect via TraceSelect Bit */ \ } \ } -- cgit v1.3.1 From b765ffb773f5a3cd5aa94ec76b6a05276b8cd5b2 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 15 Jun 2007 08:18:01 +0200 Subject: [ppc4xx] Add initial lwmon5 board support This patch adds initial support for the Liebherr lwmon5 board euqipped with an AMCC 440EPx PowerPC. Signed-off-by: Stefan Roese --- MAINTAINERS | 1 + MAKEALL | 18 +- Makefile | 3 + board/lwmon5/Makefile | 51 ++++ board/lwmon5/config.mk | 39 ++++ board/lwmon5/init.S | 90 +++++++ board/lwmon5/lwmon5.c | 464 ++++++++++++++++++++++++++++++++++++ board/lwmon5/sdram.c | 598 +++++++++++++++++++++++++++++++++++++++++++++++ board/lwmon5/sdram.h | 505 +++++++++++++++++++++++++++++++++++++++ board/lwmon5/u-boot.lds | 145 ++++++++++++ include/configs/lwmon5.h | 437 ++++++++++++++++++++++++++++++++++ include/ppc440.h | 5 +- 12 files changed, 2346 insertions(+), 10 deletions(-) create mode 100644 board/lwmon5/Makefile create mode 100644 board/lwmon5/config.mk create mode 100644 board/lwmon5/init.S create mode 100644 board/lwmon5/lwmon5.c create mode 100644 board/lwmon5/sdram.c create mode 100644 board/lwmon5/sdram.h create mode 100644 board/lwmon5/u-boot.lds create mode 100644 include/configs/lwmon5.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 2eaef1784ea..693b1157290 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -282,6 +282,7 @@ Stefan Roese bunbinga PPC405EP ebony PPC440GP katmai PPC440SPe + lwmon5 PPC440EPx ocotea PPC440GX p3p440 PPC440GP pcs440ep PPC440EP diff --git a/MAKEALL b/MAKEALL index 0e4e7440937..a9969a38506 100755 --- a/MAKEALL +++ b/MAKEALL @@ -83,15 +83,15 @@ LIST_4xx=" \ csb272 csb472 DASA_SIM DP405 \ DU405 ebony ERIC EXBITGEN \ G2000 HH405 HUB405 JSE \ - KAREF katmai luan METROBOX \ - MIP405 MIP405T ML2 ml300 \ - ocotea OCRTC ORSG p3p440 \ - PCI405 pcs440ep PIP405 PLU405 \ - PMC405 PPChameleonEVB sbc405 sc3 \ - sequoia sequoia_nand taishan VOH405 \ - VOM405 W7OLMC W7OLMG walnut \ - WUH405 XPEDITE1K yellowstone yosemite \ - yucca \ + KAREF katmai luan lwmon5 \ + METROBOX MIP405 MIP405T ML2 \ + ml300 ocotea OCRTC ORSG \ + p3p440 PCI405 pcs440ep PIP405 \ + PLU405 PMC405 PPChameleonEVB sbc405 \ + sc3 sequoia sequoia_nand taishan \ + VOH405 VOM405 W7OLMC W7OLMG \ + walnut WUH405 XPEDITE1K yellowstone \ + yosemite yucca \ " ######################################################################### diff --git a/Makefile b/Makefile index d5e220aadde..2d8cff3ffa4 100644 --- a/Makefile +++ b/Makefile @@ -1139,6 +1139,9 @@ katmai_config: unconfig luan_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc +lwmon5_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx lwmon5 + METROBOX_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx metrobox sandburst diff --git a/board/lwmon5/Makefile b/board/lwmon5/Makefile new file mode 100644 index 00000000000..06ef7f93317 --- /dev/null +++ b/board/lwmon5/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2002-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS = $(BOARD).o sdram.o +SOBJS = init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/lwmon5/config.mk b/board/lwmon5/config.mk new file mode 100644 index 00000000000..bf2b8798c1c --- /dev/null +++ b/board/lwmon5/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# lwmon5 (440EPx) +# + +ifndef TEXT_BASE +TEXT_BASE = 0xFFF80000 +endif + +PLATFORM_CPPFLAGS += -DCONFIG_440=1 + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif + +ifeq ($(dbcr),1) +PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 +endif diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S new file mode 100644 index 00000000000..6798e80985d --- /dev/null +++ b/board/lwmon5/init.S @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * Copyright (C) 2002 Scott McNutt + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/************************************************************************** + * TLB TABLE + * + * This table is used by the cpu boot code to setup the initial tlb + * entries. Rather than make broad assumptions in the cpu source tree, + * this table lets each board set things up however they like. + * + * Pointer to the table is returned in r1 + * + *************************************************************************/ + .section .bootpg,"ax" + .globl tlbtab + +tlbtab: + tlbtab_start + + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G) + + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the SPD DDR(2) detection + * routine. + */ + +#ifdef CFG_INIT_RAM_DCACHE + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry(CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) +#endif + + /* TLB-entry for PCI Memory */ + tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I) + tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I) + + /* TLB-entry for the FPGA Chip select 2 */ + tlbentry(CFG_FPGA_BASE_0, SZ_1M, CFG_FPGA_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G) + + /* TLB-entry for the FPGA Chip select 3 */ + tlbentry(CFG_FPGA_BASE_1, SZ_1M, CFG_FPGA_BASE_1, 1,AC_R|AC_W|AC_X|SA_I|SA_G) + + /* TLB-entry for the LIME Controller */ + tlbentry(CFG_LIME_BASE_0, SZ_16M, CFG_LIME_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G) + tlbentry(CFG_LIME_BASE_1, SZ_16M, CFG_LIME_BASE_1, 1, AC_R|AC_W|AC_X|SA_I|SA_G) + tlbentry(CFG_LIME_BASE_2, SZ_16M, CFG_LIME_BASE_2, 1, AC_R|AC_W|AC_X|SA_I|SA_G) + tlbentry(CFG_LIME_BASE_3, SZ_16M, CFG_LIME_BASE_3, 1, AC_R|AC_W|AC_X|SA_I|SA_G) + + /* TLB-entry for Internal Registers & OCM */ + tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I) + + /*TLB-entry PCI registers*/ + tlbentry(0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + + /* TLB-entry for peripherals */ + tlbentry(0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I) + + tlbtab_end diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c new file mode 100644 index 00000000000..69b45acac7e --- /dev/null +++ b/board/lwmon5/lwmon5.c @@ -0,0 +1,464 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +ulong flash_get_size (ulong base, int banknum); + +int board_early_init_f(void) +{ + u32 sdr0_pfc1, sdr0_pfc2; + u32 reg; + + /* PLB Write pipelining disabled. Denali Core workaround */ + mtdcr(plb0_acr, 0xDE000000); + mtdcr(plb1_acr, 0xDE000000); + + /*-------------------------------------------------------------------- + * Setup the interrupt controller polarities, triggers, etc. + *-------------------------------------------------------------------*/ + mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */ + mtdcr(uic0er, 0x00000000); /* disable all */ + mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */ + mtdcr(uic0pr, 0xfffff7ff); /* Adjustment of the polarity */ + mtdcr(uic0tr, 0x00000810); /* per ref-board manual */ + mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ + mtdcr(uic0sr, 0xffffffff); /* clear all */ + + mtdcr(uic1sr, 0xffffffff); /* clear all */ + mtdcr(uic1er, 0x00000000); /* disable all */ + mtdcr(uic1cr, 0x00000000); /* all non-critical */ + mtdcr(uic1pr, 0xFFFFC7AD); /* Adjustment of the polarity */ + mtdcr(uic1tr, 0x0600384A); /* per ref-board manual */ + mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ + mtdcr(uic1sr, 0xffffffff); /* clear all */ + + mtdcr(uic2sr, 0xffffffff); /* clear all */ + mtdcr(uic2er, 0x00000000); /* disable all */ + mtdcr(uic2cr, 0x00000000); /* all non-critical */ + mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */ + mtdcr(uic2tr, 0xDFC00000); /* per ref-board manual */ + mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */ + mtdcr(uic2sr, 0xffffffff); /* clear all. Why this??? */ + + /* Trace Pins are disabled. SDR0_PFC0 Register */ + mtsdr(SDR0_PFC0, 0x0); + + /* select Ethernet pins */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + /* SMII via ZMII */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | + SDR0_PFC1_SELECT_CONFIG_6; + mfsdr(SDR0_PFC2, sdr0_pfc2); + sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | + SDR0_PFC2_SELECT_CONFIG_6; + + /* enable SPI (SCP) */ + sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL; + + mtsdr(SDR0_PFC2, sdr0_pfc2); + mtsdr(SDR0_PFC1, sdr0_pfc1); + + mtsdr(SDR0_PFC4, 0x80000000); + + /* PCI arbiter disabled */ + /* PCI Host Configuration disbaled */ + mfsdr(sdr_pci0, reg); + reg = 0; + mtsdr(sdr_pci0, 0x00000000 | reg); + + gpio_write_bit(CFG_GPIO_FLASH_WP, 1); + + return 0; +} + +/*---------------------------------------------------------------------------+ + | misc_init_r. + +---------------------------------------------------------------------------*/ +int misc_init_r(void) +{ + u32 pbcr; + int size_val = 0; + u32 reg; + unsigned long usb2d0cr = 0; + unsigned long usb2phy0cr, usb2h0cr = 0; + unsigned long sdr0_pfc1; + + /* + * FLASH stuff... + */ + + /* Re-do sizing to get full correct info */ + + /* adjust flash start and offset */ + gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; + gd->bd->bi_flashoffset = 0; + + mfebc(pb0cr, pbcr); + switch (gd->bd->bi_flashsize) { + case 1 << 20: + size_val = 0; + break; + case 2 << 20: + size_val = 1; + break; + case 4 << 20: + size_val = 2; + break; + case 8 << 20: + size_val = 3; + break; + case 16 << 20: + size_val = 4; + break; + case 32 << 20: + size_val = 5; + break; + case 64 << 20: + size_val = 6; + break; + case 128 << 20: + size_val = 7; + break; + } + pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); + mtebc(pb0cr, pbcr); + + /* + * Re-check to get correct base address + */ + flash_get_size(gd->bd->bi_flashstart, 0); + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + -CFG_MONITOR_LEN, + 0xffffffff, + &flash_info[0]); + + /* Env protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, + &flash_info[0]); + + /* + * USB suff... + */ + /* SDR Setting */ + mfsdr(SDR0_PFC1, sdr0_pfc1); + mfsdr(SDR0_USB0, usb2d0cr); + mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mfsdr(SDR0_USB2H0CR, usb2h0cr); + + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/ + usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK; + usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/ + + /* An 8-bit/60MHz interface is the only possible alternative + when connecting the Device to the PHY */ + usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK; + usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/ + + mtsdr(SDR0_PFC1, sdr0_pfc1); + mtsdr(SDR0_USB0, usb2d0cr); + mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); + mtsdr(SDR0_USB2H0CR, usb2h0cr); + + /* + * Clear resets + */ + udelay (1000); + mtsdr(SDR0_SRST1, 0x00000000); + udelay (1000); + mtsdr(SDR0_SRST0, 0x00000000); + + printf("USB: Host(int phy) Device(ext phy)\n"); + + /* + * Clear PLB4A0_ACR[WRP] + * This fix will make the MAL burst disabling patch for the Linux + * EMAC driver obsolete. + */ + reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; + mtdcr(plb4_acr, reg); + + /* + * Reset Lime controller + */ + gpio_write_bit(CFG_GPIO_LIME_S, 1); + udelay(500); + gpio_write_bit(CFG_GPIO_LIME_RST, 1); + + /* + * Reset PHY's + */ + gpio_write_bit(CFG_GPIO_PHY0_RST, 0); + gpio_write_bit(CFG_GPIO_PHY1_RST, 0); + udelay(100); + gpio_write_bit(CFG_GPIO_PHY0_RST, 1); + gpio_write_bit(CFG_GPIO_PHY1_RST, 1); + + /* + * Reset USB hub + */ + gpio_write_bit(CFG_GPIO_HUB_RST, 0); + udelay(100); + gpio_write_bit(CFG_GPIO_HUB_RST, 1); + + return 0; +} + +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: lwmon5"); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +#if defined(CFG_DRAM_TEST) +int testdram(void) +{ + unsigned long *mem = (unsigned long *)0; + const unsigned long kend = (1024 / sizeof(unsigned long)); + unsigned long k, n; + + mtmsr(0); + + for (k = 0; k < CFG_MBYTES_SDRAM; + ++k, mem += (1024 / sizeof(unsigned long))) { + if ((k & 1023) == 0) { + printf("%3d MB\r", k / 1024); + } + + memset(mem, 0xaaaaaaaa, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0xaaaaaaaa) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + + memset(mem, 0x55555555, 1024); + for (n = 0; n < kend; ++n) { + if (mem[n] != 0x55555555) { + printf("SDRAM test fails at: %08x\n", + (uint) & mem[n]); + return 1; + } + } + } + printf("SDRAM test passes\n"); + return 0; +} +#endif + +/************************************************************************* + * pci_pre_init + * + * This routine is called just prior to registering the hose and gives + * the board the opportunity to check things. Returning a value of zero + * indicates that things are bad & PCI initialization should be aborted. + * + * Different boards may wish to customize the pci controller structure + * (add regions, override default access routines, etc) or perform + * certain pre-initialization actions. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +int pci_pre_init(struct pci_controller *hose) +{ + unsigned long addr; + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB3 devices to 0. + | Set PLB3 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp1, addr); + mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb3_acr); + mtdcr(plb3_acr, addr | 0x80000000); + + /*-------------------------------------------------------------------------+ + | Set priority for all PLB4 devices to 0. + +-------------------------------------------------------------------------*/ + mfsdr(sdr_amp0, addr); + mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ + mtdcr(plb4_acr, addr); + + /*-------------------------------------------------------------------------+ + | Set Nebula PLB4 arbiter to fair mode. + +-------------------------------------------------------------------------*/ + /* Segment0 */ + addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; + addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; + addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; + mtdcr(plb0_acr, addr); + + /* Segment1 */ + addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; + addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; + addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; + mtdcr(plb1_acr, addr); + + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + +/************************************************************************* + * pci_target_init + * + * The bootstrap configuration provides default settings for the pci + * inbound map (PIM). But the bootstrap config choices are limited and + * may not be sufficient for a given board. + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) +void pci_target_init(struct pci_controller *hose) +{ + /*--------------------------------------------------------------------------+ + * Set up Direct MMIO registers + *--------------------------------------------------------------------------*/ + /*--------------------------------------------------------------------------+ + | PowerPC440EPX PCI Master configuration. + | Map one 1Gig range of PLB/processor addresses to PCI memory space. + | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF + | Use byte reversed out routines to handle endianess. + | Make this region non-prefetchable. + +--------------------------------------------------------------------------*/ + out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + + /*--------------------------------------------------------------------------+ + * Set up Configuration registers + *--------------------------------------------------------------------------*/ + + /* Program the board's subsystem id/vendor id */ + pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, + CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); + + /* Configure command register as bus master */ + pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* 240nS PCI clock */ + pci_write_config_word(0, PCI_LATENCY_TIMER, 1); + + /* No error reporting */ + pci_write_config_word(0, PCI_ERREN, 0); + + pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); + +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ + +/************************************************************************* + * pci_master_init + * + ************************************************************************/ +#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) +void pci_master_init(struct pci_controller *hose) +{ + unsigned short temp_short; + + /*--------------------------------------------------------------------------+ + | Write the PowerPC440 EP PCI Configuration regs. + | Enable PowerPC440 EP to be a master on the PCI bus (PMM). + | Enable PowerPC440 EP to act as a PCI memory target (PTM). + +--------------------------------------------------------------------------*/ + pci_read_config_word(0, PCI_COMMAND, &temp_short); + pci_write_config_word(0, PCI_COMMAND, + temp_short | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */ + +/************************************************************************* + * is_pci_host + * + * This routine is called to determine if a pci scan should be + * performed. With various hardware environments (especially cPCI and + * PPMC) it's insufficient to depend on the state of the arbiter enable + * bit in the strap register, or generic host/adapter assumptions. + * + * Rather than hard-code a bad assumption in the general 440 code, the + * 440 pci code requires the board to decide at runtime. + * + * Return 0 for adapter mode, non-zero for host (monarch) mode. + * + * + ************************************************************************/ +#if defined(CONFIG_PCI) +int is_pci_host(struct pci_controller *hose) +{ + /* Cactus is always configured as host. */ + return (1); +} +#endif /* defined(CONFIG_PCI) */ + +void hw_watchdog_reset(void) +{ + int val; + + /* + * Toggle watchdog output + */ + val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0; + gpio_write_bit(CFG_GPIO_WATCHDOG, val); +} diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c new file mode 100644 index 00000000000..d2eb5bd1a8f --- /dev/null +++ b/board/lwmon5/sdram.c @@ -0,0 +1,598 @@ +/* + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include +#include +#include +#include +#include + +#include "sdram.h" + +/* + * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory + * region. Right now the cache should still be disabled in U-Boot because of the + * EMAC driver, that need it's buffer descriptor to be located in non cached + * memory. + * + * If at some time this restriction doesn't apply anymore, just define + * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * everything correctly. + */ +#ifdef CFG_ENABLE_SDRAM_CACHE +#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ +#else +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ +#endif + +void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); +void dcbz_area(u32 start_address, u32 num_bytes); +void dflush(void); + +#ifdef CONFIG_ADD_RAM_INFO +static u32 is_ecc_enabled(void) +{ + u32 val; + + mfsdram(DDR0_22, val); + val &= DDR0_22_CTRL_RAW_MASK; + if (val) + return 1; + else + return 0; +} + +void board_add_ram_info(int use_default) +{ + PPC440_SYS_INFO board_cfg; + u32 val; + + if (is_ecc_enabled()) + puts(" (ECC"); + else + puts(" (ECC not"); + + get_sys_info(&board_cfg); + printf(" enabled, %d MHz", (board_cfg.freqPLB * 2) / 1000000); + + mfsdram(DDR0_03, val); + val = DDR0_03_CASLAT_DECODE(val); + printf(", CL%d)", val); +} +#endif + +static int wait_for_dlllock(void) +{ + u32 val; + int wait = 0; + + /* + * Wait for the DCC master delay line to finish calibration + */ + mtdcr(ddrcfga, DDR0_17); + val = DDR0_17_DLLLOCKREG_UNLOCKED; + + while (wait != 0xffff) { + val = mfdcr(ddrcfgd); + if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED) + /* dlllockreg bit on */ + return 0; + else + wait++; + } + debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val); + debug("Waiting for dlllockreg bit to raise\n"); + + return -1; +} + +#if defined(CONFIG_DDR_DATA_EYE) +int wait_for_dram_init_complete(void) +{ + u32 val; + int wait = 0; + + /* + * Wait for 'DRAM initialization complete' bit in status register + */ + mtdcr(ddrcfga, DDR0_00); + + while (wait != 0xffff) { + val = mfdcr(ddrcfgd); + if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6) + /* 'DRAM initialization complete' bit */ + return 0; + else + wait++; + } + + debug("DRAM initialization complete bit in status register did not rise\n"); + + return -1; +} + +#define NUM_TRIES 64 +#define NUM_READS 10 + +void denali_core_search_data_eye(u32 start_addr, u32 memory_size) +{ + int k, j; + u32 val; + u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X; + u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0; + u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0; + u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0; + volatile u32 *ram_pointer; + u32 test[NUM_TRIES] = { + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, + 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 }; + + ram_pointer = (volatile u32 *)start_addr; + + for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) { + /*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/ + + /* + * De-assert 'start' parameter. + */ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + /* + * Set 'wr_dqs_shift' + */ + mtdcr(ddrcfga, DDR0_09); + val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) + | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); + mtdcr(ddrcfgd, val); + + /* + * Set 'dqs_out_shift' = wr_dqs_shift + 32 + */ + dqs_out_shift = wr_dqs_shift + 32; + mtdcr(ddrcfga, DDR0_22); + val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) + | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); + mtdcr(ddrcfgd, val); + + passing_cases = 0; + + for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) { + /*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/ + /* + * Set 'dll_dqs_delay_X'. + */ + /* dll_dqs_delay_0 */ + mtdcr(ddrcfga, DDR0_17); + val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) + | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* dll_dqs_delay_1 to dll_dqs_delay_4 */ + mtdcr(ddrcfga, DDR0_18); + val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) + | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + /* dll_dqs_delay_5 to dll_dqs_delay_8 */ + mtdcr(ddrcfga, DDR0_19); + val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) + | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + + ppcMsync(); + ppcMbar(); + + /* + * Assert 'start' parameter. + */ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; + mtdcr(ddrcfgd, val); + + ppcMsync(); + ppcMbar(); + + /* + * Wait for the DCC master delay line to finish calibration + */ + if (wait_for_dlllock() != 0) { + printf("dlllock did not occur !!!\n"); + printf("denali_core_search_data_eye!!!\n"); + printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n", + wr_dqs_shift, dll_dqs_delay_X); + hang(); + } + ppcMsync(); + ppcMbar(); + + if (wait_for_dram_init_complete() != 0) { + printf("dram init complete did not occur !!!\n"); + printf("denali_core_search_data_eye!!!\n"); + printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n", + wr_dqs_shift, dll_dqs_delay_X); + hang(); + } + udelay(100); /* wait 100us to ensure init is really completed !!! */ + + /* write values */ + for (j=0; j= max_passing_cases) { + max_passing_cases = passing_cases; + wr_dqs_shift_with_max_passing_cases = wr_dqs_shift; + dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val; + dll_dqs_delay_X_end_window = dll_dqs_delay_X; + } + } + + /* + * De-assert 'start' parameter. + */ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + } /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */ + + } /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */ + + /* + * Largest passing window is now detected. + */ + + /* Compute dll_dqs_delay_X value */ + dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2; + wr_dqs_shift = wr_dqs_shift_with_max_passing_cases; + + debug("DQS calibration - Window detected:\n"); + debug("max_passing_cases = %d\n", max_passing_cases); + debug("wr_dqs_shift = %d\n", wr_dqs_shift); + debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X); + debug("dll_dqs_delay_X window = %d - %d\n", + dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window); + + /* + * De-assert 'start' parameter. + */ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF; + mtdcr(ddrcfgd, val); + + /* + * Set 'wr_dqs_shift' + */ + mtdcr(ddrcfga, DDR0_09); + val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK) + | DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift); + mtdcr(ddrcfgd, val); + debug("DDR0_09=0x%08lx\n", val); + + /* + * Set 'dqs_out_shift' = wr_dqs_shift + 32 + */ + dqs_out_shift = wr_dqs_shift + 32; + mtdcr(ddrcfga, DDR0_22); + val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK) + | DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift); + mtdcr(ddrcfgd, val); + debug("DDR0_22=0x%08lx\n", val); + + /* + * Set 'dll_dqs_delay_X'. + */ + /* dll_dqs_delay_0 */ + mtdcr(ddrcfga, DDR0_17); + val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK) + | DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_17=0x%08lx\n", val); + + /* dll_dqs_delay_1 to dll_dqs_delay_4 */ + mtdcr(ddrcfga, DDR0_18); + val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK) + | DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X) + | DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_18=0x%08lx\n", val); + + /* dll_dqs_delay_5 to dll_dqs_delay_8 */ + mtdcr(ddrcfga, DDR0_19); + val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK) + | DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X) + | DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X); + mtdcr(ddrcfgd, val); + debug("DDR0_19=0x%08lx\n", val); + + /* + * Assert 'start' parameter. + */ + mtdcr(ddrcfga, DDR0_02); + val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON; + mtdcr(ddrcfgd, val); + + ppcMsync(); + ppcMbar(); + + /* + * Wait for the DCC master delay line to finish calibration + */ + if (wait_for_dlllock() != 0) { + printf("dlllock did not occur !!!\n"); + hang(); + } + ppcMsync(); + ppcMbar(); + + if (wait_for_dram_init_complete() != 0) { + printf("dram init complete did not occur !!!\n"); + hang(); + } + udelay(100); /* wait 100us to ensure init is really completed !!! */ +} +#endif /* CONFIG_DDR_DATA_EYE */ + +#ifdef CONFIG_DDR_ECC +static void wait_ddr_idle(void) +{ + /* + * Controller idle status cannot be determined for Denali + * DDR2 code. Just return here. + */ +} + +static void blank_string(int size) +{ + int i; + + for (i=0; i>24)&0x7F) +/* Status */ +#define DDR0_00_INT_STATUS_MASK 0x00FF0000 /* Read only */ +/* Bit0. A single access outside the defined PHYSICAL memory space detected. */ +#define DDR0_00_INT_STATUS_BIT0 0x00010000 +/* Bit1. Multiple accesses outside the defined PHYSICAL memory space detected. */ +#define DDR0_00_INT_STATUS_BIT1 0x00020000 +/* Bit2. Single correctable ECC event detected */ +#define DDR0_00_INT_STATUS_BIT2 0x00040000 +/* Bit3. Multiple correctable ECC events detected. */ +#define DDR0_00_INT_STATUS_BIT3 0x00080000 +/* Bit4. Single uncorrectable ECC event detected. */ +#define DDR0_00_INT_STATUS_BIT4 0x00100000 +/* Bit5. Multiple uncorrectable ECC events detected. */ +#define DDR0_00_INT_STATUS_BIT5 0x00200000 +/* Bit6. DRAM initialization complete. */ +#define DDR0_00_INT_STATUS_BIT6 0x00400000 +/* Bit7. Logical OR of all lower bits. */ +#define DDR0_00_INT_STATUS_BIT7 0x00800000 + +#define DDR0_00_INT_STATUS_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_00_INT_STATUS_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_00_DLL_INCREMENT_MASK 0x00007F00 +#define DDR0_00_DLL_INCREMENT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_00_DLL_INCREMENT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_00_DLL_START_POINT_MASK 0x0000007F +#define DDR0_00_DLL_START_POINT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_00_DLL_START_POINT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + + +#define DDR0_01 0x01 +#define DDR0_01_PLB0_DB_CS_LOWER_MASK 0x1F000000 +#define DDR0_01_PLB0_DB_CS_LOWER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_01_PLB0_DB_CS_LOWER_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_01_PLB0_DB_CS_UPPER_MASK 0x001F0000 +#define DDR0_01_PLB0_DB_CS_UPPER_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define DDR0_01_PLB0_DB_CS_UPPER_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) +#define DDR0_01_OUT_OF_RANGE_TYPE_MASK 0x00000700 /* Read only */ +#define DDR0_01_OUT_OF_RANGE_TYPE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_01_OUT_OF_RANGE_TYPE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) +#define DDR0_01_INT_MASK_MASK 0x000000FF +#define DDR0_01_INT_MASK_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_01_INT_MASK_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) +#define DDR0_01_INT_MASK_ALL_ON 0x000000FF +#define DDR0_01_INT_MASK_ALL_OFF 0x00000000 + +#define DDR0_02 0x02 +#define DDR0_02_MAX_CS_REG_MASK 0x02000000 /* Read only */ +#define DDR0_02_MAX_CS_REG_ENCODE(n) ((((unsigned long)(n))&0x2)<<24) +#define DDR0_02_MAX_CS_REG_DECODE(n) ((((unsigned long)(n))>>24)&0x2) +#define DDR0_02_MAX_COL_REG_MASK 0x000F0000 /* Read only */ +#define DDR0_02_MAX_COL_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) +#define DDR0_02_MAX_COL_REG_DECODE(n) ((((unsigned long)(n))>>16)&0xF) +#define DDR0_02_MAX_ROW_REG_MASK 0x00000F00 /* Read only */ +#define DDR0_02_MAX_ROW_REG_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_02_MAX_ROW_REG_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_02_START_MASK 0x00000001 +#define DDR0_02_START_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_02_START_DECODE(n) ((((unsigned long)(n))>>0)&0x1) +#define DDR0_02_START_OFF 0x00000000 +#define DDR0_02_START_ON 0x00000001 + +#define DDR0_03 0x03 +#define DDR0_03_BSTLEN_MASK 0x07000000 +#define DDR0_03_BSTLEN_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_03_BSTLEN_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_03_CASLAT_MASK 0x00070000 +#define DDR0_03_CASLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_03_CASLAT_LIN_MASK 0x00000F00 +#define DDR0_03_CASLAT_LIN_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_03_CASLAT_LIN_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_03_INITAREF_MASK 0x0000000F +#define DDR0_03_INITAREF_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) +#define DDR0_03_INITAREF_DECODE(n) ((((unsigned long)(n))>>0)&0xF) + +#define DDR0_04 0x04 +#define DDR0_04_TRC_MASK 0x1F000000 +#define DDR0_04_TRC_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_04_TRC_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_04_TRRD_MASK 0x00070000 +#define DDR0_04_TRRD_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_04_TRRD_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_04_TRTP_MASK 0x00000700 +#define DDR0_04_TRTP_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_04_TRTP_DECODE(n) ((((unsigned long)(n))>>8)&0x7) + +#define DDR0_05 0x05 +#define DDR0_05_TMRD_MASK 0x1F000000 +#define DDR0_05_TMRD_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_05_TMRD_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_05_TEMRS_MASK 0x00070000 +#define DDR0_05_TEMRS_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_05_TEMRS_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_05_TRP_MASK 0x00000F00 +#define DDR0_05_TRP_ENCODE(n) ((((unsigned long)(n))&0xF)<<8) +#define DDR0_05_TRP_DECODE(n) ((((unsigned long)(n))>>8)&0xF) +#define DDR0_05_TRAS_MIN_MASK 0x000000FF +#define DDR0_05_TRAS_MIN_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_05_TRAS_MIN_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) + +#define DDR0_06 0x06 +#define DDR0_06_WRITEINTERP_MASK 0x01000000 +#define DDR0_06_WRITEINTERP_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_06_WRITEINTERP_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_06_TWTR_MASK 0x00070000 +#define DDR0_06_TWTR_ENCODE(n) ((((unsigned long)(n))&0x7)<<16) +#define DDR0_06_TWTR_DECODE(n) ((((unsigned long)(n))>>16)&0x7) +#define DDR0_06_TDLL_MASK 0x0000FF00 +#define DDR0_06_TDLL_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_06_TDLL_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) +#define DDR0_06_TRFC_MASK 0x0000007F +#define DDR0_06_TRFC_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_06_TRFC_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_07 0x07 +#define DDR0_07_NO_CMD_INIT_MASK 0x01000000 +#define DDR0_07_NO_CMD_INIT_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_07_NO_CMD_INIT_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_07_TFAW_MASK 0x001F0000 +#define DDR0_07_TFAW_ENCODE(n) ((((unsigned long)(n))&0x1F)<<16) +#define DDR0_07_TFAW_DECODE(n) ((((unsigned long)(n))>>16)&0x1F) +#define DDR0_07_AUTO_REFRESH_MODE_MASK 0x00000100 +#define DDR0_07_AUTO_REFRESH_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_07_AUTO_REFRESH_MODE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) +#define DDR0_07_AREFRESH_MASK 0x00000001 +#define DDR0_07_AREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_07_AREFRESH_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_08 0x08 +#define DDR0_08_WRLAT_MASK 0x07000000 +#define DDR0_08_WRLAT_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_08_WRLAT_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_08_TCPD_MASK 0x00FF0000 +#define DDR0_08_TCPD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_08_TCPD_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_08_DQS_N_EN_MASK 0x00000100 +#define DDR0_08_DQS_N_EN_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_08_DQS_N_EN_DECODE(n) ((((unsigned long)(n))>>8)&0x1) +#define DDR0_08_DDRII_SDRAM_MODE_MASK 0x00000001 +#define DDR0_08_DDRII_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_08_DDRII_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_09 0x09 +#define DDR0_09_OCD_ADJUST_PDN_CS_0_MASK 0x1F000000 +#define DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<24) +#define DDR0_09_OCD_ADJUST_PDN_CS_0_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_09_RTT_0_MASK 0x00030000 +#define DDR0_09_RTT_0_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) +#define DDR0_09_RTT_0_DECODE(n) ((((unsigned long)(n))>>16)&0x3) +#define DDR0_09_WR_DQS_SHIFT_BYPASS_MASK 0x00007F00 +#define DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_09_WR_DQS_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_09_WR_DQS_SHIFT_MASK 0x0000007F +#define DDR0_09_WR_DQS_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_09_WR_DQS_SHIFT_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_10 0x0A +#define DDR0_10_WRITE_MODEREG_MASK 0x00010000 /* Write only */ +#define DDR0_10_WRITE_MODEREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_10_WRITE_MODEREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_10_CS_MAP_MASK 0x00000300 +#define DDR0_10_CS_MAP_NO_MEM 0x00000000 +#define DDR0_10_CS_MAP_RANK0_INSTALLED 0x00000100 +#define DDR0_10_CS_MAP_RANK1_INSTALLED 0x00000200 +#define DDR0_10_CS_MAP_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) +#define DDR0_10_CS_MAP_DECODE(n) ((((unsigned long)(n))>>8)&0x3) +#define DDR0_10_OCD_ADJUST_PUP_CS_0_MASK 0x0000001F +#define DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(n) ((((unsigned long)(n))&0x1F)<<0) +#define DDR0_10_OCD_ADJUST_PUP_CS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x1F) + +#define DDR0_11 0x0B +#define DDR0_11_SREFRESH_MASK 0x01000000 +#define DDR0_11_SREFRESH_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_11_SREFRESH_DECODE(n) ((((unsigned long)(n))>>24)&0x1F) +#define DDR0_11_TXSNR_MASK 0x00FF0000 +#define DDR0_11_TXSNR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_11_TXSNR_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_11_TXSR_MASK 0x0000FF00 +#define DDR0_11_TXSR_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_11_TXSR_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) + +#define DDR0_12 0x0C +#define DDR0_12_TCKE_MASK 0x0000007 +#define DDR0_12_TCKE_ENCODE(n) ((((unsigned long)(n))&0x7)<<0) +#define DDR0_12_TCKE_DECODE(n) ((((unsigned long)(n))>>0)&0x7) + +#define DDR0_13 0x0D + +#define DDR0_14 0x0E +#define DDR0_14_DLL_BYPASS_MODE_MASK 0x01000000 +#define DDR0_14_DLL_BYPASS_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<24) +#define DDR0_14_DLL_BYPASS_MODE_DECODE(n) ((((unsigned long)(n))>>24)&0x1) +#define DDR0_14_REDUC_MASK 0x00010000 +#define DDR0_14_REDUC_64BITS 0x00000000 +#define DDR0_14_REDUC_32BITS 0x00010000 +#define DDR0_14_REDUC_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_14_REDUC_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_14_REG_DIMM_ENABLE_MASK 0x00000100 +#define DDR0_14_REG_DIMM_ENABLE_ENCODE(n) ((((unsigned long)(n))&0x1)<<8) +#define DDR0_14_REG_DIMM_ENABLE_DECODE(n) ((((unsigned long)(n))>>8)&0x1) + +#define DDR0_15 0x0F + +#define DDR0_16 0x10 + +#define DDR0_17 0x11 +#define DDR0_17_DLL_DQS_DELAY_0_MASK 0x7F000000 +#define DDR0_17_DLL_DQS_DELAY_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_17_DLL_DQS_DELAY_0_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */ +#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000 +#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000 +#define DDR0_17_DLLLOCKREG_ENCODE(n) ((((unsigned long)(n))&0x1)<<16) +#define DDR0_17_DLLLOCKREG_DECODE(n) ((((unsigned long)(n))>>16)&0x1) +#define DDR0_17_DLL_LOCK_MASK 0x00007F00 /* Read only */ +#define DDR0_17_DLL_LOCK_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_17_DLL_LOCK_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) + +#define DDR0_18 0x12 +#define DDR0_18_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F +#define DDR0_18_DLL_DQS_DELAY_4_MASK 0x7F000000 +#define DDR0_18_DLL_DQS_DELAY_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_18_DLL_DQS_DELAY_4_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_3_MASK 0x007F0000 +#define DDR0_18_DLL_DQS_DELAY_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_18_DLL_DQS_DELAY_3_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_2_MASK 0x00007F00 +#define DDR0_18_DLL_DQS_DELAY_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_18_DLL_DQS_DELAY_2_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_18_DLL_DQS_DELAY_1_MASK 0x0000007F +#define DDR0_18_DLL_DQS_DELAY_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_18_DLL_DQS_DELAY_1_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_19 0x13 +#define DDR0_19_DLL_DQS_DELAY_X_MASK 0x7F7F7F7F +#define DDR0_19_DLL_DQS_DELAY_8_MASK 0x7F000000 +#define DDR0_19_DLL_DQS_DELAY_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_19_DLL_DQS_DELAY_8_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_7_MASK 0x007F0000 +#define DDR0_19_DLL_DQS_DELAY_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_19_DLL_DQS_DELAY_7_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_6_MASK 0x00007F00 +#define DDR0_19_DLL_DQS_DELAY_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_19_DLL_DQS_DELAY_6_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_19_DLL_DQS_DELAY_5_MASK 0x0000007F +#define DDR0_19_DLL_DQS_DELAY_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_19_DLL_DQS_DELAY_5_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_20 0x14 +#define DDR0_20_DLL_DQS_BYPASS_3_MASK 0x7F000000 +#define DDR0_20_DLL_DQS_BYPASS_3_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_20_DLL_DQS_BYPASS_3_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_2_MASK 0x007F0000 +#define DDR0_20_DLL_DQS_BYPASS_2_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_20_DLL_DQS_BYPASS_2_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_1_MASK 0x00007F00 +#define DDR0_20_DLL_DQS_BYPASS_1_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_20_DLL_DQS_BYPASS_1_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_20_DLL_DQS_BYPASS_0_MASK 0x0000007F +#define DDR0_20_DLL_DQS_BYPASS_0_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_20_DLL_DQS_BYPASS_0_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_21 0x15 +#define DDR0_21_DLL_DQS_BYPASS_7_MASK 0x7F000000 +#define DDR0_21_DLL_DQS_BYPASS_7_ENCODE(n) ((((unsigned long)(n))&0x7F)<<24) +#define DDR0_21_DLL_DQS_BYPASS_7_DECODE(n) ((((unsigned long)(n))>>24)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_6_MASK 0x007F0000 +#define DDR0_21_DLL_DQS_BYPASS_6_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_21_DLL_DQS_BYPASS_6_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_5_MASK 0x00007F00 +#define DDR0_21_DLL_DQS_BYPASS_5_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_21_DLL_DQS_BYPASS_5_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_21_DLL_DQS_BYPASS_4_MASK 0x0000007F +#define DDR0_21_DLL_DQS_BYPASS_4_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_21_DLL_DQS_BYPASS_4_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + +#define DDR0_22 0x16 +/* ECC */ +#define DDR0_22_CTRL_RAW_MASK 0x03000000 +#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not being used */ +#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC checking is on, but no attempts to correct*/ +#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* No ECC RAM storage available */ +#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC checking and correcting on */ +#define DDR0_22_CTRL_RAW_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_22_CTRL_RAW_DECODE(n) ((((unsigned long)(n))>>24)&0x3) + +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_MASK 0x007F0000 +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(n) ((((unsigned long)(n))&0x7F)<<16) +#define DDR0_22_DQS_OUT_SHIFT_BYPASS_DECODE(n) ((((unsigned long)(n))>>16)&0x7F) +#define DDR0_22_DQS_OUT_SHIFT_MASK 0x00007F00 +#define DDR0_22_DQS_OUT_SHIFT_ENCODE(n) ((((unsigned long)(n))&0x7F)<<8) +#define DDR0_22_DQS_OUT_SHIFT_DECODE(n) ((((unsigned long)(n))>>8)&0x7F) +#define DDR0_22_DLL_DQS_BYPASS_8_MASK 0x0000007F +#define DDR0_22_DLL_DQS_BYPASS_8_ENCODE(n) ((((unsigned long)(n))&0x7F)<<0) +#define DDR0_22_DLL_DQS_BYPASS_8_DECODE(n) ((((unsigned long)(n))>>0)&0x7F) + + +#define DDR0_23 0x17 +#define DDR0_23_ODT_RD_MAP_CS0_MASK 0x03000000 +#define DDR0_23_ODT_RD_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_23_ODT_RD_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>24)&0x3) +#define DDR0_23_ECC_C_SYND_MASK 0x00FF0000 /* Read only */ +#define DDR0_23_ECC_C_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<16) +#define DDR0_23_ECC_C_SYND_DECODE(n) ((((unsigned long)(n))>>16)&0xFF) +#define DDR0_23_ECC_U_SYND_MASK 0x0000FF00 /* Read only */ +#define DDR0_23_ECC_U_SYND_ENCODE(n) ((((unsigned long)(n))&0xFF)<<8) +#define DDR0_23_ECC_U_SYND_DECODE(n) ((((unsigned long)(n))>>8)&0xFF) +#define DDR0_23_FWC_MASK 0x00000001 /* Write only */ +#define DDR0_23_FWC_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_23_FWC_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_24 0x18 +#define DDR0_24_RTT_PAD_TERMINATION_MASK 0x03000000 +#define DDR0_24_RTT_PAD_TERMINATION_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define DDR0_24_RTT_PAD_TERMINATION_DECODE(n) ((((unsigned long)(n))>>24)&0x3) +#define DDR0_24_ODT_WR_MAP_CS1_MASK 0x00030000 +#define DDR0_24_ODT_WR_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<16) +#define DDR0_24_ODT_WR_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>16)&0x3) +#define DDR0_24_ODT_RD_MAP_CS1_MASK 0x00000300 +#define DDR0_24_ODT_RD_MAP_CS1_ENCODE(n) ((((unsigned long)(n))&0x3)<<8) +#define DDR0_24_ODT_RD_MAP_CS1_DECODE(n) ((((unsigned long)(n))>>8)&0x3) +#define DDR0_24_ODT_WR_MAP_CS0_MASK 0x00000003 +#define DDR0_24_ODT_WR_MAP_CS0_ENCODE(n) ((((unsigned long)(n))&0x3)<<0) +#define DDR0_24_ODT_WR_MAP_CS0_DECODE(n) ((((unsigned long)(n))>>0)&0x3) + +#define DDR0_25 0x19 +#define DDR0_25_VERSION_MASK 0xFFFF0000 /* Read only */ +#define DDR0_25_VERSION_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) +#define DDR0_25_VERSION_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) +#define DDR0_25_OUT_OF_RANGE_LENGTH_MASK 0x000003FF /* Read only */ +#define DDR0_25_OUT_OF_RANGE_LENGTH_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) +#define DDR0_25_OUT_OF_RANGE_LENGTH_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) + +#define DDR0_26 0x1A +#define DDR0_26_TRAS_MAX_MASK 0xFFFF0000 +#define DDR0_26_TRAS_MAX_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) +#define DDR0_26_TRAS_MAX_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) +#define DDR0_26_TREF_MASK 0x00003FFF +#define DDR0_26_TREF_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<0) +#define DDR0_26_TREF_DECODE(n) ((((unsigned long)(n))>>0)&0x3FF) + +#define DDR0_27 0x1B +#define DDR0_27_EMRS_DATA_MASK 0x3FFF0000 +#define DDR0_27_EMRS_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) +#define DDR0_27_EMRS_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) +#define DDR0_27_TINIT_MASK 0x0000FFFF +#define DDR0_27_TINIT_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) +#define DDR0_27_TINIT_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) + +#define DDR0_28 0x1C +#define DDR0_28_EMRS3_DATA_MASK 0x3FFF0000 +#define DDR0_28_EMRS3_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<16) +#define DDR0_28_EMRS3_DATA_DECODE(n) ((((unsigned long)(n))>>16)&0x3FFF) +#define DDR0_28_EMRS2_DATA_MASK 0x00003FFF +#define DDR0_28_EMRS2_DATA_ENCODE(n) ((((unsigned long)(n))&0x3FFF)<<0) +#define DDR0_28_EMRS2_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0x3FFF) + +#define DDR0_29 0x1D + +#define DDR0_30 0x1E + +#define DDR0_31 0x1F +#define DDR0_31_XOR_CHECK_BITS_MASK 0x0000FFFF +#define DDR0_31_XOR_CHECK_BITS_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<0) +#define DDR0_31_XOR_CHECK_BITS_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFF) + +#define DDR0_32 0x20 +#define DDR0_32_OUT_OF_RANGE_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_32_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_32_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_33 0x21 +#define DDR0_33_OUT_OF_RANGE_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_33_OUT_OF_RANGE_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_33_OUT_OF_RANGE_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_34 0x22 +#define DDR0_34_ECC_U_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_34_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_34_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_35 0x23 +#define DDR0_35_ECC_U_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_35_ECC_U_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_35_ECC_U_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_36 0x24 +#define DDR0_36_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_36_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_36_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_37 0x25 +#define DDR0_37_ECC_U_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_37_ECC_U_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_37_ECC_U_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_38 0x26 +#define DDR0_38_ECC_C_ADDR_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_38_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_38_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_39 0x27 +#define DDR0_39_ECC_C_ADDR_MASK 0x00000001 /* Read only */ +#define DDR0_39_ECC_C_ADDR_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_39_ECC_C_ADDR_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_40 0x28 +#define DDR0_40_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_40_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_40_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_41 0x29 +#define DDR0_41_ECC_C_DATA_MASK 0xFFFFFFFF /* Read only */ +#define DDR0_41_ECC_C_DATA_ENCODE(n) ((((unsigned long)(n))&0xFFFFFFFF)<<0) +#define DDR0_41_ECC_C_DATA_DECODE(n) ((((unsigned long)(n))>>0)&0xFFFFFFFF) + +#define DDR0_42 0x2A +#define DDR0_42_ADDR_PINS_MASK 0x07000000 +#define DDR0_42_ADDR_PINS_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_42_ADDR_PINS_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_42_CASLAT_LIN_GATE_MASK 0x0000000F +#define DDR0_42_CASLAT_LIN_GATE_ENCODE(n) ((((unsigned long)(n))&0xF)<<0) +#define DDR0_42_CASLAT_LIN_GATE_DECODE(n) ((((unsigned long)(n))>>0)&0xF) + +#define DDR0_43 0x2B +#define DDR0_43_TWR_MASK 0x07000000 +#define DDR0_43_TWR_ENCODE(n) ((((unsigned long)(n))&0x7)<<24) +#define DDR0_43_TWR_DECODE(n) ((((unsigned long)(n))>>24)&0x7) +#define DDR0_43_APREBIT_MASK 0x000F0000 +#define DDR0_43_APREBIT_ENCODE(n) ((((unsigned long)(n))&0xF)<<16) +#define DDR0_43_APREBIT_DECODE(n) ((((unsigned long)(n))>>16)&0xF) +#define DDR0_43_COLUMN_SIZE_MASK 0x00000700 +#define DDR0_43_COLUMN_SIZE_ENCODE(n) ((((unsigned long)(n))&0x7)<<8) +#define DDR0_43_COLUMN_SIZE_DECODE(n) ((((unsigned long)(n))>>8)&0x7) +#define DDR0_43_EIGHT_BANK_MODE_MASK 0x00000001 +#define DDR0_43_EIGHT_BANK_MODE_8_BANKS 0x00000001 +#define DDR0_43_EIGHT_BANK_MODE_4_BANKS 0x00000000 +#define DDR0_43_EIGHT_BANK_MODE_ENCODE(n) ((((unsigned long)(n))&0x1)<<0) +#define DDR0_43_EIGHT_BANK_MODE_DECODE(n) ((((unsigned long)(n))>>0)&0x1) + +#define DDR0_44 0x2C +#define DDR0_44_TRCD_MASK 0x000000FF +#define DDR0_44_TRCD_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) +#define DDR0_44_TRCD_DECODE(n) ((((unsigned long)(n))>>0)&0xFF) + +#endif /* _SPD_SDRAM_DENALI_H_ */ diff --git a/board/lwmon5/u-boot.lds b/board/lwmon5/u-boot.lds new file mode 100644 index 00000000000..a423f982858 --- /dev/null +++ b/board/lwmon5/u-boot.lds @@ -0,0 +1,145 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + .bootpg 0xFFFFF000 : + { + cpu/ppc4xx/start.o (.bootpg) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + + ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified."); + + _end = . ; + PROVIDE (end = .); +} diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h new file mode 100644 index 00000000000..e6e0f422e70 --- /dev/null +++ b/include/configs/lwmon5.h @@ -0,0 +1,437 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * lwmon5.h - configuration for lwmon5 board + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_LWMON5 1 /* Board is lwmon5 */ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_ADD_RAM_INFO 1 /* Print additional info */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */ + +#define CFG_BOOT_BASE_ADDR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_LIME_BASE_0 0xc0000000 +#define CFG_LIME_BASE_1 0xc1000000 +#define CFG_LIME_BASE_2 0xc2000000 +#define CFG_LIME_BASE_3 0xc3000000 +#define CFG_FPGA_BASE_0 0xc4000000 +#define CFG_FPGA_BASE_1 0xc4200000 +#define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 + +/* Don't change either of these */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ + +#define CFG_USB2D0_BASE 0xe0000100 +#define CFG_USB_DEVICE 0xe0000000 +#define CFG_USB_HOST 0xe0000400 + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ +#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ + +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* no external clock provided */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +/* define this if you want console on UART1 */ +#define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */ + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (256) /* 256MB */ +#define CFG_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */ +#define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */ +#if 0 /* test-only: disable ECC for now */ +#define CONFIG_DDR_ECC 1 /* enable ECC */ +#endif + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +#define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */ +#define CFG_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hostname=lwmon5\0" \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xxFP\0" \ + "bootfile=/tftpboot/lwmon5/uImage\0" \ + "kernel_addr=FC000000\0" \ + "ramdisk_addr=FC180000\0" \ + "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ + "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \ + "cp.b 200000 FFF80000 80000\0" \ + "upd=run load;run update\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR 1 + +/* USB */ +#ifdef CONFIG_440EPX +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +/* Comment this out to enable USB 1.1 device */ +#define USB_2_0_DEVICE + +#define CMD_USB CFG_CMD_USB +#else +#define CMD_USB 0 /* no USB on 440GRx */ +#endif /* CONFIG_440EPX */ + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CMD_USB) + +#define CONFIG_SUPPORT_VFAT + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ +#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */ + +#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE + +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x03050200 +#define CFG_EBC_PB0CR (CFG_FLASH | 0xdc000) + +/* Memory Bank 1 (Lime) initialization */ +#define CFG_EBC_PB1AP 0x01004380 +#define CFG_EBC_PB1CR (CFG_LIME_BASE_0 | 0xdc000) + +/* Memory Bank 2 (FPGA) initialization */ +#define CFG_EBC_PB2AP 0x01004400 +#define CFG_EBC_PB2CR (CFG_FPGA_BASE_0 | 0x1c000) + +/* Memory Bank 3 (FPGA2) initialization */ +#define CFG_EBC_PB3AP 0x01004400 +#define CFG_EBC_PB3CR (CFG_FPGA_BASE_1 | 0x1c000) + +#define CFG_EBC_CFG 0xb8400000 + +/*----------------------------------------------------------------------- + * GPIO Setup + *----------------------------------------------------------------------*/ +#define CFG_GPIO_PHY1_RST 12 +#define CFG_GPIO_FLASH_WP 14 +#define CFG_GPIO_PHY0_RST 22 +#define CFG_GPIO_HUB_RST 50 +#define CFG_GPIO_WATCHDOG 58 +#define CFG_GPIO_LIME_S 59 +#define CFG_GPIO_LIME_RST 60 + +/*----------------------------------------------------------------------- + * PPC440 GPIO Configuration + */ +#define CFG_440_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \ +{ \ +/* GPIO Core 0 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \ +{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \ +{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \ +}, \ +{ \ +/* GPIO Core 1 */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \ +{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ +{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO58 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \ +} \ +} + +/*----------------------------------------------------------------------- + * Cache Configuration + *----------------------------------------------------------------------*/ +#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ diff --git a/include/ppc440.h b/include/ppc440.h index 07f75de08e6..a7efcee7e9d 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -956,7 +956,8 @@ #define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) #define plb1_bearh (PLB_ARBITER_BASE+ 0x0D) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* Pin Function Control Register 1 */ #define SDR0_PFC1 0x4101 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ @@ -1103,6 +1104,8 @@ #define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */ #define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */ +#define SDR0_PFC4 0x4104 + /* USB2PHY0 Control Register */ #define SDR0_USB2PHY0CR 0x4103 #define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */ -- cgit v1.3.1 From efa35cf12d914d4caba942acd5a6c45f217de302 Mon Sep 17 00:00:00 2001 From: Grzegorz Bernacki Date: Fri, 15 Jun 2007 11:19:28 +0200 Subject: ppc4xx: Clean up 440 exceptions handling - Introduced dedicated switches for building 440 and 405 images required for 440-specific machine instructions like 'rfmci' etc. - Exception vectors moved to the proper location (_start moved away from the critical exception handler space, which it occupied) - CriticalInput now serviced (with default handler) - MachineCheck properly serviced (added a dedicated handler and return subroutine) - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, unhandled and those not relevant for 4xx were eliminated) - Eliminated Linux leftovers, removed dead code Signed-off-by: Grzegorz Bernacki Signed-off-by: Rafal Jaworowski Signed-off-by: Stefan Roese --- cpu/ppc4xx/config.mk | 10 +- cpu/ppc4xx/start.S | 329 ++++++++++++++++++++++---------------------- cpu/ppc4xx/traps.c | 107 ++++++++------ include/asm-ppc/processor.h | 15 +- include/configs/CPCI440.h | 1 + include/configs/KAREF.h | 1 + include/configs/METROBOX.h | 1 + include/configs/alpr.h | 1 + include/configs/bamboo.h | 1 + include/configs/ebony.h | 1 + include/configs/katmai.h | 2 +- include/configs/ocotea.h | 1 + include/configs/p3p440.h | 1 + include/configs/pcs440ep.h | 1 + include/configs/sequoia.h | 1 + include/configs/taishan.h | 1 + include/configs/yosemite.h | 1 + include/ppc405.h | 9 ++ include/ppc440.h | 5 +- include/ppc4xx.h | 1 + include/ppc_asm.tmpl | 96 ++++++------- 21 files changed, 319 insertions(+), 267 deletions(-) (limited to 'include') diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk index 119e061b89e..e7fc3f636e6 100644 --- a/cpu/ppc4xx/config.mk +++ b/cpu/ppc4xx/config.mk @@ -22,5 +22,13 @@ # PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing +PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -msoft-float -PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -Wa,-m405 -mcpu=405 -msoft-float +cfg=$(shell grep configs $(TOPDIR)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') +is440=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg)) + +ifneq (,$(findstring CONFIG_440,$(is440))) +PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440 +else +PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405 +endif diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 78d0042cc76..e135220f6d0 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -294,11 +294,13 @@ skip_debug_init: mtspr ivor7,r1 /* Floating point unavailable */ li r1,0x0c00 mtspr ivor8,r1 /* System call */ - li r1,0x1000 - mtspr ivor10,r1 /* Decrementer (PIT for 440) */ - li r1,0x1400 - mtspr ivor13,r1 /* Data TLB error */ + li r1,0x0a00 + mtspr ivor9,r1 /* Auxiliary Processor unavailable */ + li r1,0x0900 + mtspr ivor10,r1 /* Decrementer */ li r1,0x1300 + mtspr ivor13,r1 /* Data TLB error */ + li r1,0x1400 mtspr ivor14,r1 /* Instr TLB error */ li r1,0x2000 mtspr ivor15,r1 /* Debug */ @@ -503,11 +505,81 @@ version_string: .ascii " (", __DATE__, " - ", __TIME__, ")" .ascii CONFIG_IDENT_STRING, "\0" -/* - * Maybe this should be moved somewhere else because the current - * location (0x100) is where the CriticalInput Execption should be. - */ . = EXC_OFF_SYS_RESET + .globl _start_of_vectors +_start_of_vectors: + +/* Critical input. */ + CRIT_EXCEPTION(0x100, CritcalInput, UnknownException) + +#ifdef CONFIG_440 +/* Machine check */ + MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) +#else + CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) +#endif /* CONFIG_440 */ + +/* Data Storage exception. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG(SRR0, SRR1) + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + _START_OFFSET + .long int_return - _start + _START_OFFSET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG(SRR0, SRR1) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + _START_OFFSET + .long int_return - _start + _START_OFFSET + +#ifdef CONFIG_440 + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + STD_EXCEPTION(0x900, Decrementer, DecrementerPITException) + STD_EXCEPTION(0xa00, APU, UnknownException) +#endif + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + +#ifdef CONFIG_440 + STD_EXCEPTION(0x1300, DataTLBError, UnknownException) + STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException) +#else + STD_EXCEPTION(0x1000, PIT, DecrementerPITException) + STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) + STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) +#endif + CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) + + .globl _end_of_vectors +_end_of_vectors: + . = _START_OFFSET #endif .globl _start _start: @@ -1017,107 +1089,6 @@ start_ram: #ifndef CONFIG_NAND_SPL -/*****************************************************************************/ - .globl _start_of_vectors -_start_of_vectors: - -#if 0 -/*TODO Fixup _start above so we can do this*/ -/* Critical input. */ - CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException) -#endif - -/* Machine check */ - CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) - -/* Data Storage exception. */ - STD_EXCEPTION(0x300, DataStorage, UnknownException) - -/* Instruction Storage exception. */ - STD_EXCEPTION(0x400, InstStorage, UnknownException) - -/* External Interrupt exception. */ - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) - -/* Alignment exception. */ - . = 0x600 -Alignment: - EXCEPTION_PROLOG - mfspr r4,DAR - stw r4,_DAR(r21) - mfspr r5,DSISR - stw r5,_DSISR(r21) - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_Alignment: - .long AlignmentException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - -/* Program check exception */ - . = 0x700 -ProgramCheck: - EXCEPTION_PROLOG - addi r3,r1,STACK_FRAME_OVERHEAD - li r20,MSR_KERNEL - rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ - lwz r6,GOT(transfer_to_handler) - mtlr r6 - blrl -.L_ProgramCheck: - .long ProgramCheckException - _start + EXC_OFF_SYS_RESET - .long int_return - _start + EXC_OFF_SYS_RESET - - /* No FPU on MPC8xx. This exception is not supposed to happen. - */ - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) - - /* I guess we could implement decrementer, and may have - * to someday for timekeeping. - */ - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) - STD_EXCEPTION(0xc00, SystemCall, UnknownException) - STD_EXCEPTION(0xd00, SingleStep, UnknownException) - - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) - - /* On the MPC8xx, this is a software emulation interrupt. It occurs - * for all unimplemented and illegal instructions. - */ - STD_EXCEPTION(0x1000, PIT, PITException) - - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) - STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) - STD_EXCEPTION(0x1400, DataTLBError, UnknownException) - - STD_EXCEPTION(0x1500, Reserved5, UnknownException) - STD_EXCEPTION(0x1600, Reserved6, UnknownException) - STD_EXCEPTION(0x1700, Reserved7, UnknownException) - STD_EXCEPTION(0x1800, Reserved8, UnknownException) - STD_EXCEPTION(0x1900, Reserved9, UnknownException) - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) - - STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) - STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) - STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) - STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) - - CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) - - .globl _end_of_vectors -_end_of_vectors: - - - . = 0x2100 - /* * This code finishes saving the registers to the exception frame * and jumps to the appropriate handler for the exception. @@ -1133,28 +1104,12 @@ transfer_to_handler: SAVE_4GPRS(8, r21) SAVE_8GPRS(12, r21) SAVE_8GPRS(24, r21) -#if 0 - andi. r23,r23,MSR_PR - mfspr r23,SPRG3 /* if from user, fix up tss.regs */ - beq 2f - addi r24,r1,STACK_FRAME_OVERHEAD - stw r24,PT_REGS(r23) -2: addi r2,r23,-TSS /* set r2 to current */ - tovirt(r2,r2,r23) -#endif mflr r23 andi. r24,r23,0x3f00 /* get vector offset */ stw r24,TRAP(r21) li r22,0 stw r22,RESULT(r21) mtspr SPRG2,r22 /* r1 is now kernel sp */ -#if 0 - addi r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */ - cmplw 0,r1,r2 - cmplw 1,r1,r24 - crand 1,1,4 - bgt stack_ovf /* if r2 < r1 < r2+TASK_STRUCT_SIZE */ -#endif lwz r24,0(r23) /* virtual address of handler */ lwz r23,4(r23) /* where to go when done */ mtspr SRR0,r24 @@ -1215,16 +1170,64 @@ crit_return: REST_GPR(31, r1) lwz r2,_NIP(r1) /* Restore environment */ lwz r0,_MSR(r1) - mtspr 990,r2 /* SRR2 */ - mtspr 991,r0 /* SRR3 */ + mtspr csrr0,r2 + mtspr csrr1,r0 lwz r0,GPR0(r1) lwz r2,GPR2(r1) lwz r1,GPR1(r1) SYNC rfci -/* Cache functions. -*/ +#ifdef CONFIG_440 +mck_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr mcsrr0,r2 + mtspr mcsrr1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfmci +#endif /* CONFIG_440 */ + + +/* + * Cache functions. + * + * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM, + * although for some cache-ralated calls stubs have to be provided to satisfy + * symbols resolution. + * + */ +#ifdef CONFIG_440 + .globl dcache_disable +dcache_disable: + blr + + .globl dcache_status +dcache_status: + blr +#else flush_dcache: addis r9,r0,0x0002 /* set mask for EE and CE msr bits */ ori r9,r9,0x8000 @@ -1303,24 +1306,13 @@ dcache_status: mfdccr r3 srwi r3, r3, 31 /* >>31 => select bit 0 */ blr +#endif .globl get_pvr get_pvr: mfspr r3, PVR blr -#if !defined(CONFIG_440) - .globl wr_pit -wr_pit: - mtspr pit, r3 - blr -#endif - - .globl wr_tcr -wr_tcr: - mtspr tcr, r3 - blr - /*------------------------------------------------------------------------------- */ /* Function: out16 */ /* Description: Output 16 bits */ @@ -1518,7 +1510,7 @@ relocate_code: * initialization, now running from RAM. */ - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + addi r0, r10, in_ram - _start + _START_OFFSET mtlr r0 blr /* NEVER RETURNS! */ @@ -1588,7 +1580,7 @@ clear_bss: */ .globl trap_init trap_init: - lwz r7, GOT(_start) + lwz r7, GOT(_start_of_vectors) lwz r8, GOT(_end_of_vectors) li r9, 0x100 /* reset vector always at 0x100 */ @@ -1608,35 +1600,48 @@ trap_init: /* * relocate `hdlr' and `int_return' entries */ - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET - li r8, Alignment - _start + EXC_OFF_SYS_RESET + li r7, .L_MachineCheck - _start + _START_OFFSET + li r8, Alignment - _start + _START_OFFSET 2: bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ + addi r7, r7, 0x100 /* next exception vector */ cmplw 0, r7, r8 blt 2b - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + li r7, .L_Alignment - _start + _START_OFFSET bl trap_reloc - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + li r7, .L_ProgramCheck - _start + _START_OFFSET bl trap_reloc - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET - li r8, SystemCall - _start + EXC_OFF_SYS_RESET -3: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 3b +#ifdef CONFIG_440 + li r7, .L_FPUnavailable - _start + _START_OFFSET + bl trap_reloc - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET -4: - bl trap_reloc - addi r7, r7, 0x100 /* next exception vector */ - cmplw 0, r7, r8 - blt 4b + li r7, .L_Decrementer - _start + _START_OFFSET + bl trap_reloc + + li r7, .L_APU - _start + _START_OFFSET + bl trap_reloc + + li r7, .L_InstructionTLBError - _start + _START_OFFSET + bl trap_reloc + + li r7, .L_DataTLBError - _start + _START_OFFSET + bl trap_reloc +#else /* CONFIG_440 */ + li r7, .L_PIT - _start + _START_OFFSET + bl trap_reloc + + li r7, .L_InstructionTLBMiss - _start + _START_OFFSET + bl trap_reloc + + li r7, .L_DataTLBMiss - _start + _START_OFFSET + bl trap_reloc +#endif /* CONFIG_440 */ + + li r7, .L_DebugBreakpoint - _start + _START_OFFSET + bl trap_reloc #if !defined(CONFIG_440) addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index 6aecca2db90..54659d33702 100644 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -36,6 +36,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + #if (CONFIG_COMMANDS & CFG_CMD_KGDB) int (*debugger_exception_handler)(struct pt_regs *) = 0; #endif @@ -45,8 +47,7 @@ extern unsigned long search_exception_table(unsigned long); /* THIS NEEDS CHANGING to use the board info structure. */ -#define END_OF_MEM 0x00400000 - +#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) static __inline__ void set_tsr(unsigned long val) { @@ -88,29 +89,29 @@ extern void do_bedbug_breakpoint(struct pt_regs *); void print_backtrace(unsigned long *sp) { - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); + int cnt = 0; + unsigned long i; + + printf("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + printf("\n"); + printf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + printf("\n"); } void show_regs(struct pt_regs * regs) { int i; - printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + printf("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DEAR: %08lX\n", regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); printf("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", regs->msr, regs->msr&MSR_EE ? 1 : 0, regs->msr&MSR_PR ? 1 : 0, @@ -139,14 +140,14 @@ _exception(int signr, struct pt_regs *regs) { show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); - panic("Exception in kernel pc %lx signal %d",regs->nip,signr); + panic("Exception"); } void MachineCheckException(struct pt_regs *regs) { - unsigned long fixup; - + unsigned long fixup, val; + /* Probing PCI using config cycles cause this exception * when a device is not present. Catch it and return to * the PCI exception handler. @@ -161,26 +162,50 @@ MachineCheckException(struct pt_regs *regs) return; #endif - printf("Machine check in kernel mode.\n"); + printf("Machine Check Exception.\n"); printf("Caused by (from msr): "); - printf("regs %p ",regs); - switch( regs->msr & 0x000F0000) { - case (0x80000000>>12): - printf("Machine check signal - probably due to mm fault\n" - "with mmu off\n"); - break; - case (0x80000000>>13): - printf("Transfer error ack signal\n"); - break; - case (0x80000000>>14): - printf("Data parity signal\n"); - break; - case (0x80000000>>15): - printf("Address parity signal\n"); - break; - default: - printf("Unknown values in msr\n"); + printf("regs %p ", regs); + + val = get_esr(); + +#if !defined(CONFIG_440) + if (val& ESR_IMCP) { + printf("Instruction"); + mtspr(ESR, val & ~ESR_IMCP); + } else + printf("Data"); + printf(" machine check.\n"); + +#elif defined(CONFIG_440) + if (val& ESR_IMCP){ + printf("Instruction Synchronous Machine Check exception\n"); + mtspr(SPRN_ESR, val & ~ESR_IMCP); } + else { + val = mfspr(MCSR); + if (val & MCSR_IB) + printf("Instruction Read PLB Error\n"); + if (val & MCSR_DRB) + printf("Data Read PLB Error\n"); + if (val & MCSR_DWB) + printf("Data Write PLB Error\n"); + if (val & MCSR_TLBP) + printf("TLB Parity Error\n"); + if (val & MCSR_ICP){ + /*flush_instruction_cache(); */ + printf("I-Cache Parity Error\n"); + } + if (val & MCSR_DCSP) + printf("D-Cache Search Parity Error\n"); + if (val & MCSR_DCFP) + printf("D-Cache Flush Parity Error\n"); + if (val & MCSR_IMPE) + printf("Machine Check exception is imprecise\n"); + + /* Clear MCSR */ + mtspr(SPRN_MCSR, val); + } +#endif show_regs(regs); print_backtrace((unsigned long *)regs->gpr[1]); panic("machine check"); @@ -224,7 +249,7 @@ ProgramCheckException(struct pt_regs *regs) } void -PITException(struct pt_regs *regs) +DecrementerPITException(struct pt_regs *regs) { /* * Reset PIT interrupt diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 5efc3ee2ca7..29e6101a157 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -308,7 +308,7 @@ #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ -#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ +#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ #ifdef CONFIG_BOOKE #define SPRN_SVR 0x3FF /* System Version Register */ #else @@ -451,6 +451,17 @@ #define SPRN_PID1 0x279 /* Process ID Register 1 */ #define SPRN_PID2 0x27a /* Process ID Register 2 */ #define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ +#ifdef CONFIG_440 +#define MCSR_MCS 0x80000000 /* Machine Check Summary */ +#define MCSR_IB 0x40000000 /* Instruction PLB Error */ +#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ +#define MCSR_DWB 0x10000000 /* Data Write PLB Error */ +#define MCSR_TLBP 0x08000000 /* TLB Parity Error */ +#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ +#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ +#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ +#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ +#endif #define ESR_ST 0x00800000 /* Store Operation */ #if defined(CONFIG_MPC86xx) @@ -544,6 +555,8 @@ #define SPRG7 SPRN_SPRG7 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ +#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */ +#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */ #define SVR SPRN_SVR /* System Version Register */ #define TBRL SPRN_TBRL /* Time Base Read Lower Register */ #define TBRU SPRN_TBRU /* Time Base Read Upper Register */ diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h index 90d3a8d8fa3..7b5f72836e6 100644 --- a/include/configs/CPCI440.h +++ b/include/configs/CPCI440.h @@ -33,6 +33,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_CPCI440 1 /* Board is ebony */ #define CONFIG_440GP 1 /* Specifc GP support */ +#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #undef CFG_DRAM_TEST /* Disable-takes long time! */ diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 2ad6f06985a..fd9bd316273 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -38,6 +38,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_KAREF 1 /* Board is Kamino Ref Variant */ #define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 465a4ecb8b9..148fe9a5c32 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -104,6 +104,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_METROBOX 1 /* Board is Metrobox */ #define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_MISC_INIT_F 1 /* Call board misc_init_f */ diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 67f62d3dfbe..47893e824dd 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -29,6 +29,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_ALPR 1 /* Board is ebony */ #define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 763d1c7a8b4..af337eee8ea 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -32,6 +32,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_BAMBOO 1 /* Board is BAMBOO */ #define CONFIG_440EP 1 /* Specific PPC440EP support */ +#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index a42319b097d..5bd326b9aee 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -32,6 +32,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_EBONY 1 /* Board is ebony */ #define CONFIG_440GP 1 /* Specifc GP support */ +#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #undef CFG_DRAM_TEST /* Disable-takes long time! */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index cc47a168ed3..e6ebe3815d6 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -29,7 +29,7 @@ #ifndef __CONFIG_H #define __CONFIG_H - +//#define DEBUG /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index fe4e63810ee..31f8bb3fddf 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -41,6 +41,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_OCOTEA 1 /* Board is ebony */ #define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #undef CFG_DRAM_TEST /* Disable-takes long time! */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index aa0901f3ff4..cae5bd56f86 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -35,6 +35,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_P3P440 1 /* Board is P3P440 */ #define CONFIG_440GP 1 /* Specifc GP support */ +#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 23bdfc8dfb9..638031f48f6 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -32,6 +32,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_PCS440EP 1 /* Board is PCS440EP */ #define CONFIG_440EP 1 /* Specific PPC440EP support */ +#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 23243a4971a..42b42fc57f3 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -37,6 +37,7 @@ #else #define CONFIG_440GRX 1 /* Specific PPC440GRx */ #endif +#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ /* Detect Sequoia PLL input clock automatically via CPLD bit */ #define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \ diff --git a/include/configs/taishan.h b/include/configs/taishan.h index 2b28f93a071..cbbb0066e92 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -30,6 +30,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_TAISHAN 1 /* Board is taishan */ #define CONFIG_440GX 1 /* Specifc GX support */ +#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #undef CFG_DRAM_TEST /* Disable-takes long time! */ #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index b68ae54b94d..c96b14e8391 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -38,6 +38,7 @@ #define CONFIG_440GR 1 /* Specific PPC440GR support */ #define CONFIG_HOSTNAME yellowstone #endif +#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ diff --git a/include/ppc405.h b/include/ppc405.h index 71ad12e5159..6be2a50db75 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -27,6 +27,15 @@ /*--------------------------------------------------------------------- */ #define srr2 0x3de /* save/restore register 2 */ #define srr3 0x3df /* save/restore register 3 */ + + /* + * 405 does not really have CSRR0/1 but SRR2/3 are used during critical + * exception for the exact same purposes - let's alias them and have a + * common handling in crit_return() and CRIT_EXCEPTION + */ + #define csrr0 srr2 + #define csrr1 srr3 + #define dbsr 0x3f0 /* debug status register */ #define dbcr0 0x3f2 /* debug control register 0 */ #define dbcr1 0x3bd /* debug control register 1 */ diff --git a/include/ppc440.h b/include/ppc440.h index 07f75de08e6..4bb644e38a8 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -82,10 +82,7 @@ #define ivor13 0x19d /* interrupt vector offset register 13 */ #define ivor14 0x19e /* interrupt vector offset register 14 */ #define ivor15 0x19f /* interrupt vector offset register 15 */ -#if defined(CONFIG_440GX) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440) #define mcsrr0 0x23a /* machine check save/restore register 0 */ #define mcsrr1 0x23b /* mahcine check save/restore register 1 */ #define mcsr 0x23c /* machine check status register */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 67759c7336a..8cead66ad1a 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -22,6 +22,7 @@ #ifndef __PPC4XX_H__ #define __PPC4XX_H__ +#define _START_OFFSET 0x2100 #if defined(CONFIG_440) #include diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 3e47e82abad..f15628aa2e5 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -217,7 +217,7 @@ * We assume sprg3 has the physical address of the current * task's thread_struct. */ -#define EXCEPTION_PROLOG \ +#define EXCEPTION_PROLOG(reg1, reg2) \ mtspr SPRG0,r20; \ mtspr SPRG1,r21; \ mfcr r20; \ @@ -235,8 +235,10 @@ stw r22,_CTR(r21); \ mfspr r20,XER; \ stw r20,_XER(r21); \ - mfspr r22,SRR0; \ - mfspr r23,SRR1; \ + mfspr r20,DEAR; \ + stw r20,_DAR(r21); \ + mfspr r22,reg1; \ + mfspr r23,reg2; \ stw r0,GPR0(r21); \ stw r1,GPR1(r21); \ stw r2,GPR2(r21); \ @@ -248,41 +250,6 @@ * r21, r22 (SRR0), and r23 (SRR1). */ -/* - * Critical exception entry code. This is just like the other exception - * code except that it uses SRR2 and SRR3 instead of SRR0 and SRR1. - */ -#define CRITICAL_EXCEPTION_PROLOG \ - mtspr SPRG0,r20; \ - mtspr SPRG1,r21; \ - mfcr r20; \ - subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\ - stw r20,_CCR(r21); /* save registers */ \ - stw r22,GPR22(r21); \ - stw r23,GPR23(r21); \ - mfspr r20,SPRG0; \ - stw r20,GPR20(r21); \ - mfspr r22,SPRG1; \ - stw r22,GPR21(r21); \ - mflr r20; \ - stw r20,_LINK(r21); \ - mfctr r22; \ - stw r22,_CTR(r21); \ - mfspr r20,XER; \ - stw r20,_XER(r21); \ - mfspr r22,990; /* SRR2 */ \ - mfspr r23,991; /* SRR3 */ \ - stw r0,GPR0(r21); \ - stw r1,GPR1(r21); \ - stw r2,GPR2(r21); \ - stw r1,0(r21); \ - mr r1,r21; /* set new kernel sp */ \ - SAVE_4GPRS(3, r21); -/* - * Note: code which follows this uses cr0.eq (set if from kernel), - * r21, r22 (SRR2), and r23 (SRR3). - */ - /* * Exception vectors. * @@ -293,30 +260,45 @@ #define STD_EXCEPTION(n, label, hdlr) \ . = n; \ label: \ - EXCEPTION_PROLOG; \ + EXCEPTION_PROLOG(SRR0, SRR1); \ lwz r3,GOT(transfer_to_handler); \ mtlr r3; \ addi r3,r1,STACK_FRAME_OVERHEAD; \ li r20,MSR_KERNEL; \ rlwimi r20,r23,0,25,25; \ - blrl ; \ + blrl; \ .L_ ## label : \ - .long hdlr - _start + EXC_OFF_SYS_RESET; \ - .long int_return - _start + EXC_OFF_SYS_RESET - - -#define CRIT_EXCEPTION(n, label, hdlr) \ - . = n; \ -label: \ - CRITICAL_EXCEPTION_PROLOG; \ - lwz r3,GOT(transfer_to_handler); \ - mtlr r3; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \ - rlwimi r20,r23,0,25,25; \ - blrl ; \ -.L_ ## label : \ - .long hdlr - _start + EXC_OFF_SYS_RESET; \ - .long crit_return - _start + EXC_OFF_SYS_RESET + .long hdlr - _start + _START_OFFSET; \ + .long int_return - _start + _START_OFFSET + +#define CRIT_EXCEPTION(n, label, hdlr) \ + . = n; \ +label: \ + EXCEPTION_PROLOG(csrr0, csrr1); \ + lwz r3,GOT(transfer_to_handler); \ + mtlr r3; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \ + rlwimi r20,r23,0,25,25; \ + blrl; \ +.L_ ## label : \ + .long hdlr - _start + _START_OFFSET; \ + .long crit_return - _start + _START_OFFSET + +#ifdef CONFIG_440 +#define MCK_EXCEPTION(n, label, hdlr) \ + . = n; \ +label: \ + EXCEPTION_PROLOG(MCSRR0, MCSRR1); \ + lwz r3,GOT(transfer_to_handler); \ + mtlr r3; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \ + rlwimi r20,r23,0,25,25; \ + blrl; \ +.L_ ## label : \ + .long hdlr - _start + _START_OFFSET; \ + .long mck_return - _start + _START_OFFSET +#endif /* CONFIG_440 */ #endif /* __PPC_ASM_TMPL__ */ -- cgit v1.3.1 From e73846b7cf1e29ae635bf9bb5570269663df2ee5 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 15 Jun 2007 11:33:41 +0200 Subject: [ppc4xx] Change lwmon5 port to work with recent 440 exception rework Now CONFIG_440 has to be defined in all PPC440 board config files. Signed-off-by: Stefan Roese --- include/configs/lwmon5.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index e6e0f422e70..675df76267b 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -29,6 +29,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_LWMON5 1 /* Board is lwmon5 */ #define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_440 1 /* ... PPC440 family */ #define CONFIG_4xx 1 /* ... PPC4xx family */ #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ -- cgit v1.3.1 From df8a24cdd30151505cf57bbee5289e91bf53bd1b Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Tue, 19 Jun 2007 16:42:31 +0200 Subject: [ppc4xx] Fix problem with NAND booting on AMCC Acadia The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese --- board/amcc/acadia/Makefile | 2 +- board/amcc/acadia/acadia.c | 2 ++ board/amcc/acadia/memory.c | 11 +++++++++++ cpu/ppc4xx/start.S | 6 +++--- include/configs/acadia.h | 4 ++-- nand_spl/board/amcc/acadia/Makefile | 14 ++++++++++++-- nand_spl/board/amcc/acadia/config.mk | 4 ++-- nand_spl/board/amcc/acadia/u-boot.lds | 2 +- 8 files changed, 34 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile index ddbcb8091f7..c56b2733a93 100644 --- a/board/amcc/acadia/Makefile +++ b/board/amcc/acadia/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a -COBJS = $(BOARD).o cmd_acadia.o cpr.o memory.o +COBJS = $(BOARD).o cmd_acadia.o memory.o pll.o SOBJS = SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 46d63e6308b..0f54025fb2e 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -55,10 +55,12 @@ int board_early_init_f(void) { unsigned int reg; +#if !defined(CONFIG_NAND_U_BOOT) /* don't reinit PLL when booting via I2C bootstrap option */ mfsdr(SDR_PINSTP, reg); if (reg != 0xf0000000) board_pll_init_f(); +#endif acadia_gpio_init(); diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 25904d3b94a..9346d2c52fb 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -31,6 +31,8 @@ #include #include +extern void board_pll_init_f(void); + /* * sdram_init - Dummy implementation for start.S, spd_sdram used on this board! */ @@ -67,6 +69,15 @@ static void cram_bcr_write(u32 wr_val) long int initdram(int board_type) { +#if defined(CONFIG_NAND_SPL) + u32 reg; + + /* don't reinit PLL when booting via I2C bootstrap option */ + mfsdr(SDR_PINSTP, reg); + if (reg != 0xf0000000) + board_pll_init_f(); +#endif + #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) int i; u32 val; diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index e135220f6d0..16df1e7b35f 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -564,7 +564,7 @@ ProgramCheck: STD_EXCEPTION(0x800, FPUnavailable, UnknownException) STD_EXCEPTION(0x900, Decrementer, DecrementerPITException) STD_EXCEPTION(0xa00, APU, UnknownException) -#endif +#endif STD_EXCEPTION(0xc00, SystemCall, UnknownException) #ifdef CONFIG_440 @@ -889,7 +889,7 @@ _start: */ lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ ori r3,r3,CFG_OCM_DATA_ADDR@l - ori r3,r3,0x8270 /* 32K Offset, 16K for Bank 1, R/W/Enable */ + ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ mtdcr ocmplb3cr1,r3 /* Set PLB Access */ ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ mtdcr ocmplb3cr2,r3 /* Set PLB Access */ @@ -1623,7 +1623,7 @@ trap_init: li r7, .L_APU - _start + _START_OFFSET bl trap_reloc - + li r7, .L_InstructionTLBError - _start + _START_OFFSET bl trap_reloc diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 0f447b004a0..517d130d5ca 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -75,7 +75,7 @@ #define CFG_TEMP_STACK_OCM 1 /* OCM as init ram */ /* On Chip Memory location */ -#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_ADDR 0xf8000000 #define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ @@ -159,7 +159,7 @@ */ #define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ #define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ -#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (12 << 10)) /* Copy SPL here*/ +#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (16 << 10)) /* Copy SPL here*/ #define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ #define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */ #define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST) diff --git a/nand_spl/board/amcc/acadia/Makefile b/nand_spl/board/amcc/acadia/Makefile index 0d6828a76fb..926476f91b0 100644 --- a/nand_spl/board/amcc/acadia/Makefile +++ b/nand_spl/board/amcc/acadia/Makefile @@ -30,7 +30,7 @@ AFLAGS += -DCONFIG_NAND_SPL CFLAGS += -DCONFIG_NAND_SPL SOBJS = start.o resetvec.o -COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o +COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o pll.o SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) @@ -39,7 +39,8 @@ LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) nandobj := $(OBJTREE)/nand_spl/ -ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \ + $(nandobj)System.map all: $(obj).depend $(ALL) @@ -54,6 +55,11 @@ $(nandobj)u-boot-spl: $(OBJS) -Map $(nandobj)u-boot-spl.map \ -o $(nandobj)u-boot-spl +$(nandobj)System.map: $(nandobj)u-boot-spl + @$(NM) $< | \ + grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > $(nandobj)System.map + # create symbolic links for common files # from cpu directory @@ -78,6 +84,10 @@ $(obj)memory.c: @rm -f $(obj)memory.c ln -s $(SRCTREE)/board/amcc/acadia/memory.c $(obj)memory.c +$(obj)pll.c: + @rm -f $(obj)pll.c + ln -s $(SRCTREE)/board/amcc/acadia/pll.c $(obj)pll.c + # from nand_spl directory $(obj)nand_boot.c: @rm -f $(obj)nand_boot.c diff --git a/nand_spl/board/amcc/acadia/config.mk b/nand_spl/board/amcc/acadia/config.mk index 55069b4dfea..3b140fa7e8d 100644 --- a/nand_spl/board/amcc/acadia/config.mk +++ b/nand_spl/board/amcc/acadia/config.mk @@ -32,11 +32,11 @@ # We will copy this SPL into internal SRAM in start.S. So we set # TEXT_BASE to starting address in internal SRAM here. # -TEXT_BASE = 0xF8003000 +TEXT_BASE = 0xf8004000 # PAD_TO used to generate a 16kByte binary needed for the combined image # -> PAD_TO = TEXT_BASE + 0x4000 -PAD_TO = 0xF8007000 +PAD_TO = 0xf8008000 ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG diff --git a/nand_spl/board/amcc/acadia/u-boot.lds b/nand_spl/board/amcc/acadia/u-boot.lds index 018def1faba..a07a773e011 100644 --- a/nand_spl/board/amcc/acadia/u-boot.lds +++ b/nand_spl/board/amcc/acadia/u-boot.lds @@ -24,7 +24,7 @@ OUTPUT_ARCH(powerpc:common) SECTIONS { - .resetvec 0xF8003FFC : + .resetvec 0xf8004ffc : { *(.resetvec) } = 0xffff -- cgit v1.3.1 From 83b4cfa3d629dff0264366263c5e94d9a50ad80b Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 20 Jun 2007 18:14:24 +0200 Subject: Coding style cleanup. Refresh CHANGELOG. --- CHANGELOG | 159 ++++++++++++++++++++++++++++++++++++ board/lwmon5/lwmon5.c | 10 +-- board/lwmon5/sdram.c | 22 ++--- cpu/ppc4xx/start.S | 207 ++++++++++++++++++++++++----------------------- cpu/ppc4xx/traps.c | 68 ++++++++-------- include/configs/katmai.h | 2 +- include/ppc_asm.tmpl | 52 ++++++------ 7 files changed, 339 insertions(+), 181 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index b77eec71ba6..08f625af015 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,162 @@ +commit b3f9ec86e388207fd03dcdf7b145b9ed080bf024 +Author: Stefan Roese +Date: Tue Jun 19 17:22:44 2007 +0200 + + ppc4xx: Add bootstrap command for AMCC Sequoia (440EPx) eval board + + This patch adds a board command to configure the I2C bootstrap EEPROM + values. Right now 533 and 667MHz are supported for booting either via NOR + or NAND FLASH. Here the usage: + + => bootstrap 533 nor ;to configure the board for 533MHz NOR booting + => bootstrap 667 nand ;to configure the board for 667MHz NNAND booting + + Signed-off-by: Stefan Roese + +commit df8a24cdd30151505cf57bbee5289e91bf53bd1b +Author: Stefan Roese +Date: Tue Jun 19 16:42:31 2007 +0200 + + [ppc4xx] Fix problem with NAND booting on AMCC Acadia + + The latest changes showed a problem with the location of the NAND-SPL + image in the OCM and the init-data area (incl. cache). This patch + fixes this problem. + + Signed-off-by: Stefan Roese + +commit 86ba99e34194394052d24c04dc40d1263d29a26f +Author: Stefan Roese +Date: Tue Jun 19 16:40:58 2007 +0200 + + [ppc4xx] Change board/amcc/acadia/cpr.c to pll.c + + Signed-off-by: Stefan Roese + +commit e73846b7cf1e29ae635bf9bb5570269663df2ee5 +Author: Stefan Roese +Date: Fri Jun 15 11:33:41 2007 +0200 + + [ppc4xx] Change lwmon5 port to work with recent 440 exception rework + + Now CONFIG_440 has to be defined in all PPC440 board config files. + + Signed-off-by: Stefan Roese + +commit efa35cf12d914d4caba942acd5a6c45f217de302 +Author: Grzegorz Bernacki +Date: Fri Jun 15 11:19:28 2007 +0200 + + ppc4xx: Clean up 440 exceptions handling + + - Introduced dedicated switches for building 440 and 405 images required + for 440-specific machine instructions like 'rfmci' etc. + + - Exception vectors moved to the proper location (_start moved away from + the critical exception handler space, which it occupied) + + - CriticalInput now serviced (with default handler) + + - MachineCheck properly serviced (added a dedicated handler and return + subroutine) + + - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, + unhandled and those not relevant for 4xx were eliminated) + + - Eliminated Linux leftovers, removed dead code + + Signed-off-by: Grzegorz Bernacki + Signed-off-by: Rafal Jaworowski + Signed-off-by: Stefan Roese + +commit b765ffb773f5a3cd5aa94ec76b6a05276b8cd5b2 +Author: Stefan Roese +Date: Fri Jun 15 08:18:01 2007 +0200 + + [ppc4xx] Add initial lwmon5 board support + + This patch adds initial support for the Liebherr lwmon5 board euqipped + with an AMCC 440EPx PowerPC. + + Signed-off-by: Stefan Roese + +commit 85f737376d5ff3d5f0d45a8b657686326d175307 +Author: Stefan Roese +Date: Fri Jun 15 07:39:43 2007 +0200 + + [ppc4xx] Extend 44x GPIO setup with default output state + + The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup + is extended with the default GPIO output state (level). + + Signed-off-by: Stefan Roese + +commit dbca208518e5e7f01a6420588d1cd6e60db74c2b +Author: Stefan Roese +Date: Thu Jun 14 11:14:32 2007 +0200 + + [ppc4xx] Extend program_tlb() with virtual & physical addresses + + Now program_tlb() allows to program a TLB (or multiple) with + different virtual and physical addresses. With this change, now one + physical region (e.g. SDRAM) can be mapped 2 times, once with caches + diabled and once with caches enabled. + + Signed-off-by: Stefan Roese + +commit 9912121f7ed804ea58fd62f3f230b5dcfc357d88 +Author: Detlev Zundel +Date: Wed May 23 19:02:41 2007 +0200 + + Change 'repeatable' attribute of some commands to sensible values. + + Most prominently this changes 'erase' to be non-repeatable. + + Signed-off-by: Detlev Zundel + +commit 5afb202093f6a001797db92cf695b93a70ea9ab4 +Author: Detlev Zundel +Date: Wed May 23 18:47:48 2007 +0200 + + Fix 'run' not to continue after interrupted command + + Signed-off-by: Detlev Zundel + +commit 8f8416fada9faf94b9a92f21fe6000643cb521d5 +Author: Bartlomiej Sieka +Date: Fri Jun 8 14:52:22 2007 +0200 + + TQM5200: Add Flat Device Tree support, update default env. accordingly. + + Signed-off-by: Jan Wrobel + Acked-by: Bartlomiej Sieka + +commit 9045f33c023f698660a2e45d1b2194c0711abebc +Author: Wolfgang Denk +Date: Fri Jun 8 10:24:58 2007 +0200 + + Fix config problems on SC3 board; make ide_reset_timeout work. + +commit fba3fb0449b8a54542aed1e729de76e7f5a2ff1b +Author: Benoît Monin +Date: Fri Jun 8 09:55:24 2007 +0200 + + [PATCH] fix gpio setting when using CFG_440_GPIO_TABLE + + Set the correct value in GPIOx_TCR when configuring the gpio + with CFG_440_GPIO_TABLE. + + Signed-off-by: Benoit Monin + Signed-off-by: Stefan Roese + +commit 725671ccd2cd04c9ebc50c9e5a94dd8cbade66b7 +Author: Wolfgang Denk +Date: Wed Jun 6 16:26:56 2007 +0200 + + Coding Style cleanup; generate new CHANGELOG file. + + Signed-off-by: Wolfgang Denk + commit c440bfe6d6d92d66478a7e84402b31f48413617b Author: Stefan Roese Date: Wed Jun 6 11:42:13 2007 +0200 diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index 69b45acac7e..b303ec7cb3c 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -34,9 +34,9 @@ int board_early_init_f(void) u32 sdr0_pfc1, sdr0_pfc2; u32 reg; - /* PLB Write pipelining disabled. Denali Core workaround */ - mtdcr(plb0_acr, 0xDE000000); - mtdcr(plb1_acr, 0xDE000000); + /* PLB Write pipelining disabled. Denali Core workaround */ + mtdcr(plb0_acr, 0xDE000000); + mtdcr(plb1_acr, 0xDE000000); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -86,9 +86,9 @@ int board_early_init_f(void) mtsdr(SDR0_PFC4, 0x80000000); /* PCI arbiter disabled */ - /* PCI Host Configuration disbaled */ + /* PCI Host Configuration disbaled */ mfsdr(sdr_pci0, reg); - reg = 0; + reg = 0; mtsdr(sdr_pci0, 0x00000000 | reg); gpio_write_bit(CFG_GPIO_FLASH_WP, 1); diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index d2eb5bd1a8f..85811adadf9 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -1,10 +1,10 @@ /* * (C) Copyright 2006 - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com * * (C) Copyright 2007 * Stefan Roese, DENX Software Engineering, sr@denx.de. @@ -49,9 +49,9 @@ * everything correctly. */ #ifdef CFG_ENABLE_SDRAM_CACHE -#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ +#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #else -#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ #endif void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); @@ -325,8 +325,8 @@ void denali_core_search_data_eye(u32 start_addr, u32 memory_size) debug("DQS calibration - Window detected:\n"); debug("max_passing_cases = %d\n", max_passing_cases); - debug("wr_dqs_shift = %d\n", wr_dqs_shift); - debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X); + debug("wr_dqs_shift = %d\n", wr_dqs_shift); + debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X); debug("dll_dqs_delay_X window = %d - %d\n", dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window); @@ -561,16 +561,16 @@ long int initdram (int board_type) wait_for_dlllock(); - /* + /* * Program tlb entries for this size (dynamic) */ - program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE); + program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE); /* * Setup 2nd TLB with same physical address but different virtual address * with cache enabled. This is done for fast ECC generation. */ - program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0); + program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0); #ifdef CONFIG_DDR_DATA_EYE /* diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 16df1e7b35f..a46197dde98 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -22,26 +22,27 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ -/*------------------------------------------------------------------------------+ */ -/* */ -/* This source code has been made available to you by IBM on an AS-IS */ -/* basis. Anyone receiving this source is licensed under IBM */ -/* copyrights to use it in any way he or she deems fit, including */ -/* copying it, modifying it, compiling it, and redistributing it either */ -/* with or without modifications. No license under IBM patents or */ -/* patent applications is to be implied by the copyright license. */ -/* */ -/* Any user of this software should understand that IBM cannot provide */ -/* technical support for this software and will not be responsible for */ -/* any consequences resulting from the use of this software. */ -/* */ -/* Any person who transfers this source code or any derivative work */ -/* must include the IBM copyright notice, this paragraph, and the */ -/* preceding two paragraphs in the transferred software. */ -/* */ -/* COPYRIGHT I B M CORPORATION 1995 */ -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */ -/*------------------------------------------------------------------------------- */ +/*------------------------------------------------------------------------------+ + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + *------------------------------------------------------------------------------- + */ /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards * @@ -110,11 +111,11 @@ # endif #endif /* CFG_INIT_DCACHE_CS */ -#define function_prolog(func_name) .text; \ +#define function_prolog(func_name) .text; \ .align 2; \ .globl func_name; \ func_name: -#define function_epilog(func_name) .type func_name,@function; \ +#define function_epilog(func_name) .type func_name,@function; \ .size func_name,.-func_name /* We don't want the MMU yet. @@ -295,7 +296,7 @@ skip_debug_init: li r1,0x0c00 mtspr ivor8,r1 /* System call */ li r1,0x0a00 - mtspr ivor9,r1 /* Auxiliary Processor unavailable */ + mtspr ivor9,r1 /* Auxiliary Processor unavailable */ li r1,0x0900 mtspr ivor10,r1 /* Decrementer */ li r1,0x1300 @@ -514,9 +515,9 @@ _start_of_vectors: #ifdef CONFIG_440 /* Machine check */ - MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) + MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) #else - CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) + CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) #endif /* CONFIG_440 */ /* Data Storage exception. */ @@ -895,15 +896,15 @@ _start: mtdcr ocmplb3cr2,r3 /* Set PLB Access */ isync - lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ + lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ ori r3,r3,CFG_OCM_DATA_ADDR@l - ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ - mtdcr ocmdscr1, r3 /* Set Data Side */ - mtdcr ocmiscr1, r3 /* Set Instruction Side */ + ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ + mtdcr ocmdscr1, r3 /* Set Data Side */ + mtdcr ocmiscr1, r3 /* Set Instruction Side */ ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ - mtdcr ocmdscr2, r3 /* Set Data Side */ - mtdcr ocmiscr2, r3 /* Set Instruction Side */ - addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ + mtdcr ocmdscr2, r3 /* Set Data Side */ + mtdcr ocmiscr2, r3 /* Set Instruction Side */ + addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ mtdcr ocmdsisdpc,r3 isync @@ -922,7 +923,7 @@ _start: mtdcr ocmdscntl, r4 /* set data-side IRAM config */ isync - lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ + lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ ori r3,r3,CFG_OCM_DATA_ADDR@l mtdcr ocmdsarc, r3 addis r4, 0, 0xC000 /* OCM data area enabled */ @@ -1170,8 +1171,8 @@ crit_return: REST_GPR(31, r1) lwz r2,_NIP(r1) /* Restore environment */ lwz r0,_MSR(r1) - mtspr csrr0,r2 - mtspr csrr1,r0 + mtspr csrr0,r2 + mtspr csrr1,r0 lwz r0,GPR0(r1) lwz r2,GPR2(r1) lwz r1,GPR1(r1) @@ -1180,34 +1181,34 @@ crit_return: #ifdef CONFIG_440 mck_return: - mfmsr r28 /* Disable interrupts */ - li r4,0 - ori r4,r4,MSR_EE - andc r28,r28,r4 - SYNC /* Some chip revs need this... */ - mtmsr r28 - SYNC - lwz r2,_CTR(r1) - lwz r0,_LINK(r1) - mtctr r2 - mtlr r0 - lwz r2,_XER(r1) - lwz r0,_CCR(r1) - mtspr XER,r2 - mtcrf 0xFF,r0 - REST_10GPRS(3, r1) - REST_10GPRS(13, r1) - REST_8GPRS(23, r1) - REST_GPR(31, r1) - lwz r2,_NIP(r1) /* Restore environment */ - lwz r0,_MSR(r1) - mtspr mcsrr0,r2 - mtspr mcsrr1,r0 - lwz r0,GPR0(r1) - lwz r2,GPR2(r1) - lwz r1,GPR1(r1) - SYNC - rfmci + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr mcsrr0,r2 + mtspr mcsrr1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfmci #endif /* CONFIG_440 */ @@ -1222,11 +1223,11 @@ mck_return: #ifdef CONFIG_440 .globl dcache_disable dcache_disable: - blr + blr - .globl dcache_status + .globl dcache_status dcache_status: - blr + blr #else flush_dcache: addis r9,r0,0x0002 /* set mask for EE and CE msr bits */ @@ -1616,32 +1617,32 @@ trap_init: #ifdef CONFIG_440 li r7, .L_FPUnavailable - _start + _START_OFFSET - bl trap_reloc + bl trap_reloc li r7, .L_Decrementer - _start + _START_OFFSET - bl trap_reloc + bl trap_reloc li r7, .L_APU - _start + _START_OFFSET - bl trap_reloc + bl trap_reloc - li r7, .L_InstructionTLBError - _start + _START_OFFSET - bl trap_reloc + li r7, .L_InstructionTLBError - _start + _START_OFFSET + bl trap_reloc - li r7, .L_DataTLBError - _start + _START_OFFSET - bl trap_reloc + li r7, .L_DataTLBError - _start + _START_OFFSET + bl trap_reloc #else /* CONFIG_440 */ li r7, .L_PIT - _start + _START_OFFSET - bl trap_reloc + bl trap_reloc li r7, .L_InstructionTLBMiss - _start + _START_OFFSET - bl trap_reloc + bl trap_reloc li r7, .L_DataTLBMiss - _start + _START_OFFSET - bl trap_reloc + bl trap_reloc #endif /* CONFIG_440 */ - li r7, .L_DebugBreakpoint - _start + _START_OFFSET - bl trap_reloc + li r7, .L_DebugBreakpoint - _start + _START_OFFSET + bl trap_reloc #if !defined(CONFIG_440) addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ @@ -1684,13 +1685,13 @@ trap_reloc: +----------------------------------------------------------------------------*/ function_prolog(dcbz_area) rlwinm. r5,r4,0,27,31 - rlwinm r5,r4,27,5,31 - beq ..d_ra2 - addi r5,r5,0x0001 -..d_ra2:mtctr r5 -..d_ag2:dcbz r0,r3 - addi r3,r3,32 - bdnz ..d_ag2 + rlwinm r5,r4,27,5,31 + beq ..d_ra2 + addi r5,r5,0x0001 +..d_ra2:mtctr r5 +..d_ag2:dcbz r0,r3 + addi r3,r3,32 + bdnz ..d_ag2 sync blr function_epilog(dcbz_area) @@ -1699,26 +1700,26 @@ trap_reloc: | dflush. Assume 32K at vector address is cachable. +----------------------------------------------------------------------------*/ function_prolog(dflush) - mfmsr r9 - rlwinm r8,r9,0,15,13 - rlwinm r8,r8,0,17,15 - mtmsr r8 - addi r3,r0,0x0000 - mtspr dvlim,r3 - mfspr r3,ivpr - addi r4,r0,1024 - mtctr r4 + mfmsr r9 + rlwinm r8,r9,0,15,13 + rlwinm r8,r8,0,17,15 + mtmsr r8 + addi r3,r0,0x0000 + mtspr dvlim,r3 + mfspr r3,ivpr + addi r4,r0,1024 + mtctr r4 ..dflush_loop: - lwz r6,0x0(r3) - addi r3,r3,32 - bdnz ..dflush_loop - addi r3,r3,-32 - mtctr r4 -..ag: dcbf r0,r3 - addi r3,r3,-32 - bdnz ..ag + lwz r6,0x0(r3) + addi r3,r3,32 + bdnz ..dflush_loop + addi r3,r3,-32 + mtctr r4 +..ag: dcbf r0,r3 + addi r3,r3,-32 + bdnz ..ag sync - mtmsr r9 + mtmsr r9 blr function_epilog(dflush) #endif /* CONFIG_440 */ diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c index 54659d33702..7c44a2990b5 100644 --- a/cpu/ppc4xx/traps.c +++ b/cpu/ppc4xx/traps.c @@ -89,22 +89,22 @@ extern void do_bedbug_breakpoint(struct pt_regs *); void print_backtrace(unsigned long *sp) { - int cnt = 0; - unsigned long i; - - printf("Call backtrace: "); - while (sp) { - if ((uint)sp > END_OF_MEM) - break; - - i = sp[1]; - if (cnt++ % 7 == 0) - printf("\n"); - printf("%08lX ", i); - if (cnt > 32) break; - sp = (unsigned long *)*sp; - } - printf("\n"); + int cnt = 0; + unsigned long i; + + printf("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + printf("\n"); + printf("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *)*sp; + } + printf("\n"); } void show_regs(struct pt_regs * regs) @@ -121,14 +121,12 @@ void show_regs(struct pt_regs * regs) printf("\n"); for (i = 0; i < 32; i++) { - if ((i % 8) == 0) - { + if ((i % 8) == 0) { printf("GPR%02d: ", i); } printf("%08lX ", regs->gpr[i]); - if ((i % 8) == 7) - { + if ((i % 8) == 7) { printf("\n"); } } @@ -147,7 +145,7 @@ void MachineCheckException(struct pt_regs *regs) { unsigned long fixup, val; - + /* Probing PCI using config cycles cause this exception * when a device is not present. Catch it and return to * the PCI exception handler. @@ -172,16 +170,16 @@ MachineCheckException(struct pt_regs *regs) if (val& ESR_IMCP) { printf("Instruction"); mtspr(ESR, val & ~ESR_IMCP); - } else + } else { printf("Data"); + } printf(" machine check.\n"); #elif defined(CONFIG_440) if (val& ESR_IMCP){ printf("Instruction Synchronous Machine Check exception\n"); mtspr(SPRN_ESR, val & ~ESR_IMCP); - } - else { + } else { val = mfspr(MCSR); if (val & MCSR_IB) printf("Instruction Read PLB Error\n"); @@ -297,17 +295,17 @@ addr_probe(uint *addr) __asm__ __volatile__( \ "1: lwz %0,0(%1)\n" \ - " eieio\n" \ - " li %0,0\n" \ - "2:\n" \ - ".section .fixup,\"ax\"\n" \ - "3: li %0,-1\n" \ - " b 2b\n" \ - ".section __ex_table,\"a\"\n" \ - " .align 2\n" \ - " .long 1b,3b\n" \ - ".text" \ - : "=r" (retval) : "r"(addr)); + " eieio\n" \ + " li %0,0\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3: li %0,-1\n" \ + " b 2b\n" \ + ".section __ex_table,\"a\"\n" \ + " .align 2\n" \ + " .long 1b,3b\n" \ + ".text" \ + : "=r" (retval) : "r"(addr)); return (retval); #endif diff --git a/include/configs/katmai.h b/include/configs/katmai.h index e6ebe3815d6..cc47a168ed3 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -29,7 +29,7 @@ #ifndef __CONFIG_H #define __CONFIG_H -//#define DEBUG + /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index f15628aa2e5..ad027d61f40 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -113,11 +113,11 @@ #if defined(CONFIG_5xx) /* Some special purpose registers */ -#define DER 149 /* Debug Enable Register */ -#define COUNTA 150 /* Breakpoint Counter */ -#define COUNTB 151 /* Breakpoint Counter */ -#define LCTRL1 156 /* Load/Store Support */ -#define LCTRL2 157 /* Load/Store Support */ +#define DER 149 /* Debug Enable Register */ +#define COUNTA 150 /* Breakpoint Counter */ +#define COUNTB 151 /* Breakpoint Counter */ +#define LCTRL1 156 /* Load/Store Support */ +#define LCTRL2 157 /* Load/Store Support */ #define ICTRL 158 /* I-Bus Support Control Register */ #define EID 81 #endif /* CONFIG_5xx */ @@ -266,39 +266,39 @@ label: \ addi r3,r1,STACK_FRAME_OVERHEAD; \ li r20,MSR_KERNEL; \ rlwimi r20,r23,0,25,25; \ - blrl; \ + blrl; \ .L_ ## label : \ .long hdlr - _start + _START_OFFSET; \ .long int_return - _start + _START_OFFSET #define CRIT_EXCEPTION(n, label, hdlr) \ - . = n; \ + . = n; \ label: \ - EXCEPTION_PROLOG(csrr0, csrr1); \ - lwz r3,GOT(transfer_to_handler); \ - mtlr r3; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \ - rlwimi r20,r23,0,25,25; \ - blrl; \ + EXCEPTION_PROLOG(csrr0, csrr1); \ + lwz r3,GOT(transfer_to_handler); \ + mtlr r3; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \ + rlwimi r20,r23,0,25,25; \ + blrl; \ .L_ ## label : \ - .long hdlr - _start + _START_OFFSET; \ - .long crit_return - _start + _START_OFFSET + .long hdlr - _start + _START_OFFSET; \ + .long crit_return - _start + _START_OFFSET #ifdef CONFIG_440 #define MCK_EXCEPTION(n, label, hdlr) \ - . = n; \ + . = n; \ label: \ - EXCEPTION_PROLOG(MCSRR0, MCSRR1); \ - lwz r3,GOT(transfer_to_handler); \ - mtlr r3; \ - addi r3,r1,STACK_FRAME_OVERHEAD; \ - li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \ - rlwimi r20,r23,0,25,25; \ - blrl; \ + EXCEPTION_PROLOG(MCSRR0, MCSRR1); \ + lwz r3,GOT(transfer_to_handler); \ + mtlr r3; \ + addi r3,r1,STACK_FRAME_OVERHEAD; \ + li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \ + rlwimi r20,r23,0,25,25; \ + blrl; \ .L_ ## label : \ - .long hdlr - _start + _START_OFFSET; \ - .long mck_return - _start + _START_OFFSET + .long hdlr - _start + _START_OFFSET; \ + .long mck_return - _start + _START_OFFSET #endif /* CONFIG_440 */ #endif /* __PPC_ASM_TMPL__ */ -- cgit v1.3.1 From 02032e8f14751a1a751b09240a4f1cf9f8a2077f Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Fri, 22 Jun 2007 14:58:04 +0200 Subject: [ppc] Fix build breakage for all non-4xx PowerPC variants. - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup --- cpu/74xx_7xx/start.S | 4 ++-- cpu/mpc5xx/start.S | 4 ++-- cpu/mpc5xxx/start.S | 4 ++-- cpu/mpc8220/start.S | 4 ++-- cpu/mpc824x/start.S | 4 ++-- cpu/mpc8260/start.S | 4 ++-- cpu/mpc83xx/start.S | 4 ++-- cpu/mpc85xx/start.S | 4 ++-- cpu/mpc86xx/start.S | 4 ++-- cpu/mpc8xx/start.S | 4 ++-- cpu/ppc4xx/start.S | 1 - include/74xx_7xx.h | 1 + include/mpc5xx.h | 1 + include/mpc5xxx.h | 1 + include/mpc8220.h | 1 + include/mpc824x.h | 2 ++ include/mpc8260.h | 2 +- include/mpc83xx.h | 1 + include/mpc85xx.h | 1 + include/mpc86xx.h | 2 +- include/mpc8xx.h | 2 +- include/ppc4xx.h | 3 ++- include/ppc_asm.tmpl | 2 +- 23 files changed, 34 insertions(+), 26 deletions(-) (limited to 'include') diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index 11430388f50..b5834b91e3e 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -125,7 +125,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -143,7 +143,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S index 087435e5bee..95728373fbd 100644 --- a/cpu/mpc5xx/start.S +++ b/cpu/mpc5xx/start.S @@ -210,7 +210,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -228,7 +228,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index 3936b5551f3..9b1bd48c733 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -208,7 +208,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -227,7 +227,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S index 52332023ec5..b5145ca035d 100644 --- a/cpu/mpc8220/start.S +++ b/cpu/mpc8220/start.S @@ -169,7 +169,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -188,7 +188,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S index 9ff052c3b0e..784edc36a0c 100644 --- a/cpu/mpc824x/start.S +++ b/cpu/mpc824x/start.S @@ -220,7 +220,7 @@ _start_of_vectors: /* Alignment exception. */ . = EXC_OFF_ALIGN Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -238,7 +238,7 @@ Alignment: /* Program check exception */ . = EXC_OFF_PROGRAM ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index 2e93bbbb864..bc55b58ad24 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -279,7 +279,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -298,7 +298,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 6ee9ec96c97..496c8a5861b 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -263,7 +263,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -282,7 +282,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index 20c7ebc7238..77c155c5bdc 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -457,7 +457,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x0600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -475,7 +475,7 @@ Alignment: /* Program check exception */ . = 0x0700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 67c56db1a37..412745bdaea 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -116,7 +116,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -134,7 +134,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S index 33a3f6c88e2..eca4b50626d 100644 --- a/cpu/mpc8xx/start.S +++ b/cpu/mpc8xx/start.S @@ -224,7 +224,7 @@ _start_of_vectors: /* Alignment exception. */ . = 0x600 Alignment: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) mfspr r4,DAR stw r4,_DAR(r21) mfspr r5,DSISR @@ -242,7 +242,7 @@ Alignment: /* Program check exception */ . = 0x700 ProgramCheck: - EXCEPTION_PROLOG + EXCEPTION_PROLOG(SRR0, SRR1) addi r3,r1,STACK_FRAME_OVERHEAD li r20,MSR_KERNEL rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index a46197dde98..dfe813c3f45 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -60,7 +60,6 @@ * address and (s)dram will be positioned at address 0 */ #include -#include #include #include diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h index ba73bae9e5f..4a03cecb591 100644 --- a/include/74xx_7xx.h +++ b/include/74xx_7xx.h @@ -34,6 +34,7 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */ +#define _START_OFFSET EXC_OFF_SYS_RESET /*---------------------------------------------------------------- * l2cr values diff --git a/include/mpc5xx.h b/include/mpc5xx.h index 7508f6df20e..e9b08a0dc72 100644 --- a/include/mpc5xx.h +++ b/include/mpc5xx.h @@ -36,6 +36,7 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET EXC_OFF_SYS_RESET /*----------------------------------------------------------------------- * ISB bit in IMMR to set internal memory map diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index 089aa1322b8..a4581a3e6bb 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -39,6 +39,7 @@ /* Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET /* useful macros for manipulating CSx_START/STOP */ #if defined(CONFIG_MGT5100) diff --git a/include/mpc8220.h b/include/mpc8220.h index ff7acc6d3ab..d3b1457f9c5 100644 --- a/include/mpc8220.h +++ b/include/mpc8220.h @@ -35,6 +35,7 @@ /* Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET /* Internal memory map */ /* MPC8220 Internal Register MMAP */ diff --git a/include/mpc824x.h b/include/mpc824x.h index 30fc795382f..4bd88634819 100644 --- a/include/mpc824x.h +++ b/include/mpc824x.h @@ -142,6 +142,8 @@ #define EXC_OFF_JMDDI 0x1600 /* Java Mode denorm detect Interr -- WTF??*/ #define EXC_OFF_RMTE 0x2000 /* Run Mode or Trace Exception */ +#define _START_OFFSET EXC_OFF_SYS_RESET + #define MAP_A_CONFIG_ADDR_HIGH 0x8000 /* Upper half of CONFIG_ADDR for Map A */ #define MAP_A_CONFIG_ADDR_LOW 0x0CF8 /* Lower half of CONFIG_ADDR for Map A */ #define MAP_A_CONFIG_DATA_HIGH 0x8000 /* Upper half of CONFIG_DAT for Map A */ diff --git a/include/mpc8260.h b/include/mpc8260.h index d9dd92d9a5e..b61218ccc29 100644 --- a/include/mpc8260.h +++ b/include/mpc8260.h @@ -53,7 +53,7 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ - +#define _START_OFFSET EXC_OFF_SYS_RESET /*----------------------------------------------------------------------- * BCR - Bus Configuration Register 4-25 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 60fc214b3e2..cbf41c3a939 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -25,6 +25,7 @@ /* System reset offset (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET /* IMMRBAR - Internal Memory Register Base Address */ diff --git a/include/mpc85xx.h b/include/mpc85xx.h index a4d99b2a165..6fbd50457c4 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -8,6 +8,7 @@ #define __MPC85xx_H__ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET EXC_OFF_SYS_RESET #if defined(CONFIG_E500) #include diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 673bfed16e9..9fd349af986 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -8,7 +8,7 @@ #define __MPC86xx_H__ #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ - +#define _START_OFFSET EXC_OFF_SYS_RESET /* * platform register addresses diff --git a/include/mpc8xx.h b/include/mpc8xx.h index 29117589be9..11305987f89 100644 --- a/include/mpc8xx.h +++ b/include/mpc8xx.h @@ -35,7 +35,7 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ - +#define _START_OFFSET EXC_OFF_SYS_RESET /*----------------------------------------------------------------------- * SYPCR - System Protection Control Register 11-9 diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 8cead66ad1a..ca241d2c13c 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -22,7 +22,8 @@ #ifndef __PPC4XX_H__ #define __PPC4XX_H__ -#define _START_OFFSET 0x2100 +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) #if defined(CONFIG_440) #include diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index ad027d61f40..9f4029f2afc 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -274,7 +274,7 @@ label: \ #define CRIT_EXCEPTION(n, label, hdlr) \ . = n; \ label: \ - EXCEPTION_PROLOG(csrr0, csrr1); \ + EXCEPTION_PROLOG(CSRR0, CSRR1); \ lwz r3,GOT(transfer_to_handler); \ mtlr r3; \ addi r3,r1,STACK_FRAME_OVERHEAD; \ -- cgit v1.3.1 From 566a494f592ae3b3c0785d90d4e1ba45574880c4 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 22 Jun 2007 19:11:54 +0200 Subject: [PCS440EP] upgrade the PCS440EP board: - Show on the Status LEDs, some States of the board. - Get the MAC addresses from the EEProm - use PREBOOT - use the CF on the board. - check the U-Boot image in the Flash with a SHA1 checksum. - use dynamic TLB entries generation for the SDRAM Signed-off-by: Heiko Schocher --- Makefile | 9 +- README | 85 +++++-- board/hermes/hermes.c | 1 + board/logodl/logodl.c | 1 + board/pcs440ep/config.mk | 3 + board/pcs440ep/flash.c | 4 + board/pcs440ep/init.S | 41 ++-- board/pcs440ep/pcs440ep.c | 500 +++++++++++++++++++++++++++++++++++++++- board/pcs440ep/u-boot.lds | 1 + board/sc520_cdp/sc520_cdp.c | 1 + board/sc520_spunk/sc520_spunk.c | 1 + common/cmd_doc.c | 19 +- common/cmd_ide.c | 60 +++-- common/cmd_nand.c | 38 ++- common/cmd_net.c | 26 ++- common/cmd_reiser.c | 6 +- common/env_common.c | 2 +- cpu/ppc4xx/44x_spd_ddr.c | 26 ++- cpu/ppc4xx/44x_spd_ddr2.c | 71 +++--- disk/part.c | 3 +- fs/fat/fat.c | 42 ++-- include/configs/pcs440ep.h | 83 ++++++- include/sha1.h | 115 +++++++++ include/status_led.h | 7 + lib_generic/Makefile | 2 +- lib_generic/sha1.c | 430 ++++++++++++++++++++++++++++++++++ lib_ppc/board.c | 5 +- net/eth.c | 11 + tools/Makefile | 23 +- tools/ubsha1.c | 119 ++++++++++ 30 files changed, 1575 insertions(+), 160 deletions(-) create mode 100644 include/sha1.h create mode 100644 lib_generic/sha1.c create mode 100644 tools/ubsha1.c (limited to 'include') diff --git a/Makefile b/Makefile index d5e220aadde..3d64d1673e8 100644 --- a/Makefile +++ b/Makefile @@ -245,7 +245,7 @@ __LIBS := $(subst $(obj),,$(LIBS)) ######################################################################### ######################################################################### -ALL = $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) +ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) all: $(ALL) @@ -265,6 +265,9 @@ $(obj)u-boot.img: $(obj)u-boot.bin sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \ -d $< $@ +$(obj)u-boot.sha1: $(obj)u-boot.bin + ./tools/ubsha1 $(obj)u-boot.bin + $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@ @@ -2455,7 +2458,7 @@ clean: $(obj)examples/smc91111_eeprom $(obj)examples/interrupt \ $(obj)examples/test_burst rm -f $(obj)tools/img2srec $(obj)tools/mkimage $(obj)tools/envcrc \ - $(obj)tools/gen_eth_addr + $(obj)tools/gen_eth_addr $(obj)tools/ubsha1 rm -f $(obj)tools/mpc86x_clk $(obj)tools/ncb rm -f $(obj)tools/easylogo/easylogo $(obj)tools/bmp_logo rm -f $(obj)tools/gdb/astest $(obj)tools/gdb/gdbcont $(obj)tools/gdb/gdbsend @@ -2478,7 +2481,7 @@ clobber: clean rm -f $(OBJS) $(obj)*.bak $(obj)ctags $(obj)etags $(obj)TAGS $(obj)include/version_autogenerated.h rm -fr $(obj)*.*~ rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) - rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c + rm -f $(obj)tools/crc32.c $(obj)tools/environment.c $(obj)tools/env/crc32.c $(obj)tools/sha1.c rm -f $(obj)tools/inca-swap-bytes $(obj)cpu/mpc824x/bedbug_603e.c rm -f $(obj)include/asm/proc $(obj)include/asm/arch $(obj)include/asm [ ! -d $(OBJTREE)/nand_spl ] || find $(obj)nand_spl -lname "*" -print | xargs rm -f diff --git a/README b/README index bb5b46e3379..b64bfb2477c 100644 --- a/README +++ b/README @@ -1699,28 +1699,69 @@ The following options need to be configured: -31 post/post.c POST test failed, detected by post_output_backlog() -32 post/post.c POST test failed, detected by post_run_single() - -1 common/cmd_doc.c Bad usage of "doc" command - -1 common/cmd_doc.c No boot device - -1 common/cmd_doc.c Unknown Chip ID on boot device - -1 common/cmd_doc.c Read Error on boot device - -1 common/cmd_doc.c Image header has bad magic number - - -1 common/cmd_ide.c Bad usage of "ide" command - -1 common/cmd_ide.c No boot device - -1 common/cmd_ide.c Unknown boot device - -1 common/cmd_ide.c Unknown partition table - -1 common/cmd_ide.c Invalid partition type - -1 common/cmd_ide.c Read Error on boot device - -1 common/cmd_ide.c Image header has bad magic number - - -1 common/cmd_nand.c Bad usage of "nand" command - -1 common/cmd_nand.c No boot device - -1 common/cmd_nand.c Unknown Chip ID on boot device - -1 common/cmd_nand.c Read Error on boot device - -1 common/cmd_nand.c Image header has bad magic number - - -1 common/env_common.c Environment has a bad CRC, using default - + 34 common/cmd_doc.c before loading a Image from a DOC device + -35 common/cmd_doc.c Bad usage of "doc" command + 35 common/cmd_doc.c correct usage of "doc" command + -36 common/cmd_doc.c No boot device + 36 common/cmd_doc.c correct boot device + -37 common/cmd_doc.c Unknown Chip ID on boot device + 37 common/cmd_doc.c correct chip ID found, device available + -38 common/cmd_doc.c Read Error on boot device + 38 common/cmd_doc.c reading Image header from DOC device OK + -39 common/cmd_doc.c Image header has bad magic number + 39 common/cmd_doc.c Image header has correct magic number + -40 common/cmd_doc.c Error reading Image from DOC device + 40 common/cmd_doc.c Image header has correct magic number + 41 common/cmd_ide.c before loading a Image from a IDE device + -42 common/cmd_ide.c Bad usage of "ide" command + 42 common/cmd_ide.c correct usage of "ide" command + -43 common/cmd_ide.c No boot device + 43 common/cmd_ide.c boot device found + -44 common/cmd_ide.c Device not available + 44 common/cmd_ide.c Device available + -45 common/cmd_ide.c wrong partition selected + 45 common/cmd_ide.c partition selected + -46 common/cmd_ide.c Unknown partition table + 46 common/cmd_ide.c valid partition table found + -47 common/cmd_ide.c Invalid partition type + 47 common/cmd_ide.c correct partition type + -48 common/cmd_ide.c Error reading Image Header on boot device + 48 common/cmd_ide.c reading Image Header from IDE device OK + -49 common/cmd_ide.c Image header has bad magic number + 49 common/cmd_ide.c Image header has correct magic number + -50 common/cmd_ide.c Image header has bad checksum + 50 common/cmd_ide.c Image header has correct checksum + -51 common/cmd_ide.c Error reading Image from IDE device + 51 common/cmd_ide.c reading Image from IDE device OK + 52 common/cmd_nand.c before loading a Image from a NAND device + -53 common/cmd_nand.c Bad usage of "nand" command + 53 common/cmd_nand.c correct usage of "nand" command + -54 common/cmd_nand.c No boot device + 54 common/cmd_nand.c boot device found + -55 common/cmd_nand.c Unknown Chip ID on boot device + 55 common/cmd_nand.c correct chip ID found, device available + -56 common/cmd_nand.c Error reading Image Header on boot device + 56 common/cmd_nand.c reading Image Header from NAND device OK + -57 common/cmd_nand.c Image header has bad magic number + 57 common/cmd_nand.c Image header has correct magic number + -58 common/cmd_nand.c Error reading Image from NAND device + 58 common/cmd_nand.c reading Image from NAND device OK + + -60 common/env_common.c Environment has a bad CRC, using default + + 64 net/eth.c starting with Ethernetconfiguration. + -64 net/eth.c no Ethernet found. + 65 net/eth.c Ethernet found. + + -80 common/cmd_net.c usage wrong + 80 common/cmd_net.c before calling NetLoop() + -81 common/cmd_net.c some error in NetLoop() occured + 81 common/cmd_net.c NetLoop() back without error + -82 common/cmd_net.c size == 0 (File with size 0 loaded) + 82 common/cmd_net.c trying automatic boot + 83 common/cmd_net.c running autoscript + -83 common/cmd_net.c some error in automatic boot or autoscript + 84 common/cmd_net.c end without errors Modem Support: -------------- diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c index a523db1a487..8fd081fef3a 100644 --- a/board/hermes/hermes.c +++ b/board/hermes/hermes.c @@ -597,6 +597,7 @@ void show_boot_progress (int status) { volatile immap_t *immr = (immap_t *) CFG_IMMR; + if (status < -32) status = -1; /* let things compatible */ status ^= 0x0F; status = (status & 0x0F) << 14; immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status; diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c index 14fd28f56fc..897787bcf7a 100644 --- a/board/logodl/logodl.c +++ b/board/logodl/logodl.c @@ -107,6 +107,7 @@ void logodl_set_led(int led, int state) void show_boot_progress (int status) { + if (status < -32) status = -1; /* let things compatible */ /* switch(status) { case 1: logodl_set_led(0,1); break; diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk index 319c4fa214a..4d942ebc71b 100644 --- a/board/pcs440ep/config.mk +++ b/board/pcs440ep/config.mk @@ -25,6 +25,9 @@ # PCS440EP board # +# Check the U-Boot Image with a SHA1 checksum +ALL += $(obj)u-boot.sha1 + #TEXT_BASE = 0x00001000 ifeq ($(ramsym),1) diff --git a/board/pcs440ep/flash.c b/board/pcs440ep/flash.c index ece54781b9d..70014407c6e 100644 --- a/board/pcs440ep/flash.c +++ b/board/pcs440ep/flash.c @@ -83,6 +83,7 @@ void flash_print_info(flash_info_t *info) case FLASH_MAN_FUJ: printf ("FUJITSU "); break; case FLASH_MAN_SST: printf ("SST "); break; case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; + case FLASH_MAN_MX: printf ("MXIC "); break; default: printf ("Unknown Vendor "); break; } @@ -195,6 +196,9 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: info->flash_id = FLASH_MAN_EXCEL; break; + case (CFG_FLASH_WORD_SIZE)MX_MANUFACT: + info->flash_id = FLASH_MAN_MX; + break; default: info->flash_id = FLASH_UNKNOWN; info->sector_count = 0; diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S index 0eee4d8099e..36a40c97a3d 100644 --- a/board/pcs440ep/init.S +++ b/board/pcs440ep/init.S @@ -87,27 +87,32 @@ .globl tlbtab tlbtab: - tlbtab_start + tlbtab_start - /* - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the - * speed up boot process. It is patched after relocation to enable SA_I - */ - tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) + /* + * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the + * speed up boot process. It is patched after relocation to enable SA_I + */ + tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/) - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ - tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) + /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ + tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G ) - tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) - tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) + /* + * TLB entries for SDRAM are not needed on this platform. + * They are dynamically generated in the SPD DDR detection + * routine. + */ - /* PCI */ - tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) - tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I ) - /* USB 2.0 Device */ - tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) + /* PCI */ + tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I ) + tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I ) - tlbtab_end + /* USB 2.0 Device */ + tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I ) + + tlbtab_end diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 8858f0a5e54..f638589df29 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -23,19 +23,111 @@ #include #include +#include +#include +#include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ -static void set_leds(int val) +unsigned char sha1_checksum[SHA1_SUM_LEN]; + +/* swap 4 Bits (Bit0 = Bit3, Bit1 = Bit2, Bit2 = Bit1 and Bit3 = Bit0) */ +unsigned char swapbits[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe, + 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf}; + +static void set_leds (int val) +{ + out32(GPIO0_OR, (in32 (GPIO0_OR) & ~0x78000000) | (val << 27)); +} + +#define GET_LEDS ((in32 (GPIO0_OR) & 0x78000000) >> 27) + +void __led_init (led_id_t mask, int state) +{ + int val = GET_LEDS; + + if (state == STATUS_LED_ON) + val |= mask; + else + val &= ~mask; + set_leds (val); +} + +void __led_set (led_id_t mask, int state) +{ + int val = GET_LEDS; + + if (state == STATUS_LED_ON) + val |= mask; + else if (state == STATUS_LED_OFF) + val &= ~mask; + set_leds (val); +} + +void __led_toggle (led_id_t mask) +{ + int val = GET_LEDS; + + val ^= mask; + set_leds (val); +} + +static void status_led_blink (void) +{ + int i; + int val = GET_LEDS; + + /* set all LED which are on, to state BLINKING */ + for (i = 0; i < 4; i++) { + if (val & 0x08) status_led_set (i, STATUS_LED_BLINKING); + val = val << 1; + } +} + +#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress (int val) { - unsigned char led[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe, - 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf}; - out32(GPIO0_OR, (in32(GPIO0_OR) & ~0x78000000) | (led[val] << 27)); + /* find all valid Codes for val in README */ + if (val == -30) return; + if (val < 0) { + /* smthing goes wrong */ + status_led_blink (); + return; + } + switch (val) { + case 1: + /* validating Image */ + status_led_set (0, STATUS_LED_OFF); + status_led_set (1, STATUS_LED_ON); + status_led_set (2, STATUS_LED_ON); + break; + case 15: + /* booting */ + status_led_set (0, STATUS_LED_ON); + status_led_set (1, STATUS_LED_ON); + status_led_set (2, STATUS_LED_ON); + break; + case 64: + /* starting Ethernet configuration */ + status_led_set (0, STATUS_LED_OFF); + status_led_set (1, STATUS_LED_OFF); + status_led_set (2, STATUS_LED_ON); + break; + case 80: + /* loading Image */ + status_led_set (0, STATUS_LED_ON); + status_led_set (1, STATUS_LED_OFF); + status_led_set (2, STATUS_LED_ON); + break; + } } +#endif int board_early_init_f(void) { @@ -85,6 +177,252 @@ int board_early_init_f(void) return 0; } +#define EEPROM_LEN 256 +void load_sernum_ethaddr (void) +{ + int ret; + char buf[EEPROM_LEN]; + char mac[32]; + char *use_eeprom; + u16 checksumcrc16 = 0; + + /* read the MACs from EEprom */ + status_led_set (0, STATUS_LED_ON); + status_led_set (1, STATUS_LED_ON); + ret = eeprom_read (CFG_I2C_EEPROM_ADDR, 0, (uchar *)buf, EEPROM_LEN); + if (ret == 0) { + checksumcrc16 = cyg_crc16 ((uchar *)buf, EEPROM_LEN - 2); + /* check, if the EEprom is programmed: + * - The Prefix(Byte 0,1,2) is equal to "ATR" + * - The checksum, stored in the last 2 Bytes, is correct + */ + if ((strncmp (buf,"ATR",3) != 0) || + ((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) || + ((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) + { + /* EEprom is not programmed */ + printf("%s: EEPROM Checksum not OK\n", __FUNCTION__); + } else { + /* get the MACs */ + sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x", + buf[3], + buf[4], + buf[5], + buf[6], + buf[7], + buf[8]); + setenv ("ethaddr", (char *) mac); + sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x", + buf[9], + buf[10], + buf[11], + buf[12], + buf[13], + buf[14]); + setenv ("eth1addr", (char *) mac); + return; + } + } + + /* some error reading the EEprom */ + if ((use_eeprom = getenv ("use_eeprom_ethaddr")) == NULL) { + /* dont use bootcmd */ + setenv("bootdelay", "-1"); + return; + } + /* == default ? use standard */ + if (strncmp (use_eeprom, "default", 7) == 0) { + return; + } + /* Env doesnt exist -> hang */ + status_led_blink (); + hang (); + return; +} + +#ifdef CONFIG_PREBOOT + +static uchar kbd_magic_prefix[] = "key_magic"; +static uchar kbd_command_prefix[] = "key_cmd"; + +struct kbd_data_t { + char s1; + char s2; +}; + +struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data) +{ + char *val; + unsigned long tmp; + + /* use the DIPs for some bootoptions */ + val = getenv (ENV_NAME_DIP); + tmp = simple_strtoul (val, NULL, 16); + + kbd_data->s2 = (tmp & 0x0f); + kbd_data->s1 = (tmp & 0xf0) >> 4; + return kbd_data; +} + +static int compare_magic (const struct kbd_data_t *kbd_data, char *str) +{ + char s1 = str[0]; + + if (s1 >= '0' && s1 <= '9') + s1 -= '0'; + else if (s1 >= 'a' && s1 <= 'f') + s1 = s1 - 'a' + 10; + else if (s1 >= 'A' && s1 <= 'F') + s1 = s1 - 'A' + 10; + else + return -1; + + if (s1 != kbd_data->s1) return -1; + + s1 = str[1]; + if (s1 >= '0' && s1 <= '9') + s1 -= '0'; + else if (s1 >= 'a' && s1 <= 'f') + s1 = s1 - 'a' + 10; + else if (s1 >= 'A' && s1 <= 'F') + s1 = s1 - 'A' + 10; + else + return -1; + + if (s1 != kbd_data->s2) return -1; + return 0; +} + +static char *key_match (const struct kbd_data_t *kbd_data) +{ + char magic[sizeof (kbd_magic_prefix) + 1]; + char *suffix; + char *kbd_magic_keys; + + /* + * The following string defines the characters that can be appended + * to "key_magic" to form the names of environment variables that + * hold "magic" key codes, i. e. such key codes that can cause + * pre-boot actions. If the string is empty (""), then only + * "key_magic" is checked (old behaviour); the string "125" causes + * checks for "key_magic1", "key_magic2" and "key_magic5", etc. + */ + if ((kbd_magic_keys = getenv ("magic_keys")) == NULL) + kbd_magic_keys = ""; + + /* loop over all magic keys; + * use '\0' suffix in case of empty string + */ + for (suffix = kbd_magic_keys; *suffix || + suffix == kbd_magic_keys; ++suffix) { + sprintf (magic, "%s%c", kbd_magic_prefix, *suffix); + if (compare_magic (kbd_data, getenv (magic)) == 0) { + char cmd_name[sizeof (kbd_command_prefix) + 1]; + char *cmd; + + sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix); + cmd = getenv (cmd_name); + + return (cmd); + } + } + return (NULL); +} + +#endif /* CONFIG_PREBOOT */ + +static int pcs440ep_readinputs (void) +{ + int i; + char value[20]; + + /* read the inputs and set the Envvars */ + /* Revision Level Bit 26 - 29 */ + i = ((in32 (GPIO0_IR) & 0x0000003c) >> 2); + i = swapbits[i]; + sprintf (value, "%02x", i); + setenv (ENV_NAME_REVLEV, value); + /* Solder Switch Bit 30 - 33 */ + i = (in32 (GPIO0_IR) & 0x00000003) << 2; + i += (in32 (GPIO1_IR) & 0xc0000000) >> 30; + i = swapbits[i]; + sprintf (value, "%02x", i); + setenv (ENV_NAME_SOLDER, value); + /* DIP Switch Bit 49 - 56 */ + i = ((in32 (GPIO1_IR) & 0x00007f80) >> 7); + i = (swapbits[i & 0x0f] << 4) + swapbits[(i & 0xf0) >> 4]; + sprintf (value, "%02x", i); + setenv (ENV_NAME_DIP, value); + return 0; +} + + +#if defined(CONFIG_SHA1_CHECK_UB_IMG) +/************************************************************************* + * calculate a SHA1 sum for the U-Boot image in Flash. + * + ************************************************************************/ +static int pcs440ep_sha1 (int docheck) +{ + unsigned char *data; + unsigned char *ptroff; + unsigned char output[20]; + unsigned char org[20]; + int i, len = CONFIG_SHA1_LEN; + + memcpy ((char *)CFG_LOAD_ADDR, (char *)CONFIG_SHA1_START, len); + data = (unsigned char *)CFG_LOAD_ADDR; + ptroff = &data[len + SHA1_SUM_POS]; + + for (i = 0; i < SHA1_SUM_LEN; i++) { + org[i] = ptroff[i]; + ptroff[i] = 0; + } + + sha1_csum ((unsigned char *) data, len, (unsigned char *)output); + + if (docheck == 2) { + for (i = 0; i < 20 ; i++) { + printf("%02X ", output[i]); + } + printf("\n"); + } + if (docheck == 1) { + for (i = 0; i < 20 ; i++) { + if (org[i] != output[i]) return 1; + } + } + return 0; +} + +/************************************************************************* + * do some checks after the SHA1 checksum from the U-Boot Image was + * calculated. + * + ************************************************************************/ +static void pcs440ep_checksha1 (void) +{ + int ret; + char *cs_test; + + ret = pcs440ep_sha1 (1); + if (ret == 0) return; + + if ((cs_test = getenv ("cs_test")) == NULL) { + /* Env doesnt exist -> hang */ + status_led_blink (); + hang (); + } + + if (strncmp (cs_test, "off", 3) == 0) { + printf ("SHA1 U-Boot sum NOT ok!\n"); + setenv ("bootdelay", "-1"); + } +} +#else +static __inline__ void pcs440ep_checksha1 (void) { do {} while (0);} +#endif + int misc_init_r (void) { uint pbcr; @@ -139,6 +477,18 @@ int misc_init_r (void) CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1, &flash_info[1]); + pcs440ep_readinputs (); + pcs440ep_checksha1 (); +#ifdef CONFIG_PREBOOT + { + struct kbd_data_t kbd_data; + /* Decode keys */ + char *str = strdup (key_match (get_keys (&kbd_data))); + /* Set or delete definition */ + setenv ("preboot", str); + free (str); + } +#endif /* CONFIG_PREBOOT */ return 0; } @@ -156,13 +506,34 @@ int checkboard(void) return (0); } + +#if defined(CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG) +void spd_ddr_init_hang (void) +{ + status_led_set (0, STATUS_LED_OFF); + status_led_set (1, STATUS_LED_ON); + /* we cannot use hang() because we are still running from + Flash, and so the status_led driver is not initialized */ + puts ("### ERROR ### Please RESET the board ###\n"); + for (;;) { + __led_toggle (4); + udelay (100000); + } +} +#endif + long int initdram (int board_type) { long dram_size = 0; - set_leds(1); /* display boot info counter */ + status_led_set (0, STATUS_LED_ON); + status_led_set (1, STATUS_LED_OFF); dram_size = spd_sdram(); - set_leds(2); /* display boot info counter */ + status_led_set (0, STATUS_LED_OFF); + status_led_set (1, STATUS_LED_ON); + if (dram_size == 0) { + hang(); + } return dram_size; } @@ -377,3 +748,120 @@ void hw_watchdog_reset(void) } #endif + +/************************************************************************* + * "led" Commando for the U-Boot shell + * + ************************************************************************/ +int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = 0; + ulong pattern = 0; + + pattern = simple_strtoul (argv[1], NULL, 10); + if (pattern > 200) { + status_led_blink (); + hang (); + return rcode; + } + if (pattern > 100) { + status_led_blink (); + return rcode; + } + pattern &= 0x0f; + set_leds (pattern); + return rcode; +} + +U_BOOT_CMD( + led, 2, 1, do_led, + "led - set the led\n", + NULL +); + +#if defined(CONFIG_SHA1_CHECK_UB_IMG) +/************************************************************************* + * "sha1" Commando for the U-Boot shell + * + ************************************************************************/ +int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = -1; + + if (argc < 2) { + usage: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + if (argc >= 3) { + unsigned char *data; + unsigned char output[20]; + int len; + int i; + + data = (unsigned char *)simple_strtoul (argv[1], NULL, 16); + len = simple_strtoul (argv[2], NULL, 16); + sha1_csum (data, len, (unsigned char *)output); + printf ("U-Boot sum:\n"); + for (i = 0; i < 20 ; i++) { + printf ("%02X ", output[i]); + } + printf ("\n"); + if (argc == 4) { + data = (unsigned char *)simple_strtoul (argv[3], NULL, 16); + memcpy (data, output, 20); + } + return 0; + } + if (argc == 2) { + char *ptr = argv[1]; + if (*ptr != '-') goto usage; + ptr++; + if ((*ptr == 'c') || (*ptr == 'C')) { + rcode = pcs440ep_sha1 (1); + printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : ""); + } else if ((*ptr == 'p') || (*ptr == 'P')) { + rcode = pcs440ep_sha1 (2); + } else { + rcode = pcs440ep_sha1 (0); + } + return rcode; + } + return rcode; +} + +U_BOOT_CMD( + sha1, 4, 1, do_sha1, + "sha1 - calculate the SHA1 Sum\n", + "address len [addr] calculate the SHA1 sum [save at addr]\n" + " -p calculate the SHA1 sum from the U-Boot image in flash and print\n" + " -c check the U-Boot image in flash\n" +); +#endif + +#ifdef CONFIG_IDE_PREINIT +int ide_preinit (void) +{ + /* Set True IDE Mode */ + out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000)); + out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000)); + out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040)); + udelay (100000); + return 0; +} +#endif + +#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) +void ide_set_reset (int idereset) +{ + debug ("ide_reset(%d)\n", idereset); + if (idereset == 0) { + out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000)); + } else { + out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000)); + } + udelay (10000); +} +#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ + diff --git a/board/pcs440ep/u-boot.lds b/board/pcs440ep/u-boot.lds index 6ab476ab143..6506ccdcf36 100644 --- a/board/pcs440ep/u-boot.lds +++ b/board/pcs440ep/u-boot.lds @@ -65,6 +65,7 @@ SECTIONS { cpu/ppc4xx/start.o (.text) board/pcs440ep/init.o (.text) + lib_generic/sha1.o (.text) *(.text) *(.fixup) diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c index b6add59bb48..f6f0e724437 100644 --- a/board/sc520_cdp/sc520_cdp.c +++ b/board/sc520_cdp/sc520_cdp.c @@ -507,6 +507,7 @@ int dram_init(void) void show_boot_progress(int val) { + if (val < -32) val = -1; /* let things compatible */ outb(val&0xff, 0x80); outb((val&0xff00)>>8, 0x680); } diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c index ed226fd6423..d119a7d9977 100644 --- a/board/sc520_spunk/sc520_spunk.c +++ b/board/sc520_spunk/sc520_spunk.c @@ -507,6 +507,7 @@ void show_boot_progress(int val) { int version = read_mmcr_byte(SC520_SYSINFO); + if (val < -32) val = -1; /* let things compatible */ if (version == 0) { /* PIO31-PIO16 Data */ write_mmcr_word(SC520_PIODATA31_16, diff --git a/common/cmd_doc.c b/common/cmd_doc.c index ab375169531..4e624a2f3fa 100644 --- a/common/cmd_doc.c +++ b/common/cmd_doc.c @@ -216,6 +216,7 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) image_header_t *hdr; int rcode = 0; + SHOW_BOOT_PROGRESS (34); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -236,24 +237,27 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-35); return 1; } + SHOW_BOOT_PROGRESS (35); if (!boot_device) { puts ("\n** No boot device **\n"); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-36); return 1; } + SHOW_BOOT_PROGRESS (36); dev = simple_strtoul(boot_device, &ep, 16); if ((dev >= CFG_MAX_DOC_DEVICE) || (doc_dev_desc[dev].ChipID == DOC_ChipID_UNKNOWN)) { printf ("\n** Device %d not available\n", dev); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-37); return 1; } + SHOW_BOOT_PROGRESS (37); printf ("\nLoading from device %d: %s at 0x%lX (offset 0x%lX)\n", dev, doc_dev_desc[dev].name, doc_dev_desc[dev].physadr, @@ -262,9 +266,10 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (doc_rw (doc_dev_desc + dev, 1, offset, SECTORSIZE, NULL, (u_char *)addr)) { printf ("** Read error on %d\n", dev); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-38); return 1; } + SHOW_BOOT_PROGRESS (38); hdr = (image_header_t *)addr; @@ -276,16 +281,18 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) cnt -= SECTORSIZE; } else { puts ("\n** Bad Magic Number **\n"); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-39); return 1; } + SHOW_BOOT_PROGRESS (39); if (doc_rw (doc_dev_desc + dev, 1, offset + SECTORSIZE, cnt, NULL, (u_char *)(addr+SECTORSIZE))) { printf ("** Read error on %d\n", dev); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-40); return 1; } + SHOW_BOOT_PROGRESS (40); /* Loading ok, update default load address */ diff --git a/common/cmd_ide.c b/common/cmd_ide.c index e308474af71..c74cde96e89 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -185,6 +185,9 @@ static void input_data(int dev, ulong *sect_buf, int words); static void output_data(int dev, ulong *sect_buf, int words); static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len); +#ifndef CFG_ATA_PORT_ADDR +#define CFG_ATA_PORT_ADDR(port) (port) +#endif #ifdef CONFIG_ATAPI static void atapi_inquiry(block_dev_desc_t *dev_desc); @@ -382,6 +385,7 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) image_header_t *hdr; int rcode = 0; + SHOW_BOOT_PROGRESS (41); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -397,44 +401,50 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-42); return 1; } + SHOW_BOOT_PROGRESS (42); if (!boot_device) { puts ("\n** No boot device **\n"); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-43); return 1; } + SHOW_BOOT_PROGRESS (43); dev = simple_strtoul(boot_device, &ep, 16); if (ide_dev_desc[dev].type==DEV_TYPE_UNKNOWN) { printf ("\n** Device %d not available\n", dev); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-44); return 1; } + SHOW_BOOT_PROGRESS (44); if (*ep) { if (*ep != ':') { puts ("\n** Invalid boot device, use `dev[:part]' **\n"); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-45); return 1; } part = simple_strtoul(++ep, NULL, 16); } + SHOW_BOOT_PROGRESS (45); if (get_partition_info (&ide_dev_desc[dev], part, &info)) { - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-46); return 1; } + SHOW_BOOT_PROGRESS (46); if ((strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) && (strncmp((char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) { printf ("\n** Invalid partition type \"%.32s\"" " (expect \"" BOOT_PART_TYPE "\")\n", info.type); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-47); return 1; } + SHOW_BOOT_PROGRESS (47); printf ("\nLoading from IDE device %d, partition %d: " "Name: %.32s Type: %.32s\n", @@ -445,26 +455,29 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (ide_dev_desc[dev].block_read (dev, info.start, 1, (ulong *)addr) != 1) { printf ("** Read error on %d:%d\n", dev, part); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-48); return 1; } + SHOW_BOOT_PROGRESS (48); hdr = (image_header_t *)addr; if (ntohl(hdr->ih_magic) != IH_MAGIC) { printf("\n** Bad Magic Number **\n"); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-49); return 1; } + SHOW_BOOT_PROGRESS (49); checksum = ntohl(hdr->ih_hcrc); hdr->ih_hcrc = 0; if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) { puts ("\n** Bad Header Checksum **\n"); - SHOW_BOOT_PROGRESS (-2); + SHOW_BOOT_PROGRESS (-50); return 1; } + SHOW_BOOT_PROGRESS (50); hdr->ih_hcrc = htonl(checksum); /* restore checksum for later use */ print_image_hdr (hdr); @@ -477,9 +490,10 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (ide_dev_desc[dev].block_read (dev, info.start+1, cnt, (ulong *)(addr+info.blksz)) != cnt) { printf ("** Read error on %d:%d\n", dev, part); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-51); return 1; } + SHOW_BOOT_PROGRESS (51); /* Loading ok, update default load address */ @@ -807,13 +821,13 @@ ide_outb(int dev, int port, unsigned char val) /* Ensure I/O operations complete */ EIEIO; - *((uchar *)(ATA_CURR_BASE(dev)+port)) = val; + *((u16 *)(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))) = val; } #else /* ! __PPC__ */ static void __inline__ ide_outb(int dev, int port, unsigned char val) { - outb(val, ATA_CURR_BASE(dev)+port); + outb(val, ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)); } #endif /* __PPC__ */ @@ -825,7 +839,7 @@ ide_inb(int dev, int port) uchar val; /* Ensure I/O operations complete */ EIEIO; - val = *((uchar *)(ATA_CURR_BASE(dev)+port)); + val = *((u16 *)(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port))); debug ("ide_inb (dev= %d, port= 0x%x) : @ 0x%08lx -> 0x%02x\n", dev, port, (ATA_CURR_BASE(dev)+port), val); return (val); @@ -834,7 +848,7 @@ ide_inb(int dev, int port) static unsigned char __inline__ ide_inb(int dev, int port) { - return inb(ATA_CURR_BASE(dev)+port); + return inb(ATA_CURR_BASE(dev)+CFG_ATA_PORT_ADDR(port)); } #endif /* __PPC__ */ @@ -891,6 +905,9 @@ input_swap_data(int dev, ulong *sect_buf, int words) #ifdef __MIPS__ *dbuf++ = swab16p((u16*)pbuf); *dbuf++ = swab16p((u16*)pbuf); +#elif defined(CONFIG_PCS440EP) + *dbuf++ = *pbuf; + *dbuf++ = *pbuf; #else *dbuf++ = ld_le16(pbuf); *dbuf++ = ld_le16(pbuf); @@ -930,10 +947,18 @@ output_data(int dev, ulong *sect_buf, int words) pbuf = (ushort *)(ATA_CURR_BASE(dev)+ATA_DATA_REG); dbuf = (ushort *)sect_buf; while (words--) { +#if defined(CONFIG_PCS440EP) + /* not tested, because CF was write protected */ + EIEIO; + *pbuf = ld_le16(dbuf++); + EIEIO; + *pbuf = ld_le16(dbuf++); +#else EIEIO; *pbuf = *dbuf++; EIEIO; *pbuf = *dbuf++; +#endif } #endif } @@ -981,10 +1006,17 @@ input_data(int dev, ulong *sect_buf, int words) debug("in input data base for read is %lx\n", (unsigned long) pbuf); while (words--) { +#if defined(CONFIG_PCS440EP) + EIEIO; + *dbuf++ = ld_le16(pbuf); + EIEIO; + *dbuf++ = ld_le16(pbuf); +#else EIEIO; *dbuf++ = *pbuf; EIEIO; *dbuf++ = *pbuf; +#endif } #endif } diff --git a/common/cmd_nand.c b/common/cmd_nand.c index b011b5e3ded..b088150f3bf 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -486,17 +486,19 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, r = nand_read(nand, offset, &cnt, (u_char *) addr); if (r) { puts("** Read error\n"); - SHOW_BOOT_PROGRESS(-1); + SHOW_BOOT_PROGRESS(-56); return 1; } + SHOW_BOOT_PROGRESS(56); hdr = (image_header_t *) addr; if (ntohl(hdr->ih_magic) != IH_MAGIC) { printf("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic); - SHOW_BOOT_PROGRESS(-1); + SHOW_BOOT_PROGRESS(-57); return 1; } + SHOW_BOOT_PROGRESS(57); print_image_hdr(hdr); @@ -505,9 +507,10 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, r = nand_read(nand, offset, &cnt, (u_char *) addr); if (r) { puts("** Read error\n"); - SHOW_BOOT_PROGRESS(-1); + SHOW_BOOT_PROGRESS(-58); return 1; } + SHOW_BOOT_PROGRESS(58); /* Loading ok, update default load address */ @@ -559,6 +562,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } #endif + SHOW_BOOT_PROGRESS(52); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -582,23 +586,26 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) usage: #endif printf("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS(-1); + SHOW_BOOT_PROGRESS(-53); return 1; } + SHOW_BOOT_PROGRESS(53); if (!boot_device) { puts("\n** No boot device **\n"); - SHOW_BOOT_PROGRESS(-1); + SHOW_BOOT_PROGRESS(-54); return 1; } + SHOW_BOOT_PROGRESS(54); idx = simple_strtoul(boot_device, NULL, 16); if (idx < 0 || idx >= CFG_MAX_NAND_DEVICE || !nand_info[idx].name) { printf("\n** Device %d not available\n", idx); - SHOW_BOOT_PROGRESS(-1); + SHOW_BOOT_PROGRESS(-55); return 1; } + SHOW_BOOT_PROGRESS(55); return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]); } @@ -887,6 +894,7 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong offset = 0; image_header_t *hdr; int rcode = 0; + SHOW_BOOT_PROGRESS(52); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -907,24 +915,27 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-53); return 1; } + SHOW_BOOT_PROGRESS(53); if (!boot_device) { puts ("\n** No boot device **\n"); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-54); return 1; } + SHOW_BOOT_PROGRESS(54); dev = simple_strtoul(boot_device, &ep, 16); if ((dev >= CFG_MAX_NAND_DEVICE) || (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) { printf ("\n** Device %d not available\n", dev); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-55); return 1; } + SHOW_BOOT_PROGRESS(55); printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n", dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR, @@ -933,9 +944,10 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset, SECTORSIZE, NULL, (u_char *)addr)) { printf ("** Read error on %d\n", dev); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-56); return 1; } + SHOW_BOOT_PROGRESS(56); hdr = (image_header_t *)addr; @@ -947,17 +959,19 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) cnt -= SECTORSIZE; } else { printf ("\n** Bad Magic Number 0x%x **\n", ntohl(hdr->ih_magic)); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-57); return 1; } + SHOW_BOOT_PROGRESS(57); if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset + SECTORSIZE, cnt, NULL, (u_char *)(addr+SECTORSIZE))) { printf ("** Read error on %d\n", dev); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-58); return 1; } + SHOW_BOOT_PROGRESS(58); /* Loading ok, update default load address */ diff --git a/common/cmd_net.c b/common/cmd_net.c index 2cb2c5d34be..e9d552e2352 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -30,6 +30,13 @@ #if (CONFIG_COMMANDS & CFG_CMD_NET) +#ifdef CONFIG_SHOW_BOOT_PROGRESS +# include +extern void show_boot_progress (int val); +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress (arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif extern int do_bootm (cmd_tbl_t *, int, int, char *[]); @@ -184,18 +191,25 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); + SHOW_BOOT_PROGRESS(-80); return 1; } - if ((size = NetLoop(proto)) < 0) + SHOW_BOOT_PROGRESS(80); + if ((size = NetLoop(proto)) < 0) { + SHOW_BOOT_PROGRESS(-81); return 1; + } + SHOW_BOOT_PROGRESS(81); /* NetLoop ok, update environment */ netboot_update_env(); /* done if no file was loaded (no errors though) */ - if (size == 0) + if (size == 0) { + SHOW_BOOT_PROGRESS(-82); return 0; + } /* flush cache */ flush_cache(load_addr, size); @@ -208,14 +222,22 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) printf ("Automatic boot of image at addr 0x%08lX ...\n", load_addr); + SHOW_BOOT_PROGRESS(82); rcode = do_bootm (cmdtp, 0, 1, local_args); } #ifdef CONFIG_AUTOSCRIPT if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) { printf("Running autoscript at addr 0x%08lX ...\n", load_addr); + SHOW_BOOT_PROGRESS(83); rcode = autoscript (load_addr); } +#endif +#if defined(CONFIG_SHOW_BOOT_PROGRESS) + if (rcode < 0) + SHOW_BOOT_PROGRESS(-83); + else + SHOW_BOOT_PROGRESS(84); #endif return rcode; } diff --git a/common/cmd_reiser.c b/common/cmd_reiser.c index 09c86e66d76..d83c31ab3fe 100644 --- a/common/cmd_reiser.c +++ b/common/cmd_reiser.c @@ -90,7 +90,7 @@ int do_reiserls (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } if (!reiserfs_mount(part_length)) { - printf ("** Bad Reisefs partition or disk - %s %d:%d **\n", argv[1], dev, part); + printf ("** Bad Reiserfs partition or disk - %s %d:%d **\n", argv[1], dev, part); return 1; } @@ -183,7 +183,7 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } - if (strncmp(info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) { + if (strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) { printf ("\n** Invalid partition type \"%.32s\"" " (expect \"" BOOT_PART_TYPE "\")\n", info.type); @@ -204,7 +204,7 @@ int do_reiserload (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } if (!reiserfs_mount(part_length)) { - printf ("** Bad Reisefs partition or disk - %s %d:%d **\n", argv[1], dev, part); + printf ("** Bad Reiserfs partition or disk - %s %d:%d **\n", argv[1], dev, part); return 1; } diff --git a/common/env_common.c b/common/env_common.c index eb33422af4b..0462cad6d72 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -232,7 +232,7 @@ void env_relocate (void) puts ("Using default environment\n\n"); #else puts ("*** Warning - bad CRC, using default environment\n\n"); - SHOW_BOOT_PROGRESS (-1); + SHOW_BOOT_PROGRESS (-60); #endif if (sizeof(default_environment) > ENV_SIZE) diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index c500d3f2421..8621aa00cf4 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -70,6 +70,13 @@ #define ONE_BILLION 1000000000 +#if defined(CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG) +extern void spd_ddr_init_hang (void); +#define HANG() spd_ddr_init_hang() +#else +#define HANG() hang() +#endif + /*----------------------------------------------------------------------------- | Memory Controller Options 0 +-----------------------------------------------------------------------------*/ @@ -467,7 +474,7 @@ static void get_spd_info(unsigned long *dimm_populated, if (dimm_found == FALSE) { printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); - hang(); + HANG(); } } @@ -490,7 +497,7 @@ static void check_mem_type(unsigned long *dimm_populated, dimm_num); printf("Only DDR SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); + HANG(); break; } } @@ -510,7 +517,7 @@ static void check_volt_type(unsigned long *dimm_populated, if (voltage_type != 0x04) { printf("ERROR: DIMM %lu with unsupported voltage level.\n", dimm_num); - hang(); + HANG(); } else { debug("DIMM %lu voltage level supported.\n", dimm_num); } @@ -581,7 +588,7 @@ static void program_cfg0(unsigned long *dimm_populated, printf("WARNING: DIMM with datawidth of %lu bits.\n", data_width); printf("Only DIMMs with 32 or 64 bit datawidths supported.\n"); - hang(); + HANG(); } break; } @@ -769,7 +776,7 @@ static void program_tr0(unsigned long *dimm_populated, if ((tcyc_reg & 0x0F) >= 10) { printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n", dimm_num); - hang(); + HANG(); } cycle_time_ns_x_10[cas_index] = @@ -849,7 +856,7 @@ static void program_tr0(unsigned long *dimm_populated, printf("ERROR: No supported CAS latency with the installed DIMMs.\n"); printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n"); printf("Make sure the PLB speed is within the supported range.\n"); - hang(); + HANG(); } /* @@ -1008,6 +1015,7 @@ static int short_mem_test(void) */ for (i = 0; i < NUMMEMTESTS; i++) { for (j = 0; j < NUMMEMWORDS; j++) { +//printf("bank enabled base:%x\n", &membase[j]); membase[j] = test[i][j]; ppcDcbf((unsigned long)&(membase[j])); } @@ -1160,7 +1168,7 @@ static void program_tr1(void) */ if (window_found == FALSE) { printf("ERROR: Cannot determine a common read delay.\n"); - hang(); + HANG(); } /* @@ -1310,7 +1318,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, printf("ERROR: Unsupported value for the banksize: %d.\n", bank_size_id); printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); + HANG(); } switch (num_col_addr) { @@ -1332,7 +1340,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, printf("ERROR: Unsupported value for number of " "column addresses: %d.\n", num_col_addr); printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); + HANG(); } /* diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 48b9ee2f7e0..d748daee015 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -129,6 +129,13 @@ #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ #endif +#if defined(CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG) +extern void spd_ddr_init_hang (void); +#define HANG() spd_ddr_init_hang() +#else +#define HANG() hang() +#endif + /* Private Structure Definitions */ /* enum only to ease code for cas latency setting */ @@ -582,7 +589,7 @@ static void get_spd_info(unsigned long *dimm_populated, if (dimm_found == FALSE) { printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); - hang(); + HANG(); } } @@ -629,42 +636,42 @@ static void check_mem_type(unsigned long *dimm_populated, "slot %d.\n", (unsigned int)dimm_num); printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); + HANG(); break; case 2: printf("ERROR: EDO DIMM detected in slot %d.\n", (unsigned int)dimm_num); printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); + HANG(); break; case 3: printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n", (unsigned int)dimm_num); printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); + HANG(); break; case 4: printf("ERROR: SDRAM DIMM detected in slot %d.\n", (unsigned int)dimm_num); printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); + HANG(); break; case 5: printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n", (unsigned int)dimm_num); printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); + HANG(); break; case 6: printf("ERROR: SGRAM DIMM detected in slot %d.\n", (unsigned int)dimm_num); printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); + HANG(); break; case 7: debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num); @@ -679,7 +686,7 @@ static void check_mem_type(unsigned long *dimm_populated, (unsigned int)dimm_num); printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); + HANG(); break; } } @@ -689,7 +696,7 @@ static void check_mem_type(unsigned long *dimm_populated, && (dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) { printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n"); - hang(); + HANG(); } } } @@ -764,7 +771,7 @@ static void check_frequency(unsigned long *dimm_populated, (unsigned int)(calc_cycle_time*10)); printf("Replace the DIMM, or change DDR frequency via " "strapping bits.\n\n"); - hang(); + HANG(); } } } @@ -796,7 +803,7 @@ static void check_rank_number(unsigned long *dimm_populated, "slot %d is not supported.\n", dimm_rank, dimm_num); printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS); printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); + HANG(); } else total_rank += dimm_rank; } @@ -805,7 +812,7 @@ static void check_rank_number(unsigned long *dimm_populated, "for all slots.\n", (unsigned int)total_rank); printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS); printf("Remove one of the DIMM modules.\n\n"); - hang(); + HANG(); } } } @@ -830,28 +837,28 @@ static void check_voltage_type(unsigned long *dimm_populated, printf("This DIMM is 5.0 Volt/TTL.\n"); printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", (unsigned int)dimm_num); - hang(); + HANG(); break; case 0x01: printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); printf("This DIMM is LVTTL.\n"); printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", (unsigned int)dimm_num); - hang(); + HANG(); break; case 0x02: printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); printf("This DIMM is 1.5 Volt.\n"); printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", (unsigned int)dimm_num); - hang(); + HANG(); break; case 0x03: printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); printf("This DIMM is 3.3 Volt/TTL.\n"); printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", (unsigned int)dimm_num); - hang(); + HANG(); break; case 0x04: /* 2.5 Voltage only for DDR1 */ @@ -863,7 +870,7 @@ static void check_voltage_type(unsigned long *dimm_populated, printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", (unsigned int)dimm_num); - hang(); + HANG(); break; } } @@ -1006,13 +1013,13 @@ static void program_copt1(unsigned long *dimm_populated, if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) { if (buf0 != buf1) { printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n"); - hang(); + HANG(); } } if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) { printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n"); - hang(); + HANG(); } else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) { mcopt1 |= SDRAM_MCOPT1_DMWD_64; @@ -1020,7 +1027,7 @@ static void program_copt1(unsigned long *dimm_populated, mcopt1 |= SDRAM_MCOPT1_DMWD_32; } else { printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n"); - hang(); + HANG(); } if (ecc_enabled == TRUE) @@ -1209,7 +1216,7 @@ static void program_initplr(unsigned long *dimm_populated, break; default: printf("ERROR: ucode error on selected_cas value %d", selected_cas); - hang(); + HANG(); break; } @@ -1241,7 +1248,7 @@ static void program_initplr(unsigned long *dimm_populated, break; default: printf("ERROR: write recovery not support (%d)", write_recovery); - hang(); + HANG(); break; } #else @@ -1259,7 +1266,7 @@ static void program_initplr(unsigned long *dimm_populated, ods = ODS_REDUCED; } else { printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm); - hang(); + HANG(); } mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas; @@ -1284,7 +1291,7 @@ static void program_initplr(unsigned long *dimm_populated, mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */ } else { printf("ERROR: ucode error as unknown DDR type in program_initplr"); - hang(); + HANG(); } } @@ -1389,7 +1396,7 @@ static void program_mode(unsigned long *dimm_populated, } else { printf("ERROR: SPD reported Tcyc is incorrect for DIMM " "in slot %d\n", (unsigned int)dimm_num); - hang(); + HANG(); } } else { /* Convert from hex to decimal */ @@ -1526,7 +1533,7 @@ static void program_mode(unsigned long *dimm_populated, printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n"); printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n"); printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n"); - hang(); + HANG(); } } else { /* DDR2 */ debug("cas_3_0_available=%d\n", cas_3_0_available); @@ -1549,7 +1556,7 @@ static void program_mode(unsigned long *dimm_populated, cas_3_0_available, cas_4_0_available, cas_5_0_available); printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n", sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk); - hang(); + HANG(); } } @@ -1658,7 +1665,7 @@ static void program_rtr(unsigned long *dimm_populated, printf("ERROR: DIMM %d unsupported refresh rate/type.\n", (unsigned int)dimm_num); printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); + HANG(); break; } @@ -2066,7 +2073,7 @@ static void program_bxcf(unsigned long *dimm_populated, printf("ERROR: Unsupported value for number of " "column addresses: %d.\n", (unsigned int)num_col_addr); printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); + HANG(); } } @@ -2148,7 +2155,7 @@ static void program_memory_queue(unsigned long *dimm_populated, printf("ERROR: Unsupported value for the banksize: %d.\n", (unsigned int)rank_size_id); printf("Replace the DIMM module with a supported DIMM.\n\n"); - hang(); + HANG(); } if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1)) @@ -2693,7 +2700,7 @@ calibration_loop: printf("\nERROR: Cannot determine a common read delay for the " "DIMM(s) installed.\n"); debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__); - hang(); + HANG(); } blank_string(strlen(str)); @@ -2849,7 +2856,7 @@ static void test(void) if (window_found == FALSE) { printf("ERROR: Cannot determine a common read delay for the " "DIMM(s) installed.\n"); - hang(); + HANG(); } /*------------------------------------------------------------------ diff --git a/disk/part.c b/disk/part.c index 255b1406982..6ab5857073c 100755 --- a/disk/part.c +++ b/disk/part.c @@ -180,7 +180,6 @@ void dev_print (block_dev_desc_t *dev_desc) (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ (CONFIG_COMMANDS & CFG_CMD_USB) || \ defined(CONFIG_MMC) || \ - (defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \ defined(CONFIG_SYSTEMACE) ) #if defined(CONFIG_MAC_PARTITION) || \ @@ -223,7 +222,7 @@ void init_part (block_dev_desc_t * dev_desc) int get_partition_info (block_dev_desc_t *dev_desc, int part , disk_partition_t *info) { - switch (dev_desc->part_type) { + switch (dev_desc->part_type) { #ifdef CONFIG_MAC_PARTITION case PART_TYPE_MAC: if (get_partition_info_mac(dev_desc,part,info) == 0) { diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 3007608360a..21a00b80d41 100755 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -70,10 +70,11 @@ int fat_register_device(block_dev_desc_t *dev_desc, int part_no) { unsigned char buffer[SECTOR_SIZE]; + disk_partition_t info; if (!dev_desc->block_read) return -1; - cur_dev=dev_desc; + cur_dev = dev_desc; /* check if we have a MBR (on floppies we have only a PBR) */ if (dev_desc->block_read (dev_desc->dev, 0, 1, (ulong *) buffer) != 1) { printf ("** Can't read from device %d **\n", dev_desc->dev); @@ -84,36 +85,39 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no) /* no signature found */ return -1; } - if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) { - /* ok, we assume we are on a PBR only */ - cur_part = 1; - part_offset=0; - } - else { #if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \ (CONFIG_COMMANDS & CFG_CMD_SCSI) || \ (CONFIG_COMMANDS & CFG_CMD_USB) || \ - (defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \ + (defined(CONFIG_MMC)) || \ defined(CONFIG_SYSTEMACE) ) - disk_partition_t info; - if(!get_partition_info(dev_desc, part_no, &info)) { - part_offset = info.start; - cur_part = part_no; - } - else { - printf ("** Partition %d not valid on device %d **\n",part_no,dev_desc->dev); - return -1; - } + /* First we assume, there is a MBR */ + if (!get_partition_info (dev_desc, part_no, &info)) { + part_offset = info.start; + cur_part = part_no; + } else if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3)) { + /* ok, we assume we are on a PBR only */ + cur_part = 1; + part_offset = 0; + } else { + printf ("** Partition %d not valid on device %d **\n", part_no, dev_desc->dev); + return -1; + } #else + if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) { + /* ok, we assume we are on a PBR only */ + cur_part = 1; + part_offset = 0; + info.start = part_offset; + } else { /* FIXME we need to determine the start block of the * partition where the DOS FS resides. This can be done * by using the get_partition_info routine. For this * purpose the libpart must be included. */ - part_offset=32; + part_offset = 32; cur_part = 1; -#endif } +#endif return 0; } diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 23bdfc8dfb9..d4718088213 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -105,19 +105,27 @@ #ifdef CFG_ENV_IS_IN_FLASH #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +#define CONFIG_ENV_OVERWRITE 1 /* Address and size of Redundant Environment Sector */ #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) #endif /* CFG_ENV_IS_IN_FLASH */ +#define ENV_NAME_REVLEV "revision_level" +#define ENV_NAME_SOLDER "solder_switch" +#define ENV_NAME_DIP "dip" + /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ #undef CONFIG_DDR_ECC /* don't use ECC */ #define SPD_EEPROM_ADDRESS {0x50} +#define CONFIG_PROG_SDRAM_TLB 1 +#define CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG 1 /*----------------------------------------------------------------------- * I2C @@ -142,6 +150,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=pcs440ep\0" \ + "use_eeprom_ethaddr=default\0" \ + "cs_test=off\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -172,6 +182,36 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #endif +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +/* check U-Boot image with SHA1 sum */ +#define CONFIG_SHA1_CHECK_UB_IMG 1 +#define CONFIG_SHA1_START CFG_MONITOR_BASE +#define CONFIG_SHA1_LEN CFG_MONITOR_LEN + +/*----------------------------------------------------------------------- + * Definitions for status LED + */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED 1 + +#define STATUS_LED_BIT 0x08 /* LED 1 is on GPIO_PPC_1 */ +#define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ +#define STATUS_LED_STATE STATUS_LED_OFF +#define STATUS_LED_BIT1 0x04 /* LED 2 is on GPIO_PPC_2 */ +#define STATUS_LED_PERIOD1 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ +#define STATUS_LED_STATE1 STATUS_LED_ON +#define STATUS_LED_BIT2 0x02 /* LED 3 is on GPIO_PPC_3 */ +#define STATUS_LED_PERIOD2 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ +#define STATUS_LED_STATE2 STATUS_LED_OFF +#define STATUS_LED_BIT3 0x01 /* LED 4 is on GPIO_PPC_4 */ +#define STATUS_LED_PERIOD3 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ +#define STATUS_LED_STATE3 STATUS_LED_OFF + +#define CONFIG_SHOW_BOOT_PROGRESS 1 + #define CONFIG_BAUDRATE 115200 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ @@ -213,7 +253,10 @@ CFG_CMD_DIAG | \ CFG_CMD_EEPROM | \ CFG_CMD_ELF | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FAT | \ CFG_CMD_I2C | \ + CFG_CMD_IDE | \ CFG_CMD_IRQ | \ CFG_CMD_MII | \ CFG_CMD_NET | \ @@ -221,9 +264,8 @@ CFG_CMD_PCI | \ CFG_CMD_PING | \ CFG_CMD_REGINFO | \ + CFG_CMD_REISER | \ CFG_CMD_SDRAM | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FAT | \ CFG_CMD_USB ) @@ -410,4 +452,39 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/*----------------------------------------------------------------------- + * IDE/ATA stuff Supports IDE harddisk + *----------------------------------------------------------------------- + */ + +#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */ + +#define CONFIG_IDE_PREINIT 1 +#define CONFIG_IDE_RESET 1 + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_CF1 + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET 0 + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET (0x0000) + +/* This addresses need to be shifted one place to the left + * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0) + * This values are shifted + */ +#define CFG_ATA_PORT_ADDR(port) ((port) << 1) + #endif /* __CONFIG_H */ diff --git a/include/sha1.h b/include/sha1.h new file mode 100644 index 00000000000..3030f2975f2 --- /dev/null +++ b/include/sha1.h @@ -0,0 +1,115 @@ +/** + * \file sha1.h + * based from http://xyssl.org/code/source/sha1/ + * FIPS-180-1 compliant SHA-1 implementation + * + * Copyright (C) 2003-2006 Christophe Devine + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License, version 2.1 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ +/* + * The SHA-1 standard was published by NIST in 1993. + * + * http://www.itl.nist.gov/fipspubs/fip180-1.htm + */ +#ifndef _SHA1_H +#define _SHA1_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define SHA1_SUM_POS -0x20 +#define SHA1_SUM_LEN 20 + +/** + * \brief SHA-1 context structure + */ +typedef struct +{ + unsigned long total[2]; /*!< number of bytes processed */ + unsigned long state[5]; /*!< intermediate digest state */ + unsigned char buffer[64]; /*!< data block being processed */ +} +sha1_context; + +/** + * \brief SHA-1 context setup + * + * \param ctx SHA-1 context to be initialized + */ +void sha1_starts( sha1_context *ctx ); + +/** + * \brief SHA-1 process buffer + * + * \param ctx SHA-1 context + * \param input buffer holding the data + * \param ilen length of the input data + */ +void sha1_update( sha1_context *ctx, unsigned char *input, int ilen ); + +/** + * \brief SHA-1 final digest + * + * \param ctx SHA-1 context + * \param output SHA-1 checksum result + */ +void sha1_finish( sha1_context *ctx, unsigned char output[20] ); + +/** + * \brief Output = SHA-1( input buffer ) + * + * \param input buffer holding the data + * \param ilen length of the input data + * \param output SHA-1 checksum result + */ +void sha1_csum( unsigned char *input, int ilen, + unsigned char output[20] ); + +/** + * \brief Output = SHA-1( file contents ) + * + * \param path input file name + * \param output SHA-1 checksum result + * \return 0 if successful, or 1 if fopen failed + */ +int sha1_file( char *path, unsigned char output[20] ); + +/** + * \brief Output = HMAC-SHA-1( input buffer, hmac key ) + * + * \param key HMAC secret key + * \param keylen length of the HMAC key + * \param input buffer holding the data + * \param ilen length of the input data + * \param output HMAC-SHA-1 result + */ +void sha1_hmac( unsigned char *key, int keylen, + unsigned char *input, int ilen, + unsigned char output[20] ); + +/** + * \brief Checkup routine + * + * \return 0 if successful, or 1 if the test failed + */ +int sha1_self_test( void ); + +#ifdef __cplusplus +} +#endif + +#endif /* sha1.h */ diff --git a/include/status_led.h b/include/status_led.h index 71a202fe36e..a6468142557 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -367,6 +367,13 @@ void status_led_set (int led, int state); #define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ +#elif defined(CONFIG_BOARD_SPECIFIC_LED) +/* led_id_t is unsigned long mask */ +typedef unsigned long led_id_t; + +extern void __led_toggle (led_id_t mask); +extern void __led_init (led_id_t mask, int state); +extern void __led_set (led_id_t mask, int state); #else # error Status LED configuration missing #endif diff --git a/lib_generic/Makefile b/lib_generic/Makefile index f012cab7d8a..b2091c5e78b 100644 --- a/lib_generic/Makefile +++ b/lib_generic/Makefile @@ -27,7 +27,7 @@ LIB = $(obj)libgeneric.a COBJS = bzlib.o bzlib_crctable.o bzlib_decompress.o \ bzlib_randtable.o bzlib_huffman.o \ - crc32.o ctype.o display_options.o ldiv.o \ + crc32.o ctype.o display_options.o ldiv.o sha1.o \ string.o vsprintf.o zlib.o SRCS := $(COBJS:.o=.c) diff --git a/lib_generic/sha1.c b/lib_generic/sha1.c new file mode 100644 index 00000000000..0522d7ce67f --- /dev/null +++ b/lib_generic/sha1.c @@ -0,0 +1,430 @@ +/* + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * based on: + * FIPS-180-1 compliant SHA-1 implementation + * + * Copyright (C) 2003-2006 Christophe Devine + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License, version 2.1 as published by the Free Software Foundation. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ +/* + * The SHA-1 standard was published by NIST in 1993. + * + * http://www.itl.nist.gov/fipspubs/fip180-1.htm + */ + +#ifndef _CRT_SECURE_NO_DEPRECATE +#define _CRT_SECURE_NO_DEPRECATE 1 +#endif + +#include +#include "sha1.h" + +/* + * 32-bit integer manipulation macros (big endian) + */ +#ifndef GET_UINT32_BE +#define GET_UINT32_BE(n,b,i) \ +{ \ + (n) = ( (unsigned long) (b)[(i) ] << 24 ) \ + | ( (unsigned long) (b)[(i) + 1] << 16 ) \ + | ( (unsigned long) (b)[(i) + 2] << 8 ) \ + | ( (unsigned long) (b)[(i) + 3] ); \ +} +#endif +#ifndef PUT_UINT32_BE +#define PUT_UINT32_BE(n,b,i) \ +{ \ + (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ + (b)[(i) + 3] = (unsigned char) ( (n) ); \ +} +#endif + +/* + * SHA-1 context setup + */ +void sha1_starts( sha1_context *ctx ) +{ + ctx->total[0] = 0; + ctx->total[1] = 0; + + ctx->state[0] = 0x67452301; + ctx->state[1] = 0xEFCDAB89; + ctx->state[2] = 0x98BADCFE; + ctx->state[3] = 0x10325476; + ctx->state[4] = 0xC3D2E1F0; +} + +static void sha1_process( sha1_context *ctx, unsigned char data[64] ) +{ + unsigned long temp, W[16], A, B, C, D, E; + + GET_UINT32_BE( W[0], data, 0 ); + GET_UINT32_BE( W[1], data, 4 ); + GET_UINT32_BE( W[2], data, 8 ); + GET_UINT32_BE( W[3], data, 12 ); + GET_UINT32_BE( W[4], data, 16 ); + GET_UINT32_BE( W[5], data, 20 ); + GET_UINT32_BE( W[6], data, 24 ); + GET_UINT32_BE( W[7], data, 28 ); + GET_UINT32_BE( W[8], data, 32 ); + GET_UINT32_BE( W[9], data, 36 ); + GET_UINT32_BE( W[10], data, 40 ); + GET_UINT32_BE( W[11], data, 44 ); + GET_UINT32_BE( W[12], data, 48 ); + GET_UINT32_BE( W[13], data, 52 ); + GET_UINT32_BE( W[14], data, 56 ); + GET_UINT32_BE( W[15], data, 60 ); + +#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n))) + +#define R(t) \ +( \ + temp = W[(t - 3) & 0x0F] ^ W[(t - 8) & 0x0F] ^ \ + W[(t - 14) & 0x0F] ^ W[ t & 0x0F], \ + ( W[t & 0x0F] = S(temp,1) ) \ +) + +#define P(a,b,c,d,e,x) \ +{ \ + e += S(a,5) + F(b,c,d) + K + x; b = S(b,30); \ +} + + A = ctx->state[0]; + B = ctx->state[1]; + C = ctx->state[2]; + D = ctx->state[3]; + E = ctx->state[4]; + +#define F(x,y,z) (z ^ (x & (y ^ z))) +#define K 0x5A827999 + + P( A, B, C, D, E, W[0] ); + P( E, A, B, C, D, W[1] ); + P( D, E, A, B, C, W[2] ); + P( C, D, E, A, B, W[3] ); + P( B, C, D, E, A, W[4] ); + P( A, B, C, D, E, W[5] ); + P( E, A, B, C, D, W[6] ); + P( D, E, A, B, C, W[7] ); + P( C, D, E, A, B, W[8] ); + P( B, C, D, E, A, W[9] ); + P( A, B, C, D, E, W[10] ); + P( E, A, B, C, D, W[11] ); + P( D, E, A, B, C, W[12] ); + P( C, D, E, A, B, W[13] ); + P( B, C, D, E, A, W[14] ); + P( A, B, C, D, E, W[15] ); + P( E, A, B, C, D, R(16) ); + P( D, E, A, B, C, R(17) ); + P( C, D, E, A, B, R(18) ); + P( B, C, D, E, A, R(19) ); + +#undef K +#undef F + +#define F(x,y,z) (x ^ y ^ z) +#define K 0x6ED9EBA1 + + P( A, B, C, D, E, R(20) ); + P( E, A, B, C, D, R(21) ); + P( D, E, A, B, C, R(22) ); + P( C, D, E, A, B, R(23) ); + P( B, C, D, E, A, R(24) ); + P( A, B, C, D, E, R(25) ); + P( E, A, B, C, D, R(26) ); + P( D, E, A, B, C, R(27) ); + P( C, D, E, A, B, R(28) ); + P( B, C, D, E, A, R(29) ); + P( A, B, C, D, E, R(30) ); + P( E, A, B, C, D, R(31) ); + P( D, E, A, B, C, R(32) ); + P( C, D, E, A, B, R(33) ); + P( B, C, D, E, A, R(34) ); + P( A, B, C, D, E, R(35) ); + P( E, A, B, C, D, R(36) ); + P( D, E, A, B, C, R(37) ); + P( C, D, E, A, B, R(38) ); + P( B, C, D, E, A, R(39) ); + +#undef K +#undef F + +#define F(x,y,z) ((x & y) | (z & (x | y))) +#define K 0x8F1BBCDC + + P( A, B, C, D, E, R(40) ); + P( E, A, B, C, D, R(41) ); + P( D, E, A, B, C, R(42) ); + P( C, D, E, A, B, R(43) ); + P( B, C, D, E, A, R(44) ); + P( A, B, C, D, E, R(45) ); + P( E, A, B, C, D, R(46) ); + P( D, E, A, B, C, R(47) ); + P( C, D, E, A, B, R(48) ); + P( B, C, D, E, A, R(49) ); + P( A, B, C, D, E, R(50) ); + P( E, A, B, C, D, R(51) ); + P( D, E, A, B, C, R(52) ); + P( C, D, E, A, B, R(53) ); + P( B, C, D, E, A, R(54) ); + P( A, B, C, D, E, R(55) ); + P( E, A, B, C, D, R(56) ); + P( D, E, A, B, C, R(57) ); + P( C, D, E, A, B, R(58) ); + P( B, C, D, E, A, R(59) ); + +#undef K +#undef F + +#define F(x,y,z) (x ^ y ^ z) +#define K 0xCA62C1D6 + + P( A, B, C, D, E, R(60) ); + P( E, A, B, C, D, R(61) ); + P( D, E, A, B, C, R(62) ); + P( C, D, E, A, B, R(63) ); + P( B, C, D, E, A, R(64) ); + P( A, B, C, D, E, R(65) ); + P( E, A, B, C, D, R(66) ); + P( D, E, A, B, C, R(67) ); + P( C, D, E, A, B, R(68) ); + P( B, C, D, E, A, R(69) ); + P( A, B, C, D, E, R(70) ); + P( E, A, B, C, D, R(71) ); + P( D, E, A, B, C, R(72) ); + P( C, D, E, A, B, R(73) ); + P( B, C, D, E, A, R(74) ); + P( A, B, C, D, E, R(75) ); + P( E, A, B, C, D, R(76) ); + P( D, E, A, B, C, R(77) ); + P( C, D, E, A, B, R(78) ); + P( B, C, D, E, A, R(79) ); + +#undef K +#undef F + + ctx->state[0] += A; + ctx->state[1] += B; + ctx->state[2] += C; + ctx->state[3] += D; + ctx->state[4] += E; +} + +/* + * SHA-1 process buffer + */ +void sha1_update( sha1_context *ctx, unsigned char *input, int ilen ) +{ + int fill; + unsigned long left; + + if( ilen <= 0 ) + return; + + left = ctx->total[0] & 0x3F; + fill = 64 - left; + + ctx->total[0] += ilen; + ctx->total[0] &= 0xFFFFFFFF; + + if( ctx->total[0] < (unsigned long) ilen ) + ctx->total[1]++; + + if( left && ilen >= fill ) + { + memcpy( (void *) (ctx->buffer + left), + (void *) input, fill ); + sha1_process( ctx, ctx->buffer ); + input += fill; + ilen -= fill; + left = 0; + } + + while( ilen >= 64 ) + { + sha1_process( ctx, input ); + input += 64; + ilen -= 64; + } + + if( ilen > 0 ) + { + memcpy( (void *) (ctx->buffer + left), + (void *) input, ilen ); + } +} + +static const unsigned char sha1_padding[64] = +{ + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/* + * SHA-1 final digest + */ +void sha1_finish( sha1_context *ctx, unsigned char output[20] ) +{ + unsigned long last, padn; + unsigned long high, low; + unsigned char msglen[8]; + + high = ( ctx->total[0] >> 29 ) + | ( ctx->total[1] << 3 ); + low = ( ctx->total[0] << 3 ); + + PUT_UINT32_BE( high, msglen, 0 ); + PUT_UINT32_BE( low, msglen, 4 ); + + last = ctx->total[0] & 0x3F; + padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last ); + + sha1_update( ctx, (unsigned char *) sha1_padding, padn ); + sha1_update( ctx, msglen, 8 ); + + PUT_UINT32_BE( ctx->state[0], output, 0 ); + PUT_UINT32_BE( ctx->state[1], output, 4 ); + PUT_UINT32_BE( ctx->state[2], output, 8 ); + PUT_UINT32_BE( ctx->state[3], output, 12 ); + PUT_UINT32_BE( ctx->state[4], output, 16 ); +} + +/* + * Output = SHA-1( input buffer ) + */ +void sha1_csum( unsigned char *input, int ilen, + unsigned char output[20] ) +{ + sha1_context ctx; + + sha1_starts( &ctx ); + sha1_update( &ctx, input, ilen ); + sha1_finish( &ctx, output ); +} + +/* + * Output = HMAC-SHA-1( input buffer, hmac key ) + */ +void sha1_hmac( unsigned char *key, int keylen, + unsigned char *input, int ilen, + unsigned char output[20] ) +{ + int i; + sha1_context ctx; + unsigned char k_ipad[64]; + unsigned char k_opad[64]; + unsigned char tmpbuf[20]; + + memset( k_ipad, 0x36, 64 ); + memset( k_opad, 0x5C, 64 ); + + for( i = 0; i < keylen; i++ ) + { + if( i >= 64 ) break; + + k_ipad[i] ^= key[i]; + k_opad[i] ^= key[i]; + } + + sha1_starts( &ctx ); + sha1_update( &ctx, k_ipad, 64 ); + sha1_update( &ctx, input, ilen ); + sha1_finish( &ctx, tmpbuf ); + + sha1_starts( &ctx ); + sha1_update( &ctx, k_opad, 64 ); + sha1_update( &ctx, tmpbuf, 20 ); + sha1_finish( &ctx, output ); + + memset( k_ipad, 0, 64 ); + memset( k_opad, 0, 64 ); + memset( tmpbuf, 0, 20 ); + memset( &ctx, 0, sizeof( sha1_context ) ); +} + +static const char _sha1_src[] = "_sha1_src"; + +#ifdef SELF_TEST +/* + * FIPS-180-1 test vectors + */ +static const char sha1_test_str[3][57] = +{ + { "abc" }, + { "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" }, + { "" } +}; + +static const unsigned char sha1_test_sum[3][20] = +{ + { 0xA9, 0x99, 0x3E, 0x36, 0x47, 0x06, 0x81, 0x6A, 0xBA, 0x3E, + 0x25, 0x71, 0x78, 0x50, 0xC2, 0x6C, 0x9C, 0xD0, 0xD8, 0x9D }, + { 0x84, 0x98, 0x3E, 0x44, 0x1C, 0x3B, 0xD2, 0x6E, 0xBA, 0xAE, + 0x4A, 0xA1, 0xF9, 0x51, 0x29, 0xE5, 0xE5, 0x46, 0x70, 0xF1 }, + { 0x34, 0xAA, 0x97, 0x3C, 0xD4, 0xC4, 0xDA, 0xA4, 0xF6, 0x1E, + 0xEB, 0x2B, 0xDB, 0xAD, 0x27, 0x31, 0x65, 0x34, 0x01, 0x6F } +}; + +/* + * Checkup routine + */ +int sha1_self_test( void ) +{ + int i, j; + unsigned char buf[1000]; + unsigned char sha1sum[20]; + sha1_context ctx; + + for( i = 0; i < 3; i++ ) + { + printf( " SHA-1 test #%d: ", i + 1 ); + + sha1_starts( &ctx ); + + if( i < 2 ) + sha1_update( &ctx, (unsigned char *) sha1_test_str[i], + strlen( sha1_test_str[i] ) ); + else + { + memset( buf, 'a', 1000 ); + for( j = 0; j < 1000; j++ ) + sha1_update( &ctx, buf, 1000 ); + } + + sha1_finish( &ctx, sha1sum ); + + if( memcmp( sha1sum, sha1_test_sum[i], 20 ) != 0 ) + { + printf( "failed\n" ); + return( 1 ); + } + + printf( "passed\n" ); + } + + printf( "\n" ); + return( 0 ); +} +#else +int sha1_self_test( void ) +{ + return( 0 ); +} +#endif diff --git a/lib_ppc/board.c b/lib_ppc/board.c index c4fc5805ab6..f5d18fa9f6b 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -896,7 +896,8 @@ void board_init_r (gd_t *id, ulong dest_addr) #if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \ defined(CONFIG_TQM8272) || \ - defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) + defined(CONFIG_CCM) || defined(CONFIG_KUP4K) || \ + defined(CONFIG_KUP4X) || defined(CONFIG_PCS440EP) load_sernum_ethaddr (); #endif /* IP Address */ @@ -961,7 +962,7 @@ void board_init_r (gd_t *id, ulong dest_addr) serial_buffered_init(); #endif -#ifdef CONFIG_STATUS_LED +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); #endif diff --git a/net/eth.c b/net/eth.c index 0fc22115dc2..35e1ae95876 100644 --- a/net/eth.c +++ b/net/eth.c @@ -28,6 +28,14 @@ #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) +#if defined(CONFIG_SHOW_BOOT_PROGRESS) +# include +extern void show_ethcfg_progress (int arg); +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress (arg) +#else +# define SHOW_BOOT_PROGRESS(arg) +#endif + #ifdef CFG_GT_6426x extern int gt6426x_eth_initialize(bd_t *bis); #endif @@ -142,6 +150,7 @@ int eth_initialize(bd_t *bis) eth_devices = NULL; eth_current = NULL; + SHOW_BOOT_PROGRESS(64); #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_init(); #endif @@ -270,10 +279,12 @@ int eth_initialize(bd_t *bis) if (!eth_devices) { puts ("No ethernet found.\n"); + SHOW_BOOT_PROGRESS(-64); } else { struct eth_device *dev = eth_devices; char *ethprime = getenv ("ethprime"); + SHOW_BOOT_PROGRESS(65); do { if (eth_number) puts (", "); diff --git a/tools/Makefile b/tools/Makefile index 6177f902716..7980f6c26ee 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -21,10 +21,10 @@ # MA 02111-1307 USA # -BIN_FILES = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) +BIN_FILES = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) ubsha1$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) -OBJ_LINKS = environment.o crc32.o -OBJ_FILES = img2srec.o mkimage.o envcrc.o gen_eth_addr.o bmp_logo.o +OBJ_LINKS = environment.o crc32.o sha1.o +OBJ_FILES = img2srec.o mkimage.o envcrc.o ubsha1.o gen_eth_addr.o bmp_logo.o ifeq ($(ARCH),mips) BIN_FILES += inca-swap-bytes$(SFX) @@ -126,14 +126,17 @@ MAKEDEPEND = makedepend all: $(obj).depend $(BINS) $(LOGO_H) subdirs -$(obj)envcrc$(SFX): $(obj)envcrc.o $(obj)crc32.o $(obj)environment.o +$(obj)envcrc$(SFX): $(obj)envcrc.o $(obj)crc32.o $(obj)environment.o $(obj)sha1.o + $(CC) $(CFLAGS) -o $@ $^ + +$(obj)ubsha1$(SFX): $(obj)ubsha1.o $(obj)sha1.o $(CC) $(CFLAGS) -o $@ $^ $(obj)img2srec$(SFX): $(obj)img2srec.o $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(STRIP) $@ -$(obj)mkimage$(SFX): $(obj)mkimage.o $(obj)crc32.o +$(obj)mkimage$(SFX): $(obj)mkimage.o $(obj)crc32.o $(obj)sha1.o $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(STRIP) $@ @@ -160,9 +163,15 @@ $(obj)mpc86x_clk$(SFX): $(obj)mpc86x_clk.o $(obj)envcrc.o: $(src)envcrc.c $(CC) -g $(CFLAGS) -c -o $@ $< +$(obj)ubsha1.o: $(src)ubsha1.c + $(CC) -g $(CFLAGS) -c -o $@ $< + $(obj)crc32.o: $(obj)crc32.c $(CC) -g $(CFLAGS) -c -o $@ $< +$(obj)sha1.o: $(obj)sha1.c + $(CC) -g $(CFLAGS) -c -o $@ $< + $(obj)mkimage.o: $(src)mkimage.c $(CC) -g $(CFLAGS) -c -o $@ $< @@ -203,6 +212,10 @@ $(obj)crc32.c: @rm -f $(obj)crc32.c ln -s $(src)../lib_generic/crc32.c $(obj)crc32.c +$(obj)sha1.c: + @rm -f $(obj)sha1.c + ln -s $(src)../lib_generic/sha1.c $(obj)sha1.c + $(LOGO_H): $(obj)bmp_logo $(LOGO_BMP) $(obj)./bmp_logo $(LOGO_BMP) >$@ diff --git a/tools/ubsha1.c b/tools/ubsha1.c new file mode 100644 index 00000000000..bc877606d2f --- /dev/null +++ b/tools/ubsha1.c @@ -0,0 +1,119 @@ +/* + * (C) Copyright 2007 + * Heiko Schocher, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "sha1.h" + +#ifndef __ASSEMBLY__ +#define __ASSEMBLY__ /* Dirty trick to get only #defines */ +#endif +#include +#undef __ASSEMBLY__ + +#ifndef O_BINARY /* should be define'd on __WIN32__ */ +#define O_BINARY 0 +#endif + +#ifndef MAP_FAILED +#define MAP_FAILED (-1) +#endif + +extern int errno; + +extern void sha1_csum (unsigned char *input, int ilen, unsigned char output[20]); + +int main (int argc, char **argv) +{ + unsigned char output[20]; + int i, len; + + char *imagefile; + char *cmdname = *argv; + unsigned char *ptr; + unsigned char *data; + struct stat sbuf; + unsigned char *ptroff; + int ifd; + int off; + + if (argc > 1) { + imagefile = argv[1]; + ifd = open (imagefile, O_RDWR|O_BINARY); + if (ifd < 0) { + fprintf (stderr, "%s: Can't open %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + if (fstat (ifd, &sbuf) < 0) { + fprintf (stderr, "%s: Can't stat %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + len = sbuf.st_size; + ptr = (unsigned char *)mmap(0, len, + PROT_READ, MAP_SHARED, ifd, 0); + if (ptr == (unsigned char *)MAP_FAILED) { + fprintf (stderr, "%s: Can't read %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + /* create a copy, so we can blank out the sha1 sum */ + data = malloc (len); + memcpy (data, ptr, len); + off = SHA1_SUM_POS; + ptroff = &data[len + off]; + for (i = 0; i < SHA1_SUM_LEN; i++) { + ptroff[i] = 0; + } + + sha1_csum ((unsigned char *) data, len, (unsigned char *)output); + + printf ("U-Boot sum:\n"); + for (i = 0; i < 20 ; i++) + { + printf ("%02X ", output[i]); + } + printf ("\n"); + /* overwrite the sum in the bin file, with the actual */ + lseek (ifd, SHA1_SUM_POS, SEEK_END); + if (write (ifd, output, SHA1_SUM_LEN) != SHA1_SUM_LEN) { + fprintf (stderr, "%s: Can't write %s: %s\n", + cmdname, imagefile, strerror(errno)); + exit (EXIT_FAILURE); + } + + free (data); + (void) munmap((void *)ptr, len); + (void) close (ifd); + } + + return EXIT_SUCCESS; +} -- cgit v1.3.1 From a11e06965ec91270c51853407ff1261d3c740386 Mon Sep 17 00:00:00 2001 From: Igor Lisitsin Date: Wed, 28 Mar 2007 19:06:19 +0400 Subject: Extend POST support for PPC440 Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin -- --- board/amcc/sequoia/sequoia.c | 10 ++ cpu/ppc4xx/cpu_init.c | 2 + include/configs/sequoia.h | 15 ++- include/post.h | 1 + include/ppc440.h | 50 +++++----- post/cpu/ppc4xx/Makefile | 28 ++++++ post/cpu/ppc4xx/fpu.c | 55 +++++++++++ post/cpu/ppc4xx/spr.c | 176 +++++++++++++++++++++++++++++++++++ post/cpu/ppc4xx/uart.c | 214 +++++++++++++++++++++++++++++++++++++++++++ post/cpu/ppc4xx/watchdog.c | 68 ++++++++++++++ post/lib_ppc/asm.S | 12 +++ post/lib_ppc/b.c | 8 +- post/post.c | 2 +- post/tests.c | 14 +++ 14 files changed, 625 insertions(+), 30 deletions(-) create mode 100644 post/cpu/ppc4xx/Makefile create mode 100644 post/cpu/ppc4xx/fpu.c create mode 100644 post/cpu/ppc4xx/spr.c create mode 100644 post/cpu/ppc4xx/uart.c create mode 100644 post/cpu/ppc4xx/watchdog.c (limited to 'include') diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index ba365aea318..b49179ba0d7 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -586,3 +586,13 @@ int is_pci_host(struct pci_controller *hose) return (1); } #endif /* defined(CONFIG_PCI) */ +#if defined(CONFIG_POST) +/* + * Returns 1 if keys pressed to start the power-on long-running tests + * Called from board_init_f(). + */ +int post_hotkeys_pressed(void) +{ + return 0; /* No hotkeys supported */ +} +#endif /* CONFIG_POST */ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 66e86372603..bc1ae0e4e74 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -211,6 +211,8 @@ cpu_init_f (void) val = mfspr(tcr); #if defined(CONFIG_440EP) || defined(CONFIG_440GR) val |= 0xb8000000; /* generate system reset after 1.34 seconds */ +#elif defined(CONFIG_440EPX) + val |= 0xb0000000; /* generate system reset after 1.34 seconds */ #else val |= 0xf0000000; /* generate system reset after 2.684 seconds */ #endif diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 42b42fc57f3..ae1c129109f 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -59,6 +59,7 @@ #define CFG_MONITOR_BASE TEXT_BASE #define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ #define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_OCM_DATA_ADDR CFG_OCM_BASE #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 @@ -81,7 +82,7 @@ #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR /*----------------------------------------------------------------------- * Serial Port @@ -328,6 +329,18 @@ CFG_CMD_SDRAM | \ CMD_USB) +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_I2C | \ + CFG_POST_SPR) + +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CONFIG_LOGBUFFER + +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + #define CONFIG_SUPPORT_VFAT /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ diff --git a/include/post.h b/include/post.h index cdefbddb6f5..8259e5d2ea6 100644 --- a/include/post.h +++ b/include/post.h @@ -91,6 +91,7 @@ extern int post_hotkeys_pressed(void); #define CFG_POST_SYSMON 0x00000800 #define CFG_POST_DSP 0x00001000 #define CFG_POST_CODEC 0x00002000 +#define CFG_POST_FPU 0x00004000 #endif /* CONFIG_POST */ diff --git a/include/ppc440.h b/include/ppc440.h index 09f843041da..9ba47a53cf5 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -282,6 +282,32 @@ #define sdr_sdstp3 0x4003 #endif /* CONFIG_440GX */ +#ifdef CONFIG_440 +/*----------------------------------------------------------------------------+ +| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). ++----------------------------------------------------------------------------*/ +#define CCR0_PRE 0x40000000 +#define CCR0_CRPE 0x08000000 +#define CCR0_DSTG 0x00200000 +#define CCR0_DAPUIB 0x00100000 +#define CCR0_DTB 0x00008000 +#define CCR0_GICBT 0x00004000 +#define CCR0_GDCBT 0x00002000 +#define CCR0_FLSTA 0x00000100 +#define CCR0_ICSLC_MASK 0x0000000C +#define CCR0_ICSLT_MASK 0x00000003 +#define CCR1_TCS_MASK 0x00000080 +#define CCR1_TCS_INTCLK 0x00000000 +#define CCR1_TCS_EXTCLK 0x00000080 +#define MMUCR_SWOA 0x01000000 +#define MMUCR_U1TE 0x00400000 +#define MMUCR_U2SWOAE 0x00200000 +#define MMUCR_DULXE 0x00800000 +#define MMUCR_IULXE 0x00400000 +#define MMUCR_STS 0x00100000 +#define MMUCR_STID_MASK 0x000000FF +#endif /* CONFIG_440 */ + #ifdef CONFIG_440SPE #undef sdr_sdstp2 #define sdr_sdstp2 0x0022 @@ -307,30 +333,6 @@ #define sdr_sdstp6 0x4005 #define sdr_sdstp7 0x4007 -/*----------------------------------------------------------------------------+ -| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). -+----------------------------------------------------------------------------*/ -#define CCR0_PRE 0x40000000 -#define CCR0_CRPE 0x08000000 -#define CCR0_DSTG 0x00200000 -#define CCR0_DAPUIB 0x00100000 -#define CCR0_DTB 0x00008000 -#define CCR0_GICBT 0x00004000 -#define CCR0_GDCBT 0x00002000 -#define CCR0_FLSTA 0x00000100 -#define CCR0_ICSLC_MASK 0x0000000C -#define CCR0_ICSLT_MASK 0x00000003 -#define CCR1_TCS_MASK 0x00000080 -#define CCR1_TCS_INTCLK 0x00000000 -#define CCR1_TCS_EXTCLK 0x00000080 -#define MMUCR_SEOA 0x01000000 -#define MMUCR_U1TE 0x00400000 -#define MMUCR_U2SWOAE 0x00200000 -#define MMUCR_DULXE 0x00800000 -#define MMUCR_IULXE 0x00400000 -#define MMUCR_STS 0x00100000 -#define MMUCR_STID_MASK 0x000000FF - #define SDR0_CFGADDR 0x00E #define SDR0_CFGDATA 0x00F diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile new file mode 100644 index 00000000000..8e8ab50577a --- /dev/null +++ b/post/cpu/ppc4xx/Makefile @@ -0,0 +1,28 @@ +# +# (C) Copyright 2002-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +LIB = libpostppc4xx.a + +COBJS = fpu.o spr.o uart.o watchdog.o + +include $(TOPDIR)/post/rules.mk diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c new file mode 100644 index 00000000000..1935c011ba7 --- /dev/null +++ b/post/cpu/ppc4xx/fpu.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2007 Wolfgang Denk + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_POST +#if defined(CONFIG_440EP) || \ + defined(CONFIG_440EPX) + +#include +#include + + +int fpu_status(void) +{ + if (mfspr(ccr0) & CCR0_DAPUIB) + return 0; /* Disabled */ + else + return 1; /* Enabled */ +} + + +void fpu_disable(void) +{ + mtspr(ccr0, mfspr(ccr0) | CCR0_DAPUIB); + mtmsr(mfmsr() & ~MSR_FP); +} + + +void fpu_enable(void) +{ + mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB); + mtmsr(mfmsr() | MSR_FP); +} +#endif +#endif diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c new file mode 100644 index 00000000000..f62526a1716 --- /dev/null +++ b/post/cpu/ppc4xx/spr.c @@ -0,0 +1,176 @@ +/* + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * SPR test + * + * The test checks the contents of Special Purpose Registers (SPR) listed + * in the spr_test_list array below. + * Each SPR value is read using mfspr instruction, some bits are masked + * according to the table and the resulting value is compared to the + * corresponding table value. + */ + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_SPR + +static struct +{ + int number; + char * name; + unsigned long mask; + unsigned long value; +} spr_test_list [] = { + /* Standard Special-Purpose Registers */ + + {0x001, "XER", 0x00000000, 0x00000000}, + {0x008, "LR", 0x00000000, 0x00000000}, + {0x009, "CTR", 0x00000000, 0x00000000}, + {0x016, "DEC", 0x00000000, 0x00000000}, + {0x01a, "SRR0", 0x00000000, 0x00000000}, + {0x01b, "SRR1", 0x00000000, 0x00000000}, + {0x110, "SPRG0", 0x00000000, 0x00000000}, + {0x111, "SPRG1", 0x00000000, 0x00000000}, + {0x112, "SPRG2", 0x00000000, 0x00000000}, + {0x113, "SPRG3", 0x00000000, 0x00000000}, + {0x11f, "PVR", 0x00000000, 0x00000000}, + + /* Additional Special-Purpose Registers */ + + {0x30, "PID", 0x00000000, 0x00000000}, + {0x3a, "CSRR0", 0x00000000, 0x00000000}, + {0x3b, "CSRR1", 0x00000000, 0x00000000}, + {0x3d, "DEAR", 0x00000000, 0x00000000}, + {0x3e, "ESR", 0x00000000, 0x00000000}, + {0x3f, "IVPR", 0xffff0000, 0x00000000}, + {0x100, "USPRG0", 0x00000000, 0x00000000}, + {0x104, "SPRG4", 0x00000000, 0x00000000}, + {0x105, "SPRG5", 0x00000000, 0x00000000}, + {0x106, "SPRG6", 0x00000000, 0x00000000}, + {0x107, "SPRG7", 0x00000000, 0x00000000}, + {0x10c, "TBL", 0x00000000, 0x00000000}, + {0x10d, "TBU", 0x00000000, 0x00000000}, + {0x11e, "PIR", 0x0000000f, 0x00000000}, + {0x130, "DBSR", 0x00000000, 0x00000000}, + {0x134, "DBCR0", 0x00000000, 0x00000000}, + {0x135, "DBCR1", 0x00000000, 0x00000000}, + {0x136, "DBCR2", 0x00000000, 0x00000000}, + {0x138, "IAC1", 0x00000000, 0x00000000}, + {0x139, "IAC2", 0x00000000, 0x00000000}, + {0x13a, "IAC3", 0x00000000, 0x00000000}, + {0x13b, "IAC4", 0x00000000, 0x00000000}, + {0x13c, "DAC1", 0x00000000, 0x00000000}, + {0x13d, "DAC2", 0x00000000, 0x00000000}, + {0x13e, "DVC1", 0x00000000, 0x00000000}, + {0x13f, "DVC2", 0x00000000, 0x00000000}, + {0x150, "TSR", 0x00000000, 0x00000000}, + {0x154, "TCR", 0x00000000, 0x00000000}, + {0x190, "IVOR0", 0x00000000, 0x00000000}, + {0x191, "IVOR1", 0x00000000, 0x00000000}, + {0x192, "IVOR2", 0x00000000, 0x00000000}, + {0x193, "IVOR3", 0x00000000, 0x00000000}, + {0x194, "IVOR4", 0x00000000, 0x00000000}, + {0x195, "IVOR5", 0x00000000, 0x00000000}, + {0x196, "IVOR6", 0x00000000, 0x00000000}, + {0x197, "IVOR7", 0x00000000, 0x00000000}, + {0x198, "IVOR8", 0x00000000, 0x00000000}, + {0x199, "IVOR9", 0x00000000, 0x00000000}, + {0x19a, "IVOR10", 0x00000000, 0x00000000}, + {0x19b, "IVOR11", 0x00000000, 0x00000000}, + {0x19c, "IVOR12", 0x00000000, 0x00000000}, + {0x19d, "IVOR13", 0x00000000, 0x00000000}, + {0x19e, "IVOR14", 0x00000000, 0x00000000}, + {0x19f, "IVOR15", 0x00000000, 0x00000000}, + {0x23a, "MCSRR0", 0x00000000, 0x00000000}, + {0x23b, "MCSRR1", 0x00000000, 0x00000000}, + {0x23c, "MCSR", 0x00000000, 0x00000000}, + {0x370, "INV0", 0x00000000, 0x00000000}, + {0x371, "INV1", 0x00000000, 0x00000000}, + {0x372, "INV2", 0x00000000, 0x00000000}, + {0x373, "INV3", 0x00000000, 0x00000000}, + {0x374, "ITV0", 0x00000000, 0x00000000}, + {0x375, "ITV1", 0x00000000, 0x00000000}, + {0x376, "ITV2", 0x00000000, 0x00000000}, + {0x377, "ITV3", 0x00000000, 0x00000000}, + {0x378, "CCR1", 0x00000000, 0x00000000}, + {0x390, "DNV0", 0x00000000, 0x00000000}, + {0x391, "DNV1", 0x00000000, 0x00000000}, + {0x392, "DNV2", 0x00000000, 0x00000000}, + {0x393, "DNV3", 0x00000000, 0x00000000}, + {0x394, "DTV0", 0x00000000, 0x00000000}, + {0x395, "DTV1", 0x00000000, 0x00000000}, + {0x396, "DTV2", 0x00000000, 0x00000000}, + {0x397, "DTV3", 0x00000000, 0x00000000}, + {0x398, "DVLIM", 0x00000000, 0x00000000}, + {0x399, "IVLIM", 0x00000000, 0x00000000}, + {0x39b, "RSTCFG", 0x00000000, 0x00000000}, + {0x39c, "DCDBTRL", 0x00000000, 0x00000000}, + {0x39d, "DCDBTRH", 0x00000000, 0x00000000}, + {0x39e, "ICDBTRL", 0x00000000, 0x00000000}, + {0x39f, "ICDBTRH", 0x00000000, 0x00000000}, + {0x3b2, "MMUCR", 0x00000000, 0x00000000}, + {0x3b3, "CCR0", 0x00000000, 0x00000000}, + {0x3d3, "ICDBDR", 0x00000000, 0x00000000}, + {0x3f3, "DBDR", 0x00000000, 0x00000000}, +}; + +static int spr_test_list_size = + sizeof (spr_test_list) / sizeof (spr_test_list[0]); + +int spr_post_test (int flags) +{ + int ret = 0; + int i; + + unsigned long code[] = { + 0x7c6002a6, /* mfspr r3,SPR */ + 0x4e800020 /* blr */ + }; + unsigned long (*get_spr) (void) = (void *) code; + + for (i = 0; i < spr_test_list_size; i++) { + int num = spr_test_list[i].number; + + /* mfspr r3,num */ + code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6); + + asm volatile ("isync"); + + if ((get_spr () & spr_test_list[i].mask) != + (spr_test_list[i].value & spr_test_list[i].mask)) { + post_log ("The value of %s special register " + "is incorrect: 0x%08X\n", + spr_test_list[i].name, get_spr ()); + ret = -1; + } + } + + return ret; +} +#endif /* CONFIG_POST & CFG_POST_SPR */ +#endif /* CONFIG_POST */ diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c new file mode 100644 index 00000000000..f220dba17ab --- /dev/null +++ b/post/cpu/ppc4xx/uart.c @@ -0,0 +1,214 @@ +/* + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * UART test + * + * The controllers are configured to loopback mode and several + * characters are transmitted. + */ + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_UART + +#include +#include + +#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300 +#define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400 +#define UART2_BASE CFG_PERIPHERAL_BASE + 0x00000500 +#define UART3_BASE CFG_PERIPHERAL_BASE + 0x00000600 + +#define CR0_MASK 0xdfffffff +#define CR0_EXTCLK_ENA 0x00800000 +#define CR0_UDIV_POS 0 +#define UDIV_SUBTRACT 0 +#define UART0_SDR sdr_uart0 +#define UART1_SDR sdr_uart1 +#define UART2_SDR sdr_uart2 +#define UART3_SDR sdr_uart3 +#define MFREG(a, d) mfsdr(a, d) +#define MTREG(a, d) mtsdr(a, d) + +#define UART_RBR 0x00 +#define UART_THR 0x00 +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 +#define UART_DLL 0x00 +#define UART_DLM 0x01 + +/* + Line Status Register. +*/ +#define asyncLSRDataReady1 0x01 +#define asyncLSROverrunError1 0x02 +#define asyncLSRParityError1 0x04 +#define asyncLSRFramingError1 0x08 +#define asyncLSRBreakInterrupt1 0x10 +#define asyncLSRTxHoldEmpty1 0x20 +#define asyncLSRTxShiftEmpty1 0x40 +#define asyncLSRRxFifoError1 0x80 + +DECLARE_GLOBAL_DATA_PTR; + +static int uart_post_init (unsigned long dev_base) +{ + unsigned long reg; + unsigned long udiv; + unsigned short bdiv; + volatile char val; +#ifdef CFG_EXT_SERIAL_CLOCK + unsigned long tmp; +#endif + int i; + + for (i = 0; i < 3500; i++) { + if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1) + break; + udelay (100); + } + MFREG(UART0_SDR, reg); + reg &= ~CR0_MASK; + +#ifdef CFG_EXT_SERIAL_CLOCK + reg |= CR0_EXTCLK_ENA; + udiv = 1; + tmp = gd->baudrate * 16; + bdiv = (CFG_EXT_SERIAL_CLOCK + tmp / 2) / tmp; +#else + /* For 440, the cpu clock is on divider chain A, UART on divider + * chain B ... so cpu clock is irrelevant. Get the "optimized" + * values that are subject to the 1/2 opb clock constraint + */ + serial_divs (gd->baudrate, &udiv, &bdiv); +#endif + + reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ + + /* + * Configure input clock to baudrate generator for all + * available serial ports here + */ + MTREG(UART0_SDR, reg); +#if defined(UART1_SDR) + MTREG(UART1_SDR, reg); +#endif +#if defined(UART2_SDR) + MTREG(UART2_SDR, reg); +#endif +#if defined(UART3_SDR) + MTREG(UART3_SDR, reg); +#endif + + out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */ + out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */ + out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ + out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out8(dev_base + UART_FCR, 0x00); /* disable FIFO */ + out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */ + val = in8(dev_base + UART_LSR); /* clear line status */ + val = in8(dev_base + UART_RBR); /* read receive buffer */ + out8(dev_base + UART_SCR, 0x00); /* set scratchpad */ + out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */ + + return 0; +} + +static void uart_post_putc (unsigned long dev_base, char c) +{ + int i; + + out8 (dev_base + UART_THR, c); /* put character out */ + + /* Wait for transfer completion */ + for (i = 0; i < 3500; i++) { + if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1) + break; + udelay (100); + } +} + +static int uart_post_getc (unsigned long dev_base) +{ + int i; + + /* Wait for character available */ + for (i = 0; i < 3500; i++) { + if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1) + break; + udelay (100); + } + return 0xff & in8 (dev_base + UART_RBR); +} + +static int test_ctlr (unsigned long dev_base, int index) +{ + int res = -1; + char test_str[] = "*** UART Test String ***\r\n"; + int i; + + uart_post_init (dev_base); + + for (i = 0; i < sizeof (test_str) - 1; i++) { + uart_post_putc (dev_base, test_str[i]); + if (uart_post_getc (dev_base) != test_str[i]) + goto done; + } + res = 0; +done: + if (res) + post_log ("uart%d test failed\n", index); + + return res; +} + +int uart_post_test (int flags) +{ + int i, res = 0; + static unsigned long base[] = { + UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE + }; + + for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) { + if (test_ctlr (base[i], i)) + res = -1; + } + serial_reinit_all (); + + return res; +} + +#endif /* CONFIG_POST & CFG_POST_UART */ + +#endif /* CONFIG_POST */ diff --git a/post/cpu/ppc4xx/watchdog.c b/post/cpu/ppc4xx/watchdog.c new file mode 100644 index 00000000000..3c76cfd3484 --- /dev/null +++ b/post/cpu/ppc4xx/watchdog.c @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * Watchdog test + * + * The test verifies the watchdog timer operation. + * On the first iteration, the test routine disables interrupts and + * makes a 10-second delay. If the system does not reboot during this delay, + * the watchdog timer is not operational and the test fails. If the system + * reboots, on the second iteration the test routine reports a success. + */ + +#ifdef CONFIG_POST + +#include +#include + +#if CONFIG_POST & CFG_POST_WATCHDOG + +int watchdog_post_test (int flags) +{ + if (flags & POST_REBOOT) { + /* Test passed */ + + return 0; + } else { + /* 10-second delay */ + int ints = disable_interrupts (); + ulong base = post_time_ms (0); + + while (post_time_ms (base) < 10000) + ; + if (ints) + enable_interrupts (); + + /* + * If we have reached this point, the watchdog timer + * does not work + */ + return -1; + } +} + +#endif /* CONFIG_POST & CFG_POST_WATCHDOG */ +#endif /* CONFIG_POST */ diff --git a/post/lib_ppc/asm.S b/post/lib_ppc/asm.S index a0815a43a77..5e72b3418f5 100644 --- a/post/lib_ppc/asm.S +++ b/post/lib_ppc/asm.S @@ -34,6 +34,7 @@ /* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */ .global cpu_post_exec_02 cpu_post_exec_02: + isync mflr r0 stwu r0, -4(r1) @@ -56,6 +57,7 @@ cpu_post_exec_02: /* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */ .global cpu_post_exec_04 cpu_post_exec_04: + isync mflr r0 stwu r0, -4(r1) @@ -80,6 +82,7 @@ cpu_post_exec_04: /* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */ .global cpu_post_exec_12 cpu_post_exec_12: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -100,6 +103,7 @@ cpu_post_exec_12: /* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */ .global cpu_post_exec_11 cpu_post_exec_11: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -119,6 +123,7 @@ cpu_post_exec_11: /* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */ .global cpu_post_exec_21 cpu_post_exec_21: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -148,6 +153,7 @@ cpu_post_exec_21: ulong op2); */ .global cpu_post_exec_22 cpu_post_exec_22: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -177,6 +183,7 @@ cpu_post_exec_22: /* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */ .global cpu_post_exec_12w cpu_post_exec_12w: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -198,6 +205,7 @@ cpu_post_exec_12w: /* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */ .global cpu_post_exec_11w cpu_post_exec_11w: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -218,6 +226,7 @@ cpu_post_exec_11w: /* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */ .global cpu_post_exec_22w cpu_post_exec_22w: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -241,6 +250,7 @@ cpu_post_exec_22w: /* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */ .global cpu_post_exec_21w cpu_post_exec_21w: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -263,6 +273,7 @@ cpu_post_exec_21w: /* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */ .global cpu_post_exec_21x cpu_post_exec_21x: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) @@ -286,6 +297,7 @@ cpu_post_exec_21x: ulong cr); */ .global cpu_post_exec_31 cpu_post_exec_31: + isync mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) diff --git a/post/lib_ppc/b.c b/post/lib_ppc/b.c index b4b17c8ff07..6e276c48d5c 100644 --- a/post/lib_ppc/b.c +++ b/post/lib_ppc/b.c @@ -49,7 +49,7 @@ extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, ulong cr); static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi, - int pjump, int dec, int link, ulong pctr, ulong cr) + int pjump, int decr, int link, ulong pctr, ulong cr) { int ret = 0; ulong lr = 0; @@ -77,7 +77,7 @@ static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi, ret = pjump == jump ? 0 : -1; if (ret == 0) { - if (dec) + if (decr) ret = pctr == ctr + 1 ? 0 : -1; else ret = pctr == ctr ? 0 : -1; @@ -163,7 +163,7 @@ int cpu_post_test_b (void) { for (ctr = 1; ctr <= 2 && ret == 0; ctr++) { - int dec = cd < 2; + int decr = cd < 2; int cr = cond ? 0x80000000 : 0x00000000; int jumpc = cc >= 2 || (cc == 0 && !cond) || @@ -174,7 +174,7 @@ int cpu_post_test_b (void) int jump = jumpc && jumpd; ret = cpu_post_test_bc (link ? OP_BCL : OP_BC, - (cc << 3) + (cd << 1), 0, jump, dec, link, + (cc << 3) + (cd << 1), 0, jump, decr, link, ctr, cr); if (ret != 0) diff --git a/post/post.c b/post/post.c index ac419908605..28435cc4af8 100644 --- a/post/post.c +++ b/post/post.c @@ -428,7 +428,7 @@ void post_reloc (void) unsigned long post_time_ms (unsigned long base) { #ifdef CONFIG_PPC - return (unsigned long)get_ticks () / (get_tbclk () / CFG_HZ) - base; + return (unsigned long)(get_ticks () / (get_tbclk () / CFG_HZ)) - base; #else #warning "Not implemented yet" return 0; /* Not implemented yet */ diff --git a/post/tests.c b/post/tests.c index 3bccd1a8edd..f3604b24934 100644 --- a/post/tests.c +++ b/post/tests.c @@ -37,6 +37,7 @@ extern int i2c_post_test (int flags); extern int rtc_post_test (int flags); extern int memory_post_test (int flags); extern int cpu_post_test (int flags); +extern int fpu_post_test (int flags); extern int uart_post_test (int flags); extern int ether_post_test (int flags); extern int spi_post_test (int flags); @@ -126,6 +127,19 @@ struct post_test post_list[] = CFG_POST_CPU }, #endif +#if CONFIG_POST & CFG_POST_FPU + { + "FPU test", + "fpu", + "This test verifies the arithmetic logic unit of" + " FPU.", + POST_RAM | POST_ALWAYS, + &fpu_post_test, + NULL, + NULL, + CFG_POST_FPU + }, +#endif #if CONFIG_POST & CFG_POST_UART { "UART test", -- cgit v1.3.1 From 2dc64451b4c08ffd619372abfdc2506a2e2363b9 Mon Sep 17 00:00:00 2001 From: Igor Lisitsin Date: Wed, 18 Apr 2007 14:55:19 +0400 Subject: Adapt log buffer code to support Linux 2.6 A new environment variable, "logversion", selects the log buffer behaviour. If it is not set or set to a value other than 2, then the old, Linux 2.4.4, behaviour is selected. Signed-off-by: Igor Lisitsin -- --- common/cmd_log.c | 116 +++++++++++++++++++++++++++++++++--------------------- include/logbuff.h | 26 +++++++++++- 2 files changed, 96 insertions(+), 46 deletions(-) (limited to 'include') diff --git a/common/cmd_log.c b/common/cmd_log.c index 042a403026f..5bf811e7558 100644 --- a/common/cmd_log.c +++ b/common/cmd_log.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2002-2007 * Detlev Zundel, DENX Software Engineering, dzu@denx.de. * * Code used from linux/kernel/printk.c @@ -60,45 +60,40 @@ static char buf[1024]; /* This combination will not print messages with the default loglevel */ static unsigned console_loglevel = 3; static unsigned default_message_loglevel = 4; -static unsigned char *log_buf = NULL; -static unsigned long *ext_log_size; -static unsigned long *ext_log_start; -static unsigned long *ext_logged_chars; -#define log_size (*ext_log_size) -#define log_start (*ext_log_start) -#define logged_chars (*ext_logged_chars) +static unsigned log_version = 1; +static logbuff_t *log; -/* Forced by code, eh! */ -#define LOGBUFF_MAGIC 0xc0de4ced - -/* The mapping used here has to be the same as in setup_ext_logbuff () - in linux/kernel/printk */ void logbuff_init_ptrs (void) { - unsigned long *ext_tag; - unsigned long post_word; + unsigned long tag, post_word; char *s; - log_buf = (unsigned char *)(gd->bd->bi_memsize-LOGBUFF_LEN); - ext_tag = (unsigned long *)(log_buf)-4; - ext_log_start = (unsigned long *)(log_buf)-3; - ext_log_size = (unsigned long *)(log_buf)-2; - ext_logged_chars = (unsigned long *)(log_buf)-1; + log = (logbuff_t *)(gd->bd->bi_memsize-LOGBUFF_LEN) - 1; + + /* Set up log version */ + if ((s = getenv ("logversion")) != NULL) + log_version = (int)simple_strtoul (s, NULL, 10); + + if (log_version == 2) + tag = log->v2.tag; + else + tag = log->v1.tag; post_word = post_word_load(); #ifdef CONFIG_POST /* The post routines have setup the word so we can simply test it */ - if (post_word_load () & POST_COLDBOOT) { - logged_chars = log_size = log_start = 0; - *ext_tag = LOGBUFF_MAGIC; + if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT)) { + logbuff_reset (); } #else /* No post routines, so we do our own checking */ - if (post_word != LOGBUFF_MAGIC) { - logged_chars = log_size = log_start = 0; + if (tag != LOGBUFF_MAGIC || post_word != LOGBUFF_MAGIC) { + logbuff_reset (); post_word_store (LOGBUFF_MAGIC); - *ext_tag = LOGBUFF_MAGIC; } #endif + if (log_version == 2 && (long)log->v2.start > (long)log->v2.con) + log->v2.start = log->v2.con; + /* Initialize default loglevel if present */ if ((s = getenv ("loglevel")) != NULL) console_loglevel = (int)simple_strtoul (s, NULL, 10); @@ -106,6 +101,15 @@ void logbuff_init_ptrs (void) gd->post_log_word |= LOGBUFF_INITIALIZED; } +void logbuff_reset (void) +{ + memset (log, 0, sizeof (logbuff_t)); + if (log_version == 2) + log->v2.tag = LOGBUFF_MAGIC; + else + log->v1.tag = LOGBUFF_MAGIC; +} + int drv_logbuff_init (void) { device_t logdev; @@ -162,7 +166,7 @@ void logbuff_log(char *msg) int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { char *s; - unsigned long i; + unsigned long i, start, size; if (strcmp(argv[1],"append") == 0) { /* Log concatenation of all arguments separated by spaces */ @@ -177,21 +181,34 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) case 2: if (strcmp(argv[1],"show") == 0) { - for (i=0; i < (log_size&LOGBUFF_MASK); i++) { - s = (char *)log_buf+((log_start+i)&LOGBUFF_MASK); + if (log_version == 2) { + start = log->v2.start; + size = log->v2.end - log->v2.start; + } + else { + start = log->v1.start; + size = log->v1.size; + } + for (i=0; i < (size&LOGBUFF_MASK); i++) { + s = (char *)log->buf+((start+i)&LOGBUFF_MASK); putc (*s); } return 0; } else if (strcmp(argv[1],"reset") == 0) { - log_start = 0; - log_size = 0; - logged_chars = 0; + logbuff_reset (); return 0; } else if (strcmp(argv[1],"info") == 0) { - printf ("Logbuffer at %08lx\n", (unsigned long)log_buf); - printf ("log_start = %08lx\n", log_start); - printf ("log_size = %08lx\n", log_size); - printf ("logged_chars = %08lx\n", logged_chars); + printf ("Logbuffer at %08lx\n", (unsigned long)log->buf); + if (log_version == 2) { + printf ("log_start = %08lx\n", log->v2.start); + printf ("log_end = %08lx\n", log->v2.end); + printf ("logged_chars = %08lx\n", log->v2.chars); + } + else { + printf ("log_start = %08lx\n", log->v1.start); + printf ("log_size = %08lx\n", log->v1.size); + printf ("logged_chars = %08lx\n", log->v1.chars); + } return 0; } printf ("Usage:\n%s\n", cmdtp->usage); @@ -202,7 +219,7 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 1; } } -#if defined(CONFIG_LOGBUFFER) + U_BOOT_CMD( log, 255, 1, do_log, "log - manipulate logbuffer\n", @@ -211,7 +228,7 @@ U_BOOT_CMD( "log show - show contents\n" "log append - append to the logbuffer\n" ); -#endif /* CONFIG_LOGBUFFER */ + static int logbuff_printk(const char *line) { int i; @@ -241,13 +258,22 @@ static int logbuff_printk(const char *line) } line_feed = 0; for (; p < buf_end; p++) { - log_buf[(log_start+log_size) & LOGBUFF_MASK] = *p; - if (log_size < LOGBUFF_LEN) - log_size++; - else - log_start++; - - logged_chars++; + if (log_version == 2) { + log->buf[log->v2.end & LOGBUFF_MASK] = *p; + log->v2.end++; + if (log->v2.end - log->v2.start > LOGBUFF_LEN) + log->v2.start++; + log->v2.chars++; + } + else { + log->buf[(log->v1.start + log->v1.size) & + LOGBUFF_MASK] = *p; + if (log->v1.size < LOGBUFF_LEN) + log->v1.size++; + else + log->v1.start++; + log->v1.chars++; + } if (*p == '\n') { line_feed = 1; break; diff --git a/include/logbuff.h b/include/logbuff.h index 3acfc18a782..d4157290538 100644 --- a/include/logbuff.h +++ b/include/logbuff.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2002-2007 * Detlev Zundel, dzu@denx.de. * * See file CREDITS for list of people who contributed to this @@ -25,6 +25,7 @@ #ifdef CONFIG_LOGBUFFER +#define LOGBUFF_MAGIC 0xc0de4ced /* Forced by code, eh! */ #define LOGBUFF_LEN (16384) /* Must be 16k right now */ #define LOGBUFF_MASK (LOGBUFF_LEN-1) #define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */ @@ -32,6 +33,29 @@ #define LOGBUFF_INITIALIZED (1<<31) +/* The mapping used here has to be the same as in setup_ext_logbuff () + in linux/kernel/printk */ + +typedef struct { + union { + struct { + unsigned long tag; + unsigned long start; + unsigned long con; + unsigned long end; + unsigned long chars; + } v2; + struct { + unsigned long dummy; + unsigned long tag; + unsigned long start; + unsigned long size; + unsigned long chars; + } v1; + }; + unsigned char buf[0]; +} logbuff_t; + int drv_logbuff_init (void); void logbuff_init_ptrs (void); void logbuff_log(char *msg); -- cgit v1.3.1 From 1636d1c8529c006d106287cfbc20cd0a246fe1cb Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 22 Jun 2007 23:59:00 +0200 Subject: Coding stylke cleanup; rebuild CHANGELOG --- CHANGELOG | 39 +++++++++++++++++++++++++++++++++ board/amcc/acadia/acadia.c | 14 ++++++------ board/bf537-stamp/ether_bf537.c | 2 +- board/bf537-stamp/flash-defines.h | 6 ++--- board/bf537-stamp/stm_m25p64.c | 2 +- board/bf537-stamp/u-boot.lds.S | 12 +++++----- board/smdk2400/lowlevel_init.S | 2 +- common/cmd_log.c | 4 ++-- common/main.c | 2 +- cpu/mpc5xx/start.S | 2 +- cpu/mpc8260/start.S | 4 ++-- cpu/ppc4xx/44x_spd_ddr.c | 4 ++-- cpu/ppc4xx/44x_spd_ddr2.c | 4 ++-- cpu/ppc4xx/cpu_init.c | 2 +- include/asm-ppc/processor.h | 46 +++++++++++++++++++-------------------- include/configs/TQM5200.h | 4 ++-- include/configs/alpr.h | 4 ++-- include/configs/bamboo.h | 14 ++++++------ include/configs/ebony.h | 2 +- include/configs/lwmon5.h | 4 ++-- include/configs/ocotea.h | 2 +- include/configs/p3p440.h | 2 +- include/configs/pcs440ep.h | 2 +- include/configs/sequoia.h | 2 +- include/configs/taishan.h | 4 ++-- include/configs/yosemite.h | 2 +- include/mpc5xx.h | 42 +++++++++++++++++------------------ include/mpc824x.h | 6 ++--- include/mpc8260.h | 16 +++++++------- include/mpc83xx.h | 10 ++++----- include/mpc8xx.h | 12 +++++----- include/ppc405.h | 14 ++++++------ include/ppc440.h | 8 +++---- 33 files changed, 167 insertions(+), 128 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 08f625af015..e3c21f9bd89 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,42 @@ +commit 2dc64451b4c08ffd619372abfdc2506a2e2363b9 +Author: Igor Lisitsin +Date: Wed Apr 18 14:55:19 2007 +0400 + + Adapt log buffer code to support Linux 2.6 + + A new environment variable, "logversion", selects the log buffer + behaviour. If it is not set or set to a value other than 2, then the + old, Linux 2.4.4, behaviour is selected. + + Signed-off-by: Igor Lisitsin + -- + +commit a11e06965ec91270c51853407ff1261d3c740386 +Author: Igor Lisitsin +Date: Wed Mar 28 19:06:19 2007 +0400 + + Extend POST support for PPC440 + + Added memory, CPU, UART, I2C and SPR POST tests for PPC440. + + Signed-off-by: Igor Lisitsin + -- + +commit 02032e8f14751a1a751b09240a4f1cf9f8a2077f +Author: Rafal Jaworowski +Date: Fri Jun 22 14:58:04 2007 +0200 + + [ppc] Fix build breakage for all non-4xx PowerPC variants. + + - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros + - minor 4xx cleanup + +commit 83b4cfa3d629dff0264366263c5e94d9a50ad80b +Author: Wolfgang Denk +Date: Wed Jun 20 18:14:24 2007 +0200 + + Coding style cleanup. Refresh CHANGELOG. + commit b3f9ec86e388207fd03dcdf7b145b9ed080bf024 Author: Stefan Roese Date: Tue Jun 19 17:22:44 2007 +0200 diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c index 0f54025fb2e..8b82ea40ede 100644 --- a/board/amcc/acadia/acadia.c +++ b/board/amcc/acadia/acadia.c @@ -31,13 +31,13 @@ static void acadia_gpio_init(void) /* * GPIO0 setup (select GPIO or alternate function) */ - out32(GPIO0_OSRL, CFG_GPIO0_OSRL); - out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ - out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); - out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ - out32(GPIO0_TSRL, CFG_GPIO0_TSRL); - out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ - out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ + out32(GPIO0_OSRL, CFG_GPIO0_OSRL); + out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ + out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); + out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ + out32(GPIO0_TSRL, CFG_GPIO0_TSRL); + out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ + out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ /* * Ultra (405EZ) was nice enough to add another GPIO controller diff --git a/board/bf537-stamp/ether_bf537.c b/board/bf537-stamp/ether_bf537.c index f00837aad2c..807b9e839b4 100644 --- a/board/bf537-stamp/ether_bf537.c +++ b/board/bf537-stamp/ether_bf537.c @@ -48,7 +48,7 @@ #define TXBUF_BASE_ADDR 0xFF800000 #define TX_BUF_CNT 1 -#define TOUT_LOOP 1000000 +#define TOUT_LOOP 1000000 ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT]; ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX]; diff --git a/board/bf537-stamp/flash-defines.h b/board/bf537-stamp/flash-defines.h index acc1e8638bf..1fa7a10bdac 100644 --- a/board/bf537-stamp/flash-defines.h +++ b/board/bf537-stamp/flash-defines.h @@ -44,9 +44,9 @@ #define ERASE_SECT 6 #define READ 7 #define GET_SECTNUM 8 -#define FLASH_START_L 0x0000 -#define FLASH_START_H 0x2000 -#define FLASH_MAN_ST 2 +#define FLASH_START_L 0x0000 +#define FLASH_START_H 0x2000 +#define FLASH_MAN_ST 2 #define RESET_VAL 0xF0 flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; diff --git a/board/bf537-stamp/stm_m25p64.c b/board/bf537-stamp/stm_m25p64.c index 7077e85f412..d9c08ee8e66 100644 --- a/board/bf537-stamp/stm_m25p64.c +++ b/board/bf537-stamp/stm_m25p64.c @@ -9,7 +9,7 @@ /* Application definitions */ -#define NUM_SECTORS 128 /* number of sectors */ +#define NUM_SECTORS 128 /* number of sectors */ #define SECTOR_SIZE 0x10000 #define NOP_NUM 1000 diff --git a/board/bf537-stamp/u-boot.lds.S b/board/bf537-stamp/u-boot.lds.S index 3fb2d0cc60b..8632097b613 100644 --- a/board/bf537-stamp/u-boot.lds.S +++ b/board/bf537-stamp/u-boot.lds.S @@ -33,7 +33,7 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); __DYNAMIC = 0; */ MEMORY { - ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024) + ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024) l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000 l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000 } @@ -47,11 +47,11 @@ SECTIONS .dynsym : { *(.dynsym) } .dynstr : { *(.dynstr) } .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } + .rela.text : { *(.rela.text) } .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } .rel.got : { *(.rel.got) } .rela.got : { *(.rela.got) } .rel.ctors : { *(.rel.ctors) } @@ -68,7 +68,7 @@ SECTIONS .text : { /* WARNING - the following is hand-optimized to fit within */ - /* the sector before the environment sector. If it throws */ + /* the sector before the environment sector. If it throws */ /* an error during compilation remove an object here to get */ /* it linked after the configuration sector. */ diff --git a/board/smdk2400/lowlevel_init.S b/board/smdk2400/lowlevel_init.S index a5de806af55..a7959f391d0 100644 --- a/board/smdk2400/lowlevel_init.S +++ b/board/smdk2400/lowlevel_init.S @@ -117,7 +117,7 @@ #define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */ #define Trp 0x0 /* 2 clk */ #define Trc 0x3 /* 7 clk */ -#define Tchr 0x2 /* 3 clk */ +#define Tchr 0x2 /* 3 clk */ #define REFCNT 1113 /* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */ diff --git a/common/cmd_log.c b/common/cmd_log.c index 5bf811e7558..fba8bd8bf5c 100644 --- a/common/cmd_log.c +++ b/common/cmd_log.c @@ -83,13 +83,13 @@ void logbuff_init_ptrs (void) /* The post routines have setup the word so we can simply test it */ if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT)) { logbuff_reset (); - } + } #else /* No post routines, so we do our own checking */ if (tag != LOGBUFF_MAGIC || post_word != LOGBUFF_MAGIC) { logbuff_reset (); post_word_store (LOGBUFF_MAGIC); - } + } #endif if (log_version == 2 && (long)log->v2.start > (long)log->v2.con) log->v2.start = log->v2.con; diff --git a/common/main.c b/common/main.c index 553ac357dc3..d8123a7ce80 100644 --- a/common/main.c +++ b/common/main.c @@ -962,7 +962,7 @@ int readline (const char *const prompt) n = 0; continue; - case 0x17: /* ^W - erase word */ + case 0x17: /* ^W - erase word */ p=delete_char(console_buffer, p, &col, &n, plen); while ((n > 0) && (*p != ' ')) { p=delete_char(console_buffer, p, &col, &n, plen); diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S index 95728373fbd..0637003ce29 100644 --- a/cpu/mpc5xx/start.S +++ b/cpu/mpc5xx/start.S @@ -155,7 +155,7 @@ in_flash: /* Initialize some SPRs that are hard to access from C */ /*----------------------------------------------------------------------*/ - lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */ + lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */ lis r2, CFG_INIT_SP_ADDR@h ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */ /* Note: R0 is still 0 here */ diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index bc55b58ad24..7f5dc819cd8 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -676,13 +676,13 @@ init_debug: bdnz 1b /* Load the Instruction Address Breakpoint Register (IABR). */ - /* */ + /* */ /* The address to load is stored in the first word of dual port */ /* ram and should be preserved while the power is on, so you */ /* can plug addresses into that location then reset the cpu and */ /* this code will load that address into the IABR after the */ /* reset. */ - /* */ + /* */ /* When the program counter matches the contents of the IABR, */ /* an exception is generated (before the instruction at that */ /* location completes). The vector for this exception is 0x1300 */ diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index fe7bbabd596..e24cd81b71f 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -1340,14 +1340,14 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, */ cr |= SDRAM_BXCR_SDBE; - for (i = 0; i < num_banks; i++) { + for (i = 0; i < num_banks; i++) { bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes = (4 << 20) * bank_size_id; bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr; debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n", dimm_num, i, ctrl_bank_num[dimm_num]+i, bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes); - } + } } } diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 874cec07ed6..b5c0f53d278 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -58,8 +58,8 @@ #define SDRAM_DDR2 2 #define SDRAM_NONE 0 -#define MAXDIMMS 2 -#define MAXRANKS 4 +#define MAXDIMMS 2 +#define MAXRANKS 4 #define MAXBXCF 4 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */ diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index bc1ae0e4e74..351da36e855 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -153,7 +153,7 @@ cpu_init_f (void) */ asm volatile(" bl 0f" ::: "lr"); asm volatile("0: mflr 3" ::: "r3"); - asm volatile(" addi 4, 0, 14" ::: "r4"); + asm volatile(" addi 4, 0, 14" ::: "r4"); asm volatile(" mtctr 4" ::: "ctr"); asm volatile("1: icbt 0, 3"); asm volatile(" addi 3, 3, 32" ::: "r3"); diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 29e6101a157..9780fe15c0d 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -35,18 +35,18 @@ #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ #define MSR_BE (1<<9) /* Branch Trace */ -#define MSR_DE (1<<9) /* Debug Exception Enable */ +#define MSR_DE (1<<9) /* Debug Exception Enable */ #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ -#define MSR_IR (1<<5) /* Instruction Relocate */ +#define MSR_IR (1<<5) /* Instruction Relocate */ #define MSR_IS (1<<5) /* Book E Instruction space */ -#define MSR_DR (1<<4) /* Data Relocate */ +#define MSR_DR (1<<4) /* Data Relocate */ #define MSR_DS (1<<4) /* Book E Data space */ #define MSR_PE (1<<3) /* Protection Enable */ #define MSR_PX (1<<2) /* Protection Exclusive Mode */ #define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ #define MSR_RI (1<<1) /* Recoverable Exception */ -#define MSR_LE (1<<0) /* Little Endian */ +#define MSR_LE (1<<0) /* Little Endian */ #ifdef CONFIG_APUS_FAST_EXCEPT #define MSR_ MSR_ME|MSR_IP|MSR_RI @@ -123,9 +123,9 @@ #define DBCR_EDM 0x80000000 #define DBCR_IDM 0x40000000 #define DBCR_RST(x) (((x) & 0x3) << 28) -#define DBCR_RST_NONE 0 -#define DBCR_RST_CORE 1 -#define DBCR_RST_CHIP 2 +#define DBCR_RST_NONE 0 +#define DBCR_RST_CORE 1 +#define DBCR_RST_CHIP 2 #define DBCR_RST_SYSTEM 3 #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ @@ -266,7 +266,7 @@ #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ -#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ @@ -495,17 +495,17 @@ #define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ #define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ #define DBSR SPRN_DBSR /* Debug Status Register */ -#define DCMP SPRN_DCMP /* Data TLB Compare Register */ -#define DEC SPRN_DEC /* Decrement Register */ -#define DMISS SPRN_DMISS /* Data TLB Miss Register */ +#define DCMP SPRN_DCMP /* Data TLB Compare Register */ +#define DEC SPRN_DEC /* Decrement Register */ +#define DMISS SPRN_DMISS /* Data TLB Miss Register */ #define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ -#define EAR SPRN_EAR /* External Address Register */ +#define EAR SPRN_EAR /* External Address Register */ #define ESR SPRN_ESR /* Exception Syndrome Register */ #define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ #define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ #define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ #define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ -#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ +#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ #define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ #define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ #define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ @@ -522,13 +522,13 @@ #define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ #define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ #define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ -#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ +#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ #define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ -#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ +#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ #define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ -#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ +#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_MPC86xx) @@ -540,7 +540,7 @@ #define SVR SPRN_SVR /* System-On-Chip Version Register */ #define PVR SPRN_PVR /* Processor Version */ #define RPA SPRN_RPA /* Required Physical Address Register */ -#define SDR1 SPRN_SDR1 /* MMU hash base register */ +#define SDR1 SPRN_SDR1 /* MMU hash base register */ #define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ #define SPR1 SPRN_SPRG1 #define SPR2 SPRN_SPRG2 @@ -611,7 +611,7 @@ #define IVOR35 SPRN_IVOR35 #define MCSRR0 SPRN_MCSRR0 #define MCSRR1 SPRN_MCSRR1 -#define L1CSR0 SPRN_L1CSR0 +#define L1CSR0 SPRN_L1CSR0 #define L1CSR1 SPRN_L1CSR1 #define MCSR SPRN_MCSR #define MMUCSR0 SPRN_MMUCSR0 @@ -620,7 +620,7 @@ #define PID1 SPRN_PID1 #define PID2 SPRN_PID2 #define MAS0 SPRN_MAS0 -#define MAS1 SPRN_MAS1 +#define MAS1 SPRN_MAS1 #define MAS2 SPRN_MAS2 #define MAS3 SPRN_MAS3 #define MAS4 SPRN_MAS4 @@ -632,7 +632,7 @@ #define DCRN_BEAR 0x090 /* Bus Error Address Register */ #define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ +#define BESR_DSES 0x80000000 /* Data-Side Error Status */ #define BESR_DMES 0x40000000 /* DMA Error Status */ #define BESR_RWS 0x20000000 /* Read/Write Status */ #define BESR_ETMASK 0x1C000000 /* Error Type */ @@ -689,8 +689,8 @@ #define IOCR_E3LP 0x01000000 #define IOCR_E4TE 0x00800000 #define IOCR_E4LP 0x00400000 -#define IOCR_EDT 0x00080000 -#define IOCR_SOR 0x00040000 +#define IOCR_EDT 0x00080000 +#define IOCR_SOR 0x00040000 #define IOCR_EDO 0x00008000 #define IOCR_2XC 0x00004000 #define IOCR_ATC 0x00002000 @@ -815,7 +815,7 @@ #define PVR_823 PVR_821 #define PVR_850 PVR_821 #define PVR_860 PVR_821 -#define PVR_7400 0x000C0000 +#define PVR_7400 0x000C0000 #define PVR_8240 0x00810100 /* diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 9da1d884b14..aa3627b4d77 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -44,7 +44,7 @@ #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ @@ -238,7 +238,7 @@ "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \ "u-boot=/tftpboot/tqm5200/u-boot.bin\0" #else -#define CUSTOM_ENV_SETTINGS \ +#define CUSTOM_ENV_SETTINGS \ "bootfile=cam5200/uImage\0" \ "u-boot=cam5200/u-boot.bin\0" \ "setup=tftp 200000 cam5200/setup.img; autoscr 200000\0" diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 47893e824dd..3e571db0e13 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -95,7 +95,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ @@ -257,7 +257,7 @@ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index af337eee8ea..cd5844363f8 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -74,9 +74,9 @@ * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ #define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ -#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (4 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -115,8 +115,8 @@ /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ -#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ +#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ @@ -126,11 +126,11 @@ #define CFG_FLASH_ADDR1 0x2aa #define CFG_FLASH_WORD_SIZE unsigned char -#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ -#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ +#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ +#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 5bd326b9aee..09efe1d4004 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -122,7 +122,7 @@ #define CFG_FLASH_WORD_SIZE unsigned char #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 675df76267b..ab42b596268 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -117,7 +117,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ -#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ @@ -360,7 +360,7 @@ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 31f8bb3fddf..931fb820d1c 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -137,7 +137,7 @@ #define CFG_FLASH_WORD_SIZE unsigned char #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index cae5bd56f86..f67c5135489 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -286,7 +286,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 040e5895977..333b4a2b7fd 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -104,7 +104,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index ae1c129109f..7b7fb9eb415 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -127,7 +127,7 @@ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/taishan.h b/include/configs/taishan.h index cbbb0066e92..b45c51dc921 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -218,8 +218,8 @@ #define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_NET_MULTI 1 -#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ -#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ +#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ +#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ #define CONFIG_PHY2_ADDR 0x1 #define CONFIG_PHY3_ADDR 0x3 #define CONFIG_ET1011C_PHY 1 diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index c96b14e8391..b036d444d13 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -123,7 +123,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/mpc5xx.h b/include/mpc5xx.h index e9b08a0dc72..414651fa0f8 100644 --- a/include/mpc5xx.h +++ b/include/mpc5xx.h @@ -76,10 +76,10 @@ #define SIUMCR_DBPC01 0x00080000 /* - " - */ #define SIUMCR_DBPC10 0x00100000 /* - " - */ #define SIUMCR_DBPC11 0x00180000 /* - " - */ -#define SIUMCR_GPC00 0x00000000 /* General Pins Config */ -#define SIUMCR_GPC01 0x00020000 /* General Pins Config */ -#define SIUMCR_GPC10 0x00040000 /* General Pins Config */ -#define SIUMCR_GPC11 0x00060000 /* General Pins Config */ +#define SIUMCR_GPC00 0x00000000 /* General Pins Config */ +#define SIUMCR_GPC01 0x00020000 /* General Pins Config */ +#define SIUMCR_GPC10 0x00040000 /* General Pins Config */ +#define SIUMCR_GPC11 0x00060000 /* General Pins Config */ #define SIUMCR_DLK 0x00010000 /* Debug Register Lock */ #define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */ #define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */ @@ -90,7 +90,7 @@ #define SIUMCR_MLRC01 0x00000400 /* - " - */ #define SIUMCR_MLRC10 0x00000800 /* - " - */ #define SIUMCR_MLRC11 0x00000c00 /* - " - */ -#define SIUMCR_MTSC 0x00000100 /* Memory transfer */ +#define SIUMCR_MTSC 0x00000100 /* Memory transfer */ /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control Register @@ -123,13 +123,13 @@ * SCCR - System Clock and reset Control Register */ #define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */ -#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */ +#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */ #define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */ #define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */ #define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */ #define SCCR_EBDF11 0x00060000 /* reserved */ #define SCCR_TBS 0x02000000 /* Time Base Source */ -#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ +#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ #define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */ #define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */ #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ @@ -138,11 +138,11 @@ /*----------------------------------------------------------------------- * MC - Memory Controller */ -#define BR_V 0x00000001 /* Bank valid */ -#define BR_BI 0x00000002 /* Burst inhibit */ -#define BR_PS_8 0x00000400 /* 8 bit port size */ -#define BR_PS_16 0x00000800 /* 16 bit port size */ -#define BR_PS_32 0x00000000 /* 32 bit port size */ +#define BR_V 0x00000001 /* Bank valid */ +#define BR_BI 0x00000002 /* Burst inhibit */ +#define BR_PS_8 0x00000400 /* 8 bit port size */ +#define BR_PS_16 0x00000800 /* 16 bit port size */ +#define BR_PS_32 0x00000000 /* 32 bit port size */ #define BR_LBDIR 0x00000008 /* Late burst data in progess */ #define BR_SETA 0x00000004 /* External Data Acknowledge */ #define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */ @@ -159,8 +159,8 @@ /*----------------------------------------------------------------------- * UMCR - UIMB Module Configuration Register */ -#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */ -#define UMCR_HSPEED 0x10000000 /* Half speed */ +#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */ +#define UMCR_HSPEED 0x10000000 /* Half speed */ /*----------------------------------------------------------------------- * ICTRL - I-Bus Support Control Register @@ -174,16 +174,16 @@ * SCI - Serial communication interface */ -#define SCI_TDRE 0x0100 /* Transmit data register empty */ -#define SCI_TE 0x0008 /* Transmitter enabled */ +#define SCI_TDRE 0x0100 /* Transmit data register empty */ +#define SCI_TE 0x0008 /* Transmitter enabled */ #define SCI_RE 0x0004 /* Receiver enabled */ -#define SCI_RDRF 0x0040 /* Receive data register full */ -#define SCI_PE 0x0400 /* Parity enable */ -#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */ -#define SCI_SCXDR_MK 0x00ff /* Data register mask */ +#define SCI_RDRF 0x0040 /* Receive data register full */ +#define SCI_PE 0x0400 /* Parity enable */ +#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */ +#define SCI_SCXDR_MK 0x00ff /* Data register mask */ #define SCI_M_11 0x0200 /* Frame size is 11 bit */ #define SCI_M_10 0x0000 /* Frame size is 10 bit */ -#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */ +#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */ #define SCI_PORT_2 ((int)2) #endif /* __MPC5XX_H__ */ diff --git a/include/mpc824x.h b/include/mpc824x.h index 4bd88634819..30f01d5aa89 100644 --- a/include/mpc824x.h +++ b/include/mpc824x.h @@ -88,7 +88,7 @@ #define PREP_PCI_MEMORY_BUS 0x80000000 #define PREP_PCI_MEMORY_SIZE 0x80000000 #define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */ -#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */ +#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */ #define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */ #define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */ #define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */ @@ -98,8 +98,8 @@ #define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */ #define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */ #define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */ -#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/ -#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/ +#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/ +#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/ #define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */ #define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */ #define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */ diff --git a/include/mpc8260.h b/include/mpc8260.h index b61218ccc29..052529409a1 100644 --- a/include/mpc8260.h +++ b/include/mpc8260.h @@ -664,7 +664,7 @@ #define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */ /*----------------------------------------------------------------------- - * LSDMR - Local Bus SDRAM Mode Register 10-24 + * LSDMR - Local Bus SDRAM Mode Register 10-24 */ /* @@ -707,23 +707,23 @@ /*----------------------------------------------------------------------- * TMR1-TMR4 - Timer Mode Registers 17-6 */ -#define TMRx_PS_MSK 0xff00 /* Prescaler Value */ +#define TMRx_PS_MSK 0xff00 /* Prescaler Value */ #define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/ -#define TMRx_OM 0x0020 /* Output Mode */ +#define TMRx_OM 0x0020 /* Output Mode */ #define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/ -#define TMRx_FRR 0x0008 /* Free Run/Restart */ +#define TMRx_FRR 0x0008 /* Free Run/Restart */ #define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */ -#define TMRx_GE 0x0001 /* Gate Enable */ +#define TMRx_GE 0x0001 /* Gate Enable */ #define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/ #define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */ #define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */ -#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */ +#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */ -#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */ +#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */ #define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/ #define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/ -#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */ +#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */ /*----------------------------------------------------------------------- diff --git a/include/mpc83xx.h b/include/mpc83xx.h index cbf41c3a939..336c0ac4f22 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -439,9 +439,9 @@ #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 #if defined(CONFIG_MPC831X) -#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 +#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 -#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 +#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 #define HRCWH_RL_EXT_LEGACY 0x00000000 @@ -1218,7 +1218,7 @@ #define FCR_CMD1 0x00FF0000 #define FCR_CMD1_SHIFT 16 #define FCR_CMD2 0x0000FF00 -#define FCR_CMD2_SHIFT 8 +#define FCR_CMD2_SHIFT 8 #define FCR_CMD3 0x000000FF #define FCR_CMD3_SHIFT 0 @@ -1242,8 +1242,8 @@ /* LTESR - Transfer Error Status Register */ #define LTESR_BM 0x80000000 -#define LTESR_FCT 0x40000000 -#define LTESR_PAR 0x20000000 +#define LTESR_FCT 0x40000000 +#define LTESR_PAR 0x20000000 #define LTESR_WP 0x04000000 #define LTESR_ATMW 0x00800000 #define LTESR_ATMR 0x00400000 diff --git a/include/mpc8xx.h b/include/mpc8xx.h index 11305987f89..bef748f9003 100644 --- a/include/mpc8xx.h +++ b/include/mpc8xx.h @@ -208,12 +208,12 @@ #define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */ #define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */ #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ -#define SCCR_DFNL001 0x00000100 /* Division by 4 */ -#define SCCR_DFNL010 0x00000200 /* Division by 8 */ -#define SCCR_DFNL011 0x00000300 /* Division by 16 */ -#define SCCR_DFNL100 0x00000400 /* Division by 32 */ -#define SCCR_DFNL101 0x00000500 /* Division by 64 */ -#define SCCR_DFNL110 0x00000600 /* Division by 128 */ +#define SCCR_DFNL001 0x00000100 /* Division by 4 */ +#define SCCR_DFNL010 0x00000200 /* Division by 8 */ +#define SCCR_DFNL011 0x00000300 /* Division by 16 */ +#define SCCR_DFNL100 0x00000400 /* Division by 32 */ +#define SCCR_DFNL101 0x00000500 /* Division by 64 */ +#define SCCR_DFNL110 0x00000600 /* Division by 128 */ #define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */ #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ #define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */ diff --git a/include/ppc405.h b/include/ppc405.h index 6be2a50db75..8e64731929e 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -143,12 +143,12 @@ #define UIC_USBH1 0x00040000 /* USB Host 1 */ #define UIC_USBH2 0x00020000 /* USB Host 2 */ #define UIC_USBDEV 0x00010000 /* USB Device */ -#define UIC_ENET 0x00008000 /* Ethernet interrupt status */ -#define UIC_ENET1 0x00008000 /* dummy define */ +#define UIC_ENET 0x00008000 /* Ethernet interrupt status */ +#define UIC_ENET1 0x00008000 /* dummy define */ #define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */ #define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */ -#define UIC_MAL_SERR 0x00002000 /* MAL SERR */ +#define UIC_MAL_SERR 0x00002000 /* MAL SERR */ #define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */ #define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */ @@ -886,7 +886,7 @@ #define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ #define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ #define reset (CNTRL_DCR_BASE+0x3) /* reset register */ -#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ +#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ #define ecr (0xaa) /* edge conditioner register (405gpr) */ @@ -1119,13 +1119,13 @@ | UART Register Offsets '----------------------------------------------------------------------------*/ #define DATA_REG 0x00 -#define DL_LSB 0x00 -#define DL_MSB 0x01 +#define DL_LSB 0x00 +#define DL_MSB 0x01 #define INT_ENABLE 0x01 #define FIFO_CONTROL 0x02 #define LINE_CONTROL 0x03 #define MODEM_CONTROL 0x04 -#define LINE_STATUS 0x05 +#define LINE_STATUS 0x05 #define MODEM_STATUS 0x06 #define SCRATCH 0x07 diff --git a/include/ppc440.h b/include/ppc440.h index 9ba47a53cf5..76330f16ac6 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -112,7 +112,7 @@ #define icdbtrh 0x39f /* instruction cache debug tag register high */ #define mmucr 0x3b2 /* mmu control register */ #define ccr0 0x3b3 /* core configuration register 0 */ -#define ccr1 0x378 /* core configuration for 440x5 only */ +#define ccr1 0x378 /* core configuration for 440x5 only */ #define icdbdr 0x3d3 /* instruction cache debug data register */ #define dbdr 0x3f3 /* debug data register */ @@ -136,7 +136,7 @@ #define clk_opbd 0x00c0 #define clk_perd 0x00e0 #define clk_mald 0x0100 -#define clk_spcid 0x0120 +#define clk_spcid 0x0120 #define clk_icfg 0x0140 /* 440gx sdr register definations */ @@ -686,8 +686,8 @@ #define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 #define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 #define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 -#define SDRAM_CODT_IO_HIZ 0x00000000 -#define SDRAM_CODT_IO_NMODE 0x00000001 +#define SDRAM_CODT_IO_HIZ 0x00000000 +#define SDRAM_CODT_IO_NMODE 0x00000001 /*-----------------------------------------------------------------------------+ | SDRAM Mode Register -- cgit v1.3.1 From 6f35c53166213c24a5a0e2390ed861136ff73870 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Sun, 24 Jun 2007 17:41:21 +0200 Subject: ppc4xx: Maintenance patch for esd's CPCI405 derivats -add pci_pre_init() for pci interrupt fixup code -disable phy sleep mode via reset_phy() function -use correct io accessors -cleanup Signed-off-by: Matthias Fuchs --- board/esd/cpci405/cpci405.c | 76 ++++++++++++++++++++++++++++++++------------- include/configs/CPCI405.h | 5 +++ include/configs/CPCI4052.h | 6 ++++ include/configs/CPCI405AB.h | 5 +++ include/configs/CPCI405DT.h | 5 +++ 5 files changed, 76 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index f80361081a6..263b75d3a1a 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -23,9 +23,11 @@ #include #include +#include #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -179,11 +181,15 @@ int board_early_init_f (void) mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ +#ifdef CONFIG_CPCI405_6U if (cpci405_version() == 3) { mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ } else { mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ } +#else + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ +#endif mtdcr(uictr, 0x10000000); /* set int trigger levels */ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ @@ -227,10 +233,10 @@ int cpci405_version(void) */ cntrl0Reg = mfdcr(cntrl0); mtdcr(cntrl0, cntrl0Reg | 0x03000000); - out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000); - out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000); + out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); + out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); udelay(1000); /* wait some time before reading input */ - value = in32(GPIO0_IR) & 0x00180000; /* get config bits */ + value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ /* * Restore GPIO settings @@ -245,7 +251,7 @@ int cpci405_version(void) /* CS2==0 && CS3==1 -> version 2 */ return 2; case 0x00100000: - /* CS2==1 && CS3==0 -> version 3 */ + /* CS2==1 && CS3==0 -> version 3 or 6U board */ return 3; case 0x00000000: /* CS2==0 && CS3==0 -> version 4 */ @@ -283,7 +289,6 @@ int misc_init_r (void) * On CPCI-405 version 2 the environment is saved in eeprom! * FPGA can be gzip compressed (malloc) and booted this late. */ - if (cpci405_version() >= 2) { /* * Setup GPIO pins (CS6+CS7 as GPIO) @@ -354,6 +359,7 @@ int misc_init_r (void) SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); udelay(1000); /* wait 1ms */ +#ifdef CONFIG_CPCI405_6U if (cpci405_version() == 3) { volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR; volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR; @@ -375,6 +381,7 @@ int misc_init_r (void) udelay(100); *fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET); } +#endif } else { puts("\n*** U-Boot Version does not match Board Version!\n"); @@ -493,12 +500,6 @@ int checkboard (void) #endif putc ('\n'); - - /* - * Disable sleep mode in LXT971 - */ - lxt971_no_sleep(); - return 0; } @@ -511,24 +512,22 @@ long int initdram (int board_type) mtdcr(memcfga, mem_mb0cf); val = mfdcr(memcfgd); -#if 0 - printf("\nmb0cf=%x\n", val); /* test-only */ - printf("strap=%x\n", mfdcr(strap)); /* test-only */ -#endif - return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } -/* ------------------------------------------------------------------------- */ -int testdram (void) +void reset_phy(void) { - /* TODO: XXX XXX XXX */ - printf ("test: 16 MB - ok\n"); +#ifdef CONFIG_LXT971_NO_SLEEP - return (0); + /* + * Disable sleep mode in LXT971 + */ + lxt971_no_sleep(); +#endif } + /* ------------------------------------------------------------------------- */ #ifdef CONFIG_CPCI405_VER2 @@ -552,6 +551,41 @@ void ide_set_reset(int on) #endif /* CONFIG_CPCI405_VER2 */ +#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) +{ + unsigned char int_line = 0xff; + + /* + * Write pci interrupt line register (cpci405 specific) + */ + switch (PCI_DEV(dev) & 0x03) { + case 0: + int_line = 27 + 2; + break; + case 1: + int_line = 27 + 3; + break; + case 2: + int_line = 27 + 0; + break; + case 3: + int_line = 27 + 1; + break; + } + + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); +} + +int pci_pre_init(struct pci_controller *hose) +{ + hose->fixup_irq = cpci405_pci_fixup_irq; + return 1; +} +#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ + + + #ifdef CONFIG_CPCI405AB #define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 047e2f1eef9..67f75811301 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -55,6 +55,10 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ CONFIG_BOOTP_DNS | \ @@ -139,6 +143,7 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index d756f447f7f..8abdbdc6df2 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -37,6 +37,7 @@ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ +#undef CONFIG_CPCI405_6U /* enable this for 6U boards */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ @@ -56,6 +57,10 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ @@ -166,6 +171,7 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 852d94a410a..ab6d1168f1d 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -57,6 +57,10 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ @@ -150,6 +154,7 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 2260327c3f8..42ec0801ad7 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -56,6 +56,10 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ @@ -171,6 +175,7 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ -- cgit v1.3.1 From 466fff1a7bb5fe764a06450626f6098219f446b8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 25 Jun 2007 15:57:39 +0200 Subject: ppc4xx: Add pci_pre_init() for 405 boards This patch removes the CFG_PCI_PRE_INIT option completely, since it's not needed anymore with the patch from Matthias Fuchs with the "weak" pci_pre_init() implementation. Signed-off-by: Stefan Roese --- board/amcc/bamboo/bamboo.c | 4 ++-- board/amcc/ebony/ebony.c | 8 ++++---- board/amcc/katmai/katmai.c | 4 ++-- board/amcc/luan/luan.c | 4 ++-- board/amcc/ocotea/ocotea.c | 4 ++-- board/amcc/sequoia/sequoia.c | 17 ++--------------- board/amcc/taishan/taishan.c | 4 ++-- board/amcc/yosemite/yosemite.c | 4 ++-- board/amcc/yucca/yucca.c | 4 ++-- board/esd/cpci405/cpci405.c | 4 ++-- board/lwmon5/lwmon5.c | 4 ++-- board/pcs440ep/pcs440ep.c | 4 ++-- board/prodrive/alpr/alpr.c | 4 ++-- board/prodrive/p3p440/p3p440.c | 4 ++-- board/sandburst/common/sb_common.c | 4 ++-- board/xpedite1k/xpedite1k.c | 4 ++-- doc/README.ppc440 | 13 +++++++------ include/common.h | 9 +++++---- include/configs/CPCI405.h | 1 - include/configs/CPCI4052.h | 1 - include/configs/CPCI405AB.h | 1 - include/configs/CPCI405DT.h | 1 - include/configs/KAREF.h | 1 - include/configs/METROBOX.h | 1 - include/configs/XPEDITE1K.h | 1 - include/configs/alpr.h | 1 - include/configs/bamboo.h | 1 - include/configs/ebony.h | 1 - include/configs/katmai.h | 1 - include/configs/luan.h | 1 - include/configs/lwmon5.h | 1 - include/configs/ocotea.h | 1 - include/configs/p3p440.h | 1 - include/configs/pcs440ep.h | 1 - include/configs/sequoia.h | 1 - include/configs/taishan.h | 1 - include/configs/yosemite.h | 1 - include/configs/yucca.h | 1 - 38 files changed, 46 insertions(+), 77 deletions(-) (limited to 'include') diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 2e651df3b79..caf66909b99 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -416,7 +416,7 @@ int testdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -457,7 +457,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index dcafac950d6..ededb3e7e11 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -207,14 +207,14 @@ long int fixed_sdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long strap; /*--------------------------------------------------------------------------+ - * The ebony board is always configured as the host & requires the - * PCI arbiter to be enabled. + * The ebony board is always configured as the host & requires the + * PCI arbiter to be enabled. *--------------------------------------------------------------------------*/ strap = mfdcr(cpc0_strp1); if ((strap & 0x00100000) == 0) { @@ -224,7 +224,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index 286bdc1f21d..b804d55f2e7 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -292,7 +292,7 @@ int testdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -309,7 +309,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 778aafc7660..2eff3b33fde 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -161,7 +161,7 @@ int testdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init( struct pci_controller *hose ) { unsigned long strap; @@ -179,7 +179,7 @@ int pci_pre_init( struct pci_controller *hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 3f6d2042d72..3bd1b814006 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -306,7 +306,7 @@ long int fixed_sdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -323,7 +323,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index ba365aea318..a8966f0e5f4 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -426,23 +426,10 @@ int testdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; -#if 0 - /*--------------------------------------------------------------------------+ - * Cactus is always configured as the host & requires the - * PCI arbiter to be enabled ??? - *--------------------------------------------------------------------------*/ - unsigned long strap; - mfsdr(sdr_sdstp1, strap); - if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) { - printf("PCI: SDR0_STRP1[PAE] not set.\n"); - printf("PCI: Configuration aborted.\n"); - return 0; - } -#endif /*-------------------------------------------------------------------------+ | Set priority for all PLB3 devices to 0. @@ -480,7 +467,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index 1a2e53b1abc..bc976c75261 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -236,7 +236,7 @@ int testdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -253,7 +253,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index c2e12ba12ea..912f09ee439 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -385,7 +385,7 @@ int testdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -426,7 +426,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 90eaab1c80b..7316c34b4a7 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -604,7 +604,7 @@ int testdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -621,7 +621,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 263b75d3a1a..2ed0fc27220 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -551,7 +551,7 @@ void ide_set_reset(int on) #endif /* CONFIG_CPCI405_VER2 */ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { unsigned char int_line = 0xff; @@ -582,7 +582,7 @@ int pci_pre_init(struct pci_controller *hose) hose->fixup_irq = cpci405_pci_fixup_irq; return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index b303ec7cb3c..d5b8f8c81ba 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -304,7 +304,7 @@ int testdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -345,7 +345,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index 8858f0a5e54..b73ab2adecc 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -217,7 +217,7 @@ int testdram(void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long addr; @@ -258,7 +258,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index 5abc87dde64..b76449989bc 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -172,7 +172,7 @@ int testdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -192,7 +192,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index 2f28e9d87a3..1a8aacbdf12 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -176,7 +176,7 @@ int misc_init_r (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller *hose) { unsigned long strap; @@ -193,7 +193,7 @@ int pci_pre_init(struct pci_controller *hose) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index 78164725168..8a831fa35f1 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -313,7 +313,7 @@ long int fixed_sdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -330,7 +330,7 @@ int pci_pre_init(struct pci_controller * hose ) return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c index a569b534727..8411cf06f76 100644 --- a/board/xpedite1k/xpedite1k.c +++ b/board/xpedite1k/xpedite1k.c @@ -209,7 +209,7 @@ long int fixed_sdram (void) * certain pre-initialization actions. * ************************************************************************/ -#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) int pci_pre_init(struct pci_controller * hose ) { unsigned long strap; @@ -227,7 +227,7 @@ int pci_pre_init(struct pci_controller * hose ) #endif return 1; } -#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ +#endif /* defined(CONFIG_PCI) */ /************************************************************************* * pci_target_init diff --git a/doc/README.ppc440 b/doc/README.ppc440 index 08f34f589fa..2e04abacc8c 100644 --- a/doc/README.ppc440 +++ b/doc/README.ppc440 @@ -146,12 +146,13 @@ that maps in a single PCI I/O space and PCI memory space. The I/O space begins at PCI I/O address 0 and the PCI memory space is 256 MB starting at PCI address CFG_PCI_TARGBASE. After the pci_controller structure is initialized, the cpu-specific code will -call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is -defined. This routine is implemented by board-specific code & is where -the board can over-ride/extend the default pci_controller structure -settings and do other pre-initialization tasks. If pci_pre_init() -returns a value of zero, PCI initialization is aborted; otherwise the -controller structure is registered and initialization continues. +call the routine pci_pre_init(). This routine is implemented by +board-specific code & is where the board can over-ride/extend the +default pci_controller structure settings and exspecially provide +a routine to map the PCI interrupts and do other pre-initialization +tasks. If pci_pre_init() returns a value of zero, PCI initialization +is aborted; otherwise the controller structure is registered and +initialization continues. The default 440GP PCI target configuration is minimal -- it assumes that the strapping registers are set as necessary. Since the strapping bits diff --git a/include/common.h b/include/common.h index 3c4b37b0dcb..d8b6b469e5f 100644 --- a/include/common.h +++ b/include/common.h @@ -38,7 +38,7 @@ typedef volatile unsigned char vu_char; #include #include #include -#if defined(CONFIG_PCI) && defined(CONFIG_440) +#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000)) #include #endif #if defined(CONFIG_8xx) @@ -248,10 +248,11 @@ void pci_init (void); void pci_init_board(void); void pciinfo (int, int); -#if defined(CONFIG_PCI) && defined(CONFIG_440) -# if defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000)) int pci_pre_init (struct pci_controller * ); -# endif +#endif + +#if defined(CONFIG_PCI) && defined(CONFIG_440) # if defined(CFG_PCI_TARGET_INIT) void pci_target_init (struct pci_controller *); # endif diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 67f75811301..9acde1e6f03 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -143,7 +143,6 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ -#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 8abdbdc6df2..3fc99c50244 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -171,7 +171,6 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ -#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index ab6d1168f1d..4e2e1a834d8 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -154,7 +154,6 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ -#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 42ec0801ad7..ab302df7437 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -175,7 +175,6 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ -#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index fd9bd316273..48b94ee45ec 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -263,7 +263,6 @@ #define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ #define CFG_PCI_TARGET_INIT /* let board init pci target*/ #define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 148fe9a5c32..7aae2bd1437 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -332,7 +332,6 @@ #define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ #define CFG_PCI_TARGET_INIT /* let board init pci target*/ #define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 9b32514867a..f2ad097db29 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -238,7 +238,6 @@ extern void out32(unsigned int, unsigned long); #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 47893e824dd..a7b99f72c0f 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -275,7 +275,6 @@ #define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_MASTER_INIT diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index af337eee8ea..a1b5682abfa 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -389,7 +389,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 5bd326b9aee..70b199218db 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -270,7 +270,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index cc47a168ed3..a7eda0773bc 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -314,7 +314,6 @@ #undef CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #undef CFG_PCI_MASTER_INIT diff --git a/include/configs/luan.h b/include/configs/luan.h index 045a144aad8..cbb59c50eaf 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -273,7 +273,6 @@ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #undef CFG_PCI_MASTER_INIT diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 675df76267b..9bfc0b56a5e 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -288,7 +288,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 31f8bb3fddf..bc8ee1c6f16 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -294,7 +294,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index cae5bd56f86..544c1b83de3 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -227,7 +227,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 040e5895977..5c736589517 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -267,7 +267,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 42b42fc57f3..e4f0ac8c9aa 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -371,7 +371,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/taishan.h b/include/configs/taishan.h index cbbb0066e92..b9936fb155a 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -298,7 +298,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index c96b14e8391..6e01244008a 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -312,7 +312,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 7f8b0228aec..1fdcc4b5052 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -289,7 +289,6 @@ #undef CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #undef CFG_PCI_MASTER_INIT -- cgit v1.3.1 From a5d71e290f3673269be8eefb4ec44f53412f9461 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 25 Jun 2007 19:11:37 +0200 Subject: [PCS440EP] get rid of CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG Signed-off-by: Heiko Schocher --- board/pcs440ep/pcs440ep.c | 3 -- cpu/ppc4xx/44x_spd_ddr.c | 32 ++++++++++--------- cpu/ppc4xx/44x_spd_ddr2.c | 79 ++++++++++++++++++++++++---------------------- include/configs/pcs440ep.h | 1 - 4 files changed, 58 insertions(+), 57 deletions(-) (limited to 'include') diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index f638589df29..8b2427aa946 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -506,8 +506,6 @@ int checkboard(void) return (0); } - -#if defined(CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG) void spd_ddr_init_hang (void) { status_led_set (0, STATUS_LED_OFF); @@ -520,7 +518,6 @@ void spd_ddr_init_hang (void) udelay (100000); } } -#endif long int initdram (int board_type) { diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index 8621aa00cf4..a384392406a 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -70,12 +70,14 @@ #define ONE_BILLION 1000000000 -#if defined(CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG) -extern void spd_ddr_init_hang (void); -#define HANG() spd_ddr_init_hang() -#else -#define HANG() hang() -#endif +/* + * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed + */ +void __spd_ddr_init_hang (void) +{ + hang (); +} +void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))); /*----------------------------------------------------------------------------- | Memory Controller Options 0 @@ -474,7 +476,7 @@ static void get_spd_info(unsigned long *dimm_populated, if (dimm_found == FALSE) { printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); } } @@ -497,7 +499,7 @@ static void check_mem_type(unsigned long *dimm_populated, dimm_num); printf("Only DDR SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); break; } } @@ -517,7 +519,7 @@ static void check_volt_type(unsigned long *dimm_populated, if (voltage_type != 0x04) { printf("ERROR: DIMM %lu with unsupported voltage level.\n", dimm_num); - HANG(); + spd_ddr_init_hang (); } else { debug("DIMM %lu voltage level supported.\n", dimm_num); } @@ -588,7 +590,7 @@ static void program_cfg0(unsigned long *dimm_populated, printf("WARNING: DIMM with datawidth of %lu bits.\n", data_width); printf("Only DIMMs with 32 or 64 bit datawidths supported.\n"); - HANG(); + spd_ddr_init_hang (); } break; } @@ -776,7 +778,7 @@ static void program_tr0(unsigned long *dimm_populated, if ((tcyc_reg & 0x0F) >= 10) { printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n", dimm_num); - HANG(); + spd_ddr_init_hang (); } cycle_time_ns_x_10[cas_index] = @@ -856,7 +858,7 @@ static void program_tr0(unsigned long *dimm_populated, printf("ERROR: No supported CAS latency with the installed DIMMs.\n"); printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n"); printf("Make sure the PLB speed is within the supported range.\n"); - HANG(); + spd_ddr_init_hang (); } /* @@ -1168,7 +1170,7 @@ static void program_tr1(void) */ if (window_found == FALSE) { printf("ERROR: Cannot determine a common read delay.\n"); - HANG(); + spd_ddr_init_hang (); } /* @@ -1318,7 +1320,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, printf("ERROR: Unsupported value for the banksize: %d.\n", bank_size_id); printf("Replace the DIMM module with a supported DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); } switch (num_col_addr) { @@ -1340,7 +1342,7 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, printf("ERROR: Unsupported value for number of " "column addresses: %d.\n", num_col_addr); printf("Replace the DIMM module with a supported DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); } /* diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index d748daee015..626b3e69bd9 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -129,12 +129,15 @@ #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ #endif -#if defined(CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG) -extern void spd_ddr_init_hang (void); -#define HANG() spd_ddr_init_hang() -#else -#define HANG() hang() -#endif +/* + * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed + */ +void __spd_ddr_init_hang (void) +{ + hang (); +} +void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang"))); + /* Private Structure Definitions */ @@ -589,7 +592,7 @@ static void get_spd_info(unsigned long *dimm_populated, if (dimm_found == FALSE) { printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); } } @@ -636,42 +639,42 @@ static void check_mem_type(unsigned long *dimm_populated, "slot %d.\n", (unsigned int)dimm_num); printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); break; case 2: printf("ERROR: EDO DIMM detected in slot %d.\n", (unsigned int)dimm_num); printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); break; case 3: printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n", (unsigned int)dimm_num); printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); break; case 4: printf("ERROR: SDRAM DIMM detected in slot %d.\n", (unsigned int)dimm_num); printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); break; case 5: printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n", (unsigned int)dimm_num); printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); break; case 6: printf("ERROR: SGRAM DIMM detected in slot %d.\n", (unsigned int)dimm_num); printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); break; case 7: debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num); @@ -686,7 +689,7 @@ static void check_mem_type(unsigned long *dimm_populated, (unsigned int)dimm_num); printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n"); printf("Replace the DIMM module with a supported DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); break; } } @@ -696,7 +699,7 @@ static void check_mem_type(unsigned long *dimm_populated, && (dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) { printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n"); - HANG(); + spd_ddr_init_hang (); } } } @@ -771,7 +774,7 @@ static void check_frequency(unsigned long *dimm_populated, (unsigned int)(calc_cycle_time*10)); printf("Replace the DIMM, or change DDR frequency via " "strapping bits.\n\n"); - HANG(); + spd_ddr_init_hang (); } } } @@ -803,7 +806,7 @@ static void check_rank_number(unsigned long *dimm_populated, "slot %d is not supported.\n", dimm_rank, dimm_num); printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS); printf("Replace the DIMM module with a supported DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); } else total_rank += dimm_rank; } @@ -812,7 +815,7 @@ static void check_rank_number(unsigned long *dimm_populated, "for all slots.\n", (unsigned int)total_rank); printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS); printf("Remove one of the DIMM modules.\n\n"); - HANG(); + spd_ddr_init_hang (); } } } @@ -837,28 +840,28 @@ static void check_voltage_type(unsigned long *dimm_populated, printf("This DIMM is 5.0 Volt/TTL.\n"); printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", (unsigned int)dimm_num); - HANG(); + spd_ddr_init_hang (); break; case 0x01: printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); printf("This DIMM is LVTTL.\n"); printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", (unsigned int)dimm_num); - HANG(); + spd_ddr_init_hang (); break; case 0x02: printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); printf("This DIMM is 1.5 Volt.\n"); printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", (unsigned int)dimm_num); - HANG(); + spd_ddr_init_hang (); break; case 0x03: printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); printf("This DIMM is 3.3 Volt/TTL.\n"); printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", (unsigned int)dimm_num); - HANG(); + spd_ddr_init_hang (); break; case 0x04: /* 2.5 Voltage only for DDR1 */ @@ -870,7 +873,7 @@ static void check_voltage_type(unsigned long *dimm_populated, printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n"); printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n", (unsigned int)dimm_num); - HANG(); + spd_ddr_init_hang (); break; } } @@ -1013,13 +1016,13 @@ static void program_copt1(unsigned long *dimm_populated, if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) { if (buf0 != buf1) { printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n"); - HANG(); + spd_ddr_init_hang (); } } if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) { printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n"); - HANG(); + spd_ddr_init_hang (); } else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) { mcopt1 |= SDRAM_MCOPT1_DMWD_64; @@ -1027,7 +1030,7 @@ static void program_copt1(unsigned long *dimm_populated, mcopt1 |= SDRAM_MCOPT1_DMWD_32; } else { printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n"); - HANG(); + spd_ddr_init_hang (); } if (ecc_enabled == TRUE) @@ -1216,7 +1219,7 @@ static void program_initplr(unsigned long *dimm_populated, break; default: printf("ERROR: ucode error on selected_cas value %d", selected_cas); - HANG(); + spd_ddr_init_hang (); break; } @@ -1248,7 +1251,7 @@ static void program_initplr(unsigned long *dimm_populated, break; default: printf("ERROR: write recovery not support (%d)", write_recovery); - HANG(); + spd_ddr_init_hang (); break; } #else @@ -1266,7 +1269,7 @@ static void program_initplr(unsigned long *dimm_populated, ods = ODS_REDUCED; } else { printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm); - HANG(); + spd_ddr_init_hang (); } mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas; @@ -1291,7 +1294,7 @@ static void program_initplr(unsigned long *dimm_populated, mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */ } else { printf("ERROR: ucode error as unknown DDR type in program_initplr"); - HANG(); + spd_ddr_init_hang (); } } @@ -1396,7 +1399,7 @@ static void program_mode(unsigned long *dimm_populated, } else { printf("ERROR: SPD reported Tcyc is incorrect for DIMM " "in slot %d\n", (unsigned int)dimm_num); - HANG(); + spd_ddr_init_hang (); } } else { /* Convert from hex to decimal */ @@ -1533,7 +1536,7 @@ static void program_mode(unsigned long *dimm_populated, printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n"); printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n"); printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n"); - HANG(); + spd_ddr_init_hang (); } } else { /* DDR2 */ debug("cas_3_0_available=%d\n", cas_3_0_available); @@ -1556,7 +1559,7 @@ static void program_mode(unsigned long *dimm_populated, cas_3_0_available, cas_4_0_available, cas_5_0_available); printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n", sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk); - HANG(); + spd_ddr_init_hang (); } } @@ -1665,7 +1668,7 @@ static void program_rtr(unsigned long *dimm_populated, printf("ERROR: DIMM %d unsupported refresh rate/type.\n", (unsigned int)dimm_num); printf("Replace the DIMM module with a supported DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); break; } @@ -2073,7 +2076,7 @@ static void program_bxcf(unsigned long *dimm_populated, printf("ERROR: Unsupported value for number of " "column addresses: %d.\n", (unsigned int)num_col_addr); printf("Replace the DIMM module with a supported DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); } } @@ -2155,7 +2158,7 @@ static void program_memory_queue(unsigned long *dimm_populated, printf("ERROR: Unsupported value for the banksize: %d.\n", (unsigned int)rank_size_id); printf("Replace the DIMM module with a supported DIMM.\n\n"); - HANG(); + spd_ddr_init_hang (); } if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1)) @@ -2700,7 +2703,7 @@ calibration_loop: printf("\nERROR: Cannot determine a common read delay for the " "DIMM(s) installed.\n"); debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__); - HANG(); + spd_ddr_init_hang (); } blank_string(strlen(str)); @@ -2856,7 +2859,7 @@ static void test(void) if (window_found == FALSE) { printf("ERROR: Cannot determine a common read delay for the " "DIMM(s) installed.\n"); - HANG(); + spd_ddr_init_hang (); } /*------------------------------------------------------------------ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index d4718088213..c2b5cb8f9f5 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -125,7 +125,6 @@ #undef CONFIG_DDR_ECC /* don't use ECC */ #define SPD_EEPROM_ADDRESS {0x50} #define CONFIG_PROG_SDRAM_TLB 1 -#define CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG 1 /*----------------------------------------------------------------------- * I2C -- cgit v1.3.1 From 1f2a05898658900dc5717761e27abf2052e67e13 Mon Sep 17 00:00:00 2001 From: Mushtaq Khan Date: Sat, 30 Jun 2007 18:50:48 +0200 Subject: Fix S-ATA support. Signed-off-by: mushtaq khan --- common/cmd_sata.c | 8 ++++---- include/sata.h | 16 ++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/common/cmd_sata.c b/common/cmd_sata.c index 2e601a7d809..bd4c11fd9b7 100644 --- a/common/cmd_sata.c +++ b/common/cmd_sata.c @@ -375,9 +375,9 @@ msleep (int count) } ulong -sata_read (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer) +sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buff) { - ulong n = 0; + ulong n = 0, *buffer = (ulong *)buff; u8 dev = 0, num = 0, mask = 0, status = 0; #ifdef CONFIG_LBA48 @@ -482,9 +482,9 @@ sata_read (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer) } ulong -sata_write (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer) +sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff) { - ulong n = 0; + ulong n = 0, *buffer = (ulong *)buff; unsigned char status = 0, num = 0, dev = 0, mask = 0; #ifdef CONFIG_LBA48 diff --git a/include/sata.h b/include/sata.h index a8713f817e9..165b471b289 100644 --- a/include/sata.h +++ b/include/sata.h @@ -28,8 +28,8 @@ struct sata_port { struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */ unsigned char ctl_reg; unsigned char last_ctl; - unsigned char port_state; /* 1-port is present and */ - 0-port is not available */ + unsigned char port_state; /* 1-port is available and */ + /* 0-port is not available */ unsigned char dev_mask; }; @@ -74,18 +74,18 @@ int sata_devchk (struct sata_ioports *ioaddr, int dev); void dev_select (struct sata_ioports *ioaddr, int dev); u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max); u8 sata_chk_status (struct sata_ioports *ioaddr); -ulong sata_read (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer); -ulong sata_write (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer); +ulong sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buffer); +ulong sata_write (int device,ulong blknr, lbaint_t blkcnt, void * buffer); void msleep (int count); #else extern int sata_bus_softreset (int num); extern void sata_identify (int num, int dev); extern void sata_port (struct sata_ioports *ioport); extern void set_Feature_cmd (int num, int dev); -extern ulong sata_read (int device, lbaint_t blknr, - ulong blkcnt, ulong * buffer); -extern ulong sata_write (int device, lbaint_t blknr, - ulong blkcnt, ulong * buffer); +extern ulong sata_read (int device, ulong blknr, + lbaint_t blkcnt, void * buffer); +extern ulong sata_write (int device, ulong blknr, + lbaint_t blkcnt, void * buffer); extern void msleep (int count); #endif -- cgit v1.3.1 From ec63b10b61fd68238d4c15c1cd04c0b38228e2c1 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 11 Jun 2007 19:01:34 -0500 Subject: Introduce initial versions of new Command Config files. Derive three new files from cmd_confdefs.h: config_bootp.h - Has BOOTP related config options, not commands config_cmd_all.h - Has a CONFIG_CMD_* definition for every command config_cmd_default.h - Has a CONFIG_CMD_* definition for default cmds. For now, include "config_bootp.h" for compatability until all users of it directly include it properly. Signed-off-by: Jon Loeliger --- include/cmd_confdefs.h | 30 ++--------------- include/config_bootp.h | 41 +++++++++++++++++++++++ include/config_cmd_all.h | 80 ++++++++++++++++++++++++++++++++++++++++++++ include/config_cmd_default.h | 41 +++++++++++++++++++++++ 4 files changed, 165 insertions(+), 27 deletions(-) create mode 100644 include/config_bootp.h create mode 100644 include/config_cmd_all.h create mode 100644 include/config_cmd_default.h (limited to 'include') diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h index b3ccdcea2b0..9b4545f7b60 100644 --- a/include/cmd_confdefs.h +++ b/include/cmd_confdefs.h @@ -155,33 +155,9 @@ /* - * optional BOOTP fields + * Temporary placeholder until all users directly + * include the proper include file, "config_bootp.h". */ - -#define CONFIG_BOOTP_SUBNETMASK 0x00000001 -#define CONFIG_BOOTP_GATEWAY 0x00000002 -#define CONFIG_BOOTP_HOSTNAME 0x00000004 -#define CONFIG_BOOTP_NISDOMAIN 0x00000008 -#define CONFIG_BOOTP_BOOTPATH 0x00000010 -#define CONFIG_BOOTP_BOOTFILESIZE 0x00000020 -#define CONFIG_BOOTP_DNS 0x00000040 -#define CONFIG_BOOTP_DNS2 0x00000080 -#define CONFIG_BOOTP_SEND_HOSTNAME 0x00000100 -#define CONFIG_BOOTP_NTPSERVER 0x00000200 -#define CONFIG_BOOTP_TIMEOFFSET 0x00000400 - -#define CONFIG_BOOTP_VENDOREX 0x80000000 - -#define CONFIG_BOOTP_ALL (~CONFIG_BOOTP_VENDOREX) - - -#define CONFIG_BOOTP_DEFAULT (CONFIG_BOOTP_SUBNETMASK | \ - CONFIG_BOOTP_GATEWAY | \ - CONFIG_BOOTP_HOSTNAME | \ - CONFIG_BOOTP_BOOTPATH) - -#ifndef CONFIG_BOOTP_MASK -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -#endif +#include "config_bootp.h" #endif /* _CMD_CONFIG_H */ diff --git a/include/config_bootp.h b/include/config_bootp.h new file mode 100644 index 00000000000..f0c9360180d --- /dev/null +++ b/include/config_bootp.h @@ -0,0 +1,41 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License Version 2. This file is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef _CONFIG_BOOTP_H +#define _CONFIG_BOOTP_H + +/* + * Optional BOOTP fields + */ + +#define CONFIG_BOOTP_SUBNETMASK 0x00000001 +#define CONFIG_BOOTP_GATEWAY 0x00000002 +#define CONFIG_BOOTP_HOSTNAME 0x00000004 +#define CONFIG_BOOTP_NISDOMAIN 0x00000008 +#define CONFIG_BOOTP_BOOTPATH 0x00000010 +#define CONFIG_BOOTP_BOOTFILESIZE 0x00000020 +#define CONFIG_BOOTP_DNS 0x00000040 +#define CONFIG_BOOTP_DNS2 0x00000080 +#define CONFIG_BOOTP_SEND_HOSTNAME 0x00000100 +#define CONFIG_BOOTP_NTPSERVER 0x00000200 +#define CONFIG_BOOTP_TIMEOFFSET 0x00000400 + +#define CONFIG_BOOTP_VENDOREX 0x80000000 + +#define CONFIG_BOOTP_ALL (~CONFIG_BOOTP_VENDOREX) + +#define CONFIG_BOOTP_DEFAULT (CONFIG_BOOTP_SUBNETMASK | \ + CONFIG_BOOTP_GATEWAY | \ + CONFIG_BOOTP_HOSTNAME | \ + CONFIG_BOOTP_BOOTPATH) + +#ifndef CONFIG_BOOTP_MASK +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +#endif + +#endif /* _CONFIG_BOOTP_H */ diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h new file mode 100644 index 00000000000..14801b565c0 --- /dev/null +++ b/include/config_cmd_all.h @@ -0,0 +1,80 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License Version 2. This file is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef _CONFIG_CMD_ALL_H +#define _CONFIG_CMD_ALL_H + +/* + * Alphabetical list of all possible commands. + */ + +#define CONFIG_CMD_ASKENV /* ask for env variable */ +#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BEDBUG /* Include BedBug Debugger */ +#define CONFIG_CMD_BMP /* BMP support */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_BSP /* Board Specific functions */ +#define CONFIG_CMD_CACHE /* icache, dcache */ +#define CONFIG_CMD_CDP /* Cisco Discovery Protocol */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_DATE /* support for RTC, date/time...*/ +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_DIAG /* Diagnostics */ +#define CONFIG_CMD_DISPLAY /* Display support */ +#define CONFIG_CMD_DOC /* Disk-On-Chip Support */ +#define CONFIG_CMD_DTT /* Digital Therm and Thermostat */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_EEPROM /* EEPROM read/write support */ +#define CONFIG_CMD_ELF /* ELF (VxWorks) load/boot cmd */ +#define CONFIG_CMD_ENV /* saveenv */ +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_FDC /* Floppy Disk Support */ +#define CONFIG_CMD_FDOS /* Floppy DOS support */ +#define CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#define CONFIG_CMD_FPGA /* FPGA configuration Support */ +#define CONFIG_CMD_HWFLOW /* RTS/CTS hw flow control */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_IDE /* IDE harddisk support */ +#define CONFIG_CMD_IMI /* iminfo */ +#define CONFIG_CMD_IMLS /* List all found images */ +#define CONFIG_CMD_IMMAP /* IMMR dump support */ +#define CONFIG_CMD_IRQ /* irqinfo */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ +#define CONFIG_CMD_KGDB /* kgdb */ +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_LOADS /* loads */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MFSL /* FSL support for Microblaze */ +#define CONFIG_CMD_MII /* MII support */ +#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_PCI /* pciinfo */ +#define CONFIG_CMD_PCMCIA /* PCMCIA support */ +#define CONFIG_CMD_PING /* ping support */ +#define CONFIG_CMD_PORTIO /* Port I/O */ +#define CONFIG_CMD_REGINFO /* Register dump */ +#define CONFIG_CMD_REISER /* Reiserfs support */ +#define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SAVES /* save S record dump */ +#define CONFIG_CMD_SCSI /* SCSI Support */ +#define CONFIG_CMD_SDRAM /* SDRAM DIMM SPD info printout */ +#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ +#define CONFIG_CMD_SNTP /* SNTP support */ +#define CONFIG_CMD_SPI /* SPI utility */ +#define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */ +#define CONFIG_CMD_USB /* USB Support */ +#define CONFIG_CMD_VFD /* VFD support (TRAB) */ +#define CONFIG_CMD_XIMG /* Load part of Multi Image */ + +#endif /* _CONFIG_CMD_ALL_H */ diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h new file mode 100644 index 00000000000..81eba0165c2 --- /dev/null +++ b/include/config_cmd_default.h @@ -0,0 +1,41 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License Version 2. This file is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef _CONFIG_CMD_DEFAULT_H +#define _CONFIG_CMD_DEFAULT_H + +/* + * Alphabetical list of all commands that are configured by default. + * This is essentially all commands minus those that are considered + * "non-standard" for some reason (memory hogs, requires special + * hardware, not fully tested, etc.). + */ + +#define CONFIG_CMD_AUTOSCRIPT /* Autoscript Support */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_ENV /* saveenv */ +#define CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#define CONFIG_CMD_FPGA /* FPGA configuration Support */ +#define CONFIG_CMD_IMI /* iminfo */ +#define CONFIG_CMD_IMLS /* List all found images */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_LOADS /* loads */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#define CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ +#define CONFIG_CMD_XIMG /* Load part of Multi Image */ + +#endif /* _CONFIG_CMD_DEFAULT_H */ +#endif /* _CONFIG_CMD_DEFAULT_H */ -- cgit v1.3.1 From 72a074cec68e5bad60d63206c050974e08afd804 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 11 Jun 2007 19:03:34 -0500 Subject: include/ non-config: Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*). This is a compatibility step that allows both the older form and the new form to co-exist for a while until the older can be removed entirely. All transformations are of the form: Before: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) After: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) Signed-off-by: Jon Loeliger --- include/_exports.h | 2 +- include/config_cmd_default.h | 1 - include/exports.h | 2 +- include/lcd.h | 2 +- include/mk48t59.h | 2 +- include/net.h | 6 +++--- include/pcmcia.h | 6 +++--- 7 files changed, 10 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/_exports.h b/include/_exports.h index 2b8ec3d3f91..a5799838e00 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -15,7 +15,7 @@ EXPORT_FUNC(do_reset) EXPORT_FUNC(getenv) EXPORT_FUNC(setenv) EXPORT_FUNC(simple_strtoul) -#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) || defined(CONFIG_CMD_I2C) EXPORT_FUNC(i2c_write) EXPORT_FUNC(i2c_read) #endif /* CFG_CMD_I2C */ diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h index 81eba0165c2..f61cfc93681 100644 --- a/include/config_cmd_default.h +++ b/include/config_cmd_default.h @@ -38,4 +38,3 @@ #define CONFIG_CMD_XIMG /* Load part of Multi Image */ #endif /* _CONFIG_CMD_DEFAULT_H */ -#endif /* _CONFIG_CMD_DEFAULT_H */ diff --git a/include/exports.h b/include/exports.h index 8f7f61703c6..8a9b314cd40 100644 --- a/include/exports.h +++ b/include/exports.h @@ -23,7 +23,7 @@ void do_reset (void); unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base); char *getenv (char *name); void setenv (char *varname, char *varvalue); -#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#if (CONFIG_COMMANDS & CFG_CMD_I2C) || defined(CONFIG_CMD_I2C) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); #endif /* CFG_CMD_I2C */ diff --git a/include/lcd.h b/include/lcd.h index b688583828b..f0ec76aa3b0 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -173,7 +173,7 @@ void lcd_printf (const char *fmt, ...); /************************************************************************/ /* ** BITMAP DISPLAY SUPPORT */ /************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) +#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) # include # include #endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */ diff --git a/include/mk48t59.h b/include/mk48t59.h index 03c992e06aa..fbdb9f9d12d 100644 --- a/include/mk48t59.h +++ b/include/mk48t59.h @@ -26,7 +26,7 @@ */ -#if defined(CONFIG_RTC_MK48T59) && (CONFIG_COMMANDS & CFG_CMD_DATE) +#if defined(CONFIG_RTC_MK48T59) && ((CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_CMD_DATE)) #define RTC_PORT_ADDR0 CFG_ISA_IO + 0x70 #define RTC_PORT_ADDR1 RTC_PORT_ADDR0 + 0x1 diff --git a/include/net.h b/include/net.h index 461e0380141..853f55a758e 100644 --- a/include/net.h +++ b/include/net.h @@ -341,17 +341,17 @@ typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP /* from net/net.c */ extern char BootFile[128]; /* Boot File name */ -#if (CONFIG_COMMANDS & CFG_CMD_PING) +#if (CONFIG_COMMANDS & CFG_CMD_PING) || defined(CONFIG_CMD_PING) extern IPaddr_t NetPingIP; /* the ip address to ping */ #endif -#if (CONFIG_COMMANDS & CFG_CMD_CDP) +#if (CONFIG_COMMANDS & CFG_CMD_CDP) || defined(CONFIG_CMD_CDP) /* when CDP completes these hold the return values */ extern ushort CDPNativeVLAN; extern ushort CDPApplianceVLAN; #endif -#if (CONFIG_COMMANDS & CFG_CMD_SNTP) +#if (CONFIG_COMMANDS & CFG_CMD_SNTP) || defined(CONFIG_CMD_SNTP) extern IPaddr_t NetNtpServerIP; /* the ip address to NTP */ extern int NetTimeOffset; /* offset time from UTC */ #endif diff --git a/include/pcmcia.h b/include/pcmcia.h index 8f564da9b8c..60794f90ec9 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -31,8 +31,8 @@ * Allow configuration to select PCMCIA slot, * or try to generate a useful default */ -#if ( CONFIG_COMMANDS & CFG_CMD_PCMCIA) || \ - ((CONFIG_COMMANDS & CFG_CMD_IDE) && \ +#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) || \ + (((CONFIG_COMMANDS & CFG_CMD_IDE) || defined(CONFIG_CMD_IDE)) && \ (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) ) #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) @@ -313,7 +313,7 @@ extern u_int *pcmcia_pgcrx[]; #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) #endif -#if (CONFIG_COMMANDS & CFG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) \ +#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD) \ || defined(CONFIG_PXA_PCMCIA) extern int check_ide_device(int slot); #endif -- cgit v1.3.1 From 2f9c19e496acb6bb50d9299e1aab377625d48c38 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 11 Jun 2007 19:03:44 -0500 Subject: configs/ mpc86xx: Rewrite command line options using new CONFIG_CMD-* style. Signed-off-by: Jon Loeliger --- include/configs/MPC8641HPCN.h | 58 ++++++++++++++++--------------------------- 1 file changed, 22 insertions(+), 36 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 12af24f7499..0579a35f896 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -475,39 +475,25 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C + #if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C \ - | CFG_CMD_SCSI \ - | CFG_CMD_EXT2) \ - & \ - ~(CFG_CMD_ENV)) - #else - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_SCSI \ - | CFG_CMD_EXT2) - #else - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif + #undef CONFIG_CMD_ENV +#endif + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI + #define CONFIG_CMD_SCSI + #define CONFIG_CMD_EXT2 #endif -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -518,7 +504,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -539,8 +525,8 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#if defined(CONFIG_CMD_KGDB) + #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif /* @@ -551,9 +537,9 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#if defined(CONFIG_CMD_KGDB) + #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ + #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* -- cgit v1.3.1 From 52b8704d0245e589f86d462e9ec25aeb7ecbbbdd Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Wed, 4 Jul 2007 00:43:53 +0200 Subject: Fix a few file permission problems. Signed-off-by: Wolfgang Denk --- board/siemens/SMN42/flash.c | 0 board/xilinx/ml401/xparameters.h | 0 cpu/microblaze/cache.c | 0 cpu/microblaze/interrupts.c | 0 cpu/microblaze/irq.S | 0 cpu/ppc4xx/traps.c | 0 drivers/enc28j60.c | 0 include/asm-microblaze/asm.h | 0 include/configs/SMN42.h | 0 include/configs/lpc2292sodimm.h | 0 10 files changed, 0 insertions(+), 0 deletions(-) mode change 100755 => 100644 board/siemens/SMN42/flash.c mode change 100755 => 100644 board/xilinx/ml401/xparameters.h mode change 100755 => 100644 cpu/microblaze/cache.c mode change 100755 => 100644 cpu/microblaze/interrupts.c mode change 100755 => 100644 cpu/microblaze/irq.S mode change 100755 => 100644 cpu/ppc4xx/traps.c mode change 100755 => 100644 drivers/enc28j60.c mode change 100755 => 100644 include/asm-microblaze/asm.h mode change 100755 => 100644 include/configs/SMN42.h mode change 100755 => 100644 include/configs/lpc2292sodimm.h (limited to 'include') diff --git a/board/siemens/SMN42/flash.c b/board/siemens/SMN42/flash.c old mode 100755 new mode 100644 diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h old mode 100755 new mode 100644 diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c old mode 100755 new mode 100644 diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c old mode 100755 new mode 100644 diff --git a/cpu/microblaze/irq.S b/cpu/microblaze/irq.S old mode 100755 new mode 100644 diff --git a/cpu/ppc4xx/traps.c b/cpu/ppc4xx/traps.c old mode 100755 new mode 100644 diff --git a/drivers/enc28j60.c b/drivers/enc28j60.c old mode 100755 new mode 100644 diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h old mode 100755 new mode 100644 diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h old mode 100755 new mode 100644 diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h old mode 100755 new mode 100644 -- cgit v1.3.1 From 3649cd99ba815b6601868735765602f00ef3692b Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:34:24 -0600 Subject: Correct relocation fixup for mpc5xx Signed-off-by: Grant Likely --- cpu/mpc5xx/config.mk | 2 +- cpu/mpc5xx/u-boot.lds | 1 - include/common.h | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/cpu/mpc5xx/config.mk b/cpu/mpc5xx/config.mk index 64cd60071ad..e95b8a1a855 100644 --- a/cpu/mpc5xx/config.mk +++ b/cpu/mpc5xx/config.mk @@ -28,7 +28,7 @@ # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -ffixed-r29 -mpowerpc -msoft-float diff --git a/cpu/mpc5xx/u-boot.lds b/cpu/mpc5xx/u-boot.lds index 5b03fef66c7..10001b1c1de 100644 --- a/cpu/mpc5xx/u-boot.lds +++ b/cpu/mpc5xx/u-boot.lds @@ -59,7 +59,6 @@ SECTIONS cpu/mpc5xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/include/common.h b/include/common.h index d8b6b469e5f..7319c549392 100644 --- a/include/common.h +++ b/include/common.h @@ -63,6 +63,7 @@ typedef volatile unsigned char vu_char; #endif #elif defined(CONFIG_5xx) #include +#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC5xxx) #include #elif defined(CONFIG_MPC8220) -- cgit v1.3.1 From 6f7576b20ecf0d040c3ac3b032b5cbc860e38a90 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:34:29 -0600 Subject: Correct fixup relocation for MPC5xxx Signed-off-by: Grant Likely --- cpu/mpc5xxx/config.mk | 2 +- cpu/mpc5xxx/u-boot-customlayout.lds | 1 - cpu/mpc5xxx/u-boot.lds | 1 - include/common.h | 1 + 4 files changed, 2 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/cpu/mpc5xxx/config.mk b/cpu/mpc5xxx/config.mk index 0df51babd70..0e861c4a0f8 100644 --- a/cpu/mpc5xxx/config.mk +++ b/cpu/mpc5xxx/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 -ffixed-r29 \ -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc5xxx/u-boot-customlayout.lds b/cpu/mpc5xxx/u-boot-customlayout.lds index 123a14c5aa0..11079430d57 100644 --- a/cpu/mpc5xxx/u-boot-customlayout.lds +++ b/cpu/mpc5xxx/u-boot-customlayout.lds @@ -66,7 +66,6 @@ SECTIONS common/environment.o (.ppcenv) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/cpu/mpc5xxx/u-boot.lds b/cpu/mpc5xxx/u-boot.lds index 78818a49ebd..a28a3afc71c 100644 --- a/cpu/mpc5xxx/u-boot.lds +++ b/cpu/mpc5xxx/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS { cpu/mpc5xxx/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/include/common.h b/include/common.h index 7319c549392..a905072ae3c 100644 --- a/include/common.h +++ b/include/common.h @@ -66,6 +66,7 @@ typedef volatile unsigned char vu_char; #define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC5xxx) #include +#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC8220) #include #elif defined(CONFIG_8260) -- cgit v1.3.1 From a85dd254c0577fca13627c46e93fc2ad4c4f1f00 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:34:34 -0600 Subject: Correct fixup relocation for mpc8220 Signed-off-by: Grant Likely --- cpu/mpc8220/config.mk | 2 +- cpu/mpc8220/u-boot.lds | 1 - include/common.h | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/cpu/mpc8220/config.mk b/cpu/mpc8220/config.mk index 8e3ba54287c..c41cafe97fe 100644 --- a/cpu/mpc8220/config.mk +++ b/cpu/mpc8220/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 -ffixed-r29 \ -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc8220/u-boot.lds b/cpu/mpc8220/u-boot.lds index 889bc77d2f8..a199a64f131 100644 --- a/cpu/mpc8220/u-boot.lds +++ b/cpu/mpc8220/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS { cpu/mpc8220/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/include/common.h b/include/common.h index a905072ae3c..93ddfb85eab 100644 --- a/include/common.h +++ b/include/common.h @@ -69,6 +69,7 @@ typedef volatile unsigned char vu_char; #define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_MPC8220) #include +#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_8260) #if defined(CONFIG_MPC8247) \ || defined(CONFIG_MPC8248) \ -- cgit v1.3.1 From f3a52fe05923935db86985daf9438e2f70ac39aa Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:34:39 -0600 Subject: Correct fixup relocation for mpc824x Signed-off-by: Grant Likely --- board/mousse/u-boot.lds | 1 - cpu/mpc824x/config.mk | 2 +- cpu/mpc824x/u-boot.lds | 1 - include/common.h | 2 ++ 4 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds index 57358b8a49d..eb4d8e4e2b6 100644 --- a/board/mousse/u-boot.lds +++ b/board/mousse/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS lib_generic/crc32.o (.text) lib_generic/zlib.o (.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/cpu/mpc824x/config.mk b/cpu/mpc824x/config.mk index 66207f4354d..17fdb21d35a 100644 --- a/cpu/mpc824x/config.mk +++ b/cpu/mpc824x/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -msoft-float diff --git a/cpu/mpc824x/u-boot.lds b/cpu/mpc824x/u-boot.lds index c90d1e9457e..8cbef4aed43 100644 --- a/cpu/mpc824x/u-boot.lds +++ b/cpu/mpc824x/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS { cpu/mpc824x/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/include/common.h b/include/common.h index 93ddfb85eab..4c50053c021 100644 --- a/include/common.h +++ b/include/common.h @@ -70,6 +70,8 @@ typedef volatile unsigned char vu_char; #elif defined(CONFIG_MPC8220) #include #define CONFIG_RELOC_FIXUP_WORKS +#elif defined(CONFIG_824X) +#define CONFIG_RELOC_FIXUP_WORKS #elif defined(CONFIG_8260) #if defined(CONFIG_MPC8247) \ || defined(CONFIG_MPC8248) \ -- cgit v1.3.1 From 5af61b2f4b838a05f79be274f3e5a66edd2d9c96 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:34:44 -0600 Subject: Correct fixup relocation for mpc8260 Signed-off-by: Grant Likely --- board/cogent/u-boot.lds | 1 - board/hymod/u-boot.lds | 1 - board/rsdproto/u-boot.lds | 1 - cpu/mpc8260/config.mk | 2 +- cpu/mpc8260/u-boot.lds | 1 - include/common.h | 1 + 6 files changed, 2 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds index 5ce2694cbf7..d87a39b2496 100644 --- a/board/cogent/u-boot.lds +++ b/board/cogent/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS { *(.text) common/environment.o(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds index 337a3954d2d..9bf0f0938a2 100644 --- a/board/hymod/u-boot.lds +++ b/board/hymod/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS common/environment.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds index 70fc3a5d279..9bd62480952 100644 --- a/board/rsdproto/u-boot.lds +++ b/board/rsdproto/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS { cpu/mpc8260/start.o (.text) *(.text) - *(.fixup) *(.got1) /*. = env_offset; */ } diff --git a/cpu/mpc8260/config.mk b/cpu/mpc8260/config.mk index 683b6fbf2b2..d401e4ca04f 100644 --- a/cpu/mpc8260/config.mk +++ b/cpu/mpc8260/config.mk @@ -21,7 +21,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 -ffixed-r29 \ -mstring -mcpu=603e -mmultiple diff --git a/cpu/mpc8260/u-boot.lds b/cpu/mpc8260/u-boot.lds index 3e84f234d72..b8abc17d413 100644 --- a/cpu/mpc8260/u-boot.lds +++ b/cpu/mpc8260/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS { cpu/mpc8260/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/include/common.h b/include/common.h index 4c50053c021..b224e06976b 100644 --- a/include/common.h +++ b/include/common.h @@ -83,6 +83,7 @@ typedef volatile unsigned char vu_char; #define CONFIG_MPC8260 1 #endif #include +#define CONFIG_RELOC_FIXUP_WORKS #endif #ifdef CONFIG_MPC86xx #include -- cgit v1.3.1 From 057004f4a4863554d56cc56268bfa7c7d9738e27 Mon Sep 17 00:00:00 2001 From: Grant Likely Date: Tue, 3 Jul 2007 00:34:49 -0600 Subject: Correct fixup relocation for mpc83xx Signed-off-by: Grant Likely --- cpu/mpc83xx/config.mk | 2 +- cpu/mpc83xx/u-boot.lds | 1 - include/common.h | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/cpu/mpc83xx/config.mk b/cpu/mpc83xx/config.mk index ecf8a60bbef..2ec395d4ca9 100644 --- a/cpu/mpc83xx/config.mk +++ b/cpu/mpc83xx/config.mk @@ -20,7 +20,7 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \ -ffixed-r2 -ffixed-r29 -msoft-float diff --git a/cpu/mpc83xx/u-boot.lds b/cpu/mpc83xx/u-boot.lds index 937c87a27cd..ca663bc87bf 100644 --- a/cpu/mpc83xx/u-boot.lds +++ b/cpu/mpc83xx/u-boot.lds @@ -52,7 +52,6 @@ SECTIONS { cpu/mpc83xx/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/include/common.h b/include/common.h index b224e06976b..d89617ae2c9 100644 --- a/include/common.h +++ b/include/common.h @@ -96,6 +96,7 @@ typedef volatile unsigned char vu_char; #ifdef CONFIG_MPC83XX #include #include +#define CONFIG_RELOC_FIXUP_WORKS #endif #ifdef CONFIG_4xx #include -- cgit v1.3.1 From 04e6c38b766eaa2f3287561563c9e215e0c3a0d4 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 4 Jul 2007 10:06:30 +0200 Subject: ppc4xx: Update lwmon5 board - Add optional ECC generation routine to preserve existing RAM values. This is needed for the Linux log-buffer support - Add optional DDR2 setup with CL=4 - GPIO50 not used anymore - Lime register setup added Signed-off-by: Stefan Roese --- board/lwmon5/lwmon5.c | 17 +++++++------ board/lwmon5/sdram.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/lwmon5.h | 16 ++++++++++-- 3 files changed, 87 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index d5b8f8c81ba..d916284753d 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -19,9 +19,10 @@ */ #include -#include #include +#include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -220,6 +221,13 @@ int misc_init_r(void) udelay(500); gpio_write_bit(CFG_GPIO_LIME_RST, 1); + /* Lime memory clock adjusted to 133MHz */ + out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ); + /* Wait untill time expired. Because of requirements in lime manual */ + udelay(300); + /* Write lime controller memory parameters */ + out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); + /* * Reset PHY's */ @@ -229,13 +237,6 @@ int misc_init_r(void) gpio_write_bit(CFG_GPIO_PHY0_RST, 1); gpio_write_bit(CFG_GPIO_PHY1_RST, 1); - /* - * Reset USB hub - */ - gpio_write_bit(CFG_GPIO_HUB_RST, 0); - udelay(100); - gpio_write_bit(CFG_GPIO_HUB_RST, 1); - return 0; } diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 85811adadf9..9a4a8eea8fb 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -474,8 +474,27 @@ static void program_ecc(u32 start_address, blank_string(strlen(str)); } else { /* ECC bit set method for cached memory */ +#if 1 /* test-only: will remove this define later, when ECC problems are solved! */ + /* + * Some boards (like lwmon5) need to preserve the memory + * content upon ECC generation (for the log-buffer). + * Therefore we don't fill the memory with a pattern or + * just zero it, but write the same values back that are + * already in the memory cells. + */ + address_increment = CFG_CACHELINE_SIZE; + end_address = current_address + num_bytes; + + current_address = start_address; + while (current_address < end_address) { + ppcDcbi(current_address); + ppcDcbf(current_address); + current_address += CFG_CACHELINE_SIZE; + } +#else dcbz_area(start_address, num_bytes); dflush(); +#endif } sync(); @@ -518,6 +537,8 @@ long int initdram (int board_type) { u32 val; +#if 0 /* test-only: will remove this define later, when ECC problems are solved! */ + /* CL=3 */ mtsdram(DDR0_02, 0x00000000); mtsdram(DDR0_00, 0x0000190A); @@ -558,6 +579,49 @@ long int initdram (int board_type) mtsdram(DDR0_43, 0x030A0200); mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ +#else + /* CL=4 */ + mtsdram(DDR0_02, 0x00000000); + + mtsdram(DDR0_00, 0x0000190A); + mtsdram(DDR0_01, 0x01000000); + mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */ + + mtsdram(DDR0_04, 0x0B030300); + mtsdram(DDR0_05, 0x02020308); + mtsdram(DDR0_06, 0x0003C812); + mtsdram(DDR0_07, 0x00090100); + mtsdram(DDR0_08, 0x03c80001); + mtsdram(DDR0_09, 0x00011D5F); + mtsdram(DDR0_10, 0x00000300); + mtsdram(DDR0_11, 0x000CC800); + mtsdram(DDR0_12, 0x00000003); + mtsdram(DDR0_14, 0x00000000); + mtsdram(DDR0_17, 0x1e000000); + mtsdram(DDR0_18, 0x1e1e1e1e); + mtsdram(DDR0_19, 0x1e1e1e1e); + mtsdram(DDR0_20, 0x0B0B0B0B); + mtsdram(DDR0_21, 0x0B0B0B0B); +#ifdef CONFIG_DDR_ECC + mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */ +#else + mtsdram(DDR0_22, 0x00267F0B); +#endif + + mtsdram(DDR0_23, 0x01000000); + mtsdram(DDR0_24, 0x01010001); + + mtsdram(DDR0_26, 0x2D93028A); + mtsdram(DDR0_27, 0x0784682B); + + mtsdram(DDR0_28, 0x00000080); + mtsdram(DDR0_31, 0x00000000); + mtsdram(DDR0_42, 0x01000008); + + mtsdram(DDR0_43, 0x050A0200); + mtsdram(DDR0_44, 0x00000005); + mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ +#endif wait_for_dlllock(); diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index c6f67fee44e..1d87c73c711 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -326,13 +326,25 @@ #define CFG_EBC_CFG 0xb8400000 +/*----------------------------------------------------------------------- + * Graphics (Fujitsu Lime) + *----------------------------------------------------------------------*/ +/* SDRAM Clock frequency adjustment register */ +#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000 +/* Lime Clock frequency is to set 133MHz */ +#define CFG_LIME_CLOCK_133MHZ 0x10000 + +/* SDRAM Parameter register */ +#define CFG_LIME_MMR 0xC1FCFFFC +/* SDRAM parameter value */ +#define CFG_LIME_MMR_VALUE 0x414FB7F2 + /*----------------------------------------------------------------------- * GPIO Setup *----------------------------------------------------------------------*/ #define CFG_GPIO_PHY1_RST 12 #define CFG_GPIO_FLASH_WP 14 #define CFG_GPIO_PHY0_RST 22 -#define CFG_GPIO_HUB_RST 50 #define CFG_GPIO_WATCHDOG 58 #define CFG_GPIO_LIME_S 59 #define CFG_GPIO_LIME_RST 60 @@ -396,7 +408,7 @@ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \ -- cgit v1.3.1 From f780b83316d9af1f61d71cc88b1917b387b9b995 Mon Sep 17 00:00:00 2001 From: Niklaus Giger Date: Wed, 27 Jun 2007 18:11:38 +0200 Subject: resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPX Signed-off-by: Niklaus Giger --- board/amcc/sequoia/sequoia.c | 9 +++--- board/amcc/sequoia/sequoia.h | 67 -------------------------------------------- include/ppc440.h | 6 ++-- 3 files changed, 8 insertions(+), 74 deletions(-) delete mode 100644 board/amcc/sequoia/sequoia.h (limited to 'include') diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index b4376539503..f823117687e 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -25,7 +25,6 @@ #include #include #include -#include "sequoia.h" DECLARE_GLOBAL_DATA_PTR; @@ -226,7 +225,7 @@ int misc_init_r(void) if (act == NULL || strcmp(act, "hostdev") == 0) { /* SDR Setting */ mfsdr(SDR0_PFC1, sdr0_pfc1); - mfsdr(SDR0_USB0, usb2d0cr); + mfsdr(SDR0_USB2D0CR, usb2d0cr); mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); mfsdr(SDR0_USB2H0CR, usb2h0cr); @@ -254,7 +253,7 @@ int misc_init_r(void) sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/ mtsdr(SDR0_PFC1, sdr0_pfc1); - mtsdr(SDR0_USB0, usb2d0cr); + mtsdr(SDR0_USB2D0CR, usb2d0cr); mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); mtsdr(SDR0_USB2H0CR, usb2h0cr); @@ -298,7 +297,7 @@ int misc_init_r(void) /* SDR Setting */ mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); mfsdr(SDR0_USB2H0CR, usb2h0cr); - mfsdr(SDR0_USB0, usb2d0cr); + mfsdr(SDR0_USB2D0CR, usb2d0cr); mfsdr(SDR0_PFC1, sdr0_pfc1); usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK; @@ -323,7 +322,7 @@ int misc_init_r(void) mtsdr(SDR0_USB2H0CR, usb2h0cr); mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); - mtsdr(SDR0_USB0, usb2d0cr); + mtsdr(SDR0_USB2D0CR, usb2d0cr); mtsdr(SDR0_PFC1, sdr0_pfc1); /*clear resets*/ diff --git a/board/amcc/sequoia/sequoia.h b/board/amcc/sequoia/sequoia.h deleted file mode 100644 index 1d44b164649..00000000000 --- a/board/amcc/sequoia/sequoia.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2006 - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -/*----------------------------------------------------------------------------+ - | EBC Configuration Register - EBC0_CFG - +----------------------------------------------------------------------------*/ -/* External Bus Three-State Control */ -#define EBC0_CFG_EBTC_DRIVEN 0x80000000 -/* Device-Paced Time-out Disable */ -#define EBC0_CFG_PTD_ENABLED 0x00000000 -/* Ready Timeout Count */ -#define EBC0_CFG_RTC_MASK 0x38000000 -#define EBC0_CFG_RTC_16PERCLK 0x00000000 -#define EBC0_CFG_RTC_32PERCLK 0x08000000 -#define EBC0_CFG_RTC_64PERCLK 0x10000000 -#define EBC0_CFG_RTC_128PERCLK 0x18000000 -#define EBC0_CFG_RTC_256PERCLK 0x20000000 -#define EBC0_CFG_RTC_512PERCLK 0x28000000 -#define EBC0_CFG_RTC_1024PERCLK 0x30000000 -#define EBC0_CFG_RTC_2048PERCLK 0x38000000 -/* External Master Priority Low */ -#define EBC0_CFG_EMPL_LOW 0x00000000 -#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000 -#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000 -#define EBC0_CFG_EMPL_HIGH 0x06000000 -/* External Master Priority High */ -#define EBC0_CFG_EMPH_LOW 0x00000000 -#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000 -#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000 -#define EBC0_CFG_EMPH_HIGH 0x01800000 -/* Chip Select Three-State Control */ -#define EBC0_CFG_CSTC_DRIVEN 0x00400000 -/* Burst Prefetch */ -#define EBC0_CFG_BPF_ONEDW 0x00000000 -#define EBC0_CFG_BPF_TWODW 0x00100000 -#define EBC0_CFG_BPF_FOURDW 0x00200000 -/* External Master Size */ -#define EBC0_CFG_EMS_8BIT 0x00000000 -/* Power Management Enable */ -#define EBC0_CFG_PME_DISABLED 0x00000000 -#define EBC0_CFG_PME_ENABLED 0x00020000 -/* Power Management Timer */ -#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) - -#define SDR0_USB0 0x0320 /* USB Control Register */ diff --git a/include/ppc440.h b/include/ppc440.h index 76330f16ac6..61c937d9f9d 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -1025,7 +1025,7 @@ #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define SDR_USB2D0CR 0x0320 +#define SDR0_USB2D0CR 0x0320 #define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */ #define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */ #define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */ @@ -1423,7 +1423,7 @@ #define uicvr uic0vr #define uicvcr uic0vcr -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) /*----------------------------------------------------------------------------+ | Clock / Power-on-reset DCR's. +----------------------------------------------------------------------------*/ @@ -1492,9 +1492,11 @@ #define CPR0_OPBD_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) #define CPR0_PERD 0xE0 +#if !defined(CONFIG_440EPX) #define CPR0_PERD_PERDV0_MASK 0x03000000 #define CPR0_PERD_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) #define CPR0_PERD_PERDV0_DECODE(n) ((((((unsigned long)(n))>>24)-1)&0x03)+1) +#endif #define CPR0_MALD 0x100 #define CPR0_MALD_MALDV0_MASK 0x03000000 -- cgit v1.3.1 From 2835e518c969e5124ba1174eef3e8375e12fa7d5 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 13 Jun 2007 13:22:08 -0500 Subject: include/configs: Use new CONFIG_CMD_* in 85xx board config files. Signed-off-by: Jon Loeliger --- include/configs/MPC8540ADS.h | 49 +++++++++++++--------------------- include/configs/MPC8540EVAL.h | 36 ++++++++++++------------- include/configs/MPC8541CDS.h | 28 ++++++++++---------- include/configs/MPC8544DS.h | 33 +++++++++++------------ include/configs/MPC8548CDS.h | 28 ++++++++++---------- include/configs/MPC8555CDS.h | 28 ++++++++++---------- include/configs/MPC8560ADS.h | 61 +++++++++++++++---------------------------- include/configs/MPC8568MDS.h | 29 ++++++++++---------- include/configs/PM854.h | 58 +++++++++++++++------------------------- include/configs/PM856.h | 55 ++++++++++++++------------------------ include/configs/SBC8540.h | 46 ++++++++++++++++---------------- include/configs/TQM85xx.h | 38 ++++++++++++++------------- include/configs/sbc8560.h | 44 +++++++++++++++---------------- include/configs/stxgp3.h | 51 ++++++++++++++++-------------------- include/configs/stxssa.h | 46 +++++++++++++++----------------- 15 files changed, 280 insertions(+), 350 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 9176be388e6..f103e47925e 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -407,37 +407,24 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + #if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #else - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #else - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #endif -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -448,7 +435,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -469,7 +456,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -481,7 +468,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index b568cb4df75..dea061abee9 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -259,26 +259,24 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \ - | CFG_CMD_PCI | CFG_CMD_I2C ) & \ - ~(CFG_CMD_ENV | CFG_CMD_LOADS )) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \ - | CFG_CMD_I2C ) & \ - ~(CFG_CMD_ENV | CFG_CMD_LOADS )) -#endif -#else + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C + #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \ - | CFG_CMD_PING | CFG_CMD_I2C ) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) + #define CONFIG_CMD_PCI #endif + +#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #endif -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -288,7 +286,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -308,7 +306,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -320,7 +318,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index e047e259a5b..5f12eeecc51 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -401,19 +401,19 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII + #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) + #define CONFIG_CMD_PCI #endif -#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -423,7 +423,7 @@ extern unsigned long get_clock_freq(void); #define CFG_LONGHELP /* undef to save memory */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -443,7 +443,7 @@ extern unsigned long get_clock_freq(void); /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -455,7 +455,7 @@ extern unsigned long get_clock_freq(void); #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 7cd62e95a91..b33d2255b39 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -392,21 +392,22 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII + #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII \ - | CFG_CMD_BEDBUG \ - | CFG_CMD_NET) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) + #define CONFIG_CMD_PCI + #define CONFIG_CMD_BEDBUG + #define CONFIG_CMD_NET #endif -#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -416,7 +417,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_LONGHELP /* undef to save memory */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -436,7 +437,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -448,7 +449,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a0d291eef48..cef92d2540d 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -427,19 +427,19 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII + #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) + #define CONFIG_CMD_PCI #endif -#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -449,7 +449,7 @@ extern unsigned long get_clock_freq(void); #define CFG_LONGHELP /* undef to save memory */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -469,7 +469,7 @@ extern unsigned long get_clock_freq(void); /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -481,7 +481,7 @@ extern unsigned long get_clock_freq(void); #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index b7e703ca183..077aaa37713 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -401,19 +401,19 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII + #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) + #define CONFIG_CMD_PCI #endif -#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -423,7 +423,7 @@ extern unsigned long get_clock_freq(void); #define CFG_LONGHELP /* undef to save memory */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -443,7 +443,7 @@ extern unsigned long get_clock_freq(void); /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -455,7 +455,7 @@ extern unsigned long get_clock_freq(void); #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 043397fc21b..affe535e717 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -432,46 +432,27 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + +#if defined(CONFIG_ETHER_ON_FCC) + #define CONFIG_CMD_MII +#endif + #if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #elif defined(CONFIG_TSEC_ENET) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & ~(CFG_CMD_ENV)) - #elif defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & ~(CFG_CMD_ENV)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #elif defined(CONFIG_TSEC_ENET) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #elif defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #endif -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -482,7 +463,7 @@ #define CFG_LOAD_ADDR 0x1000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -503,7 +484,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -515,7 +496,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 0ff0416138d..41b1ae1206c 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -383,19 +383,20 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII + #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) + #define CONFIG_CMD_PCI #endif -#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -405,7 +406,7 @@ extern unsigned long get_clock_freq(void); #define CFG_LONGHELP /* undef to save memory */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -425,7 +426,7 @@ extern unsigned long get_clock_freq(void); /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -437,7 +438,7 @@ extern unsigned long get_clock_freq(void); #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 8f130f5ccd8..d79dd768f90 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -303,43 +303,27 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_EEPROM + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + #if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #else - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_EEPROM \ - | CFG_CMD_DATE \ - | CFG_CMD_MII \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #else - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_EEPROM \ - | CFG_CMD_DATE \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #endif -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -350,7 +334,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -372,7 +356,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -384,7 +368,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 0286b53e017..5681d433692 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -306,41 +306,26 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DATE +#define CONFIG_CMD_EEPROM + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + #if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #else - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_EEPROM \ - | CFG_CMD_DATE \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #else - #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_EEPROM \ - | CFG_CMD_DATE \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) - #endif + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #endif -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -351,7 +336,7 @@ #define CFG_LOAD_ADDR 0x1000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -373,7 +358,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -385,7 +370,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index f8e3397a3f0..a5397c2e08b 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -338,28 +338,28 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV | \ - CFG_CMD_LOADS )) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) - #endif + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) + #define CONFIG_CMD_MII +#endif + +#if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #endif -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -368,7 +368,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "SBC8540=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -389,7 +389,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -401,7 +401,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index b0b9dd3ab89..b17d5e30fc9 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -357,24 +357,26 @@ #define CONFIG_TIMESTAMP /* Print image info with ts */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_DTT +#define CONFIG_CMD_MII + #if defined(CONFIG_PCI) -# define ADD_PCI_CMD (CFG_CMD_PCI) -#else -# define ADD_PCI_CMD 0 + #define CONFIG_CMD_PCI #endif -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP | \ - ADD_PCI_CMD | \ - CFG_CMD_I2C | \ - CFG_CMD_DATE | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DTT | \ - CFG_CMD_MII | \ - CFG_CMD_PING ) -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -385,7 +387,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -406,7 +408,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ #endif @@ -418,7 +420,7 @@ #define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 6e4fdb2498e..ad610f031a6 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -320,28 +320,28 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) + #define CONFIG_CMD_MII +#endif + #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV | \ - CFG_CMD_LOADS )) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV)) - #endif -#else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) - #elif (defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) - #endif + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #endif -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -350,7 +350,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "SBC8560=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -371,7 +371,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -383,7 +383,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 21065b9d05c..9c55844dfe8 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -298,34 +298,29 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C + #if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV | \ - CFG_CMD_LOADS )) - #elif defined(CONFIG_TSEC_ENET) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \ - CFG_CMD_MII | CFG_CMD_I2C ) & \ - ~(CFG_CMD_ENV)) - #elif defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV)) - #endif + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C) - #elif defined(CONFIG_TSEC_ENET) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \ - CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C) - #elif defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C) - #endif + #define CONFIG_CMD_ELF +#endif + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI #endif -#include + +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) + #define CONFIG_CMD_MII +#endif + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -334,7 +329,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "GPPP=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -355,7 +350,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -367,7 +362,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index a14cd50dd34..c88d534fcc6 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -325,34 +325,30 @@ #define CONFIG_TIMESTAMP /* Print image info with ts */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C + +#if defined(CONFIG_PCI) + #define CONFIG_CMD_PCI +#endif + +#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) + #define CONFIG_CMD_MII +#endif + #if defined(CFG_RAMBOOT) - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV | \ - CFG_CMD_LOADS )) - #elif defined(CONFIG_TSEC_ENET) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | \ - CFG_CMD_MII | CFG_CMD_I2C ) & \ - ~(CFG_CMD_ENV)) - #elif defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_PING | CFG_CMD_I2C) & \ - ~(CFG_CMD_ENV)) - #endif + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #else - #if defined(CONFIG_PCI) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | \ - CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C) - #elif defined(CONFIG_TSEC_ENET) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | \ - CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_I2C) - #elif defined(CONFIG_ETHER_ON_FCC) - #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MII | \ - CFG_CMD_ELF | CFG_CMD_PING | CFG_CMD_I2C) - #endif + #define CONFIG_CMD_ELF #endif -#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ -- cgit v1.3.1 From b44896215a09c60fa40cae906f7ed207bbc2c492 Mon Sep 17 00:00:00 2001 From: Sergei Poselenov Date: Thu, 5 Jul 2007 08:17:37 +0200 Subject: Merged POST framework with the current TOT. Signed-off-by: Sergei Poselenov --- Makefile | 2 + cpu/ppc4xx/start.S | 8 + include/configs/sequoia.h | 4 + include/ppc440.h | 2 - post/cpu/mpc8xx/Makefile | 2 +- post/cpu/mpc8xx/cache.c | 81 ++++++ post/cpu/ppc4xx/Makefile | 3 +- post/cpu/ppc4xx/cache.c | 114 ++++++++ post/cpu/ppc4xx/cache_4xx.S | 448 ++++++++++++++++++++++++++++++ post/cpu/ppc4xx/ether.c | 395 ++++++++++++++++++++++++++ post/cpu/ppc4xx/fpu.c | 10 +- post/cpu/ppc4xx/spr.c | 41 +-- post/cpu/ppc4xx/uart.c | 3 +- post/cpu/ppc4xx/watchdog.c | 9 +- post/drivers/Makefile | 2 +- post/drivers/cache.c | 81 ------ post/lib_ppc/Makefile | 1 + post/lib_ppc/fpu/20001122-1.c | 62 +++++ post/lib_ppc/fpu/20010114-2.c | 66 +++++ post/lib_ppc/fpu/20010226-1.c | 54 ++++ post/lib_ppc/fpu/980619-1.c | 60 ++++ post/lib_ppc/fpu/Makefile | 32 +++ post/lib_ppc/fpu/acc1.c | 57 ++++ post/lib_ppc/fpu/compare-fp-1.c | 225 +++++++++++++++ post/lib_ppc/fpu/fpu.c | 92 ++++++ post/lib_ppc/fpu/mul-subnormal-single-1.c | 103 +++++++ 26 files changed, 1847 insertions(+), 110 deletions(-) create mode 100644 post/cpu/mpc8xx/cache.c create mode 100644 post/cpu/ppc4xx/cache.c create mode 100644 post/cpu/ppc4xx/cache_4xx.S create mode 100644 post/cpu/ppc4xx/ether.c delete mode 100644 post/drivers/cache.c create mode 100644 post/lib_ppc/fpu/20001122-1.c create mode 100644 post/lib_ppc/fpu/20010114-2.c create mode 100644 post/lib_ppc/fpu/20010226-1.c create mode 100644 post/lib_ppc/fpu/980619-1.c create mode 100644 post/lib_ppc/fpu/Makefile create mode 100644 post/lib_ppc/fpu/acc1.c create mode 100644 post/lib_ppc/fpu/compare-fp-1.c create mode 100644 post/lib_ppc/fpu/fpu.c create mode 100644 post/lib_ppc/fpu/mul-subnormal-single-1.c (limited to 'include') diff --git a/Makefile b/Makefile index 2d8cff3ffa4..626283f708b 100644 --- a/Makefile +++ b/Makefile @@ -214,6 +214,8 @@ LIBS += drivers/sk98lin/libsk98lin.a LIBS += post/libpost.a post/drivers/libpostdrivers.a LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \ "post/lib_$(ARCH)/libpost$(ARCH).a"; fi) +LIBS += $(shell if [ -d post/lib_$(ARCH)/fpu ]; then echo \ + "post/lib_$(ARCH)/fpu/libpost$(ARCH)fpu.a"; fi) LIBS += $(shell if [ -d post/cpu/$(CPU) ]; then echo \ "post/cpu/$(CPU)/libpost$(CPU).a"; fi) LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \ diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index dfe813c3f45..6086b6ceae4 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1217,15 +1217,23 @@ mck_return: * NOTE: currently the 440s run with dcache _disabled_ once relocated to DRAM, * although for some cache-ralated calls stubs have to be provided to satisfy * symbols resolution. + * Icache-related functions are used in POST framework. * */ #ifdef CONFIG_440 .globl dcache_disable + .globl icache_disable + .globl icache_enable dcache_disable: +icache_disable: +icache_enable: blr .globl dcache_status + .globl icache_status dcache_status: +icache_status: + mr r3, 0 blr #else flush_dcache: diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 44bc9555194..32199929a97 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -334,10 +334,14 @@ CFG_POST_CPU | \ CFG_POST_UART | \ CFG_POST_I2C | \ + CFG_POST_CACHE | \ + CFG_POST_FPU | \ + CFG_POST_ETHER | \ CFG_POST_SPR) #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) #define CONFIG_LOGBUFFER +#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */ #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ diff --git a/include/ppc440.h b/include/ppc440.h index 61c937d9f9d..93c10f12099 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -282,7 +282,6 @@ #define sdr_sdstp3 0x4003 #endif /* CONFIG_440GX */ -#ifdef CONFIG_440 /*----------------------------------------------------------------------------+ | Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). +----------------------------------------------------------------------------*/ @@ -306,7 +305,6 @@ #define MMUCR_IULXE 0x00400000 #define MMUCR_STS 0x00100000 #define MMUCR_STID_MASK 0x000000FF -#endif /* CONFIG_440 */ #ifdef CONFIG_440SPE #undef sdr_sdstp2 diff --git a/post/cpu/mpc8xx/Makefile b/post/cpu/mpc8xx/Makefile index 9dd3f0fce9b..f871cbab649 100644 --- a/post/cpu/mpc8xx/Makefile +++ b/post/cpu/mpc8xx/Makefile @@ -24,6 +24,6 @@ LIB = libpostmpc8xx.a AOBJS = cache_8xx.o -COBJS = ether.o spr.o uart.o usb.o watchdog.o +COBJS = cache.o ether.o spr.o uart.o usb.o watchdog.o include $(TOPDIR)/post/rules.mk diff --git a/post/cpu/mpc8xx/cache.c b/post/cpu/mpc8xx/cache.c new file mode 100644 index 00000000000..501465c06a1 --- /dev/null +++ b/post/cpu/mpc8xx/cache.c @@ -0,0 +1,81 @@ +/* + * (C) Copyright 2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* Cache test + * + * This test verifies the CPU data and instruction cache using + * several test scenarios. + */ + +#ifdef CONFIG_POST + +#include +#include + +#if CONFIG_POST & CFG_POST_CACHE + +#define CACHE_POST_SIZE 1024 + +extern int cache_post_test1 (char *, unsigned int); +extern int cache_post_test2 (char *, unsigned int); +extern int cache_post_test3 (char *, unsigned int); +extern int cache_post_test4 (char *, unsigned int); +extern int cache_post_test5 (void); +extern int cache_post_test6 (void); + +int cache_post_test (int flags) +{ + int ints = disable_interrupts (); + int res = 0; + static char ta[CACHE_POST_SIZE + 0xf]; + char *testarea = (char *) (((unsigned long) ta + 0xf) & ~0xf); + + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test1 (testarea, CACHE_POST_SIZE); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test2 (testarea, CACHE_POST_SIZE); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test3 (testarea, CACHE_POST_SIZE); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test4 (testarea, CACHE_POST_SIZE); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test5 (); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test6 (); + + WATCHDOG_RESET (); + if (ints) + enable_interrupts (); + return res; +} + +#endif /* CONFIG_POST & CFG_POST_CACHE */ +#endif /* CONFIG_POST */ diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile index 8e8ab50577a..f1034dac249 100644 --- a/post/cpu/ppc4xx/Makefile +++ b/post/cpu/ppc4xx/Makefile @@ -23,6 +23,7 @@ LIB = libpostppc4xx.a -COBJS = fpu.o spr.o uart.o watchdog.o +AOBJS = cache_4xx.o +COBJS = cache.o ether.o fpu.o spr.o uart.o watchdog.o include $(TOPDIR)/post/rules.mk diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c new file mode 100644 index 00000000000..e1f989ed937 --- /dev/null +++ b/post/cpu/ppc4xx/cache.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Author: Igor Lisitsin + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* Cache test + * + * This test verifies the CPU data and instruction cache using + * several test scenarios. + */ + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_CACHE + +#include +#include + +#define CACHE_POST_SIZE 1024 + +void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); + +int cache_post_test1 (int tlb, void *p, int size); +int cache_post_test2 (int tlb, void *p, int size); +int cache_post_test3 (int tlb, void *p, int size); +int cache_post_test4 (int tlb, void *p, int size); +int cache_post_test5 (int tlb, void *p, int size); +int cache_post_test6 (int tlb, void *p, int size); + +static int tlb = -1; /* index to the victim TLB entry */ + +static unsigned char testarea[CACHE_POST_SIZE] +__attribute__((__aligned__(CACHE_POST_SIZE))); + +int cache_post_test (int flags) +{ + void* virt = (void*)CFG_POST_CACHE_ADDR; + int ints, i, res = 0; + u32 word0; + + if (tlb < 0) { + /* + * Allocate a new TLB entry, since we are going to modify + * the write-through and caching inhibited storage attributes. + */ + program_tlb((u32)testarea, (u32)virt, + CACHE_POST_SIZE, TLB_WORD2_I_ENABLE); + + /* Find the TLB entry */ + for (i = 0;; i++) { + if (i >= PPC4XX_TLB_SIZE) { + printf ("Failed to program tlb entry\n"); + return -1; + } + word0 = mftlb1(i); + if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) { + tlb = i; + break; + } + } + } + ints = disable_interrupts (); + + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE); + WATCHDOG_RESET (); + if (res == 0) + res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE); + + if (ints) + enable_interrupts (); + + return res; +} + +#endif /* CONFIG_POST & CFG_POST_CACHE */ +#endif /* CONFIG_POST */ diff --git a/post/cpu/ppc4xx/cache_4xx.S b/post/cpu/ppc4xx/cache_4xx.S new file mode 100644 index 00000000000..785b8d60b93 --- /dev/null +++ b/post/cpu/ppc4xx/cache_4xx.S @@ -0,0 +1,448 @@ +/* + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Author: Igor Lisitsin + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#ifdef CONFIG_POST + +#include +#include +#include +#include +#include + +#if CONFIG_POST & CFG_POST_CACHE + + .text + +/* void cache_post_disable (int tlb) + */ +cache_post_disable: + tlbre r0, r3, 0x0002 + ori r0, r0, TLB_WORD2_I_ENABLE@l + tlbwe r0, r3, 0x0002 + sync + isync + blr + +/* void cache_post_wt (int tlb) + */ +cache_post_wt: + tlbre r0, r3, 0x0002 + ori r0, r0, TLB_WORD2_W_ENABLE@l + andi. r0, r0, ~TLB_WORD2_I_ENABLE@l + tlbwe r0, r3, 0x0002 + sync + isync + blr + +/* void cache_post_wb (int tlb) + */ +cache_post_wb: + tlbre r0, r3, 0x0002 + andi. r0, r0, ~TLB_WORD2_W_ENABLE@l + andi. r0, r0, ~TLB_WORD2_I_ENABLE@l + tlbwe r0, r3, 0x0002 + sync + isync + blr + +/* void cache_post_dinvalidate (void *p, int size) + */ +cache_post_dinvalidate: + dcbi r0, r3 + addi r3, r3, CFG_CACHELINE_SIZE + subic. r4, r4, CFG_CACHELINE_SIZE + bgt cache_post_dinvalidate + sync + blr + +/* void cache_post_dstore (void *p, int size) + */ +cache_post_dstore: + dcbst r0, r3 + addi r3, r3, CFG_CACHELINE_SIZE + subic. r4, r4, CFG_CACHELINE_SIZE + bgt cache_post_dstore + sync + blr + +/* void cache_post_dtouch (void *p, int size) + */ +cache_post_dtouch: + dcbt r0, r3 + addi r3, r3, CFG_CACHELINE_SIZE + subic. r4, r4, CFG_CACHELINE_SIZE + bgt cache_post_dtouch + sync + blr + +/* void cache_post_iinvalidate (void) + */ +cache_post_iinvalidate: + iccci r0, r0 + sync + blr + +/* void cache_post_memset (void *p, int val, int size) + */ +cache_post_memset: + mtctr r5 +1: + stb r4, 0(r3) + addi r3, r3, 1 + bdnz 1b + blr + +/* int cache_post_check (void *p, int size) + */ +cache_post_check: + mtctr r4 +1: + lbz r0, 0(r3) + addi r3, r3, 1 + cmpwi r0, 0xff + bne 2f + bdnz 1b + li r3, 0 + blr +2: + li r3, -1 + blr + +#define CACHE_POST_DISABLE() \ + mr r3, r10; \ + bl cache_post_disable + +#define CACHE_POST_WT() \ + mr r3, r10; \ + bl cache_post_wt + +#define CACHE_POST_WB() \ + mr r3, r10; \ + bl cache_post_wb + +#define CACHE_POST_DINVALIDATE() \ + mr r3, r11; \ + mr r4, r12; \ + bl cache_post_dinvalidate + +#define CACHE_POST_DFLUSH() \ + mr r3, r11; \ + mr r4, r12; \ + bl cache_post_dflush + +#define CACHE_POST_DSTORE() \ + mr r3, r11; \ + mr r4, r12; \ + bl cache_post_dstore + +#define CACHE_POST_DTOUCH() \ + mr r3, r11; \ + mr r4, r12; \ + bl cache_post_dtouch + +#define CACHE_POST_IINVALIDATE() \ + bl cache_post_iinvalidate + +#define CACHE_POST_MEMSET(val) \ + mr r3, r11; \ + li r4, val; \ + mr r5, r12; \ + bl cache_post_memset + +#define CACHE_POST_CHECK() \ + mr r3, r11; \ + mr r4, r12; \ + bl cache_post_check; \ + mr r13, r3 + +/* + * Write and read 0xff pattern with caching enabled. + */ + .global cache_post_test1 +cache_post_test1: + mflr r9 + mr r10, r3 /* tlb */ + mr r11, r4 /* p */ + mr r12, r5 /* size */ + + CACHE_POST_WB() + CACHE_POST_DINVALIDATE() + + /* Write the negative pattern to the test area */ + CACHE_POST_MEMSET(0xff) + + /* Read the test area */ + CACHE_POST_CHECK() + + CACHE_POST_DINVALIDATE() + CACHE_POST_DISABLE() + + mr r3, r13 + mtlr r9 + blr + +/* + * Write zeroes with caching enabled. + * Write 0xff pattern with caching disabled. + * Read 0xff pattern with caching enabled. + */ + .global cache_post_test2 +cache_post_test2: + mflr r9 + mr r10, r3 /* tlb */ + mr r11, r4 /* p */ + mr r12, r5 /* size */ + + CACHE_POST_WB() + CACHE_POST_DINVALIDATE() + + /* Write the zero pattern to the test area */ + CACHE_POST_MEMSET(0) + + CACHE_POST_DINVALIDATE() + CACHE_POST_DISABLE() + + /* Write the negative pattern to the test area */ + CACHE_POST_MEMSET(0xff) + + CACHE_POST_WB() + + /* Read the test area */ + CACHE_POST_CHECK() + + CACHE_POST_DINVALIDATE() + CACHE_POST_DISABLE() + + mr r3, r13 + mtlr r9 + blr + +/* + * Write-through mode test. + * Write zeroes, store the cache, write 0xff pattern. + * Invalidate the cache. + * Check that 0xff pattern is read. + */ + .global cache_post_test3 +cache_post_test3: + mflr r9 + mr r10, r3 /* tlb */ + mr r11, r4 /* p */ + mr r12, r5 /* size */ + + CACHE_POST_WT() + CACHE_POST_DINVALIDATE() + + /* Cache the test area */ + CACHE_POST_DTOUCH() + + /* Write the zero pattern to the test area */ + CACHE_POST_MEMSET(0) + + CACHE_POST_DSTORE() + + /* Write the negative pattern to the test area */ + CACHE_POST_MEMSET(0xff) + + CACHE_POST_DINVALIDATE() + CACHE_POST_DISABLE() + + /* Read the test area */ + CACHE_POST_CHECK() + + mr r3, r13 + mtlr r9 + blr + +/* + * Write-back mode test. + * Write 0xff pattern, store the cache, write zeroes. + * Invalidate the cache. + * Check that 0xff pattern is read. + */ + .global cache_post_test4 +cache_post_test4: + mflr r9 + mr r10, r3 /* tlb */ + mr r11, r4 /* p */ + mr r12, r5 /* size */ + + CACHE_POST_WB() + CACHE_POST_DINVALIDATE() + + /* Cache the test area */ + CACHE_POST_DTOUCH() + + /* Write the negative pattern to the test area */ + CACHE_POST_MEMSET(0xff) + + CACHE_POST_DSTORE() + + /* Write the zero pattern to the test area */ + CACHE_POST_MEMSET(0) + + CACHE_POST_DINVALIDATE() + CACHE_POST_DISABLE() + + /* Read the test area */ + CACHE_POST_CHECK() + + mr r3, r13 + mtlr r9 + blr + +/* + * Load the test instructions into the instruction cache. + * Replace the test instructions. + * Check that the original instructions are executed. + */ + .global cache_post_test5 +cache_post_test5: + mflr r9 + mr r10, r3 /* tlb */ + mr r11, r4 /* p */ + mr r12, r5 /* size */ + + CACHE_POST_WT() + CACHE_POST_IINVALIDATE() + + /* Compute r13 = cache_post_test_inst */ + bl cache_post_test5_reloc +cache_post_test5_reloc: + mflr r13 + lis r0, (cache_post_test_inst - cache_post_test5_reloc)@h + ori r0, r0, (cache_post_test_inst - cache_post_test5_reloc)@l + add r13, r13, r0 + + /* Copy the test instructions to the test area */ + lwz r0, 0(r13) + stw r0, 0(r11) + lwz r0, 8(r13) + stw r0, 4(r11) + sync + + /* Invalidate the cache line */ + icbi r0, r11 + sync + isync + + /* Execute the test instructions */ + mtlr r11 + blrl + + /* Replace the test instruction */ + lwz r0, 4(r13) + stw r0, 0(r11) + sync + + /* Do not invalidate the cache line */ + isync + + /* Execute the test instructions */ + mtlr r11 + blrl + mr r13, r3 + + CACHE_POST_IINVALIDATE() + CACHE_POST_DINVALIDATE() + CACHE_POST_DISABLE() + + mr r3, r13 + mtlr r9 + blr + +/* + * Load the test instructions into the instruction cache. + * Replace the test instructions and invalidate the cache. + * Check that the replaced instructions are executed. + */ + .global cache_post_test6 +cache_post_test6: + mflr r9 + mr r10, r3 /* tlb */ + mr r11, r4 /* p */ + mr r12, r5 /* size */ + + CACHE_POST_WT() + CACHE_POST_IINVALIDATE() + + /* Compute r13 = cache_post_test_inst */ + bl cache_post_test6_reloc +cache_post_test6_reloc: + mflr r13 + lis r0, (cache_post_test_inst - cache_post_test6_reloc)@h + ori r0, r0, (cache_post_test_inst - cache_post_test6_reloc)@l + add r13, r13, r0 + + /* Copy the test instructions to the test area */ + lwz r0, 4(r13) + stw r0, 0(r11) + lwz r0, 8(r13) + stw r0, 4(r11) + sync + + /* Invalidate the cache line */ + icbi r0, r11 + sync + isync + + /* Execute the test instructions */ + mtlr r11 + blrl + + /* Replace the test instruction */ + lwz r0, 0(r13) + stw r0, 0(r11) + sync + + /* Invalidate the cache line */ + icbi r0, r11 + sync + isync + + /* Execute the test instructions */ + mtlr r11 + blrl + mr r13, r3 + + CACHE_POST_IINVALIDATE() + CACHE_POST_DINVALIDATE() + CACHE_POST_DISABLE() + + mr r3, r13 + mtlr r9 + blr + +/* Test instructions. + */ +cache_post_test_inst: + li r3, 0 + li r3, -1 + blr + +#endif /* CONFIG_POST & CFG_POST_CACHE */ +#endif /* CONFIG_POST */ diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c new file mode 100644 index 00000000000..391c815d7ae --- /dev/null +++ b/post/cpu/ppc4xx/ether.c @@ -0,0 +1,395 @@ +/* + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Author: Igor Lisitsin + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * Ethernet test + * + * The Ethernet Media Access Controllers (EMAC) are tested in the + * internal loopback mode. + * The controllers are configured accordingly and several packets + * are transmitted. The configurable test parameters are: + * MIN_PACKET_LENGTH - minimum size of packet to transmit + * MAX_PACKET_LENGTH - maximum size of packet to transmit + * TEST_NUM - number of tests + */ + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_ETHER + +#include +#include +#include +#include <405_mal.h> +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) +#endif + +#define MIN_PACKET_LENGTH 64 +#define MAX_PACKET_LENGTH 256 +#define TEST_NUM 1 + +static volatile mal_desc_t tx __cacheline_aligned; +static volatile mal_desc_t rx __cacheline_aligned; +static char *tx_buf; +static char *rx_buf; + +static void ether_post_init (int devnum, int hw_addr) +{ + int i; + unsigned mode_reg; +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) + sys_info_t sysinfo; +#endif +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE) + unsigned long mfr; +#endif + +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) + /* Need to get the OPB frequency so we can access the PHY */ + get_sys_info (&sysinfo); +#endif + +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + /* provide clocks for EMAC internal loopback */ + mfsdr (sdr_mfr, mfr); + mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum); + mtsdr (sdr_mfr, mfr); + sync (); +#endif + /* reset emac */ + out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST); + sync (); + + for (i = 0;; i++) { + if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST)) + break; + if (i >= 1000) { + printf ("Timeout resetting EMAC\n"); + break; + } + udelay (1000); + } +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) + /* Whack the M1 register */ + mode_reg = 0x0; + if (sysinfo.freqOPB <= 50000000); + else if (sysinfo.freqOPB <= 66666667) + mode_reg |= EMAC_M1_OBCI_66; + else if (sysinfo.freqOPB <= 83333333) + mode_reg |= EMAC_M1_OBCI_83; + else if (sysinfo.freqOPB <= 100000000) + mode_reg |= EMAC_M1_OBCI_100; + else + mode_reg |= EMAC_M1_OBCI_GT100; + + out32 (EMAC_M1 + hw_addr, mode_reg); + +#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ + + /* set the Mal configuration reg */ +#if defined(CONFIG_440GX) || \ + defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) + mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | + MAL_CR_PLBLT_DEFAULT | 0x00330000); +#else + mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); + /* Errata 1.12: MAL_1 -- Disable MAL bursting */ + if (get_pvr() == PVR_440GP_RB) { + mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB); + } +#endif + /* setup buffer descriptors */ + tx.ctrl = MAL_TX_CTRL_WRAP; + tx.data_len = 0; + tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf); + + rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY; + rx.data_len = 0; + rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf); + + switch (devnum) { + case 1: + /* setup MAL tx & rx channel pointers */ +#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) + mtdcr (maltxctp2r, &tx); +#else + mtdcr (maltxctp1r, &tx); +#endif +#if defined(CONFIG_440) + mtdcr (maltxbattr, 0x0); + mtdcr (malrxbattr, 0x0); +#endif + mtdcr (malrxctp1r, &rx); + /* set RX buffer size */ + mtdcr (malrcbs1, PKTSIZE_ALIGN / 16); + break; + case 0: + default: + /* setup MAL tx & rx channel pointers */ +#if defined(CONFIG_440) + mtdcr (maltxbattr, 0x0); + mtdcr (malrxbattr, 0x0); +#endif + mtdcr (maltxctp0r, &tx); + mtdcr (malrxctp0r, &rx); + /* set RX buffer size */ + mtdcr (malrcbs0, PKTSIZE_ALIGN / 16); + break; + } + + /* Enable MAL transmit and receive channels */ +#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) + mtdcr (maltxcasr, (MAL_TXRX_CASR >> (devnum*2))); +#else + mtdcr (maltxcasr, (MAL_TXRX_CASR >> devnum)); +#endif + mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum)); + + /* set internal loopback mode */ + out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE | + EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | + EMAC_M1_MF_100MBPS | EMAC_M1_IST | + in32 (EMAC_M1)); + + /* set transmit enable & receive enable */ + out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); + + /* enable broadcast address */ + out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE); + + /* set transmit request threshold register */ + out32 (EMAC_TRTR + hw_addr, 0x18000000); /* 256 byte threshold */ + + /* set receive low/high water mark register */ +#if defined(CONFIG_440) + /* 440s has a 64 byte burst length */ + out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000); +#else + /* 405s have a 16 byte burst length */ + out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000); +#endif /* defined(CONFIG_440) */ + out32 (EMAC_TXM1 + hw_addr, 0xf8640000); + + /* Set fifo limit entry in tx mode 0 */ + out32 (EMAC_TXM0 + hw_addr, 0x00000003); + /* Frame gap set */ + out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008); + sync (); +} + +static void ether_post_halt (int devnum, int hw_addr) +{ + int i = 0; +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + unsigned long mfr; +#endif + + /* 1st reset MAL channel */ + /* Note: writing a 0 to a channel has no effect */ +#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) + mtdcr (maltxcarr, MAL_TXRX_CASR >> (devnum * 2)); +#else + mtdcr (maltxcarr, MAL_TXRX_CASR >> devnum); +#endif + mtdcr (malrxcarr, MAL_TXRX_CASR >> devnum); + + /* wait for reset */ + while (mfdcr (malrxcasr) & (MAL_TXRX_CASR >> devnum)) { + if (i++ >= 1000) + break; + udelay (1000); + } + /* emac reset */ + out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST); + +#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) + /* remove clocks for EMAC internal loopback */ + mfsdr (sdr_mfr, mfr); + mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum); + mtsdr (sdr_mfr, mfr); +#endif +} + +static void ether_post_send (int devnum, int hw_addr, void *packet, int length) +{ + int i = 0; + + while (tx.ctrl & MAL_TX_CTRL_READY) { + if (i++ > 100) { + printf ("TX timeout\n"); + return; + } + udelay (1000); + } + tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST | + EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP; + tx.data_len = length; + memcpy (tx.data_ptr, packet, length); + sync (); + + out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0); + sync (); +} + +static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length) +{ + int length; + int i = 0; + + while (rx.ctrl & MAL_RX_CTRL_EMPTY) { + if (i++ > 100) { + printf ("RX timeout\n"); + return 0; + } + udelay (1000); + } + length = rx.data_len - 4; + if (length <= max_length) + memcpy(packet, rx.data_ptr, length); + sync (); + + rx.ctrl |= MAL_RX_CTRL_EMPTY; + sync (); + + return length; +} + + /* + * Test routines + */ + +static void packet_fill (char *packet, int length) +{ + char c = (char) length; + int i; + + /* set up ethernet header */ + memset (packet, 0xff, 14); + + for (i = 14; i < length; i++) { + packet[i] = c++; + } +} + +static int packet_check (char *packet, int length) +{ + char c = (char) length; + int i; + + for (i = 14; i < length; i++) { + if (packet[i] != c++) + return -1; + } + + return 0; +} + +static int test_ctlr (int devnum, int hw_addr) +{ + int res = -1; + char packet_send[MAX_PACKET_LENGTH]; + char packet_recv[MAX_PACKET_LENGTH]; + int length; + int i; + int l; + + ether_post_init (devnum, hw_addr); + + for (i = 0; i < TEST_NUM; i++) { + for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) { + packet_fill (packet_send, l); + + ether_post_send (devnum, hw_addr, packet_send, l); + + length = ether_post_recv (devnum, hw_addr, packet_recv, + sizeof (packet_recv)); + + if (length != l || packet_check (packet_recv, length) < 0) { + goto Done; + } + } + } + + res = 0; + +Done: + + ether_post_halt (devnum, hw_addr); + + if (res != 0) { + post_log ("EMAC%d test failed\n", devnum); + } + + return res; +} + +int ether_post_test (int flags) +{ + int res = 0; + + /* Allocate tx & rx packet buffers */ + tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE); + rx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE); + + if (!tx_buf || !rx_buf) { + printf ("Failed to allocate packet buffers\n"); + res = -1; + goto out_free; + } + + /* EMAC0 */ + if (test_ctlr (0, 0)) + res = -1; + + /* EMAC1 */ + if (test_ctlr (1, 0x100)) + res = -1; + +out_free: + free (tx_buf); + free (rx_buf); + + return res; +} + +#endif /* CONFIG_POST & CFG_POST_ETHER */ +#endif /* CONFIG_POST */ diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c index 1935c011ba7..c2eb4a9bf0b 100644 --- a/post/cpu/ppc4xx/fpu.c +++ b/post/cpu/ppc4xx/fpu.c @@ -1,5 +1,8 @@ /* - * Copyright (C) 2007 Wolfgang Denk + * (C) Copyright 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Author: Sergei Poselenov * * See file CREDITS for list of people who contributed to this * project. @@ -34,7 +37,7 @@ int fpu_status(void) { if (mfspr(ccr0) & CCR0_DAPUIB) return 0; /* Disabled */ - else + else return 1; /* Enabled */ } @@ -51,5 +54,6 @@ void fpu_enable(void) mtspr(ccr0, mfspr(ccr0) & ~CCR0_DAPUIB); mtmsr(mfmsr() | MSR_FP); } + #endif -#endif +#endif /* CONFIG_POST */ diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c index f62526a1716..be5a701f317 100644 --- a/post/cpu/ppc4xx/spr.c +++ b/post/cpu/ppc4xx/spr.c @@ -2,6 +2,8 @@ * (C) Copyright 2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Author: Igor Lisitsin + * * See file CREDITS for list of people who contributed to this * project. * @@ -39,6 +41,8 @@ #if CONFIG_POST & CFG_POST_SPR +#include + static struct { int number; @@ -60,8 +64,10 @@ static struct {0x113, "SPRG3", 0x00000000, 0x00000000}, {0x11f, "PVR", 0x00000000, 0x00000000}, - /* Additional Special-Purpose Registers */ - + /* Additional Special-Purpose Registers. + * The values must match the initialization + * values from cpu/ppc4xx/start.S + */ {0x30, "PID", 0x00000000, 0x00000000}, {0x3a, "CSRR0", 0x00000000, 0x00000000}, {0x3b, "CSRR1", 0x00000000, 0x00000000}, @@ -90,22 +96,22 @@ static struct {0x13f, "DVC2", 0x00000000, 0x00000000}, {0x150, "TSR", 0x00000000, 0x00000000}, {0x154, "TCR", 0x00000000, 0x00000000}, - {0x190, "IVOR0", 0x00000000, 0x00000000}, - {0x191, "IVOR1", 0x00000000, 0x00000000}, - {0x192, "IVOR2", 0x00000000, 0x00000000}, - {0x193, "IVOR3", 0x00000000, 0x00000000}, - {0x194, "IVOR4", 0x00000000, 0x00000000}, - {0x195, "IVOR5", 0x00000000, 0x00000000}, - {0x196, "IVOR6", 0x00000000, 0x00000000}, - {0x197, "IVOR7", 0x00000000, 0x00000000}, - {0x198, "IVOR8", 0x00000000, 0x00000000}, + {0x190, "IVOR0", 0x0000fff0, 0x00000100}, + {0x191, "IVOR1", 0x0000fff0, 0x00000200}, + {0x192, "IVOR2", 0x0000fff0, 0x00000300}, + {0x193, "IVOR3", 0x0000fff0, 0x00000400}, + {0x194, "IVOR4", 0x0000fff0, 0x00000500}, + {0x195, "IVOR5", 0x0000fff0, 0x00000600}, + {0x196, "IVOR6", 0x0000fff0, 0x00000700}, + {0x197, "IVOR7", 0x0000fff0, 0x00000800}, + {0x198, "IVOR8", 0x0000fff0, 0x00000c00}, {0x199, "IVOR9", 0x00000000, 0x00000000}, - {0x19a, "IVOR10", 0x00000000, 0x00000000}, + {0x19a, "IVOR10", 0x0000fff0, 0x00000900}, {0x19b, "IVOR11", 0x00000000, 0x00000000}, {0x19c, "IVOR12", 0x00000000, 0x00000000}, - {0x19d, "IVOR13", 0x00000000, 0x00000000}, - {0x19e, "IVOR14", 0x00000000, 0x00000000}, - {0x19f, "IVOR15", 0x00000000, 0x00000000}, + {0x19d, "IVOR13", 0x0000fff0, 0x00001300}, + {0x19e, "IVOR14", 0x0000fff0, 0x00001400}, + {0x19f, "IVOR15", 0x0000fff0, 0x00002000}, {0x23a, "MCSRR0", 0x00000000, 0x00000000}, {0x23b, "MCSRR1", 0x00000000, 0x00000000}, {0x23c, "MCSR", 0x00000000, 0x00000000}, @@ -126,8 +132,8 @@ static struct {0x395, "DTV1", 0x00000000, 0x00000000}, {0x396, "DTV2", 0x00000000, 0x00000000}, {0x397, "DTV3", 0x00000000, 0x00000000}, - {0x398, "DVLIM", 0x00000000, 0x00000000}, - {0x399, "IVLIM", 0x00000000, 0x00000000}, + {0x398, "DVLIM", 0x0fc1f83f, 0x0001f800}, + {0x399, "IVLIM", 0x0fc1f83f, 0x0001f800}, {0x39b, "RSTCFG", 0x00000000, 0x00000000}, {0x39c, "DCDBTRL", 0x00000000, 0x00000000}, {0x39d, "DCDBTRH", 0x00000000, 0x00000000}, @@ -172,5 +178,6 @@ int spr_post_test (int flags) return ret; } + #endif /* CONFIG_POST & CFG_POST_SPR */ #endif /* CONFIG_POST */ diff --git a/post/cpu/ppc4xx/uart.c b/post/cpu/ppc4xx/uart.c index f220dba17ab..b047d42dfd3 100644 --- a/post/cpu/ppc4xx/uart.c +++ b/post/cpu/ppc4xx/uart.c @@ -2,6 +2,8 @@ * (C) Copyright 2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Author: Igor Lisitsin + * * See file CREDITS for list of people who contributed to this * project. * @@ -210,5 +212,4 @@ int uart_post_test (int flags) } #endif /* CONFIG_POST & CFG_POST_UART */ - #endif /* CONFIG_POST */ diff --git a/post/cpu/ppc4xx/watchdog.c b/post/cpu/ppc4xx/watchdog.c index 3c76cfd3484..bd4f4c9856b 100644 --- a/post/cpu/ppc4xx/watchdog.c +++ b/post/cpu/ppc4xx/watchdog.c @@ -2,6 +2,8 @@ * (C) Copyright 2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * Author: Igor Lisitsin + * * See file CREDITS for list of people who contributed to this * project. * @@ -36,17 +38,18 @@ #ifdef CONFIG_POST #include -#include #if CONFIG_POST & CFG_POST_WATCHDOG +#include + int watchdog_post_test (int flags) { if (flags & POST_REBOOT) { /* Test passed */ - return 0; - } else { + } + else { /* 10-second delay */ int ints = disable_interrupts (); ulong base = post_time_ms (0); diff --git a/post/drivers/Makefile b/post/drivers/Makefile index 068fa98b14c..cb2f1deacd7 100644 --- a/post/drivers/Makefile +++ b/post/drivers/Makefile @@ -26,6 +26,6 @@ SUBDIRS = LIB = libpostdrivers.a -COBJS = cache.o i2c.o memory.o rtc.o +COBJS = i2c.o memory.o rtc.o include $(TOPDIR)/post/rules.mk diff --git a/post/drivers/cache.c b/post/drivers/cache.c deleted file mode 100644 index 501465c06a1..00000000000 --- a/post/drivers/cache.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include - -/* Cache test - * - * This test verifies the CPU data and instruction cache using - * several test scenarios. - */ - -#ifdef CONFIG_POST - -#include -#include - -#if CONFIG_POST & CFG_POST_CACHE - -#define CACHE_POST_SIZE 1024 - -extern int cache_post_test1 (char *, unsigned int); -extern int cache_post_test2 (char *, unsigned int); -extern int cache_post_test3 (char *, unsigned int); -extern int cache_post_test4 (char *, unsigned int); -extern int cache_post_test5 (void); -extern int cache_post_test6 (void); - -int cache_post_test (int flags) -{ - int ints = disable_interrupts (); - int res = 0; - static char ta[CACHE_POST_SIZE + 0xf]; - char *testarea = (char *) (((unsigned long) ta + 0xf) & ~0xf); - - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test1 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test2 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test3 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test4 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test5 (); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test6 (); - - WATCHDOG_RESET (); - if (ints) - enable_interrupts (); - return res; -} - -#endif /* CONFIG_POST & CFG_POST_CACHE */ -#endif /* CONFIG_POST */ diff --git a/post/lib_ppc/Makefile b/post/lib_ppc/Makefile index 14354a03236..9f1b329d70b 100644 --- a/post/lib_ppc/Makefile +++ b/post/lib_ppc/Makefile @@ -21,6 +21,7 @@ # MA 02111-1307 USA # +SUBDIRS = fpu LIB = libpostppc.a diff --git a/post/lib_ppc/fpu/20001122-1.c b/post/lib_ppc/fpu/20001122-1.c new file mode 100644 index 00000000000..f689b8232ff --- /dev/null +++ b/post/lib_ppc/fpu/20001122-1.c @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * This file is originally a part of the GCC testsuite. + */ + +#include + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_FPU + +int fpu_post_test_math1 (void) +{ + volatile double a, *p; + double c, d; + volatile double b; + + d = 1.0; + p = &b; + + do + { + c = d; + d = c * 0.5; + b = 1 + d; + } while (b != 1.0); + + a = 1.0 + c; + + if (a == 1.0) { + post_log ("Error in FPU math1 test\n"); + return -1; + } + + return 0; +} + +#endif /* CONFIG_POST & CFG_POST_FPU */ +#endif /* CONFIG_POST */ diff --git a/post/lib_ppc/fpu/20010114-2.c b/post/lib_ppc/fpu/20010114-2.c new file mode 100644 index 00000000000..6e60507f9ca --- /dev/null +++ b/post/lib_ppc/fpu/20010114-2.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * This file is originally a part of the GCC testsuite. + */ + +#include + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_FPU + +static float rintf (float x) +{ + volatile float TWO23 = 8388608.0; + + if (__builtin_fabs (x) < TWO23) + { + if (x > 0.0) + { + x += TWO23; + x -= TWO23; + } + else if (x < 0.0) + { + x = TWO23 - x; + x = -(x - TWO23); + } + } + + return x; +} + +int fpu_post_test_math2 (void) +{ + if (rintf (-1.5) != -2.0) { + post_log ("Error in FPU math2 test\n"); + return -1; + } + return 0; +} + +#endif /* CONFIG_POST & CFG_POST_FPU */ +#endif /* CONFIG_POST */ diff --git a/post/lib_ppc/fpu/20010226-1.c b/post/lib_ppc/fpu/20010226-1.c new file mode 100644 index 00000000000..b2c47e3658a --- /dev/null +++ b/post/lib_ppc/fpu/20010226-1.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * This file is originally a part of the GCC testsuite. + */ + +#include + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_FPU + +int fpu_post_test_math3 (void) +{ + volatile long double dfrom = 1.1; + volatile long double m1; + volatile long double m2; + volatile unsigned long mant_long; + + m1 = dfrom / 2.0; + m2 = m1 * 4294967296.0; + mant_long = ((unsigned long) m2) & 0xffffffff; + + if (mant_long != 0x8ccccccc) { + post_log ("Error in FPU math3 test\n"); + return -1; + } + return 0; +} + +#endif /* CONFIG_POST & CFG_POST_FPU */ +#endif /* CONFIG_POST */ diff --git a/post/lib_ppc/fpu/980619-1.c b/post/lib_ppc/fpu/980619-1.c new file mode 100644 index 00000000000..990aa0c9899 --- /dev/null +++ b/post/lib_ppc/fpu/980619-1.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * This file is originally a part of the GCC testsuite. + */ + +#include + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_FPU + +int fpu_post_test_math4 (void) +{ + volatile float reale = 1.0f; + volatile float oneplus; + int i; + + if (sizeof (float) != 4) + return 0; + + for (i = 0; ; i++) + { + oneplus = 1.0f + reale; + if (oneplus == 1.0f) + break; + reale = reale / 2.0f; + } + /* Assumes ieee754 accurate arithmetic above. */ + if (i != 24) { + post_log ("Error in FPU math4 test\n"); + return -1; + } + return 0; +} + +#endif /* CONFIG_POST & CFG_POST_FPU */ +#endif /* CONFIG_POST */ diff --git a/post/lib_ppc/fpu/Makefile b/post/lib_ppc/fpu/Makefile new file mode 100644 index 00000000000..82646c80d65 --- /dev/null +++ b/post/lib_ppc/fpu/Makefile @@ -0,0 +1,32 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + + +LIB = libpostppcfpu.a + +COBJS += fpu.o 20001122-1.o 20010114-2.o 20010226-1.o 980619-1.o +COBJS += acc1.o compare-fp-1.o mul-subnormal-single-1.o + +include $(TOPDIR)/post/rules.mk + +CFLAGS += -mhard-float -fkeep-inline-functions diff --git a/post/lib_ppc/fpu/acc1.c b/post/lib_ppc/fpu/acc1.c new file mode 100644 index 00000000000..4cecbf6a4fe --- /dev/null +++ b/post/lib_ppc/fpu/acc1.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * This file is originally a part of the GCC testsuite. + */ + +#include + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_FPU + +static double func (const double *array) +{ + double d = *array; + + if (d == 0.0) + return d; + else + return d + func (array + 1); +} + +int fpu_post_test_math5 (void) +{ + double values[] = { 0.1e-100, 1.0, -1.0, 0.0 }; + + if (func (values) != 0.1e-100) { + post_log ("Error in FPU math5 test\n"); + return -1; + } + return 0; +} + +#endif /* CONFIG_POST & CFG_POST_FPU */ +#endif /* CONFIG_POST */ diff --git a/post/lib_ppc/fpu/compare-fp-1.c b/post/lib_ppc/fpu/compare-fp-1.c new file mode 100644 index 00000000000..d866ad5a36b --- /dev/null +++ b/post/lib_ppc/fpu/compare-fp-1.c @@ -0,0 +1,225 @@ +/* + * Copyright (C) 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * Test for correctness of composite floating-point comparisons. + * Written by Paolo Bonzini, 26th May 2004. + * This file is originally a part of the GCC testsuite. + */ + +#include + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_FPU + +static int failed; + +#define TEST(c) if ((c) != ok) failed++ +#define ORD(a, b) (!__builtin_isunordered ((a), (b))) +#define UNORD(a, b) (__builtin_isunordered ((a), (b))) +#define UNEQ(a, b) (__builtin_isunordered ((a), (b)) || ((a) == (b))) +#define UNLT(a, b) (__builtin_isunordered ((a), (b)) || ((a) < (b))) +#define UNLE(a, b) (__builtin_isunordered ((a), (b)) || ((a) <= (b))) +#define UNGT(a, b) (__builtin_isunordered ((a), (b)) || ((a) > (b))) +#define UNGE(a, b) (__builtin_isunordered ((a), (b)) || ((a) >= (b))) +#define LTGT(a, b) (__builtin_islessgreater ((a), (b))) + +static float pinf; +static float ninf; +static float NaN; + +static void iuneq (float x, float y, int ok) +{ + TEST (UNEQ (x, y)); + TEST (!LTGT (x, y)); + TEST (UNLE (x, y) && UNGE (x,y)); +} + +static void ieq (float x, float y, int ok) +{ + TEST (ORD (x, y) && UNEQ (x, y)); +} + +static void iltgt (float x, float y, int ok) +{ + TEST (!UNEQ (x, y)); /* Not optimizable. */ + TEST (LTGT (x, y)); /* Same, __builtin_islessgreater does not trap. */ + TEST (ORD (x, y) && (UNLT (x, y) || UNGT (x,y))); +} + +static void ine (float x, float y, int ok) +{ + TEST (UNLT (x, y) || UNGT (x, y)); +} + +static void iunlt (float x, float y, int ok) +{ + TEST (UNLT (x, y)); + TEST (UNORD (x, y) || (x < y)); +} + +static void ilt (float x, float y, int ok) +{ + TEST (ORD (x, y) && UNLT (x, y)); /* Not optimized */ + TEST ((x <= y) && (x != y)); + TEST ((x <= y) && (y != x)); + TEST ((x != y) && (x <= y)); /* Not optimized */ + TEST ((y != x) && (x <= y)); /* Not optimized */ +} + +static void iunle (float x, float y, int ok) +{ + TEST (UNLE (x, y)); + TEST (UNORD (x, y) || (x <= y)); +} + +static void ile (float x, float y, int ok) +{ + TEST (ORD (x, y) && UNLE (x, y)); /* Not optimized */ + TEST ((x < y) || (x == y)); + TEST ((y > x) || (x == y)); + TEST ((x == y) || (x < y)); /* Not optimized */ + TEST ((y == x) || (x < y)); /* Not optimized */ +} + +static void iungt (float x, float y, int ok) +{ + TEST (UNGT (x, y)); + TEST (UNORD (x, y) || (x > y)); +} + +static void igt (float x, float y, int ok) +{ + TEST (ORD (x, y) && UNGT (x, y)); /* Not optimized */ + TEST ((x >= y) && (x != y)); + TEST ((x >= y) && (y != x)); + TEST ((x != y) && (x >= y)); /* Not optimized */ + TEST ((y != x) && (x >= y)); /* Not optimized */ +} + +static void iunge (float x, float y, int ok) +{ + TEST (UNGE (x, y)); + TEST (UNORD (x, y) || (x >= y)); +} + +static void ige (float x, float y, int ok) +{ + TEST (ORD (x, y) && UNGE (x, y)); /* Not optimized */ + TEST ((x > y) || (x == y)); + TEST ((y < x) || (x == y)); + TEST ((x == y) || (x > y)); /* Not optimized */ + TEST ((y == x) || (x > y)); /* Not optimized */ +} + +int fpu_post_test_math6 (void) +{ + pinf = __builtin_inf (); + ninf = -__builtin_inf (); + NaN = __builtin_nan (""); + + iuneq (ninf, pinf, 0); + iuneq (NaN, NaN, 1); + iuneq (pinf, ninf, 0); + iuneq (1, 4, 0); + iuneq (3, 3, 1); + iuneq (5, 2, 0); + + ieq (1, 4, 0); + ieq (3, 3, 1); + ieq (5, 2, 0); + + iltgt (ninf, pinf, 1); + iltgt (NaN, NaN, 0); + iltgt (pinf, ninf, 1); + iltgt (1, 4, 1); + iltgt (3, 3, 0); + iltgt (5, 2, 1); + + ine (1, 4, 1); + ine (3, 3, 0); + ine (5, 2, 1); + + iunlt (NaN, ninf, 1); + iunlt (pinf, NaN, 1); + iunlt (pinf, ninf, 0); + iunlt (pinf, pinf, 0); + iunlt (ninf, ninf, 0); + iunlt (1, 4, 1); + iunlt (3, 3, 0); + iunlt (5, 2, 0); + + ilt (1, 4, 1); + ilt (3, 3, 0); + ilt (5, 2, 0); + + iunle (NaN, ninf, 1); + iunle (pinf, NaN, 1); + iunle (pinf, ninf, 0); + iunle (pinf, pinf, 1); + iunle (ninf, ninf, 1); + iunle (1, 4, 1); + iunle (3, 3, 1); + iunle (5, 2, 0); + + ile (1, 4, 1); + ile (3, 3, 1); + ile (5, 2, 0); + + iungt (NaN, ninf, 1); + iungt (pinf, NaN, 1); + iungt (pinf, ninf, 1); + iungt (pinf, pinf, 0); + iungt (ninf, ninf, 0); + iungt (1, 4, 0); + iungt (3, 3, 0); + iungt (5, 2, 1); + + igt (1, 4, 0); + igt (3, 3, 0); + igt (5, 2, 1); + + iunge (NaN, ninf, 1); + iunge (pinf, NaN, 1); + iunge (ninf, pinf, 0); + iunge (pinf, pinf, 1); + iunge (ninf, ninf, 1); + iunge (1, 4, 0); + iunge (3, 3, 1); + iunge (5, 2, 1); + + ige (1, 4, 0); + ige (3, 3, 1); + ige (5, 2, 1); + + if (failed) { + post_log ("Error in FPU math6 test\n"); + return -1; + } + return 0; +} + +#endif /* CONFIG_POST & CFG_POST_FPU */ +#endif /* CONFIG_POST */ diff --git a/post/lib_ppc/fpu/fpu.c b/post/lib_ppc/fpu/fpu.c new file mode 100644 index 00000000000..07dcba8cc92 --- /dev/null +++ b/post/lib_ppc/fpu/fpu.c @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Author: Sergei Poselenov + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +/* + * FPU test + * + * This test checks the arithmetic logic unit (ALU) of CPU. + * It tests independently various groups of instructions using + * run-time modification of the code to reduce the memory footprint. + * For more details refer to post/cpu/ *.c files. + */ + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_FPU + +#include + +extern int fpu_status (void); +extern void fpu_enable (void); +extern void fpu_disable (void); + +extern int fpu_post_test_math1 (void); +extern int fpu_post_test_math2 (void); +extern int fpu_post_test_math3 (void); +extern int fpu_post_test_math4 (void); +extern int fpu_post_test_math5 (void); +extern int fpu_post_test_math6 (void); +extern int fpu_post_test_math7 (void); + +int fpu_post_test (int flags) +{ + int fpu = fpu_status (); + + int ret = 0; + + WATCHDOG_RESET (); + + if (!fpu) + fpu_enable (); + + if (ret == 0) + ret = fpu_post_test_math1 (); + if (ret == 0) + ret = fpu_post_test_math2 (); + if (ret == 0) + ret = fpu_post_test_math3 (); + if (ret == 0) + ret = fpu_post_test_math4 (); + if (ret == 0) + ret = fpu_post_test_math5 (); + if (ret == 0) + ret = fpu_post_test_math6 (); + if (ret == 0) + ret = fpu_post_test_math7 (); + + if (!fpu) + fpu_disable (); + + WATCHDOG_RESET (); + + return ret; +} + +#endif /* CONFIG_POST & CFG_POST_FPU */ +#endif /* CONFIG_POST */ diff --git a/post/lib_ppc/fpu/mul-subnormal-single-1.c b/post/lib_ppc/fpu/mul-subnormal-single-1.c new file mode 100644 index 00000000000..67f48da3352 --- /dev/null +++ b/post/lib_ppc/fpu/mul-subnormal-single-1.c @@ -0,0 +1,103 @@ +/* + * Copyright (C) 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * This file is originally a part of the GCC testsuite. + * Check that certain subnormal numbers (formerly known as denormalized + * numbers) are rounded to within 0.5 ulp. PR other/14354. + */ + +#include + +#ifdef CONFIG_POST + +#include + +#if CONFIG_POST & CFG_POST_FPU + +union uf +{ + unsigned int u; + float f; +}; + +static float +u2f (unsigned int v) +{ + union uf u; + u.u = v; + return u.f; +} + +static unsigned int +f2u (float v) +{ + union uf u; + u.f = v; + return u.u; +} + +static int ok = 1; + +static void +tstmul (unsigned int ux, unsigned int uy, unsigned int ur) +{ + float x = u2f (ux); + float y = u2f (uy); + + if (f2u (x * y) != ur) + /* Set a variable rather than aborting here, to simplify tracing when + several computations are wrong. */ + ok = 0; +} + +/* We don't want to make this const and static, or else we risk inlining + causing the test to fold as constants at compile-time. */ +struct +{ + unsigned int p1, p2, res; +} static volatile expected[] = +{ + {0xfff, 0x3f800400, 0xfff}, + {0xf, 0x3fc88888, 0x17}, + {0xf, 0x3f844444, 0xf} +}; + +int fpu_post_test_math7 (void) +{ + unsigned int i; + + for (i = 0; i < sizeof (expected) / sizeof (expected[0]); i++) + { + tstmul (expected[i].p1, expected[i].p2, expected[i].res); + tstmul (expected[i].p2, expected[i].p1, expected[i].res); + } + + if (!ok) { + post_log ("Error in FPU math7 test\n"); + return -1; + } + return 0; +} + +#endif /* CONFIG_POST & CFG_POST_FPU */ +#endif /* CONFIG_POST */ -- cgit v1.3.1 From 8ea5499afdaba0acf60923dd99001c399d4a7c8e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:30:06 -0500 Subject: include/configs: Use new CONFIG_CMD_* in 83xx board config files. Signed-off-by: Jon Loeliger --- include/configs/MPC8313ERDB.h | 29 +++++++++++----------- include/configs/MPC832XEMDS.h | 51 +++++++++++++-------------------------- include/configs/MPC8349EMDS.h | 56 +++++++++++++++---------------------------- include/configs/MPC8349ITX.h | 42 ++++++++++++++------------------ include/configs/MPC8360EMDS.h | 51 +++++++++++++-------------------------- 5 files changed, 85 insertions(+), 144 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 7e1005c1ae9..3334f0fe99a 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -341,26 +341,25 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CFG_BASE_COMMANDS ( CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_DHCP \ - | CFG_CMD_I2C \ - | CFG_CMD_MII \ - | CFG_CMD_DATE \ - | CFG_CMD_PCI) - -#define CONFIG_CMDLINE_EDITING 1 +/* + * Command line configuration. + */ +#include -#define CFG_RAMBOOT_COMMANDS (CFG_BASE_COMMANDS & \ - ~(CFG_CMD_ENV | CFG_CMD_LOADS)) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PCI #if defined(CFG_RAMBOOT) -#define CONFIG_COMMANDS CFG_RAMBOOT_COMMANDS -#else -#define CONFIG_COMMANDS CFG_BASE_COMMANDS + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #endif -#include +#define CONFIG_CMDLINE_EDITING 1 + /* * Miscellaneous configurable options diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index cecb2258ffe..1984157e1cf 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -423,41 +423,24 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#if defined(CFG_RAMBOOT) -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_ASKENV \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#endif -#else +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_ASKENV + #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C ) + #define CONFIG_CMD_PCI #endif + +#if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #endif -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -468,7 +451,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -498,7 +481,7 @@ */ #define CFG_DCACHE_SIZE 16384 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ #endif @@ -575,7 +558,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 20c6d5a365e..9855a62a7fe 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -475,44 +475,26 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#if defined(CFG_RAMBOOT) -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C \ - | CFG_CMD_DATE) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_DATE) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#endif -#else + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DATE +#define CONFIG_CMD_MII + #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_DATE \ - ) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII \ - | CFG_CMD_DATE \ - ) + #define CONFIG_CMD_PCI #endif + +#if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #endif -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -523,7 +505,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -544,7 +526,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -695,7 +677,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 834934d0b6a..799ff4a7ab0 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -416,37 +416,31 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_LOADS_ECHO /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ -/* CONFIG_COMMANDS */ +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SDRAM #ifdef CONFIG_COMPACT_FLASH -#define CONFIG_COMMANDS_CF (CFG_CMD_IDE | CFG_CMD_FAT) -#else -#define CONFIG_COMMANDS_CF 0 + #define CONFIG_CMD_IDE + #define CONFIG_CMD_FAT #endif #ifdef CONFIG_PCI -#define CONFIG_COMMANDS_PCI CFG_CMD_PCI -#else -#define CONFIG_COMMANDS_PCI 0 + #define CONFIG_CMD_PCI #endif #ifdef CONFIG_HARD_I2C -#define CONFIG_COMMANDS_I2C CFG_CMD_I2C -#else -#define CONFIG_COMMANDS_I2C 0 + #define CONFIG_CMD_I2C #endif -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CONFIG_COMMANDS_CF | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CONFIG_COMMANDS_I2C | \ - CONFIG_COMMANDS_PCI | \ - CFG_CMD_SDRAM | \ - CFG_CMD_DATE | \ - CFG_CMD_CACHE | \ - CFG_CMD_IRQ) -#include /* Watchdog */ @@ -469,7 +463,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -492,7 +486,7 @@ boards, we say we have two, but don't display a message if we find only one. */ */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log2 of the above value */ #endif @@ -617,7 +611,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 79937dcd8f9..b355f89bf8b 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -457,41 +457,24 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#if defined(CFG_RAMBOOT) -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_ASKENV \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#endif -#else +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C +#define CONFIG_CMD_ASKENV + #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C ) + #define CONFIG_CMD_PCI #endif + +#if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #endif -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -502,7 +485,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -532,7 +515,7 @@ */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */ #endif @@ -610,7 +593,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -- cgit v1.3.1 From 1cc4c458329765b58e584a19821e796b3c10e976 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:30:28 -0500 Subject: include/configs: Use new CONFIG_CMD_* in 82xx board config files. Signed-off-by: Jon Loeliger --- include/configs/MPC8260ADS.h | 90 ++++++++++++++++++++++---------------------- include/configs/MPC8266ADS.h | 70 +++++++++++++++++----------------- 2 files changed, 82 insertions(+), 78 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 6195bca85ba..aaecd38c9df 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -198,59 +198,61 @@ #define CONFIG_BAUDRATE 115200 -#define CFG_EXCLUDE CFG_CMD_BEDBUG | \ - CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DISPLAY | \ - CFG_CMD_DOC | \ - CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FAT | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_IDE | \ - CFG_CMD_KGDB | \ - CFG_CMD_MMC | \ - CFG_CMD_NAND | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_REISER | \ - CFG_CMD_SCSI | \ - CFG_CMD_SPI | \ - CFG_CMD_SNTP | \ - CFG_CMD_UNIVERSE | \ - CFG_CMD_USB | \ - CFG_CMD_VFD | \ - CFG_CMD_XIMG +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_BEDBUG +#undef CONFIG_CMD_BMP +#undef CONFIG_CMD_BSP +#undef CONFIG_CMD_DATE +#undef CONFIG_CMD_DISPLAY +#undef CONFIG_CMD_DOC +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_EXT2 +#undef CONFIG_CMD_FAT +#undef CONFIG_CMD_FDC +#undef CONFIG_CMD_FDOS +#undef CONFIG_CMD_HWFLOW +#undef CONFIG_CMD_IDE +#undef CONFIG_CMD_KGDB +#undef CONFIG_CMD_MMC +#undef CONFIG_CMD_NAND +#undef CONFIG_CMD_PCMCIA +#undef CONFIG_CMD_REISER +#undef CONFIG_CMD_SCSI +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_SNTP +#undef CONFIG_CMD_UNIVERSE +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_VFD +#undef CONFIG_CMD_XIMG #if CONFIG_ADSTYPE == CFG_8272ADS -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_SDRAM | \ - CFG_CMD_I2C | \ - CFG_EXCLUDE ) ) + #undef CONFIG_CMD_SDRAM + #undef CONFIG_CMD_I2C + #elif CONFIG_ADSTYPE >= CFG_PQ2FADS -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_SDRAM | \ - CFG_CMD_I2C | \ - CFG_CMD_PCI | \ - CFG_EXCLUDE ) ) + #undef CONFIG_CMD_SDRAM + #undef CONFIG_CMD_I2C + #undef CONFIG_CMD_PCI + #else -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CMD_CFG_PCI | \ - CFG_EXCLUDE ) ) + #undef CONFIG_CMD_PCI + #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + + #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/mtdblock2" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -268,7 +270,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -384,7 +386,7 @@ #endif /* CFG_RAMBOOT */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index 4953b7053be..d6dd73bfd0d 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -146,35 +146,39 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS ( CFG_CMD_ALL & ~( \ - CFG_CMD_BEDBUG | \ - CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DISPLAY | \ - CFG_CMD_DOC | \ - CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_IDE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_KGDB | \ - CFG_CMD_MMC | \ - CFG_CMD_NAND | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_REISER | \ - CFG_CMD_SCSI | \ - CFG_CMD_SPI | \ - CFG_CMD_SNTP | \ - CFG_CMD_VFD | \ - CFG_CMD_UNIVERSE | \ - CFG_CMD_USB | \ - CFG_CMD_XIMG ) ) +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_BEDBUG +#undef CONFIG_CMD_BMP +#undef CONFIG_CMD_BSP +#undef CONFIG_CMD_DATE +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DISPLAY +#undef CONFIG_CMD_DOC +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_EXT2 +#undef CONFIG_CMD_FDC +#undef CONFIG_CMD_FDOS +#undef CONFIG_CMD_HWFLOW +#undef CONFIG_CMD_IDE +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_KGDB +#undef CONFIG_CMD_MMC +#undef CONFIG_CMD_NAND +#undef CONFIG_CMD_PCMCIA +#undef CONFIG_CMD_REISER +#undef CONFIG_CMD_SCSI +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_SNTP +#undef CONFIG_CMD_VFD +#undef CONFIG_CMD_UNIVERSE +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_XIMG /* Define a command string that is automatically executed when no character * is read on the console interface withing "Boot Delay" after reset. @@ -210,13 +214,11 @@ CONFIG_BOOTP_BOOTFILESIZE | \ CONFIG_BOOTP_DNS) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -231,7 +233,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -452,7 +454,7 @@ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From 2694690e285acaa34922f55f4b5ae030da60c55a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:30:50 -0500 Subject: include/configs: Use new CONFIG_CMD_* in TQM board config files. Signed-off-by: Jon Loeliger --- include/configs/TQM5200.h | 90 ++++++++++++++++++++++------------------------- include/configs/TQM823L.h | 36 +++++++++---------- include/configs/TQM823M.h | 25 +++++++------ include/configs/TQM8260.h | 23 ++++++------ include/configs/TQM8272.h | 33 +++++++++-------- include/configs/TQM834x.h | 48 +++++++++++-------------- include/configs/TQM850L.h | 24 +++++++------ include/configs/TQM850M.h | 24 +++++++------ include/configs/TQM855L.h | 25 +++++++------ include/configs/TQM855M.h | 29 ++++++++------- include/configs/TQM860L.h | 29 ++++++++------- include/configs/TQM860M.h | 29 ++++++++------- include/configs/TQM862L.h | 25 +++++++------ include/configs/TQM862M.h | 25 +++++++------ include/configs/TQM866M.h | 25 +++++++------ include/configs/TQM885D.h | 35 +++++++++--------- 16 files changed, 273 insertions(+), 252 deletions(-) (limited to 'include') diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index aa3627b4d77..24114b82d39 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -47,11 +47,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -105,12 +100,6 @@ #define CONFIG_NS8382X 1 #endif /* CONFIG_STK52XX */ -#ifdef CONFIG_PCI -#define ADD_PCI_CMD CFG_CMD_PCI -#else -#define ADD_PCI_CMD 0 -#endif - /* * Video console */ @@ -133,11 +122,6 @@ #define CFG_CONSOLE_IS_IN_ENV #endif /* #ifndef CONFIG_TQM5200S */ -#ifdef CONFIG_VIDEO -#define ADD_BMP_CMD CFG_CMD_BMP -#else -#define ADD_BMP_CMD 0 -#endif /* Partitions */ #define CONFIG_MAC_PARTITION @@ -147,10 +131,7 @@ /* USB */ #if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 #endif #ifndef CONFIG_CAM5200 @@ -168,37 +149,45 @@ #define CFG_CMD_POST_DIAG 0 #endif -/* IDE */ -#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) || defined(CONFIG_FO300) -#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) -#else -#define ADD_IDE_CMD 0 -#endif /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_BMP_CMD | \ - ADD_IDE_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP | \ - CFG_CMD_BSP) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_POST_DIAG +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_BSP + +#ifdef CONFIG_VIDEO + #define CONFIG_CMD_BMP +#endif + +#ifdef CONFIG_PCI +#define CONFIG_CMD_CMD_PCI +#endif + +#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) || defined(CONFIG_FO300) + #define CONFIG_CMD_IDE + #define CONFIG_CMD_FAT + #define CONFIG_CMD_EXT2 +#endif + +#if defined(CONFIG_STK52XX) || defined(CONFIG_FO300) + #define CONFIG_CFG_USB + #define CONFIG_CFG_FAT +#endif + #define CONFIG_TIMESTAMP /* display image timestamps */ @@ -566,7 +555,12 @@ #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ #define CFG_PROMPT_HUSH_PS2 "> " -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 247f705fb66..86df7f60d68 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -95,27 +95,23 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + #ifdef CONFIG_SPLASH_SCREEN -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BMP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#else -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) + #define CONFIG_CMD_BMP #endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options @@ -129,7 +125,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -212,7 +208,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 1461b5f2031..bd33efbc7af 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -95,16 +95,19 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options @@ -118,7 +121,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -202,7 +205,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index ffd5c0b95ca..3089fefc31f 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -222,15 +222,18 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options @@ -244,7 +247,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -385,7 +388,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h index 925bf343171..b7a1baebcf4 100644 --- a/include/configs/TQM8272.h +++ b/include/configs/TQM8272.h @@ -274,18 +274,21 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_NAND | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - ADD_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options @@ -301,7 +304,7 @@ #endif #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -392,7 +395,7 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CONFIG_CMD_NAND) #define CFG_NAND_CS_DIST 0x80 #define CFG_NAND_UPM_WRITE_CMD_OFS 0x20 @@ -502,7 +505,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 4a5f8b67578..9628703b317 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -316,38 +316,32 @@ extern int tqm834x_num_flash_banks; #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -/* Common commands */ -#define CFG_CMD_TQM8349_COMMON CFG_CMD_DATE | CFG_CMD_I2C | CFG_CMD_DTT\ - | CFG_CMD_PING | CFG_CMD_EEPROM \ - | CFG_CMD_MII | CFG_CMD_JFFS2 -#if defined(CFG_RAMBOOT) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PCI \ - | CFG_CMD_TQM8349_COMMON) \ - & \ - ~(CFG_CMD_ENV | CFG_CMD_LOADS)) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_TQM8349_COMMON) \ - & \ - ~(CFG_CMD_ENV | CFG_CMD_LOADS)) + #define CONFIG_CMD_PCI #endif -#else /* CFG_RAMBOOT */ - -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \ - | CFG_CMD_TQM8349_COMMON) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_TQM8349_COMMON) +#if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #endif -#endif /* CFG_RAMBOOT */ -#include + + /* * Miscellaneous configurable options @@ -362,7 +356,7 @@ extern int tqm834x_num_flash_banks; #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -387,7 +381,7 @@ extern int tqm834x_num_flash_banks; */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -495,7 +489,7 @@ extern int tqm834x_num_flash_banks; #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 90ecbadb2e1..923d4e5eafd 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -87,16 +87,18 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options @@ -110,7 +112,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -193,7 +195,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index b3f8f8d835a..c257fc543d5 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -85,16 +85,18 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options @@ -108,7 +110,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -192,7 +194,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 49aaeea44de..7da7b0bd886 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -90,16 +90,19 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options @@ -113,7 +116,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -196,7 +199,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 50df49e93cc..e66bbc42213 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -123,17 +123,20 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options @@ -147,7 +150,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -231,7 +234,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 9be5db1e424..495760a10d7 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -90,19 +90,22 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#define CONFIG_NETCONSOLE +/* + * Command line configuration. + */ +#include -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + + +#define CONFIG_NETCONSOLE /* * Miscellaneous configurable options @@ -116,7 +119,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -199,7 +202,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 37f6c985d3a..e86e5fb1875 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -90,17 +90,20 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options @@ -114,7 +117,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -198,7 +201,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index f03690a7b21..051225136ec 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -93,16 +93,19 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options @@ -116,7 +119,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -200,7 +203,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index 495934045f9..df141a70594 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -93,16 +93,19 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options @@ -116,7 +119,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -201,7 +204,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index 148490b5863..27e37e2d802 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -134,16 +134,19 @@ #define CONFIG_TIMESTAMP /* but print image timestmps */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS + /* * Miscellaneous configurable options @@ -157,7 +160,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -241,7 +244,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index d470ade847d..4731988eba8 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -140,19 +140,22 @@ #define CONFIG_TIMESTAMP /* but print image timestmps */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING + /* * Miscellaneous configurable options @@ -166,7 +169,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -258,7 +261,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -478,7 +481,7 @@ #define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ #define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ -#if (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_CMD_MII) #define CFG_DISCOVER_PHY #endif -- cgit v1.3.1 From 866e3089bfc826bb4dc74637f8aad87a3bab79fc Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:30:58 -0500 Subject: include/configs: Use new CONFIG_CMD_* in sbc* board config files. Signed-off-by: Jon Loeliger --- include/configs/sbc2410x.h | 38 ++++++++++++++++------------------ include/configs/sbc405.h | 32 +++++++++++++++-------------- include/configs/sbc8240.h | 29 +++++++++++++------------- include/configs/sbc8260.h | 47 ++++++++++++++++++++---------------------- include/configs/sbc8349.h | 51 ++++++++++++++++------------------------------ 5 files changed, 89 insertions(+), 108 deletions(-) (limited to 'include') diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h index 866f7b04261..fe06be674cd 100644 --- a/include/configs/sbc2410x.h +++ b/include/configs/sbc2410x.h @@ -82,24 +82,20 @@ #define CONFIG_BAUDRATE 115200 -/*********************************************************** - * Command definition - ***********************************************************/ -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - /*CFG_CMD_NAND |*/ \ - /*CFG_CMD_EEPROM |*/ \ - /*CFG_CMD_I2C |*/ \ - /*CFG_CMD_USB |*/ \ - CFG_CMD_REGINFO | \ - CFG_CMD_DATE | \ - CFG_CMD_PING | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off" @@ -110,7 +106,7 @@ /*#define CONFIG_BOOTFILE "elinos-lart" */ #define CONFIG_BOOTCOMMAND "dhcp; bootm" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ @@ -193,7 +189,7 @@ /*----------------------------------------------------------------------- * NAND flash settings */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CONFIG_CMD_NAND) #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 @@ -219,7 +215,7 @@ #define NAND_CTL_CLRCLE(nandptr) #define NAND_CTL_SETCLE(nandptr) /* #undef CONFIG_MTD_NAND_VERIFY_WRITE */ -#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ +#endif /* CONFIG_CMD_NAND */ #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index beff28ab32f..af34dbb74b7 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -88,19 +88,21 @@ #define CONFIG_ENV_OVERWRITE -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_SDRAM | \ - 0 ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SDRAM + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -123,7 +125,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -229,7 +231,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/sbc8240.h b/include/configs/sbc8240.h index d891e07b314..b81858b5fc9 100644 --- a/include/configs/sbc8240.h +++ b/include/configs/sbc8240.h @@ -79,20 +79,21 @@ #define CONFIG_ENV_OVERWRITE -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_SDRAM | \ - 0 ) - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + +/* + * Command line configuration. */ -#include +#include + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SDRAM + /* * Miscellaneous configurable options @@ -340,7 +341,7 @@ typedef unsigned int led_id_t; * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h index 9cf0654be10..2a209d32b96 100644 --- a/include/configs/sbc8260.h +++ b/include/configs/sbc8260.h @@ -444,27 +444,26 @@ */ #define CONFIG_VERSION_VARIABLE -/* What U-Boot subsytems do you want enabled? */ -#ifdef CONFIG_ETHER_ON_FCC -# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IMMAP | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM ) -#else -# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IMMAP | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM ) -#endif /* CONFIG_ETHER_ON_FCC */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + +#undef CONFIG_CMD_KGDB + +#if defined(CONFIG_ETHER_ON_FCC) + #define CONFIG_CMD_CMD_MII +#endif + #undef CONFIG_WATCHDOG /* disable the watchdog */ @@ -481,13 +480,11 @@ #define CONFIG_SBC8260 1 /* on an EST SBC8260 Board */ #define CONFIG_CPM2 1 /* Has a CPM2 */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -627,7 +624,7 @@ */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index e6e3866a07e..81322dfc70c 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -439,40 +439,25 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#if defined(CFG_RAMBOOT) -#if defined(CONFIG_PCI) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C) \ - & \ - ~(CFG_CMD_ENV \ - | CFG_CMD_LOADS)) -#endif -#else + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + #if defined(CONFIG_PCI) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PCI \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - ) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_PING \ - | CFG_CMD_I2C \ - | CFG_CMD_MII \ - ) + #define CONFG_CMD_PCI #endif + +#if defined(CFG_RAMBOOT) + #undef CONFIG_CMD_ENV + #undef CONFIG_CMD_LOADS #endif -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -483,7 +468,7 @@ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -504,7 +489,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ #endif @@ -655,7 +640,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -- cgit v1.3.1 From ef0df52ab49eea4a30c15087fd27d54c1d946f2c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:31:07 -0500 Subject: include/configs: Use new CONFIG_CMD_* in STx board config files. Signed-off-by: Jon Loeliger --- include/configs/stxssa.h | 6 +++--- include/configs/stxxtc.h | 25 ++++++++++++++----------- 2 files changed, 17 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index c88d534fcc6..f480bd530f4 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -357,7 +357,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "SSA=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -378,7 +378,7 @@ /* Cache Configuration */ #define CFG_DCACHE_SIZE 32768 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -390,7 +390,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index 614a046105c..d0d85812f9f 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -100,19 +100,22 @@ #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_NAND | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_MII | \ - CFG_CMD_NFS) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING + #define CONFIG_BOARD_EARLY_INIT_F 1 #define CONFIG_MISC_INIT_R -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ @@ -122,7 +125,7 @@ #define CFG_HUSH_PARSER 1 #define CFG_PROMPT_HUSH_PS2 "> " -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -213,7 +216,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From d794cfefead5fc177cf4f41164e80382e9c9484a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:31:15 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various 5200 board config files. Signed-off-by: Jon Loeliger --- include/configs/TB5200.h | 70 +++++++++++++++++++++------------------------ include/configs/TOP5200.h | 70 ++++++++++++++++++--------------------------- include/configs/Total5200.h | 55 +++++++++++++++-------------------- include/configs/cpci5200.h | 53 ++++++++++++++++------------------ include/configs/mecp5200.h | 39 ++++++++++++------------- include/configs/pf5200.h | 36 +++++++++++------------ include/configs/r5200.h | 16 ++++++++--- 7 files changed, 155 insertions(+), 184 deletions(-) (limited to 'include') diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 712668ab8a2..f64c5222238 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -42,11 +42,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -72,12 +67,6 @@ #define CFG_CONSOLE_IS_IN_ENV #endif -#ifdef CONFIG_VIDEO -#define ADD_BMP_CMD CFG_CMD_BMP -#else -#define ADD_BMP_CMD 0 -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -85,7 +74,6 @@ /* USB */ #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE /* POST support */ @@ -101,34 +89,35 @@ #define CFG_CMD_POST_DIAG 0 #endif -/* IDE */ -#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_BMP_CMD | \ - ADD_IDE_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP | \ - CFG_CMD_BSP) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#ifdef CONFIG_VIDEO +#define CONFIG_CMD_BMP +#endif + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_POST_DIAG +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_BSP +#define CONFIG_CMD_USB + #define CONFIG_TIMESTAMP /* display image timestamps */ @@ -394,7 +383,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -403,6 +392,11 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* Enable an alternate, more extensive memory test */ #define CFG_ALT_MEMTEST diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h index 1cc9ce94f91..73d25ea868e 100644 --- a/include/configs/TOP5200.h +++ b/include/configs/TOP5200.h @@ -50,11 +50,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -81,12 +76,6 @@ # define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS # define CONFIG_PCI_IO_SIZE 0x01000000 -# define ADD_PCI_CMD CFG_CMD_PCI - -#else /* no Evaluation board */ - -# define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ - #endif /* USB */ @@ -99,49 +88,40 @@ # else # define CONFIG_USB_CONFIG 0x00001000 # endif -# define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT # define CONFIG_DOS_PARTITION # define CONFIG_USB_STORAGE -#else - -# define ADD_USB_CMD 0 - #endif /* IDE */ #if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) - -# define ADD_IDE_CMD CFG_CMD_IDE | CFG_CMD_FAT # define CONFIG_DOS_PARTITION +#endif -#else -# define ADD_IDE_CMD 0 +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_REGINFO +#if defined (CONFIG_EVAL5200) || defined (CONFIG_LITE5200) +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_USB +#define CONFIG_CMD_PCI #endif -/* - * Supported commands - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - ADD_IDE_CMD | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_BEDBUG \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * MUST be low boot - HIGHBOOT is not supported anymore @@ -336,7 +316,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -352,6 +332,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + #ifdef CONFIG_EVAL5200 /* M48T08 is available with the Evaluation board only */ #define CONFIG_RTC_MK48T59 1 /* use M48T08 on EVAL5200 */ #define RTC(reg) (0xf0010000+reg) diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index d8686dd39c0..ba2daf73cd7 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -48,11 +48,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -63,7 +58,6 @@ /* * Video console */ -#if 1 #define CONFIG_VIDEO #define CONFIG_VIDEO_SED13806 #define CONFIG_VIDEO_SED13806_16BPP @@ -76,10 +70,6 @@ #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_SPLASH_SCREEN -#define ADD_VIDEO_CMD CFG_CMD_BMP -#else -#define ADD_VIDEO_CMD 0 -#endif #ifdef CONFIG_MPC5200 /* MGT5100 PCI is not supported yet. */ /* @@ -105,12 +95,9 @@ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#define ADD_PCI_CMD CFG_CMD_PCI - #else /* MGT5100 */ #define CONFIG_MII 1 -#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ #endif @@ -119,29 +106,27 @@ #define CONFIG_DOS_PARTITION /* USB */ -#if 1 #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 -#endif + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PING | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_IDE | \ - ADD_VIDEO_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#if definded(CONFIG_MPC5200) + #define CONFIG_CMD_PCI +#endif + +#define CONFIG_CMD_BMP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + #if (TEXT_BASE == 0xFE000000) /* Boot low */ # define CFG_LOWBOOT 1 @@ -303,7 +288,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -319,6 +304,12 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + /* * Various low-level settings */ diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index f5efcd911a5..efb89bf96cc 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -50,11 +50,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -92,12 +87,6 @@ #define CONFIG_NS8382X 1 #endif -#define ADD_PCI_CMD CFG_CMD_PCI - -#else /* MPC5100 */ - -#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ - #endif /* Partitions */ @@ -107,28 +96,29 @@ /* USB */ #if 0 #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 #endif + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_IDE | \ - CFG_CMD_I2C | \ - CFG_CMD_BSP | \ - CFG_CMD_ELF | \ - CFG_CMD_EXT2 | \ - CFG_CMD_DATE | \ - ADD_PCI_CMD ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif + +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_BSP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_DATE + + #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ # define CFG_LOWBOOT 1 @@ -277,7 +267,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -295,6 +285,11 @@ #define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Various low-level settings */ diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 0c1029426c2..6f0d4973f00 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -50,11 +50,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -88,26 +83,23 @@ /* USB */ #if 0 #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 #endif + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_EXT2 | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_BSP | \ - CFG_CMD_ELF) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_BSP +#define CONFIG_CMD_ELF + #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ # define CFG_LOWBOOT 1 @@ -258,7 +250,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -276,6 +268,11 @@ #define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Various low-level settings */ diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index 7151a9ec2e2..3e72c652bc7 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -49,11 +49,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -112,20 +107,20 @@ #define ADD_USB_CMD 0 #endif + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_BSP | \ - CFG_CMD_ELF | \ - ADD_PCI_CMD ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_BSP +#define CONFIG_PCI_CMD +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE + #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ # define CFG_LOWBOOT 1 @@ -263,7 +258,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -281,6 +276,11 @@ #define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Various low-level settings */ diff --git a/include/configs/r5200.h b/include/configs/r5200.h index e1e406bf9b5..05929390010 100644 --- a/include/configs/r5200.h +++ b/include/configs/r5200.h @@ -66,10 +66,18 @@ #define CFG_ENV_IS_IN_FLASH 1 #endif -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_NET ) & ~(CFG_CMD_LOADS | CFG_CMD_LOADB)) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_NET + +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_LOADB + /* Note: We only copy one sectors worth of application code from location * 10200000 for speed purposes. Increase the size if necessary */ @@ -79,7 +87,7 @@ #define CFG_PROMPT "u-boot> " #define CFG_LONGHELP /* undef to save memory */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -- cgit v1.3.1 From b730cda82e362df6a22f4c59c0a9b97e885b1014 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:31:35 -0500 Subject: include/configs: Use new CONFIG_CMD_* in mpc5xx board config files. Signed-off-by: Jon Loeliger --- include/configs/cmi_mpc5xx.h | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h index e4599192941..dbc41e97fbf 100644 --- a/include/configs/cmi_mpc5xx.h +++ b/include/configs/cmi_mpc5xx.h @@ -44,13 +44,24 @@ #define CONFIG_BAUDRATE 57600 -#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \ - CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ASKENV | \ - CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_ENV | CFG_CMD_RUN | \ - CFG_CMD_IMI) -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BDI +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_ENV +#define CONFIG_CMD_RUN +#define CONFIG_CMD_IMI + #if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ @@ -73,7 +84,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -- cgit v1.3.1 From 0b361c916617aff79e647b40f0e43361e0bbaccf Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:31:42 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various a* named board config files. Signed-off-by: Jon Loeliger --- include/configs/acadia.h | 62 ++++++++++++++++++++++++------------------ include/configs/adsvix.h | 17 +++++++++--- include/configs/aev.h | 49 ++++++++++++++++----------------- include/configs/alpr.h | 45 ++++++++++++++++-------------- include/configs/armadillo.h | 8 ++++-- include/configs/assabet.h | 15 ++++++---- include/configs/at91rm9200dk.h | 28 +++++++++++-------- include/configs/atc.h | 24 ++++++++-------- include/configs/atstk1002.h | 57 +++++++++++++------------------------- 9 files changed, 160 insertions(+), 145 deletions(-) (limited to 'include') diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 517d130d5ca..3f5d025ac8e 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -123,10 +123,8 @@ #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#define _CFG_CMD_INCLUDE (CFG_CMD_ALL) #else #define CFG_NO_FLASH 1 /* No NOR on Acadia when NAND-booting */ -#define _CFG_CMD_INCLUDE ((CFG_CMD_ALL) & ~(CFG_CMD_FLASH | CFG_CMD_IMLS)) #endif #ifdef CFG_ENV_IS_IN_FLASH @@ -301,27 +299,39 @@ #define CONFIG_SUPPORT_VFAT -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & _CFG_CMD_INCLUDE) | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DTT | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_USB) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DTT +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_USB + +/* + * No NOR on Acadia when NAND-booting + */ +#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#endif + + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -330,7 +340,7 @@ *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -373,7 +383,7 @@ */ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ #endif @@ -489,7 +499,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h index c4108912a6b..0d64013b212 100644 --- a/include/configs/adsvix.h +++ b/include/configs/adsvix.h @@ -68,10 +68,19 @@ #define CONFIG_DOS_PARTITION 1 -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_NET) | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_IDE | CFG_CMD_PCMCIA) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PCMCIA + +#undef CONFIG_CMD_NET + #undef CONFIG_SHOW_BOOT_PROGRESS @@ -162,7 +171,7 @@ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ /* #define CONFIG_INITRD_TAG 1 */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/aev.h b/include/configs/aev.h index f6f530cedbd..ecd84d3e20c 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -44,11 +44,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -98,27 +93,26 @@ #define CFG_CMD_POST_DIAG 0 #endif + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_BMP_CMD | \ - CFG_CMD_PCI | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_POST +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP + #define CONFIG_TIMESTAMP /* display image timestamps */ @@ -324,7 +318,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -343,6 +337,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, * which is normally part of the default commands (CFV_CMD_DFL) diff --git a/include/configs/alpr.h b/include/configs/alpr.h index df057d9c953..27f2831b525 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -210,25 +210,28 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_FPGA | \ - CFG_CMD_NAND | \ - CFG_CMD_REGINFO) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -237,7 +240,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -358,7 +361,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h index 9a1c5596b7a..7c77fa73115 100644 --- a/include/configs/armadillo.h +++ b/include/configs/armadillo.h @@ -73,10 +73,12 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL) /* | CFG_CMD_JFFS2)*/ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "root=/dev/ram0 rootfstype=ext2 console=ttyAM0,115200" diff --git a/include/configs/assabet.h b/include/configs/assabet.h index 1a69ebe0dae..7c6a65ac0a6 100644 --- a/include/configs/assabet.h +++ b/include/configs/assabet.h @@ -66,18 +66,23 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP + + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp" #define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" #define CFG_AUTOLOAD "n" /* No autoload */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index 8fad55d81cf..db57dc11f12 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -97,18 +97,22 @@ #define CONFIG_BOOTDELAY 3 /* #define CONFIG_ENV_OVERWRITE 1 */ -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | CFG_CMD_MII |\ - CFG_CMD_DHCP ) & \ - ~(CFG_CMD_BDI | \ - CFG_CMD_IMI | \ - CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_FPGA | \ - CFG_CMD_MISC | \ - CFG_CMD_LOADS )) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP + +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_LOADS + #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/atc.h b/include/configs/atc.h index bf6c1709d90..cb4e7472ec7 100644 --- a/include/configs/atc.h +++ b/include/configs/atc.h @@ -126,25 +126,27 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_PCI | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_DATE | \ - CFG_CMD_IDE) +/* + * Command line configuration. + */ +#include -#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PCMCIA +#define CONFIG_CMD_DATE +#define CONFIG_CMD_IDE -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +#define CONFIG_DOS_PARTITION /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -285,7 +287,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index beaf3851dc8..90fe8a55c5b 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -111,44 +111,25 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_SUBNETMASK \ | CONFIG_BOOTP_GATEWAY) -#define CONFIG_COMMANDS (CFG_CMD_BDI \ - | CFG_CMD_LOADS \ - | CFG_CMD_LOADB \ - | CFG_CMD_IMI \ - /* | CFG_CMD_CACHE */ \ - | CFG_CMD_FLASH \ - | CFG_CMD_MEMORY \ - | CFG_CMD_NET \ - | CFG_CMD_ENV \ - /* | CFG_CMD_IRQ */ \ - | CFG_CMD_BOOTD \ - | CFG_CMD_CONSOLE \ - /* | CFG_CMD_EEPROM */ \ - | CFG_CMD_ASKENV \ - | CFG_CMD_RUN \ - | CFG_CMD_ECHO \ - /* | CFG_CMD_I2C */ \ - | CFG_CMD_REGINFO \ - /* | CFG_CMD_DATE */ \ - | CFG_CMD_DHCP \ - /* | CFG_CMD_AUTOSCRIPT */ \ - /* | CFG_CMD_MII */ \ - | CFG_CMD_MISC \ - /* | CFG_CMD_SDRAM */ \ - /* | CFG_CMD_DIAG */ \ - /* | CFG_CMD_HWFLOW */ \ - /* | CFG_CMD_SAVES */ \ - /* | CFG_CMD_SPI */ \ - /* | CFG_CMD_PING */ \ - | CFG_CMD_MMC \ - | CFG_CMD_FAT \ - | CFG_CMD_IMLS \ - /* | CFG_CMD_ITEST */ \ - | CFG_CMD_EXT2 \ - | CFG_CMD_JFFS2 \ - ) - -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC +#define CONFIG_CMD_REGINFO + +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + + #define CONFIG_ATMEL_USART 1 #define CONFIG_MACB 1 -- cgit v1.3.1 From ba2351f9d1e841bd00ea6dad1e3c16d0259ad264 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:31:49 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various b* named board config files. Signed-off-by: Jon Loeliger --- include/configs/bamboo.h | 63 ++++++++++++++++++------------------ include/configs/barco.h | 18 ++++++----- include/configs/bf533-ezkit.h | 23 ++++++++------ include/configs/bf533-stamp.h | 49 ++++++++++++---------------- include/configs/bf537-stamp.h | 74 +++++++++++++++++++++++-------------------- include/configs/bf561-ezkit.h | 29 +++++++++-------- include/configs/bubinga.h | 49 ++++++++++++++-------------- 7 files changed, 156 insertions(+), 149 deletions(-) (limited to 'include') diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index d58344d7177..c1fdaf8d570 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -316,45 +316,46 @@ #define USB_2_0_DEVICE #endif /*CONFIG_440EP*/ + +/* + * Command line configuration. + */ +#include + + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_SNTP + #ifdef CONFIG_BAMBOO_NAND -#define _CFG_CMD_NAND CFG_CMD_NAND -#else -#define _CFG_CMD_NAND 0 -#endif /* CONFIG_BAMBOO_NAND */ +#define CONFIG_CMD_NAND +#endif -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_USB | \ - CFG_CMD_FAT | \ - CFG_CMD_EXT2 | \ - _CFG_CMD_NAND | \ - CFG_CMD_SNTP ) #define CONFIG_SUPPORT_VFAT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -407,7 +408,7 @@ */ #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -419,7 +420,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/barco.h b/include/configs/barco.h index 624fa1d6e28..225ab8d0e14 100644 --- a/include/configs/barco.h +++ b/include/configs/barco.h @@ -78,14 +78,16 @@ CONFIG_BOOTP_BOOTFILESIZE | \ CONFIG_BOOTP_DNS) -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_PCI ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_PCI -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */ #define CONFIG_BOOTDELAY 1 @@ -340,7 +342,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index 65dfc815548..487ca6a1897 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -97,19 +97,22 @@ #define CONFIG_LOADS_ECHO 1 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PING | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_DATE) -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600" +/* + * Command line configuration. + */ +#include -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_DATE + + +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 ip=192.168.0.15:192.168.0.2:192.168.0.1:255.255.255.0:ezkit:eth0:off console=ttyBF0,57600" #define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 79a1404a40d..f93c61e4b7b 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -240,23 +240,6 @@ #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" -#if (CONFIG_DRIVER_SMC91111) -#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ - CFG_CMD_PING | \ - CFG_CMD_ELF | \ - CFG_CMD_CACHE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DATE) - -#else -#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ - CFG_CMD_ELF | \ - CFG_CMD_CACHE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DATE) -#endif #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) #if (CONFIG_DRIVER_SMC91111) @@ -305,20 +288,30 @@ #endif #endif + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_DATE + +#if (CONFIG_DRIVER_SMC91111) +#define CONFIG_CMD_PING +#endif + #if (CONFIG_SOFT_I2C) -#define CONFIG_COMMANDS2 CFG_CMD_I2C -#else -#define CONFIG_COMMANDS2 0 -#endif /* CONFIG_SOFT_I2C */ +#define CONFIG_CMD_I2C +#endif #if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT) -#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 | CFG_CMD_DHCP) -#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT) -#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2) +#define CONFIG_CMD_DHCP #endif -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Console settings @@ -345,7 +338,7 @@ #endif #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -395,7 +388,7 @@ /* Enabled below option for CF support */ /* #define CONFIG_STAMP_CF 1 */ -#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE) +#if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE) #define CONFIG_MISC_INIT_R 1 #define CONFIG_DOS_PARTITION 1 diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index f6755acf694..1c23871d80f 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -159,51 +159,58 @@ #if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE) # define CONFIG_BFIN_IDE 1 -# define ADD_IDE_CMD CFG_CMD_IDE -#else -# define ADD_IDE_CMD 0 #endif /*#define CONFIG_BF537_NAND */ /* Add nand flash support */ -#ifdef CONFIG_BF537_NAND -# define ADD_NAND_CMD CFG_CMD_NAND -#else -# define ADD_NAND_CMD 0 -#endif - #define CONFIG_NETCONSOLE 1 #define CONFIG_NET_MULTI 1 + + +/* + * Command line configuration. + */ +#include + +#if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) || (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_DATE + #if (BFIN_CPU == ADSP_BF534) -#define CONFIG_BFIN_CMD (CONFIG_CMD_DFL & ~CFG_CMD_NET) +#undef CONFIG_CMD_NET #else -#define CONFIG_BFIN_CMD (CONFIG_CMD_DFL | CFG_CMD_PING) +#define CONFIG_CMD_PING +#endif + +#if defined(CONFIG_BFIN_CF_IDE) \ + || defined(CONFIG_BFIN_HDD_IDE) \ + || defined(CONFIG_BFIN_TRUE_IDE) +#define CONFIG_CMD_IDE #endif +#endif + + #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) -#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_CACHE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DHCP | \ - ADD_IDE_CMD | \ - ADD_NAND_CMD | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_DATE) -#elif (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) -#define CONFIG_COMMANDS (CONFIG_BFIN_CMD| \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_CACHE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_EEPROM | \ - ADD_IDE_CMD | \ - CFG_CMD_DATE) + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_POST_DIAG + +#ifdef CONFIG_BF537_NAND +#define CONFIG_CMD_NAND #endif +#endif + + + + #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" #define CONFIG_LOADADDR 0x1000000 @@ -256,9 +263,6 @@ #endif #endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #if (BFIN_BOOT_MODE == BF537_SPI_MASTER_BOOT) #if (BFIN_CPU == ADSP_BF534) #define CFG_PROMPT "serial_bf534> " /* Monitor Command Prompt */ @@ -277,7 +281,7 @@ #endif #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 8d826faaa0d..40f5abc7438 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -164,12 +164,6 @@ #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" #if (CONFIG_DRIVER_SMC91111) -#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ - CFG_CMD_PING | \ - CFG_CMD_ELF | \ - CFG_CMD_CACHE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_DHCP) #define CONFIG_EXTRA_ENV_SETTINGS \ "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \ @@ -186,20 +180,27 @@ "cp.b $(loadaddr) 0x20000000 $(filesize)\0" \ "" #else -#define CONFIG_COMMANDS1 (CONFIG_CMD_DFL | \ - CFG_CMD_ELF | \ - CFG_CMD_CACHE | \ - CFG_CMD_JFFS2) #define CONFIG_EXTRA_ENV_SETTINGS \ "ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \ "flashboot=bootm 0x20100000\0" \ "" #endif -#define CONFIG_COMMANDS ( CONFIG_COMMANDS1 | CONFIG_COMMANDS2 ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_JFFS2 + +#if defined(CONFIG_DRIVER_SMC91111) +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#endif + /* * Console settings @@ -208,7 +209,7 @@ #define CFG_PROMPT "ezkit> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 10c48143117..16892590e00 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -137,25 +137,28 @@ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -166,7 +169,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -219,7 +222,7 @@ #define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ -#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) +#if defined(CONFIG_CMD_EEPROM) #define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ #endif @@ -314,7 +317,7 @@ */ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405EP CPU */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -426,7 +429,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -- cgit v1.3.1 From 37e4f24b87fa255ae456d193b7cd23c18dd1d56b Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:31:56 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various c* named board config files. Signed-off-by: Jon Loeliger --- include/configs/c2mon.h | 23 ++++++++++++---------- include/configs/canmb.h | 38 ++++++++++++++++++------------------ include/configs/cerf250.h | 10 ++++++---- include/configs/cm4008.h | 12 ++++++++---- include/configs/cm41xx.h | 12 ++++++++---- include/configs/cmc_pu2.h | 42 ++++++++++++++++++++-------------------- include/configs/cobra5272.h | 18 +++++++++-------- include/configs/cogent_mpc8260.h | 18 +++++++++++------ include/configs/cogent_mpc8xx.h | 18 +++++++++++------ include/configs/cradle.h | 8 +++++--- include/configs/csb226.h | 23 ++++++++++++++++++---- include/configs/csb272.h | 36 +++++++++++++++++----------------- include/configs/csb472.h | 37 ++++++++++++++++++----------------- include/configs/csb637.h | 31 +++++++++++++++-------------- 14 files changed, 187 insertions(+), 139 deletions(-) (limited to 'include') diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h index ae75539c37a..946b179f152 100644 --- a/include/configs/c2mon.h +++ b/include/configs/c2mon.h @@ -77,15 +77,18 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options @@ -98,7 +101,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -174,7 +177,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/canmb.h b/include/configs/canmb.h index ec6d57e1e69..9bb5b830471 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -38,11 +38,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - #define CONFIG_BOARD_EARLY_INIT_R /* @@ -52,21 +47,21 @@ #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IMMAP | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP + /* * MUST be low boot - HIGHBOOT is not supported anymore @@ -181,7 +176,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -199,6 +194,11 @@ #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Various low-level settings */ diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index 6997c7a6f43..0240ef2194a 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -61,10 +61,12 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_COMMANDS (CONFIG_CMD_DFL) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + #define CONFIG_BOOTDELAY 3 #define CONFIG_ETHADDR 00:D0:CA:F1:3C:D2 @@ -75,7 +77,7 @@ #define CONFIG_BOOTARGS "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400" #define CONFIG_CMDLINE_TAG -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h index 5947c2a3193..d0ac46b3caf 100644 --- a/include/configs/cm4008.h +++ b/include/configs/cm4008.h @@ -58,10 +58,14 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -#undef CONFIG_COMMANDS -#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV)) + +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_ENV + #define CONFIG_BOOTDELAY 0 #define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200" diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h index e62fc06337b..b62e3611736 100644 --- a/include/configs/cm41xx.h +++ b/include/configs/cm41xx.h @@ -58,10 +58,14 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -#undef CONFIG_COMMANDS -#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~(CFG_CMD_NONSTD | CFG_CMD_ENV)) + +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_ENV + #define CONFIG_BOOTDELAY 0 #define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200" diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index 572a70f1200..9e70900cb70 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -104,35 +104,35 @@ #define CFG_I2C_EEPROM_ADDR 0x50 #define CFG_I2C_EEPROM_ADDR_LEN 1 #define CFG_I2C_EEPROM_ADDR_OVERFLOW +#else +#define CONFIG_TIMESTAMP #endif /* still about 20 kB free with this defined */ #define CFG_LONGHELP #define CONFIG_BOOTDELAY 1 -#ifdef CONFIG_HARD_I2C -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) & \ - ~(CFG_CMD_FPGA | CFG_CMD_MISC) ) -#else -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) & \ - ~(CFG_CMD_FPGA | CFG_CMD_MISC) ) -#define CONFIG_TIMESTAMP + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC + +#if defined(CONFIG_HARD_I2C) + #define CONFIG_CMD_DATE + #define CONFIG_CMD_EEPROM + #define CONFIG_CMD_I2C #endif -#define CFG_LONGHELP -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +#define CFG_LONGHELP #define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ #define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 9033fa88ed1..4ab60cf2717 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -130,16 +130,18 @@ #define CFG_ENV_IS_IN_FLASH 1 #endif -/* --- - * Define which commmands should be available at u-boot command prompt - * --- + +/* + * Command line configuration. */ +#include + +#define CONFIG_CMD_PING -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | CFG_CMD_PING & ~(CFG_CMD_LOADS | \ -CFG_CMD_LOADB) | CFG_CMD_MII) +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_MII -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* *----------------------------------------------------------------------------- @@ -184,7 +186,7 @@ from which user programs will be started */ #define CFG_LONGHELP /* undef to save memory */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h index aea2e64365a..ac1baf3b4e5 100644 --- a/include/configs/cogent_mpc8260.h +++ b/include/configs/cogent_mpc8260.h @@ -88,10 +88,16 @@ #define CONFIG_BAUDRATE 9600 #endif -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL|CFG_CMD_KGDB)&~CFG_CMD_NET) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_KGDB + +#undef CONFIG_CMD_NET + #ifdef DEBUG #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ @@ -102,7 +108,7 @@ #define CONFIG_BOOTARGS "root=/dev/ram rw" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -124,7 +130,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -256,7 +262,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ #endif diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h index 80962d35fdf..c246ff5e648 100644 --- a/include/configs/cogent_mpc8xx.h +++ b/include/configs/cogent_mpc8xx.h @@ -59,10 +59,16 @@ #define CFG_I2C_SLAVE 0x7F -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_KGDB | CFG_CMD_I2C) & ~CFG_CMD_NET) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_KGDB +#define CONFIG_CMD_I2C + +#undef CONFIG_CMD_NET -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ @@ -73,7 +79,7 @@ #define CONFIG_BOOTARGS "root=/dev/ram rw" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #define CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -88,7 +94,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -200,7 +206,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/cradle.h b/include/configs/cradle.h index 776e1d2b7f7..5d6419fe1f2 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -61,10 +61,12 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200" diff --git a/include/configs/csb226.h b/include/configs/csb226.h index f04102e95c5..04bdf867b17 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -57,10 +57,25 @@ #define CONFIG_BAUDRATE 19200 #undef CONFIG_MISC_INIT_R /* not used yet */ -#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_DHCP|CFG_CMD_CACHE) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BDI +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_IMI +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_ENV +#define CONFIG_CMD_RUN +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_CACHE + #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttyS0,19200 ip=192.168.1.10,192.168.1.5,,255,255,255,0,csb root=/dev/nfs, ether=0,0x08000000,eth0" @@ -73,7 +88,7 @@ #define CONFIG_CMDLINE_TAG 1 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/csb272.h b/include/configs/csb272.h index 27d64c1e434..63ea24edea0 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -79,24 +79,24 @@ #define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ CONFIG_BOOTP_DNS2 | \ CONFIG_BOOTP_BOOTFILESIZE ) + + /* - * U-Boot Monitor Command Line Functions Configuration - * + * Command line configuration. */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_PCI | \ - CFG_CMD_DATE | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_DHCP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PCI +#define CONFIG_CMD_DATE +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + /* * Serial download configuration @@ -109,7 +109,7 @@ * KGDB Configuration * */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -125,7 +125,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 09d52ded9ee..1fef94f76cf 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -79,24 +79,25 @@ #define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ CONFIG_BOOTP_DNS2 | \ CONFIG_BOOTP_BOOTFILESIZE ) + + + /* - * U-Boot Monitor Command Line Functions Configuration - * + * Command line configuration. */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_PCI | \ - CFG_CMD_DATE | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_DHCP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PCI +#define CONFIG_CMD_DATE +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + /* * Serial download configuration @@ -109,7 +110,7 @@ * KGDB Configuration * */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -125,7 +126,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/csb637.h b/include/configs/csb637.h index 071d5b7f36c..ac2fe54409d 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -99,20 +99,23 @@ #define CONFIG_BOOTDELAY 3 /* #define CONFIG_ENV_OVERWRITE 1 */ -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING ) & \ - ~(CFG_CMD_BDI | \ - CFG_CMD_IMI | \ - CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_FPGA | \ - CFG_CMD_MISC | \ - CFG_CMD_LOADS )) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING + +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_LOADS + #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 -- cgit v1.3.1 From ab999ba1b31ebe78dd16374394a55d7c6e5aa6e4 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:32:03 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various d* named board config files. Signed-off-by: Jon Loeliger --- include/configs/dbau1x00.h | 49 +++++++++++++++++++++++++++++++++++----------- include/configs/debris.h | 39 +++++++++++++++++++----------------- include/configs/delta.h | 32 ++++++++++++++++++------------ include/configs/dnp1110.h | 10 ++++++---- 4 files changed, 84 insertions(+), 46 deletions(-) (limited to 'include') diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index 4cc5085293b..c0f5a099001 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -75,21 +75,48 @@ #ifdef CONFIG_DBAU1550 /* Boot from flash by default, revert to bootp */ #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" - -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_NET) & \ - ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FPGA | CFG_CMD_IDE | \ - CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \ - CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C)) #else /* CONFIG_DBAU1550 */ #define CONFIG_BOOTCOMMAND "bootp;bootm" - -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \ - ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \ - CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | \ - CFG_CMD_ELF | CFG_CMD_BDI | CFG_CMD_BEDBUG)) #endif /* CONFIG_DBAU1550 */ -#include + +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_BEDBUG +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_FAT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_RUN + + +#ifdef CONFIG_DBAU1550 + +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_NET + +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IDE +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_PCMCIA + +#else + +#define CONFIG_CMD_IDE +#define CONFIG_CMD_DHCP + +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS + +#endif + /* * Miscellaneous configurable options diff --git a/include/configs/debris.h b/include/configs/debris.h index 8ff963f55a2..96c76483aaf 100644 --- a/include/configs/debris.h +++ b/include/configs/debris.h @@ -122,23 +122,26 @@ #define CONFIG_BAUDRATE 9600 #define CONFIG_DRAM_SPEED 100 /* MHz */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_KGBD | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_SAVES | \ - CFG_CMD_SDRAM) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_KGBD +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_SDRAM /* @@ -435,7 +438,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/delta.h b/include/configs/delta.h index 15681208b62..7df72800f58 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -87,22 +87,28 @@ #define CONFIG_BAUDRATE 115200 -/* #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) */ + +/* + * Command line configuration. + */ +#include + #ifdef TURN_ON_ETHERNET -# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) + +#define CONFIG_CMD_PING + #else -# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_ENV \ - | CFG_CMD_NAND \ - | CFG_CMD_I2C) \ - & ~(CFG_CMD_NET \ - | CFG_CMD_FLASH \ - | CFG_CMD_IMLS)) -#endif +#define CONFIG_CMD_ENV +#define CONFIG_CMD_NAND +#define CONFIG_CMD_I2C + +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS + +#endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CONFIG_BOOTDELAY -1 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b @@ -114,7 +120,7 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_TIMESTAMP -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h index 9ac2856f653..e58a2f219c8 100644 --- a/include/configs/dnp1110.h +++ b/include/configs/dnp1110.h @@ -66,10 +66,12 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" @@ -80,7 +82,7 @@ #define CONFIG_BOOTFILE "dnp1110" #define CONFIG_BOOTCOMMAND "tftp; bootm" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -- cgit v1.3.1 From 1bec3d3002d3bbbae6f2468a0f7376db1120d33e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:32:10 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various e* named board config files. Signed-off-by: Jon Loeliger --- include/configs/eXalion.h | 23 ++++++++-------- include/configs/ebony.h | 49 +++++++++++++++++---------------- include/configs/ep7312.h | 12 ++++++--- include/configs/ep8248.h | 34 ++++++++++++----------- include/configs/ep8260.h | 69 +++++++++++++++++++++++------------------------ include/configs/ep82xxm.h | 45 ++++++++++++++++--------------- include/configs/evb4510.h | 13 ++++++--- 7 files changed, 131 insertions(+), 114 deletions(-) (limited to 'include') diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h index a014c7c07f8..ac1ef959a70 100644 --- a/include/configs/eXalion.h +++ b/include/configs/eXalion.h @@ -58,17 +58,18 @@ /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_FLASH | \ - CFG_CMD_SDRAM | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ENV | \ - CFG_CMD_PCI ) +/* + * Command line configuration. + */ +#include -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_ENV +#define CONFIG_CMD_PCI /*----------------------------------------------------------------------- @@ -398,7 +399,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 4a1385ccb92..d86a9efbefd 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -208,26 +208,29 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -236,7 +239,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -286,7 +289,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -298,7 +301,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h index bdda6292ed7..12be15102f5 100644 --- a/include/configs/ep7312.h +++ b/include/configs/ep7312.h @@ -64,10 +64,14 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_JFFS2) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_JFFS2 + #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" @@ -78,7 +82,7 @@ /*#define CONFIG_BOOTFILE "impa7" */ #define CONFIG_BOOTCOMMAND "bootp;bootm" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h index 04147a55d1d..44c4388b208 100644 --- a/include/configs/ep8248.h +++ b/include/configs/ep8248.h @@ -123,23 +123,25 @@ #define CONFIG_BAUDRATE 38400 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ - | CFG_CMD_I2C \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -157,7 +159,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -183,7 +185,7 @@ #define CFG_DIRECT_FLASH_TFTP -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#if defined(CONFIG_CMD_JFFS2) #define CFG_JFFS2_FIRST_BANK 0 #define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS #define CFG_JFFS2_FIRST_SECTOR 0 @@ -192,7 +194,7 @@ #define CFG_JFFS_CUSTOM_PART #endif /* CFG_CMD_JFFS2 */ -#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#if defined(CONFIG_CMD_I2C) #define CONFIG_HARD_I2C 1 /* To enable I2C support */ #define CFG_I2C_SPEED 100000 /* I2C speed */ #define CFG_I2C_SLAVE 0x7F /* I2C slave address */ @@ -240,7 +242,7 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h index 68625193091..065f967e173 100644 --- a/include/configs/ep8260.h +++ b/include/configs/ep8260.h @@ -291,37 +291,39 @@ #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " -/* What U-Boot subsytems do you want enabled? */ + /* -*/ -#define CONFIG_COMMANDS ( CFG_CMD_ALL & \ - ~( CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_DCR | \ - CFG_CMD_DHCP | \ - CFG_CMD_DISPLAY | \ - CFG_CMD_DOC | \ - CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_IDE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_KGDB | \ - CFG_CMD_MII | \ - CFG_CMD_MMC | \ - CFG_CMD_NAND | \ - CFG_CMD_PCI | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_REISER | \ - CFG_CMD_SCSI | \ - CFG_CMD_SPI | \ - CFG_CMD_UNIVERSE| \ - CFG_CMD_USB | \ - CFG_CMD_VFD | \ - CFG_CMD_XIMG ) ) + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_BMP +#undef CONFIG_CMD_BSP +#undef CONFIG_CMD_DCR +#undef CONFIG_CMD_DHCP +#undef CONFIG_CMD_DISPLAY +#undef CONFIG_CMD_DOC +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_EXT2 +#undef CONFIG_CMD_FDC +#undef CONFIG_CMD_FDOS +#undef CONFIG_CMD_HWFLOW +#undef CONFIG_CMD_IDE +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_KGDB +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_MMC +#undef CONFIG_CMD_NAND +#undef CONFIG_CMD_PCI +#undef CONFIG_CMD_PCMCIA +#undef CONFIG_CMD_REISER +#undef CONFIG_CMD_SCSI +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_UNIVERSE +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_VFD +#undef CONFIG_CMD_XIMG /* Where do the internal registers live? */ @@ -342,13 +344,10 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -496,7 +495,7 @@ */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index a77ccef63b9..5fa70164e94 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h @@ -108,22 +108,25 @@ #define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ - | CFG_CMD_I2C \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - | CFG_CMD_DATE \ - | CFG_CMD_DTT \ - | CFG_CMD_EEPROM \ - | CFG_CMD_PCI \ - | CFG_CMD_DIAG \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DTT +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_PCI +#define CONFIG_CMD_DIAG + #define CONFIG_ETHADDR 00:10:EC:00:88:65 #define CONFIG_HAS_ETH1 @@ -138,7 +141,7 @@ #define CONFIG_AUTO_COMPLETE 1 #define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3 ETHERNET" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -156,7 +159,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "ep82xxm=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -308,7 +311,7 @@ #define CFG_DIRECT_FLASH_TFTP -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#if defined(CONFIG_CMD_JFFS2) #define CFG_JFFS2_FIRST_BANK 0 #define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS #define CFG_JFFS2_FIRST_SECTOR 0 @@ -317,7 +320,7 @@ #define CFG_JFFS_CUSTOM_PART #endif /* CFG_CMD_JFFS2 */ -#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#if defined(CONFIG_CMD_I2C) #define CONFIG_HARD_I2C 1 /* To enable I2C support */ #define CFG_I2C_SPEED 100000 /* I2C speed */ #define CFG_I2C_SLAVE 0x7F /* I2C slave address */ @@ -358,7 +361,7 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h index 88c2c7437d0..42633bea144 100644 --- a/include/configs/evb4510.h +++ b/include/configs/evb4510.h @@ -74,10 +74,15 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING + + #define CONFIG_ETHADDR 00:40:95:36:35:33 #define CONFIG_NETMASK 255.255.255.0 @@ -89,7 +94,7 @@ #define CONFIG_BOOTCOMMAND "tftp 100000 uImage" /* #define CONFIG_BOOTARGS "console=ttyS0,19200 initrd=0x100a0040,530K root=/dev/ram keepinitrd" */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -- cgit v1.3.1 From 72eb0efaed7048afcc61fc6f0085c49394b5dc36 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:32:19 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various g* named board config files. Signed-off-by: Jon Loeliger --- include/configs/evb4510.h | 1 - include/configs/gcplus.h | 15 ++++++++++----- include/configs/gth2.h | 26 +++++++++++++++++++++----- include/configs/gw8260.h | 30 +++++++++++++++++------------- 4 files changed, 48 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h index 42633bea144..0a4aeb95ade 100644 --- a/include/configs/evb4510.h +++ b/include/configs/evb4510.h @@ -83,7 +83,6 @@ #define CONFIG_CMD_PING - #define CONFIG_ETHADDR 00:40:95:36:35:33 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 10.0.0.11 diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h index b68a2dca09c..0aecb38e440 100644 --- a/include/configs/gcplus.h +++ b/include/configs/gcplus.h @@ -79,18 +79,23 @@ #define CONFIG_BAUDRATE 38400 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP + + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySA0,38400n8 mtdparts=sa1100-flash:1m@0(zImage),3m@1m(ramdisk.gz),12m@4m(userfs) root=/dev/nfs ip=bootp" #define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" #define CFG_AUTOLOAD "n" /* No autoload */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 38400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/gth2.h b/include/configs/gth2.h index a49ed3bae3e..0247b7d25c0 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -71,12 +71,28 @@ /* Boot from Compact flash partition 2 as default */ #define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm" -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP ) & \ - ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \ - CFG_CMD_MII | CFG_CMD_LOADS | CFG_CMD_LOADB | CFG_CMD_ELF | \ - CFG_CMD_BDI | CFG_CMD_BEDBUG | CFG_CMD_NFS | CFG_CMD_AUTOSCRIPT )) -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_IDE +#define CONFIG_CMD_DHCP + +#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_FAT +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_BEDBUG +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_AUTOSCRIPT + /* * Miscellaneous configurable options diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index 4f83b1945d3..cf3eb3f5a47 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -300,14 +300,21 @@ /* Monitor Command Prompt */ #define CFG_PROMPT "=> " -/* What U-Boot subsytems do you want enabled? */ -#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF | \ - CFG_CMD_ASKENV | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_MII) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII + +#undef CONFIG_CMD_KGDB + /* Where do the internal registers live? */ #define CFG_IMMR 0xf0000000 @@ -331,13 +338,10 @@ #define CONFIG_GW8260 1 /* on an GW8260 Board */ #define CONFIG_CPM2 1 /* Has a CPM2 */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -473,7 +477,7 @@ */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From 48d5d102a2f2e619c92050b9aedbb69689185bc0 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:32:25 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various h* named board config files. Signed-off-by: Jon Loeliger --- include/configs/hermes.h | 16 ++++++------- include/configs/hmi1001.h | 40 +++++++++++++++---------------- include/configs/hymod.h | 60 ++++++++++++++++++++++++----------------------- 3 files changed, 58 insertions(+), 58 deletions(-) (limited to 'include') diff --git a/include/configs/hermes.h b/include/configs/hermes.h index 91117bab726..f1cc8d263f8 100644 --- a/include/configs/hermes.h +++ b/include/configs/hermes.h @@ -64,23 +64,21 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_COMMANDS CONFIG_CMD_DFL -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/*----------------------------------------------------------------------*/ +/* + * Command line configuration. + */ +#include -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -/*----------------------------------------------------------------------*/ +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -157,7 +155,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index 4d813d8be78..7e1897a7593 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -38,11 +38,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - #define CONFIG_BOARD_EARLY_INIT_R /* @@ -55,22 +50,22 @@ /* Partitions */ #define CONFIG_DOS_PARTITION + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DISPLAY | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DISPLAY +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SNTP + #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ @@ -222,7 +217,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -231,6 +226,11 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* Enable an alternate, more extensive memory test */ #define CFG_ALT_MEMTEST diff --git a/include/configs/hymod.h b/include/configs/hymod.h index 8cad98dbd29..0fdfb1523e5 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -174,32 +174,34 @@ #define CONFIG_LAST_STAGE_INIT -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_BEDBUG | \ - CFG_CMD_BMP | \ - CFG_CMD_DISPLAY | \ - CFG_CMD_DOC | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_FPGA | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_IDE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NAND | \ - CFG_CMD_MMC | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_PCI | \ - CFG_CMD_USB | \ - CFG_CMD_REISER | \ - CFG_CMD_SCSI | \ - CFG_CMD_SPI | \ - CFG_CMD_UNIVERSE| \ - CFG_CMD_VFD | \ - CFG_CMD_XIMG ) ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_BEDBUG +#undef CONFIG_CMD_BMP +#undef CONFIG_CMD_DISPLAY +#undef CONFIG_CMD_DOC +#undef CONFIG_CMD_EXT2 +#undef CONFIG_CMD_FDC +#undef CONFIG_CMD_FDOS +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_HWFLOW +#undef CONFIG_CMD_IDE +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_NAND +#undef CONFIG_CMD_MMC +#undef CONFIG_CMD_PCMCIA +#undef CONFIG_CMD_PCI +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_REISER +#undef CONFIG_CMD_SCSI +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_UNIVERSE +#undef CONFIG_CMD_VFD +#undef CONFIG_CMD_XIMG + #ifdef DEBUG #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ @@ -218,7 +220,7 @@ #define DEBUG_BOOTKEYS 0 #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -247,7 +249,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -400,7 +402,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ #endif -- cgit v1.3.1 From 1d2c6bc491969f8d8fb34c8e30e8bea7a2af9c31 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:32:32 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various i* named board config files. Signed-off-by: Jon Loeliger --- include/configs/idmr.h | 28 ++++++++++++++-------------- include/configs/impa7.h | 12 ++++++++---- include/configs/incaip.h | 23 ++++++++++++++--------- include/configs/inka4x0.h | 38 +++++++++++++++++++------------------- include/configs/innokom.h | 23 +++++++++++++++++++---- include/configs/integratorap.h | 11 +++++++---- include/configs/integratorcp.h | 20 ++++++++++++-------- include/configs/ixdp425.h | 15 ++++++++++----- include/configs/ixdpg425.h | 22 ++++++++++++---------- 9 files changed, 115 insertions(+), 77 deletions(-) (limited to 'include') diff --git a/include/configs/idmr.h b/include/configs/idmr.h index b1dbe2ccb94..99266334636 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -78,18 +78,18 @@ "u-boot=/tftpboot/idmr/u-boot.bin\0" \ "" + /* - * Commands' definition + * Command line configuration. */ -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ - CFG_CMD_PING | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NET) & \ - ~(CFG_CMD_LOADS | \ - CFG_CMD_LOADB)) +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_NET -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_LOADB /* @@ -115,11 +115,11 @@ #define CFG_PROMPT "=> " #define CFG_LONGHELP /* undef to save memory */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#else /* !(CONFIG_COMMANDS & CFG_CMD_KGDB) */ +#else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#endif /* (CONFIG_COMMANDS & CFG_CMD_KGDB) */ +#endif #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_MAXARGS 16 /* max number of command args */ @@ -206,8 +206,8 @@ "2m(rootfs)," \ "-(user)"; -#if (CONFIG_COMMANDS & CFG_CMD_MII) +#if defined(CONFIG_CMD_MII) #error MII commands don't work on iDMR board and sholud not be enabled. -#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) */ +#endif #endif /* _IDMR_H */ diff --git a/include/configs/impa7.h b/include/configs/impa7.h index 8b841ff546f..6570815696e 100644 --- a/include/configs/impa7.h +++ b/include/configs/impa7.h @@ -63,10 +63,14 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_JFFS2) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_JFFS2 + #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "devfs=mount root=ramfs console=ttyS0,9600" @@ -77,7 +81,7 @@ /*#define CONFIG_BOOTFILE "impa7" */ #define CONFIG_BOOTCOMMAND "bootp;bootm" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/incaip.h b/include/configs/incaip.h index 1c6216be843..ef8f7249574 100644 --- a/include/configs/incaip.h +++ b/include/configs/incaip.h @@ -81,15 +81,20 @@ "" #define CONFIG_BOOTCOMMAND "run flash_self" -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_SNTP ) -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index ad3cf06e950..19f2f194f6a 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -40,11 +40,6 @@ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -76,21 +71,21 @@ #define CONFIG_DOS_PARTITION #define CONFIG_ISO_PARTITION + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FAT | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP | \ - CFG_CMD_USB ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_USB + #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ @@ -239,7 +234,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -248,6 +243,11 @@ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* Enable an alternate, more extensive memory test */ #define CFG_ALT_MEMTEST diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 3cb9ebc454c..38ccf89cd1e 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -54,10 +54,25 @@ #define CONFIG_BAUDRATE 19200 #define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */ -#define CONFIG_COMMANDS (CFG_CMD_BDI|CFG_CMD_LOADB|CFG_CMD_IMI|CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_NET|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO|CFG_CMD_I2C|CFG_CMD_DHCP|CFG_CMD_CACHE) -/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BDI +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IMI +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_RUN + #define CONFIG_BOOTDELAY 3 /* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 2f6e3993be4..3594f4ffd23 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -66,15 +66,18 @@ #define CFG_SERIAL0 0x16000000 #define CFG_SERIAL1 0x17000000 -/*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */ /*#define CONFIG_NET_MULTI */ /*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ -#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) +/* + * Command line configuration. + */ + +#define CONFIG_CMD_IMI +#define CONFIG_CMD_BDI +#define CONFIG_CMD_MEMORY -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 4189f9c995c..a5174293452 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -70,17 +70,21 @@ #define CFG_SERIAL0 0x16000000 #define CFG_SERIAL1 0x17000000 + /* -#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_PCI) -*/ -#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | \ - CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV \ - ) + * Command line configuration. + */ +#define CONFIG_CMD_BDI +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING -/* #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ #if 0 #define CONFIG_BOOTDELAY 2 diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h index 9f9fdb25e2c..8c1ab242f3c 100644 --- a/include/configs/ixdp425.h +++ b/include/configs/ixdp425.h @@ -53,14 +53,19 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF | CFG_CMD_PCI) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_PCI + #define CONFIG_PCI #define CONFIG_NET_MULTI #define CONFIG_EEPRO100 -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -/* These are u-boot generic parameters */ -#include #define CONFIG_BOOTDELAY 3 /*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b*/ @@ -71,7 +76,7 @@ #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" #define CONFIG_CMDLINE_TAG -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h index af4ecf621a3..6c103ce6f32 100644 --- a/include/configs/ixdpg425.h +++ b/include/configs/ixdpg425.h @@ -75,16 +75,18 @@ #define CONFIG_BAUDRATE 115200 #define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_NET | \ - CFG_CMD_MII | \ - CFG_CMD_PING) - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -/* These are u-boot generic parameters */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -- cgit v1.3.1 From bc234c129fa04fb9fa33530930e5cbc6084cd47a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:32:51 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various j* and k* named board config files. Signed-off-by: Jon Loeliger --- include/configs/jupiter.h | 24 ++++++++++----------- include/configs/katmai.h | 53 +++++++++++++++++++++++++---------------------- include/configs/kb9202.h | 25 ++++++++++++---------- include/configs/kvme080.h | 40 +++++++++++++++++++---------------- 4 files changed, 76 insertions(+), 66 deletions(-) (limited to 'include') diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 5b97526fc49..e53b848c34a 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -41,11 +41,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -87,15 +82,15 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP) +#include + +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Autobooting @@ -254,7 +249,7 @@ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -271,6 +266,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Various low-level settings */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index a7eda0773bc..9258e7dd809 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -210,28 +210,31 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_DTT | \ - CFG_CMD_ELF | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_DTT +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + #define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */ #define CONFIG_MII 1 /* MII PHY management */ @@ -254,7 +257,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -420,7 +423,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -432,7 +435,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index 6590f6f5f0d..4741ead8155 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -78,17 +78,20 @@ #define CONFIG_BOOTDELAY 3 #define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ - CFG_CMD_I2C | \ - CFG_CMD_PING | \ - CFG_CMD_DHCP ) & \ - ~(CFG_CMD_BDI | \ - CFG_CMD_FPGA | \ - CFG_CMD_MISC)) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC + #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h index 61cf70576d7..53d6af28cc6 100644 --- a/include/configs/kvme080.h +++ b/include/configs/kvme080.h @@ -67,25 +67,29 @@ #define CONFIG_RTC_DS164x -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP) -#define CONFIG_NETCONSOLE +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP -#include + +#define CONFIG_NETCONSOLE #define CFG_LONGHELP #define CFG_PROMPT "=> " @@ -178,7 +182,7 @@ #define CONFIG_SYS_CLK_FREQ 33333333 #define CFG_CACHELINE_SIZE 32 -#if CONFIG_COMMANDS & CFG_CMD_KGDB +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 #endif -- cgit v1.3.1 From 9bbb1c0820c1fbd3811ab6ee4ba0f6c6f76b27e4 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:32:57 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various l* named board config files. Signed-off-by: Jon Loeliger --- include/configs/lart.h | 10 +++++---- include/configs/logodl.h | 15 +++++++++---- include/configs/lpc2292sodimm.h | 20 ++++++++--------- include/configs/lpd7a400.h | 16 ++++++++------ include/configs/lpd7a404.h | 16 ++++++++------ include/configs/luan.h | 48 +++++++++++++++++++++-------------------- include/configs/lubbock.h | 13 +++++++---- include/configs/lwmon.h | 43 +++++++++++++++++++----------------- 8 files changed, 104 insertions(+), 77 deletions(-) (limited to 'include') diff --git a/include/configs/lart.h b/include/configs/lart.h index a00640bf8e6..98bc3b257b8 100644 --- a/include/configs/lart.h +++ b/include/configs/lart.h @@ -59,10 +59,12 @@ #define CONFIG_BAUDRATE 9600 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" @@ -73,7 +75,7 @@ #define CONFIG_BOOTFILE "elinos-lart" #define CONFIG_BOOTCOMMAND "tftp; bootm" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/logodl.h b/include/configs/logodl.h index 715ed74eade..7c11eeb7071 100644 --- a/include/configs/logodl.h +++ b/include/configs/logodl.h @@ -54,10 +54,17 @@ #define CONFIG_BAUDRATE 19200 #undef CONFIG_MISC_INIT_R /* FIXME: misc_init_r() missing */ -#define CONFIG_COMMANDS (CFG_CMD_FLASH|CFG_CMD_MEMORY|CFG_CMD_ENV|CFG_CMD_RUN|CFG_CMD_ASKENV|CFG_CMD_ECHO) -/* CONFIG_CMD_DFL|CFG_CMD_I2C|CFG_CMD_EEPROM|CFG_CMD_NET|CFG_CMD_JFFS2|CFG_CMD_DHCP) */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_RUN + #define CONFIG_BOOTDELAY 3 /* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */ diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h index 7b6c6953e14..bddfa528a35 100644 --- a/include/configs/lpc2292sodimm.h +++ b/include/configs/lpc2292sodimm.h @@ -68,22 +68,22 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_MMC | \ - CFG_CMD_NET | \ - CFG_CMD_PING) +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #define CONFIG_BOOTDELAY 5 /* diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h index d7d0460ef66..414cb14da8b 100644 --- a/include/configs/lpd7a400.h +++ b/include/configs/lpd7a400.h @@ -55,19 +55,23 @@ #define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ + +/* + * Command line configuration. + */ +#include + #ifndef USE_920T_MMU -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE)) + #define CONFIG_CMD_PING + #undef CONFIG_CMD_CACHE #else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE) + #define CONFIG_CMD_DATE #endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #define CONFIG_BOOTDELAY 3 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h index 4002e6849cc..87815cb170f 100644 --- a/include/configs/lpd7a404.h +++ b/include/configs/lpd7a404.h @@ -55,19 +55,23 @@ #define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ + +/* + * Command line configuration. + */ +#include + #ifndef USE_920T_MMU -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING) & ~(CFG_CMD_CACHE)) + #define CONFIG_CMD_PING) + #undef CONFIG_CMD_CACHE #else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DATE) + #define CONFIG_CMD_DATE #endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #define CONFIG_BOOTDELAY 3 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ diff --git a/include/configs/luan.h b/include/configs/luan.h index cbb59c50eaf..82af2fb0759 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -213,31 +213,33 @@ #define CONFIG_HW_WATCHDOG /* watchdog */ #endif -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - 0) - -/* this must be included AFTER the definition of CONFIG_COMMANDS */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -265,7 +267,7 @@ * PCI stuff *----------------------------------------------------------------------- */ -#if (CONFIG_COMMANDS & CFG_CMD_PCI) +#if defined(CONFIG_CMD_PCI) /* General PCI */ #define CONFIG_PCI /* include pci support */ @@ -279,7 +281,7 @@ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ #define CFG_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */ -#endif /* CONFIG_COMMANDS & CFG_CMD_PCI */ +#endif /* * For booting Linux, the board info and command line data @@ -293,7 +295,7 @@ */ #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -305,7 +307,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index ad1035b6d63..eed589066e0 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -67,10 +67,15 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT + #define CONFIG_BOOTDELAY 3 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b @@ -82,7 +87,7 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_TIMESTAMP -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index 9b4c0046ef4..627bc9cf41e 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -176,28 +176,31 @@ #define CFG_CMD_POST_DIAG 0 #endif -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_SNTP ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BMP +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_POST +#define CONFIG_CMD_SNTP + + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/*----------------------------------------------------------------------*/ /* * Miscellaneous configurable options @@ -210,7 +213,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -276,7 +279,7 @@ */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#if defined(DEBUG) || defiend(CONFIG_CMD_IDE) #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ @@ -370,7 +373,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From 5dc11a511960d490f7f01ffd746edfe6277f99b0 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:33:01 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various m* named board config files. Signed-off-by: Jon Loeliger --- include/configs/mcc200.h | 29 ++++++----- include/configs/ml300.h | 18 ++++--- include/configs/ml401.h | 109 ++++++++++++++---------------------------- include/configs/modnet50.h | 12 +++-- include/configs/motionpro.h | 40 ++++++++-------- include/configs/mp2usb.h | 62 +++++++++++++----------- include/configs/mpc7448hpc2.h | 39 ++++++++------- include/configs/mx1ads.h | 20 ++++---- include/configs/mx1fs2.h | 27 +++++------ 9 files changed, 167 insertions(+), 189 deletions(-) (limited to 'include') diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index c2324a04c91..10e25f02290 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -40,11 +40,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration * @@ -92,22 +87,21 @@ /* USB */ #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE /* automatic software updates (see board/mcc200/auto_update.c) */ #define CONFIG_AUTO_UPDATE 1 + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_USB_CMD | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C) +#include + +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_USB -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Autobooting @@ -291,7 +285,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -307,6 +301,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Various low-level settings */ diff --git a/include/configs/ml300.h b/include/configs/ml300.h index 6762cd61eae..423c6ebbb77 100644 --- a/include/configs/ml300.h +++ b/include/configs/ml300.h @@ -87,13 +87,19 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define REMOVE_COMMANDS (CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_FAT | \ - CFG_CMD_IMLS ) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_NET) \ - & ~REMOVE_COMMANDS) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_NET + +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_FAT +#undef CONFIG_CMD_IMLS + /* #define CONFIG_SYS_CLK_FREQ XPAR_CORE_CLOCK_FREQ_HZ */ /* 300000000 */ diff --git a/include/configs/ml401.h b/include/configs/ml401.h index 3db287784da..9537008e040 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -145,82 +145,45 @@ #define CFG_FLASH_PROTECTION /* hardware flash protection */ #endif /* !FLASH */ -#ifdef FLASH - #ifdef RAMENV - #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\ - CFG_CMD_MEMORY |\ - CFG_CMD_MISC |\ - CFG_CMD_AUTOSCRIPT |\ - CFG_CMD_IRQ |\ - CFG_CMD_ASKENV |\ - CFG_CMD_BDI |\ - CFG_CMD_RUN |\ - CFG_CMD_LOADS |\ - CFG_CMD_LOADB |\ - CFG_CMD_IMI |\ - CFG_CMD_NET |\ - CFG_CMD_CACHE |\ - CFG_CMD_FAT |\ - CFG_CMD_EXT2 |\ - CFG_CMD_JFFS2 |\ - CFG_CMD_ECHO |\ - CFG_CMD_IMLS |\ - CFG_CMD_FLASH |\ - CFG_CMD_MFSL |\ - CFG_CMD_PING \ - ) - #else /* !RAMENV */ - #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\ - CFG_CMD_MEMORY |\ - CFG_CMD_MISC |\ - CFG_CMD_AUTOSCRIPT |\ - CFG_CMD_IRQ |\ - CFG_CMD_ASKENV |\ - CFG_CMD_BDI |\ - CFG_CMD_RUN |\ - CFG_CMD_LOADS |\ - CFG_CMD_LOADB |\ - CFG_CMD_IMI |\ - CFG_CMD_NET |\ - CFG_CMD_CACHE |\ - CFG_CMD_IMLS |\ - CFG_CMD_FLASH |\ - CFG_CMD_PING |\ - CFG_CMD_ENV |\ - CFG_CMD_FAT |\ - CFG_CMD_EXT2 |\ - CFG_CMD_JFFS2 |\ - CFG_CMD_ECHO |\ - CFG_CMD_MFSL |\ - CFG_CMD_SAVES \ - ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_BDI +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IMI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_MFSL +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN + +#if defined(FLASH) + #define CONFIG_CMD_ECHO + #define CONFIG_CMD_FLASH + #define CONFIG_CMD_IMLS + #define CONFIG_CMD_JFFS2 + + #if !defined(RAMENV) + #define CONFIG_CMD_ENV + #define CONFIG_CMD_SAVES #endif +#endif + + -#else /* !FLASH */ - #define CONFIG_COMMANDS (CONFIG__CMD_DFL |\ - CFG_CMD_MEMORY |\ - CFG_CMD_MISC |\ - CFG_CMD_AUTOSCRIPT |\ - CFG_CMD_IRQ |\ - CFG_CMD_ASKENV |\ - CFG_CMD_BDI |\ - CFG_CMD_RUN |\ - CFG_CMD_LOADS |\ - CFG_CMD_FAT |\ - CFG_CMD_EXT2 |\ - CFG_CMD_LOADB |\ - CFG_CMD_IMI |\ - CFG_CMD_NET |\ - CFG_CMD_CACHE |\ - CFG_CMD_MFSL |\ - CFG_CMD_PING \ - ) -#endif /* !FLASH */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#if defined(CONFIG_CMD_JFFS2) /* JFFS2 partitions */ #define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */ #define MTDIDS_DEFAULT "nor0=ml401-0" diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h index 20287674fab..33ae43efe88 100644 --- a/include/configs/modnet50.h +++ b/include/configs/modnet50.h @@ -65,10 +65,14 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_JFFS2)) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_JFFS2 + #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_IPADDR 192.168.30.2 @@ -81,7 +85,7 @@ #define CONFIG_BOOTCOMMAND "bootm 0x10020000 0x100a0000" #define CONFIG_BOOTARGS "console=ttyS0,38400 initrd=0x100a0040,530K root=/dev/ram keepinitrd" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index e3899a5ab40..7a61e493956 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -37,28 +37,26 @@ /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_I2C | \ - CFG_CMD_DATE | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DTT) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MII +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DATE +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_DTT /* diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index 04f1f240808..3a6224012a2 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -123,36 +123,44 @@ #define CONFIG_BOOTDELAY 3 -#ifdef CONFIG_HARD_I2C -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP | \ - CFG_CMD_MISC)) -#else -#define CONFIG_COMMANDS \ - ((CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP | \ - CFG_CMD_USB | \ - CFG_CMD_CACHE) & \ - ~(CFG_CMD_BDI | \ - CFG_CMD_IMI | \ - CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_FPGA | \ - CFG_CMD_MISC | \ - CFG_CMD_LOADS )) + +#if !defined(CONFIG_HARD_I2C) #define CONFIG_TIMESTAMP #endif -#define CFG_LONGHELP -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + +#if defined(CONFIG_HARD_I2C) + + #define CONFIG_CMD_DATE + #define CONFIG_CMD_EEPROM + #define CONFIG_CMD_I2C + #define CONFIG_CMD_MISC + +#else + + #define CONFIG_CMD_USB + #define CONFIG_CMD_CACHE + + #undef CONFIG_CMD_AUTOSCRIPT + #undef CONFIG_CMD_BDI + #undef CONFIG_CMD_FPGA + #undef CONFIG_CMD_IMI + #undef CONFIG_CMD_LOADS + #undef CONFIG_CMD_MISC + +#endif + + +#define CFG_LONGHELP #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM 0x20000000 diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 243a3f6c8fc..36ce9bf8eea 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -149,22 +149,25 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_CACHE \ - | CFG_CMD_PCI \ - | CFG_CMD_I2C \ - | CFG_CMD_SDRAM \ - | CFG_CMD_EEPROM \ - | CFG_CMD_FLASH \ - | CFG_CMD_ENV \ - | CFG_CMD_BSP \ - | CFG_CMD_DHCP \ - | CFG_CMD_PING \ - | CFG_CMD_DATE) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_PCI +#define CONFIG_CMD_I2C +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_ENV +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_DATE + /*set date in u-boot*/ #define CONFIG_RTC_M48T35A @@ -182,7 +185,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ #else @@ -387,7 +390,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h index 7f3dfd5c987..0ae2780f202 100644 --- a/include/configs/mx1ads.h +++ b/include/configs/mx1ads.h @@ -78,25 +78,23 @@ #define CONFIG_BAUDRATE 115200 -/*********************************************************** - * Command definition - ***********************************************************/ -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - CFG_CMD_REGINFO | \ - CFG_CMD_ELF) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_ELF -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "root=/dev/msdk mem=48M" #define CONFIG_BOOTFILE "mx1ads" #define CONFIG_BOOTCOMMAND "tftp; bootm" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h index 9816be8dc4f..47ca0f1eee2 100644 --- a/include/configs/mx1fs2.h +++ b/include/configs/mx1fs2.h @@ -34,22 +34,21 @@ #undef _CONFIG_UART4 /* internal uart 4 */ #undef CONFIG_SILENT_CONSOLE /* use this to disable output */ + /* - * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if - * neccessary in include/cmd_confdefs.h file. (Un)comment for getting - * functionality or size of u-boot code. + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - & ~CFG_CMD_LOADS \ - & ~CFG_CMD_CONSOLE \ - & ~CFG_CMD_AUTOSCRIPT \ - & ~CFG_CMD_NET \ - & ~CFG_CMD_PING \ - & ~CFG_CMD_DHCP \ - | CFG_CMD_JFFS2 \ - ) - -#include +#include + +#define CONFIG_CMD_JFFS2 + +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_CONSOLE +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_PING +#undef CONFIG_CMD_DHCP + /* * Boot options. Setting delay to -1 stops autostart count down. -- cgit v1.3.1 From 929a2bfd142737003a8fc32e1b86e1f2c1850257 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:33:07 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various n* named board config files. Signed-off-by: Jon Loeliger --- include/configs/netstar.h | 48 +++++++++++++++++---------------------------- include/configs/ns9750dev.h | 40 ++++++++++++------------------------- 2 files changed, 31 insertions(+), 57 deletions(-) (limited to 'include') diff --git a/include/configs/netstar.h b/include/configs/netstar.h index 697796a1143..603c9b8be64 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -140,43 +140,31 @@ #define MTDIDS_DEFAULT "nor0=omapflash.0,nand0=omapnand.0" #define MTDPARTS_DEFAULT "mtdparts=omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);omapnand.0:48M(rootfs0),48M(rootfs1),-(data)" -#if 0 -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_BOOTD | \ - CFG_CMD_DHCP | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_LOADB | \ - CFG_CMD_NET | \ - CFG_CMD_MEMORY | \ - CFG_CMD_PING | \ - CFG_CMD_RUN) -#else -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_BOOTD | \ - CFG_CMD_DHCP | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_NAND | \ - CFG_CMD_IMI | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_LOADB | \ - CFG_CMD_NET | \ - CFG_CMD_MEMORY | \ - CFG_CMD_PING | \ - CFG_CMD_RUN) +/* + * Command line configuration. + */ + +#define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN + #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#endif #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT #define CONFIG_LOOPW -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h index 0b1541d5c34..e1806a70c60 100644 --- a/include/configs/ns9750dev.h +++ b/include/configs/ns9750dev.h @@ -69,33 +69,19 @@ #define CONFIG_BAUDRATE 38400 -/*********************************************************** - * Command definition - ***********************************************************/ -#if 0 /* @TODO */ -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - /*CFG_CMD_NAND |*/ \ - /*CFG_CMD_EEPROM |*/ \ - /*CFG_CMD_I2C |*/ \ - /*CFG_CMD_USB |*/ \ - CFG_CMD_REGINFO | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF) -#else -#define CONFIG_COMMANDS \ - (CONFIG_CMD_BDI | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_CONSOLE | \ - CFG_CMD_LOADB | \ - CFG_CMD_LOADS | \ - CFG_CMD_MEMORY) -#endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ + +#define CONFIG_CMD_BDI +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING + #define CONFIG_BOOTDELAY 3 /*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ @@ -108,7 +94,7 @@ /*#define CONFIG_BOOTFILE "elinos-lart" */ /*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -- cgit v1.3.1 From a5cb23092a7d31490a33d4ec871468b63babfa3c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:33:13 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various o* named board config files. Signed-off-by: Jon Loeliger --- include/configs/o2dnt.h | 36 +++++++++++++++---------------- include/configs/ocotea.h | 49 +++++++++++++++++++++++-------------------- include/configs/omap1510inn.h | 16 ++++++++++---- include/configs/omap1610h2.h | 14 +++++++++---- include/configs/omap1610inn.h | 14 +++++++++---- include/configs/omap2420h4.h | 22 ++++++++++++++----- include/configs/omap5912osk.h | 14 +++++++++---- include/configs/omap730p2.h | 13 +++++++----- 8 files changed, 111 insertions(+), 67 deletions(-) (limited to 'include') diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index 63d0da7d090..9ed1ed856c8 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -37,11 +37,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -82,20 +77,20 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - ADD_PCI_CMD ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NFS +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_PCI_CMD + #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ # define CFG_LOWBOOT 1 @@ -246,7 +241,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -262,6 +257,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Various low-level settings */ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 68e8cec251c..fd45c1d9705 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -232,26 +232,29 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -260,7 +263,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -310,7 +313,7 @@ */ #define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -322,7 +325,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h index 016d3d8bd02..11fdb471014 100644 --- a/include/configs/omap1510inn.h +++ b/include/configs/omap1510inn.h @@ -86,11 +86,19 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP + + #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #include #define CONFIG_BOOTDELAY 3 @@ -98,7 +106,7 @@ #define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" #define CFG_AUTOLOAD "n" /* No autoload */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h index c6ca689a5fe..d78f79f121e 100644 --- a/include/configs/omap1610h2.h +++ b/include/configs/omap1610h2.h @@ -81,11 +81,17 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP + + #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #include #define CONFIG_BOOTDELAY 3 @@ -93,7 +99,7 @@ #define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" #define CFG_AUTOLOAD "n" /* No autoload */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ #endif diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h index f28ede09674..7d0658fd7de 100644 --- a/include/configs/omap1610inn.h +++ b/include/configs/omap1610inn.h @@ -82,11 +82,17 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP + + #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #include #define CONFIG_BOOTDELAY 3 @@ -98,7 +104,7 @@ #define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ #define CONFIG_BOOTFILE "uImage" /* file to load */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ #endif diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 58374616a14..46e0dcc4782 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -119,15 +119,27 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/* + * Command line configuration. + */ +#include + #ifdef CFG_NAND_BOOT -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_NAND | CFG_CMD_JFFS2) + #define CONFIG_CMD_DHCP + #define CONFIG_CMD_I2C + #define CONFIG_CMD_NAND + #define CONFIG_CMD_JFFS2 #else -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_I2C | CFG_CMD_JFFS2) & ~CFG_CMD_AUTOSCRIPT) + #define CONFIG_CMD_DHCP + #define CONFIG_CMD_I2C + #define CONFIG_CMD_JFFS2 + + #undef CONFIG_CMD_AUTOSCRIPT #endif -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT /* * Board NAND Info. diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h index 5db4f52beb6..296b6bc9800 100644 --- a/include/configs/omap5912osk.h +++ b/include/configs/omap5912osk.h @@ -86,11 +86,17 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP + + #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #include #define CONFIG_BOOTDELAY 3 @@ -102,7 +108,7 @@ #define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ #define CONFIG_BOOTFILE "uImage" /* file to load */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ #endif diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h index fda55cf06fd..af9877f24a9 100644 --- a/include/configs/omap730p2.h +++ b/include/configs/omap730p2.h @@ -90,14 +90,17 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT /* - * This must be included AFTER the definition of CONFIG_COMMANDS (if any) + * Command line configuration. */ +#include + +#define CONFIG_CMD_DHCP + + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -#include #include #include @@ -112,7 +115,7 @@ #define CONFIG_SERVERIP 192.150.0.100 #define CONFIG_BOOTFILE "uImage" /* File to load */ -#if defined (CONFIG_COMMANDS) && defined (CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */ #endif -- cgit v1.3.1 From 26a34560d56a9df5bc2ae23525d9229736134757 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:33:17 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various p* named board config files. Signed-off-by: Jon Loeliger --- include/configs/p3mx.h | 43 ++++++++++++++++++++------------------ include/configs/p3p440.h | 47 ++++++++++++++++++++++-------------------- include/configs/pb1x00.h | 31 ++++++++++++++++++++-------- include/configs/pcs440ep.h | 49 ++++++++++++++++++++++---------------------- include/configs/pcu_e.h | 26 +++++++++++------------ include/configs/pdnb3.h | 33 +++++++++++++++-------------- include/configs/pleb2.h | 12 +++++++---- include/configs/ppmc7xx.h | 45 +++++++++++++++++++++------------------- include/configs/ppmc8260.h | 29 ++++++++++++++------------ include/configs/purple.h | 10 +++++++-- include/configs/pxa255_idp.h | 14 +++++++++---- 11 files changed, 190 insertions(+), 149 deletions(-) (limited to 'include') diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index 54462f007cd..6994f7b62b1 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -253,24 +253,27 @@ #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_PCI | \ - CFG_CMD_CACHE | \ - CFG_CMD_SDRAM) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_PCI +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_SDRAM + /*----------------------------------------------------------------------- * Miscellaneous configurable options @@ -280,7 +283,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -421,7 +424,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 22f9f84ec23..2a429614aaf 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -168,25 +168,28 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_SNTP + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -195,7 +198,7 @@ *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -304,7 +307,7 @@ */ #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -316,7 +319,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index ed1893f5742..c84795b6ab0 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -132,11 +132,8 @@ /*---USB -------------------------------------------*/ #if 0 #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION -#else -#define ADD_USB_CMD 0 #endif /*---ATA PCMCIA ------------------------------------*/ @@ -179,11 +176,27 @@ #define CFG_ICACHE_SIZE 16384 #define CFG_CACHELINE_SIZE 32 -#define CONFIG_COMMANDS \ - (((CONFIG_CMD_DFL | CFG_CMD_DHCP | CFG_CMD_ELF | CFG_CMD_MII | CFG_CMD_PING) & \ - ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | CFG_CMD_IDE | \ - CFG_CMD_LOADS | CFG_CMD_RUN | CFG_CMD_LOADB | CFG_CMD_ELF | \ - CFG_CMD_BDI | CFG_CMD_BEDBUG)) | ADD_USB_CMD) -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + +#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_FAT +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IDE +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_RUN +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_BEDBUG #endif /* __CONFIG_H */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 751b51277ce..f0cd8d3c02f 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -208,37 +208,38 @@ #define CONFIG_HW_WATCHDOG /* watchdog */ #endif -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FAT | \ - CFG_CMD_USB ) +/* + * Command line configuration. + */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB -#define CONFIG_SUPPORT_VFAT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_SUPPORT_VFAT /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -393,7 +394,7 @@ */ #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -405,7 +406,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h index 73aa3a88259..1174e1aa4f8 100644 --- a/include/configs/pcu_e.h +++ b/include/configs/pcu_e.h @@ -89,28 +89,28 @@ * ---------------------------------------------------------------- */ #define CFG_SPI_INIT_OFFSET 0xB00 -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#define CONFIG_BOOTP_MASK \ - ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) +/* + * Command line configuration. + */ +#include +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -/*----------------------------------------------------------------------*/ +#define CONFIG_BOOTP_MASK \ + ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index 06c66528784..5d6e169c26a 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -71,25 +71,24 @@ #define CONFIG_BAUDRATE 115200 #define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ -#if defined(CONFIG_SCPU) -#define CMD_NAND_ADD 0 -#else -#define CMD_NAND_ADD CFG_CMD_NAND + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_I2C +#define CONFIG_CMD_ELF +#define CONFIG_CMD_PING + +#if !defined(CONFIG_SCPU) +#define CONFIG_CMD_NAND #endif -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_NET | \ - CFG_CMD_MII | \ - CMD_NAND_ADD | \ - CFG_CMD_I2C | \ - CFG_CMD_ELF | \ - CFG_CMD_PING) - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -/* These are u-boot generic parameters */ -#include #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h index a6c23712b5d..f581fe5e23f 100644 --- a/include/configs/pleb2.h +++ b/include/configs/pleb2.h @@ -66,10 +66,14 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_NET) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_NET + #define CONFIG_BOOTDELAY 3 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b @@ -83,7 +87,7 @@ #define CONFIG_INITRD_TAG #define CONFIG_SETUP_MEMORY_TAGS -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h index 072b9dd5b46..6a3bd33d2e9 100644 --- a/include/configs/ppmc7xx.h +++ b/include/configs/ppmc7xx.h @@ -53,29 +53,35 @@ /* * Monitor configuration * - * CONFIG_COMMANDS - List of command sets to include in shell + * List of command sets to include in shell * * The following command sets have been tested and known to work: * - * CFG_CMD_CACHE - Cache control commands - * CFG_CMD_MEMORY - Memory display, change and test commands - * CFG_CMD_FLASH - Erase and program flash - * CFG_CMD_ENV - Environment commands - * CFG_CMD_RUN - Run commands stored in env vars - * CFG_CMD_ELF - Load ELF files - * CFG_CMD_NET - Networking/file download commands - * CFG_CMD_PING - ICMP Echo Request command - * CFG_CMD_PCI - PCI Bus scanning command + * CMD_CACHE - Cache control commands + * CMD_MEMORY - Memory display, change and test commands + * CMD_FLASH - Erase and program flash + * CMD_ENV - Environment commands + * CMD_RUN - Run commands stored in env vars + * CMD_ELF - Load ELF files + * CMD_NET - Networking/file download commands + * CMD_PIN - ICMP Echo Request command + * CMD_PCI - PCI Bus scanning command */ -#define CONFIG_COMMANDS ( (CFG_CMD_DFL & ~(CFG_CMD_KGDB)) | \ - CFG_CMD_FLASH | \ - CFG_CMD_ENV | \ - CFG_CMD_RUN | \ - CFG_CMD_ELF | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_PCI) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_ENV +#define CONFIG_CMD_RUN +#define CONFIG_CMD_ELF +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_PCI + +#undef CONFIG_CMD_KGDB /* @@ -149,9 +155,6 @@ */ -#include - - /* * Memory map * diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h index d671dccc19b..d99da2fdbcf 100644 --- a/include/configs/ppmc8260.h +++ b/include/configs/ppmc8260.h @@ -275,14 +275,20 @@ /* Monitor Command Prompt */ #define CFG_PROMPT "=> " -/* What U-Boot subsytems do you want enabled? */ -#define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ - CFG_CMD_ELF | \ - CFG_CMD_ASKENV | \ - CFG_CMD_REGINFO | \ - CFG_CMD_MEMTEST | \ - CFG_CMD_MII | \ - CFG_CMD_IMMAP) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_MEMTEST +#define CONFIG_CMD_MII +#define CONFIG_CMD_IMMAP + +#undef CONFIG_CMD_KGDB /* Where do the internal registers live? */ @@ -298,13 +304,10 @@ #define CONFIG_PPMC8260 1 /* on an Wind River PPMC8260 Board */ #define CONFIG_CPM2 1 /* Has a CPM2 */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -477,7 +480,7 @@ */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/purple.h b/include/configs/purple.h index 2ecb7fb2bf7..61e18d7b715 100644 --- a/include/configs/purple.h +++ b/include/configs/purple.h @@ -81,8 +81,14 @@ "" #define CONFIG_BOOTCOMMAND "run flash_self" -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF) -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ELF + #define CFG_SDRAM_BASE 0x80000000 diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index e5e27724e18..d7e4e8ac2b1 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -102,10 +102,16 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_DHCP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_DHCP + #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTCOMMAND "bootm 40000" @@ -192,7 +198,7 @@ /* "protect off" */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -- cgit v1.3.1 From 90cc3eb6d2be856d9ddd81436de9cf343bc6b5c8 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:33:23 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various q* and r* named board config files. Signed-off-by: Jon Loeliger --- include/configs/quantum.h | 28 +++++++++++++++------------- include/configs/rmu.h | 27 +++++++++++++++------------ include/configs/rsdproto.h | 18 +++++++++++------- 3 files changed, 41 insertions(+), 32 deletions(-) (limited to 'include') diff --git a/include/configs/quantum.h b/include/configs/quantum.h index 21ec5acadef..dce2f4b811c 100644 --- a/include/configs/quantum.h +++ b/include/configs/quantum.h @@ -92,18 +92,20 @@ #define CFG_NVRAM_SIZE 2048 -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) +/* + * Command line configuration. + */ +#include -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ #define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" @@ -113,7 +115,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -172,7 +174,7 @@ #endif /*%%% #define CFG_FLASH_BASE 0xFFF00000 */ -#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#if defined(DEBUG) || defined(CONFIG_CMD_IDE) #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ @@ -222,7 +224,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/rmu.h b/include/configs/rmu.h index b319cf497d3..fd27ea15872 100644 --- a/include/configs/rmu.h +++ b/include/configs/rmu.h @@ -87,17 +87,20 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * Command line configuration. + */ +#include -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ #define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" @@ -108,7 +111,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -152,7 +155,7 @@ */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE (0-flash_info[0].size) /* Put flash at end */ -#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#if defined(DEBUG) || defined(CONFIG_CMD_IDE) #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ @@ -193,7 +196,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h index 6c9e392c36b..5ea76fe9bf9 100644 --- a/include/configs/rsdproto.h +++ b/include/configs/rsdproto.h @@ -102,7 +102,14 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_KGDB) + +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_KGDB + /* Define this if you want to boot from 0x00000100. If you don't define * this, you will need to program the bootloader to 0xfff00000, and @@ -112,15 +119,12 @@ */ #define CFG_RSD_BOOT_LOW 1 -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #define CONFIG_BOOTDELAY 5 #define CONFIG_BOOTARGS "devfs=mount root=ramfs" #define CONFIG_ETHADDR 08:00:3e:26:0a:5a #define CONFIG_NETMASK 255.255.0.0 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif @@ -130,7 +134,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -287,7 +291,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From 46da1e96b7db14f4fcd2c92544e7c0862024bc76 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:33:30 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various s* named board config files. Signed-off-by: Jon Loeliger --- include/configs/sacsng.h | 53 +++++++++++--------------- include/configs/sc3.h | 48 ++++++++++++----------- include/configs/sc520_cdp.h | 17 +++++++-- include/configs/sc520_spunk.h | 17 +++++++-- include/configs/scb9328.h | 24 ++++++------ include/configs/sequoia.h | 59 ++++++++++++++-------------- include/configs/shannon.h | 14 +++---- include/configs/smdk2400.h | 29 +++++++------- include/configs/smdk2410.h | 29 ++++++-------- include/configs/smmaco4.h | 47 +++++++++++------------ include/configs/sorcery.h | 53 ++++++++++++-------------- include/configs/spc1920.h | 34 ++++++++--------- include/configs/spieval.h | 89 ++++++++++++++++++++----------------------- include/configs/suzaku.h | 8 ++-- include/configs/svm_sc8xx.h | 25 ++++++------ 15 files changed, 272 insertions(+), 274 deletions(-) (limited to 'include') diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 97b52fa1ae7..dc258312884 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -502,31 +502,28 @@ */ #define CONFIG_VERSION_VARIABLE -/* What U-Boot subsytems do you want enabled? */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_PING + +#undef CONFIG_CMD_KGDB + #ifdef CONFIG_ETHER_ON_FCC -# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ - CFG_CMD_ELF | \ - CFG_CMD_ASKENV | \ - CFG_CMD_I2C | \ - CFG_CMD_SPI | \ - CFG_CMD_SDRAM | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_IRQ | \ - CFG_CMD_PING | \ - CFG_CMD_MII ) -#else -# define CONFIG_COMMANDS (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \ - CFG_CMD_ELF | \ - CFG_CMD_ASKENV | \ - CFG_CMD_I2C | \ - CFG_CMD_SPI | \ - CFG_CMD_SDRAM | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_IRQ | \ - CFG_CMD_PING ) -#endif /* CONFIG_ETHER_ON_FCC */ +#define CONFIG_CMD_MII +#endif + /* Where do the internal registers live? */ #define CFG_IMMR 0xF0000000 @@ -544,10 +541,6 @@ #define CONFIG_SACSng 1 /* munged for the SACSng */ #define CONFIG_CPM2 1 /* Has a CPM2 */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - - /* * Miscellaneous configurable options */ @@ -589,7 +582,7 @@ #define CFG_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */ /* before it gives up. */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -732,7 +725,7 @@ */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/sc3.h b/include/configs/sc3.h index e4357b08854..578ef80aa62 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -169,25 +169,27 @@ #define CONFIG_MII 1 /* add 405GP MII PHY management */ #define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */ -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_NET | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_NAND | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_CACHE | \ - CFG_CMD_ELF ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + + +#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_NAND +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_ELF + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -277,7 +279,7 @@ * External peripheral base address *----------------------------------------------------------------------- */ -#if !(CONFIG_COMMANDS & CFG_CMD_IDE) +#if !defined(CONFIG_CMD_IDE) #undef CONFIG_IDE_LED /* no led for ide supported */ #undef CONFIG_IDE_RESET /* no reset for ide supported */ @@ -286,7 +288,7 @@ * IDE/ATA stuff *----------------------------------------------------------------------- */ -#else /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */ +#else #define CONFIG_START_IDE 1 /* check, if use IDE */ #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ @@ -346,7 +348,7 @@ #endif /* IDE_USES_ISA_EMULATION */ -#endif /* !(CONFIG_COMMANDS & CFG_CMD_IDE) */ +#endif /* #define CFG_KEY_REG_BASE_ADDR 0xF0100000 @@ -437,7 +439,7 @@ extern unsigned long offsetOfEnvironment; #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index 8b2ec077bd9..1001342a059 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -67,16 +67,25 @@ #define CONFIG_BAUDRATE 9600 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_EEPROM) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NET +#define CONFIG_CMD_EEPROM + + #define CONFIG_BOOTDELAY 15 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" /* #define CONFIG_BOOTCOMMAND "bootm 38000000" */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h index a8e355508b1..e761ca7b55b 100644 --- a/include/configs/sc520_spunk.h +++ b/include/configs/sc520_spunk.h @@ -64,16 +64,25 @@ #define CONFIG_BAUDRATE 9600 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 | CFG_CMD_IDE | CFG_CMD_NET | CFG_CMD_PCMCIA | CFG_CMD_EEPROM) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCMCIA +#define CONFIG_CMD_EEPROM + #define CONFIG_BOOTDELAY 15 #define CONFIG_BOOTARGS "root=/dev/mtdblock1 console=ttyS0,9600 mtdparts=phys:7936k(root),256k(uboot) " #define CONFIG_BOOTCOMMAND "setenv bootargs root=/dev/nfs ip=autoconf console=ttyS0,9600 mtdparts=phys:7808k(root),128k(env),256k(uboot); bootp; bootm" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index a4249c47c62..489c35ff4b4 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -36,20 +36,18 @@ /* - * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if - * neccessary in include/cmd_confdefs.h file. (Un)comment for getting - * functionality or size of u-boot code. + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - & ~CFG_CMD_LOADS \ - & ~CFG_CMD_CONSOLE \ - & ~CFG_CMD_AUTOSCRIPT \ - | CFG_CMD_NET \ - | CFG_CMD_PING \ - | CFG_CMD_DHCP \ - ) - -#include +#include + +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_CONSOLE +#undef CONFIG_CMD_AUTOSCRIPT + /* * Boot options. Setting delay to -1 stops autostart count down. diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 44bc9555194..14a64e8c3fc 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -299,9 +299,6 @@ /* Comment this out to enable USB 1.1 device */ #define USB_2_0_DEVICE -#define CMD_USB CFG_CMD_USB -#else -#define CMD_USB 0 /* no USB on 440GRx */ #endif /* CONFIG_440EPX */ /* Partitions */ @@ -309,25 +306,34 @@ #define CONFIG_DOS_PARTITION #define CONFIG_ISO_PARTITION -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DTT | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CMD_USB) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DTT +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + +#ifdef CONFIG_440EPX +#define CONFIG_CMD_USB +#endif + /* POST support */ #define CONFIG_POST (CFG_POST_MEMORY | \ @@ -343,15 +349,12 @@ #define CONFIG_SUPPORT_VFAT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /*----------------------------------------------------------------------- * Miscellaneous configurable options *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -441,7 +444,7 @@ *----------------------------------------------------------------------*/ #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -453,7 +456,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/shannon.h b/include/configs/shannon.h index 572985b051b..cad38d0c00d 100644 --- a/include/configs/shannon.h +++ b/include/configs/shannon.h @@ -66,21 +66,19 @@ #define CONFIG_BAUDRATE 115200 -#if 0 /* XXX - cannot test IDE anyway, so disabled for now - wd */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_IDE) -#endif /* 0 */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,115200" #define CONFIG_NETMASK 255.255.0.0 #define CONFIG_BOOTCOMMAND "help" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h index a137f9d7c99..22e69725b37 100644 --- a/include/configs/smdk2400.h +++ b/include/configs/smdk2400.h @@ -86,24 +86,23 @@ /* Use s3c2400's RTC */ #define CONFIG_RTC_S3C24X0 1 -#ifndef USE_920T_MMU -#define CONFIG_COMMANDS_tmp ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \ - CFG_CMD_DATE | \ - CFG_CMD_SNTP ) -#else -#define CONFIG_COMMANDS_tmp (CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_SNTP ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_SNTP + +#if defined(CONFIG_HWFLOW) + #define CONFIG_CONFIG_HWFLOW #endif -#ifdef CONFIG_HWFLOW -#define CONFIG_COMMANDS (CONFIG_COMMANDS_tmp | CFG_CMD_HWFLOW) -#else -#define CONFIG_COMMANDS CONFIG_COMMANDS_tmp +#if !defined(USE_920T_MMU) + #undef CONFIG_CMD_CACHE #endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CONFIG_BOOTDELAY 3 #if 0 @@ -118,7 +117,7 @@ #define CONFIG_BOOTCOMMAND "tftp; bootm" #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index 7edec0db43d..cd3d3276547 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -72,22 +72,17 @@ #define CONFIG_BAUDRATE 115200 -/*********************************************************** - * Command definition - ***********************************************************/ -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - /*CFG_CMD_NAND |*/ \ - /*CFG_CMD_EEPROM |*/ \ - /*CFG_CMD_I2C |*/ \ - /*CFG_CMD_USB |*/ \ - CFG_CMD_REGINFO | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF + #define CONFIG_BOOTDELAY 3 /*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ @@ -98,7 +93,7 @@ /*#define CONFIG_BOOTFILE "elinos-lart" */ /*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h index 185c2d48709..8d098579d79 100644 --- a/include/configs/smmaco4.h +++ b/include/configs/smmaco4.h @@ -42,11 +42,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -72,26 +67,25 @@ #define CFG_CMD_POST_DIAG 0 #endif + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_POST +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP + #define CONFIG_TIMESTAMP /* display image timestamps */ @@ -319,7 +313,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -338,6 +332,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, * which is normally part of the default commands (CFV_CMD_DFL) diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h index 4937638820b..e8f4cfac3ff 100644 --- a/include/configs/sorcery.h +++ b/include/configs/sorcery.h @@ -39,12 +39,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -69,30 +63,26 @@ #define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS #define CONFIG_PCI_CFG_SIZE 0x01000000 + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CACHE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP | \ - 0) - -/* CFG_CMD_MII | \ */ -/* CFG_CMD_USB | \ */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP + /* * Default Environment @@ -268,7 +258,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -284,6 +274,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Various low-level settings */ diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h index 09bbebdce89..ea6a11237d2 100644 --- a/include/configs/spc1920.h +++ b/include/configs/spc1920.h @@ -80,24 +80,24 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#ifndef CONFIG_COMMANDS -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_DATE \ - | CFG_CMD_ECHO \ - | CFG_CMD_IMMAP \ - | CFG_CMD_JFFS2 \ - | CFG_CMD_PING \ - | CFG_CMD_DHCP \ - | CFG_CMD_I2C \ - | CFG_CMD_MII) - /* & ~( CFG_CMD_NET)) */ +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII -#endif /* !CONFIG_COMMANDS */ +#undef CONFIG_CMD_NET -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options @@ -107,7 +107,7 @@ #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -202,7 +202,7 @@ /*----------------------------------------------------------------------- * I2C configuration */ -#if (CONFIG_COMMANDS & CFG_CMD_I2C) +#if defined(CONFIG_CMD_I2C) /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ diff --git a/include/configs/spieval.h b/include/configs/spieval.h index 9888d111086..e480df5f9c0 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -44,11 +44,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -88,12 +83,6 @@ #define CONFIG_NS8382X 1 #endif /* CONFIG_STK52XX */ -#ifdef CONFIG_PCI -#define ADD_PCI_CMD CFG_CMD_PCI -#else -#define ADD_PCI_CMD 0 -#endif - /* * Video console */ @@ -110,12 +99,6 @@ #define CFG_CONSOLE_IS_IN_ENV #endif -#ifdef CONFIG_VIDEO -#define ADD_BMP_CMD CFG_CMD_BMP -#else -#define ADD_BMP_CMD 0 -#endif - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -124,10 +107,7 @@ /* USB */ #ifdef CONFIG_STK52XX #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 #endif /* POST support */ @@ -143,36 +123,44 @@ #define CFG_CMD_POST_DIAG 0 #endif -/* IDE */ -#if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX) -#define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2) -#else -#define ADD_IDE_CMD 0 -#endif /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_BMP_CMD | \ - ADD_IDE_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) + #define CONFIG_CMD_IDE + #define CONFIG_CMD_FAT + #define CONFIG_CMD_EXT2 +#endif + +#ifdef CONFIG_STK52XX + #define CONFIG_CMD_USB + #define CONFIG_CMD_FAT +#endif + +#ifdef CONFIG_VIDEO + #define CONFIG_CMD_BMP +#endif + +#ifdef CONFIG_PCI + #define CONFIG_CMD_PCI +#endif + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_POST +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP + #define CONFIG_TIMESTAMP /* display image timestamps */ @@ -406,7 +394,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -425,6 +413,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, * which is normally part of the default commands (CFV_CMD_DFL) diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h index 82245558961..cb1a2e6a1a0 100644 --- a/include/configs/suzaku.h +++ b/include/configs/suzaku.h @@ -55,10 +55,12 @@ #define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000 #define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0) -#define CONFIG_COMMANDS (CONFIG__CMD_DFL) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + #define CFG_UART1_BASE (0xFFFF2000) #define CONFIG_SERIAL_BASE CFG_UART1_BASE diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h index 92ee8cb3331..0cd0219b805 100644 --- a/include/configs/svm_sc8xx.h +++ b/include/configs/svm_sc8xx.h @@ -132,15 +132,18 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ -/* CFG_CMD_IDE |*/ \ - CFG_CMD_DATE ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DOC +#define CONFIG_CMD_DATE + + #define CFG_NAND_LEGACY /* @@ -153,7 +156,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -246,7 +249,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From 6c18eb9804b525f3e4f3bb3d014dd69a200d9fa7 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:33:38 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various t* and u* named board config files. Signed-off-by: Jon Loeliger --- include/configs/taishan.h | 48 ++++++++++++++++++------------------- include/configs/tb0229.h | 19 +++++++++------ include/configs/trab.h | 61 ++++++++++++++++------------------------------- include/configs/uc100.h | 41 ++++++++++++++++--------------- include/configs/uc101.h | 46 +++++++++++++++++------------------ include/configs/utx8245.h | 33 +++++++++++++++---------- 6 files changed, 123 insertions(+), 125 deletions(-) (limited to 'include') diff --git a/include/configs/taishan.h b/include/configs/taishan.h index d756be7165f..4889f7026b8 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -234,27 +234,27 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ -/*----------------------------------------------------------------------- - * Console/Commands/Parser - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_DTT | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_DTT +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -263,7 +263,7 @@ *----------------------------------------------------------------------*/ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -315,7 +315,7 @@ *----------------------------------------------------------------------*/ #define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -327,7 +327,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h index dac1eb736d8..df031753d6a 100644 --- a/include/configs/tb0229.h +++ b/include/configs/tb0229.h @@ -87,13 +87,18 @@ /*#define CONFIG_BOOTCOMMAND "run flash_local" */ #define CONFIG_BOOTCOMMAND "run netboot" -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_PCI | \ - CFG_CMD_ELF ) -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_PCI +#define CONFIG_CMD_ELF + /* * Miscellaneous configurable options diff --git a/include/configs/trab.h b/include/configs/trab.h index a2dc8e7bff8..a696b634a9a 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -130,60 +130,41 @@ /* Use s3c2400's RTC */ #define CONFIG_RTC_S3C24X0 1 + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_USB + #ifdef CONFIG_HWFLOW -#define CONFIG_COMMANDS_ADD_HWFLOW CFG_CMD_HWFLOW -#else -#define CONFIG_COMMANDS_ADD_HWFLOW 0 + #define CONFIG_CMD_HWFLOW #endif #ifdef CONFIG_VFD -#define CONFIG_COMMANDS_ADD_VFD CFG_CMD_VFD -#else -#define CONFIG_COMMANDS_ADD_VFD 0 + #define CONFIG_CMD_VFD #endif #ifdef CONFIG_DRIVER_S3C24X0_I2C -#define CONFIG_COMMANDS_ADD_EEPROM CFG_CMD_EEPROM -#define CONFIG_COMMANDS_I2C CFG_CMD_I2C -#else -#define CONFIG_COMMANDS_ADD_EEPROM 0 -#define CONFIG_COMMANDS_I2C 0 + #define CONFIG_CMD_EEPROM + #define CONFIG_CMD_I2C #endif #ifndef USE_920T_MMU -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_CACHE) | \ - CONFIG_COMMANDS_ADD_HWFLOW | \ - CONFIG_COMMANDS_ADD_VFD | \ - CONFIG_COMMANDS_ADD_EEPROM | \ - CONFIG_COMMANDS_I2C | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP | \ - CFG_CMD_USB ) -#else -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CONFIG_COMMANDS_ADD_HWFLOW | \ - CONFIG_COMMANDS_ADD_VFD | \ - CONFIG_COMMANDS_ADD_EEPROM | \ - CONFIG_COMMANDS_I2C | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP | \ - CFG_CMD_USB ) + #undef CONFIG_CMD_CACHE #endif + /* moved up */ #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #define CONFIG_BOOTDELAY 5 #define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */ #define CONFIG_PREBOOT "echo;echo *** booting ***;echo" @@ -296,7 +277,7 @@ #define CONFIG_AUTOBOOT_DELAY_STR "R" /* 1st "password" */ #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ diff --git a/include/configs/uc100.h b/include/configs/uc100.h index c4e629ade2b..2bdc55b4673 100644 --- a/include/configs/uc100.h +++ b/include/configs/uc100.h @@ -123,25 +123,28 @@ #define CFG_CMD_POST_DIAG 0 #endif -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_SNTP ) -#define CONFIG_NETCONSOLE +/* + * Command line configuration. + */ +#include -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_POST +#define CONFIG_CMD_SNTP + + +#define CONFIG_NETCONSOLE /* * Miscellaneous configurable options @@ -156,7 +159,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -246,7 +249,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/uc101.h b/include/configs/uc101.h index ff061eecc89..64461f6a90e 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -38,11 +38,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - #define CONFIG_BOARD_EARLY_INIT_R /* @@ -55,25 +50,25 @@ /* Partitions */ #define CONFIG_DOS_PARTITION + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DISPLAY | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_DTT | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_NFS | \ - CFG_CMD_MII | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DISPLAY +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DTT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_NFS +#define CONFIG_CMD_MII +#define CONFIG_CMD_SNTP + #define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */ @@ -245,7 +240,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -264,6 +259,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, * which is normally part of the default commands (CFV_CMD_DFL) diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h index e5d4397d2c7..f3995431447 100644 --- a/include/configs/utx8245.h +++ b/include/configs/utx8245.h @@ -86,18 +86,27 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}" #define CONFIG_ENV_OVERWRITE -#define CONFIG_COMMANDS (CFG_CMD_DFL | CFG_CMD_BDI | CFG_CMD_PCI \ - | CFG_CMD_FLASH | CFG_CMD_MEMORY \ - | CFG_CMD_ENV | CFG_CMD_CONSOLE \ - | CFG_CMD_LOADS | CFG_CMD_LOADB \ - | CFG_CMD_IMI | CFG_CMD_CACHE \ - | CFG_CMD_REGINFO | CFG_CMD_NET\ - | CFG_CMD_DHCP | CFG_CMD_I2C \ - | CFG_CMD_DATE) - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + +/* + * Command line configuration. */ -#include +#include + +#define CONFIG_CMD_BDI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_ENV +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_IMI +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DATE /* @@ -403,7 +412,7 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}" * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From dca3b3d6d6396b67e5e84af53452164923c73443 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Wed, 4 Jul 2007 22:33:46 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various [v-z]* named board config files. Signed-off-by: Jon Loeliger --- include/configs/v37.h | 19 ++++++++------- include/configs/v38b.h | 48 +++++++++++++++++++------------------- include/configs/versatile.h | 18 +++++++++++---- include/configs/virtlab2.h | 38 ++++++++++++++---------------- include/configs/voiceblue.h | 47 +++++++++++++++++-------------------- include/configs/walnut.h | 49 ++++++++++++++++++++------------------- include/configs/wepep250.h | 19 +++++++-------- include/configs/xaeniax.h | 23 +++++++++++-------- include/configs/xm250.h | 19 ++++++++------- include/configs/xsengine.h | 13 ++++++++--- include/configs/xupv2p.h | 45 +++++++++++++++++++----------------- include/configs/yosemite.h | 56 ++++++++++++++++++++++++--------------------- include/configs/yucca.h | 47 +++++++++++++++++++------------------ include/configs/zylonite.h | 24 +++++++++++-------- 14 files changed, 248 insertions(+), 217 deletions(-) (limited to 'include') diff --git a/include/configs/v37.h b/include/configs/v37.h index a2e99b59e2a..402ed4b4b21 100644 --- a/include/configs/v37.h +++ b/include/configs/v37.h @@ -83,9 +83,15 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_DATE ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_DATE + /* * JFFS2 partitions @@ -105,15 +111,12 @@ #define MTDPARTS_DEFAULT "mtdparts=v37-1:-(jffs2)" */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -194,7 +197,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 0b7b19eadab..3e3d11674ed 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -46,11 +46,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -89,28 +84,28 @@ #define CONFIG_USB_CLOCK 0x0001BBBB #define CONFIG_USB_CONFIG 0x00001000 + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_PING | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_SDRAM | \ - CFG_CMD_DATE | \ - CFG_CMD_USB | \ - CFG_CMD_FAT) +#include + +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_DATE +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_TIMESTAMP /* Print image info with timestamp */ /* * Boot low with 16 MB Flash @@ -254,7 +249,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -270,6 +265,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Various low-level settings */ diff --git a/include/configs/versatile.h b/include/configs/versatile.h index 16db43bb938..b90821995c6 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -96,14 +96,22 @@ #define CFG_SERIAL0 0x101F1000 #define CFG_SERIAL1 0x101F2000 -#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_ENV) -/*#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) */ +/* + * Command line configuration. + */ -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IMI +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_BDI +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_ENV -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0" diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h index 06d8536ec31..ac87b397d29 100644 --- a/include/configs/virtlab2.h +++ b/include/configs/virtlab2.h @@ -96,27 +96,23 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#ifdef CONFIG_SPLASH_SCREEN -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BMP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#else -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + +#if defined(CONFIG_SPLASH_SCREEN) + #define CONFIG_CMD_BMP #endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options @@ -131,7 +127,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -214,7 +210,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h index 4e97b01aa1a..f8879a11960 100644 --- a/include/configs/voiceblue.h +++ b/include/configs/voiceblue.h @@ -131,32 +131,29 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#ifdef VOICEBLUE_SMALL_FLASH -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_LOADB | \ - CFG_CMD_IMI | \ - CFG_CMD_FLASH | \ - CFG_CMD_MEMORY | \ - CFG_CMD_NET | \ - CFG_CMD_BOOTD | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_RUN) -#else -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_LOADB | \ - CFG_CMD_IMI | \ - CFG_CMD_FLASH | \ - CFG_CMD_MEMORY | \ - CFG_CMD_NET | \ - CFG_CMD_ENV | \ - CFG_CMD_BOOTD | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_RUN | \ - CFG_CMD_JFFS2) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BDI +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_IMI +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN + +#if !defined(VOICEBLUE_SMALL_FLASH) + #define CONFIG_CMD_ENV + #define CONFIG_CMD_JFFS2 #endif + #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT #define CONFIG_LOOPW @@ -220,8 +217,6 @@ #endif /* VOICEBLUE_SMALL_FLASH */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options diff --git a/include/configs/walnut.h b/include/configs/walnut.h index b34dc71d23f..2112b531795 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -98,26 +98,29 @@ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -128,7 +131,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -283,7 +286,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -340,7 +343,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h index 47251bbb641..3b360402dec 100644 --- a/include/configs/wepep250.h +++ b/include/configs/wepep250.h @@ -36,18 +36,15 @@ /* - * Definition of u-boot build in commands. Check out CONFIG_CMD_DFL if - * neccessary in include/cmd_confdefs.h file. (Un)comment for getting - * functionality or size of u-boot code. + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - & ~CFG_CMD_NET \ - & ~CFG_CMD_LOADS \ - & ~CFG_CMD_CONSOLE \ - & ~CFG_CMD_AUTOSCRIPT \ -/* | CFG_CMD_JFFS2 */ \ - ) -#include +#include + +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_CONSOLE +#undef CONFIG_CMD_AUTOSCRIPT + /* * Boot options. Setting delay to -1 stops autostart count down. diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 10397628301..1149542bbe2 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -64,15 +64,20 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & ~CFG_CMD_DTT) | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_NFS | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP + +#undef CONFIG_CMD_DTT + #define CONFIG_ETHADDR 08:00:3e:26:0a:5b #define CONFIG_NETMASK 255.255.255.0 @@ -86,7 +91,7 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ #endif diff --git a/include/configs/xm250.h b/include/configs/xm250.h index 825bfd14e93..225d46a38ae 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -81,14 +81,17 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C + #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h index dc702cf4458..37daefe87ef 100644 --- a/include/configs/xsengine.h +++ b/include/configs/xsengine.h @@ -102,10 +102,17 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_BAUDRATE 115200 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_MMC | CFG_CMD_FAT | CFG_CMD_PING | CFG_CMD_JFFS2) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_PING +#define CONFIG_CMD_JFFS2 + #define CONFIG_BOOTDELAY 3 #define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h index b4c720d18b5..cfa12811351 100644 --- a/include/configs/xupv2p.h +++ b/include/configs/xupv2p.h @@ -118,27 +118,30 @@ #define CFG_ENV_IS_NOWHERE 1 #define CFG_ENV_SIZE 0x1000 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE) -#define CONFIG_COMMANDS (CONFIG__CMD_DFL |\ - CFG_CMD_MEMORY |\ - CFG_CMD_IRQ |\ - CFG_CMD_BDI |\ - CFG_CMD_NET |\ - CFG_CMD_IMI |\ - CFG_CMD_ECHO |\ - CFG_CMD_CACHE |\ - CFG_CMD_RUN |\ - CFG_CMD_AUTOSCRIPT |\ - CFG_CMD_ASKENV |\ - CFG_CMD_LOADS |\ - CFG_CMD_LOADB |\ - CFG_CMD_MISC |\ - CFG_CMD_FAT |\ - CFG_CMD_EXT2 |\ - CFG_CMD_PING \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_BDI +#define CONFIG_CMD_NET +#define CONFIG_CMD_IMI +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_RUN +#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MISC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_PING + /* Miscellaneous configurable options */ #define CFG_PROMPT "U-Boot-mONStR> " diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 3b106efdf51..853e4bcc0dd 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -239,11 +239,7 @@ /* Comment this out to enable USB 1.1 device */ #define USB_2_0_DEVICE -#define CMD_USB (CFG_CMD_USB | CFG_CMD_FAT | CFG_CMD_EXT2) - #define CONFIG_SUPPORT_VFAT -#else -#define CMD_USB 0 /* no USB on 440GR */ #endif /* CONFIG_440EP */ #ifdef DEBUG @@ -252,32 +248,40 @@ #define CONFIG_HW_WATCHDOG /* watchdog */ #endif -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CMD_USB) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + +#ifdef CONFIG_440EP + #define CONFIG_CMD_USB + #define CONFIG_CMD_FAT + #define CONFIG_CMD_EXT2 +#endif + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -344,7 +348,7 @@ */ #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -356,7 +360,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 1fdcc4b5052..ab323aaab43 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -136,7 +136,7 @@ /* Don't probe these addrs */ #define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54} -/* #if (CONFIG_COMMANDS & CFG_CMD_EEPROM) */ +/* #if defined(CONFIG_CMD_EEPROM) */ /* #define CFG_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */ #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ /* #endif */ @@ -191,24 +191,27 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + #define CONFIG_IBM_EMAC4_V4 1 #define CONFIG_MII 1 /* MII PHY management */ @@ -232,7 +235,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -313,7 +316,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -325,7 +328,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index 1e8ed7abdfc..3e636a27d2d 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -76,19 +76,23 @@ #define CONFIG_BAUDRATE 115200 + +/* + * Command line configuration. + */ +#include + #ifdef TURN_ON_ETHERNET -# define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) + #define CONFIG_CMD_PING #else -# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ - | CFG_CMD_ENV \ - | CFG_CMD_NAND) \ - & ~(CFG_CMD_NET \ - | CFG_CMD_FLASH \ - | CFG_CMD_IMLS)) + #define CONFIG_CMD_ENV + #define CONFIG_CMD_NAND + + #undef CONFIG_CMD_NET + #undef CONFIG_CMD_FLASH + #undef CONFIG_CMD_IMLS #endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CONFIG_BOOTDELAY -1 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b @@ -100,7 +104,7 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_TIMESTAMP -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -- cgit v1.3.1 From b6b4684546809f89c8bac72863ca49b5fd8ac0cd Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 5 Jul 2007 11:12:16 +0200 Subject: Minor coding style cleanup. Update CHANGELOG. --- CHANGELOG | 492 ++++++++++++++++++++++++++++++++++++++++-- include/configs/MPC8260ADS.h | 2 - include/configs/MPC8266ADS.h | 9 - include/configs/TQM834x.h | 6 - include/configs/acadia.h | 3 - include/configs/atstk1002.h | 3 - include/configs/bf537-stamp.h | 5 - include/configs/cpci5200.h | 3 - include/configs/csb472.h | 3 - include/configs/ml401.h | 4 - include/configs/sc520_cdp.h | 11 - 11 files changed, 474 insertions(+), 67 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 52b22a34e55..e907178434c 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,459 @@ +commit dca3b3d6d6396b67e5e84af53452164923c73443 +Author: Jon Loeliger +Date: Wed Jul 4 22:33:46 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various [v-z]* named board config files. + + Signed-off-by: Jon Loeliger + +commit 6c18eb9804b525f3e4f3bb3d014dd69a200d9fa7 +Author: Jon Loeliger +Date: Wed Jul 4 22:33:38 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various t* and u* named board config files. + + Signed-off-by: Jon Loeliger + +commit 46da1e96b7db14f4fcd2c92544e7c0862024bc76 +Author: Jon Loeliger +Date: Wed Jul 4 22:33:30 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various s* named board config files. + + Signed-off-by: Jon Loeliger + +commit 90cc3eb6d2be856d9ddd81436de9cf343bc6b5c8 +Author: Jon Loeliger +Date: Wed Jul 4 22:33:23 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various q* and r* named board config files. + + Signed-off-by: Jon Loeliger + +commit 26a34560d56a9df5bc2ae23525d9229736134757 +Author: Jon Loeliger +Date: Wed Jul 4 22:33:17 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various p* named board config files. + + Signed-off-by: Jon Loeliger + +commit a5cb23092a7d31490a33d4ec871468b63babfa3c +Author: Jon Loeliger +Date: Wed Jul 4 22:33:13 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various o* named board config files. + + Signed-off-by: Jon Loeliger + +commit 929a2bfd142737003a8fc32e1b86e1f2c1850257 +Author: Jon Loeliger +Date: Wed Jul 4 22:33:07 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various n* named board config files. + + Signed-off-by: Jon Loeliger + +commit 5dc11a511960d490f7f01ffd746edfe6277f99b0 +Author: Jon Loeliger +Date: Wed Jul 4 22:33:01 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various m* named board config files. + + Signed-off-by: Jon Loeliger + +commit 9bbb1c0820c1fbd3811ab6ee4ba0f6c6f76b27e4 +Author: Jon Loeliger +Date: Wed Jul 4 22:32:57 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various l* named board config files. + + Signed-off-by: Jon Loeliger + +commit bc234c129fa04fb9fa33530930e5cbc6084cd47a +Author: Jon Loeliger +Date: Wed Jul 4 22:32:51 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various j* and k* named board config files. + + Signed-off-by: Jon Loeliger + +commit 1d2c6bc491969f8d8fb34c8e30e8bea7a2af9c31 +Author: Jon Loeliger +Date: Wed Jul 4 22:32:32 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various i* named board config files. + + Signed-off-by: Jon Loeliger + +commit 48d5d102a2f2e619c92050b9aedbb69689185bc0 +Author: Jon Loeliger +Date: Wed Jul 4 22:32:25 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various h* named board config files. + + Signed-off-by: Jon Loeliger + +commit 72eb0efaed7048afcc61fc6f0085c49394b5dc36 +Author: Jon Loeliger +Date: Wed Jul 4 22:32:19 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various g* named board config files. + + Signed-off-by: Jon Loeliger + +commit 1bec3d3002d3bbbae6f2468a0f7376db1120d33e +Author: Jon Loeliger +Date: Wed Jul 4 22:32:10 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various e* named board config files. + + Signed-off-by: Jon Loeliger + +commit ab999ba1b31ebe78dd16374394a55d7c6e5aa6e4 +Author: Jon Loeliger +Date: Wed Jul 4 22:32:03 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various d* named board config files. + + Signed-off-by: Jon Loeliger + +commit 37e4f24b87fa255ae456d193b7cd23c18dd1d56b +Author: Jon Loeliger +Date: Wed Jul 4 22:31:56 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various c* named board config files. + + Signed-off-by: Jon Loeliger + +commit ba2351f9d1e841bd00ea6dad1e3c16d0259ad264 +Author: Jon Loeliger +Date: Wed Jul 4 22:31:49 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various b* named board config files. + + Signed-off-by: Jon Loeliger + +commit 0b361c916617aff79e647b40f0e43361e0bbaccf +Author: Jon Loeliger +Date: Wed Jul 4 22:31:42 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various a* named board config files. + + Signed-off-by: Jon Loeliger + +commit b730cda82e362df6a22f4c59c0a9b97e885b1014 +Author: Jon Loeliger +Date: Wed Jul 4 22:31:35 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in mpc5xx board config files. + + Signed-off-by: Jon Loeliger + +commit d794cfefead5fc177cf4f41164e80382e9c9484a +Author: Jon Loeliger +Date: Wed Jul 4 22:31:15 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various 5200 board config files. + + Signed-off-by: Jon Loeliger + +commit ef0df52ab49eea4a30c15087fd27d54c1d946f2c +Author: Jon Loeliger +Date: Wed Jul 4 22:31:07 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in STx board config files. + + Signed-off-by: Jon Loeliger + +commit 866e3089bfc826bb4dc74637f8aad87a3bab79fc +Author: Jon Loeliger +Date: Wed Jul 4 22:30:58 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in sbc* board config files. + + Signed-off-by: Jon Loeliger + +commit 2694690e285acaa34922f55f4b5ae030da60c55a +Author: Jon Loeliger +Date: Wed Jul 4 22:30:50 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in TQM board config files. + + Signed-off-by: Jon Loeliger + +commit 1cc4c458329765b58e584a19821e796b3c10e976 +Author: Jon Loeliger +Date: Wed Jul 4 22:30:28 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in 82xx board config files. + + Signed-off-by: Jon Loeliger + +commit 8ea5499afdaba0acf60923dd99001c399d4a7c8e +Author: Jon Loeliger +Date: Wed Jul 4 22:30:06 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in 83xx board config files. + + Signed-off-by: Jon Loeliger + +commit b24629fa377214d63bb40d1360e354b6d3e4af56 +Author: Jon Loeliger +Date: Wed Jun 13 13:23:15 2007 -0500 + + mpc86xx: Remove old CFG_CMD_* references. + + Signed-off-by: Jon Loeliger + +commit 46175d9764da129bb4fd341cd2554dc7d55f5b2a +Author: Jon Loeliger +Date: Wed Jun 13 13:22:54 2007 -0500 + + Add MPC8568MDS to MAKEALL 85xx target. + + It was missing from the original port submission. + + Signed-off-by: Jon Loeliger + +commit 2835e518c969e5124ba1174eef3e8375e12fa7d5 +Author: Jon Loeliger +Date: Wed Jun 13 13:22:08 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in 85xx board config files. + + Signed-off-by: Jon Loeliger + +commit 56b304ac2091689506088a9ae67f63fd6300cf16 +Author: Jon Loeliger +Date: Wed Jun 13 13:21:37 2007 -0500 + + Fix #if typo in CONFIG_CMD_* changes. + + Signed-off-by: Jon Loeliger + +commit 6810a34677dbc446334f5e451f1682426dd33b49 +Author: Grant Likely +Date: Tue Jul 3 00:17:28 2007 -0600 + + Fix Makefile to use $(MKCONFIG) macro for all board ports + + Signed-off-by: Grant Likely + +commit 90b1b2d69b9396ff2f01165ebc16c9a594eb5926 +Author: Grant Likely +Date: Tue Jul 3 00:17:28 2007 -0600 + + Fix Makefile to use $(MKCONFIG) macro for all board ports + + Signed-off-by: Grant Likely + +commit 057004f4a4863554d56cc56268bfa7c7d9738e27 +Author: Grant Likely +Date: Tue Jul 3 00:34:49 2007 -0600 + + Correct fixup relocation for mpc83xx + + Signed-off-by: Grant Likely + +commit 5af61b2f4b838a05f79be274f3e5a66edd2d9c96 +Author: Grant Likely +Date: Tue Jul 3 00:34:44 2007 -0600 + + Correct fixup relocation for mpc8260 + + Signed-off-by: Grant Likely + +commit f3a52fe05923935db86985daf9438e2f70ac39aa +Author: Grant Likely +Date: Tue Jul 3 00:34:39 2007 -0600 + + Correct fixup relocation for mpc824x + + Signed-off-by: Grant Likely + +commit a85dd254c0577fca13627c46e93fc2ad4c4f1f00 +Author: Grant Likely +Date: Tue Jul 3 00:34:34 2007 -0600 + + Correct fixup relocation for mpc8220 + + Signed-off-by: Grant Likely + +commit 6f7576b20ecf0d040c3ac3b032b5cbc860e38a90 +Author: Grant Likely +Date: Tue Jul 3 00:34:29 2007 -0600 + + Correct fixup relocation for MPC5xxx + + Signed-off-by: Grant Likely + +commit 3649cd99ba815b6601868735765602f00ef3692b +Author: Grant Likely +Date: Tue Jul 3 00:34:24 2007 -0600 + + Correct relocation fixup for mpc5xx + + Signed-off-by: Grant Likely + +commit f82b3b6304b620ef7e28bfaa1ea887a2ad2fa325 +Author: Grant Likely +Date: Tue Jul 3 00:34:19 2007 -0600 + + Don't set gd->reloc_off if relocation of .fixup works correctly + + Signed-off-by: Grant Likely + +commit e1a6144c32dc7de73bcdd33995de0148cbd0bd28 +Author: Grant Likely +Date: Tue Jul 3 00:34:14 2007 -0600 + + Remove obsolete mpc83xx linker scripts + + Signed-off-by: Grant Likely + +commit 17e32fc3908bf7089d3f16fc82a1c3ae674dd65b +Author: Grant Likely +Date: Tue Jul 3 00:34:09 2007 -0600 + + Consolidate mpc8260 linker scripts + + Signed-off-by: Grant Likely + +commit af7d38b393690d7eeaf418ac85a1e831a50d5fd0 +Author: Grant Likely +Date: Tue Jul 3 00:34:04 2007 -0600 + + Remove obsolete mpc824x linker scripts + + Signed-off-by: Grant Likely + +commit f94a3aecebc40ca0939c7d66d010009cf51be9e2 +Author: Grant Likely +Date: Tue Jul 3 00:33:59 2007 -0600 + + Remove obsolete mpc824x linker scripts (3 of 4) + + Signed-off-by: Grant Likely + +commit a71c084f3ac7fedf144537db2b2da47323068833 +Author: Grant Likely +Date: Tue Jul 3 00:33:53 2007 -0600 + + Remove obsolete mpc824x linker scripts (2 of 4) + + Signed-off-by: Grant Likely + +commit f670a15468d1365241d40022b9408e1004181f5e +Author: Grant Likely +Date: Tue Jul 3 00:33:48 2007 -0600 + + Remove obsolete mpc824x linker scripts (1 of 4) + + Signed-off-by: Grant Likely + +commit 09555bd45a04c0e54f172528d21bc18896550d28 +Author: Grant Likely +Date: Tue Jul 3 00:33:43 2007 -0600 + + Remove obsolete mpc8220 linker scripts + + Signed-off-by: Grant Likely + +commit 5efb992f046e51225c93d52f80fecbe433abd789 +Author: Grant Likely +Date: Tue Jul 3 00:33:38 2007 -0600 + + Remove obsolete mpc5xxx linker scripts (3 of 3) + + Signed-off-by: Grant Likely + +commit 07c13dfef65b31647e69d8b61daa1eec598add1a +Author: Grant Likely +Date: Tue Jul 3 00:33:33 2007 -0600 + + Remove obsolete mpc5xxx linker scripts (2 of 3) + + Signed-off-by: Grant Likely + +commit b4f67513a624ce85866c66c575bd2d9d7977d7f0 +Author: Grant Likely +Date: Tue Jul 3 00:33:28 2007 -0600 + + Remove obsolete mpc5xxx linker scripts (1 of 3) + + Signed-off-by: Grant Likely + +commit b7d8e05f8675249b5f208aa73babeed384a4519d +Author: Grant Likely +Date: Tue Jul 3 00:33:23 2007 -0600 + + Remove obsolete mpc5xx linker scripts + + Signed-off-by: Grant Likely + +commit 416a0b6d40f6eba3a2fc547253c16bda28d922f7 +Author: Grant Likely +Date: Tue Jul 3 00:33:18 2007 -0600 + + Consolidate mpc83xx linker scripts + + Signed-off-by: Grant Likely + +commit 5fc59175b92883ed5d2666a04e6bc49e70a4a365 +Author: Grant Likely +Date: Tue Jul 3 00:33:13 2007 -0600 + + Consolidate mpc8260 linker scripts + + Signed-off-by: Grant Likely + +commit 737f9eb02d7335df2b3e4d7a4d3348784d1da207 +Author: Grant Likely +Date: Tue Jul 3 00:33:08 2007 -0600 + + Consolidate mpc824x linker scripts + + Signed-off-by: Grant Likely + +commit 9c757b789a59a855db57b448dd825329c4e9c4a0 +Author: Grant Likely +Date: Tue Jul 3 00:33:03 2007 -0600 + + Consolidate mpc8220 linker scripts + + Signed-off-by: Grant Likely + +commit d181c9a15cd41863fe24840d17848429f27d3c8c +Author: Grant Likely +Date: Tue Jul 3 00:32:58 2007 -0600 + + Consolidate mpc5xxx linker scripts + + Signed-off-by: Grant Likely + +commit 287ac924adb7291bebe5086652a362a30ab28b13 +Author: Grant Likely +Date: Tue Jul 3 00:32:53 2007 -0600 + + Consolidate mpc5xx linker scripts + + Signed-off-by: Grant Likely + +commit 52b8704d0245e589f86d462e9ec25aeb7ecbbbdd +Author: Wolfgang Denk +Date: Wed Jul 4 00:43:53 2007 +0200 + + Fix a few file permission problems. + + Signed-off-by: Wolfgang Denk + +commit 78e0cf2de7be7f1eaeeb622eb61fd50e4d5e205c +Author: Wolfgang Denk +Date: Wed Jul 4 00:38:38 2007 +0200 + + Minor coding style cleanup. Rebuild CHANGELOG file. + commit 2f9c19e496acb6bb50d9299e1aab377625d48c38 Author: Jon Loeliger Date: Mon Jun 11 19:03:44 2007 -0500 @@ -1358,7 +1814,7 @@ Date: Sat May 5 08:12:30 2007 +0200 5xxx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -1500,7 +1956,7 @@ Date: Sat May 5 08:12:30 2007 +0200 5xxx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -1631,7 +2087,7 @@ Date: Mon Apr 30 13:59:50 2007 -0500 Fix memory initialization on MPC8349E-mITX Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. - This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary + This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into @@ -1788,7 +2244,7 @@ Date: Mon Feb 12 13:34:55 2007 -0600 85xx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2097,7 +2553,7 @@ Date: Fri Apr 20 14:12:26 2007 -0500 mpc86xx; Write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2150,7 +2606,7 @@ Date: Thu Apr 19 23:14:39 2007 -0400 What was suppose to be a stack variable was declared as a pointer, overwriting random memory. - Also moved the libfdt.a requirement into the main Makefile. That is + Also moved the libfdt.a requirement into the main Makefile. That is The U-Boot Way. commit d21686263574e95cb3e9e9b0496f968b1b897fdb @@ -2745,7 +3201,7 @@ Date: Sat Mar 31 12:22:10 2007 -0400 Add a flattened device tree (fdt) command (1 of 2) The fdt command uses David Gibson's libfdt library to manipulate as well - as print the flattened device tree. This patch is the new command, + as print the flattened device tree. This patch is the new command, the second part is the modifications to the existing code. commit 3af0d587d93e0be5f96e1b30fa41e662f8b0803e @@ -3446,7 +3902,7 @@ Date: Tue Feb 13 10:41:42 2007 -0600 mpc83xx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, this patch + and some have both. To support all of these device trees, this patch updates ftp_cpu_setup() to write the MAC address to mac-address if it exists. This function already updates local-mac-address. @@ -3669,7 +4125,7 @@ Date: Wed Dec 6 21:23:55 2006 -0500 mpc83xx: Put the version (and magic) after the HRCW. - Put the version (and magic) after the HRCW. This puts it in a fixed + Put the version (and magic) after the HRCW. This puts it in a fixed location in flash, not at the start of flash but as close as we can get. Signed-off-by: Jerry Van Baren @@ -3963,7 +4419,7 @@ Date: Tue Feb 20 09:05:31 2007 +0100 [PATCH 7_9] Replace ace_readw_ace_writeb functions with macros - Register read/write does not need to be wrapped in a full function. The + Register read/write does not need to be wrapped in a full function. The patch replaces them with macros. Signed-off-by: Grant Likely @@ -4266,7 +4722,7 @@ commit fdef388758506765d4d6a7155c8f1584c63ff581 Author: roy zang Date: Mon Jan 22 13:19:21 2007 +0800 - use CFG_WRITE_SWAPPED_DATA define instead of define CFG_FLASH_CFI_SWAP + use CFG_WRITE_SWAPPED_DATA define instead of define CFG_FLASH_CFI_SWAP The patch by Heiko Schocher on Jan, 19, 2007 fixes cfi_driver bug for mpc7448hpc2 board. The default cfi_driver can support mpc7448hpc2 board. @@ -4954,7 +5410,7 @@ Date: Mon Nov 27 17:04:06 2006 +0100 [PATCH] Allow CONFIG_OF_FLAT_TREE to boot a non-arch/powerpc kernel This patch allows an arch/ppc kernel to be booted by just passing 1 or 2 - arguments to bootm. It removes the getenv("disable_of") test that used + arguments to bootm. It removes the getenv("disable_of") test that used to be used for this purpose. Signed-off-by: Grant Likely @@ -5530,7 +5986,7 @@ Date: Thu Nov 2 19:08:55 2006 +0800 Gigabit Ethernet ports,E0 and E1. It uses a single Management interface to manage the two physical connection devices (PHYs). Each Ethernet port has its own statistics monitor that tracks and reports key interface - statistics. Each port supports a 256-entry hash table for address + statistics. Each port supports a 256-entry hash table for address filtering. In addition, each port is bridged to the Switch Fabric through a 2-Kbyte transmit FIFO and a 4-Kbyte Receive FIFO. @@ -5576,7 +6032,7 @@ commit 87c4db09699c6b89176b31004afcb83eb1585d47 Author: roy zang Date: Thu Nov 2 18:59:15 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. mpc7448hpc2 board support high level code:tsi108 init + mpc7448hpc2. Signed-off-by: Alexandre Bounine @@ -5586,7 +6042,7 @@ commit 27801b8ab11c61b577e45742a515bb3b23b80241 Author: roy zang Date: Thu Nov 2 18:57:21 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. Make ,config.mk and link file for the mpc7448hpc2 board. Signed-off-by: Alexandre Bounine @@ -5596,7 +6052,7 @@ commit c6411c0c3bbc79f9ba8aef58296a42d8f9d8a0a6 Author: roy zang Date: Thu Nov 2 18:55:04 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. The mpc7448hpc2 board support header file. Signed-off-by: Alexandre Bounine @@ -5606,7 +6062,7 @@ commit 625bb5ddb50b243f931262ca8c46956409471917 Author: roy zang Date: Thu Nov 2 18:52:21 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. The mpc7448hpc2 board support low level assemble language init code. Signed-off-by: Alexandre Bounine @@ -5831,7 +6287,7 @@ Date: Tue Oct 24 23:47:37 2006 -0500 If a Multi-Image file contains a third image we try to use it as a device tree. The device tree image is assumed to be uncompressed in the - image file. We automatically allocate space for the device tree in memory + image file. We automatically allocate space for the device tree in memory and provide an 8k pad to allow more than a reasonable amount of growth. Additionally, a device tree that was contained in flash will now automatically diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index aaecd38c9df..eceeb5e3973 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -246,8 +246,6 @@ #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ - - #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/mtdblock2" diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index d6dd73bfd0d..306ee49eb4d 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -141,11 +141,9 @@ */ #define SPD_EEPROM_ADDRESS 0x50 - #define CONFIG_8260_CLKIN 66000000 /* in Hz */ #define CONFIG_BAUDRATE 115200 - /* * Command line configuration. */ @@ -214,8 +212,6 @@ CONFIG_BOOTP_BOOTFILESIZE | \ CONFIG_BOOTP_DNS) - - #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #if defined(CONFIG_CMD_KGDB) @@ -285,7 +281,6 @@ #define SDRAM_SPD_ADDR 0x50 - /*----------------------------------------------------------------------- * BR2,BR3 - Base Register * Ref: Section 10.3.1 on page 10-14 @@ -383,7 +378,6 @@ #error "INVALID SDRAM CONFIGURATION" #endif - #define RS232EN_1 0x02000002 #define RS232EN_2 0x01000001 #define FETHIEN 0x08000008 @@ -395,7 +389,6 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - /* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2) */ /* 0x0EB2B645 */ #define CFG_HRCW_MASTER (( HRCW_BPS11 | HRCW_CIP ) |\ @@ -452,13 +445,11 @@ # define CFG_ENV_SIZE 0x200 #endif /* CFG_RAMBOOT */ - #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ #if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif - /*----------------------------------------------------------------------- * HIDx - Hardware Implementation-dependent Registers 2-11 *----------------------------------------------------------------------- diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 9628703b317..684cb304568 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -281,7 +281,6 @@ extern int tqm834x_num_flash_banks; #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ - #undef CONFIG_EEPRO100 #define CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -316,7 +315,6 @@ extern int tqm834x_num_flash_banks; #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - /* * Command line configuration. */ @@ -339,10 +337,6 @@ extern int tqm834x_num_flash_banks; #undef CONFIG_CMD_LOADS #endif - - - - /* * Miscellaneous configurable options */ diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 3f5d025ac8e..5bd8ac63e1d 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -299,7 +299,6 @@ #define CONFIG_SUPPORT_VFAT - /* * Command line configuration. */ @@ -331,8 +330,6 @@ #undef CONFIG_CMD_IMLS #endif - - #undef CONFIG_WATCHDOG /* watchdog disabled */ /*----------------------------------------------------------------------- diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 90fe8a55c5b..de2fd31af25 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -111,7 +111,6 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_SUBNETMASK \ | CONFIG_BOOTP_GATEWAY) - /* * Command line configuration. */ @@ -129,8 +128,6 @@ #undef CONFIG_CMD_SETGETDCR #undef CONFIG_CMD_XIMG - - #define CONFIG_ATMEL_USART 1 #define CONFIG_MACB 1 #define CONFIG_PIO2 1 diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 1c23871d80f..36f55d164c8 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -166,8 +166,6 @@ #define CONFIG_NETCONSOLE 1 #define CONFIG_NET_MULTI 1 - - /* * Command line configuration. */ @@ -196,7 +194,6 @@ #endif - #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) #define CONFIG_CMD_DHCP @@ -209,8 +206,6 @@ #endif - - #define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600" #define CONFIG_LOADADDR 0x1000000 diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index efb89bf96cc..c4ed19abdd1 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -99,7 +99,6 @@ #define CONFIG_USB_STORAGE #endif - /* * Command line configuration. */ @@ -118,8 +117,6 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_DATE - - #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ # define CFG_LOWBOOT 1 # define CFG_LOWBOOT16 1 diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 1fef94f76cf..316b1fee21d 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -80,8 +80,6 @@ CONFIG_BOOTP_DNS2 | \ CONFIG_BOOTP_BOOTFILESIZE ) - - /* * Command line configuration. */ @@ -98,7 +96,6 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP - /* * Serial download configuration * diff --git a/include/configs/ml401.h b/include/configs/ml401.h index 9537008e040..6cfc9478a24 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -145,8 +145,6 @@ #define CFG_FLASH_PROTECTION /* hardware flash protection */ #endif /* !FLASH */ - - /* * Command line configuration. */ @@ -181,8 +179,6 @@ #endif #endif - - #if defined(CONFIG_CMD_JFFS2) /* JFFS2 partitions */ #define CONFIG_JFFS2_CMDLINE /* mtdparts command line support */ diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index 1001342a059..8689be4df3f 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -64,10 +64,8 @@ */ #define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024) - #define CONFIG_BAUDRATE 9600 - /* * Command line configuration. */ @@ -79,8 +77,6 @@ #define CONFIG_CMD_NET #define CONFIG_CMD_EEPROM - - #define CONFIG_BOOTDELAY 15 #define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600" /* #define CONFIG_BOOTCOMMAND "bootm 38000000" */ @@ -90,7 +86,6 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif - /* * Miscellaneous configurable options */ @@ -113,7 +108,6 @@ /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - /*----------------------------------------------------------------------- * Physical Memory Map */ @@ -122,8 +116,6 @@ /*----------------------------------------------------------------------- * FLASH and environment organization */ - - #define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */ #define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ @@ -134,11 +126,9 @@ #define CONFIG_SPI_EEPROM /* Support for SPI EEPROMs (AT25128) */ #define CONFIG_MW_EEPROM /* Support for MicroWire EEPROMs (AT93LC46) */ - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE - /* Environment in EEPROM */ #define CFG_ENV_IS_IN_EEPROM 1 #define CONFIG_SPI @@ -218,7 +208,6 @@ #define CONFIG_I8042_KBD #define CFG_ISA_IO 0 - /************************************************************ * RTC ***********************************************************/ -- cgit v1.3.1 From e4dbe1b215f5c6c462e76909d240bd96472b84de Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 5 Jul 2007 17:56:27 +0200 Subject: Fixing some typos etc. introduced mainly by cfg patches. Signed-off-by: Wolfgang Denk --- cpu/mpc8260/cpu_init.c | 2 +- fs/jffs2/jffs2_1pass.c | 9 ++++++--- include/configs/MPC8260ADS.h | 4 ++-- include/configs/Total5200.h | 2 +- include/configs/ZPC1900.h | 12 ++++++------ include/configs/lwmon.h | 2 +- 6 files changed, 17 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c index 380d7af13d3..36fc1eba5fd 100644 --- a/cpu/mpc8260/cpu_init.c +++ b/cpu/mpc8260/cpu_init.c @@ -182,7 +182,7 @@ void cpu_init_f (volatile immap_t * immr) #endif /* now restrict to preliminary range */ - /* the PS came from the HRCW, don´t change it */ + /* the PS came from the HRCW, don´t change it */ memctl->memc_br0 = SET_VAL_MASK(memctl->memc_br0 , CFG_BR0_PRELIM, BRx_PS_MSK); memctl->memc_or0 = CFG_OR0_PRELIM; diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index 6a7d7f7fac6..af2a8e28067 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -143,7 +143,8 @@ /* keeps pointer to currentlu processed partition */ static struct part_info *current_part; -#if (defined(CONFIG_JFFS2_NAND) && ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) +#if (defined(CONFIG_JFFS2_NAND) && \ + ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND)) ) #if defined(CFG_NAND_LEGACY) #include #else @@ -334,7 +335,8 @@ static inline void *get_node_mem(u32 off) return get_node_mem_nor(off); #endif -#if defined(CONFIG_JFFS2_NAND) && ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND) +#if defined(CONFIG_JFFS2_NAND) && \ + (CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND) if (id->type == MTD_DEV_TYPE_NAND) return get_node_mem_nand(off); #endif @@ -345,7 +347,8 @@ static inline void *get_node_mem(u32 off) static inline void put_fl_mem(void *buf) { -#if defined(CONFIG_JFFS2_NAND) && ((CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND) +#if defined(CONFIG_JFFS2_NAND) && \ + (CONFIG_COMMANDS & CFG_CMD_NAND) || defined(CONFIG_CMD_NAND) struct mtdids *id = current_part->dev->id; if (id->type == MTD_DEV_TYPE_NAND) diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index eceeb5e3973..69d4c28f03d 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -250,7 +250,7 @@ #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/mtdblock2" -#if defined(CONFIG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) || (CONFIG_COMMANDS & CFG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -268,7 +268,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) || (CONFIG_COMMANDS & CFG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index ba2daf73cd7..2a1cb89ad4f 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -115,7 +115,7 @@ */ #include -#if definded(CONFIG_MPC5200) +#if defined(CONFIG_MPC5200) #define CONFIG_CMD_PCI #endif diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index a5085cfb79d..2b02fe75093 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -248,18 +248,18 @@ #define CFG_LSRT 0x0F #define CFG_MPTPR 0x4000 -#define CFG_PSDRAM_BR CFG_SDRAM_BASE | 0x00000041 +#define CFG_PSDRAM_BR (CFG_SDRAM_BASE | 0x00000041) #define CFG_PSDRAM_OR 0xFC0028C0 -#define CFG_LSDRAM_BR CFG_LSDRAM_BASE | 0x00001861 +#define CFG_LSDRAM_BR (CFG_LSDRAM_BASE | 0x00001861) #define CFG_LSDRAM_OR 0xFF803480 -#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801 +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00000801) #define CFG_OR0_PRELIM 0xFFE00856 -#define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801 +#define CFG_BR5_PRELIM (CFG_EEPROM | 0x00000801) #define CFG_OR5_PRELIM 0xFFFF03F6 -#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00001801 +#define CFG_BR6_PRELIM (CFG_FLSIMM_BASE | 0x00001801) #define CFG_OR6_PRELIM 0xFF000856 -#define CFG_BR7_PRELIM CFG_BCSR | 0x00000801 +#define CFG_BR7_PRELIM (CFG_BCSR | 0x00000801) #define CFG_OR7_PRELIM 0xFFFF83F6 #define CFG_RESET_ADDRESS 0xC0000000 diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index 627bc9cf41e..3dc7a8eb650 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -279,7 +279,7 @@ */ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0x40000000 -#if defined(DEBUG) || defiend(CONFIG_CMD_IDE) +#if defined(DEBUG) || defined(CONFIG_CMD_IDE) #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ -- cgit v1.3.1 From f1152f8c28db4a22087c21c618a3f7baa48e9a4f Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 6 Jul 2007 02:50:19 +0200 Subject: Code cleanup and default config update for STC GP3 SSA board. Signed-off-by: Wolfgang Denk --- board/stxssa/stxssa.c | 274 +++++++++++++++++++++++------------------------ include/configs/stxssa.h | 126 +++++++++++----------- 2 files changed, 200 insertions(+), 200 deletions(-) (limited to 'include') diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c index 0fb233d818a..5882124150e 100644 --- a/board/stxssa/stxssa.c +++ b/board/stxssa/stxssa.c @@ -52,147 +52,147 @@ long int fixed_sdram (void); const iop_conf_t iop_conf_tab[4][32] = { /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ - /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ - /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ - /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ - /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ - /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ - /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ - /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ - /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ - /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ - /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ - /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ - /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */ + /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */ + /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */ + /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */ + /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */ + /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */ + /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ + /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ + /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ + /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ + /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */ + /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */ + /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */ + /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */ + /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */ + /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */ + /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */ + /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */ + /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ + /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ + /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ + /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ + /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ + /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ + /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ + /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ + /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */ + /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ }, /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ + /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ + /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ + /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ + /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ + /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ + /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ + /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ + /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ + /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ + /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ + /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ + /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ + /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ + /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ + /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ + /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ + /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ + /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */ + /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ + /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ + /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ }, /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ - /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ + /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ + /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ + /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ + /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ + /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ + /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ + /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ + /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ + /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ + /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ + /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ + /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ + /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */ + /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ + /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ + /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ + /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ + /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ + /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ + /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ }, /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */ - /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ + /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ + /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ + /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ + /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */ + /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ + /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ + /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ + /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ + /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ + /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ + /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ + /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ + /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ } }; @@ -227,12 +227,12 @@ reset_phy(void) #if (CONFIG_ETHER_INDEX == 2) bcsr->bcsr2 &= ~FETH2_RST; udelay(2); - bcsr->bcsr2 |= FETH2_RST; + bcsr->bcsr2 |= FETH2_RST; udelay(1000); #elif (CONFIG_ETHER_INDEX == 3) bcsr->bcsr3 &= ~FETH3_RST; udelay(2); - bcsr->bcsr3 |= FETH3_RST; + bcsr->bcsr3 |= FETH3_RST; udelay(1000); #endif #if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC) @@ -252,10 +252,10 @@ int board_early_init_f(void) { #if defined(CONFIG_PCI) - volatile immap_t *immr = (immap_t *)CFG_IMMR; - volatile ccsr_pcix_t *pci = &immr->im_pcix; + volatile immap_t *immr = (immap_t *)CFG_IMMR; + volatile ccsr_pcix_t *pci = &immr->im_pcix; - pci->peer &= 0xfffffffdf; /* disable master abort */ + pci->peer &= 0xffffffdf; /* disable master abort */ #endif /* Why is the phy reset done _after_ the ethernet diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index a14cd50dd34..2e527b23ab5 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -42,20 +42,20 @@ #define CONFIG_CPM2 1 /* has CPM2 */ #define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/ -#undef CONFIG_PCI /* pci ethernet support */ -#define CONFIG_TSEC_ENET /* tsec ethernet support*/ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#define CONFIG_PCI /* PCI ethernet support */ +#define CONFIG_TSEC_ENET /* tsec ethernet support*/ +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ +#undef CONFIG_DDR_ECC /* only for ECC DDR module */ +#undef CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ /* sysclk for MPC85xx */ -#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ +#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ /* Blinkin' LEDs for Robert :-) */ @@ -64,23 +64,23 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ -#undef CFG_DRAM_TEST /* memory test, takes time */ -#define CFG_MEMTEST_START 0x00200000 /* memtest region */ -#define CFG_MEMTEST_END 0x00400000 +#undef CFG_DRAM_TEST /* memory test, takes time */ +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 -/* Localbus connector. There are many options that can be +/* Localbus connector. There are many options that can be * connected here, including sdram or lots of flash. * This address, however, is used to configure a 256M local bus * window that includes the Config latch below. */ -#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */ +#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */ #define CFG_LBC_OPTION_SIZE 256 /* 256MB */ /* There are various flash options used, we configure for the largest, @@ -88,16 +88,16 @@ * sizes. */ #ifdef CONFIG_STXSSA_4M -#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */ +#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */ #else -#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */ +#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */ #endif #define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x1801) /* port size 32bit */ #define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7) #define CFG_FLASH_CFI 1 #define CFG_FLASH_CFI_DRIVER 1 -#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ +#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ #define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ @@ -110,22 +110,22 @@ */ #define CFG_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */ #define CFG_BR1_PRELIM 0xFB001801 /* 32-bit port */ -#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */ +#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */ -#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #define CFG_RAMBOOT #else -#undef CFG_RAMBOOT +#undef CFG_RAMBOOT #endif #ifdef CFG_RAMBOOT -#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ +#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ #else -#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif -#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ @@ -140,14 +140,14 @@ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE -#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */ +#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */ #undef CONFIG_CLOCKS_IN_MHZ /* local bus definitions */ -#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ +#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ #define CFG_OR2_PRELIM 0xfc006901 -#define CFG_LBC_LCRR 0x00030004 /* local bus freq */ +#define CFG_LBC_LCRR 0x00030004 /* local bus freq */ #define CFG_LBC_LBCR 0x00000000 #define CFG_LBC_LSRT 0x20000000 #define CFG_LBC_MRTPR 0x20000000 @@ -158,52 +158,52 @@ #define CFG_LBC_LSDMR_5 0x4061b723 #define CONFIG_L1_INIT_RAM -#define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ -#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ +#define CFG_INIT_RAM_LOCK 1 +#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ -#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET -#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 2 #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CFG_NS16550 #define CFG_NS16550_SERIAL -#define CFG_NS16550_REG_SIZE 1 +#define CFG_NS16550_REG_SIZE 1 #define CFG_NS16550_CLK get_bus_freq(0) #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} -#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) -#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) +#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) +#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ -#ifdef CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif /* I2C */ #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ -#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F #if 0 -#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */ #else /* I did the 'if 0' so we could keep the syntax above if ever needed. */ #undef CFG_I2C_NOPROBES #endif #define CFG_I2C_OFFSET 0x3000 -/* I2C EEPROM. AT24C32, we keep our environment in here. +/* I2C EEPROM. AT24C32, we keep our environment in here. */ #define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */ #define CFG_I2C_EEPROM_ADDR_LEN 2 @@ -232,26 +232,26 @@ #if defined(CONFIG_PCI) /* PCI Ethernet card */ #define CONFIG_NET_MULTI -#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_PCI_PNP /* do pci plug-and-play */ -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP +#define CONFIG_EEPRO100 +#define CONFIG_TULIP #if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ + #define PCI_ENET0_IOADDR 0xe0000000 + #define PCI_ENET0_MEMADDR 0xe0000000 + #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif -#undef CONFIG_PCI_SCAN_SHOW -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ +#define CONFIG_PCI_SCAN_SHOW +#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #endif /* CONFIG_PCI */ #if defined(CONFIG_TSEC_ENET) #ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_MULTI 1 #endif #define CONFIG_MII 1 /* MII PHY management */ @@ -260,7 +260,7 @@ #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 #define CONFIG_TSEC2_NAME "TSEC1" -#undef CONFIG_MPS85XX_FEC +#define CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 4 @@ -270,9 +270,9 @@ #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ -#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ +#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ +#undef CONFIG_ETHER_NONE /* define if ether on something else */ +#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ #if (CONFIG_ETHER_INDEX == 2) /* @@ -281,19 +281,19 @@ * - Select bus for bd/buffers * - Full duplex */ - #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CFG_CPMFCR_RAMTYPE 0 + #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) + #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) + #define CFG_CPMFCR_RAMTYPE 0 #if 0 - #define CFG_FCC_PSMR (FCC_PSMR_FDE) + #define CFG_FCC_PSMR (FCC_PSMR_FDE) #else - #define CFG_FCC_PSMR 0 + #define CFG_FCC_PSMR 0 #endif #define FETH2_RST 0x01 #elif (CONFIG_ETHER_INDEX == 3) /* need more definitions here for FE3 */ #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ +#endif /* CONFIG_ETHER_INDEX */ /* MDIO is done through the TSEC0 control. */ @@ -415,13 +415,13 @@ */ #ifdef CFG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */ -#define CONFIG_BAUDRATE 38400 +#define CONFIG_BAUDRATE 38400 #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ #define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000" #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate" #define CONFIG_SERVERIP 192.168.85.1 -#define CONFIG_IPADDR 192.168.85.60 +#define CONFIG_IPADDR 192.168.85.60 #define CONFIG_GATEWAYIP 192.168.85.1 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_HOSTNAME STX_SSA @@ -431,7 +431,7 @@ #else /* ENV IS IN FLASH -- use a full-blown envionment */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ -- cgit v1.3.1 From 498ff9a228485bd4b9f23d066bada268f9add1dd Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 5 Jul 2007 19:13:52 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various A* named board config files. Since ADS860.h includes "board/fads/fads.h" with ramifications on the CONFIG_COMMAND treatment, it too has to be adjusted to exclude already configured commands in this same commit. Signed-off-by: Jon Loeliger --- board/fads/fads.h | 32 +++++++++-------- include/configs/A3000.h | 22 +++--------- include/configs/ADCIOP.h | 20 ++++++----- include/configs/ADNPESC1.h | 81 ++++++++++++++++++++---------------------- include/configs/ADS860.h | 18 ++++++---- include/configs/AMX860.h | 40 +++++++++++---------- include/configs/AP1000.h | 32 +++++++++-------- include/configs/APC405.h | 36 ++++++++++--------- include/configs/AR405.h | 29 ++++++++------- include/configs/ASH405.h | 33 +++++++++-------- include/configs/Adder.h | 20 ++++++----- include/configs/Alaska8220.h | 51 +++++++++++++------------- include/configs/AmigaOneG3SE.h | 43 +++++++++++----------- 13 files changed, 232 insertions(+), 225 deletions(-) (limited to 'include') diff --git a/board/fads/fads.h b/board/fads/fads.h index 29c226af917..ac37f96d752 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -95,21 +95,23 @@ #define CFG_DISCOVER_PHY #endif -#ifndef CONFIG_COMMANDS -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_DHCP \ - | CFG_CMD_ECHO \ - | CFG_CMD_IMMAP \ - | CFG_CMD_JFFS2 \ - | CFG_CMD_MII \ - | CFG_CMD_PCMCIA \ - | CFG_CMD_PING \ - ) -#endif /* !CONFIG_COMMANDS */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#if !defined(FADS_COMMANDS_ALREADY_DEFINED) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_PCMCIA +#define CONFIG_CMD_PING + +#endif + /* * Miscellaneous configurable options diff --git a/include/configs/A3000.h b/include/configs/A3000.h index ca9592c23bc..eb074907666 100644 --- a/include/configs/A3000.h +++ b/include/configs/A3000.h @@ -52,23 +52,11 @@ #define CONFIG_BOOTDELAY 5 -#if 0 -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_BSP | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_FLASH | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_NET | \ - CFG_CMD_PCI ) -#endif - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include /* @@ -309,7 +297,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h index 821efe5d48b..f79fad18612 100644 --- a/include/configs/ADCIOP.h +++ b/include/configs/ADCIOP.h @@ -59,21 +59,23 @@ #define CONFIG_IPADDR 10.0.18.222 #define CONFIG_SERVERIP 10.0.18.190 -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_ASKENV ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ASKENV -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -185,7 +187,7 @@ */ #define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ #define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h index 2efca1056e9..0635506e628 100644 --- a/include/configs/ADNPESC1.h +++ b/include/configs/ADNPESC1.h @@ -401,15 +401,8 @@ #define CONFIG_RTC_DS1306 1 /* Dallas 1306 real time clock */ #define CFG_SPI_RTC_DEVID 0 /* as 1st SPI device */ -#define __SPI_CMD_OFF 0 /* allow default commands: */ - /* CFG_CMD_SPI */ - /* CFG_CMD_DATE */ - #else #undef CONFIG_NIOS_SPI /* NO SPI support */ -#define __SPI_CMD_OFF ( CFG_CMD_SPI \ - | CFG_CMD_DATE \ - ) #endif /*------------------------------------------------------------------------ @@ -570,45 +563,49 @@ #define CONFIG_POST CFG_POST_RTC #define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_ASKENV | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_BMP | \ - CFG_CMD_CACHE | \ - CFG_CMD_DOC | \ - CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_IDE | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_KGDB | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_MMC | \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_SCSI | \ - CFG_CMD_VFD | \ - CFG_CMD_USB | \ - CFG_CMD_XIMG | \ - __SPI_CMD_OFF ) ) - - -#include + +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_ASKENV +#undef CONFIG_CMD_BEDBUG +#undef CONFIG_CMD_BMP +#undef CONFIG_CMD_CACHE +#undef CONFIG_CMD_DOC +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_FAT +#undef CONFIG_CMD_FDC +#undef CONFIG_CMD_FDOS +#undef CONFIG_CMD_HWFLOW +#undef CONFIG_CMD_IDE +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_KGDB +#undef CONFIG_CMD_NAND +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_MMC +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_PCI +#undef CONFIG_CMD_PCMCIA +#undef CONFIG_CMD_SCSI +#undef CONFIG_CMD_VFD +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_XIMG + +#if (CFG_NIOS_CPU_SPI_NUMS != 1) +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_DATE +#endif + /*------------------------------------------------------------------------ * KGDB *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 9600 #endif diff --git a/include/configs/ADS860.h b/include/configs/ADS860.h index df20965640e..2ee8c61cea4 100644 --- a/include/configs/ADS860.h +++ b/include/configs/ADS860.h @@ -37,13 +37,19 @@ #define CONFIG_DRAM_50MHZ 1 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_PCMCIA \ - | CFG_CMD_PING \ - ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_PCMCIA +#define CONFIG_CMD_PING + +/* This is picked up again in fads.h */ +#define FADS_COMMANDS_ALREADY_DEFINED #include "fads.h" diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h index 14d56bfd97d..9e4303fb9e4 100644 --- a/include/configs/AMX860.h +++ b/include/configs/AMX860.h @@ -61,38 +61,40 @@ #undef CONFIG_BOOTARGS -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ -#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ -#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ -#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ -#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ -#endif - - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * Command line configuration. + */ +#include -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + + +#if defined(CONFIG_CMD_KGDB) +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ +#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ +#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ +#endif + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -196,7 +198,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h index ba4b1a2bc8c..015699dbdcf 100644 --- a/include/configs/AP1000.h +++ b/include/configs/AP1000.h @@ -66,18 +66,20 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_IRQ | \ - CFG_CMD_MVENV | \ - CFG_CMD_PCI | \ - CFG_CMD_PING \ - ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MVENV +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -89,7 +91,7 @@ * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -188,7 +190,7 @@ */ #define CFG_DCACHE_SIZE 16384 #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -228,7 +230,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 3df99a008b9..5ac86bef860 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -67,27 +67,29 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ @@ -106,7 +108,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -266,7 +268,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/AR405.h b/include/configs/AR405.h index 1cd0280e217..785f9455051 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -71,17 +71,20 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_BSP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_BSP + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -92,7 +95,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -207,7 +210,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index d03c05bf349..f0ec761ebb5 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -59,19 +59,22 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_NAND | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -91,7 +94,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -270,7 +273,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/Adder.h b/include/configs/Adder.h index 0e6b50f8b0e..9a429442fd9 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -52,15 +52,17 @@ #define CFG_8xx_CPUCLK_MAX 133000000 #endif /* CONFIG_MPC852T */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -/* This must be included AFTER the definition of CONFIG_COMMANDS */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */ diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h index c08b2c39f88..e47872d27ea 100644 --- a/include/configs/Alaska8220.h +++ b/include/configs/Alaska8220.h @@ -39,12 +39,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -70,31 +64,31 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CACHE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) +#include + +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP + #define CONFIG_NET_MULTI #define CONFIG_MII -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Autobooting */ @@ -282,7 +276,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -298,6 +292,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Various low-level settings */ diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h index ea50f41504c..8e902fef82a 100644 --- a/include/configs/AmigaOneG3SE.h +++ b/include/configs/AmigaOneG3SE.h @@ -63,32 +63,31 @@ #define CONFIG_DOS_PARTITION #define CONFIG_AMIGA_PARTITION -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_NET | \ - CFG_CMD_IDE | \ - CFG_CMD_FDC | \ - CFG_CMD_CACHE | \ - CFG_CMD_CONSOLE| \ - CFG_CMD_USB | \ - CFG_CMD_BSP | \ - CFG_CMD_PCI ) - -/* CFG_CMD_MII | \ */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_NET +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FDC +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_CONSOLE| +#define CONFIG_CMD_USB +#define CONFIG_CMD_BSP +#define CONFIG_CMD_PCI + #define CONFIG_PCI 1 /* #define CONFIG_PCI_SCAN_SHOW 1 */ #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include - - /* * Miscellaneous configurable options */ @@ -247,7 +246,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From de8b2a6e33298dcdb10bdda48db25e53c3089eba Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 5 Jul 2007 19:32:07 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various B* named board config files. Signed-off-by: Jon Loeliger --- include/configs/B2.h | 19 ++++---- include/configs/BAB7xx.h | 21 ++++++--- include/configs/BC3450.h | 115 +++++++++++++++++++---------------------------- include/configs/BMW.h | 26 +++++------ 4 files changed, 84 insertions(+), 97 deletions(-) (limited to 'include') diff --git a/include/configs/B2.h b/include/configs/B2.h index e55858d34bc..244ad4ffb77 100644 --- a/include/configs/B2.h +++ b/include/configs/B2.h @@ -74,14 +74,17 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C + #define CONFIG_BOOTDELAY 5 #define CONFIG_ETHADDR 00:50:c2:1e:af:fb diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h index 46bdfa2ee62..2569c914831 100644 --- a/include/configs/BAB7xx.h +++ b/include/configs/BAB7xx.h @@ -68,12 +68,19 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2 |\ - CFG_CMD_SCSI | CFG_CMD_IDE | CFG_CMD_DATE |\ - CFG_CMD_FDC | CFG_CMD_ELF) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_IDE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_FDC +#define CONFIG_CMD_ELF -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options @@ -86,7 +93,7 @@ */ #define CONFIG_CONS_INDEX 1 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -436,7 +443,7 @@ extern unsigned long bab7xx_get_gclk_freq (void); * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index bc30977fd7a..00b656e737d 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -61,11 +61,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -106,12 +101,6 @@ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#ifdef CONFIG_PCI -# define ADD_PCI_CMD CFG_CMD_PCI -#else -# define ADD_PCI_CMD 0 -#endif - /* * Video console */ @@ -126,12 +115,6 @@ # define CONFIG_SPLASH_SCREEN # define CFG_CONSOLE_IS_IN_ENV -#ifdef CONFIG_VIDEO -# define ADD_BMP_CMD CFG_CMD_BMP -#else -# define ADD_BMP_CMD 0 -#endif - /* * Partitions */ @@ -144,10 +127,7 @@ */ #ifdef CONFIG_BC3450_USB # define CONFIG_USB_OHCI -# define ADD_USB_CMD CFG_CMD_USB # define CONFIG_USB_STORAGE -#else /* !CONFIG_BC3450_USB */ -# define ADD_USB_CMD 0 #endif /* CONFIG_BC3450_USB */ /* @@ -165,59 +145,53 @@ # define CFG_CMD_POST_DIAG 0 #endif /* CONFIG_POST */ + /* - * IDE + * Command line configuration. */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_POST_DIAG +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_BSP + +#ifdef CONFIG_VIDEO + #define CONFIG_CMD_BMP +#endif + #ifdef CONFIG_BC3450_IDE -# define ADD_IDE_CMD CFG_CMD_IDE -#else -# define ADD_IDE_CMD 0 -#endif /* CONFIG_BC3450_IDE */ + #define CONFIG_CMD_IDE +#endif -/* - * Filesystem support - */ -#if defined (CONFIG_BC3450_IDE) || defined (CONFIG_BC3450_USB) -#ifdef CONFIG_FAT -# define ADD_FAT_CMD CFG_CMD_FAT -#else -# define ADD_FAT_CMD 0 -#endif /* CONFIG_FAT */ +#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB) + #ifdef CONFIG_FAT + #define CONFIG_CMD_FAT + #endif -#ifdef CONFIG_EXT2 -# define ADD_EXT2_CMD CFG_CMD_EXT2 -#else -# define ADD_EXT2_CMD 0 -#endif /* CONFIG_EXT2 */ -#endif /* CONFIG_BC3450_IDE / _USB */ + #ifdef CONFIG_EXT2 + #define CONFIG_CMD_EXT2 + #endif +#endif + +#ifdef CONFIG_BC3450_USB + #define CONFIG_CMD_USB +#endif + +#ifdef CONFIG_PCI + #define CONFIG_CMD_PCI +#endif -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_BMP_CMD | \ - ADD_IDE_CMD | \ - ADD_FAT_CMD | \ - ADD_EXT2_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP | \ - CFG_CMD_BSP) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CONFIG_TIMESTAMP /* display image timestamps */ @@ -450,7 +424,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -469,6 +443,11 @@ #define CFG_HZ 1000 /* dec freq: 1ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, * which is normally part of the default commands (CFV_CMD_DFL) diff --git a/include/configs/BMW.h b/include/configs/BMW.h index 3bd43d83693..b062316a09b 100644 --- a/include/configs/BMW.h +++ b/include/configs/BMW.h @@ -64,28 +64,26 @@ #define CFG_DOC_SUPPORT_2000 1 #define CFG_DOC_SUPPORT_MILLENNIUM 1 #define CFG_DOC_SHORT_TIMEOUT 1 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DOC | \ - CFG_CMD_ELF | \ - 0 ) + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DOC +#define CONFIG_CMD_ELF + /* CFG_CMD_DOC required legacy NAND support */ #define CFG_NAND_LEGACY #if 0 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_DHCP | \ - CFG_CMD_PCI | CFG_CMD_DOC | CFG_CMD_DATE) - #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ #endif -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include - - /* * Miscellaneous configurable options */ @@ -293,7 +291,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From 49cf7e8ee7ef943fdfe866ce28410b0bfbf6a26c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Thu, 5 Jul 2007 19:52:35 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various C* named board config files. Signed-off-by: Jon Loeliger --- include/configs/CANBT.h | 20 +++++++++++-------- include/configs/CATcenter.h | 35 ++++++++++++++++++--------------- include/configs/CCM.h | 23 +++++++++++----------- include/configs/CMS700.h | 36 ++++++++++++++++++---------------- include/configs/CPC45.h | 39 +++++++++++++++++++------------------ include/configs/CPCI2DP.h | 26 ++++++++++++++----------- include/configs/CPCI405.h | 30 +++++++++++++++-------------- include/configs/CPCI4052.h | 40 ++++++++++++++++++++------------------ include/configs/CPCI405AB.h | 38 +++++++++++++++++++----------------- include/configs/CPCI405DT.h | 40 ++++++++++++++++++++------------------ include/configs/CPCI440.h | 39 ++++++++++++++----------------------- include/configs/CPCI750.h | 39 +++++++++++++++++++------------------ include/configs/CPCIISER4.h | 23 ++++++++++++---------- include/configs/CPU86.h | 31 ++++++++++++++++-------------- include/configs/CPU87.h | 37 ++++++++++++++++------------------- include/configs/CRAYL1.h | 47 +++++++++++++++++++++++---------------------- include/configs/CU824.h | 22 ++++++++++----------- 17 files changed, 291 insertions(+), 274 deletions(-) (limited to 'include') diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index e0262a8f674..8e09c527646 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -56,13 +56,17 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \ - CFG_CMD_IRQ | \ - CFG_CMD_EEPROM ) & \ - ~CFG_CMD_NET) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_EEPROM + +#undef CONFIG_CMD_NET + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -73,7 +77,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -173,7 +177,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index 7ec4599ebb5..33c8b1c2d7b 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -119,24 +119,27 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ @@ -155,7 +158,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -413,7 +416,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CCM.h b/include/configs/CCM.h index e8994ffef79..199b01f0cc8 100644 --- a/include/configs/CCM.h +++ b/include/configs/CCM.h @@ -96,25 +96,26 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_EEPROM | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP -/*----------------------------------------------------------------------*/ /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 1cca2859f4b..2d1280ffe07 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -65,21 +65,23 @@ CONFIG_BOOTP_DNS2 | \ CONFIG_BOOTP_SEND_HOSTNAME ) -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_BSP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_NAND | \ - CFG_CMD_I2C | \ - CFG_CMD_DATE | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_BSP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_NAND +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DATE +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM + #define CFG_NAND_LEGACY @@ -100,7 +102,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -289,7 +291,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h index b882f7a9bfe..c1aec62fb39 100644 --- a/include/configs/CPC45.h +++ b/include/configs/CPC45.h @@ -56,25 +56,26 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FAT | \ - CFG_CMD_FLASH | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + +/* + * Command line configuration. */ -#include +#include + +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP /* @@ -325,7 +326,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 56fd9a6d356..def2646cc20 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -54,16 +54,20 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_BSP +#define CONFIG_CMD_EEPROM + +#undef CONFIG_CMD_NET -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -80,7 +84,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -216,7 +220,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 9acde1e6f03..f49eb4b6ddb 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -65,24 +65,26 @@ CONFIG_BOOTP_DNS2 | \ CONFIG_BOOTP_SEND_HOSTNAME ) -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_EEPROM ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MII +#define CONFIG_CMD_EEPROM + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #define CFG_NAND_LEGACY #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -100,7 +102,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -264,7 +266,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 3fc99c50244..b88b029aa01 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -69,20 +69,25 @@ CONFIG_BOOTP_DNS2 | \ CONFIG_BOOTP_SEND_HOSTNAME ) -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_BSP +#define CONFIG_CMD_EEPROM + #if 0 /* test-only */ #define CONFIG_NETCONSOLE @@ -102,9 +107,6 @@ #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ #endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #define CFG_NAND_LEGACY #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -122,7 +124,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -316,7 +318,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 4e2e1a834d8..94faeed105d 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -69,28 +69,30 @@ CONFIG_BOOTP_DNS2 | \ CONFIG_BOOTP_SEND_HOSTNAME ) -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #define CFG_NAND_LEGACY @@ -109,7 +111,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -288,7 +290,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index ab302df7437..81528eae524 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -68,20 +68,25 @@ CONFIG_BOOTP_DNS2 | \ CONFIG_BOOTP_SEND_HOSTNAME ) -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_BSP +#define CONFIG_CMD_EEPROM + #if 0 /* test-only */ #define CONFIG_NETCONSOLE @@ -99,9 +104,6 @@ #undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #define CFG_NAND_LEGACY #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -119,7 +121,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -318,7 +320,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h index 7b5f72836e6..73b3e8a6ebe 100644 --- a/include/configs/CPCI440.h +++ b/include/configs/CPCI440.h @@ -172,29 +172,18 @@ #define CONFIG_PHY_ADDR 1 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#if 0 /* test-only */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_KGDB | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF ) -#else -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM ) -/* test-only: support fehlt bisher... */ -/* CFG_CMD_IDE | \*/ -/* CFG_CMD_PCI | \*/ -#endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -205,7 +194,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -269,7 +258,7 @@ */ #define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -291,7 +280,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index bc23fc02788..000aaa55ee8 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -137,25 +137,26 @@ CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C \ - | CFG_CMD_CACHE \ - | CFG_CMD_EEPROM \ - | CFG_CMD_PCI \ - | CFG_CMD_ELF \ - | CFG_CMD_DATE \ - | CFG_CMD_NET \ - | CFG_CMD_PING \ - | CFG_CMD_IDE \ - | CFG_CMD_FAT \ - | CFG_CMD_EXT2 \ - ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_PCI +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 -#define CONFIG_DOS_PARTITION -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_DOS_PARTITION #define CONFIG_USE_CPCIDVI @@ -179,7 +180,7 @@ #define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -585,7 +586,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index 93d49f3862d..e0b4d8c178e 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -54,15 +54,18 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -73,7 +76,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -189,7 +192,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index 16a9ea5dd71..631c78e6ee8 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -165,25 +165,28 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DOC +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -348,7 +351,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h index ce969ecdd18..666cb1307d4 100644 --- a/include/configs/CPU87.h +++ b/include/configs/CPU87.h @@ -169,25 +169,22 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DOC +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C + #ifdef CONFIG_PCI -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_PCI) -#else /* ! PCI */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C ) -#endif /* CONFIG_PCI */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + #define CONFIG_CMD_PCI +#endif + #define CFG_NAND_LEGACY @@ -196,7 +193,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -369,7 +366,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index 63d7a924043..627c0c82014 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -75,26 +75,30 @@ #define CONFIG_AUTOSCRIPT 1 -#define CONFIG_COMMANDS (\ - CFG_CMD_BDI|\ - CFG_CMD_IMI|\ - CFG_CMD_FLASH|\ - CFG_CMD_MEMORY|\ - CFG_CMD_NET|\ - CFG_CMD_ENV|\ - CFG_CMD_CONSOLE|\ - CFG_CMD_ASKENV|\ - CFG_CMD_ECHO|\ - CFG_CMD_IMMAP|\ - CFG_CMD_REGINFO|\ - CFG_CMD_DHCP|\ - CFG_CMD_DATE|\ - CFG_CMD_RUN|\ - CFG_CMD_I2C|\ - CFG_CMD_EEPROM|\ - CFG_CMD_DIAG|\ - CFG_CMD_AUTOSCRIPT|\ - CFG_CMD_SETGETDCR) +/* + * Command line configuration. + */ + +#define CONFIG_CMD_BDI +#define CONFIG_CMD_IMI +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_ENV +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_RUN +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_SETGETDCR + /* * optional BOOTP / DHCP fields @@ -123,9 +127,6 @@ #define CFG_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ diff --git a/include/configs/CU824.h b/include/configs/CU824.h index acc84847178..1c2033515e2 100644 --- a/include/configs/CU824.h +++ b/include/configs/CU824.h @@ -59,17 +59,17 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - 0 /* CFG_CMD_DATE */ | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) + +/* + * Command line configuration. */ -#include +#include + +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP /* @@ -278,7 +278,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From 3c3227f3c737502311b25b72084573901cbbf17d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sat, 7 Jul 2007 20:40:43 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various D* named board config files. Signed-off-by: Jon Loeliger --- include/configs/DASA_SIM.h | 26 ++++++---------- include/configs/DB64360.h | 29 ++++++++++-------- include/configs/DB64460.h | 29 ++++++++++-------- include/configs/DK1C20.h | 76 +++++++++++++++++++++++----------------------- include/configs/DK1S10.h | 73 ++++++++++++++++++++++---------------------- include/configs/DP405.h | 29 ++++++++++-------- include/configs/DU405.h | 29 ++++++++++-------- 7 files changed, 148 insertions(+), 143 deletions(-) (limited to 'include') diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h index 997e1baa9a7..b1638ce1a29 100644 --- a/include/configs/DASA_SIM.h +++ b/include/configs/DASA_SIM.h @@ -57,32 +57,26 @@ #define CONFIG_IPADDR 10.0.18.222 #define CONFIG_SERVERIP 10.0.18.190 -#if 0 -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_IRQ | \ - CFG_CMD_BSP | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ELF ) -#else -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP ) -#endif + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BSP + #if 0 /* Does not appear to be used?! If it is used, needs to be fixed */ #define CONFIG_SOFT_I2C /* Software I2C support enabled */ #endif #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -184,7 +178,7 @@ */ #define CFG_DCACHE_SIZE 2048 /* For PLX IOP480 */ #define CFG_CACHELINE_SIZE 16 /* For AMCC 401/403 CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h index bd7aff12cc1..f7e1c4da84f 100644 --- a/include/configs/DB64360.h +++ b/include/configs/DB64360.h @@ -239,17 +239,20 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" #define MTDPARTS_DEFAULT "mtdparts=db64360-1:-(jffs2)" */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C \ - | CFG_CMD_EEPROM \ - | CFG_CMD_CACHE \ - | CFG_CMD_JFFS2 \ - | CFG_CMD_PCI \ - | CFG_CMD_NET ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET + /* * Miscellaneous configurable options @@ -261,7 +264,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" /* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -558,7 +561,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h index 4b72e9b9e40..8cba0b26053 100644 --- a/include/configs/DB64460.h +++ b/include/configs/DB64460.h @@ -177,17 +177,20 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" #define MTDPARTS_DEFAULT "mtdparts=db64460-1:-(jffs2)" */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_I2C \ - | CFG_CMD_EEPROM \ - | CFG_CMD_CACHE \ - | CFG_CMD_JFFS2 \ - | CFG_CMD_PCI \ - | CFG_CMD_NET ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET + /* * Miscellaneous configurable options @@ -199,7 +202,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" /* #define CFG_GT_DUAL_CPU also for JTAG even with one cpu */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -496,7 +499,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h index b58846d8316..c3bd2cb8415 100644 --- a/include/configs/DK1C20.h +++ b/include/configs/DK1C20.h @@ -446,46 +446,46 @@ #define CONFIG_NIOS_ASMI /* Enable ASMI */ #define CFG_NIOS_ASMIBASE CFG_NIOS_CPU_ASMI0 /* ASMI base address */ -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_ASKENV | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_DOC | \ - CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_KGDB | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_MMC | \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_REISER | \ - CFG_CMD_SCSI | \ - CFG_CMD_SPI | \ - CFG_CMD_VFD | \ - CFG_CMD_USB | \ - CFG_CMD_XIMG ) ) - - -#include + +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_ASKENV +#undef CONFIG_CMD_BEDBUG +#undef CONFIG_CMD_BMP +#undef CONFIG_CMD_BSP +#undef CONFIG_CMD_CACHE +#undef CONFIG_CMD_DATE +#undef CONFIG_CMD_DOC +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_FDC +#undef CONFIG_CMD_FDOS +#undef CONFIG_CMD_HWFLOW +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_KGDB +#undef CONFIG_CMD_NAND +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_MMC +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_PCI +#undef CONFIG_CMD_PCMCIA +#undef CONFIG_CMD_REISER +#undef CONFIG_CMD_SCSI +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_VFD +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_XIMG + /*------------------------------------------------------------------------ * COMPACT FLASH *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_IDE) +#if defined(CONFIG_CMD_IDE) #define CONFIG_IDE_PREINIT /* Implement id_preinit */ #define CFG_IDE_MAXBUS 1 /* 1 IDE bus */ #define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ @@ -503,12 +503,12 @@ #define CFG_CF_POWER 0x009209c0 /* CF Power FET PIO base*/ #define CFG_CF_ATASEL 0x009209d0 /* CF ATASEL PIO base */ -#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ +#endif /*------------------------------------------------------------------------ * KGDB *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 9600 #endif diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h index 3e3803cd235..a5530a6c8dc 100644 --- a/include/configs/DK1S10.h +++ b/include/configs/DK1S10.h @@ -454,47 +454,46 @@ #endif /* CFG_NIOS_CPU_PIO_NUMS */ -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_ASKENV | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_DOC | \ - CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_IDE | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_KGDB | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_MMC | \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_SCSI | \ - CFG_CMD_SPI | \ - CFG_CMD_VFD | \ - CFG_CMD_USB | \ - CFG_CMD_XIMG ) ) - - -#include +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_ASKENV +#undef COND_CMD_BEDBUG +#undef COND_CMD_BMP +#undef COND_CMD_BSP +#undef COND_CMD_CACHE +#undef COND_CMD_DATE +#undef COND_CMD_DOC +#undef COND_CMD_DTT +#undef COND_CMD_EEPROM +#undef COND_CMD_ELF +#undef COND_CMD_FAT +#undef COND_CMD_FDC +#undef COND_CMD_FDOS +#undef COND_CMD_HWFLOW +#undef COND_CMD_IDE +#undef COND_CMD_I2C +#undef COND_CMD_JFFS2 +#undef COND_CMD_KGDB +#undef COND_CMD_NAND +#undef COND_CMD_NFS +#undef COND_CMD_MMC +#undef COND_CMD_MII +#undef COND_CMD_PCI +#undef COND_CMD_PCMCIA +#undef COND_CMD_SCSI +#undef COND_CMD_SPI +#undef COND_CMD_VFD +#undef COND_CMD_USB +#undef COND_CMD_XIMG + /*------------------------------------------------------------------------ * KGDB *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 9600 #endif diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 2ae794dc26c..b50d4f905b6 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -55,17 +55,20 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_DHCP | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -87,7 +90,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -235,7 +238,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/DU405.h b/include/configs/DU405.h index 5489a539360..2093b373644 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -58,21 +58,24 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_DATE | \ - CFG_CMD_EEPROM ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_IDE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE +#define CONFIG_CMD_EEPROM + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_MC146818 /* BQ3285 is MC146818 compatible*/ @@ -85,7 +88,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -225,7 +228,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From dcaa71562826a2466e894c868d132509dcda8444 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sat, 7 Jul 2007 20:56:05 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various E* named board config files. Signed-off-by: Jon Loeliger --- include/configs/EB+MCF-EV123.h | 13 ++++++++----- include/configs/ELPPC.h | 15 ++++++++++----- include/configs/ELPT860.h | 17 ++++++++++------- include/configs/EP1C20.h | 40 +++++++++++++++++++++------------------- include/configs/EP1S10.h | 39 ++++++++++++++++++++------------------- include/configs/EP1S40.h | 39 ++++++++++++++++++++------------------- include/configs/EP88x.h | 19 ++++++++++--------- include/configs/ERIC.h | 26 ++++++++++---------------- include/configs/ESTEEM192E.h | 7 +++++-- include/configs/ETX094.h | 12 ++++++++---- include/configs/EVB64260.h | 13 ++++++++----- include/configs/EXBITGEN.h | 12 +++++++----- 12 files changed, 137 insertions(+), 115 deletions(-) (limited to 'include') diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index 720b335b099..07f31d52c07 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -68,17 +68,20 @@ #define CFG_ENV_IS_IN_FLASH 1 #endif -/*#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB)) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_LOADB + #define CONFIG_BOOTDELAY 5 #define CFG_PROMPT "\nEV123 U-Boot> " #define CFG_LONGHELP /* undef to save memory */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h index 2c99b4b1628..b2191606159 100644 --- a/include/configs/ELPPC.h +++ b/include/configs/ELPPC.h @@ -68,10 +68,15 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_JFFS2 + /* * Miscellaneous configurable options @@ -84,7 +89,7 @@ */ #define CONFIG_CONS_INDEX 1 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -317,7 +322,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h index e73bcec4485..2a909f351b4 100644 --- a/include/configs/ELPT860.h +++ b/include/configs/ELPT860.h @@ -91,12 +91,15 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE + /* * Miscellaneous configurable options @@ -104,7 +107,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "LEOX_elpt860: " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -224,7 +227,7 @@ */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h index 5507f352b90..db133c64407 100644 --- a/include/configs/EP1C20.h +++ b/include/configs/EP1C20.h @@ -160,25 +160,27 @@ #define CONFIG_IPADDR 192.168.2.21 #define CONFIG_SERVERIP 192.168.2.16 -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IRQ | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_RUN | \ - CFG_CMD_SAVES ) -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES + +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_BOOTD +#undef CONFIG_CMD_CONSOLE +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_ITEST +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG + /*------------------------------------------------------------------------ * MISC diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h index 6eca9f23dc7..67a162d9d3a 100644 --- a/include/configs/EP1S10.h +++ b/include/configs/EP1S10.h @@ -154,25 +154,26 @@ #define CONFIG_IPADDR 192.168.2.21 #define CONFIG_SERVERIP 192.168.2.16 -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IRQ | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_RUN | \ - CFG_CMD_SAVES ) -#include + +/* + * Command line configuration. + */ +#define CONFIG_CMD_BDI +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVES + /*------------------------------------------------------------------------ * MISC diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h index 976e79acb6f..2363835b9f4 100644 --- a/include/configs/EP1S40.h +++ b/include/configs/EP1S40.h @@ -154,25 +154,26 @@ #define CONFIG_IPADDR 192.168.2.21 #define CONFIG_SERVERIP 192.168.2.16 -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IRQ | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_RUN | \ - CFG_CMD_SAVES ) -#include + +/* + * Command line configuration. + */ +#define CONFIG_CMD_BDI +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVES + /*------------------------------------------------------------------------ * MISC diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h index 738763b86ff..60a45086d65 100644 --- a/include/configs/EP88x.h +++ b/include/configs/EP88x.h @@ -50,15 +50,16 @@ #define CFG_8xx_CPUCLK_MIN 40000000 #define CFG_8xx_CPUCLK_MAX 133000000 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) - -/* This must be included AFTER the definition of CONFIG_COMMANDS */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm fe060000" /* Autoboot command */ diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index c203aea9245..2320747c36d 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -96,23 +96,17 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH) /* - * #define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | \ - * CFG_CMD_KGDB | CFG_CMD_I2C | CFG_CMD_EEPROM | \ - * CFG_CMD_ENV | CFG_CMD_FLASH) + * Command line configuration. */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH -/* CFG_CMD_ENV est definie */ -/* ((CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_KGDB) & ~(CFG_CMD_ENV)) - */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -121,7 +115,7 @@ */ #undef CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -325,7 +319,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -365,7 +359,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h index b176c6f37e9..06d4f344e76 100644 --- a/include/configs/ESTEEM192E.h +++ b/include/configs/ESTEEM192E.h @@ -72,8 +72,11 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "BOOT: " /* Monitor Command Prompt */ diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h index d55eb7d192e..2193918a9ef 100644 --- a/include/configs/ETX094.h +++ b/include/configs/ETX094.h @@ -84,15 +84,19 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -179,7 +183,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h index 78e57168854..c78bbfa61b1 100644 --- a/include/configs/EVB64260.h +++ b/include/configs/EVB64260.h @@ -107,17 +107,20 @@ CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ASKENV) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -391,7 +394,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h index d85be424a2a..fdbf1258229 100644 --- a/include/configs/EXBITGEN.h +++ b/include/configs/EXBITGEN.h @@ -82,10 +82,12 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -94,7 +96,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -206,7 +208,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif -- cgit v1.3.1 From 60a0876b5106b34220e459c208bbf648073306c0 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sat, 7 Jul 2007 21:04:26 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various F* and G* named board config files. Signed-off-by: Jon Loeliger --- include/configs/FADS823.h | 11 ++++++---- include/configs/FADS850SAR.h | 12 +++++++---- include/configs/FLAGADM.h | 24 +++++++++++++++------- include/configs/FPS850L.h | 23 ++++++++++++--------- include/configs/FPS860L.h | 22 +++++++++++--------- include/configs/G2000.h | 35 +++++++++++++++++--------------- include/configs/GEN860T.h | 48 +++++++++++++++++++------------------------- include/configs/GENIETV.h | 12 +++++++---- include/configs/GTH.h | 17 ++++++++++------ 9 files changed, 116 insertions(+), 88 deletions(-) (limited to 'include') diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h index 1b562d60635..7857cf18c6d 100644 --- a/include/configs/FADS823.h +++ b/include/configs/FADS823.h @@ -107,15 +107,18 @@ #define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT ":>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -190,7 +193,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h index 2a986f07680..c2238c9a96c 100644 --- a/include/configs/FADS850SAR.h +++ b/include/configs/FADS850SAR.h @@ -61,15 +61,19 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + /* * Miscellaneous configurable options */ #undef CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT ":>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -148,7 +152,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h index 8babee140f9..af31f700e21 100644 --- a/include/configs/FLAGADM.h +++ b/include/configs/FLAGADM.h @@ -64,19 +64,29 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CFG_CMD_BDI | CFG_CMD_IMI | CFG_CMD_CACHE | \ - CFG_CMD_MEMORY | CFG_CMD_FLASH | CFG_CMD_LOADB | CFG_CMD_LOADS | \ - CFG_CMD_ENV | CFG_CMD_REGINFO | CFG_CMD_IMMAP | CFG_CMD_NET) +/* + * Command line configuration. + */ + +#define CONFIG_CMD_BDI +#define CONFIG_CMD_IMI +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_ENV +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_NET -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "EEG> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -152,7 +162,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h index 0dd21bc618c..12956939b00 100644 --- a/include/configs/FPS850L.h +++ b/include/configs/FPS850L.h @@ -62,22 +62,25 @@ #define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~( \ - CFG_CMD_CONSOLE | \ - CFG_CMD_BDI | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_CACHE ) ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_CONSOLE +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_CACHE + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -160,7 +163,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h index 423d74ea07a..d97151fa61e 100644 --- a/include/configs/FPS860L.h +++ b/include/configs/FPS860L.h @@ -62,22 +62,24 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -160,7 +162,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/G2000.h b/include/configs/G2000.h index db42fd06fe5..24eff02ac66 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -88,20 +88,23 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ #endif -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_BSP +#define CONFIG_CMD_EEPROM + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -120,7 +123,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -324,7 +327,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index 6613f90a770..612b661ad22 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -228,31 +228,30 @@ #define CFG_CMD_POST_DIAG 0 #endif + /* - * List of available monitor commands. Use the system default list - * plus add some of the "non-standard" commands back in. - * See ./cmd_confdefs.h - */ -#define BASE_CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_FPGA | \ - CFG_CMD_MII | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_POST_DIAG ) + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_MII +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_POST_DIAG #if !defined(CONFIG_SC) -#define CONFIG_COMMANDS ( BASE_CONFIG_COMMANDS | CFG_CMD_DOC ) -#else -#define CONFIG_COMMANDS BASE_CONFIG_COMMANDS + #define CONFIG_CMD_DOC #endif + /* * There is no IDE/PCMCIA hardware support on the board. */ @@ -279,11 +278,6 @@ #define CFG_FPGA_PROG_FEEDBACK -/************************************************************************ - * This must be included AFTER the definition of any CONFIG_COMMANDS - */ -#include - #define CFG_NAND_LEGACY /* @@ -306,7 +300,7 @@ /* * Set buffer size for console I/O */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 #else #define CFG_CBSIZE 256 @@ -471,7 +465,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of above value */ #endif diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h index 8c01d97fa33..67525db3312 100644 --- a/include/configs/GENIETV.h +++ b/include/configs/GENIETV.h @@ -105,15 +105,19 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT ":>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -193,7 +197,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/GTH.h b/include/configs/GTH.h index 03b96594979..f398bad79a0 100644 --- a/include/configs/GTH.h +++ b/include/configs/GTH.h @@ -97,18 +97,23 @@ #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured #endif -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_IDE + + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ #define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -190,7 +195,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From 6c4f4da9bfc9f9403f54fce678ed0364b7c86a6a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sun, 8 Jul 2007 10:09:35 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various H* named board config files. Signed-off-by: Jon Loeliger --- include/configs/HH405.h | 42 +++++++++++++++++++++-------------------- include/configs/HIDDEN_DRAGON.h | 22 +++++++++++---------- include/configs/HMI10.h | 42 ++++++++++++++++++----------------------- include/configs/HUB405.h | 31 ++++++++++++++++-------------- 4 files changed, 69 insertions(+), 68 deletions(-) (limited to 'include') diff --git a/include/configs/HH405.h b/include/configs/HH405.h index dc40ebc861d..58f29cd6667 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -103,21 +103,26 @@ #define ADD_BMP_CMD 0 #endif /* CONFIG_VIDEO */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_EXT2 | \ - CFG_CMD_ELF | \ - CFG_CMD_NAND | \ - CFG_CMD_I2C | \ - CFG_CMD_DATE | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - ADD_BMP_CMD | \ - CFG_CMD_EEPROM ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_ELF +#define CONFIG_CMD_NAND +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DATE +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_BMP_CMD +#define CONFIG_CMD_EEPROM + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -127,9 +132,6 @@ #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ #undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #define CFG_NAND_LEGACY #undef CONFIG_BZIP2 /* include support for bzip2 compressed images */ @@ -148,7 +150,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -377,7 +379,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h index 68647407733..972ca0884f2 100644 --- a/include/configs/HIDDEN_DRAGON.h +++ b/include/configs/HIDDEN_DRAGON.h @@ -52,16 +52,18 @@ #define CONFIG_BAUDRATE 9600 #define CONFIG_DRAM_SPEED 100 /* MHz */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_NET | \ - CFG_CMD_PCI | \ - CFG_CMD_PING ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING /* * Miscellaneous configurable options @@ -363,7 +365,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h index 7cce876924e..29748e1fd53 100644 --- a/include/configs/HMI10.h +++ b/include/configs/HMI10.h @@ -125,31 +125,25 @@ #define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + #ifdef CONFIG_SPLASH_SCREEN -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BMP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#else -# define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) + #define CONFIG_CMD_BMP #endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options @@ -164,7 +158,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -247,7 +241,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index f84e356216b..d29bddbe1ca 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -60,18 +60,21 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_NAND | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_NAND +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -88,7 +91,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -271,7 +274,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From 348f258f24253433e4a2302a0bbceb6740a67246 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sun, 8 Jul 2007 13:46:18 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various [IJKL]* named board config files. Signed-off-by: Jon Loeliger --- include/configs/IAD210.h | 19 ++++++---- include/configs/ICU862.h | 31 +++++++++------- include/configs/IDS8247.h | 27 ++++++++------ include/configs/IP860.h | 26 ++++++------- include/configs/IPHASE4539.h | 13 ++++--- include/configs/ISPAN.h | 24 ++++++------ include/configs/IVML24.h | 19 ++++++---- include/configs/IVMS8.h | 18 +++++---- include/configs/IceCube.h | 38 +++++++++---------- include/configs/JSE.h | 37 ++++++++++--------- include/configs/KAREF.h | 46 +++++++++++------------ include/configs/KUP4K.h | 29 ++++++++------- include/configs/KUP4X.h | 33 +++++++++-------- include/configs/LANTEC.h | 88 +++++++++++++++++++++----------------------- 14 files changed, 233 insertions(+), 215 deletions(-) (limited to 'include') diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h index 35d84aedf8a..59ea919be70 100644 --- a/include/configs/IAD210.h +++ b/include/configs/IAD210.h @@ -123,20 +123,23 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DATE + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -217,7 +220,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h index cd17935893f..9750c8718fe 100644 --- a/include/configs/ICU862.h +++ b/include/configs/ICU862.h @@ -123,25 +123,28 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -228,7 +231,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 29eb874dbf0..45a96ae787d 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -161,22 +161,25 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_NFS | \ - CFG_CMD_NAND | \ - CFG_CMD_I2C | \ - CFG_CMD_SNTP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_I2C +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -234,7 +237,7 @@ * NAND-FLASH stuff *----------------------------------------------------------------------- */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CONFIG_CMD_NAND) #define CFG_NAND_LEGACY #define CFG_NAND0_BASE 0xE1000000 @@ -355,7 +358,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -474,7 +477,7 @@ #define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH_SIZE) |\ ORxG_SCY_6_CLK ) -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CONFIG_CMD_NAND) /* Bank 1 - NAND Flash */ #define CFG_NAND_BASE CFG_NAND0_BASE diff --git a/include/configs/IP860.h b/include/configs/IP860.h index 0e20e567634..07c7955d14d 100644 --- a/include/configs/IP860.h +++ b/include/configs/IP860.h @@ -88,28 +88,26 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT - -/*----------------------------------------------------------------------*/ +/* + * Command line configuration. + */ +#include -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP -/*----------------------------------------------------------------------*/ +#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -202,7 +200,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h index c1565fc037c..383ffe2e23f 100644 --- a/include/configs/IPHASE4539.h +++ b/include/configs/IPHASE4539.h @@ -124,17 +124,18 @@ #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ #endif /* CONFIG_SOFT_I2C */ -#define CONFIG_COMMANDS CONFIG_CMD_DFL -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/ram rw" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -149,7 +150,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -257,7 +258,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h index 706bdb94f57..75dea18f571 100644 --- a/include/configs/ISPAN.h +++ b/include/configs/ISPAN.h @@ -106,17 +106,19 @@ #define CONFIG_8260_CLKIN 65536000 /* in Hz */ #define CONFIG_BAUDRATE 38400 -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - | CFG_CMD_REGINFO \ - ) - -/* This must be included AFTER the definition of CONFIG_COMMANDS */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO + #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */ diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h index a0cb1dd484b..313f8d8b2d1 100644 --- a/include/configs/IVML24.h +++ b/include/configs/IVML24.h @@ -72,24 +72,27 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_IDE + + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_BOOTP_MASK \ ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/*----------------------------------------------------------------------*/ - /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -182,7 +185,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h index 46b4d535462..7633679544a 100644 --- a/include/configs/IVMS8.h +++ b/include/configs/IVMS8.h @@ -72,24 +72,26 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_IDE) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_IDE + + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_BOOTP_MASK \ ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - -/*----------------------------------------------------------------------*/ - /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -179,7 +181,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 73be06950bc..c80c2d4ad3c 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -37,11 +37,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -103,21 +98,21 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP | \ - ADD_PCI_CMD | \ - ADD_USB_CMD ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP +#define CONFIG_PCI_CMD +#define CONFIG_USB_CMD + #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ # define CFG_LOWBOOT 1 @@ -312,7 +307,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -328,6 +323,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Various low-level settings */ diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 7fa9ed2d42a..c67c063e8bf 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -135,20 +135,23 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_FLASH | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_PCI | \ - CFG_CMD_PING ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + /* watchdog disabled */ #undef CONFIG_WATCHDOG @@ -167,7 +170,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -272,7 +275,7 @@ */ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405GPr CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -298,7 +301,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 48b94ee45ec..f0368049d1d 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -178,23 +178,25 @@ #define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ -/*----------------------------------------------------------------------- - * Console/Commands/Parser - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_PING | \ - CFG_CMD_DIAG | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_ELF | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_PING +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT + /* Include NetConsole support */ #define CONFIG_NETCONSOLE @@ -203,10 +205,6 @@ #define CONFIG_AUTO_COMPLETE 1 #define CFG_ALT_MEMTEST 1 /* use real memory test */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "KaRefDes=> " /* Monitor Command Prompt */ @@ -217,7 +215,7 @@ /*----------------------------------------------------------------------- * Console Buffer *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -279,7 +277,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ #endif @@ -291,7 +289,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ #define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */ #endif diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h index 9b950fc5d16..24222017659 100644 --- a/include/configs/KUP4K.h +++ b/include/configs/KUP4K.h @@ -164,24 +164,27 @@ #endif #endif -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_POST_DIAG +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -269,7 +272,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h index cd38b0f2c2f..184338b97d2 100644 --- a/include/configs/KUP4X.h +++ b/include/configs/KUP4X.h @@ -175,26 +175,29 @@ #endif #endif -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_POST_DIAG | \ - CFG_CMD_SNTP | \ - CFG_CMD_USB ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_POST_DIAG +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_USB + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -281,7 +284,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h index e44f1cc627a..089fb9df871 100644 --- a/include/configs/LANTEC.h +++ b/include/configs/LANTEC.h @@ -76,62 +76,58 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_CMD_MINIMAL 0 -#define CONFIG_CMD_TINY (CFG_CMD_FLASH | \ - CFG_CMD_MEMORY | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB) -#define CONFIG_CMD_NORMAL (CONFIG_CMD_DFL & ~CFG_CMD_BOOTD & ~CFG_CMD_REISER) -#define CONFIG_CMD_GDB (CONFIG_CMD_NORMAL | CFG_CMD_KGDB) -#define CONFIG_CMD_FULL (CFG_CMD_ALL & ~CFG_CMD_BEDBUG \ - & ~CFG_CMD_BMP \ - & ~CFG_CMD_BSP \ - & ~CFG_CMD_DISPLAY \ - & ~CFG_CMD_DOC \ - & ~CFG_CMD_DTT \ - & ~CFG_CMD_EEPROM \ - & ~CFG_CMD_ELF \ - & ~CFG_CMD_EXT2 \ - & ~CFG_CMD_FDC \ - & ~CFG_CMD_FDOS \ - & ~CFG_CMD_HWFLOW \ - & ~CFG_CMD_I2C \ - & ~CFG_CMD_IDE \ - & ~CFG_CMD_IRQ \ - & ~CFG_CMD_JFFS2 \ - & ~CFG_CMD_KGDB \ - & ~CFG_CMD_MII \ - & ~CFG_CMD_MMC \ - & ~CFG_CMD_NAND \ - & ~CFG_CMD_PCI \ - & ~CFG_CMD_PCMCIA \ - & ~CFG_CMD_REISER \ - & ~CFG_CMD_SCSI \ - & ~CFG_CMD_SPI \ - & ~CFG_CMD_UNIVERSE\ - & ~CFG_CMD_USB \ - & ~CFG_CMD_VFD \ - & ~CFG_CMD_XIMG ) -#if CONFIG_LANTEC >= 2 -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_BEDBUG +#undef CONFIG_CMD_BMP +#undef CONFIG_CMD_BSP +#undef CONFIG_CMD_DISPLAY +#undef CONFIG_CMD_DOC +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_EEPROM +#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_EXT2 +#undef CONFIG_CMD_FDC +#undef CONFIG_CMD_FDOS +#undef CONFIG_CMD_HWFLOW +#undef CONFIG_CMD_I2C +#undef CONFIG_CMD_IDE +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_KGDB +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_MMC +#undef CONFIG_CMD_NAND +#undef CONFIG_CMD_PCI +#undef CONFIG_CMD_PCMCIA +#undef CONFIG_CMD_REISER +#undef CONFIG_CMD_SCSI +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_UNIVERSE +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_VFD +#undef CONFIG_CMD_XIMG + +#if !(CONFIG_LANTEC >= 2) + #undef CONFIG_CMD_DATE + #undef CONFIG_CMD_NET #endif + #if CONFIG_LANTEC >= 2 -# define CONFIG_COMMANDS CONFIG_CMD_FULL -#else -# define CONFIG_COMMANDS (CONFIG_CMD_FULL & ~CFG_CMD_DATE & ~CFG_CMD_NET) +#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ #endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -203,7 +199,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From 8353e139bfad9059c54f5b2421f1a3090e15a2e2 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sun, 8 Jul 2007 14:14:17 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various M* named board config files. Signed-off-by: Jon Loeliger --- include/configs/M5271EVB.h | 15 ++++++++--- include/configs/M5272C3.h | 17 ++++++++---- include/configs/M5282EVB.h | 13 +++++++--- include/configs/MBX.h | 19 +++++++++----- include/configs/MBX860T.h | 2 +- include/configs/METROBOX.h | 48 +++++++++++++++------------------- include/configs/MHPC.h | 27 +++++++++++--------- include/configs/MIP405.h | 61 ++++++++++++++++++++------------------------ include/configs/ML2.h | 36 ++++++++++++++------------ include/configs/MOUSSE.h | 16 +++++++++--- include/configs/MPC8260ADS.h | 4 +-- include/configs/MUSENKI.h | 10 ++++---- include/configs/MVBLUE.h | 25 +++++++++++++----- include/configs/MVS1.h | 33 ++++++++++++------------ 14 files changed, 181 insertions(+), 145 deletions(-) (limited to 'include') diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index f0fc0134341..1907a3c4396 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -65,15 +65,22 @@ #define CFG_ENV_IS_IN_FLASH 1 #endif -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_NET ) & ~(CFG_CMD_LOADS | CFG_CMD_LOADB)) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PING +#define CONFIG_CMD_NET + +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_LOADB -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CFG_PROMPT "=> " #define CFG_LONGHELP /* undef to save memory */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 5fd6a95c4d1..417166524f6 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -60,17 +60,24 @@ #define CFG_ENV_IS_IN_FLASH 1 #endif -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) | \ - CFG_CMD_MII) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_MII + +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_LOADB + + #define CONFIG_BOOTDELAY 5 #define CFG_PROMPT "-> " #define CFG_LONGHELP /* undef to save memory */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index cbb3e3bb9f9..cf3076efc59 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -51,16 +51,21 @@ #define CFG_ENV_IS_IN_FLASH 1 -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_LOADB + -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CONFIG_BOOTDELAY 5 #define CFG_PROMPT "-> " #define CFG_LONGHELP /* undef to save memory */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/MBX.h b/include/configs/MBX.h index d6e3fb8de9b..ae8913ca86a 100644 --- a/include/configs/MBX.h +++ b/include/configs/MBX.h @@ -71,13 +71,18 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_COMMANDS ( CFG_CMD_NET | CONFIG_CMD_DFL | CFG_CMD_SDRAM | \ - CFG_CMD_PCMCIA | CFG_CMD_IDE ) -#define CONFIG_DOS_PARTITION +/* + * Command line configuration. + */ +#define CONFIG_CMD_NET +#define CONFIG_CMD_DFL +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_PCMCIA +#define CONFIG_CMD_IDE -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +#define CONFIG_DOS_PARTITION /* * Miscellaneous configurable options @@ -88,7 +93,7 @@ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -187,7 +192,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/MBX860T.h b/include/configs/MBX860T.h index 0ca0970075c..69d195dc028 100644 --- a/include/configs/MBX860T.h +++ b/include/configs/MBX860T.h @@ -151,7 +151,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 7aae2bd1437..e9aaedb8181 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -242,26 +242,24 @@ #define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ -/*----------------------------------------------------------------------- - * Console/Commands/Parser - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_PING | \ - CFG_CMD_DIAG | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_ELF | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT) - -/* tbs 09-March-2005 Removed to be able to use 2nd serial */ -/* CFG_CMD_KGDB | \ */ +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_PING +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT /* Include NetConsole support */ @@ -272,10 +270,6 @@ #define CONFIG_AUTO_COMPLETE 1 #define CFG_ALT_MEMTEST 1 /* use real memory test */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "MetroBox=> " /* Monitor Command Prompt */ @@ -286,7 +280,7 @@ /*----------------------------------------------------------------------- * Console Buffer *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -348,7 +342,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above */ #endif @@ -360,7 +354,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal PowerOn: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port baud */ #define CONFIG_KGDB_SER_INDEX 2 /* kgdb serial port */ #endif diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h index 53684ca6b57..a8dd36d9e05 100644 --- a/include/configs/MHPC.h +++ b/include/configs/MHPC.h @@ -115,25 +115,28 @@ #define CONFIG_BR0_WORKAROUND 1 -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_REGINFO ) -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * Command line configuration. + */ +#include -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_CMD_DATE +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_REGINFO + + +#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -225,7 +228,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 7e57a0fae14..192998e7956 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -50,41 +50,34 @@ ***********************************************************/ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ -/*********************************************************** - * Command definitions - ***********************************************************/ -#define MIP405_COMMON_CMDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SAVES | \ - CFG_CMD_BSP ) -#if defined(CONFIG_MIP405T) -#define CONFIG_COMMANDS \ - MIP405_COMMON_CMDS -#else -#define CONFIG_COMMANDS \ - (MIP405_COMMON_CMDS | \ - CFG_CMD_USB | \ - CFG_CMD_DOC ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_BSP +#if !defined(CONFIG_MIP405T) + #define CONFIG_CMD_USB + #define CONFIG_CMD_DOC #endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CFG_NAND_LEGACY @@ -165,7 +158,7 @@ **********************************************************/ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -260,7 +253,7 @@ */ #define CFG_DCACHE_SIZE 0x4000 /* For AMCC 405GPr CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -426,7 +419,7 @@ /************************************************************ * Debug support ************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/ML2.h b/include/configs/ML2.h index d8805ea5a70..8d61d4861e7 100644 --- a/include/configs/ML2.h +++ b/include/configs/ML2.h @@ -76,20 +76,22 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & \ - ~( CFG_CMD_NET | \ - CFG_CMD_RTC | \ - CFG_CMD_PCI | \ - CFG_CMD_I2C \ - ) ) | \ - CFG_CMD_IRQ | \ - CFG_CMD_KGDB | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_ELF | \ - CFG_CMD_JFFS2 ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_KGDB +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_ELF +#define CONFIG_CMD_JFFS2 + +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_RTC +#undef CONFIG_CMD_PCI +#undef CONFIG_CMD_I2C + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -102,7 +104,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -195,7 +197,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -236,7 +238,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h index 6ad2feb28e7..518bf1213ee 100644 --- a/include/configs/MOUSSE.h +++ b/include/configs/MOUSSE.h @@ -58,14 +58,22 @@ #endif #define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138" #define CONFIG_BOOTDELAY 3 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL|CFG_CMD_ASKENV|CFG_CMD_DATE) + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE + + #define CONFIG_ENV_OVERWRITE 1 #define CONFIG_ETH_ADDR "00:10:18:10:00:06" #define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */ -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include + #include "../board/mousse/mousse.h" /* diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 69d4c28f03d..b41866fcf57 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -250,7 +250,7 @@ #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/mtdblock2" -#if defined(CONFIG_CMD_KGDB) || (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -268,7 +268,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) || (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h index da52e0ec0b8..d6dafb2c8e2 100644 --- a/include/configs/MUSENKI.h +++ b/include/configs/MUSENKI.h @@ -52,11 +52,11 @@ #define CONFIG_BOOTDELAY 5 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ - -#include +/* + * Command line configuration. + */ +#include /* @@ -280,7 +280,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h index 88eefa19074..bea8cb196b4 100644 --- a/include/configs/MVBLUE.h +++ b/include/configs/MVBLUE.h @@ -76,15 +76,26 @@ #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_RESET_TO_RETRY 60 -#define CONFIG_COMMANDS ( CFG_CMD_ASKENV | CFG_CMD_BOOTD | CFG_CMD_CACHE | CFG_CMD_DHCP | \ - CFG_CMD_ECHO | CFG_CMD_ENV | CFG_CMD_FLASH | CFG_CMD_IMI | \ - CFG_CMD_IRQ | CFG_CMD_NET | CFG_CMD_PCI | CFG_CMD_RUN ) +/* + * Command line configuration. + */ -#define CONFIG_BOOTP_MASK ( 0xffffffff ) +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_RUN -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +#define CONFIG_BOOTP_MASK ( 0xffffffff ) /* * Miscellaneous configurable options @@ -310,7 +321,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h index 5995918266d..709ee86ab28 100644 --- a/include/configs/MVS1.h +++ b/include/configs/MVS1.h @@ -70,20 +70,21 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -/* MVsensor uses a really minimal U-Boot ! */ -#define CONFIG_COMMANDS (CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_IMI | \ - CFG_CMD_FLASH | \ - CFG_CMD_MEMORY | \ - CFG_CMD_NET | \ - CFG_CMD_DHCP | \ - CFG_CMD_ENV | \ - CFG_CMD_BOOTD | \ - CFG_CMD_RUN ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_IMI +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_RUN + /* * Miscellaneous configurable options @@ -96,7 +97,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -172,7 +173,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From e18a1061a8630cb67995fdf99afd3fb50d1b187d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sun, 8 Jul 2007 14:21:43 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various [NO]* named board config files. Signed-off-by: Jon Loeliger --- include/configs/NC650.h | 31 +++++++++++++++++-------------- include/configs/NETPHONE.h | 26 ++++++++++++++------------ include/configs/NETTA.h | 38 ++++++++++++++++++++------------------ include/configs/NETTA2.h | 26 ++++++++++++++------------ include/configs/NETVIA.h | 23 ++++++++++++----------- include/configs/NSCU.h | 25 ++++++++++++++----------- include/configs/NX823.h | 17 +++++++++++------ include/configs/OCRTC.h | 27 +++++++++++++++------------ include/configs/ORSG.h | 27 +++++++++++++++------------ include/configs/OXC.h | 12 ++++++++---- 10 files changed, 140 insertions(+), 112 deletions(-) (limited to 'include') diff --git a/include/configs/NC650.h b/include/configs/NC650.h index a12c8da13ec..221fce92598 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -134,25 +134,28 @@ #define CONFIG_RTC_PCF8563 #define CFG_I2C_RTC_ADDR 0x51 -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_NAND | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NAND +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -230,7 +233,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h index 444f721cc85..cfca8114d73 100644 --- a/include/configs/NETPHONE.h +++ b/include/configs/NETPHONE.h @@ -105,20 +105,22 @@ #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_NAND | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_MII | \ - CFG_CMD_CDP \ - ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_CMD_CDP + #define CONFIG_BOARD_EARLY_INIT_F 1 #define CONFIG_MISC_INIT_R -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ @@ -128,7 +130,7 @@ #define CFG_HUSH_PARSER 1 #define CFG_PROMPT_HUSH_PS2 "> " -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -220,7 +222,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 25b63457c74..e2e8803394e 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -111,26 +111,28 @@ CFG_POST_CODEC | \ CFG_POST_DSP ) -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_CDP | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_FAT | \ - CFG_CMD_IDE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_PING | \ - 0) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_CDP +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCMCIA +#define CONFIG_CMD_PING + #define CONFIG_BOARD_EARLY_INIT_F 1 #define CONFIG_MISC_INIT_R -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ @@ -140,7 +142,7 @@ #define CFG_HUSH_PARSER 1 #define CFG_PROMPT_HUSH_PS2 "> " -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -223,7 +225,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index e20e72495cc..ac8e4815d37 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -105,20 +105,22 @@ #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_NAND | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_MII | \ - CFG_CMD_CDP \ - ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_CMD_CDP + #define CONFIG_BOARD_EARLY_INIT_F 1 #define CONFIG_MISC_INIT_R -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ @@ -128,7 +130,7 @@ #define CFG_HUSH_PARSER 1 #define CFG_PROMPT_HUSH_PS2 "> " -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -220,7 +222,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index e30be0987aa..fa91306a6c4 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -88,28 +88,29 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS_BASE ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING #if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2 -#define CONFIG_COMMANDS (CONFIG_COMMANDS_BASE | CFG_CMD_NAND) -#else -#define CONFIG_COMMANDS CONFIG_COMMANDS_BASE +#define CONFIG_CMD_NAND #endif + #define CONFIG_BOARD_EARLY_INIT_F 1 #define CONFIG_MISC_INIT_R -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -192,7 +193,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h index d994420096b..0edfebf9e9f 100644 --- a/include/configs/NSCU.h +++ b/include/configs/NSCU.h @@ -93,16 +93,19 @@ #define CONFIG_ISP1362_USB /* ISP1362 USB OTG controller */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options @@ -117,7 +120,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -201,7 +204,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/NX823.h b/include/configs/NX823.h index 1cb8b8ff3b5..527bd9d6a95 100644 --- a/include/configs/NX823.h +++ b/include/configs/NX823.h @@ -56,21 +56,26 @@ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled, for now */ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_AUTOSCRIPT) #define CONFIG_AUTOSCRIPT + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_AUTOSCRIPT + + /* call various generic functions */ #define CONFIG_MISC_INIT_R -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -152,7 +157,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index aa9d1ba735a..00f747ef431 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -54,20 +54,23 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ELF | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_ELF +#define CONFIG_CMD_BSP +#define CONFIG_CMD_EEPROM + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -77,7 +80,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -215,7 +218,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index 2e7c505f99e..bab4c3d37d3 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -54,20 +54,23 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ASKENV | \ - CFG_CMD_ELF | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_ELF +#define CONFIG_CMD_BSP +#define CONFIG_CMD_EEPROM + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -77,7 +80,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -213,7 +216,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/OXC.h b/include/configs/OXC.h index 787407c5eb8..e70d4850a9f 100644 --- a/include/configs/OXC.h +++ b/include/configs/OXC.h @@ -51,10 +51,14 @@ #define CONFIG_BAUDRATE 9600 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_ELF) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ELF + /* * Miscellaneous configurable options @@ -299,7 +303,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From acf0269779422f3e147d2ddfb499c9f6ff10ad5e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sun, 8 Jul 2007 14:49:44 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various P* named board config files. Signed-off-by: Jon Loeliger --- include/configs/P3G4.h | 31 ++++++++++--------- include/configs/PATI.h | 28 ++++++++++++----- include/configs/PCI405.h | 29 ++++++++++-------- include/configs/PCI5441.h | 33 ++++++++++---------- include/configs/PCIPPC2.h | 31 ++++++++++--------- include/configs/PCIPPC6.h | 33 ++++++++++---------- include/configs/PIP405.h | 60 ++++++++++++++++++------------------ include/configs/PK1C20.h | 46 ++++++++++++++-------------- include/configs/PLU405.h | 39 +++++++++++++----------- include/configs/PM520.h | 66 ++++++++++++++++++---------------------- include/configs/PM826.h | 46 ++++++++++++---------------- include/configs/PM828.h | 46 ++++++++++++---------------- include/configs/PMC405.h | 37 +++++++++++----------- include/configs/PN62.h | 27 ++++++++-------- include/configs/PPChameleonEVB.h | 39 +++++++++++++----------- 15 files changed, 303 insertions(+), 288 deletions(-) (limited to 'include') diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h index a933e1b180c..bfcfbc1bad3 100644 --- a/include/configs/P3G4.h +++ b/include/configs/P3G4.h @@ -125,25 +125,28 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_UNIVERSE| \ - CFG_CMD_BSP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_UNIVERSE +#define CONFIG_CMD_BSP + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -396,7 +399,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/PATI.h b/include/configs/PATI.h index d88fff33ead..b0f86157deb 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -39,14 +39,26 @@ #define CONFIG_BAUDRATE 9600 -#define CONFIG_COMMANDS (CFG_CMD_MEMORY | CFG_CMD_LOADB | CFG_CMD_REGINFO | \ - CFG_CMD_FLASH | CFG_CMD_LOADS | CFG_CMD_ENV | CFG_CMD_REGINFO | \ - CFG_CMD_BDI | CFG_CMD_CONSOLE | CFG_CMD_RUN | CFG_CMD_BSP | \ - CFG_CMD_IMI | CFG_CMD_EEPROM | CFG_CMD_IRQ | CFG_CMD_MISC \ -) -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_ENV +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_BDI +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_RUN +#define CONFIG_CMD_BSP +#define CONFIG_CMD_IMI +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MISC + #if 0 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ @@ -71,7 +83,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "pati=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 027dd22bf46..2dfd2311738 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -68,17 +68,20 @@ #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_BSP +#define CONFIG_CMD_EEPROM + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -97,7 +100,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -244,7 +247,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h index 3a7f7f06474..1bfcd37d060 100644 --- a/include/configs/PCI5441.h +++ b/include/configs/PCI5441.h @@ -122,22 +122,23 @@ #define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) #define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_ECHO | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IRQ | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_RUN | \ - CFG_CMD_SAVES ) -#include + +/* + * Command line configuration. + */ +#define CONFIG_CMD_BDI +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVES + /*------------------------------------------------------------------------ * MISC diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h index 3a97fbcbde8..68b9d756926 100644 --- a/include/configs/PCIPPC2.h +++ b/include/configs/PCIPPC2.h @@ -59,24 +59,25 @@ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_ELF | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DOC +#define CONFIG_CMD_ELF +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SNTP #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include - #define CFG_NAND_LEGACY /* @@ -223,7 +224,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h index 130beb78e63..a8e27153eeb 100644 --- a/include/configs/PCIPPC6.h +++ b/include/configs/PCIPPC6.h @@ -59,26 +59,27 @@ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_ELF | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SCSI | \ - CFG_CMD_SNTP ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DOC +#define CONFIG_CMD_ELF +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_SNTP #define CONFIG_PCI 1 #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ -/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) - */ -#include - #define CFG_NAND_LEGACY /* @@ -225,7 +226,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 806e95f4808..0a2d7d7f9d4 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -40,33 +40,33 @@ ***********************************************************/ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ -/*********************************************************** - * Command definitions - ***********************************************************/ -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_IDE | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_CACHE | \ - CFG_CMD_IRQ | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_REGINFO | \ - CFG_CMD_FDC | \ - CFG_CMD_SCSI | \ - CFG_CMD_FAT | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF | \ - CFG_CMD_USB | \ - CFG_CMD_MII | \ - CFG_CMD_SDRAM | \ - CFG_CMD_DOC | \ - CFG_CMD_PING | \ - CFG_CMD_SAVES | \ - CFG_CMD_BSP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_IDE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_FDC +#define CONFIG_CMD_SCSI +#define CONFIG_CMD_FAT +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_USB +#define CONFIG_CMD_MII +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_DOC +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_BSP + #define CFG_NAND_LEGACY @@ -150,7 +150,7 @@ **********************************************************/ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -227,7 +227,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -366,7 +366,7 @@ /************************************************************ * Debug support ************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index 83a7ec27b43..49a285c5d1c 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -160,30 +160,32 @@ #define CONFIG_IPADDR 192.168.2.21 #define CONFIG_SERVERIP 192.168.2.16 -/*------------------------------------------------------------------------ - * COMMANDS - *----------------------------------------------------------------------*/ -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IRQ | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_RUN | \ - CFG_CMD_SAVES ) -#include + +/* + * Command line configuration. + */ + +#define CONFIG_CMD_BDI +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVES + /*------------------------------------------------------------------------ * COMPACT FLASH *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_IDE) +#if defined(CONFIG_CMD_IDE) #define CONFIG_IDE_PREINIT /* Implement id_preinit */ #define CFG_IDE_MAXBUS 1 /* 1 IDE bus */ #define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */ @@ -201,12 +203,12 @@ #define CFG_CF_POWER 0x00900890 /* CF Power FET PIO base*/ #define CFG_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base */ -#endif /* CONFIG_COMMANDS & CFG_CMD_IDE */ +#endif /*------------------------------------------------------------------------ * JFFS2 *----------------------------------------------------------------------*/ -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#if defined(CONFIG_CMD_JFFS2) #define CFG_JFFS_CUSTOM_PART /* board defined part */ #endif diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index d02c39b28f9..5742db6f2a2 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -61,19 +61,25 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_NAND | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_ELF +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -83,9 +89,6 @@ #define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ #define CONFIG_AUTO_UPDATE_SHOW 1 /* use board show routine */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ @@ -104,7 +107,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -331,7 +334,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/PM520.h b/include/configs/PM520.h index 7d91a0160c4..3cd3511f787 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -40,11 +40,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -77,12 +72,6 @@ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #undef CONFIG_NS8382X -#define ADD_PCI_CMD CFG_CMD_PCI - -#else /* MPC5100 */ - -#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ - #endif /* Partitions */ @@ -91,39 +80,39 @@ /* USB */ #if 1 #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 #endif -#if defined(CONFIG_BOOT_ROM) -#define ADD_DOC_CMD 0 -#else -#define ADD_DOC_CMD CFG_CMD_DOC +#if !defined(CONFIG_BOOT_ROM) /* DoC requires legacy NAND for now */ #define CFG_NAND_LEGACY #endif + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - ADD_DOC_CMD | \ - ADD_PCI_CMD | \ - ADD_USB_CMD | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#include + +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_USB + +#if !defined(CONFIG_BOOT_ROM) +#define CONFIG_CMD_DOC +#endif + +#if defined(CONFIG_MPC5200) +#define CONFIG_CMD_PCI +#endif + /* * Autobooting @@ -294,7 +283,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -310,6 +299,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Various low-level settings */ diff --git a/include/configs/PM826.h b/include/configs/PM826.h index 88fdb51adef..a93400d9920 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -154,31 +154,25 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DOC +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + #ifdef CONFIG_PCI -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) -#else /* ! PCI */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#endif /* CONFIG_PCI */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_CMD_PCI +#endif + #define CFG_NAND_LEGACY @@ -197,7 +191,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -345,7 +339,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/PM828.h b/include/configs/PM828.h index 37ee9771b52..5095a050ac5 100644 --- a/include/configs/PM828.h +++ b/include/configs/PM828.h @@ -154,31 +154,25 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DOC +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP + #ifdef CONFIG_PCI -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) -#else /* ! PCI */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DOC | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) -#endif /* CONFIG_PCI */ - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_CMD_PCI +#endif + /* * Disk-On-Chip configuration @@ -196,7 +190,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -338,7 +332,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 6e0bd7f23ec..bdbc900ba0c 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -63,25 +63,28 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_I2C | \ - CFG_CMD_PING | \ - CFG_CMD_UNIVERSE | \ - CFG_CMD_EEPROM ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_UNIVERSE +#define CONFIG_CMD_EEPROM + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ @@ -100,7 +103,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -263,7 +266,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/PN62.h b/include/configs/PN62.h index a717659bb69..8346d8ca028 100644 --- a/include/configs/PN62.h +++ b/include/configs/PN62.h @@ -42,15 +42,20 @@ #define CONFIG_CONS_INDEX 1 -#define REMOVE_COMMANDS ( CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_LOADS | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMLS ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_BSP + +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS -#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~REMOVE_COMMANDS) |\ - CFG_CMD_PCI |\ - CFG_CMD_BSP) #define CONFIG_BAUDRATE 19200 /* console baudrate */ @@ -82,10 +87,6 @@ "loadp 200000; bootm" #endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - - /* * Miscellaneous configurable options */ @@ -287,7 +288,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 16e2cc6d648..709ce5f0e94 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -113,26 +113,29 @@ #endif #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SNTP + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_M41T11 1 /* uses a M41T00 RTC */ @@ -162,7 +165,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -446,7 +449,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From 12aa9fd23d724bd6ab88e1baa0db35133a27303f Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sun, 8 Jul 2007 14:55:07 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various Q* named board config files. Signed-off-by: Jon Loeliger --- include/configs/QS823.h | 34 ++++++++++++++++++---------------- include/configs/QS850.h | 35 +++++++++++++++++++---------------- include/configs/QS860T.h | 24 +++++++++++++----------- 3 files changed, 50 insertions(+), 43 deletions(-) (limited to 'include') diff --git a/include/configs/QS823.h b/include/configs/QS823.h index 235bc480c7f..478ab93de06 100644 --- a/include/configs/QS823.h +++ b/include/configs/QS823.h @@ -196,20 +196,22 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CONSOLE | \ - CFG_CMD_DATE | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IMMAP | \ - CFG_CMD_MEMORY | \ - CFG_CMD_NET | \ - CFG_CMD_RUN) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_RUN + /*----------------------------------------------------------------------- * Environment variable storage is in FLASH, one sector before U-boot @@ -228,7 +230,7 @@ #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ #define CFG_PROMPT_HUSH_PS2 "> " -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -303,7 +305,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/QS850.h b/include/configs/QS850.h index 967582b45ed..8664eb0f36f 100644 --- a/include/configs/QS850.h +++ b/include/configs/QS850.h @@ -196,20 +196,23 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS (CFG_CMD_BDI | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CONSOLE | \ - CFG_CMD_DATE | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IMMAP | \ - CFG_CMD_MEMORY | \ - CFG_CMD_NET | \ - CFG_CMD_RUN) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ + +#define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_RUN + /*----------------------------------------------------------------------- * Environment variable storage is in FLASH, one sector before U-boot @@ -228,7 +231,7 @@ #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ #define CFG_PROMPT_HUSH_PS2 "> " -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -303,7 +306,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h index 32faa61607b..906e117fb20 100644 --- a/include/configs/QS860T.h +++ b/include/configs/QS860T.h @@ -99,16 +99,18 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_ASKENV | \ - CFG_CMD_NET | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_NET +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DATE /* TODO */ @@ -136,7 +138,7 @@ CONFIG_SPI #define CFG_HUSH_PARSER 1 /* use "hush" command parser */ #define CFG_PROMPT_HUSH_PS2 "> " -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -210,7 +212,7 @@ CONFIG_SPI * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From e9a0f8f15c11f337967aa0600ad6e8af33037f50 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sun, 8 Jul 2007 15:12:40 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various R* named board config files. Signed-off-by: Jon Loeliger --- include/configs/R360MPI.h | 35 +++++++++++++----------- include/configs/RBC823.h | 64 +++++++++++++++++++++++--------------------- include/configs/RPXClassic.h | 15 ++++++----- include/configs/RPXlite.h | 11 +++++--- include/configs/RPXlite_DW.h | 42 +++++++++++++---------------- include/configs/RPXsuper.h | 27 ++++++++++--------- include/configs/RRvision.h | 25 +++++++++-------- include/configs/Rattler.h | 28 ++++++++++--------- 8 files changed, 131 insertions(+), 116 deletions(-) (limited to 'include') diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h index 82228c0126b..c00ed3d4c01 100644 --- a/include/configs/R360MPI.h +++ b/include/configs/R360MPI.h @@ -111,20 +111,23 @@ #define CFG_I2C_KEY_ADDR 0x9 /* Keyboard coprocessor */ #define CFG_I2C_TEM_ADDR 0x49 /* Temperature Sensors */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NFS | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BMP +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCMCIA +#define CONFIG_CMD_SNTP + /* * Miscellaneous configurable options @@ -134,7 +137,7 @@ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -228,7 +231,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index 242c837a3b8..d73a367616b 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -94,42 +94,44 @@ #define CFG_EEPROM_WRITE_BITS 4 #define CFG_EEPROM_WRITE_DELAY_MS 10 -#define CONFIG_COMMANDS ( CFG_CMD_ALL & \ - ~CFG_CMD_BSP & \ - ~CFG_CMD_DATE & \ - ~CFG_CMD_DISPLAY& \ - ~CFG_CMD_DTT & \ - ~CFG_CMD_EXT2 & \ - ~CFG_CMD_FDC & \ - ~CFG_CMD_FDOS & \ - ~CFG_CMD_HWFLOW & \ - ~CFG_CMD_IDE & \ - ~CFG_CMD_IRQ & \ - ~CFG_CMD_JFFS2 & \ - ~CFG_CMD_MII & \ - ~CFG_CMD_MMC & \ - ~CFG_CMD_NAND & \ - ~CFG_CMD_PCI & \ - ~CFG_CMD_PCMCIA & \ - ~CFG_CMD_REISER & \ - ~CFG_CMD_SCSI & \ - ~CFG_CMD_SETGETDCR & \ - ~CFG_CMD_SNTP & \ - ~CFG_CMD_SPI & \ - ~CFG_CMD_UNIVERSE & \ - ~CFG_CMD_USB & \ - ~CFG_CMD_VFD & \ - ~CFG_CMD_XIMG ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#undef CONFIG_CMD_BSP +#undef CONFIG_CMD_DATE +#undef CONFIG_CMD_DISPLAY +#undef CONFIG_CMD_DTT +#undef CONFIG_CMD_EXT2 +#undef CONFIG_CMD_FDC +#undef CONFIG_CMD_FDOS +#undef CONFIG_CMD_HWFLOW +#undef CONFIG_CMD_IDE +#undef CONFIG_CMD_IRQ +#undef CONFIG_CMD_JFFS2 +#undef CONFIG_CMD_MII +#undef CONFIG_CMD_MMC +#undef CONFIG_CMD_NAND +#undef CONFIG_CMD_PCI +#undef CONFIG_CMD_PCMCIA +#undef CONFIG_CMD_REISER +#undef CONFIG_CMD_SCSI +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_SNTP +#undef CONFIG_CMD_SPI +#undef CONFIG_CMD_UNIVERSE +#undef CONFIG_CMD_USB +#undef CONFIG_CMD_VFD +#undef CONFIG_CMD_XIMG + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -205,7 +207,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h index 591382cd24d..2091735aae0 100644 --- a/include/configs/RPXClassic.h +++ b/include/configs/RPXClassic.h @@ -93,10 +93,13 @@ #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ -#define CONFIG_COMMANDS ((CFG_CMD_ALL & ~CFG_CMD_NONSTD) | CFG_CMD_ELF) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ELF -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options @@ -104,7 +107,7 @@ #define CFG_RESET_ADDRESS 0x80000000 #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -182,7 +185,7 @@ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFF000000 -#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#if defined(DEBUG) || defined (CONFIG_VIDEO_SED13806) || defined(CONFIG_CMD_IDE) #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ @@ -222,7 +225,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h index 48ada0ed9b6..a478a067df6 100644 --- a/include/configs/RPXlite.h +++ b/include/configs/RPXlite.h @@ -64,15 +64,18 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -154,7 +157,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h index 31025473f43..9bf7770d3ab 100644 --- a/include/configs/RPXlite_DW.h +++ b/include/configs/RPXlite_DW.h @@ -120,24 +120,23 @@ #if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you don't want the advanced function */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_DHCP + #ifdef CONFIG_SPLASH_SCREEN -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BMP | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_PING | \ - CFG_CMD_ELF | \ - CFG_CMD_REGINFO | \ - CFG_CMD_DHCP ) -#else -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_PING | \ - CFG_CMD_ELF | \ - CFG_CMD_REGINFO | \ - CFG_CMD_DHCP ) -#endif /* CONFIG_SPLASH_SCREEN */ +#define CONFIG_CMD_BMP +#endif + /* test-only */ #define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ @@ -147,16 +146,13 @@ #endif /* 1 */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "u-boot>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -200,7 +196,7 @@ #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xFF000000 -#if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE) +#if defined(DEBUG) || defined(CONFIG_CMD_IDE) #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ #else #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ @@ -239,7 +235,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h index 45907aa0e79..c39aff19bc0 100644 --- a/include/configs/RPXsuper.h +++ b/include/configs/RPXsuper.h @@ -150,13 +150,19 @@ /* Monitor Command Prompt */ #define CFG_PROMPT "=> " -/* What U-Boot subsytems do you want enabled? */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_IMMAP | \ - CFG_CMD_ASKENV | \ - CFG_CMD_I2C | \ - CFG_CMD_REGINFO & \ - ~CFG_CMD_KGDB ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_REGINFO + +#undef CONFIG_CMD_KGDB + /* Where do the internal registers live? */ #define CFG_IMMR 0xF0000000 @@ -176,13 +182,10 @@ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else # define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -310,7 +313,7 @@ */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h index 3885bcdb1ef..2c590af83bc 100644 --- a/include/configs/RRvision.h +++ b/include/configs/RRvision.h @@ -135,23 +135,26 @@ #endif /* CONFIG_SOFT_I2C */ -#define CONFIG_COMMANDS ( ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_DATE ) & \ - ~( CFG_CMD_PCMCIA | \ - CFG_CMD_IDE ) ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_DATE + +#undef CONFIG_CMD_PCMCIA +#undef CONFIG_CMD_IDE -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -228,7 +231,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h index dbc57e8b271..5c6431487c4 100644 --- a/include/configs/Rattler.h +++ b/include/configs/Rattler.h @@ -125,22 +125,24 @@ #define CONFIG_BAUDRATE 38400 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_JFFS2 \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -158,7 +160,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -184,7 +186,7 @@ #define CFG_DIRECT_FLASH_TFTP -#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) +#if defined(CONFIG_CMD_JFFS2) #define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS #define CFG_JFFS2_SORT_FRAGMENTS @@ -256,7 +258,7 @@ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From fe7f782d5b8c64a0195c68c31a0a11d4f641355e Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sun, 8 Jul 2007 15:02:44 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various S* named board config files. Signed-off-by: Jon Loeliger --- include/configs/SCM.h | 21 ++++++++++++--------- include/configs/SL8245.h | 10 ++++++---- include/configs/SM850.h | 17 ++++++++++------- include/configs/SMN42.h | 21 ++++++++++----------- include/configs/SPD823TS.h | 20 +++++++++++++------- include/configs/SX1.h | 15 ++++++++++----- include/configs/SXNI855T.h | 21 ++++++++++++--------- include/configs/Sandpoint8240.h | 29 ++++++++++++++++------------- include/configs/Sandpoint8245.h | 24 +++++++++++++----------- 9 files changed, 102 insertions(+), 76 deletions(-) (limited to 'include') diff --git a/include/configs/SCM.h b/include/configs/SCM.h index e263db65a2f..67dbc55dbb5 100644 --- a/include/configs/SCM.h +++ b/include/configs/SCM.h @@ -193,21 +193,24 @@ #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_BSP) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_BSP + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -353,7 +356,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/SL8245.h b/include/configs/SL8245.h index 61896d0d7d1..b8e5c7de730 100644 --- a/include/configs/SL8245.h +++ b/include/configs/SL8245.h @@ -53,11 +53,13 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +/* + * Command line configuration. + */ +#include -#include +#define CONFIG_CMD_PCI /* @@ -255,7 +257,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/SM850.h b/include/configs/SM850.h index 49776291211..0ec63b88111 100644 --- a/include/configs/SM850.h +++ b/include/configs/SM850.h @@ -72,19 +72,22 @@ #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DATE + /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) && defined(KGDB_DEBUG) +#if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -167,7 +170,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h index d588818fc2e..7b6d27686cc 100644 --- a/include/configs/SMN42.h +++ b/include/configs/SMN42.h @@ -101,21 +101,20 @@ PUT32(IO0DIR, i2ctmp); } #endif /* CONFIG_SOFT_I2C */ + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_FAT | \ - CFG_CMD_MMC | \ - CFG_CMD_NET | \ - CFG_CMD_EEPROM | \ - CFG_CMD_PING) +#include +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_PING -#define CONFIG_DOS_PARTITION -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +#define CONFIG_DOS_PARTITION #define CONFIG_BOOTDELAY 5 diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h index ae4dcc2ccca..fa4cdc63a23 100644 --- a/include/configs/SPD823TS.h +++ b/include/configs/SPD823TS.h @@ -59,16 +59,22 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_COMMANDS \ -((CONFIG_CMD_DFL & ~(CFG_CMD_FLASH)) | CFG_CMD_IDE) /* no Flash, but IDE */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_IDE + +#undef CONFIG_CMD_FLASH + + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /*----------------------------------------------------------------------*/ #define CONFIG_ETHADDR 00:D0:93:00:01:CB #define CONFIG_IPADDR 10.0.0.98 @@ -82,7 +88,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -160,7 +166,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/SX1.h b/include/configs/SX1.h index 6ed98b8fb18..588d3459e09 100644 --- a/include/configs/SX1.h +++ b/include/configs/SX1.h @@ -93,12 +93,17 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_COMMANDS (( CONFIG_CMD_DFL | \ - CFG_CMD_I2C ) & \ - ~CFG_CMD_NET) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_I2C + +#undef CONFIG_CMD_NET + + #include #define CONFIG_BOOTARGS "mem=16M console=ttyS0,115200n8 root=/dev/mtdblock3 rw" diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h index a8454d99fc0..efc500ca5b3 100644 --- a/include/configs/SXNI855T.h +++ b/include/configs/SXNI855T.h @@ -146,14 +146,17 @@ #define CFG_DISCOVER_PHY -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_EEPROM | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_NAND | \ - CFG_CMD_DATE) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DATE + #define CFG_JFFS2_SORT_FRAGMENTS @@ -226,7 +229,7 @@ */ #define CFG_LONGHELP /* undef to save a little memory */ #define CFG_PROMPT "=>" /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -309,7 +312,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h index f4339ecd9c8..d19c27e84b2 100644 --- a/include/configs/Sandpoint8240.h +++ b/include/configs/Sandpoint8240.h @@ -80,18 +80,21 @@ "" #define CONFIG_BOOTCOMMAND "run flash_self" -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_SDRAM | \ - CFG_CMD_EEPROM | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SNTP + #define CONFIG_DRAM_SPEED 100 /* MHz */ @@ -384,7 +387,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h index d42bd69231e..cbad484b072 100644 --- a/include/configs/Sandpoint8245.h +++ b/include/configs/Sandpoint8245.h @@ -51,17 +51,19 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_SNTP ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_SNTP /* @@ -363,7 +365,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From a5562901661bd428f7e5feb333f796372cb81019 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sun, 8 Jul 2007 15:31:57 -0500 Subject: include/configs: Use new CONFIG_CMD_* in various [TUVWZYZ]* named board config files. Signed-off-by: Jon Loeliger --- include/configs/TASREG.h | 23 ++++++++++++-------- include/configs/TOP860.h | 38 ++++++++++++++++----------------- include/configs/VCMA9.h | 45 +++++++++++++++++++-------------------- include/configs/VOH405.h | 39 ++++++++++++++++++---------------- include/configs/VOM405.h | 33 ++++++++++++++++------------- include/configs/VoVPN-GW.h | 41 ++++++++++++++++++------------------ include/configs/W7OLMC.h | 29 +++++++++++++++++--------- include/configs/W7OLMG.h | 31 ++++++++++++++++++--------- include/configs/WUH405.h | 33 ++++++++++++++++------------- include/configs/XPEDITE1K.h | 43 +++++++++++++++++++------------------- include/configs/Yukon8220.h | 51 ++++++++++++++++++++++----------------------- include/configs/ZPC1900.h | 26 ++++++++++++----------- include/configs/ZUMA.h | 25 ++++++++++++---------- 13 files changed, 245 insertions(+), 212 deletions(-) (limited to 'include') diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h index 119bc2442bb..b0116e7acda 100644 --- a/include/configs/TASREG.h +++ b/include/configs/TASREG.h @@ -50,20 +50,25 @@ #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ -#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C ) & \ - ~(CFG_CMD_NET)) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C + +#undef CONFIG_CMD_NET + + #define CONFIG_BOOTDELAY 3 #define CFG_PROMPT "=> " #define CFG_LONGHELP /* undef to save memory */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h index 2344b96811b..717b779570e 100644 --- a/include/configs/TOP860.h +++ b/include/configs/TOP860.h @@ -107,30 +107,28 @@ */ #define CFG_MATCH_PARTIAL_CMD + /* - * List of available monitor commands. Use the system default list - * plus add some of the "non-standard" commands back in. - * See ./cmd_confdefs.h - */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_I2C | \ - CFG_CMD_EEPROM | \ - CFG_CMD_REGINFO | \ - CFG_CMD_IMMAP | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_MII | \ - CFG_CMD_BEDBUG \ - ) + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_MII +#define CONFIG_CMD_BEDBUG + #define CONFIG_AUTOSCRIPT 1 #define CFG_LOADS_BAUD_CHANGE 1 #undef CONFIG_LOADS_ECHO /* NO echo on for serial download */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ @@ -141,7 +139,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -239,7 +237,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 5f48a709381..ab802a3cd58 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -48,27 +48,24 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 -/*********************************************************** - * Command definition - ***********************************************************/ -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_CACHE | \ - /*CFG_CMD_JFFS2 |*/ \ - /*CFG_CMD_NAND |*/ \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_USB | \ - CFG_CMD_REGINFO | \ - CFG_CMD_FAT | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF | \ - CFG_CMD_DHCP | \ - CFG_CMD_PING | \ - CFG_CMD_BSP) - -/* this must be included after the definiton of CONFIG_COMMANDS */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_USB +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_FAT +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_BSP + #define CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " @@ -145,7 +142,7 @@ #define CONFIG_IPADDR 10.0.0.110 #define CONFIG_SERVERIP 10.0.0.1 -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ /* what's this ? it's not used anywhere */ #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ @@ -246,7 +243,7 @@ /*----------------------------------------------------------------------- * NAND flash settings */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CONFIG_CMD_NAND) #define CFG_NAND_LEGACY #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ @@ -280,6 +277,6 @@ #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_MTD_NAND_ECC_JFFS2 1 -#endif /* CONFIG_COMMANDS & CFG_CMD_NAND */ +#endif #endif /* __CONFIG_H */ diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 96f3d26cc5e..3f2c32b6b25 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -58,28 +58,31 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_NAND | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_ELF +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/ @@ -98,7 +101,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -319,7 +322,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index f2f3ea7cc4d..f312ea46ac4 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -65,19 +65,22 @@ CONFIG_BOOTP_DNS2 | \ CONFIG_BOOTP_SEND_HOSTNAME ) -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_BSP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_BSP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -96,7 +99,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -244,7 +247,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h index 92bade5187e..88062441969 100644 --- a/include/configs/VoVPN-GW.h +++ b/include/configs/VoVPN-GW.h @@ -138,24 +138,25 @@ #endif -/* configure commands */ -#define CONFIG_COMMANDS ( CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_BDI | \ - CFG_CMD_CONSOLE | \ - CFG_CMD_ECHO | \ - CFG_CMD_ENV | \ - CFG_CMD_FLASH | \ - CFG_CMD_IMI | \ - CFG_CMD_IMLS | \ - CFG_CMD_LOADB | \ - CFG_CMD_MEMORY | \ - CFG_CMD_MISC | \ - CFG_CMD_NET | \ - CFG_CMD_PING | \ - CFG_CMD_RUN ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ + +#define CONFIG_CMD_AUTOSCRIPT +#define CONFIG_CMD_BDI +#define CONFIG_CMD_CONSOLE +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMI +#define CONFIG_CMD_IMLS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MISC +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN + /* * boot options & environment @@ -206,7 +207,7 @@ #define CFG_PROMPT "=> " /* console i/o buffer size */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 #else #define CFG_CBSIZE 256 @@ -305,7 +306,7 @@ /* cache configuration */ #define CFG_CACHELINE_SIZE 32 /* for MPC8260 */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of above */ #endif diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index 8dc623ea069..fd810961d0e 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -70,13 +70,22 @@ #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \ - CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_BSP +#define CONFIG_CMD_REGINFO #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ @@ -92,7 +101,7 @@ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -277,7 +286,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ #endif @@ -309,7 +318,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index 2bd98b3af33..a5ce6854124 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -75,14 +75,25 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3 -#define CONFIG_COMMANDS \ - (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \ - CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO | \ - CFG_CMD_DTT) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_BSP +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_DTT + #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */ @@ -98,7 +109,7 @@ #ifdef CFG_HUSH_PARSER #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -278,7 +289,7 @@ */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */ #endif @@ -310,7 +321,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index faf855d2492..f7865200c1e 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -60,19 +60,22 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_IRQ | \ - CFG_CMD_ELF | \ - CFG_CMD_NAND | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_EEPROM ) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_ELF +#define CONFIG_CMD_NAND +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_EEPROM + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -92,7 +95,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -270,7 +273,7 @@ #define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */ /* have only 8kB, 16kB is save here */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index f2ad097db29..4b8fbe6f4d6 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -182,25 +182,24 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_HAS_ETH2 1 /* add support for "eth2addr" */ #define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_I2C | \ - CFG_CMD_DATE | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_PING | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_DIAG | \ - CFG_CMD_FAT ) - -/* CFG_CMD_DHCP | \ */ -/* CFG_CMD_KGDB | \ */ - - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_DATE +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_MII +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_FAT + #undef CONFIG_WATCHDOG /* watchdog disabled */ @@ -209,7 +208,7 @@ extern void out32(unsigned int, unsigned long); */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -254,7 +253,7 @@ extern void out32(unsigned int, unsigned long); */ #define CFG_DCACHE_SIZE 8192 /* For AMCC 440GX CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -266,7 +265,7 @@ extern void out32(unsigned int, unsigned long); #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h index 37ef1058f90..07fab44314d 100644 --- a/include/configs/Yukon8220.h +++ b/include/configs/Yukon8220.h @@ -39,12 +39,6 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ - -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Serial console configuration */ @@ -70,31 +64,31 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ + /* - * Supported commands + * Command line configuration. */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CACHE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_I2C | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP ) +#include + +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_SNTP + #define CONFIG_NET_MULTI #define CONFIG_MII -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Autobooting */ @@ -293,7 +287,7 @@ */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -309,6 +303,11 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + /* * Various low-level settings */ diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index 2b02fe75093..30c7790c877 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -106,22 +106,24 @@ #define CONFIG_BAUDRATE 38400 -#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ - | CFG_CMD_ASKENV \ - | CFG_CMD_DHCP \ - | CFG_CMD_IMMAP \ - | CFG_CMD_MII \ - | CFG_CMD_PING \ - ) -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -139,7 +141,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -223,7 +225,7 @@ #endif #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h index f163d003b9a..662093834a3 100644 --- a/include/configs/ZUMA.h +++ b/include/configs/ZUMA.h @@ -106,12 +106,18 @@ #define CONFIG_MII /* enable MII commands */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_BSP | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_DATE) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BSP +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_DATE + /* * JFFS2 partitions @@ -131,15 +137,12 @@ #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -349,7 +352,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif -- cgit v1.3.1 From a22d4da95e20049b4daa1c2a022f61e8a72f2fb6 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sun, 8 Jul 2007 15:42:59 -0500 Subject: include/configs: Catch some CONFIG_CMD_* conversion stragglers. Use new CONFIG_CMD_* in lwmon5.h board config file. Fix CONFIG_CMD_* typo braindamage in omap1510inn.h Signed-off-by: Jon Loeliger --- include/configs/lwmon5.h | 57 +++++++++++++++++++++++-------------------- include/configs/omap1510inn.h | 2 -- 2 files changed, 30 insertions(+), 29 deletions(-) (limited to 'include') diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index c6f67fee44e..13cbed5e9a5 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -216,9 +216,6 @@ /* Comment this out to enable USB 1.1 device */ #define USB_2_0_DEVICE -#define CMD_USB CFG_CMD_USB -#else -#define CMD_USB 0 /* no USB on 440GRx */ #endif /* CONFIG_440EPX */ /* Partitions */ @@ -226,36 +223,42 @@ #define CONFIG_DOS_PARTITION #define CONFIG_ISO_PARTITION -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_IRQ | \ - CFG_CMD_MII | \ - CFG_CMD_NET | \ - CFG_CMD_NFS | \ - CFG_CMD_PCI | \ - CFG_CMD_PING | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SDRAM | \ - CMD_USB) -#define CONFIG_SUPPORT_VFAT +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + +#ifdef CONFIG_440EPX +#define CONFIG_CMD_USB +#endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /*----------------------------------------------------------------------- * Miscellaneous configurable options *----------------------------------------------------------------------*/ +#define CONFIG_SUPPORT_VFAT + #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -418,7 +421,7 @@ *----------------------------------------------------------------------*/ #define CFG_DCACHE_SIZE (32<<10) /* For AMCC 440 CPUs */ #define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -430,7 +433,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h index 11fdb471014..9f4be5ca19b 100644 --- a/include/configs/omap1510inn.h +++ b/include/configs/omap1510inn.h @@ -86,8 +86,6 @@ #define CONFIG_BAUDRATE 115200 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_COMMANDS (CONFIG_CMD_DFL - /* * Command line configuration. -- cgit v1.3.1 From b3631487105a57ab7cbadfc26efbaf9676275018 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sun, 8 Jul 2007 15:45:08 -0500 Subject: Remove references to the old cmd_confdefs.h include file. Signed-off-by: Jon Loeliger --- doc/README.bedbug | 3 --- include/command.h | 6 ------ 2 files changed, 9 deletions(-) (limited to 'include') diff --git a/doc/README.bedbug b/doc/README.bedbug index 9cfb4217fe1..6b3fe687dd2 100644 --- a/doc/README.bedbug +++ b/doc/README.bedbug @@ -31,9 +31,6 @@ can be easily implemented. if it is an illegal instruction, privileged instruction or a trap. Also added debug trap handler. -./include/cmd_confdefs.h - Added definition of CFG_CMD_BEDBUG. - ./include/config_WALNUT405.h Added CFG_CMD_BEDBUG to the CONFIG_COMMANDS for the WALNUT. diff --git a/include/command.h b/include/command.h index a2936ad8b3e..0597c10dafe 100644 --- a/include/command.h +++ b/include/command.h @@ -84,12 +84,6 @@ typedef void command_t (cmd_tbl_t *, int, int, char *[]); #define CMD_FLAG_REPEAT 0x0001 /* repeat last command */ #define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */ -/* - * Configurable monitor commands definitions have been moved - * to include/cmd_confdefs.h - */ - - #define Struct_Section __attribute__ ((unused,section (".u_boot_cmd"))) #ifdef CFG_LONGHELP -- cgit v1.3.1 From af075ee96e52dda7b6bca6c937588aeaaec5f2cd Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Sun, 8 Jul 2007 17:02:01 -0500 Subject: Clear up confusion over the CMD_POST and POST_DIAG mess. For some reason, CONFIG_POST permeated as CONFIG_CMD_POST_DIAG when it really means just CONFIG_CMD_DIAG. There is no CMD_POST. Clear this mess up some. Signed-off-by: Jon Loeliger --- include/configs/BC3450.h | 8 ++++---- include/configs/GEN860T.h | 10 +++------- include/configs/KUP4K.h | 10 +++------- include/configs/KUP4X.h | 10 +++------- include/configs/TB5200.h | 16 ++++++++-------- include/configs/TQM5200.h | 8 ++++---- include/configs/aev.h | 8 ++++---- include/configs/bf537-stamp.h | 8 ++++---- include/configs/lwmon.h | 11 ++++------- include/configs/smmaco4.h | 8 ++++---- include/configs/spieval.h | 30 +++++++++++++++--------------- include/configs/uc100.h | 11 ++++------- 12 files changed, 60 insertions(+), 78 deletions(-) (limited to 'include') diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 00b656e737d..aec4d83f251 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -138,11 +138,8 @@ CFG_POST_I2C) #ifdef CONFIG_POST -# define CFG_CMD_POST_DIAG CFG_CMD_DIAG /* preserve space for the post_word at end of on-chip SRAM */ # define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -# define CFG_CMD_POST_DIAG 0 #endif /* CONFIG_POST */ @@ -161,7 +158,6 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_NFS #define CONFIG_CMD_PING -#define CONFIG_CMD_POST_DIAG #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SNTP #define CONFIG_CMD_BSP @@ -192,6 +188,10 @@ #define CONFIG_CMD_PCI #endif +#ifdef CONFIG_POST + #define CONFIG_CMD_DIAG +#endif + #define CONFIG_TIMESTAMP /* display image timestamps */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index 612b661ad22..2b2d15a7629 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -222,12 +222,6 @@ CFG_POST_UART | \ CFG_POST_SPR ) -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -#else -#define CFG_CMD_POST_DIAG 0 -#endif - /* * Command line configuration. @@ -245,12 +239,14 @@ #define CONFIG_CMD_FPGA #define CONFIG_CMD_MII #define CONFIG_CMD_BEDBUG -#define CONFIG_CMD_POST_DIAG #if !defined(CONFIG_SC) #define CONFIG_CMD_DOC #endif +#ifdef CONFIG_POST +u #define CONFIG_CMD_DIAG +#endif /* * There is no IDE/PCMCIA hardware support on the board. diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h index 24222017659..2f056059c18 100644 --- a/include/configs/KUP4K.h +++ b/include/configs/KUP4K.h @@ -156,12 +156,6 @@ #define CONFIG_POST (CFG_POST_CPU | \ CFG_POST_RTC | \ CFG_POST_I2C) - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -#else -#define CFG_CMD_POST_DIAG 0 -#endif #endif @@ -175,9 +169,11 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE #define CONFIG_CMD_NFS -#define CONFIG_CMD_POST_DIAG #define CONFIG_CMD_SNTP +#ifdef CONFIG_POST + #define CONFIG_CMD_DIAG +#endif /* * Miscellaneous configurable options diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h index 184338b97d2..c59b70f15c1 100644 --- a/include/configs/KUP4X.h +++ b/include/configs/KUP4X.h @@ -167,12 +167,6 @@ #define CONFIG_POST (CFG_POST_CPU | \ CFG_POST_RTC | \ CFG_POST_I2C) - -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -#else -#define CFG_CMD_POST_DIAG 0 -#endif #endif @@ -187,10 +181,12 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE #define CONFIG_CMD_NFS -#define CONFIG_CMD_POST_DIAG #define CONFIG_CMD_SNTP #define CONFIG_CMD_USB +#ifdef CONFIG_POST + #define CONFIG_CMD_DIAG +#endif /* * Miscellaneous configurable options diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index f64c5222238..3d90efb1c17 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -82,11 +82,8 @@ CFG_POST_I2C) #ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG /* preserve space for the post_word at end of on-chip SRAM */ #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -#define CFG_CMD_POST_DIAG 0 #endif @@ -95,10 +92,6 @@ */ #include -#ifdef CONFIG_VIDEO -#define CONFIG_CMD_BMP -#endif - #define CONFIG_CMD_ASKENV #define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP @@ -112,12 +105,19 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_NFS #define CONFIG_CMD_PING -#define CONFIG_CMD_POST_DIAG #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SNTP #define CONFIG_CMD_BSP #define CONFIG_CMD_USB +#ifdef CONFIG_VIDEO +#define CONFIG_CMD_BMP +#endif + +#ifdef CONFIG_POST +#define CONFIG__CMD_DIAG +#endif + #define CONFIG_TIMESTAMP /* display image timestamps */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 24114b82d39..598c1c61c61 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -142,11 +142,8 @@ #endif #ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG /* preserve space for the post_word at end of on-chip SRAM */ #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -#define CFG_CMD_POST_DIAG 0 #endif @@ -164,7 +161,6 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_NFS #define CONFIG_CMD_PING -#define CONFIG_CMD_POST_DIAG #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SNTP #define CONFIG_CMD_BSP @@ -188,6 +184,10 @@ #define CONFIG_CFG_FAT #endif +#ifdef CONFIG_POST + #define CONFIG_CMD_DIAG +#endif + #define CONFIG_TIMESTAMP /* display image timestamps */ diff --git a/include/configs/aev.h b/include/configs/aev.h index ecd84d3e20c..93b20db5cea 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -86,11 +86,8 @@ CFG_POST_I2C) #ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG /* preserve space for the post_word at end of on-chip SRAM */ #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -#define CFG_CMD_POST_DIAG 0 #endif @@ -109,10 +106,13 @@ #define CONFIG_CMD_NFS #define CONFIG_CMD_PCI #define CONFIG_CMD_PING -#define CONFIG_CMD_POST #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SNTP +#ifdef CONFIG_POST +#define CONFIG_CMD_DIAG +#endif + #define CONFIG_TIMESTAMP /* display image timestamps */ diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index 36f55d164c8..bea157a45f6 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -144,11 +144,8 @@ #endif #ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG #define FLASH_START_POST_BLOCK 11 /* Should > = 11 */ #define FLASH_END_POST_BLOCK 71 /* Should < = 71 */ -#else -#define CFG_CMD_POST_DIAG 0 #endif /* CF-CARD IDE-HDD Support */ @@ -197,7 +194,10 @@ #if (BFIN_BOOT_MODE == BF537_BYPASS_BOOT) #define CONFIG_CMD_DHCP -#define CONFIG_CMD_POST_DIAG + +#if defined(CONFIG_POST) +#define CONFIG_CMD_DIAG +#endif #ifdef CONFIG_BF537_NAND #define CONFIG_CMD_NAND diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index 3dc7a8eb650..1db5e90965d 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -170,12 +170,6 @@ #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */ -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -#else -#define CFG_CMD_POST_DIAG 0 -#endif - /* * Command line configuration. @@ -192,9 +186,12 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE #define CONFIG_CMD_NFS -#define CONFIG_CMD_POST #define CONFIG_CMD_SNTP +#ifdef CONFIG_POST +#define CONFIG_CMD_DIAG +#endif + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h index 8d098579d79..a965e8ac8ee 100644 --- a/include/configs/smmaco4.h +++ b/include/configs/smmaco4.h @@ -60,11 +60,8 @@ CFG_POST_I2C) #ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG /* preserve space for the post_word at end of on-chip SRAM */ #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -#define CFG_CMD_POST_DIAG 0 #endif @@ -82,10 +79,13 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_NFS #define CONFIG_CMD_PING -#define CONFIG_CMD_POST #define CONFIG_CMD_REGINFO #define CONFIG_CMD_SNTP +#ifdef CONFIG_POST +#define CONFIG_CMD_DIAG +#endif + #define CONFIG_TIMESTAMP /* display image timestamps */ diff --git a/include/configs/spieval.h b/include/configs/spieval.h index e480df5f9c0..ccfcf1c8dc0 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -116,11 +116,8 @@ CFG_POST_I2C) #ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG /* preserve space for the post_word at end of on-chip SRAM */ #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#else -#define CFG_CMD_POST_DIAG 0 #endif @@ -129,6 +126,18 @@ */ #include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SNTP + #if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX) #define CONFIG_CMD_IDE #define CONFIG_CMD_FAT @@ -148,18 +157,9 @@ #define CONFIG_CMD_PCI #endif -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_POST -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP +#ifdef CONFIG_POST +#define CONFIG_CMD_DIAG +#endif #define CONFIG_TIMESTAMP /* display image timestamps */ diff --git a/include/configs/uc100.h b/include/configs/uc100.h index 2bdc55b4673..d223c58da32 100644 --- a/include/configs/uc100.h +++ b/include/configs/uc100.h @@ -117,12 +117,6 @@ CFG_POST_SPR ) #undef CONFIG_POST -#ifdef CONFIG_POST -#define CFG_CMD_POST_DIAG CFG_CMD_DIAG -#else -#define CFG_CMD_POST_DIAG 0 -#endif - /* * Command line configuration. @@ -140,9 +134,12 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_NFS #define CONFIG_CMD_PING -#define CONFIG_CMD_POST #define CONFIG_CMD_SNTP +#ifdef CONFIG_POST +#define CONFIG_CMD_DIAG +#endif + #define CONFIG_NETCONSOLE -- cgit v1.3.1 From 4ef218f6fdf8d747f4589da5252b004e7d2c2876 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 10 Jul 2007 00:01:28 +0200 Subject: Coding style cleanup; update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 369 ++++++++++++++++++++++++++++ board/esd/cpci405/cpci405.c | 68 ++---- board/pcs440ep/pcs440ep.c | 16 +- cpu/ppc4xx/start.S | 2 +- include/configs/pcs440ep.h | 4 +- include/sha1.h | 50 ++-- lib_generic/sha1.c | 569 +++++++++++++++++++++----------------------- post/cpu/ppc4xx/cache_4xx.S | 2 +- post/cpu/ppc4xx/fpu.c | 2 +- post/cpu/ppc4xx/spr.c | 13 +- tools/ubsha1.c | 9 +- 11 files changed, 716 insertions(+), 388 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index e3c21f9bd89..2397191fc97 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,133 @@ +commit f1152f8c28db4a22087c21c618a3f7baa48e9a4f +Author: Wolfgang Denk +Date: Fri Jul 6 02:50:19 2007 +0200 + + Code cleanup and default config update for STC GP3 SSA board. + + Signed-off-by: Wolfgang Denk + +commit b44896215a09c60fa40cae906f7ed207bbc2c492 +Author: Sergei Poselenov +Date: Thu Jul 5 08:17:37 2007 +0200 + + Merged POST framework with the current TOT. + + Signed-off-by: Sergei Poselenov + +commit f780b83316d9af1f61d71cc88b1917b387b9b995 +Author: Niklaus Giger +Date: Wed Jun 27 18:11:38 2007 +0200 + + resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPX + + Signed-off-by: Niklaus Giger + +commit 04e6c38b766eaa2f3287561563c9e215e0c3a0d4 +Author: Stefan Roese +Date: Wed Jul 4 10:06:30 2007 +0200 + + ppc4xx: Update lwmon5 board + + - Add optional ECC generation routine to preserve existing + RAM values. This is needed for the Linux log-buffer support + - Add optional DDR2 setup with CL=4 + - GPIO50 not used anymore + - Lime register setup added + + Signed-off-by: Stefan Roese + +commit 1f2a05898658900dc5717761e27abf2052e67e13 +Author: Mushtaq Khan +Date: Sat Jun 30 18:50:48 2007 +0200 + + Fix S-ATA support. + + Signed-off-by: mushtaq khan + +commit a5d71e290f3673269be8eefb4ec44f53412f9461 +Author: Heiko Schocher +Date: Mon Jun 25 19:11:37 2007 +0200 + + [PCS440EP] get rid of CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANG + + Signed-off-by: Heiko Schocher + +commit a1bd6200eccd3a02040a955d5f43d3ee1fc9f93b +Author: Niklaus Giger +Date: Mon Jun 25 17:03:13 2007 +0200 + + ppc4xx: PPC440EPx Emit DDR0 registers on machine check interrupt + + This patch prints the DDR status registers upon machine check + interrupt on the 440EPx/GRx. This can be useful especially when + ECC support is enabled. + + I added some small changes to the original patch from Niklaus to + make it compile clean. + + Signed-off-by: Niklaus Giger + Signed-off-by: Stefan Roese + +commit 807018fb7faceb429ce0cb47baa2073746b33a4e +Author: Niklaus Giger +Date: Mon Jun 25 16:50:55 2007 +0200 + + ppc4xx: Fix O=buildir builds + + This patch fixes the problem to assemble cpu/ppc4xx/start.S + experienced last week where building failed having specified + O=../build.sequoia. + + Signed-off-by: Niklaus Giger + +commit 466fff1a7bb5fe764a06450626f6098219f446b8 +Author: Stefan Roese +Date: Mon Jun 25 15:57:39 2007 +0200 + + ppc4xx: Add pci_pre_init() for 405 boards + + This patch removes the CFG_PCI_PRE_INIT option completely, since + it's not needed anymore with the patch from Matthias Fuchs with + the "weak" pci_pre_init() implementation. + + Signed-off-by: Stefan Roese + +commit 6f35c53166213c24a5a0e2390ed861136ff73870 +Author: Matthias Fuchs +Date: Sun Jun 24 17:41:21 2007 +0200 + + ppc4xx: Maintenance patch for esd's CPCI405 derivats + + -add pci_pre_init() for pci interrupt fixup code + -disable phy sleep mode via reset_phy() function + -use correct io accessors + -cleanup + + Signed-off-by: Matthias Fuchs + +commit 5a1c9ff0c44305b57cb4d8f9369bba90bcf0e1f8 +Author: Matthias Fuchs +Date: Sun Jun 24 17:23:41 2007 +0200 + + ppc4xx: Add pci_pre_init() for 405 boards + + This patch adds support for calling a plattform dependant + pci_pre_init() function for 405 boards. This can be used to + move the current pci_405gp_fixup_irq() function into the + board code. + + This patch also makes the CFG_PCI_PRE_INIT define obsolete. + A default function with 'weak' attribute is used when + a board specific pci_pre_init() is not implemented. + + Signed-off-by: Matthias Fuchs + +commit 1636d1c8529c006d106287cfbc20cd0a246fe1cb +Author: Wolfgang Denk +Date: Fri Jun 22 23:59:00 2007 +0200 + + Coding stylke cleanup; rebuild CHANGELOG + commit 2dc64451b4c08ffd619372abfdc2506a2e2363b9 Author: Igor Lisitsin Date: Wed Apr 18 14:55:19 2007 +0400 @@ -22,6 +152,34 @@ Date: Wed Mar 28 19:06:19 2007 +0400 Signed-off-by: Igor Lisitsin -- +commit 566a494f592ae3b3c0785d90d4e1ba45574880c4 +Author: Heiko Schocher +Date: Fri Jun 22 19:11:54 2007 +0200 + + [PCS440EP] upgrade the PCS440EP board: + - Show on the Status LEDs, some States of the board. + - Get the MAC addresses from the EEProm + - use PREBOOT + - use the CF on the board. + - check the U-Boot image in the Flash with a SHA1 + checksum. + - use dynamic TLB entries generation for the SDRAM + + Signed-off-by: Heiko Schocher + +commit 3a1f5c81b0b9557817a789bece839905581c2205 +Author: Stefan Roese +Date: Fri Jun 22 16:58:40 2007 +0200 + + ppc4xx: Fix problem with extended program_tlb() funtion + + The recently extended program_tlb() function had a problem when + multiple TLB's had to be setup (for example with 512MB of SDRAM). The + virtual address was not incremented. This patch fixes this issue + and is tested on Katmai with 512MB SDRAM. + + Signed-off-by: Stefan Roese + commit 02032e8f14751a1a751b09240a4f1cf9f8a2077f Author: Rafal Jaworowski Date: Fri Jun 22 14:58:04 2007 +0200 @@ -526,6 +684,14 @@ Date: Thu May 24 08:22:09 2007 +0200 Signed-off-by: Stefan Roese +commit 822d55365bb557e084d0e33625a6dedcc866110b +Author: Jon Loeliger +Date: Wed May 23 14:09:46 2007 -0500 + + Add LIST_86xx MAKEALL target for PowerPC builds. + + Signed-off-by: Jon Loeliger + commit 9f0077abd69f7a7c756a915b961037302be3e6f2 Author: Stefan Roese Date: Tue May 22 12:48:09 2007 +0200 @@ -574,6 +740,17 @@ Date: Fri May 18 14:33:11 2007 +0100 Makefile permissions +commit 255a3577c848706441daee0174543efe205a77f8 +Author: Kim Phillips +Date: Wed May 16 16:52:19 2007 -0500 + + Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx + + For all practical u-boot purposes, TSECs don't differ throughout the + mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx. + + Signed-off-by: Kim Phillips + commit 70124c2602ae2d4c5d3dba05b482d91548242de8 Author: Stefano Babic Date: Wed May 16 14:49:12 2007 +0200 @@ -615,6 +792,109 @@ Date: Wed May 16 00:13:33 2007 +0200 Coding Style Cleanup, new CHANGELOG +commit 3162eb836903c8b247fdc7470dd39bfa6996f495 +Author: Wolfgang Denk +Date: Tue May 15 23:38:05 2007 +0200 + + Minor coding style cleanup. + +commit 66d9dbec1cc27d6398ee6cf84639dbe14971251e +Author: mushtaq khan +Date: Fri Apr 20 14:23:02 2007 +0530 + + Add driver for S-ATA-controller on Intel processors with South + Bridge, ICH-5, ICH-6 and ICH-7. + + Implementation: + + 1. Code is divided in to two files. All functions, which are + controller specific are kept in "drivers/ata_piix.c" file and + functions, which are not controller specific, are kept in + "common/cmd_sata.c" file. + + 2. Reading and Writing from the S-ATA drive is done using PIO method. + + 3. Driver can be configured for 48-bit addressing by defining macro + CONFIG_LBA48, if this macro is not defined driver uses the 28-bit + addressing. + + 4. S-ATA read function is hooked to the File system, commands like + ext2ls and ext2load file can be used. This has been tested. + + 5. U-Boot command "SATA_init" is added, which initializes the S-ATA + controller and identifies the S-ATA drives connected to it. + + 6. U-Boot command "sata" is added, which is used to read/write, print + partition table and get info about the drives present. This I have + implemented in same way as "ide" command is implemented in U-Boot. + + 7. This driver is for S-ATA in native mode. + + 8. This driver does not support the Native command queuing and + Hot-plugging. + + Signed-off-by: Mushtaq Khan + +commit 644e6fb4eb8be90ea04ba34b643a8bf019d680e0 +Author: mushtaq khan +Date: Mon Apr 30 15:57:22 2007 +0530 + + Fixes bug clearing the bss section for i386 + + Hi, + There is a bug in the code of clearing the bss section for processor + i386.(File: cpu/i386/start.S) + In the code, bss_start addr (starting addr of bss section) is put into + the register %eax, but the code which clears the bss section refers to + the addr pointed by %edi. + + This patch fixes this bug by putting bss_start into %edi register. + + Signed-off-by: Mushtaq Khan + +commit c3243cf7b490057277d61acffe4ad0946f9eb4a4 +Author: Joe Hamman +Date: Mon Apr 30 16:47:28 2007 -0500 + + Add support for BCM5464 Quad Phy + + Added support for Broadcom's BCM5464 Quad Phy + + Signed-off-by: Joe Hamman + +commit 1b305bdc754c8468e1d5d858f5dcf8a7a0a4bb7a +Author: Zang Roy-r61911 +Date: Wed May 9 08:10:57 2007 +0800 + + Search the exception table with linear algorithm + + Search the exception table with linear algorithm instead of + bisecting algorithm. + Because the exception table might be unsorted. + + Signed-off-by: Roy Zang + +commit 5dfaa50eb819686bfba1927e8c5b8a70a4d65fd3 +Author: Aubrey.Li +Date: Mon May 14 11:47:35 2007 +0800 + + Fix compilation issues on MACOSX + + Singed-off-by: Marc Hoffman + Signed-off-by: Aubrey Li + +commit 56fd7162985c412317bbf763a225fba23c64fd31 +Author: Stephen Williams +Date: Tue May 15 07:55:42 2007 -0700 + + Fix for compile of JSE target + + The attached patch fixes the compile of the JSE board in the + denx git as of 14 may 2007. It is an extremely simple patch, + it just adds the missing define of CFG_SYSTEMACE_WIDTH. + + Fix to compile JSE against 20070514 git of u-boot + commit 61936667e86a250ae12fd2dc189d3588f0a59e0b Author: Stefan Roese Date: Fri May 11 12:01:49 2007 +0200 @@ -954,6 +1234,20 @@ Date: Sat May 5 08:29:01 2007 +0200 Signed-off-by: Stefan Roese +commit 2f550ab976405300f5b07bf2890800840d0aa05f +Author: Timur Tabi +Date: Sat May 5 08:12:30 2007 +0200 + + 5xxx: write MAC address to mac-address and local-mac-address + + Some device trees have a mac-address property, some have local-mac-address, + and some have both. To support all of these device trees, ftp_cpu_setup() + should write the MAC address to mac-address and local-mac-address, if they + exist. + + Signed-off-by: Timur Tabi + Acked-by: Grant Likely + commit a79886590593ba1d667c840caa4940c61639f18f Author: Thomas Knobloch Date: Sat May 5 07:04:42 2007 +0200 @@ -1117,12 +1411,35 @@ Date: Sun Apr 29 14:13:01 2007 +0200 Signed-off-by: Stefan Roese +commit 864aa6a6a466fcb92bf32b1d7dba79cd709b52c9 +Author: Grzegorz Wianecki +Date: Sun Apr 29 14:01:54 2007 +0200 + + [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message + + MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up + message. Use PVR to distinguish between the two variants, and print proper CPU + information. + + Signed-off-by: Grzegorz Wianecki + Signed-off-by: Bartlomiej Sieka + Signed-off-by: Grant Likely + commit 5c5d3242935cf3543af01142627494434834cf98 Author: Kim Phillips Date: Wed Apr 25 12:34:38 2007 -0500 mpc83xx: minor fixups for 8313rdb introduction +commit ada4d40091f6ed4a4f0040e08d20db21967e4a67 +Author: Ladislav Michl +Date: Wed Apr 25 16:01:26 2007 +0200 + + [PATCH] simplify silent console + + Signed-off-by: Ladislav Michl + Acked-by: Stefan Roese + commit 144876a380f5756f57412caf74c1d6dc201dd796 Author: Michal Simek Date: Tue Apr 24 23:01:02 2007 +0200 @@ -1419,6 +1736,58 @@ Date: Mon Apr 16 14:31:55 2007 -0500 Signed-off-by: Scott Wood +commit 7fc4c71a143be8666d70803fb25ae60379c95622 +Author: Stefan Roese +Date: Mon Apr 23 15:39:59 2007 +0200 + + Fix file mode + + Signed-off-by: Stefan Roese + +commit 38257988abfe74d459ca2ad748b109ca04e4efe1 +Author: Sergei Shtylyov +Date: Mon Apr 23 15:30:39 2007 +0200 + + [PATCH] Avoid assigning PCI resources from zero address + + If a PCI IDE card happens to get a zero address assigned to it, the Linux IDE + core complains and IDE drivers fails to work. Also, assigning zero to a BAR + was illegal according to PCI 2.1 (the later revisions seem to have excluded the + sentence about "0" being considered an invalid address) -- so, use a reasonable + starting value of 0x1000 (that's what the most Linux archs are using). + + Alternatively, one might have fixed the calls to pci_set_region() individually + (some code even seems to have taken care of this issue) but that would have + been a lot more work. :-) + + Signed-off-by: Sergei Shtylyov + Acked-by: Stefan Roese + +commit afb903a2eb9436baa9270ccc0c27082d86497d89 +Author: Jeffrey Mann +Date: Mon Apr 23 14:00:11 2007 +0200 + + [patch] setenv(...) can delete environmentalvariables + + update setenv() function so that entering a NULL value for the + variable's value will delete the environmental variable + + Signed-off-by: Jeffrey Mann + Acked-by: Stefan Roese + +commit 36f104e5caa747d568eff26b369565af57c2ffa6 +Author: Mike Frysinger +Date: Mon Apr 23 13:54:24 2007 +0200 + + [patch] use unsigned char in smc91111 driver for mac + + the v_mac variable in the smc91111 driver is declared as a signed char ... + this causes problems when one of the bytes in the MAC is "signed" like 0xE0 + because when it gets printed out, you get a display like: + 0xFFFFFFE0 and that's no good + + Signed-off-by: Mike Frysinger + commit 323bfa8f436dc3bc57187c9b1488bc3146ff1522 Author: Stefan Roese Date: Mon Apr 23 12:00:22 2007 +0200 diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c index 2ed0fc27220..69cb8cef562 100644 --- a/board/esd/cpci405/cpci405.c +++ b/board/esd/cpci405/cpci405.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; -extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/ +extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/ #if 0 #define FPGA_DEBUG #endif @@ -54,8 +54,6 @@ const unsigned char fpgadata[] = * include common fpga code (for esd boards) */ #include "../common/fpga.c" - - #include "../common/auto_update.h" #ifdef CONFIG_CPCI405AB @@ -88,13 +86,11 @@ au_image_t au_image[] = { int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0])); - /* Prototypes */ int cpci405_version(void); int gunzip(void *, int, unsigned char *, unsigned long *); void lxt971_no_sleep(void); - int board_early_init_f (void) { #ifndef CONFIG_CPCI405_VER2 @@ -113,10 +109,10 @@ int board_early_init_f (void) /* * First pull fpga-prg pin low, to disable fpga logic (on version 2 board) */ - out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ - out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ + out32(GPIO0_ODR, 0x00000000); /* no open drain pins */ + out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */ out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */ - out32(GPIO0_OR, 0); /* pull prg low */ + out32(GPIO0_OR, 0); /* pull prg low */ /* * Boot onboard FPGA @@ -178,51 +174,48 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive */ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr(uicer, 0x00000000); /* disable all ints */ - mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/ #ifdef CONFIG_CPCI405_6U if (cpci405_version() == 3) { - mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ + mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */ } else { - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ } #else - mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ + mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */ #endif - mtdcr(uictr, 0x10000000); /* set int trigger levels */ - mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ - mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uictr, 0x10000000); /* set int trigger levels */ + mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ return 0; } - /* ------------------------------------------------------------------------- */ int ctermm2(void) { #ifdef CONFIG_CPCI405_VER2 - return 0; /* no, board is cpci405 */ + return 0; /* no, board is cpci405 */ #else if ((*(unsigned char *)0xf0000400 == 0x00) && (*(unsigned char *)0xf0000401 == 0x01)) - return 0; /* no, board is cpci405 */ + return 0; /* no, board is cpci405 */ else - return -1; /* yes, board is cterm-m2 */ + return -1; /* yes, board is cterm-m2 */ #endif } - int cpci405_host(void) { if (mfdcr(strap) & PSR_PCI_ARBIT_EN) - return -1; /* yes, board is cpci405 host */ + return -1; /* yes, board is cpci405 host */ else - return 0; /* no, board is cpci405 adapter */ + return 0; /* no, board is cpci405 adapter */ } - int cpci405_version(void) { unsigned long cntrl0Reg; @@ -235,8 +228,8 @@ int cpci405_version(void) mtdcr(cntrl0, cntrl0Reg | 0x03000000); out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000); out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000); - udelay(1000); /* wait some time before reading input */ - value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ + udelay(1000); /* wait some time before reading input */ + value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */ /* * Restore GPIO settings @@ -262,13 +255,11 @@ int cpci405_version(void) } } - int misc_init_f (void) { return 0; /* dummy implementation */ } - int misc_init_r (void) { unsigned long cntrl0Reg; @@ -432,7 +423,6 @@ int misc_init_r (void) return (0); } - /* * Check Board Identity: */ @@ -488,7 +478,7 @@ int checkboard (void) } #ifndef CONFIG_CPCI405_VER2 - puts ("\nFPGA: "); + puts ("\nFPGA: "); /* display infos on fpgaimage */ index = 15; @@ -515,7 +505,6 @@ long int initdram (int board_type) return (4*1024*1024 << ((val & 0x000e0000) >> 17)); } - void reset_phy(void) { #ifdef CONFIG_LXT971_NO_SLEEP @@ -527,7 +516,6 @@ void reset_phy(void) #endif } - /* ------------------------------------------------------------------------- */ #ifdef CONFIG_CPCI405_VER2 @@ -550,7 +538,6 @@ void ide_set_reset(int on) #endif /* CONFIG_IDE_RESET */ #endif /* CONFIG_CPCI405_VER2 */ - #if defined(CONFIG_PCI) void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { @@ -585,14 +572,13 @@ int pci_pre_init(struct pci_controller *hose) #endif /* defined(CONFIG_PCI) */ - #ifdef CONFIG_CPCI405AB -#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ +#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ |= CFG_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ +#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \ &= ~CFG_FPGA_MODE_1WIRE_DIR) -#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \ +#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \ & CFG_FPGA_MODE_1WIRE) /* @@ -615,7 +601,6 @@ int OWTouchReset(void) return result; } - /* * Send 1 a 1-wire write bit. * Provide 10us recovery time. @@ -641,7 +626,6 @@ void OWWriteBit(int bit) } } - /* * Read a bit from the 1-wire bus and return it. * Provide 10us recovery time. @@ -661,7 +645,6 @@ int OWReadBit(void) return result; } - void OWWriteByte(int data) { int loop; @@ -672,7 +655,6 @@ void OWWriteByte(int data) } } - int OWReadByte(void) { int loop, result = 0; @@ -687,7 +669,6 @@ int OWReadByte(void) return result; } - int do_onewire(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { volatile unsigned short val; @@ -728,7 +709,6 @@ U_BOOT_CMD( NULL ); - #define CFG_I2C_EEPROM_ADDR_2 0x51 /* EEPROM CAT28WC32 */ #define CFG_ENV_SIZE_2 0x800 /* 2048 bytes may be used for env vars*/ diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index da907fbc345..ada6b82c927 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -197,14 +197,13 @@ void load_sernum_ethaddr (void) * - The checksum, stored in the last 2 Bytes, is correct */ if ((strncmp (buf,"ATR",3) != 0) || - ((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) || - ((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) - { + ((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) || + ((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) { /* EEprom is not programmed */ printf("%s: EEPROM Checksum not OK\n", __FUNCTION__); } else { /* get the MACs */ - sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x", + sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x", buf[3], buf[4], buf[5], @@ -212,7 +211,7 @@ void load_sernum_ethaddr (void) buf[7], buf[8]); setenv ("ethaddr", (char *) mac); - sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x", + sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x", buf[9], buf[10], buf[11], @@ -378,7 +377,7 @@ static int pcs440ep_sha1 (int docheck) org[i] = ptroff[i]; ptroff[i] = 0; } - + sha1_csum ((unsigned char *) data, len, (unsigned char *)output); if (docheck == 2) { @@ -796,7 +795,7 @@ int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) unsigned char output[20]; int len; int i; - + data = (unsigned char *)simple_strtoul (argv[1], NULL, 16); len = simple_strtoul (argv[2], NULL, 16); sha1_csum (data, len, (unsigned char *)output); @@ -823,7 +822,7 @@ int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else { rcode = pcs440ep_sha1 (0); } - return rcode; + return rcode; } return rcode; } @@ -861,4 +860,3 @@ void ide_set_reset (int idereset) udelay (10000); } #endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */ - diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 6086b6ceae4..8ecaaea4d9a 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1222,7 +1222,7 @@ mck_return: */ #ifdef CONFIG_440 .globl dcache_disable - .globl icache_disable + .globl icache_disable .globl icache_enable dcache_disable: icache_disable: diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 0e83e4881a4..69d97d66ea1 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -480,9 +480,9 @@ /* Offset for alternate registers */ #define CFG_ATA_ALT_OFFSET (0x0000) -/* This addresses need to be shifted one place to the left +/* These addresses need to be shifted one place to the left * ( bus per_addr 20 -30 is connectsd on CF bus A10-A0) - * This values are shifted + * These values are shifted */ #define CFG_ATA_PORT_ADDR(port) ((port) << 1) diff --git a/include/sha1.h b/include/sha1.h index 3030f2975f2..15ea13cd3a7 100644 --- a/include/sha1.h +++ b/include/sha1.h @@ -17,7 +17,7 @@ * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA + * MA 02110-1301 USA */ /* * The SHA-1 standard was published by NIST in 1993. @@ -35,76 +35,76 @@ extern "C" { #define SHA1_SUM_LEN 20 /** - * \brief SHA-1 context structure + * \brief SHA-1 context structure */ typedef struct { - unsigned long total[2]; /*!< number of bytes processed */ - unsigned long state[5]; /*!< intermediate digest state */ - unsigned char buffer[64]; /*!< data block being processed */ + unsigned long total[2]; /*!< number of bytes processed */ + unsigned long state[5]; /*!< intermediate digest state */ + unsigned char buffer[64]; /*!< data block being processed */ } sha1_context; /** - * \brief SHA-1 context setup + * \brief SHA-1 context setup * - * \param ctx SHA-1 context to be initialized + * \param ctx SHA-1 context to be initialized */ void sha1_starts( sha1_context *ctx ); /** - * \brief SHA-1 process buffer + * \brief SHA-1 process buffer * - * \param ctx SHA-1 context + * \param ctx SHA-1 context * \param input buffer holding the data - * \param ilen length of the input data + * \param ilen length of the input data */ void sha1_update( sha1_context *ctx, unsigned char *input, int ilen ); /** - * \brief SHA-1 final digest + * \brief SHA-1 final digest * - * \param ctx SHA-1 context + * \param ctx SHA-1 context * \param output SHA-1 checksum result */ void sha1_finish( sha1_context *ctx, unsigned char output[20] ); /** - * \brief Output = SHA-1( input buffer ) + * \brief Output = SHA-1( input buffer ) * * \param input buffer holding the data - * \param ilen length of the input data + * \param ilen length of the input data * \param output SHA-1 checksum result */ void sha1_csum( unsigned char *input, int ilen, - unsigned char output[20] ); + unsigned char output[20] ); /** - * \brief Output = SHA-1( file contents ) + * \brief Output = SHA-1( file contents ) * - * \param path input file name + * \param path input file name * \param output SHA-1 checksum result - * \return 0 if successful, or 1 if fopen failed + * \return 0 if successful, or 1 if fopen failed */ int sha1_file( char *path, unsigned char output[20] ); /** - * \brief Output = HMAC-SHA-1( input buffer, hmac key ) + * \brief Output = HMAC-SHA-1( input buffer, hmac key ) * - * \param key HMAC secret key + * \param key HMAC secret key * \param keylen length of the HMAC key * \param input buffer holding the data - * \param ilen length of the input data + * \param ilen length of the input data * \param output HMAC-SHA-1 result */ void sha1_hmac( unsigned char *key, int keylen, - unsigned char *input, int ilen, - unsigned char output[20] ); + unsigned char *input, int ilen, + unsigned char output[20] ); /** - * \brief Checkup routine + * \brief Checkup routine * - * \return 0 if successful, or 1 if the test failed + * \return 0 if successful, or 1 if the test failed */ int sha1_self_test( void ); diff --git a/lib_generic/sha1.c b/lib_generic/sha1.c index 0522d7ce67f..08ffa6b9bac 100644 --- a/lib_generic/sha1.c +++ b/lib_generic/sha1.c @@ -36,103 +36,99 @@ * 32-bit integer manipulation macros (big endian) */ #ifndef GET_UINT32_BE -#define GET_UINT32_BE(n,b,i) \ -{ \ - (n) = ( (unsigned long) (b)[(i) ] << 24 ) \ - | ( (unsigned long) (b)[(i) + 1] << 16 ) \ - | ( (unsigned long) (b)[(i) + 2] << 8 ) \ - | ( (unsigned long) (b)[(i) + 3] ); \ +#define GET_UINT32_BE(n,b,i) { \ + (n) = ( (unsigned long) (b)[(i) ] << 24 ) \ + | ( (unsigned long) (b)[(i) + 1] << 16 ) \ + | ( (unsigned long) (b)[(i) + 2] << 8 ) \ + | ( (unsigned long) (b)[(i) + 3] ); \ } #endif #ifndef PUT_UINT32_BE -#define PUT_UINT32_BE(n,b,i) \ -{ \ - (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ - (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ - (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ - (b)[(i) + 3] = (unsigned char) ( (n) ); \ +#define PUT_UINT32_BE(n,b,i) { \ + (b)[(i) ] = (unsigned char) ( (n) >> 24 ); \ + (b)[(i) + 1] = (unsigned char) ( (n) >> 16 ); \ + (b)[(i) + 2] = (unsigned char) ( (n) >> 8 ); \ + (b)[(i) + 3] = (unsigned char) ( (n) ); \ } #endif /* * SHA-1 context setup */ -void sha1_starts( sha1_context *ctx ) +void sha1_starts (sha1_context * ctx) { - ctx->total[0] = 0; - ctx->total[1] = 0; - - ctx->state[0] = 0x67452301; - ctx->state[1] = 0xEFCDAB89; - ctx->state[2] = 0x98BADCFE; - ctx->state[3] = 0x10325476; - ctx->state[4] = 0xC3D2E1F0; + ctx->total[0] = 0; + ctx->total[1] = 0; + + ctx->state[0] = 0x67452301; + ctx->state[1] = 0xEFCDAB89; + ctx->state[2] = 0x98BADCFE; + ctx->state[3] = 0x10325476; + ctx->state[4] = 0xC3D2E1F0; } -static void sha1_process( sha1_context *ctx, unsigned char data[64] ) +static void sha1_process (sha1_context * ctx, unsigned char data[64]) { - unsigned long temp, W[16], A, B, C, D, E; - - GET_UINT32_BE( W[0], data, 0 ); - GET_UINT32_BE( W[1], data, 4 ); - GET_UINT32_BE( W[2], data, 8 ); - GET_UINT32_BE( W[3], data, 12 ); - GET_UINT32_BE( W[4], data, 16 ); - GET_UINT32_BE( W[5], data, 20 ); - GET_UINT32_BE( W[6], data, 24 ); - GET_UINT32_BE( W[7], data, 28 ); - GET_UINT32_BE( W[8], data, 32 ); - GET_UINT32_BE( W[9], data, 36 ); - GET_UINT32_BE( W[10], data, 40 ); - GET_UINT32_BE( W[11], data, 44 ); - GET_UINT32_BE( W[12], data, 48 ); - GET_UINT32_BE( W[13], data, 52 ); - GET_UINT32_BE( W[14], data, 56 ); - GET_UINT32_BE( W[15], data, 60 ); - -#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n))) - -#define R(t) \ -( \ - temp = W[(t - 3) & 0x0F] ^ W[(t - 8) & 0x0F] ^ \ - W[(t - 14) & 0x0F] ^ W[ t & 0x0F], \ - ( W[t & 0x0F] = S(temp,1) ) \ + unsigned long temp, W[16], A, B, C, D, E; + + GET_UINT32_BE (W[0], data, 0); + GET_UINT32_BE (W[1], data, 4); + GET_UINT32_BE (W[2], data, 8); + GET_UINT32_BE (W[3], data, 12); + GET_UINT32_BE (W[4], data, 16); + GET_UINT32_BE (W[5], data, 20); + GET_UINT32_BE (W[6], data, 24); + GET_UINT32_BE (W[7], data, 28); + GET_UINT32_BE (W[8], data, 32); + GET_UINT32_BE (W[9], data, 36); + GET_UINT32_BE (W[10], data, 40); + GET_UINT32_BE (W[11], data, 44); + GET_UINT32_BE (W[12], data, 48); + GET_UINT32_BE (W[13], data, 52); + GET_UINT32_BE (W[14], data, 56); + GET_UINT32_BE (W[15], data, 60); + +#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n))) + +#define R(t) ( \ + temp = W[(t - 3) & 0x0F] ^ W[(t - 8) & 0x0F] ^ \ + W[(t - 14) & 0x0F] ^ W[ t & 0x0F], \ + ( W[t & 0x0F] = S(temp,1) ) \ ) -#define P(a,b,c,d,e,x) \ -{ \ - e += S(a,5) + F(b,c,d) + K + x; b = S(b,30); \ +#define P(a,b,c,d,e,x) { \ + e += S(a,5) + F(b,c,d) + K + x; b = S(b,30); \ } - A = ctx->state[0]; - B = ctx->state[1]; - C = ctx->state[2]; - D = ctx->state[3]; - E = ctx->state[4]; + A = ctx->state[0]; + B = ctx->state[1]; + C = ctx->state[2]; + D = ctx->state[3]; + E = ctx->state[4]; #define F(x,y,z) (z ^ (x & (y ^ z))) #define K 0x5A827999 - P( A, B, C, D, E, W[0] ); - P( E, A, B, C, D, W[1] ); - P( D, E, A, B, C, W[2] ); - P( C, D, E, A, B, W[3] ); - P( B, C, D, E, A, W[4] ); - P( A, B, C, D, E, W[5] ); - P( E, A, B, C, D, W[6] ); - P( D, E, A, B, C, W[7] ); - P( C, D, E, A, B, W[8] ); - P( B, C, D, E, A, W[9] ); - P( A, B, C, D, E, W[10] ); - P( E, A, B, C, D, W[11] ); - P( D, E, A, B, C, W[12] ); - P( C, D, E, A, B, W[13] ); - P( B, C, D, E, A, W[14] ); - P( A, B, C, D, E, W[15] ); - P( E, A, B, C, D, R(16) ); - P( D, E, A, B, C, R(17) ); - P( C, D, E, A, B, R(18) ); - P( B, C, D, E, A, R(19) ); + P (A, B, C, D, E, W[0]); + P (E, A, B, C, D, W[1]); + P (D, E, A, B, C, W[2]); + P (C, D, E, A, B, W[3]); + P (B, C, D, E, A, W[4]); + P (A, B, C, D, E, W[5]); + P (E, A, B, C, D, W[6]); + P (D, E, A, B, C, W[7]); + P (C, D, E, A, B, W[8]); + P (B, C, D, E, A, W[9]); + P (A, B, C, D, E, W[10]); + P (E, A, B, C, D, W[11]); + P (D, E, A, B, C, W[12]); + P (C, D, E, A, B, W[13]); + P (B, C, D, E, A, W[14]); + P (A, B, C, D, E, W[15]); + P (E, A, B, C, D, R (16)); + P (D, E, A, B, C, R (17)); + P (C, D, E, A, B, R (18)); + P (B, C, D, E, A, R (19)); #undef K #undef F @@ -140,26 +136,26 @@ static void sha1_process( sha1_context *ctx, unsigned char data[64] ) #define F(x,y,z) (x ^ y ^ z) #define K 0x6ED9EBA1 - P( A, B, C, D, E, R(20) ); - P( E, A, B, C, D, R(21) ); - P( D, E, A, B, C, R(22) ); - P( C, D, E, A, B, R(23) ); - P( B, C, D, E, A, R(24) ); - P( A, B, C, D, E, R(25) ); - P( E, A, B, C, D, R(26) ); - P( D, E, A, B, C, R(27) ); - P( C, D, E, A, B, R(28) ); - P( B, C, D, E, A, R(29) ); - P( A, B, C, D, E, R(30) ); - P( E, A, B, C, D, R(31) ); - P( D, E, A, B, C, R(32) ); - P( C, D, E, A, B, R(33) ); - P( B, C, D, E, A, R(34) ); - P( A, B, C, D, E, R(35) ); - P( E, A, B, C, D, R(36) ); - P( D, E, A, B, C, R(37) ); - P( C, D, E, A, B, R(38) ); - P( B, C, D, E, A, R(39) ); + P (A, B, C, D, E, R (20)); + P (E, A, B, C, D, R (21)); + P (D, E, A, B, C, R (22)); + P (C, D, E, A, B, R (23)); + P (B, C, D, E, A, R (24)); + P (A, B, C, D, E, R (25)); + P (E, A, B, C, D, R (26)); + P (D, E, A, B, C, R (27)); + P (C, D, E, A, B, R (28)); + P (B, C, D, E, A, R (29)); + P (A, B, C, D, E, R (30)); + P (E, A, B, C, D, R (31)); + P (D, E, A, B, C, R (32)); + P (C, D, E, A, B, R (33)); + P (B, C, D, E, A, R (34)); + P (A, B, C, D, E, R (35)); + P (E, A, B, C, D, R (36)); + P (D, E, A, B, C, R (37)); + P (C, D, E, A, B, R (38)); + P (B, C, D, E, A, R (39)); #undef K #undef F @@ -167,26 +163,26 @@ static void sha1_process( sha1_context *ctx, unsigned char data[64] ) #define F(x,y,z) ((x & y) | (z & (x | y))) #define K 0x8F1BBCDC - P( A, B, C, D, E, R(40) ); - P( E, A, B, C, D, R(41) ); - P( D, E, A, B, C, R(42) ); - P( C, D, E, A, B, R(43) ); - P( B, C, D, E, A, R(44) ); - P( A, B, C, D, E, R(45) ); - P( E, A, B, C, D, R(46) ); - P( D, E, A, B, C, R(47) ); - P( C, D, E, A, B, R(48) ); - P( B, C, D, E, A, R(49) ); - P( A, B, C, D, E, R(50) ); - P( E, A, B, C, D, R(51) ); - P( D, E, A, B, C, R(52) ); - P( C, D, E, A, B, R(53) ); - P( B, C, D, E, A, R(54) ); - P( A, B, C, D, E, R(55) ); - P( E, A, B, C, D, R(56) ); - P( D, E, A, B, C, R(57) ); - P( C, D, E, A, B, R(58) ); - P( B, C, D, E, A, R(59) ); + P (A, B, C, D, E, R (40)); + P (E, A, B, C, D, R (41)); + P (D, E, A, B, C, R (42)); + P (C, D, E, A, B, R (43)); + P (B, C, D, E, A, R (44)); + P (A, B, C, D, E, R (45)); + P (E, A, B, C, D, R (46)); + P (D, E, A, B, C, R (47)); + P (C, D, E, A, B, R (48)); + P (B, C, D, E, A, R (49)); + P (A, B, C, D, E, R (50)); + P (E, A, B, C, D, R (51)); + P (D, E, A, B, C, R (52)); + P (C, D, E, A, B, R (53)); + P (B, C, D, E, A, R (54)); + P (A, B, C, D, E, R (55)); + P (E, A, B, C, D, R (56)); + P (D, E, A, B, C, R (57)); + P (C, D, E, A, B, R (58)); + P (B, C, D, E, A, R (59)); #undef K #undef F @@ -194,169 +190,161 @@ static void sha1_process( sha1_context *ctx, unsigned char data[64] ) #define F(x,y,z) (x ^ y ^ z) #define K 0xCA62C1D6 - P( A, B, C, D, E, R(60) ); - P( E, A, B, C, D, R(61) ); - P( D, E, A, B, C, R(62) ); - P( C, D, E, A, B, R(63) ); - P( B, C, D, E, A, R(64) ); - P( A, B, C, D, E, R(65) ); - P( E, A, B, C, D, R(66) ); - P( D, E, A, B, C, R(67) ); - P( C, D, E, A, B, R(68) ); - P( B, C, D, E, A, R(69) ); - P( A, B, C, D, E, R(70) ); - P( E, A, B, C, D, R(71) ); - P( D, E, A, B, C, R(72) ); - P( C, D, E, A, B, R(73) ); - P( B, C, D, E, A, R(74) ); - P( A, B, C, D, E, R(75) ); - P( E, A, B, C, D, R(76) ); - P( D, E, A, B, C, R(77) ); - P( C, D, E, A, B, R(78) ); - P( B, C, D, E, A, R(79) ); + P (A, B, C, D, E, R (60)); + P (E, A, B, C, D, R (61)); + P (D, E, A, B, C, R (62)); + P (C, D, E, A, B, R (63)); + P (B, C, D, E, A, R (64)); + P (A, B, C, D, E, R (65)); + P (E, A, B, C, D, R (66)); + P (D, E, A, B, C, R (67)); + P (C, D, E, A, B, R (68)); + P (B, C, D, E, A, R (69)); + P (A, B, C, D, E, R (70)); + P (E, A, B, C, D, R (71)); + P (D, E, A, B, C, R (72)); + P (C, D, E, A, B, R (73)); + P (B, C, D, E, A, R (74)); + P (A, B, C, D, E, R (75)); + P (E, A, B, C, D, R (76)); + P (D, E, A, B, C, R (77)); + P (C, D, E, A, B, R (78)); + P (B, C, D, E, A, R (79)); #undef K #undef F - ctx->state[0] += A; - ctx->state[1] += B; - ctx->state[2] += C; - ctx->state[3] += D; - ctx->state[4] += E; + ctx->state[0] += A; + ctx->state[1] += B; + ctx->state[2] += C; + ctx->state[3] += D; + ctx->state[4] += E; } /* * SHA-1 process buffer */ -void sha1_update( sha1_context *ctx, unsigned char *input, int ilen ) +void sha1_update (sha1_context * ctx, unsigned char *input, int ilen) { - int fill; - unsigned long left; - - if( ilen <= 0 ) - return; - - left = ctx->total[0] & 0x3F; - fill = 64 - left; - - ctx->total[0] += ilen; - ctx->total[0] &= 0xFFFFFFFF; - - if( ctx->total[0] < (unsigned long) ilen ) - ctx->total[1]++; - - if( left && ilen >= fill ) - { - memcpy( (void *) (ctx->buffer + left), - (void *) input, fill ); - sha1_process( ctx, ctx->buffer ); - input += fill; - ilen -= fill; - left = 0; - } - - while( ilen >= 64 ) - { - sha1_process( ctx, input ); - input += 64; - ilen -= 64; - } - - if( ilen > 0 ) - { - memcpy( (void *) (ctx->buffer + left), - (void *) input, ilen ); - } + int fill; + unsigned long left; + + if (ilen <= 0) + return; + + left = ctx->total[0] & 0x3F; + fill = 64 - left; + + ctx->total[0] += ilen; + ctx->total[0] &= 0xFFFFFFFF; + + if (ctx->total[0] < (unsigned long) ilen) + ctx->total[1]++; + + if (left && ilen >= fill) { + memcpy ((void *) (ctx->buffer + left), (void *) input, fill); + sha1_process (ctx, ctx->buffer); + input += fill; + ilen -= fill; + left = 0; + } + + while (ilen >= 64) { + sha1_process (ctx, input); + input += 64; + ilen -= 64; + } + + if (ilen > 0) { + memcpy ((void *) (ctx->buffer + left), (void *) input, ilen); + } } -static const unsigned char sha1_padding[64] = -{ - 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +static const unsigned char sha1_padding[64] = { + 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; /* * SHA-1 final digest */ -void sha1_finish( sha1_context *ctx, unsigned char output[20] ) +void sha1_finish (sha1_context * ctx, unsigned char output[20]) { - unsigned long last, padn; - unsigned long high, low; - unsigned char msglen[8]; + unsigned long last, padn; + unsigned long high, low; + unsigned char msglen[8]; - high = ( ctx->total[0] >> 29 ) - | ( ctx->total[1] << 3 ); - low = ( ctx->total[0] << 3 ); + high = (ctx->total[0] >> 29) + | (ctx->total[1] << 3); + low = (ctx->total[0] << 3); - PUT_UINT32_BE( high, msglen, 0 ); - PUT_UINT32_BE( low, msglen, 4 ); + PUT_UINT32_BE (high, msglen, 0); + PUT_UINT32_BE (low, msglen, 4); - last = ctx->total[0] & 0x3F; - padn = ( last < 56 ) ? ( 56 - last ) : ( 120 - last ); + last = ctx->total[0] & 0x3F; + padn = (last < 56) ? (56 - last) : (120 - last); - sha1_update( ctx, (unsigned char *) sha1_padding, padn ); - sha1_update( ctx, msglen, 8 ); + sha1_update (ctx, (unsigned char *) sha1_padding, padn); + sha1_update (ctx, msglen, 8); - PUT_UINT32_BE( ctx->state[0], output, 0 ); - PUT_UINT32_BE( ctx->state[1], output, 4 ); - PUT_UINT32_BE( ctx->state[2], output, 8 ); - PUT_UINT32_BE( ctx->state[3], output, 12 ); - PUT_UINT32_BE( ctx->state[4], output, 16 ); + PUT_UINT32_BE (ctx->state[0], output, 0); + PUT_UINT32_BE (ctx->state[1], output, 4); + PUT_UINT32_BE (ctx->state[2], output, 8); + PUT_UINT32_BE (ctx->state[3], output, 12); + PUT_UINT32_BE (ctx->state[4], output, 16); } /* * Output = SHA-1( input buffer ) */ -void sha1_csum( unsigned char *input, int ilen, - unsigned char output[20] ) +void sha1_csum (unsigned char *input, int ilen, unsigned char output[20]) { - sha1_context ctx; + sha1_context ctx; - sha1_starts( &ctx ); - sha1_update( &ctx, input, ilen ); - sha1_finish( &ctx, output ); + sha1_starts (&ctx); + sha1_update (&ctx, input, ilen); + sha1_finish (&ctx, output); } /* * Output = HMAC-SHA-1( input buffer, hmac key ) */ -void sha1_hmac( unsigned char *key, int keylen, - unsigned char *input, int ilen, - unsigned char output[20] ) +void sha1_hmac (unsigned char *key, int keylen, + unsigned char *input, int ilen, unsigned char output[20]) { - int i; - sha1_context ctx; - unsigned char k_ipad[64]; - unsigned char k_opad[64]; - unsigned char tmpbuf[20]; - - memset( k_ipad, 0x36, 64 ); - memset( k_opad, 0x5C, 64 ); - - for( i = 0; i < keylen; i++ ) - { - if( i >= 64 ) break; - - k_ipad[i] ^= key[i]; - k_opad[i] ^= key[i]; - } - - sha1_starts( &ctx ); - sha1_update( &ctx, k_ipad, 64 ); - sha1_update( &ctx, input, ilen ); - sha1_finish( &ctx, tmpbuf ); - - sha1_starts( &ctx ); - sha1_update( &ctx, k_opad, 64 ); - sha1_update( &ctx, tmpbuf, 20 ); - sha1_finish( &ctx, output ); - - memset( k_ipad, 0, 64 ); - memset( k_opad, 0, 64 ); - memset( tmpbuf, 0, 20 ); - memset( &ctx, 0, sizeof( sha1_context ) ); + int i; + sha1_context ctx; + unsigned char k_ipad[64]; + unsigned char k_opad[64]; + unsigned char tmpbuf[20]; + + memset (k_ipad, 0x36, 64); + memset (k_opad, 0x5C, 64); + + for (i = 0; i < keylen; i++) { + if (i >= 64) + break; + + k_ipad[i] ^= key[i]; + k_opad[i] ^= key[i]; + } + + sha1_starts (&ctx); + sha1_update (&ctx, k_ipad, 64); + sha1_update (&ctx, input, ilen); + sha1_finish (&ctx, tmpbuf); + + sha1_starts (&ctx); + sha1_update (&ctx, k_opad, 64); + sha1_update (&ctx, tmpbuf, 20); + sha1_finish (&ctx, output); + + memset (k_ipad, 0, 64); + memset (k_opad, 0, 64); + memset (tmpbuf, 0, 20); + memset (&ctx, 0, sizeof (sha1_context)); } static const char _sha1_src[] = "_sha1_src"; @@ -365,66 +353,61 @@ static const char _sha1_src[] = "_sha1_src"; /* * FIPS-180-1 test vectors */ -static const char sha1_test_str[3][57] = -{ - { "abc" }, - { "abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq" }, - { "" } +static const char sha1_test_str[3][57] = { + {"abc"}, + {"abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopq"}, + {""} }; -static const unsigned char sha1_test_sum[3][20] = -{ - { 0xA9, 0x99, 0x3E, 0x36, 0x47, 0x06, 0x81, 0x6A, 0xBA, 0x3E, - 0x25, 0x71, 0x78, 0x50, 0xC2, 0x6C, 0x9C, 0xD0, 0xD8, 0x9D }, - { 0x84, 0x98, 0x3E, 0x44, 0x1C, 0x3B, 0xD2, 0x6E, 0xBA, 0xAE, - 0x4A, 0xA1, 0xF9, 0x51, 0x29, 0xE5, 0xE5, 0x46, 0x70, 0xF1 }, - { 0x34, 0xAA, 0x97, 0x3C, 0xD4, 0xC4, 0xDA, 0xA4, 0xF6, 0x1E, - 0xEB, 0x2B, 0xDB, 0xAD, 0x27, 0x31, 0x65, 0x34, 0x01, 0x6F } +static const unsigned char sha1_test_sum[3][20] = { + {0xA9, 0x99, 0x3E, 0x36, 0x47, 0x06, 0x81, 0x6A, 0xBA, 0x3E, + 0x25, 0x71, 0x78, 0x50, 0xC2, 0x6C, 0x9C, 0xD0, 0xD8, 0x9D}, + {0x84, 0x98, 0x3E, 0x44, 0x1C, 0x3B, 0xD2, 0x6E, 0xBA, 0xAE, + 0x4A, 0xA1, 0xF9, 0x51, 0x29, 0xE5, 0xE5, 0x46, 0x70, 0xF1}, + {0x34, 0xAA, 0x97, 0x3C, 0xD4, 0xC4, 0xDA, 0xA4, 0xF6, 0x1E, + 0xEB, 0x2B, 0xDB, 0xAD, 0x27, 0x31, 0x65, 0x34, 0x01, 0x6F} }; /* * Checkup routine */ -int sha1_self_test( void ) +int sha1_self_test (void) { - int i, j; - unsigned char buf[1000]; - unsigned char sha1sum[20]; - sha1_context ctx; - - for( i = 0; i < 3; i++ ) - { - printf( " SHA-1 test #%d: ", i + 1 ); - - sha1_starts( &ctx ); - - if( i < 2 ) - sha1_update( &ctx, (unsigned char *) sha1_test_str[i], - strlen( sha1_test_str[i] ) ); - else - { - memset( buf, 'a', 1000 ); - for( j = 0; j < 1000; j++ ) - sha1_update( &ctx, buf, 1000 ); - } - - sha1_finish( &ctx, sha1sum ); - - if( memcmp( sha1sum, sha1_test_sum[i], 20 ) != 0 ) - { - printf( "failed\n" ); - return( 1 ); - } - - printf( "passed\n" ); - } - - printf( "\n" ); - return( 0 ); + int i, j; + unsigned char buf[1000]; + unsigned char sha1sum[20]; + sha1_context ctx; + + for (i = 0; i < 3; i++) { + printf (" SHA-1 test #%d: ", i + 1); + + sha1_starts (&ctx); + + if (i < 2) + sha1_update (&ctx, (unsigned char *) sha1_test_str[i], + strlen (sha1_test_str[i])); + else { + memset (buf, 'a', 1000); + for (j = 0; j < 1000; j++) + sha1_update (&ctx, buf, 1000); + } + + sha1_finish (&ctx, sha1sum); + + if (memcmp (sha1sum, sha1_test_sum[i], 20) != 0) { + printf ("failed\n"); + return (1); + } + + printf ("passed\n"); + } + + printf ("\n"); + return (0); } #else -int sha1_self_test( void ) +int sha1_self_test (void) { - return( 0 ); + return (0); } #endif diff --git a/post/cpu/ppc4xx/cache_4xx.S b/post/cpu/ppc4xx/cache_4xx.S index 785b8d60b93..dddd76b2355 100644 --- a/post/cpu/ppc4xx/cache_4xx.S +++ b/post/cpu/ppc4xx/cache_4xx.S @@ -438,7 +438,7 @@ cache_post_test6_reloc: blr /* Test instructions. - */ + */ cache_post_test_inst: li r3, 0 li r3, -1 diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c index c2eb4a9bf0b..27e9ed01afc 100644 --- a/post/cpu/ppc4xx/fpu.c +++ b/post/cpu/ppc4xx/fpu.c @@ -37,7 +37,7 @@ int fpu_status(void) { if (mfspr(ccr0) & CCR0_DAPUIB) return 0; /* Disabled */ - else + else return 1; /* Enabled */ } diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c index be5a701f317..3e746343d15 100644 --- a/post/cpu/ppc4xx/spr.c +++ b/post/cpu/ppc4xx/spr.c @@ -43,12 +43,11 @@ #include -static struct -{ - int number; - char * name; - unsigned long mask; - unsigned long value; +static struct { + int number; + char * name; + unsigned long mask; + unsigned long value; } spr_test_list [] = { /* Standard Special-Purpose Registers */ @@ -65,7 +64,7 @@ static struct {0x11f, "PVR", 0x00000000, 0x00000000}, /* Additional Special-Purpose Registers. - * The values must match the initialization + * The values must match the initialization * values from cpu/ppc4xx/start.S */ {0x30, "PID", 0x00000000, 0x00000000}, diff --git a/tools/ubsha1.c b/tools/ubsha1.c index bc877606d2f..b37b2b72242 100644 --- a/tools/ubsha1.c +++ b/tools/ubsha1.c @@ -84,7 +84,7 @@ int main (int argc, char **argv) cmdname, imagefile, strerror(errno)); exit (EXIT_FAILURE); } - + /* create a copy, so we can blank out the sha1 sum */ data = malloc (len); memcpy (data, ptr, len); @@ -93,12 +93,11 @@ int main (int argc, char **argv) for (i = 0; i < SHA1_SUM_LEN; i++) { ptroff[i] = 0; } - + sha1_csum ((unsigned char *) data, len, (unsigned char *)output); printf ("U-Boot sum:\n"); - for (i = 0; i < 20 ; i++) - { + for (i = 0; i < 20 ; i++) { printf ("%02X ", output[i]); } printf ("\n"); @@ -109,7 +108,7 @@ int main (int argc, char **argv) cmdname, imagefile, strerror(errno)); exit (EXIT_FAILURE); } - + free (data); (void) munmap((void *)ptr, len); (void) close (ifd); -- cgit v1.3.1 From 639221c76c88215bd55af83ad174fc30d1940f8f Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 9 Jul 2007 17:15:49 -0500 Subject: include/: Remove obsolete references to CONFIG_COMMANDS Mostly removed from comments here. Signed-off-by: Jon Loeliger --- include/_exports.h | 2 +- include/configs/CPU86.h | 4 +--- include/configs/CPU87.h | 4 +--- include/configs/IDS8247.h | 4 +--- include/configs/IPHASE4539.h | 3 +-- include/configs/ISPAN.h | 3 +-- include/configs/MPC8260ADS.h | 3 +-- include/configs/MPC8266ADS.h | 3 +-- include/configs/PM826.h | 3 +-- include/configs/PM828.h | 3 +-- include/configs/RPXsuper.h | 3 +-- include/configs/Rattler.h | 4 ++-- include/configs/SCM.h | 3 +-- include/configs/TQM8260.h | 3 +-- include/configs/TQM8272.h | 3 +-- include/configs/VoVPN-GW.h | 3 +-- include/configs/ZPC1900.h | 4 ++-- include/configs/atc.h | 4 +--- include/configs/cogent_mpc8260.h | 3 +-- include/configs/ep8248.h | 4 ++-- include/configs/ep8260.h | 3 +-- include/configs/ep82xxm.h | 4 ++-- include/configs/gw8260.h | 3 +-- include/configs/hymod.h | 3 +-- include/configs/ppmc8260.h | 3 +-- include/configs/rsdproto.h | 3 +-- include/configs/sacsng.h | 3 +-- include/configs/sbc8260.h | 3 +-- include/configs/sc3.h | 3 +-- include/exports.h | 2 +- include/lcd.h | 4 ++-- include/mk48t59.h | 2 +- include/net.h | 6 +++--- include/pcmcia.h | 6 +++--- 34 files changed, 43 insertions(+), 71 deletions(-) (limited to 'include') diff --git a/include/_exports.h b/include/_exports.h index a5799838e00..eeb65f40ae4 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -15,7 +15,7 @@ EXPORT_FUNC(do_reset) EXPORT_FUNC(getenv) EXPORT_FUNC(setenv) EXPORT_FUNC(simple_strtoul) -#if (CONFIG_COMMANDS & CFG_CMD_I2C) || defined(CONFIG_CMD_I2C) +#if defined(CONFIG_CMD_I2C) EXPORT_FUNC(i2c_write) EXPORT_FUNC(i2c_read) #endif /* CFG_CMD_I2C */ diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index 631c78e6ee8..202914b1f9d 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -68,9 +68,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - * + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h index 666cb1307d4..ce25aa58fce 100644 --- a/include/configs/CPU87.h +++ b/include/configs/CPU87.h @@ -69,9 +69,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - * + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 45a96ae787d..e26dc5666a1 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -128,9 +128,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - * + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h index 383ffe2e23f..1cb2d6b5121 100644 --- a/include/configs/IPHASE4539.h +++ b/include/configs/IPHASE4539.h @@ -67,8 +67,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h index 75dea18f571..e6ef7656629 100644 --- a/include/configs/ISPAN.h +++ b/include/configs/ISPAN.h @@ -58,8 +58,7 @@ * for FCC). * * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must - * be defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */ #define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */ diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index b41866fcf57..a36b69d6bbd 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -101,8 +101,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index 306ee49eb4d..a8c40cf0709 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -83,8 +83,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ diff --git a/include/configs/PM826.h b/include/configs/PM826.h index a93400d9920..57d46acbc84 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -103,8 +103,7 @@ * - CONFIG_NET_MULTI must be defined * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #define CONFIG_NET_MULTI #undef CONFIG_ETHER_NONE /* define if ether on something else */ diff --git a/include/configs/PM828.h b/include/configs/PM828.h index 5095a050ac5..3f1bb8e40d5 100644 --- a/include/configs/PM828.h +++ b/include/configs/PM828.h @@ -103,8 +103,7 @@ * - CONFIG_NET_MULTI must be defined * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #define CONFIG_NET_MULTI #undef CONFIG_ETHER_NONE /* define if ether on something else */ diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h index c39aff19bc0..1401da35abc 100644 --- a/include/configs/RPXsuper.h +++ b/include/configs/RPXsuper.h @@ -91,8 +91,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h index 5c6431487c4..5bdf57193be 100644 --- a/include/configs/Rattler.h +++ b/include/configs/Rattler.h @@ -62,8 +62,8 @@ * SCC, 1-3 for FCC) * * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CFG_CMD_NET must - * be removed from CONFIG_COMMANDS to remove support for networking. + * must be defined elsewhere (as for the console), or CONFIG_CMD_NET + * must be unset. */ #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ diff --git a/include/configs/SCM.h b/include/configs/SCM.h index 67dbc55dbb5..46861f838f2 100644 --- a/include/configs/SCM.h +++ b/include/configs/SCM.h @@ -133,8 +133,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. * * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the * X.29 connector, and FCC2 is hardwired to the X.1 connector) diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index 3089fefc31f..ee5e6f76250 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -167,8 +167,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. * * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the * X.29 connector, and FCC2 is hardwired to the X.1 connector) diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h index b7a1baebcf4..a55aec27672 100644 --- a/include/configs/TQM8272.h +++ b/include/configs/TQM8272.h @@ -177,8 +177,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. * * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the * X.29 connector, and FCC2 is hardwired to the X.1 connector) diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h index 88062441969..ebe634f133c 100644 --- a/include/configs/VoVPN-GW.h +++ b/include/configs/VoVPN-GW.h @@ -95,8 +95,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC #define CONFIG_ETHER_ON_FCC diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index 30c7790c877..fb5bc0fdb3b 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -55,8 +55,8 @@ * SCC, 1-3 for FCC) * * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CFG_CMD_NET must - * be removed from CONFIG_COMMANDS to remove support for networking. + * must be defined elsewhere (as for the console), or CONFIG_CMD_NET + * must be unset. */ #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ diff --git a/include/configs/atc.h b/include/configs/atc.h index cb4e7472ec7..4f527fa40d5 100644 --- a/include/configs/atc.h +++ b/include/configs/atc.h @@ -64,9 +64,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - * + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #undef CONFIG_ETHER_NONE /* define if ether on something else */ diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h index ac1baf3b4e5..63150902c87 100644 --- a/include/configs/cogent_mpc8260.h +++ b/include/configs/cogent_mpc8260.h @@ -71,8 +71,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h index 44c4388b208..8653b55affe 100644 --- a/include/configs/ep8248.h +++ b/include/configs/ep8248.h @@ -60,8 +60,8 @@ * SCC, 1-3 for FCC) * * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CFG_CMD_NET must - * be removed from CONFIG_COMMANDS to remove support for networking. + * must be defined elsewhere (as for the console), or CONFIG_CMD_NET + * must be unset. */ #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h index 065f967e173..25f9bd6a718 100644 --- a/include/configs/ep8260.h +++ b/include/configs/ep8260.h @@ -183,8 +183,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index 5fa70164e94..430ff4b8f48 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h @@ -60,8 +60,8 @@ * SCC, 1-3 for FCC) * * If CONFIG_ETHER_NONE is defined, then either the ethernet routines - * must be defined elsewhere (as for the console), or CFG_CMD_NET must - * be removed from CONFIG_COMMANDS to remove support for networking. + * must be defined elsewhere (as for the console), or CONFIG_CMD_NET + * must be unset. */ #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index cf3eb3f5a47..a8bc928b63b 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -194,8 +194,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC diff --git a/include/configs/hymod.h b/include/configs/hymod.h index 0fdfb1523e5..8a3ad6861e4 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -69,8 +69,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h index d99da2fdbcf..610fcfdfedd 100644 --- a/include/configs/ppmc8260.h +++ b/include/configs/ppmc8260.h @@ -169,8 +169,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h index 5ea76fe9bf9..93f5c6be8d8 100644 --- a/include/configs/rsdproto.h +++ b/include/configs/rsdproto.h @@ -64,8 +64,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index dc258312884..41f1f25fce0 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -159,8 +159,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h index 2a209d32b96..bf6dab23d3c 100644 --- a/include/configs/sbc8260.h +++ b/include/configs/sbc8260.h @@ -182,8 +182,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 578ef80aa62..9709fe292c2 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -68,8 +68,7 @@ * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range * If undefined, IDE access uses a seperat emulation with higher access speed. * Consider to inform your Linux IDE driver about the different addresses! - * IDE_USES_ISA_EMULATION is only used if your CONFIG_COMMANDS macro includes - * the CFG_CMD_IDE macro! + * IDE_USES_ISA_EMULATION is only used if you define CONFIG_CMD_IDE! */ #define IDE_USES_ISA_EMULATION diff --git a/include/exports.h b/include/exports.h index 8a9b314cd40..ad20502a67a 100644 --- a/include/exports.h +++ b/include/exports.h @@ -23,7 +23,7 @@ void do_reset (void); unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base); char *getenv (char *name); void setenv (char *varname, char *varvalue); -#if (CONFIG_COMMANDS & CFG_CMD_I2C) || defined(CONFIG_CMD_I2C) +#if defined(CONFIG_CMD_I2C) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); #endif /* CFG_CMD_I2C */ diff --git a/include/lcd.h b/include/lcd.h index f0ec76aa3b0..8a4273cce15 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -173,10 +173,10 @@ void lcd_printf (const char *fmt, ...); /************************************************************************/ /* ** BITMAP DISPLAY SUPPORT */ /************************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_BMP) || defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) +#if defined(CONFIG_CMD_BMP) || defined(CONFIG_SPLASH_SCREEN) # include # include -#endif /* (CONFIG_COMMANDS & CFG_CMD_BMP) || CONFIG_SPLASH_SCREEN */ +#endif /* * Information about displays we are using. This is for configuring diff --git a/include/mk48t59.h b/include/mk48t59.h index fbdb9f9d12d..a4459c092c2 100644 --- a/include/mk48t59.h +++ b/include/mk48t59.h @@ -26,7 +26,7 @@ */ -#if defined(CONFIG_RTC_MK48T59) && ((CONFIG_COMMANDS & CFG_CMD_DATE) || defined(CONFIG_CMD_DATE)) +#if defined(CONFIG_RTC_MK48T59) && defined(CONFIG_CMD_DATE) #define RTC_PORT_ADDR0 CFG_ISA_IO + 0x70 #define RTC_PORT_ADDR1 RTC_PORT_ADDR0 + 0x1 diff --git a/include/net.h b/include/net.h index 853f55a758e..f6f33fff91a 100644 --- a/include/net.h +++ b/include/net.h @@ -341,17 +341,17 @@ typedef enum { BOOTP, RARP, ARP, TFTP, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP /* from net/net.c */ extern char BootFile[128]; /* Boot File name */ -#if (CONFIG_COMMANDS & CFG_CMD_PING) || defined(CONFIG_CMD_PING) +#if defined(CONFIG_CMD_PING) extern IPaddr_t NetPingIP; /* the ip address to ping */ #endif -#if (CONFIG_COMMANDS & CFG_CMD_CDP) || defined(CONFIG_CMD_CDP) +#if defined(CONFIG_CMD_CDP) /* when CDP completes these hold the return values */ extern ushort CDPNativeVLAN; extern ushort CDPApplianceVLAN; #endif -#if (CONFIG_COMMANDS & CFG_CMD_SNTP) || defined(CONFIG_CMD_SNTP) +#if defined(CONFIG_CMD_SNTP) extern IPaddr_t NetNtpServerIP; /* the ip address to NTP */ extern int NetTimeOffset; /* offset time from UTC */ #endif diff --git a/include/pcmcia.h b/include/pcmcia.h index 60794f90ec9..c028ab735db 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -31,8 +31,8 @@ * Allow configuration to select PCMCIA slot, * or try to generate a useful default */ -#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA) || \ - (((CONFIG_COMMANDS & CFG_CMD_IDE) || defined(CONFIG_CMD_IDE)) && \ +#if defined(CONFIG_CMD_PCMCIA) || \ + (defined(CONFIG_CMD_IDE) && \ (defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT) ) ) #if !defined(CONFIG_PCMCIA_SLOT_A) && !defined(CONFIG_PCMCIA_SLOT_B) @@ -313,7 +313,7 @@ extern u_int *pcmcia_pgcrx[]; #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) #endif -#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD) \ +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) \ || defined(CONFIG_PXA_PCMCIA) extern int check_ide_device(int slot); #endif -- cgit v1.3.1 From f55f7f8d83f36021ab1f0e3d738f5d8c8083a7e3 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 9 Jul 2007 19:12:30 -0500 Subject: Retire CONFIG_COMMANDS finally. Strip old CFG_CMD_* symbols out. Signed-off-by: Jon Loeliger --- include/cmd_confdefs.h | 130 ------------------------------------------------- 1 file changed, 130 deletions(-) (limited to 'include') diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h index 9b4545f7b60..3bfb2aed396 100644 --- a/include/cmd_confdefs.h +++ b/include/cmd_confdefs.h @@ -21,139 +21,9 @@ * MA 02111-1307 USA */ -/* - * Definitions for Configuring the monitor commands - */ #ifndef _CMD_CONFIG_H #define _CMD_CONFIG_H -/* - * Configurable monitor commands - */ -#define CFG_CMD_BDI 0x00000001ULL /* bdinfo */ -#define CFG_CMD_LOADS 0x00000002ULL /* loads */ -#define CFG_CMD_LOADB 0x00000004ULL /* loadb */ -#define CFG_CMD_IMI 0x00000008ULL /* iminfo */ -#define CFG_CMD_CACHE 0x00000010ULL /* icache, dcache */ -#define CFG_CMD_FLASH 0x00000020ULL /* flinfo, erase, protect */ -#define CFG_CMD_MEMORY 0x00000040ULL /* md, mm, nm, mw, cp, cmp, */ - /* crc, base, loop, mtest */ -#define CFG_CMD_NET 0x00000080ULL /* bootp, tftpboot, rarpboot */ -#define CFG_CMD_ENV 0x00000100ULL /* saveenv */ -#define CFG_CMD_KGDB 0x0000000000000200ULL /* kgdb */ -#define CFG_CMD_PCMCIA 0x00000400ULL /* PCMCIA support */ -#define CFG_CMD_IDE 0x00000800ULL /* IDE harddisk support */ -#define CFG_CMD_PCI 0x00001000ULL /* pciinfo */ -#define CFG_CMD_IRQ 0x00002000ULL /* irqinfo */ -#define CFG_CMD_BOOTD 0x00004000ULL /* bootd */ -#define CFG_CMD_CONSOLE 0x00008000ULL /* coninfo */ -#define CFG_CMD_EEPROM 0x00010000ULL /* EEPROM read/write support */ -#define CFG_CMD_ASKENV 0x00020000ULL /* ask for env variable */ -#define CFG_CMD_RUN 0x00040000ULL /* run command in env variable */ -#define CFG_CMD_ECHO 0x00080000ULL /* echo arguments */ -#define CFG_CMD_I2C 0x00100000ULL /* I2C serial bus support */ -#define CFG_CMD_REGINFO 0x00200000ULL /* Register dump */ -#define CFG_CMD_IMMAP 0x00400000ULL /* IMMR dump support */ -#define CFG_CMD_DATE 0x00800000ULL /* support for RTC, date/time...*/ -#define CFG_CMD_DHCP 0x01000000ULL /* DHCP Support */ -#define CFG_CMD_BEDBUG 0x02000000ULL /* Include BedBug Debugger */ -#define CFG_CMD_FDC 0x04000000ULL /* Floppy Disk Support */ -#define CFG_CMD_SCSI 0x08000000ULL /* SCSI Support */ -#define CFG_CMD_AUTOSCRIPT 0x10000000ULL /* Autoscript Support */ -#define CFG_CMD_MII 0x20000000ULL /* MII support */ -#define CFG_CMD_SETGETDCR 0x40000000ULL /* DCR support on 4xx */ -#define CFG_CMD_BSP 0x80000000ULL /* Board Specific functions */ - -#define CFG_CMD_ELF 0x0000000100000000ULL /* ELF (VxWorks) load/boot cmd */ -#define CFG_CMD_MISC 0x0000000200000000ULL /* Misc functions like sleep etc*/ -#define CFG_CMD_USB 0x0000000400000000ULL /* USB Support */ -#define CFG_CMD_DOC 0x0000000800000000ULL /* Disk-On-Chip Support */ -#define CFG_CMD_JFFS2 0x0000001000000000ULL /* JFFS2 Support */ -#define CFG_CMD_DTT 0x0000002000000000ULL /* Digital Therm and Thermostat */ -#define CFG_CMD_SDRAM 0x0000004000000000ULL /* SDRAM DIMM SPD info printout */ -#define CFG_CMD_DIAG 0x0000008000000000ULL /* Diagnostics */ -#define CFG_CMD_FPGA 0x0000010000000000ULL /* FPGA configuration Support */ -#define CFG_CMD_HWFLOW 0x0000020000000000ULL /* RTS/CTS hw flow control */ -#define CFG_CMD_SAVES 0x0000040000000000ULL /* save S record dump */ -#define CFG_CMD_SPI 0x0000100000000000ULL /* SPI utility */ -#define CFG_CMD_FDOS 0x0000200000000000ULL /* Floppy DOS support */ -#define CFG_CMD_VFD 0x0000400000000000ULL /* VFD support (TRAB) */ -#define CFG_CMD_NAND 0x0000800000000000ULL /* NAND support */ -#define CFG_CMD_BMP 0x0001000000000000ULL /* BMP support */ -#define CFG_CMD_PORTIO 0x0002000000000000ULL /* Port I/O */ -#define CFG_CMD_PING 0x0004000000000000ULL /* ping support */ -#define CFG_CMD_MMC 0x0008000000000000ULL /* MMC support */ -#define CFG_CMD_FAT 0x0010000000000000ULL /* FAT support */ -#define CFG_CMD_IMLS 0x0020000000000000ULL /* List all found images */ -#define CFG_CMD_ITEST 0x0040000000000000ULL /* Integer (and string) test */ -#define CFG_CMD_NFS 0x0080000000000000ULL /* NFS support */ -#define CFG_CMD_REISER 0x0100000000000000ULL /* Reiserfs support */ -#define CFG_CMD_CDP 0x0200000000000000ULL /* Cisco Discovery Protocol */ -#define CFG_CMD_XIMG 0x0400000000000000ULL /* Load part of Multi Image */ -#define CFG_CMD_UNIVERSE 0x0800000000000000ULL /* Tundra Universe Support */ -#define CFG_CMD_EXT2 0x1000000000000000ULL /* EXT2 Support */ -#define CFG_CMD_SNTP 0x2000000000000000ULL /* SNTP support */ -#define CFG_CMD_DISPLAY 0x4000000000000000ULL /* Display support */ -#define CFG_CMD_MFSL 0x8000000000000000ULL /* FSL support for Microblaze */ - -#define CFG_CMD_ALL 0xFFFFFFFFFFFFFFFFULL /* ALL commands */ - -/* Commands that are considered "non-standard" for some reason - * (memory hogs, requires special hardware, not fully tested, etc.) - */ -#define CFG_CMD_NONSTD (CFG_CMD_ASKENV | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_CACHE | \ - CFG_CMD_CDP | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_DISPLAY | \ - CFG_CMD_DOC | \ - CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_EXT2 | \ - CFG_CMD_FDC | \ - CFG_CMD_FAT | \ - CFG_CMD_FDOS | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_I2C | \ - CFG_CMD_IDE | \ - CFG_CMD_IMMAP | \ - CFG_CMD_IRQ | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_KGDB | \ - CFG_CMD_MFSL | \ - CFG_CMD_MII | \ - CFG_CMD_MMC | \ - CFG_CMD_NAND | \ - CFG_CMD_PCI | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_PING | \ - CFG_CMD_PORTIO | \ - CFG_CMD_REGINFO | \ - CFG_CMD_REISER | \ - CFG_CMD_SAVES | \ - CFG_CMD_SCSI | \ - CFG_CMD_SDRAM | \ - CFG_CMD_SNTP | \ - CFG_CMD_SPI | \ - CFG_CMD_UNIVERSE | \ - CFG_CMD_USB | \ - CFG_CMD_VFD ) - -/* Default configuration - */ -#define CONFIG_CMD_DFL (CFG_CMD_ALL & ~CFG_CMD_NONSTD) - -#ifndef CONFIG_COMMANDS -#define CONFIG_COMMANDS CONFIG_CMD_DFL -#endif - - /* * Temporary placeholder until all users directly * include the proper include file, "config_bootp.h". -- cgit v1.3.1 From 5d2ebe1b3ef0055c661bb1a0d252bf252380069f Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 9 Jul 2007 21:16:53 -0500 Subject: include/configs/[A-G]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. Signed-off-by: Jon Loeliger --- include/configs/AMX860.h | 11 ++++++++++- include/configs/AmigaOneG3SE.h | 13 +++++++++---- include/configs/B2.h | 9 ++++++++- include/configs/BAB7xx.h | 11 ++++++++++- include/configs/CCM.h | 9 ++++++++- include/configs/CMS700.h | 15 +++++++++++---- include/configs/CPC45.h | 10 +++++++++- include/configs/CPCI405.h | 15 +++++++++++---- include/configs/CPCI4052.h | 15 +++++++++++---- include/configs/CPCI405AB.h | 15 +++++++++++---- include/configs/CPCI405DT.h | 15 +++++++++++---- include/configs/CPCI750.h | 10 ++++++++-- include/configs/CPU86.h | 9 ++++++++- include/configs/CPU87.h | 9 ++++++++- include/configs/CRAYL1.h | 20 ++++++++++---------- include/configs/CU824.h | 10 +++++++++- include/configs/DB64360.h | 12 ++++++++++-- include/configs/DB64460.h | 12 ++++++++++-- include/configs/ELPPC.h | 10 +++++++++- include/configs/ELPT860.h | 10 +++++++++- include/configs/ESTEEM192E.h | 10 +++++++++- include/configs/ETX094.h | 10 +++++++++- include/configs/EVB64260.h | 10 ++++++++-- include/configs/FADS823.h | 21 ++++++++++++++++++++- include/configs/FLAGADM.h | 10 +++++++++- include/configs/FPS850L.h | 20 +++++++++++++++++++- include/configs/FPS860L.h | 19 ++++++++++++++++++- include/configs/GEN860T.h | 9 ++++++--- 28 files changed, 288 insertions(+), 61 deletions(-) (limited to 'include') diff --git a/include/configs/AMX860.h b/include/configs/AMX860.h index 9e4303fb9e4..6f640380739 100644 --- a/include/configs/AMX860.h +++ b/include/configs/AMX860.h @@ -87,7 +87,16 @@ #define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ #endif -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_SUBNETMASK + /* * Miscellaneous configurable options diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h index 8e902fef82a..661149e66b6 100644 --- a/include/configs/AmigaOneG3SE.h +++ b/include/configs/AmigaOneG3SE.h @@ -56,8 +56,15 @@ #define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=4096" -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -347,8 +354,6 @@ #define CONFIG_3COM /* #define CONFIG_BOOTP_RANDOM_DELAY */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) /* * USB configuration diff --git a/include/configs/B2.h b/include/configs/B2.h index 244ad4ffb77..f1411db66c3 100644 --- a/include/configs/B2.h +++ b/include/configs/B2.h @@ -72,7 +72,14 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h index 2569c914831..d8d09838eb4 100644 --- a/include/configs/BAB7xx.h +++ b/include/configs/BAB7xx.h @@ -66,7 +66,16 @@ #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + +#define CONFIG_BOOTP_BOOTFILESIZE + /* * Command line configuration. diff --git a/include/configs/CCM.h b/include/configs/CCM.h index 199b01f0cc8..9f06957d2ff 100644 --- a/include/configs/CCM.h +++ b/include/configs/CCM.h @@ -94,7 +94,14 @@ #define CONFIG_MAC_PARTITION /* nod used yet */ #define CONFIG_DOS_PARTITION -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 2d1280ffe07..08ef9b5da6b 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -60,10 +60,17 @@ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME ) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME + /* * Command line configuration. diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h index c1aec62fb39..aea85233f96 100644 --- a/include/configs/CPC45.h +++ b/include/configs/CPC45.h @@ -54,7 +54,15 @@ #define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index f49eb4b6ddb..0a4e1e9d30d 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -60,10 +60,17 @@ #define CONFIG_NET_MULTI 1 #undef CONFIG_HAS_ETH1 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME ) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME + /* * Command line configuration. diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index b88b029aa01..ceeba6e122e 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -64,10 +64,17 @@ #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME ) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME + /* * Command line configuration. diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 94faeed105d..1aefbbac686 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -64,10 +64,17 @@ #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME ) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME + /* * Command line configuration. diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 81528eae524..e2652e6aa6e 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -63,10 +63,17 @@ #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME ) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME + /* * Command line configuration. diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 000aaa55ee8..8d04104e58a 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -133,8 +133,14 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_ALTIVEC /* undef to disable */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index 202914b1f9d..c589f288789 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -161,7 +161,14 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h index ce25aa58fce..b087ebaa0bc 100644 --- a/include/configs/CPU87.h +++ b/include/configs/CPU87.h @@ -165,7 +165,14 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index 627c0c82014..a965c125f3f 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -101,16 +101,16 @@ /* - * optional BOOTP / DHCP fields - */ -#define CONFIG_BOOTP_MASK (\ - CONFIG_BOOTP_VENDOREX|\ - CONFIG_BOOTP_SUBNETMASK|\ - CONFIG_BOOTP_GATEWAY|\ - CONFIG_BOOTP_DNS|\ - CONFIG_BOOTP_HOSTNAME|\ - CONFIG_BOOTP_BOOTFILESIZE|\ - CONFIG_BOOTP_BOOTPATH) + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_VENDOREX +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_BOOTFILESIZE + /* * how many time to fail & restart a net-TFTP before giving up & resetting diff --git a/include/configs/CU824.h b/include/configs/CU824.h index 1c2033515e2..f7fdd2d6ee8 100644 --- a/include/configs/CU824.h +++ b/include/configs/CU824.h @@ -55,7 +55,15 @@ #define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */ #define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_TIMESTAMP /* Print image info with timestamp */ diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h index f7e1c4da84f..db2e96c227d 100644 --- a/include/configs/DB64360.h +++ b/include/configs/DB64360.h @@ -215,8 +215,16 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_ALTIVEC /* undef to disable */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + + /* * JFFS2 partitions * diff --git a/include/configs/DB64460.h b/include/configs/DB64460.h index 8cba0b26053..b5d3f773f38 100644 --- a/include/configs/DB64460.h +++ b/include/configs/DB64460.h @@ -153,8 +153,16 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0" #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_ALTIVEC /* undef to disable */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + + /* * JFFS2 partitions * diff --git a/include/configs/ELPPC.h b/include/configs/ELPPC.h index b2191606159..bb771887243 100644 --- a/include/configs/ELPPC.h +++ b/include/configs/ELPPC.h @@ -66,7 +66,15 @@ #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ #define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/ELPT860.h b/include/configs/ELPT860.h index 2a909f351b4..f927a2c9cca 100644 --- a/include/configs/ELPT860.h +++ b/include/configs/ELPT860.h @@ -81,7 +81,15 @@ "" #define CONFIG_BOOTCOMMAND "run ramboot" -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ diff --git a/include/configs/ESTEEM192E.h b/include/configs/ESTEEM192E.h index 06d4f344e76..66e1203b7dd 100644 --- a/include/configs/ESTEEM192E.h +++ b/include/configs/ESTEEM192E.h @@ -70,7 +70,15 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + /* * Command line configuration. diff --git a/include/configs/ETX094.h b/include/configs/ETX094.h index 2193918a9ef..ed439b1922b 100644 --- a/include/configs/ETX094.h +++ b/include/configs/ETX094.h @@ -82,7 +82,15 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/EVB64260.h b/include/configs/EVB64260.h index c78bbfa61b1..1c44a0c6d73 100644 --- a/include/configs/EVB64260.h +++ b/include/configs/EVB64260.h @@ -103,8 +103,14 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_ALTIVEC /* undef to disable */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h index 7857cf18c6d..bc3957629ca 100644 --- a/include/configs/FADS823.h +++ b/include/configs/FADS823.h @@ -105,7 +105,26 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_NISDOMAIN +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_NTPSERVER +#define CONFIG_BOOTP_TIMEOFFSET + /* * Command line configuration. diff --git a/include/configs/FLAGADM.h b/include/configs/FLAGADM.h index af31f700e21..431844c7f3d 100644 --- a/include/configs/FLAGADM.h +++ b/include/configs/FLAGADM.h @@ -62,7 +62,15 @@ /*#define CONFIG_WATCHDOG*/ /* watchdog enabled */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + /* * Command line configuration. diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h index 12956939b00..322158c7b81 100644 --- a/include/configs/FPS850L.h +++ b/include/configs/FPS850L.h @@ -60,7 +60,25 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_NISDOMAIN +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_NTPSERVER +#define CONFIG_BOOTP_TIMEOFFSET /* diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h index d97151fa61e..f8698b57085 100644 --- a/include/configs/FPS860L.h +++ b/include/configs/FPS860L.h @@ -58,7 +58,24 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_ALL +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_NISDOMAIN +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_NTPSERVER +#define CONFIG_BOOTP_TIMEOFFSET #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index 2b2d15a7629..d88124a3b42 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -132,9 +132,12 @@ /* * BOOTP options */ -#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE \ - ) +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + /* * The GEN860T network interface uses the on-chip 10/100 FEC with -- cgit v1.3.1 From 7be044e4ea644b0ef1c486dadc1a4c2665b4374d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 9 Jul 2007 21:24:19 -0500 Subject: include/configs/[H-N]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. Signed-off-by: Jon Loeliger --- include/configs/HMI10.h | 10 +++++++++- include/configs/IAD210.h | 10 +++++++++- include/configs/ICU862.h | 10 +++++++++- include/configs/IDS8247.h | 9 ++++++++- include/configs/IP860.h | 8 +++++++- include/configs/IPHASE4539.h | 9 ++++++++- include/configs/IVML24.h | 10 ++++++++-- include/configs/IVMS8.h | 10 ++++++++-- include/configs/KUP4K.h | 10 +++++++++- include/configs/KUP4X.h | 10 +++++++++- include/configs/LANTEC.h | 9 ++++++++- include/configs/MHPC.h | 10 +++++++++- include/configs/MPC8266ADS.h | 14 ++++++++------ include/configs/MVBLUE.h | 20 +++++++++++++++++++- include/configs/MVS1.h | 10 +++++++++- include/configs/NC650.h | 10 +++++++++- include/configs/NETPHONE.h | 10 +++++++++- include/configs/NETTA.h | 11 ++++++++++- include/configs/NETTA2.h | 11 ++++++++++- include/configs/NETVIA.h | 11 ++++++++++- include/configs/NSCU.h | 10 +++++++++- include/configs/NX823.h | 10 +++++++++- 22 files changed, 203 insertions(+), 29 deletions(-) (limited to 'include') diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h index 29748e1fd53..02ae5d005df 100644 --- a/include/configs/HMI10.h +++ b/include/configs/HMI10.h @@ -117,7 +117,15 @@ #define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/IAD210.h b/include/configs/IAD210.h index 59ea919be70..bd0894c29ab 100644 --- a/include/configs/IAD210.h +++ b/include/configs/IAD210.h @@ -84,7 +84,15 @@ /* #define CONFIG_STATUS_LED 1*/ /* Status LED enabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + # undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ # define CONFIG_FEC_ENET 1 /* use FEC ethernet */ diff --git a/include/configs/ICU862.h b/include/configs/ICU862.h index 9750c8718fe..27a5bc302fc 100644 --- a/include/configs/ICU862.h +++ b/include/configs/ICU862.h @@ -81,7 +81,15 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #undef CONFIG_SCC1_ENET /* disable SCC1 ethernet */ #define CONFIG_FEC_ENET 1 /* use FEC ethernet */ diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index e26dc5666a1..455bbe3f633 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -157,7 +157,14 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/IP860.h b/include/configs/IP860.h index 07c7955d14d..bd961d8426a 100644 --- a/include/configs/IP860.h +++ b/include/configs/IP860.h @@ -100,7 +100,13 @@ #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH /* * Miscellaneous configurable options diff --git a/include/configs/IPHASE4539.h b/include/configs/IPHASE4539.h index 1cb2d6b5121..6fee4558dee 100644 --- a/include/configs/IPHASE4539.h +++ b/include/configs/IPHASE4539.h @@ -94,7 +94,14 @@ #define CONFIG_8260_CLKIN 66666666 /* in Hz */ #define CONFIG_BAUDRATE 19200 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* * select i2c support configuration diff --git a/include/configs/IVML24.h b/include/configs/IVML24.h index 313f8d8b2d1..1142f2afac1 100644 --- a/include/configs/IVML24.h +++ b/include/configs/IVML24.h @@ -84,8 +84,14 @@ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -#define CONFIG_BOOTP_MASK \ - ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + /* * Miscellaneous configurable options diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h index 7633679544a..bd19dad1ff4 100644 --- a/include/configs/IVMS8.h +++ b/include/configs/IVMS8.h @@ -83,8 +83,14 @@ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -#define CONFIG_BOOTP_MASK \ - ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + /* * Miscellaneous configurable options diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h index 2f056059c18..f6c31ea8497 100644 --- a/include/configs/KUP4K.h +++ b/include/configs/KUP4K.h @@ -89,7 +89,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h index c59b70f15c1..e558aa481b3 100644 --- a/include/configs/KUP4X.h +++ b/include/configs/KUP4X.h @@ -99,7 +99,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h index 089fb9df871..2191c7b99c1 100644 --- a/include/configs/LANTEC.h +++ b/include/configs/LANTEC.h @@ -74,7 +74,14 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/MHPC.h b/include/configs/MHPC.h index a8dd36d9e05..dde77427113 100644 --- a/include/configs/MHPC.h +++ b/include/configs/MHPC.h @@ -129,7 +129,15 @@ #define CONFIG_CMD_REGINFO -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + /* * Miscellaneous configurable options diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index a8c40cf0709..3a6c977a606 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -203,13 +203,15 @@ "bootm" #endif /* CONFIG_BOOT_ROOT_NFS */ -/* Add support for a few extra bootp options like: - * - File size - * - DNS +/* + * BOOTP options */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE | \ - CONFIG_BOOTP_DNS) +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_DNS #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h index bea8cb196b4..0defafec260 100644 --- a/include/configs/MVBLUE.h +++ b/include/configs/MVBLUE.h @@ -95,7 +95,25 @@ #define CONFIG_CMD_RUN -#define CONFIG_BOOTP_MASK ( 0xffffffff ) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_NISDOMAIN +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_NTPSERVER +#define CONFIG_BOOTP_TIMEOFFSET + /* * Miscellaneous configurable options diff --git a/include/configs/MVS1.h b/include/configs/MVS1.h index 709ee86ab28..75efd1e0e42 100644 --- a/include/configs/MVS1.h +++ b/include/configs/MVS1.h @@ -63,7 +63,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_VENDOREX ) + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_VENDOREX #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 221fce92598..c051a351e85 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -85,7 +85,15 @@ #undef CONFIG_STATUS_LED /* Status LED disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_FEC_ENET 1 /* use FEC ethernet */ #define FEC_ENET diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h index cfca8114d73..bb3d19d14ca 100644 --- a/include/configs/NETPHONE.h +++ b/include/configs/NETPHONE.h @@ -82,7 +82,15 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_NISDOMAIN #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index e2e8803394e..19743c04e87 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -77,7 +77,16 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_NISDOMAIN + #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index ac8e4815d37..fb8085d56c7 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -82,7 +82,16 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_NISDOMAIN + #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION diff --git a/include/configs/NETVIA.h b/include/configs/NETVIA.h index fa91306a6c4..d4cb9e7ea9e 100644 --- a/include/configs/NETVIA.h +++ b/include/configs/NETVIA.h @@ -81,7 +81,16 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_NISDOMAIN + #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION diff --git a/include/configs/NSCU.h b/include/configs/NSCU.h index 0edfebf9e9f..4cd44720611 100644 --- a/include/configs/NSCU.h +++ b/include/configs/NSCU.h @@ -84,7 +84,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/NX823.h b/include/configs/NX823.h index 527bd9d6a95..524aa0621b9 100644 --- a/include/configs/NX823.h +++ b/include/configs/NX823.h @@ -55,9 +55,17 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #undef CONFIG_WATCHDOG /* watchdog disabled, for now */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) #define CONFIG_AUTOSCRIPT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + /* * Command line configuration. -- cgit v1.3.1 From 18225e8dd1950bd6dbf35011e436db7f474c187d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 9 Jul 2007 21:31:24 -0500 Subject: include/configs/[P-S]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. Signed-off-by: Jon Loeliger --- include/configs/P3G4.h | 11 +++++++++-- include/configs/PCIPPC2.h | 10 ++++++++-- include/configs/PCIPPC6.h | 10 ++++++++-- include/configs/PM826.h | 9 ++++++++- include/configs/PM828.h | 9 ++++++++- include/configs/QS823.h | 10 +++++++++- include/configs/QS850.h | 9 ++++++++- include/configs/QS860T.h | 10 +++++++++- include/configs/R360MPI.h | 9 ++++++++- include/configs/RBC823.h | 10 +++++++++- include/configs/RPXClassic.h | 10 +++++++++- include/configs/RPXlite.h | 10 +++++++++- include/configs/RPXlite_DW.h | 10 +++++++++- include/configs/RRvision.h | 10 +++++++++- include/configs/SCM.h | 9 ++++++++- include/configs/SM850.h | 10 +++++++++- include/configs/SMN42.h | 10 +++++++++- include/configs/SPD823TS.h | 10 +++++++++- 18 files changed, 155 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h index bfcfbc1bad3..ef970f1cd7e 100644 --- a/include/configs/P3G4.h +++ b/include/configs/P3G4.h @@ -120,8 +120,15 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_ALTIVEC /* undef to disable */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_TIMESTAMP /* Print image info with timestamp */ diff --git a/include/configs/PCIPPC2.h b/include/configs/PCIPPC2.h index 68b9d756926..268b0343a36 100644 --- a/include/configs/PCIPPC2.h +++ b/include/configs/PCIPPC2.h @@ -53,8 +53,14 @@ #define CONFIG_PREBOOT "" #define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/PCIPPC6.h b/include/configs/PCIPPC6.h index a8e27153eeb..250b5860481 100644 --- a/include/configs/PCIPPC6.h +++ b/include/configs/PCIPPC6.h @@ -53,8 +53,14 @@ #define CONFIG_PREBOOT "" #define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/PM826.h b/include/configs/PM826.h index 57d46acbc84..c80b1538807 100644 --- a/include/configs/PM826.h +++ b/include/configs/PM826.h @@ -151,7 +151,14 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/PM828.h b/include/configs/PM828.h index 3f1bb8e40d5..8f5be5f63a5 100644 --- a/include/configs/PM828.h +++ b/include/configs/PM828.h @@ -151,7 +151,14 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/QS823.h b/include/configs/QS823.h index 478ab93de06..3657feaf703 100644 --- a/include/configs/QS823.h +++ b/include/configs/QS823.h @@ -189,7 +189,15 @@ #undef CONFIG_STATUS_LED /* Status LED disabled */ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION diff --git a/include/configs/QS850.h b/include/configs/QS850.h index 8664eb0f36f..3db539fa90a 100644 --- a/include/configs/QS850.h +++ b/include/configs/QS850.h @@ -189,7 +189,14 @@ #undef CONFIG_STATUS_LED /* Status LED disabled */ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h index 906e117fb20..b3442de3627 100644 --- a/include/configs/QS860T.h +++ b/include/configs/QS860T.h @@ -92,7 +92,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/R360MPI.h b/include/configs/R360MPI.h index c00ed3d4c01..516ec643d65 100644 --- a/include/configs/R360MPI.h +++ b/include/configs/R360MPI.h @@ -79,7 +79,14 @@ #define CONFIG_CAN_DRIVER /* CAN Driver support enabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index d73a367616b..5e12dabecf7 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -79,7 +79,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #undef CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/RPXClassic.h b/include/configs/RPXClassic.h index 2091735aae0..793b1db8894 100644 --- a/include/configs/RPXClassic.h +++ b/include/configs/RPXClassic.h @@ -88,7 +88,15 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ diff --git a/include/configs/RPXlite.h b/include/configs/RPXlite.h index a478a067df6..3c5e6b89139 100644 --- a/include/configs/RPXlite.h +++ b/include/configs/RPXlite.h @@ -62,7 +62,15 @@ #define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + /* * Command line configuration. diff --git a/include/configs/RPXlite_DW.h b/include/configs/RPXlite_DW.h index 9bf7770d3ab..872765c92f4 100644 --- a/include/configs/RPXlite_DW.h +++ b/include/configs/RPXlite_DW.h @@ -115,7 +115,15 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_STATUS_LED /* disturbs display. Status LED disabled. */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #if 1 /* Enable this stuff could make image enlarge about 25KB. Mask it if you don't want the advanced function */ diff --git a/include/configs/RRvision.h b/include/configs/RRvision.h index 2c590af83bc..1e6e8c0aa23 100644 --- a/include/configs/RRvision.h +++ b/include/configs/RRvision.h @@ -92,7 +92,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/SCM.h b/include/configs/SCM.h index 46861f838f2..f900968c5a1 100644 --- a/include/configs/SCM.h +++ b/include/configs/SCM.h @@ -190,7 +190,14 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/SM850.h b/include/configs/SM850.h index 0ec63b88111..41a54f0f5ad 100644 --- a/include/configs/SM850.h +++ b/include/configs/SM850.h @@ -68,7 +68,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h index 7b6d27686cc..a5d3d695889 100644 --- a/include/configs/SMN42.h +++ b/include/configs/SMN42.h @@ -66,7 +66,15 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ diff --git a/include/configs/SPD823TS.h b/include/configs/SPD823TS.h index fa4cdc63a23..395c7a1e7a0 100644 --- a/include/configs/SPD823TS.h +++ b/include/configs/SPD823TS.h @@ -73,7 +73,15 @@ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + /*----------------------------------------------------------------------*/ #define CONFIG_ETHADDR 00:D0:93:00:01:CB -- cgit v1.3.1 From 37d4bb70586659dedef1658ce1bed071be098aec Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 9 Jul 2007 21:38:02 -0500 Subject: include/configs/[T-Z]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. Signed-off-by: Jon Loeliger --- include/configs/TOP860.h | 9 +++++---- include/configs/TQM823L.h | 10 +++++++++- include/configs/TQM823M.h | 10 +++++++++- include/configs/TQM8260.h | 10 +++++++++- include/configs/TQM8272.h | 9 ++++++++- include/configs/TQM850L.h | 10 +++++++++- include/configs/TQM850M.h | 10 +++++++++- include/configs/TQM855L.h | 10 +++++++++- include/configs/TQM855M.h | 10 +++++++++- include/configs/TQM860L.h | 10 +++++++++- include/configs/TQM860M.h | 10 +++++++++- include/configs/TQM862L.h | 10 +++++++++- include/configs/TQM862M.h | 10 +++++++++- include/configs/TQM866M.h | 10 +++++++++- include/configs/TQM885D.h | 10 +++++++++- include/configs/VOM405.h | 14 ++++++++++---- include/configs/ZUMA.h | 10 ++++++++-- 17 files changed, 148 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h index 717b779570e..66f7a1150d0 100644 --- a/include/configs/TOP860.h +++ b/include/configs/TOP860.h @@ -409,10 +409,11 @@ /* * BOOTP options */ -#undef CONFIG_BOOTP_MASK -#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE \ - ) +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index 86df7f60d68..2bdcf2cf951 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -88,7 +88,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index bd33efbc7af..58bc5d3f956 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -88,7 +88,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/TQM8260.h b/include/configs/TQM8260.h index ee5e6f76250..3b7832397f2 100644 --- a/include/configs/TQM8260.h +++ b/include/configs/TQM8260.h @@ -219,7 +219,15 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h index a55aec27672..05e2e9ac188 100644 --- a/include/configs/TQM8272.h +++ b/include/configs/TQM8272.h @@ -271,7 +271,14 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index 923d4e5eafd..74b16c7cf9c 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -80,7 +80,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index c257fc543d5..e3936c33043 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -78,7 +78,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 7da7b0bd886..ae22b77d7f9 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -83,7 +83,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index e66bbc42213..5d54f876c8a 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -116,7 +116,15 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 5 #endif -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 495760a10d7..40c0940d5a2 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -83,7 +83,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index e86e5fb1875..481e3d0d532 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -83,7 +83,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index 051225136ec..bb3b1cc5411 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -86,7 +86,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index df141a70594..d687d082c94 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -86,7 +86,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index 27e37e2d802..ff00c133080 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -125,7 +125,15 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 4 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index 4731988eba8..19fdaf0b6bc 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -131,7 +131,15 @@ # define CONFIG_RTC_DS1337 1 # define CFG_I2C_RTC_ADDR 0x68 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index f312ea46ac4..5512f4be21a 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -60,10 +60,16 @@ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME ) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME /* diff --git a/include/configs/ZUMA.h b/include/configs/ZUMA.h index 662093834a3..5ba8d1a7157 100644 --- a/include/configs/ZUMA.h +++ b/include/configs/ZUMA.h @@ -101,8 +101,14 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_ALTIVEC /* undef to disable */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE #define CONFIG_MII /* enable MII commands */ -- cgit v1.3.1 From 2fd90ce575b02d189cbf443c85309bcd001aa393 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 9 Jul 2007 21:48:26 -0500 Subject: include/configs/[a-m]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. Signed-off-by: Jon Loeliger --- include/configs/armadillo.h | 9 ++++++++- include/configs/assabet.h | 9 ++++++++- include/configs/atc.h | 10 +++++++++- include/configs/atstk1002.h | 8 ++++++-- include/configs/barco.h | 16 ++++++++++------ include/configs/c2mon.h | 10 +++++++++- include/configs/csb272.h | 12 +++++++----- include/configs/csb472.h | 13 ++++++++----- include/configs/ep7312.h | 9 ++++++++- include/configs/evb4510.h | 9 ++++++++- include/configs/gcplus.h | 9 ++++++++- include/configs/gw8260.h | 15 +++++++++------ include/configs/hermes.h | 9 ++++++++- include/configs/impa7.h | 9 ++++++++- include/configs/integratorap.h | 1 - include/configs/integratorcp.h | 2 -- include/configs/kvme080.h | 10 +++++++++- include/configs/lpc2292sodimm.h | 9 ++++++++- include/configs/lwmon.h | 9 ++++++++- include/configs/modnet50.h | 9 ++++++++- 20 files changed, 147 insertions(+), 40 deletions(-) (limited to 'include') diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h index 7c77fa73115..73a88854b38 100644 --- a/include/configs/armadillo.h +++ b/include/configs/armadillo.h @@ -71,7 +71,14 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/assabet.h b/include/configs/assabet.h index 7c6a65ac0a6..226ad54723e 100644 --- a/include/configs/assabet.h +++ b/include/configs/assabet.h @@ -75,7 +75,14 @@ #define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySA0,115200n8 root=/dev/nfs ip=bootp" diff --git a/include/configs/atc.h b/include/configs/atc.h index 4f527fa40d5..3ff4b68083a 100644 --- a/include/configs/atc.h +++ b/include/configs/atc.h @@ -122,7 +122,15 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index de2fd31af25..e1d8f74c5ec 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -108,8 +108,12 @@ #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 #define CONFIG_NET_MULTI 1 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_SUBNETMASK \ - | CONFIG_BOOTP_GATEWAY) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + /* * Command line configuration. diff --git a/include/configs/barco.h b/include/configs/barco.h index 225ab8d0e14..09078d42c62 100644 --- a/include/configs/barco.h +++ b/include/configs/barco.h @@ -70,13 +70,17 @@ #define CONFIG_BOOTARGS "mem=32M" -/* Add support for a few extra bootp options like: - * - File size - * - DNS + +/* + * BOOTP options */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE | \ - CONFIG_BOOTP_DNS) +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_DNS + /* * Command line configuration. diff --git a/include/configs/c2mon.h b/include/configs/c2mon.h index 946b179f152..a9a52547756 100644 --- a/include/configs/c2mon.h +++ b/include/configs/c2mon.h @@ -68,7 +68,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/csb272.h b/include/configs/csb272.h index 63ea24edea0..c43b49737d9 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -73,12 +73,14 @@ #endif /* - * BOOTP/DHCP protocol configuration - * + * BOOTP options */ -#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_BOOTFILESIZE ) +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_DNS2 /* diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 316b1fee21d..a7120aa57f9 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -73,12 +73,15 @@ #endif /* - * BOOTP/DHCP protocol configuration - * + * BOOTP options */ -#define CONFIG_BOOTP_MASK ( CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_BOOTFILESIZE ) +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_DNS2 + /* * Command line configuration. diff --git a/include/configs/ep7312.h b/include/configs/ep7312.h index 12be15102f5..f5cf477a313 100644 --- a/include/configs/ep7312.h +++ b/include/configs/ep7312.h @@ -62,7 +62,14 @@ #define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/evb4510.h b/include/configs/evb4510.h index 0a4aeb95ade..66500c21e02 100644 --- a/include/configs/evb4510.h +++ b/include/configs/evb4510.h @@ -72,7 +72,14 @@ #define CONFIG_BAUDRATE 19200 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h index 0aecb38e440..e11ce4c715e 100644 --- a/include/configs/gcplus.h +++ b/include/configs/gcplus.h @@ -88,7 +88,14 @@ #define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + #define CONFIG_BOOTDELAY 3 #define CONFIG_BOOTARGS "console=ttySA0,38400n8 mtdparts=sa1100-flash:1m@0(zImage),3m@1m(ramdisk.gz),12m@4m(userfs) root=/dev/nfs ip=bootp" diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index a8bc928b63b..79e6aa1ba6c 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -285,13 +285,16 @@ #undef CONFIG_AUTOBOOT_DELAY_STR #define DEBUG_BOOTKEYS 0 -/* Add support for a few extra bootp options like: - * - File size - * - DNS +/* + * BOOTP options */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE | \ - CONFIG_BOOTP_DNS) +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + +#define CONFIG_BOOTP_BOOTFILESIZE +#definef CONFIG_BOOTP_DNS /* undef this to save memory */ #define CFG_LONGHELP diff --git a/include/configs/hermes.h b/include/configs/hermes.h index f1cc8d263f8..e3a2ed28034 100644 --- a/include/configs/hermes.h +++ b/include/configs/hermes.h @@ -71,7 +71,14 @@ #include -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + /* * Miscellaneous configurable options diff --git a/include/configs/impa7.h b/include/configs/impa7.h index 6570815696e..0e52ffe0a29 100644 --- a/include/configs/impa7.h +++ b/include/configs/impa7.h @@ -61,7 +61,14 @@ #define CONFIG_BAUDRATE 9600 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 3594f4ffd23..be3b1140bb1 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -67,7 +67,6 @@ #define CFG_SERIAL1 0x17000000 /*#define CONFIG_NET_MULTI */ -/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ /* diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index a5174293452..191c5e61e32 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -84,8 +84,6 @@ #define CONFIG_CMD_PING -/* #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ - #if 0 #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/nfs nfsroot=:/ mem=128M ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" diff --git a/include/configs/kvme080.h b/include/configs/kvme080.h index 53d6af28cc6..569800aa231 100644 --- a/include/configs/kvme080.h +++ b/include/configs/kvme080.h @@ -60,7 +60,15 @@ #undef CONFIG_WATCHDOG -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h index bddfa528a35..e3fef5e2ce9 100644 --- a/include/configs/lpc2292sodimm.h +++ b/include/configs/lpc2292sodimm.h @@ -66,7 +66,14 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/lwmon.h b/include/configs/lwmon.h index 1db5e90965d..8a8270260a3 100644 --- a/include/configs/lwmon.h +++ b/include/configs/lwmon.h @@ -196,7 +196,14 @@ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/modnet50.h b/include/configs/modnet50.h index 33ae43efe88..4461bdfd187 100644 --- a/include/configs/modnet50.h +++ b/include/configs/modnet50.h @@ -63,7 +63,14 @@ #define CONFIG_BAUDRATE 38400 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* -- cgit v1.3.1 From d3b8c1a743dcd31625c99e6a44590f207eb00028 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 9 Jul 2007 21:57:31 -0500 Subject: include/configs/[m-z]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. Signed-off-by: Jon Loeliger --- include/configs/mpc7448hpc2.h | 10 ++++++++-- include/configs/netstar.h | 9 ++++++++- include/configs/omap1510inn.h | 9 ++++++++- include/configs/omap1610h2.h | 9 ++++++++- include/configs/omap1610inn.h | 9 ++++++++- include/configs/omap2420h4.h | 9 ++++++++- include/configs/omap5912osk.h | 9 ++++++++- include/configs/omap730p2.h | 9 ++++++++- include/configs/p3mx.h | 11 +++++++++-- include/configs/pcu_e.h | 10 ++++++++-- include/configs/ppmc8260.h | 16 ++++++++++------ include/configs/quantum.h | 10 +++++++++- include/configs/rmu.h | 10 +++++++++- include/configs/sacsng.h | 20 +++++++++++--------- include/configs/sbc405.h | 10 +++++++++- include/configs/sbc8240.h | 10 +++++++++- include/configs/sbc8260.h | 22 ++++++++++++---------- include/configs/stxxtc.h | 11 ++++++++++- include/configs/svm_sc8xx.h | 9 ++++++++- include/configs/uc100.h | 10 +++++++++- include/configs/v37.h | 10 +++++++++- include/configs/versatile.h | 9 ++++++++- include/configs/virtlab2.h | 10 +++++++++- include/configs/voiceblue.h | 10 +++++++++- 24 files changed, 212 insertions(+), 49 deletions(-) (limited to 'include') diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 36ce9bf8eea..4237228bebe 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -146,8 +146,14 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* diff --git a/include/configs/netstar.h b/include/configs/netstar.h index 603c9b8be64..33159d31563 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -162,7 +162,14 @@ #define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + #define CONFIG_LOOPW #define CONFIG_BOOTDELAY 3 diff --git a/include/configs/omap1510inn.h b/include/configs/omap1510inn.h index 9f4be5ca19b..8623ed3cc88 100644 --- a/include/configs/omap1510inn.h +++ b/include/configs/omap1510inn.h @@ -95,7 +95,14 @@ #define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + #include diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h index d78f79f121e..74bba05fe8a 100644 --- a/include/configs/omap1610h2.h +++ b/include/configs/omap1610h2.h @@ -90,7 +90,14 @@ #define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + #include diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h index 7d0658fd7de..734f3543927 100644 --- a/include/configs/omap1610inn.h +++ b/include/configs/omap1610inn.h @@ -91,7 +91,14 @@ #define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + #include diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 46e0dcc4782..8ae8efeb817 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -139,7 +139,14 @@ #endif -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + /* * Board NAND Info. diff --git a/include/configs/omap5912osk.h b/include/configs/omap5912osk.h index 296b6bc9800..16ce2f61aec 100644 --- a/include/configs/omap5912osk.h +++ b/include/configs/omap5912osk.h @@ -95,7 +95,14 @@ #define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + #include diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h index af9877f24a9..c4d253af45c 100644 --- a/include/configs/omap730p2.h +++ b/include/configs/omap730p2.h @@ -99,7 +99,14 @@ #define CONFIG_CMD_DHCP -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + #include #include diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index 6994f7b62b1..8ae38cb2775 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -251,8 +251,15 @@ #endif #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE) + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE /* * Command line configuration. diff --git a/include/configs/pcu_e.h b/include/configs/pcu_e.h index 1174e1aa4f8..e3c884392c7 100644 --- a/include/configs/pcu_e.h +++ b/include/configs/pcu_e.h @@ -102,8 +102,14 @@ #define CONFIG_CMD_SNTP -#define CONFIG_BOOTP_MASK \ - ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + /* * Miscellaneous configurable options diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h index 610fcfdfedd..fb5ae99e4cc 100644 --- a/include/configs/ppmc8260.h +++ b/include/configs/ppmc8260.h @@ -260,13 +260,17 @@ "bootm" #endif /* CONFIG_BOOT_ROOT_NFS */ -/* Add support for a few extra bootp options like: - * - File size - * - DNS + +/* + * BOOTP options */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE | \ - CONFIG_BOOTP_DNS) +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_DNS + /* undef this to save memory */ #define CFG_LONGHELP diff --git a/include/configs/quantum.h b/include/configs/quantum.h index dce2f4b811c..f49e2b0716e 100644 --- a/include/configs/quantum.h +++ b/include/configs/quantum.h @@ -105,7 +105,15 @@ #define CONFIG_CMD_SNTP -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ #define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" diff --git a/include/configs/rmu.h b/include/configs/rmu.h index fd27ea15872..2ca60b731ea 100644 --- a/include/configs/rmu.h +++ b/include/configs/rmu.h @@ -100,7 +100,15 @@ #define CONFIG_CMD_SNTP -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_AUTOBOOT_KEYED /* Enable password protection */ #define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n" diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 41f1f25fce0..c474acd70ec 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -469,16 +469,18 @@ #define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */ -/* Add support for a few extra bootp options like: - * - File size - * - DNS (up to 2 servers) - * - Send hostname to DHCP server +/* + * BOOTP options */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME) +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME + /* undef this to save memory */ #define CFG_LONGHELP diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index af34dbb74b7..dc906b15006 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -84,7 +84,15 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/sbc8240.h b/include/configs/sbc8240.h index b81858b5fc9..0e878f054ff 100644 --- a/include/configs/sbc8240.h +++ b/include/configs/sbc8240.h @@ -75,7 +75,15 @@ #define CONFIG_BOOTDELAY 5 -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_ENV_OVERWRITE diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h index bf6dab23d3c..b1d41a6d42b 100644 --- a/include/configs/sbc8260.h +++ b/include/configs/sbc8260.h @@ -411,16 +411,18 @@ "bootm" #endif /* CONFIG_BOOT_ROOT_NFS */ -/* Add support for a few extra bootp options like: - * - File size - * - DNS (up to 2 servers) - * - Send hostname to DHCP server - */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_BOOTFILESIZE | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME + /* undef this to save memory */ #define CFG_LONGHELP diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index d0d85812f9f..0dbf4b7feb6 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -77,7 +77,16 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_NISDOMAIN + #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION diff --git a/include/configs/svm_sc8xx.h b/include/configs/svm_sc8xx.h index 0cd0219b805..3b90f3ceb1d 100644 --- a/include/configs/svm_sc8xx.h +++ b/include/configs/svm_sc8xx.h @@ -125,7 +125,14 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/uc100.h b/include/configs/uc100.h index d223c58da32..92148e20543 100644 --- a/include/configs/uc100.h +++ b/include/configs/uc100.h @@ -98,7 +98,15 @@ #undef CONFIG_STATUS_LED /* no status-led */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/v37.h b/include/configs/v37.h index 402ed4b4b21..04072534810 100644 --- a/include/configs/v37.h +++ b/include/configs/v37.h @@ -76,7 +76,15 @@ #define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/versatile.h b/include/configs/versatile.h index b90821995c6..d2501501276 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -111,7 +111,14 @@ #define CONFIG_CMD_ENV -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + #define CONFIG_BOOTDELAY 2 #define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0" diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h index ac87b397d29..561a8bc47b5 100644 --- a/include/configs/virtlab2.h +++ b/include/configs/virtlab2.h @@ -89,7 +89,15 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h index f8879a11960..7cab31dee4d 100644 --- a/include/configs/voiceblue.h +++ b/include/configs/voiceblue.h @@ -154,7 +154,15 @@ #endif -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH + + #define CONFIG_LOOPW #ifdef VOICEBLUE_SMALL_FLASH -- cgit v1.3.1 From 1fe80d79c5c4e52d3410a7ab4b8515da095cdab3 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Mon, 9 Jul 2007 22:08:34 -0500 Subject: Finally retire cmd_confdefs.h and CONFIG_BOOTP_MASK! All of the choices for CONFIG_BOOTP_ are now documented in the README file. You must now individually select exactly the set that you want using a series of #define CONFIG_BOOTP_ statements in the board port config files now. Signed-off-by: Jon Loeliger --- README | 28 +++++++++++++++++--------- common/cmd_net.c | 6 +++--- include/cmd_confdefs.h | 33 ------------------------------ include/config_bootp.h | 41 -------------------------------------- include/net.h | 2 +- net/bootp.c | 54 +++++++++++++++++++++++++------------------------- net/net.c | 2 +- 7 files changed, 51 insertions(+), 115 deletions(-) delete mode 100644 include/cmd_confdefs.h delete mode 100644 include/config_bootp.h (limited to 'include') diff --git a/README b/README index a45181961d2..cfbd39afb59 100644 --- a/README +++ b/README @@ -1125,10 +1125,21 @@ The following options need to be configured: BOOTP requests: delay 0 ... 8 sec - DHCP Advanced Options: - CONFIG_BOOTP_MASK - - You can fine tune the DHCP functionality by adding - these flags to the CONFIG_BOOTP_MASK define: + You can fine tune the DHCP functionality by defining + CONFIG_BOOTP_* symbols: + + CONFIG_BOOTP_SUBNETMASK + CONFIG_BOOTP_GATEWAY + CONFIG_BOOTP_HOSTNAME + CONFIG_BOOTP_NISDOMAIN + CONFIG_BOOTP_BOOTPATH + CONFIG_BOOTP_BOOTFILESIZE + CONFIG_BOOTP_DNS + CONFIG_BOOTP_DNS2 + CONFIG_BOOTP_SEND_HOSTNAME + CONFIG_BOOTP_NTPSERVER + CONFIG_BOOTP_TIMEOFFSET + CONFIG_BOOTP_VENDOREX CONFIG_BOOTP_DNS2 - If a DHCP client requests the DNS serverip from a DHCP server, it is possible that more @@ -1137,15 +1148,14 @@ The following options need to be configured: serverip will be stored in the additional environment variable "dnsip2". The first DNS serverip is always stored in the variable "dnsip", when CONFIG_BOOTP_DNS - is added to the CONFIG_BOOTP_MASK. + is defined. CONFIG_BOOTP_SEND_HOSTNAME - Some DHCP servers are capable to do a dynamic update of a DNS server. To do this, they need the hostname of the DHCP requester. - If CONFIG_BOOP_SEND_HOSTNAME is added to the - CONFIG_BOOTP_MASK, the content of the "hostname" - environment variable is passed as option 12 to - the DHCP server. + If CONFIG_BOOP_SEND_HOSTNAME is defined, the content + of the "hostname" environment variable is passed as + option 12 to the DHCP server. - CDP Options: CONFIG_CDP_DEVICE_ID diff --git a/common/cmd_net.c b/common/cmd_net.c index da55f14a2eb..8f766c8dbb2 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -128,7 +128,7 @@ static void netboot_update_env (void) ip_to_string (NetOurDNSIP, tmp); setenv ("dnsip", tmp); } -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) +#if defined(CONFIG_BOOTP_DNS2) if (NetOurDNS2IP) { ip_to_string (NetOurDNS2IP, tmp); setenv ("dnsip2", tmp); @@ -138,14 +138,14 @@ static void netboot_update_env (void) setenv ("domain", NetOurNISDomain); #if defined(CONFIG_CMD_SNTP) \ - && (CONFIG_BOOTP_MASK & CONFIG_BOOTP_TIMEOFFSET) + && defined(CONFIG_BOOTP_TIMEOFFSET) if (NetTimeOffset) { sprintf (tmp, "%d", NetTimeOffset); setenv ("timeoffset", tmp); } #endif #if defined(CONFIG_CMD_SNTP) \ - && (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NTPSERVER) + && defined(CONFIG_BOOTP_NTPSERVER) if (NetNtpServerIP) { ip_to_string (NetNtpServerIP, tmp); setenv ("ntpserverip", tmp); diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h deleted file mode 100644 index 3bfb2aed396..00000000000 --- a/include/cmd_confdefs.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * (C) Copyright 2000-2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _CMD_CONFIG_H -#define _CMD_CONFIG_H - -/* - * Temporary placeholder until all users directly - * include the proper include file, "config_bootp.h". - */ -#include "config_bootp.h" - -#endif /* _CMD_CONFIG_H */ diff --git a/include/config_bootp.h b/include/config_bootp.h deleted file mode 100644 index f0c9360180d..00000000000 --- a/include/config_bootp.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2007 Freescale Semiconductor, Inc. - * - * This file is licensed under the terms of the GNU General Public - * License Version 2. This file is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#ifndef _CONFIG_BOOTP_H -#define _CONFIG_BOOTP_H - -/* - * Optional BOOTP fields - */ - -#define CONFIG_BOOTP_SUBNETMASK 0x00000001 -#define CONFIG_BOOTP_GATEWAY 0x00000002 -#define CONFIG_BOOTP_HOSTNAME 0x00000004 -#define CONFIG_BOOTP_NISDOMAIN 0x00000008 -#define CONFIG_BOOTP_BOOTPATH 0x00000010 -#define CONFIG_BOOTP_BOOTFILESIZE 0x00000020 -#define CONFIG_BOOTP_DNS 0x00000040 -#define CONFIG_BOOTP_DNS2 0x00000080 -#define CONFIG_BOOTP_SEND_HOSTNAME 0x00000100 -#define CONFIG_BOOTP_NTPSERVER 0x00000200 -#define CONFIG_BOOTP_TIMEOFFSET 0x00000400 - -#define CONFIG_BOOTP_VENDOREX 0x80000000 - -#define CONFIG_BOOTP_ALL (~CONFIG_BOOTP_VENDOREX) - -#define CONFIG_BOOTP_DEFAULT (CONFIG_BOOTP_SUBNETMASK | \ - CONFIG_BOOTP_GATEWAY | \ - CONFIG_BOOTP_HOSTNAME | \ - CONFIG_BOOTP_BOOTPATH) - -#ifndef CONFIG_BOOTP_MASK -#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT -#endif - -#endif /* _CONFIG_BOOTP_H */ diff --git a/include/net.h b/include/net.h index f6f33fff91a..96719480097 100644 --- a/include/net.h +++ b/include/net.h @@ -296,7 +296,7 @@ typedef struct icmphdr { extern IPaddr_t NetOurGatewayIP; /* Our gateway IP addresse */ extern IPaddr_t NetOurSubnetMask; /* Our subnet mask (0 = unknown)*/ extern IPaddr_t NetOurDNSIP; /* Our Domain Name Server (0 = unknown)*/ -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) +#if defined(CONFIG_BOOTP_DNS2) extern IPaddr_t NetOurDNS2IP; /* Our 2nd Domain Name Server (0 = unknown)*/ #endif extern char NetOurNISDomain[32]; /* Our NIS domain */ diff --git a/net/bootp.c b/net/bootp.c index 0c7c193e8b0..ac9455e1ab4 100644 --- a/net/bootp.c +++ b/net/bootp.c @@ -76,7 +76,7 @@ static char *dhcpmsg2str(int type) } #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) +#if defined(CONFIG_BOOTP_VENDOREX) extern u8 *dhcp_vendorex_prep (u8 *e); /*rtn new e after add own opts. */ extern u8 *dhcp_vendorex_proc (u8 *e); /*rtn next e if mine,else NULL */ #endif @@ -181,7 +181,7 @@ static void BootpVendorFieldProcess (u8 * ext) if (NetOurDNSIP == 0) { NetCopyIP (&NetOurDNSIP, (IPaddr_t *) (ext + 2)); } -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) +#if defined(CONFIG_BOOTP_DNS2) if ((NetOurDNS2IP == 0) && (size > 4)) { NetCopyIP (&NetOurDNS2IP, (IPaddr_t *) (ext + 2 + 4)); } @@ -383,10 +383,10 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R u8 *start = e; u8 *cnt; -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) +#if defined(CONFIG_BOOTP_VENDOREX) u8 *x; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SEND_HOSTNAME) +#if defined(CONFIG_BOOTP_SEND_HOSTNAME) char *hostname; #endif @@ -425,7 +425,7 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R *e++ = tmp >> 8; *e++ = tmp & 0xff; } -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SEND_HOSTNAME) +#if defined(CONFIG_BOOTP_SEND_HOSTNAME) if ((hostname = getenv ("hostname"))) { int hostnamelen = strlen (hostname); @@ -436,7 +436,7 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R } #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) +#if defined(CONFIG_BOOTP_VENDOREX) if ((x = dhcp_vendorex_prep (e))) return x - start; #endif @@ -444,39 +444,39 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R *e++ = 55; /* Parameter Request List */ cnt = e++; /* Pointer to count of requested items */ *cnt = 0; -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SUBNETMASK) +#if defined(CONFIG_BOOTP_SUBNETMASK) *e++ = 1; /* Subnet Mask */ *cnt += 1; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_TIMEOFFSET) +#if defined(CONFIG_BOOTP_TIMEOFFSET) *e++ = 2; *cnt += 1; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_GATEWAY) +#if defined(CONFIG_BOOTP_GATEWAY) *e++ = 3; /* Router Option */ *cnt += 1; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS) +#if defined(CONFIG_BOOTP_DNS) *e++ = 6; /* DNS Server(s) */ *cnt += 1; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_HOSTNAME) +#if defined(CONFIG_BOOTP_HOSTNAME) *e++ = 12; /* Hostname */ *cnt += 1; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_BOOTFILESIZE) +#if defined(CONFIG_BOOTP_BOOTFILESIZE) *e++ = 13; /* Boot File Size */ *cnt += 1; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_BOOTPATH) +#if defined(CONFIG_BOOTP_BOOTPATH) *e++ = 17; /* Boot path */ *cnt += 1; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NISDOMAIN) +#if defined(CONFIG_BOOTP_NISDOMAIN) *e++ = 40; /* NIS Domain name request */ *cnt += 1; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NTPSERVER) +#if defined(CONFIG_BOOTP_NTPSERVER) *e++ = 42; *cnt += 1; #endif @@ -493,7 +493,7 @@ static int DhcpExtended (u8 * e, int message_type, IPaddr_t ServerID, IPaddr_t R #else /* CFG_CMD_DHCP */ /* - * Warning: no field size check - change CONFIG_BOOTP_MASK at your own risk! + * Warning: no field size check - change CONFIG_BOOTP_* at your own risk! */ static int BootpExtended (u8 * e) { @@ -515,43 +515,43 @@ static int BootpExtended (u8 * e) *e++ = (576 - 312 + OPT_SIZE) & 0xff; #endif /* CFG_CMD_DHCP */ -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_SUBNETMASK) +#if defined(CONFIG_BOOTP_SUBNETMASK) *e++ = 1; /* Subnet mask request */ *e++ = 4; e += 4; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_GATEWAY) +#if defined(CONFIG_BOOTP_GATEWAY) *e++ = 3; /* Default gateway request */ *e++ = 4; e += 4; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS) +#if defined(CONFIG_BOOTP_DNS) *e++ = 6; /* Domain Name Server */ *e++ = 4; e += 4; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_HOSTNAME) +#if defined(CONFIG_BOOTP_HOSTNAME) *e++ = 12; /* Host name request */ *e++ = 32; e += 32; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_BOOTFILESIZE) +#if defined(CONFIG_BOOTP_BOOTFILESIZE) *e++ = 13; /* Boot file size */ *e++ = 2; e += 2; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_BOOTPATH) +#if defined(CONFIG_BOOTP_BOOTPATH) *e++ = 17; /* Boot path */ *e++ = 32; e += 32; #endif -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NISDOMAIN) +#if defined(CONFIG_BOOTP_NISDOMAIN) *e++ = 40; /* NIS Domain name request */ *e++ = 32; e += 32; @@ -726,7 +726,7 @@ static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp) case 1: NetCopyIP (&NetOurSubnetMask, (popt + 2)); break; -#if defined(CONFIG_CMD_SNTP) && (CONFIG_BOOTP_MASK & CONFIG_BOOTP_TIMEOFFSET) +#if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_TIMEOFFSET) case 2: /* Time offset */ NetCopyLong (&NetTimeOffset, (ulong *) (popt + 2)); NetTimeOffset = ntohl (NetTimeOffset); @@ -737,7 +737,7 @@ static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp) break; case 6: NetCopyIP (&NetOurDNSIP, (popt + 2)); -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) +#if defined(CONFIG_BOOTP_DNS2) if (*(popt + 1) > 4) { NetCopyIP (&NetOurDNS2IP, (popt + 2 + 4)); } @@ -755,7 +755,7 @@ static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp) memcpy (&NetOurRootPath, popt + 2, size); NetOurRootPath[size] = 0; break; -#if defined(CONFIG_CMD_SNTP) && (CONFIG_BOOTP_MASK & CONFIG_BOOTP_NTPSERVER) +#if defined(CONFIG_CMD_SNTP) && defined(CONFIG_BOOTP_NTPSERVER) case 42: /* NTP server IP */ NetCopyIP (&NetNtpServerIP, (popt + 2)); break; @@ -801,7 +801,7 @@ static void DhcpOptionsProcess (uchar * popt, Bootp_t *bp) } break; default: -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_VENDOREX) +#if defined(CONFIG_BOOTP_VENDOREX) if (dhcp_vendorex_proc (popt)) break; #endif diff --git a/net/net.c b/net/net.c index 1b7b4a8637a..f96eb28b35e 100644 --- a/net/net.c +++ b/net/net.c @@ -110,7 +110,7 @@ DECLARE_GLOBAL_DATA_PTR; IPaddr_t NetOurSubnetMask=0; /* Our subnet mask (0=unknown) */ IPaddr_t NetOurGatewayIP=0; /* Our gateways IP address */ IPaddr_t NetOurDNSIP=0; /* Our DNS IP address */ -#if (CONFIG_BOOTP_MASK & CONFIG_BOOTP_DNS2) +#if defined(CONFIG_BOOTP_DNS2) IPaddr_t NetOurDNS2IP=0; /* Our 2nd DNS IP address */ #endif char NetOurNISDomain[32]={0,}; /* Our NIS domain */ -- cgit v1.3.1 From 11799434c5ff15a612577bb1ad1f4ea1a0595e4b Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Jul 2007 09:02:57 -0500 Subject: include/configs/[A-I]*: Cleanup BOOTP and lingering CFG_CMD_*. Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h used to be included but CONFIG_BOOTP_MASK was not defined. Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger --- include/configs/A3000.h | 9 +++++++++ include/configs/ADCIOP.h | 9 +++++++++ include/configs/ADNPESC1.h | 9 +++++++++ include/configs/AP1000.h | 8 ++++++++ include/configs/APC405.h | 9 +++++++++ include/configs/AR405.h | 9 +++++++++ include/configs/ASH405.h | 9 +++++++++ include/configs/Adder.h | 9 +++++++++ include/configs/Alaska8220.h | 9 +++++++++ include/configs/BC3450.h | 12 ++++++++++-- include/configs/BMW.h | 11 ++++++++++- include/configs/CANBT.h | 9 +++++++++ include/configs/CATcenter.h | 9 +++++++++ include/configs/CPCI2DP.h | 9 +++++++++ include/configs/CPCI440.h | 9 +++++++++ include/configs/CPCIISER4.h | 18 ++++++++++++++++++ include/configs/DASA_SIM.h | 9 +++++++++ include/configs/DK1C20.h | 9 +++++++++ include/configs/DK1S10.h | 9 +++++++++ include/configs/DP405.h | 9 +++++++++ include/configs/DU405.h | 9 +++++++++ include/configs/EB+MCF-EV123.h | 9 +++++++++ include/configs/EP1C20.h | 9 +++++++++ include/configs/EP1S10.h | 9 +++++++++ include/configs/EP1S40.h | 9 +++++++++ include/configs/EP88x.h | 9 +++++++++ include/configs/ERIC.h | 9 +++++++++ include/configs/EXBITGEN.h | 9 +++++++++ include/configs/FADS823.h | 1 - include/configs/FADS850SAR.h | 9 +++++++++ include/configs/G2000.h | 9 +++++++++ include/configs/GENIETV.h | 9 +++++++++ include/configs/GTH.h | 9 +++++++++ include/configs/HH405.h | 17 +++++++++++++---- include/configs/HIDDEN_DRAGON.h | 9 +++++++++ include/configs/HUB405.h | 9 +++++++++ include/configs/IDS8247.h | 2 +- include/configs/ISPAN.h | 9 +++++++++ include/configs/IceCube.h | 25 +++++++++++++++---------- 39 files changed, 354 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/include/configs/A3000.h b/include/configs/A3000.h index eb074907666..0a9a1ff90c8 100644 --- a/include/configs/A3000.h +++ b/include/configs/A3000.h @@ -53,6 +53,15 @@ #define CONFIG_BOOTDELAY 5 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/ADCIOP.h b/include/configs/ADCIOP.h index f79fad18612..46329918ef1 100644 --- a/include/configs/ADCIOP.h +++ b/include/configs/ADCIOP.h @@ -59,6 +59,15 @@ #define CONFIG_IPADDR 10.0.18.222 #define CONFIG_SERVERIP 10.0.18.190 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + /* * Command line configuration. */ diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h index 0635506e628..d4ee14c837f 100644 --- a/include/configs/ADNPESC1.h +++ b/include/configs/ADNPESC1.h @@ -564,6 +564,15 @@ #define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + /* * Command line configuration. */ diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h index 015699dbdcf..d25aa74a452 100644 --- a/include/configs/AP1000.h +++ b/include/configs/AP1000.h @@ -67,6 +67,14 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + /* * Command line configuration. */ diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 5ac86bef860..6dcfbc15d4c 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -68,6 +68,15 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/AR405.h b/include/configs/AR405.h index 785f9455051..0f301ec0c6a 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -72,6 +72,15 @@ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index f0ec761ebb5..9e0ee371c2c 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -60,6 +60,15 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/Adder.h b/include/configs/Adder.h index 9a429442fd9..5e076dcc41c 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -53,6 +53,15 @@ #endif /* CONFIG_MPC852T */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h index e47872d27ea..3f2f6140f63 100644 --- a/include/configs/Alaska8220.h +++ b/include/configs/Alaska8220.h @@ -65,6 +65,15 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index aec4d83f251..844bdc5d883 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -143,6 +143,15 @@ #endif /* CONFIG_POST */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -449,8 +458,7 @@ #endif /* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) + * Enable loopw command. */ #define CONFIG_LOOPW diff --git a/include/configs/BMW.h b/include/configs/BMW.h index b062316a09b..bb7856f675d 100644 --- a/include/configs/BMW.h +++ b/include/configs/BMW.h @@ -66,6 +66,15 @@ #define CFG_DOC_SHORT_TIMEOUT 1 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -76,7 +85,7 @@ #define CONFIG_CMD_ELF -/* CFG_CMD_DOC required legacy NAND support */ +/* CONFIG_CMD_DOC required legacy NAND support */ #define CFG_NAND_LEGACY #if 0 diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index 8e09c527646..0e082b318bb 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -57,6 +57,15 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index 33c8b1c2d7b..62a2eaa2365 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -120,6 +120,15 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index def2646cc20..a3717b9052f 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -54,6 +54,15 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/CPCI440.h b/include/configs/CPCI440.h index 73b3e8a6ebe..318ada1a4fb 100644 --- a/include/configs/CPCI440.h +++ b/include/configs/CPCI440.h @@ -173,6 +173,15 @@ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index e0b4d8c178e..c7b623a1d6d 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -55,6 +55,24 @@ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/DASA_SIM.h b/include/configs/DASA_SIM.h index b1638ce1a29..627ea14826b 100644 --- a/include/configs/DASA_SIM.h +++ b/include/configs/DASA_SIM.h @@ -58,6 +58,15 @@ #define CONFIG_SERVERIP 10.0.18.190 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/DK1C20.h b/include/configs/DK1C20.h index c3bd2cb8415..0ddf0e3aeb9 100644 --- a/include/configs/DK1C20.h +++ b/include/configs/DK1C20.h @@ -447,6 +447,15 @@ #define CFG_NIOS_ASMIBASE CFG_NIOS_CPU_ASMI0 /* ASMI base address */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/DK1S10.h b/include/configs/DK1S10.h index a5530a6c8dc..0032fd3db71 100644 --- a/include/configs/DK1S10.h +++ b/include/configs/DK1S10.h @@ -454,6 +454,15 @@ #endif /* CFG_NIOS_CPU_PIO_NUMS */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/DP405.h b/include/configs/DP405.h index b50d4f905b6..2eadbea35d6 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -56,6 +56,15 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/DU405.h b/include/configs/DU405.h index 2093b373644..5c595f57d26 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -59,6 +59,15 @@ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index 07f31d52c07..a8697ec88de 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -69,6 +69,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h index db133c64407..cfa6335927a 100644 --- a/include/configs/EP1C20.h +++ b/include/configs/EP1C20.h @@ -161,6 +161,15 @@ #define CONFIG_SERVERIP 192.168.2.16 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h index 67a162d9d3a..7c526f759e7 100644 --- a/include/configs/EP1S10.h +++ b/include/configs/EP1S10.h @@ -155,6 +155,15 @@ #define CONFIG_SERVERIP 192.168.2.16 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h index 2363835b9f4..1fe8f68c2e6 100644 --- a/include/configs/EP1S40.h +++ b/include/configs/EP1S40.h @@ -155,6 +155,15 @@ #define CONFIG_SERVERIP 192.168.2.16 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h index 60a45086d65..89e0eebeead 100644 --- a/include/configs/EP88x.h +++ b/include/configs/EP88x.h @@ -50,6 +50,15 @@ #define CFG_8xx_CPUCLK_MIN 40000000 #define CFG_8xx_CPUCLK_MAX 133000000 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index 2320747c36d..5d48d2bbb68 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -97,6 +97,15 @@ #define CONFIG_PHY_ADDR 1 /* PHY address */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h index fdbf1258229..a3f38bb3a32 100644 --- a/include/configs/EXBITGEN.h +++ b/include/configs/EXBITGEN.h @@ -83,6 +83,15 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/FADS823.h b/include/configs/FADS823.h index bc3957629ca..a562b2fa4e8 100644 --- a/include/configs/FADS823.h +++ b/include/configs/FADS823.h @@ -46,7 +46,6 @@ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -/*Now included by CFG_CMD_PCMCIA */ /*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */ /* Video related */ diff --git a/include/configs/FADS850SAR.h b/include/configs/FADS850SAR.h index c2238c9a96c..c8ce25957b0 100644 --- a/include/configs/FADS850SAR.h +++ b/include/configs/FADS850SAR.h @@ -62,6 +62,15 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/G2000.h b/include/configs/G2000.h index 24eff02ac66..9c713c6c26f 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -89,6 +89,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/GENIETV.h b/include/configs/GENIETV.h index 67525db3312..785355a8e66 100644 --- a/include/configs/GENIETV.h +++ b/include/configs/GENIETV.h @@ -106,6 +106,15 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/GTH.h b/include/configs/GTH.h index f398bad79a0..79f5714e6f0 100644 --- a/include/configs/GTH.h +++ b/include/configs/GTH.h @@ -98,6 +98,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 58f29cd6667..00f481c4b52 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -98,11 +98,18 @@ #define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ #define CFG_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */ -#define ADD_BMP_CMD CFG_CMD_BMP -#else -#define ADD_BMP_CMD 0 #endif /* CONFIG_VIDEO */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -120,9 +127,11 @@ #define CONFIG_CMD_DATE #define CONFIG_CMD_MII #define CONFIG_CMD_PING -#define CONFIG_BMP_CMD #define CONFIG_CMD_EEPROM +#ifdef CONFIG_VIDEO +#define CONFIG_CMD_BMP +#endif #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/HIDDEN_DRAGON.h b/include/configs/HIDDEN_DRAGON.h index 972ca0884f2..26dd954c18a 100644 --- a/include/configs/HIDDEN_DRAGON.h +++ b/include/configs/HIDDEN_DRAGON.h @@ -53,6 +53,15 @@ #define CONFIG_DRAM_SPEED 100 /* MHz */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index d29bddbe1ca..661b895f9a1 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -61,6 +61,15 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 455bbe3f633..85d2bb3f513 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -303,7 +303,7 @@ #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0) #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0))) -#endif /* CFG_CMD_NAND */ +#endif /* CONFIG_CMD_NAND */ /*----------------------------------------------------------------------- * Hard Reset Configuration Words diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h index e6ef7656629..965b515f0e6 100644 --- a/include/configs/ISPAN.h +++ b/include/configs/ISPAN.h @@ -106,6 +106,15 @@ #define CONFIG_BAUDRATE 38400 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index c80c2d4ad3c..cc902c842d5 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -64,7 +64,6 @@ #define CONFIG_PCI_IO_BUS 0x50000000 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0x01000000 -#define ADD_PCI_CMD CFG_CMD_PCI #endif #define CFG_XLB_PIPELINING 1 @@ -75,11 +74,8 @@ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#else /* MPC5100 */ - +#else #define CONFIG_MII 1 -#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ - #endif /* Partitions */ @@ -90,15 +86,21 @@ /* USB */ #if 1 #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 #endif #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -110,8 +112,11 @@ #define CONFIG_CMD_IDE #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP -#define CONFIG_PCI_CMD -#define CONFIG_USB_CMD +#define CONFIG_CMD_USB + +#if defined(CONFIG_PCI) +#define CONFIG_CMD_PCI +#endif #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ -- cgit v1.3.1 From 659e2f6736232a08acca8785c206e2b4d9cd07d7 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Jul 2007 09:10:49 -0500 Subject: include/configs/[J-O]*: Cleanup BOOTP and lingering CFG_CMD_*. Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h used to be included but CONFIG_BOOTP_MASK was not defined. Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger --- include/configs/JSE.h | 9 +++++++++ include/configs/KAREF.h | 9 +++++++++ include/configs/M5271EVB.h | 9 +++++++++ include/configs/M5272C3.h | 9 +++++++++ include/configs/M5282EVB.h | 9 +++++++++ include/configs/MBX.h | 9 +++++++++ include/configs/METROBOX.h | 9 +++++++++ include/configs/MIP405.h | 9 +++++++++ include/configs/ML2.h | 9 +++++++++ include/configs/MOUSSE.h | 9 +++++++++ include/configs/MPC8260ADS.h | 9 +++++++++ include/configs/MPC8349EMDS.h | 9 +++++++++ include/configs/MPC8349ITX.h | 11 ++++++++++- include/configs/MPC8360EMDS.h | 9 +++++++++ include/configs/MPC8540ADS.h | 9 +++++++++ include/configs/MPC8540EVAL.h | 9 +++++++++ include/configs/MPC8541CDS.h | 9 +++++++++ include/configs/MPC8544DS.h | 9 +++++++++ include/configs/MPC8548CDS.h | 9 +++++++++ include/configs/MPC8555CDS.h | 9 +++++++++ include/configs/MPC8560ADS.h | 9 +++++++++ include/configs/MPC8641HPCN.h | 9 +++++++++ include/configs/MUSENKI.h | 9 +++++++++ include/configs/OCRTC.h | 9 +++++++++ include/configs/ORSG.h | 9 +++++++++ include/configs/OXC.h | 9 +++++++++ 26 files changed, 235 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/JSE.h b/include/configs/JSE.h index c67c063e8bf..ea3b0b4a325 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -136,6 +136,15 @@ #define CONFIG_PHY_ADDR 1 /* PHY address */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index f0368049d1d..3644e43885e 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -178,6 +178,15 @@ #define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index 1907a3c4396..885a8821bf9 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -65,6 +65,15 @@ #define CFG_ENV_IS_IN_FLASH 1 #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 417166524f6..cc456dc08a9 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -61,6 +61,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index cf3076efc59..f2a7644930f 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -51,6 +51,15 @@ #define CFG_ENV_IS_IN_FLASH 1 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MBX.h b/include/configs/MBX.h index ae8913ca86a..d9f2addb565 100644 --- a/include/configs/MBX.h +++ b/include/configs/MBX.h @@ -72,6 +72,15 @@ #undef CONFIG_WATCHDOG /* watchdog disabled */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index e9aaedb8181..8d7ec5926bc 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -242,6 +242,15 @@ #define CFG_RX_ETH_BUFFER 32 /* #eth rx buff & descrs */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 192998e7956..5b526a0993f 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -51,6 +51,15 @@ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/ML2.h b/include/configs/ML2.h index 8d61d4861e7..f488275f239 100644 --- a/include/configs/ML2.h +++ b/include/configs/ML2.h @@ -76,6 +76,15 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MOUSSE.h b/include/configs/MOUSSE.h index 518bf1213ee..9370c24c500 100644 --- a/include/configs/MOUSSE.h +++ b/include/configs/MOUSSE.h @@ -60,6 +60,15 @@ #define CONFIG_BOOTDELAY 3 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index a36b69d6bbd..f3e5330c779 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -197,6 +197,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 9855a62a7fe..1567fcfae32 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -476,6 +476,15 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 799ff4a7ab0..121ff06dc5c 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -372,7 +372,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_NET_MULTI #define CONFIG_MII -#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ +#define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ #define CONFIG_TSEC1 @@ -416,6 +416,15 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_LOADS_ECHO /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index b355f89bf8b..4b32a140e81 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -457,6 +457,15 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index f103e47925e..7b010bfb595 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -408,6 +408,15 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index dea061abee9..0ce25cf24e7 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -260,6 +260,15 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 5f12eeecc51..50d3b6b8727 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -401,6 +401,15 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index b33d2255b39..d0f94a3e220 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -393,6 +393,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index cef92d2540d..2e84fc8748d 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -427,6 +427,15 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 077aaa37713..a3025bd7157 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -401,6 +401,15 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index affe535e717..8ce8a537526 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -432,6 +432,15 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 0579a35f896..808c19f7673 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -476,6 +476,15 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MUSENKI.h b/include/configs/MUSENKI.h index d6dafb2c8e2..f8cf01e5d3e 100644 --- a/include/configs/MUSENKI.h +++ b/include/configs/MUSENKI.h @@ -53,6 +53,15 @@ #define CONFIG_BOOTDELAY 5 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 00f747ef431..5840ea25f4b 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -55,6 +55,15 @@ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index bab4c3d37d3..937df229f16 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -55,6 +55,15 @@ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/OXC.h b/include/configs/OXC.h index e70d4850a9f..8d61bcd2d41 100644 --- a/include/configs/OXC.h +++ b/include/configs/OXC.h @@ -52,6 +52,15 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ -- cgit v1.3.1 From a1aa0bb502e25fd598b5e0ccdfb2c174921d714a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Jul 2007 09:22:23 -0500 Subject: include/configs/[P-Z]*: Cleanup BOOTP and lingering CFG_CMD_*. Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h used to be included but CONFIG_BOOTP_MASK was not defined. Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger --- include/configs/PATI.h | 9 +++++++++ include/configs/PCI405.h | 9 +++++++++ include/configs/PCI5441.h | 9 +++++++++ include/configs/PIP405.h | 9 +++++++++ include/configs/PK1C20.h | 9 +++++++++ include/configs/PLU405.h | 9 +++++++++ include/configs/PM520.h | 9 +++++++++ include/configs/PM854.h | 9 +++++++++ include/configs/PM856.h | 9 +++++++++ include/configs/PMC405.h | 9 +++++++++ include/configs/PN62.h | 9 +++++++++ include/configs/PPChameleonEVB.h | 9 +++++++++ include/configs/RPXsuper.h | 9 +++++++++ include/configs/Rattler.h | 11 ++++++++++- include/configs/SBC8540.h | 9 +++++++++ include/configs/SL8245.h | 9 +++++++++ include/configs/SX1.h | 9 +++++++++ include/configs/SXNI855T.h | 9 +++++++++ include/configs/Sandpoint8240.h | 9 +++++++++ include/configs/Sandpoint8245.h | 9 +++++++++ include/configs/TASREG.h | 9 +++++++++ include/configs/TB5200.h | 12 ++++++++++-- include/configs/TOP5200.h | 9 +++++++++ include/configs/TQM5200.h | 12 ++++++++++-- include/configs/TQM8272.h | 14 ++++++++------ include/configs/TQM834x.h | 9 +++++++++ include/configs/TQM85xx.h | 9 +++++++++ include/configs/TQM885D.h | 3 +-- include/configs/Total5200.h | 9 +++++++++ include/configs/VCMA9.h | 9 +++++++++ include/configs/VOH405.h | 9 +++++++++ include/configs/VoVPN-GW.h | 9 +++++++++ include/configs/W7OLMC.h | 9 +++++++++ include/configs/W7OLMG.h | 9 +++++++++ include/configs/WUH405.h | 9 +++++++++ include/configs/XPEDITE1K.h | 9 +++++++++ include/configs/Yukon8220.h | 9 +++++++++ include/configs/ZPC1900.h | 9 +++++++++ 38 files changed, 336 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/include/configs/PATI.h b/include/configs/PATI.h index b0f86157deb..0de7591da66 100644 --- a/include/configs/PATI.h +++ b/include/configs/PATI.h @@ -40,6 +40,15 @@ #define CONFIG_BAUDRATE 9600 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 2dfd2311738..d6e7082f6a9 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -69,6 +69,15 @@ #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/PCI5441.h b/include/configs/PCI5441.h index 1bfcd37d060..24b25d98500 100644 --- a/include/configs/PCI5441.h +++ b/include/configs/PCI5441.h @@ -123,6 +123,15 @@ #define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 0a2d7d7f9d4..efa015746e1 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -41,6 +41,15 @@ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index 49a285c5d1c..d90351add35 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -161,6 +161,15 @@ #define CONFIG_SERVERIP 192.168.2.16 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 5742db6f2a2..54703731af7 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -62,6 +62,15 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/PM520.h b/include/configs/PM520.h index 3cd3511f787..5ba8f4a4e2a 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -89,6 +89,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/PM854.h b/include/configs/PM854.h index d79dd768f90..dbf94228ae6 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -304,6 +304,15 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 5681d433692..6bdfa5d8f1f 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -307,6 +307,15 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index bdbc900ba0c..b29f368f57c 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -64,6 +64,15 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/PN62.h b/include/configs/PN62.h index 8346d8ca028..72acf5ae8d5 100644 --- a/include/configs/PN62.h +++ b/include/configs/PN62.h @@ -42,6 +42,15 @@ #define CONFIG_CONS_INDEX 1 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 709ce5f0e94..dd1decdcd94 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -114,6 +114,15 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/RPXsuper.h b/include/configs/RPXsuper.h index 1401da35abc..dfadd2a11f0 100644 --- a/include/configs/RPXsuper.h +++ b/include/configs/RPXsuper.h @@ -150,6 +150,15 @@ #define CFG_PROMPT "=> " +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h index 5bdf57193be..d7652fa9ba5 100644 --- a/include/configs/Rattler.h +++ b/include/configs/Rattler.h @@ -126,6 +126,15 @@ #define CONFIG_BAUDRATE 38400 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -207,7 +216,7 @@ #define MTDIDS_DEFAULT "nor0=rattler-0" #define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)" */ -#endif /* CFG_CMD_JFFS2 */ +#endif /* CONFIG_CMD_JFFS2 */ #define CFG_MONITOR_BASE TEXT_BASE #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index a5397c2e08b..f2c3699ab74 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -339,6 +339,15 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/SL8245.h b/include/configs/SL8245.h index b8e5c7de730..4d9d41b9277 100644 --- a/include/configs/SL8245.h +++ b/include/configs/SL8245.h @@ -54,6 +54,15 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/SX1.h b/include/configs/SX1.h index 588d3459e09..05cef873e5f 100644 --- a/include/configs/SX1.h +++ b/include/configs/SX1.h @@ -94,6 +94,15 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/SXNI855T.h b/include/configs/SXNI855T.h index efc500ca5b3..8f2a5ece2c7 100644 --- a/include/configs/SXNI855T.h +++ b/include/configs/SXNI855T.h @@ -147,6 +147,15 @@ #define CFG_DISCOVER_PHY +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/Sandpoint8240.h b/include/configs/Sandpoint8240.h index d19c27e84b2..5bbe3c5919d 100644 --- a/include/configs/Sandpoint8240.h +++ b/include/configs/Sandpoint8240.h @@ -81,6 +81,15 @@ #define CONFIG_BOOTCOMMAND "run flash_self" +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/Sandpoint8245.h b/include/configs/Sandpoint8245.h index cbad484b072..a08451eb30b 100644 --- a/include/configs/Sandpoint8245.h +++ b/include/configs/Sandpoint8245.h @@ -52,6 +52,15 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/TASREG.h b/include/configs/TASREG.h index b0116e7acda..2b2ae01f635 100644 --- a/include/configs/TASREG.h +++ b/include/configs/TASREG.h @@ -51,6 +51,15 @@ #undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 3d90efb1c17..1c6a9ae4f1b 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -87,6 +87,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -408,8 +417,7 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ /* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) + * Enable loopw command. */ #define CONFIG_LOOPW diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h index 73d25ea868e..7240ce12835 100644 --- a/include/configs/TOP5200.h +++ b/include/configs/TOP5200.h @@ -99,6 +99,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 598c1c61c61..63d77e2941a 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -147,6 +147,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -580,8 +589,7 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ /* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) + * Enable loopw command. */ #define CONFIG_LOOPW diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h index 05e2e9ac188..50f67524fde 100644 --- a/include/configs/TQM8272.h +++ b/include/configs/TQM8272.h @@ -97,10 +97,6 @@ /* enable I2C and select the hardware/software driver */ #undef CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ -#define ADD_CMD_I2C CFG_CMD_I2C | \ - CFG_CMD_DATE |\ - CFG_CMD_DTT |\ - CFG_CMD_EEPROM #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F @@ -140,7 +136,6 @@ #else #undef CONFIG_HARD_I2C #undef CONFIG_SOFT_I2C -#define ADD_CMD_I2C 0 #endif /* @@ -295,6 +290,13 @@ #define CONFIG_CMD_PING #define CONFIG_CMD_SNTP +#if CONFIG_I2C + #define CONFIG_CMD_I2C + #define CONFIG_CMD_DATE + #define CONFIG_CMD_DTT + #define CONFIG_CMD_EEPROM +#endif + /* * Miscellaneous configurable options @@ -439,7 +441,7 @@ WRITE_NAND(d, addr); \ } while(0) -#endif /* CFG_CMD_NAND */ +#endif /* CONFIG_CMD_NAND */ #define CONFIG_PCI #ifdef CONFIG_PCI diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 684cb304568..c3efb7bb9c7 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -315,6 +315,15 @@ extern int tqm834x_num_flash_banks; #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index b17d5e30fc9..d5ce3ba7169 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -358,6 +358,15 @@ #define CONFIG_TIMESTAMP /* Print image info with ts */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index 19fdaf0b6bc..f36b729cd5e 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -198,8 +198,7 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* - * Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) + * Enable loopw command. */ #define CONFIG_LOOPW diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 2a1cb89ad4f..9edf79022dc 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -110,6 +110,15 @@ #define CONFIG_USB_STORAGE +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index ab802a3cd58..df6894f3240 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -49,6 +49,15 @@ #define CONFIG_INITRD_TAG 1 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 3f2c32b6b25..34f0ebdcfa2 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -59,6 +59,15 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h index ebe634f133c..14057847b82 100644 --- a/include/configs/VoVPN-GW.h +++ b/include/configs/VoVPN-GW.h @@ -137,6 +137,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index fd810961d0e..fc177fb1f56 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -70,6 +70,15 @@ #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index a5ce6854124..20d693fa478 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -76,6 +76,15 @@ #define CFG_DTT_HYSTERESIS 3 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index f7865200c1e..c1b3da863ed 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -61,6 +61,15 @@ #define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 4b8fbe6f4d6..611f5a62caa 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -183,6 +183,15 @@ extern void out32(unsigned int, unsigned long); #define CONFIG_HAS_ETH3 1 /* add support for "eth3addr" */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h index 07fab44314d..00c4ff093a6 100644 --- a/include/configs/Yukon8220.h +++ b/include/configs/Yukon8220.h @@ -65,6 +65,15 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index fb5bc0fdb3b..7c1a5b9e88f 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -107,6 +107,15 @@ #define CONFIG_BAUDRATE 38400 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ -- cgit v1.3.1 From 80ff4f99b84b64edca3fd10da365ec1493be1c95 Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Jul 2007 09:29:01 -0500 Subject: include/configs/[a-e]*: Cleanup BOOTP and lingering CFG_CMD_*. Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h used to be included but CONFIG_BOOTP_MASK was not defined. Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger --- include/configs/adsvix.h | 9 +++++++++ include/configs/aev.h | 12 ++++++++++-- include/configs/alpr.h | 9 +++++++++ include/configs/at91rm9200dk.h | 9 +++++++++ include/configs/bamboo.h | 9 +++++++++ include/configs/barco.h | 3 ++- include/configs/bubinga.h | 9 +++++++++ include/configs/canmb.h | 9 +++++++++ include/configs/cerf250.h | 9 +++++++++ include/configs/cm4008.h | 9 +++++++++ include/configs/cm41xx.h | 9 +++++++++ include/configs/cmc_pu2.h | 9 +++++++++ include/configs/cmi_mpc5xx.h | 9 +++++++++ include/configs/cobra5272.h | 9 +++++++++ include/configs/cogent_mpc8260.h | 9 +++++++++ include/configs/cogent_mpc8xx.h | 9 +++++++++ include/configs/cpci5200.h | 9 +++++++++ include/configs/cradle.h | 9 +++++++++ include/configs/csb226.h | 9 +++++++++ include/configs/csb637.h | 9 +++++++++ include/configs/dbau1x00.h | 9 +++++++++ include/configs/debris.h | 9 +++++++++ include/configs/delta.h | 9 +++++++++ include/configs/dnp1110.h | 9 +++++++++ include/configs/eXalion.h | 9 +++++++++ include/configs/ebony.h | 9 +++++++++ include/configs/ep8248.h | 13 +++++++++++-- include/configs/ep8260.h | 9 +++++++++ include/configs/ep82xxm.h | 13 +++++++++++-- 29 files changed, 259 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/adsvix.h b/include/configs/adsvix.h index 0d64013b212..703d3124e6f 100644 --- a/include/configs/adsvix.h +++ b/include/configs/adsvix.h @@ -69,6 +69,15 @@ #define CONFIG_DOS_PARTITION 1 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/aev.h b/include/configs/aev.h index 93b20db5cea..5bab793e9cc 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -91,6 +91,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -343,8 +352,7 @@ #endif /* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) + * Enable loopw command. */ #define CONFIG_LOOPW diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 27f2831b525..d88c3ad43b0 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -211,6 +211,15 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h index db57dc11f12..ecfa21d8280 100644 --- a/include/configs/at91rm9200dk.h +++ b/include/configs/at91rm9200dk.h @@ -98,6 +98,15 @@ /* #define CONFIG_ENV_OVERWRITE 1 */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index c1fdaf8d570..19b29aaf36c 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -317,6 +317,15 @@ #endif /*CONFIG_440EP*/ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/barco.h b/include/configs/barco.h index 09078d42c62..0bb446f7844 100644 --- a/include/configs/barco.h +++ b/include/configs/barco.h @@ -92,6 +92,8 @@ #define CONFIG_CMD_EEPROM #define CONFIG_CMD_PCI +#undef CONFIG_CMD_NET + #define CONFIG_HUSH_PARSER 1 /* use "hush" command parser */ #define CONFIG_BOOTDELAY 1 @@ -116,7 +118,6 @@ */ #define CONFIG_PCI /* include pci support */ #undef CONFIG_PCI_PNP -#undef CFG_CMD_NET #define PCI_ENET0_IOADDR 0x80000000 #define PCI_ENET0_MEMADDR 0x80000000 diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 16892590e00..7736a1e32d0 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -138,6 +138,15 @@ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Bubinga */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/canmb.h b/include/configs/canmb.h index 9bb5b830471..d577b95e05d 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -48,6 +48,15 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index 0240ef2194a..e06735da631 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -62,6 +62,15 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h index d0ac46b3caf..ae40b358e95 100644 --- a/include/configs/cm4008.h +++ b/include/configs/cm4008.h @@ -59,6 +59,15 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h index b62e3611736..c1dd33d1d25 100644 --- a/include/configs/cm41xx.h +++ b/include/configs/cm41xx.h @@ -59,6 +59,15 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h index 9e70900cb70..f32c8c2c66b 100644 --- a/include/configs/cmc_pu2.h +++ b/include/configs/cmc_pu2.h @@ -113,6 +113,15 @@ #define CONFIG_BOOTDELAY 1 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/cmi_mpc5xx.h b/include/configs/cmi_mpc5xx.h index dbc41e97fbf..cd92af23522 100644 --- a/include/configs/cmi_mpc5xx.h +++ b/include/configs/cmi_mpc5xx.h @@ -45,6 +45,15 @@ #define CONFIG_BAUDRATE 57600 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 4ab60cf2717..510524ad36a 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -131,6 +131,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/cogent_mpc8260.h b/include/configs/cogent_mpc8260.h index 63150902c87..84d50c71dd5 100644 --- a/include/configs/cogent_mpc8260.h +++ b/include/configs/cogent_mpc8260.h @@ -88,6 +88,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/cogent_mpc8xx.h b/include/configs/cogent_mpc8xx.h index c246ff5e648..ce38af1dd85 100644 --- a/include/configs/cogent_mpc8xx.h +++ b/include/configs/cogent_mpc8xx.h @@ -59,6 +59,15 @@ #define CFG_I2C_SLAVE 0x7F +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index c4ed19abdd1..ce4ea1f8dbe 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -99,6 +99,15 @@ #define CONFIG_USB_STORAGE #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/cradle.h b/include/configs/cradle.h index 5d6419fe1f2..eb93a8f083f 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -62,6 +62,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/csb226.h b/include/configs/csb226.h index 04bdf867b17..0be0f219248 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -58,6 +58,15 @@ #undef CONFIG_MISC_INIT_R /* not used yet */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/csb637.h b/include/configs/csb637.h index ac2fe54409d..976dae39f69 100644 --- a/include/configs/csb637.h +++ b/include/configs/csb637.h @@ -100,6 +100,15 @@ /* #define CONFIG_ENV_OVERWRITE 1 */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index c0f5a099001..b2f606f498b 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -80,6 +80,15 @@ #endif /* CONFIG_DBAU1550 */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/debris.h b/include/configs/debris.h index 96c76483aaf..7667e5e60e3 100644 --- a/include/configs/debris.h +++ b/include/configs/debris.h @@ -123,6 +123,15 @@ #define CONFIG_DRAM_SPEED 100 /* MHz */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/delta.h b/include/configs/delta.h index 7df72800f58..dbfe7a702b5 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -88,6 +88,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h index e58a2f219c8..d32e0460234 100644 --- a/include/configs/dnp1110.h +++ b/include/configs/dnp1110.h @@ -67,6 +67,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/eXalion.h b/include/configs/eXalion.h index ac1ef959a70..f8e2c885b06 100644 --- a/include/configs/eXalion.h +++ b/include/configs/eXalion.h @@ -58,6 +58,15 @@ /*#define CONFIG_DRAM_SPEED 66 */ /* MHz */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index d86a9efbefd..2c626a03288 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -209,6 +209,15 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h index 8653b55affe..85ad70a0d50 100644 --- a/include/configs/ep8248.h +++ b/include/configs/ep8248.h @@ -124,6 +124,15 @@ #define CONFIG_BAUDRATE 38400 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -192,13 +201,13 @@ #define CFG_JFFS2_LAST_SECTOR 62 #define CFG_JFFS2_SORT_FRAGMENTS #define CFG_JFFS_CUSTOM_PART -#endif /* CFG_CMD_JFFS2 */ +#endif #if defined(CONFIG_CMD_I2C) #define CONFIG_HARD_I2C 1 /* To enable I2C support */ #define CFG_I2C_SPEED 100000 /* I2C speed */ #define CFG_I2C_SLAVE 0x7F /* I2C slave address */ -#endif /* CFG_CMD_I2C */ +#endif #define CFG_MONITOR_BASE TEXT_BASE #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h index 25f9bd6a718..f412ec8ed80 100644 --- a/include/configs/ep8260.h +++ b/include/configs/ep8260.h @@ -291,6 +291,15 @@ #define CFG_PROMPT_HUSH_PS2 "> " +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index 430ff4b8f48..4febd322a4f 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h @@ -109,6 +109,15 @@ #define CFG_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -318,13 +327,13 @@ #define CFG_JFFS2_LAST_SECTOR 62 #define CFG_JFFS2_SORT_FRAGMENTS #define CFG_JFFS_CUSTOM_PART -#endif /* CFG_CMD_JFFS2 */ +#endif #if defined(CONFIG_CMD_I2C) #define CONFIG_HARD_I2C 1 /* To enable I2C support */ #define CFG_I2C_SPEED 100000 /* I2C speed */ #define CFG_I2C_SLAVE 0x7F /* I2C slave address */ -#endif /* CFG_CMD_I2C */ +#endif #define CFG_MONITOR_BASE TEXT_BASE #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -- cgit v1.3.1 From 7f5c01577400c74cc5bac74f41dd0d3c79df623c Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Jul 2007 09:38:02 -0500 Subject: include/configs/[g-o]*: Cleanup BOOTP and lingering CFG_CMD_*. Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h used to be included but CONFIG_BOOTP_MASK was not defined. Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger --- include/configs/gth2.h | 9 +++++++++ include/configs/hmi1001.h | 12 ++++++++++-- include/configs/hymod.h | 9 +++++++++ include/configs/idmr.h | 9 +++++++++ include/configs/incaip.h | 9 +++++++++ include/configs/inka4x0.h | 12 ++++++++++-- include/configs/innokom.h | 9 +++++++++ include/configs/ixdp425.h | 9 +++++++++ include/configs/ixdpg425.h | 9 +++++++++ include/configs/jupiter.h | 14 +++++++++++++- include/configs/kb9202.h | 9 +++++++++ include/configs/lart.h | 9 +++++++++ include/configs/logodl.h | 9 +++++++++ include/configs/lpd7a400.h | 9 +++++++++ include/configs/lpd7a404.h | 9 +++++++++ include/configs/luan.h | 9 +++++++++ include/configs/lubbock.h | 9 +++++++++ include/configs/mcc200.h | 9 +++++++++ include/configs/mecp5200.h | 9 +++++++++ include/configs/ml300.h | 9 +++++++++ include/configs/mp2usb.h | 9 +++++++++ include/configs/mx1ads.h | 9 +++++++++ include/configs/mx1fs2.h | 11 ++++++++++- include/configs/ns9750dev.h | 9 +++++++++ include/configs/o2dnt.h | 13 ++++++++++--- include/configs/ocotea.h | 9 +++++++++ 26 files changed, 242 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/configs/gth2.h b/include/configs/gth2.h index 0247b7d25c0..c2a50c1f473 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -72,6 +72,15 @@ #define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm" +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index 7e1897a7593..6c15b4e14c0 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -51,6 +51,15 @@ #define CONFIG_DOS_PARTITION +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -242,8 +251,7 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ /* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) + * Enable loopw command. */ #define CONFIG_LOOPW diff --git a/include/configs/hymod.h b/include/configs/hymod.h index 8a3ad6861e4..b789067f81d 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -173,6 +173,15 @@ #define CONFIG_LAST_STAGE_INIT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/idmr.h b/include/configs/idmr.h index 99266334636..1ab7b27a5d8 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -79,6 +79,15 @@ "" +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/incaip.h b/include/configs/incaip.h index ef8f7249574..4caf54efd31 100644 --- a/include/configs/incaip.h +++ b/include/configs/incaip.h @@ -82,6 +82,15 @@ #define CONFIG_BOOTCOMMAND "run flash_self" +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 19f2f194f6a..0fac28fadd7 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -72,6 +72,15 @@ #define CONFIG_ISO_PARTITION +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -259,8 +268,7 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ /* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) + * Enable loopw command. */ #define CONFIG_LOOPW diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 38ccf89cd1e..5310e0d428f 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -55,6 +55,15 @@ #define CONFIG_MISC_INIT_R 1 /* we have a misc_init_r() function */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/ixdp425.h b/include/configs/ixdp425.h index 8c1ab242f3c..bc5f9e19bdc 100644 --- a/include/configs/ixdp425.h +++ b/include/configs/ixdp425.h @@ -54,6 +54,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h index 6c103ce6f32..da59230bb65 100644 --- a/include/configs/ixdpg425.h +++ b/include/configs/ixdpg425.h @@ -76,6 +76,15 @@ #define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index e53b848c34a..b68c5aa46e5 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -66,7 +66,6 @@ #define CONFIG_PCI_IO_BUS 0x50000000 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0x01000000 -#define ADD_PCI_CMD CFG_CMD_PCI #endif #define CFG_XLB_PIPELINING 1 @@ -83,6 +82,15 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -91,6 +99,10 @@ #define CONFIG_CMD_NFS #define CONFIG_CMD_SNTP +#if defined(CONFIG_PCI) +#define CODFIG_CMD_PCI +#endif + /* * Autobooting diff --git a/include/configs/kb9202.h b/include/configs/kb9202.h index 4741ead8155..75d9c3b3b46 100644 --- a/include/configs/kb9202.h +++ b/include/configs/kb9202.h @@ -79,6 +79,15 @@ #define CONFIG_ENV_OVERWRITE 1 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/lart.h b/include/configs/lart.h index 98bc3b257b8..8f18c9f1b1b 100644 --- a/include/configs/lart.h +++ b/include/configs/lart.h @@ -60,6 +60,15 @@ #define CONFIG_BAUDRATE 9600 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/logodl.h b/include/configs/logodl.h index 7c11eeb7071..2b2d37751e0 100644 --- a/include/configs/logodl.h +++ b/include/configs/logodl.h @@ -55,6 +55,15 @@ #undef CONFIG_MISC_INIT_R /* FIXME: misc_init_r() missing */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h index 414cb14da8b..04148898eac 100644 --- a/include/configs/lpd7a400.h +++ b/include/configs/lpd7a400.h @@ -56,6 +56,15 @@ #define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h index 87815cb170f..11ede968180 100644 --- a/include/configs/lpd7a404.h +++ b/include/configs/lpd7a404.h @@ -56,6 +56,15 @@ #define CONFIG_TIMESTAMP 1 /* Print timestamp info for images */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/luan.h b/include/configs/luan.h index 82af2fb0759..72aae09d039 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -214,6 +214,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index eed589066e0..4adf2542219 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -68,6 +68,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index 10e25f02290..744f551c3e8 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -92,6 +92,15 @@ #define CONFIG_AUTO_UPDATE 1 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 6f0d4973f00..49919fbafbb 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -87,6 +87,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/ml300.h b/include/configs/ml300.h index 423c6ebbb77..0183041842a 100644 --- a/include/configs/ml300.h +++ b/include/configs/ml300.h @@ -88,6 +88,15 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h index 3a6224012a2..8d6f2613c17 100644 --- a/include/configs/mp2usb.h +++ b/include/configs/mp2usb.h @@ -129,6 +129,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h index 0ae2780f202..5125b21e04f 100644 --- a/include/configs/mx1ads.h +++ b/include/configs/mx1ads.h @@ -79,6 +79,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h index 47ca0f1eee2..d527d098f57 100644 --- a/include/configs/mx1fs2.h +++ b/include/configs/mx1fs2.h @@ -35,6 +35,15 @@ #undef CONFIG_SILENT_CONSOLE /* use this to disable output */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -159,7 +168,7 @@ * Right now there is no gain for user, but later on booting kernel might be * possible. Consider using XIP kernel running from flash to save RAM * footprint. - * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. */ /* diff --git a/include/configs/ns9750dev.h b/include/configs/ns9750dev.h index e1806a70c60..1d691f9731d 100644 --- a/include/configs/ns9750dev.h +++ b/include/configs/ns9750dev.h @@ -70,6 +70,15 @@ #define CONFIG_BAUDRATE 38400 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index 9ed1ed856c8..f1d73e4c539 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -68,8 +68,6 @@ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#define ADD_PCI_CMD CFG_CMD_PCI - /* Partitions */ #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION @@ -78,6 +76,15 @@ #define CONFIG_TIMESTAMP /* Print image info with timestamp */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -89,7 +96,7 @@ #define CONFIG_CMD_NFS #define CONFIG_CMD_MII #define CONFIG_CMD_PING -#define CONFIG_PCI_CMD +#define CONFIG_CMD_PCI #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index fd45c1d9705..bc2fd33ff5e 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -233,6 +233,15 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ -- cgit v1.3.1 From 079a136c3588814784561d6e4856970ee82d6e2a Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Jul 2007 10:12:10 -0500 Subject: include/configs/[p-z]* + misc: Cleanup BOOTP and lingering CFG_CMD_*. Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h used to be included but CONFIG_BOOTP_MASK was not defined. Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger --- board/fads/fads.h | 10 ++++++++++ include/configs/MPC8313ERDB.h | 9 +++++++++ include/configs/MPC832XEMDS.h | 9 +++++++++ include/configs/MPC8568MDS.h | 9 +++++++++ include/configs/acadia.h | 9 +++++++++ include/configs/bf533-ezkit.h | 9 +++++++++ include/configs/bf533-stamp.h | 9 +++++++++ include/configs/bf537-stamp.h | 9 +++++++++ include/configs/bf561-ezkit.h | 9 +++++++++ include/configs/integratorap.h | 9 +++++++++ include/configs/integratorcp.h | 9 +++++++++ include/configs/katmai.h | 9 +++++++++ include/configs/lwmon5.h | 9 +++++++++ include/configs/ml401.h | 9 +++++++++ include/configs/motionpro.h | 9 +++++++++ include/configs/p3p440.h | 9 +++++++++ include/configs/pb1x00.h | 9 +++++++++ include/configs/pcs440ep.h | 9 +++++++++ include/configs/pdnb3.h | 9 +++++++++ include/configs/pf5200.h | 24 +++++++++++++----------- include/configs/pleb2.h | 9 +++++++++ include/configs/ppmc7xx.h | 9 +++++++++ include/configs/purple.h | 9 +++++++++ include/configs/pxa255_idp.h | 9 +++++++++ include/configs/r5200.h | 9 +++++++++ include/configs/rsdproto.h | 9 +++++++++ include/configs/sbc2410x.h | 9 +++++++++ include/configs/sbc8349.h | 9 +++++++++ include/configs/sbc8560.h | 9 +++++++++ include/configs/sc3.h | 9 +++++++++ include/configs/sc520_cdp.h | 9 +++++++++ include/configs/sc520_spunk.h | 9 +++++++++ include/configs/scb9328.h | 11 ++++++++++- include/configs/sequoia.h | 9 +++++++++ include/configs/shannon.h | 9 +++++++++ include/configs/smdk2400.h | 9 +++++++++ include/configs/smdk2410.h | 9 +++++++++ include/configs/smmaco4.h | 12 ++++++++++-- include/configs/sorcery.h | 9 +++++++++ include/configs/spc1920.h | 11 ++++++++++- include/configs/spieval.h | 12 ++++++++++-- include/configs/stxgp3.h | 9 +++++++++ include/configs/stxssa.h | 9 +++++++++ include/configs/suzaku.h | 9 +++++++++ include/configs/taishan.h | 9 +++++++++ include/configs/tb0229.h | 9 +++++++++ include/configs/trab.h | 9 +++++++++ include/configs/uc101.h | 12 ++++++++++-- include/configs/utx8245.h | 9 +++++++++ include/configs/v38b.h | 9 +++++++++ include/configs/walnut.h | 9 +++++++++ include/configs/wepep250.h | 11 ++++++++++- include/configs/xaeniax.h | 9 +++++++++ include/configs/xm250.h | 9 +++++++++ include/configs/xsengine.h | 9 +++++++++ include/configs/xupv2p.h | 9 +++++++++ include/configs/yosemite.h | 9 +++++++++ include/configs/yucca.h | 9 +++++++++ include/configs/zylonite.h | 9 +++++++++ 59 files changed, 542 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/board/fads/fads.h b/board/fads/fads.h index 8558b7426be..75237818cef 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -95,6 +95,16 @@ #define CFG_DISCOVER_PHY #endif + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + #if !defined(FADS_COMMANDS_ALREADY_DEFINED) /* * Command line configuration. diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 3334f0fe99a..45a7d81792d 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -341,6 +341,15 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 1984157e1cf..f62ca2c42be 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -423,6 +423,15 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 41b1ae1206c..eef168c252d 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -384,6 +384,15 @@ extern unsigned long get_clock_freq(void); #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 5bd8ac63e1d..e3f6e2c8b34 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -299,6 +299,15 @@ #define CONFIG_SUPPORT_VFAT +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index 487ca6a1897..6cb6bc4f71c 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -97,6 +97,15 @@ #define CONFIG_LOADS_ECHO 1 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index f93c61e4b7b..cce6ef79f27 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -289,6 +289,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h index bea157a45f6..b9a9e3cb792 100644 --- a/include/configs/bf537-stamp.h +++ b/include/configs/bf537-stamp.h @@ -163,6 +163,15 @@ #define CONFIG_NETCONSOLE 1 #define CONFIG_NET_MULTI 1 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 40f5abc7438..29662604f99 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -187,6 +187,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index be3b1140bb1..1452bf2c467 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -69,6 +69,15 @@ /*#define CONFIG_NET_MULTI */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 191c5e61e32..69310d4dfbc 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -71,6 +71,15 @@ #define CFG_SERIAL1 0x17000000 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 9258e7dd809..110ad44ee1b 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -211,6 +211,15 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 13cbed5e9a5..f24dac41704 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -224,6 +224,15 @@ #define CONFIG_ISO_PARTITION +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/ml401.h b/include/configs/ml401.h index 6cfc9478a24..7eeae708a72 100644 --- a/include/configs/ml401.h +++ b/include/configs/ml401.h @@ -145,6 +145,15 @@ #define CFG_FLASH_PROTECTION /* hardware flash protection */ #endif /* !FLASH */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 7a61e493956..e0a827fdd71 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -36,6 +36,15 @@ #define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 2a429614aaf..51f19a1456c 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -169,6 +169,15 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index c84795b6ab0..810e0f04628 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -177,6 +177,15 @@ #define CFG_CACHELINE_SIZE 32 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index f0cd8d3c02f..aa66c30f0ea 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -209,6 +209,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index 5d6e169c26a..5b5b0efb76a 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -72,6 +72,15 @@ #define CFG_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index 3e72c652bc7..18d0c879a9e 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -85,13 +85,6 @@ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 #endif - -#define ADD_PCI_CMD CFG_CMD_PCI - -#else /* MPC5100 */ - -#define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */ - #endif /* Partitions */ @@ -101,26 +94,35 @@ /* USB */ #if 0 #define CONFIG_USB_OHCI -#define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT #define CONFIG_USB_STORAGE -#else -#define ADD_USB_CMD 0 #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ #include #define CONFIG_CMD_BSP -#define CONFIG_PCI_CMD #define CONFIG_CMD_EEPROM #define CONFIG_CMD_ELF #define CONFIG_CMD_FAT #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE +#ifdef CONFIG_MPC5200 +#define CONFIG_CMD_PCI +#endif + #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ # define CFG_LOWBOOT 1 diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h index f581fe5e23f..863029d146d 100644 --- a/include/configs/pleb2.h +++ b/include/configs/pleb2.h @@ -67,6 +67,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h index 6a3bd33d2e9..6e451d8b6cb 100644 --- a/include/configs/ppmc7xx.h +++ b/include/configs/ppmc7xx.h @@ -68,6 +68,15 @@ * CMD_PCI - PCI Bus scanning command */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/purple.h b/include/configs/purple.h index 61e18d7b715..6eb618ed6d3 100644 --- a/include/configs/purple.h +++ b/include/configs/purple.h @@ -82,6 +82,15 @@ #define CONFIG_BOOTCOMMAND "run flash_self" +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index d7e4e8ac2b1..0e884fc114c 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -103,6 +103,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/r5200.h b/include/configs/r5200.h index 05929390010..0e743bb2e48 100644 --- a/include/configs/r5200.h +++ b/include/configs/r5200.h @@ -67,6 +67,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/rsdproto.h b/include/configs/rsdproto.h index 93f5c6be8d8..814082ccc63 100644 --- a/include/configs/rsdproto.h +++ b/include/configs/rsdproto.h @@ -102,6 +102,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h index fe06be674cd..b4a063a1d4c 100644 --- a/include/configs/sbc2410x.h +++ b/include/configs/sbc2410x.h @@ -83,6 +83,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 81322dfc70c..83a81fec139 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -440,6 +440,15 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index ad610f031a6..defc428819b 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -321,6 +321,15 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 9709fe292c2..cb225369871 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -168,6 +168,15 @@ #define CONFIG_MII 1 /* add 405GP MII PHY management */ #define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index 8689be4df3f..8491d97ae42 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -66,6 +66,15 @@ #define CONFIG_BAUDRATE 9600 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h index e761ca7b55b..c6f7f1526c6 100644 --- a/include/configs/sc520_spunk.h +++ b/include/configs/sc520_spunk.h @@ -65,6 +65,15 @@ #define CONFIG_BAUDRATE 9600 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/scb9328.h b/include/configs/scb9328.h index 489c35ff4b4..d140241bff4 100644 --- a/include/configs/scb9328.h +++ b/include/configs/scb9328.h @@ -35,6 +35,15 @@ */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -180,7 +189,7 @@ * Right now there is no gain for user, but later on booting kernel might be * possible. Consider using XIP kernel running from flash to save RAM * footprint. - * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. */ #define CFG_JFFS2_FIRST_BANK 0 #define CFG_JFFS2_FIRST_SECTOR 5 diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 14a64e8c3fc..ec6e9bd6b31 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -307,6 +307,15 @@ #define CONFIG_ISO_PARTITION +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/shannon.h b/include/configs/shannon.h index cad38d0c00d..c1fa53f1a8a 100644 --- a/include/configs/shannon.h +++ b/include/configs/shannon.h @@ -67,6 +67,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h index 22e69725b37..05f60537270 100644 --- a/include/configs/smdk2400.h +++ b/include/configs/smdk2400.h @@ -87,6 +87,15 @@ #define CONFIG_RTC_S3C24X0 1 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h index cd3d3276547..ca404ff452a 100644 --- a/include/configs/smdk2410.h +++ b/include/configs/smdk2410.h @@ -73,6 +73,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h index a965e8ac8ee..ad68c751c89 100644 --- a/include/configs/smmaco4.h +++ b/include/configs/smmaco4.h @@ -65,6 +65,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -338,8 +347,7 @@ #endif /* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) + * Enable loopw command. */ #define CONFIG_LOOPW diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h index e8f4cfac3ff..fe014eabcbc 100644 --- a/include/configs/sorcery.h +++ b/include/configs/sorcery.h @@ -64,6 +64,15 @@ #define CONFIG_PCI_CFG_SIZE 0x01000000 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h index ea6a11237d2..b4ab9ad9726 100644 --- a/include/configs/spc1920.h +++ b/include/configs/spc1920.h @@ -81,6 +81,15 @@ #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -194,7 +203,7 @@ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#ifdef CFG_CMD_DATE +#ifdef CONFIG_CMD_DATE # define CONFIG_RTC_DS3231 # define CFG_I2C_RTC_ADDR 0x68 #endif diff --git a/include/configs/spieval.h b/include/configs/spieval.h index ccfcf1c8dc0..4b618f36a87 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -121,6 +121,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -419,8 +428,7 @@ #endif /* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) + * Enable loopw command. */ #define CONFIG_LOOPW diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 9c55844dfe8..1f41cf7699e 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -298,6 +298,15 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index f480bd530f4..a880931cb1c 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -326,6 +326,15 @@ #define CONFIG_TIMESTAMP /* Print image info with ts */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/suzaku.h b/include/configs/suzaku.h index cb1a2e6a1a0..08ac9cbd58b 100644 --- a/include/configs/suzaku.h +++ b/include/configs/suzaku.h @@ -56,6 +56,15 @@ #define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/taishan.h b/include/configs/taishan.h index 4889f7026b8..baa4fbd312b 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -235,6 +235,15 @@ #define CONFIG_NETCONSOLE /* include NetConsole support */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h index df031753d6a..a21af219a7e 100644 --- a/include/configs/tb0229.h +++ b/include/configs/tb0229.h @@ -88,6 +88,15 @@ #define CONFIG_BOOTCOMMAND "run netboot" +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/trab.h b/include/configs/trab.h index a696b634a9a..52bcbfc158b 100644 --- a/include/configs/trab.h +++ b/include/configs/trab.h @@ -131,6 +131,15 @@ #define CONFIG_RTC_S3C24X0 1 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/uc101.h b/include/configs/uc101.h index 64461f6a90e..3b471d0a97f 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -51,6 +51,15 @@ #define CONFIG_DOS_PARTITION +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -265,8 +274,7 @@ #endif /* - * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined, - * which is normally part of the default commands (CFV_CMD_DFL) + * Enable loopw command. */ #define CONFIG_LOOPW diff --git a/include/configs/utx8245.h b/include/configs/utx8245.h index f3995431447..cd00c49fc22 100644 --- a/include/configs/utx8245.h +++ b/include/configs/utx8245.h @@ -87,6 +87,15 @@ protect on ${u-boot_startaddr} ${u-boot_endaddr}" #define CONFIG_ENV_OVERWRITE +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h index 3e3d11674ed..c0b1a15e6b2 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -85,6 +85,15 @@ #define CONFIG_USB_CONFIG 0x00001000 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/walnut.h b/include/configs/walnut.h index 2112b531795..180549efad3 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -99,6 +99,15 @@ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h index 3b360402dec..c67b3012276 100644 --- a/include/configs/wepep250.h +++ b/include/configs/wepep250.h @@ -35,6 +35,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ @@ -149,7 +158,7 @@ * Right now there is no gain for user, but later on booting kernel might be * possible. Consider using XIP kernel running from flash to save RAM * footprint. - * NOTE: Enable CFG_CMD_JFFS2 for JFFS2 support. + * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. */ #define CFG_JFFS2_FIRST_BANK 0 #define CFG_JFFS2_FIRST_SECTOR 5 diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 1149542bbe2..7418986caac 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -65,6 +65,15 @@ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/xm250.h b/include/configs/xm250.h index 225d46a38ae..bcd16ec5da0 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -82,6 +82,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h index 37daefe87ef..5733933d616 100644 --- a/include/configs/xsengine.h +++ b/include/configs/xsengine.h @@ -103,6 +103,15 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h index cfa12811351..35001d7ada3 100644 --- a/include/configs/xupv2p.h +++ b/include/configs/xupv2p.h @@ -120,6 +120,15 @@ #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 853e4bcc0dd..dd6d9acdd5d 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -249,6 +249,15 @@ #endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/yucca.h b/include/configs/yucca.h index ab323aaab43..9c536fd12da 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -192,6 +192,15 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index 3e636a27d2d..517ecb13b7f 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -77,6 +77,15 @@ #define CONFIG_BAUDRATE 115200 +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + /* * Command line configuration. */ -- cgit v1.3.1 From 068b60a0eb7e73b243ca55399f2a7df76e2c3f3d Mon Sep 17 00:00:00 2001 From: Jon Loeliger Date: Tue, 10 Jul 2007 10:27:39 -0500 Subject: cpu/ rtc/ include/: Remove lingering references to CFG_CMD_* symbols. Signed-off-by: Jon Loeliger --- cpu/74xx_7xx/kgdb.S | 2 +- cpu/i386/serial.c | 2 +- cpu/mcf52x2/fec.c | 2 +- cpu/mpc5xxx/ide.c | 4 ++-- cpu/mpc8260/ether_fcc.c | 2 +- cpu/mpc8260/ether_scc.c | 2 +- cpu/mpc8260/kgdb.S | 2 +- cpu/mpc85xx/ether_fcc.c | 2 +- cpu/mpc8xx/fec.c | 2 +- cpu/mpc8xx/kgdb.S | 2 +- cpu/mpc8xx/scc.c | 2 +- cpu/mpc8xx/serial.c | 2 +- cpu/ppc4xx/dcr.S | 2 +- cpu/ppc4xx/kgdb.S | 2 +- cpu/ppc4xx/serial.c | 2 +- include/_exports.h | 2 +- include/exports.h | 2 +- include/pcmcia.h | 2 +- rtc/bf5xx_rtc.c | 2 +- rtc/date.c | 2 +- rtc/ds1307.c | 2 +- rtc/ds1337.c | 2 +- rtc/ds1374.c | 2 +- rtc/ds1556.c | 2 +- rtc/ds164x.c | 2 +- rtc/ds174x.c | 2 +- rtc/m41t11.c | 2 +- rtc/m48t35ax.c | 2 +- rtc/max6900.c | 2 +- rtc/mc146818.c | 2 +- rtc/mpc5xxx.c | 2 +- rtc/mpc8xx.c | 4 +--- rtc/pcf8563.c | 2 +- rtc/s3c24x0_rtc.c | 4 +--- 34 files changed, 35 insertions(+), 39 deletions(-) (limited to 'include') diff --git a/cpu/74xx_7xx/kgdb.S b/cpu/74xx_7xx/kgdb.S index cd8869c2006..4f231228c22 100644 --- a/cpu/74xx_7xx/kgdb.S +++ b/cpu/74xx_7xx/kgdb.S @@ -74,4 +74,4 @@ kgdb_flush_cache_range: SYNC blr -#endif /* CFG_CMD_KGDB */ +#endif diff --git a/cpu/i386/serial.c b/cpu/i386/serial.c index 4933d23fd41..baf35e53d57 100644 --- a/cpu/i386/serial.c +++ b/cpu/i386/serial.c @@ -500,4 +500,4 @@ void kgdb_interruptible(int yes) return; } #endif /* (CONFIG_KGDB_SER_INDEX & 2) */ -#endif /* CFG_CMD_KGDB */ +#endif diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c index 255b3d8b7bc..ef9c7984ca3 100644 --- a/cpu/mcf52x2/fec.c +++ b/cpu/mcf52x2/fec.c @@ -592,7 +592,7 @@ int mcf52x2_miiphy_write (char *devname, unsigned char addr, return 0; } #endif -#endif /* CFG_CMD_NET, FEC_ENET */ +#endif int mcf52x2_miiphy_initialize(bd_t *bis) { diff --git a/cpu/mpc5xxx/ide.c b/cpu/mpc5xxx/ide.c index 29b99f6b15d..087ddac109d 100644 --- a/cpu/mpc5xxx/ide.c +++ b/cpu/mpc5xxx/ide.c @@ -24,7 +24,7 @@ */ #include -#ifdef CFG_CMD_IDE +#if defined(CONFIG_CMD_IDE) #include DECLARE_GLOBAL_DATA_PTR; @@ -85,4 +85,4 @@ int ide_preinit (void) return (0); } -#endif /* CFG_CMD_IDE */ +#endif diff --git a/cpu/mpc8260/ether_fcc.c b/cpu/mpc8260/ether_fcc.c index 08d2847b96b..37bf4456ed1 100644 --- a/cpu/mpc8260/ether_fcc.c +++ b/cpu/mpc8260/ether_fcc.c @@ -1187,4 +1187,4 @@ eth_loopback_test (void) #endif /* CONFIG_ETHER_LOOPBACK_TEST */ -#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */ +#endif diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c index b9ae0826687..e56839d3aad 100644 --- a/cpu/mpc8260/ether_scc.c +++ b/cpu/mpc8260/ether_scc.c @@ -353,4 +353,4 @@ void restart(void) } #endif -#endif /* CONFIG_ETHER_ON_SCC && CFG_CMD_NET */ +#endif diff --git a/cpu/mpc8260/kgdb.S b/cpu/mpc8260/kgdb.S index 5a7d0b7b2bb..dae87bb97c7 100644 --- a/cpu/mpc8260/kgdb.S +++ b/cpu/mpc8260/kgdb.S @@ -69,4 +69,4 @@ kgdb_flush_cache_range: SYNC blr -#endif /* CFG_CMD_KGDB */ +#endif diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c index 4448cc3b8f5..5b23a80e1ca 100644 --- a/cpu/mpc85xx/ether_fcc.c +++ b/cpu/mpc85xx/ether_fcc.c @@ -468,6 +468,6 @@ int fec_initialize(bd_t *bis) return 1; } -#endif /* CONFIG_ETHER_ON_FCC && CFG_CMD_NET && CONFIG_NET_MULTI */ +#endif #endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc8xx/fec.c b/cpu/mpc8xx/fec.c index 10d825f5729..08a3715812d 100644 --- a/cpu/mpc8xx/fec.c +++ b/cpu/mpc8xx/fec.c @@ -1022,4 +1022,4 @@ int fec8xx_miiphy_write(char *devname, unsigned char addr, } #endif -#endif /* CFG_CMD_NET, FEC_ENET */ +#endif diff --git a/cpu/mpc8xx/kgdb.S b/cpu/mpc8xx/kgdb.S index d4c77e79668..812baa3ecd4 100644 --- a/cpu/mpc8xx/kgdb.S +++ b/cpu/mpc8xx/kgdb.S @@ -71,4 +71,4 @@ kgdb_flush_cache_range: SYNC blr -#endif /* CFG_CMD_KGDB */ +#endif diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c index a0ec5d78706..744dcdde91f 100644 --- a/cpu/mpc8xx/scc.c +++ b/cpu/mpc8xx/scc.c @@ -567,4 +567,4 @@ void restart (void) (SCC_GSMRL_ENR | SCC_GSMRL_ENT); } #endif -#endif /* CFG_CMD_NET, SCC_ENET */ +#endif diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index 6e08b53525b..68804cc4394 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -723,6 +723,6 @@ kgdb_interruptible (int yes) { return; } -#endif /* CFG_CMD_KGDB */ +#endif #endif /* CONFIG_8xx_CONS_NONE */ diff --git a/cpu/ppc4xx/dcr.S b/cpu/ppc4xx/dcr.S index fe136e0fa29..93465a3b513 100644 --- a/cpu/ppc4xx/dcr.S +++ b/cpu/ppc4xx/dcr.S @@ -195,4 +195,4 @@ set_dcr: blr /* Return to calling function */ .Lfe4: .size set_dcr,.Lfe4-set_dcr /* end set_dcr() */ -#endif /* CONFIG_4xx & CFG_CMD_SETGETDCR */ +#endif diff --git a/cpu/ppc4xx/kgdb.S b/cpu/ppc4xx/kgdb.S index cd12727be3c..8c4bbf2e4de 100644 --- a/cpu/ppc4xx/kgdb.S +++ b/cpu/ppc4xx/kgdb.S @@ -75,4 +75,4 @@ kgdb_flush_cache_range: SYNC blr -#endif /* CFG_CMD_KGDB */ +#endif diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index aefa4cabab6..3f67136be53 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -949,7 +949,7 @@ void kgdb_interruptible (int yes) return; } #endif /* (CONFIG_KGDB_SER_INDEX & 2) */ -#endif /* CFG_CMD_KGDB */ +#endif #if defined(CONFIG_SERIAL_MULTI) diff --git a/include/_exports.h b/include/_exports.h index eeb65f40ae4..a0fbf2aba36 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -18,4 +18,4 @@ EXPORT_FUNC(simple_strtoul) #if defined(CONFIG_CMD_I2C) EXPORT_FUNC(i2c_write) EXPORT_FUNC(i2c_read) -#endif /* CFG_CMD_I2C */ +#endif diff --git a/include/exports.h b/include/exports.h index ad20502a67a..704b1330b89 100644 --- a/include/exports.h +++ b/include/exports.h @@ -26,7 +26,7 @@ void setenv (char *varname, char *varvalue); #if defined(CONFIG_CMD_I2C) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); -#endif /* CFG_CMD_I2C */ +#endif void app_startup(char **); diff --git a/include/pcmcia.h b/include/pcmcia.h index c028ab735db..7305805e40c 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -306,7 +306,7 @@ typedef struct { #define CISTPL_IDE_HAS_INDEX 0x20 #define CISTPL_IDE_IOIS16 0x40 -#endif /* CFG_CMD_PCMCIA || CFG_CMD_IDE && (CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT) */ +#endif #ifdef CONFIG_8xx extern u_int *pcmcia_pgcrx[]; diff --git a/rtc/bf5xx_rtc.c b/rtc/bf5xx_rtc.c index 17a19eb4f1d..8856bb9b5f8 100644 --- a/rtc/bf5xx_rtc.c +++ b/rtc/bf5xx_rtc.c @@ -140,4 +140,4 @@ void rtc_get(struct rtc_time *tmp) MIN_TO_SECS(tm_min) + HRS_TO_SECS(tm_hour) + DAYS_TO_SECS(tm_day); to_tm(time_in_sec, tmp); } -#endif /* CONFIG_RTC_BFIN && CFG_CMD_DATE */ +#endif diff --git a/rtc/date.c b/rtc/date.c index d00b1444807..a83a7235ab6 100644 --- a/rtc/date.c +++ b/rtc/date.c @@ -153,4 +153,4 @@ mktime (unsigned int year, unsigned int mon, )*60 + sec; /* finally seconds */ } -#endif /* CFG_CMD_DATE */ +#endif diff --git a/rtc/ds1307.c b/rtc/ds1307.c index a2a86337848..c882d7989a0 100644 --- a/rtc/ds1307.c +++ b/rtc/ds1307.c @@ -201,4 +201,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* (CONFIG_RTC_DS1307 || CONFIG_RTC_DS1338) && (CFG_COMMANDS & CFG_CMD_DATE) */ +#endif diff --git a/rtc/ds1337.c b/rtc/ds1337.c index b871d079502..c636ac5948f 100644 --- a/rtc/ds1337.c +++ b/rtc/ds1337.c @@ -188,4 +188,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_DS1337 && (CFG_COMMANDS & CFG_CMD_DATE) */ +#endif diff --git a/rtc/ds1374.c b/rtc/ds1374.c index 6ee7ab4b980..e773dd92615 100644 --- a/rtc/ds1374.c +++ b/rtc/ds1374.c @@ -250,4 +250,4 @@ static void rtc_write_raw (uchar reg, uchar val) { i2c_reg_write (CFG_I2C_RTC_ADDR, reg, val); } -#endif /* (CONFIG_RTC_DS1374) && (CFG_COMMANDS & CFG_CMD_DATE) */ +#endif diff --git a/rtc/ds1556.c b/rtc/ds1556.c index 440d43aef3b..4365cfb9813 100644 --- a/rtc/ds1556.c +++ b/rtc/ds1556.c @@ -203,4 +203,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_DS1556 && CFG_CMD_DATE */ +#endif diff --git a/rtc/ds164x.c b/rtc/ds164x.c index e82ca591636..bff22b9a058 100644 --- a/rtc/ds164x.c +++ b/rtc/ds164x.c @@ -197,4 +197,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_DS164x && CFG_CMD_DATE */ +#endif diff --git a/rtc/ds174x.c b/rtc/ds174x.c index e3028e2540b..5f85a68170b 100644 --- a/rtc/ds174x.c +++ b/rtc/ds174x.c @@ -199,4 +199,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_MC146818 && CFG_CMD_DATE */ +#endif diff --git a/rtc/m41t11.c b/rtc/m41t11.c index 1e35b068e61..81da33a31e1 100644 --- a/rtc/m41t11.c +++ b/rtc/m41t11.c @@ -199,4 +199,4 @@ int rtc_recall(int addr, unsigned char* data, int size) return i2c_read( CFG_I2C_RTC_ADDR, REG_CNT+addr, 1, data, size ); } -#endif /* CONFIG_RTC_M41T11 && CFG_I2C_RTC_ADDR && CFG_CMD_DATE */ +#endif diff --git a/rtc/m48t35ax.c b/rtc/m48t35ax.c index 6133b46acd4..0a0ffa8aac1 100644 --- a/rtc/m48t35ax.c +++ b/rtc/m48t35ax.c @@ -163,4 +163,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_M48T35A && CFG_CMD_DATE */ +#endif diff --git a/rtc/max6900.c b/rtc/max6900.c index 63f643c1a71..c75a8e04c24 100644 --- a/rtc/max6900.c +++ b/rtc/max6900.c @@ -128,4 +128,4 @@ void rtc_reset (void) { } -#endif /* CONFIG_RTC_MAX6900 && CFG_CMD_DATE */ +#endif diff --git a/rtc/mc146818.c b/rtc/mc146818.c index bbb6486cf92..ab377ed73e5 100644 --- a/rtc/mc146818.c +++ b/rtc/mc146818.c @@ -175,4 +175,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_MC146818 && CFG_CMD_DATE */ +#endif diff --git a/rtc/mpc5xxx.c b/rtc/mpc5xxx.c index 72f3111957e..216386aba05 100644 --- a/rtc/mpc5xxx.c +++ b/rtc/mpc5xxx.c @@ -137,4 +137,4 @@ void rtc_reset (void) return; /* nothing to do */ } -#endif /* CONFIG_RTC_MPC5200 && CFG_CMD_DATE */ +#endif diff --git a/rtc/mpc8xx.c b/rtc/mpc8xx.c index 716cd53eac4..8d10c0e465e 100644 --- a/rtc/mpc8xx.c +++ b/rtc/mpc8xx.c @@ -70,6 +70,4 @@ void rtc_reset (void) return; /* nothing to do */ } -/* ------------------------------------------------------------------------- */ - -#endif /* CONFIG_RTC_MPC8xx && CFG_CMD_DATE */ +#endif diff --git a/rtc/pcf8563.c b/rtc/pcf8563.c index 5e868367c8c..2d73d5d7ef9 100644 --- a/rtc/pcf8563.c +++ b/rtc/pcf8563.c @@ -141,4 +141,4 @@ static unsigned char bin2bcd (unsigned int n) return (((n / 10) << 4) | (n % 10)); } -#endif /* CONFIG_RTC_PCF8563 && CFG_CMD_DATE */ +#endif diff --git a/rtc/s3c24x0_rtc.c b/rtc/s3c24x0_rtc.c index 902b737410a..7f8b4fad0dd 100644 --- a/rtc/s3c24x0_rtc.c +++ b/rtc/s3c24x0_rtc.c @@ -175,6 +175,4 @@ void rtc_reset (void) rtc->RTCCON &= ~(0x08|0x01); } -/* ------------------------------------------------------------------------- */ - -#endif /* CONFIG_RTC_S3C24X0 && CFG_CMD_DATE */ +#endif -- cgit v1.3.1 From 96e1d75be8193ca79e4215a368bf9d7f2362450f Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 11 Jul 2007 18:39:11 +0200 Subject: [PCS440EP] - Show on the DIAG LEDs, if the SHA1 check failed - now the Flash ST M29W040B is supported (not tested) - fix the "led" command - fix compile error, if BUILD_DIR is used Signed-off-by: Heiko Schocher --- Makefile | 2 +- board/pcs440ep/flash.c | 11 +++++++++ board/pcs440ep/pcs440ep.c | 37 ++++++++++++++++++++++-------- doc/README.sha1 | 57 ++++++++++++++++++++++++++++++++++++++++++++++ include/configs/pcs440ep.h | 8 +++---- 5 files changed, 101 insertions(+), 14 deletions(-) create mode 100644 doc/README.sha1 (limited to 'include') diff --git a/Makefile b/Makefile index 47e4e670abd..c45700e08d6 100644 --- a/Makefile +++ b/Makefile @@ -268,7 +268,7 @@ $(obj)u-boot.img: $(obj)u-boot.bin -d $< $@ $(obj)u-boot.sha1: $(obj)u-boot.bin - ./tools/ubsha1 $(obj)u-boot.bin + $(obj)./tools/ubsha1 $(obj)u-boot.bin $(obj)u-boot.dis: $(obj)u-boot $(OBJDUMP) -d $< > $@ diff --git a/board/pcs440ep/flash.c b/board/pcs440ep/flash.c index 70014407c6e..c5a62e25436 100644 --- a/board/pcs440ep/flash.c +++ b/board/pcs440ep/flash.c @@ -82,6 +82,7 @@ void flash_print_info(flash_info_t *info) case FLASH_MAN_AMD: printf ("AMD "); break; case FLASH_MAN_FUJ: printf ("FUJITSU "); break; case FLASH_MAN_SST: printf ("SST "); break; + case FLASH_MAN_STM: printf ("ST Micro"); break; case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break; case FLASH_MAN_MX: printf ("MXIC "); break; default: printf ("Unknown Vendor "); break; @@ -118,6 +119,8 @@ void flash_print_info(flash_info_t *info) break; case FLASH_SST040: printf ("SST39LF/VF040 (4 Mbit, uniform sector size)\n"); break; + case STM_ID_M29W040B: printf ("ST Micro M29W040B (4 Mbit, uniform sector size)\n"); + break; default: printf ("Unknown Chip Type\n"); break; } @@ -193,6 +196,9 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) case (CFG_FLASH_WORD_SIZE)SST_MANUFACT: info->flash_id = FLASH_MAN_SST; break; + case (CFG_FLASH_WORD_SIZE)STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT: info->flash_id = FLASH_MAN_EXCEL; break; @@ -226,6 +232,11 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info) info->sector_count = 8; info->size = 0x0080000; /* => 0.5 MB */ break; + case (CFG_FLASH_WORD_SIZE)STM_ID_M29W040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 0,5 MB */ + break; case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T: info->flash_id += FLASH_AM800T; diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index ada6b82c927..0e34a76cb9f 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -85,8 +85,9 @@ static void status_led_blink (void) /* set all LED which are on, to state BLINKING */ for (i = 0; i < 4; i++) { - if (val & 0x08) status_led_set (i, STATUS_LED_BLINKING); - val = val << 1; + if (val & 0x01) status_led_set (3 - i, STATUS_LED_BLINKING); + else status_led_set (3 - i, STATUS_LED_OFF); + val = val >> 1; } } @@ -113,12 +114,14 @@ void show_boot_progress (int val) status_led_set (1, STATUS_LED_ON); status_led_set (2, STATUS_LED_ON); break; +#if 0 case 64: /* starting Ethernet configuration */ status_led_set (0, STATUS_LED_OFF); status_led_set (1, STATUS_LED_OFF); status_led_set (2, STATUS_LED_ON); break; +#endif case 80: /* loading Image */ status_led_set (0, STATUS_LED_ON); @@ -404,6 +407,9 @@ static void pcs440ep_checksha1 (void) int ret; char *cs_test; + status_led_set (0, STATUS_LED_OFF); + status_led_set (1, STATUS_LED_OFF); + status_led_set (2, STATUS_LED_ON); ret = pcs440ep_sha1 (1); if (ret == 0) return; @@ -751,28 +757,41 @@ void hw_watchdog_reset(void) ************************************************************************/ int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - int rcode = 0; + int rcode = 0, i; ulong pattern = 0; - pattern = simple_strtoul (argv[1], NULL, 10); - if (pattern > 200) { + pattern = simple_strtoul (argv[1], NULL, 16); + if (pattern > 0x400) { + int val = GET_LEDS; + printf ("led: %x\n", val); + return rcode; + } + if (pattern > 0x200) { status_led_blink (); hang (); return rcode; } - if (pattern > 100) { + if (pattern > 0x100) { status_led_blink (); return rcode; } pattern &= 0x0f; - set_leds (pattern); + for (i = 0; i < 4; i++) { + if (pattern & 0x01) status_led_set (i, STATUS_LED_ON); + else status_led_set (i, STATUS_LED_OFF); + pattern = pattern >> 1; + } return rcode; } U_BOOT_CMD( led, 2, 1, do_led, - "led - set the led\n", - NULL + "led [bitmask] - set the DIAG-LED\n", + "[bitmask] 0x01 = DIAG 1 on\n" + " 0x02 = DIAG 2 on\n" + " 0x04 = DIAG 3 on\n" + " 0x08 = DIAG 4 on\n" + " > 0x100 set the LED, who are on, to state blinking\n" ); #if defined(CONFIG_SHA1_CHECK_UB_IMG) diff --git a/doc/README.sha1 b/doc/README.sha1 new file mode 100644 index 00000000000..92dc8fffaea --- /dev/null +++ b/doc/README.sha1 @@ -0,0 +1,57 @@ +SHA1 usage: +----------- + +In the U-Boot Image for the pcs440ep board is a SHA1 checksum integrated. +This SHA1 sum is used, to check, if the U-Boot Image in Flash is not +corrupted. + +The following command is available: + +=> help sha1 +sha1 address len [addr] calculate the SHA1 sum [save at addr] + -p calculate the SHA1 sum from the U-Boot image in flash and print + -c check the U-Boot image in flash + +"sha1 -p" + calculates and prints the SHA1 sum, from the Image stored in Flash + +"sha1 -c" + check, if the SHA1 sum from the Image stored in Flash is correct + + +It is possible to calculate a SHA1 checksum from a memoryrange with: + +"sha1 address len" + +If you want to store a new Image in Flash for the pcs440ep board, +which has no SHA1 sum, you can do the following: + +a) cp the new Image on a position in RAM (here 0x300000) + (for this example we use the Image from Flash, stored at 0xfffa0000 and + 0x60000 Bytes long) + +"cp.b fffa0000 300000 60000" + +b) Initialize the SHA1 sum in the Image with 0x00 + The SHA1 sum is stored in Flash at: + CFG_MONITOR_BASE + CFG_MONITOR_LEN + SHA1_SUM_POS + for the pcs440ep Flash: 0xfffa0000 + 0x60000 + -0x20 + = 0xffffffe0 + for the example in RAM: 0x300000 + 0x60000 + -0x20 + = 0x35ffe0 + + note: a SHA1 checksum is 20 bytes long. + +"mw.b 35ffe0 0 14" + +c) now calculate the SHA1 sum from the memoryrange and write + the calculated checksum at the right place: + +"sha1 300000 60000 35ffe0" + +Now you have a U-Boot-Image for the pcs440ep board with the correct SHA1 sum. + +If you do a "./MAKEALL pcs440ep" or a "make all" to get the U-Boot image, +the correct SHA1 sum will be automagically included in the U-Boot image. + +Heiko Schocher, 11 Jul 2007 diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 69d97d66ea1..5ee97c12794 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -197,16 +197,16 @@ #define CONFIG_STATUS_LED 1 /* Status LED enabled */ #define CONFIG_BOARD_SPECIFIC_LED 1 -#define STATUS_LED_BIT 0x08 /* LED 1 is on GPIO_PPC_1 */ +#define STATUS_LED_BIT 0x08 /* DIAG1 is on GPIO_PPC_1 */ #define STATUS_LED_PERIOD ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ #define STATUS_LED_STATE STATUS_LED_OFF -#define STATUS_LED_BIT1 0x04 /* LED 2 is on GPIO_PPC_2 */ +#define STATUS_LED_BIT1 0x04 /* DIAG2 is on GPIO_PPC_2 */ #define STATUS_LED_PERIOD1 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ #define STATUS_LED_STATE1 STATUS_LED_ON -#define STATUS_LED_BIT2 0x02 /* LED 3 is on GPIO_PPC_3 */ +#define STATUS_LED_BIT2 0x02 /* DIAG3 is on GPIO_PPC_3 */ #define STATUS_LED_PERIOD2 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ #define STATUS_LED_STATE2 STATUS_LED_OFF -#define STATUS_LED_BIT3 0x01 /* LED 4 is on GPIO_PPC_4 */ +#define STATUS_LED_BIT3 0x01 /* DIAG4 is on GPIO_PPC_4 */ #define STATUS_LED_PERIOD3 ((CFG_HZ / 2) / 5) /* blink at 5 Hz */ #define STATUS_LED_STATE3 STATUS_LED_OFF -- cgit v1.3.1 From fa1df308926a6f70e3504c57514ef27ac31fd13a Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Wed, 11 Jul 2007 20:11:07 +0200 Subject: CM1.QP1: Support for the Schindler CM1.QP1 board. Signed-off-by: Piotr Kruszynski Signed-off-by: Bartlomiej Sieka --- MAKEALL | 12 +- Makefile | 8 + board/cm1_qp1/Makefile | 50 +++++ board/cm1_qp1/cm1_qp1.c | 222 ++++++++++++++++++++++ board/cm1_qp1/cmd_cm1_qp1.c | 446 ++++++++++++++++++++++++++++++++++++++++++++ board/cm1_qp1/config.mk | 26 +++ board/cm1_qp1/fwupdate.c | 187 +++++++++++++++++++ board/cm1_qp1/fwupdate.h | 47 +++++ board/cm1_qp1/u-boot.lds | 123 ++++++++++++ cpu/mpc5xxx/fec.c | 21 ++- include/configs/cm1_qp1.h | 358 +++++++++++++++++++++++++++++++++++ 11 files changed, 1487 insertions(+), 13 deletions(-) create mode 100644 board/cm1_qp1/Makefile create mode 100644 board/cm1_qp1/cm1_qp1.c create mode 100644 board/cm1_qp1/cmd_cm1_qp1.c create mode 100644 board/cm1_qp1/config.mk create mode 100644 board/cm1_qp1/fwupdate.c create mode 100644 board/cm1_qp1/fwupdate.h create mode 100644 board/cm1_qp1/u-boot.lds create mode 100644 include/configs/cm1_qp1.h (limited to 'include') diff --git a/MAKEALL b/MAKEALL index f931e1dd71e..127faa83a32 100755 --- a/MAKEALL +++ b/MAKEALL @@ -35,12 +35,12 @@ LIST_5xx=" \ ######################################################################### LIST_5xxx=" \ - BC3450 cpci5200 EVAL5200 fo300 \ - icecube_5100 icecube_5200 lite5200b mcc200 \ - mecp5200 motionpro o2dnt pf5200 \ - PM520 TB5200 Total5100 Total5200 \ - Total5200_Rev2 TQM5200 TQM5200_B TQM5200S \ - v38b \ + BC3450 cm1_qp1 cpci5200 EVAL5200 \ + fo300 icecube_5100 icecube_5200 lite5200b \ + mcc200 mecp5200 motionpro o2dnt \ + pf5200 PM520 TB5200 Total5100 \ + Total5200 Total5200_Rev2 TQM5200 TQM5200_B \ + TQM5200S v38b \ " ######################################################################### diff --git a/Makefile b/Makefile index 626283f708b..9c1a0b2a37e 100644 --- a/Makefile +++ b/Makefile @@ -529,6 +529,14 @@ PM520_ROMBOOT_DDR_config: unconfig smmaco4_config: unconfig @$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200 +cm1_qp1_config: unconfig + @ >include/config.h + @[ -z "$(findstring cm1_qp1,$@)" ] || \ + { echo "... with 64 MByte SDRAM" ; \ + echo "... with 32 MByte Flash" ; \ + } + @./mkconfig -a cm1_qp1 ppc mpc5xxx cm1_qp1 + spieval_config: unconfig @$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200 diff --git a/board/cm1_qp1/Makefile b/board/cm1_qp1/Makefile new file mode 100644 index 00000000000..e7393267e7a --- /dev/null +++ b/board/cm1_qp1/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2003-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o cmd_cm1_qp1.o fwupdate.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cm1_qp1/cm1_qp1.c b/board/cm1_qp1/cm1_qp1.c new file mode 100644 index 00000000000..b49298f64b6 --- /dev/null +++ b/board/cm1_qp1/cm1_qp1.c @@ -0,0 +1,222 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2004-2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#ifdef CONFIG_OF_FLAT_TREE +#include +#endif /* CONFIG_OF_FLAT_TREE */ + +#include "fwupdate.h" + +#ifndef CFG_RAMBOOT +/* + * Helper function to initialize SDRAM controller. + */ +static void sdram_start(int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | + hi_addr_bit; + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | + hi_addr_bit; + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | + hi_addr_bit; + + /* auto refresh, second time */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | + hi_addr_bit; + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; +} +#endif /* CFG_RAMBOOT */ + +/* + * Initalize SDRAM - configure SDRAM controller, detect memory size. + */ +long int initdram(int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + + /* configure SDRAM start/end for detection */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; + + sdram_start(0); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else + dramsize = test2; + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) + dramsize = 0; + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + + __builtin_ffs(dramsize >> 20) - 1; + } else + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ +#else /* CFG_RAMBOOT */ + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) + dramsize = (1 << (dramsize - 0x13)) << 20; + else + dramsize = 0; +#endif /* CFG_RAMBOOT */ + + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of + * the MPC5200B User's Manual. + */ + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + + return dramsize; +} + + +int checkboard(void) +{ + puts("Board: CM1.QP1\n"); + return 0; +} + + +int board_early_init_r(void) +{ + /* + * Now, when we are in RAM, enable flash write access for detection + * process. Note that CS_BOOT cannot be cleared when executing in + * flash. + */ + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ + return 0; +} + + +#ifdef CONFIG_POST +int post_hotkeys_pressed(void) +{ + return 0; +} +#endif /* CONFIG_POST */ + + +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) +void post_word_store(ulong a) +{ + vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + *save_addr = a; +} + + +ulong post_word_load(void) +{ + vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + return *save_addr; +} +#endif /* CONFIG_POST || CONFIG_LOGBUFFER */ + + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) + uchar buf[6]; + char str[18]; + + /* Read ethaddr from EEPROM */ + if (i2c_read(CFG_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) { + sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + /* Check if MAC addr is owned by Schindler */ + if (strstr(str, "00:06:C3") != str) { + printf(LOG_PREFIX "Warning - Illegal MAC address (%s)" + " in EEPROM.\n", str); + printf(LOG_PREFIX "Using MAC from environment\n"); + } else { + printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n", + str); + setenv("ethaddr", str); + } + } else { + printf(LOG_PREFIX "Warning - Unable to read MAC from I2C" + " device at address %02X:%04X\n", CFG_I2C_EEPROM, + CONFIG_MAC_OFFSET); + printf(LOG_PREFIX "Using MAC from environment\n"); + } + return 0; +#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */ +} +#endif /* CONFIG_MISC_INIT_R */ + + +#ifdef CONFIG_LAST_STAGE_INIT +int last_stage_init(void) +{ +#ifdef CONFIG_USB_STORAGE + cm1_fwupdate(); +#endif /* CONFIG_USB_STORAGE */ + return 0; +} +#endif /* CONFIG_LAST_STAGE_INIT */ + + +#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/cm1_qp1/cmd_cm1_qp1.c b/board/cm1_qp1/cmd_cm1_qp1.c new file mode 100644 index 00000000000..4a01d2a7f4c --- /dev/null +++ b/board/cm1_qp1/cmd_cm1_qp1.c @@ -0,0 +1,446 @@ +/* + * (C) Copyright 2007 Markus Kappeler + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +int do_i2c(char *argv[]) +{ + unsigned char temp, temp1; + + printf("Starting I2C Test\n" + "Please set Jumper:\nI2C SDA 2-3\nI2C SCL 2-3\n\n" + "Please press any key to start\n\n"); + getc(); + + temp = 0xf0; /* set io 0-4 as output */ + i2c_write(CFG_I2C_IO, 3, 1, (uchar *)&temp, 1); + + printf("Press I2C4-7. LED I2C0-3 should have the same state\n\n" + "Press any key to stop\n\n"); + + while (!tstc()) { + i2c_read(CFG_I2C_IO, 0, 1, (uchar *)&temp, 1); + temp1 = (temp >> 4) & 0x03; + temp1 |= (temp >> 3) & 0x08; /* S302 -> LED303 */ + temp1 |= (temp >> 5) & 0x04; /* S303 -> LED302 */ + temp = temp1; + i2c_write(CFG_I2C_IO, 1, 1, (uchar *)&temp, 1); + } + getc(); + + return 0; +} + +int do_usbtest(char *argv[]) +{ + int i; + static int usb_stor_curr_dev = -1; /* current device */ + + printf("Starting USB Test\n" + "Please insert USB Memmory Stick\n\n" + "Please press any key to start\n\n"); + getc(); + + usb_stop(); + printf("(Re)start USB...\n"); + i = usb_init(); +#ifdef CONFIG_USB_STORAGE + /* try to recognize storage devices immediately */ + if (i >= 0) + usb_stor_curr_dev = usb_stor_scan(1); +#endif /* CONFIG_USB_STORAGE */ + if (usb_stor_curr_dev >= 0) + printf("Found USB Storage Dev continue with Test...\n"); + else { + printf("No USB Storage Device detected.. Stop Test\n"); + return 1; + } + + usb_stor_info(); + + printf("stopping USB..\n"); + usb_stop(); + + return 0; +} + +int do_led(char *argv[]) +{ + int i = 0; + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + printf("Starting LED Test\n" + "Please set Switch S500 all off\n\n" + "Please press any key to start\n\n"); + getc(); + + /* configure timer 2-3 for simple GPIO output High */ + gpt->gpt2.emsr |= 0x00000034; + gpt->gpt3.emsr |= 0x00000034; + + (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000; + (*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000; + printf("Please press any key to stop\n\n"); + while (!tstc()) { + if (i == 1) { + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; + gpt->gpt2.emsr &= ~0x00000010; + gpt->gpt3.emsr &= ~0x00000010; + } else if (i == 2) { + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; + gpt->gpt2.emsr &= ~0x00000010; + gpt->gpt3.emsr |= 0x00000010; + } else if (i >= 3) { + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; + gpt->gpt3.emsr &= ~0x00000010; + gpt->gpt2.emsr |= 0x00000010; + i = 0; + } + i++; + udelay(200000); + } + getc(); + + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; + gpt->gpt2.emsr |= 0x00000010; + gpt->gpt3.emsr |= 0x00000010; + + return 0; +} + +int do_rs232(char *argv[]) +{ + int error_status = 0; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1; + + /* Configure PSC 2-3-6 as GPIO */ + gpio->port_config &= 0xFF0FF80F; + + switch (simple_strtoul(argv[2], NULL, 10)) { + case 1: + /* check RTS <-> CTS loop */ + /* set rts to 0 */ + printf("Uart 1 test: RX TX tested by using U-Boot\n" + "Please connect RTS with CTS on Uart1 plug\n\n" + "Press any key to start\n\n"); + getc(); + + psc1->op1 |= 0x01; + + /* wait some time before requesting status */ + udelay(10); + + /* check status at cts */ + if ((psc1->ip & 0x01) != 0) { + error_status = 3; + printf("%s: failure at rs232_1, cts status is %d " + "(should be 0)\n", + __FUNCTION__, (psc1->ip & 0x01)); + } + + /* set rts to 1 */ + psc1->op0 |= 0x01; + + /* wait some time before requesting status */ + udelay(10); + + /* check status at cts */ + if ((psc1->ip & 0x01) != 1) { + error_status = 3; + printf("%s: failure at rs232_1, cts status is %d " + "(should be 1)\n", + __FUNCTION__, (psc1->ip & 0x01)); + } + break; + case 2: + /* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */ + printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n" + "\nPress any key to start\n\n"); + getc(); + + gpio->simple_gpioe &= ~(0x000000F0); + gpio->simple_gpioe |= 0x000000F0; + gpio->simple_ddr &= ~(0x000000F0); + gpio->simple_ddr |= 0x00000050; + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 4); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000020) != 0x00000020) { + error_status = 2; + printf("%s: failure at rs232_2, rxd status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000020) >> 5); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 4); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000020) != 0x00000000) { + error_status = 2; + printf("%s: failure at rs232_2, rxd status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000020) >> 5); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 6); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000080) != 0x00000080) { + error_status = 3; + printf("%s: failure at rs232_2, cts status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000080) >> 7); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 6); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000080) != 0x00000000) { + error_status = 3; + printf("%s: failure at rs232_2, cts status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000080) >> 7); + } + break; + case 3: + /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */ + printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n" + "\nPress any key to start\n\n"); + getc(); + + gpio->simple_gpioe &= ~(0x00000F00); + gpio->simple_gpioe |= 0x00000F00; + + gpio->simple_ddr &= ~(0x00000F00); + gpio->simple_ddr |= 0x00000500; + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 8); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000200) != 0x00000200) { + error_status = 2; + printf("%s: failure at rs232_3, rxd status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000200) >> 9); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 8); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000200) != 0x00000000) { + error_status = 2; + printf("%s: failure at rs232_3, rxd status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000200) >> 9); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 10); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000800) != 0x00000800) { + error_status = 3; + printf("%s: failure at rs232_3, cts status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000800) >> 11); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 10); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000800) != 0x00000000) { + error_status = 3; + printf("%s: failure at rs232_3, cts status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000800) >> 11); + } + break; + case 4: + /* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */ + printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n" + "\nPress any key to start\n\n"); + getc(); + + gpio->simple_gpioe &= ~(0xF0000000); + gpio->simple_gpioe |= 0x30000000; + + gpio->simple_ddr &= ~(0xf0000000); + gpio->simple_ddr |= 0x30000000; + + (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000; + (*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000); + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 28); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != + 0x10000000) { + error_status = 2; + printf("%s: failure at rs232_4, rxd status is %d " + "(should be 1)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x10000000) >> 28); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 28); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != + 0x00000000) { + error_status = 2; + printf("%s: failure at rs232_4, rxd status is %d " + "(should be 0)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x10000000) >> 28); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 29); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != + 0x20000000) { + error_status = 3; + printf("%s: failure at rs232_4, cts status is %d " + "(should be 1)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x20000000) >> 29); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 29); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != + 0x00000000) { + error_status = 3; + printf("%s: failure at rs232_4, cts status is %d " + "(should be 0)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x20000000) >> 29); + } + break; + default: + printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]); + error_status = 1; + break; + } + gpio->port_config |= (CFG_GPS_PORT_CONFIG & 0xFF0FF80F); + + return error_status; +} + +int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = -1; + + switch (argc) { + case 2: + if (strncmp(argv[1], "i2c", 3) == 0) + rcode = do_i2c(argv); + else if (strncmp(argv[1], "led", 3) == 0) + rcode = do_led(argv); + else if (strncmp(argv[1], "usb", 3) == 0) + rcode = do_usbtest(argv); + break; + case 3: + if (strncmp(argv[1], "rs232", 3) == 0) + rcode = do_rs232(argv); + break; + } + + switch (rcode) { + case -1: + printf("Usage:\n" + "fkt { i2c | led | usb }\n" + "fkt rs232 number\n"); + rcode = 1; + break; + case 0: + printf("Test passed\n"); + break; + default: + printf("Test failed with code: %d\n", rcode); + } + + return rcode; +} + +U_BOOT_CMD( + fkt, 4, 1, cmd_fkt, + "fkt - Function test routines\n", + "i2c\n" + " - Test I2C communication\n" + "fkt led\n" + " - Test LEDs\n" + "fkt rs232 number\n" + " - Test RS232 (loopback plug(s) for RS232 required)\n" + "fkt usb\n" + " - Test USB communication\n" +); +#endif /* CFG_CMD_BSP */ diff --git a/board/cm1_qp1/config.mk b/board/cm1_qp1/config.mk new file mode 100644 index 00000000000..7f061391a24 --- /dev/null +++ b/board/cm1_qp1/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xfc000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/cm1_qp1/fwupdate.c b/board/cm1_qp1/fwupdate.c new file mode 100644 index 00000000000..637375e5989 --- /dev/null +++ b/board/cm1_qp1/fwupdate.c @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2007 Schindler Lift Inc. + * (C) Copyright 2007 Semihalf + * + * Author: Michel Marti + * Adapted for U-Boot 1.2 by Piotr Kruszynski : + * - code clean-up + * - bugfix for overwriting bootargs by user + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include "fwupdate.h" + +extern int do_bootm(cmd_tbl_t *, int, int, char *[]); +extern long do_fat_read(const char *, void *, unsigned long, int); +extern int do_fat_fsload(cmd_tbl_t *, int, int, char *[]); + +static int load_rescue_image(ulong); + +void cm1_fwupdate(void) +{ + cmd_tbl_t *bcmd; + char *rsargs; + char *tmp = NULL; + char ka[16]; + char *argv[3] = { "bootm", ka, NULL }; + + /* Check if rescue system is disabled... */ + if (getenv("norescue")) { + printf(LOG_PREFIX "Rescue System disabled.\n"); + return; + } + + /* Check if we have a USB storage device and load image */ + if (load_rescue_image(LOAD_ADDR)) + return; + + bcmd = find_cmd("bootm"); + if (!bcmd) + return; + + sprintf(ka, "%lx", LOAD_ADDR); + + /* prepare our bootargs */ + rsargs = getenv("rs-args"); + if (!rsargs) + rsargs = RS_BOOTARGS; + else { + tmp = malloc(strlen(rsargs+1)); + if (!tmp) { + printf(LOG_PREFIX "Memory allocation failed\n"); + return; + } + strcpy(tmp, rsargs); + rsargs = tmp; + } + + setenv("bootargs", rsargs); + + if (rsargs == tmp) + free(rsargs); + + printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs); + do_bootm(bcmd, 0, 2, argv); +} + +static int load_rescue_image(ulong addr) +{ + disk_partition_t info; + int devno; + int partno; + int i; + char fwdir[64]; + char nxri[128]; + char *tmp; + char dev[7]; + char addr_str[16]; + char *argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL }; + block_dev_desc_t *stor_dev = NULL; + cmd_tbl_t *bcmd; + + /* Get name of firmware directory */ + tmp = getenv("fw-dir"); + + /* Copy it into fwdir */ + strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir)); + fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */ + + printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB" + " storage...\n", fwdir); + usb_stop(); + if (usb_init() != 0) + return 1; + + /* Check for storage device */ + if (usb_stor_scan(1) != 0) { + usb_stop(); + return 1; + } + + /* Detect storage device */ + for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) { + stor_dev = usb_stor_get_dev(devno); + if (stor_dev->type != DEV_TYPE_UNKNOWN) + break; + } + if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) { + printf(LOG_PREFIX "No valid storage device found...\n"); + usb_stop(); + return 1; + } + + /* Detect partition */ + for (partno = -1, i = 0; i < 6; i++) { + if (get_partition_info(stor_dev, i, &info) == 0) { + if (fat_register_device(stor_dev, i) == 0) { + /* Check if rescue image is present */ + FW_DEBUG("Looking for firmware directory '%s'" + " on partition %d\n", fwdir, i); + if (do_fat_read(fwdir, NULL, 0, LS_NO) == -1) { + FW_DEBUG("No NX rescue image on " + "partition %d.\n", i); + } else { + partno = i; + FW_DEBUG("Partition %d contains " + "firmware directory\n", partno); + break; + } + } + } + } + + if (partno == -1) { + printf(LOG_PREFIX "Error: No valid (FAT) partition detected\n"); + usb_stop(); + return 1; + } + + /* Load the rescue image */ + bcmd = find_cmd("fatload"); + if (!bcmd) { + printf(LOG_PREFIX "Error - 'fatload' command not present.\n"); + usb_stop(); + return 1; + } + + tmp = getenv("nx-rescue-image"); + sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE); + sprintf(dev, "%d:%d", devno, partno); + sprintf(addr_str, "%lx", addr); + + FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n", + dev, addr_str, nxri); + + if (do_fat_fsload(bcmd, 0, 5, argv) != 0) { + usb_stop(); + return 1; + } + + /* Stop USB */ + usb_stop(); + return 0; +} diff --git a/board/cm1_qp1/fwupdate.h b/board/cm1_qp1/fwupdate.h new file mode 100644 index 00000000000..119c2d691c8 --- /dev/null +++ b/board/cm1_qp1/fwupdate.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2007 Schindler Lift Inc. + * + * Author: Michel Marti + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FW_UPDATE_H +#define __FW_UPDATE_H + +/* Default prefix for output messages */ +#define LOG_PREFIX "CM1: " + +/* Extra debug macro */ +#ifdef CONFIG_FWUPDATE_DEBUG +#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt) +#else +#define FW_DEBUG(fmt...) +#endif + +/* Name of the directory holding firmware images */ +#define FW_DIR "nx-fw" +#define RESCUE_IMAGE "nxrs.img" +#define LOAD_ADDR 0x400000 +#define RS_BOOTARGS "ramdisk=8192K" + +/* Main function for fwupdate */ +void cm1_fwupdate(void); + +#endif /* __FW_UPDATE_H */ diff --git a/board/cm1_qp1/u-boot.lds b/board/cm1_qp1/u-boot.lds new file mode 100644 index 00000000000..8fa9c0f7ed5 --- /dev/null +++ b/board/cm1_qp1/u-boot.lds @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c index 813636655b2..3d99d5c1ec6 100644 --- a/cpu/mpc5xxx/fec.c +++ b/cpu/mpc5xxx/fec.c @@ -889,13 +889,20 @@ int mpc5xxx_fec_initialize(bd_t * bis) fec->eth = (ethernet_regs *)MPC5XXX_FEC; fec->tbdBase = (FEC_TBD *)FEC_BD_BASE; fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD)); -#if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \ - defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \ - defined(CONFIG_JUPITER) || defined(CONFIG_MCC200) || \ - defined(CONFIG_MOTIONPRO)|| defined(CONFIG_O2DNT) || \ - defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \ - defined(CONFIG_TQM5200) || defined(CONFIG_UC101) || \ - defined(CONFIG_V38B) +#if defined(CONFIG_CANMB) || \ + defined(CONFIG_CM1_QP1) || \ + defined(CONFIG_HMI1001) || \ + defined(CONFIG_ICECUBE) || \ + defined(CONFIG_INKA4X0) || \ + defined(CONFIG_JUPITER) || \ + defined(CONFIG_MCC200) || \ + defined(CONFIG_MOTIONPRO) || \ + defined(CONFIG_O2DNT) || \ + defined(CONFIG_PM520) || \ + defined(CONFIG_TOP5200) || \ + defined(CONFIG_TQM5200) || \ + defined(CONFIG_UC101) || \ + defined(CONFIG_V38B) # ifndef CONFIG_FEC_10MBIT fec->xcv_type = MII100; # else diff --git a/include/configs/cm1_qp1.h b/include/configs/cm1_qp1.h new file mode 100644 index 00000000000..effa41c0525 --- /dev/null +++ b/include/configs/cm1_qp1.h @@ -0,0 +1,358 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_CM1_QP1 1 /* ... on CM1.QP1 module */ + + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_I2C | \ + CFG_CMD_FLASH | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_DIAG | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP | \ + CFG_CMD_BSP | \ + CFG_CMD_USB | \ + CFG_CMD_FAT | \ + CFG_CMD_JFFS2) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */ +/* use misc_init_r() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */ +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */ + + +/* + * POST support + */ +#define CONFIG_POST (CFG_POST_MEMORY | CFG_POST_CPU | CFG_POST_I2C) +#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) +/* List of I2C addresses to be verified by POST */ +#define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM } + + +/* display image timestamps */ +#define CONFIG_TIMESTAMP 1 + + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \ + "echo" +#undef CONFIG_BOOTARGS + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=cm1_qp1\0" \ + "netmask=255.255.0.0\0" \ + "ipaddr=192.168.160.33\0" \ + "serverip=192.168.1.1\0" \ + "gatewayip=192.168.1.1\0" \ + "console=ttyPSC0\0" \ + "u-boot_addr=100000\0" \ + "kernel_addr=200000\0" \ + "kernel_addr_flash=fc0c0000\0" \ + "fdt_addr=400000\0" \ + "fdt_addr_flash=fc0a0000\0" \ + "ramdisk_addr=500000\0" \ + "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ + "u-boot=/tftpboot/cm1_qp1/u-boot.bin\0" \ + "bootfile=/tftpboot/cm1_qp1/uImage\0" \ + "fdt_file=/tftpboot/cm1_qp1/cm1_qp1.dtb\0" \ + "load=tftp ${u-boot_addr} ${u-boot}\0" \ + "update=prot off fc000000 fc05ffff; era fc000000 fc05ffff; " \ + "cp.b ${u-boot_addr} fc000000 ${filesize}; " \ + "prot on fc000000 fc05ffff\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \ + "addcons=setenv bootargs ${bootargs} " \ + "console=${console},${baudrate}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off panic=1\0" \ + "flash_flash=run flashargs addinit addip addcons;" \ + "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \ + "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \ + "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \ + "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_flash" + + +/* + * Low level configuration + */ + + +/* + * Clock configuration + */ +#define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */ +#define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */ + + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +#define CFG_LOWBOOT 1 + +/* Use ON-Chip SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT 1 +#endif + + +/* + * Chip selects configuration + */ +/* Boot Chipselect */ +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */ +/* use board_early_init_r to enable flash write in CS_BOOT */ +#define CONFIG_BOARD_EARLY_INIT_R + +/* Flash memory addressing */ +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +/* No burst, dead cycle = 1 for CS0 (Flash) */ +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x00000001 + + +/* + * SDRAM configuration + * settings for k4s561632E-xx75, assuming XLB = 132 MHz + */ +#define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */ +#define SDRAM_CONTROL 0x514F0000 +#define SDRAM_CONFIG1 0xE2333900 +#define SDRAM_CONFIG2 0x8EE70000 + + +/* + * Flash configuration + */ +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_BASE TEXT_BASE +/* we need these despite using CFI */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */ +#define CFG_FLASH_SIZE 0x02000000 /* 32 MiB */ + + +/* + * MTD configuration + */ +#define CONFIG_JFFS2_CMDLINE 1 +#define MTDIDS_DEFAULT "nor0=cm1qp1-0" +#define MTDPARTS_DEFAULT "mtdparts=cm1qp1-0:" \ + "384k(uboot),128k(env)," \ + "128k(redund_env),128k(dtb)," \ + "2m(kernel),27904k(rootfs)," \ + "-(config)" + + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #2 */ +#define CFG_I2C_SPEED 40000 /* 40 kHz */ +#define CFG_I2C_SLAVE 0x0 +#define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */ +#define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */ + + +/* + * RTC configuration + */ +#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ + + +/* + * USB configuration + */ +#define CONFIG_USB_OHCI 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 +/* Partitions (for USB) */ +#define CONFIG_MAC_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_ISO_PARTITION 1 + +/* + * Invoke our last_stage_init function - needed by fwupdate + */ +#define CONFIG_LAST_STAGE_INIT 1 + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +/* Configuration of redundant environment */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + + +/* + * Pin multiplexing configuration + */ + +/* + * CS1/GPIO_WKUP_6: GPIO (default) + * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1 + * IRDA/PSC6: UART + * Ether: Ethernet 100Mbit with MD + * PCI_DIS: PCI controller disabled + * USB: USB + * PSC3: SPI with UART3 + * PSC2: UART + * PSC1: UART + */ +#define CFG_GPS_PORT_CONFIG 0x10559C44 + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_ALT_MEMTEST 1 +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */ + +#define CONFIG_LOOPW 1 + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */ + + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/* + * Flat Device Tree support + */ +#define CONFIG_OF_FLAT_TREE 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define OF_FLAT_TREE_MAX_SIZE 8192 /* max size of the flat tree (8K) */ +#define OF_CPU "PowerPC,5200@0" +#define OF_SOC "soc5200@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From ccc091aac61a38cd998d575d92f7232e256d6312 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 8 May 2007 17:27:43 -0500 Subject: Add support for CPM device tree configuration to 8560 ADS * Adds code to modify CPM frequencies * Cleans up the config file to #define TSEC and (for now) #undef FCC * Adds the MII command for all 8560 ADS configurations * Updates config file to provide convenience commands for booting with a device tree Signed-off-by: Vitaly Bordug Signed-off-by: Andy Fleming --- board/mpc8560ads/mpc8560ads.c | 26 ++++++++++++++++++++++++++ include/configs/MPC8560ADS.h | 31 ++++++++++++++++++++----------- 2 files changed, 46 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c index d19bad68353..41acb97af7e 100644 --- a/board/mpc8560ads/mpc8560ads.c +++ b/board/mpc8560ads/mpc8560ads.c @@ -549,9 +549,35 @@ pci_init_board(void) #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) +void +ft_soc_setup(void *blob, bd_t *bd) +{ + u32 *p; + int len; + ulong data; + + p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len); + + if (p != NULL) + *p = cpu_to_be32(bd->bi_brgfreq); + + p = ft_get_prop(blob, + "/" OF_SOC "/cpm@e0000000/scc@91a00/current-speed", + &len); + if (p != NULL) + *p = cpu_to_be32(bd->bi_baudrate); + + p = ft_get_prop(blob, + "/" OF_SOC "/cpm@e0000000/scc@91a20/current-speed", + &len); + if (p != NULL) + *p = cpu_to_be32(bd->bi_baudrate); +} + void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + ft_soc_setup(blob, bd); } #endif diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 043397fc21b..90fef8bc386 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -43,9 +43,7 @@ #define CONFIG_PCI #define CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_TSEC_ENET /* tsec ethernet support */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ +#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_DLL /* possible DLL fix needed */ @@ -349,13 +347,15 @@ #endif /* CONFIG_PCI */ -#if defined(CONFIG_TSEC_ENET) +#ifdef CONFIG_TSEC_ENET #ifndef CONFIG_NET_MULTI #define CONFIG_NET_MULTI 1 #endif +#ifndef CONFIG_MII #define CONFIG_MII 1 /* MII PHY management */ +#endif #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "TSEC0" #define CONFIG_TSEC2 1 @@ -369,9 +369,10 @@ /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC0" -#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ +#endif /* CONFIG_TSEC_ENET */ + +#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ -#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ #undef CONFIG_ETHER_NONE /* define if ether on something else */ #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ @@ -392,7 +393,10 @@ #define FETH3_RST 0x80 #endif /* CONFIG_ETHER_INDEX */ -#define CONFIG_MII /* MII PHY management */ +#ifndef CONFIG_MII +#define CONFIG_MII 1 /* MII PHY management */ +#endif + #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ /* @@ -458,11 +462,13 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_PCI \ | CFG_CMD_PING \ + | CFG_CMD_MII \ | CFG_CMD_I2C) #elif defined(CONFIG_TSEC_ENET) #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_PING \ - | CFG_CMD_I2C) + | CFG_CMD_I2C \ + | CFG_CMD_MII) #elif defined(CONFIG_ETHER_ON_FCC) #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_MII \ @@ -554,8 +560,10 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=400000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" + "ramdiskaddr=600000\0" \ + "ramdiskfile=your.ramdisk.u-boot\0" \ + "fdtaddr=400000\0" \ + "fdtfile=mpc8560ads.dtb\0" #define CONFIG_NFSBOOTCOMMAND \ "setenv bootargs root=/dev/nfs rw " \ @@ -563,7 +571,8 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ "setenv bootargs root=/dev/ram rw " \ -- cgit v1.3.1 From d3ec0d943a045bdb99e159e7bbc77430e09f11d7 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Thu, 10 May 2007 17:50:01 -0500 Subject: Polished the 85xx ADS config files Made the boot commands use device trees by default. Also moved the ramdisk to 1000000 (I think the previous address was getting overridden during boot). Signed-off-by: Andy Fleming --- include/configs/MPC8540ADS.h | 4 ++-- include/configs/MPC8560ADS.h | 7 ++++--- 2 files changed, 6 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 9176be388e6..f5e7f77b6d0 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -520,7 +520,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "ramdiskaddr=600000\0" \ + "ramdiskaddr=1000000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ "fdtaddr=400000\0" \ "fdtfile=your.fdt.dtb\0" @@ -540,7 +540,7 @@ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr" + "bootm $loadaddr $ramdiskaddr $fdtaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 90fef8bc386..3d413717cb0 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -559,8 +559,8 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=600000\0" \ + "consoledev=ttyCPM\0" \ + "ramdiskaddr=1000000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \ "fdtaddr=400000\0" \ "fdtfile=mpc8560ads.dtb\0" @@ -579,7 +579,8 @@ "console=$consoledev,$baudrate $othbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \ "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND -- cgit v1.3.1 From 982efcf23fd03647e01e2fbe28a7a36239156cc0 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Tue, 5 Jun 2007 16:38:44 -0500 Subject: From: eran liberty adds the reset register to 85xx immap Signed-off-by: Eran Liberty Signed-off-by: Andy Fleming --- include/asm-ppc/immap_85xx.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 5377c2eb5be..e002d2838e9 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1548,7 +1548,9 @@ typedef struct ccsr_gur { char res9[12]; uint pvr; /* 0xe00a0 - Processor version register */ uint svr; /* 0xe00a4 - System version register */ - char res10[3416]; + char res10a[8]; + uint rstcr; /* 0xe00b0 - Reset control register */ + char res10b[3404]; uint clkocr; /* 0xe0e00 - Clock out select register */ char res11[12]; uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ -- cgit v1.3.1 From fad63407154f46246ce80d53a9c669a44362ac67 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 13 Jul 2007 09:54:17 +0200 Subject: make show_boot_progress () weak. Signed-off-by: Heiko Schocher --- common/cmd_bootm.c | 69 ++++++++++++++++++--------------------- common/cmd_doc.c | 33 ++++++++----------- common/cmd_ide.c | 49 ++++++++++++--------------- common/cmd_nand.c | 66 ++++++++++++++++--------------------- common/cmd_net.c | 28 +++++----------- common/env_common.c | 9 +---- common/main.c | 6 ++++ drivers/nand_legacy/nand_legacy.c | 7 ---- include/common.h | 8 +++-- lib_arm/armlinux.c | 27 ++++++--------- lib_avr32/avr32_linux.c | 27 ++++++--------- lib_blackfin/bf533_linux.c | 7 ---- lib_blackfin/post.c | 8 ++--- lib_m68k/m68k_linux.c | 27 ++++++--------- lib_microblaze/microblaze_linux.c | 27 ++++++--------- lib_mips/mips_linux.c | 27 ++++++--------- lib_ppc/board.c | 2 -- net/eth.c | 14 ++------ post/post.c | 8 ++--- 19 files changed, 173 insertions(+), 276 deletions(-) (limited to 'include') diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index a6499e8dd9b..ba286f1e636 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -56,13 +56,6 @@ DECLARE_GLOBAL_DATA_PTR; #include #endif -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - #ifdef CFG_INIT_RAM_LOCK #include #endif @@ -176,7 +169,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) addr = simple_strtoul(argv[1], NULL, 16); } - SHOW_BOOT_PROGRESS (1); + show_boot_progress (1); printf ("## Booting image at %08lx ...\n", addr); /* Copy header so we can blank CRC field for re-calculation */ @@ -200,11 +193,11 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif /* __I386__ */ { puts ("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS (-1); + show_boot_progress (-1); return 1; } } - SHOW_BOOT_PROGRESS (2); + show_boot_progress (2); data = (ulong)&header; len = sizeof(image_header_t); @@ -214,10 +207,10 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (crc32 (0, (uchar *)data, len) != checksum) { puts ("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS (-2); + show_boot_progress (-2); return 1; } - SHOW_BOOT_PROGRESS (3); + show_boot_progress (3); #ifdef CONFIG_HAS_DATAFLASH if (addr_dataflash(addr)){ @@ -238,12 +231,12 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) puts (" Verifying Checksum ... "); if (crc32 (0, (uchar *)data, len) != ntohl(hdr->ih_dcrc)) { printf ("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS (-3); + show_boot_progress (-3); return 1; } puts ("OK\n"); } - SHOW_BOOT_PROGRESS (4); + show_boot_progress (4); len_ptr = (ulong *)data; @@ -272,10 +265,10 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif { printf ("Unsupported Architecture 0x%x\n", hdr->ih_arch); - SHOW_BOOT_PROGRESS (-4); + show_boot_progress (-4); return 1; } - SHOW_BOOT_PROGRESS (5); + show_boot_progress (5); switch (hdr->ih_type) { case IH_TYPE_STANDALONE: @@ -297,10 +290,10 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) data += 4; break; default: printf ("Wrong Image Type for %s command\n", cmdtp->name); - SHOW_BOOT_PROGRESS (-5); + show_boot_progress (-5); return 1; } - SHOW_BOOT_PROGRESS (6); + show_boot_progress (6); /* * We have reached the point of no return: we are going to @@ -351,7 +344,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (gunzip ((void *)ntohl(hdr->ih_load), unc_len, (uchar *)data, &len) != 0) { puts ("GUNZIP ERROR - must RESET board to recover\n"); - SHOW_BOOT_PROGRESS (-6); + show_boot_progress (-6); do_reset (cmdtp, flag, argc, argv); } break; @@ -368,7 +361,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) CFG_MALLOC_LEN < (4096 * 1024), 0); if (i != BZ_OK) { printf ("BUNZIP2 ERROR %d - must RESET board to recover\n", i); - SHOW_BOOT_PROGRESS (-6); + show_boot_progress (-6); udelay(100000); do_reset (cmdtp, flag, argc, argv); } @@ -378,11 +371,11 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (iflag) enable_interrupts(); printf ("Unimplemented compression type %d\n", hdr->ih_comp); - SHOW_BOOT_PROGRESS (-7); + show_boot_progress (-7); return 1; } puts ("OK\n"); - SHOW_BOOT_PROGRESS (7); + show_boot_progress (7); switch (hdr->ih_type) { case IH_TYPE_STANDALONE: @@ -409,10 +402,10 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (iflag) enable_interrupts(); printf ("Can't boot image type %d\n", hdr->ih_type); - SHOW_BOOT_PROGRESS (-8); + show_boot_progress (-8); return 1; } - SHOW_BOOT_PROGRESS (8); + show_boot_progress (8); switch (hdr->ih_os) { default: /* handled by (original) Linux case */ @@ -458,7 +451,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #endif } - SHOW_BOOT_PROGRESS (-9); + show_boot_progress (-9); #ifdef DEBUG puts ("\n## Control returned to monitor - resetting...\n"); do_reset (cmdtp, flag, argc, argv); @@ -637,7 +630,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, #endif if (argc >= 3) { debug ("Not skipping initrd\n"); - SHOW_BOOT_PROGRESS (9); + show_boot_progress (9); addr = simple_strtoul(argv[2], NULL, 16); @@ -648,7 +641,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, if (ntohl(hdr->ih_magic) != IH_MAGIC) { puts ("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS (-10); + show_boot_progress (-10); do_reset (cmdtp, flag, argc, argv); } @@ -660,11 +653,11 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, if (crc32 (0, (uchar *)data, len) != checksum) { puts ("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS (-11); + show_boot_progress (-11); do_reset (cmdtp, flag, argc, argv); } - SHOW_BOOT_PROGRESS (10); + show_boot_progress (10); print_image_hdr (hdr); @@ -697,19 +690,19 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, if (csum != ntohl(hdr->ih_dcrc)) { puts ("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS (-12); + show_boot_progress (-12); do_reset (cmdtp, flag, argc, argv); } puts ("OK\n"); } - SHOW_BOOT_PROGRESS (11); + show_boot_progress (11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_PPC) || (hdr->ih_type != IH_TYPE_RAMDISK) ) { puts ("No Linux PPC Ramdisk Image\n"); - SHOW_BOOT_PROGRESS (-13); + show_boot_progress (-13); do_reset (cmdtp, flag, argc, argv); } @@ -720,7 +713,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, u_long tail = ntohl(len_ptr[0]) % 4; int i; - SHOW_BOOT_PROGRESS (13); + show_boot_progress (13); /* skip kernel length and terminator */ data = (ulong)(&len_ptr[2]); @@ -739,7 +732,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, /* * no initrd image */ - SHOW_BOOT_PROGRESS (14); + show_boot_progress (14); len = data = 0; } @@ -890,7 +883,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, initrd_start = nsp; } - SHOW_BOOT_PROGRESS (12); + show_boot_progress (12); debug ("## initrd at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n", data, data + len - 1, len, len); @@ -926,7 +919,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag, debug ("## Transferring control to Linux (at address %08lx) ...\n", (ulong)kernel); - SHOW_BOOT_PROGRESS (15); + show_boot_progress (15); #if defined(CFG_INIT_RAM_LOCK) && !defined(CONFIG_E500) unlock_ram_in_cache(); @@ -1115,7 +1108,7 @@ do_bootm_netbsd (cmd_tbl_t *cmdtp, int flag, printf ("## Transferring control to NetBSD stage-2 loader (at address %08lx) ...\n", (ulong)loader); - SHOW_BOOT_PROGRESS (15); + show_boot_progress (15); /* * NetBSD Stage-2 Loader Parameters: @@ -1578,7 +1571,7 @@ do_bootm_rtems (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], printf ("## Transferring control to RTEMS (at address %08lx) ...\n", (ulong)entry_point); - SHOW_BOOT_PROGRESS (15); + show_boot_progress (15); /* * RTEMS Parameters: diff --git a/common/cmd_doc.c b/common/cmd_doc.c index 4e624a2f3fa..9814d754fb7 100644 --- a/common/cmd_doc.c +++ b/common/cmd_doc.c @@ -12,13 +12,6 @@ #include #include -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - #if (CONFIG_COMMANDS & CFG_CMD_DOC) #include @@ -216,7 +209,7 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) image_header_t *hdr; int rcode = 0; - SHOW_BOOT_PROGRESS (34); + show_boot_progress (34); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -237,27 +230,27 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS (-35); + show_boot_progress (-35); return 1; } - SHOW_BOOT_PROGRESS (35); + show_boot_progress (35); if (!boot_device) { puts ("\n** No boot device **\n"); - SHOW_BOOT_PROGRESS (-36); + show_boot_progress (-36); return 1; } - SHOW_BOOT_PROGRESS (36); + show_boot_progress (36); dev = simple_strtoul(boot_device, &ep, 16); if ((dev >= CFG_MAX_DOC_DEVICE) || (doc_dev_desc[dev].ChipID == DOC_ChipID_UNKNOWN)) { printf ("\n** Device %d not available\n", dev); - SHOW_BOOT_PROGRESS (-37); + show_boot_progress (-37); return 1; } - SHOW_BOOT_PROGRESS (37); + show_boot_progress (37); printf ("\nLoading from device %d: %s at 0x%lX (offset 0x%lX)\n", dev, doc_dev_desc[dev].name, doc_dev_desc[dev].physadr, @@ -266,10 +259,10 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (doc_rw (doc_dev_desc + dev, 1, offset, SECTORSIZE, NULL, (u_char *)addr)) { printf ("** Read error on %d\n", dev); - SHOW_BOOT_PROGRESS (-38); + show_boot_progress (-38); return 1; } - SHOW_BOOT_PROGRESS (38); + show_boot_progress (38); hdr = (image_header_t *)addr; @@ -281,18 +274,18 @@ int do_docboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) cnt -= SECTORSIZE; } else { puts ("\n** Bad Magic Number **\n"); - SHOW_BOOT_PROGRESS (-39); + show_boot_progress (-39); return 1; } - SHOW_BOOT_PROGRESS (39); + show_boot_progress (39); if (doc_rw (doc_dev_desc + dev, 1, offset + SECTORSIZE, cnt, NULL, (u_char *)(addr+SECTORSIZE))) { printf ("** Read error on %d\n", dev); - SHOW_BOOT_PROGRESS (-40); + show_boot_progress (-40); return 1; } - SHOW_BOOT_PROGRESS (40); + show_boot_progress (40); /* Loading ok, update default load address */ diff --git a/common/cmd_ide.c b/common/cmd_ide.c index c74cde96e89..87791569490 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -59,13 +59,6 @@ unsigned long mips_io_port_base = 0; #endif #endif -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - #ifdef CONFIG_IDE_8xx_DIRECT DECLARE_GLOBAL_DATA_PTR; #endif @@ -385,7 +378,7 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) image_header_t *hdr; int rcode = 0; - SHOW_BOOT_PROGRESS (41); + show_boot_progress (41); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -401,50 +394,50 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS (-42); + show_boot_progress (-42); return 1; } - SHOW_BOOT_PROGRESS (42); + show_boot_progress (42); if (!boot_device) { puts ("\n** No boot device **\n"); - SHOW_BOOT_PROGRESS (-43); + show_boot_progress (-43); return 1; } - SHOW_BOOT_PROGRESS (43); + show_boot_progress (43); dev = simple_strtoul(boot_device, &ep, 16); if (ide_dev_desc[dev].type==DEV_TYPE_UNKNOWN) { printf ("\n** Device %d not available\n", dev); - SHOW_BOOT_PROGRESS (-44); + show_boot_progress (-44); return 1; } - SHOW_BOOT_PROGRESS (44); + show_boot_progress (44); if (*ep) { if (*ep != ':') { puts ("\n** Invalid boot device, use `dev[:part]' **\n"); - SHOW_BOOT_PROGRESS (-45); + show_boot_progress (-45); return 1; } part = simple_strtoul(++ep, NULL, 16); } - SHOW_BOOT_PROGRESS (45); + show_boot_progress (45); if (get_partition_info (&ide_dev_desc[dev], part, &info)) { - SHOW_BOOT_PROGRESS (-46); + show_boot_progress (-46); return 1; } - SHOW_BOOT_PROGRESS (46); + show_boot_progress (46); if ((strncmp((char *)info.type, BOOT_PART_TYPE, sizeof(info.type)) != 0) && (strncmp((char *)info.type, BOOT_PART_COMP, sizeof(info.type)) != 0)) { printf ("\n** Invalid partition type \"%.32s\"" " (expect \"" BOOT_PART_TYPE "\")\n", info.type); - SHOW_BOOT_PROGRESS (-47); + show_boot_progress (-47); return 1; } - SHOW_BOOT_PROGRESS (47); + show_boot_progress (47); printf ("\nLoading from IDE device %d, partition %d: " "Name: %.32s Type: %.32s\n", @@ -455,29 +448,29 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (ide_dev_desc[dev].block_read (dev, info.start, 1, (ulong *)addr) != 1) { printf ("** Read error on %d:%d\n", dev, part); - SHOW_BOOT_PROGRESS (-48); + show_boot_progress (-48); return 1; } - SHOW_BOOT_PROGRESS (48); + show_boot_progress (48); hdr = (image_header_t *)addr; if (ntohl(hdr->ih_magic) != IH_MAGIC) { printf("\n** Bad Magic Number **\n"); - SHOW_BOOT_PROGRESS (-49); + show_boot_progress (-49); return 1; } - SHOW_BOOT_PROGRESS (49); + show_boot_progress (49); checksum = ntohl(hdr->ih_hcrc); hdr->ih_hcrc = 0; if (crc32 (0, (uchar *)hdr, sizeof(image_header_t)) != checksum) { puts ("\n** Bad Header Checksum **\n"); - SHOW_BOOT_PROGRESS (-50); + show_boot_progress (-50); return 1; } - SHOW_BOOT_PROGRESS (50); + show_boot_progress (50); hdr->ih_hcrc = htonl(checksum); /* restore checksum for later use */ print_image_hdr (hdr); @@ -490,10 +483,10 @@ int do_diskboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (ide_dev_desc[dev].block_read (dev, info.start+1, cnt, (ulong *)(addr+info.blksz)) != cnt) { printf ("** Read error on %d:%d\n", dev, part); - SHOW_BOOT_PROGRESS (-51); + show_boot_progress (-51); return 1; } - SHOW_BOOT_PROGRESS (51); + show_boot_progress (51); /* Loading ok, update default load address */ diff --git a/common/cmd_nand.c b/common/cmd_nand.c index b088150f3bf..cb62661ec27 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -25,14 +25,6 @@ #include #include #include - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - #include #include @@ -486,19 +478,19 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, r = nand_read(nand, offset, &cnt, (u_char *) addr); if (r) { puts("** Read error\n"); - SHOW_BOOT_PROGRESS(-56); + show_boot_progress (-56); return 1; } - SHOW_BOOT_PROGRESS(56); + show_boot_progress (56); hdr = (image_header_t *) addr; if (ntohl(hdr->ih_magic) != IH_MAGIC) { printf("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic); - SHOW_BOOT_PROGRESS(-57); + show_boot_progress (-57); return 1; } - SHOW_BOOT_PROGRESS(57); + show_boot_progress (57); print_image_hdr(hdr); @@ -507,10 +499,10 @@ static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, r = nand_read(nand, offset, &cnt, (u_char *) addr); if (r) { puts("** Read error\n"); - SHOW_BOOT_PROGRESS(-58); + show_boot_progress (-58); return 1; } - SHOW_BOOT_PROGRESS(58); + show_boot_progress (58); /* Loading ok, update default load address */ @@ -562,7 +554,7 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } #endif - SHOW_BOOT_PROGRESS(52); + show_boot_progress(52); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -586,26 +578,26 @@ int do_nandboot(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) usage: #endif printf("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS(-53); + show_boot_progress(-53); return 1; } - SHOW_BOOT_PROGRESS(53); + show_boot_progress(53); if (!boot_device) { puts("\n** No boot device **\n"); - SHOW_BOOT_PROGRESS(-54); + show_boot_progress(-54); return 1; } - SHOW_BOOT_PROGRESS(54); + show_boot_progress(54); idx = simple_strtoul(boot_device, NULL, 16); if (idx < 0 || idx >= CFG_MAX_NAND_DEVICE || !nand_info[idx].name) { printf("\n** Device %d not available\n", idx); - SHOW_BOOT_PROGRESS(-55); + show_boot_progress(-55); return 1; } - SHOW_BOOT_PROGRESS(55); + show_boot_progress(55); return nand_load_image(cmdtp, &nand_info[idx], offset, addr, argv[0]); } @@ -627,11 +619,11 @@ U_BOOT_CMD(nboot, 4, 1, do_nandboot, #include #include -#ifdef CONFIG_SHOW_BOOT_PROGRESS +#ifdef CONFIG_show_boot_progress # include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) +# define show_boot_progress(arg) show_boot_progress(arg) #else -# define SHOW_BOOT_PROGRESS(arg) +# define show_boot_progress(arg) #endif #if (CONFIG_COMMANDS & CFG_CMD_NAND) @@ -894,7 +886,7 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong offset = 0; image_header_t *hdr; int rcode = 0; - SHOW_BOOT_PROGRESS(52); + show_boot_progress (52); switch (argc) { case 1: addr = CFG_LOAD_ADDR; @@ -915,27 +907,27 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS (-53); + show_boot_progress (-53); return 1; } - SHOW_BOOT_PROGRESS(53); + show_boot_progress (53); if (!boot_device) { puts ("\n** No boot device **\n"); - SHOW_BOOT_PROGRESS (-54); + show_boot_progress (-54); return 1; } - SHOW_BOOT_PROGRESS(54); + show_boot_progress (54); dev = simple_strtoul(boot_device, &ep, 16); if ((dev >= CFG_MAX_NAND_DEVICE) || (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) { printf ("\n** Device %d not available\n", dev); - SHOW_BOOT_PROGRESS (-55); + show_boot_progress (-55); return 1; } - SHOW_BOOT_PROGRESS(55); + show_boot_progress (55); printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n", dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR, @@ -944,10 +936,10 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset, SECTORSIZE, NULL, (u_char *)addr)) { printf ("** Read error on %d\n", dev); - SHOW_BOOT_PROGRESS (-56); + show_boot_progress (-56); return 1; } - SHOW_BOOT_PROGRESS(56); + show_boot_progress (56); hdr = (image_header_t *)addr; @@ -959,19 +951,19 @@ int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) cnt -= SECTORSIZE; } else { printf ("\n** Bad Magic Number 0x%x **\n", ntohl(hdr->ih_magic)); - SHOW_BOOT_PROGRESS (-57); + show_boot_progress (-57); return 1; } - SHOW_BOOT_PROGRESS(57); + show_boot_progress (57); if (nand_legacy_rw (nand_dev_desc + dev, NANDRW_READ, offset + SECTORSIZE, cnt, NULL, (u_char *)(addr+SECTORSIZE))) { printf ("** Read error on %d\n", dev); - SHOW_BOOT_PROGRESS (-58); + show_boot_progress (-58); return 1; } - SHOW_BOOT_PROGRESS(58); + show_boot_progress (58); /* Loading ok, update default load address */ diff --git a/common/cmd_net.c b/common/cmd_net.c index e9d552e2352..f1097a9951d 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -30,14 +30,6 @@ #if (CONFIG_COMMANDS & CFG_CMD_NET) -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -extern void show_boot_progress (int val); -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress (arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - extern int do_bootm (cmd_tbl_t *, int, int, char *[]); static int netboot_common (proto_t, cmd_tbl_t *, int , char *[]); @@ -191,23 +183,23 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) break; default: printf ("Usage:\n%s\n", cmdtp->usage); - SHOW_BOOT_PROGRESS(-80); + show_boot_progress (-80); return 1; } - SHOW_BOOT_PROGRESS(80); + show_boot_progress (80); if ((size = NetLoop(proto)) < 0) { - SHOW_BOOT_PROGRESS(-81); + show_boot_progress (-81); return 1; } - SHOW_BOOT_PROGRESS(81); + show_boot_progress (81); /* NetLoop ok, update environment */ netboot_update_env(); /* done if no file was loaded (no errors though) */ if (size == 0) { - SHOW_BOOT_PROGRESS(-82); + show_boot_progress (-82); return 0; } @@ -222,23 +214,21 @@ netboot_common (proto_t proto, cmd_tbl_t *cmdtp, int argc, char *argv[]) printf ("Automatic boot of image at addr 0x%08lX ...\n", load_addr); - SHOW_BOOT_PROGRESS(82); + show_boot_progress (82); rcode = do_bootm (cmdtp, 0, 1, local_args); } #ifdef CONFIG_AUTOSCRIPT if (((s = getenv("autoscript")) != NULL) && (strcmp(s,"yes") == 0)) { printf("Running autoscript at addr 0x%08lX ...\n", load_addr); - SHOW_BOOT_PROGRESS(83); + show_boot_progress (83); rcode = autoscript (load_addr); } #endif -#if defined(CONFIG_SHOW_BOOT_PROGRESS) if (rcode < 0) - SHOW_BOOT_PROGRESS(-83); + show_boot_progress (-83); else - SHOW_BOOT_PROGRESS(84); -#endif + show_boot_progress (84); return rcode; } diff --git a/common/env_common.c b/common/env_common.c index 0462cad6d72..a49481244e2 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -30,13 +30,6 @@ #include #include -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_AMIGAONEG3SE @@ -232,7 +225,7 @@ void env_relocate (void) puts ("Using default environment\n\n"); #else puts ("*** Warning - bad CRC, using default environment\n\n"); - SHOW_BOOT_PROGRESS (-60); + show_boot_progress (-60); #endif if (sizeof(default_environment) > ENV_SIZE) diff --git a/common/main.c b/common/main.c index a00ebc194c5..000686d85a9 100644 --- a/common/main.c +++ b/common/main.c @@ -44,6 +44,12 @@ DECLARE_GLOBAL_DATA_PTR; #endif +/* + * Board-specific Platform code can reimplement show_boot_progress () if needed + */ +void inline __show_boot_progress (int val) {} +void inline show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress"))); + #if defined(CONFIG_BOOT_RETRY_TIME) && defined(CONFIG_RESET_TO_RETRY) extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* for do_reset() prototype */ #endif diff --git a/drivers/nand_legacy/nand_legacy.c b/drivers/nand_legacy/nand_legacy.c index 458046d41c3..753f5412953 100644 --- a/drivers/nand_legacy/nand_legacy.c +++ b/drivers/nand_legacy/nand_legacy.c @@ -15,13 +15,6 @@ #include #include -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - #if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) #include diff --git a/include/common.h b/include/common.h index d8b6b469e5f..23f93907ee4 100644 --- a/include/common.h +++ b/include/common.h @@ -626,9 +626,13 @@ int fgetc(int file); int pcmcia_init (void); -#ifdef CONFIG_SHOW_BOOT_PROGRESS -void show_boot_progress (int status); +#ifdef CONFIG_STATUS_LED +# include #endif +/* + * Board-specific Platform code can reimplement show_boot_progress () if needed + */ +void inline show_boot_progress (int val); #ifdef CONFIG_INIT_CRITICAL #error CONFIG_INIT_CRITICAL is deprecated! diff --git a/lib_arm/armlinux.c b/lib_arm/armlinux.c index 56b7fca8333..6d32a411fde 100644 --- a/lib_arm/armlinux.c +++ b/lib_arm/armlinux.c @@ -66,13 +66,6 @@ static void setup_videolfb_tag (gd_t *gd); static struct tag *params; #endif /* CONFIG_SETUP_MEMORY_TAGS || CONFIG_CMDLINE_TAG || CONFIG_INITRD_TAG */ -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - extern image_header_t header; /* from cmd_bootm.c */ @@ -96,7 +89,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], * Check if there is an initrd image */ if (argc >= 3) { - SHOW_BOOT_PROGRESS (9); + show_boot_progress (9); addr = simple_strtoul (argv[2], NULL, 16); @@ -114,7 +107,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], if (ntohl (hdr->ih_magic) != IH_MAGIC) { printf ("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS (-10); + show_boot_progress (-10); do_reset (cmdtp, flag, argc, argv); } @@ -126,11 +119,11 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], if (crc32 (0, (unsigned char *) data, len) != checksum) { printf ("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS (-11); + show_boot_progress (-11); do_reset (cmdtp, flag, argc, argv); } - SHOW_BOOT_PROGRESS (10); + show_boot_progress (10); print_image_hdr (hdr); @@ -151,19 +144,19 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], csum = crc32 (0, (unsigned char *) data, len); if (csum != ntohl (hdr->ih_dcrc)) { printf ("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS (-12); + show_boot_progress (-12); do_reset (cmdtp, flag, argc, argv); } printf ("OK\n"); } - SHOW_BOOT_PROGRESS (11); + show_boot_progress (11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_ARM) || (hdr->ih_type != IH_TYPE_RAMDISK)) { printf ("No Linux ARM Ramdisk Image\n"); - SHOW_BOOT_PROGRESS (-13); + show_boot_progress (-13); do_reset (cmdtp, flag, argc, argv); } @@ -182,7 +175,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], ulong tail = ntohl (len_ptr[0]) % 4; int i; - SHOW_BOOT_PROGRESS (13); + show_boot_progress (13); /* skip kernel length and terminator */ data = (ulong) (&len_ptr[2]); @@ -201,7 +194,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], /* * no initrd image */ - SHOW_BOOT_PROGRESS (14); + show_boot_progress (14); len = data = 0; } @@ -220,7 +213,7 @@ void do_bootm_linux (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], initrd_end = 0; } - SHOW_BOOT_PROGRESS (15); + show_boot_progress (15); debug ("## Transferring control to Linux (at address %08lx) ...\n", (ulong) theKernel); diff --git a/lib_avr32/avr32_linux.c b/lib_avr32/avr32_linux.c index 6095e2ff214..62afbd24974 100644 --- a/lib_avr32/avr32_linux.c +++ b/lib_avr32/avr32_linux.c @@ -36,13 +36,6 @@ extern int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /* CPU-specific hook to allow flushing of caches, etc. */ extern void prepare_to_boot(void); -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - extern image_header_t header; /* from cmd_bootm.c */ static struct tag *setup_start_tag(struct tag *params) @@ -204,7 +197,7 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], * Check if there is an initrd image */ if (argc >= 3) { - SHOW_BOOT_PROGRESS(9); + show_boot_progress (9); addr = simple_strtoul(argv[2], NULL, 16); @@ -215,7 +208,7 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], if (ntohl(hdr->ih_magic) != IH_MAGIC) { puts("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS(-10); + show_boot_progress (-10); do_reset(cmdtp, flag, argc, argv); } @@ -226,11 +219,11 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], if (crc32(0, (unsigned char *)data, len) != checksum) { puts("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS(-11); + show_boot_progress (-11); do_reset(cmdtp, flag, argc, argv); } - SHOW_BOOT_PROGRESS(10); + show_boot_progress (10); print_image_hdr(hdr); @@ -244,26 +237,26 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], csum = crc32(0, (unsigned char *)data, len); if (csum != ntohl(hdr->ih_dcrc)) { puts("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS(-12); + show_boot_progress (-12); do_reset(cmdtp, flag, argc, argv); } puts("OK\n"); } - SHOW_BOOT_PROGRESS(11); + show_boot_progress (11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_AVR32) || (hdr->ih_type != IH_TYPE_RAMDISK)) { puts("Not a Linux/AVR32 RAMDISK image\n"); - SHOW_BOOT_PROGRESS(-13); + show_boot_progress (-13); do_reset(cmdtp, flag, argc, argv); } } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) { ulong tail = ntohl (len_ptr[0]) % 4; int i; - SHOW_BOOT_PROGRESS (13); + show_boot_progress (13); /* skip kernel length and terminator */ data = (ulong) (&len_ptr[2]); @@ -279,7 +272,7 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], len = ntohl (len_ptr[1]); } else { /* no initrd image */ - SHOW_BOOT_PROGRESS(14); + show_boot_progress (14); len = data = 0; } @@ -291,7 +284,7 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[], initrd_end = 0; } - SHOW_BOOT_PROGRESS(15); + show_boot_progress (15); params = params_start = (struct tag *)gd->bd->bi_boot_params; params = setup_start_tag(params); diff --git a/lib_blackfin/bf533_linux.c b/lib_blackfin/bf533_linux.c index 3b9c4df9883..80a3dc7d6e1 100644 --- a/lib_blackfin/bf533_linux.c +++ b/lib_blackfin/bf533_linux.c @@ -36,13 +36,6 @@ #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 -#ifdef CONFIG_SHOW_BOOT_PROGRESS -#include -#define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -#define SHOW_BOOT_PROGRESS(arg) -#endif - #define CMD_LINE_ADDR 0xFF900000 /* L1 scratchpad */ #ifdef SHARED_RESOURCES diff --git a/lib_blackfin/post.c b/lib_blackfin/post.c index 0e76026adf1..7c9478def5c 100644 --- a/lib_blackfin/post.c +++ b/lib_blackfin/post.c @@ -132,9 +132,7 @@ void post_output_backlog(void) post_log("PASSED\n"); else { post_log("FAILED\n"); -#ifdef CONFIG_SHOW_BOOT_PROGRESS - show_boot_progress(-31); -#endif + show_boot_progress (-31); } } } @@ -245,9 +243,7 @@ static int post_run_single(struct post_test *test, } else { if ((*test->test) (flags) != 0) { post_log("FAILED\n"); -#ifdef CONFIG_SHOW_BOOT_PROGRESS - show_boot_progress(-32); -#endif + show_boot_progress (-32); } else post_log("PASSED\n"); } diff --git a/lib_m68k/m68k_linux.c b/lib_m68k/m68k_linux.c index f87f56ea8f2..6c194f80aa7 100644 --- a/lib_m68k/m68k_linux.c +++ b/lib_m68k/m68k_linux.c @@ -34,13 +34,6 @@ DECLARE_GLOBAL_DATA_PTR; #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - extern image_header_t header; /* from cmd_bootm.c */ extern int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); @@ -73,7 +66,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], * Check if there is an initrd image */ if (argc >= 3) { - SHOW_BOOT_PROGRESS (9); + show_boot_progress (9); addr = simple_strtoul (argv[2], NULL, 16); @@ -84,7 +77,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], if (ntohl (hdr->ih_magic) != IH_MAGIC) { printf ("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS (-10); + show_boot_progress (-10); do_reset (cmdtp, flag, argc, argv); } @@ -96,11 +89,11 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], if (crc32 (0, (char *) data, len) != checksum) { printf ("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS (-11); + show_boot_progress (-11); do_reset (cmdtp, flag, argc, argv); } - SHOW_BOOT_PROGRESS (10); + show_boot_progress (10); print_image_hdr (hdr); @@ -114,19 +107,19 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], csum = crc32 (0, (char *) data, len); if (csum != ntohl (hdr->ih_dcrc)) { printf ("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS (-12); + show_boot_progress (-12); do_reset (cmdtp, flag, argc, argv); } printf ("OK\n"); } - SHOW_BOOT_PROGRESS (11); + show_boot_progress (11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_M68K) || (hdr->ih_type != IH_TYPE_RAMDISK)) { printf ("No Linux M68K Ramdisk Image\n"); - SHOW_BOOT_PROGRESS (-13); + show_boot_progress (-13); do_reset (cmdtp, flag, argc, argv); } @@ -137,7 +130,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], ulong tail = ntohl (len_ptr[0]) % 4; int i; - SHOW_BOOT_PROGRESS (13); + show_boot_progress (13); /* skip kernel length and terminator */ data = (ulong) (&len_ptr[2]); @@ -156,7 +149,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], /* * no initrd image */ - SHOW_BOOT_PROGRESS (14); + show_boot_progress (14); data = 0; } @@ -175,7 +168,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], initrd_end = 0; } - SHOW_BOOT_PROGRESS (15); + show_boot_progress (15); #ifdef DEBUG printf ("## Transferring control to Linux (at address %08lx) ...\n", diff --git a/lib_microblaze/microblaze_linux.c b/lib_microblaze/microblaze_linux.c index 2c7885c1f11..68b58d4be89 100644 --- a/lib_microblaze/microblaze_linux.c +++ b/lib_microblaze/microblaze_linux.c @@ -32,13 +32,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - extern image_header_t header; /* from cmd_bootm.c */ /*cmd_boot.c*/ extern int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]); @@ -59,7 +52,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], /* Check if there is an initrd image */ if (argc >= 3) { - SHOW_BOOT_PROGRESS (9); + show_boot_progress (9); addr = simple_strtoul (argv[2], NULL, 16); @@ -70,7 +63,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], if (ntohl (hdr->ih_magic) != IH_MAGIC) { printf ("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS (-10); + show_boot_progress (-10); do_reset (cmdtp, flag, argc, argv); } @@ -82,11 +75,11 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], if (crc32 (0, (char *)data, len) != checksum) { printf ("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS (-11); + show_boot_progress (-11); do_reset (cmdtp, flag, argc, argv); } - SHOW_BOOT_PROGRESS (10); + show_boot_progress (10); print_image_hdr (hdr); @@ -100,19 +93,19 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], csum = crc32 (0, (char *)data, len); if (csum != ntohl (hdr->ih_dcrc)) { printf ("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS (-12); + show_boot_progress (-12); do_reset (cmdtp, flag, argc, argv); } printf ("OK\n"); } - SHOW_BOOT_PROGRESS (11); + show_boot_progress (11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_MICROBLAZE) || (hdr->ih_type != IH_TYPE_RAMDISK)) { printf ("No Linux Microblaze Ramdisk Image\n"); - SHOW_BOOT_PROGRESS (-13); + show_boot_progress (-13); do_reset (cmdtp, flag, argc, argv); } @@ -122,7 +115,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], } else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) { ulong tail = ntohl (len_ptr[0]) % 4; - SHOW_BOOT_PROGRESS (13); + show_boot_progress (13); /* skip kernel length and terminator */ data = (ulong) (&len_ptr[2]); @@ -141,7 +134,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], /* * no initrd image */ - SHOW_BOOT_PROGRESS (14); + show_boot_progress (14); data = 0; } @@ -160,7 +153,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], initrd_end = 0; } - SHOW_BOOT_PROGRESS (15); + show_boot_progress (15); #ifdef DEBUG printf ("## Transferring control to Linux (at address %08lx) ...\n", diff --git a/lib_mips/mips_linux.c b/lib_mips/mips_linux.c index 952d5a90ee9..556b1804e04 100644 --- a/lib_mips/mips_linux.c +++ b/lib_mips/mips_linux.c @@ -33,13 +33,6 @@ DECLARE_GLOBAL_DATA_PTR; #define LINUX_MAX_ENVS 256 #define LINUX_MAX_ARGS 256 -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - extern image_header_t header; /* from cmd_bootm.c */ extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); @@ -73,7 +66,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], * Check if there is an initrd image */ if (argc >= 3) { - SHOW_BOOT_PROGRESS (9); + show_boot_progress (9); addr = simple_strtoul (argv[2], NULL, 16); @@ -84,7 +77,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], if (ntohl (hdr->ih_magic) != IH_MAGIC) { printf ("Bad Magic Number\n"); - SHOW_BOOT_PROGRESS (-10); + show_boot_progress (-10); do_reset (cmdtp, flag, argc, argv); } @@ -96,11 +89,11 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], if (crc32 (0, (uchar *) data, len) != checksum) { printf ("Bad Header Checksum\n"); - SHOW_BOOT_PROGRESS (-11); + show_boot_progress (-11); do_reset (cmdtp, flag, argc, argv); } - SHOW_BOOT_PROGRESS (10); + show_boot_progress (10); print_image_hdr (hdr); @@ -114,19 +107,19 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], csum = crc32 (0, (uchar *) data, len); if (csum != ntohl (hdr->ih_dcrc)) { printf ("Bad Data CRC\n"); - SHOW_BOOT_PROGRESS (-12); + show_boot_progress (-12); do_reset (cmdtp, flag, argc, argv); } printf ("OK\n"); } - SHOW_BOOT_PROGRESS (11); + show_boot_progress (11); if ((hdr->ih_os != IH_OS_LINUX) || (hdr->ih_arch != IH_CPU_MIPS) || (hdr->ih_type != IH_TYPE_RAMDISK)) { printf ("No Linux MIPS Ramdisk Image\n"); - SHOW_BOOT_PROGRESS (-13); + show_boot_progress (-13); do_reset (cmdtp, flag, argc, argv); } @@ -137,7 +130,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], ulong tail = ntohl (len_ptr[0]) % 4; int i; - SHOW_BOOT_PROGRESS (13); + show_boot_progress (13); /* skip kernel length and terminator */ data = (ulong) (&len_ptr[2]); @@ -156,7 +149,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], /* * no initrd image */ - SHOW_BOOT_PROGRESS (14); + show_boot_progress (14); data = 0; } @@ -175,7 +168,7 @@ void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[], initrd_end = 0; } - SHOW_BOOT_PROGRESS (15); + show_boot_progress (15); #ifdef DEBUG printf ("## Transferring control to Linux (at address %08lx) ...\n", diff --git a/lib_ppc/board.c b/lib_ppc/board.c index f5d18fa9f6b..3b1bfeab4a5 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -1117,9 +1117,7 @@ void board_init_r (gd_t *id, ulong dest_addr) void hang (void) { puts ("### ERROR ### Please RESET the board ###\n"); -#ifdef CONFIG_SHOW_BOOT_PROGRESS show_boot_progress(-30); -#endif for (;;); } diff --git a/net/eth.c b/net/eth.c index 7414d70a033..9fb3a10edb8 100644 --- a/net/eth.c +++ b/net/eth.c @@ -28,14 +28,6 @@ #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) -#if defined(CONFIG_SHOW_BOOT_PROGRESS) -# include -extern void show_ethcfg_progress (int arg); -# define SHOW_BOOT_PROGRESS(arg) show_boot_progress (arg) -#else -# define SHOW_BOOT_PROGRESS(arg) -#endif - #ifdef CFG_GT_6426x extern int gt6426x_eth_initialize(bd_t *bis); #endif @@ -150,7 +142,7 @@ int eth_initialize(bd_t *bis) eth_devices = NULL; eth_current = NULL; - SHOW_BOOT_PROGRESS(64); + show_boot_progress (64); #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) miiphy_init(); #endif @@ -256,12 +248,12 @@ int eth_initialize(bd_t *bis) if (!eth_devices) { puts ("No ethernet found.\n"); - SHOW_BOOT_PROGRESS(-64); + show_boot_progress (-64); } else { struct eth_device *dev = eth_devices; char *ethprime = getenv ("ethprime"); - SHOW_BOOT_PROGRESS(65); + show_boot_progress (65); do { if (eth_number) puts (", "); diff --git a/post/post.c b/post/post.c index 28435cc4af8..4ff75ee4b12 100644 --- a/post/post.c +++ b/post/post.c @@ -129,9 +129,7 @@ void post_output_backlog ( void ) post_log ("PASSED\n"); else { post_log ("FAILED\n"); -#ifdef CONFIG_SHOW_BOOT_PROGRESS - show_boot_progress(-31); -#endif + show_boot_progress (-31); } } } @@ -241,9 +239,7 @@ static int post_run_single (struct post_test *test, } else { if ((*test->test) (flags) != 0) { post_log ("FAILED\n"); -#ifdef CONFIG_SHOW_BOOT_PROGRESS - show_boot_progress(-32); -#endif + show_boot_progress (-32); } else post_log ("PASSED\n"); -- cgit v1.3.1 From cc3023b9f95d7ac959a764471a65001062aecf41 Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Thu, 19 Jul 2007 17:12:28 +0200 Subject: Fix breakage of 8xx boards from recent commit. This patch fixes the negative consequences for 8xx of the recent "ppc4xx: Clean up 440 exceptions handling" commit. Signed-off-by: Rafal Jaworowski --- include/asm-ppc/processor.h | 6 ++++++ include/ppc_asm.tmpl | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 9780fe15c0d..4898dd41cc3 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -628,6 +628,12 @@ #define MAS6 SPRN_MAS6 #define MAS7 SPRN_MAS7 +#if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx) +#define DAR_DEAR DEAR +#else +#define DAR_DEAR DAR +#endif + /* Device Control Registers */ #define DCRN_BEAR 0x090 /* Bus Error Address Register */ diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index 9f4029f2afc..ac8f3176831 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -235,7 +235,7 @@ stw r22,_CTR(r21); \ mfspr r20,XER; \ stw r20,_XER(r21); \ - mfspr r20,DEAR; \ + mfspr r20, DAR_DEAR; \ stw r20,_DAR(r21); \ mfspr r22,reg1; \ mfspr r23,reg2; \ -- cgit v1.3.1 From 1863cfb7b100ba0ee3401799457a01dc058745f8 Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Fri, 27 Jul 2007 14:22:04 +0200 Subject: [PPC] Remove unused MSR_USER definition Signed-off-by: Rafal Jaworowski --- include/asm-ppc/processor.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 4898dd41cc3..71e2e847a46 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -58,7 +58,6 @@ #else #define MSR_KERNEL MSR_ME #endif -#define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE /* Floating Point Status and Control Register (FPSCR) Fields */ -- cgit v1.3.1 From 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6 Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Fri, 27 Jul 2007 14:43:59 +0200 Subject: [ADS5121] Support for the ADS5121 board The following MPC5121e subsystems are supported: - low-level CPU init - NOR Boot Flash (common CFI driver) - DDR SDRAM - FEC - I2C - Watchdog Signed-off-by: Grzegorz Bernacki Signed-off-by: Rafal Jaworowski Signed-off-by: Jan Wrobel --- MAKEALL | 10 +- Makefile | 7 + board/ads5121/Makefile | 50 +++ board/ads5121/ads5121.c | 188 ++++++++++ board/ads5121/config.mk | 23 ++ board/ads5121/u-boot.lds | 122 +++++++ cpu/mpc512x/Makefile | 46 +++ cpu/mpc512x/config.mk | 25 ++ cpu/mpc512x/cpu.c | 127 +++++++ cpu/mpc512x/cpu_init.c | 87 +++++ cpu/mpc512x/fec.c | 801 ++++++++++++++++++++++++++++++++++++++++++ cpu/mpc512x/fec.h | 224 ++++++++++++ cpu/mpc512x/i2c.c | 431 +++++++++++++++++++++++ cpu/mpc512x/interrupts.c | 61 ++++ cpu/mpc512x/serial.c | 197 +++++++++++ cpu/mpc512x/speed.c | 135 +++++++ cpu/mpc512x/start.S | 780 ++++++++++++++++++++++++++++++++++++++++ cpu/mpc512x/traps.c | 205 +++++++++++ include/asm-ppc/e300.h | 1 + include/asm-ppc/global_data.h | 4 + include/asm-ppc/immap_512x.h | 569 ++++++++++++++++++++++++++++++ include/common.h | 8 +- include/configs/ads5121.h | 410 +++++++++++++++++++++ include/mpc512x.h | 398 +++++++++++++++++++++ net/eth.c | 4 + 25 files changed, 4911 insertions(+), 2 deletions(-) create mode 100644 board/ads5121/Makefile create mode 100644 board/ads5121/ads5121.c create mode 100644 board/ads5121/config.mk create mode 100644 board/ads5121/u-boot.lds create mode 100644 cpu/mpc512x/Makefile create mode 100644 cpu/mpc512x/config.mk create mode 100644 cpu/mpc512x/cpu.c create mode 100644 cpu/mpc512x/cpu_init.c create mode 100644 cpu/mpc512x/fec.c create mode 100644 cpu/mpc512x/fec.h create mode 100644 cpu/mpc512x/i2c.c create mode 100644 cpu/mpc512x/interrupts.c create mode 100644 cpu/mpc512x/serial.c create mode 100644 cpu/mpc512x/speed.c create mode 100644 cpu/mpc512x/start.S create mode 100644 cpu/mpc512x/traps.c create mode 100644 include/asm-ppc/immap_512x.h create mode 100644 include/configs/ads5121.h create mode 100644 include/mpc512x.h (limited to 'include') diff --git a/MAKEALL b/MAKEALL index 127faa83a32..2a03b687083 100755 --- a/MAKEALL +++ b/MAKEALL @@ -43,6 +43,14 @@ LIST_5xxx=" \ TQM5200S v38b \ " +######################################################################### +## MPC512x Systems +######################################################################### + +LIST_512x=" \ + ads5121 \ +" + ######################################################################### ## MPC8xx Systems ######################################################################### @@ -365,7 +373,7 @@ do microblaze| \ mips|mips_el| \ nios|nios2| \ - ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \ + ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \ x86|I486) for target in `eval echo '$LIST_'${arg}` do diff --git a/Makefile b/Makefile index 3af9962e678..5b87aad5b9f 100644 --- a/Makefile +++ b/Makefile @@ -641,6 +641,13 @@ motionpro_config: unconfig @$(MKCONFIG) motionpro ppc mpc5xxx motionpro +######################################################################### +## MPC512x Systems +######################################################################### +ads5121_config: unconfig + @$(MKCONFIG) ads5121 ppc mpc512x ads5121 + + ######################################################################### ## MPC8xx Systems ######################################################################### diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile new file mode 100644 index 00000000000..cd8148c43ea --- /dev/null +++ b/board/ads5121/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c new file mode 100644 index 00000000000..0a99a34ac05 --- /dev/null +++ b/board/ads5121/ads5121.c @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include + +/* Clocks in use */ +#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ + CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ + CLOCK_SCCR1_PSCFIFO_EN | \ + CLOCK_SCCR1_DDR_EN | \ + CLOCK_SCCR1_FEC_EN) + +#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_I2C_EN) + +#define CSAW_START(start) ((start) & 0xFFFF0000) +#define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) + +long int fixed_sdram(void); + +int board_early_init_f (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 lpcaw; + + /* + * Initialize Local Window for the CPLD registers access (CS2 selects + * the CPLD chip) + */ + im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) | + CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE); + im->lpc.cs_cfg[2] = CFG_CS2_CFG; + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + lpcaw = im->sysconf.lpcs2aw; + __asm__ __volatile__ ("isync"); + + /* + * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control + * + * Without this the flash identification routine fails, as it needs to issue + * write commands in order to establish the device ID. + */ + *((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1; + + /* + * Enable clocks + */ + im->clk.sccr[0] = SCCR1_CLOCKS_EN; + im->clk.sccr[1] = SCCR2_CLOCKS_EN; + + return 0; +} + +long int initdram (int board_type) +{ + u32 msize = 0; + + puts ("Initializing\n"); + msize = fixed_sdram (); + puts (" DDR RAM: "); + + return msize; +} + +/* + * fixed sdram init -- the board doesn't use memory modules that have serial presence + * detect or similar mechanism for discovery of the DRAM settings + */ +long int fixed_sdram (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = CFG_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2 (msize); + u32 i; + + /* Initialize IO Control */ + im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR; + + /* Initialize DDR Local Window */ + im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000; + im->sysconf.ddrlaw.ar = msize_log2 - 1; + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + i = im->sysconf.ddrlaw.ar; + __asm__ __volatile__ ("isync"); + + /* Enable DDR */ + im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN; + + /* Initialize DDR Priority Manager */ + im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1; + im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2; + im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG; + im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU; + im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU; + im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU; + im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU; + im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU; + im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML; + im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML; + im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML; + im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML; + im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML; + im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU; + im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU; + im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU; + im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU; + im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU; + im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AU; + im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL; + im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL; + im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL; + im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL; + + /* Initialize MDDRC */ + im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG; + im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1; + im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2; + + /* Initialize DDR */ + for (i = 0; i < 10; i++) + im->mddrc.ddr_command = CFG_MICRON_NOP; + + im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CFG_MICRON_EM2; + im->mddrc.ddr_command = CFG_MICRON_EM3; + im->mddrc.ddr_command = CFG_MICRON_EN_DLL; + im->mddrc.ddr_command = CFG_MICRON_RST_DLL; + im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CFG_MICRON_RFSH; + im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT; + im->mddrc.ddr_command = CFG_MICRON_OCD_EXIT; + + for (i = 0; i < 10; i++) + im->mddrc.ddr_command = CFG_MICRON_NOP; + + /* Start MDDRC */ + im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN; + im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN; + + return msize; +} + +int checkboard (void) +{ + ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00); + uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02); + + printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", + brd_rev, cpld_rev); + return 0; +} diff --git a/board/ads5121/config.mk b/board/ads5121/config.mk new file mode 100644 index 00000000000..14998f47506 --- /dev/null +++ b/board/ads5121/config.mk @@ -0,0 +1,23 @@ +# +# (C) Copyright 2007 DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFFF00000 diff --git a/board/ads5121/u-boot.lds b/board/ads5121/u-boot.lds new file mode 100644 index 00000000000..038d8495531 --- /dev/null +++ b/board/ads5121/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2007 DENX Software Engineering. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc512x/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} +ENTRY(_start) diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile new file mode 100644 index 00000000000..2be35b2bc62 --- /dev/null +++ b/cpu/mpc512x/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2007 DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START = start.o +COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/mpc512x/config.mk b/cpu/mpc512x/config.mk new file mode 100644 index 00000000000..8a07c5a3b67 --- /dev/null +++ b/cpu/mpc512x/config.mk @@ -0,0 +1,25 @@ +# +# (C) Copyright 2007 DENX Software Engineering +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi + +PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ + -ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c new file mode 100644 index 00000000000..3be565ad034 --- /dev/null +++ b/cpu/mpc512x/cpu.c @@ -0,0 +1,127 @@ +/* + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code for the MPC512x family. + * + * Derived from the MPC83xx code. + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int checkcpu (void) +{ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + ulong clock = gd->cpu_clk; + u32 pvr = get_pvr (); + u32 spridr = immr->sysconf.spridr; + char buf[32]; + + puts("CPU: "); + + switch (spridr & 0xffff0000) { + case SPR_5121E: + puts ("MPC5121e "); + break; + default: + printf ("Unknown part ID %08x ", spridr & 0xffff0000); + } + printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr)); + + switch (pvr & 0xffff0000) { + case PVR_E300C4: + puts ("e300c4 "); + break; + default: + puts ("unknown "); + } + printf ("at %s MHz, CSB at %3d MHz\n", strmhz(buf, clock), + gd->csb_clk / 1000000); + return 0; +} + + +int +do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + ulong msr; + volatile immap_t *immap = (immap_t *) CFG_IMMR; + + /* Interrupts and MMU off */ + __asm__ __volatile__ ("mfmsr %0":"=r" (msr):); + + msr &= ~( MSR_EE | MSR_IR | MSR_DR); + __asm__ __volatile__ ("mtmsr %0"::"r" (msr)); + + /* + * Enable Reset Control Reg - "RSTE" is the magic word that let us go + */ + immap->reset.rpr = 0x52535445; + + /* Verify Reset Control Reg is enabled */ + while (!((immap->reset.rcer) & RCER_CRE)) + ; + + printf ("Resetting the board.\n"); + udelay(200); + + /* Perform reset */ + immap->reset.rcr = RCR_SWHR; + + /* Unreached... */ + return 1; +} + + +/* + * Get timebase clock frequency (like cpu_clk in Hz) + */ +unsigned long get_tbclk (void) +{ + ulong tbclk; + + tbclk = (gd->bus_clk + 3L) / 4L; + + return tbclk; +} + + +#if defined(CONFIG_WATCHDOG) +void watchdog_reset (void) +{ + int re_enable = disable_interrupts (); + + /* Reset watchdog */ + volatile immap_t *immr = (immap_t *) CFG_IMMR; + immr->wdt.swsrr = 0x556c; + immr->wdt.swsrr = 0xaa39; + + if (re_enable) + enable_interrupts (); +} +#endif diff --git a/cpu/mpc512x/cpu_init.c b/cpu/mpc512x/cpu_init.c new file mode 100644 index 00000000000..566e08b0ddd --- /dev/null +++ b/cpu/mpc512x/cpu_init.c @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Derived from the MPC83xx code. + * + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Set up the memory map, initialize registers, + */ +void cpu_init_f (volatile immap_t * im) +{ + u32 ips_div; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); + + /* system performance tweaking */ + +#ifdef CFG_ACR_PIPE_DEP + /* Arbiter pipeline depth */ + im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | + (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT); +#endif + +#ifdef CFG_ACR_RPTCNT + /* Arbiter repeat count */ + im->arbiter.acr = ((im->arbiter.acr & ~(ACR_RPTCNT)) | + (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT)); +#endif + + /* RSR - Reset Status Register - clear all status */ + gd->reset_status = im->reset.rsr; + im->reset.rsr = ~(RSR_RES); + + /* + * RMR - Reset Mode Register - enable checkstop reset + */ + im->reset.rmr = (RMR_CSRE & (1 << RMR_CSRE_SHIFT)); + + /* Set IPS-CSB divider: IPS = 1/2 CSB */ + ips_div = im->clk.scfr[0]; + ips_div &= ~(SCFR1_IPS_DIV_MASK); + ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT; + im->clk.scfr[0] = ips_div; + + /* + * Enable Time Base/Decrementer + * + * NOTICE: TB needs to be enabled as early as possible in order to + * have udelay() working; if not enabled, usually leads to a hang, like + * during FLASH chip identification etc. + */ + im->sysconf.spcr |= SPCR_TBEN; +} + +int cpu_init_r (void) +{ + return 0; +} diff --git a/cpu/mpc512x/fec.c b/cpu/mpc512x/fec.c new file mode 100644 index 00000000000..f1b7a2563ed --- /dev/null +++ b/cpu/mpc512x/fec.c @@ -0,0 +1,801 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Derived from the MPC8xx FEC driver. + * Adapted for MPC512x by Grzegorz Bernacki + */ + +#include +#include +#include +#include +#include +#include "fec.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define DEBUG 0 + +#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \ + defined(CONFIG_MPC512x_FEC) + +#if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)) +#error "CONFIG_MII has to be defined!" +#endif + +#if (DEBUG & 0x40) +static uint32 local_crc32(char *string, unsigned int crc_value, int len); +#endif + +int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal); +int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data); +int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis); + +/********************************************************************/ +#if (DEBUG & 0x2) +static void mpc512x_fec_phydump (char *devname) +{ + uint16 phyStatus, i; + uint8 phyAddr = CONFIG_PHY_ADDR; + uint8 reg_mask[] = { + /* regs to print: 0...8, 21,27,31 */ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, + }; + + for (i = 0; i < 32; i++) { + if (reg_mask[i]) { + miiphy_read (devname, phyAddr, i, &phyStatus); + printf ("Mii reg %d: 0x%04x\n", i, phyStatus); + } + } +} +#endif + +/********************************************************************/ +static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec) +{ + int ix; + + /* + * Receive BDs init + */ + for (ix = 0; ix < FEC_RBD_NUM; ix++) { + fec->bdBase->rbd[ix].dataPointer = (uint32)&fec->bdBase->recv_frames[ix]; + fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY; + fec->bdBase->rbd[ix].dataLength = 0; + } + + /* + * have the last RBD to close the ring + */ + fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP; + fec->rbdIndex = 0; + + /* + * Trasmit BDs init + */ + for (ix = 0; ix < FEC_TBD_NUM; ix++) { + fec->bdBase->tbd[ix].status = 0; + } + + /* + * Have the last TBD to close the ring + */ + fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP; + + /* + * Initialize some indices + */ + fec->tbdIndex = 0; + fec->usedTbdIndex = 0; + fec->cleanTbdNum = FEC_TBD_NUM; + + return 0; +} + +/********************************************************************/ +static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd) +{ + /* + * Reset buffer descriptor as empty + */ + if ((fec->rbdIndex) == (FEC_RBD_NUM - 1)) + pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY); + else + pRbd->status = FEC_RBD_EMPTY; + + pRbd->dataLength = 0; + + /* + * Increment BD count + */ + fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM; + + /* + * Now, we have an empty RxBD, notify FEC + */ + fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */ +} + +/********************************************************************/ +static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec) +{ + volatile FEC_TBD *pUsedTbd; + +#if (DEBUG & 0x1) + printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n", + fec->cleanTbdNum, fec->usedTbdIndex); +#endif + + /* + * process all the consumed TBDs + */ + while (fec->cleanTbdNum < FEC_TBD_NUM) { + pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex]; + if (pUsedTbd->status & FEC_TBD_READY) { +#if (DEBUG & 0x20) + printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex); +#endif + return; + } + + /* + * clean this buffer descriptor + */ + if (fec->usedTbdIndex == (FEC_TBD_NUM - 1)) + pUsedTbd->status = FEC_TBD_WRAP; + else + pUsedTbd->status = 0; + + /* + * update some indeces for a correct handling of the TBD ring + */ + fec->cleanTbdNum++; + fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM; + } +} + +/********************************************************************/ +static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac) +{ + uint8 currByte; /* byte for which to compute the CRC */ + int byte; /* loop - counter */ + int bit; /* loop - counter */ + uint32 crc = 0xffffffff; /* initial value */ + + /* + * The algorithm used is the following: + * we loop on each of the six bytes of the provided address, + * and we compute the CRC by left-shifting the previous + * value by one position, so that each bit in the current + * byte of the address may contribute the calculation. If + * the latter and the MSB in the CRC are different, then + * the CRC value so computed is also ex-ored with the + * "polynomium generator". The current byte of the address + * is also shifted right by one bit at each iteration. + * This is because the CRC generatore in hardware is implemented + * as a shift-register with as many ex-ores as the radixes + * in the polynomium. This suggests that we represent the + * polynomiumm itself as a 32-bit constant. + */ + for (byte = 0; byte < 6; byte++) { + currByte = mac[byte]; + for (bit = 0; bit < 8; bit++) { + if ((currByte & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + currByte >>= 1; + } + } + + crc = crc >> 26; + + /* + * Set individual hash table register + */ + if (crc >= 32) { + fec->eth->iaddr1 = (1 << (crc - 32)); + fec->eth->iaddr2 = 0; + } else { + fec->eth->iaddr1 = 0; + fec->eth->iaddr2 = (1 << crc); + } + + /* + * Set physical address + */ + fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; + fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808; +} + +/********************************************************************/ +static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) +{ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_init... Begin\n"); +#endif + + /* Set interrupt mask register */ + fec->eth->imask = 0x00000000; + + /* Clear FEC-Lite interrupt event register(IEVENT) */ + fec->eth->ievent = 0xffffffff; + + /* Set transmit fifo watermark register(X_WMRK), default = 64 */ + fec->eth->x_wmrk = 0x0; + + /* Set Opcode/Pause Duration Register */ + fec->eth->op_pause = 0x00010020; + + /* Frame length=1518; MII mode */ + fec->eth->r_cntrl = 0x05ee000c; + + /* Half-duplex, heartbeat disabled */ + fec->eth->x_cntrl = 0x00000000; + + /* Enable MIB counters */ + fec->eth->mib_control = 0x0; + + /* Setup recv fifo start and buff size */ + fec->eth->r_fstart = 0x500; + fec->eth->r_buff_size = 0x5e0; + + /* Setup BD base addresses */ + fec->eth->r_des_start = (uint32)fec->bdBase->rbd; + fec->eth->x_des_start = (uint32)fec->bdBase->tbd; + + /* DMA Control */ + fec->eth->dma_control = 0xc0000000; + + /* Enable FEC */ + fec->eth->ecntrl |= 0x00000006; + + /* Initilize addresses and status words of BDs */ + mpc512x_fec_bd_init (fec); + + /* Descriptor polling active */ + fec->eth->r_des_active = 0x01000000; + +#if (DEBUG & 0x1) + printf("mpc512x_fec_init... Done \n"); +#endif + return 1; +} + +/********************************************************************/ +int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis) +{ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */ + int timeout = 1; + uint16 phyStatus; + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_init_phy... Begin\n"); +#endif + + /* + * Clear FEC-Lite interrupt event register(IEVENT) + */ + fec->eth->ievent = 0xffffffff; + + /* + * Set interrupt mask register + */ + fec->eth->imask = 0x00000000; + + if (fec->xcv_type != SEVENWIRE) { + /* + * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock + * and do not drop the Preamble. + */ + fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1; + + /* + * Reset PHY, then delay 300ns + */ + miiphy_write (dev->name, phyAddr, 0x0, 0x8000); + udelay (1000); + + if (fec->xcv_type == MII10) { + /* + * Force 10Base-T, FDX operation + */ +#if (DEBUG & 0x2) + printf ("Forcing 10 Mbps ethernet link... "); +#endif + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); + + miiphy_write (dev->name, phyAddr, 0x0, 0x0180); + + timeout = 20; + do { /* wait for link status to go down */ + udelay (10000); + if ((timeout--) == 0) { +#if (DEBUG & 0x2) + printf ("hmmm, should not have waited..."); +#endif + break; + } + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); +#if (DEBUG & 0x2) + printf ("="); +#endif + } while ((phyStatus & 0x0004)); /* !link up */ + + timeout = 1000; + do { /* wait for link status to come back up */ + udelay (10000); + if ((timeout--) == 0) { + printf ("failed. Link is down.\n"); + break; + } + miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); +#if (DEBUG & 0x2) + printf ("+"); +#endif + } while (!(phyStatus & 0x0004)); /* !link up */ + +#if (DEBUG & 0x2) + printf ("done.\n"); +#endif + } else { /* MII100 */ + /* + * Set the auto-negotiation advertisement register bits + */ + miiphy_write (dev->name, phyAddr, 0x4, 0x01e1); + + /* + * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation + */ + miiphy_write (dev->name, phyAddr, 0x0, 0x1200); + + /* + * Wait for AN completion + */ + timeout = 50000; + do { + udelay (1000); + + if ((timeout--) == 0) { +#if (DEBUG & 0x2) + printf ("PHY auto neg 0 failed...\n"); +#endif + return -1; + } + + if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) { +#if (DEBUG & 0x2) + printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus); +#endif + return -1; + } + } while (!(phyStatus & 0x0004)); + +#if (DEBUG & 0x2) + printf ("PHY auto neg complete! \n"); +#endif + } + } + +#if (DEBUG & 0x2) + if (fec->xcv_type != SEVENWIRE) + mpc512x_fec_phydump (dev->name); +#endif + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_init_phy... Done \n"); +#endif + return 1; +} + +/********************************************************************/ +static void mpc512x_fec_halt (struct eth_device *dev) +{ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + int counter = 0xffff; + +#if (DEBUG & 0x2) + if (fec->xcv_type != SEVENWIRE) + mpc512x_fec_phydump (dev->name); +#endif + + /* + * mask FEC chip interrupts + */ + fec->eth->imask = 0; + + /* + * issue graceful stop command to the FEC transmitter if necessary + */ + fec->eth->x_cntrl |= 0x00000001; + + /* + * wait for graceful stop to register + */ + while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ; + + /* + * Disable the Ethernet Controller + */ + fec->eth->ecntrl &= 0xfffffffd; + + /* + * Issue a reset command to the FEC chip + */ + fec->eth->ecntrl |= 0x1; + + /* + * wait at least 16 clock cycles + */ + udelay (10); +#if (DEBUG & 0x3) + printf ("Ethernet task stopped\n"); +#endif +} + +/********************************************************************/ + +static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data, + int data_length) +{ + /* + * This routine transmits one frame. This routine only accepts + * 6-byte Ethernet addresses. + */ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + volatile FEC_TBD *pTbd; + +#if (DEBUG & 0x20) + printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status); +#endif + + /* + * Clear Tx BD ring at first + */ + mpc512x_fec_tbd_scrub (fec); + + /* + * Check for valid length of data. + */ + if ((data_length > 1500) || (data_length <= 0)) { + return -1; + } + + /* + * Check the number of vacant TxBDs. + */ + if (fec->cleanTbdNum < 1) { +#if (DEBUG & 0x20) + printf ("No available TxBDs ...\n"); +#endif + return -1; + } + + /* + * Get the first TxBD to send the mac header + */ + pTbd = &fec->bdBase->tbd[fec->tbdIndex]; + pTbd->dataLength = data_length; + pTbd->dataPointer = (uint32)eth_data; + pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; + fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; + + /* Activate transmit Buffer Descriptor polling */ + fec->eth->x_des_active = 0x01000000; /* Descriptor polling active */ + +#if (DEBUG & 0x8) + printf ( "+" ); +#endif + + fec->cleanTbdNum -= 1; + + /* + * wait until frame is sent . + */ + while (pTbd->status & FEC_TBD_READY) { + udelay (10); +#if (DEBUG & 0x8) + printf ("TDB status = %04x\n", pTbd->status); +#endif + } + + return 0; +} + + +/********************************************************************/ +static int mpc512x_fec_recv (struct eth_device *dev) +{ + /* + * This command pulls one frame from the card + */ + mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv; + volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex]; + unsigned long ievent; + int frame_length, len = 0; + uchar buff[FEC_MAX_PKT_SIZE]; + +#if (DEBUG & 0x1) + printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex); +#endif +#if (DEBUG & 0x8) + printf( "-" ); +#endif + + /* + * Check if any critical events have happened + */ + ievent = fec->eth->ievent; + fec->eth->ievent = ievent; + if (ievent & 0x20060000) { + /* BABT, Rx/Tx FIFO errors */ + mpc512x_fec_halt (dev); + mpc512x_fec_init (dev, NULL); + return 0; + } + if (ievent & 0x80000000) { + /* Heartbeat error */ + fec->eth->x_cntrl |= 0x00000001; + } + if (ievent & 0x10000000) { + /* Graceful stop complete */ + if (fec->eth->x_cntrl & 0x00000001) { + mpc512x_fec_halt (dev); + fec->eth->x_cntrl &= ~0x00000001; + mpc512x_fec_init (dev, NULL); + } + } + + if (!(pRbd->status & FEC_RBD_EMPTY)) { + if ((pRbd->status & FEC_RBD_LAST) && + !(pRbd->status & FEC_RBD_ERR) && + ((pRbd->dataLength - 4) > 14)) { + + /* + * Get buffer size + */ + frame_length = pRbd->dataLength - 4; + +#if (DEBUG & 0x20) + { + int i; + printf ("recv data hdr:"); + for (i = 0; i < 14; i++) + printf ("%x ", *((uint8*)pRbd->dataPointer + i)); + printf("\n"); + } +#endif + + /* + * Fill the buffer and pass it to upper layers + */ + memcpy (buff, (void*)pRbd->dataPointer, frame_length); + NetReceive ((uchar*)buff, frame_length); + len = frame_length; + } + + /* + * Reset buffer descriptor as empty + */ + mpc512x_fec_rbd_clean (fec, pRbd); + } + + /* Try to fill Buffer Descriptors */ + fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */ + return len; +} + +/********************************************************************/ +int mpc512x_fec_initialize (bd_t * bis) +{ + + immap_t *im = (immap_t*) CFG_IMMR; + mpc512x_fec_priv *fec; + struct eth_device *dev; + int i; + char *tmp, *end, env_enetaddr[6]; + uint32 *reg; + void * bd; + + fec = (mpc512x_fec_priv *) malloc (sizeof(*fec)); + dev = (struct eth_device *) malloc (sizeof(*dev)); + memset (dev, 0, sizeof *dev); + + fec->eth = (ethernet_regs *) MPC512X_FEC; + +# ifndef CONFIG_FEC_10MBIT + fec->xcv_type = MII100; +# else + fec->xcv_type = MII10; +# endif + dev->priv = (void *)fec; + dev->iobase = MPC512X_FEC; + dev->init = mpc512x_fec_init; + dev->halt = mpc512x_fec_halt; + dev->send = mpc512x_fec_send; + dev->recv = mpc512x_fec_recv; + + sprintf (dev->name, "FEC ETHERNET"); + eth_register (dev); + +#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) + miiphy_register (dev->name, + fec512x_miiphy_read, fec512x_miiphy_write); +#endif + + /* + * Initialize I\O pins + */ + reg = (uint32 *) &(im->io_ctrl.regs[PSC0_0_IDX]); + + for (i = 0; i < 15; i++) + reg[i] = IOCTRL_MUX_FEC | 0x00000001; + + im->io_ctrl.regs[SPDIF_TXCLOCK_IDX] = IOCTRL_MUX_FEC | 0x00000001; + im->io_ctrl.regs[SPDIF_TX_IDX] = IOCTRL_MUX_FEC | 0x00000001; + im->io_ctrl.regs[SPDIF_RX_IDX] = IOCTRL_MUX_FEC | 0x00000001; + + /* Clean up space FEC's MIB and FIFO RAM ...*/ + memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400); + + /* + * Malloc space for BDs (must be quad word-aligned) + * this pointer is lost, so cannot be freed + */ + bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f); + fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0); + memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f); + + /* + * Set interrupt mask register + */ + fec->eth->imask = 0x00000000; + + /* + * Clear FEC-Lite interrupt event register(IEVENT) + */ + fec->eth->ievent = 0xffffffff; + + /* + * Try to set the mac address now. The fec mac address is + * a garbage after reset. When not using fec for booting + * the Linux fec driver will try to work with this garbage. + */ + tmp = getenv ("ethaddr"); + if (tmp) { + for (i=0; i<6; i++) { + env_enetaddr[i] = tmp ? simple_strtoul (tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + mpc512x_fec_set_hwaddr (fec, env_enetaddr); + fec->eth->gaddr1 = 0x00000000; + fec->eth->gaddr2 = 0x00000000; + } + + mpc512x_fec_init_phy (dev, bis); + + return 1; +} + +/* MII-interface related functions */ +/********************************************************************/ +int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal) +{ + ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC; + uint32 reg; /* convenient holder for the PHY register */ + uint32 phy; /* convenient holder for the PHY */ + int timeout = 0xffff; + + /* + * reading from any PHY's register is done by properly + * programming the FEC's MII data register. + */ + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg); + + /* + * wait for the related interrupt + */ + while ((timeout--) && (!(eth->ievent & 0x00800000))) ; + + if (timeout == 0) { +#if (DEBUG & 0x2) + printf ("Read MDIO failed...\n"); +#endif + return -1; + } + + /* + * clear mii interrupt bit + */ + eth->ievent = 0x00800000; + + /* + * it's now safe to read the PHY's register + */ + *retVal = (uint16) eth->mii_data; + + return 0; +} + +/********************************************************************/ +int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 data) +{ + ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC; + uint32 reg; /* convenient holder for the PHY register */ + uint32 phy; /* convenient holder for the PHY */ + int timeout = 0xffff; + + reg = regAddr << FEC_MII_DATA_RA_SHIFT; + phy = phyAddr << FEC_MII_DATA_PA_SHIFT; + + eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | + FEC_MII_DATA_TA | phy | reg | data); + + /* + * wait for the MII interrupt + */ + while ((timeout--) && (!(eth->ievent & 0x00800000))) ; + + if (timeout == 0) { +#if (DEBUG & 0x2) + printf ("Write MDIO failed...\n"); +#endif + return -1; + } + + /* + * clear MII interrupt bit + */ + eth->ievent = 0x00800000; + + return 0; +} + +#if (DEBUG & 0x40) +static uint32 local_crc32 (char *string, unsigned int crc_value, int len) +{ + int i; + char c; + unsigned int crc, count; + + /* + * crc32 algorithm + */ + /* + * crc = 0xffffffff; * The initialized value should be 0xffffffff + */ + crc = crc_value; + + for (i = len; --i >= 0;) { + c = *string++; + for (count = 0; count < 8; count++) { + if ((c & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + c >>= 1; + } + } + + /* + * In big endian system, do byte swaping for crc value + */ + /**/ return crc; +} +#endif /* DEBUG */ + +#endif /* CONFIG_MPC512x_FEC */ diff --git a/cpu/mpc512x/fec.h b/cpu/mpc512x/fec.h new file mode 100644 index 00000000000..71459197a51 --- /dev/null +++ b/cpu/mpc512x/fec.h @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2003 - 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Derived from the MPC8xx driver's header file. + */ + +#ifndef __MPC512X_FEC_H +#define __MPC512X_FEC_H + +#include +#include + +typedef unsigned long uint32; +typedef unsigned short uint16; +typedef unsigned char uint8; + +typedef struct ethernet_register_set { + +/* [10:2]addr = 00 */ + +/* Control and status Registers (offset 000-1FF) */ + + volatile uint32 fec_id; /* MBAR_ETH + 0x000 */ + volatile uint32 ievent; /* MBAR_ETH + 0x004 */ + volatile uint32 imask; /* MBAR_ETH + 0x008 */ + + volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */ + volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */ + volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */ + + volatile uint32 RES1[3]; /* MBAR_ETH + 0x018-020 */ + volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */ + + volatile uint32 RES2[6]; /* MBAR_ETH + 0x028-03C */ + volatile uint32 mii_data; /* MBAR_ETH + 0x040 */ + volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */ + + volatile uint32 RES3[7]; /* MBAR_ETH + 0x048-060 */ + volatile uint32 mib_control; /* MBAR_ETH + 0x064 */ + + volatile uint32 RES4[7]; /* MBAR_ETH + 0x068-80 */ + volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */ + volatile uint32 r_hash; /* MBAR_ETH + 0x088 */ + + volatile uint32 RES5[14]; /* MBAR_ETH + 0x08c-0C0 */ + volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */ + + volatile uint32 RES6[7]; /* MBAR_ETH + 0x0C8-0E0 */ + volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */ + volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */ + volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */ + + volatile uint32 RES7[10]; /* MBAR_ETH + 0x0F0-114 */ + volatile uint32 iaddr1; /* MBAR_ETH + 0x118 */ + volatile uint32 iaddr2; /* MBAR_ETH + 0x11C */ + volatile uint32 gaddr1; /* MBAR_ETH + 0x120 */ + volatile uint32 gaddr2; /* MBAR_ETH + 0x124 */ + + volatile uint32 RES8[6]; /* MBAR_ETH + 0x128-13C */ + volatile uint32 fifo_id; /* MBAR_ETH + 0x140 */ + volatile uint32 x_wmrk; /* MBAR_ETH + 0x144 */ + volatile uint32 RES9[1]; /* MBAR_ETH + 0x148 */ + volatile uint32 r_bound; /* MBAR_ETH + 0x14C */ + volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */ + + volatile uint32 RES10[11]; /* MBAR_ETH + 0x154-17C */ + volatile uint32 r_des_start; /* MBAR_ETH + 0x180 */ + volatile uint32 x_des_start; /* MBAR_ETH + 0x184 */ + volatile uint32 r_buff_size; /* MBAR_ETH + 0x188 */ + volatile uint32 RES11[26]; /* MBAR_ETH + 0x18C-1F0 */ + volatile uint32 dma_control; /* MBAR_ETH + 0x1F4 */ + volatile uint32 RES12[2]; /* MBAR_ETH + 0x1F8-1FC */ + +/* MIB COUNTERS (Offset 200-2FF) */ + + volatile uint32 rmon_t_drop; /* MBAR_ETH + 0x200 */ + volatile uint32 rmon_t_packets; /* MBAR_ETH + 0x204 */ + volatile uint32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ + volatile uint32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ + volatile uint32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */ + volatile uint32 rmon_t_undersize; /* MBAR_ETH + 0x214 */ + volatile uint32 rmon_t_oversize; /* MBAR_ETH + 0x218 */ + volatile uint32 rmon_t_frag; /* MBAR_ETH + 0x21C */ + volatile uint32 rmon_t_jab; /* MBAR_ETH + 0x220 */ + volatile uint32 rmon_t_col; /* MBAR_ETH + 0x224 */ + volatile uint32 rmon_t_p64; /* MBAR_ETH + 0x228 */ + volatile uint32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */ + volatile uint32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */ + volatile uint32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */ + volatile uint32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ + volatile uint32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */ + volatile uint32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ + volatile uint32 rmon_t_octets; /* MBAR_ETH + 0x244 */ + volatile uint32 ieee_t_drop; /* MBAR_ETH + 0x248 */ + volatile uint32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ + volatile uint32 ieee_t_1col; /* MBAR_ETH + 0x250 */ + volatile uint32 ieee_t_mcol; /* MBAR_ETH + 0x254 */ + volatile uint32 ieee_t_def; /* MBAR_ETH + 0x258 */ + volatile uint32 ieee_t_lcol; /* MBAR_ETH + 0x25C */ + volatile uint32 ieee_t_excol; /* MBAR_ETH + 0x260 */ + volatile uint32 ieee_t_macerr; /* MBAR_ETH + 0x264 */ + volatile uint32 ieee_t_cserr; /* MBAR_ETH + 0x268 */ + volatile uint32 ieee_t_sqe; /* MBAR_ETH + 0x26C */ + volatile uint32 t_fdxfc; /* MBAR_ETH + 0x270 */ + volatile uint32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ + + volatile uint32 RES13[2]; /* MBAR_ETH + 0x278-27C */ + volatile uint32 rmon_r_drop; /* MBAR_ETH + 0x280 */ + volatile uint32 rmon_r_packets; /* MBAR_ETH + 0x284 */ + volatile uint32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ + volatile uint32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ + volatile uint32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */ + volatile uint32 rmon_r_undersize; /* MBAR_ETH + 0x294 */ + volatile uint32 rmon_r_oversize; /* MBAR_ETH + 0x298 */ + volatile uint32 rmon_r_frag; /* MBAR_ETH + 0x29C */ + volatile uint32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */ + + volatile uint32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ + + volatile uint32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */ + volatile uint32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ + volatile uint32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ + volatile uint32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ + volatile uint32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ + volatile uint32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */ + volatile uint32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ + volatile uint32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */ + volatile uint32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */ + volatile uint32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ + volatile uint32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */ + volatile uint32 ieee_r_align; /* MBAR_ETH + 0x2D4 */ + volatile uint32 r_macerr; /* MBAR_ETH + 0x2D8 */ + volatile uint32 r_fdxfc; /* MBAR_ETH + 0x2DC */ + volatile uint32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ + + volatile uint32 RES14[6]; /* MBAR_ETH + 0x2E4-2FC */ + + volatile uint32 RES15[64]; /* MBAR_ETH + 0x300-3FF */ +} ethernet_regs; + +/* Receive & Transmit Buffer Descriptor definitions */ +typedef struct BufferDescriptor { + uint16 status; + uint16 dataLength; + uint32 dataPointer; +} FEC_RBD; + +typedef struct { + uint16 status; + uint16 dataLength; + uint32 dataPointer; +} FEC_TBD; + +/* private structure */ +typedef enum { + SEVENWIRE, /* 7-wire */ + MII10, /* MII 10Mbps */ + MII100 /* MII 100Mbps */ +} xceiver_type; + +/* BD Numer definitions */ +#define FEC_TBD_NUM 48 /* The user can adjust this value */ +#define FEC_RBD_NUM 32 /* The user can adjust this value */ + +/* packet size limit */ +#define FEC_MAX_PKT_SIZE 1536 + +typedef struct { + uint8 frame[FEC_MAX_PKT_SIZE]; +} mpc512x_frame; + +typedef struct { + FEC_RBD rbd[FEC_RBD_NUM]; /* RBD ring */ + FEC_TBD tbd[FEC_TBD_NUM]; /* TBD ring */ + mpc512x_frame recv_frames[FEC_RBD_NUM]; /* receive buff */ +} mpc512x_buff_descs; + +typedef struct { + ethernet_regs *eth; + xceiver_type xcv_type; /* transceiver type */ + mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */ + uint16 rbdIndex; /* next receive BD to read */ + uint16 tbdIndex; /* next transmit BD to send */ + uint16 usedTbdIndex; /* next transmit BD to clean */ + uint16 cleanTbdNum; /* the number of available transmit BDs */ +} mpc512x_fec_priv; + +/* RBD bits definitions */ +#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */ +#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */ +#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */ +#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */ +#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */ +#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */ +#define FEC_RBD_LG 0x0020 /* Frame length violation */ +#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */ +#define FEC_RBD_SH 0x0008 /* Short frame */ +#define FEC_RBD_CR 0x0004 /* CRC error */ +#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */ +#define FEC_RBD_TR 0x0001 /* Frame is truncated */ +#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ + FEC_RBD_OV | FEC_RBD_TR) + +/* TBD bits definitions */ +#define FEC_TBD_READY 0x8000 /* Buffer is ready */ +#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */ +#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */ +#define FEC_TBD_TC 0x0400 /* Transmit the CRC */ +#define FEC_TBD_ABC 0x0200 /* Append bad CRC */ + +/* MII-related definitios */ +#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ +#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ +#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ +#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ +#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ +#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ +#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ + +#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ +#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ + +#endif /* __MPC512X_FEC_H */ diff --git a/cpu/mpc512x/i2c.c b/cpu/mpc512x/i2c.c new file mode 100644 index 00000000000..00e28d6404d --- /dev/null +++ b/cpu/mpc512x/i2c.c @@ -0,0 +1,431 @@ +/* + * (C) Copyright 2003 - 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based on the MPC5xxx code. + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_HARD_I2C + +#include +#include + +#define immr ((immap_t *)CFG_IMMR) + +/* by default set I2C bus 0 active */ +static unsigned int bus_num = 0; + +#define I2C_TIMEOUT 100 +#define I2C_RETRIES 3 + +struct mpc512x_i2c_tap { + int scl2tap; + int tap2tap; +}; + +static int mpc_reg_in(volatile u32 *reg); +static void mpc_reg_out(volatile u32 *reg, int val, int mask); +static int wait_for_bb(void); +static int wait_for_pin(int *status); +static int do_address(uchar chip, char rdwr_flag); +static int send_bytes(uchar chip, char *buf, int len); +static int receive_bytes(uchar chip, char *buf, int len); +static int mpc_get_fdr(int); + +static int mpc_reg_in (volatile u32 *reg) +{ + int ret = *reg >> 24; + __asm__ __volatile__ ("eieio"); + return ret; +} + +static void mpc_reg_out (volatile u32 *reg, int val, int mask) +{ + int tmp; + + if (!mask) { + *reg = val << 24; + } else { + tmp = mpc_reg_in (reg); + *reg = ((tmp & ~mask) | (val & mask)) << 24; + } + __asm__ __volatile__ ("eieio"); + + return; +} + +static int wait_for_bb (void) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int timeout = I2C_TIMEOUT; + int status; + + status = mpc_reg_in (®s->msr); + + while (timeout-- && (status & I2C_BB)) { + volatile int temp; + mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); + temp = mpc_reg_in (®s->mdr); + mpc_reg_out (®s->mcr, 0, I2C_STA); + mpc_reg_out (®s->mcr, 0, 0); + mpc_reg_out (®s->mcr, I2C_EN, 0); + + udelay (1000); + status = mpc_reg_in (®s->msr); + } + + return (status & I2C_BB); +} + +static int wait_for_pin (int *status) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int timeout = I2C_TIMEOUT; + + *status = mpc_reg_in (®s->msr); + + while (timeout-- && !(*status & I2C_IF)) { + udelay (1000); + *status = mpc_reg_in (®s->msr); + } + + if (!(*status & I2C_IF)) { + return -1; + } + + mpc_reg_out (®s->msr, 0, I2C_IF); + + return 0; +} + +static int do_address (uchar chip, char rdwr_flag) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int status; + + chip <<= 1; + + if (rdwr_flag) { + chip |= 1; + } + + mpc_reg_out (®s->mcr, I2C_TX, I2C_TX); + mpc_reg_out (®s->mdr, chip, 0); + + if (wait_for_pin (&status)) { + return -2; + } + + if (status & I2C_RXAK) { + return -3; + } + + return 0; +} + +static int send_bytes (uchar chip, char *buf, int len) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int wrcount; + int status; + + for (wrcount = 0; wrcount < len; ++wrcount) { + + mpc_reg_out (®s->mdr, buf[wrcount], 0); + + if (wait_for_pin (&status)) { + break; + } + + if (status & I2C_RXAK) { + break; + } + + } + + return !(wrcount == len); +} + +static int receive_bytes (uchar chip, char *buf, int len) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int dummy = 1; + int rdcount = 0; + int status; + int i; + + mpc_reg_out (®s->mcr, 0, I2C_TX); + + for (i = 0; i < len; ++i) { + buf[rdcount] = mpc_reg_in (®s->mdr); + + if (dummy) { + dummy = 0; + } else { + rdcount++; + } + + if (wait_for_pin (&status)) { + return -4; + } + } + + mpc_reg_out (®s->mcr, I2C_TXAK, I2C_TXAK); + buf[rdcount++] = mpc_reg_in (®s->mdr); + + if (wait_for_pin (&status)) { + return -5; + } + + mpc_reg_out (®s->mcr, 0, I2C_TXAK); + + return 0; +} + +/**************** I2C API ****************/ + +void i2c_init (int speed, int saddr) +{ + int i; + for(i = 0; i < I2C_BUS_CNT; i++){ + i2c512x_dev_t *regs = &immr->i2c.dev[i]; + mpc_reg_out (®s->mcr, 0, 0); + + /* Set clock */ + mpc_reg_out (®s->mfdr, mpc_get_fdr (speed), 0); + mpc_reg_out (®s->madr, saddr << 1, 0); + + /* Enable module */ + mpc_reg_out (®s->mcr, I2C_EN, I2C_INIT_MASK); + mpc_reg_out (®s->msr, 0, I2C_IF); + } + + /* Disable interrupts */ + immr->i2c.icr = 0; + /* Turn off filters */ + immr->i2c.mifr = 0; + return; +} + +static int mpc_get_fdr (int speed) +{ + static int fdr = -1; + + if (fdr == -1) { + ulong best_speed = 0; + ulong divider; + ulong ipb, scl; + ulong bestmatch = 0xffffffffUL; + int best_i = 0, best_j = 0, i, j; + int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8}; + struct mpc512x_i2c_tap scltap[] = { + {4, 1}, + {4, 2}, + {6, 4}, + {6, 8}, + {14, 16}, + {30, 32}, + {62, 64}, + {126, 128} + }; + + ipb = gd->ipb_clk; + for (i = 7; i >= 0; i--) { + for (j = 7; j >= 0; j--) { + scl = 2 * (scltap[j].scl2tap + + (SCL_Tap[i] - 1) * scltap[j].tap2tap + + 2); + if (ipb <= speed*scl) { + if ((speed*scl - ipb) < bestmatch) { + bestmatch = speed*scl - ipb; + best_i = i; + best_j = j; + best_speed = ipb/scl; + } + } + } + } + divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2); + if (gd->flags & GD_FLG_RELOC) { + fdr = divider; + } else { + debug("%ld kHz, \n", best_speed / 1000); + return divider; + } + } + + return fdr; +} + +int i2c_probe (uchar chip) +{ + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int i; + + for (i = 0; i < I2C_RETRIES; i++) { + mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); + + if (! do_address (chip, 0)) { + mpc_reg_out (®s->mcr, 0, I2C_STA); + udelay (500); + break; + } + + mpc_reg_out (®s->mcr, 0, I2C_STA); + udelay (500); + } + + return (i == I2C_RETRIES); +} + +int i2c_read (uchar chip, uint addr, int alen, uchar *buf, int len) +{ + char xaddr[4]; + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int ret = -1; + + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + + if (wait_for_bb ()) { + printf ("i2c_read: bus is busy\n"); + goto Done; + } + + mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); + if (do_address (chip, 0)) { + printf ("i2c_read: failed to address chip\n"); + goto Done; + } + + if (send_bytes (chip, &xaddr[4-alen], alen)) { + printf ("i2c_read: send_bytes failed\n"); + goto Done; + } + + mpc_reg_out (®s->mcr, I2C_RSTA, I2C_RSTA); + if (do_address (chip, 1)) { + printf ("i2c_read: failed to address chip\n"); + goto Done; + } + + if (receive_bytes (chip, (char *)buf, len)) { + printf ("i2c_read: receive_bytes failed\n"); + goto Done; + } + + ret = 0; +Done: + mpc_reg_out (®s->mcr, 0, I2C_STA); + return ret; +} + +int i2c_write (uchar chip, uint addr, int alen, uchar *buf, int len) +{ + char xaddr[4]; + i2c512x_dev_t *regs = &immr->i2c.dev[bus_num]; + int ret = -1; + + xaddr[0] = (addr >> 24) & 0xFF; + xaddr[1] = (addr >> 16) & 0xFF; + xaddr[2] = (addr >> 8) & 0xFF; + xaddr[3] = addr & 0xFF; + + if (wait_for_bb ()) { + printf ("i2c_write: bus is busy\n"); + goto Done; + } + + mpc_reg_out (®s->mcr, I2C_STA, I2C_STA); + if (do_address (chip, 0)) { + printf ("i2c_write: failed to address chip\n"); + goto Done; + } + + if (send_bytes (chip, &xaddr[4-alen], alen)) { + printf ("i2c_write: send_bytes failed\n"); + goto Done; + } + + if (send_bytes (chip, (char *)buf, len)) { + printf ("i2c_write: send_bytes failed\n"); + goto Done; + } + + ret = 0; +Done: + mpc_reg_out (®s->mcr, 0, I2C_STA); + return ret; +} + +uchar i2c_reg_read (uchar chip, uchar reg) +{ + uchar buf; + + i2c_read (chip, reg, 1, &buf, 1); + + return buf; +} + +void i2c_reg_write (uchar chip, uchar reg, uchar val) +{ + i2c_write (chip, reg, 1, &val, 1); + + return; +} + + +int i2c_set_bus_num (unsigned int bus) +{ + if (bus >= I2C_BUS_CNT) { + return -1; + } + bus_num = bus; + + return 0; +} + +unsigned int i2c_get_bus_num (void) +{ + return bus_num; +} + +/* TODO */ +unsigned int i2c_get_bus_speed (void) +{ + return -1; +} + +int i2c_set_bus_speed (unsigned int speed) +{ + if (speed != CFG_I2C_SPEED) + return -1; + + return 0; +} + +#endif /* CONFIG_HARD_I2C */ diff --git a/cpu/mpc512x/interrupts.c b/cpu/mpc512x/interrupts.c new file mode 100644 index 00000000000..8cc241c8998 --- /dev/null +++ b/cpu/mpc512x/interrupts.c @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2000-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright 2004 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Derived from the MPC83xx code. + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct irq_action { + interrupt_handler_t *handler; + void *arg; + ulong count; +}; + +int interrupt_init_cpu (unsigned *decrementer_count) +{ + *decrementer_count = get_tbclk () / CFG_HZ; + + return 0; +} + +/* + * Install and free an interrupt handler. + */ +void +irq_install_handler (int irq, interrupt_handler_t * handler, void *arg) +{ +} + +void irq_free_handler (int irq) +{ +} + +void timer_interrupt_cpu (struct pt_regs *regs) +{ + /* nothing to do here */ + return; +} diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c new file mode 100644 index 00000000000..200ff2c4964 --- /dev/null +++ b/cpu/mpc512x/serial.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2000 - 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based ont the MPC5200 PSC driver. + * Adapted for MPC512x by Jan Wrobel + */ + +/* + * Minimal serial functions needed to use one of the PSC ports + * as serial console interface. + */ + +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_PSC_CONSOLE) + +static void fifo_init (volatile psc512x_t *psc) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + + /* reset Rx & Tx fifo slice */ + psc->rfcmd = PSC_FIFO_RESET_SLICE; + psc->tfcmd = PSC_FIFO_RESET_SLICE; + + /* disable Tx & Rx FIFO interrupts */ + psc->rfintmask = 0; + psc->tfintmask = 0; + + psc->tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16); + psc->rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16); + + /* enable Tx & Rx FIFO slice */ + psc->rfcmd = PSC_FIFO_ENABLE_SLICE; + psc->tfcmd = PSC_FIFO_ENABLE_SLICE; + + im->fifoc.fifoc_cmd = FIFOC_DISABLE_CLOCK_GATE; + __asm__ volatile ("sync"); +} + +int serial_init(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + unsigned long baseclk; + int div; + + fifo_init (psc); + + /* set MR register to point to MR1 */ + psc->command = PSC_SEL_MODE_REG_1; + + /* disable Tx/Rx */ + psc->command = PSC_TX_DISABLE | PSC_RX_DISABLE; + + /* choose the prescaler by 16 for the Tx/Rx clock generation */ + psc->psc_clock_select = 0xdd00; + + /* switch to UART mode */ + psc->sicr = 0; + + /* mode register points to mr1 */ + /* configure parity, bit length and so on in mode register 1*/ + psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; + /* now, mode register points to mr2 */ + psc->mode = PSC_MODE_1_STOPBIT; + + /* calculate dividor for setting PSC CTUR and CTLR registers */ + baseclk = (gd->ipb_clk + 8) / 16; + div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; + + psc->ctur = (div >> 8) & 0xff; + /* set baudrate */ + psc->ctlr = div & 0xff; + + /* disable all interrupts */ + psc->psc_imr = 0; + + /* reset and enable Rx/Tx */ + psc->command = PSC_RST_RX; + psc->command = PSC_RST_TX; + psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE; + + return 0; +} + +void serial_putc (const char c) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + if (c == '\n') + serial_putc ('\r'); + + /* Wait for last character to go. */ + while (!(psc->psc_status & PSC_SR_TXEMP)) + ; + + psc->tfdata_8 = c; +} + +void serial_putc_raw (const char c) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + /* Wait for last character to go. */ + while (!(psc->psc_status & PSC_SR_TXEMP)) + ; + + psc->tfdata_8 = c; +} + + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_getc (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + /* Wait for a character to arrive. */ + while (psc->rfstat & PSC_FIFO_EMPTY) + ; + + return psc->rfdata_8; +} + +int serial_tstc (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + return !(psc->rfstat & PSC_FIFO_EMPTY); +} + +void serial_setbrg (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + unsigned long baseclk, div; + + baseclk = (gd->csb_clk + 8) / 16; + div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; + + psc->ctur = (div >> 8) & 0xFF; + psc->ctlr = div & 0xff; /* set baudrate */ +} + +void serial_setrts(int s) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + if (s) { + /* Assert RTS (become LOW) */ + psc->op1 = 0x1; + } + else { + /* Negate RTS (become HIGH) */ + psc->op0 = 0x1; + } +} + +int serial_getcts(void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + volatile psc512x_t *psc = (psc512x_t *) &im->psc[CONFIG_PSC_CONSOLE]; + + return (psc->ip & 0x1) ? 0 : 1; +} +#endif /* CONFIG_PSC_CONSOLE */ diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c new file mode 100644 index 00000000000..9a31155ed2d --- /dev/null +++ b/cpu/mpc512x/speed.c @@ -0,0 +1,135 @@ +/* + * (C) Copyright 2000-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based on the MPC83xx code. + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int spmf_mult[] = { + 68, 1, 12, 16, + 20, 24, 28, 32, + 36, 40, 44, 48, + 52, 56, 60, 64 +}; + +static int cpmf_mult[][2] = { + {0, 1}, {0, 1}, /* 0 and 1 are not valid */ + {1, 1}, {3, 2}, + {2, 1}, {5, 2}, + {3, 1}, {7, 2}, + {0, 1}, {0, 1}, /* and all above 7 are not valid too */ + {0, 1}, {0, 1}, + {0, 1}, {0, 1}, + {0, 1}, {0, 1} +}; + +static int sys_dividors[][2] = { + {2, 1}, {5, 2}, {3, 1}, {7, 2}, {4, 1}, + {9, 2}, {5, 1}, {7, 1}, {6, 1}, {8, 1}, + {9, 1}, {11, 1}, {10, 1}, {12, 1}, {13, 1}, + {15, 1}, {14, 1}, {16, 1}, {17, 1}, {19, 1}, + {18, 1}, {20, 1}, {21, 1}, {23, 1}, {22, 1}, + {24, 1}, {25, 1}, {27, 1}, {26, 1}, {28, 1}, + {29, 1}, {31, 1}, {30, 1}, {32, 1}, {33, 1} +}; + +int get_clocks (void) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u8 spmf; + u8 cpmf; + u8 sys_div; + u8 ips_div; + u32 ref_clk = CFG_MPC512X_CLKIN; + u32 spll; + u32 sys_clk; + u32 core_clk; + u32 csb_clk; + u32 ips_clk; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; + spll = ref_clk * spmf_mult[spmf]; + + sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT; + sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0]; + + csb_clk = sys_clk / 2; + + cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT; + core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1]; + + ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT; + if (ips_div != 0) { + ips_clk = csb_clk / ips_div; + } else { + /* in case we cannot get a sane IPS divisor, fail gracefully */ + ips_clk = 0; + } + + gd->ipb_clk = ips_clk; + gd->csb_clk = csb_clk; + gd->cpu_clk = core_clk; + gd->bus_clk = csb_clk; + return 0; + +} + +/******************************************** + * get_bus_freq + * return system bus freq in Hz + *********************************************/ +ulong get_bus_freq (ulong dummy) +{ + return gd->csb_clk; +} + +int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) +{ + printf ("Clock configuration:\n"); + printf (" CPU: %4d MHz\n", gd->cpu_clk / 1000000); + printf (" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000); + printf (" IPS Bus: %4d MHz\n", gd->ipb_clk / 1000000); + printf (" DDR: %4d MHz\n", 2 * gd->csb_clk / 1000000); + return 0; +} + +U_BOOT_CMD(clocks, 1, 0, do_clocks, + "clocks - print clock configuration\n", + " clocks\n" +); + +int prt_mpc512x_clks (void) +{ + do_clocks (NULL, 0, 0, NULL); + return (0); +} diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S new file mode 100644 index 00000000000..8b749ac54e9 --- /dev/null +++ b/cpu/mpc512x/start.S @@ -0,0 +1,780 @@ +/* + * Copyright (C) 1998 Dan Malek + * Copyright (C) 1999 Magnus Damm + * Copyright (C) 2000, 2001, 2002, 2007 Wolfgang Denk + * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based on the MPC83xx code. + */ + +/* + * U-Boot - Startup Code for MPC512x based Embedded Boards + */ + +#include +#include +#include + +#define CONFIG_521X 1 /* needed for Linux kernel header files*/ + +#include +#include + +#include +#include + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "MPC512X" +#endif + +/* + * Floating Point enable, Machine Check and Recoverable Interr. + */ +#undef MSR_KERNEL +#ifdef DEBUG +#define MSR_KERNEL (MSR_FP|MSR_RI) +#else +#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI) +#endif + +/* Macros for manipulating CSx_START/STOP */ +#define START_REG(start) ((start) >> 16) +#define STOP_REG(start, size) (((start) + (size) - 1) >> 16) + +/* + * Set up GOT: Global Offset Table + * + * Use r14 to access the GOT + */ + START_GOT + GOT_ENTRY(_GOT2_TABLE_) + GOT_ENTRY(_FIXUP_TABLE_) + + GOT_ENTRY(_start) + GOT_ENTRY(_start_of_vectors) + GOT_ENTRY(_end_of_vectors) + GOT_ENTRY(transfer_to_handler) + + GOT_ENTRY(__init_end) + GOT_ENTRY(_end) + GOT_ENTRY(__bss_start) + END_GOT + +/* + * Magic number and version string + */ + .long 0x27051956 /* U-Boot Magic Number */ + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", __DATE__, " - ", __TIME__, ")" + .ascii " ", CONFIG_IDENT_STRING, "\0" + +/* + * Vector Table + */ + .text + . = EXC_OFF_SYS_RESET + + .globl _start + /* Start from here after reset/power on */ +_start: + li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */ + b boot_cold + + .globl _start_of_vectors +_start_of_vectors: + +/* Machine check */ + STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) + +/* Data Storage exception. */ + STD_EXCEPTION(0x300, DataStorage, UnknownException) + +/* Instruction Storage exception. */ + STD_EXCEPTION(0x400, InstStorage, UnknownException) + +/* External Interrupt exception. */ + STD_EXCEPTION(0x500, ExtInterrupt, UnknownException) + +/* Alignment exception. */ + . = 0x600 +Alignment: + EXCEPTION_PROLOG(SRR0, SRR1) + mfspr r4,DAR + stw r4,_DAR(r21) + mfspr r5,DSISR + stw r5,_DSISR(r21) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_Alignment: + .long AlignmentException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Program check exception */ + . = 0x700 +ProgramCheck: + EXCEPTION_PROLOG(SRR0, SRR1) + addi r3,r1,STACK_FRAME_OVERHEAD + li r20,MSR_KERNEL + rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */ + rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */ + lwz r6,GOT(transfer_to_handler) + mtlr r6 + blrl +.L_ProgramCheck: + .long ProgramCheckException - _start + EXC_OFF_SYS_RESET + .long int_return - _start + EXC_OFF_SYS_RESET + +/* Floating Point Unit unavailable exception */ + STD_EXCEPTION(0x800, FPUnavailable, UnknownException) + +/* Decrementer */ + STD_EXCEPTION(0x900, Decrementer, timer_interrupt) + +/* Critical interrupt */ + STD_EXCEPTION(0xa00, Critical, UnknownException) + +/* System Call */ + STD_EXCEPTION(0xc00, SystemCall, UnknownException) + +/* Trace interrupt */ + STD_EXCEPTION(0xd00, Trace, UnknownException) + +/* Performance Monitor interrupt */ + STD_EXCEPTION(0xf00, PerfMon, UnknownException) + +/* Intruction Translation Miss */ + STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException) + +/* Data Load Translation Miss */ + STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException) + +/* Data Store Translation Miss */ + STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException) + +/* Instruction Address Breakpoint */ + STD_EXCEPTION(0x1300, InstructionAddrBreakpoint, DebugException) + +/* System Management interrupt */ + STD_EXCEPTION(0x1400, SystemMgmtInterrupt, UnknownException) + + .globl _end_of_vectors +_end_of_vectors: + + . = 0x3000 +boot_cold: + /* Save msr contents */ + mfmsr r5 + + /* Set IMMR area to our preferred location */ + lis r4, CONFIG_DEFAULT_IMMR@h + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l + stw r3, IMMRBAR(r4) + mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */ + + /* Initialise the machine */ + bl cpu_early_init + + /* + * Set up Local Access Windows: + * + * 1) Boot/CS0 (boot FLASH) + * 2) On-chip SRAM (initial stack purposes) + */ + + /* Boot CS/CS0 window range */ + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l + + lis r4, START_REG(CFG_FLASH_BASE) + ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE) + stw r4, LPCS0AW(r3) + + /* + * The SRAM window has a fixed size (256K), so only the start address + * is necessary + */ + lis r4, START_REG(CFG_SRAM_BASE) & 0xff00 + stw r4, SRAMBAR(r3) + + /* + * According to MPC5121e RM, configuring local access windows should + * be followed by a dummy read of the config register that was + * modified last and an isync + */ + lwz r4, SRAMBAR(r3) + isync + + /* + * Set configuration of the Boot/CS0, the SRAM window does not have a + * config register so no params can be set for it + */ + lis r3, (CFG_IMMR + LPC_OFFSET)@h + ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l + + lis r4, CFG_CS0_CFG@h + ori r4, r4, CFG_CS0_CFG@l + stw r4, CS0_CONFIG(r3) + + /* Master enable all CS's */ + lis r4, CS_CTRL_ME@h + ori r4, r4, CS_CTRL_ME@l + stw r4, CS_CTRL(r3) + + lis r4, (CFG_MONITOR_BASE)@h + ori r4, r4, (CFG_MONITOR_BASE)@l + addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET + mtlr r5 + blr + +in_flash: + lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h + ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l + + li r0, 0 /* Make room for stack frame header and */ + stwu r0, -4(r1) /* clear final stack frame so that */ + stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + + /* let the C-code set up the rest */ + /* */ + /* Be careful to keep code relocatable & stack humble */ + /*------------------------------------------------------*/ + + GET_GOT /* initialize GOT access */ + + /* r3: IMMR */ + lis r3, CFG_IMMR@h + /* run low-level CPU init code (in Flash) */ + bl cpu_init_f + + /* r3: BOOTFLAG */ + mr r3, r21 + /* run 1st part of board init code (in Flash) */ + bl board_init_f + + /* NOTREACHED - board_init_f() does not return */ + +/* + * This code finishes saving the registers to the exception frame + * and jumps to the appropriate handler for the exception. + * Register r21 is pointer into trap frame, r1 has new stack pointer. + */ + .globl transfer_to_handler +transfer_to_handler: + stw r22,_NIP(r21) + lis r22,MSR_POW@h + andc r23,r23,r22 + stw r23,_MSR(r21) + SAVE_GPR(7, r21) + SAVE_4GPRS(8, r21) + SAVE_8GPRS(12, r21) + SAVE_8GPRS(24, r21) + mflr r23 + andi. r24,r23,0x3f00 /* get vector offset */ + stw r24,TRAP(r21) + li r22,0 + stw r22,RESULT(r21) + lwz r24,0(r23) /* virtual address of handler */ + lwz r23,4(r23) /* where to go when done */ + mtspr SRR0,r24 + mtspr SRR1,r20 + mtlr r23 + SYNC + rfi /* jump to handler, enable MMU */ + +int_return: + mfmsr r28 /* Disable interrupts */ + li r4,0 + ori r4,r4,MSR_EE + andc r28,r28,r4 + SYNC /* Some chip revs need this... */ + mtmsr r28 + SYNC + lwz r2,_CTR(r1) + lwz r0,_LINK(r1) + mtctr r2 + mtlr r0 + lwz r2,_XER(r1) + lwz r0,_CCR(r1) + mtspr XER,r2 + mtcrf 0xFF,r0 + REST_10GPRS(3, r1) + REST_10GPRS(13, r1) + REST_8GPRS(23, r1) + REST_GPR(31, r1) + lwz r2,_NIP(r1) /* Restore environment */ + lwz r0,_MSR(r1) + mtspr SRR0,r2 + mtspr SRR1,r0 + lwz r0,GPR0(r1) + lwz r2,GPR2(r1) + lwz r1,GPR1(r1) + SYNC + rfi + +/* + * This code initialises the machine, it expects original MSR contents to be in r5. + */ +cpu_early_init: + /* Initialize machine status; enable machine check interrupt */ + /*-----------------------------------------------------------*/ + + li r3, MSR_KERNEL /* Set ME and RI flags */ + rlwimi r3, r5, 0, 25, 25 /* preserve IP bit */ +#ifdef DEBUG + rlwimi r3, r5, 0, 21, 22 /* debugger might set SE, BE bits */ +#endif + mtmsr r3 + SYNC + mtspr SRR1, r3 /* Mirror current MSR state in SRR1 */ + + lis r3, CFG_IMMR@h + +#if defined(CONFIG_WATCHDOG) + /* Initialise the watchdog and reset it */ + /*--------------------------------------*/ + lis r4, CFG_WATCHDOG_VALUE + ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) + stw r4, SWCRR(r3) + + /* reset */ + li r4, 0x556C + sth r4, SWSRR@l(r3) + li r4, 0x0 + ori r4, r4, 0xAA39 + sth r4, SWSRR@l(r3) +#else + /* Disable the watchdog */ + /*----------------------*/ + lwz r4, SWCRR(r3) + /* + * Check to see if it's enabled for disabling: once disabled by s/w + * it's not possible to re-enable it + */ + andi. r4, r4, 0x4 + beq 1f + xor r4, r4, r4 + stw r4, SWCRR(r3) +1: +#endif /* CONFIG_WATCHDOG */ + + /* Initialize the Hardware Implementation-dependent Registers */ + /* HID0 also contains cache control */ + /*------------------------------------------------------*/ + lis r3, CFG_HID0_INIT@h + ori r3, r3, CFG_HID0_INIT@l + SYNC + mtspr HID0, r3 + + lis r3, CFG_HID0_FINAL@h + ori r3, r3, CFG_HID0_FINAL@l + SYNC + mtspr HID0, r3 + + lis r3, CFG_HID2@h + ori r3, r3, CFG_HID2@l + SYNC + mtspr HID2, r3 + sync + blr + + +/* Cache functions. + * + * Note: requires that all cache bits in + * HID0 are in the low half word. + */ + .globl icache_enable +icache_enable: + mfspr r3, HID0 + ori r3, r3, HID0_ICE + lis r4, 0 + ori r4, r4, HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets enable and invalidate, clears lock */ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl icache_disable +icache_disable: + mfspr r3, HID0 + lis r4, 0 + ori r4, r4, HID0_ICE|HID0_ILOCK + andc r3, r3, r4 + ori r4, r3, HID0_ICFI + isync + mtspr HID0, r4 /* sets invalidate, clears enable and lock*/ + isync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl icache_status +icache_status: + mfspr r3, HID0 + rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31 + blr + + .globl dcache_enable +dcache_enable: + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + ori r3, r3, HID0_DCE + ori r5, r3, HID0_DCFI + mtspr HID0, r5 /* enable + invalidate */ + mtspr HID0, r3 /* enable */ + sync + blr + + .globl dcache_disable +dcache_disable: + mfspr r3, HID0 + lis r4, 0 + ori r4, r4, HID0_DCE|HID0_DLOCK + andc r3, r3, r4 + ori r4, r3, HID0_DCI + sync + mtspr HID0, r4 /* sets invalidate, clears enable and lock */ + sync + mtspr HID0, r3 /* clears invalidate */ + blr + + .globl dcache_status +dcache_status: + mfspr r3, HID0 + rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 + blr + + .globl get_pvr +get_pvr: + mfspr r3, PVR + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbf */ +/* Description: Data Cache block flush */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbf +ppcDcbf: + dcbf r0,r3 + blr + +/*------------------------------------------------------------------------------- */ +/* Function: ppcDcbi */ +/* Description: Data Cache block Invalidate */ +/* Input: r3 = effective address */ +/* Output: none. */ +/*------------------------------------------------------------------------------- */ + .globl ppcDcbi +ppcDcbi: + dcbi r0,r3 + blr + +/*-------------------------------------------------------------------------- + * Function: ppcDcbz + * Description: Data Cache block zero. + * Input: r3 = effective address + * Output: none. + *-------------------------------------------------------------------------- */ + + .globl ppcDcbz +ppcDcbz: + dcbz r0,r3 + blr + + .globl ppcDWstore +ppcDWstore: + lfd 1, 0(r4) + stfd 1, 0(r3) + blr + + .globl ppcDWload +ppcDWload: + lfd 1, 0(r3) + stfd 1, 0(r4) + blr + +/*-------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + mr r1, r3 /* Set new stack pointer */ + mr r9, r4 /* Save copy of Global Data pointer */ + mr r10, r5 /* Save copy of Destination Address */ + + mr r3, r5 /* Destination Address */ + lis r4, CFG_MONITOR_BASE@h /* Source Address */ + ori r4, r4, CFG_MONITOR_BASE@l + lwz r5, GOT(__init_end) + sub r5, r5, r4 + li r6, CFG_CACHELINE_SIZE /* Cache Line Size */ + + /* + * Fix GOT pointer: + * + * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + * + Destination Address + * + * Offset: + */ + sub r15, r10, r4 + + /* First our own GOT */ + add r14, r14, r15 + /* then the one used by the C code */ + add r30, r30, r15 + + /* + * Now relocate code + */ + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + la r8,-4(r4) + la r7,-4(r3) + + /* copy */ +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + + addi r0,r5,3 + srwi. r0,r0,2 + mtctr r0 + la r8,-4(r4) + la r7,-4(r3) + + /* and compare */ +20: lwzu r20,4(r8) + lwzu r21,4(r7) + xor. r22, r20, r21 + bne 30f + bdnz 20b + b 4f + + /* compare failed */ +30: li r3, 0 + blr + +2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */ + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* + * Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: dcbst 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: icbi 0,r4 + add r4,r4,r6 + cmplw r4,r5 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET + mtlr r0 + blr + +in_ram: + /* + * Relocation Function, r14 point to got2+0x8000 + * + * Adjust got2 pointers, no need to check for 0, this code + * already puts a few entries in the table. + */ + li r0,__got2_entries@sectoff@l + la r3,GOT(_GOT2_TABLE_) + lwz r11,GOT(_GOT2_TABLE_) + mtctr r0 + sub r11,r3,r11 + addi r3,r3,-4 +1: lwzu r0,4(r3) + add r0,r0,r11 + stw r0,0(r3) + bdnz 1b + + /* + * Now adjust the fixups and the pointers to the fixups + * in case we need to move ourselves again. + */ +2: li r0,__fixup_entries@sectoff@l + lwz r3,GOT(_FIXUP_TABLE_) + cmpwi r0,0 + mtctr r0 + addi r3,r3,-4 + beq 4f +3: lwzu r4,4(r3) + lwzux r0,r4,r11 + add r0,r0,r11 + stw r10,0(r3) + stw r0,0(r4) + bdnz 3b +4: +clear_bss: + /* + * Now clear BSS segment + */ + lwz r3,GOT(__bss_start) + lwz r4,GOT(_end) + + cmplw 0, r3, r4 + beq 6f + + li r0, 0 +5: + stw r0, 0(r3) + addi r3, r3, 4 + cmplw 0, r3, r4 + bne 5b +6: + mr r3, r9 /* Global Data pointer */ + mr r4, r10 /* Destination Address */ + bl board_init_r + + /* + * Copy exception vector code to low memory + * + * r3: dest_addr + * r7: source address, r8: end address, r9: target address + */ + .globl trap_init +trap_init: + lwz r7, GOT(_start) + lwz r8, GOT(_end_of_vectors) + + li r9, 0x100 /* reset vector at 0x100 */ + + cmplw 0, r7, r8 + bgelr /* return if r7>=r8 - just in case */ + + mflr r4 /* save link register */ +1: + lwz r0, 0(r7) + stw r0, 0(r9) + addi r7, r7, 4 + addi r9, r9, 4 + cmplw 0, r7, r8 + bne 1b + + /* + * relocate `hdlr' and `int_return' entries + */ + li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET + li r8, Alignment - _start + EXC_OFF_SYS_RESET +2: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 2b + + li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET + bl trap_reloc + + li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET + li r8, SystemCall - _start + EXC_OFF_SYS_RESET +3: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 3b + + li r7, .L_Trace - _start + EXC_OFF_SYS_RESET + li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET +4: + bl trap_reloc + addi r7, r7, 0x100 /* next exception vector */ + cmplw 0, r7, r8 + blt 4b + + mfmsr r3 /* now that the vectors have */ + lis r7, MSR_IP@h /* relocated into low memory */ + ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */ + andc r3, r3, r7 /* (if it was on) */ + SYNC /* Some chip revs need this... */ + mtmsr r3 + SYNC + + mtlr r4 /* restore link register */ + blr + + /* + * Function: relocate entries for one exception vector + */ +trap_reloc: + lwz r0, 0(r7) /* hdlr ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 0(r7) + + lwz r0, 4(r7) /* int_return ... */ + add r0, r0, r3 /* ... += dest_addr */ + stw r0, 4(r7) + + blr diff --git a/cpu/mpc512x/traps.c b/cpu/mpc512x/traps.c new file mode 100644 index 00000000000..40281a2cbb4 --- /dev/null +++ b/cpu/mpc512x/traps.c @@ -0,0 +1,205 @@ +/* + * (C) Copyright 2000 - 2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Derived from the MPC83xx code. + */ + +/* + * This file handles the architecture-dependent parts of hardware + * exceptions + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +extern unsigned long search_exception_table(unsigned long); + +#define END_OF_MEM (gd->bd->bi_memstart + gd->bd->bi_memsize) + +/* + * Trap & Exception support + */ + +void +print_backtrace (unsigned long *sp) +{ + int cnt = 0; + unsigned long i; + + puts ("Call backtrace: "); + while (sp) { + if ((uint)sp > END_OF_MEM) + break; + + i = sp[1]; + if (cnt++ % 7 == 0) + putc ('\n'); + printf ("%08lX ", i); + if (cnt > 32) break; + sp = (unsigned long *) *sp; + } + putc ('\n'); +} + +void show_regs (struct pt_regs * regs) +{ + int i; + + printf ("NIP: %08lX XER: %08lX LR: %08lX REGS: %p TRAP: %04lx DAR: %08lX\n", + regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); + printf ("MSR: %08lx EE: %01x PR: %01x FP: %01x ME: %01x IR/DR: %01x%01x\n", + regs->msr, regs->msr & MSR_EE ? 1 : 0, regs->msr & MSR_PR ? 1 : 0, + regs->msr & MSR_FP ? 1 : 0,regs->msr & MSR_ME ? 1 : 0, + regs->msr & MSR_IR ? 1 : 0, + regs->msr & MSR_DR ? 1 : 0); + + putc ('\n'); + for (i = 0; i < 32; i++) { + if ((i % 8) == 0) { + printf ("GPR%02d: ", i); + } + + printf ("%08lX ", regs->gpr[i]); + if ((i % 8) == 7) { + putc ('\n'); + } + } +} + + +void +_exception (int signr, struct pt_regs *regs) +{ + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + panic ("Exception at pc %lx signal %d", regs->nip,signr); +} + + +void +MachineCheckException (struct pt_regs *regs) +{ + unsigned long fixup; + + if ((fixup = search_exception_table (regs->nip)) != 0) { + regs->nip = fixup; + return; + } + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + + puts ("Machine check.\nCaused by (from msr): "); + printf ("regs %p ",regs); + switch (regs->msr & 0x00FF0000) { + case (0x80000000 >> 10): + puts ("Instruction cache parity signal\n"); + break; + case (0x80000000 >> 11): + puts ("Data cache parity signal\n"); + break; + case (0x80000000 >> 12): + puts ("Machine check signal\n"); + break; + case (0x80000000 >> 13): + puts ("Transfer error ack signal\n"); + break; + case (0x80000000 >> 14): + puts ("Data parity signal\n"); + break; + case (0x80000000 >> 15): + puts ("Address parity signal\n"); + break; + default: + puts ("Unknown values in msr\n"); + } + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + + panic ("machine check"); +} + +void +AlignmentException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + panic ("Alignment Exception"); +} + +void +ProgramCheckException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + panic ("Program Check Exception"); +} + +void +SoftEmuException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + show_regs (regs); + print_backtrace ((unsigned long *)regs->gpr[1]); + panic ("Software Emulation Exception"); +} + + +void +UnknownException (struct pt_regs *regs) +{ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + if (debugger_exception_handler && (*debugger_exception_handler)(regs)) + return; +#endif + printf ("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", + regs->nip, regs->msr, regs->trap); + _exception (0, regs); +} + +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) +extern void do_bedbug_breakpoint (struct pt_regs *); +#endif + +void +DebugException (struct pt_regs *regs) +{ + printf ("Debugger trap at @ %lx\n", regs->nip ); + show_regs (regs); +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) + do_bedbug_breakpoint (regs); +#endif +} diff --git a/include/asm-ppc/e300.h b/include/asm-ppc/e300.h index d1bb159aefa..de8239965aa 100644 --- a/include/asm-ppc/e300.h +++ b/include/asm-ppc/e300.h @@ -9,6 +9,7 @@ #define PVR_E300C1 0x80830000 #define PVR_E300C2 0x80840000 #define PVR_E300C3 0x80850000 +#define PVR_E300C4 0x80860000 /* * Hardware Implementation-Dependent Register 0 (HID0) diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index cd2463643ce..bbaeb3f575f 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -85,6 +85,10 @@ typedef struct global_data { unsigned long ipb_clk; unsigned long pci_clk; #endif +#if defined(CONFIG_MPC512X) + u32 ipb_clk; + u32 csb_clk; +#endif /* CONFIG_MPC512X */ #if defined(CONFIG_MPC8220) unsigned long bExtUart; unsigned long inp_clk; diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h new file mode 100644 index 00000000000..23d10d4eb41 --- /dev/null +++ b/include/asm-ppc/immap_512x.h @@ -0,0 +1,569 @@ +/* + * (C) Copyright 2007 DENX Software Engineering + * + * MPC512x Internal Memory Map + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Based on the MPC83xx header. + */ + +#ifndef __IMMAP_512x__ +#define __IMMAP_512x__ + +#include + +typedef struct law512x { + u32 bar; /* Base Addr Register */ + u32 ar; /* Attributes Register */ +} law521x_t; + +/* + * System configuration registers + */ +typedef struct sysconf512x { + u32 immrbar; /* Internal memory map base address register */ + u8 res0[0x1c]; + u32 lpbaw; /* LP Boot Access Window */ + u32 lpcs0aw; /* LP CS0 Access Window */ + u32 lpcs1aw; /* LP CS1 Access Window */ + u32 lpcs2aw; /* LP CS2 Access Window */ + u32 lpcs3aw; /* LP CS3 Access Window */ + u32 lpcs4aw; /* LP CS4 Access Window */ + u32 lpcs5aw; /* LP CS5 Access Window */ + u32 lpcs6aw; /* LP CS6 Access Window */ + u32 lpcs7aw; /* LP CS7 Access Window */ + u8 res1[0x1c]; + law521x_t pcilaw[3]; /* PCI Local Access Window 0-2 Registers */ + u8 res2[0x28]; + law521x_t ddrlaw; /* DDR Local Access Window */ + u8 res3[0x18]; + u32 mbxbar; /* MBX Base Address */ + u32 srambar; /* SRAM Base Address */ + u32 nfcbar; /* NFC Base Address */ + u8 res4[0x34]; + u32 spridr; /* System Part and Revision ID Register */ + u32 spcr; /* System Priority Configuration Register */ + u8 res5[0xf8]; +} sysconf512x_t; + +/* + * Watch Dog Timer (WDT) Registers + */ +typedef struct wdt512x { + u8 res0[4]; + u32 swcrr; /* System watchdog control register */ + u32 swcnr; /* System watchdog count register */ + u8 res1[2]; + u16 swsrr; /* System watchdog service register */ + u8 res2[0xF0]; +} wdt512x_t; + +/* + * RTC Module Registers + */ +typedef struct rtclk512x { + u8 fixme[0x100]; +} rtclk512x_t; + +/* + * General Purpose Timer + */ +typedef struct gpt512x { + u8 fixme[0x100]; +} gpt512x_t; + +/* + * Integrated Programmable Interrupt Controller + */ +typedef struct ipic512x { + u8 fixme[0x100]; +} ipic512x_t; + +/* + * System Arbiter Registers + */ +typedef struct arbiter512x { + u32 acr; /* Arbiter Configuration Register */ + u32 atr; /* Arbiter Timers Register */ + u32 ater; /* Arbiter Transfer Error Register */ + u32 aer; /* Arbiter Event Register */ + u32 aidr; /* Arbiter Interrupt Definition Register */ + u32 amr; /* Arbiter Mask Register */ + u32 aeatr; /* Arbiter Event Attributes Register */ + u32 aeadr; /* Arbiter Event Address Register */ + u32 aerr; /* Arbiter Event Response Register */ + u8 res1[0xDC]; +} arbiter512x_t; + +/* + * Reset Module + */ +typedef struct reset512x { + u32 rcwl; /* Reset Configuration Word Low Register */ + u32 rcwh; /* Reset Configuration Word High Register */ + u8 res0[8]; + u32 rsr; /* Reset Status Register */ + u32 rmr; /* Reset Mode Register */ + u32 rpr; /* Reset protection Register */ + u32 rcr; /* Reset Control Register */ + u32 rcer; /* Reset Control Enable Register */ + u8 res1[0xDC]; +} reset512x_t; + +/* + * Clock Module + */ +typedef struct clk512x { + u32 spmr; /* System PLL Mode Register */ + u32 sccr[2]; /* System Clock Control Registers */ + u32 scfr[2]; /* System Clock Frequency Registers */ + u8 res0[4]; + u32 bcr; /* Bread Crumb Register */ + u32 pscccr[12]; /* PSC0-11 Clock Control Registers */ + u32 spccr; /* SPDIF Clock Control Registers */ + u32 cccr; /* CFM Clock Control Registers */ + u32 dccr; /* DIU Clock Control Registers */ + u8 res1[0xa8]; +} clk512x_t; + +/* + * Power Management Control Module + */ +typedef struct pmc512x { + u8 fixme[0x100]; +} pmc512x_t; + +/* + * General purpose I/O module + */ +typedef struct gpio512x { + u8 fixme[0x100]; +} gpio512x_t; + +/* + * DDR Memory Controller Memory Map + */ +typedef struct ddr512x { + u32 ddr_sys_config; /* System Configuration Register */ + u32 ddr_time_config0; /* Timing Configuration Register */ + u32 ddr_time_config1; /* Timing Configuration Register */ + u32 ddr_time_config2; /* Timing Configuration Register */ + u32 ddr_command; /* Command Register */ + u32 ddr_compact_command; /* Compact Command Register */ + u32 self_refresh_cmd_0; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_1; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_2; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_3; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_4; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_5; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_6; /* Enter/Exit Self Refresh Registers */ + u32 self_refresh_cmd_7; /* Enter/Exit Self Refresh Registers */ + u32 DQS_config_offset_count; /* DQS Config Offset Count */ + u32 DQS_config_offset_time; /* DQS Config Offset Time */ + u32 DQS_delay_status; /* DQS Delay Status */ + u32 res0[0xF]; + u32 prioman_config1; /* Priority Manager Configuration */ + u32 prioman_config2; /* Priority Manager Configuration */ + u32 hiprio_config; /* High Priority Configuration */ + u32 lut_table0_main_upper; /* LUT0 Main Upper */ + u32 lut_table1_main_upper; /* LUT1 Main Upper */ + u32 lut_table2_main_upper; /* LUT2 Main Upper */ + u32 lut_table3_main_upper; /* LUT3 Main Upper */ + u32 lut_table4_main_upper; /* LUT4 Main Upper */ + u32 lut_table0_main_lower; /* LUT0 Main Lower */ + u32 lut_table1_main_lower; /* LUT1 Main Lower */ + u32 lut_table2_main_lower; /* LUT2 Main Lower */ + u32 lut_table3_main_lower; /* LUT3 Main Lower */ + u32 lut_table4_main_lower; /* LUT4 Main Lower */ + u32 lut_table0_alternate_upper; /* LUT0 Alternate Upper */ + u32 lut_table1_alternate_upper; /* LUT1 Alternate Upper */ + u32 lut_table2_alternate_upper; /* LUT2 Alternate Upper */ + u32 lut_table3_alternate_upper; /* LUT3 Alternate Upper */ + u32 lut_table4_alternate_upper; /* LUT4 Alternate Upper */ + u32 lut_table0_alternate_lower; /* LUT0 Alternate Lower */ + u32 lut_table1_alternate_lower; /* LUT1 Alternate Lower */ + u32 lut_table2_alternate_lower; /* LUT2 Alternate Lower */ + u32 lut_table3_alternate_lower; /* LUT3 Alternate Lower */ + u32 lut_table4_alternate_lower; /* LUT4 Alternate Lower */ + u32 performance_monitor_config; + u32 event_time_counter; + u32 event_time_preset; + u32 performance_monitor1_address_low; + u32 performance_monitor2_address_low; + u32 performance_monitor1_address_hi; + u32 performance_monitor2_address_hi; + u32 res1[2]; + u32 performance_monitor1_read_counter; + u32 performance_monitor2_read_counter; + u32 performance_monitor1_write_counter; + u32 performance_monitor2_write_counter; + u32 granted_ack_counter0; + u32 granted_ack_counter1; + u32 granted_ack_counter2; + u32 granted_ack_counter3; + u32 granted_ack_counter4; + u32 cumulative_wait_counter0; + u32 cumulative_wait_counter1; + u32 cumulative_wait_counter2; + u32 cumulative_wait_counter3; + u32 cumulative_wait_counter4; + u32 summed_priority_counter0; + u32 summed_priority_counter1; + u32 summed_priority_counter2; + u32 summed_priority_counter3; + u32 summed_priority_counter4; + u32 res2[0x3AD]; +} ddr512x_t; + + +/* + * DMA/Messaging Unit + */ +typedef struct dma512x { + u8 fixme[0x1800]; +} dma512x_t; + +/* + * PCI Software Configuration Registers + */ +typedef struct pciconf512x { + u8 fixme[0x80]; +} pciconf512x_t; + +/* + * Sequencer + */ +typedef struct ios512x { + u8 fixme[0x100]; +} ios512x_t; + +/* + * PCI Controller + */ +typedef struct pcictrl512x { + u8 fixme[0x100]; +} pcictrl512x_t; + + +/* + * MSCAN + */ +typedef struct mscan512x { + u8 fixme[0x100]; +} mscan512x_t; + +/* + * BDLC + */ +typedef struct bdlc512x { + u8 fixme[0x100]; +} bdlc512x_t; + +/* + * SDHC + */ +typedef struct sdhc512x { + u8 fixme[0x100]; +} sdhc512x_t; + +/* + * SPDIF + */ +typedef struct spdif512x { + u8 fixme[0x100]; +} spdif512x_t; + +/* + * I2C + */ +typedef struct i2c512x_dev { + volatile u32 madr; /* I2Cn + 0x00 */ + volatile u32 mfdr; /* I2Cn + 0x04 */ + volatile u32 mcr; /* I2Cn + 0x08 */ + volatile u32 msr; /* I2Cn + 0x0C */ + volatile u32 mdr; /* I2Cn + 0x10 */ + u8 res0[0x0C]; +} i2c512x_dev_t; + +typedef struct i2c512x { + i2c512x_dev_t dev[3]; + volatile u32 icr; + volatile u32 mifr; + u8 res0[0x98]; +} i2c512x_t; + +/* + * AXE + */ +typedef struct axe512x { + u8 fixme[0x100]; +} axe512x_t; + +/* + * DIU + */ +typedef struct diu512x { + u8 fixme[0x100]; +} diu512x_t; + +/* + * CFM + */ +typedef struct cfm512x { + u8 fixme[0x100]; +} cfm512x_t; + +/* + * FEC + */ +typedef struct fec512x { + u8 fixme[0x800]; +} fec512x_t; + +/* + * ULPI + */ +typedef struct ulpi512x { + u8 fixme[0x600]; +} ulpi512x_t; + +/* + * UTMI + */ +typedef struct utmi512x { + u8 fixme[0x3000]; +} utmi512x_t; + +/* + * PCI DMA + */ +typedef struct pcidma512x { + u8 fixme[0x300]; +} pcidma512x_t; + +/* + * IO Control + */ +typedef struct ioctrl512x { + u32 regs[0x400]; +} ioctrl512x_t; + +/* + * IIM + */ +typedef struct iim512x { + u8 fixme[0x1000]; +} iim512x_t; + +/* + * LPC + */ +typedef struct lpc512x { + u32 cs_cfg[8]; /* Chip Select N Configuration Registers + No dedicated entry for CS Boot as == CS0 */ + u32 cs_cr; /* Chip Select Control Register */ + u32 cs_sr; /* Chip Select Status Register */ + u32 cs_bcr; /* Chip Select Burst Control Register */ + u32 cs_dccr; /* Chip Select Deadcycle Control Register */ + u32 cs_hccr; /* Chip Select Holdcycle Control Register */ + u8 res0[0xcc]; + u32 sclpc_psr; /* SCLPC Packet Size Register */ + u32 sclpc_sar; /* SCLPC Start Address Register */ + u32 sclpc_cr; /* SCLPC Control Register */ + u32 sclpc_er; /* SCLPC Enable Register */ + u32 sclpc_nar; /* SCLPC NextAddress Register */ + u32 sclpc_sr; /* SCLPC Status Register */ + u32 sclpc_bdr; /* SCLPC Bytes Done Register */ + u32 emb_scr; /* EMB Share Counter Register */ + u32 emb_pcr; /* EMB Pause Control Register */ + u8 res1[0x1c]; + u32 lpc_fdwr; /* LPC RX/TX FIFO Data Word Register */ + u32 lpc_fsr; /* LPC RX/TX FIFO Status Register */ + u32 lpc_cr; /* LPC RX/TX FIFO Control Register */ + u32 lpc_ar; /* LPC RX/TX FIFO Alarm Register */ + u8 res2[0xb0]; +} lpc512x_t; + +/* + * PATA + */ +typedef struct pata512x { + u8 fixme[0x100]; +} pata512x_t; + +/* + * PSC + */ +typedef struct psc512x { + volatile u8 mode; /* PSC + 0x00 */ + volatile u8 res0[3]; + union { /* PSC + 0x04 */ + volatile u16 status; + volatile u16 clock_select; + } sr_csr; +#define psc_status sr_csr.status +#define psc_clock_select sr_csr.clock_select + volatile u16 res1; + volatile u8 command; /* PSC + 0x08 */ + volatile u8 res2[3]; + union { /* PSC + 0x0c */ + volatile u8 buffer_8; + volatile u16 buffer_16; + volatile u32 buffer_32; + } buffer; +#define psc_buffer_8 buffer.buffer_8 +#define psc_buffer_16 buffer.buffer_16 +#define psc_buffer_32 buffer.buffer_32 + union { /* PSC + 0x10 */ + volatile u8 ipcr; + volatile u8 acr; + } ipcr_acr; +#define psc_ipcr ipcr_acr.ipcr +#define psc_acr ipcr_acr.acr + volatile u8 res3[3]; + union { /* PSC + 0x14 */ + volatile u16 isr; + volatile u16 imr; + } isr_imr; +#define psc_isr isr_imr.isr +#define psc_imr isr_imr.imr + volatile u16 res4; + volatile u8 ctur; /* PSC + 0x18 */ + volatile u8 res5[3]; + volatile u8 ctlr; /* PSC + 0x1c */ + volatile u8 res6[3]; + volatile u32 ccr; /* PSC + 0x20 */ + volatile u8 res7[12]; + volatile u8 ivr; /* PSC + 0x30 */ + volatile u8 res8[3]; + volatile u8 ip; /* PSC + 0x34 */ + volatile u8 res9[3]; + volatile u8 op1; /* PSC + 0x38 */ + volatile u8 res10[3]; + volatile u8 op0; /* PSC + 0x3c */ + volatile u8 res11[3]; + volatile u32 sicr; /* PSC + 0x40 */ + volatile u8 res12[60]; + volatile u32 tfcmd; /* PSC + 0x80 */ + volatile u32 tfalarm; /* PSC + 0x84 */ + volatile u32 tfstat; /* PSC + 0x88 */ + volatile u32 tfintstat; /* PSC + 0x8C */ + volatile u32 tfintmask; /* PSC + 0x90 */ + volatile u32 tfcount; /* PSC + 0x94 */ + volatile u16 tfwptr; /* PSC + 0x98 */ + volatile u16 tfrptr; /* PSC + 0x9A */ + volatile u32 tfsize; /* PSC + 0x9C */ + volatile u8 res13[28]; + union { /* PSC + 0xBC */ + volatile u8 buffer_8; + volatile u16 buffer_16; + volatile u32 buffer_32; + } tfdata_buffer; +#define tfdata_8 tfdata_buffer.buffer_8 +#define tfdata_16 tfdata_buffer.buffer_16 +#define tfdata_32 tfdata_buffer.buffer_32 + + volatile u32 rfcmd; /* PSC + 0xC0 */ + volatile u32 rfalarm; /* PSC + 0xC4 */ + volatile u32 rfstat; /* PSC + 0xC8 */ + volatile u32 rfintstat; /* PSC + 0xCC */ + volatile u32 rfintmask; /* PSC + 0xD0 */ + volatile u32 rfcount; /* PSC + 0xD4 */ + volatile u16 rfwptr; /* PSC + 0xD8 */ + volatile u16 rfrptr; /* PSC + 0xDA */ + volatile u32 rfsize; /* PSC + 0xDC */ + volatile u8 res18[28]; + union { /* PSC + 0xFC */ + volatile u8 buffer_8; + volatile u16 buffer_16; + volatile u32 buffer_32; + } rfdata_buffer; +#define rfdata_8 rfdata_buffer.buffer_8 +#define rfdata_16 rfdata_buffer.buffer_16 +#define rfdata_32 rfdata_buffer.buffer_32 +} psc512x_t; + +/* + * FIFOC + */ +typedef struct fifoc512x { + u32 fifoc_cmd; + u32 fifoc_int; + u32 fifoc_dma; + u32 fifoc_axe; + u32 fifoc_debug; + u8 fixme[0xEC]; +} fifoc512x_t; + +/* + * SATA + */ +typedef struct sata512x { + u8 fixme[0x2000]; +} sata512x_t; + +typedef struct immap { + sysconf512x_t sysconf; /* System configuration */ + u8 res0[0x700]; + wdt512x_t wdt; /* Watch Dog Timer (WDT) */ + rtclk512x_t rtc; /* Real Time Clock Module */ + gpt512x_t gpt; /* General Purpose Timer */ + ipic512x_t ipic; /* Integrated Programmable Interrupt Controller */ + arbiter512x_t arbiter; /* CSB Arbiter */ + reset512x_t reset; /* Reset Module */ + clk512x_t clk; /* Clock Module */ + pmc512x_t pmc; /* Power Management Control Module */ + gpio512x_t gpio; /* General purpose I/O module */ + u8 res1[0x100]; + mscan512x_t mscan; /* MSCAN */ + bdlc512x_t bdlc; /* BDLC */ + sdhc512x_t sdhc; /* SDHC */ + spdif512x_t spdif; /* SPDIF */ + i2c512x_t i2c; /* I2C Controllers */ + u8 res2[0x800]; + axe512x_t axe; /* AXE */ + diu512x_t diu; /* Display Interface Unit */ + cfm512x_t cfm; /* Clock Frequency Measurement */ + u8 res3[0x500]; + fec512x_t fec; /* Fast Ethernet Controller */ + ulpi512x_t ulpi; /* USB ULPI */ + u8 res4[0xa00]; + utmi512x_t utmi; /* USB UTMI */ + u8 res5[0x1000]; + pcidma512x_t pci_dma; /* PCI DMA */ + pciconf512x_t pci_conf; /* PCI Configuration */ + u8 res6[0x80]; + ios512x_t ios; /* PCI Sequencer */ + pcictrl512x_t pci_ctrl; /* PCI Controller Control and Status */ + u8 res7[0xa00]; + ddr512x_t mddrc; /* Multi-port DDR Memory Controller */ + ioctrl512x_t io_ctrl; /* IO Control */ + iim512x_t iim; /* IC Identification module */ + u8 res8[0x4000]; + lpc512x_t lpc; /* LocalPlus Controller */ + pata512x_t pata; /* Parallel ATA */ + u8 res9[0xd00]; + psc512x_t psc[12]; /* PSCs */ + u8 res10[0x300]; + fifoc512x_t fifoc; /* FIFO Controller */ + u8 res11[0x2000]; + dma512x_t dma; /* DMA */ + u8 res12[0xa800]; + sata512x_t sata; /* Serial ATA */ + u8 res13[0xde000]; +} immap_t; +#endif /* __IMMAP_512x__ */ diff --git a/include/common.h b/include/common.h index 23f93907ee4..d823733b67f 100644 --- a/include/common.h +++ b/include/common.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2004 + * (C) Copyright 2000-2007 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -65,6 +65,9 @@ typedef volatile unsigned char vu_char; #include #elif defined(CONFIG_MPC5xxx) #include +#elif defined(CONFIG_MPC512X) +#include +#include #elif defined(CONFIG_MPC8220) #include #elif defined(CONFIG_8260) @@ -448,6 +451,9 @@ int prt_8260_clks (void); #elif defined(CONFIG_MPC5xxx) int prt_mpc5xxx_clks (void); #endif +#if defined(CONFIG_MPC512x) +int prt_mpc512xxx_clks (void); +#endif #if defined(CONFIG_MPC8220) int prt_mpc8220_clks (void); #endif diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h new file mode 100644 index 00000000000..a1b8eefa02c --- /dev/null +++ b/include/configs/ads5121.h @@ -0,0 +1,410 @@ +/* + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * ADS5121 board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define DEBUG +#undef DEBUG + +/* + * Memory map for the ADS5121 board: + * + * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) + * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) + * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) + * 0x8200_0000 - 0x8200_001F CPLD (32 B) + * 0xFC00_0000 - 0xFFFF_FFFF NOR Boot FLASH (64 MB) + */ + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 Family */ +#define CONFIG_MPC512X 1 /* MPC512X family */ + +#undef CONFIG_PCI + +#define CFG_MPC512X_CLKIN 66000000 /* in Hz */ + +#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */ + +#define CFG_IMMR 0x80000000 + +#define CFG_MEMTEST_START 0x00200000 /* memtest region */ +#define CFG_MEMTEST_END 0x00400000 + +/* + * DDR Setup - manually set all parameters as there's no SPD etc. + */ +#define CFG_DDR_SIZE 256 /* MB */ +#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ +#define CFG_SDRAM_BASE CFG_DDR_BASE + +/* DDR Controller Configuration + +SYS_CFG: + [31:31] MDDRC Soft Reset: Diabled + [30:30] DRAM CKE pin: Enabled + [29:29] DRAM CLK: Enabled + [28:28] Command Mode: Enabled (For initialization only) + [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] + [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] + [20:19] Read Test: DON'T USE + [18:18] Self Refresh: Enabled + [17:17] 16bit Mode: Disabled + [16:13] Ready Delay: 2 + [12:12] Half DQS Delay: Disabled + [11:11] Quarter DQS Delay: Disabled + [10:08] Write Delay: 2 + [07:07] Early ODT: Disabled + [06:06] On DIE Termination: Disabled + [05:05] FIFO Overflow Clear: DON'T USE here + [04:04] FIFO Underflow Clear: DON'T USE here + [03:03] FIFO Overflow Pending: DON'T USE here + [02:02] FIFO Underlfow Pending: DON'T USE here + [01:01] FIFO Overlfow Enabled: Enabled + [00:00] FIFO Underflow Enabled: Enabled + TIME_CFG0 + [31:16] DRAM Refresh Time: 0 CSB clocks + [15:8] DRAM Command Time: 0 CSB clocks + [07:00] DRAM Precharge Time: 0 CSB clocks + TIME_CFG1 + [31:26] DRAM tRFC: + [25:21] DRAM tWR1: + [20:17] DRAM tWRT1: + [16:11] DRAM tDRR: + [10:05] DRAM tRC: + [04:00] DRAM tRAS: + TIME_CFG2 + [31:28] DRAM tRCD: + [27:23] DRAM tFAW: + [22:19] DRAM tRTW1: + [18:15] DRAM tCCD: + [14:10] DRAM tRTP: + [09:05] DRAM tRP: + [04:00] DRAM tRPA */ + +#define CFG_MDDRC_SYS_CFG 0xF8604200 +#define CFG_MDDRC_SYS_CFG_RUN 0xE8604200 +#define CFG_MDDRC_SYS_CFG_EN 0x30000000 +#define CFG_MDDRC_TIME_CFG0 0x0000281E +#define CFG_MDDRC_TIME_CFG0_RUN 0x01F4281E +#define CFG_MDDRC_TIME_CFG1 0x54EC1168 +#define CFG_MDDRC_TIME_CFG2 0x35210864 + +#define CFG_MICRON_NOP 0x01380000 +#define CFG_MICRON_PCHG_ALL 0x01100400 +#define CFG_MICRON_MR 0x01000022 +#define CFG_MICRON_EM2 0x01020000 +#define CFG_MICRON_EM3 0x01030000 +#define CFG_MICRON_EN_DLL 0x01010000 +#define CFG_MICRON_RST_DLL 0x01000932 +#define CFG_MICRON_RFSH 0x01080000 +#define CFG_MICRON_INIT_DEV_OP 0x01000832 +#define CFG_MICRON_OCD_DEFAULT 0x01010780 +#define CFG_MICRON_OCD_EXIT 0x01010400 + +/* DDR Priority Manager Configuration */ +#define CFG_MDDRCGRP_PM_CFG1 0x000777AA +#define CFG_MDDRCGRP_PM_CFG2 0x00000055 +#define CFG_MDDRCGRP_HIPRIO_CFG 0x00000000 +#define CFG_MDDRCGRP_LUT0_MU 0x11111117 +#define CFG_MDDRCGRP_LUT0_ML 0x7777777A +#define CFG_MDDRCGRP_LUT1_MU 0x4444EEEE +#define CFG_MDDRCGRP_LUT1_ML 0xEEEEEEEE +#define CFG_MDDRCGRP_LUT2_MU 0x44444444 +#define CFG_MDDRCGRP_LUT2_ML 0x44444444 +#define CFG_MDDRCGRP_LUT3_MU 0x55555555 +#define CFG_MDDRCGRP_LUT3_ML 0x55555558 +#define CFG_MDDRCGRP_LUT4_MU 0x11111111 +#define CFG_MDDRCGRP_LUT4_ML 0x1111117C +#define CFG_MDDRCGRP_LUT0_AU 0x33333377 +#define CFG_MDDRCGRP_LUT0_AL 0x7777EEEE +#define CFG_MDDRCGRP_LUT1_AU 0x11111111 +#define CFG_MDDRCGRP_LUT1_AL 0x11111111 +#define CFG_MDDRCGRP_LUT2_AU 0x11111111 +#define CFG_MDDRCGRP_LUT2_AL 0x11111111 +#define CFG_MDDRCGRP_LUT3_AU 0x11111111 +#define CFG_MDDRCGRP_LUT3_AL 0x11111111 +#define CFG_MDDRCGRP_LUT4_AU 0x11111111 +#define CFG_MDDRCGRP_LUT4_AL 0x11111111 + +/* + * NOR FLASH on the Local Bus + */ +#define CFG_FLASH_CFI /* use the Common Flash Interface */ +#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH */ +#define CFG_FLASH_SIZE 0x04000000 /* max flash size in bytes */ +#define CFG_FLASH_USE_BUFFER_WRITE + +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ + +#undef CFG_FLASH_CHECKSUM + +/* + * CPLD registers area is really only 32 bytes in size, but the smallest possible LP + * window is 64KB + */ +#define CFG_CPLD_BASE 0x82000000 +#define CFG_CPLD_SIZE 0x00010000 /* 64 KB */ + +#define CFG_SRAM_BASE 0x30000000 +#define CFG_SRAM_SIZE 0x00020000 /* 128 KB */ + +#define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ +#define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ + +/* Use SRAM for initial stack */ +#define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END CFG_SRAM_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE /* Start of monitor */ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */ +#if CONFIG_PSC_CONSOLE != 3 +#error CONFIG_PSC_CONSOLE must be 3 +#endif +#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} + +#define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE +#define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR +#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE +#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +/* Use the HUSH parser */ +#define CFG_HUSH_PARSER +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* so disable bit-banged I2C */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#if 0 +#define CFG_I2C_NOPROBES {{0,0x69}} * Don't probe these addrs */ +#endif + +/* + * Ethernet configuration + */ +#define CONFIG_MPC512x_FEC 1 +#define CONFIG_NET_MULTI +#define CONFIG_PHY_ADDR 0x1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_ETHADDR 00:e0:5e:00:e5:14 + +#if 0 +/* + * Configure on-board RTC + */ +#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ +#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +#endif + +/* + * Environment + */ +#define CFG_ENV_IS_IN_FLASH 1 +/* This has to be a multiple of the Flash sector size */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_SECT_SIZE 0x40000 /* one sector (256K) for env */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#if defined(CONFIG_PCI) +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_PCI \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + ) +#else +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ + | CFG_CMD_NET \ + | CFG_CMD_PING \ + | CFG_CMD_MII \ + | CFG_CMD_I2C) +#endif + +#include + +/* + * Watchdog timeout = CFG_WATCHDOG_VALUE * 65536 / IPS clock. + * For example, when IPS is set to 66MHz and CFG_WATCHDOG_VALUE is set + * to 0xFFFF, watchdog timeouts after about 64s. For details refer + * to chapter 36 of the MPC5121e Reference Manual. + */ +#define CONFIG_WATCHDOG /* enable watchdog */ +#define CFG_WATCHDOG_VALUE 0xFFFF + + /* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LOAD_ADDR 0x2000000 /* default load address */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else + #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif + + +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ + +/* Cache Configuration */ +#define CFG_DCACHE_SIZE 32768 +#define CFG_CACHELINE_SIZE 32 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ +#endif + +#define CFG_HID0_INIT 0x000000000 +#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CFG_HID2 HID2_HBE + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_HOSTNAME ads5121 +#define CONFIG_ROOTPATH /nfsroot/rootfs +#define CONFIG_BOOTFILE uImage + +#define CONFIG_IPADDR 192.168.160.77 +#define CONFIG_SERVERIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_NETMASK 255.255.0.0 + +#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ + +//#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ +#define CONFIG_BOOTDELAY -1 +#undef CONFIG_BOOTARGS /* the boot command will set bootargs */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "load=tftp 100000 /tftpboot/ads5121/u-boot.bin\0" \ + "update=protect off fff00000 fff3ffff; " \ + "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ + "upd=run load;run update\0" \ + "" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#endif /* __CONFIG_H */ diff --git a/include/mpc512x.h b/include/mpc512x.h new file mode 100644 index 00000000000..03e0e9a1473 --- /dev/null +++ b/include/mpc512x.h @@ -0,0 +1,398 @@ +/* + * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * (C) Copyright 2007 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * Derived from the MPC83xx header. + */ + +#ifndef __MPC512X_H__ +#define __MPC512X_H__ + +#include +#if defined(CONFIG_E300) +#include +#endif + +/* System reset offset (PowerPC standard) + */ +#define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET + + +/* IMMRBAR - Internal Memory Register Base Address + */ +#define CONFIG_DEFAULT_IMMR 0xFF400000 /* Default IMMR base address */ +#define IMMRBAR 0x0000 /* Register offset to immr */ +#define IMMRBAR_BASE_ADDR 0xFFF00000 /* Base address mask */ +#define IMMRBAR_RES ~(IMMRBAR_BASE_ADDR) + +/* LAWBAR - Local Access Window Base Address Register + */ +#define LPBAW 0x0020 /* Register offset to immr */ +#define LPCS0AW 0x0024 +#define LPCS1AW 0x0028 +#define LPCS2AW 0x002C +#define LPCS3AW 0x0030 +#define LPCS4AW 0x0034 +#define LPCS5AW 0x0038 +#define LPCS6AW 0x003C +#define LPCA7AW 0x0040 +#define SRAMBAR 0x00C4 + +#define LPC_OFFSET 0x10000 + +#define CS0_CONFIG 0x00000 +#define CS1_CONFIG 0x00004 +#define CS2_CONFIG 0x00008 +#define CS3_CONFIG 0x0000C +#define CS4_CONFIG 0x00010 +#define CS5_CONFIG 0x00014 +#define CS6_CONFIG 0x00018 +#define CS7_CONFIG 0x0001C + +#define CS_CTRL 0x00020 +#define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ +#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */ + +/* SPRIDR - System Part and Revision ID Register + */ +#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification */ +#define SPRIDR_REVID 0x0000FFFF /* Revision Identification */ + +#define SPR_5121E 0x80180000 + +/* SPCR - System Priority Configuration Register + */ +#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable */ +#define SPCR_PCIHPE_SHIFT (31-3) +#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority */ +#define SPCR_PCIPR_SHIFT (31-7) +#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable */ +#define SPCR_TBEN_SHIFT (31-9) +#define SPCR_COREPR 0x00300000 /* E300 PowerPC Core system bus request priority */ +#define SPCR_COREPR_SHIFT (31-11) + +/* SWCRR - System Watchdog Control Register + */ +#define SWCRR 0x0904 /* Register offset to immr */ +#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count */ +#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit */ +#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit */ +#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit */ +#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) + +/* SWCNR - System Watchdog Counter Register + */ +#define SWCNR 0x0908 /* Register offset to immr */ +#define SWCNR_SWCN 0x0000FFFF /* Software Watchdog Count mask */ +#define SWCNR_RES ~(SWCNR_SWCN) + +/* SWSRR - System Watchdog Service Register + */ +#define SWSRR 0x090E /* Register offset to immr */ + +/* ACR - Arbiter Configuration Register + */ +#define ACR_COREDIS 0x10000000 /* Core disable */ +#define ACR_COREDIS_SHIFT (31-7) +#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth */ +#define ACR_PIPE_DEP_SHIFT (31-15) +#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count */ +#define ACR_PCI_RPTCNT_SHIFT (31-19) +#define ACR_RPTCNT 0x00000700 /* Repeat count */ +#define ACR_RPTCNT_SHIFT (31-23) +#define ACR_APARK 0x00000030 /* Address parking */ +#define ACR_APARK_SHIFT (31-27) +#define ACR_PARKM 0x0000000F /* Parking master */ +#define ACR_PARKM_SHIFT (31-31) + +/* ATR - Arbiter Timers Register + */ +#define ATR_DTO 0x00FF0000 /* Data time out */ +#define ATR_ATO 0x000000FF /* Address time out */ + +/* AER - Arbiter Event Register + */ +#define AER_ETEA 0x00000020 /* Transfer error */ +#define AER_RES 0x00000010 /* Reserved transfer type */ +#define AER_ECW 0x00000008 /* External control word transfer type */ +#define AER_AO 0x00000004 /* Address Only transfer type */ +#define AER_DTO 0x00000002 /* Data time out */ +#define AER_ATO 0x00000001 /* Address time out */ + +/* AEATR - Arbiter Event Address Register + */ +#define AEATR_EVENT 0x07000000 /* Event type */ +#define AEATR_MSTR_ID 0x001F0000 /* Master Id */ +#define AEATR_TBST 0x00000800 /* Transfer burst */ +#define AEATR_TSIZE 0x00000700 /* Transfer Size */ +#define AEATR_TTYPE 0x0000001F /* Transfer Type */ + +/* RSR - Reset Status Register + */ +#define RSR_SWSR 0x00002000 /* software soft reset */ +#define RSR_SWSR_SHIFT 13 +#define RSR_SWHR 0x00001000 /* software hard reset */ +#define RSR_SWHR_SHIFT 12 +#define RSR_JHRS 0x00000200 /* jtag hreset */ +#define RSR_JHRS_SHIFT 9 +#define RSR_JSRS 0x00000100 /* jtag sreset status */ +#define RSR_JSRS_SHIFT 8 +#define RSR_CSHR 0x00000010 /* checkstop reset status */ +#define RSR_CSHR_SHIFT 4 +#define RSR_SWRS 0x00000008 /* software watchdog reset status */ +#define RSR_SWRS_SHIFT 3 +#define RSR_BMRS 0x00000004 /* bus monitop reset status */ +#define RSR_BMRS_SHIFT 2 +#define RSR_SRS 0x00000002 /* soft reset status */ +#define RSR_SRS_SHIFT 1 +#define RSR_HRS 0x00000001 /* hard reset status */ +#define RSR_HRS_SHIFT 0 +#define RSR_RES ~(RSR_SWSR | RSR_SWHR |\ + RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\ + RSR_BMRS | RSR_SRS | RSR_HRS) +/* RMR - Reset Mode Register + */ +#define RMR_CSRE 0x00000001 /* checkstop reset enable */ +#define RMR_CSRE_SHIFT 0 +#define RMR_RES ~(RMR_CSRE) + +/* RCR - Reset Control Register + */ +#define RCR_SWHR 0x00000002 /* software hard reset */ +#define RCR_SWSR 0x00000001 /* software soft reset */ +#define RCR_RES ~(RCR_SWHR | RCR_SWSR) + +/* RCER - Reset Control Enable Register + */ +#define RCER_CRE 0x00000001 /* software hard reset */ +#define RCER_RES ~(RCER_CRE) + +/* SPMR - System PLL Mode Register + */ +#define SPMR_SPMF 0x0F000000 +#define SPMR_SPMF_SHIFT 24 +#define SPMR_CPMF 0x000F0000 +#define SPMR_CPMF_SHIFT 16 + +/* SCFR1 System Clock Frequency Register 1 + */ +#define SCFR1_IPS_DIV 0x2 +#define SCFR1_IPS_DIV_MASK 0x03800000 +#define SCFR1_IPS_DIV_SHIFT 23 + +/* SCFR2 System Clock Frequency Register 2 + */ +#define SCFR2_SYS_DIV 0xFC000000 +#define SCFR2_SYS_DIV_SHIFT 26 + +/* SCCR - System Clock Control Registers + */ + +/* System Clock Control Register 1 commands */ +#define CLOCK_SCCR1_CFG_EN 0x80000000 +#define CLOCK_SCCR1_LPC_EN 0x40000000 +#define CLOCK_SCCR1_NFC_EN 0x20000000 +#define CLOCK_SCCR1_PATA_EN 0x10000000 +#define CLOCK_SCCR1_PSC_EN(cn) (0x08000000 >> (cn)) +#define CLOCK_SCCR1_PSCFIFO_EN 0x00008000 +#define CLOCK_SCCR1_SATA_EN 0x00004000 +#define CLOCK_SCCR1_FEC_EN 0x00002000 +#define CLOCK_SCCR1_TPR_EN 0x00001000 +#define CLOCK_SCCR1_PCI_EN 0x00000800 +#define CLOCK_SCCR1_DDR_EN 0x00000400 + +/* System Clock Control Register 2 commands */ +#define CLOCK_SCCR2_DIU_EN 0x80000000 +#define CLOCK_SCCR2_AXE_EN 0x40000000 +#define CLOCK_SCCR2_MEM_EN 0x20000000 +#define CLOCK_SCCR2_USB2_EN 0x10000000 +#define CLOCK_SCCR2_USB1_EN 0x08000000 +#define CLOCK_SCCR2_I2C_EN 0x04000000 +#define CLOCK_SCCR2_BDLC_EN 0x02000000 +#define CLOCK_SCCR2_SDHC_EN 0x01000000 +#define CLOCK_SCCR2_SPDIF_EN 0x00800000 +#define CLOCK_SCCR2_MBX_BUS_EN 0x00400000 +#define CLOCK_SCCR2_MBX_EN 0x00200000 +#define CLOCK_SCCR2_MBX_3D_EN 0x00100000 +#define CLOCK_SCCR2_IIM_EN 0x00080000 + +/* PSC FIFO Command values */ +#define PSC_FIFO_RESET_SLICE 0x80 +#define PSC_FIFO_ENABLE_SLICE 0x01 + +/* PSC FIFO Controller Command values */ +#define FIFOC_ENABLE_CLOCK_GATE 0x01 +#define FIFOC_DISABLE_CLOCK_GATE 0x00 + +/* PSC FIFO status */ +#define PSC_FIFO_EMPTY 0x01 + +/* PSC Command values */ +#define PSC_RX_ENABLE 0x01 +#define PSC_RX_DISABLE 0x02 +#define PSC_TX_ENABLE 0x04 +#define PSC_TX_DISABLE 0x08 +#define PSC_SEL_MODE_REG_1 0x10 +#define PSC_RST_RX 0x20 +#define PSC_RST_TX 0x30 +#define PSC_RST_ERR_STAT 0x40 +#define PSC_RST_BRK_CHG_INT 0x50 +#define PSC_START_BRK 0x60 +#define PSC_STOP_BRK 0x70 + +/* PSC status register bits */ +#define PSC_SR_CDE 0x0080 +#define PSC_SR_TXEMP 0x0800 +#define PSC_SR_OE 0x1000 +#define PSC_SR_PE 0x2000 +#define PSC_SR_FE 0x4000 +#define PSC_SR_RB 0x8000 + +/* PSC mode fields */ +#define PSC_MODE_5_BITS 0x00 +#define PSC_MODE_6_BITS 0x01 +#define PSC_MODE_7_BITS 0x02 +#define PSC_MODE_8_BITS 0x03 +#define PSC_MODE_PAREVEN 0x00 +#define PSC_MODE_PARODD 0x04 +#define PSC_MODE_PARFORCE 0x08 +#define PSC_MODE_PARNONE 0x10 +#define PSC_MODE_ENTIMEOUT 0x20 +#define PSC_MODE_RXRTS 0x80 +#define PSC_MODE_1_STOPBIT 0x07 + +/* + * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs + * + * NOTE: individual PSC units are free to use whatever area (and size) of the + * FIFOC internal memory, so make sure memory areas for FIFO slices used by + * different PSCs do not overlap! + * + * Overall size of FIFOC memory is not documented in the MPC5121e RM, but + * tests indicate that it is 1024 words total. + */ +#define FIFOC_PSC0_TX_SIZE 0x0 /* number of 4-byte words for FIFO slice */ +#define FIFOC_PSC0_TX_ADDR 0x0 +#define FIFOC_PSC0_RX_SIZE 0x0 +#define FIFOC_PSC0_RX_ADDR 0x0 + +#define FIFOC_PSC1_TX_SIZE 0x0 +#define FIFOC_PSC1_TX_ADDR 0x0 +#define FIFOC_PSC1_RX_SIZE 0x0 +#define FIFOC_PSC1_RX_ADDR 0x0 + +#define FIFOC_PSC2_TX_SIZE 0x0 +#define FIFOC_PSC2_TX_ADDR 0x0 +#define FIFOC_PSC2_RX_SIZE 0x0 +#define FIFOC_PSC2_RX_ADDR 0x0 + +#define FIFOC_PSC3_TX_SIZE 0x04 +#define FIFOC_PSC3_TX_ADDR 0x0 +#define FIFOC_PSC3_RX_SIZE 0x04 +#define FIFOC_PSC3_RX_ADDR 0x10 + +#define FIFOC_PSC4_TX_SIZE 0x0 +#define FIFOC_PSC4_TX_ADDR 0x0 +#define FIFOC_PSC4_RX_SIZE 0x0 +#define FIFOC_PSC4_RX_ADDR 0x0 + +#define FIFOC_PSC5_TX_SIZE 0x0 +#define FIFOC_PSC5_TX_ADDR 0x0 +#define FIFOC_PSC5_RX_SIZE 0x0 +#define FIFOC_PSC5_RX_ADDR 0x0 + +#define FIFOC_PSC6_TX_SIZE 0x0 +#define FIFOC_PSC6_TX_ADDR 0x0 +#define FIFOC_PSC6_RX_SIZE 0x0 +#define FIFOC_PSC6_RX_ADDR 0x0 + +#define FIFOC_PSC7_TX_SIZE 0x0 +#define FIFOC_PSC7_TX_ADDR 0x0 +#define FIFOC_PSC7_RX_SIZE 0x0 +#define FIFOC_PSC7_RX_ADDR 0x0 + +#define FIFOC_PSC8_TX_SIZE 0x0 +#define FIFOC_PSC8_TX_ADDR 0x0 +#define FIFOC_PSC8_RX_SIZE 0x0 +#define FIFOC_PSC8_RX_ADDR 0x0 + +#define FIFOC_PSC9_TX_SIZE 0x0 +#define FIFOC_PSC9_TX_ADDR 0x0 +#define FIFOC_PSC9_RX_SIZE 0x0 +#define FIFOC_PSC9_RX_ADDR 0x0 + +#define FIFOC_PSC10_TX_SIZE 0x0 +#define FIFOC_PSC10_TX_ADDR 0x0 +#define FIFOC_PSC10_RX_SIZE 0x0 +#define FIFOC_PSC10_RX_ADDR 0x0 + +#define FIFOC_PSC11_TX_SIZE 0x0 +#define FIFOC_PSC11_TX_ADDR 0x0 +#define FIFOC_PSC11_RX_SIZE 0x0 +#define FIFOC_PSC11_RX_ADDR 0x0 + +/* IO Control Register + */ + +/* Indexes in regs array */ +#define MEM_IDX 0x00 +#define SPDIF_TXCLOCK_IDX 0x73 +#define SPDIF_TX_IDX 0x74 +#define SPDIF_RX_IDX 0x75 +#define PSC0_0_IDX 0x83 +#define PSC0_1_IDX 0x84 +#define PSC0_2_IDX 0x85 +#define PSC0_3_IDX 0x86 +#define PSC0_4_IDX 0x87 +#define PSC1_0_IDX 0x88 +#define PSC1_1_IDX 0x89 +#define PSC1_2_IDX 0x8a +#define PSC1_3_IDX 0x8b +#define PSC1_4_IDX 0x8c +#define PSC2_0_IDX 0x8d +#define PSC2_1_IDX 0x8e +#define PSC2_2_IDX 0x8f +#define PSC2_3_IDX 0x90 +#define PSC2_4_IDX 0x91 + +#define IOCTRL_FUNCMUX_SHIFT 7 +#define IOCTRL_FUNCMUX_FEC 1 +#define IOCTRL_MUX_FEC (IOCTRL_FUNCMUX_FEC << IOCTRL_FUNCMUX_SHIFT) + +/* Set for DDR */ +#define IOCTRL_MUX_DDR 0x00000036 + + /* Register Offset Base */ +#define MPC512X_FEC (CFG_IMMR + 0x02800) + +/* Number of I2C buses */ +#define I2C_BUS_CNT 3 + +/* I2Cn control register bits */ +#define I2C_EN 0x80 +#define I2C_IEN 0x40 +#define I2C_STA 0x20 +#define I2C_TX 0x10 +#define I2C_TXAK 0x08 +#define I2C_RSTA 0x04 +#define I2C_INIT_MASK (I2C_EN | I2C_STA | I2C_TX | I2C_RSTA) + +/* I2Cn status register bits */ +#define I2C_CF 0x80 +#define I2C_AAS 0x40 +#define I2C_BB 0x20 +#define I2C_AL 0x10 +#define I2C_SRW 0x04 +#define I2C_IF 0x02 +#define I2C_RXAK 0x01 + +#endif /* __MPC512X_H__ */ diff --git a/net/eth.c b/net/eth.c index 9fb3a10edb8..68e2c54b2ea 100644 --- a/net/eth.c +++ b/net/eth.c @@ -40,6 +40,7 @@ extern int eth_3com_initialize(bd_t*); extern int fec_initialize(bd_t*); extern int inca_switch_initialize(bd_t*); extern int mpc5xxx_fec_initialize(bd_t*); +extern int mpc512x_fec_initialize(bd_t*); extern int mpc8220_fec_initialize(bd_t*); extern int mv6436x_eth_initialize(bd_t *); extern int mv6446x_eth_initialize(bd_t *); @@ -168,6 +169,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_MPC5xxx_FEC) mpc5xxx_fec_initialize(bis); #endif +#if defined(CONFIG_MPC512x_FEC) + mpc512x_fec_initialize (bis); +#endif #if defined(CONFIG_MPC8220_FEC) mpc8220_fec_initialize(bis); #endif -- cgit v1.3.1 From cdd917a43da6fa7fc8f54a3cc9f420ce5ecf3197 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 2 Aug 2007 00:48:45 +0200 Subject: Fix build errors and warnings / code cleanup. Signed-off-by: Wolfgang Denk --- MAKEALL | 5 +- Makefile | 74 +++++++------ board/esd/cpci750/sdram_init.c | 2 +- board/freescale/common/pixis.c | 8 +- board/mpc8641hpcn/mpc8641hpcn.c | 3 +- board/mpc8641hpcn/sys_eeprom.c | 16 +-- board/spc1920/hpi.c | 8 ++ cpu/mpc86xx/interrupts.c | 6 +- include/configs/GEN860T.h | 2 +- include/configs/LANTEC.h | 1 + include/configs/MPC8260ADS.h | 5 +- include/configs/MPC8266ADS.h | 1 + include/configs/MPC8313ERDB.h | 2 +- include/configs/RBC823.h | 1 + include/configs/ep8260.h | 1 + include/configs/gw8260.h | 2 +- include/configs/hymod.h | 1 + include/configs/mpc7448hpc2.h | 4 +- include/configs/ppmc7xx.h | 237 ++++++++++++++++++++-------------------- include/configs/sbc8349.h | 2 +- 20 files changed, 202 insertions(+), 179 deletions(-) (limited to 'include') diff --git a/MAKEALL b/MAKEALL index a53500053e9..0721472c0ec 100755 --- a/MAKEALL +++ b/MAKEALL @@ -133,8 +133,9 @@ LIST_8260=" \ ######################################################################### LIST_83xx=" \ - MPC8313ERDB MPC832XEMDS MPC8349EMDS MPC8349ITX \ - MPC8349ITXGP MPC8360EMDS sbc8349 TQM834x \ + MPC8313ERDB_33 MPC8313ERDB_66 MPC832XEMDS MPC8349EMDS \ + MPC8349ITX MPC8349ITXGP MPC8360EMDS sbc8349 \ + TQM834x \ " diff --git a/Makefile b/Makefile index 3b71b21e22e..97dfb9d2ed8 100644 --- a/Makefile +++ b/Makefile @@ -1646,14 +1646,15 @@ r5200_config : unconfig MPC8313ERDB_33_config \ MPC8313ERDB_66_config: unconfig - @echo "" >include/config.h ; \ + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ if [ "$(findstring _33_,$@)" ] ; then \ - echo -n "...33M ..." ; \ - echo "#define CFG_33MHZ" >>include/config.h ; \ + echo "...33M ..." ; \ + echo "#define CFG_33MHZ" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _66_,$@)" ] ; then \ - echo -n "...66M..." ; \ - echo "#define CFG_66MHZ" >>include/config.h ; \ + echo "...66M..." ; \ + echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \ fi ; @$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb @@ -1661,23 +1662,24 @@ MPC832XEMDS_config \ MPC832XEMDS_HOST_33_config \ MPC832XEMDS_HOST_66_config \ MPC832XEMDS_SLAVE_config: unconfig - @echo "" >include/config.h ; \ + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ if [ "$(findstring _HOST_,$@)" ] ; then \ - echo -n "... PCI HOST " ; \ - echo "#define CONFIG_PCI" >>include/config.h ; \ + echo "... PCI HOST " ; \ + echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _SLAVE_,$@)" ] ; then \ echo "...PCI SLAVE 66M" ; \ - echo "#define CONFIG_PCI" >>include/config.h ; \ - echo "#define CONFIG_PCISLAVE" >>include/config.h ; \ + echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ + echo "#define CONFIG_PCISLAVE" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _33_,$@)" ] ; then \ - echo -n "...33M ..." ; \ - echo "#define PCI_33M" >>include/config.h ; \ + echo "...33M ..." ; \ + echo "#define PCI_33M" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _66_,$@)" ] ; then \ - echo -n "...66M..." ; \ - echo "#define PCI_66M" >>include/config.h ; \ + echo "...66M..." ; \ + echo "#define PCI_66M" >>$(obj)include/config.h ; \ fi ; @$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds @@ -1702,23 +1704,24 @@ MPC8360EMDS_config \ MPC8360EMDS_HOST_33_config \ MPC8360EMDS_HOST_66_config \ MPC8360EMDS_SLAVE_config: unconfig - @echo "" >include/config.h ; \ + @mkdir -p $(obj)include + @echo "" >$(obj)include/config.h ; \ if [ "$(findstring _HOST_,$@)" ] ; then \ - echo -n "... PCI HOST " ; \ - echo "#define CONFIG_PCI" >>include/config.h ; \ + echo "... PCI HOST " ; \ + echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _SLAVE_,$@)" ] ; then \ echo "...PCI SLAVE 66M" ; \ - echo "#define CONFIG_PCI" >>include/config.h ; \ - echo "#define CONFIG_PCISLAVE" >>include/config.h ; \ + echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ + echo "#define CONFIG_PCISLAVE" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _33_,$@)" ] ; then \ - echo -n "...33M ..." ; \ - echo "#define PCI_33M" >>include/config.h ; \ + echo "...33M ..." ; \ + echo "#define PCI_33M" >>$(obj)include/config.h ; \ fi ; \ if [ "$(findstring _66_,$@)" ] ; then \ - echo -n "...66M..." ; \ - echo "#define PCI_66M" >>include/config.h ; \ + echo "...66M..." ; \ + echo "#define PCI_66M" >>$(obj)include/config.h ; \ fi ; @$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds @@ -1744,10 +1747,10 @@ MPC8540EVAL_66_slave_config: unconfig @mkdir -p $(obj)include @echo "" >$(obj)include/config.h ; \ if [ "$(findstring _33_,$@)" ] ; then \ - echo -n "... 33 MHz PCI" ; \ + echo "... 33 MHz PCI" ; \ else \ echo "#define CONFIG_SYSCLK_66M" >>$(obj)include/config.h ; \ - echo -n "... 66 MHz PCI" ; \ + echo "... 66 MHz PCI" ; \ fi ; \ if [ "$(findstring _slave_,$@)" ] ; then \ echo "#define CONFIG_PCI_SLAVE" >>$(obj)include/config.h ; \ @@ -2008,13 +2011,13 @@ omap1610h2_cs3boot_config \ omap1610h2_cs_autoboot_config: unconfig @mkdir -p $(obj)include @if [ "$(findstring _cs0boot_, $@)" ] ; then \ - echo "#define CONFIG_CS0_BOOT" >> .$(obj)/include/config.h ; \ + echo "#define CONFIG_CS0_BOOT" >> .$(obj)include/config.h ; \ echo "... configured for CS0 boot"; \ elif [ "$(findstring _cs_autoboot_, $@)" ] ; then \ - echo "#define CONFIG_CS_AUTOBOOT" >> $(obj)./include/config.h ; \ + echo "#define CONFIG_CS_AUTOBOOT" >> $(obj)include/config.h ; \ echo "... configured for CS_AUTO boot"; \ else \ - echo "#define CONFIG_CS3_BOOT" >> $(obj)./include/config.h ; \ + echo "#define CONFIG_CS3_BOOT" >> $(obj)include/config.h ; \ echo "... configured for CS3 boot"; \ fi; @$(MKCONFIG) -a $(call xtract_omap1610xxx,$@) arm arm926ejs omap1610inn NULL omap @@ -2183,11 +2186,12 @@ logodl_config : unconfig pdnb3_config \ scpu_config: unconfig + @mkdir -p $(obj)include @if [ "$(findstring scpu_,$@)" ] ; then \ - echo "#define CONFIG_SCPU" >>include/config.h ; \ + echo "#define CONFIG_SCPU" >>$(obj)include/config.h ; \ echo "... on SCPU board variant" ; \ else \ - >include/config.h ; \ + >$(obj)include/config.h ; \ fi @$(MKCONFIG) -a pdnb3 arm ixp pdnb3 prodrive @@ -2409,13 +2413,15 @@ suzaku_config: unconfig @$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno ml401_config: unconfig - @ >include/config.h - @echo "#define CONFIG_ML401 1" >> include/config.h + @mkdir -p $(obj)include + @ >$(obj)include/config.h + @echo "#define CONFIG_ML401 1" >> $(obj)include/config.h @$(MKCONFIG) -a $(@:_config=) microblaze microblaze ml401 xilinx xupv2p_config: unconfig - @ >include/config.h - @echo "#define CONFIG_XUPV2P 1" >> include/config.h + @mkdir -p $(obj)include + @ >$(obj)include/config.h + @echo "#define CONFIG_XUPV2P 1" >> $(obj)include/config.h @$(MKCONFIG) -a $(@:_config=) microblaze microblaze xupv2p xilinx ######################################################################### diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c index c094755351c..78d18801854 100644 --- a/board/esd/cpci750/sdram_init.c +++ b/board/esd/cpci750/sdram_init.c @@ -1252,7 +1252,7 @@ static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) /* sets up the GT properly with information passed in */ int setup_sdram (AUX_MEM_DIMM_INFO * info) { - ulong tmp, check; + ulong tmp; ulong tmp_sdram_mode = 0; /* 0x141c */ ulong tmp_dunit_control_low = 0; /* 0x1404 */ int i; diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c index af98157dfd7..99cc2ee197e 100644 --- a/board/freescale/common/pixis.c +++ b/board/freescale/common/pixis.c @@ -321,10 +321,10 @@ static ulong strfractoint(uchar *strptr) mulconst = 1; for (i = 0; i < decarr_len; i++) mulconst *= 10; - decval = simple_strtoul(decarr, NULL, 10); + decval = simple_strtoul((char *)decarr, NULL, 10); } - intval = simple_strtoul(intarr, NULL, 10); + intval = simple_strtoul((char *)intarr, NULL, 10); intval = intval * mulconst; retval = intval + decval; @@ -362,7 +362,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10)); - corepll = strfractoint(argv[3]); + corepll = strfractoint((uchar *)argv[3]); val = val + set_px_corepll(corepll); val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10)); if (val == 3) { @@ -410,7 +410,7 @@ pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) read_from_px_regs(0); read_from_px_regs_altbank(0); val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10)); - corepll = strfractoint(argv[4]); + corepll = strfractoint((uchar *)argv[4]); val = val + set_px_corepll(corepll); val = val + set_px_mpxpll(simple_strtoul(argv[5], NULL, 10)); diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 7d7e2afad31..5e02cc5a5e6 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -63,9 +63,10 @@ int checkboard(void) uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; +#ifdef DEBUG uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); - +#endif if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || io_sel == 7 || io_sel == 0xF) && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { diff --git a/board/mpc8641hpcn/sys_eeprom.c b/board/mpc8641hpcn/sys_eeprom.c index 74e2a3d46ff..7bc663bba46 100644 --- a/board/mpc8641hpcn/sys_eeprom.c +++ b/board/mpc8641hpcn/sys_eeprom.c @@ -68,7 +68,7 @@ int mac_show(void) mac_data.date[5], mac_data.date[6]); for (i = 0; i < 8; i++) { - sprintf(ethaddr[i], + sprintf((char *)ethaddr[i], "%02x:%02x:%02x:%02x:%02x:%02x", mac_data.mac[i][0], mac_data.mac[i][1], @@ -79,10 +79,10 @@ int mac_show(void) printf("MAC %d %s\n", i, ethaddr[i]); } - setenv("ethaddr", ethaddr[0]); - setenv("eth1addr", ethaddr[1]); - setenv("eth2addr", ethaddr[2]); - setenv("eth3addr", ethaddr[3]); + setenv("ethaddr", (char *)ethaddr[0]); + setenv("eth1addr", (char *)ethaddr[1]); + setenv("eth2addr", (char *)ethaddr[2]); + setenv("eth3addr", (char *)ethaddr[3]); return 0; } @@ -236,7 +236,7 @@ int mac_read_from_eeprom(void) } else { for (i = 0; i < 4; i++) { if (memcmp(&mac_data.mac[i], "\0\0\0\0\0\0", 6)) { - sprintf(ethaddr[i], + sprintf((char *)ethaddr[i], "%02x:%02x:%02x:%02x:%02x:%02x", mac_data.mac[i][0], mac_data.mac[i][1], @@ -244,10 +244,10 @@ int mac_read_from_eeprom(void) mac_data.mac[i][3], mac_data.mac[i][4], mac_data.mac[i][5]); - sprintf(enetvar, + sprintf((char *)enetvar, i ? "eth%daddr" : "ethaddr", i); - setenv(enetvar, ethaddr[i]); + setenv((char *)enetvar, (char *)ethaddr[i]); } } } diff --git a/board/spc1920/hpi.c b/board/spc1920/hpi.c index 3c36f7911bc..cd7799b277b 100644 --- a/board/spc1920/hpi.c +++ b/board/spc1920/hpi.c @@ -122,7 +122,9 @@ const uint dsp_table_fast[] = #define TINY_AUTOINC_BASE_ADDR 0x0 static int hpi_activate(void); +#if 0 static void hpi_inactivate(void); +#endif static void dsp_reset(void); static int hpi_write_inc(u32 addr, u32 *data, u32 count); @@ -133,7 +135,9 @@ static u32 hpi_read_noinc(u32 addr); int hpi_test(void); static int hpi_write_addr_test(u32 addr); static int hpi_read_write_test(u32 addr, u32 data); +#ifdef DO_TINY_TEST static int hpi_tiny_autoinc_test(void); +#endif /* DO_TINY_TEST */ #endif /* CONFIG_SPC1920_HPI_TEST */ @@ -185,6 +189,7 @@ static int hpi_activate(void) return 0; } +#if 0 /* turn off the host port interface */ static void hpi_inactivate(void) { @@ -200,6 +205,7 @@ static void hpi_inactivate(void) /* currently always on TBD */ } +#endif /* reset the DSP */ static void dsp_reset(void) @@ -570,6 +576,7 @@ static int hpi_read_write_test(u32 addr, u32 data) return 0; } +#ifdef DO_TINY_TEST static int hpi_tiny_autoinc_test(void) { int i; @@ -599,5 +606,6 @@ static int hpi_tiny_autoinc_test(void) } return 0; } +#endif /* DO_TINY_TEST */ #endif /* CONFIG_SPC1920_HPI_TEST */ diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index 49820bbd811..08e0675fee4 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -71,7 +71,7 @@ static __inline__ void set_dec(unsigned long val) } /* interrupt is not supported yet */ -int interrupt_init_cpu(unsigned *decrementer_count) +int interrupt_init_cpu(unsigned long *decrementer_count) { return 0; } @@ -107,7 +107,7 @@ int interrupt_init(void) return ret; decrementer_count = get_tbclk() / CFG_HZ; - debug("interrupt init: tbclk() = %d MHz, decrementer_count = %d\n", + debug("interrupt init: tbclk() = %d MHz, decrementer_count = %ld\n", (get_tbclk() / 1000000), decrementer_count); @@ -158,7 +158,7 @@ void timer_interrupt(struct pt_regs *regs) timestamp++; - ppcDcbf(×tamp); + ppcDcbf((unsigned long)×tamp); /* Restore Decrementer Count */ set_dec(decrementer_count); diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index d88124a3b42..bfbf3a839cf 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -248,7 +248,7 @@ #endif #ifdef CONFIG_POST -u #define CONFIG_CMD_DIAG +#define CONFIG_CMD_DIAG #endif /* diff --git a/include/configs/LANTEC.h b/include/configs/LANTEC.h index 2191c7b99c1..46edd08a91f 100644 --- a/include/configs/LANTEC.h +++ b/include/configs/LANTEC.h @@ -106,6 +106,7 @@ #undef CONFIG_CMD_IRQ #undef CONFIG_CMD_JFFS2 #undef CONFIG_CMD_KGDB +#undef CONFIG_CMD_MFSL #undef CONFIG_CMD_MII #undef CONFIG_CMD_MMC #undef CONFIG_CMD_NAND diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index f3e5330c779..713518d0da2 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -227,6 +227,7 @@ #undef CONFIG_CMD_HWFLOW #undef CONFIG_CMD_IDE #undef CONFIG_CMD_KGDB +#undef CONFIG_CMD_MFSL #undef CONFIG_CMD_MMC #undef CONFIG_CMD_NAND #undef CONFIG_CMD_PCMCIA @@ -405,9 +406,9 @@ #define CFG_BCR 0x100C0000 #define CFG_SIUMCR 0x0A200000 #define CFG_SCCR SCCR_DFBRG01 -#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00001801 +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801) #define CFG_OR0_PRELIM 0xFF800876 -#define CFG_BR1_PRELIM CFG_BCSR | 0x00001801 +#define CFG_BR1_PRELIM (CFG_BCSR | 0x00001801) #define CFG_OR1_PRELIM 0xFFFF8010 /*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/ diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index 3a6c977a606..14b041e3aec 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -165,6 +165,7 @@ #undef CONFIG_CMD_IDE #undef CONFIG_CMD_JFFS2 #undef CONFIG_CMD_KGDB +#undef CONFIG_CMD_MFSL #undef CONFIG_CMD_MMC #undef CONFIG_CMD_NAND #undef CONFIG_CMD_PCMCIA diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 45a7d81792d..81db96f4661 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -265,7 +265,7 @@ #define CONFIG_I2C_CMD_TREE #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index 5e12dabecf7..2f6de815514 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -119,6 +119,7 @@ #undef CONFIG_CMD_IRQ #undef CONFIG_CMD_JFFS2 #undef CONFIG_CMD_MII +#undef CONFIG_CMD_MFSL #undef CONFIG_CMD_MMC #undef CONFIG_CMD_NAND #undef CONFIG_CMD_PCI diff --git a/include/configs/ep8260.h b/include/configs/ep8260.h index f412ec8ed80..025c24960d2 100644 --- a/include/configs/ep8260.h +++ b/include/configs/ep8260.h @@ -321,6 +321,7 @@ #undef CONFIG_CMD_JFFS2 #undef CONFIG_CMD_KGDB #undef CONFIG_CMD_MII +#undef CONFIG_CMD_MFSL #undef CONFIG_CMD_MMC #undef CONFIG_CMD_NAND #undef CONFIG_CMD_PCI diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index 79e6aa1ba6c..ff5724082d0 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -294,7 +294,7 @@ #define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_BOOTFILESIZE -#definef CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS /* undef this to save memory */ #define CFG_LONGHELP diff --git a/include/configs/hymod.h b/include/configs/hymod.h index b789067f81d..2f64ec238c6 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -199,6 +199,7 @@ #undef CONFIG_CMD_IDE #undef CONFIG_CMD_JFFS2 #undef CONFIG_CMD_NAND +#undef CONFIG_CMD_MFSL #undef CONFIG_CMD_MMC #undef CONFIG_CMD_PCMCIA #undef CONFIG_CMD_PCI diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index 4237228bebe..f4f33f3e089 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -375,9 +375,9 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1/* Flash can be at one of two addresses */ +#define CFG_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */ #define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ -#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2} +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, /* CFG_FLASH_BASE2 */ } #define CFG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI diff --git a/include/configs/ppmc7xx.h b/include/configs/ppmc7xx.h index 6e451d8b6cb..fe7de7bed0f 100644 --- a/include/configs/ppmc7xx.h +++ b/include/configs/ppmc7xx.h @@ -25,29 +25,30 @@ /* * Debug * - * DEBUG - Define this is you want extra debug info - * GTREGREAD - Required to build with debug - * do_bdinfo - Required to build with debug + * DEBUG - Define this is you want extra debug info + * GTREGREAD - Required to build with debug + * do_bdinfo - Required to build with debug */ #undef DEBUG -#define GTREGREAD(x) 0xFFFFFFFF +#ifdef DEBUG +#define GTREGREAD(x) 0xFFFFFFFF #define do_bdinfo(a,b,c,d) - +#endif /* * CPU type * - * CONFIG_7xx - We have a 750 or 755 CPU - * CONFIG_74xx - We have a 7400 CPU - * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400) - * CONFIG_BUS_CLK - System bus clock in Hz + * CONFIG_7xx - We have a 750 or 755 CPU + * CONFIG_74xx - We have a 7400 CPU + * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400) + * CONFIG_BUS_CLK - System bus clock in Hz */ #define CONFIG_7xx #undef CONFIG_74xx #undef CONFIG_ALTIVEC -#define CONFIG_BUS_CLK 66000000 +#define CONFIG_BUS_CLK 66000000 /* @@ -97,18 +98,18 @@ * Serial configuration * * CONFIG_CONS_INDEX - Serial console port number (COM1) - * CONFIG_BAUDRATE - Serial speed + * CONFIG_BAUDRATE - Serial speed */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 9600 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 9600 /* * PCI config * - * CONFIG_PCI - Enable PCI bus - * CONFIG_PCI_PNP - Enable Plug & Play support + * CONFIG_PCI - Enable PCI bus + * CONFIG_PCI_PNP - Enable Plug & Play support * CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup */ @@ -120,9 +121,9 @@ /* * Network config * - * CONFIG_NET_MULTI - Support for multiple network interfaces - * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller - * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM + * CONFIG_NET_MULTI - Support for multiple network interfaces + * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller + * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM */ #define CONFIG_NET_MULTI @@ -145,7 +146,7 @@ * Boot config * * CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot - * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec) + * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec) */ #define CONFIG_BOOTCOMMAND \ @@ -169,79 +170,79 @@ * * This board runs in a standard CHRP (Map-B) configuration. * - * Type Start End Size Width Chip Sel + * Type Start End Size Width Chip Sel * ----------- ----------- ----------- ------- ------- -------- - * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0 - * User LED's 0x78000000 RCS3 - * UART 0x7C000000 RCS2 - * Mailbox 0xFF000000 RCS1 - * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0 + * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0 + * User LED's 0x78000000 RCS3 + * UART 0x7C000000 RCS2 + * Mailbox 0xFF000000 RCS1 + * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0 * * Flash sectors are laid out as follows. * - * Sector Start End Size Comments + * Sector Start End Size Comments * ------- ----------- ----------- ------- ----------- - * 0 0xFFC00000 0xFFC3FFFF 256KB - * 1 0xFFC40000 0xFFC7FFFF 256KB - * 2 0xFFC80000 0xFFCBFFFF 256KB - * 3 0xFFCC0000 0xFFCFFFFF 256KB - * 4 0xFFD00000 0xFFD3FFFF 256KB - * 5 0xFFD40000 0xFFD7FFFF 256KB - * 6 0xFFD80000 0xFFDBFFFF 256KB - * 7 0xFFDC0000 0xFFDFFFFF 256KB - * 8 0xFFE00000 0xFFE3FFFF 256KB - * 9 0xFFE40000 0xFFE7FFFF 256KB - * 10 0xFFE80000 0xFFEBFFFF 256KB - * 11 0xFFEC0000 0xFFEFFFFF 256KB - * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here - * 13 0xFFF40000 0xFFF7FFFF 256KB - * 14 0xFFF80000 0xFFFBFFFF 256KB - * 15 0xFFFC0000 0xFFFDFFFF 128KB - * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here - * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here - * 18 0xFFFF0000 0xFFFFFFFF 64KB + * 0 0xFFC00000 0xFFC3FFFF 256KB + * 1 0xFFC40000 0xFFC7FFFF 256KB + * 2 0xFFC80000 0xFFCBFFFF 256KB + * 3 0xFFCC0000 0xFFCFFFFF 256KB + * 4 0xFFD00000 0xFFD3FFFF 256KB + * 5 0xFFD40000 0xFFD7FFFF 256KB + * 6 0xFFD80000 0xFFDBFFFF 256KB + * 7 0xFFDC0000 0xFFDFFFFF 256KB + * 8 0xFFE00000 0xFFE3FFFF 256KB + * 9 0xFFE40000 0xFFE7FFFF 256KB + * 10 0xFFE80000 0xFFEBFFFF 256KB + * 11 0xFFEC0000 0xFFEFFFFF 256KB + * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here + * 13 0xFFF40000 0xFFF7FFFF 256KB + * 14 0xFFF80000 0xFFFBFFFF 256KB + * 15 0xFFFC0000 0xFFFDFFFF 128KB + * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here + * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here + * 18 0xFFFF0000 0xFFFFFFFF 64KB */ /* * SDRAM config - see memory map details above. * - * CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero! - * CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s) + * CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero! + * CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s) */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_SDRAM_SIZE 0x04000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_SDRAM_SIZE 0x04000000 /* * Flash config - see memory map details above. * - * CFG_FLASH_BASE - Start address of flash memory - * CFG_FLASH_SIZE - Total size of contiguous flash mem + * CFG_FLASH_BASE - Start address of flash memory + * CFG_FLASH_SIZE - Total size of contiguous flash mem * CFG_FLASH_ERASE_TOUT - Erase timeout in ms * CFG_FLASH_WRITE_TOUT - Write timeout in ms * CFG_MAX_FLASH_BANKS - Number of banks of flash on board * CFG_MAX_FLASH_SECT - Number of sectors in a bank */ -#define CFG_FLASH_BASE 0xFFC00000 -#define CFG_FLASH_SIZE 0x00400000 +#define CFG_FLASH_BASE 0xFFC00000 +#define CFG_FLASH_SIZE 0x00400000 #define CFG_FLASH_ERASE_TOUT 250000 #define CFG_FLASH_WRITE_TOUT 5000 -#define CFG_MAX_FLASH_BANKS 1 -#define CFG_MAX_FLASH_SECT 19 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 19 /* * Monitor config - see memory map details above * - * CFG_MONITOR_BASE - Base address of monitor code - * CFG_MALLOC_LEN - Size of malloc pool (128KB) + * CFG_MONITOR_BASE - Base address of monitor code + * CFG_MALLOC_LEN - Size of malloc pool (128KB) */ -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MALLOC_LEN 0x20000 +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_LEN 0x20000 /* @@ -259,16 +260,16 @@ * CFG_PROMPT - Prompt string */ -#define CFG_BARGSIZE 1024 -#define CFG_BOOTMAPSZ 0x800000 -#define CFG_CBSIZE 1024 -#define CFG_LOAD_ADDR 0x100000 +#define CFG_BARGSIZE 1024 +#define CFG_BOOTMAPSZ 0x800000 +#define CFG_CBSIZE 1024 +#define CFG_LOAD_ADDR 0x100000 #define CFG_LONGHELP -#define CFG_MAXARGS 16 -#define CFG_MEMTEST_START 0x00040000 -#define CFG_MEMTEST_END 0x00040100 -#define CFG_PBSIZE 1024 -#define CFG_PROMPT "=> " +#define CFG_MAXARGS 16 +#define CFG_MEMTEST_START 0x00040000 +#define CFG_MEMTEST_END 0x00040100 +#define CFG_PBSIZE 1024 +#define CFG_PROMPT "=> " /* @@ -280,12 +281,12 @@ * CFG_ENV_SECT_SIZE - Size of sector containing env vars (32KB) */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR 0xFFFE0000 -#define CFG_ENV_SIZE 0x1000 -#define CFG_ENV_ADDR_REDUND 0xFFFE8000 -#define CFG_ENV_SIZE_REDUND 0x1000 -#define CFG_ENV_SECT_SIZE 0x8000 +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_ADDR 0xFFFE0000 +#define CFG_ENV_SIZE 0x1000 +#define CFG_ENV_ADDR_REDUND 0xFFFE8000 +#define CFG_ENV_SIZE_REDUND 0x1000 +#define CFG_ENV_SECT_SIZE 0x8000 /* @@ -296,15 +297,15 @@ * copied to top of RAM by the init code. * * CFG_INIT_RAM_ADDR - Address of Init RAM, above exception vect - * CFG_INIT_RAM_END - Size of Init RAM + * CFG_INIT_RAM_END - Size of Init RAM * CFG_GBL_DATA_SIZE - Ammount of RAM to reserve for global data * CFG_GBL_DATA_OFFSET - Start of global data, top of stack */ -#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000) -#define CFG_INIT_RAM_END 0x4000 -#define CFG_GBL_DATA_SIZE 128 -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000) +#define CFG_INIT_RAM_END 0x4000 +#define CFG_GBL_DATA_SIZE 128 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) /* @@ -341,71 +342,71 @@ * Cache config * * CFG_CACHELINE_SIZE - Size of a cache line (CPU specific) - * CFG_L2 - L2 cache enabled if defined - * L2_INIT - L2 cache init flags - * L2_ENABLE - L2 cache enable flags + * CFG_L2 - L2 cache enabled if defined + * L2_INIT - L2 cache init flags + * L2_ENABLE - L2 cache enable flags */ -#define CFG_CACHELINE_SIZE 32 +#define CFG_CACHELINE_SIZE 32 #undef CFG_L2 -#define L2_INIT 0 -#define L2_ENABLE 0 +#define L2_INIT 0 +#define L2_ENABLE 0 /* * Clocks config * - * CFG_BUS_HZ - Bus clock frequency in Hz - * CFG_BUS_CLK - As above (?) - * CFG_HZ - Decrementer freq in Hz + * CFG_BUS_HZ - Bus clock frequency in Hz + * CFG_BUS_CLK - As above (?) + * CFG_HZ - Decrementer freq in Hz */ -#define CFG_BUS_HZ CONFIG_BUS_CLK -#define CFG_BUS_CLK CONFIG_BUS_CLK -#define CFG_HZ 1000 +#define CFG_BUS_HZ CONFIG_BUS_CLK +#define CFG_BUS_CLK CONFIG_BUS_CLK +#define CFG_HZ 1000 /* * Serial port config * * CFG_BAUDRATE_TABLE - List of valid baud rates - * CFG_NS16550 - Include the NS16550 driver + * CFG_NS16550 - Include the NS16550 driver * CFG_NS16550_SERIAL - Include the serial (wrapper) driver - * CFG_NS16550_CLK - Frequency of reference clock + * CFG_NS16550_CLK - Frequency of reference clock * CFG_NS16550_REG_SIZE - 64-bit accesses to 8-bit port - * CFG_NS16550_COM1 - Base address of 1st serial port + * CFG_NS16550_COM1 - Base address of 1st serial port */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CFG_NS16550 #define CFG_NS16550_SERIAL -#define CFG_NS16550_CLK 3686400 +#define CFG_NS16550_CLK 3686400 #define CFG_NS16550_REG_SIZE -8 -#define CFG_NS16550_COM1 0x7C000000 +#define CFG_NS16550_COM1 0x7C000000 /* * PCI Config - Address Map B (CHRP) */ -#define CFG_PCI_MEMORY_BUS 0x00000000 -#define CFG_PCI_MEMORY_PHYS 0x00000000 -#define CFG_PCI_MEMORY_SIZE 0x40000000 -#define CFG_PCI_MEM_BUS 0x80000000 -#define CFG_PCI_MEM_PHYS 0x80000000 -#define CFG_PCI_MEM_SIZE 0x7D000000 -#define CFG_ISA_MEM_BUS 0x00000000 -#define CFG_ISA_MEM_PHYS 0xFD000000 -#define CFG_ISA_MEM_SIZE 0x01000000 -#define CFG_PCI_IO_BUS 0x00800000 -#define CFG_PCI_IO_PHYS 0xFE800000 -#define CFG_PCI_IO_SIZE 0x00400000 -#define CFG_ISA_IO_BUS 0x00000000 -#define CFG_ISA_IO_PHYS 0xFE000000 -#define CFG_ISA_IO_SIZE 0x00800000 +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x40000000 +#define CFG_PCI_MEM_BUS 0x80000000 +#define CFG_PCI_MEM_PHYS 0x80000000 +#define CFG_PCI_MEM_SIZE 0x7D000000 +#define CFG_ISA_MEM_BUS 0x00000000 +#define CFG_ISA_MEM_PHYS 0xFD000000 +#define CFG_ISA_MEM_SIZE 0x01000000 +#define CFG_PCI_IO_BUS 0x00800000 +#define CFG_PCI_IO_PHYS 0xFE800000 +#define CFG_PCI_IO_SIZE 0x00400000 +#define CFG_ISA_IO_BUS 0x00000000 +#define CFG_ISA_IO_PHYS 0xFE000000 +#define CFG_ISA_IO_SIZE 0x00800000 #define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS -#define CFG_ISA_IO CFG_ISA_IO_PHYS -#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS +#define CFG_ISA_IO CFG_ISA_IO_PHYS +#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS /* @@ -420,12 +421,12 @@ /* * Boot flags * - * BOOTFLAG_COLD - Indicates a power-on boot - * BOOTFLAG_WARM - Indicates a software reset + * BOOTFLAG_COLD - Indicates a power-on boot + * BOOTFLAG_WARM - Indicates a software reset */ -#define BOOTFLAG_COLD 0x01 -#define BOOTFLAG_WARM 0x02 +#define BOOTFLAG_COLD 0x01 +#define BOOTFLAG_WARM 0x02 #endif /* __CONFIG_H */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 83a81fec139..1831bef0de1 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -328,7 +328,7 @@ #define CONFIG_I2C_CMD_TREE #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F -#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ #define CFG_I2C1_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 #define CFG_I2C_OFFSET CFG_I2C2_OFFSET -- cgit v1.3.1 From b1b54e352028ed370c3aa95d6fdeb9d64c5d2f86 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 2 Aug 2007 21:27:46 +0200 Subject: Coding style cleanup, update CHANGELOG Signed-off-by: Wolfgang Denk --- CHANGELOG | 46 ++++++++++++++++++ board/ads5121/ads5121.c | 4 +- cpu/mpc512x/cpu_init.c | 2 +- cpu/mpc512x/fec.c | 52 ++++++++++----------- cpu/mpc512x/fec.h | 8 ++-- cpu/mpc512x/speed.c | 6 +-- cpu/mpc512x/start.S | 18 +++---- include/configs/ads5121.h | 117 +++++++++++++++++++++++----------------------- include/mpc512x.h | 2 +- 9 files changed, 151 insertions(+), 104 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index bcbf36e78d2..f8a04e6207e 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,49 @@ +commit 8993e54b6f397973794f3d6f47d3b3c0c98dd4f6 +Author: Rafal Jaworowski +Date: Fri Jul 27 14:43:59 2007 +0200 + + [ADS5121] Support for the ADS5121 board + + The following MPC5121e subsystems are supported: + + - low-level CPU init + - NOR Boot Flash (common CFI driver) + - DDR SDRAM + - FEC + - I2C + - Watchdog + + Signed-off-by: Grzegorz Bernacki + Signed-off-by: Rafal Jaworowski + Signed-off-by: Jan Wrobel + +commit 1863cfb7b100ba0ee3401799457a01dc058745f8 +Author: Rafal Jaworowski +Date: Fri Jul 27 14:22:04 2007 +0200 + + [PPC] Remove unused MSR_USER definition + + Signed-off-by: Rafal Jaworowski + +commit cc3023b9f95d7ac959a764471a65001062aecf41 +Author: Rafal Jaworowski +Date: Thu Jul 19 17:12:28 2007 +0200 + + Fix breakage of 8xx boards from recent commit. + + This patch fixes the negative consequences for 8xx of the recent + "ppc4xx: Clean up 440 exceptions handling" commit. + + Signed-off-by: Rafal Jaworowski + +commit 3a6cab844cf74f76639d795e0be8717e02c86af7 +Author: Wolfgang Denk +Date: Sat Jul 14 22:51:02 2007 +0200 + + Update CHANGELOG + + Signed-off-by: Wolfgang Denk + commit 011595307731a7a67a7445d107c279d031e8ab97 Author: Heiko Schocher Date: Sat Jul 14 01:06:58 2007 +0200 diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 0a99a34ac05..c8bfdb86921 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -114,7 +114,7 @@ long int fixed_sdram (void) * According to MPC5121e RM, configuring local access windows should * be followed by a dummy read of the config register that was * modified last and an isync - */ + */ i = im->sysconf.ddrlaw.ar; __asm__ __volatile__ ("isync"); @@ -183,6 +183,6 @@ int checkboard (void) uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02); printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", - brd_rev, cpld_rev); + brd_rev, cpld_rev); return 0; } diff --git a/cpu/mpc512x/cpu_init.c b/cpu/mpc512x/cpu_init.c index 566e08b0ddd..d6949f6bba0 100644 --- a/cpu/mpc512x/cpu_init.c +++ b/cpu/mpc512x/cpu_init.c @@ -76,7 +76,7 @@ void cpu_init_f (volatile immap_t * im) * * NOTICE: TB needs to be enabled as early as possible in order to * have udelay() working; if not enabled, usually leads to a hang, like - * during FLASH chip identification etc. + * during FLASH chip identification etc. */ im->sysconf.spcr |= SPCR_TBEN; } diff --git a/cpu/mpc512x/fec.c b/cpu/mpc512x/fec.c index f1b7a2563ed..1c87a53859d 100644 --- a/cpu/mpc512x/fec.c +++ b/cpu/mpc512x/fec.c @@ -77,20 +77,20 @@ static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec) * Trasmit BDs init */ for (ix = 0; ix < FEC_TBD_NUM; ix++) { - fec->bdBase->tbd[ix].status = 0; - } + fec->bdBase->tbd[ix].status = 0; + } - /* - * Have the last TBD to close the ring - */ - fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP; + /* + * Have the last TBD to close the ring + */ + fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP; - /* - * Initialize some indices - */ - fec->tbdIndex = 0; - fec->usedTbdIndex = 0; - fec->cleanTbdNum = FEC_TBD_NUM; + /* + * Initialize some indices + */ + fec->tbdIndex = 0; + fec->usedTbdIndex = 0; + fec->cleanTbdNum = FEC_TBD_NUM; return 0; } @@ -238,7 +238,7 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) fec->eth->r_cntrl = 0x05ee000c; /* Half-duplex, heartbeat disabled */ - fec->eth->x_cntrl = 0x00000000; + fec->eth->x_cntrl = 0x00000000; /* Enable MIB counters */ fec->eth->mib_control = 0x0; @@ -260,7 +260,7 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis) /* Initilize addresses and status words of BDs */ mpc512x_fec_bd_init (fec); - /* Descriptor polling active */ + /* Descriptor polling active */ fec->eth->r_des_active = 0x01000000; #if (DEBUG & 0x1) @@ -296,7 +296,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis) * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock * and do not drop the Preamble. */ - fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1; + fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1; /* * Reset PHY, then delay 300ns @@ -312,7 +312,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis) printf ("Forcing 10 Mbps ethernet link... "); #endif miiphy_read (dev->name, phyAddr, 0x1, &phyStatus); - + miiphy_write (dev->name, phyAddr, 0x0, 0x0180); timeout = 20; @@ -346,7 +346,7 @@ int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis) #if (DEBUG & 0x2) printf ("done.\n"); #endif - } else { /* MII100 */ + } else { /* MII100 */ /* * Set the auto-negotiation advertisement register bits */ @@ -487,7 +487,7 @@ static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data, pTbd->dataPointer = (uint32)eth_data; pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM; - + /* Activate transmit Buffer Descriptor polling */ fec->eth->x_des_active = 0x01000000; /* Descriptor polling active */ @@ -529,7 +529,7 @@ static int mpc512x_fec_recv (struct eth_device *dev) #if (DEBUG & 0x8) printf( "-" ); #endif - + /* * Check if any critical events have happened */ @@ -555,10 +555,10 @@ static int mpc512x_fec_recv (struct eth_device *dev) } if (!(pRbd->status & FEC_RBD_EMPTY)) { - if ((pRbd->status & FEC_RBD_LAST) && + if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) && ((pRbd->dataLength - 4) > 14)) { - + /* * Get buffer size */ @@ -635,7 +635,7 @@ int mpc512x_fec_initialize (bd_t * bis) * Initialize I\O pins */ reg = (uint32 *) &(im->io_ctrl.regs[PSC0_0_IDX]); - + for (i = 0; i < 15; i++) reg[i] = IOCTRL_MUX_FEC | 0x00000001; @@ -645,13 +645,13 @@ int mpc512x_fec_initialize (bd_t * bis) /* Clean up space FEC's MIB and FIFO RAM ...*/ memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400); - - /* + + /* * Malloc space for BDs (must be quad word-aligned) - * this pointer is lost, so cannot be freed + * this pointer is lost, so cannot be freed */ bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f); - fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0); + fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0); memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f); /* diff --git a/cpu/mpc512x/fec.h b/cpu/mpc512x/fec.h index 71459197a51..d2d877aa528 100644 --- a/cpu/mpc512x/fec.h +++ b/cpu/mpc512x/fec.h @@ -28,7 +28,7 @@ typedef struct ethernet_register_set { volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */ volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */ volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */ - + volatile uint32 RES1[3]; /* MBAR_ETH + 0x018-020 */ volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */ @@ -42,10 +42,10 @@ typedef struct ethernet_register_set { volatile uint32 RES4[7]; /* MBAR_ETH + 0x068-80 */ volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */ volatile uint32 r_hash; /* MBAR_ETH + 0x088 */ - + volatile uint32 RES5[14]; /* MBAR_ETH + 0x08c-0C0 */ volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */ - + volatile uint32 RES6[7]; /* MBAR_ETH + 0x0C8-0E0 */ volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */ volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */ @@ -63,7 +63,7 @@ typedef struct ethernet_register_set { volatile uint32 RES9[1]; /* MBAR_ETH + 0x148 */ volatile uint32 r_bound; /* MBAR_ETH + 0x14C */ volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */ - + volatile uint32 RES10[11]; /* MBAR_ETH + 0x154-17C */ volatile uint32 r_des_start; /* MBAR_ETH + 0x180 */ volatile uint32 x_des_start; /* MBAR_ETH + 0x184 */ diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c index 9a31155ed2d..a609827387b 100644 --- a/cpu/mpc512x/speed.c +++ b/cpu/mpc512x/speed.c @@ -79,14 +79,14 @@ int get_clocks (void) spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; spll = ref_clk * spmf_mult[spmf]; - + sys_div = (im->clk.scfr[1] & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT; sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0]; csb_clk = sys_clk / 2; - cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT; - core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1]; + cpmf = (im->clk.spmr & SPMR_CPMF) >> SPMR_CPMF_SHIFT; + core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1]; ips_div = (im->clk.scfr[0] & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT; if (ips_div != 0) { diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 8b749ac54e9..244c69b8124 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -208,8 +208,8 @@ boot_cold: */ /* Boot CS/CS0 window range */ - lis r3, CFG_IMMR@h - ori r3, r3, CFG_IMMR@l + lis r3, CFG_IMMR@h + ori r3, r3, CFG_IMMR@l lis r4, START_REG(CFG_FLASH_BASE) ori r4, r4, STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE) @@ -222,11 +222,11 @@ boot_cold: lis r4, START_REG(CFG_SRAM_BASE) & 0xff00 stw r4, SRAMBAR(r3) - /* + /* * According to MPC5121e RM, configuring local access windows should - * be followed by a dummy read of the config register that was + * be followed by a dummy read of the config register that was * modified last and an isync - */ + */ lwz r4, SRAMBAR(r3) isync @@ -235,11 +235,11 @@ boot_cold: * config register so no params can be set for it */ lis r3, (CFG_IMMR + LPC_OFFSET)@h - ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l + ori r3, r3, (CFG_IMMR + LPC_OFFSET)@l - lis r4, CFG_CS0_CFG@h - ori r4, r4, CFG_CS0_CFG@l - stw r4, CS0_CONFIG(r3) + lis r4, CFG_CS0_CFG@h + ori r4, r4, CFG_CS0_CFG@l + stw r4, CS0_CONFIG(r3) /* Master enable all CS's */ lis r4, CS_CTRL_ME@h diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index a1b8eefa02c..89564a90e9e 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -65,48 +65,49 @@ #define CFG_SDRAM_BASE CFG_DDR_BASE /* DDR Controller Configuration - -SYS_CFG: - [31:31] MDDRC Soft Reset: Diabled - [30:30] DRAM CKE pin: Enabled - [29:29] DRAM CLK: Enabled - [28:28] Command Mode: Enabled (For initialization only) - [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] - [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] - [20:19] Read Test: DON'T USE - [18:18] Self Refresh: Enabled - [17:17] 16bit Mode: Disabled - [16:13] Ready Delay: 2 - [12:12] Half DQS Delay: Disabled - [11:11] Quarter DQS Delay: Disabled - [10:08] Write Delay: 2 - [07:07] Early ODT: Disabled - [06:06] On DIE Termination: Disabled - [05:05] FIFO Overflow Clear: DON'T USE here - [04:04] FIFO Underflow Clear: DON'T USE here - [03:03] FIFO Overflow Pending: DON'T USE here - [02:02] FIFO Underlfow Pending: DON'T USE here - [01:01] FIFO Overlfow Enabled: Enabled - [00:00] FIFO Underflow Enabled: Enabled - TIME_CFG0 - [31:16] DRAM Refresh Time: 0 CSB clocks - [15:8] DRAM Command Time: 0 CSB clocks - [07:00] DRAM Precharge Time: 0 CSB clocks - TIME_CFG1 - [31:26] DRAM tRFC: - [25:21] DRAM tWR1: - [20:17] DRAM tWRT1: - [16:11] DRAM tDRR: - [10:05] DRAM tRC: - [04:00] DRAM tRAS: - TIME_CFG2 - [31:28] DRAM tRCD: - [27:23] DRAM tFAW: - [22:19] DRAM tRTW1: - [18:15] DRAM tCCD: - [14:10] DRAM tRTP: - [09:05] DRAM tRP: - [04:00] DRAM tRPA */ + * + * SYS_CFG: + * [31:31] MDDRC Soft Reset: Diabled + * [30:30] DRAM CKE pin: Enabled + * [29:29] DRAM CLK: Enabled + * [28:28] Command Mode: Enabled (For initialization only) + * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] + * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] + * [20:19] Read Test: DON'T USE + * [18:18] Self Refresh: Enabled + * [17:17] 16bit Mode: Disabled + * [16:13] Ready Delay: 2 + * [12:12] Half DQS Delay: Disabled + * [11:11] Quarter DQS Delay: Disabled + * [10:08] Write Delay: 2 + * [07:07] Early ODT: Disabled + * [06:06] On DIE Termination: Disabled + * [05:05] FIFO Overflow Clear: DON'T USE here + * [04:04] FIFO Underflow Clear: DON'T USE here + * [03:03] FIFO Overflow Pending: DON'T USE here + * [02:02] FIFO Underlfow Pending: DON'T USE here + * [01:01] FIFO Overlfow Enabled: Enabled + * [00:00] FIFO Underflow Enabled: Enabled + * TIME_CFG0 + * [31:16] DRAM Refresh Time: 0 CSB clocks + * [15:8] DRAM Command Time: 0 CSB clocks + * [07:00] DRAM Precharge Time: 0 CSB clocks + * TIME_CFG1 + * [31:26] DRAM tRFC: + * [25:21] DRAM tWR1: + * [20:17] DRAM tWRT1: + * [16:11] DRAM tDRR: + * [10:05] DRAM tRC: + * [04:00] DRAM tRAS: + * TIME_CFG2 + * [31:28] DRAM tRCD: + * [27:23] DRAM tFAW: + * [22:19] DRAM tRTW1: + * [18:15] DRAM tCCD: + * [14:10] DRAM tRTP: + * [09:05] DRAM tRP: + * [04:00] DRAM tRPA + */ #define CFG_MDDRC_SYS_CFG 0xF8604200 #define CFG_MDDRC_SYS_CFG_RUN 0xE8604200 @@ -276,7 +277,7 @@ SYS_CFG: #define CONFIG_COMMANDS (CONFIG_CMD_DFL \ | CFG_CMD_NET \ | CFG_CMD_PING \ - | CFG_CMD_MII \ + | CFG_CMD_MII \ | CFG_CMD_I2C) #endif @@ -384,26 +385,26 @@ SYS_CFG: "bootm\0" \ "load=tftp 100000 /tftpboot/ads5121/u-boot.bin\0" \ "update=protect off fff00000 fff3ffff; " \ - "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ + "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ "upd=run load;run update\0" \ "" -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" #define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/mpc512x.h b/include/mpc512x.h index 03e0e9a1473..a100b22daf8 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -60,7 +60,7 @@ #define CS_CTRL 0x00020 #define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ -#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */ +#define CS_CTRL_IE 0x08000000 /* CS Interrupt Enable bit */ /* SPRIDR - System Part and Revision ID Register */ -- cgit v1.3.1 From 86b116b1b1e165ca4840daefed36d2e3b8460173 Mon Sep 17 00:00:00 2001 From: Bartlomiej Sieka Date: Fri, 3 Aug 2007 12:08:16 +0200 Subject: cm1_qp1 -> cm5200: single U-Boot image for modules from the cm5200 family. Add the ability for modules from the Schindler cm5200 family to use a single U-Boot image: - rename cm1_qp1 to cm5200 - add run-time module detection - parametrize SDRAM configuration according to the module we are running on Few minor, board-specific fixes included in this patch: - better MAC address handling - updated default environment ('update' command uses +{filesize} now) - improved error messages in the auto-update code - allow booting U-Boot from RAM (CFG_RAMBOOT) Signed-off-by: Grzegorz Bernacki Signed-off-by: Piotr Kruszynski Signed-off-by: Bartlomiej Sieka --- MAKEALL | 2 +- Makefile | 9 +- board/cm1_qp1/Makefile | 50 ----- board/cm1_qp1/cm1_qp1.c | 222 ---------------------- board/cm1_qp1/cmd_cm1_qp1.c | 446 ------------------------------------------- board/cm1_qp1/config.mk | 26 --- board/cm1_qp1/fwupdate.c | 187 ------------------ board/cm1_qp1/fwupdate.h | 47 ----- board/cm1_qp1/u-boot.lds | 123 ------------ board/cm5200/Makefile | 50 +++++ board/cm5200/cm5200.c | 425 +++++++++++++++++++++++++++++++++++++++++ board/cm5200/cm5200.h | 184 ++++++++++++++++++ board/cm5200/cmd_cm5200.c | 448 ++++++++++++++++++++++++++++++++++++++++++++ board/cm5200/config.mk | 26 +++ board/cm5200/fwupdate.c | 200 ++++++++++++++++++++ board/cm5200/fwupdate.h | 47 +++++ board/cm5200/u-boot.lds | 123 ++++++++++++ cpu/mpc5xxx/fec.c | 2 +- include/configs/cm1_qp1.h | 358 ----------------------------------- include/configs/cm5200.h | 362 +++++++++++++++++++++++++++++++++++ 20 files changed, 1869 insertions(+), 1468 deletions(-) delete mode 100644 board/cm1_qp1/Makefile delete mode 100644 board/cm1_qp1/cm1_qp1.c delete mode 100644 board/cm1_qp1/cmd_cm1_qp1.c delete mode 100644 board/cm1_qp1/config.mk delete mode 100644 board/cm1_qp1/fwupdate.c delete mode 100644 board/cm1_qp1/fwupdate.h delete mode 100644 board/cm1_qp1/u-boot.lds create mode 100644 board/cm5200/Makefile create mode 100644 board/cm5200/cm5200.c create mode 100644 board/cm5200/cm5200.h create mode 100644 board/cm5200/cmd_cm5200.c create mode 100644 board/cm5200/config.mk create mode 100644 board/cm5200/fwupdate.c create mode 100644 board/cm5200/fwupdate.h create mode 100644 board/cm5200/u-boot.lds delete mode 100644 include/configs/cm1_qp1.h create mode 100644 include/configs/cm5200.h (limited to 'include') diff --git a/MAKEALL b/MAKEALL index 2a03b687083..c69dc1b3c47 100755 --- a/MAKEALL +++ b/MAKEALL @@ -35,7 +35,7 @@ LIST_5xx=" \ ######################################################################### LIST_5xxx=" \ - BC3450 cm1_qp1 cpci5200 EVAL5200 \ + BC3450 cm5200 cpci5200 EVAL5200 \ fo300 icecube_5100 icecube_5200 lite5200b \ mcc200 mecp5200 motionpro o2dnt \ pf5200 PM520 TB5200 Total5100 \ diff --git a/Makefile b/Makefile index 5b87aad5b9f..7f5aefe4734 100644 --- a/Makefile +++ b/Makefile @@ -532,13 +532,8 @@ PM520_ROMBOOT_DDR_config: unconfig smmaco4_config: unconfig @$(MKCONFIG) -a smmaco4 ppc mpc5xxx tqm5200 -cm1_qp1_config: unconfig - @ >include/config.h - @[ -z "$(findstring cm1_qp1,$@)" ] || \ - { echo "... with 64 MByte SDRAM" ; \ - echo "... with 32 MByte Flash" ; \ - } - @./mkconfig -a cm1_qp1 ppc mpc5xxx cm1_qp1 +cm5200_config: unconfig + @./mkconfig -a cm5200 ppc mpc5xxx cm5200 spieval_config: unconfig @$(MKCONFIG) -a spieval ppc mpc5xxx tqm5200 diff --git a/board/cm1_qp1/Makefile b/board/cm1_qp1/Makefile deleted file mode 100644 index e7393267e7a..00000000000 --- a/board/cm1_qp1/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2003-2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := $(BOARD).o cmd_cm1_qp1.o fwupdate.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/cm1_qp1/cm1_qp1.c b/board/cm1_qp1/cm1_qp1.c deleted file mode 100644 index b49298f64b6..00000000000 --- a/board/cm1_qp1/cm1_qp1.c +++ /dev/null @@ -1,222 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#ifdef CONFIG_OF_FLAT_TREE -#include -#endif /* CONFIG_OF_FLAT_TREE */ - -#include "fwupdate.h" - -#ifndef CFG_RAMBOOT -/* - * Helper function to initialize SDRAM controller. - */ -static void sdram_start(int hi_addr) -{ - long hi_addr_bit = hi_addr ? 0x01000000 : 0; - - /* unlock mode register */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | - hi_addr_bit; - - /* precharge all banks */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | - hi_addr_bit; - - /* auto refresh */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; - - /* auto refresh, second time */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | - hi_addr_bit; - - /* set mode register */ - *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; - - /* normal operation */ - *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; -} -#endif /* CFG_RAMBOOT */ - -/* - * Initalize SDRAM - configure SDRAM controller, detect memory size. - */ -long int initdram(int board_type) -{ - ulong dramsize = 0; -#ifndef CFG_RAMBOOT - ulong test1, test2; - - /* configure SDRAM start/end for detection */ - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ - - /* setup config registers */ - *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; - *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; - - sdram_start(0); - test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - sdram_start(1); - test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); - if (test1 > test2) { - sdram_start(0); - dramsize = test1; - } else - dramsize = test2; - - /* memory smaller than 1MB is impossible */ - if (dramsize < (1 << 20)) - dramsize = 0; - - /* set SDRAM CS0 size according to the amount of RAM found */ - if (dramsize > 0) { - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + - __builtin_ffs(dramsize >> 20) - 1; - } else - *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ -#else /* CFG_RAMBOOT */ - /* retrieve size of memory connected to SDRAM CS0 */ - dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; - if (dramsize >= 0x13) - dramsize = (1 << (dramsize - 0x13)) << 20; - else - dramsize = 0; -#endif /* CFG_RAMBOOT */ - - /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of - * the MPC5200B User's Manual. - */ - *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; - __asm__ volatile ("sync"); - - return dramsize; -} - - -int checkboard(void) -{ - puts("Board: CM1.QP1\n"); - return 0; -} - - -int board_early_init_r(void) -{ - /* - * Now, when we are in RAM, enable flash write access for detection - * process. Note that CS_BOOT cannot be cleared when executing in - * flash. - */ - *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ - return 0; -} - - -#ifdef CONFIG_POST -int post_hotkeys_pressed(void) -{ - return 0; -} -#endif /* CONFIG_POST */ - - -#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) -void post_word_store(ulong a) -{ - vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); - *save_addr = a; -} - - -ulong post_word_load(void) -{ - vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); - return *save_addr; -} -#endif /* CONFIG_POST || CONFIG_LOGBUFFER */ - - -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) -{ -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) - uchar buf[6]; - char str[18]; - - /* Read ethaddr from EEPROM */ - if (i2c_read(CFG_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) { - sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", - buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); - /* Check if MAC addr is owned by Schindler */ - if (strstr(str, "00:06:C3") != str) { - printf(LOG_PREFIX "Warning - Illegal MAC address (%s)" - " in EEPROM.\n", str); - printf(LOG_PREFIX "Using MAC from environment\n"); - } else { - printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n", - str); - setenv("ethaddr", str); - } - } else { - printf(LOG_PREFIX "Warning - Unable to read MAC from I2C" - " device at address %02X:%04X\n", CFG_I2C_EEPROM, - CONFIG_MAC_OFFSET); - printf(LOG_PREFIX "Using MAC from environment\n"); - } - return 0; -#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */ -} -#endif /* CONFIG_MISC_INIT_R */ - - -#ifdef CONFIG_LAST_STAGE_INIT -int last_stage_init(void) -{ -#ifdef CONFIG_USB_STORAGE - cm1_fwupdate(); -#endif /* CONFIG_USB_STORAGE */ - return 0; -} -#endif /* CONFIG_LAST_STAGE_INIT */ - - -#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -} -#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/cm1_qp1/cmd_cm1_qp1.c b/board/cm1_qp1/cmd_cm1_qp1.c deleted file mode 100644 index 4a01d2a7f4c..00000000000 --- a/board/cm1_qp1/cmd_cm1_qp1.c +++ /dev/null @@ -1,446 +0,0 @@ -/* - * (C) Copyright 2007 Markus Kappeler - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -#if (CONFIG_COMMANDS & CFG_CMD_BSP) - -int do_i2c(char *argv[]) -{ - unsigned char temp, temp1; - - printf("Starting I2C Test\n" - "Please set Jumper:\nI2C SDA 2-3\nI2C SCL 2-3\n\n" - "Please press any key to start\n\n"); - getc(); - - temp = 0xf0; /* set io 0-4 as output */ - i2c_write(CFG_I2C_IO, 3, 1, (uchar *)&temp, 1); - - printf("Press I2C4-7. LED I2C0-3 should have the same state\n\n" - "Press any key to stop\n\n"); - - while (!tstc()) { - i2c_read(CFG_I2C_IO, 0, 1, (uchar *)&temp, 1); - temp1 = (temp >> 4) & 0x03; - temp1 |= (temp >> 3) & 0x08; /* S302 -> LED303 */ - temp1 |= (temp >> 5) & 0x04; /* S303 -> LED302 */ - temp = temp1; - i2c_write(CFG_I2C_IO, 1, 1, (uchar *)&temp, 1); - } - getc(); - - return 0; -} - -int do_usbtest(char *argv[]) -{ - int i; - static int usb_stor_curr_dev = -1; /* current device */ - - printf("Starting USB Test\n" - "Please insert USB Memmory Stick\n\n" - "Please press any key to start\n\n"); - getc(); - - usb_stop(); - printf("(Re)start USB...\n"); - i = usb_init(); -#ifdef CONFIG_USB_STORAGE - /* try to recognize storage devices immediately */ - if (i >= 0) - usb_stor_curr_dev = usb_stor_scan(1); -#endif /* CONFIG_USB_STORAGE */ - if (usb_stor_curr_dev >= 0) - printf("Found USB Storage Dev continue with Test...\n"); - else { - printf("No USB Storage Device detected.. Stop Test\n"); - return 1; - } - - usb_stor_info(); - - printf("stopping USB..\n"); - usb_stop(); - - return 0; -} - -int do_led(char *argv[]) -{ - int i = 0; - struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; - - printf("Starting LED Test\n" - "Please set Switch S500 all off\n\n" - "Please press any key to start\n\n"); - getc(); - - /* configure timer 2-3 for simple GPIO output High */ - gpt->gpt2.emsr |= 0x00000034; - gpt->gpt3.emsr |= 0x00000034; - - (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000; - (*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000; - printf("Please press any key to stop\n\n"); - while (!tstc()) { - if (i == 1) { - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; - gpt->gpt2.emsr &= ~0x00000010; - gpt->gpt3.emsr &= ~0x00000010; - } else if (i == 2) { - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; - gpt->gpt2.emsr &= ~0x00000010; - gpt->gpt3.emsr |= 0x00000010; - } else if (i >= 3) { - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; - gpt->gpt3.emsr &= ~0x00000010; - gpt->gpt2.emsr |= 0x00000010; - i = 0; - } - i++; - udelay(200000); - } - getc(); - - (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; - gpt->gpt2.emsr |= 0x00000010; - gpt->gpt3.emsr |= 0x00000010; - - return 0; -} - -int do_rs232(char *argv[]) -{ - int error_status = 0; - struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; - struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1; - - /* Configure PSC 2-3-6 as GPIO */ - gpio->port_config &= 0xFF0FF80F; - - switch (simple_strtoul(argv[2], NULL, 10)) { - case 1: - /* check RTS <-> CTS loop */ - /* set rts to 0 */ - printf("Uart 1 test: RX TX tested by using U-Boot\n" - "Please connect RTS with CTS on Uart1 plug\n\n" - "Press any key to start\n\n"); - getc(); - - psc1->op1 |= 0x01; - - /* wait some time before requesting status */ - udelay(10); - - /* check status at cts */ - if ((psc1->ip & 0x01) != 0) { - error_status = 3; - printf("%s: failure at rs232_1, cts status is %d " - "(should be 0)\n", - __FUNCTION__, (psc1->ip & 0x01)); - } - - /* set rts to 1 */ - psc1->op0 |= 0x01; - - /* wait some time before requesting status */ - udelay(10); - - /* check status at cts */ - if ((psc1->ip & 0x01) != 1) { - error_status = 3; - printf("%s: failure at rs232_1, cts status is %d " - "(should be 1)\n", - __FUNCTION__, (psc1->ip & 0x01)); - } - break; - case 2: - /* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */ - printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n" - "\nPress any key to start\n\n"); - getc(); - - gpio->simple_gpioe &= ~(0x000000F0); - gpio->simple_gpioe |= 0x000000F0; - gpio->simple_ddr &= ~(0x000000F0); - gpio->simple_ddr |= 0x00000050; - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 4); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000020) != 0x00000020) { - error_status = 2; - printf("%s: failure at rs232_2, rxd status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000020) >> 5); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 4); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000020) != 0x00000000) { - error_status = 2; - printf("%s: failure at rs232_2, rxd status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000020) >> 5); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 6); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000080) != 0x00000080) { - error_status = 3; - printf("%s: failure at rs232_2, cts status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000080) >> 7); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 6); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000080) != 0x00000000) { - error_status = 3; - printf("%s: failure at rs232_2, cts status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000080) >> 7); - } - break; - case 3: - /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */ - printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n" - "\nPress any key to start\n\n"); - getc(); - - gpio->simple_gpioe &= ~(0x00000F00); - gpio->simple_gpioe |= 0x00000F00; - - gpio->simple_ddr &= ~(0x00000F00); - gpio->simple_ddr |= 0x00000500; - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 8); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000200) != 0x00000200) { - error_status = 2; - printf("%s: failure at rs232_3, rxd status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000200) >> 9); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 8); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000200) != 0x00000000) { - error_status = 2; - printf("%s: failure at rs232_3, rxd status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000200) >> 9); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 10); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000800) != 0x00000800) { - error_status = 3; - printf("%s: failure at rs232_3, cts status is %d " - "(should be 1)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000800) >> 11); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 10); - - /* wait some time before requesting status */ - udelay(10); - - if ((gpio->simple_ival & 0x00000800) != 0x00000000) { - error_status = 3; - printf("%s: failure at rs232_3, cts status is %d " - "(should be 0)\n", __FUNCTION__, - (gpio->simple_ival & 0x00000800) >> 11); - } - break; - case 4: - /* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */ - printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n" - "\nPress any key to start\n\n"); - getc(); - - gpio->simple_gpioe &= ~(0xF0000000); - gpio->simple_gpioe |= 0x30000000; - - gpio->simple_ddr &= ~(0xf0000000); - gpio->simple_ddr |= 0x30000000; - - (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000; - (*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000); - - /* check TXD <-> RXD loop */ - /* set TXD to 1 */ - gpio->simple_dvo |= (1 << 28); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != - 0x10000000) { - error_status = 2; - printf("%s: failure at rs232_4, rxd status is %d " - "(should be 1)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x10000000) >> 28); - } - - /* set TXD to 0 */ - gpio->simple_dvo &= ~(1 << 28); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != - 0x00000000) { - error_status = 2; - printf("%s: failure at rs232_4, rxd status is %d " - "(should be 0)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x10000000) >> 28); - } - - /* check RTS <-> CTS loop */ - /* set RTS to 1 */ - gpio->simple_dvo |= (1 << 29); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != - 0x20000000) { - error_status = 3; - printf("%s: failure at rs232_4, cts status is %d " - "(should be 1)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x20000000) >> 29); - } - - /* set RTS to 0 */ - gpio->simple_dvo &= ~(1 << 29); - - /* wait some time before requesting status */ - udelay(10); - - if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != - 0x00000000) { - error_status = 3; - printf("%s: failure at rs232_4, cts status is %d " - "(should be 0)\n", __FUNCTION__, - ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & - 0x20000000) >> 29); - } - break; - default: - printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]); - error_status = 1; - break; - } - gpio->port_config |= (CFG_GPS_PORT_CONFIG & 0xFF0FF80F); - - return error_status; -} - -int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) -{ - int rcode = -1; - - switch (argc) { - case 2: - if (strncmp(argv[1], "i2c", 3) == 0) - rcode = do_i2c(argv); - else if (strncmp(argv[1], "led", 3) == 0) - rcode = do_led(argv); - else if (strncmp(argv[1], "usb", 3) == 0) - rcode = do_usbtest(argv); - break; - case 3: - if (strncmp(argv[1], "rs232", 3) == 0) - rcode = do_rs232(argv); - break; - } - - switch (rcode) { - case -1: - printf("Usage:\n" - "fkt { i2c | led | usb }\n" - "fkt rs232 number\n"); - rcode = 1; - break; - case 0: - printf("Test passed\n"); - break; - default: - printf("Test failed with code: %d\n", rcode); - } - - return rcode; -} - -U_BOOT_CMD( - fkt, 4, 1, cmd_fkt, - "fkt - Function test routines\n", - "i2c\n" - " - Test I2C communication\n" - "fkt led\n" - " - Test LEDs\n" - "fkt rs232 number\n" - " - Test RS232 (loopback plug(s) for RS232 required)\n" - "fkt usb\n" - " - Test USB communication\n" -); -#endif /* CFG_CMD_BSP */ diff --git a/board/cm1_qp1/config.mk b/board/cm1_qp1/config.mk deleted file mode 100644 index 7f061391a24..00000000000 --- a/board/cm1_qp1/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2007 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -TEXT_BASE = 0xfc000000 - -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/cm1_qp1/fwupdate.c b/board/cm1_qp1/fwupdate.c deleted file mode 100644 index 637375e5989..00000000000 --- a/board/cm1_qp1/fwupdate.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * (C) Copyright 2007 Schindler Lift Inc. - * (C) Copyright 2007 Semihalf - * - * Author: Michel Marti - * Adapted for U-Boot 1.2 by Piotr Kruszynski : - * - code clean-up - * - bugfix for overwriting bootargs by user - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -#include "fwupdate.h" - -extern int do_bootm(cmd_tbl_t *, int, int, char *[]); -extern long do_fat_read(const char *, void *, unsigned long, int); -extern int do_fat_fsload(cmd_tbl_t *, int, int, char *[]); - -static int load_rescue_image(ulong); - -void cm1_fwupdate(void) -{ - cmd_tbl_t *bcmd; - char *rsargs; - char *tmp = NULL; - char ka[16]; - char *argv[3] = { "bootm", ka, NULL }; - - /* Check if rescue system is disabled... */ - if (getenv("norescue")) { - printf(LOG_PREFIX "Rescue System disabled.\n"); - return; - } - - /* Check if we have a USB storage device and load image */ - if (load_rescue_image(LOAD_ADDR)) - return; - - bcmd = find_cmd("bootm"); - if (!bcmd) - return; - - sprintf(ka, "%lx", LOAD_ADDR); - - /* prepare our bootargs */ - rsargs = getenv("rs-args"); - if (!rsargs) - rsargs = RS_BOOTARGS; - else { - tmp = malloc(strlen(rsargs+1)); - if (!tmp) { - printf(LOG_PREFIX "Memory allocation failed\n"); - return; - } - strcpy(tmp, rsargs); - rsargs = tmp; - } - - setenv("bootargs", rsargs); - - if (rsargs == tmp) - free(rsargs); - - printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs); - do_bootm(bcmd, 0, 2, argv); -} - -static int load_rescue_image(ulong addr) -{ - disk_partition_t info; - int devno; - int partno; - int i; - char fwdir[64]; - char nxri[128]; - char *tmp; - char dev[7]; - char addr_str[16]; - char *argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL }; - block_dev_desc_t *stor_dev = NULL; - cmd_tbl_t *bcmd; - - /* Get name of firmware directory */ - tmp = getenv("fw-dir"); - - /* Copy it into fwdir */ - strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir)); - fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */ - - printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB" - " storage...\n", fwdir); - usb_stop(); - if (usb_init() != 0) - return 1; - - /* Check for storage device */ - if (usb_stor_scan(1) != 0) { - usb_stop(); - return 1; - } - - /* Detect storage device */ - for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) { - stor_dev = usb_stor_get_dev(devno); - if (stor_dev->type != DEV_TYPE_UNKNOWN) - break; - } - if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) { - printf(LOG_PREFIX "No valid storage device found...\n"); - usb_stop(); - return 1; - } - - /* Detect partition */ - for (partno = -1, i = 0; i < 6; i++) { - if (get_partition_info(stor_dev, i, &info) == 0) { - if (fat_register_device(stor_dev, i) == 0) { - /* Check if rescue image is present */ - FW_DEBUG("Looking for firmware directory '%s'" - " on partition %d\n", fwdir, i); - if (do_fat_read(fwdir, NULL, 0, LS_NO) == -1) { - FW_DEBUG("No NX rescue image on " - "partition %d.\n", i); - } else { - partno = i; - FW_DEBUG("Partition %d contains " - "firmware directory\n", partno); - break; - } - } - } - } - - if (partno == -1) { - printf(LOG_PREFIX "Error: No valid (FAT) partition detected\n"); - usb_stop(); - return 1; - } - - /* Load the rescue image */ - bcmd = find_cmd("fatload"); - if (!bcmd) { - printf(LOG_PREFIX "Error - 'fatload' command not present.\n"); - usb_stop(); - return 1; - } - - tmp = getenv("nx-rescue-image"); - sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE); - sprintf(dev, "%d:%d", devno, partno); - sprintf(addr_str, "%lx", addr); - - FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n", - dev, addr_str, nxri); - - if (do_fat_fsload(bcmd, 0, 5, argv) != 0) { - usb_stop(); - return 1; - } - - /* Stop USB */ - usb_stop(); - return 0; -} diff --git a/board/cm1_qp1/fwupdate.h b/board/cm1_qp1/fwupdate.h deleted file mode 100644 index 119c2d691c8..00000000000 --- a/board/cm1_qp1/fwupdate.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2007 Schindler Lift Inc. - * - * Author: Michel Marti - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __FW_UPDATE_H -#define __FW_UPDATE_H - -/* Default prefix for output messages */ -#define LOG_PREFIX "CM1: " - -/* Extra debug macro */ -#ifdef CONFIG_FWUPDATE_DEBUG -#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt) -#else -#define FW_DEBUG(fmt...) -#endif - -/* Name of the directory holding firmware images */ -#define FW_DIR "nx-fw" -#define RESCUE_IMAGE "nxrs.img" -#define LOAD_ADDR 0x400000 -#define RS_BOOTARGS "ramdisk=8192K" - -/* Main function for fwupdate */ -void cm1_fwupdate(void); - -#endif /* __FW_UPDATE_H */ diff --git a/board/cm1_qp1/u-boot.lds b/board/cm1_qp1/u-boot.lds deleted file mode 100644 index 8fa9c0f7ed5..00000000000 --- a/board/cm1_qp1/u-boot.lds +++ /dev/null @@ -1,123 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_ARCH(powerpc) -SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - cpu/mpc5xxx/start.o (.text) - *(.text) - *(.fixup) - *(.got1) - . = ALIGN(16); - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - _end = . ; - PROVIDE (end = .); -} diff --git a/board/cm5200/Makefile b/board/cm5200/Makefile new file mode 100644 index 00000000000..8ebdb1aa28b --- /dev/null +++ b/board/cm5200/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2003-2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o cmd_cm5200.o fwupdate.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c new file mode 100644 index 00000000000..6804e33c27e --- /dev/null +++ b/board/cm5200/cm5200.c @@ -0,0 +1,425 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2004-2005 + * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de + * + * Adapted to U-Boot 1.2 by: + * Bartlomiej Sieka : + * - HW ID readout from EEPROM + * - module detection + * Grzegorz Bernacki : + * - run-time SDRAM controller configuration + * - LIBFDT support + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_OF_LIBFDT +#include +#include +#include +#endif /* CONFIG_OF_LIBFDT */ + + +#include "cm5200.h" +#include "fwupdate.h" + +DECLARE_GLOBAL_DATA_PTR; + +static hw_id_t hw_id; + + +#ifndef CFG_RAMBOOT +/* + * Helper function to initialize SDRAM controller. + */ +static void sdram_start(int hi_addr, mem_conf_t *mem_conf) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + + /* unlock mode register */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000000 | + hi_addr_bit; + + /* precharge all banks */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000002 | + hi_addr_bit; + + /* auto refresh */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 | + hi_addr_bit; + + /* auto refresh, second time */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | 0x80000004 | + hi_addr_bit; + + /* set mode register */ + *(vu_long *)MPC5XXX_SDRAM_MODE = mem_conf->mode; + + /* normal operation */ + *(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit; +} +#endif /* CFG_RAMBOOT */ + + +/* + * Retrieve memory configuration for a given module. board_type is the index + * in hw_id_list[] corresponding to the module we are executing on; we return + * SDRAM controller settings approprate for this module. + */ +static mem_conf_t* get_mem_config(int board_type) +{ + switch(board_type){ + case CM1_QA: + return memory_config[0]; + case CM11_QA: + case CMU1_QA: + return memory_config[1]; + default: + printf("ERROR: Unknown module, using a default SDRAM " + "configuration - things may not work!!!.\n"); + return memory_config[0]; + } +} + + +/* + * Initalize SDRAM - configure SDRAM controller, detect memory size. + */ +long int initdram(int board_type) +{ + ulong dramsize = 0; +#ifndef CFG_RAMBOOT + ulong test1, test2; + mem_conf_t *mem_conf; + + mem_conf = get_mem_config(board_type); + + /* configure SDRAM start/end for detection */ + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ + + /* setup config registers */ + *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = mem_conf->config1; + *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2; + + sdram_start(0, mem_conf); + test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + sdram_start(1, mem_conf); + test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0, mem_conf); + dramsize = test1; + } else + dramsize = test2; + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) + dramsize = 0; + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + + __builtin_ffs(dramsize >> 20) - 1; + } else + *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ +#else /* CFG_RAMBOOT */ + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; + if (dramsize >= 0x13) + dramsize = (1 << (dramsize - 0x13)) << 20; + else + dramsize = 0; +#endif /* !CFG_RAMBOOT */ + + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Refer to chapter 8.7.5 SDelay--MBAR + 0x0190 of + * the MPC5200B User's Manual. + */ + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + + return dramsize; +} + + +/* + * Read module hardware identification data from the I2C EEPROM. + */ +static void read_hw_id(hw_id_t hw_id) +{ + int i; + for (i = 0; i < HW_ID_ELEM_COUNT; ++i) + if (i2c_read(CFG_I2C_EEPROM, + hw_id_format[i].offset, + 2, + (uchar *)&hw_id[i][0], + hw_id_format[i].length) != 0) + printf("ERROR: can't read HW ID from EEPROM\n"); +} + + +/* + * Identify module we are running on, set gd->board_type to the index in + * hw_id_list[] corresponding to the module identifed, or to + * CM5200_UNKNOWN_MODULE if we can't identify the module. + */ +static void identify_module(hw_id_t hw_id) +{ + int i, j, element; + char match; + gd->board_type = CM5200_UNKNOWN_MODULE; + for (i = 0; i < sizeof (hw_id_list) / sizeof (char **); ++i) { + match = 1; + for (j = 0; j < sizeof (hw_id_identify) / sizeof (int); ++j) { + element = hw_id_identify[j]; + if (strncmp(hw_id_list[i][element], + &hw_id[element][0], + hw_id_format[element].length) != 0) { + match = 0; + break; + } + } + if (match) { + gd->board_type = i; + break; + } + } +} + + +/* + * Compose string with module name. + * buf is assumed to have enough space, and be null-terminated. + */ +static void compose_module_name(hw_id_t hw_id, char *buf) +{ + char tmp[MODULE_NAME_MAXLEN]; + strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length); + strncat(buf, ".", 1); + strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length); + strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length); + strncat(buf, " (", 2); + strncat(buf, &hw_id[IDENTIFICATION_NUMBER][0], + hw_id_format[IDENTIFICATION_NUMBER].length); + sprintf(tmp, " / %u.%u)", + hw_id[MAJOR_SW_VERSION][0], + hw_id[MINOR_SW_VERSION][0]); + strcat(buf, tmp); +} + + +/* + * Compose string with hostname. + * buf is assumed to have enough space, and be null-terminated. + */ +static void compose_hostname(hw_id_t hw_id, char *buf) +{ + char *p; + strncat(buf, &hw_id[PCB_NAME][0], hw_id_format[PCB_NAME].length); + strncat(buf, "_", 1); + strncat(buf, &hw_id[FORM][0], hw_id_format[FORM].length); + strncat(buf, &hw_id[VERSION][0], hw_id_format[VERSION].length); + for (p = buf; *p; ++p) + *p = tolower(*p); + +} + + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +/* + * Update 'model' and 'memory' properties in the blob according to the module + * that we are running on. + */ +static void ft_blob_update(void *blob, bd_t *bd) +{ + int len, ret, nodeoffset = 0; + char module_name[MODULE_NAME_MAXLEN] = {0}; + ulong memory_data[2] = {0}; + + compose_module_name(hw_id, module_name); + len = strlen(module_name) + 1; + + ret = fdt_setprop(blob, nodeoffset, "model", module_name, len); + if (ret < 0) + printf("ft_blob_update(): cannot set /model property err:%s\n", + fdt_strerror(ret)); + + memory_data[0] = cpu_to_be32(bd->bi_memstart); + memory_data[1] = cpu_to_be32(bd->bi_memsize); + + nodeoffset = fdt_find_node_by_path (blob, "/memory"); + if (nodeoffset >= 0) { + ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, + sizeof(memory_data)); + if (ret < 0) + printf("ft_blob_update): cannot set /memory/reg " + "property err:%s\n", fdt_strerror(ret)); + } + else { + /* memory node is required in dts */ + printf("ft_blob_update(): cannot find /memory node " + "err:%s\n", fdt_strerror(nodeoffset)); + } +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ + + +/* + * Read HW ID from I2C EEPROM and detect the modue we are running on. Note + * that we need to use local variable for readout, because global data is not + * writable yet (and we'll have to redo the readout later on). + */ +int checkboard(void) +{ + hw_id_t hw_id_tmp; + char module_name_tmp[MODULE_NAME_MAXLEN] = ""; + + /* + * We need I2C to access HW ID data from EEPROM, so we call i2c_init() + * here despite the fact that it will be called again later on. We + * also use a little trick to silence I2C-related output. + */ + gd->flags |= GD_FLG_SILENT; + i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); + gd->flags &= ~GD_FLG_SILENT; + + read_hw_id(hw_id_tmp); + identify_module(hw_id_tmp); /* this sets gd->board_type */ + compose_module_name(hw_id_tmp, module_name_tmp); + + if (gd->board_type != CM5200_UNKNOWN_MODULE) + printf("Board: %s\n", module_name_tmp); + else + printf("Board: unrecognized cm5200 module (%s)\n", + module_name_tmp); + + return 0; +} + + +int board_early_init_r(void) +{ + /* + * Now, when we are in RAM, enable flash write access for detection + * process. Note that CS_BOOT cannot be cleared when executing in + * flash. + */ + *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ + + /* Now that we can write to global data, read HW ID again. */ + read_hw_id(hw_id); + return 0; +} + + +#ifdef CONFIG_POST +int post_hotkeys_pressed(void) +{ + return 0; +} +#endif /* CONFIG_POST */ + + +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) +void post_word_store(ulong a) +{ + vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + *save_addr = a; +} + + +ulong post_word_load(void) +{ + vu_long *save_addr = (vu_long *)(MPC5XXX_SRAM + MPC5XXX_SRAM_POST_SIZE); + return *save_addr; +} +#endif /* CONFIG_POST || CONFIG_LOGBUFFER */ + + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) + uchar buf[6]; + char str[18]; + char hostname[MODULE_NAME_MAXLEN]; + + /* Read ethaddr from EEPROM */ + if (i2c_read(CFG_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) { + sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X", + buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + /* Check if MAC addr is owned by Schindler */ + if (strstr(str, "00:06:C3") != str) + printf(LOG_PREFIX "Warning - Illegal MAC address (%s)" + " in EEPROM.\n", str); + else { + printf(LOG_PREFIX "Using MAC (%s) from I2C EEPROM\n", + str); + setenv("ethaddr", str); + } + } else { + printf(LOG_PREFIX "Warning - Unable to read MAC from I2C" + " device at address %02X:%04X\n", CFG_I2C_EEPROM, + CONFIG_MAC_OFFSET); + } +#endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */ + if (!getenv("ethaddr")) + printf(LOG_PREFIX "MAC address not set, networking is not " + "operational\n"); + + /* set the hostname appropriate to the module we're running on */ + compose_hostname(hw_id, hostname); + setenv("hostname", hostname); + + return 0; +} +#endif /* CONFIG_MISC_INIT_R */ + + +#ifdef CONFIG_LAST_STAGE_INIT +int last_stage_init(void) +{ +#ifdef CONFIG_USB_STORAGE + cm5200_fwupdate(); +#endif /* CONFIG_USB_STORAGE */ + return 0; +} +#endif /* CONFIG_LAST_STAGE_INIT */ + + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + ft_blob_update(blob, bd); +} +#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ diff --git a/board/cm5200/cm5200.h b/board/cm5200/cm5200.h new file mode 100644 index 00000000000..a6cbc88f47c --- /dev/null +++ b/board/cm5200/cm5200.h @@ -0,0 +1,184 @@ +/* + * (C) Copyright 2007 DENX Software Engineering + * + * Author: Bartlomiej Sieka + * Author: Grzegorz Bernacki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _CM5200_H +#define _CM5200_H + + +/* + * Definitions and declarations for the modules of the cm5200 platform. Mostly + * related to reading the hardware identification data (HW ID) from the I2C + * EEPROM, detection of the particular module we are executing on, and + * appropriate SDRAM controller initialization. + */ + + +#define CM5200_UNKNOWN_MODULE 0xffffffff + +enum { + DEVICE_NAME, /* 0 */ + GENERATION, /* 1 */ + PCB_NAME, /* 2 */ + FORM, /* 3 */ + VERSION, /* 4 */ + IDENTIFICATION_NUMBER, /* 5 */ + MAJOR_SW_VERSION, /* 6 */ + MINOR_SW_VERSION, /* 7 */ + /* add new alements above this line */ + HW_ID_ELEM_COUNT /* count */ +}; + +/* + * Sect. 4.1 "CM1.Q/CMU1.Q Supervisory Microcontroller Interface Definition" + */ + +#define DEVICE_NAME_OFFSET 0x02 +#define GENERATION_OFFSET 0x0b +#define PCB_NAME_OFFSET 0x0c +#define FORM_OFFSET 0x15 +#define VERSION_OFFSET 0x16 +#define IDENTIFICATION_NUMBER_OFFSET 0x19 +#define MAJOR_SW_VERSION_OFFSET 0x0480 +#define MINOR_SW_VERSION_OFFSET 0x0481 + + +#define DEVICE_NAME_LEN 0x09 +#define GENERATION_LEN 0x01 +#define PCB_NAME_LEN 0x09 +#define FORM_LEN 0x01 +#define VERSION_LEN 0x03 +#define IDENTIFICATION_NUMBER_LEN 0x09 +#define MAJOR_SW_VERSION_LEN 0x01 +#define MINOR_SW_VERSION_LEN 0x01 + +#define HW_ID_ELEM_MAXLEN 0x09 /* MAX(XXX_LEN) */ + +/* entire HW ID in EEPROM is 64 bytes, so longer module name is unlikely */ +#define MODULE_NAME_MAXLEN 64 + + +/* storage for HW ID read from EEPROM */ +typedef char hw_id_t[HW_ID_ELEM_COUNT][HW_ID_ELEM_MAXLEN]; + + +/* HW ID layout in EEPROM */ +static struct { + unsigned int offset; + unsigned int length; +} hw_id_format[HW_ID_ELEM_COUNT] = { + {DEVICE_NAME_OFFSET, DEVICE_NAME_LEN}, + {GENERATION_OFFSET, GENERATION_LEN}, + {PCB_NAME_OFFSET, PCB_NAME_LEN}, + {FORM_OFFSET, FORM_LEN}, + {VERSION_OFFSET, VERSION_LEN}, + {IDENTIFICATION_NUMBER_OFFSET, IDENTIFICATION_NUMBER_LEN}, + {MAJOR_SW_VERSION_OFFSET, MAJOR_SW_VERSION_LEN}, + {MINOR_SW_VERSION_OFFSET, MINOR_SW_VERSION_LEN}, +}; + + +/* HW ID data found in EEPROM on supported modules */ +static char *cm1_qa_hw_id[HW_ID_ELEM_COUNT] = { + "CM", /* DEVICE_NAME */ + "1", /* GENERATION */ + "CM1", /* PCB_NAME */ + "Q", /* FORM */ + "A", /* VERSION */ + "591881", /* IDENTIFICATION_NUMBER */ + "", /* MAJOR_SW_VERSION */ + "", /* MINOR_SW_VERSION */ +}; + +static char *cm11_qa_hw_id[HW_ID_ELEM_COUNT] = { + "CM", /* DEVICE_NAME */ + "1", /* GENERATION */ + "CM11", /* PCB_NAME */ + "Q", /* FORM */ + "A", /* VERSION */ + "594200", /* IDENTIFICATION_NUMBER */ + "", /* MAJOR_SW_VERSION */ + "", /* MINOR_SW_VERSION */ +}; + +static char *cmu1_qa_hw_id[HW_ID_ELEM_COUNT] = { + "CMU", /* DEVICE_NAME */ + "1", /* GENERATION */ + "CMU1", /* PCB_NAME */ + "Q", /* FORM */ + "A", /* VERSION */ + "594128", /* IDENTIFICATION_NUMBER */ + "", /* MAJOR_SW_VERSION */ + "", /* MINOR_SW_VERSION */ +}; + + +/* list of known modules */ +static char **hw_id_list[] = { + cm1_qa_hw_id, + cm11_qa_hw_id, + cmu1_qa_hw_id, +}; + +/* indices to the above list - keep in sync */ +enum { + CM1_QA, + CM11_QA, + CMU1_QA, +}; + + +/* identify modules based on these hw id elements */ +static int hw_id_identify[] = { + PCB_NAME, + FORM, + VERSION, +}; + + +/* Registers' settings for SDRAM controller intialization */ +typedef struct { + ulong mode; + ulong control; + ulong config1; + ulong config2; +} mem_conf_t; + +static mem_conf_t k4s561632E = { + 0x00CD0000, /* CASL 3, burst length 8 */ + 0x514F0000, + 0xE2333900, + 0x8EE70000 +}; + +static mem_conf_t mt48lc32m16a2 = { + 0x00CD0000, /* CASL 3, burst length 8 */ + 0x514F0000, + 0xD2322800, + 0x8AD70000 +}; + +static mem_conf_t* memory_config[] = { + &k4s561632E, + &mt48lc32m16a2 +}; + +#endif /* _CM5200_H */ diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c new file mode 100644 index 00000000000..5119a99ca23 --- /dev/null +++ b/board/cm5200/cmd_cm5200.c @@ -0,0 +1,448 @@ +/* + * (C) Copyright 2007 Markus Kappeler + * + * Adapted for U-Boot 1.2 by Piotr Kruszynski + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +#if (CONFIG_COMMANDS & CFG_CMD_BSP) + +int do_i2c(char *argv[]) +{ + unsigned char temp, temp1; + + printf("Starting I2C Test\n" + "Please set Jumper:\nI2C SDA 2-3\nI2C SCL 2-3\n\n" + "Please press any key to start\n\n"); + getc(); + + temp = 0xf0; /* set io 0-4 as output */ + i2c_write(CFG_I2C_IO, 3, 1, (uchar *)&temp, 1); + + printf("Press I2C4-7. LED I2C0-3 should have the same state\n\n" + "Press any key to stop\n\n"); + + while (!tstc()) { + i2c_read(CFG_I2C_IO, 0, 1, (uchar *)&temp, 1); + temp1 = (temp >> 4) & 0x03; + temp1 |= (temp >> 3) & 0x08; /* S302 -> LED303 */ + temp1 |= (temp >> 5) & 0x04; /* S303 -> LED302 */ + temp = temp1; + i2c_write(CFG_I2C_IO, 1, 1, (uchar *)&temp, 1); + } + getc(); + + return 0; +} + +int do_usbtest(char *argv[]) +{ + int i; + static int usb_stor_curr_dev = -1; /* current device */ + + printf("Starting USB Test\n" + "Please insert USB Memmory Stick\n\n" + "Please press any key to start\n\n"); + getc(); + + usb_stop(); + printf("(Re)start USB...\n"); + i = usb_init(); +#ifdef CONFIG_USB_STORAGE + /* try to recognize storage devices immediately */ + if (i >= 0) + usb_stor_curr_dev = usb_stor_scan(1); +#endif /* CONFIG_USB_STORAGE */ + if (usb_stor_curr_dev >= 0) + printf("Found USB Storage Dev continue with Test...\n"); + else { + printf("No USB Storage Device detected.. Stop Test\n"); + return 1; + } + + usb_stor_info(); + + printf("stopping USB..\n"); + usb_stop(); + + return 0; +} + +int do_led(char *argv[]) +{ + int i = 0; + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + + printf("Starting LED Test\n" + "Please set Switch S500 all off\n\n" + "Please press any key to start\n\n"); + getc(); + + /* configure timer 2-3 for simple GPIO output High */ + gpt->gpt2.emsr |= 0x00000034; + gpt->gpt3.emsr |= 0x00000034; + + (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x80000000; + (*(vu_long *)MPC5XXX_WU_GPIO_DIR) |= 0x80000000; + printf("Please press any key to stop\n\n"); + while (!tstc()) { + if (i == 1) { + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; + gpt->gpt2.emsr &= ~0x00000010; + gpt->gpt3.emsr &= ~0x00000010; + } else if (i == 2) { + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; + gpt->gpt2.emsr &= ~0x00000010; + gpt->gpt3.emsr |= 0x00000010; + } else if (i >= 3) { + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) &= ~0x80000000; + gpt->gpt3.emsr &= ~0x00000010; + gpt->gpt2.emsr |= 0x00000010; + i = 0; + } + i++; + udelay(200000); + } + getc(); + + (*(vu_long *)MPC5XXX_WU_GPIO_DATA_O) |= 0x80000000; + gpt->gpt2.emsr |= 0x00000010; + gpt->gpt3.emsr |= 0x00000010; + + return 0; +} + +int do_rs232(char *argv[]) +{ + int error_status = 0; + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_psc *psc1 = (struct mpc5xxx_psc *)MPC5XXX_PSC1; + + /* Configure PSC 2-3-6 as GPIO */ + gpio->port_config &= 0xFF0FF80F; + + switch (simple_strtoul(argv[2], NULL, 10)) { + case 1: + /* check RTS <-> CTS loop */ + /* set rts to 0 */ + printf("Uart 1 test: RX TX tested by using U-Boot\n" + "Please connect RTS with CTS on Uart1 plug\n\n" + "Press any key to start\n\n"); + getc(); + + psc1->op1 |= 0x01; + + /* wait some time before requesting status */ + udelay(10); + + /* check status at cts */ + if ((psc1->ip & 0x01) != 0) { + error_status = 3; + printf("%s: failure at rs232_1, cts status is %d " + "(should be 0)\n", + __FUNCTION__, (psc1->ip & 0x01)); + } + + /* set rts to 1 */ + psc1->op0 |= 0x01; + + /* wait some time before requesting status */ + udelay(10); + + /* check status at cts */ + if ((psc1->ip & 0x01) != 1) { + error_status = 3; + printf("%s: failure at rs232_1, cts status is %d " + "(should be 1)\n", + __FUNCTION__, (psc1->ip & 0x01)); + } + break; + case 2: + /* set PSC2_0, PSC2_2 as output and PSC2_1, PSC2_3 as input */ + printf("Uart 2 test: Please use RS232 Loopback plug on UART2\n" + "\nPress any key to start\n\n"); + getc(); + + gpio->simple_gpioe &= ~(0x000000F0); + gpio->simple_gpioe |= 0x000000F0; + gpio->simple_ddr &= ~(0x000000F0); + gpio->simple_ddr |= 0x00000050; + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 4); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000020) != 0x00000020) { + error_status = 2; + printf("%s: failure at rs232_2, rxd status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000020) >> 5); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 4); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000020) != 0x00000000) { + error_status = 2; + printf("%s: failure at rs232_2, rxd status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000020) >> 5); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 6); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000080) != 0x00000080) { + error_status = 3; + printf("%s: failure at rs232_2, cts status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000080) >> 7); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 6); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000080) != 0x00000000) { + error_status = 3; + printf("%s: failure at rs232_2, cts status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000080) >> 7); + } + break; + case 3: + /* set PSC3_0, PSC3_2 as output and PSC3_1, PSC3_3 as input */ + printf("Uart 3 test: Please use RS232 Loopback plug on UART2\n" + "\nPress any key to start\n\n"); + getc(); + + gpio->simple_gpioe &= ~(0x00000F00); + gpio->simple_gpioe |= 0x00000F00; + + gpio->simple_ddr &= ~(0x00000F00); + gpio->simple_ddr |= 0x00000500; + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 8); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000200) != 0x00000200) { + error_status = 2; + printf("%s: failure at rs232_3, rxd status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000200) >> 9); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 8); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000200) != 0x00000000) { + error_status = 2; + printf("%s: failure at rs232_3, rxd status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000200) >> 9); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 10); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000800) != 0x00000800) { + error_status = 3; + printf("%s: failure at rs232_3, cts status is %d " + "(should be 1)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000800) >> 11); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 10); + + /* wait some time before requesting status */ + udelay(10); + + if ((gpio->simple_ival & 0x00000800) != 0x00000000) { + error_status = 3; + printf("%s: failure at rs232_3, cts status is %d " + "(should be 0)\n", __FUNCTION__, + (gpio->simple_ival & 0x00000800) >> 11); + } + break; + case 4: + /* set PSC6_2, PSC6_3 as output and PSC6_0, PSC6_1 as input */ + printf("Uart 4 test: Please use RS232 Loopback plug on UART2\n" + "\nPress any key to start\n\n"); + getc(); + + gpio->simple_gpioe &= ~(0xF0000000); + gpio->simple_gpioe |= 0x30000000; + + gpio->simple_ddr &= ~(0xf0000000); + gpio->simple_ddr |= 0x30000000; + + (*(vu_long *)MPC5XXX_WU_GPIO_ENABLE) |= 0x30000000; + (*(vu_long *)MPC5XXX_WU_GPIO_DIR) &= ~(0x30000000); + + /* check TXD <-> RXD loop */ + /* set TXD to 1 */ + gpio->simple_dvo |= (1 << 28); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != + 0x10000000) { + error_status = 2; + printf("%s: failure at rs232_4, rxd status is %d " + "(should be 1)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x10000000) >> 28); + } + + /* set TXD to 0 */ + gpio->simple_dvo &= ~(1 << 28); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x10000000) != + 0x00000000) { + error_status = 2; + printf("%s: failure at rs232_4, rxd status is %d " + "(should be 0)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x10000000) >> 28); + } + + /* check RTS <-> CTS loop */ + /* set RTS to 1 */ + gpio->simple_dvo |= (1 << 29); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != + 0x20000000) { + error_status = 3; + printf("%s: failure at rs232_4, cts status is %d " + "(should be 1)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x20000000) >> 29); + } + + /* set RTS to 0 */ + gpio->simple_dvo &= ~(1 << 29); + + /* wait some time before requesting status */ + udelay(10); + + if (((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & 0x20000000) != + 0x00000000) { + error_status = 3; + printf("%s: failure at rs232_4, cts status is %d " + "(should be 0)\n", __FUNCTION__, + ((*(vu_long *)MPC5XXX_WU_GPIO_DATA_I) & + 0x20000000) >> 29); + } + break; + default: + printf("%s: invalid rs232 number %s\n", __FUNCTION__, argv[2]); + error_status = 1; + break; + } + gpio->port_config |= (CFG_GPS_PORT_CONFIG & 0xFF0FF80F); + + return error_status; +} + +int cmd_fkt(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int rcode = -1; + + switch (argc) { + case 2: + if (strncmp(argv[1], "i2c", 3) == 0) + rcode = do_i2c(argv); + else if (strncmp(argv[1], "led", 3) == 0) + rcode = do_led(argv); + else if (strncmp(argv[1], "usb", 3) == 0) + rcode = do_usbtest(argv); + break; + case 3: + if (strncmp(argv[1], "rs232", 3) == 0) + rcode = do_rs232(argv); + break; + } + + switch (rcode) { + case -1: + printf("Usage:\n" + "fkt { i2c | led | usb }\n" + "fkt rs232 number\n"); + rcode = 1; + break; + case 0: + printf("Test passed\n"); + break; + default: + printf("Test failed with code: %d\n", rcode); + } + + return rcode; +} + +U_BOOT_CMD( + fkt, 4, 1, cmd_fkt, + "fkt - Function test routines\n", + "i2c\n" + " - Test I2C communication\n" + "fkt led\n" + " - Test LEDs\n" + "fkt rs232 number\n" + " - Test RS232 (loopback plug(s) for RS232 required)\n" + "fkt usb\n" + " - Test USB communication\n" +); +#endif /* CFG_CMD_BSP */ diff --git a/board/cm5200/config.mk b/board/cm5200/config.mk new file mode 100644 index 00000000000..7f061391a24 --- /dev/null +++ b/board/cm5200/config.mk @@ -0,0 +1,26 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xfc000000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/cm5200/fwupdate.c b/board/cm5200/fwupdate.c new file mode 100644 index 00000000000..19aa94a5a03 --- /dev/null +++ b/board/cm5200/fwupdate.c @@ -0,0 +1,200 @@ +/* + * (C) Copyright 2007 Schindler Lift Inc. + * (C) Copyright 2007 DENX Software Engineering + * + * Author: Michel Marti + * Adapted for U-Boot 1.2 by Piotr Kruszynski : + * - code clean-up + * - bugfix for overwriting bootargs by user + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +#include "fwupdate.h" + +extern int do_bootm(cmd_tbl_t *, int, int, char *[]); +extern long do_fat_read(const char *, void *, unsigned long, int); +extern int do_fat_fsload(cmd_tbl_t *, int, int, char *[]); + +static int load_rescue_image(ulong); + +void cm5200_fwupdate(void) +{ + cmd_tbl_t *bcmd; + char *rsargs; + char *tmp = NULL; + char ka[16]; + char *argv[3] = { "bootm", ka, NULL }; + + /* Check if rescue system is disabled... */ + if (getenv("norescue")) { + printf(LOG_PREFIX "Rescue System disabled.\n"); + return; + } + + /* Check if we have a USB storage device and load image */ + if (load_rescue_image(LOAD_ADDR)) + return; + + bcmd = find_cmd("bootm"); + if (!bcmd) + return; + + sprintf(ka, "%lx", LOAD_ADDR); + + /* prepare our bootargs */ + rsargs = getenv("rs-args"); + if (!rsargs) + rsargs = RS_BOOTARGS; + else { + tmp = malloc(strlen(rsargs+1)); + if (!tmp) { + printf(LOG_PREFIX "Memory allocation failed\n"); + return; + } + strcpy(tmp, rsargs); + rsargs = tmp; + } + + setenv("bootargs", rsargs); + + if (rsargs == tmp) + free(rsargs); + + printf(LOG_PREFIX "Starting update system (bootargs=%s)...\n", rsargs); + do_bootm(bcmd, 0, 2, argv); +} + +static int load_rescue_image(ulong addr) +{ + disk_partition_t info; + int devno; + int partno; + int i; + char fwdir[64]; + char nxri[128]; + char *tmp; + char dev[7]; + char addr_str[16]; + char *argv[6] = { "fatload", "usb", dev, addr_str, nxri, NULL }; + block_dev_desc_t *stor_dev = NULL; + cmd_tbl_t *bcmd; + + /* Get name of firmware directory */ + tmp = getenv("fw-dir"); + + /* Copy it into fwdir */ + strncpy(fwdir, tmp ? tmp : FW_DIR, sizeof(fwdir)); + fwdir[sizeof(fwdir) - 1] = 0; /* Terminate string */ + + printf(LOG_PREFIX "Checking for firmware image directory '%s' on USB" + " storage...\n", fwdir); + usb_stop(); + if (usb_init() != 0) + return 1; + + /* Check for storage device */ + if (usb_stor_scan(1) != 0) { + usb_stop(); + return 1; + } + + /* Detect storage device */ + for (devno = 0; devno < USB_MAX_STOR_DEV; devno++) { + stor_dev = usb_stor_get_dev(devno); + if (stor_dev->type != DEV_TYPE_UNKNOWN) + break; + } + if (!stor_dev || stor_dev->type == DEV_TYPE_UNKNOWN) { + printf(LOG_PREFIX "No valid storage device found...\n"); + usb_stop(); + return 1; + } + + /* Detect partition */ + for (partno = -1, i = 0; i < 6; i++) { + if (get_partition_info(stor_dev, i, &info) == 0) { + if (fat_register_device(stor_dev, i) == 0) { + /* Check if rescue image is present */ + FW_DEBUG("Looking for firmware directory '%s'" + " on partition %d\n", fwdir, i); + if (do_fat_read(fwdir, NULL, 0, LS_NO) == -1) { + FW_DEBUG("No NX rescue image on " + "partition %d.\n", i); + partno = -2; + } else { + partno = i; + FW_DEBUG("Partition %d contains " + "firmware directory\n", partno); + break; + } + } + } + } + + if (partno < 0) { + switch (partno) { + case -1: + printf(LOG_PREFIX "Error: No valid (FAT) partition " + "detected\n"); + break; + case -2: + printf(LOG_PREFIX "Error: No NX rescue image on FAT " + "partition\n"); + break; + default: + printf(LOG_PREFIX "Error: Failed with code %d\n", + partno); + } + usb_stop(); + return 1; + } + + /* Load the rescue image */ + bcmd = find_cmd("fatload"); + if (!bcmd) { + printf(LOG_PREFIX "Error - 'fatload' command not present.\n"); + usb_stop(); + return 1; + } + + tmp = getenv("nx-rescue-image"); + sprintf(nxri, "%s/%s", fwdir, tmp ? tmp : RESCUE_IMAGE); + sprintf(dev, "%d:%d", devno, partno); + sprintf(addr_str, "%lx", addr); + + FW_DEBUG("fat_fsload device='%s', addr='%s', file: %s\n", + dev, addr_str, nxri); + + if (do_fat_fsload(bcmd, 0, 5, argv) != 0) { + usb_stop(); + return 1; + } + + /* Stop USB */ + usb_stop(); + return 0; +} diff --git a/board/cm5200/fwupdate.h b/board/cm5200/fwupdate.h new file mode 100644 index 00000000000..4e3f1e164aa --- /dev/null +++ b/board/cm5200/fwupdate.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2007 Schindler Lift Inc. + * + * Author: Michel Marti + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FW_UPDATE_H +#define __FW_UPDATE_H + +/* Default prefix for output messages */ +#define LOG_PREFIX "CM5200:" + +/* Extra debug macro */ +#ifdef CONFIG_FWUPDATE_DEBUG +#define FW_DEBUG(fmt...) printf(LOG_PREFIX fmt) +#else +#define FW_DEBUG(fmt...) +#endif + +/* Name of the directory holding firmware images */ +#define FW_DIR "nx-fw" +#define RESCUE_IMAGE "nxrs.img" +#define LOAD_ADDR 0x400000 +#define RS_BOOTARGS "ramdisk=8192K" + +/* Main function for fwupdate */ +void cm5200_fwupdate(void); + +#endif /* __FW_UPDATE_H */ diff --git a/board/cm5200/u-boot.lds b/board/cm5200/u-boot.lds new file mode 100644 index 00000000000..8fa9c0f7ed5 --- /dev/null +++ b/board/cm5200/u-boot.lds @@ -0,0 +1,123 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc5xxx/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c index 3d99d5c1ec6..2b5b5278dcf 100644 --- a/cpu/mpc5xxx/fec.c +++ b/cpu/mpc5xxx/fec.c @@ -890,7 +890,7 @@ int mpc5xxx_fec_initialize(bd_t * bis) fec->tbdBase = (FEC_TBD *)FEC_BD_BASE; fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD)); #if defined(CONFIG_CANMB) || \ - defined(CONFIG_CM1_QP1) || \ + defined(CONFIG_CM5200) || \ defined(CONFIG_HMI1001) || \ defined(CONFIG_ICECUBE) || \ defined(CONFIG_INKA4X0) || \ diff --git a/include/configs/cm1_qp1.h b/include/configs/cm1_qp1.h deleted file mode 100644 index effa41c0525..00000000000 --- a/include/configs/cm1_qp1.h +++ /dev/null @@ -1,358 +0,0 @@ -/* - * (C) Copyright 2003-2007 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_CM1_QP1 1 /* ... on CM1.QP1 module */ - - -/* - * Supported commands - */ -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_ECHO | \ - CFG_CMD_I2C | \ - CFG_CMD_FLASH | \ - CFG_CMD_MII | \ - CFG_CMD_NFS | \ - CFG_CMD_PING | \ - CFG_CMD_DIAG | \ - CFG_CMD_REGINFO | \ - CFG_CMD_SNTP | \ - CFG_CMD_BSP | \ - CFG_CMD_USB | \ - CFG_CMD_FAT | \ - CFG_CMD_JFFS2) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -#define CONFIG_PHY_ADDR 0x00 -#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */ -/* use misc_init_r() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */ -#define CONFIG_MISC_INIT_R 1 -#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */ - - -/* - * POST support - */ -#define CONFIG_POST (CFG_POST_MEMORY | CFG_POST_CPU | CFG_POST_I2C) -#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) -/* List of I2C addresses to be verified by POST */ -#define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM } - - -/* display image timestamps */ -#define CONFIG_TIMESTAMP 1 - - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \ - "echo" -#undef CONFIG_BOOTARGS - -/* - * Default environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=cm1_qp1\0" \ - "netmask=255.255.0.0\0" \ - "ipaddr=192.168.160.33\0" \ - "serverip=192.168.1.1\0" \ - "gatewayip=192.168.1.1\0" \ - "console=ttyPSC0\0" \ - "u-boot_addr=100000\0" \ - "kernel_addr=200000\0" \ - "kernel_addr_flash=fc0c0000\0" \ - "fdt_addr=400000\0" \ - "fdt_addr_flash=fc0a0000\0" \ - "ramdisk_addr=500000\0" \ - "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ - "u-boot=/tftpboot/cm1_qp1/u-boot.bin\0" \ - "bootfile=/tftpboot/cm1_qp1/uImage\0" \ - "fdt_file=/tftpboot/cm1_qp1/cm1_qp1.dtb\0" \ - "load=tftp ${u-boot_addr} ${u-boot}\0" \ - "update=prot off fc000000 fc05ffff; era fc000000 fc05ffff; " \ - "cp.b ${u-boot_addr} fc000000 ${filesize}; " \ - "prot on fc000000 fc05ffff\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off panic=1\0" \ - "flash_flash=run flashargs addinit addip addcons;" \ - "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \ - "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \ - "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \ - "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_flash" - - -/* - * Low level configuration - */ - - -/* - * Clock configuration - */ -#define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */ -#define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */ - - -/* - * Memory map - */ -#define CFG_MBAR 0xF0000000 -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_DEFAULT_MBAR 0x80000000 - -#define CFG_LOWBOOT 1 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - -#define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -#define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ -#define CFG_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */ -#define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ - -#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) -#define CFG_RAMBOOT 1 -#endif - - -/* - * Chip selects configuration - */ -/* Boot Chipselect */ -#define CFG_BOOTCS_START CFG_FLASH_BASE -#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE -#define CFG_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */ -/* use board_early_init_r to enable flash write in CS_BOOT */ -#define CONFIG_BOARD_EARLY_INIT_R - -/* Flash memory addressing */ -#define CFG_CS0_START CFG_FLASH_BASE -#define CFG_CS0_SIZE CFG_FLASH_SIZE - -/* No burst, dead cycle = 1 for CS0 (Flash) */ -#define CFG_CS_BURST 0x00000000 -#define CFG_CS_DEADCYCLE 0x00000001 - - -/* - * SDRAM configuration - * settings for k4s561632E-xx75, assuming XLB = 132 MHz - */ -#define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */ -#define SDRAM_CONTROL 0x514F0000 -#define SDRAM_CONFIG1 0xE2333900 -#define SDRAM_CONFIG2 0x8EE70000 - - -/* - * Flash configuration - */ -#define CFG_FLASH_CFI 1 -#define CFG_FLASH_CFI_DRIVER 1 -#define CFG_FLASH_BASE TEXT_BASE -/* we need these despite using CFI */ -#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */ -#define CFG_FLASH_SIZE 0x02000000 /* 32 MiB */ - - -/* - * MTD configuration - */ -#define CONFIG_JFFS2_CMDLINE 1 -#define MTDIDS_DEFAULT "nor0=cm1qp1-0" -#define MTDPARTS_DEFAULT "mtdparts=cm1qp1-0:" \ - "384k(uboot),128k(env)," \ - "128k(redund_env),128k(dtb)," \ - "2m(kernel),27904k(rootfs)," \ - "-(config)" - - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #2 */ -#define CFG_I2C_SPEED 40000 /* 40 kHz */ -#define CFG_I2C_SLAVE 0x0 -#define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */ -#define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */ - - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - - -/* - * USB configuration - */ -#define CONFIG_USB_OHCI 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_USB_CLOCK 0x0001BBBB -#define CONFIG_USB_CONFIG 0x00001000 -/* Partitions (for USB) */ -#define CONFIG_MAC_PARTITION 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_ISO_PARTITION 1 - -/* - * Invoke our last_stage_init function - needed by fwupdate - */ -#define CONFIG_LAST_STAGE_INIT 1 - -/* - * Environment settings - */ -#define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_SIZE 0x10000 -#define CFG_ENV_SECT_SIZE 0x20000 -#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) -/* Configuration of redundant environment */ -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) -#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) - - -/* - * Pin multiplexing configuration - */ - -/* - * CS1/GPIO_WKUP_6: GPIO (default) - * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1 - * IRDA/PSC6: UART - * Ether: Ethernet 100Mbit with MD - * PCI_DIS: PCI controller disabled - * USB: USB - * PSC3: SPI with UART3 - * PSC2: UART - * PSC1: UART - */ -#define CFG_GPS_PORT_CONFIG 0x10559C44 - - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP 1 /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ - -#define CFG_ALT_MEMTEST 1 -#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */ - -#define CONFIG_LOOPW 1 - -#define CFG_LOAD_ADDR 0x100000 /* default load address */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ - - -/* - * Various low-level settings - */ -#define CFG_HID0_INIT HID0_ICE | HID0_ICFI -#define CFG_HID0_FINAL HID0_ICE - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */ - - -/* - * Cache Configuration - */ -#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - - -/* - * Flat Device Tree support - */ -#define CONFIG_OF_FLAT_TREE 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define OF_FLAT_TREE_MAX_SIZE 8192 /* max size of the flat tree (8K) */ -#define OF_CPU "PowerPC,5200@0" -#define OF_SOC "soc5200@f0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" - -#endif /* __CONFIG_H */ diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h new file mode 100644 index 00000000000..76628560e5a --- /dev/null +++ b/include/configs/cm5200.h @@ -0,0 +1,362 @@ +/* + * (C) Copyright 2003-2007 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ +#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ +#define CONFIG_CM5200 1 /* ... on CM5200 platform */ + + +/* + * Supported commands + */ +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_I2C | \ + CFG_CMD_FLASH | \ + CFG_CMD_MII | \ + CFG_CMD_NFS | \ + CFG_CMD_PING | \ + CFG_CMD_DIAG | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SNTP | \ + CFG_CMD_BSP | \ + CFG_CMD_USB | \ + CFG_CMD_FAT | \ + CFG_CMD_JFFS2) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + + +/* + * Serial console configuration + */ +#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ +#define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CONFIG_SILENT_CONSOLE 1 /* needed to silence i2c_init() */ + + +/* + * Ethernet configuration + */ +#define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_PHY_ADDR 0x00 +#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */ +/* use misc_init_r() to read ethaddr from I2C EEPROM (see CFG_I2C_EEPROM) */ +#define CONFIG_MISC_INIT_R 1 +#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */ + + +/* + * POST support + */ +#define CONFIG_POST (CFG_POST_MEMORY | CFG_POST_CPU | CFG_POST_I2C) +#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4) +/* List of I2C addresses to be verified by POST */ +#define I2C_ADDR_LIST { CFG_I2C_SLAVE, CFG_I2C_IO, CFG_I2C_EEPROM } + + +/* display image timestamps */ +#define CONFIG_TIMESTAMP 1 + + +/* + * Autobooting + */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \ + "echo" +#undef CONFIG_BOOTARGS + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "netmask=255.255.0.0\0" \ + "ipaddr=192.168.160.33\0" \ + "serverip=192.168.1.1\0" \ + "gatewayip=192.168.1.1\0" \ + "console=ttyPSC0\0" \ + "u-boot_addr=100000\0" \ + "kernel_addr=200000\0" \ + "kernel_addr_flash=fc0c0000\0" \ + "fdt_addr=400000\0" \ + "fdt_addr_flash=fc0a0000\0" \ + "ramdisk_addr=500000\0" \ + "rootpath=/opt/eldk-4.1/ppc_6xx\0" \ + "u-boot=/tftpboot/cm5200/u-boot.bin\0" \ + "bootfile_fdt=/tftpboot/cm5200/uImage\0" \ + "fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \ + "load=tftp ${u-boot_addr} ${u-boot}\0" \ + "update=prot off fc000000 +${filesize}; " \ + "era fc000000 +${filesize}; " \ + "cp.b ${u-boot_addr} fc000000 ${filesize}; " \ + "prot on fc000000 +${filesize}\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \ + "addcons=setenv bootargs ${bootargs} " \ + "console=${console},${baudrate}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off panic=1\0" \ + "flash_flash=run flashargs addinit addip addcons;" \ + "bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \ + "net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \ + "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \ + "addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_flash" + + +/* + * Low level configuration + */ + + +/* + * Clock configuration + */ +#define CFG_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */ +#define CFG_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */ + + +/* + * Memory map + */ +#define CFG_MBAR 0xF0000000 +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_DEFAULT_MBAR 0x80000000 + +#define CFG_LOWBOOT 1 + +/* Use ON-Chip SRAM until RAM will be available */ +#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM +#ifdef CONFIG_POST +/* preserve space for the post_word at end of on-chip SRAM */ +#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE +#else +#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE +#endif + +#define CFG_GBL_DATA_SIZE 128 /* size in bytes for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CONFIG_BOARD_TYPES 1 /* we use board_type */ + +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */ +#define CFG_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */ + +/* + * Flash configuration + */ +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 +#define CFG_FLASH_BASE 0xfc000000 +/* we need these despite using CFI */ +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 256 /* max num of sectors on one chip */ +#define CFG_FLASH_SIZE 0x02000000 /* 32 MiB */ + + +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT 1 +#undef CFG_LOWBOOT +#endif + + +/* + * Chip selects configuration + */ +/* Boot Chipselect */ +#define CFG_BOOTCS_START CFG_FLASH_BASE +#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE +#define CFG_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */ +/* use board_early_init_r to enable flash write in CS_BOOT */ +#define CONFIG_BOARD_EARLY_INIT_R + +/* Flash memory addressing */ +#define CFG_CS0_START CFG_FLASH_BASE +#define CFG_CS0_SIZE CFG_FLASH_SIZE + +/* No burst, dead cycle = 1 for CS0 (Flash) */ +#define CFG_CS_BURST 0x00000000 +#define CFG_CS_DEADCYCLE 0x00000001 + + +/* + * SDRAM configuration + * settings for k4s561632E-xx75, assuming XLB = 132 MHz + */ +#define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */ +#define SDRAM_CONTROL 0x514F0000 +#define SDRAM_CONFIG1 0xE2333900 +#define SDRAM_CONFIG2 0x8EE70000 + + + +/* + * MTD configuration + */ +#define CONFIG_JFFS2_CMDLINE 1 +#define MTDIDS_DEFAULT "nor0=cm5200-0" +#define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \ + "384k(uboot),128k(env)," \ + "128k(redund_env),128k(dtb)," \ + "2m(kernel),27904k(rootfs)," \ + "-(config)" + + +/* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#define CFG_I2C_MODULE 2 /* Select I2C module #2 */ +#define CFG_I2C_SPEED 40000 /* 40 kHz */ +#define CFG_I2C_SLAVE 0x0 +#define CFG_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */ +#define CFG_I2C_EEPROM 0x53 /* I2C EEPROM device address */ + + +/* + * RTC configuration + */ +#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ + + +/* + * USB configuration + */ +#define CONFIG_USB_OHCI 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_USB_CLOCK 0x0001BBBB +#define CONFIG_USB_CONFIG 0x00001000 +/* Partitions (for USB) */ +#define CONFIG_MAC_PARTITION 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_ISO_PARTITION 1 + +/* + * Invoke our last_stage_init function - needed by fwupdate + */ +#define CONFIG_LAST_STAGE_INIT 1 + +/* + * Environment settings + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x10000 +#define CFG_ENV_SECT_SIZE 0x20000 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) +/* Configuration of redundant environment */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + + +/* + * Pin multiplexing configuration + */ + +/* + * CS1/GPIO_WKUP_6: GPIO (default) + * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1 + * IRDA/PSC6: UART + * Ether: Ethernet 100Mbit with MD + * PCI_DIS: PCI controller disabled + * USB: USB + * PSC3: SPI with UART3 + * PSC2: UART + * PSC1: UART + */ +#define CFG_GPS_PORT_CONFIG 0x10559C44 + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP 1 /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_ALT_MEMTEST 1 +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */ + +#define CONFIG_LOOPW 1 + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + + +/* + * Various low-level settings + */ +#define CFG_HID0_INIT HID0_ICE | HID0_ICFI +#define CFG_HID0_FINAL HID0_ICE + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_XLB_PIPELINING 1 /* enable transaction pipeling */ + + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + + +/* + * Flat Device Tree support + */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define OF_CPU "PowerPC,5200@0" +#define OF_SOC "soc5200@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 63cec5814fab5d2b1c86982327433807a5ac0249 Mon Sep 17 00:00:00 2001 From: Ed Swarthout Date: Thu, 2 Aug 2007 14:09:49 -0500 Subject: Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. All of the PCI/PCI-Express driver and initialization code that was in the MPC8641HPCN port has now been moved into the common drivers/fsl_pci_init.c. In a subsequent patch, this will be utilized by the 85xx ports as well. Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. Also enable the second PCI-Express controller on 8641 by getting its BATS and CFG_ setup right. Fixed a u16 vendor compiler warning in AHCI driver too. Signed-off-by: Ed Swarthout Signed-off-by: Zhang Wei Signed-off-by: Jon Loeliger --- board/mpc8641hpcn/mpc8641hpcn.c | 165 +++++++++++++++++++++++++-------- board/mpc8641hpcn/u-boot.lds | 1 - cpu/mpc86xx/Makefile | 3 +- cpu/mpc86xx/pci.c | 146 ----------------------------- cpu/mpc86xx/pcie_indirect.c | 199 ---------------------------------------- drivers/Makefile | 2 +- drivers/ahci.c | 3 +- drivers/fsl_pci_init.c | 180 ++++++++++++++++++++++++++++++++++++ include/asm-ppc/immap_fsl_pci.h | 150 ++++++++++++++++++++++++++++++ include/configs/MPC8641HPCN.h | 44 +++++---- include/pci.h | 6 ++ 11 files changed, 493 insertions(+), 406 deletions(-) delete mode 100644 cpu/mpc86xx/pci.c delete mode 100644 cpu/mpc86xx/pcie_indirect.c create mode 100644 drivers/fsl_pci_init.c create mode 100644 include/asm-ppc/immap_fsl_pci.h (limited to 'include') diff --git a/board/mpc8641hpcn/mpc8641hpcn.c b/board/mpc8641hpcn/mpc8641hpcn.c index 5e02cc5a5e6..d2182aba5f0 100644 --- a/board/mpc8641hpcn/mpc8641hpcn.c +++ b/board/mpc8641hpcn/mpc8641hpcn.c @@ -11,7 +11,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -55,37 +56,6 @@ int checkboard(void) { puts("Board: MPC8641HPCN\n"); -#ifdef CONFIG_PCI - - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_gur_t *gur = &immap->im_gur; - volatile ccsr_pex_t *pex1 = &immap->im_pex1; - - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; -#ifdef DEBUG - uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); -#endif - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 - || io_sel == 6 || io_sel == 7 || io_sel == 0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); - debug("0x%08x=0x%08x ", &pex1->pme_msg_det, pex1->pme_msg_det); - if (pex1->pme_msg_det) { - pex1->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pex1->pme_msg_det); - } - debug("\n"); - } else { - puts("PCI-EXPRESS 1: Disabled\n"); - } - -#else - puts("PCI-EXPRESS1: Disabled\n"); -#endif - return 0; } @@ -220,21 +190,138 @@ static struct pci_config_table pci_fsl86xxads_config_table[] = { #endif -static struct pci_controller hose = { +static struct pci_controller pci1_hose = { #ifndef CONFIG_PCI_PNP - config_table:pci_mpc86xxcts_config_table, + config_table:pci_mpc86xxcts_config_table #endif }; - #endif /* CONFIG_PCI */ +#ifdef CONFIG_PCI2 +static struct pci_controller pci2_hose; +#endif /* CONFIG_PCI2 */ + +int first_free_busno = 0; + + void pci_init_board(void) { -#ifdef CONFIG_PCI - extern void pci_mpc86xx_init(struct pci_controller *hose); + volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; + volatile ccsr_gur_t *gur = &immap->im_gur; + uint devdisr = gur->devdisr; + uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; + +#ifdef CONFIG_PCI1 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; +#ifdef DEBUG + uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; + uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); +#endif + if ((io_sel == 2 || io_sel == 3 || io_sel == 5 + || io_sel == 6 || io_sel == 7 || io_sel == 0xF) + && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); + debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug(" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + debug("\n"); + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); + + /* + * Activate ULI1575 legacy chip by performing a fake + * memory access. Needed to make ULI RTC work. + */ + in_be32((unsigned *) CFG_PCI1_MEM_BASE + + CFG_PCI1_MEM_SIZE - 0x1000000); + + } else { + puts("PCI-EXPRESS 1: Disabled\n"); + } +} +#else + puts("PCI-EXPRESS1: Disabled\n"); +#endif /* CONFIG_PCI1 */ + +#ifdef CONFIG_PCI2 +{ + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci2_hose; + + + /* inbound */ + pci_set_region(hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region(hose->regions + 1, + CFG_PCI2_MEM_BASE, + CFG_PCI2_MEM_PHYS, + CFG_PCI2_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(hose->regions + 2, + CFG_PCI2_IO_BASE, + CFG_PCI2_IO_PHYS, + CFG_PCI2_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno=first_free_busno; + pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data); + + fsl_pci_init(hose); + + first_free_busno=hose->last_busno+1; + printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", + hose->first_busno,hose->last_busno); +} +#else + puts("PCI-EXPRESS 2: Disabled\n"); +#endif /* CONFIG_PCI2 */ - pci_mpc86xx_init(&hose); -#endif /* CONFIG_PCI */ } #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds index 34b50e4be20..e4792ef1998 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/mpc8641hpcn/u-boot.lds @@ -57,7 +57,6 @@ SECTIONS cpu/mpc86xx/cpu_init.o (.text) cpu/mpc86xx/cpu.o (.text) cpu/mpc86xx/speed.o (.text) - cpu/mpc86xx/pci.o (.text) common/dlmalloc.o (.text) lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile index fffcfd24029..6d9300e22e7 100644 --- a/cpu/mpc86xx/Makefile +++ b/cpu/mpc86xx/Makefile @@ -1,4 +1,5 @@ # +# Copyright 2007 Freescale Semiconductor, Inc. # (C) Copyright 2002,2003 Motorola Inc. # Xianghua Xiao,X.Xiao@motorola.com # @@ -30,7 +31,7 @@ LIB = $(obj)lib$(CPU).a START = start.o #resetvec.o SOBJS = cache.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ - pci.o pcie_indirect.o spd_sdram.o + spd_sdram.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc86xx/pci.c b/cpu/mpc86xx/pci.c deleted file mode 100644 index b86548db4f9..00000000000 --- a/cpu/mpc86xx/pci.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor,Inc. - * 2005, 2006. All rights reserved. - * - * Ed Swarthout (ed.swarthout@freescale.com) - * Jason Jin (Jason.jin@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * PCIE Configuration space access support for PCIE Bridge - */ -#include -#include - -#if defined(CONFIG_PCI) -void -pci_mpc86xx_init(struct pci_controller *hose) -{ - volatile immap_t *immap = (immap_t *) CFG_CCSRBAR; - volatile ccsr_pex_t *pcie1 = &immap->im_pex1; - u16 temp16; - u32 temp32; - - volatile ccsr_gur_t *gur = &immap->im_gur; - uint host1_agent = (gur->porbmsr & MPC86xx_PORBMSR_HA) >> 17; - uint pcie1_host = (host1_agent == 2) || (host1_agent == 3); - uint pcie1_agent = (host1_agent == 0) || (host1_agent == 1); - uint devdisr = gur->devdisr; - uint io_sel = (gur->pordevsr & MPC86xx_PORDEVSR_IO_SEL) >> 16; - - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 || io_sel == 6 || - io_sel == 7 || io_sel == 0xf) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - printf("PCI-EXPRESS 1: Configured as %s \n", - pcie1_agent ? "Agent" : "Host"); - if (pcie1_agent) - return; /*Don't scan bus when configured as agent */ - printf(" Scanning PCIE bus"); - debug("0x%08x=0x%08x ", - &pcie1->pme_msg_det, - pcie1->pme_msg_det); - if (pcie1->pme_msg_det) { - pcie1->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pcie1->pme_msg_det); - } - debug("\n"); - } else { - printf("PCI-EXPRESS 1 disabled!\n"); - return; - } - - /* - * Set first_bus=0 only skipped B0:D0:F0 which is - * a reserved device in M1575, but make it easy for - * most of the scan process. - */ - hose->first_busno = 0x00; - hose->last_busno = 0xfe; - - pcie_setup_indirect(hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004)); - - pci_hose_read_config_word(hose, - PCI_BDF(0, 0, 0), PCI_COMMAND, &temp16); - temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_hose_write_config_word(hose, - PCI_BDF(0, 0, 0), PCI_COMMAND, temp16); - - pci_hose_write_config_word(hose, PCI_BDF(0, 0, 0), PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, - PCI_BDF(0, 0, 0), PCI_LATENCY_TIMER, 0x80); - - pci_hose_read_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, - &temp32); - temp32 = (temp32 & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16); - pci_hose_write_config_dword(hose, PCI_BDF(0, 0, 0), PCI_PRIMARY_BUS, - temp32); - - pcie1->powar1 = 0; - pcie1->powar2 = 0; - pcie1->piwar1 = 0; - pcie1->piwar1 = 0; - - pcie1->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcie1->powar1 = 0x8004401c; /* 512M MEM space */ - pcie1->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff; - pcie1->potear1 = 0x00000000; - - pcie1->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff; - pcie1->powar2 = 0x80088017; /* 16M IO space */ - pcie1->potar2 = 0x00000000; - pcie1->potear2 = 0x00000000; - - pcie1->pitar1 = 0x00000000; - pcie1->piwbar1 = 0x00000000; - /* Enable, Prefetch, Local Mem, * Snoop R/W, 2G */ - pcie1->piwar1 = 0xa0f5501e; - - pci_set_region(hose->regions + 0, - CFG_PCI_MEMORY_BUS, - CFG_PCI_MEMORY_PHYS, - CFG_PCI_MEMORY_SIZE, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - pci_set_region(hose->regions + 1, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, - PCI_REGION_MEM); - - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = 3; - - pci_register_hose(hose); - - hose->last_busno = pci_hose_scan(hose); - debug("pcie_mpc86xx_init: last_busno %x\n", hose->last_busno); - debug("pcie_mpc86xx init: current_busno %x\n ", hose->current_busno); - - printf("....PCIE1 scan & enumeration done\n"); -} -#endif /* CONFIG_PCI */ diff --git a/cpu/mpc86xx/pcie_indirect.c b/cpu/mpc86xx/pcie_indirect.c deleted file mode 100644 index b00ad76ab89..00000000000 --- a/cpu/mpc86xx/pcie_indirect.c +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Support for indirect PCI bridges. - * - * Copyright (c) Freescale Semiconductor, Inc. - * 2006. All rights reserved. - * - * Jason Jin - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - * partly derived from - * arch/powerpc/platforms/86xx/mpc86xx_pcie.c - */ - -#include - -#ifdef CONFIG_PCI - -#include -#include -#include - -#define PCI_CFG_OUT out_be32 -#define PEX_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff) - -static int -indirect_read_config_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - int len, - u32 *val) -{ - int bus = PCI_BUS(dev); - - volatile unsigned char *cfg_data; - u32 temp; - - PEX_FIX; - if (bus == 0xff) { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000001); - } else { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000000); - } - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ - cfg_data = hose->cfg_data; - PEX_FIX; - temp = in_le32((u32 *) cfg_data); - switch (len) { - case 1: - *val = (temp >> (((offset & 3)) * 8)) & 0xff; - break; - case 2: - *val = (temp >> (((offset & 3)) * 8)) & 0xffff; - break; - default: - *val = temp; - break; - } - - return 0; -} - -static int -indirect_write_config_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - int len, - u32 val) -{ - int bus = PCI_BUS(dev); - volatile unsigned char *cfg_data; - u32 temp; - - PEX_FIX; - if (bus == 0xff) { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000001); - } else { - PCI_CFG_OUT(hose->cfg_addr, - dev | (offset & 0xfc) | 0x80000000); - } - - /* - * Note: the caller has already checked that offset is - * suitably aligned and that len is 1, 2 or 4. - */ - /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */ - cfg_data = hose->cfg_data; - switch (len) { - case 1: - PEX_FIX; - temp = in_le32((u32 *) cfg_data); - temp = (temp & ~(0xff << ((offset & 3) * 8))) | - (val << ((offset & 3) * 8)); - PEX_FIX; - out_le32((u32 *) cfg_data, temp); - break; - case 2: - PEX_FIX; - temp = in_le32((u32 *) cfg_data); - temp = (temp & ~(0xffff << ((offset & 3) * 8))); - temp |= (val << ((offset & 3) * 8)); - PEX_FIX; - out_le32((u32 *) cfg_data, temp); - break; - default: - PEX_FIX; - out_le32((u32 *) cfg_data, val); - break; - } - PEX_FIX; - return 0; -} - -static int -indirect_read_config_byte_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u8 *val) -{ - u32 val32; - indirect_read_config_pcie(hose, dev, offset, 1, &val32); - *val = (u8) val32; - return 0; -} - -static int -indirect_read_config_word_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u16 *val) -{ - u32 val32; - indirect_read_config_pcie(hose, dev, offset, 2, &val32); - *val = (u16) val32; - return 0; -} - -static int -indirect_read_config_dword_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u32 *val) -{ - return indirect_read_config_pcie(hose, dev, offset, 4, val); -} - -static int -indirect_write_config_byte_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u8 val) -{ - return indirect_write_config_pcie(hose, dev, offset, 1, (u32) val); -} - -static int -indirect_write_config_word_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - unsigned short val) -{ - return indirect_write_config_pcie(hose, dev, offset, 2, (u32) val); -} - -static int -indirect_write_config_dword_pcie(struct pci_controller *hose, - pci_dev_t dev, - int offset, - u32 val) -{ - return indirect_write_config_pcie(hose, dev, offset, 4, val); -} - -void -pcie_setup_indirect(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) -{ - pci_set_ops(hose, - indirect_read_config_byte_pcie, - indirect_read_config_word_pcie, - indirect_read_config_dword_pcie, - indirect_write_config_byte_pcie, - indirect_write_config_word_pcie, - indirect_write_config_dword_pcie); - - hose->cfg_addr = (unsigned int *)cfg_addr; - hose->cfg_data = (unsigned char *)cfg_data; -} - -#endif /* CONFIG_PCI */ diff --git a/drivers/Makefile b/drivers/Makefile index 48fd4eaade0..fa2e86fd20f 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -52,7 +52,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \ ks8695eth.o \ pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ rpx_pcmcia.o \ - fsl_i2c.o + fsl_i2c.o fsl_pci_init.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/ahci.c b/drivers/ahci.c index 8ceff00925f..ccd4d71e8ae 100644 --- a/drivers/ahci.c +++ b/drivers/ahci.c @@ -253,7 +253,8 @@ static void ahci_print_info(struct ahci_probe_ent *probe_ent) static int ahci_init_one(pci_dev_t pdev) { - u32 iobase, vendor; + u32 iobase; + u16 vendor; int rc; memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); diff --git a/drivers/fsl_pci_init.c b/drivers/fsl_pci_init.c new file mode 100644 index 00000000000..1d1f6df997a --- /dev/null +++ b/drivers/fsl_pci_init.c @@ -0,0 +1,180 @@ +/* + * Copyright 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define DEBUG +#include + +#ifdef CONFIG_FSL_PCI_INIT + +/* + * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's + * + * Initialize controller and call the common driver/pci pci_hose_scan to + * scan for bridges and devices. + * + * Hose fields which need to be pre-initialized by board specific code: + * regions[] + * first_busno + * + * Fields updated: + * last_busno + */ + +#include +#include + +void pciauto_prescan_setup_bridge(struct pci_controller *hose, + pci_dev_t dev, int sub_bus); +void pciauto_postscan_setup_bridge(struct pci_controller *hose, + pci_dev_t dev, int sub_bus); + +void pciauto_config_init(struct pci_controller *hose); +void +fsl_pci_init(struct pci_controller *hose) +{ + u16 temp16; + u32 temp32; + int busno = hose->first_busno; + int enabled; + u16 ltssm; + u8 temp8; + int r; + int bridge; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr; + pci_dev_t dev = PCI_BDF(busno,0,0); + + /* Initialize ATMU registers based on hose regions and flags */ + volatile pot_t *po=&pci->pot[1]; /* skip 0 */ + volatile pit_t *pi=&pci->pit[0]; /* ranges from: 3 to 1 */ + +#ifdef DEBUG + int neg_link_w; +#endif + + for (r=0; rregion_count; r++) { + if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */ + pi->pitar = (hose->regions[r].bus_start >> 12) & 0x000fffff; + pi->piwbar = (hose->regions[r].phys_start >> 12) & 0x000fffff; + pi->piwbear = 0; + pi->piwar = PIWAR_EN | PIWAR_PF | PIWAR_LOCAL | + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | + (__ilog2(hose->regions[r].size) - 1); + pi++; + } else { /* Outbound */ + po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff; + po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff; + po->potear = 0; + if (hose->regions[r].flags & PCI_REGION_IO) + po->powar = POWAR_EN | POWAR_IO_READ | POWAR_IO_WRITE | + (__ilog2(hose->regions[r].size) - 1); + else + po->powar = POWAR_EN | POWAR_MEM_READ | POWAR_MEM_WRITE | + (__ilog2(hose->regions[r].size) - 1); + po++; + } + } + + pci_register_hose(hose); + pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */ + hose->current_busno = hose->first_busno; + + pci->pedr = 0xffffffff; /* Clear any errors */ + pci->peer = 0xffffffff; /* Enable Error Interupts */ + pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32); + temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */ + pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32); + + pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8); + bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */ + + if ( bridge ) { + + pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); + enabled = ltssm >= PCI_LTSSM_L0; + + if (!enabled) { + debug("....PCIE link error. Skipping scan." + "LTSSM=0x%02x\n", temp16); + hose->last_busno = hose->first_busno; + return; + } + + pci->pme_msg_det = 0xffffffff; + pci->pme_msg_int_en = 0xffffffff; +#ifdef DEBUG + pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16); + neg_link_w = (temp16 & 0x3f0 ) >> 4; + debug("...PCIE LTSSM=0x%x, Negotiated link width=%d\n", + ltssm, neg_link_w); +#endif + hose->current_busno++; /* Start scan with secondary */ + pciauto_prescan_setup_bridge(hose, dev, hose->current_busno); + + } else { +#if 0 +/* done in pci_hose_config_device() */ + pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16); + temp16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_hose_write_config_word(hose, dev, PCI_COMMAND, temp16); + pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); + pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); +#endif + } + + /* Call setup to allocate PCSRBAR window */ + pciauto_setup_device(hose, dev, 1, hose->pci_mem, + hose->pci_prefetch, hose->pci_io); + + printf (" Scanning PCI bus %02x\n", hose->current_busno); + hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno); + + if ( bridge ) { /* update limit regs and subordinate busno */ + pciauto_postscan_setup_bridge(hose, dev, hose->last_busno); + } + + /* Clear all error indications */ + + if (pci->pme_msg_det && pci->pme_msg_det != 0xffffffff) { + debug("pci_fsl_init: pme_msg_det@%x=%x. Clearing\n", + &pci->pme_msg_det, pci->pme_msg_det); + pci->pme_msg_det = 0xffffffff; + } + + if (pci->pedr) { + debug("pci_fsl_init: pedr@%x=%x. Clearing\n", + &pci->pedr, pci->pedr); + pci->pedr = 0xffffffff; + } + + pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16); + if (temp16) { + debug("pci_fsl_init: PCI_DSR@%x=%x. Clearing\n", + PCI_DSR, temp16); + pci_hose_write_config_word(hose, dev, + PCI_DSR, 0xffff); + } + + pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16); + if (temp16) { + debug("pci_fsl_init: PCI_SEC_STATUS@%x=%x. Clearing\n", + PCI_SEC_STATUS, temp16); + pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff); + } +} + +#endif /* CONFIG_FSL_PCI */ diff --git a/include/asm-ppc/immap_fsl_pci.h b/include/asm-ppc/immap_fsl_pci.h new file mode 100644 index 00000000000..bd732b66889 --- /dev/null +++ b/include/asm-ppc/immap_fsl_pci.h @@ -0,0 +1,150 @@ +/* (C) Copyright 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef __IMMAP_85xx_fsl_pci__ +#define __IMMAP_85xx_fsl_pci__ + +/* + * Common PCI/PCIE Register structure for mpc85xx and mpc86xx + */ + +/* + * PCI Translation Registers + */ +typedef struct pci_outbound_window { + u32 potar; /* 0x00 - Address */ + u32 potear; /* 0x04 - Address Extended */ + u32 powbar; /* 0x08 - Window Base Address */ + u32 res1; + u32 powar; /* 0x10 - Window Attributes */ +#define POWAR_EN 0x80000000 +#define POWAR_IO_READ 0x00080000 +#define POWAR_MEM_READ 0x00040000 +#define POWAR_IO_WRITE 0x00008000 +#define POWAR_MEM_WRITE 0x00004000 + u32 res2[3]; +} pot_t; + +typedef struct pci_inbound_window { + u32 pitar; /* 0x00 - Address */ + u32 res1; + u32 piwbar; /* 0x08 - Window Base Address */ + u32 piwbear; /* 0x0c - Window Base Address Extended */ + u32 piwar; /* 0x10 - Window Attributes */ +#define PIWAR_EN 0x80000000 +#define PIWAR_PF 0x20000000 +#define PIWAR_LOCAL 0x00f00000 +#define PIWAR_READ_SNOOP 0x00050000 +#define PIWAR_WRITE_SNOOP 0x00005000 + u32 res2[3]; +} pit_t; + +/* PCI/PCI Express Registers */ +typedef struct ccsr_pci { + u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */ + u32 cfg_data; /* 0x004 - PCI Configuration Data Register */ + u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */ + u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */ + u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */ + u32 config; /* 0x014 - PCIE CONFIG Register */ + char res2[8]; + u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */ + u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ + u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ + u32 pm_command; /* 0x02c - PCIE PM Command register */ + char res4[3016]; /* (- #xbf8 #x30)3016 */ + u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ + u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ + + pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */ + u32 res5[64]; + pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */ +#define PIT3 0 +#define PIT2 1 +#define PIT1 2 + +#if 0 + u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */ + u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */ + char res5[8]; + u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */ + char res6[12]; + u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */ + u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */ + u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */ + char res7[4]; + u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */ + char res8[12]; + u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */ + u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */ + u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */ + char res9[4]; + u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */ + char res10[12]; + u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */ + u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */ + u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */ + char res11[4]; + u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */ + char res12[12]; + u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */ + u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */ + u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */ + char res13[4]; + u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */ + char res14[268]; + u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */ + char res15[4]; + u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */ + u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */ + u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */ + char res16[12]; + u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */ + char res17[4]; + u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */ + u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */ + u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */ + char res18[12]; + u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */ + char res19[4]; + u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */ + char res20[4]; + u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */ + char res21[12]; +#endif + u32 pedr; /* 0xe00 - PCI Error Detect Register */ + u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */ + u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */ + u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */ + u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */ +/* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */ + u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */ + u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */ + u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */ + u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */ +/* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */ + char res22[4]; + u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */ + u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */ + u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */ + u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ + char res23[456]; /* (- #x1000 #xe38) 456 */ +} ccsr_fsl_pci_t; + +#endif /*__IMMAP_fsl_pci__*/ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 808c19f7673..5a511e53244 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -46,8 +46,10 @@ #define CFG_RESET_ADDRESS 0xfff00100 -/*#undef CONFIG_PCI*/ -#define CONFIG_PCI +#define CONFIG_PCI 1 /* Enable PCI/PCIE */ +#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ +#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -76,6 +78,9 @@ #define L2_ENABLE (L2CR_L2E) #ifndef CONFIG_SYS_CLK_FREQ +#ifndef __ASSEMBLY__ +extern unsigned long get_board_sys_clk(unsigned long dummy); +#endif #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) #endif @@ -93,6 +98,9 @@ #define CFG_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ +#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) +#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000) + /* * DDR Setup */ @@ -296,9 +304,9 @@ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ /* PCI view of System Memory */ #define CFG_PCI_MEMORY_BUS 0x00000000 @@ -311,10 +319,10 @@ #define CFG_PCI2_MEM_BASE 0xa0000000 #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE -#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CFG_PCI2_IO_BASE 0xe3000000 -#define CFG_PCI2_IO_PHYS CFG_PCI2_IO_BASE -#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCI2_IO_BASE 0x00000000 +#define CFG_PCI2_IO_PHYS 0xe3000000 +#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */ #if defined(CONFIG_PCI) @@ -396,20 +404,20 @@ * 0xa000_0000 512M PCI-Express 2 Memory * Changed it for operating from 0xd0000000 */ -#define CFG_DBAT1L ( CFG_PCI1_MEM_BASE | BATL_PP_RW \ +#define CFG_DBAT1L ( CFG_PCI1_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT1U (CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CFG_IBAT1L (CFG_PCI1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_DBAT1U (CFG_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP) +#define CFG_IBAT1L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT1U CFG_DBAT1U /* * BAT2 512M Cache-inhibited, guarded * 0xc000_0000 512M RapidIO Memory */ -#define CFG_DBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW \ +#define CFG_DBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT2U (CFG_RIO_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) -#define CFG_IBAT2L (CFG_RIO_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_DBAT2U (CFG_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) +#define CFG_IBAT2L (CFG_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT2U CFG_DBAT2U /* @@ -428,10 +436,10 @@ * 0xe300_0000 16M PCI-Express 2 I/0 * Note that this is at 0xe0000000 */ -#define CFG_DBAT4L ( CFG_PCI1_IO_BASE | BATL_PP_RW \ +#define CFG_DBAT4L ( CFG_PCI1_IO_PHYS | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CFG_DBAT4U (CFG_PCI1_IO_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CFG_IBAT4L (CFG_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) +#define CFG_DBAT4U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) +#define CFG_IBAT4L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT4U CFG_DBAT4U /* diff --git a/include/pci.h b/include/pci.h index 7c9a0e34410..8e5dacc0df6 100644 --- a/include/pci.h +++ b/include/pci.h @@ -302,6 +302,12 @@ #define PCI_MAX_PCI_DEVICES 32 #define PCI_MAX_PCI_FUNCTIONS 8 +#define PCI_DCR 0x54 /* PCIe Device Control Register */ +#define PCI_DSR 0x56 /* PCIe Device Status Register */ +#define PCI_LSR 0x5e /* PCIe Link Status Register */ +#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */ +#define PCI_LTSSM_L0 0x16 /* L0 state */ + /* Include the ID list */ #include -- cgit v1.3.1 From 8092fef4c29b395958bb649647da7e3775731517 Mon Sep 17 00:00:00 2001 From: Martin Krause Date: Tue, 12 Dec 2006 14:26:01 +0100 Subject: Add functions to list of exported functions Additionally export the following fuctions (to make trab_config build again): - simple_strtol() - strcmp() Also bump the ABI version to reflect this change Signed-off-by: Martin Krause --- board/trab/Makefile | 1 - common/exports.c | 2 ++ include/_exports.h | 2 ++ include/exports.h | 4 +++- 4 files changed, 7 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/trab/Makefile b/board/trab/Makefile index 868ca4281f1..fbe1c3640fc 100644 --- a/board/trab/Makefile +++ b/board/trab/Makefile @@ -50,7 +50,6 @@ $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(obj)trab_fkt.srec: $(OBJS_FKT) $(LIB) $(LD) -g -Ttext $(LOAD_ADDR) -o $(<:.o=) -e trab_fkt $^ $(LIB) \ -L$(obj)../../examples -lstubs \ - -L$(obj)../../lib_generic -lgeneric \ -L$(gcclibdir) -lgcc $(OBJCOPY) -O srec $(<:.o=) $@ diff --git a/common/exports.c b/common/exports.c index a579554ab52..ec4656bfbd1 100644 --- a/common/exports.c +++ b/common/exports.c @@ -28,6 +28,8 @@ void jumptable_init (void) gd->jt[XF_get_timer] = (void *) get_timer; gd->jt[XF_simple_strtoul] = (void *) simple_strtoul; gd->jt[XF_udelay] = (void *) udelay; + gd->jt[XF_simple_strtol] = (void *) simple_strtol; + gd->jt[XF_strcmp] = (void *) strcmp; #if defined(CONFIG_I386) || defined(CONFIG_PPC) gd->jt[XF_install_hdlr] = (void *) irq_install_handler; gd->jt[XF_free_hdlr] = (void *) irq_free_handler; diff --git a/include/_exports.h b/include/_exports.h index a0fbf2aba36..da6e088163e 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -15,6 +15,8 @@ EXPORT_FUNC(do_reset) EXPORT_FUNC(getenv) EXPORT_FUNC(setenv) EXPORT_FUNC(simple_strtoul) +EXPORT_FUNC(simple_strtol) +EXPORT_FUNC(strcmp) #if defined(CONFIG_CMD_I2C) EXPORT_FUNC(i2c_write) EXPORT_FUNC(i2c_read) diff --git a/include/exports.h b/include/exports.h index 704b1330b89..0516da93749 100644 --- a/include/exports.h +++ b/include/exports.h @@ -23,6 +23,8 @@ void do_reset (void); unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base); char *getenv (char *name); void setenv (char *varname, char *varvalue); +long simple_strtol(const char *cp,char **endp,unsigned int base); +int strcmp(const char * cs,const char * ct); #if defined(CONFIG_CMD_I2C) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); @@ -40,7 +42,7 @@ enum { XF_MAX }; -#define XF_VERSION 3 +#define XF_VERSION 4 #if defined(CONFIG_I386) extern gd_t *global_data; -- cgit v1.3.1 From 5728be389e65fd47f34b33c2596271eb4db751ae Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 6 Aug 2007 01:01:49 +0200 Subject: Coding style cleanup. Update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 931 ++++++++++++++++++++++++++++++++++++++++++--- cpu/ppc4xx/44x_spd_ddr.c | 2 +- drivers/tsec.c | 62 +-- include/configs/ADNPESC1.h | 6 +- include/configs/APC405.h | 2 +- include/configs/Adder.h | 8 +- include/configs/BAB7xx.h | 6 +- include/configs/BC3450.h | 2 +- include/configs/CANBT.h | 2 +- include/configs/CPCI750.h | 24 +- include/configs/CU824.h | 2 +- 11 files changed, 931 insertions(+), 116 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 207f1bc653e..58ef66ecdc4 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,830 @@ +commit 8092fef4c29b395958bb649647da7e3775731517 +Author: Martin Krause +Date: Tue Dec 12 14:26:01 2006 +0100 + + Add functions to list of exported functions + + Additionally export the following fuctions (to make trab_config build again): + - simple_strtol() + - strcmp() + + Also bump the ABI version to reflect this change + + Signed-off-by: Martin Krause + +commit 63cec5814fab5d2b1c86982327433807a5ac0249 +Author: Ed Swarthout +Date: Thu Aug 2 14:09:49 2007 -0500 + + Make MPC8641's PCI/PCI-E driver a common driver for many FSL parts. + + All of the PCI/PCI-Express driver and initialization code that + was in the MPC8641HPCN port has now been moved into the common + drivers/fsl_pci_init.c. In a subsequent patch, this will be + utilized by the 85xx ports as well. + + Common PCI-E IMMAP register blocks for FSL 85xx/86xx are added. + + Also enable the second PCI-Express controller on 8641 + by getting its BATS and CFG_ setup right. + + Fixed a u16 vendor compiler warning in AHCI driver too. + + Signed-off-by: Ed Swarthout + Signed-off-by: Zhang Wei + Signed-off-by: Jon Loeliger + +commit c7e717ebc2b044d7a71062552c9dc0f54ea9b779 +Author: Andy Fleming +Date: Fri Aug 3 04:05:25 2007 -0500 + + Add Marvell 1149 PHY support to the TSEC + +commit 63e22764d2f8653f68888c667eb65b3996b52680 +Author: Wolfgang Denk +Date: Thu Aug 2 10:11:18 2007 +0200 + + Minor cleanup of _nand build rules. + +commit cdd917a43da6fa7fc8f54a3cc9f420ce5ecf3197 +Author: Wolfgang Denk +Date: Thu Aug 2 00:48:45 2007 +0200 + + Fix build errors and warnings / code cleanup. + + Signed-off-by: Wolfgang Denk + +commit 5a56af3b522ba47fb33a3fee84d23bf1e5429654 +Author: Andy Fleming +Date: Fri Jun 8 16:41:18 2007 -0500 + + Remove erroneous errata code from Marvel 88E1111S driver + + The Marvel 88E1111S driver for the TSEC was copied from the + 88E1101 driver, and included a fix for an erratum which does not + exist on that part. Now it is removed + + Signed-off-by: Andy Fleming + +commit 982efcf23fd03647e01e2fbe28a7a36239156cc0 +Author: Andy Fleming +Date: Tue Jun 5 16:38:44 2007 -0500 + + From: eran liberty + + adds the reset register to 85xx immap + + Signed-off-by: Eran Liberty + Signed-off-by: Andy Fleming + +commit d3ec0d943a045bdb99e159e7bbc77430e09f11d7 +Author: Andy Fleming +Date: Thu May 10 17:50:01 2007 -0500 + + Polished the 85xx ADS config files + + Made the boot commands use device trees by default. + Also moved the ramdisk to 1000000 (I think the previous address + was getting overridden during boot). + + Signed-off-by: Andy Fleming + +commit bfb37b32d1b0b03f18077dba49cc66a6e76fa038 +Author: Ed Swarthout +Date: Wed May 9 11:03:32 2007 -0500 + + 8544ds: Fix Makefile after moving pixis to board/freescale. + + The OBJTREE != SRCTREE build scenario was broken. + This fixes it. + + Signed-off-by: Ed Swarthout + Signed-off-by: Jon Loeliger + +commit 2a3cee43c3b71fa5b8d91db19f05067865290f3e +Author: Andy Fleming +Date: Wed May 9 00:54:20 2007 -0500 + + tsec: Fix PHY code to match first driver + + Jarrold Wen noticed that the generic PHY code always matches + under the current implementation. Change it so the first match + wins, and *only* unknown PHYs trigger the generic driver + + Signed-off-by: Andy Fleming + +commit ccc091aac61a38cd998d575d92f7232e256d6312 +Author: Andy Fleming +Date: Tue May 8 17:27:43 2007 -0500 + + Add support for CPM device tree configuration to 8560 ADS + + * Adds code to modify CPM frequencies + * Cleans up the config file to #define TSEC and (for now) #undef FCC + * Adds the MII command for all 8560 ADS configurations + * Updates config file to provide convenience commands for booting + with a device tree + + Signed-off-by: Vitaly Bordug + Signed-off-by: Andy Fleming + +commit 7507d56ccaf7aae1c474342a9a5540165cd7e9d9 +Author: Andy Fleming +Date: Tue May 8 17:23:02 2007 -0500 + + Fix Marvell 88e1145 PHY init code + + Fix a bug in the Marvell 88e1145 PHY init code in the TSEC driver + where the reset was being done after the errata code instead of + before. + + Signed-off-by: Haiying Wang + Signed-off-by: Andy Fleming + +commit 5dc210dec5bace98a50b6ba905347890091a9bb0 +Author: Ed Swarthout +Date: Wed Jul 11 14:52:16 2007 -0500 + + Add simple agent/end-point configuration in PCI AutoConfig for PCI_CLASS_PROCESSOR_POWERPC. + + Signed-off-by: Ed Swarthout + +commit e8b85f3ba4cd8930e0a2fea2100c815d64201765 +Author: Ed Swarthout +Date: Wed Jul 11 14:52:08 2007 -0500 + + pciauto setup bridge + + The P2P bridge bus numbers programmed into the device are relative to + hose->first_busno. + + Signed-off-by: Ed Swarthout + +commit 571f49fa717004ca4268b4e24057efc7bf9f987b +Author: Ed Swarthout +Date: Wed Jul 11 14:52:01 2007 -0500 + + Support PCIe extended config registers + + FSL PCIe block has extended cfg registers in the 100 and 400 range. + For example, to read the LTSSM register: pci display .0 404 1 + + Signed-off-by: Ed Swarthout + +commit ba5feb12581bb2912ce301e4866b71f846e9fc07 +Author: Ed Swarthout +Date: Wed Jul 11 14:51:48 2007 -0500 + + Minor improvements to drivers/pci_auto.c + + - Make pciauto_{pre,post}scan_setup_bridge non-static + - Added physical address display in debug messages. + + Signed-off-by: Ed Swarthout + +commit 40e81addab7bb74d20ddf681ce9babc880a828ee +Author: Ed Swarthout +Date: Wed Jul 11 14:51:35 2007 -0500 + + Start pci hose scan from hose->current_busno. + + Ensure hose->current_busno is not less than first_busno. This fixes + broken board code which leaves current_busno=0 when first_busno is + greater than 0 for the cases with multiple controllers. + + Signed-off-by: Ed Swarthout + +commit 3865b1fb7843a08ad49a6319a36415752276ff48 +Author: Stefan Roese +Date: Wed Jul 11 12:13:53 2007 +0200 + + Fix some compile problems introduced by the latest CFG_CMD_xxx cleanup + + Signed-off-by: Stefan Roese + +commit e9514751cfa5cce61ea699fa0d3eb37898a5eeb5 +Author: Stefan Roese +Date: Sun Jul 8 13:44:27 2007 +0200 + + Fix malloc problem introduced with the relocation fixup for the PPC platform + + The relocation fixup didn't handle the malloc pointer initialization + correctly. This patch fixes this problem. Tested successfully on 4xx. + The relocation fixup patches for 4xx will follow soon. + + Signed-off-by: Stefan Roese + +commit b3aff0cb9ecf236d7e8c93761dd1dadf6837a582 +Author: Jon Loeliger +Date: Tue Jul 10 11:19:50 2007 -0500 + + disk/ doc/ lib_*/ and tools/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit ddb5d86f0215bcb6c293510c50eb050e92883b7a +Author: Jon Loeliger +Date: Tue Jul 10 11:13:21 2007 -0500 + + drivers/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit f40a7f3e3888b42a43674b099e5470022c8c544c +Author: Jon Loeliger +Date: Tue Jul 10 11:07:56 2007 -0500 + + fs/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit 610f2e9c28a9c101e09fa1b78143cf5f00ed1593 +Author: Jon Loeliger +Date: Tue Jul 10 11:05:02 2007 -0500 + + net/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit 902531788376046da212afd1661cffb62f3daa1c +Author: Jon Loeliger +Date: Tue Jul 10 11:02:44 2007 -0500 + + common/: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit d39b57415838c73fb0a37eca84de3c68ba990586 +Author: Jon Loeliger +Date: Tue Jul 10 10:48:22 2007 -0500 + + board/[j-z]*: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit 77a318545d57aefa844752465b94c7e09a3f26d0 +Author: Jon Loeliger +Date: Tue Jul 10 10:39:10 2007 -0500 + + board/[A-Za-i]*: Remove lingering references to CFG_CMD_* symbols. + + Fixed some broken instances of "#ifdef CMD_CFG_IDE" too. + Those always evaluated TRUE, and thus were always compiled + even when IDE really wasn't defined/wanted. + + Signed-off-by: Jon Loeliger + +commit 068b60a0eb7e73b243ca55399f2a7df76e2c3f3d +Author: Jon Loeliger +Date: Tue Jul 10 10:27:39 2007 -0500 + + cpu/ rtc/ include/: Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 079a136c3588814784561d6e4856970ee82d6e2a +Author: Jon Loeliger +Date: Tue Jul 10 10:12:10 2007 -0500 + + include/configs/[p-z]* + misc: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 7f5c01577400c74cc5bac74f41dd0d3c79df623c +Author: Jon Loeliger +Date: Tue Jul 10 09:38:02 2007 -0500 + + include/configs/[g-o]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 80ff4f99b84b64edca3fd10da365ec1493be1c95 +Author: Jon Loeliger +Date: Tue Jul 10 09:29:01 2007 -0500 + + include/configs/[a-e]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit a1aa0bb502e25fd598b5e0ccdfb2c174921d714a +Author: Jon Loeliger +Date: Tue Jul 10 09:22:23 2007 -0500 + + include/configs/[P-Z]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 659e2f6736232a08acca8785c206e2b4d9cd07d7 +Author: Jon Loeliger +Date: Tue Jul 10 09:10:49 2007 -0500 + + include/configs/[J-O]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 11799434c5ff15a612577bb1ad1f4ea1a0595e4b +Author: Jon Loeliger +Date: Tue Jul 10 09:02:57 2007 -0500 + + include/configs/[A-I]*: Cleanup BOOTP and lingering CFG_CMD_*. + + Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h + used to be included but CONFIG_BOOTP_MASK was not defined. + + Remove lingering references to CFG_CMD_* symbols. + + Signed-off-by: Jon Loeliger + +commit 1fe80d79c5c4e52d3410a7ab4b8515da095cdab3 +Author: Jon Loeliger +Date: Mon Jul 9 22:08:34 2007 -0500 + + Finally retire cmd_confdefs.h and CONFIG_BOOTP_MASK! + + All of the choices for CONFIG_BOOTP_ are now documented in + the README file. You must now individually select exactly + the set that you want using a series of + #define CONFIG_BOOTP_ + statements in the board port config files now. + + Signed-off-by: Jon Loeliger + +commit d3b8c1a743dcd31625c99e6a44590f207eb00028 +Author: Jon Loeliger +Date: Mon Jul 9 21:57:31 2007 -0500 + + include/configs/[m-z]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 2fd90ce575b02d189cbf443c85309bcd001aa393 +Author: Jon Loeliger +Date: Mon Jul 9 21:48:26 2007 -0500 + + include/configs/[a-m]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 37d4bb70586659dedef1658ce1bed071be098aec +Author: Jon Loeliger +Date: Mon Jul 9 21:38:02 2007 -0500 + + include/configs/[T-Z]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 18225e8dd1950bd6dbf35011e436db7f474c187d +Author: Jon Loeliger +Date: Mon Jul 9 21:31:24 2007 -0500 + + include/configs/[P-S]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 7be044e4ea644b0ef1c486dadc1a4c2665b4374d +Author: Jon Loeliger +Date: Mon Jul 9 21:24:19 2007 -0500 + + include/configs/[H-N]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit 5d2ebe1b3ef0055c661bb1a0d252bf252380069f +Author: Jon Loeliger +Date: Mon Jul 9 21:16:53 2007 -0500 + + include/configs/[A-G]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_MASK. + + Signed-off-by: Jon Loeliger + +commit f55f7f8d83f36021ab1f0e3d738f5d8c8083a7e3 +Author: Jon Loeliger +Date: Mon Jul 9 19:12:30 2007 -0500 + + Retire CONFIG_COMMANDS finally. + Strip old CFG_CMD_* symbols out. + + Signed-off-by: Jon Loeliger + +commit b5501f7d720fed99ab0b42c83f5dea52868ce007 +Author: Jon Loeliger +Date: Mon Jul 9 19:10:03 2007 -0500 + + Update README.* to reference new CONFIG_CMD_* names now. + + Signed-off-by: Jon Loeliger + +commit 4431283c7e6d54ae180d466e51bf2d97471a0ad9 +Author: Jon Loeliger +Date: Mon Jul 9 19:06:00 2007 -0500 + + cpu/m*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 3a1ed1e1f922c419bb71f7df4949d783ade369fa +Author: Jon Loeliger +Date: Mon Jul 9 18:57:22 2007 -0500 + + cpu/[7a-ln-z]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit ab3abcbabd840928fb1eb5122118ca466b5e5013 +Author: Jon Loeliger +Date: Mon Jul 9 18:45:16 2007 -0500 + + board/[q-z]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 3fe00109a5f12de55b6e25b1f98dfc24bc9090c9 +Author: Jon Loeliger +Date: Mon Jul 9 18:38:39 2007 -0500 + + board/[m-p]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit c508a4cefd8a953fc64957650506a035e6e3d9d1 +Author: Jon Loeliger +Date: Mon Jul 9 18:31:28 2007 -0500 + + board/[f-l]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit b9307262f8a9f3b5c9e15a6067eadc17407146f6 +Author: Jon Loeliger +Date: Mon Jul 9 18:24:55 2007 -0500 + + board/[d-e]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit fcec2eb93e126400009729328e797f12bc94f1fd +Author: Jon Loeliger +Date: Mon Jul 9 18:19:09 2007 -0500 + + board/[A-Za-c]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit a593814f2be0c9cdc3133cd550b167b8a988328f +Author: Jon Loeliger +Date: Mon Jul 9 18:10:50 2007 -0500 + + rtc/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 67350568f9d46e66c21829f3513b3db0caeb948b +Author: Jon Loeliger +Date: Mon Jul 9 18:05:38 2007 -0500 + + lib_{arm,avr32,blackfin,generic,i386}/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 7def6b34f910f08d7ef0a14646da067719237ca2 +Author: Jon Loeliger +Date: Mon Jul 9 18:02:11 2007 -0500 + + lib_{m68k,microblaze,mips,ppc}/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit dd60d1223b99a88a7216f3e041fe40634ad4c2bb +Author: Jon Loeliger +Date: Mon Jul 9 17:56:50 2007 -0500 + + fs/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit c91898bbc505aff3e12a807af88e76da18efb7ee +Author: Jon Loeliger +Date: Mon Jul 9 17:46:09 2007 -0500 + + tools/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 643d1ab23960950b52e0a2803c2d3ea4c558fa01 +Author: Jon Loeliger +Date: Mon Jul 9 17:45:14 2007 -0500 + + net/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit cb51c0bf88f95a1bca68324b0126f8eed8b43273 +Author: Jon Loeliger +Date: Mon Jul 9 17:39:42 2007 -0500 + + drivers/[n-z]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 07d38a17e964aec4c7827f0ee9a583bc8cc1ad6b +Author: Jon Loeliger +Date: Mon Jul 9 17:30:01 2007 -0500 + + drivers/[a-m]*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit cde5c64d17cf4834aa7b5c373f288bc7dad27b29 +Author: Jon Loeliger +Date: Mon Jul 9 17:22:37 2007 -0500 + + disk/: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit 639221c76c88215bd55af83ad174fc30d1940f8f +Author: Jon Loeliger +Date: Mon Jul 9 17:15:49 2007 -0500 + + include/: Remove obsolete references to CONFIG_COMMANDS + Mostly removed from comments here. + + Signed-off-by: Jon Loeliger + +commit 4ef218f6fdf8d747f4589da5252b004e7d2c2876 +Author: Wolfgang Denk +Date: Tue Jul 10 00:01:28 2007 +0200 + + Coding style cleanup; update CHANGELOG. + + Signed-off-by: Wolfgang Denk + +commit c3517f919d0f61650cf3027fd4faf0f631142f6c +Author: Jon Loeliger +Date: Sun Jul 8 18:10:08 2007 -0500 + + common/* non-cmd*: Remove obsolete references to CONFIG_COMMANDS + + Signed-off-by: Jon Loeliger + +commit fd9bcaa35be64fe41a4223fdb6ecdbad52470b39 +Author: Jon Loeliger +Date: Sun Jul 8 18:05:39 2007 -0500 + + common/cmd_[p-x]*: Remove obsolete references to CONFIG_COMMANDS. + + Signed-off-by: Jon Loeliger + +commit c76fe47425afc7d5d670ff0539823c85d65d9c42 +Author: Jon Loeliger +Date: Sun Jul 8 18:02:23 2007 -0500 + + common/cmd_[i-n]*: Remove obsolete references to CONFIG_COMMANDS. + + Signed-off-by: Jon Loeliger + +commit baa26db4113679b80970ff447d91cc10217742a6 +Author: Jon Loeliger +Date: Sun Jul 8 17:51:39 2007 -0500 + + common/cmd_[af]*: Remove obsolete references to CONFIG_COMMANDS. + + Signed-off-by: Jon Loeliger + +commit af075ee96e52dda7b6bca6c937588aeaaec5f2cd +Author: Jon Loeliger +Date: Sun Jul 8 17:02:01 2007 -0500 + + Clear up confusion over the CMD_POST and POST_DIAG mess. + + For some reason, CONFIG_POST permeated as CONFIG_CMD_POST_DIAG + when it really means just CONFIG_CMD_DIAG. There is no CMD_POST. + Clear this mess up some. + + Signed-off-by: Jon Loeliger + +commit b3631487105a57ab7cbadfc26efbaf9676275018 +Author: Jon Loeliger +Date: Sun Jul 8 15:45:08 2007 -0500 + + Remove references to the old cmd_confdefs.h include file. + + Signed-off-by: Jon Loeliger + +commit a22d4da95e20049b4daa1c2a022f61e8a72f2fb6 +Author: Jon Loeliger +Date: Sun Jul 8 15:42:59 2007 -0500 + + include/configs: Catch some CONFIG_CMD_* conversion stragglers. + + Use new CONFIG_CMD_* in lwmon5.h board config file. + Fix CONFIG_CMD_* typo braindamage in omap1510inn.h + + Signed-off-by: Jon Loeliger + +commit a5562901661bd428f7e5feb333f796372cb81019 +Author: Jon Loeliger +Date: Sun Jul 8 15:31:57 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various [TUVWZYZ]* named board config files. + + Signed-off-by: Jon Loeliger + +commit fe7f782d5b8c64a0195c68c31a0a11d4f641355e +Author: Jon Loeliger +Date: Sun Jul 8 15:02:44 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various S* named board config files. + + Signed-off-by: Jon Loeliger + +commit e9a0f8f15c11f337967aa0600ad6e8af33037f50 +Author: Jon Loeliger +Date: Sun Jul 8 15:12:40 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various R* named board config files. + + Signed-off-by: Jon Loeliger + +commit 12aa9fd23d724bd6ab88e1baa0db35133a27303f +Author: Jon Loeliger +Date: Sun Jul 8 14:55:07 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various Q* named board config files. + + Signed-off-by: Jon Loeliger + +commit acf0269779422f3e147d2ddfb499c9f6ff10ad5e +Author: Jon Loeliger +Date: Sun Jul 8 14:49:44 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various P* named board config files. + + Signed-off-by: Jon Loeliger + +commit e18a1061a8630cb67995fdf99afd3fb50d1b187d +Author: Jon Loeliger +Date: Sun Jul 8 14:21:43 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various [NO]* named board config files. + + Signed-off-by: Jon Loeliger + +commit 8353e139bfad9059c54f5b2421f1a3090e15a2e2 +Author: Jon Loeliger +Date: Sun Jul 8 14:14:17 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various M* named board config files. + + Signed-off-by: Jon Loeliger + +commit 348f258f24253433e4a2302a0bbceb6740a67246 +Author: Jon Loeliger +Date: Sun Jul 8 13:46:18 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various [IJKL]* named board config files. + + Signed-off-by: Jon Loeliger + +commit 6c4f4da9bfc9f9403f54fce678ed0364b7c86a6a +Author: Jon Loeliger +Date: Sun Jul 8 10:09:35 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various H* named board config files. + + Signed-off-by: Jon Loeliger + +commit 60a0876b5106b34220e459c208bbf648073306c0 +Author: Jon Loeliger +Date: Sat Jul 7 21:04:26 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various F* and G* named board config files. + + Signed-off-by: Jon Loeliger + +commit dcaa71562826a2466e894c868d132509dcda8444 +Author: Jon Loeliger +Date: Sat Jul 7 20:56:05 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various E* named board config files. + + Signed-off-by: Jon Loeliger + +commit 3c3227f3c737502311b25b72084573901cbbf17d +Author: Jon Loeliger +Date: Sat Jul 7 20:40:43 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various D* named board config files. + + Signed-off-by: Jon Loeliger + +commit 49cf7e8ee7ef943fdfe866ce28410b0bfbf6a26c +Author: Jon Loeliger +Date: Thu Jul 5 19:52:35 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various C* named board config files. + + Signed-off-by: Jon Loeliger + +commit de8b2a6e33298dcdb10bdda48db25e53c3089eba +Author: Jon Loeliger +Date: Thu Jul 5 19:32:07 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various B* named board config files. + + Signed-off-by: Jon Loeliger + +commit 498ff9a228485bd4b9f23d066bada268f9add1dd +Author: Jon Loeliger +Date: Thu Jul 5 19:13:52 2007 -0500 + + include/configs: Use new CONFIG_CMD_* in various A* named board config files. + + Since ADS860.h includes "board/fads/fads.h" with ramifications + on the CONFIG_COMMAND treatment, it too has to be adjusted to + exclude already configured commands in this same commit. + + Signed-off-by: Jon Loeliger + +commit 6b0a174a1e6f55e1f5a1fbb223cdad7645a4646e +Author: Stefan Roese +Date: Fri Jul 6 09:45:47 2007 +0200 + + Fix problem with get/setdcr commands introduced by cfg patches + + Signed-off-by: Stefan Roese + +commit f1152f8c28db4a22087c21c618a3f7baa48e9a4f +Author: Wolfgang Denk +Date: Fri Jul 6 02:50:19 2007 +0200 + + Code cleanup and default config update for STC GP3 SSA board. + + Signed-off-by: Wolfgang Denk + +commit e4dbe1b215f5c6c462e76909d240bd96472b84de +Author: Wolfgang Denk +Date: Thu Jul 5 17:56:27 2007 +0200 + + Fixing some typos etc. introduced mainly by cfg patches. + + Signed-off-by: Wolfgang Denk + +commit b6b4684546809f89c8bac72863ca49b5fd8ac0cd +Author: Wolfgang Denk +Date: Thu Jul 5 11:12:16 2007 +0200 + + Minor coding style cleanup. Update CHANGELOG. + commit dca3b3d6d6396b67e5e84af53452164923c73443 Author: Jon Loeliger Date: Wed Jul 4 22:33:46 2007 -0500 @@ -198,6 +1025,14 @@ Date: Wed Jul 4 22:30:06 2007 -0500 Signed-off-by: Jon Loeliger +commit b44896215a09c60fa40cae906f7ed207bbc2c492 +Author: Sergei Poselenov +Date: Thu Jul 5 08:17:37 2007 +0200 + + Merged POST framework with the current TOT. + + Signed-off-by: Sergei Poselenov + commit b24629fa377214d63bb40d1360e354b6d3e4af56 Author: Jon Loeliger Date: Wed Jun 13 13:23:15 2007 -0500 @@ -232,6 +1067,28 @@ Date: Wed Jun 13 13:21:37 2007 -0500 Signed-off-by: Jon Loeliger +commit f780b83316d9af1f61d71cc88b1917b387b9b995 +Author: Niklaus Giger +Date: Wed Jun 27 18:11:38 2007 +0200 + + resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPX + + Signed-off-by: Niklaus Giger + +commit 04e6c38b766eaa2f3287561563c9e215e0c3a0d4 +Author: Stefan Roese +Date: Wed Jul 4 10:06:30 2007 +0200 + + ppc4xx: Update lwmon5 board + + - Add optional ECC generation routine to preserve existing + RAM values. This is needed for the Linux log-buffer support + - Add optional DDR2 setup with CL=4 + - GPIO50 not used anymore + - Lime register setup added + + Signed-off-by: Stefan Roese + commit 6810a34677dbc446334f5e451f1682426dd33b49 Author: Grant Likely Date: Tue Jul 3 00:17:28 2007 -0600 @@ -440,14 +1297,6 @@ Date: Tue Jul 3 00:32:53 2007 -0600 Signed-off-by: Grant Likely -commit f1152f8c28db4a22087c21c618a3f7baa48e9a4f -Author: Wolfgang Denk -Date: Fri Jul 6 02:50:19 2007 +0200 - - Code cleanup and default config update for STC GP3 SSA board. - - Signed-off-by: Wolfgang Denk - commit 52b8704d0245e589f86d462e9ec25aeb7ecbbbdd Author: Wolfgang Denk Date: Wed Jul 4 00:43:53 2007 +0200 @@ -456,14 +1305,6 @@ Date: Wed Jul 4 00:43:53 2007 +0200 Signed-off-by: Wolfgang Denk -commit b44896215a09c60fa40cae906f7ed207bbc2c492 -Author: Sergei Poselenov -Date: Thu Jul 5 08:17:37 2007 +0200 - - Merged POST framework with the current TOT. - - Signed-off-by: Sergei Poselenov - commit 78e0cf2de7be7f1eaeeb622eb61fd50e4d5e205c Author: Wolfgang Denk Date: Wed Jul 4 00:38:38 2007 +0200 @@ -478,14 +1319,6 @@ Date: Mon Jun 11 19:03:44 2007 -0500 Signed-off-by: Jon Loeliger -commit f780b83316d9af1f61d71cc88b1917b387b9b995 -Author: Niklaus Giger -Date: Wed Jun 27 18:11:38 2007 +0200 - - resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPX - - Signed-off-by: Niklaus Giger - commit 602ad3b33d9ceef83dbab46be68646d645d637ee Author: Jon Loeliger Date: Mon Jun 11 19:03:39 2007 -0500 @@ -494,20 +1327,6 @@ Date: Mon Jun 11 19:03:39 2007 -0500 Signed-off-by: Jon Loeliger -commit 04e6c38b766eaa2f3287561563c9e215e0c3a0d4 -Author: Stefan Roese -Date: Wed Jul 4 10:06:30 2007 +0200 - - ppc4xx: Update lwmon5 board - - - Add optional ECC generation routine to preserve existing - RAM values. This is needed for the Linux log-buffer support - - Add optional DDR2 setup with CL=4 - - GPIO50 not used anymore - - Lime register setup added - - Signed-off-by: Stefan Roese - commit 72a074cec68e5bad60d63206c050974e08afd804 Author: Jon Loeliger Date: Mon Jun 11 19:03:34 2007 -0500 @@ -1875,7 +2694,7 @@ Date: Sat May 5 08:12:30 2007 +0200 5xxx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2017,7 +2836,7 @@ Date: Sat May 5 08:12:30 2007 +0200 5xxx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2148,7 +2967,7 @@ Date: Mon Apr 30 13:59:50 2007 -0500 Fix memory initialization on MPC8349E-mITX Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. - This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary + This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into @@ -2305,7 +3124,7 @@ Date: Mon Feb 12 13:34:55 2007 -0600 85xx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2614,7 +3433,7 @@ Date: Fri Apr 20 14:12:26 2007 -0500 mpc86xx; Write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, ftp_cpu_setup() + and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. @@ -2667,7 +3486,7 @@ Date: Thu Apr 19 23:14:39 2007 -0400 What was suppose to be a stack variable was declared as a pointer, overwriting random memory. - Also moved the libfdt.a requirement into the main Makefile. That is + Also moved the libfdt.a requirement into the main Makefile. That is The U-Boot Way. commit d21686263574e95cb3e9e9b0496f968b1b897fdb @@ -3262,7 +4081,7 @@ Date: Sat Mar 31 12:22:10 2007 -0400 Add a flattened device tree (fdt) command (1 of 2) The fdt command uses David Gibson's libfdt library to manipulate as well - as print the flattened device tree. This patch is the new command, + as print the flattened device tree. This patch is the new command, the second part is the modifications to the existing code. commit 3af0d587d93e0be5f96e1b30fa41e662f8b0803e @@ -3963,7 +4782,7 @@ Date: Tue Feb 13 10:41:42 2007 -0600 mpc83xx: write MAC address to mac-address and local-mac-address Some device trees have a mac-address property, some have local-mac-address, - and some have both. To support all of these device trees, this patch + and some have both. To support all of these device trees, this patch updates ftp_cpu_setup() to write the MAC address to mac-address if it exists. This function already updates local-mac-address. @@ -4186,7 +5005,7 @@ Date: Wed Dec 6 21:23:55 2006 -0500 mpc83xx: Put the version (and magic) after the HRCW. - Put the version (and magic) after the HRCW. This puts it in a fixed + Put the version (and magic) after the HRCW. This puts it in a fixed location in flash, not at the start of flash but as close as we can get. Signed-off-by: Jerry Van Baren @@ -4480,7 +5299,7 @@ Date: Tue Feb 20 09:05:31 2007 +0100 [PATCH 7_9] Replace ace_readw_ace_writeb functions with macros - Register read/write does not need to be wrapped in a full function. The + Register read/write does not need to be wrapped in a full function. The patch replaces them with macros. Signed-off-by: Grant Likely @@ -4783,7 +5602,7 @@ commit fdef388758506765d4d6a7155c8f1584c63ff581 Author: roy zang Date: Mon Jan 22 13:19:21 2007 +0800 - use CFG_WRITE_SWAPPED_DATA define instead of define CFG_FLASH_CFI_SWAP + use CFG_WRITE_SWAPPED_DATA define instead of define CFG_FLASH_CFI_SWAP The patch by Heiko Schocher on Jan, 19, 2007 fixes cfi_driver bug for mpc7448hpc2 board. The default cfi_driver can support mpc7448hpc2 board. @@ -5471,7 +6290,7 @@ Date: Mon Nov 27 17:04:06 2006 +0100 [PATCH] Allow CONFIG_OF_FLAT_TREE to boot a non-arch/powerpc kernel This patch allows an arch/ppc kernel to be booted by just passing 1 or 2 - arguments to bootm. It removes the getenv("disable_of") test that used + arguments to bootm. It removes the getenv("disable_of") test that used to be used for this purpose. Signed-off-by: Grant Likely @@ -6047,7 +6866,7 @@ Date: Thu Nov 2 19:08:55 2006 +0800 Gigabit Ethernet ports,E0 and E1. It uses a single Management interface to manage the two physical connection devices (PHYs). Each Ethernet port has its own statistics monitor that tracks and reports key interface - statistics. Each port supports a 256-entry hash table for address + statistics. Each port supports a 256-entry hash table for address filtering. In addition, each port is bridged to the Switch Fabric through a 2-Kbyte transmit FIFO and a 4-Kbyte Receive FIFO. @@ -6093,7 +6912,7 @@ commit 87c4db09699c6b89176b31004afcb83eb1585d47 Author: roy zang Date: Thu Nov 2 18:59:15 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. mpc7448hpc2 board support high level code:tsi108 init + mpc7448hpc2. Signed-off-by: Alexandre Bounine @@ -6103,7 +6922,7 @@ commit 27801b8ab11c61b577e45742a515bb3b23b80241 Author: roy zang Date: Thu Nov 2 18:57:21 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. Make ,config.mk and link file for the mpc7448hpc2 board. Signed-off-by: Alexandre Bounine @@ -6113,7 +6932,7 @@ commit c6411c0c3bbc79f9ba8aef58296a42d8f9d8a0a6 Author: roy zang Date: Thu Nov 2 18:55:04 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. The mpc7448hpc2 board support header file. Signed-off-by: Alexandre Bounine @@ -6123,7 +6942,7 @@ commit 625bb5ddb50b243f931262ca8c46956409471917 Author: roy zang Date: Thu Nov 2 18:52:21 2006 +0800 - Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. + Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support. The mpc7448hpc2 board support low level assemble language init code. Signed-off-by: Alexandre Bounine @@ -6348,7 +7167,7 @@ Date: Tue Oct 24 23:47:37 2006 -0500 If a Multi-Image file contains a third image we try to use it as a device tree. The device tree image is assumed to be uncompressed in the - image file. We automatically allocate space for the device tree in memory + image file. We automatically allocate space for the device tree in memory and provide an 8k pad to allow more than a reasonable amount of growth. Additionally, a device tree that was contained in flash will now automatically diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index 8c18d0f4e21..4a31d323039 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -1017,7 +1017,7 @@ static int short_mem_test(void) */ for (i = 0; i < NUMMEMTESTS; i++) { for (j = 0; j < NUMMEMWORDS; j++) { -//printf("bank enabled base:%x\n", &membase[j]); + /*printf("bank enabled base:%x\n", &membase[j]);*/ membase[j] = test[i][j]; ppcDcbf((unsigned long)&(membase[j])); } diff --git a/drivers/tsec.c b/drivers/tsec.c index 1399d076891..60bef9af394 100644 --- a/drivers/tsec.c +++ b/drivers/tsec.c @@ -899,36 +899,36 @@ static void tsec_halt(struct eth_device *dev) } struct phy_info phy_info_M88E1149S = { - 0x1410ca, - "Marvell 88E1149S", - 4, - (struct phy_cmd[]){ /* config */ - /* Reset and configure the PHY */ - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {0x1d, 0x1f, NULL}, - {0x1e, 0x200c, NULL}, - {0x1d, 0x5, NULL}, - {0x1e, 0x0, NULL}, - {0x1e, 0x100, NULL}, - {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, - {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, - {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, - {miim_end,} - }, - (struct phy_cmd[]){ /* startup */ - /* Status is read once to clear old link state */ - {MIIM_STATUS, miim_read, NULL}, - /* Auto-negotiate */ - {MIIM_STATUS, miim_read, &mii_parse_sr}, - /* Read the status */ - {MIIM_88E1011_PHY_STATUS, miim_read, - &mii_parse_88E1011_psr}, - {miim_end,} - }, - (struct phy_cmd[]){ /* shutdown */ - {miim_end,} - }, + 0x1410ca, + "Marvell 88E1149S", + 4, + (struct phy_cmd[]){ /* config */ + /* Reset and configure the PHY */ + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {0x1d, 0x1f, NULL}, + {0x1e, 0x200c, NULL}, + {0x1d, 0x5, NULL}, + {0x1e, 0x0, NULL}, + {0x1e, 0x100, NULL}, + {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL}, + {MIIM_ANAR, MIIM_ANAR_INIT, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL}, + {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init}, + {miim_end,} + }, + (struct phy_cmd[]){ /* startup */ + /* Status is read once to clear old link state */ + {MIIM_STATUS, miim_read, NULL}, + /* Auto-negotiate */ + {MIIM_STATUS, miim_read, &mii_parse_sr}, + /* Read the status */ + {MIIM_88E1011_PHY_STATUS, miim_read, + &mii_parse_88E1011_psr}, + {miim_end,} + }, + (struct phy_cmd[]){ /* shutdown */ + {miim_end,} + }, }; /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */ @@ -1351,7 +1351,7 @@ struct phy_info *phy_info[] = { &phy_info_M88E1011S, &phy_info_M88E1111S, &phy_info_M88E1145, - &phy_info_M88E1149S, + &phy_info_M88E1149S, &phy_info_dm9161, &phy_info_lxt971, &phy_info_VSC8244, diff --git a/include/configs/ADNPESC1.h b/include/configs/ADNPESC1.h index d4ee14c837f..77938b140da 100644 --- a/include/configs/ADNPESC1.h +++ b/include/configs/ADNPESC1.h @@ -563,8 +563,6 @@ #define CONFIG_POST CFG_POST_RTC #define CFG_NIOS_POST_WORD_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) - - /* * BOOTP options */ @@ -585,7 +583,7 @@ #undef CONFIG_CMD_DOC #undef CONFIG_CMD_DTT #undef CONFIG_CMD_EEPROM -#undef CONFIG_CMD_ELF +#undef CONFIG_CMD_ELF #undef CONFIG_CMD_FAT #undef CONFIG_CMD_FDC #undef CONFIG_CMD_FDOS @@ -610,7 +608,6 @@ #undef CONFIG_CMD_DATE #endif - /*------------------------------------------------------------------------ * KGDB *----------------------------------------------------------------------*/ @@ -657,7 +654,6 @@ #undef CFG_LOAD_ADDR /* force error break */ #endif - /* MEM test area */ #if (CFG_SDRAM_SIZE != 0) diff --git a/include/configs/APC405.h b/include/configs/APC405.h index 6dcfbc15d4c..f6495e4841a 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -92,7 +92,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_MII #define CONFIG_CMD_PING -#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EEPROM #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION diff --git a/include/configs/Adder.h b/include/configs/Adder.h index 5e076dcc41c..4304ecca7de 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -67,10 +67,10 @@ */ #include -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_IMMAP -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING #define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ diff --git a/include/configs/BAB7xx.h b/include/configs/BAB7xx.h index d8d09838eb4..c11e9c911d3 100644 --- a/include/configs/BAB7xx.h +++ b/include/configs/BAB7xx.h @@ -84,10 +84,10 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_SCSI +#define CONFIG_CMD_SCSI #define CONFIG_CMD_IDE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_FDC +#define CONFIG_CMD_DATE +#define CONFIG_CMD_FDC #define CONFIG_CMD_ELF diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 844bdc5d883..5c2bfc991f5 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -192,7 +192,7 @@ #ifdef CONFIG_BC3450_USB #define CONFIG_CMD_USB #endif - + #ifdef CONFIG_PCI #define CONFIG_CMD_PCI #endif diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index 0e082b318bb..ae32f6b14ac 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -72,7 +72,7 @@ #include #define CONFIG_CMD_IRQ -#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_EEPROM #undef CONFIG_CMD_NET diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 8d04104e58a..48e29a20876 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -148,18 +148,18 @@ */ #include -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_I2C -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ELF -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_IDE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_I2C +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_PCI +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 #define CONFIG_DOS_PARTITION diff --git a/include/configs/CU824.h b/include/configs/CU824.h index f7fdd2d6ee8..68e816a7443 100644 --- a/include/configs/CU824.h +++ b/include/configs/CU824.h @@ -73,7 +73,7 @@ */ #include -#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_BEDBUG #define CONFIG_CMD_DHCP #define CONFIG_CMD_PCI #define CONFIG_CMD_NFS -- cgit v1.3.1 From 5072188acabde3178fac7f5a597150e6e74fd40c Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Fri, 6 Jul 2007 08:33:33 +0800 Subject: This is a framebuffer driver for ATI video card, can work for PCI9200, X300, X700, X800 ATI video cards. Signed-off-by: Zhang Wei Signed-off-by: Jason Jin --- drivers/Makefile | 2 +- drivers/ati_ids.h | 212 +++++ drivers/ati_radeon_fb.c | 486 ++++++++++++ drivers/ati_radeon_fb.h | 293 +++++++ include/radeon.h | 1986 +++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 2978 insertions(+), 1 deletion(-) create mode 100644 drivers/ati_ids.h create mode 100644 drivers/ati_radeon_fb.c create mode 100644 drivers/ati_radeon_fb.h create mode 100644 include/radeon.h (limited to 'include') diff --git a/drivers/Makefile b/drivers/Makefile index fa2e86fd20f..881153ac9dd 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -52,7 +52,7 @@ COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \ ks8695eth.o \ pxa_pcmcia.o mpc8xx_pcmcia.o tqm8xx_pcmcia.o \ rpx_pcmcia.o \ - fsl_i2c.o fsl_pci_init.o + fsl_i2c.o fsl_pci_init.o ati_radeon_fb.o SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/drivers/ati_ids.h b/drivers/ati_ids.h new file mode 100644 index 00000000000..35fe505735f --- /dev/null +++ b/drivers/ati_ids.h @@ -0,0 +1,212 @@ +/* + * ATI PCI IDs from XFree86, kept here to make sync'ing with + * XFree much simpler. Currently, this list is only used by + * radeonfb + */ + +#define PCI_CHIP_RV380_3150 0x3150 +#define PCI_CHIP_RV380_3151 0x3151 +#define PCI_CHIP_RV380_3152 0x3152 +#define PCI_CHIP_RV380_3153 0x3153 +#define PCI_CHIP_RV380_3154 0x3154 +#define PCI_CHIP_RV380_3156 0x3156 +#define PCI_CHIP_RV380_3E50 0x3E50 +#define PCI_CHIP_RV380_3E51 0x3E51 +#define PCI_CHIP_RV380_3E52 0x3E52 +#define PCI_CHIP_RV380_3E53 0x3E53 +#define PCI_CHIP_RV380_3E54 0x3E54 +#define PCI_CHIP_RV380_3E56 0x3E56 +#define PCI_CHIP_RS100_4136 0x4136 +#define PCI_CHIP_RS200_4137 0x4137 +#define PCI_CHIP_R300_AD 0x4144 +#define PCI_CHIP_R300_AE 0x4145 +#define PCI_CHIP_R300_AF 0x4146 +#define PCI_CHIP_R300_AG 0x4147 +#define PCI_CHIP_R350_AH 0x4148 +#define PCI_CHIP_R350_AI 0x4149 +#define PCI_CHIP_R350_AJ 0x414A +#define PCI_CHIP_R350_AK 0x414B +#define PCI_CHIP_RV350_AP 0x4150 +#define PCI_CHIP_RV350_AQ 0x4151 +#define PCI_CHIP_RV360_AR 0x4152 +#define PCI_CHIP_RV350_AS 0x4153 +#define PCI_CHIP_RV350_AT 0x4154 +#define PCI_CHIP_RV350_AV 0x4156 +#define PCI_CHIP_MACH32 0x4158 +#define PCI_CHIP_RS250_4237 0x4237 +#define PCI_CHIP_R200_BB 0x4242 +#define PCI_CHIP_R200_BC 0x4243 +#define PCI_CHIP_RS100_4336 0x4336 +#define PCI_CHIP_RS200_4337 0x4337 +#define PCI_CHIP_MACH64CT 0x4354 +#define PCI_CHIP_MACH64CX 0x4358 +#define PCI_CHIP_RS250_4437 0x4437 +#define PCI_CHIP_MACH64ET 0x4554 +#define PCI_CHIP_MACH64GB 0x4742 +#define PCI_CHIP_MACH64GD 0x4744 +#define PCI_CHIP_MACH64GI 0x4749 +#define PCI_CHIP_MACH64GL 0x474C +#define PCI_CHIP_MACH64GM 0x474D +#define PCI_CHIP_MACH64GN 0x474E +#define PCI_CHIP_MACH64GO 0x474F +#define PCI_CHIP_MACH64GP 0x4750 +#define PCI_CHIP_MACH64GQ 0x4751 +#define PCI_CHIP_MACH64GR 0x4752 +#define PCI_CHIP_MACH64GS 0x4753 +#define PCI_CHIP_MACH64GT 0x4754 +#define PCI_CHIP_MACH64GU 0x4755 +#define PCI_CHIP_MACH64GV 0x4756 +#define PCI_CHIP_MACH64GW 0x4757 +#define PCI_CHIP_MACH64GX 0x4758 +#define PCI_CHIP_MACH64GY 0x4759 +#define PCI_CHIP_MACH64GZ 0x475A +#define PCI_CHIP_RV250_Id 0x4964 +#define PCI_CHIP_RV250_Ie 0x4965 +#define PCI_CHIP_RV250_If 0x4966 +#define PCI_CHIP_RV250_Ig 0x4967 +#define PCI_CHIP_R420_JH 0x4A48 +#define PCI_CHIP_R420_JI 0x4A49 +#define PCI_CHIP_R420_JJ 0x4A4A +#define PCI_CHIP_R420_JK 0x4A4B +#define PCI_CHIP_R420_JL 0x4A4C +#define PCI_CHIP_R420_JM 0x4A4D +#define PCI_CHIP_R420_JN 0x4A4E +#define PCI_CHIP_R420_JP 0x4A50 +#define PCI_CHIP_MACH64LB 0x4C42 +#define PCI_CHIP_MACH64LD 0x4C44 +#define PCI_CHIP_RAGE128LE 0x4C45 +#define PCI_CHIP_RAGE128LF 0x4C46 +#define PCI_CHIP_MACH64LG 0x4C47 +#define PCI_CHIP_MACH64LI 0x4C49 +#define PCI_CHIP_MACH64LM 0x4C4D +#define PCI_CHIP_MACH64LN 0x4C4E +#define PCI_CHIP_MACH64LP 0x4C50 +#define PCI_CHIP_MACH64LQ 0x4C51 +#define PCI_CHIP_MACH64LR 0x4C52 +#define PCI_CHIP_MACH64LS 0x4C53 +#define PCI_CHIP_MACH64LT 0x4C54 +#define PCI_CHIP_RADEON_LW 0x4C57 +#define PCI_CHIP_RADEON_LX 0x4C58 +#define PCI_CHIP_RADEON_LY 0x4C59 +#define PCI_CHIP_RADEON_LZ 0x4C5A +#define PCI_CHIP_RV250_Ld 0x4C64 +#define PCI_CHIP_RV250_Le 0x4C65 +#define PCI_CHIP_RV250_Lf 0x4C66 +#define PCI_CHIP_RV250_Lg 0x4C67 +#define PCI_CHIP_RV250_Ln 0x4C6E +#define PCI_CHIP_RAGE128MF 0x4D46 +#define PCI_CHIP_RAGE128ML 0x4D4C +#define PCI_CHIP_R300_ND 0x4E44 +#define PCI_CHIP_R300_NE 0x4E45 +#define PCI_CHIP_R300_NF 0x4E46 +#define PCI_CHIP_R300_NG 0x4E47 +#define PCI_CHIP_R350_NH 0x4E48 +#define PCI_CHIP_R350_NI 0x4E49 +#define PCI_CHIP_R360_NJ 0x4E4A +#define PCI_CHIP_R350_NK 0x4E4B +#define PCI_CHIP_RV350_NP 0x4E50 +#define PCI_CHIP_RV350_NQ 0x4E51 +#define PCI_CHIP_RV350_NR 0x4E52 +#define PCI_CHIP_RV350_NS 0x4E53 +#define PCI_CHIP_RV350_NT 0x4E54 +#define PCI_CHIP_RV350_NV 0x4E56 +#define PCI_CHIP_RAGE128PA 0x5041 +#define PCI_CHIP_RAGE128PB 0x5042 +#define PCI_CHIP_RAGE128PC 0x5043 +#define PCI_CHIP_RAGE128PD 0x5044 +#define PCI_CHIP_RAGE128PE 0x5045 +#define PCI_CHIP_RAGE128PF 0x5046 +#define PCI_CHIP_RAGE128PG 0x5047 +#define PCI_CHIP_RAGE128PH 0x5048 +#define PCI_CHIP_RAGE128PI 0x5049 +#define PCI_CHIP_RAGE128PJ 0x504A +#define PCI_CHIP_RAGE128PK 0x504B +#define PCI_CHIP_RAGE128PL 0x504C +#define PCI_CHIP_RAGE128PM 0x504D +#define PCI_CHIP_RAGE128PN 0x504E +#define PCI_CHIP_RAGE128PO 0x504F +#define PCI_CHIP_RAGE128PP 0x5050 +#define PCI_CHIP_RAGE128PQ 0x5051 +#define PCI_CHIP_RAGE128PR 0x5052 +#define PCI_CHIP_RAGE128PS 0x5053 +#define PCI_CHIP_RAGE128PT 0x5054 +#define PCI_CHIP_RAGE128PU 0x5055 +#define PCI_CHIP_RAGE128PV 0x5056 +#define PCI_CHIP_RAGE128PW 0x5057 +#define PCI_CHIP_RAGE128PX 0x5058 +#define PCI_CHIP_RADEON_QD 0x5144 +#define PCI_CHIP_RADEON_QE 0x5145 +#define PCI_CHIP_RADEON_QF 0x5146 +#define PCI_CHIP_RADEON_QG 0x5147 +#define PCI_CHIP_R200_QH 0x5148 +#define PCI_CHIP_R200_QI 0x5149 +#define PCI_CHIP_R200_QJ 0x514A +#define PCI_CHIP_R200_QK 0x514B +#define PCI_CHIP_R200_QL 0x514C +#define PCI_CHIP_R200_QM 0x514D +#define PCI_CHIP_R200_QN 0x514E +#define PCI_CHIP_R200_QO 0x514F +#define PCI_CHIP_RV200_QW 0x5157 +#define PCI_CHIP_RV200_QX 0x5158 +#define PCI_CHIP_RV100_QY 0x5159 +#define PCI_CHIP_RV100_QZ 0x515A +#define PCI_CHIP_RN50 0x515E +#define PCI_CHIP_RAGE128RE 0x5245 +#define PCI_CHIP_RAGE128RF 0x5246 +#define PCI_CHIP_RAGE128RG 0x5247 +#define PCI_CHIP_RAGE128RK 0x524B +#define PCI_CHIP_RAGE128RL 0x524C +#define PCI_CHIP_RAGE128SE 0x5345 +#define PCI_CHIP_RAGE128SF 0x5346 +#define PCI_CHIP_RAGE128SG 0x5347 +#define PCI_CHIP_RAGE128SH 0x5348 +#define PCI_CHIP_RAGE128SK 0x534B +#define PCI_CHIP_RAGE128SL 0x534C +#define PCI_CHIP_RAGE128SM 0x534D +#define PCI_CHIP_RAGE128SN 0x534E +#define PCI_CHIP_RAGE128TF 0x5446 +#define PCI_CHIP_RAGE128TL 0x544C +#define PCI_CHIP_RAGE128TR 0x5452 +#define PCI_CHIP_RAGE128TS 0x5453 +#define PCI_CHIP_RAGE128TT 0x5454 +#define PCI_CHIP_RAGE128TU 0x5455 +#define PCI_CHIP_RV370_5460 0x5460 +#define PCI_CHIP_RV370_5461 0x5461 +#define PCI_CHIP_RV370_5462 0x5462 +#define PCI_CHIP_RV370_5463 0x5463 +#define PCI_CHIP_RV370_5464 0x5464 +#define PCI_CHIP_RV370_5465 0x5465 +#define PCI_CHIP_RV370_5466 0x5466 +#define PCI_CHIP_RV370_5467 0x5467 +#define PCI_CHIP_R423_UH 0x5548 +#define PCI_CHIP_R423_UI 0x5549 +#define PCI_CHIP_R423_UJ 0x554A +#define PCI_CHIP_R423_UK 0x554B +#define PCI_CHIP_R423_UQ 0x5551 +#define PCI_CHIP_R423_UR 0x5552 +#define PCI_CHIP_R423_UT 0x5554 +#define PCI_CHIP_MACH64VT 0x5654 +#define PCI_CHIP_MACH64VU 0x5655 +#define PCI_CHIP_MACH64VV 0x5656 +#define PCI_CHIP_RS300_5834 0x5834 +#define PCI_CHIP_RS300_5835 0x5835 +#define PCI_CHIP_RS300_5836 0x5836 +#define PCI_CHIP_RS300_5837 0x5837 +#define PCI_CHIP_RV370_5B60 0x5B60 +#define PCI_CHIP_RV370_5B61 0x5B61 +#define PCI_CHIP_RV370_5B62 0x5B62 +#define PCI_CHIP_RV370_5B63 0x5B63 +#define PCI_CHIP_RV370_5B64 0x5B64 +#define PCI_CHIP_RV370_5B65 0x5B65 +#define PCI_CHIP_RV370_5B66 0x5B66 +#define PCI_CHIP_RV370_5B67 0x5B67 +#define PCI_CHIP_RV280_5960 0x5960 +#define PCI_CHIP_RV280_5961 0x5961 +#define PCI_CHIP_RV280_5962 0x5962 +#define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV280_5C61 0x5C61 +#define PCI_CHIP_RV280_5C63 0x5C63 +#define PCI_CHIP_R423_5D57 0x5D57 +#define PCI_CHIP_RS350_7834 0x7834 +#define PCI_CHIP_RS350_7835 0x7835 + diff --git a/drivers/ati_radeon_fb.c b/drivers/ati_radeon_fb.c new file mode 100644 index 00000000000..e15140ab38d --- /dev/null +++ b/drivers/ati_radeon_fb.c @@ -0,0 +1,486 @@ +/* + * ATI Radeon Video card Framebuffer driver. + * + * Copyright 2007 Freescale Semiconductor, Inc. + * Zhang Wei + * Jason Jin + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Some codes of this file is partly ported from Linux kernel + * ATI video framebuffer driver. + * + * Now the driver is tested on below ATI chips: + * 9200 + * X300 + * X700 + * + */ + +#include + +#ifdef CONFIG_ATI_RADEON_FB + +#include +#include +#include +#include +#include +#include +#include + +#include +#include "ati_ids.h" +#include "ati_radeon_fb.h" + +#undef DEBUG + +#ifdef DEBUG +#define DPRINT(x...) printf(x) +#else +#define DPRINT(x...) do{}while(0) +#endif + +#ifndef min_t +#define min_t(type,x,y) \ + ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; }) +#endif + +#define MAX_MAPPED_VRAM (2048*2048*4) +#define MIN_MAPPED_VRAM (1024*768*1) + +/*#define PCI_VENDOR_ID_ATI*/ +#define PCI_CHIP_RV280_5960 0x5960 +#define PCI_CHIP_RV280_5961 0x5961 +#define PCI_CHIP_RV280_5962 0x5962 +#define PCI_CHIP_RV280_5964 0x5964 +#define PCI_CHIP_RV370_5B60 0x5B60 +#define PCI_CHIP_RV380_5657 0x5657 +#define PCI_CHIP_R420_554d 0x554d + +static struct pci_device_id ati_radeon_pci_ids[] = { + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5960}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5961}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5962}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV280_5964}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV370_5B60}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_RV380_5657}, + {PCI_VENDOR_ID_ATI, PCI_CHIP_R420_554d}, + {0, 0} +}; + +static u16 ati_radeon_id_family_table[][2] = { + {PCI_CHIP_RV280_5960, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV280_5961, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV280_5962, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV280_5964, CHIP_FAMILY_RV280}, + {PCI_CHIP_RV370_5B60, CHIP_FAMILY_RV380}, + {PCI_CHIP_RV380_5657, CHIP_FAMILY_RV380}, + {PCI_CHIP_R420_554d, CHIP_FAMILY_R420}, + {0, 0} +}; + +u16 get_radeon_id_family(u16 device) +{ + int i; + for (i=0; ati_radeon_id_family_table[0][i]; i+=2) + if (ati_radeon_id_family_table[0][i] == device) + return ati_radeon_id_family_table[0][i + 1]; + return 0; +} + +struct radeonfb_info *rinfo; + +static void radeon_identify_vram(struct radeonfb_info *rinfo) +{ + u32 tmp; + + /* framebuffer size */ + if ((rinfo->family == CHIP_FAMILY_RS100) || + (rinfo->family == CHIP_FAMILY_RS200) || + (rinfo->family == CHIP_FAMILY_RS300)) { + u32 tom = INREG(NB_TOM); + tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); + + radeon_fifo_wait(6); + OUTREG(MC_FB_LOCATION, tom); + OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); + OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); + OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); + + /* This is supposed to fix the crtc2 noise problem. */ + OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000); + + if ((rinfo->family == CHIP_FAMILY_RS100) || + (rinfo->family == CHIP_FAMILY_RS200)) { + /* This is to workaround the asic bug for RMX, some versions + of BIOS dosen't have this register initialized correctly. + */ + OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN, + ~CRTC_H_CUTOFF_ACTIVE_EN); + } + } else { + tmp = INREG(CONFIG_MEMSIZE); + } + + /* mem size is bits [28:0], mask off the rest */ + rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; + + /* + * Hack to get around some busted production M6's + * reporting no ram + */ + if (rinfo->video_ram == 0) { + switch (rinfo->pdev.device) { + case PCI_CHIP_RADEON_LY: + case PCI_CHIP_RADEON_LZ: + rinfo->video_ram = 8192 * 1024; + break; + default: + break; + } + } + + /* + * Now try to identify VRAM type + */ + if ((rinfo->family >= CHIP_FAMILY_R300) || + (INREG(MEM_SDRAM_MODE_REG) & (1<<30))) + rinfo->vram_ddr = 1; + else + rinfo->vram_ddr = 0; + + tmp = INREG(MEM_CNTL); + if (IS_R300_VARIANT(rinfo)) { + tmp &= R300_MEM_NUM_CHANNELS_MASK; + switch (tmp) { + case 0: rinfo->vram_width = 64; break; + case 1: rinfo->vram_width = 128; break; + case 2: rinfo->vram_width = 256; break; + default: rinfo->vram_width = 128; break; + } + } else if ((rinfo->family == CHIP_FAMILY_RV100) || + (rinfo->family == CHIP_FAMILY_RS100) || + (rinfo->family == CHIP_FAMILY_RS200)){ + if (tmp & RV100_MEM_HALF_MODE) + rinfo->vram_width = 32; + else + rinfo->vram_width = 64; + } else { + if (tmp & MEM_NUM_CHANNELS_MASK) + rinfo->vram_width = 128; + else + rinfo->vram_width = 64; + } + + /* This may not be correct, as some cards can have half of channel disabled + * ToDo: identify these cases + */ + + DPRINT("radeonfb: Found %ldk of %s %d bits wide videoram\n", + rinfo->video_ram / 1024, + rinfo->vram_ddr ? "DDR" : "SDRAM", + rinfo->vram_width); + +} + +static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) +{ + int i; + + radeon_fifo_wait(20); + +#if 0 + /* Workaround from XFree */ + if (rinfo->is_mobility) { + /* A temporal workaround for the occational blanking on certain laptop + * panels. This appears to related to the PLL divider registers + * (fail to lock?). It occurs even when all dividers are the same + * with their old settings. In this case we really don't need to + * fiddle with PLL registers. By doing this we can avoid the blanking + * problem with some panels. + */ + if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && + (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & + (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { + /* We still have to force a switch to selected PPLL div thanks to + * an XFree86 driver bug which will switch it away in some cases + * even when using UseFDev */ + OUTREGP(CLOCK_CNTL_INDEX, + mode->clk_cntl_index & PPLL_DIV_SEL_MASK, + ~PPLL_DIV_SEL_MASK); + radeon_pll_errata_after_index(rinfo); + radeon_pll_errata_after_data(rinfo); + return; + } + } +#endif + if(rinfo->pdev.device == PCI_CHIP_RV370_5B60) return; + + /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/ + OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK); + + /* Reset PPLL & enable atomic update */ + OUTPLLP(PPLL_CNTL, + PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN, + ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); + + /* Switch to selected PPLL divider */ + OUTREGP(CLOCK_CNTL_INDEX, + mode->clk_cntl_index & PPLL_DIV_SEL_MASK, + ~PPLL_DIV_SEL_MASK); + + /* Set PPLL ref. div */ + if (rinfo->family == CHIP_FAMILY_R300 || + rinfo->family == CHIP_FAMILY_RS300 || + rinfo->family == CHIP_FAMILY_R350 || + rinfo->family == CHIP_FAMILY_RV350) { + if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { + /* When restoring console mode, use saved PPLL_REF_DIV + * setting. + */ + OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); + } else { + /* R300 uses ref_div_acc field as real ref divider */ + OUTPLLP(PPLL_REF_DIV, + (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), + ~R300_PPLL_REF_DIV_ACC_MASK); + } + } else + OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); + + /* Set PPLL divider 3 & post divider*/ + OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); + OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); + + /* Write update */ + while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R) + ; + OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W); + + /* Wait read update complete */ + /* FIXME: Certain revisions of R300 can't recover here. Not sure of + the cause yet, but this workaround will mask the problem for now. + Other chips usually will pass at the very first test, so the + workaround shouldn't have any effect on them. */ + for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++) + ; + + OUTPLL(HTOTAL_CNTL, 0); + + /* Clear reset & atomic update */ + OUTPLLP(PPLL_CNTL, 0, + ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN)); + + /* We may want some locking ... oh well */ + udelay(5000); + + /* Switch back VCLK source to PPLL */ + OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK); +} + +typedef struct { + u16 reg; + u32 val; +} reg_val; + + +/* these common regs are cleared before mode setting so they do not + * interfere with anything + */ +static reg_val common_regs[] = { + { OVR_CLR, 0 }, + { OVR_WID_LEFT_RIGHT, 0 }, + { OVR_WID_TOP_BOTTOM, 0 }, + { OV0_SCALE_CNTL, 0 }, + { SUBPIC_CNTL, 0 }, + { VIPH_CONTROL, 0 }, + { I2C_CNTL_1, 0 }, + { GEN_INT_CNTL, 0 }, + { CAP0_TRIG_CNTL, 0 }, + { CAP1_TRIG_CNTL, 0 }, +}; + + +void radeon_setmode(void) +{ + int i; + struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); + + mode->crtc_gen_cntl = 0x03000200; + mode->crtc_ext_cntl = 0x00008048; + mode->dac_cntl = 0xff002100; + mode->crtc_h_total_disp = 0x4f0063; + mode->crtc_h_sync_strt_wid = 0x8c02a2; + mode->crtc_v_total_disp = 0x01df020c; + mode->crtc_v_sync_strt_wid = 0x8201ea; + mode->crtc_pitch = 0x00500050; + + OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); + OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, + ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS)); + OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); + OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); + OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); + OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); + OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); + OUTREG(CRTC_OFFSET, 0); + OUTREG(CRTC_OFFSET_CNTL, 0); + OUTREG(CRTC_PITCH, mode->crtc_pitch); + + mode->clk_cntl_index = 0x300; + mode->ppll_ref_div = 0xc; + mode->ppll_div_3 = 0x00030059; + + radeon_write_pll_regs(rinfo, mode); +} + +int radeon_probe(struct radeonfb_info *rinfo) +{ + pci_dev_t pdev; + u16 did; + + pdev = pci_find_devices(ati_radeon_pci_ids, 0); + + if (pdev != -1) { + pci_read_config_word(pdev, PCI_DEVICE_ID, &did); + printf("ATI Radeon video card (%04x, %04x) found @(%d:%d:%d)\n", + PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff, + (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7); + + strcpy(rinfo->name, "ATI Radeon"); + rinfo->pdev.vendor = PCI_VENDOR_ID_ATI; + rinfo->pdev.device = did; + rinfo->family = get_radeon_id_family(rinfo->pdev.device); + pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, + &rinfo->fb_base_phys); + pci_read_config_dword(pdev, PCI_BASE_ADDRESS_2, + &rinfo->mmio_base_phys); + rinfo->fb_base_phys &= 0xfffff000; + rinfo->mmio_base_phys &= ~0x04; + + rinfo->mmio_base = (void *)rinfo->mmio_base_phys; + DPRINT("rinfo->mmio_base = 0x%x\n",rinfo->mmio_base); + rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; + DPRINT("rinfo->fb_local_base = 0x%x\n",rinfo->fb_local_base); + /* PostBIOS with x86 emulater */ + BootVideoCardBIOS(pdev, NULL, 0); + + /* + * Check for errata + * (These will be added in the future for the chipfamily + * R300, RV200, RS200, RV100, RS100.) + */ + + /* Get VRAM size and type */ + radeon_identify_vram(rinfo); + + rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, + rinfo->video_ram); + rinfo->fb_base = (void *)rinfo->fb_base_phys; + + DPRINT("Radeon: framebuffer base phy address 0x%08x," \ + "MMIO base phy address 0x%08x," \ + "framebuffer local base 0x%08x.\n ", + rinfo->fb_base_phys, rinfo->mmio_base_phys, + rinfo->fb_local_base); + + return 0; + } + return -1; +} + +/* + * The Graphic Device + */ +GraphicDevice ctfb; + +#define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */ +#define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */ +#define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */ +#define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */ + +void *video_hw_init(void) +{ + GraphicDevice *pGD = (GraphicDevice *) & ctfb; + int i; + u32 *vm; + + rinfo = malloc(sizeof(struct radeonfb_info)); + + if(radeon_probe(rinfo)) { + printf("No radeon video card found!\n"); + return NULL; + } + + /* fill in Graphic device struct */ + sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", 640, + 480, 16, (1000 / 1000), + (2000 / 1000)); + printf ("%s\n", pGD->modeIdent); + + pGD->winSizeX = 640; + pGD->winSizeY = 480; + pGD->plnSizeX = 640; + pGD->plnSizeY = 480; + + pGD->gdfBytesPP = 1; + pGD->gdfIndex = GDF__8BIT_INDEX; + + pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS; + pGD->pciBase = rinfo->fb_base_phys; + pGD->frameAdrs = rinfo->fb_base_phys; + pGD->memSize = 64 * 1024 * 1024; + + /* Cursor Start Address */ + pGD->dprBase = + (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + rinfo->fb_base_phys; + if ((pGD->dprBase & 0x0fff) != 0) { + /* allign it */ + pGD->dprBase &= 0xfffff000; + pGD->dprBase += 0x00001000; + } + DPRINT ("Cursor Start %x Pattern Start %x\n", pGD->dprBase, + PATTERN_ADR); + pGD->vprBase = rinfo->fb_base_phys; /* Dummy */ + pGD->cprBase = rinfo->fb_base_phys; /* Dummy */ + /* set up Hardware */ + + /* Clear video memory */ + i = pGD->memSize / 4; + vm = (unsigned int *) pGD->pciBase; + while (i--) + *vm++ = 0; + /*SetDrawingEngine (bits_per_pixel);*/ + + radeon_setmode(); + + return ((void *) pGD); +} + +void video_set_lut (unsigned int index, /* color number */ + unsigned char r, /* red */ + unsigned char g, /* green */ + unsigned char b /* blue */ + ) +{ + OUTREG(PALETTE_INDEX, index); + OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b); +} +#endif diff --git a/drivers/ati_radeon_fb.h b/drivers/ati_radeon_fb.h new file mode 100644 index 00000000000..1c3ba64cfb0 --- /dev/null +++ b/drivers/ati_radeon_fb.h @@ -0,0 +1,293 @@ +#ifndef __ATI_RADEON_FB_H +#define __ATI_RADEON_FB_H + +/*************************************************************** + * Most of the definitions here are adapted right from XFree86 * + ***************************************************************/ + + +/* + * Chip families. Must fit in the low 16 bits of a long word + */ +enum radeon_family { + CHIP_FAMILY_UNKNOW, + CHIP_FAMILY_LEGACY, + CHIP_FAMILY_RADEON, + CHIP_FAMILY_RV100, + CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/ + CHIP_FAMILY_RV200, + CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), + RS250 (IGP 7000) */ + CHIP_FAMILY_R200, + CHIP_FAMILY_RV250, + CHIP_FAMILY_RS300, /* Radeon 9000 IGP */ + CHIP_FAMILY_RV280, + CHIP_FAMILY_R300, + CHIP_FAMILY_R350, + CHIP_FAMILY_RV350, + CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */ + CHIP_FAMILY_R420, /* R420/R423/M18 */ + CHIP_FAMILY_LAST, +}; + +#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \ + ((rinfo)->family == CHIP_FAMILY_RV200) || \ + ((rinfo)->family == CHIP_FAMILY_RS100) || \ + ((rinfo)->family == CHIP_FAMILY_RS200) || \ + ((rinfo)->family == CHIP_FAMILY_RV250) || \ + ((rinfo)->family == CHIP_FAMILY_RV280) || \ + ((rinfo)->family == CHIP_FAMILY_RS300)) + + +#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \ + ((rinfo)->family == CHIP_FAMILY_RV350) || \ + ((rinfo)->family == CHIP_FAMILY_R350) || \ + ((rinfo)->family == CHIP_FAMILY_RV380) || \ + ((rinfo)->family == CHIP_FAMILY_R420)) + + +struct radeonfb_info { + char name[20]; + + struct pci_device_id pdev; + u16 family; + + u32 fb_base_phys; + u32 mmio_base_phys; + + void *mmio_base; + void *fb_base; + + u32 video_ram; + u32 mapped_vram; + int vram_width; + int vram_ddr; + + u32 fb_local_base; +}; + +#define INREG8(addr) readb((rinfo->mmio_base)+addr) +#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr) +#define INREG16(addr) readw((rinfo->mmio_base)+addr) +#define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr) +#define INREG(addr) readl((rinfo->mmio_base)+addr) +#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr) + +static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, + u32 val, u32 mask) +{ + unsigned int tmp; + + tmp = INREG(addr); + tmp &= (mask); + tmp |= (val); + OUTREG(addr, tmp); +} + +#define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask) + + +/* + * 2D Engine helper routines + */ +static inline void radeon_engine_flush (struct radeonfb_info *rinfo) +{ + int i; + + /* initiate flush */ + OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, + ~RB2D_DC_FLUSH_ALL); + + for (i=0; i < 2000000; i++) { + if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) + return; + udelay(1); + } + printf("radeonfb: Flush Timeout !\n"); +} + + +static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) +{ + int i; + + for (i=0; i<2000000; i++) { + if ((INREG(RBBM_STATUS) & 0x7f) >= entries) + return; + udelay(1); + } + printf("radeonfb: FIFO Timeout !\n"); +} + + +static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) +{ + int i; + + /* ensure FIFO is empty before waiting for idle */ + _radeon_fifo_wait (rinfo, 64); + + for (i=0; i<2000000; i++) { + if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) { + radeon_engine_flush (rinfo); + return; + } + udelay(1); + } + printf("radeonfb: Idle Timeout !\n"); +} + + +#define radeon_engine_idle() _radeon_engine_idle(rinfo) +#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) +#define radeon_msleep(ms) _radeon_msleep(rinfo,ms) + +/* + * This structure contains the various registers manipulated by this + * driver for setting or restoring a mode. It's mostly copied from + * XFree's RADEONSaveRec structure. A few chip settings might still be + * tweaked without beeing reflected or saved in these registers though + */ +struct radeon_regs { + /* Common registers */ + u32 ovr_clr; + u32 ovr_wid_left_right; + u32 ovr_wid_top_bottom; + u32 ov0_scale_cntl; + u32 mpp_tb_config; + u32 mpp_gp_config; + u32 subpic_cntl; + u32 viph_control; + u32 i2c_cntl_1; + u32 gen_int_cntl; + u32 cap0_trig_cntl; + u32 cap1_trig_cntl; + u32 bus_cntl; + u32 surface_cntl; + u32 bios_5_scratch; + + /* Other registers to save for VT switches or driver load/unload */ + u32 dp_datatype; + u32 rbbm_soft_reset; + u32 clock_cntl_index; + u32 amcgpio_en_reg; + u32 amcgpio_mask; + + /* Surface/tiling registers */ + u32 surf_lower_bound[8]; + u32 surf_upper_bound[8]; + u32 surf_info[8]; + + /* CRTC registers */ + u32 crtc_gen_cntl; + u32 crtc_ext_cntl; + u32 dac_cntl; + u32 crtc_h_total_disp; + u32 crtc_h_sync_strt_wid; + u32 crtc_v_total_disp; + u32 crtc_v_sync_strt_wid; + u32 crtc_offset; + u32 crtc_offset_cntl; + u32 crtc_pitch; + u32 disp_merge_cntl; + u32 grph_buffer_cntl; + u32 crtc_more_cntl; + + /* CRTC2 registers */ + u32 crtc2_gen_cntl; + u32 dac2_cntl; + u32 disp_output_cntl; + u32 disp_hw_debug; + u32 disp2_merge_cntl; + u32 grph2_buffer_cntl; + u32 crtc2_h_total_disp; + u32 crtc2_h_sync_strt_wid; + u32 crtc2_v_total_disp; + u32 crtc2_v_sync_strt_wid; + u32 crtc2_offset; + u32 crtc2_offset_cntl; + u32 crtc2_pitch; + + /* Flat panel regs */ + u32 fp_crtc_h_total_disp; + u32 fp_crtc_v_total_disp; + u32 fp_gen_cntl; + u32 fp2_gen_cntl; + u32 fp_h_sync_strt_wid; + u32 fp2_h_sync_strt_wid; + u32 fp_horz_stretch; + u32 fp_panel_cntl; + u32 fp_v_sync_strt_wid; + u32 fp2_v_sync_strt_wid; + u32 fp_vert_stretch; + u32 lvds_gen_cntl; + u32 lvds_pll_cntl; + u32 tmds_crc; + u32 tmds_transmitter_cntl; + + /* Computed values for PLL */ + u32 dot_clock_freq; + int feedback_div; + int post_div; + + /* PLL registers */ + u32 ppll_div_3; + u32 ppll_ref_div; + u32 vclk_ecp_cntl; + u32 clk_cntl_index; + + /* Computed values for PLL2 */ + u32 dot_clock_freq_2; + int feedback_div_2; + int post_div_2; + + /* PLL2 registers */ + u32 p2pll_ref_div; + u32 p2pll_div_0; + u32 htotal_cntl2; + + /* Palette */ + int palette_valid; +}; + +static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) +{ + u32 data; + + OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); + //radeon_pll_errata_after_index(rinfo); + data = INREG(CLOCK_CNTL_DATA); + //radeon_pll_errata_after_data(rinfo); + return data; +} + +static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, + u32 val) +{ + + OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); + //radeon_pll_errata_after_index(rinfo); + OUTREG(CLOCK_CNTL_DATA, val); + //radeon_pll_errata_after_data(rinfo); +} + + +static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, + u32 val, u32 mask) +{ + unsigned int tmp; + + tmp = __INPLL(rinfo, index); + tmp &= (mask); + tmp |= (val); + __OUTPLL(rinfo, index, tmp); +} + + +#define INPLL(addr) __INPLL(rinfo, addr) +#define OUTPLL(index, val) __OUTPLL(rinfo, index, val) +#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask) + + + +#endif diff --git a/include/radeon.h b/include/radeon.h new file mode 100644 index 00000000000..f4e24a7134b --- /dev/null +++ b/include/radeon.h @@ -0,0 +1,1986 @@ +#ifndef _RADEON_H +#define _RADEON_H + + +#define RADEON_REGSIZE 0x4000 + + +#define MM_INDEX 0x0000 +#define MM_DATA 0x0004 +#define BUS_CNTL 0x0030 +#define HI_STAT 0x004C +#define BUS_CNTL1 0x0034 +#define I2C_CNTL_1 0x0094 +#define CONFIG_CNTL 0x00E0 +#define CONFIG_MEMSIZE 0x00F8 +#define CONFIG_APER_0_BASE 0x0100 +#define CONFIG_APER_1_BASE 0x0104 +#define CONFIG_APER_SIZE 0x0108 +#define CONFIG_REG_1_BASE 0x010C +#define CONFIG_REG_APER_SIZE 0x0110 +#define PAD_AGPINPUT_DELAY 0x0164 +#define PAD_CTLR_STRENGTH 0x0168 +#define PAD_CTLR_UPDATE 0x016C +#define PAD_CTLR_MISC 0x0aa0 +#define AGP_CNTL 0x0174 +#define BM_STATUS 0x0160 +#define CAP0_TRIG_CNTL 0x0950 +#define CAP1_TRIG_CNTL 0x09c0 +#define VIPH_CONTROL 0x0C40 +#define VENDOR_ID 0x0F00 +#define DEVICE_ID 0x0F02 +#define COMMAND 0x0F04 +#define STATUS 0x0F06 +#define REVISION_ID 0x0F08 +#define REGPROG_INF 0x0F09 +#define SUB_CLASS 0x0F0A +#define BASE_CODE 0x0F0B +#define CACHE_LINE 0x0F0C +#define LATENCY 0x0F0D +#define HEADER 0x0F0E +#define BIST 0x0F0F +#define REG_MEM_BASE 0x0F10 +#define REG_IO_BASE 0x0F14 +#define REG_REG_BASE 0x0F18 +#define ADAPTER_ID 0x0F2C +#define BIOS_ROM 0x0F30 +#define CAPABILITIES_PTR 0x0F34 +#define INTERRUPT_LINE 0x0F3C +#define INTERRUPT_PIN 0x0F3D +#define MIN_GRANT 0x0F3E +#define MAX_LATENCY 0x0F3F +#define ADAPTER_ID_W 0x0F4C +#define PMI_CAP_ID 0x0F50 +#define PMI_NXT_CAP_PTR 0x0F51 +#define PMI_PMC_REG 0x0F52 +#define PM_STATUS 0x0F54 +#define PMI_DATA 0x0F57 +#define AGP_CAP_ID 0x0F58 +#define AGP_STATUS 0x0F5C +#define AGP_COMMAND 0x0F60 +#define AIC_CTRL 0x01D0 +#define AIC_STAT 0x01D4 +#define AIC_PT_BASE 0x01D8 +#define AIC_LO_ADDR 0x01DC +#define AIC_HI_ADDR 0x01E0 +#define AIC_TLB_ADDR 0x01E4 +#define AIC_TLB_DATA 0x01E8 +#define DAC_CNTL 0x0058 +#define DAC_CNTL2 0x007c +#define CRTC_GEN_CNTL 0x0050 +#define MEM_CNTL 0x0140 +#define MC_CNTL 0x0140 +#define EXT_MEM_CNTL 0x0144 +#define MC_TIMING_CNTL 0x0144 +#define MC_AGP_LOCATION 0x014C +#define MEM_IO_CNTL_A0 0x0178 +#define MEM_REFRESH_CNTL 0x0178 +#define MEM_INIT_LATENCY_TIMER 0x0154 +#define MC_INIT_GFX_LAT_TIMER 0x0154 +#define MEM_SDRAM_MODE_REG 0x0158 +#define AGP_BASE 0x0170 +#define MEM_IO_CNTL_A1 0x017C +#define MC_READ_CNTL_AB 0x017C +#define MEM_IO_CNTL_B0 0x0180 +#define MC_INIT_MISC_LAT_TIMER 0x0180 +#define MEM_IO_CNTL_B1 0x0184 +#define MC_IOPAD_CNTL 0x0184 +#define MC_DEBUG 0x0188 +#define MC_STATUS 0x0150 +#define MEM_IO_OE_CNTL 0x018C +#define MC_CHIP_IO_OE_CNTL_AB 0x018C +#define MC_FB_LOCATION 0x0148 +//#define MC_FB_LOCATION 0x0188 +#define HOST_PATH_CNTL 0x0130 +#define MEM_VGA_WP_SEL 0x0038 +#define MEM_VGA_RP_SEL 0x003C +#define HDP_DEBUG 0x0138 +#define SW_SEMAPHORE 0x013C +#define CRTC2_GEN_CNTL 0x03f8 +#define CRTC2_DISPLAY_BASE_ADDR 0x033c +#define SURFACE_CNTL 0x0B00 +#define SURFACE0_LOWER_BOUND 0x0B04 +#define SURFACE1_LOWER_BOUND 0x0B14 +#define SURFACE2_LOWER_BOUND 0x0B24 +#define SURFACE3_LOWER_BOUND 0x0B34 +#define SURFACE4_LOWER_BOUND 0x0B44 +#define SURFACE5_LOWER_BOUND 0x0B54 +#define SURFACE6_LOWER_BOUND 0x0B64 +#define SURFACE7_LOWER_BOUND 0x0B74 +#define SURFACE0_UPPER_BOUND 0x0B08 +#define SURFACE1_UPPER_BOUND 0x0B18 +#define SURFACE2_UPPER_BOUND 0x0B28 +#define SURFACE3_UPPER_BOUND 0x0B38 +#define SURFACE4_UPPER_BOUND 0x0B48 +#define SURFACE5_UPPER_BOUND 0x0B58 +#define SURFACE6_UPPER_BOUND 0x0B68 +#define SURFACE7_UPPER_BOUND 0x0B78 +#define SURFACE0_INFO 0x0B0C +#define SURFACE1_INFO 0x0B1C +#define SURFACE2_INFO 0x0B2C +#define SURFACE3_INFO 0x0B3C +#define SURFACE4_INFO 0x0B4C +#define SURFACE5_INFO 0x0B5C +#define SURFACE6_INFO 0x0B6C +#define SURFACE7_INFO 0x0B7C +#define SURFACE_ACCESS_FLAGS 0x0BF8 +#define SURFACE_ACCESS_CLR 0x0BFC +#define GEN_INT_CNTL 0x0040 +#define GEN_INT_STATUS 0x0044 +#define CRTC_EXT_CNTL 0x0054 +#define RB3D_CNTL 0x1C3C +#define WAIT_UNTIL 0x1720 +#define ISYNC_CNTL 0x1724 +#define RBBM_GUICNTL 0x172C +#define RBBM_STATUS 0x0E40 +#define RBBM_STATUS_alt_1 0x1740 +#define RBBM_CNTL 0x00EC +#define RBBM_CNTL_alt_1 0x0E44 +#define RBBM_SOFT_RESET 0x00F0 +#define RBBM_SOFT_RESET_alt_1 0x0E48 +#define NQWAIT_UNTIL 0x0E50 +#define RBBM_DEBUG 0x0E6C +#define RBBM_CMDFIFO_ADDR 0x0E70 +#define RBBM_CMDFIFO_DATAL 0x0E74 +#define RBBM_CMDFIFO_DATAH 0x0E78 +#define RBBM_CMDFIFO_STAT 0x0E7C +#define CRTC_STATUS 0x005C +#define GPIO_VGA_DDC 0x0060 +#define GPIO_DVI_DDC 0x0064 +#define GPIO_MONID 0x0068 +#define GPIO_CRT2_DDC 0x006c +#define PALETTE_INDEX 0x00B0 +#define PALETTE_DATA 0x00B4 +#define PALETTE_30_DATA 0x00B8 +#define CRTC_H_TOTAL_DISP 0x0200 +#define CRTC_H_SYNC_STRT_WID 0x0204 +#define CRTC_V_TOTAL_DISP 0x0208 +#define CRTC_V_SYNC_STRT_WID 0x020C +#define CRTC_VLINE_CRNT_VLINE 0x0210 +#define CRTC_CRNT_FRAME 0x0214 +#define CRTC_GUI_TRIG_VLINE 0x0218 +#define CRTC_DEBUG 0x021C +#define CRTC_OFFSET_RIGHT 0x0220 +#define CRTC_OFFSET 0x0224 +#define CRTC_OFFSET_CNTL 0x0228 +#define CRTC_PITCH 0x022C +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 +#define DISPLAY_BASE_ADDR 0x023C +#define SNAPSHOT_VH_COUNTS 0x0240 +#define SNAPSHOT_F_COUNT 0x0244 +#define N_VIF_COUNT 0x0248 +#define SNAPSHOT_VIF_COUNT 0x024C +#define FP_CRTC_H_TOTAL_DISP 0x0250 +#define FP_CRTC_V_TOTAL_DISP 0x0254 +#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 +#define CRT_CRTC_V_SYNC_STRT_WID 0x025C +#define CUR_OFFSET 0x0260 +#define CUR_HORZ_VERT_POSN 0x0264 +#define CUR_HORZ_VERT_OFF 0x0268 +#define CUR_CLR0 0x026C +#define CUR_CLR1 0x0270 +#define FP_HORZ_VERT_ACTIVE 0x0278 +#define CRTC_MORE_CNTL 0x027C +#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) +#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) +#define DAC_EXT_CNTL 0x0280 +#define FP_GEN_CNTL 0x0284 +#define FP_HORZ_STRETCH 0x028C +#define FP_VERT_STRETCH 0x0290 +#define FP_H_SYNC_STRT_WID 0x02C4 +#define FP_V_SYNC_STRT_WID 0x02C8 +#define AUX_WINDOW_HORZ_CNTL 0x02D8 +#define AUX_WINDOW_VERT_CNTL 0x02DC +//#define DDA_CONFIG 0x02e0 +//#define DDA_ON_OFF 0x02e4 +#define DVI_I2C_CNTL_1 0x02e4 +#define GRPH_BUFFER_CNTL 0x02F0 +#define GRPH2_BUFFER_CNTL 0x03F0 +#define VGA_BUFFER_CNTL 0x02F4 +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 +#define OV0_PIPELINE_CNTL 0x0408 +#define OV0_REG_LOAD_CNTL 0x0410 +#define OV0_SCALE_CNTL 0x0420 +#define OV0_V_INC 0x0424 +#define OV0_P1_V_ACCUM_INIT 0x0428 +#define OV0_P23_V_ACCUM_INIT 0x042C +#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +#define OV0_BASE_ADDR 0x043C +#define OV0_VID_BUF0_BASE_ADRS 0x0440 +#define OV0_VID_BUF1_BASE_ADRS 0x0444 +#define OV0_VID_BUF2_BASE_ADRS 0x0448 +#define OV0_VID_BUF3_BASE_ADRS 0x044C +#define OV0_VID_BUF4_BASE_ADRS 0x0450 +#define OV0_VID_BUF5_BASE_ADRS 0x0454 +#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define OV0_AUTO_FLIP_CNTRL 0x0470 +#define OV0_DEINTERLACE_PATTERN 0x0474 +#define OV0_SUBMIT_HISTORY 0x0478 +#define OV0_H_INC 0x0480 +#define OV0_STEP_BY 0x0484 +#define OV0_P1_H_ACCUM_INIT 0x0488 +#define OV0_P23_H_ACCUM_INIT 0x048C +#define OV0_P1_X_START_END 0x0494 +#define OV0_P2_X_START_END 0x0498 +#define OV0_P3_X_START_END 0x049C +#define OV0_FILTER_CNTL 0x04A0 +#define OV0_FOUR_TAP_COEF_0 0x04B0 +#define OV0_FOUR_TAP_COEF_1 0x04B4 +#define OV0_FOUR_TAP_COEF_2 0x04B8 +#define OV0_FOUR_TAP_COEF_3 0x04BC +#define OV0_FOUR_TAP_COEF_4 0x04C0 +#define OV0_FLAG_CNTRL 0x04DC +#define OV0_SLICE_CNTL 0x04E0 +#define OV0_VID_KEY_CLR_LOW 0x04E4 +#define OV0_VID_KEY_CLR_HIGH 0x04E8 +#define OV0_GRPH_KEY_CLR_LOW 0x04EC +#define OV0_GRPH_KEY_CLR_HIGH 0x04F0 +#define OV0_KEY_CNTL 0x04F4 +#define OV0_TEST 0x04F8 +#define SUBPIC_CNTL 0x0540 +#define SUBPIC_DEFCOLCON 0x0544 +#define SUBPIC_Y_X_START 0x054C +#define SUBPIC_Y_X_END 0x0550 +#define SUBPIC_V_INC 0x0554 +#define SUBPIC_H_INC 0x0558 +#define SUBPIC_BUF0_OFFSET 0x055C +#define SUBPIC_BUF1_OFFSET 0x0560 +#define SUBPIC_LC0_OFFSET 0x0564 +#define SUBPIC_LC1_OFFSET 0x0568 +#define SUBPIC_PITCH 0x056C +#define SUBPIC_BTN_HLI_COLCON 0x0570 +#define SUBPIC_BTN_HLI_Y_X_START 0x0574 +#define SUBPIC_BTN_HLI_Y_X_END 0x0578 +#define SUBPIC_PALETTE_INDEX 0x057C +#define SUBPIC_PALETTE_DATA 0x0580 +#define SUBPIC_H_ACCUM_INIT 0x0584 +#define SUBPIC_V_ACCUM_INIT 0x0588 +#define DISP_MISC_CNTL 0x0D00 +#define DAC_MACRO_CNTL 0x0D04 +#define DISP_PWR_MAN 0x0D08 +#define DISP_TEST_DEBUG_CNTL 0x0D10 +#define DISP_HW_DEBUG 0x0D14 +#define DAC_CRC_SIG1 0x0D18 +#define DAC_CRC_SIG2 0x0D1C +#define OV0_LIN_TRANS_A 0x0D20 +#define OV0_LIN_TRANS_B 0x0D24 +#define OV0_LIN_TRANS_C 0x0D28 +#define OV0_LIN_TRANS_D 0x0D2C +#define OV0_LIN_TRANS_E 0x0D30 +#define OV0_LIN_TRANS_F 0x0D34 +#define OV0_GAMMA_0_F 0x0D40 +#define OV0_GAMMA_10_1F 0x0D44 +#define OV0_GAMMA_20_3F 0x0D48 +#define OV0_GAMMA_40_7F 0x0D4C +#define OV0_GAMMA_380_3BF 0x0D50 +#define OV0_GAMMA_3C0_3FF 0x0D54 +#define DISP_MERGE_CNTL 0x0D60 +#define DISP_OUTPUT_CNTL 0x0D64 +#define DISP_LIN_TRANS_GRPH_A 0x0D80 +#define DISP_LIN_TRANS_GRPH_B 0x0D84 +#define DISP_LIN_TRANS_GRPH_C 0x0D88 +#define DISP_LIN_TRANS_GRPH_D 0x0D8C +#define DISP_LIN_TRANS_GRPH_E 0x0D90 +#define DISP_LIN_TRANS_GRPH_F 0x0D94 +#define DISP_LIN_TRANS_VID_A 0x0D98 +#define DISP_LIN_TRANS_VID_B 0x0D9C +#define DISP_LIN_TRANS_VID_C 0x0DA0 +#define DISP_LIN_TRANS_VID_D 0x0DA4 +#define DISP_LIN_TRANS_VID_E 0x0DA8 +#define DISP_LIN_TRANS_VID_F 0x0DAC +#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 +#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 +#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 +#define RMX_HORZ_PHASE 0x0DBC +#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 +#define DAC_BROAD_PULSE 0x0DC4 +#define DAC_SKEW_CLKS 0x0DC8 +#define DAC_INCR 0x0DCC +#define DAC_NEG_SYNC_LEVEL 0x0DD0 +#define DAC_POS_SYNC_LEVEL 0x0DD4 +#define DAC_BLANK_LEVEL 0x0DD8 +#define CLOCK_CNTL_INDEX 0x0008 +#define CLOCK_CNTL_DATA 0x000C +#define CP_RB_CNTL 0x0704 +#define CP_RB_BASE 0x0700 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define SCRATCH_REG0 0x15E0 +#define GUI_SCRATCH_REG0 0x15E0 +#define SCRATCH_REG1 0x15E4 +#define GUI_SCRATCH_REG1 0x15E4 +#define SCRATCH_REG2 0x15E8 +#define GUI_SCRATCH_REG2 0x15E8 +#define SCRATCH_REG3 0x15EC +#define GUI_SCRATCH_REG3 0x15EC +#define SCRATCH_REG4 0x15F0 +#define GUI_SCRATCH_REG4 0x15F0 +#define SCRATCH_REG5 0x15F4 +#define GUI_SCRATCH_REG5 0x15F4 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DP_BRUSH_FRGD_CLR 0x147C +#define DP_BRUSH_BKGD_CLR 0x1478 +#define DST_LINE_START 0x1600 +#define DST_LINE_END 0x1604 +#define SRC_OFFSET 0x15AC +#define SRC_PITCH 0x15B0 +#define SRC_TILE 0x1704 +#define SRC_PITCH_OFFSET 0x1428 +#define SRC_X 0x1414 +#define SRC_Y 0x1418 +#define SRC_X_Y 0x1590 +#define SRC_Y_X 0x1434 +#define DST_Y_X 0x1438 +#define DST_WIDTH_HEIGHT 0x1598 +#define DST_HEIGHT_WIDTH 0x143c +#define DST_OFFSET 0x1404 +#define SRC_CLUT_ADDRESS 0x1780 +#define SRC_CLUT_DATA 0x1784 +#define SRC_CLUT_DATA_RD 0x1788 +#define HOST_DATA0 0x17C0 +#define HOST_DATA1 0x17C4 +#define HOST_DATA2 0x17C8 +#define HOST_DATA3 0x17CC +#define HOST_DATA4 0x17D0 +#define HOST_DATA5 0x17D4 +#define HOST_DATA6 0x17D8 +#define HOST_DATA7 0x17DC +#define HOST_DATA_LAST 0x17E0 +#define DP_SRC_ENDIAN 0x15D4 +#define DP_SRC_FRGD_CLR 0x15D8 +#define DP_SRC_BKGD_CLR 0x15DC +#define SC_LEFT 0x1640 +#define SC_RIGHT 0x1644 +#define SC_TOP 0x1648 +#define SC_BOTTOM 0x164C +#define SRC_SC_RIGHT 0x1654 +#define SRC_SC_BOTTOM 0x165C +#define DP_CNTL 0x16C0 +#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 +#define DP_DATATYPE 0x16C4 +#define DP_MIX 0x16C8 +#define DP_WRITE_MSK 0x16CC +#define DP_XOP 0x17F8 +#define CLR_CMP_CLR_SRC 0x15C4 +#define CLR_CMP_CLR_DST 0x15C8 +#define CLR_CMP_CNTL 0x15C0 +#define CLR_CMP_MSK 0x15CC +#define DSTCACHE_MODE 0x1710 +#define DSTCACHE_CTLSTAT 0x1714 +#define DEFAULT_PITCH_OFFSET 0x16E0 +#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 +#define DEFAULT_SC_TOP_LEFT 0x16EC +#define SRC_PITCH_OFFSET 0x1428 +#define DST_PITCH_OFFSET 0x142C +#define DP_GUI_MASTER_CNTL 0x146C +#define SC_TOP_LEFT 0x16EC +#define SC_BOTTOM_RIGHT 0x16F0 +#define SRC_SC_BOTTOM_RIGHT 0x16F4 +#define RB2D_DSTCACHE_MODE 0x3428 +#define RB2D_DSTCACHE_CTLSTAT 0x342C +#define LVDS_GEN_CNTL 0x02d0 +#define LVDS_PLL_CNTL 0x02d4 +#define FP2_GEN_CNTL 0x0288 +#define TMDS_CNTL 0x0294 +#define TMDS_CRC 0x02a0 +#define TMDS_TRANSMITTER_CNTL 0x02a4 +#define MPP_TB_CONFIG 0x01c0 +#define PAMAC0_DLY_CNTL 0x0a94 +#define PAMAC1_DLY_CNTL 0x0a98 +#define PAMAC2_DLY_CNTL 0x0a9c +#define FW_CNTL 0x0118 +#define FCP_CNTL 0x0910 +#define VGA_DDA_ON_OFF 0x02ec +#define TV_MASTER_CNTL 0x0800 + +//#define BASE_CODE 0x0f0b +#define BIOS_0_SCRATCH 0x0010 +#define BIOS_1_SCRATCH 0x0014 +#define BIOS_2_SCRATCH 0x0018 +#define BIOS_3_SCRATCH 0x001c +#define BIOS_4_SCRATCH 0x0020 +#define BIOS_5_SCRATCH 0x0024 +#define BIOS_6_SCRATCH 0x0028 +#define BIOS_7_SCRATCH 0x002c + +#define HDP_SOFT_RESET (1 << 26) + +#define TV_DAC_CNTL 0x088c +#define GPIOPAD_MASK 0x0198 +#define GPIOPAD_A 0x019c +#define GPIOPAD_EN 0x01a0 +#define GPIOPAD_Y 0x01a4 +#define ZV_LCDPAD_MASK 0x01a8 +#define ZV_LCDPAD_A 0x01ac +#define ZV_LCDPAD_EN 0x01b0 +#define ZV_LCDPAD_Y 0x01b4 + +/* PLL Registers */ +#define CLK_PIN_CNTL 0x0001 +#define PPLL_CNTL 0x0002 +#define PPLL_REF_DIV 0x0003 +#define PPLL_DIV_0 0x0004 +#define PPLL_DIV_1 0x0005 +#define PPLL_DIV_2 0x0006 +#define PPLL_DIV_3 0x0007 +#define VCLK_ECP_CNTL 0x0008 +#define HTOTAL_CNTL 0x0009 +#define M_SPLL_REF_FB_DIV 0x000a +#define AGP_PLL_CNTL 0x000b +#define SPLL_CNTL 0x000c +#define SCLK_CNTL 0x000d +#define MPLL_CNTL 0x000e +#define MDLL_CKO 0x000f +#define MDLL_RDCKA 0x0010 +#define MCLK_CNTL 0x0012 +#define AGP_PLL_CNTL 0x000b +#define PLL_TEST_CNTL 0x0013 +#define CLK_PWRMGT_CNTL 0x0014 +#define PLL_PWRMGT_CNTL 0x0015 +#define MCLK_MISC 0x001f +#define P2PLL_CNTL 0x002a +#define P2PLL_REF_DIV 0x002b +#define PIXCLKS_CNTL 0x002d +#define SCLK_MORE_CNTL 0x0035 + +/* MCLK_CNTL bit constants */ +#define FORCEON_MCLKA (1 << 16) +#define FORCEON_MCLKB (1 << 17) +#define FORCEON_YCLKA (1 << 18) +#define FORCEON_YCLKB (1 << 19) +#define FORCEON_MC (1 << 20) +#define FORCEON_AIC (1 << 21) + +/* SCLK_CNTL bit constants */ +#define DYN_STOP_LAT_MASK 0x00007ff8 +#define CP_MAX_DYN_STOP_LAT 0x0008 +#define SCLK_FORCEON_MASK 0xffff8000 + +/* SCLK_MORE_CNTL bit constants */ +#define SCLK_MORE_FORCEON 0x0700 + +/* BUS_CNTL bit constants */ +#define BUS_DBL_RESYNC 0x00000001 +#define BUS_MSTR_RESET 0x00000002 +#define BUS_FLUSH_BUF 0x00000004 +#define BUS_STOP_REQ_DIS 0x00000008 +#define BUS_ROTATION_DIS 0x00000010 +#define BUS_MASTER_DIS 0x00000040 +#define BUS_ROM_WRT_EN 0x00000080 +#define BUS_DIS_ROM 0x00001000 +#define BUS_PCI_READ_RETRY_EN 0x00002000 +#define BUS_AGP_AD_STEPPING_EN 0x00004000 +#define BUS_PCI_WRT_RETRY_EN 0x00008000 +#define BUS_MSTR_RD_MULT 0x00100000 +#define BUS_MSTR_RD_LINE 0x00200000 +#define BUS_SUSPEND 0x00400000 +#define LAT_16X 0x00800000 +#define BUS_RD_DISCARD_EN 0x01000000 +#define BUS_RD_ABORT_EN 0x02000000 +#define BUS_MSTR_WS 0x04000000 +#define BUS_PARKING_DIS 0x08000000 +#define BUS_MSTR_DISCONNECT_EN 0x10000000 +#define BUS_WRT_BURST 0x20000000 +#define BUS_READ_BURST 0x40000000 +#define BUS_RDY_READ_DLY 0x80000000 + +/* PIXCLKS_CNTL */ +#define PIX2CLK_SRC_SEL_MASK 0x03 +#define PIX2CLK_SRC_SEL_CPUCLK 0x00 +#define PIX2CLK_SRC_SEL_PSCANCLK 0x01 +#define PIX2CLK_SRC_SEL_BYTECLK 0x02 +#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 +#define PIX2CLK_ALWAYS_ONb (1<<6) +#define PIX2CLK_DAC_ALWAYS_ONb (1<<7) +#define PIXCLK_TV_SRC_SEL (1 << 8) +#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) +#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) + + +/* CLOCK_CNTL_INDEX bit constants */ +#define PLL_WR_EN 0x00000080 + +/* CONFIG_CNTL bit constants */ +#define CFG_VGA_RAM_EN 0x00000100 +#define CFG_ATI_REV_ID_MASK (0xf << 16) +#define CFG_ATI_REV_A11 (0 << 16) +#define CFG_ATI_REV_A12 (1 << 16) +#define CFG_ATI_REV_A13 (2 << 16) + +/* CRTC_EXT_CNTL bit constants */ +#define VGA_ATI_LINEAR 0x00000008 +#define VGA_128KAP_PAGING 0x00000010 +#define XCRT_CNT_EN (1 << 6) +#define CRTC_HSYNC_DIS (1 << 8) +#define CRTC_VSYNC_DIS (1 << 9) +#define CRTC_DISPLAY_DIS (1 << 10) +#define CRTC_CRT_ON (1 << 15) + + +/* DSTCACHE_CTLSTAT bit constants */ +#define RB2D_DC_FLUSH (3 << 0) +#define RB2D_DC_FLUSH_ALL 0xf +#define RB2D_DC_BUSY (1 << 31) + + +/* CRTC_GEN_CNTL bit constants */ +#define CRTC_DBL_SCAN_EN 0x00000001 +#define CRTC_CUR_EN 0x00010000 +#define CRTC_INTERLACE_EN (1 << 1) +#define CRTC_BYPASS_LUT_EN (1 << 14) +#define CRTC_EXT_DISP_EN (1 << 24) +#define CRTC_EN (1 << 25) +#define CRTC_DISP_REQ_EN_B (1 << 26) + +/* CRTC_STATUS bit constants */ +#define CRTC_VBLANK 0x00000001 + +/* CRTC2_GEN_CNTL bit constants */ +#define CRT2_ON (1 << 7) +#define CRTC2_DISPLAY_DIS (1 << 23) +#define CRTC2_EN (1 << 25) +#define CRTC2_DISP_REQ_EN_B (1 << 26) + +/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ +#define CUR_LOCK 0x80000000 + +/* GPIO bit constants */ +#define GPIO_A_0 (1 << 0) +#define GPIO_A_1 (1 << 1) +#define GPIO_Y_0 (1 << 8) +#define GPIO_Y_1 (1 << 9) +#define GPIO_EN_0 (1 << 16) +#define GPIO_EN_1 (1 << 17) +#define GPIO_MASK_0 (1 << 24) +#define GPIO_MASK_1 (1 << 25) +#define VGA_DDC_DATA_OUTPUT GPIO_A_0 +#define VGA_DDC_CLK_OUTPUT GPIO_A_1 +#define VGA_DDC_DATA_INPUT GPIO_Y_0 +#define VGA_DDC_CLK_INPUT GPIO_Y_1 +#define VGA_DDC_DATA_OUT_EN GPIO_EN_0 +#define VGA_DDC_CLK_OUT_EN GPIO_EN_1 + + +/* FP bit constants */ +#define FP_CRTC_H_TOTAL_MASK 0x000003ff +#define FP_CRTC_H_DISP_MASK 0x01ff0000 +#define FP_CRTC_V_TOTAL_MASK 0x00000fff +#define FP_CRTC_V_DISP_MASK 0x0fff0000 +#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +#define FP_H_SYNC_WID_MASK 0x003f0000 +#define FP_V_SYNC_STRT_MASK 0x00000fff +#define FP_V_SYNC_WID_MASK 0x001f0000 +#define FP_CRTC_H_TOTAL_SHIFT 0x00000000 +#define FP_CRTC_H_DISP_SHIFT 0x00000010 +#define FP_CRTC_V_TOTAL_SHIFT 0x00000000 +#define FP_CRTC_V_DISP_SHIFT 0x00000010 +#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +#define FP_H_SYNC_WID_SHIFT 0x00000010 +#define FP_V_SYNC_STRT_SHIFT 0x00000000 +#define FP_V_SYNC_WID_SHIFT 0x00000010 + +/* FP_GEN_CNTL bit constants */ +#define FP_FPON (1 << 0) +#define FP_TMDS_EN (1 << 2) +#define FP_PANEL_FORMAT (1 << 3) +#define FP_EN_TMDS (1 << 7) +#define FP_DETECT_SENSE (1 << 8) +#define R200_FP_SOURCE_SEL_MASK (3 << 10) +#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) +#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) +#define R200_FP_SOURCE_SEL_RMX (2 << 10) +#define R200_FP_SOURCE_SEL_TRANS (3 << 10) +#define FP_SEL_CRTC1 (0 << 13) +#define FP_SEL_CRTC2 (1 << 13) +#define FP_USE_VGA_HSYNC (1 << 14) +#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +#define FP_CRTC_DONT_SHADOW_HEND (1 << 17) +#define FP_CRTC_USE_SHADOW_VEND (1 << 18) +#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +#define FP_DFP_SYNC_SEL (1 << 21) +#define FP_CRTC_LOCK_8DOT (1 << 22) +#define FP_CRT_SYNC_SEL (1 << 23) +#define FP_USE_SHADOW_EN (1 << 24) +#define FP_CRT_SYNC_ALT (1 << 26) + +/* FP2_GEN_CNTL bit constants */ +#define FP2_BLANK_EN (1 << 1) +#define FP2_ON (1 << 2) +#define FP2_PANEL_FORMAT (1 << 3) +#define FP2_SOURCE_SEL_MASK (3 << 10) +#define FP2_SOURCE_SEL_CRTC2 (1 << 10) +#define FP2_SRC_SEL_MASK (3 << 13) +#define FP2_SRC_SEL_CRTC2 (1 << 13) +#define FP2_FP_POL (1 << 16) +#define FP2_LP_POL (1 << 17) +#define FP2_SCK_POL (1 << 18) +#define FP2_LCD_CNTL_MASK (7 << 19) +#define FP2_PAD_FLOP_EN (1 << 22) +#define FP2_CRC_EN (1 << 23) +#define FP2_CRC_READ_EN (1 << 24) +#define FP2_DV0_EN (1 << 25) +#define FP2_DV0_RATE_SEL_SDR (1 << 26) + + +/* LVDS_GEN_CNTL bit constants */ +#define LVDS_ON (1 << 0) +#define LVDS_DISPLAY_DIS (1 << 1) +#define LVDS_PANEL_TYPE (1 << 2) +#define LVDS_PANEL_FORMAT (1 << 3) +#define LVDS_EN (1 << 7) +#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 +#define LVDS_BL_MOD_LEVEL_SHIFT 8 +#define LVDS_BL_MOD_EN (1 << 16) +#define LVDS_DIGON (1 << 18) +#define LVDS_BLON (1 << 19) +#define LVDS_SEL_CRTC2 (1 << 23) +#define LVDS_STATE_MASK \ + (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON) + +/* LVDS_PLL_CNTL bit constatns */ +#define HSYNC_DELAY_SHIFT 0x1c +#define HSYNC_DELAY_MASK (0xf << 0x1c) + +/* TMDS_TRANSMITTER_CNTL bit constants */ +#define TMDS_PLL_EN (1 << 0) +#define TMDS_PLLRST (1 << 1) +#define TMDS_RAN_PAT_RST (1 << 7) +#define TMDS_ICHCSEL (1 << 28) + +/* FP_HORZ_STRETCH bit constants */ +#define HORZ_STRETCH_RATIO_MASK 0xffff +#define HORZ_STRETCH_RATIO_MAX 4096 +#define HORZ_PANEL_SIZE (0x1ff << 16) +#define HORZ_PANEL_SHIFT 16 +#define HORZ_STRETCH_PIXREP (0 << 25) +#define HORZ_STRETCH_BLEND (1 << 26) +#define HORZ_STRETCH_ENABLE (1 << 25) +#define HORZ_AUTO_RATIO (1 << 27) +#define HORZ_FP_LOOP_STRETCH (0x7 << 28) +#define HORZ_AUTO_RATIO_INC (1 << 31) + + +/* FP_VERT_STRETCH bit constants */ +#define VERT_STRETCH_RATIO_MASK 0xfff +#define VERT_STRETCH_RATIO_MAX 4096 +#define VERT_PANEL_SIZE (0xfff << 12) +#define VERT_PANEL_SHIFT 12 +#define VERT_STRETCH_LINREP (0 << 26) +#define VERT_STRETCH_BLEND (1 << 26) +#define VERT_STRETCH_ENABLE (1 << 25) +#define VERT_AUTO_RATIO_EN (1 << 27) +#define VERT_FP_LOOP_STRETCH (0x7 << 28) +#define VERT_STRETCH_RESERVED 0xf1000000 + +/* DAC_CNTL bit constants */ +#define DAC_8BIT_EN 0x00000100 +#define DAC_4BPP_PIX_ORDER 0x00000200 +#define DAC_CRC_EN 0x00080000 +#define DAC_MASK_ALL (0xff << 24) +#define DAC_PDWN (1 << 15) +#define DAC_EXPAND_MODE (1 << 14) +#define DAC_VGA_ADR_EN (1 << 13) +#define DAC_RANGE_CNTL (3 << 0) +#define DAC_RANGE_CNTL_MASK 0x03 +#define DAC_BLANKING (1 << 2) +#define DAC_CMP_EN (1 << 3) +#define DAC_CMP_OUTPUT (1 << 7) + +/* DAC_CNTL2 bit constants */ +#define DAC2_EXPAND_MODE (1 << 14) +#define DAC2_CMP_EN (1 << 7) +#define DAC2_PALETTE_ACCESS_CNTL (1 << 5) + +/* DAC_EXT_CNTL bit constants */ +#define DAC_FORCE_BLANK_OFF_EN (1 << 4) +#define DAC_FORCE_DATA_EN (1 << 5) +#define DAC_FORCE_DATA_SEL_MASK (3 << 6) +#define DAC_FORCE_DATA_MASK 0x0003ff00 +#define DAC_FORCE_DATA_SHIFT 8 + +/* GEN_RESET_CNTL bit constants */ +#define SOFT_RESET_GUI 0x00000001 +#define SOFT_RESET_VCLK 0x00000100 +#define SOFT_RESET_PCLK 0x00000200 +#define SOFT_RESET_ECP 0x00000400 +#define SOFT_RESET_DISPENG_XCLK 0x00000800 + +/* MEM_CNTL bit constants */ +#define MEM_CTLR_STATUS_IDLE 0x00000000 +#define MEM_CTLR_STATUS_BUSY 0x00100000 +#define MEM_SEQNCR_STATUS_IDLE 0x00000000 +#define MEM_SEQNCR_STATUS_BUSY 0x00200000 +#define MEM_ARBITER_STATUS_IDLE 0x00000000 +#define MEM_ARBITER_STATUS_BUSY 0x00400000 +#define MEM_REQ_UNLOCK 0x00000000 +#define MEM_REQ_LOCK 0x00800000 +#define MEM_NUM_CHANNELS_MASK 0x00000001 +#define MEM_USE_B_CH_ONLY 0x00000002 +#define RV100_MEM_HALF_MODE 0x00000008 +#define R300_MEM_NUM_CHANNELS_MASK 0x00000003 +#define R300_MEM_USE_CD_CH_ONLY 0x00000004 + + +/* RBBM_SOFT_RESET bit constants */ +#define SOFT_RESET_CP (1 << 0) +#define SOFT_RESET_HI (1 << 1) +#define SOFT_RESET_SE (1 << 2) +#define SOFT_RESET_RE (1 << 3) +#define SOFT_RESET_PP (1 << 4) +#define SOFT_RESET_E2 (1 << 5) +#define SOFT_RESET_RB (1 << 6) +#define SOFT_RESET_HDP (1 << 7) + +/* SURFACE_CNTL bit consants */ +#define SURF_TRANSLATION_DIS (1 << 8) +#define NONSURF_AP0_SWP_16BPP (1 << 20) +#define NONSURF_AP0_SWP_32BPP (1 << 21) +#define NONSURF_AP1_SWP_16BPP (1 << 22) +#define NONSURF_AP1_SWP_32BPP (1 << 23) + +/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ +#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) + +/* MM_INDEX bit constants */ +#define MM_APER 0x80000000 + +/* CLR_CMP_CNTL bit constants */ +#define COMPARE_SRC_FALSE 0x00000000 +#define COMPARE_SRC_TRUE 0x00000001 +#define COMPARE_SRC_NOT_EQUAL 0x00000004 +#define COMPARE_SRC_EQUAL 0x00000005 +#define COMPARE_SRC_EQUAL_FLIP 0x00000007 +#define COMPARE_DST_FALSE 0x00000000 +#define COMPARE_DST_TRUE 0x00000100 +#define COMPARE_DST_NOT_EQUAL 0x00000400 +#define COMPARE_DST_EQUAL 0x00000500 +#define COMPARE_DESTINATION 0x00000000 +#define COMPARE_SOURCE 0x01000000 +#define COMPARE_SRC_AND_DST 0x02000000 + + +/* DP_CNTL bit constants */ +#define DST_X_RIGHT_TO_LEFT 0x00000000 +#define DST_X_LEFT_TO_RIGHT 0x00000001 +#define DST_Y_BOTTOM_TO_TOP 0x00000000 +#define DST_Y_TOP_TO_BOTTOM 0x00000002 +#define DST_X_MAJOR 0x00000000 +#define DST_Y_MAJOR 0x00000004 +#define DST_X_TILE 0x00000008 +#define DST_Y_TILE 0x00000010 +#define DST_LAST_PEL 0x00000020 +#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 +#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 +#define DST_BRES_SIGN 0x00000100 +#define DST_HOST_BIG_ENDIAN_EN 0x00000200 +#define DST_POLYLINE_NONLAST 0x00008000 +#define DST_RASTER_STALL 0x00010000 +#define DST_POLY_EDGE 0x00040000 + + +/* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ +#define DST_X_MAJOR_S 0x00000000 +#define DST_Y_MAJOR_S 0x00000001 +#define DST_Y_BOTTOM_TO_TOP_S 0x00000000 +#define DST_Y_TOP_TO_BOTTOM_S 0x00008000 +#define DST_X_RIGHT_TO_LEFT_S 0x00000000 +#define DST_X_LEFT_TO_RIGHT_S 0x80000000 + + +/* DP_DATATYPE bit constants */ +#define DST_8BPP 0x00000002 +#define DST_15BPP 0x00000003 +#define DST_16BPP 0x00000004 +#define DST_24BPP 0x00000005 +#define DST_32BPP 0x00000006 +#define DST_8BPP_RGB332 0x00000007 +#define DST_8BPP_Y8 0x00000008 +#define DST_8BPP_RGB8 0x00000009 +#define DST_16BPP_VYUY422 0x0000000b +#define DST_16BPP_YVYU422 0x0000000c +#define DST_32BPP_AYUV444 0x0000000e +#define DST_16BPP_ARGB4444 0x0000000f +#define BRUSH_SOLIDCOLOR 0x00000d00 +#define SRC_MONO 0x00000000 +#define SRC_MONO_LBKGD 0x00010000 +#define SRC_DSTCOLOR 0x00030000 +#define BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define BYTE_ORDER_LSB_TO_MSB 0x40000000 +#define DP_CONVERSION_TEMP 0x80000000 +#define HOST_BIG_ENDIAN_EN (1 << 29) + + +/* DP_GUI_MASTER_CNTL bit constants */ +#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 +#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 +#define GMC_SRC_CLIP_DEFAULT 0x00000000 +#define GMC_SRC_CLIP_LEAVE 0x00000004 +#define GMC_DST_CLIP_DEFAULT 0x00000000 +#define GMC_DST_CLIP_LEAVE 0x00000008 +#define GMC_BRUSH_8x8MONO 0x00000000 +#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 +#define GMC_BRUSH_8x1MONO 0x00000020 +#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 +#define GMC_BRUSH_1x8MONO 0x00000040 +#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 +#define GMC_BRUSH_32x1MONO 0x00000060 +#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 +#define GMC_BRUSH_32x32MONO 0x00000080 +#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 +#define GMC_BRUSH_8x8COLOR 0x000000a0 +#define GMC_BRUSH_8x1COLOR 0x000000b0 +#define GMC_BRUSH_1x8COLOR 0x000000c0 +#define GMC_BRUSH_SOLID_COLOR 0x000000d0 +#define GMC_DST_8BPP 0x00000200 +#define GMC_DST_15BPP 0x00000300 +#define GMC_DST_16BPP 0x00000400 +#define GMC_DST_24BPP 0x00000500 +#define GMC_DST_32BPP 0x00000600 +#define GMC_DST_8BPP_RGB332 0x00000700 +#define GMC_DST_8BPP_Y8 0x00000800 +#define GMC_DST_8BPP_RGB8 0x00000900 +#define GMC_DST_16BPP_VYUY422 0x00000b00 +#define GMC_DST_16BPP_YVYU422 0x00000c00 +#define GMC_DST_32BPP_AYUV444 0x00000e00 +#define GMC_DST_16BPP_ARGB4444 0x00000f00 +#define GMC_SRC_MONO 0x00000000 +#define GMC_SRC_MONO_LBKGD 0x00001000 +#define GMC_SRC_DSTCOLOR 0x00003000 +#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 +#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 +#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 +#define GMC_DP_SRC_RECT 0x02000000 +#define GMC_DP_SRC_HOST 0x03000000 +#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 +#define GMC_3D_FCN_EN_CLR 0x00000000 +#define GMC_3D_FCN_EN_SET 0x08000000 +#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 +#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 +#define GMC_AUX_CLIP_LEAVE 0x00000000 +#define GMC_AUX_CLIP_CLEAR 0x20000000 +#define GMC_WRITE_MASK_LEAVE 0x00000000 +#define GMC_WRITE_MASK_SET 0x40000000 +#define GMC_CLR_CMP_CNTL_DIS (1 << 28) +#define GMC_SRC_DATATYPE_COLOR (3 << 12) +#define ROP3_S 0x00cc0000 +#define ROP3_SRCCOPY 0x00cc0000 +#define ROP3_P 0x00f00000 +#define ROP3_PATCOPY 0x00f00000 +#define DP_SRC_SOURCE_MASK (7 << 24) +#define GMC_BRUSH_NONE (15 << 4) +#define DP_SRC_SOURCE_MEMORY (2 << 24) +#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 + +/* DP_MIX bit constants */ +#define DP_SRC_RECT 0x00000200 +#define DP_SRC_HOST 0x00000300 +#define DP_SRC_HOST_BYTEALIGN 0x00000400 + +/* MPLL_CNTL bit constants */ +#define MPLL_RESET 0x00000001 + +/* MDLL_CKO bit constants */ +#define MCKOA_SLEEP 0x00000001 +#define MCKOA_RESET 0x00000002 +#define MCKOA_REF_SKEW_MASK 0x00000700 +#define MCKOA_FB_SKEW_MASK 0x00007000 + +/* MDLL_RDCKA bit constants */ +#define MRDCKA0_SLEEP 0x00000001 +#define MRDCKA0_RESET 0x00000002 +#define MRDCKA1_SLEEP 0x00010000 +#define MRDCKA1_RESET 0x00020000 + +/* VCLK_ECP_CNTL constants */ +#define VCLK_SRC_SEL_MASK 0x03 +#define VCLK_SRC_SEL_CPUCLK 0x00 +#define VCLK_SRC_SEL_PSCANCLK 0x01 +#define VCLK_SRC_SEL_BYTECLK 0x02 +#define VCLK_SRC_SEL_PPLLCLK 0x03 +#define PIXCLK_ALWAYS_ONb 0x00000040 +#define PIXCLK_DAC_ALWAYS_ONb 0x00000080 + +/* BUS_CNTL1 constants */ +#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 +#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 +#define BUS_CNTL1_AGPCLK_VALID 0x80000000 + +/* PLL_PWRMGT_CNTL constants */ +#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 +#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 +#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 +#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 +#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 +#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 +#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 + +/* TV_DAC_CNTL constants */ +#define TV_DAC_CNTL_BGSLEEP 0x00000040 +#define TV_DAC_CNTL_DETECT 0x00000010 +#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 +#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 +#define TV_DAC_CNTL_BGADJ__SHIFT 16 +#define TV_DAC_CNTL_DACADJ__SHIFT 20 +#define TV_DAC_CNTL_RDACPD 0x01000000 +#define TV_DAC_CNTL_GDACPD 0x02000000 +#define TV_DAC_CNTL_BDACPD 0x04000000 + +/* DISP_MISC_CNTL constants */ +#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) +#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) +#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) +#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) +#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) +#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) +#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) +#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) +#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) + +/* DISP_PWR_MAN constants */ +#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) +#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) +#define DISP_PWR_MAN_DISP_D3_RST (1 << 16) +#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) +#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) +#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) +#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) +#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) +#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) +#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) +#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) +#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) +#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) + +/* masks */ + +#define CONFIG_MEMSIZE_MASK 0x1f000000 +#define MEM_CFG_TYPE 0x40000000 +#define DST_OFFSET_MASK 0x003fffff +#define DST_PITCH_MASK 0x3fc00000 +#define DEFAULT_TILE_MASK 0xc0000000 +#define PPLL_DIV_SEL_MASK 0x00000300 +#define PPLL_RESET 0x00000001 +#define PPLL_SLEEP 0x00000002 +#define PPLL_ATOMIC_UPDATE_EN 0x00010000 +#define PPLL_REF_DIV_MASK 0x000003ff +#define PPLL_FB3_DIV_MASK 0x000007ff +#define PPLL_POST3_DIV_MASK 0x00070000 +#define PPLL_ATOMIC_UPDATE_R 0x00008000 +#define PPLL_ATOMIC_UPDATE_W 0x00008000 +#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 +#define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) +#define R300_PPLL_REF_DIV_ACC_SHIFT 18 + +#define GUI_ACTIVE 0x80000000 + + +#define MC_IND_INDEX 0x01F8 +#define MC_IND_DATA 0x01FC + +/* PAD_CTLR_STRENGTH */ +#define PAD_MANUAL_OVERRIDE 0x80000000 + +// pllCLK_PIN_CNTL +#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L +#define CLK_PIN_CNTL__OSC_EN 0x00000001L +#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L +#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L +#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L +#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L +#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L +#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L +#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L +#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L +#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L +#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L +#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L +#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L +#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L +#define CLK_PIN_CNTL__CG_SPARE 0x00004000L +#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L +#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L +#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L +#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L +#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L +#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L +#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L +#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L + +// pllCLK_PWRMGT_CNTL +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004 +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005 +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006 +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007 +#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008 +#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009 +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c +#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f +#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010 +#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011 +#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012 +#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013 +#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014 +#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015 +#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018 +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f + +// pllP2PLL_CNTL +#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L +#define P2PLL_CNTL__P2PLL_RESET 0x00000001L +#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L +#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L +#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L +#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L +#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L +#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L +#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L +#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L +#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L +#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L +#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L +#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L +#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L +#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L +#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L +#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L +#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L + +// pllPIXCLKS_CNTL +#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 +#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 +#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 +#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 +#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 +#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 +#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b +#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c +#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d +#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e +#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f + + +// pllPIXCLKS_CNTL +#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L +#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L +#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L +#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L +#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L +#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L +#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L +#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L +#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L +#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L +#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L +#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) +#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) +#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) +#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) +#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) +#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) +#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) +#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) + + +// pllP2PLL_DIV_0 +#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L +#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L + +// pllSCLK_CNTL +#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L +#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L +#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L +#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L +#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L +#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L +#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L +#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L +#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L +#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L +#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L +#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L +#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L +#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8 +#define SCLK_CNTL__FORCE_DISP2 0x00008000L +#define SCLK_CNTL__FORCE_CP 0x00010000L +#define SCLK_CNTL__FORCE_HDP 0x00020000L +#define SCLK_CNTL__FORCE_DISP1 0x00040000L +#define SCLK_CNTL__FORCE_TOP 0x00080000L +#define SCLK_CNTL__FORCE_E2 0x00100000L +#define SCLK_CNTL__FORCE_SE 0x00200000L +#define SCLK_CNTL__FORCE_IDCT 0x00400000L +#define SCLK_CNTL__FORCE_VIP 0x00800000L +#define SCLK_CNTL__FORCE_RE 0x01000000L +#define SCLK_CNTL__FORCE_PB 0x02000000L +#define SCLK_CNTL__FORCE_TAM 0x04000000L +#define SCLK_CNTL__FORCE_TDM 0x08000000L +#define SCLK_CNTL__FORCE_RB 0x10000000L +#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L +#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L +#define SCLK_CNTL__FORCE_OV0 0x80000000L +#define SCLK_CNTL__R300_FORCE_VAP (1<<21) +#define SCLK_CNTL__R300_FORCE_SR (1<<25) +#define SCLK_CNTL__R300_FORCE_PX (1<<26) +#define SCLK_CNTL__R300_FORCE_TX (1<<27) +#define SCLK_CNTL__R300_FORCE_US (1<<28) +#define SCLK_CNTL__R300_FORCE_SU (1<<30) +#define SCLK_CNTL__FORCEON_MASK 0xffff8000L + +// pllSCLK_CNTL2 +#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) +#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) +#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) +#define SCLK_CNTL2__R300_FORCE_TCL (1<<13) +#define SCLK_CNTL2__R300_FORCE_CBA (1<<14) +#define SCLK_CNTL2__R300_FORCE_GA (1<<15) + +// SCLK_MORE_CNTL +#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L +#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L +#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L +#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L +#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L +#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L +#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L +#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L +#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L +#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L +#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L +#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L +#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L +#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L +#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L +#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L +#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L +#define SCLK_MORE_CNTL__FORCEON 0x00000700L + +// MCLK_CNTL +#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L +#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L +#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L +#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L +#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L +#define MCLK_CNTL__FORCE_MCLKA 0x00010000L +#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L +#define MCLK_CNTL__FORCE_MCLKB 0x00020000L +#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L +#define MCLK_CNTL__FORCE_YCLKA 0x00040000L +#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L +#define MCLK_CNTL__FORCE_YCLKB 0x00080000L +#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L +#define MCLK_CNTL__FORCE_MC 0x00100000L +#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L +#define MCLK_CNTL__FORCE_AIC 0x00200000L +#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L +#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L +#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L +#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L +#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) +#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) + +// MCLK_MISC +#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L +#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L +#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L +#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L +#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L +#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L +#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L +#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L +#define MCLK_MISC__DLL_READY_LAT 0x00000100L +#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L +#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L +#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L +#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L +#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L +#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L +#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L +#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L +#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L +#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L +#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L +#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L +#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L +#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L +#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L +#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L +#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L +#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L +#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L + +// VCLK_ECP_CNTL +#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L +#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L +#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L +#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L +#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L +#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L +#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L +#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L +#define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) + +// PLL_PWRMGT_CNTL +#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L +#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L +#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L +#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L +#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L +#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L +#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L +#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L +#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L +#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L +#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L +#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L +#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L +#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L +#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L +#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L +#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L +#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L +#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L +#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L +#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L +#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L +#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L +#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L +#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L +#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L +#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L +#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L +#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L +#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L +#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L +#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L + +// CLK_PWRMGT_CNTL +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L +#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L +#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L +#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L +#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L +#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L +#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L +#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L +#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L +#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L +#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L +#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L +#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L +#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L +#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L +#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L +#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L +#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L + +// BUS_CNTL1 +#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L +#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L +#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L +#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L +#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L +#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L +#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L +#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L +#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L +#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L +#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L +#define BUS_CNTL1__AGPCLK_VALID 0x80000000L + +// BUS_CNTL1 +#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 +#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 +#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 +#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b +#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a +#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c +#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f + +// CRTC_OFFSET_CNTL +#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL +#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L + +// CRTC_GEN_CNTL +#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L +#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L +#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L +#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L +#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L +#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L +#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L +#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L +#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L +#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L +#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L +#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L +#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L +#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L +#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L +#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L +#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L +#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L +#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L + +// CRTC2_GEN_CNTL +#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L +#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L +#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L +#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L +#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L +#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L +#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L +#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L +#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L +#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L +#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L +#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L +#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L +#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L +#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L +#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L +#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L +#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L +#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L + +// AGP_CNTL +#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL +#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L +#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L +#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L +#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L +#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L +#define AGP_CNTL__EN_2X_STBB 0x00000400L +#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L +#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L +#define AGP_CNTL__SBA_DIS_MASK 0x00001000L +#define AGP_CNTL__SBA_DIS 0x00001000L +#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L +#define AGP_CNTL__AGP_REV_ID 0x00002000L +#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L +#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L +#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L +#define AGP_CNTL__FORCE_INT_VREF 0x00010000L +#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L +#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L +#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L +#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L +#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L +#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L +#define AGP_CNTL__EN_RBFCALM 0x00800000L +#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L +#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L +#define AGP_CNTL__DIS_RBF_MASK 0x02000000L +#define AGP_CNTL__DIS_RBF 0x02000000L +#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L +#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L +#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L +#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L + +// AGP_CNTL +#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 +#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 +#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 +#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a +#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b +#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c +#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d +#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f +#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 +#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 +#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 +#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 +#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 +#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 +#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 +#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a +#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b +#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e + +// DISP_MISC_CNTL +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L +#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L +#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L +#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L +#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L +#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L +#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L +#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L +#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L +#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L +#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L +#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L +#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L +#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L +#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L + +// DISP_PWR_MAN +#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L +#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L +#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L +#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L +#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L +#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L +#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L +#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L +#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L +#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L +#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L +#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L +#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L +#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L +#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L +#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L +#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L +#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L +#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L +#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L +#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L +#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L +#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L +#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L +#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L +#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L +#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L + +// MC_IND_INDEX +#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL +#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L +#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L + +// MC_IND_DATA +#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL + +// MC_CHP_IO_CNTL_A1 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a +#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c +#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e +#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 +#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f + +// MC_CHP_IO_CNTL_B1 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a +#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c +#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e +#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 +#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f + +// MC_CHP_IO_CNTL_A1 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L +#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L + +// MC_CHP_IO_CNTL_B1 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L +#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L + +// MEM_SDRAM_MODE_REG +#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL +#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L +#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L + +// MEM_SDRAM_MODE_REG +#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 +#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 +#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f + +// MEM_REFRESH_CNTL +#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL +#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L +#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L +#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L +#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L +#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L +#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L +#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L +#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L +#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L +#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L +#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L +#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L +#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L +#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L +#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L +#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L +#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L +#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L +#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L +#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L + +// MC_STATUS +#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L +#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L +#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L +#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L +#define MC_STATUS__MC_IDLE_MASK 0x00000004L +#define MC_STATUS__MC_IDLE 0x00000004L +#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L +#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L +#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L +#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L +#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L +#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L +#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L +#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L +#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L +#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L + +// MDLL_CKO +#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L +#define MDLL_CKO__MCKOA_SLEEP 0x00000001L +#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L +#define MDLL_CKO__MCKOA_RESET 0x00000002L +#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL +#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L +#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L +#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L +#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L +#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L +#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L +#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L +#define MDLL_CKO__MCKOB_SLEEP 0x00010000L +#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L +#define MDLL_CKO__MCKOB_RESET 0x00020000L +#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L +#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L +#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L +#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L +#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L +#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L +#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L + +// MDLL_RDCKA +#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L +#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L +#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L +#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L +#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL +#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L +#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L +#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L +#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L +#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L +#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L +#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L +#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L +#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L +#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L +#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L +#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L +#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L +#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L +#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L +#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L +#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L +#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L +#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L +#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L +#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L + +// MDLL_RDCKB +#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L +#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L +#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L +#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L +#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL +#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L +#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L +#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L +#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L +#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L +#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L +#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L +#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L +#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L +#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L +#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L +#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L +#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L +#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L +#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L +#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L +#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L +#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L +#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L +#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L +#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L + +#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L +#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L +#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L +#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L +#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L +#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L +#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L +#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L + +#define pllCLK_PIN_CNTL 0x0001 +#define pllPPLL_CNTL 0x0002 +#define pllPPLL_REF_DIV 0x0003 +#define pllPPLL_DIV_0 0x0004 +#define pllPPLL_DIV_1 0x0005 +#define pllPPLL_DIV_2 0x0006 +#define pllPPLL_DIV_3 0x0007 +#define pllVCLK_ECP_CNTL 0x0008 +#define pllHTOTAL_CNTL 0x0009 +#define pllM_SPLL_REF_FB_DIV 0x000A +#define pllAGP_PLL_CNTL 0x000B +#define pllSPLL_CNTL 0x000C +#define pllSCLK_CNTL 0x000D +#define pllMPLL_CNTL 0x000E +#define pllMDLL_CKO 0x000F +#define pllMDLL_RDCKA 0x0010 +#define pllMDLL_RDCKB 0x0011 +#define pllMCLK_CNTL 0x0012 +#define pllPLL_TEST_CNTL 0x0013 +#define pllCLK_PWRMGT_CNTL 0x0014 +#define pllPLL_PWRMGT_CNTL 0x0015 +#define pllCG_TEST_MACRO_RW_WRITE 0x0016 +#define pllCG_TEST_MACRO_RW_READ 0x0017 +#define pllCG_TEST_MACRO_RW_DATA 0x0018 +#define pllCG_TEST_MACRO_RW_CNTL 0x0019 +#define pllDISP_TEST_MACRO_RW_WRITE 0x001A +#define pllDISP_TEST_MACRO_RW_READ 0x001B +#define pllDISP_TEST_MACRO_RW_DATA 0x001C +#define pllDISP_TEST_MACRO_RW_CNTL 0x001D +#define pllSCLK_CNTL2 0x001E +#define pllMCLK_MISC 0x001F +#define pllTV_PLL_FINE_CNTL 0x0020 +#define pllTV_PLL_CNTL 0x0021 +#define pllTV_PLL_CNTL1 0x0022 +#define pllTV_DTO_INCREMENTS 0x0023 +#define pllSPLL_AUX_CNTL 0x0024 +#define pllMPLL_AUX_CNTL 0x0025 +#define pllP2PLL_CNTL 0x002A +#define pllP2PLL_REF_DIV 0x002B +#define pllP2PLL_DIV_0 0x002C +#define pllPIXCLKS_CNTL 0x002D +#define pllHTOTAL2_CNTL 0x002E +#define pllSSPLL_CNTL 0x0030 +#define pllSSPLL_REF_DIV 0x0031 +#define pllSSPLL_DIV_0 0x0032 +#define pllSS_INT_CNTL 0x0033 +#define pllSS_TST_CNTL 0x0034 +#define pllSCLK_MORE_CNTL 0x0035 + +#define ixMC_PERF_CNTL 0x0000 +#define ixMC_PERF_SEL 0x0001 +#define ixMC_PERF_REGION_0 0x0002 +#define ixMC_PERF_REGION_1 0x0003 +#define ixMC_PERF_COUNT_0 0x0004 +#define ixMC_PERF_COUNT_1 0x0005 +#define ixMC_PERF_COUNT_2 0x0006 +#define ixMC_PERF_COUNT_3 0x0007 +#define ixMC_PERF_COUNT_MEMCH_A 0x0008 +#define ixMC_PERF_COUNT_MEMCH_B 0x0009 +#define ixMC_IMP_CNTL 0x000A +#define ixMC_CHP_IO_CNTL_A0 0x000B +#define ixMC_CHP_IO_CNTL_A1 0x000C +#define ixMC_CHP_IO_CNTL_B0 0x000D +#define ixMC_CHP_IO_CNTL_B1 0x000E +#define ixMC_IMP_CNTL_0 0x000F +#define ixTC_MISMATCH_1 0x0010 +#define ixTC_MISMATCH_2 0x0011 +#define ixMC_BIST_CTRL 0x0012 +#define ixREG_COLLAR_WRITE 0x0013 +#define ixREG_COLLAR_READ 0x0014 +#define ixR300_MC_IMP_CNTL 0x0018 +#define ixR300_MC_CHP_IO_CNTL_A0 0x0019 +#define ixR300_MC_CHP_IO_CNTL_A1 0x001a +#define ixR300_MC_CHP_IO_CNTL_B0 0x001b +#define ixR300_MC_CHP_IO_CNTL_B1 0x001c +#define ixR300_MC_CHP_IO_CNTL_C0 0x001d +#define ixR300_MC_CHP_IO_CNTL_C1 0x001e +#define ixR300_MC_CHP_IO_CNTL_D0 0x001f +#define ixR300_MC_CHP_IO_CNTL_D1 0x0020 +#define ixR300_MC_IMP_CNTL_0 0x0021 +#define ixR300_MC_ELPIDA_CNTL 0x0022 +#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023 +#define ixR300_MC_READ_CNTL_CD 0x0024 +#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025 +#define ixR300_MC_DEBUG_CNTL 0x0026 +#define ixR300_MC_BIST_CNTL_0 0x0028 +#define ixR300_MC_BIST_CNTL_1 0x0029 +#define ixR300_MC_BIST_CNTL_2 0x002a +#define ixR300_MC_BIST_CNTL_3 0x002b +#define ixR300_MC_BIST_CNTL_4 0x002c +#define ixR300_MC_BIST_CNTL_5 0x002d +#define ixR300_MC_IMP_STATUS 0x002e +#define ixR300_MC_DLL_CNTL 0x002f +#define NB_TOM 0x15C + + +#endif /* _RADEON_H */ + -- cgit v1.3.1 From 0f460a1ee148b648ee242c3157650287d4296260 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Fri, 13 Jul 2007 12:14:58 +0800 Subject: Configurations for ATI video card BIOS emulator This patch add definition of the BIOS emulator and the ATI framebuffer driver for MPC8641HPCN board. Signed-off-by: Jason Jin Signed-off-by: Zhang Wei --- Makefile | 1 + board/mpc8641hpcn/u-boot.lds | 1 + include/configs/MPC8641HPCN.h | 28 +++++++++++++++++++++++++--- 3 files changed, 27 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/Makefile b/Makefile index 4fdd485fb73..20aa9c26f1a 100644 --- a/Makefile +++ b/Makefile @@ -205,6 +205,7 @@ LIBS += disk/libdisk.a LIBS += rtc/librtc.a LIBS += dtt/libdtt.a LIBS += drivers/libdrivers.a +LIBS += drivers/bios_emulator/libatibiosemu.a LIBS += drivers/nand/libnand.a LIBS += drivers/nand_legacy/libnand_legacy.a ifeq ($(CPU),mpc83xx) diff --git a/board/mpc8641hpcn/u-boot.lds b/board/mpc8641hpcn/u-boot.lds index e4792ef1998..58644648c78 100644 --- a/board/mpc8641hpcn/u-boot.lds +++ b/board/mpc8641hpcn/u-boot.lds @@ -61,6 +61,7 @@ SECTIONS lib_generic/crc32.o (.text) lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) + drivers/bios_emulator/atibios.o (.text) *(.text) *(.fixup) *(.got1) diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 5a511e53244..888af530c24 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -240,7 +240,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -344,6 +344,26 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #endif +/*PCIE video card used*/ +#define VIDEO_IO_OFFSET CFG_PCI2_IO_PHYS + +/*PCI video card used*/ +/*#define VIDEO_IO_OFFSET CFG_PCI1_IO_PHYS*/ + +/* video */ +#define CONFIG_VIDEO + +#if defined(CONFIG_VIDEO) +#define CONFIG_BIOSEMU +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_SW_CURSOR +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_ATI_RADEON_FB +#define CONFIG_VIDEO_LOGO +/*#define CONFIG_CONSOLE_CURSOR*/ +#define CFG_ISA_IO_BASE_ADDRESS CFG_PCI2_IO_PHYS +#endif + #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CONFIG_DOS_PARTITION @@ -357,6 +377,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE #endif +#define CONFIG_MPC86XX_PCI2 + #endif /* CONFIG_PCI */ #if defined(CONFIG_TSEC_ENET) @@ -471,8 +493,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) - #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000) + #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 #else #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ -- cgit v1.3.1 From 5618332409bb96f4448d1712899369fc80c0b489 Mon Sep 17 00:00:00 2001 From: Jason Jin Date: Fri, 13 Jul 2007 12:14:59 +0800 Subject: Fix some compile issues for MAI board. Signed-off-by: Jason Jin --- board/MAI/AmigaOneG3SE/AmigaOneG3SE.c | 86 +++++++++++++++++------------------ board/MAI/AmigaOneG3SE/video.c | 1 + include/configs/AmigaOneG3SE.h | 2 + 3 files changed, 46 insertions(+), 43 deletions(-) (limited to 'include') diff --git a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c index 40f41c78185..b472176635b 100644 --- a/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c +++ b/board/MAI/AmigaOneG3SE/AmigaOneG3SE.c @@ -30,49 +30,49 @@ #include "memio.h" #include "via686.h" -__asm(" .globl send_kb \n - send_kb: \n - lis r9, 0xfe00 \n - \n - li r4, 0x10 # retries \n - mtctr r4 \n - \n - idle: \n - lbz r4, 0x64(r9) \n - andi. r4, r4, 0x02 \n - bne idle \n - \n - ready: \n - stb r3, 0x60(r9) \n - \n - check: \n - lbz r4, 0x64(r9) \n - andi. r4, r4, 0x01 \n - beq check \n - \n - lbz r4, 0x60(r9) \n - cmpwi r4, 0xfa \n - beq done \n - \n - bdnz idle \n - \n - li r3, 0 \n - blr \n - \n - done: \n - li r3, 1 \n - blr \n - \n - .globl test_kb \n - test_kb: \n - mflr r10 \n - li r3, 0xed \n - bl send_kb \n - li r3, 0x01 \n - bl send_kb \n - mtlr r10 \n - blr \n -"); +__asm__(" .globl send_kb \n " + "send_kb: \n " + " lis r9, 0xfe00 \n " + " \n " + " li r4, 0x10 # retries \n " + " mtctr r4 \n " + " \n " + "idle: \n " + " lbz r4, 0x64(r9) \n " + " andi. r4, r4, 0x02 \n " + " bne idle \n " + + "ready: \n " + " stb r3, 0x60(r9) \n " + " \n " + "check: \n " + " lbz r4, 0x64(r9) \n " + " andi. r4, r4, 0x01 \n " + " beq check \n " + " \n " + " lbz r4, 0x60(r9) \n " + " cmpwi r4, 0xfa \n " + " beq done \n " + + " bdnz idle \n " + + " li r3, 0 \n " + " blr \n " + + "done: \n " + " li r3, 1 \n " + " blr \n " + + ".globl test_kb \n " + "test_kb: \n " + " mflr r10 \n " + " li r3, 0xed \n " + " bl send_kb \n " + " li r3, 0x01 \n " + " bl send_kb \n " + " mtlr r10 \n " + " blr " +); int checkboard (void) diff --git a/board/MAI/AmigaOneG3SE/video.c b/board/MAI/AmigaOneG3SE/video.c index f6327f72038..fc27c685835 100644 --- a/board/MAI/AmigaOneG3SE/video.c +++ b/board/MAI/AmigaOneG3SE/video.c @@ -56,6 +56,7 @@ int video_rows(void); int video_cols(void); char *prompt_string = "=>"; +unsigned char video_get_attr(void); void video_set_color(unsigned char attr) { diff --git a/include/configs/AmigaOneG3SE.h b/include/configs/AmigaOneG3SE.h index 661149e66b6..d914dccfbb4 100644 --- a/include/configs/AmigaOneG3SE.h +++ b/include/configs/AmigaOneG3SE.h @@ -95,6 +95,8 @@ /* #define CONFIG_PCI_SCAN_SHOW 1 */ #define CONFIG_PCI_PNP 1 /* PCI plug-and-play */ +#define atoi(x) simple_strtoul(x,NULL,10) + /* * Miscellaneous configurable options */ -- cgit v1.3.1 From 9c7e4b06214db61bb21f1bcbe57c97519669baae Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Mon, 6 Aug 2007 02:17:36 +0200 Subject: Coding style cleanup. Update CHANGELOG. Signed-off-by: Wolfgang Denk --- CHANGELOG | 61 + drivers/ati_ids.h | 1 - drivers/ati_radeon_fb.c | 6 +- drivers/ati_radeon_fb.h | 19 +- drivers/bios_emulator/atibios.c | 48 +- drivers/bios_emulator/besys.c | 243 +- drivers/bios_emulator/biosemu.c | 84 +- drivers/bios_emulator/biosemui.h | 58 +- drivers/bios_emulator/include/x86emu/debug.h | 166 +- drivers/bios_emulator/include/x86emu/prim_ops.h | 1 - drivers/bios_emulator/include/x86emu/regs.h | 148 +- drivers/bios_emulator/x86emu/decode.c | 874 +++-- drivers/bios_emulator/x86emu/ops.c | 4610 +++++++++++------------ drivers/bios_emulator/x86emu/ops2.c | 1874 ++++----- drivers/bios_emulator/x86emu/prim_ops.c | 1389 ++++--- include/radeon.h | 3686 +++++++++--------- 16 files changed, 6653 insertions(+), 6615 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 58ef66ecdc4..e07d243bf3f 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,3 +1,64 @@ +commit 221838cc7eb178370ff62aa05920a582e12ac322 +Author: Jason Jin +Date: Tue Jul 10 09:03:22 2007 +0800 + + Remove the bios emulator from MAI board. + + The bios emulator in the MAI board can not pass compile + and have a lot of crap in it. remove it and will have a + clean and small bios emulator in the drivers directory + which can be uesed for every board. + + Signed-off-by: Jason Jin + +commit 5618332409bb96f4448d1712899369fc80c0b489 +Author: Jason Jin +Date: Fri Jul 13 12:14:59 2007 +0800 + + Fix some compile issues for MAI board. + + Signed-off-by: Jason Jin + +commit 0f460a1ee148b648ee242c3157650287d4296260 +Author: Jason Jin +Date: Fri Jul 13 12:14:58 2007 +0800 + + Configurations for ATI video card BIOS emulator + + This patch add definition of the BIOS emulator and the ATI framebuffer + driver for MPC8641HPCN board. + + Signed-off-by: Jason Jin + Signed-off-by: Zhang Wei + +commit ece92f85053b8df613edcf05b26a416cbc3d629c +Author: Jason Jin +Date: Fri Jul 6 08:34:56 2007 +0800 + + This is a BIOS emulator, porting from SciTech for u-boot, mainly for + ATI video card BIOS. and can be used for x86 code emulation by some + modifications. + + Signed-off-by: Jason Jin + +commit 5072188acabde3178fac7f5a597150e6e74fd40c +Author: Jason Jin +Date: Fri Jul 6 08:33:33 2007 +0800 + + This is a framebuffer driver for ATI video card, can work for PCI9200, + X300, X700, X800 ATI video cards. + + Signed-off-by: Zhang Wei + Signed-off-by: Jason Jin + +commit 5728be389e65fd47f34b33c2596271eb4db751ae +Author: Wolfgang Denk +Date: Mon Aug 6 01:01:49 2007 +0200 + + Coding style cleanup. Update CHANGELOG. + + Signed-off-by: Wolfgang Denk + commit 8092fef4c29b395958bb649647da7e3775731517 Author: Martin Krause Date: Tue Dec 12 14:26:01 2006 +0100 diff --git a/drivers/ati_ids.h b/drivers/ati_ids.h index 35fe505735f..3e72a7dd4c0 100644 --- a/drivers/ati_ids.h +++ b/drivers/ati_ids.h @@ -209,4 +209,3 @@ #define PCI_CHIP_R423_5D57 0x5D57 #define PCI_CHIP_RS350_7834 0x7834 #define PCI_CHIP_RS350_7835 0x7835 - diff --git a/drivers/ati_radeon_fb.c b/drivers/ati_radeon_fb.c index e15140ab38d..c174f37b3fa 100644 --- a/drivers/ati_radeon_fb.c +++ b/drivers/ati_radeon_fb.c @@ -137,7 +137,7 @@ static void radeon_identify_vram(struct radeonfb_info *rinfo) } } else { tmp = INREG(CONFIG_MEMSIZE); - } + } /* mem size is bits [28:0], mask off the rest */ rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK; @@ -209,13 +209,13 @@ static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_reg #if 0 /* Workaround from XFree */ if (rinfo->is_mobility) { - /* A temporal workaround for the occational blanking on certain laptop + /* A temporal workaround for the occational blanking on certain laptop * panels. This appears to related to the PLL divider registers * (fail to lock?). It occurs even when all dividers are the same * with their old settings. In this case we really don't need to * fiddle with PLL registers. By doing this we can avoid the blanking * problem with some panels. - */ + */ if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) { diff --git a/drivers/ati_radeon_fb.h b/drivers/ati_radeon_fb.h index 1c3ba64cfb0..b5c4b8b5779 100644 --- a/drivers/ati_radeon_fb.h +++ b/drivers/ati_radeon_fb.h @@ -5,7 +5,6 @@ * Most of the definitions here are adapted right from XFree86 * ***************************************************************/ - /* * Chip families. Must fit in the low 16 bits of a long word */ @@ -38,14 +37,12 @@ enum radeon_family { ((rinfo)->family == CHIP_FAMILY_RV280) || \ ((rinfo)->family == CHIP_FAMILY_RS300)) - #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \ ((rinfo)->family == CHIP_FAMILY_RV350) || \ ((rinfo)->family == CHIP_FAMILY_R350) || \ ((rinfo)->family == CHIP_FAMILY_RV380) || \ ((rinfo)->family == CHIP_FAMILY_R420)) - struct radeonfb_info { char name[20]; @@ -86,7 +83,6 @@ static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr, #define OUTREGP(addr,val,mask) _OUTREGP(rinfo, addr, val,mask) - /* * 2D Engine helper routines */ @@ -106,7 +102,6 @@ static inline void radeon_engine_flush (struct radeonfb_info *rinfo) printf("radeonfb: Flush Timeout !\n"); } - static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) { int i; @@ -119,7 +114,6 @@ static inline void _radeon_fifo_wait(struct radeonfb_info *rinfo, int entries) printf("radeonfb: FIFO Timeout !\n"); } - static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) { int i; @@ -137,7 +131,6 @@ static inline void _radeon_engine_idle(struct radeonfb_info *rinfo) printf("radeonfb: Idle Timeout !\n"); } - #define radeon_engine_idle() _radeon_engine_idle(rinfo) #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries) #define radeon_msleep(ms) _radeon_msleep(rinfo,ms) @@ -255,9 +248,9 @@ static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr) u32 data; OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f); - //radeon_pll_errata_after_index(rinfo); + /* radeon_pll_errata_after_index(rinfo); */ data = INREG(CLOCK_CNTL_DATA); - //radeon_pll_errata_after_data(rinfo); + /* radeon_pll_errata_after_data(rinfo); */ return data; } @@ -266,12 +259,11 @@ static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index, { OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080); - //radeon_pll_errata_after_index(rinfo); + /* radeon_pll_errata_after_index(rinfo); */ OUTREG(CLOCK_CNTL_DATA, val); - //radeon_pll_errata_after_data(rinfo); + /* radeon_pll_errata_after_data(rinfo); */ } - static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, u32 val, u32 mask) { @@ -283,11 +275,8 @@ static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index, __OUTPLL(rinfo, index, tmp); } - #define INPLL(addr) __INPLL(rinfo, addr) #define OUTPLL(index, val) __OUTPLL(rinfo, index, val) #define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask) - - #endif diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c index 084339c1b29..5779f99f1f6 100644 --- a/drivers/bios_emulator/atibios.c +++ b/drivers/bios_emulator/atibios.c @@ -1,6 +1,6 @@ /**************************************************************************** * -* Video BOOT Graphics Card POST Module +* Video BOOT Graphics Card POST Module * * ======================================================================== * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. @@ -30,20 +30,20 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Linux Kernel -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Linux Kernel +* Developer: Kendall Bennett * -* Description: Module to implement booting PCI/AGP controllers on the -* bus. We use the x86 real mode emulator to run the BIOS on -* graphics controllers to bring the cards up. +* Description: Module to implement booting PCI/AGP controllers on the +* bus. We use the x86 real mode emulator to run the BIOS on +* graphics controllers to bring the cards up. * -* Note that at present this module does *not* support -* multiple controllers. +* Note that at present this module does *not* support +* multiple controllers. * -* The orignal name of this file is warmboot.c. -* Jason ported this file to u-boot to run the ATI video card -* BIOS in u-boot. +* The orignal name of this file is warmboot.c. +* Jason ported this file to u-boot to run the ATI video card +* BIOS in u-boot. ****************************************************************************/ #include @@ -53,11 +53,11 @@ #include /* Length of the BIOS image */ -#define MAX_BIOSLEN (128 * 1024L) +#define MAX_BIOSLEN (128 * 1024L) /* Define some useful types and macros */ -#define true 1 -#define false 0 +#define true 1 +#define false 0 /* Place to save PCI BAR's that we change and later restore */ static u32 saveROMBaseAddress; @@ -68,7 +68,7 @@ static u32 saveBaseAddress20; /**************************************************************************** PARAMETERS: -pcidev - PCI device info for the video card on the bus to boot +pcidev - PCI device info for the video card on the bus to boot VGAInfo - BIOS emulator VGA info structure REMARKS: @@ -102,8 +102,8 @@ static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo * VGAInfo) /**************************************************************************** PARAMETERS: -pcidev - PCI device info for the video card on the bus -bar - Place to return the base address register offset to use +pcidev - PCI device info for the video card on the bus +bar - Place to return the base address register offset to use RETURNS: The address to use to map the secondary BIOS (AGP devices) @@ -166,7 +166,7 @@ static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base) /**************************************************************************** PARAMETERS: -pcidev - PCI device info for the video card on the bus +pcidev - PCI device info for the video card on the bus RETURNS: Pointers to the mapped BIOS image @@ -196,7 +196,7 @@ void *PCI_mapBIOSImage(pci_dev_t pcidev) /* Some cards have problems that stop us from being able to read the BIOS image from the ROM BAR. To fix this we have to do some chipset specific programming for different cards to solve this problem. - */ + */ if ((BIOSImagePhys = PCI_findBIOSAddr(pcidev, &BIOSImageBAR)) == 0) { printf("Find bios addr error\n"); @@ -223,7 +223,7 @@ void *PCI_mapBIOSImage(pci_dev_t pcidev) /**************************************************************************** PARAMETERS: -pcidev - PCI device info for the video card on the bus +pcidev - PCI device info for the video card on the bus REMARKS: Unmaps the BIOS image for the device and restores framebuffer mappings @@ -239,7 +239,7 @@ void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage) /**************************************************************************** PARAMETERS: -pcidev - PCI device info for the video card on the bus to boot +pcidev - PCI device info for the video card on the bus to boot VGAInfo - BIOS emulator VGA info structure RETURNS: @@ -294,9 +294,9 @@ static int PCI_postController(pci_dev_t pcidev, BE_VGAInfo * VGAInfo) /**************************************************************************** PARAMETERS: -pcidev - PCI device info for the video card on the bus to boot +pcidev - PCI device info for the video card on the bus to boot pVGAInfo - Place to return VGA info structure is requested -cleanUp - True to clean up on exit, false to leave emulator active +cleanUp - True to clean up on exit, false to leave emulator active REMARKS: Boots the PCI/AGP video card on the bus using the Video ROM BIOS image diff --git a/drivers/bios_emulator/besys.c b/drivers/bios_emulator/besys.c index 894012fa898..2a8e1a01c1f 100644 --- a/drivers/bios_emulator/besys.c +++ b/drivers/bios_emulator/besys.c @@ -251,71 +251,69 @@ hardware does not support mapping the VGA I/O and memory (such as some PowerPC systems), we emulate the VGA so that the BIOS will still be able to set NonVGA display modes such as on ATI hardware. ****************************************************************************/ -static u8 VGA_inpb( - const int port) +static u8 VGA_inpb (const int port) { - u8 val = 0xff; - - switch (port) { - case 0x3C0: - /* 3C0 has funky characteristics because it can act as either - a data register or index register depending on the state - of an internal flip flop in the hardware. Hence we have - to emulate that functionality in here. */ - if (_BE_env.flipFlop3C0 == 0) { - /* Access 3C0 as index register*/ - val = _BE_env.emu3C0; - } - else { - /* Access 3C0 as data register*/ - if (_BE_env.emu3C0 < ATT_C) - val = _BE_env.emu3C1[_BE_env.emu3C0]; - } - _BE_env.flipFlop3C0 ^= 1; - break; - case 0x3C1: - if (_BE_env.emu3C0 < ATT_C) - return _BE_env.emu3C1[_BE_env.emu3C0]; - break; - case 0x3CC: - return _BE_env.emu3C2; - case 0x3C4: - return _BE_env.emu3C4; - case 0x3C5: - if (_BE_env.emu3C4 < ATT_C) - return _BE_env.emu3C5[_BE_env.emu3C4]; - break; - case 0x3C6: - return _BE_env.emu3C6; - case 0x3C7: - return _BE_env.emu3C7; - case 0x3C8: - return _BE_env.emu3C8; - case 0x3C9: - if (_BE_env.emu3C7 < PAL_C) - return _BE_env.emu3C9[_BE_env.emu3C7++]; - break; - case 0x3CE: - return _BE_env.emu3CE; - case 0x3CF: - if (_BE_env.emu3CE < GRA_C) - return _BE_env.emu3CF[_BE_env.emu3CE]; - break; - case 0x3D4: - if (_BE_env.emu3C2 & 0x1) - return _BE_env.emu3D4; - break; - case 0x3D5: - if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C)) - return _BE_env.emu3D5[_BE_env.emu3D4]; - break; - case 0x3DA: - _BE_env.flipFlop3C0 = 0; - val = _BE_env.emu3DA; - _BE_env.emu3DA ^= 0x9; - break; - } - return val; + u8 val = 0xff; + + switch (port) { + case 0x3C0: + /* 3C0 has funky characteristics because it can act as either + a data register or index register depending on the state + of an internal flip flop in the hardware. Hence we have + to emulate that functionality in here. */ + if (_BE_env.flipFlop3C0 == 0) { + /* Access 3C0 as index register */ + val = _BE_env.emu3C0; + } else { + /* Access 3C0 as data register */ + if (_BE_env.emu3C0 < ATT_C) + val = _BE_env.emu3C1[_BE_env.emu3C0]; + } + _BE_env.flipFlop3C0 ^= 1; + break; + case 0x3C1: + if (_BE_env.emu3C0 < ATT_C) + return _BE_env.emu3C1[_BE_env.emu3C0]; + break; + case 0x3CC: + return _BE_env.emu3C2; + case 0x3C4: + return _BE_env.emu3C4; + case 0x3C5: + if (_BE_env.emu3C4 < ATT_C) + return _BE_env.emu3C5[_BE_env.emu3C4]; + break; + case 0x3C6: + return _BE_env.emu3C6; + case 0x3C7: + return _BE_env.emu3C7; + case 0x3C8: + return _BE_env.emu3C8; + case 0x3C9: + if (_BE_env.emu3C7 < PAL_C) + return _BE_env.emu3C9[_BE_env.emu3C7++]; + break; + case 0x3CE: + return _BE_env.emu3CE; + case 0x3CF: + if (_BE_env.emu3CE < GRA_C) + return _BE_env.emu3CF[_BE_env.emu3CE]; + break; + case 0x3D4: + if (_BE_env.emu3C2 & 0x1) + return _BE_env.emu3D4; + break; + case 0x3D5: + if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C)) + return _BE_env.emu3D5[_BE_env.emu3D4]; + break; + case 0x3DA: + _BE_env.flipFlop3C0 = 0; + val = _BE_env.emu3DA; + _BE_env.emu3DA ^= 0x9; + break; + } + return val; } /**************************************************************************** @@ -328,66 +326,65 @@ Performs an emulated write to one of the 8253 timer registers. For now we only emulate timer 0 which is the only timer that the BIOS code appears to use. ****************************************************************************/ -static void VGA_outpb( - int port, - u8 val) +static void VGA_outpb (int port, u8 val) { - switch (port) { - case 0x3C0: - /* 3C0 has funky characteristics because it can act as either - a data register or index register depending on the state - of an internal flip flop in the hardware. Hence we have - to emulate that functionality in here.*/ - if (_BE_env.flipFlop3C0 == 0) { - /* Access 3C0 as index register*/ - _BE_env.emu3C0 = val; - } - else { - /* Access 3C0 as data register*/ - if (_BE_env.emu3C0 < ATT_C) - _BE_env.emu3C1[_BE_env.emu3C0] = val; - } - _BE_env.flipFlop3C0 ^= 1; - break; - case 0x3C2: - _BE_env.emu3C2 = val; - break; - case 0x3C4: - _BE_env.emu3C4 = val; - break; - case 0x3C5: - if (_BE_env.emu3C4 < ATT_C) - _BE_env.emu3C5[_BE_env.emu3C4] = val; - break; - case 0x3C6: - _BE_env.emu3C6 = val; - break; - case 0x3C7: - _BE_env.emu3C7 = (int)val * 3; - break; - case 0x3C8: - _BE_env.emu3C8 = (int)val * 3; - break; - case 0x3C9: - if (_BE_env.emu3C8 < PAL_C) - _BE_env.emu3C9[_BE_env.emu3C8++] = val; - break; - case 0x3CE: - _BE_env.emu3CE = val; - break; - case 0x3CF: - if (_BE_env.emu3CE < GRA_C) - _BE_env.emu3CF[_BE_env.emu3CE] = val; - break; - case 0x3D4: - if (_BE_env.emu3C2 & 0x1) - _BE_env.emu3D4 = val; - break; - case 0x3D5: - if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C)) - _BE_env.emu3D5[_BE_env.emu3D4] = val; - break; - } + switch (port) { + case 0x3C0: + /* 3C0 has funky characteristics because it can act as either + a data register or index register depending on the state + of an internal flip flop in the hardware. Hence we have + to emulate that functionality in here. */ + if (_BE_env.flipFlop3C0 == 0) { + /* Access 3C0 as index register */ + _BE_env.emu3C0 = val; + } else { + /* Access 3C0 as data register */ + if (_BE_env.emu3C0 < ATT_C) + _BE_env.emu3C1[_BE_env.emu3C0] = val; + } + _BE_env.flipFlop3C0 ^= 1; + break; + case 0x3C2: + _BE_env.emu3C2 = val; + break; + case 0x3C4: + _BE_env.emu3C4 = val; + break; + case 0x3C5: + if (_BE_env.emu3C4 < ATT_C) + _BE_env.emu3C5[_BE_env.emu3C4] = val; + break; + case 0x3C6: + _BE_env.emu3C6 = val; + break; + case 0x3C7: + _BE_env.emu3C7 = (int) val *3; + + break; + case 0x3C8: + _BE_env.emu3C8 = (int) val *3; + + break; + case 0x3C9: + if (_BE_env.emu3C8 < PAL_C) + _BE_env.emu3C9[_BE_env.emu3C8++] = val; + break; + case 0x3CE: + _BE_env.emu3CE = val; + break; + case 0x3CF: + if (_BE_env.emu3CE < GRA_C) + _BE_env.emu3CF[_BE_env.emu3CE] = val; + break; + case 0x3D4: + if (_BE_env.emu3C2 & 0x1) + _BE_env.emu3D4 = val; + break; + case 0x3D5: + if ((_BE_env.emu3C2 & 0x1) && (_BE_env.emu3D4 < CRT_C)) + _BE_env.emu3D5[_BE_env.emu3D4] = val; + break; + } } /**************************************************************************** diff --git a/drivers/bios_emulator/biosemu.c b/drivers/bios_emulator/biosemu.c index aca594ce711..06d4ad380f3 100644 --- a/drivers/bios_emulator/biosemu.c +++ b/drivers/bios_emulator/biosemu.c @@ -1,12 +1,12 @@ /**************************************************************************** * -* BIOS emulator and interface -* to Realmode X86 Emulator Library +* BIOS emulator and interface +* to Realmode X86 Emulator Library * * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. * Jason Jin * -* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) 1996-1999 SciTech Software, Inc. * * ======================================================================== * @@ -16,7 +16,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -30,18 +30,18 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett * -* Description: Module implementing the system specific functions. This -* module is always compiled and linked in the OS depedent -* libraries, and never in a binary portable driver. +* Description: Module implementing the system specific functions. This +* module is always compiled and linked in the OS depedent +* libraries, and never in a binary portable driver. * -* Jason ported this file to u-boot to run the ATI video card BIOS -* in u-boot. Made all the video memory be emulated during the -* BIOS runing process which may affect the VGA function but the -* frambuffer function can work after run the BIOS. +* Jason ported this file to u-boot to run the ATI video card BIOS +* in u-boot. Made all the video memory be emulated during the +* BIOS runing process which may affect the VGA function but the +* frambuffer function can work after run the BIOS. * ****************************************************************************/ @@ -67,14 +67,14 @@ static X86EMU_pioFuncs _BE_pio __attribute__((section(".got2"))) = { BE_outl, }; -#define OFF(addr) (u16)(((addr) >> 0) & 0xffff) -#define SEG(addr) (u16)(((addr) >> 4) & 0xf000) +#define OFF(addr) (u16)(((addr) >> 0) & 0xffff) +#define SEG(addr) (u16)(((addr) >> 4) & 0xf000) /**************************************************************************** PARAMETERS: debugFlags - Flags to enable debugging options (debug builds only) -memSize - Amount of memory to allocate for real mode machine -info - Pointer to default VGA device information +memSize - Amount of memory to allocate for real mode machine +info - Pointer to default VGA device information REMARKS: This functions initialises the BElib, and uses the passed in @@ -116,7 +116,7 @@ int X86API BE_init(u32 debugFlags, int memSize, BE_VGAInfo * info, int shared) /**************************************************************************** PARAMETERS: -info - Pointer to VGA device information to make current +info - Pointer to VGA device information to make current REMARKS: This function sets the VGA BIOS functions in the emulator to point to the @@ -150,7 +150,7 @@ void X86API BE_setVGA(BE_VGAInfo * info) /**************************************************************************** PARAMETERS: -info - Pointer to VGA device information to retrieve current +info - Pointer to VGA device information to retrieve current REMARKS: This function returns the VGA BIOS functions currently active in the @@ -172,16 +172,16 @@ void X86API BE_getVGA(BE_VGAInfo * info) /**************************************************************************** PARAMETERS: -r_seg - Segment for pointer to convert -r_off - Offset for pointer to convert +r_seg - Segment for pointer to convert +r_off - Offset for pointer to convert REMARKS: This function maps a real mode pointer in the emulator memory to a protected mode pointer that can be used to directly access the memory. -NOTE: The memory is *always* in little endian format, son on non-x86 - systems you will need to do endian translations to access this - memory. +NOTE: The memory is *always* in little endian format, son on non-x86 + systems you will need to do endian translations to access this + memory. ****************************************************************************/ void *X86API BE_mapRealPointer(uint r_seg, uint r_off) { @@ -197,9 +197,9 @@ void *X86API BE_mapRealPointer(uint r_seg, uint r_off) /**************************************************************************** PARAMETERS: -len - Return the length of the VESA buffer -rseg - Place to store VESA buffer segment -roff - Place to store VESA buffer offset +len - Return the length of the VESA buffer +rseg - Place to store VESA buffer segment +roff - Place to store VESA buffer offset REMARKS: This function returns the address of the VESA transfer buffer in real @@ -207,9 +207,9 @@ _BE_piomode emulator memory. The VESA transfer buffer is always 1024 bytes long, and located at 15Kb into the start of the real mode memory (16Kb is where we put the real mode code we execute for issuing interrupts). -NOTE: The memory is *always* in little endian format, son on non-x86 - systems you will need to do endian translations to access this - memory. +NOTE: The memory is *always* in little endian format, son on non-x86 + systems you will need to do endian translations to access this + memory. ****************************************************************************/ void *X86API BE_getVESABuf(uint * len, uint * rseg, uint * roff) { @@ -231,10 +231,10 @@ void X86API BE_exit(void) /**************************************************************************** PARAMETERS: -seg - Segment of code to call -off - Offset of code to call -regs - Real mode registers to load -sregs - Real mode segment registers to load +seg - Segment of code to call +off - Offset of code to call +regs - Real mode registers to load +sregs - Real mode segment registers to load REMARKS: This functions calls a real mode far function at the specified address, @@ -284,9 +284,9 @@ void X86API BE_callRealMode(uint seg, uint off, RMREGS * regs, RMSREGS * sregs) /**************************************************************************** PARAMETERS: -intno - Interrupt number to execute -in - Real mode registers to load -out - Place to store resulting real mode registers +intno - Interrupt number to execute +in - Real mode registers to load +out - Place to store resulting real mode registers REMARKS: This functions calls a real mode interrupt function at the specified address, @@ -323,10 +323,10 @@ int X86API BE_int86(int intno, RMREGS * in, RMREGS * out) /**************************************************************************** PARAMETERS: -intno - Interrupt number to execute -in - Real mode registers to load -out - Place to store resulting real mode registers -sregs - Real mode segment registers to load +intno - Interrupt number to execute +in - Real mode registers to load +out - Place to store resulting real mode registers +sregs - Real mode segment registers to load REMARKS: This functions calls a real mode interrupt function at the specified address, diff --git a/drivers/bios_emulator/biosemui.h b/drivers/bios_emulator/biosemui.h index 3265ac15cb6..e85e656cb45 100644 --- a/drivers/bios_emulator/biosemui.h +++ b/drivers/bios_emulator/biosemui.h @@ -1,12 +1,12 @@ /**************************************************************************** * -* BIOS emulator and interface -* to Realmode X86 Emulator Library +* BIOS emulator and interface +* to Realmode X86 Emulator Library * * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. * Jason Jin * -* Copyright (C) 1996-1999 SciTech Software, Inc. +* Copyright (C) 1996-1999 SciTech Software, Inc. * * ======================================================================== * @@ -16,7 +16,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -30,14 +30,14 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett * -* Description: Internal header file for the BIOS emulator library. +* Description: Internal header file for the BIOS emulator library. * -* Jason ported this file to u-boot, Added some architecture -* related Macro. +* Jason ported this file to u-boot, Added some architecture +* related Macro. * ****************************************************************************/ @@ -49,14 +49,14 @@ /*---------------------- Macros and type definitions ----------------------*/ #ifdef DEBUG -#define DB(x) x +#define DB(x) x #else -#define DB(x) do{}while(0); +#define DB(x) do{}while(0); #endif -#define BIOS_SEG 0xfff0 +#define BIOS_SEG 0xfff0 extern X86EMU_sysEnv _X86EMU_env; -#define M _X86EMU_env +#define M _X86EMU_env /* Macros to read and write values to x86 emulator memory. Memory is always * considered to be little endian, so we use macros to do endian swapping @@ -64,21 +64,21 @@ extern X86EMU_sysEnv _X86EMU_env; */ #ifdef __BIG_ENDIAN__ -#define readb_le(base) *((u8*)(base)) -#define readw_le(base) ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8)) -#define readl_le(base) ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \ - ((u32)readb_le((base) + 2) << 16) | ((u32)readb_le((base) + 3) << 24)) +#define readb_le(base) *((u8*)(base)) +#define readw_le(base) ((u16)readb_le(base) | ((u16)readb_le((base) + 1) << 8)) +#define readl_le(base) ((u32)readb_le((base) + 0) | ((u32)readb_le((base) + 1) << 8) | \ + ((u32)readb_le((base) + 2) << 16) | ((u32)readb_le((base) + 3) << 24)) #define writeb_le(base, v) *((u8*)(base)) = (v) -#define writew_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ - writeb_le(base + 1, (v >> 8) & 0xff) -#define writel_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ - writeb_le(base + 1, (v >> 8) & 0xff), \ - writeb_le(base + 2, (v >> 16) & 0xff), \ - writeb_le(base + 3, (v >> 24) & 0xff) +#define writew_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ + writeb_le(base + 1, (v >> 8) & 0xff) +#define writel_le(base, v) writeb_le(base + 0, (v >> 0) & 0xff), \ + writeb_le(base + 1, (v >> 8) & 0xff), \ + writeb_le(base + 2, (v >> 16) & 0xff), \ + writeb_le(base + 3, (v >> 24) & 0xff) #else -#define readb_le(base) *((u8*)(base)) -#define readw_le(base) *((u16*)(base)) -#define readl_le(base) *((u32*)(base)) +#define readb_le(base) *((u8*)(base)) +#define readw_le(base) *((u16*)(base)) +#define readl_le(base) *((u32*)(base)) #define writeb_le(base, v) *((u8*)(base)) = (v) #define writew_le(base, v) *((u16*)(base)) = (v) #define writel_le(base, v) *((u32*)(base)) = (v) @@ -118,8 +118,8 @@ HEADER: biosemu.h MEMBERS: -type - Type of port access (1 = byte, 2 = word, 3 = dword) -defVal - Default power on value +type - Type of port access (1 = byte, 2 = word, 3 = dword) +defVal - Default power on value finalVal - Final value ****************************************************************************/ typedef struct { diff --git a/drivers/bios_emulator/include/x86emu/debug.h b/drivers/bios_emulator/include/x86emu/debug.h index 35e1e9a92fb..268c9d391e2 100644 --- a/drivers/bios_emulator/include/x86emu/debug.h +++ b/drivers/bios_emulator/include/x86emu/debug.h @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -14,7 +14,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -28,11 +28,11 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett * -* Description: Header file for debug definitions. +* Description: Header file for debug definitions. * ****************************************************************************/ @@ -43,16 +43,16 @@ /* checks to be enabled for "runtime" */ -#define CHECK_IP_FETCH_F 0x1 -#define CHECK_SP_ACCESS_F 0x2 -#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ -#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset */ +#define CHECK_IP_FETCH_F 0x1 +#define CHECK_SP_ACCESS_F 0x2 +#define CHECK_MEM_ACCESS_F 0x4 /*using regular linear pointer */ +#define CHECK_DATA_ACCESS_F 0x8 /*using segment:offset */ #ifdef DEBUG -# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) -# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) -# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) -# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) +# define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F) +# define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F) +# define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F) +# define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F) #else # define CHECK_IP_FETCH() # define CHECK_SP_ACCESS() @@ -61,50 +61,50 @@ #endif #ifdef DEBUG -# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) -# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) -# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) -# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) -# define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) -# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) -# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) -# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_CS_IP) - -# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) -# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) -# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) -# define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) -# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) -# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) -# define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) -# define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) +# define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F) +# define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F) +# define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F) +# define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F) +# define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F) +# define DEBUG_BREAK() (M.x86.debug & DEBUG_BREAK_F) +# define DEBUG_SVC() (M.x86.debug & DEBUG_SVC_F) +# define DEBUG_SAVE_IP_CS() (M.x86.debug & DEBUG_SAVE_CS_IP) + +# define DEBUG_FS() (M.x86.debug & DEBUG_FS_F) +# define DEBUG_PROC() (M.x86.debug & DEBUG_PROC_F) +# define DEBUG_SYSINT() (M.x86.debug & DEBUG_SYSINT_F) +# define DEBUG_TRACECALL() (M.x86.debug & DEBUG_TRACECALL_F) +# define DEBUG_TRACECALLREGS() (M.x86.debug & DEBUG_TRACECALL_REGS_F) +# define DEBUG_SYS() (M.x86.debug & DEBUG_SYS_F) +# define DEBUG_MEM_TRACE() (M.x86.debug & DEBUG_MEM_TRACE_F) +# define DEBUG_IO_TRACE() (M.x86.debug & DEBUG_IO_TRACE_F) # define DEBUG_DECODE_NOPRINT() (M.x86.debug & DEBUG_DECODE_NOPRINT_F) #else -# define DEBUG_INSTRUMENT() 0 -# define DEBUG_DECODE() 0 -# define DEBUG_TRACE() 0 -# define DEBUG_STEP() 0 -# define DEBUG_DISASSEMBLE() 0 -# define DEBUG_BREAK() 0 -# define DEBUG_SVC() 0 -# define DEBUG_SAVE_IP_CS() 0 -# define DEBUG_FS() 0 -# define DEBUG_PROC() 0 -# define DEBUG_SYSINT() 0 -# define DEBUG_TRACECALL() 0 -# define DEBUG_TRACECALLREGS() 0 -# define DEBUG_SYS() 0 -# define DEBUG_MEM_TRACE() 0 -# define DEBUG_IO_TRACE() 0 +# define DEBUG_INSTRUMENT() 0 +# define DEBUG_DECODE() 0 +# define DEBUG_TRACE() 0 +# define DEBUG_STEP() 0 +# define DEBUG_DISASSEMBLE() 0 +# define DEBUG_BREAK() 0 +# define DEBUG_SVC() 0 +# define DEBUG_SAVE_IP_CS() 0 +# define DEBUG_FS() 0 +# define DEBUG_PROC() 0 +# define DEBUG_SYSINT() 0 +# define DEBUG_TRACECALL() 0 +# define DEBUG_TRACECALLREGS() 0 +# define DEBUG_SYS() 0 +# define DEBUG_MEM_TRACE() 0 +# define DEBUG_IO_TRACE() 0 # define DEBUG_DECODE_NOPRINT() 0 #endif #ifdef DEBUG -# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ - x86emu_decode_printf(x) -# define DECODE_PRINTF2(x,y) if (DEBUG_DECODE()) \ - x86emu_decode_printf2(x,y) +# define DECODE_PRINTF(x) if (DEBUG_DECODE()) \ + x86emu_decode_printf(x) +# define DECODE_PRINTF2(x,y) if (DEBUG_DECODE()) \ + x86emu_decode_printf2(x,y) /* * The following allow us to look at the bytes of an instruction. The @@ -112,15 +112,15 @@ * the decoding process. The SAVE_IP_CS is called initially when the * major opcode of the instruction is accessed. */ -#define INC_DECODED_INST_LEN(x) \ - if (DEBUG_DECODE()) \ - x86emu_inc_decoded_inst_len(x) +#define INC_DECODED_INST_LEN(x) \ + if (DEBUG_DECODE()) \ + x86emu_inc_decoded_inst_len(x) -#define SAVE_IP_CS(x,y) \ +#define SAVE_IP_CS(x,y) \ if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \ - | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ - M.x86.saved_cs = x; \ - M.x86.saved_ip = y; \ + | DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \ + M.x86.saved_cs = x; \ + M.x86.saved_ip = y; \ } #else # define INC_DECODED_INST_LEN(x) @@ -130,29 +130,29 @@ #endif #ifdef DEBUG -#define TRACE_REGS() \ - if (DEBUG_DISASSEMBLE()) { \ - x86emu_just_disassemble(); \ - goto EndOfTheInstructionProcedure; \ - } \ +#define TRACE_REGS() \ + if (DEBUG_DISASSEMBLE()) { \ + x86emu_just_disassemble(); \ + goto EndOfTheInstructionProcedure; \ + } \ if (DEBUG_TRACE() || DEBUG_DECODE()) X86EMU_trace_regs() #else # define TRACE_REGS() #endif #ifdef DEBUG -# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() +# define SINGLE_STEP() if (DEBUG_STEP()) x86emu_single_step() #else # define SINGLE_STEP() #endif #define TRACE_AND_STEP() \ - TRACE_REGS(); \ + TRACE_REGS(); \ SINGLE_STEP() #ifdef DEBUG # define START_OF_INSTR() -# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); +# define END_OF_INSTR() EndOfTheInstructionProcedure: x86emu_end_instr(); # define END_OF_INSTR_NO_TRACE() x86emu_end_instr(); #else # define START_OF_INSTR() @@ -161,30 +161,30 @@ #endif #ifdef DEBUG -# define CALL_TRACE(u,v,w,x,s) \ - if (DEBUG_TRACECALLREGS()) \ - x86emu_dump_regs(); \ - if (DEBUG_TRACECALL()) \ - printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); -# define RETURN_TRACE(n,u,v) \ - if (DEBUG_TRACECALLREGS()) \ - x86emu_dump_regs(); \ - if (DEBUG_TRACECALL()) \ - printk("%04x:%04x: %s\n",u,v,n); +# define CALL_TRACE(u,v,w,x,s) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + printk("%04x:%04x: CALL %s%04x:%04x\n", u , v, s, w, x); +# define RETURN_TRACE(n,u,v) \ + if (DEBUG_TRACECALLREGS()) \ + x86emu_dump_regs(); \ + if (DEBUG_TRACECALL()) \ + printk("%04x:%04x: %s\n",u,v,n); #else # define CALL_TRACE(u,v,w,x,s) # define RETURN_TRACE(n,u,v) #endif #ifdef DEBUG -#define DB(x) x +#define DB(x) x #else #define DB(x) #endif /*-------------------------- Function Prototypes --------------------------*/ -#ifdef __cplusplus +#ifdef __cplusplus extern "C" { /* Use "C" linkage when in C++ mode */ #endif @@ -203,7 +203,7 @@ extern "C" { /* Use "C" linkage when in C++ mode */ extern void x86emu_check_mem_access(u32 p); extern void x86emu_check_data_access(uint s, uint o); -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_DEBUG_H */ diff --git a/drivers/bios_emulator/include/x86emu/prim_ops.h b/drivers/bios_emulator/include/x86emu/prim_ops.h index 0ea825d3c1a..2291e8488a5 100644 --- a/drivers/bios_emulator/include/x86emu/prim_ops.h +++ b/drivers/bios_emulator/include/x86emu/prim_ops.h @@ -139,4 +139,3 @@ u32 pop_long (void); #endif #endif /* __X86EMU_PRIM_OPS_H */ - diff --git a/drivers/bios_emulator/include/x86emu/regs.h b/drivers/bios_emulator/include/x86emu/regs.h index 9dbed503175..a7fedd2f6ca 100644 --- a/drivers/bios_emulator/include/x86emu/regs.h +++ b/drivers/bios_emulator/include/x86emu/regs.h @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -14,7 +14,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -28,11 +28,11 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett * -* Description: Header file for x86 register definitions. +* Description: Header file for x86 register definitions. * ****************************************************************************/ @@ -54,11 +54,11 @@ * EAX & 0xff === AL * EAX & 0xffff == AX * - * etc. The result is that alot of the calculations can then be + * etc. The result is that alot of the calculations can then be * done using the native instruction set fully. */ -#ifdef __BIG_ENDIAN__ +#ifdef __BIG_ENDIAN__ typedef struct { u32 e_reg; @@ -178,7 +178,7 @@ struct i386_segment_regs { /* flag conditions */ #define FB_CF 0x0001 /* CARRY flag */ #define FB_PF 0x0004 /* PARITY flag */ -#define FB_AF 0x0010 /* AUX flag */ +#define FB_AF 0x0010 /* AUX flag */ #define FB_ZF 0x0040 /* ZERO flag */ #define FB_SF 0x0080 /* SIGN flag */ #define FB_TF 0x0100 /* TRAP flag */ @@ -199,7 +199,7 @@ struct i386_segment_regs { #define F_CF 0x0001 /* CARRY flag */ #define F_PF 0x0004 /* PARITY flag */ -#define F_AF 0x0010 /* AUX flag */ +#define F_AF 0x0010 /* AUX flag */ #define F_ZF 0x0040 /* ZERO flag */ #define F_SF 0x0080 /* SIGN flag */ #define F_TF 0x0100 /* TRAP flag */ @@ -207,60 +207,60 @@ struct i386_segment_regs { #define F_DF 0x0400 /* DIR flag */ #define F_OF 0x0800 /* OVERFLOW flag */ -#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) -#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) -#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) -#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) -#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) +#define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag)) +#define SET_FLAG(flag) (M.x86.R_FLG |= (flag)) +#define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag)) +#define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag)) +#define CLEARALL_FLAG(m) (M.x86.R_FLG = 0) #define CONDITIONAL_SET_FLAG(COND,FLAG) \ if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG) -#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ -#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ -#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ +#define F_PF_CALC 0x010000 /* PARITY flag has been calced */ +#define F_ZF_CALC 0x020000 /* ZERO flag has been calced */ +#define F_SF_CALC 0x040000 /* SIGN flag has been calced */ -#define F_ALL_CALC 0xff0000 /* All have been calced */ +#define F_ALL_CALC 0xff0000 /* All have been calced */ /* * Emulator machine state. * Segment usage control. */ -#define SYSMODE_SEG_DS_SS 0x00000001 -#define SYSMODE_SEGOVR_CS 0x00000002 -#define SYSMODE_SEGOVR_DS 0x00000004 -#define SYSMODE_SEGOVR_ES 0x00000008 -#define SYSMODE_SEGOVR_FS 0x00000010 -#define SYSMODE_SEGOVR_GS 0x00000020 -#define SYSMODE_SEGOVR_SS 0x00000040 -#define SYSMODE_PREFIX_REPE 0x00000080 -#define SYSMODE_PREFIX_REPNE 0x00000100 -#define SYSMODE_PREFIX_DATA 0x00000200 -#define SYSMODE_PREFIX_ADDR 0x00000400 -#define SYSMODE_INTR_PENDING 0x10000000 -#define SYSMODE_EXTRN_INTR 0x20000000 -#define SYSMODE_HALTED 0x40000000 - -#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ - SYSMODE_SEGOVR_CS | \ - SYSMODE_SEGOVR_DS | \ - SYSMODE_SEGOVR_ES | \ - SYSMODE_SEGOVR_FS | \ - SYSMODE_SEGOVR_GS | \ - SYSMODE_SEGOVR_SS) -#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ - SYSMODE_SEGOVR_CS | \ - SYSMODE_SEGOVR_DS | \ - SYSMODE_SEGOVR_ES | \ - SYSMODE_SEGOVR_FS | \ - SYSMODE_SEGOVR_GS | \ - SYSMODE_SEGOVR_SS | \ - SYSMODE_PREFIX_DATA | \ - SYSMODE_PREFIX_ADDR) - -#define INTR_SYNCH 0x1 -#define INTR_ASYNCH 0x2 -#define INTR_HALTED 0x4 +#define SYSMODE_SEG_DS_SS 0x00000001 +#define SYSMODE_SEGOVR_CS 0x00000002 +#define SYSMODE_SEGOVR_DS 0x00000004 +#define SYSMODE_SEGOVR_ES 0x00000008 +#define SYSMODE_SEGOVR_FS 0x00000010 +#define SYSMODE_SEGOVR_GS 0x00000020 +#define SYSMODE_SEGOVR_SS 0x00000040 +#define SYSMODE_PREFIX_REPE 0x00000080 +#define SYSMODE_PREFIX_REPNE 0x00000100 +#define SYSMODE_PREFIX_DATA 0x00000200 +#define SYSMODE_PREFIX_ADDR 0x00000400 +#define SYSMODE_INTR_PENDING 0x10000000 +#define SYSMODE_EXTRN_INTR 0x20000000 +#define SYSMODE_HALTED 0x40000000 + +#define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS) +#define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \ + SYSMODE_SEGOVR_CS | \ + SYSMODE_SEGOVR_DS | \ + SYSMODE_SEGOVR_ES | \ + SYSMODE_SEGOVR_FS | \ + SYSMODE_SEGOVR_GS | \ + SYSMODE_SEGOVR_SS | \ + SYSMODE_PREFIX_DATA | \ + SYSMODE_PREFIX_ADDR) + +#define INTR_SYNCH 0x1 +#define INTR_ASYNCH 0x2 +#define INTR_HALTED 0x4 typedef struct { struct i386_general_regs gen; @@ -268,15 +268,15 @@ typedef struct { struct i386_segment_regs seg; /* * MODE contains information on: - * REPE prefix 2 bits repe,repne - * SEGMENT overrides 5 bits normal,DS,SS,CS,ES - * Delayed flag set 3 bits (zero, signed, parity) - * reserved 6 bits - * interrupt # 8 bits instruction raised interrupt - * BIOS video segregs 4 bits - * Interrupt Pending 1 bits - * Extern interrupt 1 bits - * Halted 1 bits + * REPE prefix 2 bits repe,repne + * SEGMENT overrides 5 bits normal,DS,SS,CS,ES + * Delayed flag set 3 bits (zero, signed, parity) + * reserved 6 bits + * interrupt # 8 bits instruction raised interrupt + * BIOS video segregs 4 bits + * Interrupt Pending 1 bits + * Extern interrupt 1 bits + * Halted 1 bits */ long mode; u8 intno; @@ -288,7 +288,7 @@ typedef struct { u16 saved_cs; int enc_pos; int enc_str_pos; - char decode_buf[32]; /* encoded byte stream */ + char decode_buf[32]; /* encoded byte stream */ char decoded_buf[256]; /* disassembled strings */ #endif } X86EMU_regs; @@ -298,9 +298,9 @@ REMARKS: Structure maintaining the emulator machine state. MEMBERS: -x86 - X86 registers -mem_base - Base real mode memory for the emulator -mem_size - Size of the real mode memory block for the emulator +x86 - X86 registers +mem_base - Base real mode memory for the emulator +mem_size - Size of the real mode memory block for the emulator ****************************************************************************/ #undef x86 typedef struct { @@ -314,7 +314,7 @@ typedef struct { /*----------------------------- Global Variables --------------------------*/ -#ifdef __cplusplus +#ifdef __cplusplus extern "C" { /* Use "C" linkage when in C++ mode */ #endif @@ -324,7 +324,7 @@ extern "C" { /* Use "C" linkage when in C++ mode */ */ extern X86EMU_sysEnv _X86EMU_env; -#define M _X86EMU_env +#define M _X86EMU_env /*-------------------------- Function Prototypes --------------------------*/ @@ -334,7 +334,7 @@ extern "C" { /* Use "C" linkage when in C++ mode */ void printk(const char *fmt, ...); #endif -#ifdef __cplusplus -} /* End of "C" linkage for C++ */ +#ifdef __cplusplus +} /* End of "C" linkage for C++ */ #endif #endif /* __X86EMU_REGS_H */ diff --git a/drivers/bios_emulator/x86emu/decode.c b/drivers/bios_emulator/x86emu/decode.c index b4dbb20797d..1e2dcfe4b2b 100644 --- a/drivers/bios_emulator/x86emu/decode.c +++ b/drivers/bios_emulator/x86emu/decode.c @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -14,7 +14,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -28,12 +28,12 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett * -* Description: This file includes subroutines which are related to -* instruction decoding and accessess of immediate data via IP. etc. +* Description: This file includes subroutines which are related to +* instruction decoding and accessess of immediate data via IP. etc. * ****************************************************************************/ @@ -47,22 +47,22 @@ Handles any pending asychronous interrupts. ****************************************************************************/ static void x86emu_intr_handle(void) { - u8 intno; + u8 intno; if (M.x86.intr & INTR_SYNCH) { - intno = M.x86.intno; - if (_X86EMU_intrTab[intno]) { - (*_X86EMU_intrTab[intno])(intno); - } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(intno * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(intno * 4); - M.x86.intr = 0; - } + intno = M.x86.intno; + if (_X86EMU_intrTab[intno]) { + (*_X86EMU_intrTab[intno])(intno); + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intno * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intno * 4); + M.x86.intr = 0; + } } } @@ -95,34 +95,34 @@ void X86EMU_exec(void) DB(x86emu_end_instr();) for (;;) { -DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) - /* If debugging, save the IP and CS values. */ - SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); - INC_DECODED_INST_LEN(1); - if (M.x86.intr) { - if (M.x86.intr & INTR_HALTED) { -DB( if (M.x86.R_SP != 0) { - printk("halted\n"); - X86EMU_trace_regs(); - } - else { - if (M.x86.debug) - printk("Service completed successfully\n"); - }) - return; - } - if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || - !ACCESS_FLAG(F_IF)) { - x86emu_intr_handle(); - } - } - op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); - (*x86emu_optab[op1])(op1); - if (M.x86.debug & DEBUG_EXIT) { - M.x86.debug &= ~DEBUG_EXIT; - return; - } +DB( if (CHECK_IP_FETCH()) + x86emu_check_ip_access();) + /* If debugging, save the IP and CS values. */ + SAVE_IP_CS(M.x86.R_CS, M.x86.R_IP); + INC_DECODED_INST_LEN(1); + if (M.x86.intr) { + if (M.x86.intr & INTR_HALTED) { +DB( if (M.x86.R_SP != 0) { + printk("halted\n"); + X86EMU_trace_regs(); + } + else { + if (M.x86.debug) + printk("Service completed successfully\n"); + }) + return; + } + if (((M.x86.intr & INTR_SYNCH) && (M.x86.intno == 0 || M.x86.intno == 2)) || + !ACCESS_FLAG(F_IF)) { + x86emu_intr_handle(); + } + } + op1 = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); + (*x86emu_optab[op1])(op1); + if (M.x86.debug & DEBUG_EXIT) { + M.x86.debug &= ~DEBUG_EXIT; + return; + } } } @@ -137,9 +137,9 @@ void X86EMU_halt_sys(void) /**************************************************************************** PARAMETERS: -mod - Mod value from decoded byte -regh - Reg h value from decoded byte -regl - Reg l value from decoded byte +mod - Mod value from decoded byte +regh - Reg h value from decoded byte +regl - Reg l value from decoded byte REMARKS: Raise the specified interrupt to be handled before the execution of the @@ -155,7 +155,7 @@ void fetch_decode_modrm( int fetched; DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); INC_DECODED_INST_LEN(1); *mod = (fetched >> 6) & 0x03; @@ -178,7 +178,7 @@ u8 fetch_byte_imm(void) u8 fetched; DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdb)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP++)); INC_DECODED_INST_LEN(1); return fetched; @@ -199,7 +199,7 @@ u16 fetch_word_imm(void) u16 fetched; DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdw)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); M.x86.R_IP += 2; INC_DECODED_INST_LEN(2); @@ -221,7 +221,7 @@ u32 fetch_long_imm(void) u32 fetched; DB( if (CHECK_IP_FETCH()) - x86emu_check_ip_access();) + x86emu_check_ip_access();) fetched = (*sys_rdl)(((u32)M.x86.R_CS << 4) + (M.x86.R_IP)); M.x86.R_IP += 4; INC_DECODED_INST_LEN(4); @@ -261,39 +261,39 @@ _INLINE u32 get_data_segment(void) { #define GET_SEGMENT(segment) switch (M.x86.mode & SYSMODE_SEGMASK) { - case 0: /* default case: use ds register */ + case 0: /* default case: use ds register */ case SYSMODE_SEGOVR_DS: case SYSMODE_SEGOVR_DS | SYSMODE_SEG_DS_SS: - return M.x86.R_DS; - case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ - return M.x86.R_SS; + return M.x86.R_DS; + case SYSMODE_SEG_DS_SS: /* non-overridden, use ss register */ + return M.x86.R_SS; case SYSMODE_SEGOVR_CS: case SYSMODE_SEGOVR_CS | SYSMODE_SEG_DS_SS: - return M.x86.R_CS; + return M.x86.R_CS; case SYSMODE_SEGOVR_ES: case SYSMODE_SEGOVR_ES | SYSMODE_SEG_DS_SS: - return M.x86.R_ES; + return M.x86.R_ES; case SYSMODE_SEGOVR_FS: case SYSMODE_SEGOVR_FS | SYSMODE_SEG_DS_SS: - return M.x86.R_FS; + return M.x86.R_FS; case SYSMODE_SEGOVR_GS: case SYSMODE_SEGOVR_GS | SYSMODE_SEG_DS_SS: - return M.x86.R_GS; + return M.x86.R_GS; case SYSMODE_SEGOVR_SS: case SYSMODE_SEGOVR_SS | SYSMODE_SEG_DS_SS: - return M.x86.R_SS; + return M.x86.R_SS; default: -#ifdef DEBUG - printk("error: should not happen: multiple overrides.\n"); +#ifdef DEBUG + printk("error: should not happen: multiple overrides.\n"); #endif - HALT_SYS(); - return 0; + HALT_SYS(); + return 0; } } /**************************************************************************** PARAMETERS: -offset - Offset to load data from +offset - Offset to load data from RETURNS: Byte value read from the absolute memory location. @@ -305,14 +305,14 @@ u8 fetch_data_byte( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdb)((get_data_segment() << 4) + offset); } /**************************************************************************** PARAMETERS: -offset - Offset to load data from +offset - Offset to load data from RETURNS: Word value read from the absolute memory location. @@ -324,14 +324,14 @@ u16 fetch_data_word( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdw)((get_data_segment() << 4) + offset); } /**************************************************************************** PARAMETERS: -offset - Offset to load data from +offset - Offset to load data from RETURNS: Long value read from the absolute memory location. @@ -343,7 +343,7 @@ u32 fetch_data_long( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif return (*sys_rdl)((get_data_segment() << 4) + offset); } @@ -351,7 +351,7 @@ u32 fetch_data_long( /**************************************************************************** PARAMETERS: segment - Segment to load data from -offset - Offset to load data from +offset - Offset to load data from RETURNS: Byte value read from the absolute memory location. @@ -364,7 +364,7 @@ u8 fetch_data_byte_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif return (*sys_rdb)(((u32)segment << 4) + offset); } @@ -372,7 +372,7 @@ u8 fetch_data_byte_abs( /**************************************************************************** PARAMETERS: segment - Segment to load data from -offset - Offset to load data from +offset - Offset to load data from RETURNS: Word value read from the absolute memory location. @@ -385,7 +385,7 @@ u16 fetch_data_word_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif return (*sys_rdw)(((u32)segment << 4) + offset); } @@ -393,7 +393,7 @@ u16 fetch_data_word_abs( /**************************************************************************** PARAMETERS: segment - Segment to load data from -offset - Offset to load data from +offset - Offset to load data from RETURNS: Long value read from the absolute memory location. @@ -406,15 +406,15 @@ u32 fetch_data_long_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif return (*sys_rdl)(((u32)segment << 4) + offset); } /**************************************************************************** PARAMETERS: -offset - Offset to store data at -val - Value to store +offset - Offset to store data at +val - Value to store REMARKS: Writes a word value to an segmented memory location. The segment used is @@ -428,15 +428,15 @@ void store_data_byte( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrb)((get_data_segment() << 4) + offset, val); } /**************************************************************************** PARAMETERS: -offset - Offset to store data at -val - Value to store +offset - Offset to store data at +val - Value to store REMARKS: Writes a word value to an segmented memory location. The segment used is @@ -450,15 +450,15 @@ void store_data_word( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrw)((get_data_segment() << 4) + offset, val); } /**************************************************************************** PARAMETERS: -offset - Offset to store data at -val - Value to store +offset - Offset to store data at +val - Value to store REMARKS: Writes a long value to an segmented memory location. The segment used is @@ -472,7 +472,7 @@ void store_data_long( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access((u16)get_data_segment(), offset); + x86emu_check_data_access((u16)get_data_segment(), offset); #endif (*sys_wrl)((get_data_segment() << 4) + offset, val); } @@ -480,8 +480,8 @@ void store_data_long( /**************************************************************************** PARAMETERS: segment - Segment to store data at -offset - Offset to store data at -val - Value to store +offset - Offset to store data at +val - Value to store REMARKS: Writes a byte value to an absolute memory location. @@ -495,7 +495,7 @@ void store_data_byte_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif (*sys_wrb)(((u32)segment << 4) + offset, val); } @@ -503,8 +503,8 @@ void store_data_byte_abs( /**************************************************************************** PARAMETERS: segment - Segment to store data at -offset - Offset to store data at -val - Value to store +offset - Offset to store data at +val - Value to store REMARKS: Writes a word value to an absolute memory location. @@ -518,7 +518,7 @@ void store_data_word_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif (*sys_wrw)(((u32)segment << 4) + offset, val); } @@ -526,8 +526,8 @@ void store_data_word_abs( /**************************************************************************** PARAMETERS: segment - Segment to store data at -offset - Offset to store data at -val - Value to store +offset - Offset to store data at +val - Value to store REMARKS: Writes a long value to an absolute memory location. @@ -541,7 +541,7 @@ void store_data_long_abs( { #ifdef DEBUG if (CHECK_DATA_ACCESS()) - x86emu_check_data_access(segment, offset); + x86emu_check_data_access(segment, offset); #endif (*sys_wrl)(((u32)segment << 4) + offset, val); } @@ -562,32 +562,32 @@ u8* decode_rm_byte_register( { switch (reg) { case 0: - DECODE_PRINTF("AL"); - return &M.x86.R_AL; + DECODE_PRINTF("AL"); + return &M.x86.R_AL; case 1: - DECODE_PRINTF("CL"); - return &M.x86.R_CL; + DECODE_PRINTF("CL"); + return &M.x86.R_CL; case 2: - DECODE_PRINTF("DL"); - return &M.x86.R_DL; + DECODE_PRINTF("DL"); + return &M.x86.R_DL; case 3: - DECODE_PRINTF("BL"); - return &M.x86.R_BL; + DECODE_PRINTF("BL"); + return &M.x86.R_BL; case 4: - DECODE_PRINTF("AH"); - return &M.x86.R_AH; + DECODE_PRINTF("AH"); + return &M.x86.R_AH; case 5: - DECODE_PRINTF("CH"); - return &M.x86.R_CH; + DECODE_PRINTF("CH"); + return &M.x86.R_CH; case 6: - DECODE_PRINTF("DH"); - return &M.x86.R_DH; + DECODE_PRINTF("DH"); + return &M.x86.R_DH; case 7: - DECODE_PRINTF("BH"); - return &M.x86.R_BH; + DECODE_PRINTF("BH"); + return &M.x86.R_BH; } HALT_SYS(); - return NULL; /* NOT REACHED OR REACHED ON ERROR */ + return NULL; /* NOT REACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -599,39 +599,39 @@ Pointer to the appropriate register REMARKS: Return a pointer to the register given by the R/RM field of the -modrm byte, for word operands. Also enables the decoding of instructions. +modrm byte, for word operands. Also enables the decoding of instructions. ****************************************************************************/ u16* decode_rm_word_register( int reg) { switch (reg) { case 0: - DECODE_PRINTF("AX"); - return &M.x86.R_AX; + DECODE_PRINTF("AX"); + return &M.x86.R_AX; case 1: - DECODE_PRINTF("CX"); - return &M.x86.R_CX; + DECODE_PRINTF("CX"); + return &M.x86.R_CX; case 2: - DECODE_PRINTF("DX"); - return &M.x86.R_DX; + DECODE_PRINTF("DX"); + return &M.x86.R_DX; case 3: - DECODE_PRINTF("BX"); - return &M.x86.R_BX; + DECODE_PRINTF("BX"); + return &M.x86.R_BX; case 4: - DECODE_PRINTF("SP"); - return &M.x86.R_SP; + DECODE_PRINTF("SP"); + return &M.x86.R_SP; case 5: - DECODE_PRINTF("BP"); - return &M.x86.R_BP; + DECODE_PRINTF("BP"); + return &M.x86.R_BP; case 6: - DECODE_PRINTF("SI"); - return &M.x86.R_SI; + DECODE_PRINTF("SI"); + return &M.x86.R_SI; case 7: - DECODE_PRINTF("DI"); - return &M.x86.R_DI; + DECODE_PRINTF("DI"); + return &M.x86.R_DI; } HALT_SYS(); - return NULL; /* NOTREACHED OR REACHED ON ERROR */ + return NULL; /* NOTREACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -643,39 +643,39 @@ Pointer to the appropriate register REMARKS: Return a pointer to the register given by the R/RM field of the -modrm byte, for dword operands. Also enables the decoding of instructions. +modrm byte, for dword operands. Also enables the decoding of instructions. ****************************************************************************/ u32* decode_rm_long_register( int reg) { switch (reg) { case 0: - DECODE_PRINTF("EAX"); - return &M.x86.R_EAX; + DECODE_PRINTF("EAX"); + return &M.x86.R_EAX; case 1: - DECODE_PRINTF("ECX"); - return &M.x86.R_ECX; + DECODE_PRINTF("ECX"); + return &M.x86.R_ECX; case 2: - DECODE_PRINTF("EDX"); - return &M.x86.R_EDX; + DECODE_PRINTF("EDX"); + return &M.x86.R_EDX; case 3: - DECODE_PRINTF("EBX"); - return &M.x86.R_EBX; + DECODE_PRINTF("EBX"); + return &M.x86.R_EBX; case 4: - DECODE_PRINTF("ESP"); - return &M.x86.R_ESP; + DECODE_PRINTF("ESP"); + return &M.x86.R_ESP; case 5: - DECODE_PRINTF("EBP"); - return &M.x86.R_EBP; + DECODE_PRINTF("EBP"); + return &M.x86.R_EBP; case 6: - DECODE_PRINTF("ESI"); - return &M.x86.R_ESI; + DECODE_PRINTF("ESI"); + return &M.x86.R_ESI; case 7: - DECODE_PRINTF("EDI"); - return &M.x86.R_EDI; + DECODE_PRINTF("EDI"); + return &M.x86.R_EDI; } HALT_SYS(); - return NULL; /* NOTREACHED OR REACHED ON ERROR */ + return NULL; /* NOTREACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -695,30 +695,30 @@ u16* decode_rm_seg_register( { switch (reg) { case 0: - DECODE_PRINTF("ES"); - return &M.x86.R_ES; + DECODE_PRINTF("ES"); + return &M.x86.R_ES; case 1: - DECODE_PRINTF("CS"); - return &M.x86.R_CS; + DECODE_PRINTF("CS"); + return &M.x86.R_CS; case 2: - DECODE_PRINTF("SS"); - return &M.x86.R_SS; + DECODE_PRINTF("SS"); + return &M.x86.R_SS; case 3: - DECODE_PRINTF("DS"); - return &M.x86.R_DS; + DECODE_PRINTF("DS"); + return &M.x86.R_DS; case 4: - DECODE_PRINTF("FS"); - return &M.x86.R_FS; + DECODE_PRINTF("FS"); + return &M.x86.R_FS; case 5: - DECODE_PRINTF("GS"); - return &M.x86.R_GS; + DECODE_PRINTF("GS"); + return &M.x86.R_GS; case 6: case 7: - DECODE_PRINTF("ILLEGAL SEGREG"); - break; + DECODE_PRINTF("ILLEGAL SEGREG"); + break; } HALT_SYS(); - return NULL; /* NOT REACHED OR REACHED ON ERROR */ + return NULL; /* NOT REACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -739,38 +739,38 @@ unsigned decode_sib_si( { scale = 1 << scale; if (scale > 1) { - DECODE_PRINTF2("[%d*", scale); + DECODE_PRINTF2("[%d*", scale); } else { - DECODE_PRINTF("["); + DECODE_PRINTF("["); } switch (index) { case 0: - DECODE_PRINTF("EAX]"); - return M.x86.R_EAX * index; + DECODE_PRINTF("EAX]"); + return M.x86.R_EAX * index; case 1: - DECODE_PRINTF("ECX]"); - return M.x86.R_ECX * index; + DECODE_PRINTF("ECX]"); + return M.x86.R_ECX * index; case 2: - DECODE_PRINTF("EDX]"); - return M.x86.R_EDX * index; + DECODE_PRINTF("EDX]"); + return M.x86.R_EDX * index; case 3: - DECODE_PRINTF("EBX]"); - return M.x86.R_EBX * index; + DECODE_PRINTF("EBX]"); + return M.x86.R_EBX * index; case 4: - DECODE_PRINTF("0]"); - return 0; + DECODE_PRINTF("0]"); + return 0; case 5: - DECODE_PRINTF("EBP]"); - return M.x86.R_EBP * index; + DECODE_PRINTF("EBP]"); + return M.x86.R_EBP * index; case 6: - DECODE_PRINTF("ESI]"); - return M.x86.R_ESI * index; + DECODE_PRINTF("ESI]"); + return M.x86.R_ESI * index; case 7: - DECODE_PRINTF("EDI]"); - return M.x86.R_EDI * index; + DECODE_PRINTF("EDI]"); + return M.x86.R_EDI * index; } HALT_SYS(); - return 0; /* NOT REACHED OR REACHED ON ERROR */ + return 0; /* NOT REACHED OR REACHED ON ERROR */ } /**************************************************************************** @@ -795,58 +795,58 @@ unsigned decode_sib_address( switch (base) { case 0: - DECODE_PRINTF("[EAX]"); - offset = M.x86.R_EAX; - break; + DECODE_PRINTF("[EAX]"); + offset = M.x86.R_EAX; + break; case 1: - DECODE_PRINTF("[ECX]"); - offset = M.x86.R_ECX; - break; + DECODE_PRINTF("[ECX]"); + offset = M.x86.R_ECX; + break; case 2: - DECODE_PRINTF("[EDX]"); - offset = M.x86.R_EDX; - break; + DECODE_PRINTF("[EDX]"); + offset = M.x86.R_EDX; + break; case 3: - DECODE_PRINTF("[EBX]"); - offset = M.x86.R_EBX; - break; + DECODE_PRINTF("[EBX]"); + offset = M.x86.R_EBX; + break; case 4: - DECODE_PRINTF("[ESP]"); - offset = M.x86.R_ESP; - break; + DECODE_PRINTF("[ESP]"); + offset = M.x86.R_ESP; + break; case 5: - switch (mod) { - case 0: - displacement = (s32)fetch_long_imm(); - DECODE_PRINTF2("[%d]", displacement); - offset = displacement; - break; - case 1: - displacement = (s8)fetch_byte_imm(); - DECODE_PRINTF2("[%d][EBP]", displacement); - offset = M.x86.R_EBP + displacement; - break; - case 2: - displacement = (s32)fetch_long_imm(); - DECODE_PRINTF2("[%d][EBP]", displacement); - offset = M.x86.R_EBP + displacement; - break; - default: - HALT_SYS(); - } - DECODE_PRINTF("[EAX]"); - offset = M.x86.R_EAX; - break; + switch (mod) { + case 0: + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d]", displacement); + offset = displacement; + break; + case 1: + displacement = (s8)fetch_byte_imm(); + DECODE_PRINTF2("[%d][EBP]", displacement); + offset = M.x86.R_EBP + displacement; + break; + case 2: + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d][EBP]", displacement); + offset = M.x86.R_EBP + displacement; + break; + default: + HALT_SYS(); + } + DECODE_PRINTF("[EAX]"); + offset = M.x86.R_EAX; + break; case 6: - DECODE_PRINTF("[ESI]"); - offset = M.x86.R_ESI; - break; + DECODE_PRINTF("[ESI]"); + offset = M.x86.R_ESI; + break; case 7: - DECODE_PRINTF("[EDI]"); - offset = M.x86.R_EDI; - break; + DECODE_PRINTF("[EDI]"); + offset = M.x86.R_EDI; + break; default: - HALT_SYS(); + HALT_SYS(); } offset += decode_sib_si(ss, index); return offset; @@ -864,14 +864,14 @@ REMARKS: Return the offset given by mod=00 addressing. Also enables the decoding of instructions. -NOTE: The code which specifies the corresponding segment (ds vs ss) - below in the case of [BP+..]. The assumption here is that at the - point that this subroutine is called, the bit corresponding to - SYSMODE_SEG_DS_SS will be zero. After every instruction - except the segment override instructions, this bit (as well - as any bits indicating segment overrides) will be clear. So - if a SS access is needed, set this bit. Otherwise, DS access - occurs (unless any of the segment override bits are set). +NOTE: The code which specifies the corresponding segment (ds vs ss) + below in the case of [BP+..]. The assumption here is that at the + point that this subroutine is called, the bit corresponding to + SYSMODE_SEG_DS_SS will be zero. After every instruction + except the segment override instructions, this bit (as well + as any bits indicating segment overrides) will be clear. So + if a SS access is needed, set this bit. Otherwise, DS access + occurs (unless any of the segment override bits are set). ****************************************************************************/ unsigned decode_rm00_address( int rm) @@ -879,64 +879,64 @@ unsigned decode_rm00_address( unsigned offset; if (M.x86.mode & SYSMODE_PREFIX_ADDR) { - /* 32-bit addressing */ - switch (rm) { - case 0: - DECODE_PRINTF("[EAX]"); - return M.x86.R_EAX; - case 1: - DECODE_PRINTF("[ECX]"); - return M.x86.R_ECX; - case 2: - DECODE_PRINTF("[EDX]"); - return M.x86.R_EDX; - case 3: - DECODE_PRINTF("[EBX]"); - return M.x86.R_EBX; - case 4: - return decode_sib_address(0); - case 5: - offset = fetch_long_imm(); - DECODE_PRINTF2("[%08x]", offset); - return offset; - case 6: - DECODE_PRINTF("[ESI]"); - return M.x86.R_ESI; - case 7: - DECODE_PRINTF("[EDI]"); - return M.x86.R_EDI; - } + /* 32-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[EAX]"); + return M.x86.R_EAX; + case 1: + DECODE_PRINTF("[ECX]"); + return M.x86.R_ECX; + case 2: + DECODE_PRINTF("[EDX]"); + return M.x86.R_EDX; + case 3: + DECODE_PRINTF("[EBX]"); + return M.x86.R_EBX; + case 4: + return decode_sib_address(0); + case 5: + offset = fetch_long_imm(); + DECODE_PRINTF2("[%08x]", offset); + return offset; + case 6: + DECODE_PRINTF("[ESI]"); + return M.x86.R_ESI; + case 7: + DECODE_PRINTF("[EDI]"); + return M.x86.R_EDI; + } } else { - /* 16-bit addressing */ - switch (rm) { - case 0: - DECODE_PRINTF("[BX+SI]"); - return (M.x86.R_BX + M.x86.R_SI) & 0xffff; - case 1: - DECODE_PRINTF("[BX+DI]"); - return (M.x86.R_BX + M.x86.R_DI) & 0xffff; - case 2: - DECODE_PRINTF("[BP+SI]"); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_SI) & 0xffff; - case 3: - DECODE_PRINTF("[BP+DI]"); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_DI) & 0xffff; - case 4: - DECODE_PRINTF("[SI]"); - return M.x86.R_SI; - case 5: - DECODE_PRINTF("[DI]"); - return M.x86.R_DI; - case 6: - offset = fetch_word_imm(); - DECODE_PRINTF2("[%04x]", offset); - return offset; - case 7: - DECODE_PRINTF("[BX]"); - return M.x86.R_BX; - } + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF("[BX+SI]"); + return (M.x86.R_BX + M.x86.R_SI) & 0xffff; + case 1: + DECODE_PRINTF("[BX+DI]"); + return (M.x86.R_BX + M.x86.R_DI) & 0xffff; + case 2: + DECODE_PRINTF("[BP+SI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI) & 0xffff; + case 3: + DECODE_PRINTF("[BP+DI]"); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI) & 0xffff; + case 4: + DECODE_PRINTF("[SI]"); + return M.x86.R_SI; + case 5: + DECODE_PRINTF("[DI]"); + return M.x86.R_DI; + case 6: + offset = fetch_word_imm(); + DECODE_PRINTF2("[%04x]", offset); + return offset; + case 7: + DECODE_PRINTF("[BX]"); + return M.x86.R_BX; + } } HALT_SYS(); return 0; @@ -959,76 +959,76 @@ unsigned decode_rm01_address( int displacement; if (M.x86.mode & SYSMODE_PREFIX_ADDR) { - /* 32-bit addressing */ - if (rm != 4) - displacement = (s8)fetch_byte_imm(); - else - displacement = 0; - - switch (rm) { - case 0: - DECODE_PRINTF2("%d[EAX]", displacement); - return M.x86.R_EAX + displacement; - case 1: - DECODE_PRINTF2("%d[ECX]", displacement); - return M.x86.R_ECX + displacement; - case 2: - DECODE_PRINTF2("%d[EDX]", displacement); - return M.x86.R_EDX + displacement; - case 3: - DECODE_PRINTF2("%d[EBX]", displacement); - return M.x86.R_EBX + displacement; - case 4: { - int offset = decode_sib_address(1); - displacement = (s8)fetch_byte_imm(); - DECODE_PRINTF2("[%d]", displacement); - return offset + displacement; - } - case 5: - DECODE_PRINTF2("%d[EBP]", displacement); - return M.x86.R_EBP + displacement; - case 6: - DECODE_PRINTF2("%d[ESI]", displacement); - return M.x86.R_ESI + displacement; - case 7: - DECODE_PRINTF2("%d[EDI]", displacement); - return M.x86.R_EDI + displacement; - } + /* 32-bit addressing */ + if (rm != 4) + displacement = (s8)fetch_byte_imm(); + else + displacement = 0; + + switch (rm) { + case 0: + DECODE_PRINTF2("%d[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: { + int offset = decode_sib_address(1); + displacement = (s8)fetch_byte_imm(); + DECODE_PRINTF2("[%d]", displacement); + return offset + displacement; + } + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } } else { - /* 16-bit addressing */ - displacement = (s8)fetch_byte_imm(); - switch (rm) { - case 0: - DECODE_PRINTF2("%d[BX+SI]", displacement); - return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; - case 1: - DECODE_PRINTF2("%d[BX+DI]", displacement); - return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; - case 2: - DECODE_PRINTF2("%d[BP+SI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; - case 3: - DECODE_PRINTF2("%d[BP+DI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; - case 4: - DECODE_PRINTF2("%d[SI]", displacement); - return (M.x86.R_SI + displacement) & 0xffff; - case 5: - DECODE_PRINTF2("%d[DI]", displacement); - return (M.x86.R_DI + displacement) & 0xffff; - case 6: - DECODE_PRINTF2("%d[BP]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + displacement) & 0xffff; - case 7: - DECODE_PRINTF2("%d[BX]", displacement); - return (M.x86.R_BX + displacement) & 0xffff; - } + /* 16-bit addressing */ + displacement = (s8)fetch_byte_imm(); + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } } HALT_SYS(); - return 0; /* SHOULD NOT HAPPEN */ + return 0; /* SHOULD NOT HAPPEN */ } /**************************************************************************** @@ -1046,82 +1046,81 @@ unsigned decode_rm10_address( int rm) { if (M.x86.mode & SYSMODE_PREFIX_ADDR) { - int displacement; - - /* 32-bit addressing */ - if (rm != 4) - displacement = (s32)fetch_long_imm(); - else - displacement = 0; - - switch (rm) { - case 0: - DECODE_PRINTF2("%d[EAX]", displacement); - return M.x86.R_EAX + displacement; - case 1: - DECODE_PRINTF2("%d[ECX]", displacement); - return M.x86.R_ECX + displacement; - case 2: - DECODE_PRINTF2("%d[EDX]", displacement); - return M.x86.R_EDX + displacement; - case 3: - DECODE_PRINTF2("%d[EBX]", displacement); - return M.x86.R_EBX + displacement; - case 4: { - int offset = decode_sib_address(2); - displacement = (s32)fetch_long_imm(); - DECODE_PRINTF2("[%d]", displacement); - return offset + displacement; - } - case 5: - DECODE_PRINTF2("%d[EBP]", displacement); - return M.x86.R_EBP + displacement; - case 6: - DECODE_PRINTF2("%d[ESI]", displacement); - return M.x86.R_ESI + displacement; - case 7: - DECODE_PRINTF2("%d[EDI]", displacement); - return M.x86.R_EDI + displacement; - } + int displacement; + + /* 32-bit addressing */ + if (rm != 4) + displacement = (s32)fetch_long_imm(); + else + displacement = 0; + + switch (rm) { + case 0: + DECODE_PRINTF2("%d[EAX]", displacement); + return M.x86.R_EAX + displacement; + case 1: + DECODE_PRINTF2("%d[ECX]", displacement); + return M.x86.R_ECX + displacement; + case 2: + DECODE_PRINTF2("%d[EDX]", displacement); + return M.x86.R_EDX + displacement; + case 3: + DECODE_PRINTF2("%d[EBX]", displacement); + return M.x86.R_EBX + displacement; + case 4: { + int offset = decode_sib_address(2); + displacement = (s32)fetch_long_imm(); + DECODE_PRINTF2("[%d]", displacement); + return offset + displacement; + } + case 5: + DECODE_PRINTF2("%d[EBP]", displacement); + return M.x86.R_EBP + displacement; + case 6: + DECODE_PRINTF2("%d[ESI]", displacement); + return M.x86.R_ESI + displacement; + case 7: + DECODE_PRINTF2("%d[EDI]", displacement); + return M.x86.R_EDI + displacement; + } } else { - int displacement = (s16)fetch_word_imm(); - - /* 16-bit addressing */ - switch (rm) { - case 0: - DECODE_PRINTF2("%d[BX+SI]", displacement); - return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; - case 1: - DECODE_PRINTF2("%d[BX+DI]", displacement); - return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; - case 2: - DECODE_PRINTF2("%d[BP+SI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; - case 3: - DECODE_PRINTF2("%d[BP+DI]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; - case 4: - DECODE_PRINTF2("%d[SI]", displacement); - return (M.x86.R_SI + displacement) & 0xffff; - case 5: - DECODE_PRINTF2("%d[DI]", displacement); - return (M.x86.R_DI + displacement) & 0xffff; - case 6: - DECODE_PRINTF2("%d[BP]", displacement); - M.x86.mode |= SYSMODE_SEG_DS_SS; - return (M.x86.R_BP + displacement) & 0xffff; - case 7: - DECODE_PRINTF2("%d[BX]", displacement); - return (M.x86.R_BX + displacement) & 0xffff; - } + int displacement = (s16)fetch_word_imm(); + + /* 16-bit addressing */ + switch (rm) { + case 0: + DECODE_PRINTF2("%d[BX+SI]", displacement); + return (M.x86.R_BX + M.x86.R_SI + displacement) & 0xffff; + case 1: + DECODE_PRINTF2("%d[BX+DI]", displacement); + return (M.x86.R_BX + M.x86.R_DI + displacement) & 0xffff; + case 2: + DECODE_PRINTF2("%d[BP+SI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_SI + displacement) & 0xffff; + case 3: + DECODE_PRINTF2("%d[BP+DI]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + M.x86.R_DI + displacement) & 0xffff; + case 4: + DECODE_PRINTF2("%d[SI]", displacement); + return (M.x86.R_SI + displacement) & 0xffff; + case 5: + DECODE_PRINTF2("%d[DI]", displacement); + return (M.x86.R_DI + displacement) & 0xffff; + case 6: + DECODE_PRINTF2("%d[BP]", displacement); + M.x86.mode |= SYSMODE_SEG_DS_SS; + return (M.x86.R_BP + displacement) & 0xffff; + case 7: + DECODE_PRINTF2("%d[BX]", displacement); + return (M.x86.R_BX + displacement) & 0xffff; + } } HALT_SYS(); - return 0; /* SHOULD NOT HAPPEN */ + return 0; /* SHOULD NOT HAPPEN */ } - /**************************************************************************** PARAMETERS: mod - modifier @@ -1143,6 +1142,3 @@ unsigned decode_rmXX_address(int mod, int rm) return decode_rm01_address(rm); return decode_rm10_address(rm); } - - - diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index 632979dd574..d1380ceec00 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -4,9 +4,9 @@ * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. * Jason Jin * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -16,7 +16,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -32,13 +32,13 @@ * * Language: ANSI C * Environment: Any -* Developer: Kendall Bennett +* Developer: Kendall Bennett * -* Description: This file includes subroutines to implement the decoding -* and emulation of all the x86 processor instructions. +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 processor instructions. * * There are approximately 250 subroutines in here, which correspond -* to the 256 byte-"opcodes" found on the 8086. The table which +* to the 256 byte-"opcodes" found on the 8086. The table which * dispatches this is found in the files optab.[ch]. * * Each opcode proc has a comment preceeding it which gives it's table @@ -48,14 +48,14 @@ * DECODE_PRINTF2), debugging (TRACE_REGS, SINGLE_STEP), and misc * functions (START_OF_INSTR, END_OF_INSTR). * -* Many of the procedures are *VERY* similar in coding. This has +* Many of the procedures are *VERY* similar in coding. This has * allowed for a very large amount of code to be generated in a fairly * short amount of time (i.e. cut, paste, and modify). The result is * that much of the code below could have been folded into subroutines * for a large reduction in size of this file. The downside would be * that there would be a penalty in execution speed. The file could * also have been *MUCH* larger by inlining certain functions which -* were called. This could have resulted even faster execution. The +* were called. This could have resulted even faster execution. The * prime directive I used to decide whether to inline the code or to * modularize it, was basically: 1) no unnecessary subroutine calls, * 2) no routines more than about 200 lines in size, and 3) modularize @@ -88,38 +88,38 @@ static char *x86emu_GenOpName[8] = { /* used by several opcodes */ static u8 (*genop_byte_operation[])(u8 d, u8 s) __attribute__ ((section(".got2"))) = { - add_byte, /* 00 */ - or_byte, /* 01 */ - adc_byte, /* 02 */ - sbb_byte, /* 03 */ - and_byte, /* 04 */ - sub_byte, /* 05 */ - xor_byte, /* 06 */ - cmp_byte, /* 07 */ + add_byte, /* 00 */ + or_byte, /* 01 */ + adc_byte, /* 02 */ + sbb_byte, /* 03 */ + and_byte, /* 04 */ + sub_byte, /* 05 */ + xor_byte, /* 06 */ + cmp_byte, /* 07 */ }; static u16 (*genop_word_operation[])(u16 d, u16 s) __attribute__ ((section(".got2"))) = { - add_word, /*00 */ - or_word, /*01 */ - adc_word, /*02 */ - sbb_word, /*03 */ - and_word, /*04 */ - sub_word, /*05 */ - xor_word, /*06 */ - cmp_word, /*07 */ + add_word, /*00 */ + or_word, /*01 */ + adc_word, /*02 */ + sbb_word, /*03 */ + and_word, /*04 */ + sub_word, /*05 */ + xor_word, /*06 */ + cmp_word, /*07 */ }; static u32 (*genop_long_operation[])(u32 d, u32 s) __attribute__ ((section(".got2"))) = { - add_long, /*00 */ - or_long, /*01 */ - adc_long, /*02 */ - sbb_long, /*03 */ - and_long, /*04 */ - sub_long, /*05 */ - xor_long, /*06 */ - cmp_long, /*07 */ + add_long, /*00 */ + or_long, /*01 */ + adc_long, /*02 */ + sbb_long, /*03 */ + and_long, /*04 */ + sub_long, /*05 */ + xor_long, /*06 */ + cmp_long, /*07 */ }; /* used by opcodes 80, c0, d0, and d2. */ @@ -131,7 +131,7 @@ static u8(*opcD0_byte_operation[])(u8 d, u8 s) __attribute__ ((section(".got2")) rcr_byte, shl_byte, shr_byte, - shl_byte, /* sal_byte === shl_byte by definition */ + shl_byte, /* sal_byte === shl_byte by definition */ sar_byte, }; @@ -144,7 +144,7 @@ static u16(*opcD1_word_operation[])(u16 s, u8 d) __attribute__ ((section(".got2" rcr_word, shl_word, shr_word, - shl_word, /* sal_byte === shl_byte by definition */ + shl_word, /* sal_byte === shl_byte by definition */ sar_word, }; @@ -157,7 +157,7 @@ static u32 (*opcD1_long_operation[])(u32 s, u8 d) __attribute__ ((section(".got2 rcr_long, shl_long, shr_long, - shl_long, /* sal_byte === shl_byte by definition */ + shl_long, /* sal_byte === shl_byte by definition */ sar_long, }; @@ -180,21 +180,21 @@ void x86emuOp_illegal_op( { START_OF_INSTR(); if (M.x86.R_SP != 0) { - DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); - TRACE_REGS(); - DB( printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", - M.x86.R_CS, M.x86.R_IP-1,op1)); - HALT_SYS(); - } + DECODE_PRINTF("ILLEGAL X86 OPCODE\n"); + TRACE_REGS(); + DB( printk("%04x:%04x: %02X ILLEGAL X86 OPCODE!\n", + M.x86.R_CS, M.x86.R_IP-1,op1)); + HALT_SYS(); + } else { - /* If we get here, it means the stack pointer is back to zero - * so we are just returning from an emulator service call - * so therte is no need to display an error message. We trap - * the emulator with an 0xF1 opcode to finish the service - * call. - */ - X86EMU_halt_sys(); - } + /* If we get here, it means the stack pointer is back to zero + * so we are just returning from an emulator service call + * so therte is no need to display an error message. We trap + * the emulator with an 0xF1 opcode to finish the service + * call. + */ + X86EMU_halt_sys(); + } END_OF_INSTR(); } @@ -216,24 +216,24 @@ void x86emuOp_genop_byte_RM_R(u8 op1) DECODE_PRINTF("\t"); FETCH_DECODE_MODRM(mod, rh, rl); if(mod<3) - { destoffset = decode_rmXX_address(mod,rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = genop_byte_operation[op1](destval, *srcreg); - store_data_byte(destoffset, destval); - } + { destoffset = decode_rmXX_address(mod,rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_byte_operation[op1](destval, *srcreg); + store_data_byte(destoffset, destval); + } else - { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_byte_operation[op1](*destreg, *srcreg); - } + { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_byte_operation[op1](*destreg, *srcreg); + } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -255,50 +255,50 @@ void x86emuOp_genop_word_RM_R(u8 op1) FETCH_DECODE_MODRM(mod, rh, rl); if(mod<3) { - destoffset = decode_rmXX_address(mod,rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = genop_long_operation[op1](destval, *srcreg); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = genop_word_operation[op1](destval, *srcreg); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_long_operation[op1](*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_word_operation[op1](*destreg, *srcreg); - } + destoffset = decode_rmXX_address(mod,rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_long_operation[op1](destval, *srcreg); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = genop_word_operation[op1](destval, *srcreg); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_long_operation[op1](*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, *srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -322,15 +322,15 @@ void x86emuOp_genop_byte_R_RM(u8 op1) DECODE_PRINTF("\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod,rl); - srcval = fetch_data_byte(srcoffset); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - srcval = *srcreg; + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod,rl); + srcval = fetch_data_byte(srcoffset); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + srcval = *srcreg; } DECODE_PRINTF("\n"); TRACE_AND_STEP(); @@ -358,40 +358,40 @@ void x86emuOp_genop_word_R_RM(u8 op1) DECODE_PRINTF("\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod,rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - destreg32 = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg32 = genop_long_operation[op1](*destreg32, srcval); - } else { - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_word_operation[op1](*destreg, srcval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - destreg32 = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg32 = genop_long_operation[op1](*destreg32, *srcreg); - } else { - u16 *srcreg; - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = genop_word_operation[op1](*destreg, *srcreg); - } + srcoffset = decode_rmXX_address(mod,rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + destreg32 = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg32 = genop_long_operation[op1](*destreg32, srcval); + } else { + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, srcval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + destreg32 = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg32 = genop_long_operation[op1](*destreg32, *srcreg); + } else { + u16 *srcreg; + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = genop_word_operation[op1](*destreg, *srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -430,20 +430,20 @@ void x86emuOp_genop_word_AX_IMM(u8 op1) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF(x86emu_GenOpName[op1]); - DECODE_PRINTF("\tEAX,"); - srcval = fetch_long_imm(); + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\tEAX,"); + srcval = fetch_long_imm(); } else { - DECODE_PRINTF(x86emu_GenOpName[op1]); - DECODE_PRINTF("\tAX,"); - srcval = fetch_word_imm(); + DECODE_PRINTF(x86emu_GenOpName[op1]); + DECODE_PRINTF("\tAX,"); + srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = genop_long_operation[op1](M.x86.R_EAX, srcval); + M.x86.R_EAX = genop_long_operation[op1](M.x86.R_EAX, srcval); } else { - M.x86.R_AX = genop_word_operation[op1](M.x86.R_AX, (u16)srcval); + M.x86.R_AX = genop_word_operation[op1](M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -683,17 +683,17 @@ void x86emuOp_inc_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("INC\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = inc_long(*reg); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = inc_long(*reg); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = inc_word(*reg); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = inc_word(*reg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -709,17 +709,17 @@ void x86emuOp_dec_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("DEC\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = dec_long(*reg); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = dec_long(*reg); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = dec_word(*reg); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = dec_word(*reg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -735,17 +735,17 @@ void x86emuOp_push_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("PUSH\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_long(*reg); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*reg); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(*reg); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*reg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -761,17 +761,17 @@ void x86emuOp_pop_register(u8 op1) op1 &= 0x7; DECODE_PRINTF("POP\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg; - reg = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = pop_long(); + u32 *reg; + reg = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = pop_long(); } else { - u16 *reg; - reg = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *reg = pop_word(); + u16 *reg; + reg = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *reg = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -785,33 +785,33 @@ void x86emuOp_push_all(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSHAD\n"); + DECODE_PRINTF("PUSHAD\n"); } else { - DECODE_PRINTF("PUSHA\n"); + DECODE_PRINTF("PUSHA\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 old_sp = M.x86.R_ESP; - - push_long(M.x86.R_EAX); - push_long(M.x86.R_ECX); - push_long(M.x86.R_EDX); - push_long(M.x86.R_EBX); - push_long(old_sp); - push_long(M.x86.R_EBP); - push_long(M.x86.R_ESI); - push_long(M.x86.R_EDI); + u32 old_sp = M.x86.R_ESP; + + push_long(M.x86.R_EAX); + push_long(M.x86.R_ECX); + push_long(M.x86.R_EDX); + push_long(M.x86.R_EBX); + push_long(old_sp); + push_long(M.x86.R_EBP); + push_long(M.x86.R_ESI); + push_long(M.x86.R_EDI); } else { - u16 old_sp = M.x86.R_SP; - - push_word(M.x86.R_AX); - push_word(M.x86.R_CX); - push_word(M.x86.R_DX); - push_word(M.x86.R_BX); - push_word(old_sp); - push_word(M.x86.R_BP); - push_word(M.x86.R_SI); - push_word(M.x86.R_DI); + u16 old_sp = M.x86.R_SP; + + push_word(M.x86.R_AX); + push_word(M.x86.R_CX); + push_word(M.x86.R_DX); + push_word(M.x86.R_BX); + push_word(old_sp); + push_word(M.x86.R_BP); + push_word(M.x86.R_SI); + push_word(M.x86.R_DI); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -825,36 +825,36 @@ void x86emuOp_pop_all(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POPAD\n"); + DECODE_PRINTF("POPAD\n"); } else { - DECODE_PRINTF("POPA\n"); + DECODE_PRINTF("POPA\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EDI = pop_long(); - M.x86.R_ESI = pop_long(); - M.x86.R_EBP = pop_long(); - M.x86.R_ESP += 4; /* skip ESP */ - M.x86.R_EBX = pop_long(); - M.x86.R_EDX = pop_long(); - M.x86.R_ECX = pop_long(); - M.x86.R_EAX = pop_long(); + M.x86.R_EDI = pop_long(); + M.x86.R_ESI = pop_long(); + M.x86.R_EBP = pop_long(); + M.x86.R_ESP += 4; /* skip ESP */ + M.x86.R_EBX = pop_long(); + M.x86.R_EDX = pop_long(); + M.x86.R_ECX = pop_long(); + M.x86.R_EAX = pop_long(); } else { - M.x86.R_DI = pop_word(); - M.x86.R_SI = pop_word(); - M.x86.R_BP = pop_word(); - M.x86.R_SP += 2; /* skip SP */ - M.x86.R_BX = pop_word(); - M.x86.R_DX = pop_word(); - M.x86.R_CX = pop_word(); - M.x86.R_AX = pop_word(); + M.x86.R_DI = pop_word(); + M.x86.R_SI = pop_word(); + M.x86.R_BP = pop_word(); + M.x86.R_SP += 2; /* skip SP */ + M.x86.R_BX = pop_word(); + M.x86.R_DX = pop_word(); + M.x86.R_CX = pop_word(); + M.x86.R_AX = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } -/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ -/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x62 ILLEGAL OP, calls x86emuOp_illegal_op() */ +/*opcode 0x63 ILLEGAL OP, calls x86emuOp_illegal_op() */ /**************************************************************************** REMARKS: @@ -928,16 +928,16 @@ void x86emuOp_push_word_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - imm = fetch_long_imm(); + imm = fetch_long_imm(); } else { - imm = fetch_word_imm(); + imm = fetch_word_imm(); } DECODE_PRINTF2("PUSH\t%x\n", imm); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(imm); + push_long(imm); } else { - push_word((u16)imm); + push_word((u16)imm); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -956,95 +956,95 @@ void x86emuOp_imul_word_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("IMUL\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - s32 imm; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_long(srcoffset); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - s16 imm; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_word(srcoffset); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)srcval * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 res_lo,res_hi; - s32 imm; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg,*srcreg; - u32 res; - s16 imm; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - res = (s16)*srcreg * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + s32 imm; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + s16 imm; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + res = (s16)*srcreg * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1075,98 +1075,98 @@ void x86emuOp_imul_byte_IMM(u8 X86EMU_UNUSED(op1)) { int mod, rl, rh; uint srcoffset; - s8 imm; + s8 imm; START_OF_INSTR(); DECODE_PRINTF("IMUL\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_long(srcoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcval = fetch_data_word(srcoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)srcval * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); - if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || - (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg,*srcreg; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", (s32)imm); - TRACE_AND_STEP(); - res = (s16)*srcreg * (s16)imm; - if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || - (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } - *destreg = (u16)res; - } + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_long(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)srcval,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcval = fetch_data_word(srcoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)srcval * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*srcreg,(s32)imm); + if ((((res_lo & 0x80000000) == 0) && (res_hi == 0x00000000)) || + (((res_lo & 0x80000000) != 0) && (res_hi == 0xFFFFFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", (s32)imm); + TRACE_AND_STEP(); + res = (s16)*srcreg * (s16)imm; + if ((((res & 0x8000) == 0) && ((res >> 16) == 0x0000)) || + (((res & 0x8000) != 0) && ((res >> 16) == 0xFFFF))) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } else { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } + *destreg = (u16)res; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1194,11 +1194,11 @@ void x86emuOp_ins_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INSD\n"); - ins(4); + DECODE_PRINTF("INSD\n"); + ins(4); } else { - DECODE_PRINTF("INSW\n"); - ins(2); + DECODE_PRINTF("INSW\n"); + ins(2); } TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); @@ -1227,11 +1227,11 @@ void x86emuOp_outs_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("OUTSD\n"); - outs(4); + DECODE_PRINTF("OUTSD\n"); + outs(4); } else { - DECODE_PRINTF("OUTSW\n"); - outs(2); + DECODE_PRINTF("OUTSW\n"); + outs(2); } TRACE_AND_STEP(); DECODE_CLEAR_SEGOVR(); @@ -1258,7 +1258,7 @@ void x86emuOp_jump_near_cond(u8 op1) DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (cond) - M.x86.R_IP = target; + M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -1276,7 +1276,7 @@ void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) u8 destval; /* - * Weirdo special case instruction format. Part of the opcode + * Weirdo special case instruction format. Part of the opcode * held below in "RH". Doubly nested case would result, except * that the decoded instruction */ @@ -1284,61 +1284,61 @@ void x86emuOp_opc80_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_byte_operation[rh]) (destval, imm); - if (rh != 7) - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_byte_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_byte_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_byte_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1354,7 +1354,7 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) uint destoffset; /* - * Weirdo special case instruction format. Part of the opcode + * Weirdo special case instruction format. Part of the opcode * held below in "RH". Doubly nested case would result, except * that the decoded instruction */ @@ -1362,37 +1362,37 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* @@ -1400,57 +1400,57 @@ void x86emuOp_opc81_word_RM_IMM(u8 X86EMU_UNUSED(op1)) * mode. */ if (mod < 3) { - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,imm; - - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - imm = fetch_long_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_long_operation[rh]) (destval, imm); - if (rh != 7) - store_data_long(destoffset, destval); - } else { - u16 destval,imm; - - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - imm = fetch_word_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_word_operation[rh]) (destval, imm); - if (rh != 7) - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 destval,imm; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_long_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_long_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; - } else { - u16 *destreg; - u16 destval,imm; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - imm = fetch_word_imm(); - DECODE_PRINTF2("%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_word_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; - } + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_long_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + imm = fetch_word_imm(); + DECODE_PRINTF2("%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1469,7 +1469,7 @@ void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) u8 destval; /* - * Weirdo special case instruction format. Part of the opcode + * Weirdo special case instruction format. Part of the opcode * held below in "RH". Doubly nested case would result, except * that the decoded instruction Similar to opcode 81, except that * the immediate byte is sign extended to a word length. @@ -1478,58 +1478,58 @@ void x86emuOp_opc82_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_byte(destoffset); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_byte_operation[rh]) (destval, imm); - if (rh != 7) - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_byte_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_byte(destoffset); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (destval, imm); + if (rh != 7) + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_byte_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1545,7 +1545,7 @@ void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) uint destoffset; /* - * Weirdo special case instruction format. Part of the opcode + * Weirdo special case instruction format. Part of the opcode * held below in "RH". Doubly nested case would result, except * that the decoded instruction Similar to opcode 81, except that * the immediate byte is sign extended to a word length. @@ -1554,89 +1554,89 @@ void x86emuOp_opc83_word_RM_IMM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ switch (rh) { - case 0: - DECODE_PRINTF("ADD\t"); - break; - case 1: - DECODE_PRINTF("OR\t"); - break; - case 2: - DECODE_PRINTF("ADC\t"); - break; - case 3: - DECODE_PRINTF("SBB\t"); - break; - case 4: - DECODE_PRINTF("AND\t"); - break; - case 5: - DECODE_PRINTF("SUB\t"); - break; - case 6: - DECODE_PRINTF("XOR\t"); - break; - case 7: - DECODE_PRINTF("CMP\t"); - break; - } + case 0: + DECODE_PRINTF("ADD\t"); + break; + case 1: + DECODE_PRINTF("OR\t"); + break; + case 2: + DECODE_PRINTF("ADC\t"); + break; + case 3: + DECODE_PRINTF("SBB\t"); + break; + case 4: + DECODE_PRINTF("AND\t"); + break; + case 5: + DECODE_PRINTF("SUB\t"); + break; + case 6: + DECODE_PRINTF("XOR\t"); + break; + case 7: + DECODE_PRINTF("CMP\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod,rl); - - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval,imm; - - destval = fetch_data_long(destoffset); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_long_operation[rh]) (destval, imm); - if (rh != 7) - store_data_long(destoffset, destval); - } else { - u16 destval,imm; - - destval = fetch_data_word(destoffset); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_word_operation[rh]) (destval, imm); - if (rh != 7) - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 destval,imm; - - destreg = DECODE_RM_LONG_REGISTER(rl); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_long_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; - } else { - u16 *destreg; - u16 destval,imm; - - destreg = DECODE_RM_WORD_REGISTER(rl); - imm = (s8) fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - destval = (*genop_word_operation[rh]) (*destreg, imm); - if (rh != 7) - *destreg = destval; - } + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod,rl); + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval,imm; + + destval = fetch_data_long(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (destval, imm); + if (rh != 7) + store_data_long(destoffset, destval); + } else { + u16 destval,imm; + + destval = fetch_data_word(destoffset); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (destval, imm); + if (rh != 7) + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 destval,imm; + + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_long_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } else { + u16 *destreg; + u16 destval,imm; + + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = (s8) fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + destval = (*genop_word_operation[rh]) (*destreg, imm); + if (rh != 7) + *destreg = destval; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1657,20 +1657,20 @@ void x86emuOp_test_byte_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("TEST\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_byte(destval, *srcreg); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_byte(*destreg, *srcreg); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(destval, *srcreg); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_byte(*destreg, *srcreg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1689,48 +1689,48 @@ void x86emuOp_test_word_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("TEST\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_long(destval, *srcreg); - } else { - u16 destval; - u16 *srcreg; - - DECODE_PRINTF(","); - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_word(destval, *srcreg); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_long(*destreg, *srcreg); - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - test_word(*destreg, *srcreg); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(destval, *srcreg); + } else { + u16 destval; + u16 *srcreg; + + DECODE_PRINTF(","); + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(destval, *srcreg); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_long(*destreg, *srcreg); + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + test_word(*destreg, *srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1752,25 +1752,25 @@ void x86emuOp_xchg_byte_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("XCHG\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - destval = fetch_data_byte(destoffset); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + destval = fetch_data_byte(destoffset); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1789,59 +1789,59 @@ void x86emuOp_xchg_word_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("XCHG\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - u32 destval,tmp; - - destval = fetch_data_long(destoffset); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_long(destoffset, destval); - } else { - u16 *srcreg; - u16 destval,tmp; - - destval = fetch_data_word(destoffset); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = destval; - destval = tmp; - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 tmp; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; - } else { - u16 *destreg,*srcreg; - u16 tmp; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = *srcreg; - *srcreg = *destreg; - *destreg = tmp; - } + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 destval,tmp; + + destval = fetch_data_long(destoffset); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_long(destoffset, destval); + } else { + u16 *srcreg; + u16 destval,tmp; + + destval = fetch_data_word(destoffset); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = destval; + destval = tmp; + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 tmp; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } else { + u16 *destreg,*srcreg; + u16 tmp; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = *srcreg; + *srcreg = *destreg; + *destreg = tmp; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1861,19 +1861,19 @@ void x86emuOp_mov_byte_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_byte(destoffset, *srcreg); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_byte(destoffset, *srcreg); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1892,44 +1892,44 @@ void x86emuOp_mov_word_RM_R(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_long(destoffset, *srcreg); - } else { - u16 *srcreg; - - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - store_data_word(destoffset, *srcreg); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } else { - u16 *destreg,*srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_long(destoffset, *srcreg); + } else { + u16 *srcreg; + + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + store_data_word(destoffset, *srcreg); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg,*srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1950,20 +1950,20 @@ void x86emuOp_mov_byte_R_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1982,49 +1982,49 @@ void x86emuOp_mov_word_R_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_long(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg, *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } else { - u16 *destreg, *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_long(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg, *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg, *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2045,20 +2045,20 @@ void x86emuOp_mov_word_RM_SR(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - srcreg = decode_rm_seg_register(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = *srcreg; - store_data_word(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - srcreg = decode_rm_seg_register(rh); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = *srcreg; + store_data_word(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + srcreg = decode_rm_seg_register(rh); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2077,20 +2077,20 @@ void x86emuOp_lea_word_R_M(u8 X86EMU_UNUSED(op1)) /* * TODO: Need to handle address size prefix! * - * lea eax,[eax+ebx*2] ?? + * lea eax,[eax+ebx*2] ?? */ START_OF_INSTR(); DECODE_PRINTF("LEA\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *srcreg = (u16)destoffset; - } + srcreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *srcreg = (u16)destoffset; + } /* } else { undefined. Do nothing. } */ DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2111,20 +2111,20 @@ void x86emuOp_mov_word_SR_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = decode_rm_seg_register(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { /* register to register */ - destreg = decode_rm_seg_register(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = decode_rm_seg_register(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } /* * Clean up, and reset all the R_xSP pointers to the correct @@ -2149,42 +2149,42 @@ void x86emuOp_pop_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("POP\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); } if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = pop_long(); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = pop_word(); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = pop_long(); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = pop_word(); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_long(); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = pop_word(); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_long(); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = pop_word(); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2216,23 +2216,23 @@ void x86emuOp_xchg_word_AX_register(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg32; - DECODE_PRINTF("XCHG\tEAX,"); - reg32 = DECODE_RM_LONG_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = M.x86.R_EAX; - M.x86.R_EAX = *reg32; - *reg32 = tmp; + u32 *reg32; + DECODE_PRINTF("XCHG\tEAX,"); + reg32 = DECODE_RM_LONG_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = M.x86.R_EAX; + M.x86.R_EAX = *reg32; + *reg32 = tmp; } else { - u16 *reg16; - DECODE_PRINTF("XCHG\tAX,"); - reg16 = DECODE_RM_WORD_REGISTER(op1); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - tmp = M.x86.R_AX; - M.x86.R_EAX = *reg16; - *reg16 = (u16)tmp; + u16 *reg16; + DECODE_PRINTF("XCHG\tAX,"); + reg16 = DECODE_RM_WORD_REGISTER(op1); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + tmp = M.x86.R_AX; + M.x86.R_EAX = *reg16; + *reg16 = (u16)tmp; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2246,23 +2246,23 @@ void x86emuOp_cbw(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CWDE\n"); + DECODE_PRINTF("CWDE\n"); } else { - DECODE_PRINTF("CBW\n"); + DECODE_PRINTF("CBW\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - if (M.x86.R_AX & 0x8000) { - M.x86.R_EAX |= 0xffff0000; - } else { - M.x86.R_EAX &= 0x0000ffff; - } + if (M.x86.R_AX & 0x8000) { + M.x86.R_EAX |= 0xffff0000; + } else { + M.x86.R_EAX &= 0x0000ffff; + } } else { - if (M.x86.R_AL & 0x80) { - M.x86.R_AH = 0xff; - } else { - M.x86.R_AH = 0x0; - } + if (M.x86.R_AL & 0x80) { + M.x86.R_AH = 0xff; + } else { + M.x86.R_AH = 0x0; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2276,24 +2276,24 @@ void x86emuOp_cwd(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CDQ\n"); + DECODE_PRINTF("CDQ\n"); } else { - DECODE_PRINTF("CWD\n"); + DECODE_PRINTF("CWD\n"); } DECODE_PRINTF("CWD\n"); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - if (M.x86.R_EAX & 0x80000000) { - M.x86.R_EDX = 0xffffffff; - } else { - M.x86.R_EDX = 0x0; - } + if (M.x86.R_EAX & 0x80000000) { + M.x86.R_EDX = 0xffffffff; + } else { + M.x86.R_EDX = 0x0; + } } else { - if (M.x86.R_AX & 0x8000) { - M.x86.R_DX = 0xffff; - } else { - M.x86.R_DX = 0x0; - } + if (M.x86.R_AX & 0x8000) { + M.x86.R_DX = 0xffff; + } else { + M.x86.R_DX = 0x0; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2319,7 +2319,7 @@ void x86emuOp_call_far_IMM(u8 X86EMU_UNUSED(op1)) * * Hooked interrupt vectors calling into our "BIOS" will cause * problems unless all intersegment stuff is checked for BIOS - * access. Check needed here. For moment, let it alone. + * access. Check needed here. For moment, let it alone. */ TRACE_AND_STEP(); push_word(M.x86.R_CS); @@ -2354,18 +2354,18 @@ void x86emuOp_pushf_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("PUSHFD\n"); + DECODE_PRINTF("PUSHFD\n"); } else { - DECODE_PRINTF("PUSHF\n"); + DECODE_PRINTF("PUSHF\n"); } TRACE_AND_STEP(); /* clear out *all* bits not representing flags, and turn on real bits */ flags = (M.x86.R_EFLG & F_MSK) | F_ALWAYS_ON; if (M.x86.mode & SYSMODE_PREFIX_DATA) { - push_long(flags); + push_long(flags); } else { - push_word((u16)flags); + push_word((u16)flags); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2379,15 +2379,15 @@ void x86emuOp_popf_word(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("POPFD\n"); + DECODE_PRINTF("POPFD\n"); } else { - DECODE_PRINTF("POPF\n"); + DECODE_PRINTF("POPF\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EFLG = pop_long(); + M.x86.R_EFLG = pop_long(); } else { - M.x86.R_FLG = pop_word(); + M.x86.R_FLG = pop_word(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2456,15 +2456,15 @@ void x86emuOp_mov_AX_M_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); offset = fetch_word_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); + DECODE_PRINTF2("MOV\tEAX,[%04x]\n", offset); } else { - DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); + DECODE_PRINTF2("MOV\tAX,[%04x]\n", offset); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = fetch_data_long(offset); + M.x86.R_EAX = fetch_data_long(offset); } else { - M.x86.R_AX = fetch_data_word(offset); + M.x86.R_AX = fetch_data_word(offset); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2499,15 +2499,15 @@ void x86emuOp_mov_M_AX_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); offset = fetch_word_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); + DECODE_PRINTF2("MOV\t[%04x],EAX\n", offset); } else { - DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); + DECODE_PRINTF2("MOV\t[%04x],AX\n", offset); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - store_data_long(offset, M.x86.R_EAX); + store_data_long(offset, M.x86.R_EAX); } else { - store_data_word(offset, M.x86.R_AX); + store_data_word(offset, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2519,30 +2519,30 @@ Handles opcode 0xa4 ****************************************************************************/ void x86emuOp_movs_byte(u8 X86EMU_UNUSED(op1)) { - u8 val; + u8 val; u32 count; int inc; START_OF_INSTR(); DECODE_PRINTF("MOVS\tBYTE\n"); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - count = M.x86.R_CX; - M.x86.R_CX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - val = fetch_data_byte(M.x86.R_SI); - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); - M.x86.R_SI += inc; - M.x86.R_DI += inc; + val = fetch_data_byte(M.x86.R_SI); + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, val); + M.x86.R_SI += inc; + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2560,37 +2560,37 @@ void x86emuOp_movs_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("MOVS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("MOVS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("MOVS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("MOVS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - count = M.x86.R_CX; - M.x86.R_CX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long(M.x86.R_SI); - store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); - } else { - val = fetch_data_word(M.x86.R_SI); - store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); - } - M.x86.R_SI += inc; - M.x86.R_DI += inc; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long(M.x86.R_SI); + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, val); + } else { + val = fetch_data_word(M.x86.R_SI); + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, (u16)val); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2609,30 +2609,30 @@ void x86emuOp_cmps_byte(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("CMPS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* REPE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - val1 = fetch_data_byte(M.x86.R_SI); - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(val1, val2); - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && (ACCESS_FLAG(F_ZF) == 0) ) break; - if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && (ACCESS_FLAG(F_ZF) == 0) ) break; + if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - val1 = fetch_data_byte(M.x86.R_SI); - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(val1, val2); - M.x86.R_SI += inc; - M.x86.R_DI += inc; + val1 = fetch_data_byte(M.x86.R_SI); + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(val1, val2); + M.x86.R_SI += inc; + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2649,48 +2649,48 @@ void x86emuOp_cmps_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("CMPS\tDWORD\n"); - inc = 4; + DECODE_PRINTF("CMPS\tDWORD\n"); + inc = 4; } else { - DECODE_PRINTF("CMPS\tWORD\n"); - inc = 2; + DECODE_PRINTF("CMPS\tWORD\n"); + inc = 2; } if (ACCESS_FLAG(F_DF)) /* down */ - inc = -inc; + inc = -inc; TRACE_AND_STEP(); if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* REPE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val1 = fetch_data_long(M.x86.R_SI); - val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(val1, val2); - } else { - val1 = fetch_data_word(M.x86.R_SI); - val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word((u16)val1, (u16)val2); - } - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - M.x86.R_DI += inc; - if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && ACCESS_FLAG(F_ZF) == 0 ) break; - if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + M.x86.R_DI += inc; + if ( (M.x86.mode & SYSMODE_PREFIX_REPE) && ACCESS_FLAG(F_ZF) == 0 ) break; + if ( (M.x86.mode & SYSMODE_PREFIX_REPNE) && ACCESS_FLAG(F_ZF) ) break; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val1 = fetch_data_long(M.x86.R_SI); - val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(val1, val2); - } else { - val1 = fetch_data_word(M.x86.R_SI); - val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word((u16)val1, (u16)val2); - } - M.x86.R_SI += inc; - M.x86.R_DI += inc; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val1 = fetch_data_long(M.x86.R_SI); + val2 = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(val1, val2); + } else { + val1 = fetch_data_word(M.x86.R_SI); + val2 = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word((u16)val1, (u16)val2); + } + M.x86.R_SI += inc; + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2724,18 +2724,18 @@ void x86emuOp_test_AX_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("TEST\tEAX,"); - srcval = fetch_long_imm(); + DECODE_PRINTF("TEST\tEAX,"); + srcval = fetch_long_imm(); } else { - DECODE_PRINTF("TEST\tAX,"); - srcval = fetch_word_imm(); + DECODE_PRINTF("TEST\tAX,"); + srcval = fetch_word_imm(); } DECODE_PRINTF2("%x\n", srcval); TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - test_long(M.x86.R_EAX, srcval); + test_long(M.x86.R_EAX, srcval); } else { - test_word(M.x86.R_AX, (u16)srcval); + test_word(M.x86.R_AX, (u16)srcval); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2752,22 +2752,22 @@ void x86emuOp_stos_byte(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("STOS\tBYTE\n"); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; TRACE_AND_STEP(); if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); - M.x86.R_DI += inc; + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AL); + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2784,34 +2784,34 @@ void x86emuOp_stos_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("STOS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("STOS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("STOS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("STOS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - count = M.x86.R_CX; - M.x86.R_CX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); - } else { - store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); - } - M.x86.R_DI += inc; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + store_data_long_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_EAX); + } else { + store_data_word_abs(M.x86.R_ES, M.x86.R_DI, M.x86.R_AX); + } + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2829,21 +2829,21 @@ void x86emuOp_lods_byte(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LODS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - M.x86.R_AL = fetch_data_byte(M.x86.R_SI); - M.x86.R_CX -= 1; - M.x86.R_SI += inc; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_CX -= 1; + M.x86.R_SI += inc; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - M.x86.R_AL = fetch_data_byte(M.x86.R_SI); - M.x86.R_SI += inc; + M.x86.R_AL = fetch_data_byte(M.x86.R_SI); + M.x86.R_SI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2860,34 +2860,34 @@ void x86emuOp_lods_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("LODS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("LODS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("LODS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("LODS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); count = 1; if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* move them until CX is ZERO. */ - count = M.x86.R_CX; - M.x86.R_CX = 0; - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* move them until CX is ZERO. */ + count = M.x86.R_CX; + M.x86.R_CX = 0; + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } while (count--) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = fetch_data_long(M.x86.R_SI); - } else { - M.x86.R_AX = fetch_data_word(M.x86.R_SI); - } - M.x86.R_SI += inc; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_EAX = fetch_data_long(M.x86.R_SI); + } else { + M.x86.R_AX = fetch_data_word(M.x86.R_SI); + } + M.x86.R_SI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2906,37 +2906,37 @@ void x86emuOp_scas_byte(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("SCAS\tBYTE\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_DF)) /* down */ - inc = -1; + inc = -1; else - inc = 1; + inc = 1; if (M.x86.mode & SYSMODE_PREFIX_REPE) { - /* REPE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF) == 0) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPE; + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { - /* REPNE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF)) - break; /* zero flag set means equal */ - } - M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; } else { - val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); - cmp_byte(M.x86.R_AL, val2); - M.x86.R_DI += inc; + val2 = fetch_data_byte_abs(M.x86.R_ES, M.x86.R_DI); + cmp_byte(M.x86.R_AL, val2); + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -2953,62 +2953,62 @@ void x86emuOp_scas_word(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("SCAS\tDWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -4; - else - inc = 4; + DECODE_PRINTF("SCAS\tDWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -4; + else + inc = 4; } else { - DECODE_PRINTF("SCAS\tWORD\n"); - if (ACCESS_FLAG(F_DF)) /* down */ - inc = -2; - else - inc = 2; + DECODE_PRINTF("SCAS\tWORD\n"); + if (ACCESS_FLAG(F_DF)) /* down */ + inc = -2; + else + inc = 2; } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_REPE) { - /* REPE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF) == 0) - break; - } - M.x86.mode &= ~SYSMODE_PREFIX_REPE; + /* REPE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF) == 0) + break; + } + M.x86.mode &= ~SYSMODE_PREFIX_REPE; } else if (M.x86.mode & SYSMODE_PREFIX_REPNE) { - /* REPNE */ - /* move them until CX is ZERO. */ - while (M.x86.R_CX != 0) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - M.x86.R_CX -= 1; - M.x86.R_DI += inc; - if (ACCESS_FLAG(F_ZF)) - break; /* zero flag set means equal */ - } - M.x86.mode &= ~SYSMODE_PREFIX_REPNE; + /* REPNE */ + /* move them until CX is ZERO. */ + while (M.x86.R_CX != 0) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_CX -= 1; + M.x86.R_DI += inc; + if (ACCESS_FLAG(F_ZF)) + break; /* zero flag set means equal */ + } + M.x86.mode &= ~SYSMODE_PREFIX_REPNE; } else { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); - cmp_long(M.x86.R_EAX, val); - } else { - val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); - cmp_word(M.x86.R_AX, (u16)val); - } - M.x86.R_DI += inc; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + val = fetch_data_long_abs(M.x86.R_ES, M.x86.R_DI); + cmp_long(M.x86.R_EAX, val); + } else { + val = fetch_data_word_abs(M.x86.R_ES, M.x86.R_DI); + cmp_word(M.x86.R_AX, (u16)val); + } + M.x86.R_DI += inc; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3047,19 +3047,19 @@ void x86emuOp_mov_word_register_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("MOV\t"); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *reg32; - reg32 = DECODE_RM_LONG_REGISTER(op1); - srcval = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", srcval); - TRACE_AND_STEP(); - *reg32 = srcval; + u32 *reg32; + reg32 = DECODE_RM_LONG_REGISTER(op1); + srcval = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", srcval); + TRACE_AND_STEP(); + *reg32 = srcval; } else { - u16 *reg16; - reg16 = DECODE_RM_WORD_REGISTER(op1); - srcval = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", srcval); - TRACE_AND_STEP(); - *reg16 = (u16)srcval; + u16 *reg16; + reg16 = DECODE_RM_WORD_REGISTER(op1); + srcval = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", srcval); + TRACE_AND_STEP(); + *reg16 = (u16)srcval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3086,57 +3086,57 @@ void x86emuOp_opcC0_byte_RM_MEM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, amt); - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, amt); - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3161,83 +3161,83 @@ void x86emuOp_opcC1_word_RM_MEM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, amt); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, amt); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - amt = fetch_byte_imm(); - DECODE_PRINTF2(",%x\n", amt); - TRACE_AND_STEP(); - *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + amt = fetch_byte_imm(); + DECODE_PRINTF2(",%x\n", amt); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3292,15 +3292,15 @@ void x86emuOp_les_R_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LES\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_ES = fetch_data_word(srcoffset + 2); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_ES = fetch_data_word(srcoffset + 2); } - /* else UNDEFINED! register to register */ + /* else UNDEFINED! register to register */ DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3320,13 +3320,13 @@ void x86emuOp_lds_R_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("LDS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_DS = fetch_data_word(srcoffset + 2); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_DS = fetch_data_word(srcoffset + 2); } /* else UNDEFINED! */ DECODE_CLEAR_SEGOVR(); @@ -3348,22 +3348,22 @@ void x86emuOp_mov_byte_RM_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE c6\n"); + HALT_SYS(); } if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%2x\n", imm); - TRACE_AND_STEP(); - store_data_byte(destoffset, imm); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - imm = fetch_byte_imm(); - DECODE_PRINTF2(",%2x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + store_data_byte(destoffset, imm); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + imm = fetch_byte_imm(); + DECODE_PRINTF2(",%2x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3382,49 +3382,49 @@ void x86emuOp_mov_word_RM_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("MOV\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (rh != 0) { - DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL DECODE OF OPCODE 8F\n"); + HALT_SYS(); } if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 imm; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - store_data_long(destoffset, imm); - } else { - u16 imm; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - store_data_word(destoffset, imm); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 imm; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_long(destoffset, imm); + } else { + u16 imm; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + store_data_word(destoffset, imm); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 *destreg; u32 imm; - destreg = DECODE_RM_LONG_REGISTER(rl); - imm = fetch_long_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; - } else { + destreg = DECODE_RM_LONG_REGISTER(rl); + imm = fetch_long_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } else { u16 *destreg; u16 imm; - destreg = DECODE_RM_WORD_REGISTER(rl); - imm = fetch_word_imm(); - DECODE_PRINTF2(",%x\n", imm); - TRACE_AND_STEP(); - *destreg = imm; - } + destreg = DECODE_RM_WORD_REGISTER(rl); + imm = fetch_word_imm(); + DECODE_PRINTF2(",%x\n", imm); + TRACE_AND_STEP(); + *destreg = imm; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3437,7 +3437,7 @@ Handles opcode 0xc8 void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) { u16 local,frame_pointer; - u8 nesting; + u8 nesting; int i; START_OF_INSTR(); @@ -3449,12 +3449,12 @@ void x86emuOp_enter(u8 X86EMU_UNUSED(op1)) push_word(M.x86.R_BP); frame_pointer = M.x86.R_SP; if (nesting > 0) { - for (i = 1; i < nesting; i++) { - M.x86.R_BP -= 2; - push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); - } - push_word(frame_pointer); - } + for (i = 1; i < nesting; i++) { + M.x86.R_BP -= 2; + push_word(fetch_data_word_abs(M.x86.R_SS, M.x86.R_BP)); + } + push_word(frame_pointer); + } M.x86.R_BP = frame_pointer; M.x86.R_SP = (u16)(M.x86.R_SP - local); DECODE_CLEAR_SEGOVR(); @@ -3529,13 +3529,13 @@ void x86emuOp_int3(u8 X86EMU_UNUSED(op1)) if (_X86EMU_intrTab[3]) { (*_X86EMU_intrTab[3])(3); } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(3 * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(3 * 4); + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(3 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(3 * 4); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3559,13 +3559,13 @@ void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1)) if (_X86EMU_intrTab[intnum]) { (*_X86EMU_intrTab[intnum])(intnum); } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(intnum * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(intnum * 4); + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(intnum * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(intnum * 4); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3583,18 +3583,18 @@ void x86emuOp_into(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("INTO\n"); TRACE_AND_STEP(); if (ACCESS_FLAG(F_OF)) { - tmp = mem_access_word(4 * 4 + 2); + tmp = mem_access_word(4 * 4 + 2); if (_X86EMU_intrTab[4]) { (*_X86EMU_intrTab[4])(4); - } else { - push_word((u16)M.x86.R_FLG); - CLEAR_FLAG(F_IF); - CLEAR_FLAG(F_TF); - push_word(M.x86.R_CS); - M.x86.R_CS = mem_access_word(4 * 4 + 2); - push_word(M.x86.R_IP); - M.x86.R_IP = mem_access_word(4 * 4); - } + } else { + push_word((u16)M.x86.R_FLG); + CLEAR_FLAG(F_IF); + CLEAR_FLAG(F_TF); + push_word(M.x86.R_CS); + M.x86.R_CS = mem_access_word(4 * 4 + 2); + push_word(M.x86.R_IP); + M.x86.R_IP = mem_access_word(4 * 4); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3638,54 +3638,54 @@ void x86emuOp_opcD0_byte_RM_1(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, 1); - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, 1); - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, 1); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, 1); + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3709,82 +3709,82 @@ void x86emuOp_opcD1_word_RM_1(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, 1); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",1\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, 1); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, 1); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",1\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, 1); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { u32 destval; u32 *destreg; - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (*destreg, 1); - *destreg = destval; - } else { + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (*destreg, 1); + *destreg = destval; + } else { u16 destval; u16 *destreg; - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(",1\n"); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (*destreg, 1); - *destreg = destval; - } + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",1\n"); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (*destreg, 1); + *destreg = destval; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3811,55 +3811,55 @@ void x86emuOp_opcD2_byte_RM_CL(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ amt = M.x86.R_CL; if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (destval, amt); - store_data_byte(destoffset, destval); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = (*opcD0_byte_operation[rh]) (*destreg, amt); - *destreg = destval; + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (destval, amt); + store_data_byte(destoffset, destval); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = (*opcD0_byte_operation[rh]) (*destreg, amt); + *destreg = destval; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3884,79 +3884,79 @@ void x86emuOp_opcD3_word_RM_CL(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - switch (rh) { - case 0: - DECODE_PRINTF("ROL\t"); - break; - case 1: - DECODE_PRINTF("ROR\t"); - break; - case 2: - DECODE_PRINTF("RCL\t"); - break; - case 3: - DECODE_PRINTF("RCR\t"); - break; - case 4: - DECODE_PRINTF("SHL\t"); - break; - case 5: - DECODE_PRINTF("SHR\t"); - break; - case 6: - DECODE_PRINTF("SAL\t"); - break; - case 7: - DECODE_PRINTF("SAR\t"); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + switch (rh) { + case 0: + DECODE_PRINTF("ROL\t"); + break; + case 1: + DECODE_PRINTF("ROR\t"); + break; + case 2: + DECODE_PRINTF("RCL\t"); + break; + case 3: + DECODE_PRINTF("RCR\t"); + break; + case 4: + DECODE_PRINTF("SHL\t"); + break; + case 5: + DECODE_PRINTF("SHR\t"); + break; + case 6: + DECODE_PRINTF("SAL\t"); + break; + case 7: + DECODE_PRINTF("SAR\t"); + break; + } } #endif /* know operation, decode the mod byte to find the addressing mode. */ amt = M.x86.R_CL; if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_long_operation[rh]) (destval, amt); - store_data_long(destoffset, destval); - } else { - u16 destval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(",CL\n"); - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = (*opcD1_word_operation[rh]) (destval, amt); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_long_operation[rh]) (destval, amt); + store_data_long(destoffset, destval); + } else { + u16 destval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(",CL\n"); + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = (*opcD1_word_operation[rh]) (destval, amt); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_long_operation[rh]) (*destreg, amt); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = (*opcD1_word_operation[rh]) (*destreg, amt); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -3974,9 +3974,9 @@ void x86emuOp_aam(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("AAM\n"); a = fetch_byte_imm(); /* this is a stupid encoding. */ if (a != 10) { - DECODE_PRINTF("ERROR DECODING AAM\n"); - TRACE_REGS(); - HALT_SYS(); + DECODE_PRINTF("ERROR DECODING AAM\n"); + TRACE_REGS(); + HALT_SYS(); } TRACE_AND_STEP(); /* note the type change here --- returning AL and AH in AX. */ @@ -4021,7 +4021,7 @@ void x86emuOp_xlat(u8 X86EMU_UNUSED(op1)) END_OF_INSTR(); } -/* instuctions D8 .. DF are in i87_ops.c */ +/* instuctions D8 .. DF are in i87_ops.c */ /**************************************************************************** REMARKS: @@ -4038,8 +4038,8 @@ void x86emuOp_loopne(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); M.x86.R_CX -= 1; - if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF)) /* CX != 0 and !ZF */ - M.x86.R_IP = ip; + if (M.x86.R_CX != 0 && !ACCESS_FLAG(F_ZF)) /* CX != 0 and !ZF */ + M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4059,8 +4059,8 @@ void x86emuOp_loope(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%04x\n", ip); TRACE_AND_STEP(); M.x86.R_CX -= 1; - if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF)) /* CX != 0 and ZF */ - M.x86.R_IP = ip; + if (M.x86.R_CX != 0 && ACCESS_FLAG(F_ZF)) /* CX != 0 and ZF */ + M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4081,7 +4081,7 @@ void x86emuOp_loop(u8 X86EMU_UNUSED(op1)) TRACE_AND_STEP(); M.x86.R_CX -= 1; if (M.x86.R_CX != 0) - M.x86.R_IP = ip; + M.x86.R_IP = ip; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4093,7 +4093,7 @@ Handles opcode 0xe3 void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) { u16 target; - s8 offset; + s8 offset; /* jump to byte offset if overflow flag is set */ START_OF_INSTR(); @@ -4103,7 +4103,7 @@ void x86emuOp_jcxz(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF2("%x\n", target); TRACE_AND_STEP(); if (M.x86.R_CX == 0) - M.x86.R_IP = target; + M.x86.R_IP = target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -4138,15 +4138,15 @@ void x86emuOp_in_word_AX_IMM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("IN\t"); port = (u8) fetch_byte_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("EAX,%x\n", port); + DECODE_PRINTF2("EAX,%x\n", port); } else { - DECODE_PRINTF2("AX,%x\n", port); + DECODE_PRINTF2("AX,%x\n", port); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = (*sys_inl)(port); + M.x86.R_EAX = (*sys_inl)(port); } else { - M.x86.R_AX = (*sys_inw)(port); + M.x86.R_AX = (*sys_inw)(port); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4182,15 +4182,15 @@ void x86emuOp_out_word_IMM_AX(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF("OUT\t"); port = (u8) fetch_byte_imm(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF2("%x,EAX\n", port); + DECODE_PRINTF2("%x,EAX\n", port); } else { - DECODE_PRINTF2("%x,AX\n", port); + DECODE_PRINTF2("%x,AX\n", port); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - (*sys_outl)(port, M.x86.R_EAX); + (*sys_outl)(port, M.x86.R_EAX); } else { - (*sys_outw)(port, M.x86.R_AX); + (*sys_outw)(port, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4207,7 +4207,7 @@ void x86emuOp_call_near_IMM(u8 X86EMU_UNUSED(op1)) START_OF_INSTR(); DECODE_PRINTF("CALL\t"); ip = (s16) fetch_word_imm(); - ip += (s16) M.x86.R_IP; /* CHECK SIGN */ + ip += (s16) M.x86.R_IP; /* CHECK SIGN */ DECODE_PRINTF2("%04x\n", ip); CALL_TRACE(M.x86.saved_cs, M.x86.saved_ip, M.x86.R_CS, ip, ""); TRACE_AND_STEP(); @@ -4299,15 +4299,15 @@ void x86emuOp_in_word_AX_DX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("IN\tEAX,DX\n"); + DECODE_PRINTF("IN\tEAX,DX\n"); } else { - DECODE_PRINTF("IN\tAX,DX\n"); + DECODE_PRINTF("IN\tAX,DX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); + M.x86.R_EAX = (*sys_inl)(M.x86.R_DX); } else { - M.x86.R_AX = (*sys_inw)(M.x86.R_DX); + M.x86.R_AX = (*sys_inw)(M.x86.R_DX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4335,15 +4335,15 @@ void x86emuOp_out_word_DX_AX(u8 X86EMU_UNUSED(op1)) { START_OF_INSTR(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("OUT\tDX,EAX\n"); + DECODE_PRINTF("OUT\tDX,EAX\n"); } else { - DECODE_PRINTF("OUT\tDX,AX\n"); + DECODE_PRINTF("OUT\tDX,AX\n"); } TRACE_AND_STEP(); if (M.x86.mode & SYSMODE_PREFIX_DATA) { - (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); + (*sys_outl)(M.x86.R_DX, M.x86.R_EAX); } else { - (*sys_outw)(M.x86.R_DX, M.x86.R_AX); + (*sys_outw)(M.x86.R_DX, M.x86.R_AX); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4438,100 +4438,100 @@ void x86emuOp_opcF6_byte_RM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); DECODE_PRINTF(opF6_names[rh]); if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_byte(destoffset); - - switch (rh) { - case 0: /* test byte imm */ - DECODE_PRINTF(","); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%02x\n", srcval); - TRACE_AND_STEP(); - test_byte(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = not_byte(destval); - store_data_byte(destoffset, destval); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = neg_byte(destval); - store_data_byte(destoffset, destval); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_byte(destval); - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_byte(destval); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_byte(destval); - break; - default: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_byte(destval); - break; - } - } else { /* mod=11 */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - switch (rh) { - case 0: /* test byte imm */ - DECODE_PRINTF(","); - srcval = fetch_byte_imm(); - DECODE_PRINTF2("%02x\n", srcval); - TRACE_AND_STEP(); - test_byte(*destreg, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_byte(*destreg); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_byte(*destreg); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_byte(*destreg); /*!!! */ - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_byte(*destreg); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_byte(*destreg); - break; - default: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_byte(*destreg); - break; - } + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_byte(destoffset); + + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_byte(destval); + store_data_byte(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_byte(destval); + store_data_byte(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(destval); + break; + default: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(destval); + break; + } + } else { /* mod=11 */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + switch (rh) { + case 0: /* test byte imm */ + DECODE_PRINTF(","); + srcval = fetch_byte_imm(); + DECODE_PRINTF2("%02x\n", srcval); + TRACE_AND_STEP(); + test_byte(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_byte(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_byte(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_byte(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_byte(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_byte(*destreg); + break; + default: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_byte(*destreg); + break; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4551,213 +4551,213 @@ void x86emuOp_opcF7_word_RM(u8 X86EMU_UNUSED(op1)) DECODE_PRINTF(opF6_names[rh]); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval, srcval; - - DECODE_PRINTF("DWORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_long(destoffset); - - switch (rh) { - case 0: - DECODE_PRINTF(","); - srcval = fetch_long_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_long(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = not_long(destval); - store_data_long(destoffset, destval); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = neg_long(destval); - store_data_long(destoffset, destval); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_long(destval); - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_long(destval); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_long(destval); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_long(destval); - break; - } - } else { - u16 destval, srcval; - - DECODE_PRINTF("WORD PTR "); - destoffset = decode_rmXX_address(mod, rl); - destval = fetch_data_word(destoffset); - - switch (rh) { - case 0: /* test word imm */ - DECODE_PRINTF(","); - srcval = fetch_word_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_word(destval, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = not_word(destval); - store_data_word(destoffset, destval); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - destval = neg_word(destval); - store_data_word(destoffset, destval); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_word(destval); - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_word(destval); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_word(destval); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_word(destval); - break; - } - } - - } else { /* mod=11 */ - - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rl); - - switch (rh) { - case 0: /* test word imm */ - DECODE_PRINTF(","); - srcval = fetch_long_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_long(*destreg, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_long(*destreg); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_long(*destreg); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_long(*destreg); /*!!! */ - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_long(*destreg); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_long(*destreg); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_long(*destreg); - break; - } - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rl); - - switch (rh) { - case 0: /* test word imm */ - DECODE_PRINTF(","); - srcval = fetch_word_imm(); - DECODE_PRINTF2("%x\n", srcval); - TRACE_AND_STEP(); - test_word(*destreg, srcval); - break; - case 1: - DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); - HALT_SYS(); - break; - case 2: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = not_word(*destreg); - break; - case 3: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = neg_word(*destreg); - break; - case 4: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - mul_word(*destreg); /*!!! */ - break; - case 5: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - imul_word(*destreg); - break; - case 6: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - div_word(*destreg); - break; - case 7: - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - idiv_word(*destreg); - break; - } - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval, srcval; + + DECODE_PRINTF("DWORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_long(destoffset); + + switch (rh) { + case 0: + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_long(destval); + store_data_long(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_long(destval); + store_data_long(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(destval); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(destval); + break; + } + } else { + u16 destval, srcval; + + DECODE_PRINTF("WORD PTR "); + destoffset = decode_rmXX_address(mod, rl); + destval = fetch_data_word(destoffset); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(destval, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F7\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = not_word(destval); + store_data_word(destoffset, destval); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + destval = neg_word(destval); + store_data_word(destoffset, destval); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(destval); + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(destval); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(destval); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(destval); + break; + } + } + + } else { /* mod=11 */ + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rl); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_long_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_long(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_long(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_long(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_long(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_long(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_long(*destreg); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_long(*destreg); + break; + } + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rl); + + switch (rh) { + case 0: /* test word imm */ + DECODE_PRINTF(","); + srcval = fetch_word_imm(); + DECODE_PRINTF2("%x\n", srcval); + TRACE_AND_STEP(); + test_word(*destreg, srcval); + break; + case 1: + DECODE_PRINTF("ILLEGAL OP MOD=00 RH=01 OP=F6\n"); + HALT_SYS(); + break; + case 2: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = not_word(*destreg); + break; + case 3: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = neg_word(*destreg); + break; + case 4: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + mul_word(*destreg); /*!!! */ + break; + case 5: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + imul_word(*destreg); + break; + case 6: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + div_word(*destreg); + break; + case 7: + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + idiv_word(*destreg); + break; + } + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4869,49 +4869,49 @@ void x86emuOp_opcFE_byte_RM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - DECODE_PRINTF("INC\t"); - break; - case 1: - DECODE_PRINTF("DEC\t"); - break; - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: - DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); - HALT_SYS(); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + DECODE_PRINTF("INC\t"); + break; + case 1: + DECODE_PRINTF("DEC\t"); + break; + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + DECODE_PRINTF2("ILLEGAL OP MAJOR OP 0xFE MINOR OP %x \n", mod); + HALT_SYS(); + break; + } } #endif if (mod < 3) { - DECODE_PRINTF("BYTE PTR "); - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - destval = fetch_data_byte(destoffset); - TRACE_AND_STEP(); - if (rh == 0) - destval = inc_byte(destval); - else - destval = dec_byte(destval); - store_data_byte(destoffset, destval); + DECODE_PRINTF("BYTE PTR "); + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + destval = fetch_data_byte(destoffset); + TRACE_AND_STEP(); + if (rh == 0) + destval = inc_byte(destval); + else + destval = dec_byte(destval); + store_data_byte(destoffset, destval); } else { - destreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - if (rh == 0) - *destreg = inc_byte(*destreg); - else - *destreg = dec_byte(*destreg); + destreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + if (rh == 0) + *destreg = inc_byte(*destreg); + else + *destreg = dec_byte(*destreg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -4933,207 +4933,207 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) FETCH_DECODE_MODRM(mod, rh, rl); #ifdef DEBUG if (DEBUG_DECODE()) { - /* XXX DECODE_PRINTF may be changed to something more - general, so that it is important to leave the strings - in the same format, even though the result is that the - above test is done twice. */ - - switch (rh) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("INC\tDWORD PTR "); - } else { - DECODE_PRINTF("INC\tWORD PTR "); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - DECODE_PRINTF("DEC\tDWORD PTR "); - } else { - DECODE_PRINTF("DEC\tWORD PTR "); - } - break; - case 2: - DECODE_PRINTF("CALL\t "); - break; - case 3: - DECODE_PRINTF("CALL\tFAR "); - break; - case 4: - DECODE_PRINTF("JMP\t"); - break; - case 5: - DECODE_PRINTF("JMP\tFAR "); - break; - case 6: - DECODE_PRINTF("PUSH\t"); - break; - case 7: - DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); - HALT_SYS(); - break; - } + /* XXX DECODE_PRINTF may be changed to something more + general, so that it is important to leave the strings + in the same format, even though the result is that the + above test is done twice. */ + + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("INC\tDWORD PTR "); + } else { + DECODE_PRINTF("INC\tWORD PTR "); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + DECODE_PRINTF("DEC\tDWORD PTR "); + } else { + DECODE_PRINTF("DEC\tWORD PTR "); + } + break; + case 2: + DECODE_PRINTF("CALL\t "); + break; + case 3: + DECODE_PRINTF("CALL\tFAR "); + break; + case 4: + DECODE_PRINTF("JMP\t"); + break; + case 5: + DECODE_PRINTF("JMP\tFAR "); + break; + case 6: + DECODE_PRINTF("PUSH\t"); + break; + case 7: + DECODE_PRINTF("ILLEGAL DECODING OF OPCODE FF\t"); + HALT_SYS(); + break; + } } #endif if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - switch (rh) { - case 0: /* inc word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = inc_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = inc_word(destval); - store_data_word(destoffset, destval); - } - break; - case 1: /* dec word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - destval = dec_long(destval); - store_data_long(destoffset, destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - destval = dec_word(destval); - store_data_word(destoffset, destval); - } - break; - case 2: /* call word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = destval; - break; - case 3: /* call far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - push_word(M.x86.R_CS); - M.x86.R_CS = destval2; - push_word(M.x86.R_IP); - M.x86.R_IP = destval; - break; - case 4: /* jmp word ptr ... */ - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - M.x86.R_IP = destval; - break; - case 5: /* jmp far ptr ... */ - destval = fetch_data_word(destoffset); - destval2 = fetch_data_word(destoffset + 2); - TRACE_AND_STEP(); - M.x86.R_IP = destval; - M.x86.R_CS = destval2; - break; - case 6: /* push word ptr ... */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - - destval = fetch_data_long(destoffset); - TRACE_AND_STEP(); - push_long(destval); - } else { - u16 destval; - - destval = fetch_data_word(destoffset); - TRACE_AND_STEP(); - push_word(destval); - } - break; - } + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + switch (rh) { + case 0: /* inc word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = inc_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = inc_word(destval); + store_data_word(destoffset, destval); + } + break; + case 1: /* dec word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + destval = dec_long(destval); + store_data_long(destoffset, destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + destval = dec_word(destval); + store_data_word(destoffset, destval); + } + break; + case 2: /* call word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 3: /* call far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + push_word(M.x86.R_CS); + M.x86.R_CS = destval2; + push_word(M.x86.R_IP); + M.x86.R_IP = destval; + break; + case 4: /* jmp word ptr ... */ + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + break; + case 5: /* jmp far ptr ... */ + destval = fetch_data_word(destoffset); + destval2 = fetch_data_word(destoffset + 2); + TRACE_AND_STEP(); + M.x86.R_IP = destval; + M.x86.R_CS = destval2; + break; + case 6: /* push word ptr ... */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + + destval = fetch_data_long(destoffset); + TRACE_AND_STEP(); + push_long(destval); + } else { + u16 destval; + + destval = fetch_data_word(destoffset); + TRACE_AND_STEP(); + push_word(destval); + } + break; + } } else { - switch (rh) { - case 0: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = inc_long(*destreg); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = inc_word(*destreg); - } - break; - case 1: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = dec_long(*destreg); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = dec_word(*destreg); - } - break; - case 2: /* call word ptr ... */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(M.x86.R_IP); - M.x86.R_IP = *destreg; - break; - case 3: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); - TRACE_AND_STEP(); - HALT_SYS(); - break; - - case 4: /* jmp ... */ - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - M.x86.R_IP = (u16) (*destreg); - break; - case 5: /* jmp far ptr ... */ - DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); - TRACE_AND_STEP(); - HALT_SYS(); - break; - case 6: - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_long(*destreg); - } else { - u16 *destreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - push_word(*destreg); - } - break; - } + switch (rh) { + case 0: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = inc_word(*destreg); + } + break; + case 1: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = dec_word(*destreg); + } + break; + case 2: /* call word ptr ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(M.x86.R_IP); + M.x86.R_IP = *destreg; + break; + case 3: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + + case 4: /* jmp ... */ + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + M.x86.R_IP = (u16) (*destreg); + break; + case 5: /* jmp far ptr ... */ + DECODE_PRINTF("OPERATION UNDEFINED 0XFF \n"); + TRACE_AND_STEP(); + HALT_SYS(); + break; + case 6: + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_long(*destreg); + } else { + u16 *destreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + push_word(*destreg); + } + break; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index 2412b24cd80..631a340ed2b 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -1,13 +1,13 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. * Jason Jin * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -17,7 +17,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -31,16 +31,16 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett * -* Description: This file includes subroutines to implement the decoding -* and emulation of all the x86 extended two-byte processor -* instructions. +* Description: This file includes subroutines to implement the decoding +* and emulation of all the x86 extended two-byte processor +* instructions. * -* Jason port this file to u-boot. Put the function pointer into -* got2 sector. +* Jason port this file to u-boot. Put the function pointer into +* got2 sector. * ****************************************************************************/ @@ -62,7 +62,7 @@ void x86emuOp2_illegal_op( DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); TRACE_REGS(); printk("%04x:%04x: %02X ILLEGAL EXTENDED X86 OPCODE!\n", - M.x86.R_CS, M.x86.R_IP-2,op2); + M.x86.R_CS, M.x86.R_IP-2,op2); HALT_SYS(); END_OF_INSTR(); } @@ -77,69 +77,69 @@ int x86emu_check_jump_condition(u8 op) { switch (op) { case 0x0: - DECODE_PRINTF("JO\t"); - return ACCESS_FLAG(F_OF); + DECODE_PRINTF("JO\t"); + return ACCESS_FLAG(F_OF); case 0x1: - DECODE_PRINTF("JNO\t"); - return !ACCESS_FLAG(F_OF); - break; + DECODE_PRINTF("JNO\t"); + return !ACCESS_FLAG(F_OF); + break; case 0x2: - DECODE_PRINTF("JB\t"); - return ACCESS_FLAG(F_CF); - break; + DECODE_PRINTF("JB\t"); + return ACCESS_FLAG(F_CF); + break; case 0x3: - DECODE_PRINTF("JNB\t"); - return !ACCESS_FLAG(F_CF); - break; + DECODE_PRINTF("JNB\t"); + return !ACCESS_FLAG(F_CF); + break; case 0x4: - DECODE_PRINTF("JZ\t"); - return ACCESS_FLAG(F_ZF); - break; + DECODE_PRINTF("JZ\t"); + return ACCESS_FLAG(F_ZF); + break; case 0x5: - DECODE_PRINTF("JNZ\t"); - return !ACCESS_FLAG(F_ZF); - break; + DECODE_PRINTF("JNZ\t"); + return !ACCESS_FLAG(F_ZF); + break; case 0x6: - DECODE_PRINTF("JBE\t"); - return ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); - break; + DECODE_PRINTF("JBE\t"); + return ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; case 0x7: - DECODE_PRINTF("JNBE\t"); - return !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); - break; + DECODE_PRINTF("JNBE\t"); + return !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; case 0x8: - DECODE_PRINTF("JS\t"); - return ACCESS_FLAG(F_SF); - break; + DECODE_PRINTF("JS\t"); + return ACCESS_FLAG(F_SF); + break; case 0x9: - DECODE_PRINTF("JNS\t"); - return !ACCESS_FLAG(F_SF); - break; + DECODE_PRINTF("JNS\t"); + return !ACCESS_FLAG(F_SF); + break; case 0xa: - DECODE_PRINTF("JP\t"); - return ACCESS_FLAG(F_PF); - break; + DECODE_PRINTF("JP\t"); + return ACCESS_FLAG(F_PF); + break; case 0xb: - DECODE_PRINTF("JNP\t"); - return !ACCESS_FLAG(F_PF); - break; + DECODE_PRINTF("JNP\t"); + return !ACCESS_FLAG(F_PF); + break; case 0xc: - DECODE_PRINTF("JL\t"); - return xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; + DECODE_PRINTF("JL\t"); + return xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; case 0xd: - DECODE_PRINTF("JNL\t"); - return !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; + DECODE_PRINTF("JNL\t"); + return !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; case 0xe: - DECODE_PRINTF("JLE\t"); - return (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); - break; + DECODE_PRINTF("JLE\t"); + return (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; default: - DECODE_PRINTF("JNLE\t"); - return !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); + DECODE_PRINTF("JNLE\t"); + return !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); } } @@ -156,7 +156,7 @@ void x86emuOp2_long_jump(u8 op2) DECODE_PRINTF2("%04x\n", target); TRACE_AND_STEP(); if (cond) - M.x86.R_IP = (u16)target; + M.x86.R_IP = (u16)target; DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); } @@ -169,89 +169,89 @@ void x86emuOp2_set_byte(u8 op2) { int mod, rl, rh; uint destoffset; - u8 *destreg; + u8 *destreg; char *name = 0; int cond = 0; START_OF_INSTR(); switch (op2) { case 0x90: - name = "SETO\t"; - cond = ACCESS_FLAG(F_OF); - break; + name = "SETO\t"; + cond = ACCESS_FLAG(F_OF); + break; case 0x91: - name = "SETNO\t"; - cond = !ACCESS_FLAG(F_OF); - break; + name = "SETNO\t"; + cond = !ACCESS_FLAG(F_OF); + break; case 0x92: - name = "SETB\t"; - cond = ACCESS_FLAG(F_CF); - break; + name = "SETB\t"; + cond = ACCESS_FLAG(F_CF); + break; case 0x93: - name = "SETNB\t"; - cond = !ACCESS_FLAG(F_CF); - break; + name = "SETNB\t"; + cond = !ACCESS_FLAG(F_CF); + break; case 0x94: - name = "SETZ\t"; - cond = ACCESS_FLAG(F_ZF); - break; + name = "SETZ\t"; + cond = ACCESS_FLAG(F_ZF); + break; case 0x95: - name = "SETNZ\t"; - cond = !ACCESS_FLAG(F_ZF); - break; + name = "SETNZ\t"; + cond = !ACCESS_FLAG(F_ZF); + break; case 0x96: - name = "SETBE\t"; - cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); - break; + name = "SETBE\t"; + cond = ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF); + break; case 0x97: - name = "SETNBE\t"; - cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); - break; + name = "SETNBE\t"; + cond = !(ACCESS_FLAG(F_CF) || ACCESS_FLAG(F_ZF)); + break; case 0x98: - name = "SETS\t"; - cond = ACCESS_FLAG(F_SF); - break; + name = "SETS\t"; + cond = ACCESS_FLAG(F_SF); + break; case 0x99: - name = "SETNS\t"; - cond = !ACCESS_FLAG(F_SF); - break; + name = "SETNS\t"; + cond = !ACCESS_FLAG(F_SF); + break; case 0x9a: - name = "SETP\t"; - cond = ACCESS_FLAG(F_PF); - break; + name = "SETP\t"; + cond = ACCESS_FLAG(F_PF); + break; case 0x9b: - name = "SETNP\t"; - cond = !ACCESS_FLAG(F_PF); - break; + name = "SETNP\t"; + cond = !ACCESS_FLAG(F_PF); + break; case 0x9c: - name = "SETL\t"; - cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; + name = "SETL\t"; + cond = xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; case 0x9d: - name = "SETNL\t"; - cond = !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); - break; + name = "SETNL\t"; + cond = !xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)); + break; case 0x9e: - name = "SETLE\t"; - cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); - break; + name = "SETLE\t"; + cond = (xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; case 0x9f: - name = "SETNLE\t"; - cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || - ACCESS_FLAG(F_ZF)); - break; + name = "SETNLE\t"; + cond = !(xorl(ACCESS_FLAG(F_SF), ACCESS_FLAG(F_OF)) || + ACCESS_FLAG(F_ZF)); + break; } DECODE_PRINTF(name); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - TRACE_AND_STEP(); - store_data_byte(destoffset, cond ? 0x01 : 0x00); - } else { /* register to register */ - destreg = DECODE_RM_BYTE_REGISTER(rl); - TRACE_AND_STEP(); - *destreg = cond ? 0x01 : 0x00; + destoffset = decode_rmXX_address(mod, rl); + TRACE_AND_STEP(); + store_data_byte(destoffset, cond ? 0x01 : 0x00); + } else { /* register to register */ + destreg = DECODE_RM_BYTE_REGISTER(rl); + TRACE_AND_STEP(); + *destreg = cond ? 0x01 : 0x00; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -299,50 +299,50 @@ void x86emuOp2_bt_R(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BT\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); - } else { - u16 srcval; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); - } else { - u16 *srcreg,*shiftreg; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); - } + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } else { + u16 srcval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + CONDITIONAL_SET_FLAG(srcval & (0x1 << bit),F_CF); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } else { + u16 *srcreg,*shiftreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + CONDITIONAL_SET_FLAG(*srcreg & (0x1 << bit),F_CF); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -362,58 +362,58 @@ void x86emuOp2_shld_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shld_long(destval,*shiftreg,shift); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shld_word(destval,*shiftreg,shift); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shld_long(*destreg,*shiftreg,shift); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shld_word(*destreg,*shiftreg,shift); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,shift); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -432,50 +432,50 @@ void x86emuOp2_shld_CL(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shld_long(destval,*shiftreg,M.x86.R_CL); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shld_word(destval,*shiftreg,M.x86.R_CL); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shld_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shld_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shld_word(*destreg,*shiftreg,M.x86.R_CL); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -523,60 +523,60 @@ void x86emuOp2_bts_R(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BTS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval | mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, srcval | mask); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg |= mask; - } else { - u16 *srcreg,*shiftreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg |= mask; - } + srcoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval | mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, srcval | mask); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg |= mask; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -596,58 +596,58 @@ void x86emuOp2_shrd_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shrd_long(destval,*shiftreg,shift); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shrd_word(destval,*shiftreg,shift); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shrd_long(*destreg,*shiftreg,shift); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - shift = fetch_byte_imm(); - DECODE_PRINTF2("%d\n", shift); - TRACE_AND_STEP(); - *destreg = shrd_word(*destreg,*shiftreg,shift); - } + destoffset = decode_rmXX_address(mod, rl); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,shift); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,shift); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,shift); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + shift = fetch_byte_imm(); + DECODE_PRINTF2("%d\n", shift); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,shift); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -666,49 +666,49 @@ void x86emuOp2_shrd_CL(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("SHLD\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 destval; - u32 *shiftreg; - - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_long(destoffset); - destval = shrd_long(destval,*shiftreg,M.x86.R_CL); - store_data_long(destoffset, destval); - } else { - u16 destval; - u16 *shiftreg; - - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - destval = fetch_data_word(destoffset); - destval = shrd_word(destval,*shiftreg,M.x86.R_CL); - store_data_word(destoffset, destval); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*shiftreg; - - destreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL); - } else { - u16 *destreg,*shiftreg; - - destreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(",CL\n"); - TRACE_AND_STEP(); - *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL); - } + destoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 destval; + u32 *shiftreg; + + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_long(destoffset); + destval = shrd_long(destval,*shiftreg,M.x86.R_CL); + store_data_long(destoffset, destval); + } else { + u16 destval; + u16 *shiftreg; + + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + destval = fetch_data_word(destoffset); + destval = shrd_word(destval,*shiftreg,M.x86.R_CL); + store_data_word(destoffset, destval); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*shiftreg; + + destreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_long(*destreg,*shiftreg,M.x86.R_CL); + } else { + u16 *destreg,*shiftreg; + + destreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(",CL\n"); + TRACE_AND_STEP(); + *destreg = shrd_word(*destreg,*shiftreg,M.x86.R_CL); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -727,80 +727,80 @@ void x86emuOp2_imul_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("IMUL\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_long(srcoffset); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg; - u16 srcval; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_word(srcoffset); - TRACE_AND_STEP(); - res = (s16)*destreg * (s16)srcval; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg,*srcreg; - u32 res_lo,res_hi; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_LONG_REGISTER(rl); - TRACE_AND_STEP(); - imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg); - if (res_hi != 0) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u32)res_lo; - } else { - u16 *destreg,*srcreg; - u32 res; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - res = (s16)*destreg * (s16)*srcreg; - if (res > 0xFFFF) { - SET_FLAG(F_CF); - SET_FLAG(F_OF); - } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - } - *destreg = (u16)res; - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_long(srcoffset); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)srcval); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg; + u16 srcval; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + TRACE_AND_STEP(); + res = (s16)*destreg * (s16)srcval; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg,*srcreg; + u32 res_lo,res_hi; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_LONG_REGISTER(rl); + TRACE_AND_STEP(); + imul_long_direct(&res_lo,&res_hi,(s32)*destreg,(s32)*srcreg); + if (res_hi != 0) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u32)res_lo; + } else { + u16 *destreg,*srcreg; + u32 res; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + res = (s16)*destreg * (s16)*srcreg; + if (res > 0xFFFF) { + SET_FLAG(F_CF); + SET_FLAG(F_OF); + } else { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + } + *destreg = (u16)res; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -820,16 +820,16 @@ void x86emuOp2_lss_R_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("LSS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_SS = fetch_data_word(srcoffset + 2); - } else { /* register to register */ - /* UNDEFINED! */ - TRACE_AND_STEP(); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_SS = fetch_data_word(srcoffset + 2); + } else { /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -849,59 +849,59 @@ void x86emuOp2_btr_R(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BTR\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval & ~mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg &= ~mask; - } else { - u16 *srcreg,*shiftreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg &= ~mask; - } + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval & ~mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval & ~mask)); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg &= ~mask; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -921,16 +921,16 @@ void x86emuOp2_lfs_R_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("LFS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_FS = fetch_data_word(srcoffset + 2); - } else { /* register to register */ - /* UNDEFINED! */ - TRACE_AND_STEP(); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_FS = fetch_data_word(srcoffset + 2); + } else { /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -950,16 +950,16 @@ void x86emuOp2_lgs_R_IMM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("LGS\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - dstreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *dstreg = fetch_data_word(srcoffset); - M.x86.R_GS = fetch_data_word(srcoffset + 2); - } else { /* register to register */ - /* UNDEFINED! */ - TRACE_AND_STEP(); + dstreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *dstreg = fetch_data_word(srcoffset); + M.x86.R_GS = fetch_data_word(srcoffset + 2); + } else { /* register to register */ + /* UNDEFINED! */ + TRACE_AND_STEP(); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -978,51 +978,51 @@ void x86emuOp2_movzx_byte_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("MOVZX\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_byte(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } else { - u16 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_byte(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1044,20 +1044,20 @@ void x86emuOp2_movzx_word_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("MOVZX\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = fetch_data_word(srcoffset); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { /* register to register */ - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = *srcreg; + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = fetch_data_word(srcoffset); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = *srcreg; } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1078,122 +1078,122 @@ void x86emuOp2_btX_I(u8 X86EMU_UNUSED(op2)) FETCH_DECODE_MODRM(mod, rh, rl); switch (rh) { case 4: - DECODE_PRINTF("BT\t"); - break; + DECODE_PRINTF("BT\t"); + break; case 5: - DECODE_PRINTF("BTS\t"); - break; + DECODE_PRINTF("BTS\t"); + break; case 6: - DECODE_PRINTF("BTR\t"); - break; + DECODE_PRINTF("BTR\t"); + break; case 7: - DECODE_PRINTF("BTC\t"); - break; + DECODE_PRINTF("BTC\t"); + break; default: - DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); - TRACE_REGS(); - printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", - M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl); - HALT_SYS(); + DECODE_PRINTF("ILLEGAL EXTENDED X86 OPCODE\n"); + TRACE_REGS(); + printk("%04x:%04x: %02X%02X ILLEGAL EXTENDED X86 OPCODE EXTENSION!\n", + M.x86.R_CS, M.x86.R_IP-3,op2, (mod<<6)|(rh<<3)|rl); + HALT_SYS(); } if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - shift = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", shift); - TRACE_AND_STEP(); - - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, mask; - - bit = shift & 0x1F; - srcval = fetch_data_long(srcoffset); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - switch (rh) { - case 5: - store_data_long(srcoffset, srcval | mask); - break; - case 6: - store_data_long(srcoffset, srcval & ~mask); - break; - case 7: - store_data_long(srcoffset, srcval ^ mask); - break; - default: - break; - } - } else { - u16 srcval, mask; - - bit = shift & 0xF; - srcval = fetch_data_word(srcoffset); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - switch (rh) { - case 5: - store_data_word(srcoffset, srcval | mask); - break; - case 6: - store_data_word(srcoffset, srcval & ~mask); - break; - case 7: - store_data_word(srcoffset, srcval ^ mask); - break; - default: - break; - } - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - shift = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", shift); - TRACE_AND_STEP(); - bit = shift & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - switch (rh) { - case 5: - *srcreg |= mask; - break; - case 6: - *srcreg &= ~mask; - break; - case 7: - *srcreg ^= mask; - break; - default: - break; - } - } else { - u16 *srcreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - shift = fetch_byte_imm(); - DECODE_PRINTF2(",%d\n", shift); - TRACE_AND_STEP(); - bit = shift & 0xF; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - switch (rh) { - case 5: - *srcreg |= mask; - break; - case 6: - *srcreg &= ~mask; - break; - case 7: - *srcreg ^= mask; - break; - default: - break; - } - } + srcoffset = decode_rmXX_address(mod, rl); + shift = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", shift); + TRACE_AND_STEP(); + + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, mask; + + bit = shift & 0x1F; + srcval = fetch_data_long(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_long(srcoffset, srcval | mask); + break; + case 6: + store_data_long(srcoffset, srcval & ~mask); + break; + case 7: + store_data_long(srcoffset, srcval ^ mask); + break; + default: + break; + } + } else { + u16 srcval, mask; + + bit = shift & 0xF; + srcval = fetch_data_word(srcoffset); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + switch (rh) { + case 5: + store_data_word(srcoffset, srcval | mask); + break; + case 6: + store_data_word(srcoffset, srcval & ~mask); + break; + case 7: + store_data_word(srcoffset, srcval ^ mask); + break; + default: + break; + } + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + shift = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", shift); + TRACE_AND_STEP(); + bit = shift & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 5: + *srcreg |= mask; + break; + case 6: + *srcreg &= ~mask; + break; + case 7: + *srcreg ^= mask; + break; + default: + break; + } + } else { + u16 *srcreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + shift = fetch_byte_imm(); + DECODE_PRINTF2(",%d\n", shift); + TRACE_AND_STEP(); + bit = shift & 0xF; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + switch (rh) { + case 5: + *srcreg |= mask; + break; + case 6: + *srcreg &= ~mask; + break; + case 7: + *srcreg ^= mask; + break; + default: + break; + } + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1213,59 +1213,59 @@ void x86emuOp2_btc_R(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BTC\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval,mask; - u32 *shiftreg; - - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - disp = (s16)*shiftreg >> 5; - srcval = fetch_data_long(srcoffset+disp); - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_long(srcoffset+disp, srcval ^ mask); - } else { - u16 srcval,mask; - u16 *shiftreg; - - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - disp = (s16)*shiftreg >> 4; - srcval = fetch_data_word(srcoffset+disp); - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(srcval & mask,F_CF); - store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg,*shiftreg; - u32 mask; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0x1F; - mask = (0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg ^= mask; - } else { - u16 *srcreg,*shiftreg; - u16 mask; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - shiftreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - bit = *shiftreg & 0xF; - mask = (u16)(0x1 << bit); - CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); - *srcreg ^= mask; - } + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval,mask; + u32 *shiftreg; + + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + disp = (s16)*shiftreg >> 5; + srcval = fetch_data_long(srcoffset+disp); + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_long(srcoffset+disp, srcval ^ mask); + } else { + u16 srcval,mask; + u16 *shiftreg; + + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + disp = (s16)*shiftreg >> 4; + srcval = fetch_data_word(srcoffset+disp); + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(srcval & mask,F_CF); + store_data_word(srcoffset+disp, (u16)(srcval ^ mask)); + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg,*shiftreg; + u32 mask; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0x1F; + mask = (0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } else { + u16 *srcreg,*shiftreg; + u16 mask; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + shiftreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + bit = *shiftreg & 0xF; + mask = (u16)(0x1 << bit); + CONDITIONAL_SET_FLAG(*srcreg & mask,F_CF); + *srcreg ^= mask; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1284,49 +1284,49 @@ void x86emuOp2_bsf(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BSF\n"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, *dstreg; - - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_long(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 32; (*dstreg)++) - if ((srcval >> *dstreg) & 1) break; - } else { - u16 srcval, *dstreg; - - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_word(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 0; *dstreg < 16; (*dstreg)++) - if ((srcval >> *dstreg) & 1) break; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg, *dstreg; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); - for(*dstreg = 0; *dstreg < 32; (*dstreg)++) - if ((*srcreg >> *dstreg) & 1) break; - } else { - u16 *srcreg, *dstreg; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); - for(*dstreg = 0; *dstreg < 16; (*dstreg)++) - if ((*srcreg >> *dstreg) & 1) break; - } + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((srcval >> *dstreg) & 1) break; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg, *dstreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 0; *dstreg < 32; (*dstreg)++) + if ((*srcreg >> *dstreg) & 1) break; + } else { + u16 *srcreg, *dstreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 0; *dstreg < 16; (*dstreg)++) + if ((*srcreg >> *dstreg) & 1) break; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1345,49 +1345,49 @@ void x86emuOp2_bsr(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("BSF\n"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - srcoffset = decode_rmXX_address(mod, rl); - DECODE_PRINTF(","); - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 srcval, *dstreg; - - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_long(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 31; *dstreg > 0; (*dstreg)--) - if ((srcval >> *dstreg) & 1) break; - } else { - u16 srcval, *dstreg; - - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - srcval = fetch_data_word(srcoffset); - CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); - for(*dstreg = 15; *dstreg > 0; (*dstreg)--) - if ((srcval >> *dstreg) & 1) break; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *srcreg, *dstreg; - - srcreg = DECODE_RM_LONG_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_LONG_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); - for(*dstreg = 31; *dstreg > 0; (*dstreg)--) - if ((*srcreg >> *dstreg) & 1) break; - } else { - u16 *srcreg, *dstreg; - - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF(","); - dstreg = DECODE_RM_WORD_REGISTER(rh); - TRACE_AND_STEP(); - CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); - for(*dstreg = 15; *dstreg > 0; (*dstreg)--) - if ((*srcreg >> *dstreg) & 1) break; - } + srcoffset = decode_rmXX_address(mod, rl); + DECODE_PRINTF(","); + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 srcval, *dstreg; + + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_long(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } else { + u16 srcval, *dstreg; + + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + srcval = fetch_data_word(srcoffset); + CONDITIONAL_SET_FLAG(srcval == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((srcval >> *dstreg) & 1) break; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *srcreg, *dstreg; + + srcreg = DECODE_RM_LONG_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_LONG_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 31; *dstreg > 0; (*dstreg)--) + if ((*srcreg >> *dstreg) & 1) break; + } else { + u16 *srcreg, *dstreg; + + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF(","); + dstreg = DECODE_RM_WORD_REGISTER(rh); + TRACE_AND_STEP(); + CONDITIONAL_SET_FLAG(*srcreg == 0, F_ZF); + for(*dstreg = 15; *dstreg > 0; (*dstreg)--) + if ((*srcreg >> *dstreg) & 1) break; + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1406,51 +1406,51 @@ void x86emuOp2_movsx_byte_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("MOVSX\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u32 srcval; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = (s32)((s8)fetch_data_byte(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { - u16 *destreg; - u16 srcval; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = (s16)((s8)fetch_data_byte(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } - } else { /* register to register */ - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - u32 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = (s32)((s8)*srcreg); - } else { - u16 *destreg; - u8 *srcreg; - - destreg = DECODE_RM_WORD_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_BYTE_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = (s16)((s8)*srcreg); - } + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u32 srcval; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = (s32)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { + u16 *destreg; + u16 srcval; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = (s16)((s8)fetch_data_byte(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } + } else { /* register to register */ + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + u32 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s8)*srcreg); + } else { + u16 *destreg; + u8 *srcreg; + + destreg = DECODE_RM_WORD_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_BYTE_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s16)((s8)*srcreg); + } } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1472,20 +1472,20 @@ void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) DECODE_PRINTF("MOVSX\t"); FETCH_DECODE_MODRM(mod, rh, rl); if (mod < 3) { - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcoffset = decode_rmXX_address(mod, rl); - srcval = (s32)((s16)fetch_data_word(srcoffset)); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = srcval; - } else { /* register to register */ - destreg = DECODE_RM_LONG_REGISTER(rh); - DECODE_PRINTF(","); - srcreg = DECODE_RM_WORD_REGISTER(rl); - DECODE_PRINTF("\n"); - TRACE_AND_STEP(); - *destreg = (s32)((s16)*srcreg); + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcoffset = decode_rmXX_address(mod, rl); + srcval = (s32)((s16)fetch_data_word(srcoffset)); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = srcval; + } else { /* register to register */ + destreg = DECODE_RM_LONG_REGISTER(rh); + DECODE_PRINTF(","); + srcreg = DECODE_RM_WORD_REGISTER(rl); + DECODE_PRINTF("\n"); + TRACE_AND_STEP(); + *destreg = (s32)((s16)*srcreg); } DECODE_CLEAR_SEGOVR(); END_OF_INSTR(); @@ -1498,13 +1498,13 @@ void (*x86emu_optab2[256])(u8) __attribute__((section(".got2"))) = { /* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ /* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ -/* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ -/* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ +/* 0x02 */ x86emuOp2_illegal_op, /* lar (ring 0 PM) */ +/* 0x03 */ x86emuOp2_illegal_op, /* lsl (ring 0 PM) */ /* 0x04 */ x86emuOp2_illegal_op, /* 0x05 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ -/* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ +/* 0x06 */ x86emuOp2_illegal_op, /* clts (ring 0 PM) */ /* 0x07 */ x86emuOp2_illegal_op, /* loadall (undocumented) */ -/* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */ +/* 0x08 */ x86emuOp2_illegal_op, /* invd (ring 0 PM) */ /* 0x09 */ x86emuOp2_illegal_op, /* wbinvd (ring 0 PM) */ /* 0x0a */ x86emuOp2_illegal_op, /* 0x0b */ x86emuOp2_illegal_op, diff --git a/drivers/bios_emulator/x86emu/prim_ops.c b/drivers/bios_emulator/x86emu/prim_ops.c index dc8cea80039..e0827d74782 100644 --- a/drivers/bios_emulator/x86emu/prim_ops.c +++ b/drivers/bios_emulator/x86emu/prim_ops.c @@ -1,10 +1,10 @@ /**************************************************************************** * -* Realmode X86 Emulator Library +* Realmode X86 Emulator Library * -* Copyright (C) 1991-2004 SciTech Software, Inc. -* Copyright (C) David Mosberger-Tang -* Copyright (C) 1999 Egbert Eich +* Copyright (C) 1991-2004 SciTech Software, Inc. +* Copyright (C) David Mosberger-Tang +* Copyright (C) 1999 Egbert Eich * * ======================================================================== * @@ -14,7 +14,7 @@ * both that copyright notice and this permission notice appear in * supporting documentation, and that the name of the authors not be used * in advertising or publicity pertaining to distribution of the software -* without specific, written prior permission. The authors makes no +* without specific, written prior permission. The authors makes no * representations about the suitability of this software for any purpose. * It is provided "as is" without express or implied warranty. * @@ -28,12 +28,12 @@ * * ======================================================================== * -* Language: ANSI C -* Environment: Any -* Developer: Kendall Bennett +* Language: ANSI C +* Environment: Any +* Developer: Kendall Bennett * -* Description: This file contains the code to implement the primitive -* machine operations used by the emulation code in ops.c +* Description: This file contains the code to implement the primitive +* machine operations used by the emulation code in ops.c * * Carry Chain Calculation * @@ -48,23 +48,23 @@ * So, given the following table, which represents the addition of two * bits, we can derive a formula for the carry chain. * -* a b cin r cout -* 0 0 0 0 0 -* 0 0 1 1 0 -* 0 1 0 1 0 -* 0 1 1 0 1 -* 1 0 0 1 0 -* 1 0 1 0 1 -* 1 1 0 0 1 -* 1 1 1 1 1 +* a b cin r cout +* 0 0 0 0 0 +* 0 0 1 1 0 +* 0 1 0 1 0 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 1 +* 1 1 0 0 1 +* 1 1 1 1 1 * * Construction of table for cout: * * ab -* r \ 00 01 11 10 +* r \ 00 01 11 10 * |------------------ -* 0 | 0 1 1 1 -* 1 | 0 0 1 0 +* 0 | 0 1 1 1 +* 1 | 0 0 1 0 * * By inspection, one gets: cc = ab + r'(a + b) * @@ -75,25 +75,25 @@ * The following table represents the subtraction of two bits, from * which we can derive a formula for the borrow chain. * -* a b bin r bout -* 0 0 0 0 0 -* 0 0 1 1 1 -* 0 1 0 1 1 -* 0 1 1 0 1 -* 1 0 0 1 0 -* 1 0 1 0 0 -* 1 1 0 0 0 -* 1 1 1 1 1 +* a b bin r bout +* 0 0 0 0 0 +* 0 0 1 1 1 +* 0 1 0 1 1 +* 0 1 1 0 1 +* 1 0 0 1 0 +* 1 0 1 0 0 +* 1 1 0 0 0 +* 1 1 1 1 1 * * Construction of table for cout: * * ab -* r \ 00 01 11 10 +* r \ 00 01 11 10 * |------------------ -* 0 | 0 1 0 0 -* 1 | 1 1 1 0 +* 0 | 0 1 0 0 +* 1 | 1 1 1 0 * -* By inspection, one gets: bc = a'b + r(a' + b) +* By inspection, one gets: bc = a'b + r(a' + b) * ****************************************************************************/ @@ -115,7 +115,7 @@ static u32 x86emu_parity_tab[8] = }; #define PARITY(x) (((x86emu_parity_tab[(x) / 32] >> ((x) % 32)) & 1) == 0) -#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) +#define XOR2(x) (((x) ^ ((x)>>1)) & 0x1) /*----------------------------- Implementation ----------------------------*/ int abs(int v) { @@ -190,7 +190,7 @@ static void calc_carry_chain(int bits, u32 d, u32 s, u32 res, int set_carry) CONDITIONAL_SET_FLAG(XOR2(cc >> (bits - 2)), F_OF); CONDITIONAL_SET_FLAG(cc & 0x8, F_AF); if (set_carry) { - CONDITIONAL_SET_FLAG(res & (1 << bits), F_CF); + CONDITIONAL_SET_FLAG(res & (1 << bits), F_CF); } } @@ -202,7 +202,7 @@ static void calc_borrow_chain(int bits, u32 d, u32 s, u32 res, int set_carry) CONDITIONAL_SET_FLAG(XOR2(bc >> (bits - 2)), F_OF); CONDITIONAL_SET_FLAG(bc & 0x8, F_AF); if (set_carry) { - CONDITIONAL_SET_FLAG(bc & (1 << (bits - 1)), F_CF); + CONDITIONAL_SET_FLAG(bc & (1 << (bits - 1)), F_CF); } } @@ -214,13 +214,13 @@ u16 aaa_word(u16 d) { u16 res; if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { - d += 0x6; - d += 0x100; - SET_FLAG(F_AF); - SET_FLAG(F_CF); + d += 0x6; + d += 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); } res = (u16)(d & 0xFF0F); set_szp_flags_16(res); @@ -235,13 +235,13 @@ u16 aas_word(u16 d) { u16 res; if ((d & 0xf) > 0x9 || ACCESS_FLAG(F_AF)) { - d -= 0x6; - d -= 0x100; - SET_FLAG(F_AF); - SET_FLAG(F_CF); + d -= 0x6; + d -= 0x100; + SET_FLAG(F_AF); + SET_FLAG(F_CF); } else { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_AF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_AF); } res = (u16)(d & 0xFF0F); set_szp_flags_16(res); @@ -308,7 +308,7 @@ u16 adc_word(u16 d, u16 s) res = d + s; if (ACCESS_FLAG(F_CF)) - res++; + res++; set_szp_flags_16((u16)res); calc_carry_chain(16,s,d,res,1); @@ -330,8 +330,8 @@ u32 adc_long(u32 d, u32 s) res = d + s; if (ACCESS_FLAG(F_CF)) { - lo++; - res++; + lo++; + res++; } hi = (lo >> 16) + (d >> 16) + (s >> 16); @@ -485,12 +485,12 @@ u8 daa_byte(u8 d) { u32 res = d; if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { - res += 6; - SET_FLAG(F_AF); + res += 6; + SET_FLAG(F_AF); } if (res > 0x9F || ACCESS_FLAG(F_CF)) { - res += 0x60; - SET_FLAG(F_CF); + res += 0x60; + SET_FLAG(F_CF); } set_szp_flags_8((u8)res); return (u8)res; @@ -503,12 +503,12 @@ Implements the DAS instruction and side effects. u8 das_byte(u8 d) { if ((d & 0xf) > 9 || ACCESS_FLAG(F_AF)) { - d -= 6; - SET_FLAG(F_AF); + d -= 6; + SET_FLAG(F_AF); } if (d > 0x9F || ACCESS_FLAG(F_CF)) { - d -= 0x60; - SET_FLAG(F_CF); + d -= 0x60; + SET_FLAG(F_CF); } set_szp_flags_8(d); return d; @@ -749,45 +749,45 @@ u8 rcl_byte(u8 d, u8 s) original values, this can be expressed as: IF n > 0 - 1) CF <- b_(8-n) + 1) CF <- b_(8-n) 2) B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 3) B_(n-1) <- cf 4) B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ res = d; if ((cnt = s % 9) != 0) { - /* extract the new CARRY FLAG. */ - /* CF <- b_(8-n) */ - cf = (d >> (8 - cnt)) & 0x1; - - /* get the low stuff which rotated - into the range B_7 .. B_cnt */ - /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ - /* note that the right hand side done by the mask */ - res = (d << cnt) & 0xff; - - /* now the high stuff which rotated around - into the positions B_cnt-2 .. B_0 */ - /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ - /* shift it downward, 7-(n-2) = 9-n positions. - and mask off the result before or'ing in. - */ - mask = (1 << (cnt - 1)) - 1; - res |= (d >> (9 - cnt)) & mask; - - /* if the carry flag was set, or it in. */ - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - /* B_(n-1) <- cf */ - res |= 1 << (cnt - 1); - } - /* set the new carry flag, based on the variable "cf" */ - CONDITIONAL_SET_FLAG(cf, F_CF); - /* OVERFLOW is set *IFF* cnt==1, then it is the - xor of CF and the most significant bit. Blecck. */ - /* parenthesized this expression since it appears to - be causing OF to be misset */ - CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), - F_OF); + /* extract the new CARRY FLAG. */ + /* CF <- b_(8-n) */ + cf = (d >> (8 - cnt)) & 0x1; + + /* get the low stuff which rotated + into the range B_7 .. B_cnt */ + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_0 */ + /* note that the right hand side done by the mask */ + res = (d << cnt) & 0xff; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(n-2) .. B_0 <- b_7 .. b_(8-(n-1)) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (9 - cnt)) & mask; + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(n-1) <- cf */ + res |= 1 << (cnt - 1); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized this expression since it appears to + be causing OF to be misset */ + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 6) & 0x2)), + F_OF); } return (u8)res; @@ -803,16 +803,16 @@ u16 rcl_word(u16 d, u8 s) res = d; if ((cnt = s % 17) != 0) { - cf = (d >> (16 - cnt)) & 0x1; - res = (d << cnt) & 0xffff; - mask = (1 << (cnt - 1)) - 1; - res |= (d >> (17 - cnt)) & mask; - if (ACCESS_FLAG(F_CF)) { - res |= 1 << (cnt - 1); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), - F_OF); + cf = (d >> (16 - cnt)) & 0x1; + res = (d << cnt) & 0xffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (17 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 14) & 0x2)), + F_OF); } return (u16)res; } @@ -827,16 +827,16 @@ u32 rcl_long(u32 d, u8 s) res = d; if ((cnt = s % 33) != 0) { - cf = (d >> (32 - cnt)) & 0x1; - res = (d << cnt) & 0xffffffff; - mask = (1 << (cnt - 1)) - 1; - res |= (d >> (33 - cnt)) & mask; - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - res |= 1 << (cnt - 1); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), - F_OF); + cf = (d >> (32 - cnt)) & 0x1; + res = (d << cnt) & 0xffffffff; + mask = (1 << (cnt - 1)) - 1; + res |= (d >> (33 - cnt)) & mask; + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (cnt - 1); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + CONDITIONAL_SET_FLAG(cnt == 1 && XOR2(cf + ((res >> 30) & 0x2)), + F_OF); } return res; } @@ -867,60 +867,60 @@ u8 rcr_byte(u8 d, u8 s) original values, this can be expressed as: IF n > 0 - 1) CF <- b_(n-1) - 2) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 1) CF <- b_(n-1) + 2) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) 3) B_(8-n) <- cf 4) B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ res = d; if ((cnt = s % 9) != 0) { - /* extract the new CARRY FLAG. */ - /* CF <- b_(n-1) */ - if (cnt == 1) { - cf = d & 0x1; - /* note hackery here. Access_flag(..) evaluates to either - 0 if flag not set - non-zero if flag is set. - doing access_flag(..) != 0 casts that into either - 0..1 in any representation of the flags register - (i.e. packed bit array or unpacked.) - */ - ocf = ACCESS_FLAG(F_CF) != 0; - } else - cf = (d >> (cnt - 1)) & 0x1; - - /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ - /* note that the right hand side done by the mask - This is effectively done by shifting the - object to the right. The result must be masked, - in case the object came in and was treated - as a negative number. Needed??? */ - - mask = (1 << (8 - cnt)) - 1; - res = (d >> cnt) & mask; - - /* now the high stuff which rotated around - into the positions B_cnt-2 .. B_0 */ - /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ - /* shift it downward, 7-(n-2) = 9-n positions. - and mask off the result before or'ing in. - */ - res |= (d << (9 - cnt)); - - /* if the carry flag was set, or it in. */ - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - /* B_(8-n) <- cf */ - res |= 1 << (8 - cnt); - } - /* set the new carry flag, based on the variable "cf" */ - CONDITIONAL_SET_FLAG(cf, F_CF); - /* OVERFLOW is set *IFF* cnt==1, then it is the - xor of CF and the most significant bit. Blecck. */ - /* parenthesized... */ - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), - F_OF); - } + /* extract the new CARRY FLAG. */ + /* CF <- b_(n-1) */ + if (cnt == 1) { + cf = d & 0x1; + /* note hackery here. Access_flag(..) evaluates to either + 0 if flag not set + non-zero if flag is set. + doing access_flag(..) != 0 casts that into either + 0..1 in any representation of the flags register + (i.e. packed bit array or unpacked.) + */ + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_n */ + /* note that the right hand side done by the mask + This is effectively done by shifting the + object to the right. The result must be masked, + in case the object came in and was treated + as a negative number. Needed??? */ + + mask = (1 << (8 - cnt)) - 1; + res = (d >> cnt) & mask; + + /* now the high stuff which rotated around + into the positions B_cnt-2 .. B_0 */ + /* B_(7) .. B_(8-(n-1)) <- b_(n-2) .. b_(0) */ + /* shift it downward, 7-(n-2) = 9-n positions. + and mask off the result before or'ing in. + */ + res |= (d << (9 - cnt)); + + /* if the carry flag was set, or it in. */ + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + /* B_(8-n) <- cf */ + res |= 1 << (8 - cnt); + } + /* set the new carry flag, based on the variable "cf" */ + CONDITIONAL_SET_FLAG(cf, F_CF); + /* OVERFLOW is set *IFF* cnt==1, then it is the + xor of CF and the most significant bit. Blecck. */ + /* parenthesized... */ + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 6) & 0x2)), + F_OF); + } } return (u8)res; } @@ -937,22 +937,22 @@ u16 rcr_word(u16 d, u8 s) /* rotate right through carry */ res = d; if ((cnt = s % 17) != 0) { - if (cnt == 1) { - cf = d & 0x1; - ocf = ACCESS_FLAG(F_CF) != 0; - } else - cf = (d >> (cnt - 1)) & 0x1; - mask = (1 << (16 - cnt)) - 1; - res = (d >> cnt) & mask; - res |= (d << (17 - cnt)); - if (ACCESS_FLAG(F_CF)) { - res |= 1 << (16 - cnt); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), - F_OF); - } + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (16 - cnt)) - 1; + res = (d >> cnt) & mask; + res |= (d << (17 - cnt)); + if (ACCESS_FLAG(F_CF)) { + res |= 1 << (16 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 14) & 0x2)), + F_OF); + } } return (u16)res; } @@ -969,23 +969,23 @@ u32 rcr_long(u32 d, u8 s) /* rotate right through carry */ res = d; if ((cnt = s % 33) != 0) { - if (cnt == 1) { - cf = d & 0x1; - ocf = ACCESS_FLAG(F_CF) != 0; - } else - cf = (d >> (cnt - 1)) & 0x1; - mask = (1 << (32 - cnt)) - 1; - res = (d >> cnt) & mask; - if (cnt != 1) - res |= (d << (33 - cnt)); - if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ - res |= 1 << (32 - cnt); - } - CONDITIONAL_SET_FLAG(cf, F_CF); - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), - F_OF); - } + if (cnt == 1) { + cf = d & 0x1; + ocf = ACCESS_FLAG(F_CF) != 0; + } else + cf = (d >> (cnt - 1)) & 0x1; + mask = (1 << (32 - cnt)) - 1; + res = (d >> cnt) & mask; + if (cnt != 1) + res |= (d << (33 - cnt)); + if (ACCESS_FLAG(F_CF)) { /* carry flag is set */ + res |= 1 << (32 - cnt); + } + CONDITIONAL_SET_FLAG(cf, F_CF); + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(ocf + ((d >> 30) & 0x2)), + F_OF); + } } return res; } @@ -1016,25 +1016,25 @@ u8 rol_byte(u8 d, u8 s) */ res = d; if ((cnt = s % 8) != 0) { - /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ - res = (d << cnt); - - /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ - mask = (1 << cnt) - 1; - res |= (d >> (8 - cnt)) & mask; - - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - /* OVERFLOW is set *IFF* s==1, then it is the - xor of CF and the most significant bit. Blecck. */ - CONDITIONAL_SET_FLAG(s == 1 && - XOR2((res & 0x1) + ((res >> 6) & 0x2)), - F_OF); + /* B_(7) .. B_(n) <- b_(8-(n+1)) .. b_(0) */ + res = (d << cnt); + + /* B_(n-1) .. B_(0) <- b_(7) .. b_(8-n) */ + mask = (1 << cnt) - 1; + res |= (d >> (8 - cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of CF and the most significant bit. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 6) & 0x2)), + F_OF); } if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); } return (u8)res; } @@ -1049,17 +1049,17 @@ u16 rol_word(u16 d, u8 s) res = d; if ((cnt = s % 16) != 0) { - res = (d << cnt); - mask = (1 << cnt) - 1; - res |= (d >> (16 - cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && - XOR2((res & 0x1) + ((res >> 14) & 0x2)), - F_OF); + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (16 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 14) & 0x2)), + F_OF); } if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); } return (u16)res; } @@ -1074,17 +1074,17 @@ u32 rol_long(u32 d, u8 s) res = d; if ((cnt = s % 32) != 0) { - res = (d << cnt); - mask = (1 << cnt) - 1; - res |= (d >> (32 - cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && - XOR2((res & 0x1) + ((res >> 30) & 0x2)), - F_OF); + res = (d << cnt); + mask = (1 << cnt) - 1; + res |= (d >> (32 - cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && + XOR2((res & 0x1) + ((res >> 30) & 0x2)), + F_OF); } if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x1, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x1, F_CF); } return res; } @@ -1109,28 +1109,28 @@ u8 ror_byte(u8 d, u8 s) The rotate is done mod 8. IF n > 0 - 1) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) + 1) B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) 2) B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ res = d; - if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ - /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ - res = (d << (8 - cnt)); - - /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ - mask = (1 << (8 - cnt)) - 1; - res |= (d >> (cnt)) & mask; - - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x80, F_CF); - /* OVERFLOW is set *IFF* s==1, then it is the - xor of the two most significant bits. Blecck. */ - CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); + if ((cnt = s % 8) != 0) { /* not a typo, do nada if cnt==0 */ + /* B_(7) .. B_(8-n) <- b_(n-1) .. b_(0) */ + res = (d << (8 - cnt)); + + /* B_(8-(n+1)) .. B_(0) <- b_(7) .. b_(n) */ + mask = (1 << (8 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + /* OVERFLOW is set *IFF* s==1, then it is the + xor of the two most significant bits. Blecck. */ + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 6), F_OF); } else if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x80, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80, F_CF); } return (u8)res; } @@ -1145,15 +1145,15 @@ u16 ror_word(u16 d, u8 s) res = d; if ((cnt = s % 16) != 0) { - res = (d << (16 - cnt)); - mask = (1 << (16 - cnt)) - 1; - res |= (d >> (cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); + res = (d << (16 - cnt)); + mask = (1 << (16 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 14), F_OF); } else if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x8000, F_CF); } return (u16)res; } @@ -1168,15 +1168,15 @@ u32 ror_long(u32 d, u8 s) res = d; if ((cnt = s % 32) != 0) { - res = (d << (32 - cnt)); - mask = (1 << (32 - cnt)) - 1; - res |= (d >> (cnt)) & mask; - CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); - CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); + res = (d << (32 - cnt)); + mask = (1 << (32 - cnt)) - 1; + res |= (d >> (cnt)) & mask; + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + CONDITIONAL_SET_FLAG(s == 1 && XOR2(res >> 30), F_OF); } else if (s != 0) { - /* set the new carry flag, Note that it is the low order - bit of the result!!! */ - CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); + /* set the new carry flag, Note that it is the low order + bit of the result!!! */ + CONDITIONAL_SET_FLAG(res & 0x80000000, F_CF); } return res; } @@ -1190,35 +1190,35 @@ u8 shl_byte(u8 d, u8 s) unsigned int cnt, res, cf; if (s < 8) { - cnt = s % 8; - - /* last bit shifted out goes into carry flag */ - if (cnt > 0) { - res = d << cnt; - cf = d & (1 << (8 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_8((u8)res); - } else { - res = (u8) d; - } - - if (cnt == 1) { - /* Needs simplification. */ - CONDITIONAL_SET_FLAG( - (((res & 0x80) == 0x80) ^ - (ACCESS_FLAG(F_CF) != 0)), - /* was (M.x86.R_FLG&F_CF)==F_CF)), */ - F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 8; + + /* last bit shifted out goes into carry flag */ + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (8 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_8((u8)res); + } else { + res = (u8) d; + } + + if (cnt == 1) { + /* Needs simplification. */ + CONDITIONAL_SET_FLAG( + (((res & 0x80) == 0x80) ^ + (ACCESS_FLAG(F_CF) != 0)), + /* was (M.x86.R_FLG&F_CF)==F_CF)), */ + F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return (u8)res; } @@ -1232,31 +1232,31 @@ u16 shl_word(u16 d, u8 s) unsigned int cnt, res, cf; if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - res = d << cnt; - cf = d & (1 << (16 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_16((u16)res); - } else { - res = (u16) d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG( - (((res & 0x8000) == 0x8000) ^ - (ACCESS_FLAG(F_CF) != 0)), - F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 16; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = (u16) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG( + (((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), + F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return (u16)res; } @@ -1270,28 +1270,28 @@ u32 shl_long(u32 d, u8 s) unsigned int cnt, res, cf; if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - res = d << cnt; - cf = d & (1 << (32 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_32((u32)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ - (ACCESS_FLAG(F_CF) != 0)), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 32; + if (cnt > 0) { + res = d << cnt; + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return res; } @@ -1305,28 +1305,28 @@ u8 shr_byte(u8 d, u8 s) unsigned int cnt, res, cf; if (s < 8) { - cnt = s % 8; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = d >> cnt; - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_8((u8)res); - } else { - res = (u8) d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 8; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_8((u8)res); + } else { + res = (u8) d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 6), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d >> (s-1)) & 0x1, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return (u8)res; } @@ -1340,28 +1340,28 @@ u16 shr_word(u16 d, u8 s) unsigned int cnt, res, cf; if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = d >> cnt; - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_16((u16)res); - } else { - res = d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); } return (u16)res; } @@ -1375,27 +1375,27 @@ u32 shr_long(u32 d, u8 s) unsigned int cnt, res, cf; if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = d >> cnt; - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_32((u32)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = d >> cnt; + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); } return res; } @@ -1412,28 +1412,28 @@ u8 sar_byte(u8 d, u8 s) sf = d & 0x80; cnt = s % 8; if (cnt > 0 && cnt < 8) { - mask = (1 << (8 - cnt)) - 1; - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) & mask; - CONDITIONAL_SET_FLAG(cf, F_CF); - if (sf) { - res |= ~mask; - } - set_szp_flags_8((u8)res); + mask = (1 << (8 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + set_szp_flags_8((u8)res); } else if (cnt >= 8) { - if (sf) { - res = 0xff; - SET_FLAG(F_CF); - CLEAR_FLAG(F_ZF); - SET_FLAG(F_SF); - SET_FLAG(F_PF); - } else { - res = 0; - CLEAR_FLAG(F_CF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } + if (sf) { + res = 0xff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } } return (u8)res; } @@ -1450,28 +1450,28 @@ u16 sar_word(u16 d, u8 s) cnt = s % 16; res = d; if (cnt > 0 && cnt < 16) { - mask = (1 << (16 - cnt)) - 1; - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) & mask; - CONDITIONAL_SET_FLAG(cf, F_CF); - if (sf) { - res |= ~mask; - } - set_szp_flags_16((u16)res); + mask = (1 << (16 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + set_szp_flags_16((u16)res); } else if (cnt >= 16) { - if (sf) { - res = 0xffff; - SET_FLAG(F_CF); - CLEAR_FLAG(F_ZF); - SET_FLAG(F_SF); - SET_FLAG(F_PF); - } else { - res = 0; - CLEAR_FLAG(F_CF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } + if (sf) { + res = 0xffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } } return (u16)res; } @@ -1488,28 +1488,28 @@ u32 sar_long(u32 d, u8 s) cnt = s % 32; res = d; if (cnt > 0 && cnt < 32) { - mask = (1 << (32 - cnt)) - 1; - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) & mask; - CONDITIONAL_SET_FLAG(cf, F_CF); - if (sf) { - res |= ~mask; - } - set_szp_flags_32(res); + mask = (1 << (32 - cnt)) - 1; + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) & mask; + CONDITIONAL_SET_FLAG(cf, F_CF); + if (sf) { + res |= ~mask; + } + set_szp_flags_32(res); } else if (cnt >= 32) { - if (sf) { - res = 0xffffffff; - SET_FLAG(F_CF); - CLEAR_FLAG(F_ZF); - SET_FLAG(F_SF); - SET_FLAG(F_PF); - } else { - res = 0; - CLEAR_FLAG(F_CF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); - } + if (sf) { + res = 0xffffffff; + SET_FLAG(F_CF); + CLEAR_FLAG(F_ZF); + SET_FLAG(F_SF); + SET_FLAG(F_PF); + } else { + res = 0; + CLEAR_FLAG(F_CF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); + } } return res; } @@ -1523,28 +1523,28 @@ u16 shld_word (u16 d, u16 fill, u8 s) unsigned int cnt, res, cf; if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - res = (d << cnt) | (fill >> (16-cnt)); - cf = d & (1 << (16 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_16((u16)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ - (ACCESS_FLAG(F_CF) != 0)), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 16; + if (cnt > 0) { + res = (d << cnt) | (fill >> (16-cnt)); + cf = d & (1 << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x8000) == 0x8000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x8000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return (u16)res; } @@ -1558,28 +1558,28 @@ u32 shld_long (u32 d, u32 fill, u8 s) unsigned int cnt, res, cf; if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - res = (d << cnt) | (fill >> (32-cnt)); - cf = d & (1 << (32 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_32((u32)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ - (ACCESS_FLAG(F_CF) != 0)), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 32; + if (cnt > 0) { + res = (d << cnt) | (fill >> (32-cnt)); + cf = d & (1 << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG((((res & 0x80000000) == 0x80000000) ^ + (ACCESS_FLAG(F_CF) != 0)), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); - CLEAR_FLAG(F_OF); - CLEAR_FLAG(F_SF); - SET_FLAG(F_PF); - SET_FLAG(F_ZF); + res = 0; + CONDITIONAL_SET_FLAG((d << (s-1)) & 0x80000000, F_CF); + CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_SF); + SET_FLAG(F_PF); + SET_FLAG(F_ZF); } return res; } @@ -1593,28 +1593,28 @@ u16 shrd_word (u16 d, u16 fill, u8 s) unsigned int cnt, res, cf; if (s < 16) { - cnt = s % 16; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) | (fill << (16 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_16((u16)res); - } else { - res = d; - } - - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 16; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (16 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_16((u16)res); + } else { + res = d; + } + + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 14), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); } return (u16)res; } @@ -1628,27 +1628,27 @@ u32 shrd_long (u32 d, u32 fill, u8 s) unsigned int cnt, res, cf; if (s < 32) { - cnt = s % 32; - if (cnt > 0) { - cf = d & (1 << (cnt - 1)); - res = (d >> cnt) | (fill << (32 - cnt)); - CONDITIONAL_SET_FLAG(cf, F_CF); - set_szp_flags_32((u32)res); - } else { - res = d; - } - if (cnt == 1) { - CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); - } else { - CLEAR_FLAG(F_OF); - } + cnt = s % 32; + if (cnt > 0) { + cf = d & (1 << (cnt - 1)); + res = (d >> cnt) | (fill << (32 - cnt)); + CONDITIONAL_SET_FLAG(cf, F_CF); + set_szp_flags_32((u32)res); + } else { + res = d; + } + if (cnt == 1) { + CONDITIONAL_SET_FLAG(XOR2(res >> 30), F_OF); + } else { + CLEAR_FLAG(F_OF); + } } else { - res = 0; - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); - SET_FLAG(F_ZF); - CLEAR_FLAG(F_SF); - CLEAR_FLAG(F_PF); + res = 0; + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); + SET_FLAG(F_ZF); + CLEAR_FLAG(F_SF); + CLEAR_FLAG(F_PF); } return res; } @@ -1663,9 +1663,9 @@ u8 sbb_byte(u8 d, u8 s) u32 bc; if (ACCESS_FLAG(F_CF)) - res = d - s - 1; + res = d - s - 1; else - res = d - s; + res = d - s; set_szp_flags_8((u8)res); /* calculate the borrow chain. See note at top */ @@ -1686,9 +1686,9 @@ u16 sbb_word(u16 d, u16 s) u32 bc; if (ACCESS_FLAG(F_CF)) - res = d - s - 1; + res = d - s - 1; else - res = d - s; + res = d - s; set_szp_flags_16((u16)res); /* calculate the borrow chain. See note at top */ @@ -1709,9 +1709,9 @@ u32 sbb_long(u32 d, u32 s) u32 bc; if (ACCESS_FLAG(F_CF)) - res = d - s - 1; + res = d - s - 1; else - res = d - s; + res = d - s; set_szp_flags_32(res); @@ -1880,12 +1880,12 @@ void imul_byte(u8 s) M.x86.R_AX = res; if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) || - ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } } @@ -1900,12 +1900,12 @@ void imul_word(u16 s) M.x86.R_AX = (u16)res; M.x86.R_DX = (u16)(res >> 16); if (((M.x86.R_AX & 0x8000) == 0 && M.x86.R_DX == 0x0000) || - ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFFFF)) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + ((M.x86.R_AX & 0x8000) != 0 && M.x86.R_DX == 0xFFFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } } @@ -1915,7 +1915,7 @@ Implements the IMUL instruction and side effects. ****************************************************************************/ void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) { -#ifdef __HAS_LONG_LONG__ +#ifdef __HAS_LONG_LONG__ s64 res = (s32)d * (s32)s; *res_lo = (u32)res; @@ -1926,11 +1926,11 @@ void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) u32 rlo_lo,rlo_hi,rhi_lo; if ((d_sign = d & 0x80000000) != 0) - d = -d; + d = -d; d_lo = d & 0xFFFF; d_hi = d >> 16; if ((s_sign = s & 0x80000000) != 0) - s = -s; + s = -s; s_lo = s & 0xFFFF; s_hi = s >> 16; rlo_lo = d_lo * s_lo; @@ -1939,11 +1939,11 @@ void imul_long_direct(u32 *res_lo, u32* res_hi,u32 d, u32 s) *res_lo = (rlo_hi << 16) | (rlo_lo & 0xFFFF); *res_hi = rhi_lo; if (d_sign != s_sign) { - d = ~*res_lo; - s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16); - *res_lo = ~*res_lo+1; - *res_hi = ~*res_hi+(s >> 16); - } + d = ~*res_lo; + s = (((d & 0xFFFF) + 1) >> 16) + (d >> 16); + *res_lo = ~*res_lo+1; + *res_hi = ~*res_hi+(s >> 16); + } #endif } @@ -1955,12 +1955,12 @@ void imul_long(u32 s) { imul_long_direct(&M.x86.R_EAX,&M.x86.R_EDX,M.x86.R_EAX,s); if (((M.x86.R_EAX & 0x80000000) == 0 && M.x86.R_EDX == 0x00000000) || - ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFFFFFFFF)) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + ((M.x86.R_EAX & 0x80000000) != 0 && M.x86.R_EDX == 0xFFFFFFFF)) { + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } } @@ -1974,11 +1974,11 @@ void mul_byte(u8 s) M.x86.R_AX = res; if (M.x86.R_AH == 0) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } } @@ -1993,11 +1993,11 @@ void mul_word(u16 s) M.x86.R_AX = (u16)res; M.x86.R_DX = (u16)(res >> 16); if (M.x86.R_DX == 0) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } } @@ -2007,7 +2007,7 @@ Implements the MUL instruction and side effects. ****************************************************************************/ void mul_long(u32 s) { -#ifdef __HAS_LONG_LONG__ +#ifdef __HAS_LONG_LONG__ u64 res = (u32)M.x86.R_EAX * (u32)s; M.x86.R_EAX = (u32)res; @@ -2029,11 +2029,11 @@ void mul_long(u32 s) M.x86.R_EDX = rhi_lo; #endif if (M.x86.R_EDX == 0) { - CLEAR_FLAG(F_CF); - CLEAR_FLAG(F_OF); + CLEAR_FLAG(F_CF); + CLEAR_FLAG(F_OF); } else { - SET_FLAG(F_CF); - SET_FLAG(F_OF); + SET_FLAG(F_CF); + SET_FLAG(F_OF); } } @@ -2047,14 +2047,14 @@ void idiv_byte(u8 s) dvd = (s16)M.x86.R_AX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (s8)s; mod = dvd % (s8)s; if (abs(div) > 0x7f) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } M.x86.R_AL = (s8) div; M.x86.R_AH = (s8) mod; @@ -2070,14 +2070,14 @@ void idiv_word(u16 s) dvd = (((s32)M.x86.R_DX) << 16) | M.x86.R_AX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (s16)s; mod = dvd % (s16)s; if (abs(div) > 0x7fff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } CLEAR_FLAG(F_CF); CLEAR_FLAG(F_SF); @@ -2094,19 +2094,19 @@ Implements the IDIV instruction and side effects. ****************************************************************************/ void idiv_long(u32 s) { -#ifdef __HAS_LONG_LONG__ +#ifdef __HAS_LONG_LONG__ s64 dvd, div, mod; dvd = (((s64)M.x86.R_EDX) << 32) | M.x86.R_EAX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (s32)s; mod = dvd % (s32)s; if (abs(div) > 0x7fffffff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } #else s32 div = 0, mod; @@ -2120,32 +2120,32 @@ void idiv_long(u32 s) int carry; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } do { - div <<= 1; - carry = (l_dvd >= l_s) ? 0 : 1; - - if (abs_h_dvd < (h_s + carry)) { - h_s >>= 1; - l_s = abs_s << (--counter); - continue; - } else { - abs_h_dvd -= (h_s + carry); - l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) - : (l_dvd - l_s); - h_s >>= 1; - l_s = abs_s << (--counter); - div |= 1; - continue; - } + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (abs_h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = abs_s << (--counter); + continue; + } else { + abs_h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = abs_s << (--counter); + div |= 1; + continue; + } } while (counter > -1); /* overflow */ if (abs_h_dvd || (l_dvd > abs_s)) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } /* sign */ div |= ((h_dvd & 0x10000000) ^ (s & 0x10000000)); @@ -2172,14 +2172,14 @@ void div_byte(u8 s) dvd = M.x86.R_AX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (u8)s; mod = dvd % (u8)s; if (abs(div) > 0xff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } M.x86.R_AL = (u8)div; M.x86.R_AH = (u8)mod; @@ -2195,14 +2195,14 @@ void div_word(u16 s) dvd = (((u32)M.x86.R_DX) << 16) | M.x86.R_AX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (u16)s; mod = dvd % (u16)s; if (abs(div) > 0xffff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } CLEAR_FLAG(F_CF); CLEAR_FLAG(F_SF); @@ -2219,19 +2219,19 @@ Implements the DIV instruction and side effects. ****************************************************************************/ void div_long(u32 s) { -#ifdef __HAS_LONG_LONG__ +#ifdef __HAS_LONG_LONG__ u64 dvd, div, mod; dvd = (((u64)M.x86.R_EDX) << 32) | M.x86.R_EAX; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } div = dvd / (u32)s; mod = dvd % (u32)s; if (abs(div) > 0xffffffff) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } #else s32 div = 0, mod; @@ -2244,32 +2244,32 @@ void div_long(u32 s) int carry; if (s == 0) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } do { - div <<= 1; - carry = (l_dvd >= l_s) ? 0 : 1; - - if (h_dvd < (h_s + carry)) { - h_s >>= 1; - l_s = s << (--counter); - continue; - } else { - h_dvd -= (h_s + carry); - l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) - : (l_dvd - l_s); - h_s >>= 1; - l_s = s << (--counter); - div |= 1; - continue; - } + div <<= 1; + carry = (l_dvd >= l_s) ? 0 : 1; + + if (h_dvd < (h_s + carry)) { + h_s >>= 1; + l_s = s << (--counter); + continue; + } else { + h_dvd -= (h_s + carry); + l_dvd = carry ? ((0xFFFFFFFF - l_s) + l_dvd + 1) + : (l_dvd - l_s); + h_s >>= 1; + l_s = s << (--counter); + div |= 1; + continue; + } } while (counter > -1); /* overflow */ if (h_dvd || (l_dvd > s)) { - x86emu_intr_raise(0); - return; + x86emu_intr_raise(0); + return; } mod = l_dvd; #endif @@ -2291,11 +2291,11 @@ Implements the IN string instruction and side effects. static void single_in(int size) { if(size == 1) - store_data_byte_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inb)(M.x86.R_DX)); + store_data_byte_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inb)(M.x86.R_DX)); else if (size == 2) - store_data_word_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inw)(M.x86.R_DX)); + store_data_word_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inw)(M.x86.R_DX)); else - store_data_long_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inl)(M.x86.R_DX)); + store_data_long_abs(M.x86.R_ES, M.x86.R_DI,(*sys_inl)(M.x86.R_DX)); } void ins(int size) @@ -2303,26 +2303,26 @@ void ins(int size) int inc = size; if (ACCESS_FLAG(F_DF)) { - inc = -size; + inc = -size; } if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* in until CX is ZERO. */ - u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? - M.x86.R_ECX : M.x86.R_CX); - - while (count--) { - single_in(size); - M.x86.R_DI += inc; - } - M.x86.R_CX = 0; - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ECX = 0; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* in until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + + while (count--) { + single_in(size); + M.x86.R_DI += inc; + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - single_in(size); - M.x86.R_DI += inc; + single_in(size); + M.x86.R_DI += inc; } } @@ -2346,31 +2346,31 @@ void outs(int size) int inc = size; if (ACCESS_FLAG(F_DF)) { - inc = -size; + inc = -size; } if (M.x86.mode & (SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE)) { - /* dont care whether REPE or REPNE */ - /* out until CX is ZERO. */ - u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? - M.x86.R_ECX : M.x86.R_CX); - while (count--) { - single_out(size); - M.x86.R_SI += inc; - } - M.x86.R_CX = 0; - if (M.x86.mode & SYSMODE_PREFIX_DATA) { - M.x86.R_ECX = 0; - } - M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); + /* dont care whether REPE or REPNE */ + /* out until CX is ZERO. */ + u32 count = ((M.x86.mode & SYSMODE_PREFIX_DATA) ? + M.x86.R_ECX : M.x86.R_CX); + while (count--) { + single_out(size); + M.x86.R_SI += inc; + } + M.x86.R_CX = 0; + if (M.x86.mode & SYSMODE_PREFIX_DATA) { + M.x86.R_ECX = 0; + } + M.x86.mode &= ~(SYSMODE_PREFIX_REPE | SYSMODE_PREFIX_REPNE); } else { - single_out(size); - M.x86.R_SI += inc; + single_out(size); + M.x86.R_SI += inc; } } /**************************************************************************** PARAMETERS: -addr - Address to fetch word from +addr - Address to fetch word from REMARKS: Fetches a word from emulator memory using an absolute address. @@ -2443,4 +2443,3 @@ DB( if (CHECK_SP_ACCESS()) M.x86.R_SP += 4; return res; } - diff --git a/include/radeon.h b/include/radeon.h index f4e24a7134b..3d11b0572b2 100644 --- a/include/radeon.h +++ b/include/radeon.h @@ -5,971 +5,971 @@ #define RADEON_REGSIZE 0x4000 -#define MM_INDEX 0x0000 -#define MM_DATA 0x0004 -#define BUS_CNTL 0x0030 -#define HI_STAT 0x004C -#define BUS_CNTL1 0x0034 -#define I2C_CNTL_1 0x0094 -#define CONFIG_CNTL 0x00E0 -#define CONFIG_MEMSIZE 0x00F8 -#define CONFIG_APER_0_BASE 0x0100 -#define CONFIG_APER_1_BASE 0x0104 -#define CONFIG_APER_SIZE 0x0108 -#define CONFIG_REG_1_BASE 0x010C -#define CONFIG_REG_APER_SIZE 0x0110 -#define PAD_AGPINPUT_DELAY 0x0164 -#define PAD_CTLR_STRENGTH 0x0168 -#define PAD_CTLR_UPDATE 0x016C -#define PAD_CTLR_MISC 0x0aa0 -#define AGP_CNTL 0x0174 -#define BM_STATUS 0x0160 -#define CAP0_TRIG_CNTL 0x0950 -#define CAP1_TRIG_CNTL 0x09c0 -#define VIPH_CONTROL 0x0C40 -#define VENDOR_ID 0x0F00 -#define DEVICE_ID 0x0F02 -#define COMMAND 0x0F04 -#define STATUS 0x0F06 -#define REVISION_ID 0x0F08 -#define REGPROG_INF 0x0F09 -#define SUB_CLASS 0x0F0A -#define BASE_CODE 0x0F0B -#define CACHE_LINE 0x0F0C -#define LATENCY 0x0F0D -#define HEADER 0x0F0E -#define BIST 0x0F0F -#define REG_MEM_BASE 0x0F10 -#define REG_IO_BASE 0x0F14 -#define REG_REG_BASE 0x0F18 -#define ADAPTER_ID 0x0F2C -#define BIOS_ROM 0x0F30 -#define CAPABILITIES_PTR 0x0F34 -#define INTERRUPT_LINE 0x0F3C -#define INTERRUPT_PIN 0x0F3D -#define MIN_GRANT 0x0F3E -#define MAX_LATENCY 0x0F3F -#define ADAPTER_ID_W 0x0F4C -#define PMI_CAP_ID 0x0F50 -#define PMI_NXT_CAP_PTR 0x0F51 -#define PMI_PMC_REG 0x0F52 -#define PM_STATUS 0x0F54 -#define PMI_DATA 0x0F57 -#define AGP_CAP_ID 0x0F58 -#define AGP_STATUS 0x0F5C -#define AGP_COMMAND 0x0F60 -#define AIC_CTRL 0x01D0 -#define AIC_STAT 0x01D4 -#define AIC_PT_BASE 0x01D8 -#define AIC_LO_ADDR 0x01DC -#define AIC_HI_ADDR 0x01E0 -#define AIC_TLB_ADDR 0x01E4 -#define AIC_TLB_DATA 0x01E8 -#define DAC_CNTL 0x0058 -#define DAC_CNTL2 0x007c -#define CRTC_GEN_CNTL 0x0050 -#define MEM_CNTL 0x0140 -#define MC_CNTL 0x0140 -#define EXT_MEM_CNTL 0x0144 -#define MC_TIMING_CNTL 0x0144 -#define MC_AGP_LOCATION 0x014C -#define MEM_IO_CNTL_A0 0x0178 -#define MEM_REFRESH_CNTL 0x0178 -#define MEM_INIT_LATENCY_TIMER 0x0154 -#define MC_INIT_GFX_LAT_TIMER 0x0154 -#define MEM_SDRAM_MODE_REG 0x0158 -#define AGP_BASE 0x0170 -#define MEM_IO_CNTL_A1 0x017C -#define MC_READ_CNTL_AB 0x017C -#define MEM_IO_CNTL_B0 0x0180 -#define MC_INIT_MISC_LAT_TIMER 0x0180 -#define MEM_IO_CNTL_B1 0x0184 -#define MC_IOPAD_CNTL 0x0184 -#define MC_DEBUG 0x0188 -#define MC_STATUS 0x0150 -#define MEM_IO_OE_CNTL 0x018C -#define MC_CHIP_IO_OE_CNTL_AB 0x018C -#define MC_FB_LOCATION 0x0148 -//#define MC_FB_LOCATION 0x0188 -#define HOST_PATH_CNTL 0x0130 -#define MEM_VGA_WP_SEL 0x0038 -#define MEM_VGA_RP_SEL 0x003C -#define HDP_DEBUG 0x0138 -#define SW_SEMAPHORE 0x013C -#define CRTC2_GEN_CNTL 0x03f8 -#define CRTC2_DISPLAY_BASE_ADDR 0x033c -#define SURFACE_CNTL 0x0B00 -#define SURFACE0_LOWER_BOUND 0x0B04 -#define SURFACE1_LOWER_BOUND 0x0B14 -#define SURFACE2_LOWER_BOUND 0x0B24 -#define SURFACE3_LOWER_BOUND 0x0B34 -#define SURFACE4_LOWER_BOUND 0x0B44 -#define SURFACE5_LOWER_BOUND 0x0B54 -#define SURFACE6_LOWER_BOUND 0x0B64 -#define SURFACE7_LOWER_BOUND 0x0B74 -#define SURFACE0_UPPER_BOUND 0x0B08 -#define SURFACE1_UPPER_BOUND 0x0B18 -#define SURFACE2_UPPER_BOUND 0x0B28 -#define SURFACE3_UPPER_BOUND 0x0B38 -#define SURFACE4_UPPER_BOUND 0x0B48 -#define SURFACE5_UPPER_BOUND 0x0B58 -#define SURFACE6_UPPER_BOUND 0x0B68 -#define SURFACE7_UPPER_BOUND 0x0B78 -#define SURFACE0_INFO 0x0B0C -#define SURFACE1_INFO 0x0B1C -#define SURFACE2_INFO 0x0B2C -#define SURFACE3_INFO 0x0B3C -#define SURFACE4_INFO 0x0B4C -#define SURFACE5_INFO 0x0B5C -#define SURFACE6_INFO 0x0B6C -#define SURFACE7_INFO 0x0B7C -#define SURFACE_ACCESS_FLAGS 0x0BF8 -#define SURFACE_ACCESS_CLR 0x0BFC -#define GEN_INT_CNTL 0x0040 -#define GEN_INT_STATUS 0x0044 -#define CRTC_EXT_CNTL 0x0054 -#define RB3D_CNTL 0x1C3C -#define WAIT_UNTIL 0x1720 -#define ISYNC_CNTL 0x1724 -#define RBBM_GUICNTL 0x172C -#define RBBM_STATUS 0x0E40 -#define RBBM_STATUS_alt_1 0x1740 -#define RBBM_CNTL 0x00EC -#define RBBM_CNTL_alt_1 0x0E44 -#define RBBM_SOFT_RESET 0x00F0 -#define RBBM_SOFT_RESET_alt_1 0x0E48 -#define NQWAIT_UNTIL 0x0E50 -#define RBBM_DEBUG 0x0E6C -#define RBBM_CMDFIFO_ADDR 0x0E70 -#define RBBM_CMDFIFO_DATAL 0x0E74 -#define RBBM_CMDFIFO_DATAH 0x0E78 -#define RBBM_CMDFIFO_STAT 0x0E7C -#define CRTC_STATUS 0x005C -#define GPIO_VGA_DDC 0x0060 -#define GPIO_DVI_DDC 0x0064 -#define GPIO_MONID 0x0068 -#define GPIO_CRT2_DDC 0x006c -#define PALETTE_INDEX 0x00B0 -#define PALETTE_DATA 0x00B4 -#define PALETTE_30_DATA 0x00B8 -#define CRTC_H_TOTAL_DISP 0x0200 -#define CRTC_H_SYNC_STRT_WID 0x0204 -#define CRTC_V_TOTAL_DISP 0x0208 -#define CRTC_V_SYNC_STRT_WID 0x020C -#define CRTC_VLINE_CRNT_VLINE 0x0210 -#define CRTC_CRNT_FRAME 0x0214 -#define CRTC_GUI_TRIG_VLINE 0x0218 -#define CRTC_DEBUG 0x021C -#define CRTC_OFFSET_RIGHT 0x0220 -#define CRTC_OFFSET 0x0224 -#define CRTC_OFFSET_CNTL 0x0228 -#define CRTC_PITCH 0x022C -#define OVR_CLR 0x0230 -#define OVR_WID_LEFT_RIGHT 0x0234 -#define OVR_WID_TOP_BOTTOM 0x0238 -#define DISPLAY_BASE_ADDR 0x023C -#define SNAPSHOT_VH_COUNTS 0x0240 -#define SNAPSHOT_F_COUNT 0x0244 -#define N_VIF_COUNT 0x0248 -#define SNAPSHOT_VIF_COUNT 0x024C -#define FP_CRTC_H_TOTAL_DISP 0x0250 -#define FP_CRTC_V_TOTAL_DISP 0x0254 -#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 -#define CRT_CRTC_V_SYNC_STRT_WID 0x025C -#define CUR_OFFSET 0x0260 -#define CUR_HORZ_VERT_POSN 0x0264 -#define CUR_HORZ_VERT_OFF 0x0268 -#define CUR_CLR0 0x026C -#define CUR_CLR1 0x0270 -#define FP_HORZ_VERT_ACTIVE 0x0278 -#define CRTC_MORE_CNTL 0x027C -#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) -#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) -#define DAC_EXT_CNTL 0x0280 -#define FP_GEN_CNTL 0x0284 -#define FP_HORZ_STRETCH 0x028C -#define FP_VERT_STRETCH 0x0290 -#define FP_H_SYNC_STRT_WID 0x02C4 -#define FP_V_SYNC_STRT_WID 0x02C8 -#define AUX_WINDOW_HORZ_CNTL 0x02D8 -#define AUX_WINDOW_VERT_CNTL 0x02DC -//#define DDA_CONFIG 0x02e0 -//#define DDA_ON_OFF 0x02e4 -#define DVI_I2C_CNTL_1 0x02e4 -#define GRPH_BUFFER_CNTL 0x02F0 -#define GRPH2_BUFFER_CNTL 0x03F0 -#define VGA_BUFFER_CNTL 0x02F4 -#define OV0_Y_X_START 0x0400 -#define OV0_Y_X_END 0x0404 -#define OV0_PIPELINE_CNTL 0x0408 -#define OV0_REG_LOAD_CNTL 0x0410 -#define OV0_SCALE_CNTL 0x0420 -#define OV0_V_INC 0x0424 -#define OV0_P1_V_ACCUM_INIT 0x0428 -#define OV0_P23_V_ACCUM_INIT 0x042C -#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 -#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 -#define OV0_BASE_ADDR 0x043C -#define OV0_VID_BUF0_BASE_ADRS 0x0440 -#define OV0_VID_BUF1_BASE_ADRS 0x0444 -#define OV0_VID_BUF2_BASE_ADRS 0x0448 -#define OV0_VID_BUF3_BASE_ADRS 0x044C -#define OV0_VID_BUF4_BASE_ADRS 0x0450 -#define OV0_VID_BUF5_BASE_ADRS 0x0454 -#define OV0_VID_BUF_PITCH0_VALUE 0x0460 -#define OV0_VID_BUF_PITCH1_VALUE 0x0464 -#define OV0_AUTO_FLIP_CNTRL 0x0470 -#define OV0_DEINTERLACE_PATTERN 0x0474 -#define OV0_SUBMIT_HISTORY 0x0478 -#define OV0_H_INC 0x0480 -#define OV0_STEP_BY 0x0484 -#define OV0_P1_H_ACCUM_INIT 0x0488 -#define OV0_P23_H_ACCUM_INIT 0x048C -#define OV0_P1_X_START_END 0x0494 -#define OV0_P2_X_START_END 0x0498 -#define OV0_P3_X_START_END 0x049C -#define OV0_FILTER_CNTL 0x04A0 -#define OV0_FOUR_TAP_COEF_0 0x04B0 -#define OV0_FOUR_TAP_COEF_1 0x04B4 -#define OV0_FOUR_TAP_COEF_2 0x04B8 -#define OV0_FOUR_TAP_COEF_3 0x04BC -#define OV0_FOUR_TAP_COEF_4 0x04C0 -#define OV0_FLAG_CNTRL 0x04DC -#define OV0_SLICE_CNTL 0x04E0 -#define OV0_VID_KEY_CLR_LOW 0x04E4 -#define OV0_VID_KEY_CLR_HIGH 0x04E8 -#define OV0_GRPH_KEY_CLR_LOW 0x04EC -#define OV0_GRPH_KEY_CLR_HIGH 0x04F0 -#define OV0_KEY_CNTL 0x04F4 -#define OV0_TEST 0x04F8 -#define SUBPIC_CNTL 0x0540 -#define SUBPIC_DEFCOLCON 0x0544 -#define SUBPIC_Y_X_START 0x054C -#define SUBPIC_Y_X_END 0x0550 -#define SUBPIC_V_INC 0x0554 -#define SUBPIC_H_INC 0x0558 -#define SUBPIC_BUF0_OFFSET 0x055C -#define SUBPIC_BUF1_OFFSET 0x0560 -#define SUBPIC_LC0_OFFSET 0x0564 -#define SUBPIC_LC1_OFFSET 0x0568 -#define SUBPIC_PITCH 0x056C -#define SUBPIC_BTN_HLI_COLCON 0x0570 -#define SUBPIC_BTN_HLI_Y_X_START 0x0574 -#define SUBPIC_BTN_HLI_Y_X_END 0x0578 -#define SUBPIC_PALETTE_INDEX 0x057C -#define SUBPIC_PALETTE_DATA 0x0580 -#define SUBPIC_H_ACCUM_INIT 0x0584 -#define SUBPIC_V_ACCUM_INIT 0x0588 -#define DISP_MISC_CNTL 0x0D00 -#define DAC_MACRO_CNTL 0x0D04 -#define DISP_PWR_MAN 0x0D08 -#define DISP_TEST_DEBUG_CNTL 0x0D10 -#define DISP_HW_DEBUG 0x0D14 -#define DAC_CRC_SIG1 0x0D18 -#define DAC_CRC_SIG2 0x0D1C -#define OV0_LIN_TRANS_A 0x0D20 -#define OV0_LIN_TRANS_B 0x0D24 -#define OV0_LIN_TRANS_C 0x0D28 -#define OV0_LIN_TRANS_D 0x0D2C -#define OV0_LIN_TRANS_E 0x0D30 -#define OV0_LIN_TRANS_F 0x0D34 -#define OV0_GAMMA_0_F 0x0D40 -#define OV0_GAMMA_10_1F 0x0D44 -#define OV0_GAMMA_20_3F 0x0D48 -#define OV0_GAMMA_40_7F 0x0D4C -#define OV0_GAMMA_380_3BF 0x0D50 -#define OV0_GAMMA_3C0_3FF 0x0D54 -#define DISP_MERGE_CNTL 0x0D60 -#define DISP_OUTPUT_CNTL 0x0D64 -#define DISP_LIN_TRANS_GRPH_A 0x0D80 -#define DISP_LIN_TRANS_GRPH_B 0x0D84 -#define DISP_LIN_TRANS_GRPH_C 0x0D88 -#define DISP_LIN_TRANS_GRPH_D 0x0D8C -#define DISP_LIN_TRANS_GRPH_E 0x0D90 -#define DISP_LIN_TRANS_GRPH_F 0x0D94 -#define DISP_LIN_TRANS_VID_A 0x0D98 -#define DISP_LIN_TRANS_VID_B 0x0D9C -#define DISP_LIN_TRANS_VID_C 0x0DA0 -#define DISP_LIN_TRANS_VID_D 0x0DA4 -#define DISP_LIN_TRANS_VID_E 0x0DA8 -#define DISP_LIN_TRANS_VID_F 0x0DAC -#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 -#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 -#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 -#define RMX_HORZ_PHASE 0x0DBC -#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 -#define DAC_BROAD_PULSE 0x0DC4 -#define DAC_SKEW_CLKS 0x0DC8 -#define DAC_INCR 0x0DCC -#define DAC_NEG_SYNC_LEVEL 0x0DD0 -#define DAC_POS_SYNC_LEVEL 0x0DD4 -#define DAC_BLANK_LEVEL 0x0DD8 -#define CLOCK_CNTL_INDEX 0x0008 -#define CLOCK_CNTL_DATA 0x000C -#define CP_RB_CNTL 0x0704 -#define CP_RB_BASE 0x0700 -#define CP_RB_RPTR_ADDR 0x070C -#define CP_RB_RPTR 0x0710 -#define CP_RB_WPTR 0x0714 -#define CP_RB_WPTR_DELAY 0x0718 -#define CP_IB_BASE 0x0738 -#define CP_IB_BUFSZ 0x073C -#define SCRATCH_REG0 0x15E0 -#define GUI_SCRATCH_REG0 0x15E0 -#define SCRATCH_REG1 0x15E4 -#define GUI_SCRATCH_REG1 0x15E4 -#define SCRATCH_REG2 0x15E8 -#define GUI_SCRATCH_REG2 0x15E8 -#define SCRATCH_REG3 0x15EC -#define GUI_SCRATCH_REG3 0x15EC -#define SCRATCH_REG4 0x15F0 -#define GUI_SCRATCH_REG4 0x15F0 -#define SCRATCH_REG5 0x15F4 -#define GUI_SCRATCH_REG5 0x15F4 -#define SCRATCH_UMSK 0x0770 -#define SCRATCH_ADDR 0x0774 -#define DP_BRUSH_FRGD_CLR 0x147C -#define DP_BRUSH_BKGD_CLR 0x1478 -#define DST_LINE_START 0x1600 -#define DST_LINE_END 0x1604 -#define SRC_OFFSET 0x15AC -#define SRC_PITCH 0x15B0 -#define SRC_TILE 0x1704 -#define SRC_PITCH_OFFSET 0x1428 -#define SRC_X 0x1414 -#define SRC_Y 0x1418 -#define SRC_X_Y 0x1590 -#define SRC_Y_X 0x1434 +#define MM_INDEX 0x0000 +#define MM_DATA 0x0004 +#define BUS_CNTL 0x0030 +#define HI_STAT 0x004C +#define BUS_CNTL1 0x0034 +#define I2C_CNTL_1 0x0094 +#define CONFIG_CNTL 0x00E0 +#define CONFIG_MEMSIZE 0x00F8 +#define CONFIG_APER_0_BASE 0x0100 +#define CONFIG_APER_1_BASE 0x0104 +#define CONFIG_APER_SIZE 0x0108 +#define CONFIG_REG_1_BASE 0x010C +#define CONFIG_REG_APER_SIZE 0x0110 +#define PAD_AGPINPUT_DELAY 0x0164 +#define PAD_CTLR_STRENGTH 0x0168 +#define PAD_CTLR_UPDATE 0x016C +#define PAD_CTLR_MISC 0x0aa0 +#define AGP_CNTL 0x0174 +#define BM_STATUS 0x0160 +#define CAP0_TRIG_CNTL 0x0950 +#define CAP1_TRIG_CNTL 0x09c0 +#define VIPH_CONTROL 0x0C40 +#define VENDOR_ID 0x0F00 +#define DEVICE_ID 0x0F02 +#define COMMAND 0x0F04 +#define STATUS 0x0F06 +#define REVISION_ID 0x0F08 +#define REGPROG_INF 0x0F09 +#define SUB_CLASS 0x0F0A +#define BASE_CODE 0x0F0B +#define CACHE_LINE 0x0F0C +#define LATENCY 0x0F0D +#define HEADER 0x0F0E +#define BIST 0x0F0F +#define REG_MEM_BASE 0x0F10 +#define REG_IO_BASE 0x0F14 +#define REG_REG_BASE 0x0F18 +#define ADAPTER_ID 0x0F2C +#define BIOS_ROM 0x0F30 +#define CAPABILITIES_PTR 0x0F34 +#define INTERRUPT_LINE 0x0F3C +#define INTERRUPT_PIN 0x0F3D +#define MIN_GRANT 0x0F3E +#define MAX_LATENCY 0x0F3F +#define ADAPTER_ID_W 0x0F4C +#define PMI_CAP_ID 0x0F50 +#define PMI_NXT_CAP_PTR 0x0F51 +#define PMI_PMC_REG 0x0F52 +#define PM_STATUS 0x0F54 +#define PMI_DATA 0x0F57 +#define AGP_CAP_ID 0x0F58 +#define AGP_STATUS 0x0F5C +#define AGP_COMMAND 0x0F60 +#define AIC_CTRL 0x01D0 +#define AIC_STAT 0x01D4 +#define AIC_PT_BASE 0x01D8 +#define AIC_LO_ADDR 0x01DC +#define AIC_HI_ADDR 0x01E0 +#define AIC_TLB_ADDR 0x01E4 +#define AIC_TLB_DATA 0x01E8 +#define DAC_CNTL 0x0058 +#define DAC_CNTL2 0x007c +#define CRTC_GEN_CNTL 0x0050 +#define MEM_CNTL 0x0140 +#define MC_CNTL 0x0140 +#define EXT_MEM_CNTL 0x0144 +#define MC_TIMING_CNTL 0x0144 +#define MC_AGP_LOCATION 0x014C +#define MEM_IO_CNTL_A0 0x0178 +#define MEM_REFRESH_CNTL 0x0178 +#define MEM_INIT_LATENCY_TIMER 0x0154 +#define MC_INIT_GFX_LAT_TIMER 0x0154 +#define MEM_SDRAM_MODE_REG 0x0158 +#define AGP_BASE 0x0170 +#define MEM_IO_CNTL_A1 0x017C +#define MC_READ_CNTL_AB 0x017C +#define MEM_IO_CNTL_B0 0x0180 +#define MC_INIT_MISC_LAT_TIMER 0x0180 +#define MEM_IO_CNTL_B1 0x0184 +#define MC_IOPAD_CNTL 0x0184 +#define MC_DEBUG 0x0188 +#define MC_STATUS 0x0150 +#define MEM_IO_OE_CNTL 0x018C +#define MC_CHIP_IO_OE_CNTL_AB 0x018C +#define MC_FB_LOCATION 0x0148 +/* #define MC_FB_LOCATION 0x0188 */ +#define HOST_PATH_CNTL 0x0130 +#define MEM_VGA_WP_SEL 0x0038 +#define MEM_VGA_RP_SEL 0x003C +#define HDP_DEBUG 0x0138 +#define SW_SEMAPHORE 0x013C +#define CRTC2_GEN_CNTL 0x03f8 +#define CRTC2_DISPLAY_BASE_ADDR 0x033c +#define SURFACE_CNTL 0x0B00 +#define SURFACE0_LOWER_BOUND 0x0B04 +#define SURFACE1_LOWER_BOUND 0x0B14 +#define SURFACE2_LOWER_BOUND 0x0B24 +#define SURFACE3_LOWER_BOUND 0x0B34 +#define SURFACE4_LOWER_BOUND 0x0B44 +#define SURFACE5_LOWER_BOUND 0x0B54 +#define SURFACE6_LOWER_BOUND 0x0B64 +#define SURFACE7_LOWER_BOUND 0x0B74 +#define SURFACE0_UPPER_BOUND 0x0B08 +#define SURFACE1_UPPER_BOUND 0x0B18 +#define SURFACE2_UPPER_BOUND 0x0B28 +#define SURFACE3_UPPER_BOUND 0x0B38 +#define SURFACE4_UPPER_BOUND 0x0B48 +#define SURFACE5_UPPER_BOUND 0x0B58 +#define SURFACE6_UPPER_BOUND 0x0B68 +#define SURFACE7_UPPER_BOUND 0x0B78 +#define SURFACE0_INFO 0x0B0C +#define SURFACE1_INFO 0x0B1C +#define SURFACE2_INFO 0x0B2C +#define SURFACE3_INFO 0x0B3C +#define SURFACE4_INFO 0x0B4C +#define SURFACE5_INFO 0x0B5C +#define SURFACE6_INFO 0x0B6C +#define SURFACE7_INFO 0x0B7C +#define SURFACE_ACCESS_FLAGS 0x0BF8 +#define SURFACE_ACCESS_CLR 0x0BFC +#define GEN_INT_CNTL 0x0040 +#define GEN_INT_STATUS 0x0044 +#define CRTC_EXT_CNTL 0x0054 +#define RB3D_CNTL 0x1C3C +#define WAIT_UNTIL 0x1720 +#define ISYNC_CNTL 0x1724 +#define RBBM_GUICNTL 0x172C +#define RBBM_STATUS 0x0E40 +#define RBBM_STATUS_alt_1 0x1740 +#define RBBM_CNTL 0x00EC +#define RBBM_CNTL_alt_1 0x0E44 +#define RBBM_SOFT_RESET 0x00F0 +#define RBBM_SOFT_RESET_alt_1 0x0E48 +#define NQWAIT_UNTIL 0x0E50 +#define RBBM_DEBUG 0x0E6C +#define RBBM_CMDFIFO_ADDR 0x0E70 +#define RBBM_CMDFIFO_DATAL 0x0E74 +#define RBBM_CMDFIFO_DATAH 0x0E78 +#define RBBM_CMDFIFO_STAT 0x0E7C +#define CRTC_STATUS 0x005C +#define GPIO_VGA_DDC 0x0060 +#define GPIO_DVI_DDC 0x0064 +#define GPIO_MONID 0x0068 +#define GPIO_CRT2_DDC 0x006c +#define PALETTE_INDEX 0x00B0 +#define PALETTE_DATA 0x00B4 +#define PALETTE_30_DATA 0x00B8 +#define CRTC_H_TOTAL_DISP 0x0200 +#define CRTC_H_SYNC_STRT_WID 0x0204 +#define CRTC_V_TOTAL_DISP 0x0208 +#define CRTC_V_SYNC_STRT_WID 0x020C +#define CRTC_VLINE_CRNT_VLINE 0x0210 +#define CRTC_CRNT_FRAME 0x0214 +#define CRTC_GUI_TRIG_VLINE 0x0218 +#define CRTC_DEBUG 0x021C +#define CRTC_OFFSET_RIGHT 0x0220 +#define CRTC_OFFSET 0x0224 +#define CRTC_OFFSET_CNTL 0x0228 +#define CRTC_PITCH 0x022C +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 +#define DISPLAY_BASE_ADDR 0x023C +#define SNAPSHOT_VH_COUNTS 0x0240 +#define SNAPSHOT_F_COUNT 0x0244 +#define N_VIF_COUNT 0x0248 +#define SNAPSHOT_VIF_COUNT 0x024C +#define FP_CRTC_H_TOTAL_DISP 0x0250 +#define FP_CRTC_V_TOTAL_DISP 0x0254 +#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 +#define CRT_CRTC_V_SYNC_STRT_WID 0x025C +#define CUR_OFFSET 0x0260 +#define CUR_HORZ_VERT_POSN 0x0264 +#define CUR_HORZ_VERT_OFF 0x0268 +#define CUR_CLR0 0x026C +#define CUR_CLR1 0x0270 +#define FP_HORZ_VERT_ACTIVE 0x0278 +#define CRTC_MORE_CNTL 0x027C +#define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) +#define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) +#define DAC_EXT_CNTL 0x0280 +#define FP_GEN_CNTL 0x0284 +#define FP_HORZ_STRETCH 0x028C +#define FP_VERT_STRETCH 0x0290 +#define FP_H_SYNC_STRT_WID 0x02C4 +#define FP_V_SYNC_STRT_WID 0x02C8 +#define AUX_WINDOW_HORZ_CNTL 0x02D8 +#define AUX_WINDOW_VERT_CNTL 0x02DC +/* #define DDA_CONFIG 0x02e0 */ +/* #define DDA_ON_OFF 0x02e4 */ +#define DVI_I2C_CNTL_1 0x02e4 +#define GRPH_BUFFER_CNTL 0x02F0 +#define GRPH2_BUFFER_CNTL 0x03F0 +#define VGA_BUFFER_CNTL 0x02F4 +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 +#define OV0_PIPELINE_CNTL 0x0408 +#define OV0_REG_LOAD_CNTL 0x0410 +#define OV0_SCALE_CNTL 0x0420 +#define OV0_V_INC 0x0424 +#define OV0_P1_V_ACCUM_INIT 0x0428 +#define OV0_P23_V_ACCUM_INIT 0x042C +#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +#define OV0_BASE_ADDR 0x043C +#define OV0_VID_BUF0_BASE_ADRS 0x0440 +#define OV0_VID_BUF1_BASE_ADRS 0x0444 +#define OV0_VID_BUF2_BASE_ADRS 0x0448 +#define OV0_VID_BUF3_BASE_ADRS 0x044C +#define OV0_VID_BUF4_BASE_ADRS 0x0450 +#define OV0_VID_BUF5_BASE_ADRS 0x0454 +#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define OV0_AUTO_FLIP_CNTRL 0x0470 +#define OV0_DEINTERLACE_PATTERN 0x0474 +#define OV0_SUBMIT_HISTORY 0x0478 +#define OV0_H_INC 0x0480 +#define OV0_STEP_BY 0x0484 +#define OV0_P1_H_ACCUM_INIT 0x0488 +#define OV0_P23_H_ACCUM_INIT 0x048C +#define OV0_P1_X_START_END 0x0494 +#define OV0_P2_X_START_END 0x0498 +#define OV0_P3_X_START_END 0x049C +#define OV0_FILTER_CNTL 0x04A0 +#define OV0_FOUR_TAP_COEF_0 0x04B0 +#define OV0_FOUR_TAP_COEF_1 0x04B4 +#define OV0_FOUR_TAP_COEF_2 0x04B8 +#define OV0_FOUR_TAP_COEF_3 0x04BC +#define OV0_FOUR_TAP_COEF_4 0x04C0 +#define OV0_FLAG_CNTRL 0x04DC +#define OV0_SLICE_CNTL 0x04E0 +#define OV0_VID_KEY_CLR_LOW 0x04E4 +#define OV0_VID_KEY_CLR_HIGH 0x04E8 +#define OV0_GRPH_KEY_CLR_LOW 0x04EC +#define OV0_GRPH_KEY_CLR_HIGH 0x04F0 +#define OV0_KEY_CNTL 0x04F4 +#define OV0_TEST 0x04F8 +#define SUBPIC_CNTL 0x0540 +#define SUBPIC_DEFCOLCON 0x0544 +#define SUBPIC_Y_X_START 0x054C +#define SUBPIC_Y_X_END 0x0550 +#define SUBPIC_V_INC 0x0554 +#define SUBPIC_H_INC 0x0558 +#define SUBPIC_BUF0_OFFSET 0x055C +#define SUBPIC_BUF1_OFFSET 0x0560 +#define SUBPIC_LC0_OFFSET 0x0564 +#define SUBPIC_LC1_OFFSET 0x0568 +#define SUBPIC_PITCH 0x056C +#define SUBPIC_BTN_HLI_COLCON 0x0570 +#define SUBPIC_BTN_HLI_Y_X_START 0x0574 +#define SUBPIC_BTN_HLI_Y_X_END 0x0578 +#define SUBPIC_PALETTE_INDEX 0x057C +#define SUBPIC_PALETTE_DATA 0x0580 +#define SUBPIC_H_ACCUM_INIT 0x0584 +#define SUBPIC_V_ACCUM_INIT 0x0588 +#define DISP_MISC_CNTL 0x0D00 +#define DAC_MACRO_CNTL 0x0D04 +#define DISP_PWR_MAN 0x0D08 +#define DISP_TEST_DEBUG_CNTL 0x0D10 +#define DISP_HW_DEBUG 0x0D14 +#define DAC_CRC_SIG1 0x0D18 +#define DAC_CRC_SIG2 0x0D1C +#define OV0_LIN_TRANS_A 0x0D20 +#define OV0_LIN_TRANS_B 0x0D24 +#define OV0_LIN_TRANS_C 0x0D28 +#define OV0_LIN_TRANS_D 0x0D2C +#define OV0_LIN_TRANS_E 0x0D30 +#define OV0_LIN_TRANS_F 0x0D34 +#define OV0_GAMMA_0_F 0x0D40 +#define OV0_GAMMA_10_1F 0x0D44 +#define OV0_GAMMA_20_3F 0x0D48 +#define OV0_GAMMA_40_7F 0x0D4C +#define OV0_GAMMA_380_3BF 0x0D50 +#define OV0_GAMMA_3C0_3FF 0x0D54 +#define DISP_MERGE_CNTL 0x0D60 +#define DISP_OUTPUT_CNTL 0x0D64 +#define DISP_LIN_TRANS_GRPH_A 0x0D80 +#define DISP_LIN_TRANS_GRPH_B 0x0D84 +#define DISP_LIN_TRANS_GRPH_C 0x0D88 +#define DISP_LIN_TRANS_GRPH_D 0x0D8C +#define DISP_LIN_TRANS_GRPH_E 0x0D90 +#define DISP_LIN_TRANS_GRPH_F 0x0D94 +#define DISP_LIN_TRANS_VID_A 0x0D98 +#define DISP_LIN_TRANS_VID_B 0x0D9C +#define DISP_LIN_TRANS_VID_C 0x0DA0 +#define DISP_LIN_TRANS_VID_D 0x0DA4 +#define DISP_LIN_TRANS_VID_E 0x0DA8 +#define DISP_LIN_TRANS_VID_F 0x0DAC +#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 +#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 +#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 +#define RMX_HORZ_PHASE 0x0DBC +#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 +#define DAC_BROAD_PULSE 0x0DC4 +#define DAC_SKEW_CLKS 0x0DC8 +#define DAC_INCR 0x0DCC +#define DAC_NEG_SYNC_LEVEL 0x0DD0 +#define DAC_POS_SYNC_LEVEL 0x0DD4 +#define DAC_BLANK_LEVEL 0x0DD8 +#define CLOCK_CNTL_INDEX 0x0008 +#define CLOCK_CNTL_DATA 0x000C +#define CP_RB_CNTL 0x0704 +#define CP_RB_BASE 0x0700 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define SCRATCH_REG0 0x15E0 +#define GUI_SCRATCH_REG0 0x15E0 +#define SCRATCH_REG1 0x15E4 +#define GUI_SCRATCH_REG1 0x15E4 +#define SCRATCH_REG2 0x15E8 +#define GUI_SCRATCH_REG2 0x15E8 +#define SCRATCH_REG3 0x15EC +#define GUI_SCRATCH_REG3 0x15EC +#define SCRATCH_REG4 0x15F0 +#define GUI_SCRATCH_REG4 0x15F0 +#define SCRATCH_REG5 0x15F4 +#define GUI_SCRATCH_REG5 0x15F4 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DP_BRUSH_FRGD_CLR 0x147C +#define DP_BRUSH_BKGD_CLR 0x1478 +#define DST_LINE_START 0x1600 +#define DST_LINE_END 0x1604 +#define SRC_OFFSET 0x15AC +#define SRC_PITCH 0x15B0 +#define SRC_TILE 0x1704 +#define SRC_PITCH_OFFSET 0x1428 +#define SRC_X 0x1414 +#define SRC_Y 0x1418 +#define SRC_X_Y 0x1590 +#define SRC_Y_X 0x1434 #define DST_Y_X 0x1438 -#define DST_WIDTH_HEIGHT 0x1598 -#define DST_HEIGHT_WIDTH 0x143c -#define DST_OFFSET 0x1404 -#define SRC_CLUT_ADDRESS 0x1780 -#define SRC_CLUT_DATA 0x1784 -#define SRC_CLUT_DATA_RD 0x1788 -#define HOST_DATA0 0x17C0 -#define HOST_DATA1 0x17C4 -#define HOST_DATA2 0x17C8 -#define HOST_DATA3 0x17CC -#define HOST_DATA4 0x17D0 -#define HOST_DATA5 0x17D4 -#define HOST_DATA6 0x17D8 -#define HOST_DATA7 0x17DC -#define HOST_DATA_LAST 0x17E0 -#define DP_SRC_ENDIAN 0x15D4 -#define DP_SRC_FRGD_CLR 0x15D8 -#define DP_SRC_BKGD_CLR 0x15DC -#define SC_LEFT 0x1640 -#define SC_RIGHT 0x1644 -#define SC_TOP 0x1648 -#define SC_BOTTOM 0x164C -#define SRC_SC_RIGHT 0x1654 -#define SRC_SC_BOTTOM 0x165C -#define DP_CNTL 0x16C0 -#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 -#define DP_DATATYPE 0x16C4 -#define DP_MIX 0x16C8 -#define DP_WRITE_MSK 0x16CC -#define DP_XOP 0x17F8 -#define CLR_CMP_CLR_SRC 0x15C4 -#define CLR_CMP_CLR_DST 0x15C8 -#define CLR_CMP_CNTL 0x15C0 -#define CLR_CMP_MSK 0x15CC -#define DSTCACHE_MODE 0x1710 -#define DSTCACHE_CTLSTAT 0x1714 -#define DEFAULT_PITCH_OFFSET 0x16E0 -#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 -#define DEFAULT_SC_TOP_LEFT 0x16EC -#define SRC_PITCH_OFFSET 0x1428 -#define DST_PITCH_OFFSET 0x142C -#define DP_GUI_MASTER_CNTL 0x146C -#define SC_TOP_LEFT 0x16EC -#define SC_BOTTOM_RIGHT 0x16F0 -#define SRC_SC_BOTTOM_RIGHT 0x16F4 -#define RB2D_DSTCACHE_MODE 0x3428 -#define RB2D_DSTCACHE_CTLSTAT 0x342C -#define LVDS_GEN_CNTL 0x02d0 -#define LVDS_PLL_CNTL 0x02d4 -#define FP2_GEN_CNTL 0x0288 -#define TMDS_CNTL 0x0294 -#define TMDS_CRC 0x02a0 -#define TMDS_TRANSMITTER_CNTL 0x02a4 -#define MPP_TB_CONFIG 0x01c0 -#define PAMAC0_DLY_CNTL 0x0a94 -#define PAMAC1_DLY_CNTL 0x0a98 -#define PAMAC2_DLY_CNTL 0x0a9c -#define FW_CNTL 0x0118 -#define FCP_CNTL 0x0910 -#define VGA_DDA_ON_OFF 0x02ec -#define TV_MASTER_CNTL 0x0800 - -//#define BASE_CODE 0x0f0b -#define BIOS_0_SCRATCH 0x0010 -#define BIOS_1_SCRATCH 0x0014 -#define BIOS_2_SCRATCH 0x0018 -#define BIOS_3_SCRATCH 0x001c -#define BIOS_4_SCRATCH 0x0020 -#define BIOS_5_SCRATCH 0x0024 -#define BIOS_6_SCRATCH 0x0028 -#define BIOS_7_SCRATCH 0x002c - -#define HDP_SOFT_RESET (1 << 26) - -#define TV_DAC_CNTL 0x088c -#define GPIOPAD_MASK 0x0198 -#define GPIOPAD_A 0x019c -#define GPIOPAD_EN 0x01a0 -#define GPIOPAD_Y 0x01a4 -#define ZV_LCDPAD_MASK 0x01a8 -#define ZV_LCDPAD_A 0x01ac -#define ZV_LCDPAD_EN 0x01b0 -#define ZV_LCDPAD_Y 0x01b4 +#define DST_WIDTH_HEIGHT 0x1598 +#define DST_HEIGHT_WIDTH 0x143c +#define DST_OFFSET 0x1404 +#define SRC_CLUT_ADDRESS 0x1780 +#define SRC_CLUT_DATA 0x1784 +#define SRC_CLUT_DATA_RD 0x1788 +#define HOST_DATA0 0x17C0 +#define HOST_DATA1 0x17C4 +#define HOST_DATA2 0x17C8 +#define HOST_DATA3 0x17CC +#define HOST_DATA4 0x17D0 +#define HOST_DATA5 0x17D4 +#define HOST_DATA6 0x17D8 +#define HOST_DATA7 0x17DC +#define HOST_DATA_LAST 0x17E0 +#define DP_SRC_ENDIAN 0x15D4 +#define DP_SRC_FRGD_CLR 0x15D8 +#define DP_SRC_BKGD_CLR 0x15DC +#define SC_LEFT 0x1640 +#define SC_RIGHT 0x1644 +#define SC_TOP 0x1648 +#define SC_BOTTOM 0x164C +#define SRC_SC_RIGHT 0x1654 +#define SRC_SC_BOTTOM 0x165C +#define DP_CNTL 0x16C0 +#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 +#define DP_DATATYPE 0x16C4 +#define DP_MIX 0x16C8 +#define DP_WRITE_MSK 0x16CC +#define DP_XOP 0x17F8 +#define CLR_CMP_CLR_SRC 0x15C4 +#define CLR_CMP_CLR_DST 0x15C8 +#define CLR_CMP_CNTL 0x15C0 +#define CLR_CMP_MSK 0x15CC +#define DSTCACHE_MODE 0x1710 +#define DSTCACHE_CTLSTAT 0x1714 +#define DEFAULT_PITCH_OFFSET 0x16E0 +#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 +#define DEFAULT_SC_TOP_LEFT 0x16EC +#define SRC_PITCH_OFFSET 0x1428 +#define DST_PITCH_OFFSET 0x142C +#define DP_GUI_MASTER_CNTL 0x146C +#define SC_TOP_LEFT 0x16EC +#define SC_BOTTOM_RIGHT 0x16F0 +#define SRC_SC_BOTTOM_RIGHT 0x16F4 +#define RB2D_DSTCACHE_MODE 0x3428 +#define RB2D_DSTCACHE_CTLSTAT 0x342C +#define LVDS_GEN_CNTL 0x02d0 +#define LVDS_PLL_CNTL 0x02d4 +#define FP2_GEN_CNTL 0x0288 +#define TMDS_CNTL 0x0294 +#define TMDS_CRC 0x02a0 +#define TMDS_TRANSMITTER_CNTL 0x02a4 +#define MPP_TB_CONFIG 0x01c0 +#define PAMAC0_DLY_CNTL 0x0a94 +#define PAMAC1_DLY_CNTL 0x0a98 +#define PAMAC2_DLY_CNTL 0x0a9c +#define FW_CNTL 0x0118 +#define FCP_CNTL 0x0910 +#define VGA_DDA_ON_OFF 0x02ec +#define TV_MASTER_CNTL 0x0800 + +/* #define BASE_CODE 0x0f0b */ +#define BIOS_0_SCRATCH 0x0010 +#define BIOS_1_SCRATCH 0x0014 +#define BIOS_2_SCRATCH 0x0018 +#define BIOS_3_SCRATCH 0x001c +#define BIOS_4_SCRATCH 0x0020 +#define BIOS_5_SCRATCH 0x0024 +#define BIOS_6_SCRATCH 0x0028 +#define BIOS_7_SCRATCH 0x002c + +#define HDP_SOFT_RESET (1 << 26) + +#define TV_DAC_CNTL 0x088c +#define GPIOPAD_MASK 0x0198 +#define GPIOPAD_A 0x019c +#define GPIOPAD_EN 0x01a0 +#define GPIOPAD_Y 0x01a4 +#define ZV_LCDPAD_MASK 0x01a8 +#define ZV_LCDPAD_A 0x01ac +#define ZV_LCDPAD_EN 0x01b0 +#define ZV_LCDPAD_Y 0x01b4 /* PLL Registers */ -#define CLK_PIN_CNTL 0x0001 -#define PPLL_CNTL 0x0002 -#define PPLL_REF_DIV 0x0003 -#define PPLL_DIV_0 0x0004 -#define PPLL_DIV_1 0x0005 -#define PPLL_DIV_2 0x0006 -#define PPLL_DIV_3 0x0007 -#define VCLK_ECP_CNTL 0x0008 -#define HTOTAL_CNTL 0x0009 -#define M_SPLL_REF_FB_DIV 0x000a -#define AGP_PLL_CNTL 0x000b -#define SPLL_CNTL 0x000c -#define SCLK_CNTL 0x000d -#define MPLL_CNTL 0x000e -#define MDLL_CKO 0x000f -#define MDLL_RDCKA 0x0010 -#define MCLK_CNTL 0x0012 -#define AGP_PLL_CNTL 0x000b -#define PLL_TEST_CNTL 0x0013 -#define CLK_PWRMGT_CNTL 0x0014 -#define PLL_PWRMGT_CNTL 0x0015 -#define MCLK_MISC 0x001f -#define P2PLL_CNTL 0x002a -#define P2PLL_REF_DIV 0x002b -#define PIXCLKS_CNTL 0x002d -#define SCLK_MORE_CNTL 0x0035 +#define CLK_PIN_CNTL 0x0001 +#define PPLL_CNTL 0x0002 +#define PPLL_REF_DIV 0x0003 +#define PPLL_DIV_0 0x0004 +#define PPLL_DIV_1 0x0005 +#define PPLL_DIV_2 0x0006 +#define PPLL_DIV_3 0x0007 +#define VCLK_ECP_CNTL 0x0008 +#define HTOTAL_CNTL 0x0009 +#define M_SPLL_REF_FB_DIV 0x000a +#define AGP_PLL_CNTL 0x000b +#define SPLL_CNTL 0x000c +#define SCLK_CNTL 0x000d +#define MPLL_CNTL 0x000e +#define MDLL_CKO 0x000f +#define MDLL_RDCKA 0x0010 +#define MCLK_CNTL 0x0012 +#define AGP_PLL_CNTL 0x000b +#define PLL_TEST_CNTL 0x0013 +#define CLK_PWRMGT_CNTL 0x0014 +#define PLL_PWRMGT_CNTL 0x0015 +#define MCLK_MISC 0x001f +#define P2PLL_CNTL 0x002a +#define P2PLL_REF_DIV 0x002b +#define PIXCLKS_CNTL 0x002d +#define SCLK_MORE_CNTL 0x0035 /* MCLK_CNTL bit constants */ -#define FORCEON_MCLKA (1 << 16) -#define FORCEON_MCLKB (1 << 17) -#define FORCEON_YCLKA (1 << 18) -#define FORCEON_YCLKB (1 << 19) -#define FORCEON_MC (1 << 20) -#define FORCEON_AIC (1 << 21) +#define FORCEON_MCLKA (1 << 16) +#define FORCEON_MCLKB (1 << 17) +#define FORCEON_YCLKA (1 << 18) +#define FORCEON_YCLKB (1 << 19) +#define FORCEON_MC (1 << 20) +#define FORCEON_AIC (1 << 21) /* SCLK_CNTL bit constants */ -#define DYN_STOP_LAT_MASK 0x00007ff8 -#define CP_MAX_DYN_STOP_LAT 0x0008 -#define SCLK_FORCEON_MASK 0xffff8000 +#define DYN_STOP_LAT_MASK 0x00007ff8 +#define CP_MAX_DYN_STOP_LAT 0x0008 +#define SCLK_FORCEON_MASK 0xffff8000 /* SCLK_MORE_CNTL bit constants */ -#define SCLK_MORE_FORCEON 0x0700 +#define SCLK_MORE_FORCEON 0x0700 /* BUS_CNTL bit constants */ -#define BUS_DBL_RESYNC 0x00000001 -#define BUS_MSTR_RESET 0x00000002 -#define BUS_FLUSH_BUF 0x00000004 -#define BUS_STOP_REQ_DIS 0x00000008 -#define BUS_ROTATION_DIS 0x00000010 -#define BUS_MASTER_DIS 0x00000040 -#define BUS_ROM_WRT_EN 0x00000080 -#define BUS_DIS_ROM 0x00001000 -#define BUS_PCI_READ_RETRY_EN 0x00002000 -#define BUS_AGP_AD_STEPPING_EN 0x00004000 -#define BUS_PCI_WRT_RETRY_EN 0x00008000 -#define BUS_MSTR_RD_MULT 0x00100000 -#define BUS_MSTR_RD_LINE 0x00200000 -#define BUS_SUSPEND 0x00400000 -#define LAT_16X 0x00800000 -#define BUS_RD_DISCARD_EN 0x01000000 -#define BUS_RD_ABORT_EN 0x02000000 -#define BUS_MSTR_WS 0x04000000 -#define BUS_PARKING_DIS 0x08000000 -#define BUS_MSTR_DISCONNECT_EN 0x10000000 -#define BUS_WRT_BURST 0x20000000 -#define BUS_READ_BURST 0x40000000 -#define BUS_RDY_READ_DLY 0x80000000 +#define BUS_DBL_RESYNC 0x00000001 +#define BUS_MSTR_RESET 0x00000002 +#define BUS_FLUSH_BUF 0x00000004 +#define BUS_STOP_REQ_DIS 0x00000008 +#define BUS_ROTATION_DIS 0x00000010 +#define BUS_MASTER_DIS 0x00000040 +#define BUS_ROM_WRT_EN 0x00000080 +#define BUS_DIS_ROM 0x00001000 +#define BUS_PCI_READ_RETRY_EN 0x00002000 +#define BUS_AGP_AD_STEPPING_EN 0x00004000 +#define BUS_PCI_WRT_RETRY_EN 0x00008000 +#define BUS_MSTR_RD_MULT 0x00100000 +#define BUS_MSTR_RD_LINE 0x00200000 +#define BUS_SUSPEND 0x00400000 +#define LAT_16X 0x00800000 +#define BUS_RD_DISCARD_EN 0x01000000 +#define BUS_RD_ABORT_EN 0x02000000 +#define BUS_MSTR_WS 0x04000000 +#define BUS_PARKING_DIS 0x08000000 +#define BUS_MSTR_DISCONNECT_EN 0x10000000 +#define BUS_WRT_BURST 0x20000000 +#define BUS_READ_BURST 0x40000000 +#define BUS_RDY_READ_DLY 0x80000000 /* PIXCLKS_CNTL */ -#define PIX2CLK_SRC_SEL_MASK 0x03 -#define PIX2CLK_SRC_SEL_CPUCLK 0x00 -#define PIX2CLK_SRC_SEL_PSCANCLK 0x01 -#define PIX2CLK_SRC_SEL_BYTECLK 0x02 -#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 -#define PIX2CLK_ALWAYS_ONb (1<<6) -#define PIX2CLK_DAC_ALWAYS_ONb (1<<7) -#define PIXCLK_TV_SRC_SEL (1 << 8) -#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) -#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) +#define PIX2CLK_SRC_SEL_MASK 0x03 +#define PIX2CLK_SRC_SEL_CPUCLK 0x00 +#define PIX2CLK_SRC_SEL_PSCANCLK 0x01 +#define PIX2CLK_SRC_SEL_BYTECLK 0x02 +#define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 +#define PIX2CLK_ALWAYS_ONb (1<<6) +#define PIX2CLK_DAC_ALWAYS_ONb (1<<7) +#define PIXCLK_TV_SRC_SEL (1 << 8) +#define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) +#define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) /* CLOCK_CNTL_INDEX bit constants */ -#define PLL_WR_EN 0x00000080 +#define PLL_WR_EN 0x00000080 /* CONFIG_CNTL bit constants */ -#define CFG_VGA_RAM_EN 0x00000100 -#define CFG_ATI_REV_ID_MASK (0xf << 16) -#define CFG_ATI_REV_A11 (0 << 16) -#define CFG_ATI_REV_A12 (1 << 16) -#define CFG_ATI_REV_A13 (2 << 16) +#define CFG_VGA_RAM_EN 0x00000100 +#define CFG_ATI_REV_ID_MASK (0xf << 16) +#define CFG_ATI_REV_A11 (0 << 16) +#define CFG_ATI_REV_A12 (1 << 16) +#define CFG_ATI_REV_A13 (2 << 16) /* CRTC_EXT_CNTL bit constants */ -#define VGA_ATI_LINEAR 0x00000008 -#define VGA_128KAP_PAGING 0x00000010 -#define XCRT_CNT_EN (1 << 6) -#define CRTC_HSYNC_DIS (1 << 8) -#define CRTC_VSYNC_DIS (1 << 9) -#define CRTC_DISPLAY_DIS (1 << 10) -#define CRTC_CRT_ON (1 << 15) +#define VGA_ATI_LINEAR 0x00000008 +#define VGA_128KAP_PAGING 0x00000010 +#define XCRT_CNT_EN (1 << 6) +#define CRTC_HSYNC_DIS (1 << 8) +#define CRTC_VSYNC_DIS (1 << 9) +#define CRTC_DISPLAY_DIS (1 << 10) +#define CRTC_CRT_ON (1 << 15) /* DSTCACHE_CTLSTAT bit constants */ -#define RB2D_DC_FLUSH (3 << 0) -#define RB2D_DC_FLUSH_ALL 0xf -#define RB2D_DC_BUSY (1 << 31) +#define RB2D_DC_FLUSH (3 << 0) +#define RB2D_DC_FLUSH_ALL 0xf +#define RB2D_DC_BUSY (1 << 31) /* CRTC_GEN_CNTL bit constants */ -#define CRTC_DBL_SCAN_EN 0x00000001 -#define CRTC_CUR_EN 0x00010000 -#define CRTC_INTERLACE_EN (1 << 1) -#define CRTC_BYPASS_LUT_EN (1 << 14) -#define CRTC_EXT_DISP_EN (1 << 24) -#define CRTC_EN (1 << 25) -#define CRTC_DISP_REQ_EN_B (1 << 26) +#define CRTC_DBL_SCAN_EN 0x00000001 +#define CRTC_CUR_EN 0x00010000 +#define CRTC_INTERLACE_EN (1 << 1) +#define CRTC_BYPASS_LUT_EN (1 << 14) +#define CRTC_EXT_DISP_EN (1 << 24) +#define CRTC_EN (1 << 25) +#define CRTC_DISP_REQ_EN_B (1 << 26) /* CRTC_STATUS bit constants */ -#define CRTC_VBLANK 0x00000001 +#define CRTC_VBLANK 0x00000001 /* CRTC2_GEN_CNTL bit constants */ -#define CRT2_ON (1 << 7) -#define CRTC2_DISPLAY_DIS (1 << 23) -#define CRTC2_EN (1 << 25) -#define CRTC2_DISP_REQ_EN_B (1 << 26) +#define CRT2_ON (1 << 7) +#define CRTC2_DISPLAY_DIS (1 << 23) +#define CRTC2_EN (1 << 25) +#define CRTC2_DISP_REQ_EN_B (1 << 26) /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ -#define CUR_LOCK 0x80000000 +#define CUR_LOCK 0x80000000 /* GPIO bit constants */ -#define GPIO_A_0 (1 << 0) -#define GPIO_A_1 (1 << 1) -#define GPIO_Y_0 (1 << 8) -#define GPIO_Y_1 (1 << 9) -#define GPIO_EN_0 (1 << 16) -#define GPIO_EN_1 (1 << 17) -#define GPIO_MASK_0 (1 << 24) -#define GPIO_MASK_1 (1 << 25) -#define VGA_DDC_DATA_OUTPUT GPIO_A_0 -#define VGA_DDC_CLK_OUTPUT GPIO_A_1 -#define VGA_DDC_DATA_INPUT GPIO_Y_0 -#define VGA_DDC_CLK_INPUT GPIO_Y_1 -#define VGA_DDC_DATA_OUT_EN GPIO_EN_0 -#define VGA_DDC_CLK_OUT_EN GPIO_EN_1 +#define GPIO_A_0 (1 << 0) +#define GPIO_A_1 (1 << 1) +#define GPIO_Y_0 (1 << 8) +#define GPIO_Y_1 (1 << 9) +#define GPIO_EN_0 (1 << 16) +#define GPIO_EN_1 (1 << 17) +#define GPIO_MASK_0 (1 << 24) +#define GPIO_MASK_1 (1 << 25) +#define VGA_DDC_DATA_OUTPUT GPIO_A_0 +#define VGA_DDC_CLK_OUTPUT GPIO_A_1 +#define VGA_DDC_DATA_INPUT GPIO_Y_0 +#define VGA_DDC_CLK_INPUT GPIO_Y_1 +#define VGA_DDC_DATA_OUT_EN GPIO_EN_0 +#define VGA_DDC_CLK_OUT_EN GPIO_EN_1 /* FP bit constants */ -#define FP_CRTC_H_TOTAL_MASK 0x000003ff -#define FP_CRTC_H_DISP_MASK 0x01ff0000 -#define FP_CRTC_V_TOTAL_MASK 0x00000fff -#define FP_CRTC_V_DISP_MASK 0x0fff0000 -#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 -#define FP_H_SYNC_WID_MASK 0x003f0000 -#define FP_V_SYNC_STRT_MASK 0x00000fff -#define FP_V_SYNC_WID_MASK 0x001f0000 -#define FP_CRTC_H_TOTAL_SHIFT 0x00000000 -#define FP_CRTC_H_DISP_SHIFT 0x00000010 -#define FP_CRTC_V_TOTAL_SHIFT 0x00000000 -#define FP_CRTC_V_DISP_SHIFT 0x00000010 -#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 -#define FP_H_SYNC_WID_SHIFT 0x00000010 -#define FP_V_SYNC_STRT_SHIFT 0x00000000 -#define FP_V_SYNC_WID_SHIFT 0x00000010 +#define FP_CRTC_H_TOTAL_MASK 000003ff +#define FP_CRTC_H_DISP_MASK 0x01ff0000 +#define FP_CRTC_V_TOTAL_MASK 0x00000fff +#define FP_CRTC_V_DISP_MASK 0x0fff0000 +#define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +#define FP_H_SYNC_WID_MASK 0x003f0000 +#define FP_V_SYNC_STRT_MASK 0x00000fff +#define FP_V_SYNC_WID_MASK 0x001f0000 +#define FP_CRTC_H_TOTAL_SHIFT 0x00000000 +#define FP_CRTC_H_DISP_SHIFT 0x00000010 +#define FP_CRTC_V_TOTAL_SHIFT 0x00000000 +#define FP_CRTC_V_DISP_SHIFT 0x00000010 +#define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +#define FP_H_SYNC_WID_SHIFT 0x00000010 +#define FP_V_SYNC_STRT_SHIFT 0x00000000 +#define FP_V_SYNC_WID_SHIFT 0x00000010 /* FP_GEN_CNTL bit constants */ -#define FP_FPON (1 << 0) -#define FP_TMDS_EN (1 << 2) -#define FP_PANEL_FORMAT (1 << 3) -#define FP_EN_TMDS (1 << 7) -#define FP_DETECT_SENSE (1 << 8) -#define R200_FP_SOURCE_SEL_MASK (3 << 10) -#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) -#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) -#define R200_FP_SOURCE_SEL_RMX (2 << 10) -#define R200_FP_SOURCE_SEL_TRANS (3 << 10) -#define FP_SEL_CRTC1 (0 << 13) -#define FP_SEL_CRTC2 (1 << 13) -#define FP_USE_VGA_HSYNC (1 << 14) -#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) -#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) -#define FP_CRTC_DONT_SHADOW_HEND (1 << 17) -#define FP_CRTC_USE_SHADOW_VEND (1 << 18) -#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) -#define FP_DFP_SYNC_SEL (1 << 21) -#define FP_CRTC_LOCK_8DOT (1 << 22) -#define FP_CRT_SYNC_SEL (1 << 23) -#define FP_USE_SHADOW_EN (1 << 24) -#define FP_CRT_SYNC_ALT (1 << 26) +#define FP_FPON (1 << 0) +#define FP_TMDS_EN (1 << 2) +#define FP_PANEL_FORMAT (1 << 3) +#define FP_EN_TMDS (1 << 7) +#define FP_DETECT_SENSE (1 << 8) +#define R200_FP_SOURCE_SEL_MASK (3 << 10) +#define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) +#define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) +#define R200_FP_SOURCE_SEL_RMX (2 << 10) +#define R200_FP_SOURCE_SEL_TRANS (3 << 10) +#define FP_SEL_CRTC1 (0 << 13) +#define FP_SEL_CRTC2 (1 << 13) +#define FP_USE_VGA_HSYNC (1 << 14) +#define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +#define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +#define FP_CRTC_DONT_SHADOW_HEND (1 << 17) +#define FP_CRTC_USE_SHADOW_VEND (1 << 18) +#define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +#define FP_DFP_SYNC_SEL (1 << 21) +#define FP_CRTC_LOCK_8DOT (1 << 22) +#define FP_CRT_SYNC_SEL (1 << 23) +#define FP_USE_SHADOW_EN (1 << 24) +#define FP_CRT_SYNC_ALT (1 << 26) /* FP2_GEN_CNTL bit constants */ -#define FP2_BLANK_EN (1 << 1) -#define FP2_ON (1 << 2) -#define FP2_PANEL_FORMAT (1 << 3) -#define FP2_SOURCE_SEL_MASK (3 << 10) -#define FP2_SOURCE_SEL_CRTC2 (1 << 10) -#define FP2_SRC_SEL_MASK (3 << 13) -#define FP2_SRC_SEL_CRTC2 (1 << 13) -#define FP2_FP_POL (1 << 16) -#define FP2_LP_POL (1 << 17) -#define FP2_SCK_POL (1 << 18) -#define FP2_LCD_CNTL_MASK (7 << 19) -#define FP2_PAD_FLOP_EN (1 << 22) -#define FP2_CRC_EN (1 << 23) -#define FP2_CRC_READ_EN (1 << 24) -#define FP2_DV0_EN (1 << 25) -#define FP2_DV0_RATE_SEL_SDR (1 << 26) +#define FP2_BLANK_EN (1 << 1) +#define FP2_ON (1 << 2) +#define FP2_PANEL_FORMAT (1 << 3) +#define FP2_SOURCE_SEL_MASK (3 << 10) +#define FP2_SOURCE_SEL_CRTC2 (1 << 10) +#define FP2_SRC_SEL_MASK (3 << 13) +#define FP2_SRC_SEL_CRTC2 (1 << 13) +#define FP2_FP_POL (1 << 16) +#define FP2_LP_POL (1 << 17) +#define FP2_SCK_POL (1 << 18) +#define FP2_LCD_CNTL_MASK (7 << 19) +#define FP2_PAD_FLOP_EN (1 << 22) +#define FP2_CRC_EN (1 << 23) +#define FP2_CRC_READ_EN (1 << 24) +#define FP2_DV0_EN (1 << 25) +#define FP2_DV0_RATE_SEL_SDR (1 << 26) /* LVDS_GEN_CNTL bit constants */ -#define LVDS_ON (1 << 0) -#define LVDS_DISPLAY_DIS (1 << 1) -#define LVDS_PANEL_TYPE (1 << 2) -#define LVDS_PANEL_FORMAT (1 << 3) -#define LVDS_EN (1 << 7) -#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 -#define LVDS_BL_MOD_LEVEL_SHIFT 8 -#define LVDS_BL_MOD_EN (1 << 16) -#define LVDS_DIGON (1 << 18) -#define LVDS_BLON (1 << 19) -#define LVDS_SEL_CRTC2 (1 << 23) -#define LVDS_STATE_MASK \ +#define LVDS_ON (1 << 0) +#define LVDS_DISPLAY_DIS (1 << 1) +#define LVDS_PANEL_TYPE (1 << 2) +#define LVDS_PANEL_FORMAT (1 << 3) +#define LVDS_EN (1 << 7) +#define LVDS_BL_MOD_LEVEL_MASK 0x0000ff00 +#define LVDS_BL_MOD_LEVEL_SHIFT 8 +#define LVDS_BL_MOD_EN (1 << 16) +#define LVDS_DIGON (1 << 18) +#define LVDS_BLON (1 << 19) +#define LVDS_SEL_CRTC2 (1 << 23) +#define LVDS_STATE_MASK \ (LVDS_ON | LVDS_DISPLAY_DIS | LVDS_BL_MOD_LEVEL_MASK | LVDS_BLON) /* LVDS_PLL_CNTL bit constatns */ -#define HSYNC_DELAY_SHIFT 0x1c -#define HSYNC_DELAY_MASK (0xf << 0x1c) +#define HSYNC_DELAY_SHIFT 0x1c +#define HSYNC_DELAY_MASK (0xf << 0x1c) /* TMDS_TRANSMITTER_CNTL bit constants */ -#define TMDS_PLL_EN (1 << 0) -#define TMDS_PLLRST (1 << 1) -#define TMDS_RAN_PAT_RST (1 << 7) -#define TMDS_ICHCSEL (1 << 28) +#define TMDS_PLL_EN (1 << 0) +#define TMDS_PLLRST (1 << 1) +#define TMDS_RAN_PAT_RST (1 << 7) +#define TMDS_ICHCSEL (1 << 28) /* FP_HORZ_STRETCH bit constants */ -#define HORZ_STRETCH_RATIO_MASK 0xffff -#define HORZ_STRETCH_RATIO_MAX 4096 -#define HORZ_PANEL_SIZE (0x1ff << 16) -#define HORZ_PANEL_SHIFT 16 -#define HORZ_STRETCH_PIXREP (0 << 25) -#define HORZ_STRETCH_BLEND (1 << 26) -#define HORZ_STRETCH_ENABLE (1 << 25) -#define HORZ_AUTO_RATIO (1 << 27) -#define HORZ_FP_LOOP_STRETCH (0x7 << 28) -#define HORZ_AUTO_RATIO_INC (1 << 31) +#define HORZ_STRETCH_RATIO_MASK 0xffff +#define HORZ_STRETCH_RATIO_MAX 4096 +#define HORZ_PANEL_SIZE (0x1ff << 16) +#define HORZ_PANEL_SHIFT 16 +#define HORZ_STRETCH_PIXREP (0 << 25) +#define HORZ_STRETCH_BLEND (1 << 26) +#define HORZ_STRETCH_ENABLE (1 << 25) +#define HORZ_AUTO_RATIO (1 << 27) +#define HORZ_FP_LOOP_STRETCH (0x7 << 28) +#define HORZ_AUTO_RATIO_INC (1 << 31) /* FP_VERT_STRETCH bit constants */ -#define VERT_STRETCH_RATIO_MASK 0xfff -#define VERT_STRETCH_RATIO_MAX 4096 -#define VERT_PANEL_SIZE (0xfff << 12) -#define VERT_PANEL_SHIFT 12 -#define VERT_STRETCH_LINREP (0 << 26) -#define VERT_STRETCH_BLEND (1 << 26) -#define VERT_STRETCH_ENABLE (1 << 25) -#define VERT_AUTO_RATIO_EN (1 << 27) -#define VERT_FP_LOOP_STRETCH (0x7 << 28) -#define VERT_STRETCH_RESERVED 0xf1000000 +#define VERT_STRETCH_RATIO_MASK 0xfff +#define VERT_STRETCH_RATIO_MAX 4096 +#define VERT_PANEL_SIZE (0xfff << 12) +#define VERT_PANEL_SHIFT 12 +#define VERT_STRETCH_LINREP (0 << 26) +#define VERT_STRETCH_BLEND (1 << 26) +#define VERT_STRETCH_ENABLE (1 << 25) +#define VERT_AUTO_RATIO_EN (1 << 27) +#define VERT_FP_LOOP_STRETCH (0x7 << 28) +#define VERT_STRETCH_RESERVED 0xf1000000 /* DAC_CNTL bit constants */ -#define DAC_8BIT_EN 0x00000100 -#define DAC_4BPP_PIX_ORDER 0x00000200 -#define DAC_CRC_EN 0x00080000 -#define DAC_MASK_ALL (0xff << 24) -#define DAC_PDWN (1 << 15) -#define DAC_EXPAND_MODE (1 << 14) -#define DAC_VGA_ADR_EN (1 << 13) -#define DAC_RANGE_CNTL (3 << 0) -#define DAC_RANGE_CNTL_MASK 0x03 -#define DAC_BLANKING (1 << 2) -#define DAC_CMP_EN (1 << 3) -#define DAC_CMP_OUTPUT (1 << 7) +#define DAC_8BIT_EN 0x00000100 +#define DAC_4BPP_PIX_ORDER 0x00000200 +#define DAC_CRC_EN 0x00080000 +#define DAC_MASK_ALL (0xff << 24) +#define DAC_PDWN (1 << 15) +#define DAC_EXPAND_MODE (1 << 14) +#define DAC_VGA_ADR_EN (1 << 13) +#define DAC_RANGE_CNTL (3 << 0) +#define DAC_RANGE_CNTL_MASK 0x03 +#define DAC_BLANKING (1 << 2) +#define DAC_CMP_EN (1 << 3) +#define DAC_CMP_OUTPUT (1 << 7) /* DAC_CNTL2 bit constants */ -#define DAC2_EXPAND_MODE (1 << 14) -#define DAC2_CMP_EN (1 << 7) -#define DAC2_PALETTE_ACCESS_CNTL (1 << 5) +#define DAC2_EXPAND_MODE (1 << 14) +#define DAC2_CMP_EN (1 << 7) +#define DAC2_PALETTE_ACCESS_CNTL (1 << 5) /* DAC_EXT_CNTL bit constants */ -#define DAC_FORCE_BLANK_OFF_EN (1 << 4) -#define DAC_FORCE_DATA_EN (1 << 5) -#define DAC_FORCE_DATA_SEL_MASK (3 << 6) -#define DAC_FORCE_DATA_MASK 0x0003ff00 -#define DAC_FORCE_DATA_SHIFT 8 +#define DAC_FORCE_BLANK_OFF_EN (1 << 4) +#define DAC_FORCE_DATA_EN (1 << 5) +#define DAC_FORCE_DATA_SEL_MASK (3 << 6) +#define DAC_FORCE_DATA_MASK 0x0003ff00 +#define DAC_FORCE_DATA_SHIFT 8 /* GEN_RESET_CNTL bit constants */ -#define SOFT_RESET_GUI 0x00000001 -#define SOFT_RESET_VCLK 0x00000100 -#define SOFT_RESET_PCLK 0x00000200 -#define SOFT_RESET_ECP 0x00000400 -#define SOFT_RESET_DISPENG_XCLK 0x00000800 +#define SOFT_RESET_GUI 0x00000001 +#define SOFT_RESET_VCLK 0x00000100 +#define SOFT_RESET_PCLK 0x00000200 +#define SOFT_RESET_ECP 0x00000400 +#define SOFT_RESET_DISPENG_XCLK 0x00000800 /* MEM_CNTL bit constants */ -#define MEM_CTLR_STATUS_IDLE 0x00000000 -#define MEM_CTLR_STATUS_BUSY 0x00100000 -#define MEM_SEQNCR_STATUS_IDLE 0x00000000 -#define MEM_SEQNCR_STATUS_BUSY 0x00200000 -#define MEM_ARBITER_STATUS_IDLE 0x00000000 -#define MEM_ARBITER_STATUS_BUSY 0x00400000 -#define MEM_REQ_UNLOCK 0x00000000 -#define MEM_REQ_LOCK 0x00800000 -#define MEM_NUM_CHANNELS_MASK 0x00000001 -#define MEM_USE_B_CH_ONLY 0x00000002 -#define RV100_MEM_HALF_MODE 0x00000008 -#define R300_MEM_NUM_CHANNELS_MASK 0x00000003 -#define R300_MEM_USE_CD_CH_ONLY 0x00000004 +#define MEM_CTLR_STATUS_IDLE 0x00000000 +#define MEM_CTLR_STATUS_BUSY 0x00100000 +#define MEM_SEQNCR_STATUS_IDLE 0x00000000 +#define MEM_SEQNCR_STATUS_BUSY 0x00200000 +#define MEM_ARBITER_STATUS_IDLE 0x00000000 +#define MEM_ARBITER_STATUS_BUSY 0x00400000 +#define MEM_REQ_UNLOCK 0x00000000 +#define MEM_REQ_LOCK 0x00800000 +#define MEM_NUM_CHANNELS_MASK 0x00000001 +#define MEM_USE_B_CH_ONLY 0x00000002 +#define RV100_MEM_HALF_MODE 0x00000008 +#define R300_MEM_NUM_CHANNELS_MASK 0x00000003 +#define R300_MEM_USE_CD_CH_ONLY 0x00000004 /* RBBM_SOFT_RESET bit constants */ -#define SOFT_RESET_CP (1 << 0) -#define SOFT_RESET_HI (1 << 1) -#define SOFT_RESET_SE (1 << 2) -#define SOFT_RESET_RE (1 << 3) -#define SOFT_RESET_PP (1 << 4) -#define SOFT_RESET_E2 (1 << 5) -#define SOFT_RESET_RB (1 << 6) -#define SOFT_RESET_HDP (1 << 7) +#define SOFT_RESET_CP (1 << 0) +#define SOFT_RESET_HI (1 << 1) +#define SOFT_RESET_SE (1 << 2) +#define SOFT_RESET_RE (1 << 3) +#define SOFT_RESET_PP (1 << 4) +#define SOFT_RESET_E2 (1 << 5) +#define SOFT_RESET_RB (1 << 6) +#define SOFT_RESET_HDP (1 << 7) /* SURFACE_CNTL bit consants */ -#define SURF_TRANSLATION_DIS (1 << 8) -#define NONSURF_AP0_SWP_16BPP (1 << 20) -#define NONSURF_AP0_SWP_32BPP (1 << 21) -#define NONSURF_AP1_SWP_16BPP (1 << 22) -#define NONSURF_AP1_SWP_32BPP (1 << 23) +#define SURF_TRANSLATION_DIS (1 << 8) +#define NONSURF_AP0_SWP_16BPP (1 << 20) +#define NONSURF_AP0_SWP_32BPP (1 << 21) +#define NONSURF_AP1_SWP_16BPP (1 << 22) +#define NONSURF_AP1_SWP_32BPP (1 << 23) /* DEFAULT_SC_BOTTOM_RIGHT bit constants */ -#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) -#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +#define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) /* MM_INDEX bit constants */ -#define MM_APER 0x80000000 +#define MM_APER 0x80000000 /* CLR_CMP_CNTL bit constants */ -#define COMPARE_SRC_FALSE 0x00000000 -#define COMPARE_SRC_TRUE 0x00000001 -#define COMPARE_SRC_NOT_EQUAL 0x00000004 -#define COMPARE_SRC_EQUAL 0x00000005 -#define COMPARE_SRC_EQUAL_FLIP 0x00000007 -#define COMPARE_DST_FALSE 0x00000000 -#define COMPARE_DST_TRUE 0x00000100 -#define COMPARE_DST_NOT_EQUAL 0x00000400 -#define COMPARE_DST_EQUAL 0x00000500 -#define COMPARE_DESTINATION 0x00000000 -#define COMPARE_SOURCE 0x01000000 -#define COMPARE_SRC_AND_DST 0x02000000 +#define COMPARE_SRC_FALSE 0x00000000 +#define COMPARE_SRC_TRUE 0x00000001 +#define COMPARE_SRC_NOT_EQUAL 0x00000004 +#define COMPARE_SRC_EQUAL 0x00000005 +#define COMPARE_SRC_EQUAL_FLIP 0x00000007 +#define COMPARE_DST_FALSE 0x00000000 +#define COMPARE_DST_TRUE 0x00000100 +#define COMPARE_DST_NOT_EQUAL 0x00000400 +#define COMPARE_DST_EQUAL 0x00000500 +#define COMPARE_DESTINATION 0x00000000 +#define COMPARE_SOURCE 0x01000000 +#define COMPARE_SRC_AND_DST 0x02000000 /* DP_CNTL bit constants */ -#define DST_X_RIGHT_TO_LEFT 0x00000000 -#define DST_X_LEFT_TO_RIGHT 0x00000001 -#define DST_Y_BOTTOM_TO_TOP 0x00000000 -#define DST_Y_TOP_TO_BOTTOM 0x00000002 -#define DST_X_MAJOR 0x00000000 -#define DST_Y_MAJOR 0x00000004 -#define DST_X_TILE 0x00000008 -#define DST_Y_TILE 0x00000010 -#define DST_LAST_PEL 0x00000020 -#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 -#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 -#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 -#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 -#define DST_BRES_SIGN 0x00000100 -#define DST_HOST_BIG_ENDIAN_EN 0x00000200 -#define DST_POLYLINE_NONLAST 0x00008000 -#define DST_RASTER_STALL 0x00010000 -#define DST_POLY_EDGE 0x00040000 +#define DST_X_RIGHT_TO_LEFT 0x00000000 +#define DST_X_LEFT_TO_RIGHT 0x00000001 +#define DST_Y_BOTTOM_TO_TOP 0x00000000 +#define DST_Y_TOP_TO_BOTTOM 0x00000002 +#define DST_X_MAJOR 0x00000000 +#define DST_Y_MAJOR 0x00000004 +#define DST_X_TILE 0x00000008 +#define DST_Y_TILE 0x00000010 +#define DST_LAST_PEL 0x00000020 +#define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 +#define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 +#define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 +#define DST_BRES_SIGN 0x00000100 +#define DST_HOST_BIG_ENDIAN_EN 0x00000200 +#define DST_POLYLINE_NONLAST 0x00008000 +#define DST_RASTER_STALL 0x00010000 +#define DST_POLY_EDGE 0x00040000 /* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ -#define DST_X_MAJOR_S 0x00000000 -#define DST_Y_MAJOR_S 0x00000001 -#define DST_Y_BOTTOM_TO_TOP_S 0x00000000 -#define DST_Y_TOP_TO_BOTTOM_S 0x00008000 -#define DST_X_RIGHT_TO_LEFT_S 0x00000000 -#define DST_X_LEFT_TO_RIGHT_S 0x80000000 +#define DST_X_MAJOR_S 0x00000000 +#define DST_Y_MAJOR_S 0x00000001 +#define DST_Y_BOTTOM_TO_TOP_S 0x00000000 +#define DST_Y_TOP_TO_BOTTOM_S 0x00008000 +#define DST_X_RIGHT_TO_LEFT_S 0x00000000 +#define DST_X_LEFT_TO_RIGHT_S 0x80000000 /* DP_DATATYPE bit constants */ -#define DST_8BPP 0x00000002 -#define DST_15BPP 0x00000003 -#define DST_16BPP 0x00000004 -#define DST_24BPP 0x00000005 -#define DST_32BPP 0x00000006 -#define DST_8BPP_RGB332 0x00000007 -#define DST_8BPP_Y8 0x00000008 -#define DST_8BPP_RGB8 0x00000009 -#define DST_16BPP_VYUY422 0x0000000b -#define DST_16BPP_YVYU422 0x0000000c -#define DST_32BPP_AYUV444 0x0000000e -#define DST_16BPP_ARGB4444 0x0000000f -#define BRUSH_SOLIDCOLOR 0x00000d00 -#define SRC_MONO 0x00000000 -#define SRC_MONO_LBKGD 0x00010000 -#define SRC_DSTCOLOR 0x00030000 -#define BYTE_ORDER_MSB_TO_LSB 0x00000000 -#define BYTE_ORDER_LSB_TO_MSB 0x40000000 -#define DP_CONVERSION_TEMP 0x80000000 -#define HOST_BIG_ENDIAN_EN (1 << 29) +#define DST_8BPP 0x00000002 +#define DST_15BPP 0x00000003 +#define DST_16BPP 0x00000004 +#define DST_24BPP 0x00000005 +#define DST_32BPP 0x00000006 +#define DST_8BPP_RGB332 0x00000007 +#define DST_8BPP_Y8 0x00000008 +#define DST_8BPP_RGB8 0x00000009 +#define DST_16BPP_VYUY422 0x0000000b +#define DST_16BPP_YVYU422 0x0000000c +#define DST_32BPP_AYUV444 0x0000000e +#define DST_16BPP_ARGB4444 0x0000000f +#define BRUSH_SOLIDCOLOR 0x00000d00 +#define SRC_MONO 0x00000000 +#define SRC_MONO_LBKGD 0x00010000 +#define SRC_DSTCOLOR 0x00030000 +#define BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define BYTE_ORDER_LSB_TO_MSB 0x40000000 +#define DP_CONVERSION_TEMP 0x80000000 +#define HOST_BIG_ENDIAN_EN (1 << 29) /* DP_GUI_MASTER_CNTL bit constants */ -#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 -#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 -#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 -#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 -#define GMC_SRC_CLIP_DEFAULT 0x00000000 -#define GMC_SRC_CLIP_LEAVE 0x00000004 -#define GMC_DST_CLIP_DEFAULT 0x00000000 -#define GMC_DST_CLIP_LEAVE 0x00000008 -#define GMC_BRUSH_8x8MONO 0x00000000 -#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 -#define GMC_BRUSH_8x1MONO 0x00000020 -#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 -#define GMC_BRUSH_1x8MONO 0x00000040 -#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 -#define GMC_BRUSH_32x1MONO 0x00000060 -#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 -#define GMC_BRUSH_32x32MONO 0x00000080 -#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 -#define GMC_BRUSH_8x8COLOR 0x000000a0 -#define GMC_BRUSH_8x1COLOR 0x000000b0 -#define GMC_BRUSH_1x8COLOR 0x000000c0 -#define GMC_BRUSH_SOLID_COLOR 0x000000d0 -#define GMC_DST_8BPP 0x00000200 -#define GMC_DST_15BPP 0x00000300 -#define GMC_DST_16BPP 0x00000400 -#define GMC_DST_24BPP 0x00000500 -#define GMC_DST_32BPP 0x00000600 -#define GMC_DST_8BPP_RGB332 0x00000700 -#define GMC_DST_8BPP_Y8 0x00000800 -#define GMC_DST_8BPP_RGB8 0x00000900 -#define GMC_DST_16BPP_VYUY422 0x00000b00 -#define GMC_DST_16BPP_YVYU422 0x00000c00 -#define GMC_DST_32BPP_AYUV444 0x00000e00 -#define GMC_DST_16BPP_ARGB4444 0x00000f00 -#define GMC_SRC_MONO 0x00000000 -#define GMC_SRC_MONO_LBKGD 0x00001000 -#define GMC_SRC_DSTCOLOR 0x00003000 -#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 -#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 -#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 -#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 -#define GMC_DP_SRC_RECT 0x02000000 -#define GMC_DP_SRC_HOST 0x03000000 -#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 -#define GMC_3D_FCN_EN_CLR 0x00000000 -#define GMC_3D_FCN_EN_SET 0x08000000 -#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 -#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 -#define GMC_AUX_CLIP_LEAVE 0x00000000 -#define GMC_AUX_CLIP_CLEAR 0x20000000 -#define GMC_WRITE_MASK_LEAVE 0x00000000 -#define GMC_WRITE_MASK_SET 0x40000000 -#define GMC_CLR_CMP_CNTL_DIS (1 << 28) -#define GMC_SRC_DATATYPE_COLOR (3 << 12) -#define ROP3_S 0x00cc0000 -#define ROP3_SRCCOPY 0x00cc0000 -#define ROP3_P 0x00f00000 -#define ROP3_PATCOPY 0x00f00000 -#define DP_SRC_SOURCE_MASK (7 << 24) -#define GMC_BRUSH_NONE (15 << 4) -#define DP_SRC_SOURCE_MEMORY (2 << 24) -#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 +#define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 +#define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +#define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 +#define GMC_SRC_CLIP_DEFAULT 0x00000000 +#define GMC_SRC_CLIP_LEAVE 0x00000004 +#define GMC_DST_CLIP_DEFAULT 0x00000000 +#define GMC_DST_CLIP_LEAVE 0x00000008 +#define GMC_BRUSH_8x8MONO 0x00000000 +#define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 +#define GMC_BRUSH_8x1MONO 0x00000020 +#define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 +#define GMC_BRUSH_1x8MONO 0x00000040 +#define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 +#define GMC_BRUSH_32x1MONO 0x00000060 +#define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 +#define GMC_BRUSH_32x32MONO 0x00000080 +#define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 +#define GMC_BRUSH_8x8COLOR 0x000000a0 +#define GMC_BRUSH_8x1COLOR 0x000000b0 +#define GMC_BRUSH_1x8COLOR 0x000000c0 +#define GMC_BRUSH_SOLID_COLOR 0x000000d0 +#define GMC_DST_8BPP 0x00000200 +#define GMC_DST_15BPP 0x00000300 +#define GMC_DST_16BPP 0x00000400 +#define GMC_DST_24BPP 0x00000500 +#define GMC_DST_32BPP 0x00000600 +#define GMC_DST_8BPP_RGB332 0x00000700 +#define GMC_DST_8BPP_Y8 0x00000800 +#define GMC_DST_8BPP_RGB8 0x00000900 +#define GMC_DST_16BPP_VYUY422 0x00000b00 +#define GMC_DST_16BPP_YVYU422 0x00000c00 +#define GMC_DST_32BPP_AYUV444 0x00000e00 +#define GMC_DST_16BPP_ARGB4444 0x00000f00 +#define GMC_SRC_MONO 0x00000000 +#define GMC_SRC_MONO_LBKGD 0x00001000 +#define GMC_SRC_DSTCOLOR 0x00003000 +#define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 +#define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 +#define GMC_DP_CONVERSION_TEMP_9300 0x00008000 +#define GMC_DP_CONVERSION_TEMP_6500 0x00000000 +#define GMC_DP_SRC_RECT 0x02000000 +#define GMC_DP_SRC_HOST 0x03000000 +#define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 +#define GMC_3D_FCN_EN_CLR 0x00000000 +#define GMC_3D_FCN_EN_SET 0x08000000 +#define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 +#define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 +#define GMC_AUX_CLIP_LEAVE 0x00000000 +#define GMC_AUX_CLIP_CLEAR 0x20000000 +#define GMC_WRITE_MASK_LEAVE 0x00000000 +#define GMC_WRITE_MASK_SET 0x40000000 +#define GMC_CLR_CMP_CNTL_DIS (1 << 28) +#define GMC_SRC_DATATYPE_COLOR (3 << 12) +#define ROP3_S 0x00cc0000 +#define ROP3_SRCCOPY 0x00cc0000 +#define ROP3_P 0x00f00000 +#define ROP3_PATCOPY 0x00f00000 +#define DP_SRC_SOURCE_MASK (7 << 24) +#define GMC_BRUSH_NONE (15 << 4) +#define DP_SRC_SOURCE_MEMORY (2 << 24) +#define GMC_BRUSH_SOLIDCOLOR 0x000000d0 /* DP_MIX bit constants */ -#define DP_SRC_RECT 0x00000200 -#define DP_SRC_HOST 0x00000300 -#define DP_SRC_HOST_BYTEALIGN 0x00000400 +#define DP_SRC_RECT 0x00000200 +#define DP_SRC_HOST 0x00000300 +#define DP_SRC_HOST_BYTEALIGN 0x00000400 /* MPLL_CNTL bit constants */ -#define MPLL_RESET 0x00000001 +#define MPLL_RESET 0x00000001 /* MDLL_CKO bit constants */ -#define MCKOA_SLEEP 0x00000001 -#define MCKOA_RESET 0x00000002 -#define MCKOA_REF_SKEW_MASK 0x00000700 -#define MCKOA_FB_SKEW_MASK 0x00007000 +#define MCKOA_SLEEP 0x00000001 +#define MCKOA_RESET 0x00000002 +#define MCKOA_REF_SKEW_MASK 0x00000700 +#define MCKOA_FB_SKEW_MASK 0x00007000 /* MDLL_RDCKA bit constants */ -#define MRDCKA0_SLEEP 0x00000001 -#define MRDCKA0_RESET 0x00000002 -#define MRDCKA1_SLEEP 0x00010000 -#define MRDCKA1_RESET 0x00020000 +#define MRDCKA0_SLEEP 0x00000001 +#define MRDCKA0_RESET 0x00000002 +#define MRDCKA1_SLEEP 0x00010000 +#define MRDCKA1_RESET 0x00020000 /* VCLK_ECP_CNTL constants */ -#define VCLK_SRC_SEL_MASK 0x03 -#define VCLK_SRC_SEL_CPUCLK 0x00 -#define VCLK_SRC_SEL_PSCANCLK 0x01 -#define VCLK_SRC_SEL_BYTECLK 0x02 -#define VCLK_SRC_SEL_PPLLCLK 0x03 -#define PIXCLK_ALWAYS_ONb 0x00000040 -#define PIXCLK_DAC_ALWAYS_ONb 0x00000080 +#define VCLK_SRC_SEL_MASK 0x03 +#define VCLK_SRC_SEL_CPUCLK 0x00 +#define VCLK_SRC_SEL_PSCANCLK 0x01 +#define VCLK_SRC_SEL_BYTECLK 0x02 +#define VCLK_SRC_SEL_PPLLCLK 0x03 +#define PIXCLK_ALWAYS_ONb 0x00000040 +#define PIXCLK_DAC_ALWAYS_ONb 0x00000080 /* BUS_CNTL1 constants */ -#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 -#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 -#define BUS_CNTL1_AGPCLK_VALID 0x80000000 +#define BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK 0x0c000000 +#define BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT 26 +#define BUS_CNTL1_AGPCLK_VALID 0x80000000 /* PLL_PWRMGT_CNTL constants */ -#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 -#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 -#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 -#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 -#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 -#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 -#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 +#define PLL_PWRMGT_CNTL_SPLL_TURNOFF 0x00000002 +#define PLL_PWRMGT_CNTL_PPLL_TURNOFF 0x00000004 +#define PLL_PWRMGT_CNTL_P2PLL_TURNOFF 0x00000008 +#define PLL_PWRMGT_CNTL_TVPLL_TURNOFF 0x00000010 +#define PLL_PWRMGT_CNTL_MOBILE_SU 0x00010000 +#define PLL_PWRMGT_CNTL_SU_SCLK_USE_BCLK 0x00020000 +#define PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK 0x00040000 /* TV_DAC_CNTL constants */ -#define TV_DAC_CNTL_BGSLEEP 0x00000040 -#define TV_DAC_CNTL_DETECT 0x00000010 -#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 -#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 -#define TV_DAC_CNTL_BGADJ__SHIFT 16 -#define TV_DAC_CNTL_DACADJ__SHIFT 20 -#define TV_DAC_CNTL_RDACPD 0x01000000 -#define TV_DAC_CNTL_GDACPD 0x02000000 -#define TV_DAC_CNTL_BDACPD 0x04000000 +#define TV_DAC_CNTL_BGSLEEP 0x00000040 +#define TV_DAC_CNTL_DETECT 0x00000010 +#define TV_DAC_CNTL_BGADJ_MASK 0x000f0000 +#define TV_DAC_CNTL_DACADJ_MASK 0x00f00000 +#define TV_DAC_CNTL_BGADJ__SHIFT 16 +#define TV_DAC_CNTL_DACADJ__SHIFT 20 +#define TV_DAC_CNTL_RDACPD 0x01000000 +#define TV_DAC_CNTL_GDACPD 0x02000000 +#define TV_DAC_CNTL_BDACPD 0x04000000 /* DISP_MISC_CNTL constants */ -#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) -#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) -#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) -#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) -#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) -#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) -#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) -#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) -#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) -#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH_PP (1 << 0) +#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP (1 << 1) +#define DISP_MISC_CNTL_SOFT_RESET_OV0_PP (1 << 2) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK (1 << 4) +#define DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK (1 << 5) +#define DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK (1 << 6) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP (1 << 12) +#define DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK (1 << 15) +#define DISP_MISC_CNTL_SOFT_RESET_LVDS (1 << 16) +#define DISP_MISC_CNTL_SOFT_RESET_TMDS (1 << 17) +#define DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS (1 << 18) +#define DISP_MISC_CNTL_SOFT_RESET_TV (1 << 19) /* DISP_PWR_MAN constants */ -#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) -#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) -#define DISP_PWR_MAN_DISP_D3_RST (1 << 16) -#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) -#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) -#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) -#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) -#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) -#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) -#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) -#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) -#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) -#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) +#define DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN (1 << 0) +#define DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN (1 << 4) +#define DISP_PWR_MAN_DISP_D3_RST (1 << 16) +#define DISP_PWR_MAN_DISP_D3_REG_RST (1 << 17) +#define DISP_PWR_MAN_DISP_D3_GRPH_RST (1 << 18) +#define DISP_PWR_MAN_DISP_D3_SUBPIC_RST (1 << 19) +#define DISP_PWR_MAN_DISP_D3_OV0_RST (1 << 20) +#define DISP_PWR_MAN_DISP_D1D2_GRPH_RST (1 << 21) +#define DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST (1 << 22) +#define DISP_PWR_MAN_DISP_D1D2_OV0_RST (1 << 23) +#define DISP_PWR_MAN_DIG_TMDS_ENABLE_RST (1 << 24) +#define DISP_PWR_MAN_TV_ENABLE_RST (1 << 25) +#define DISP_PWR_MAN_AUTO_PWRUP_EN (1 << 26) /* masks */ @@ -978,1009 +978,1007 @@ #define DST_OFFSET_MASK 0x003fffff #define DST_PITCH_MASK 0x3fc00000 #define DEFAULT_TILE_MASK 0xc0000000 -#define PPLL_DIV_SEL_MASK 0x00000300 -#define PPLL_RESET 0x00000001 -#define PPLL_SLEEP 0x00000002 +#define PPLL_DIV_SEL_MASK 0x00000300 +#define PPLL_RESET 0x00000001 +#define PPLL_SLEEP 0x00000002 #define PPLL_ATOMIC_UPDATE_EN 0x00010000 #define PPLL_REF_DIV_MASK 0x000003ff -#define PPLL_FB3_DIV_MASK 0x000007ff -#define PPLL_POST3_DIV_MASK 0x00070000 +#define PPLL_FB3_DIV_MASK 0x000007ff +#define PPLL_POST3_DIV_MASK 0x00070000 #define PPLL_ATOMIC_UPDATE_R 0x00008000 #define PPLL_ATOMIC_UPDATE_W 0x00008000 -#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 +#define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 #define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) #define R300_PPLL_REF_DIV_ACC_SHIFT 18 #define GUI_ACTIVE 0x80000000 -#define MC_IND_INDEX 0x01F8 -#define MC_IND_DATA 0x01FC +#define MC_IND_INDEX 0x01F8 +#define MC_IND_DATA 0x01FC /* PAD_CTLR_STRENGTH */ #define PAD_MANUAL_OVERRIDE 0x80000000 -// pllCLK_PIN_CNTL -#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L -#define CLK_PIN_CNTL__OSC_EN 0x00000001L -#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L -#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L -#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L -#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L -#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L -#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L -#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L -#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L -#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L -#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L -#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L -#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L -#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L -#define CLK_PIN_CNTL__CG_SPARE 0x00004000L -#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L -#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L -#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L -#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L -#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L -#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L -#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L -#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L - -// pllCLK_PWRMGT_CNTL -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004 -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005 -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006 -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007 -#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008 -#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009 -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c -#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f -#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010 -#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011 -#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012 -#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013 -#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014 -#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015 -#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018 -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f - -// pllP2PLL_CNTL -#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L -#define P2PLL_CNTL__P2PLL_RESET 0x00000001L -#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L -#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L -#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L -#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L -#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L -#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L -#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L -#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L -#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L -#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L -#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L -#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L -#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L -#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L -#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L -#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L -#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L -#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L - -// pllPIXCLKS_CNTL -#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 -#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 -#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 -#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 -#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 -#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 -#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b -#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c -#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d -#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e -#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f - - -// pllPIXCLKS_CNTL -#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L -#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L -#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L -#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L -#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L -#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L -#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L -#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L -#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L -#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L -#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L -#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) -#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) -#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) -#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) -#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) -#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) -#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) -#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) - - -// pllP2PLL_DIV_0 -#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L -#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L -#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L - -// pllSCLK_CNTL -#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L -#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L -#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L -#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L -#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L -#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L -#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L -#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L -#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L -#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L -#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L -#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L -#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L -#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8 -#define SCLK_CNTL__FORCE_DISP2 0x00008000L -#define SCLK_CNTL__FORCE_CP 0x00010000L -#define SCLK_CNTL__FORCE_HDP 0x00020000L -#define SCLK_CNTL__FORCE_DISP1 0x00040000L -#define SCLK_CNTL__FORCE_TOP 0x00080000L -#define SCLK_CNTL__FORCE_E2 0x00100000L -#define SCLK_CNTL__FORCE_SE 0x00200000L -#define SCLK_CNTL__FORCE_IDCT 0x00400000L -#define SCLK_CNTL__FORCE_VIP 0x00800000L -#define SCLK_CNTL__FORCE_RE 0x01000000L -#define SCLK_CNTL__FORCE_PB 0x02000000L -#define SCLK_CNTL__FORCE_TAM 0x04000000L -#define SCLK_CNTL__FORCE_TDM 0x08000000L -#define SCLK_CNTL__FORCE_RB 0x10000000L -#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L -#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L -#define SCLK_CNTL__FORCE_OV0 0x80000000L -#define SCLK_CNTL__R300_FORCE_VAP (1<<21) -#define SCLK_CNTL__R300_FORCE_SR (1<<25) -#define SCLK_CNTL__R300_FORCE_PX (1<<26) -#define SCLK_CNTL__R300_FORCE_TX (1<<27) -#define SCLK_CNTL__R300_FORCE_US (1<<28) -#define SCLK_CNTL__R300_FORCE_SU (1<<30) -#define SCLK_CNTL__FORCEON_MASK 0xffff8000L - -// pllSCLK_CNTL2 -#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) -#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) -#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) -#define SCLK_CNTL2__R300_FORCE_TCL (1<<13) -#define SCLK_CNTL2__R300_FORCE_CBA (1<<14) -#define SCLK_CNTL2__R300_FORCE_GA (1<<15) - -// SCLK_MORE_CNTL -#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L -#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L -#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L -#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L -#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L -#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L -#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L -#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L -#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L -#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L -#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L -#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L -#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L -#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L -#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L -#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L -#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L -#define SCLK_MORE_CNTL__FORCEON 0x00000700L - -// MCLK_CNTL -#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L -#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L -#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L -#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L -#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L -#define MCLK_CNTL__FORCE_MCLKA 0x00010000L -#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L -#define MCLK_CNTL__FORCE_MCLKB 0x00020000L -#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L -#define MCLK_CNTL__FORCE_YCLKA 0x00040000L -#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L -#define MCLK_CNTL__FORCE_YCLKB 0x00080000L -#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L -#define MCLK_CNTL__FORCE_MC 0x00100000L -#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L -#define MCLK_CNTL__FORCE_AIC 0x00200000L -#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L -#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L -#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L -#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L -#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) -#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) - -// MCLK_MISC -#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L -#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L -#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L -#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L -#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L -#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L -#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L -#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L -#define MCLK_MISC__DLL_READY_LAT 0x00000100L -#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L -#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L -#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L -#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L -#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L -#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L -#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L -#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L -#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L -#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L -#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L -#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L -#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L -#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L -#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L -#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L -#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L -#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L -#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L - -// VCLK_ECP_CNTL -#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L -#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L -#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L -#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L -#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L -#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L -#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L -#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L +/* pllCLK_PIN_CNTL */ +#define CLK_PIN_CNTL__OSC_EN_MASK 0x00000001L +#define CLK_PIN_CNTL__OSC_EN 0x00000001L +#define CLK_PIN_CNTL__XTL_LOW_GAIN_MASK 0x00000004L +#define CLK_PIN_CNTL__XTL_LOW_GAIN 0x00000004L +#define CLK_PIN_CNTL__DONT_USE_XTALIN_MASK 0x00000010L +#define CLK_PIN_CNTL__DONT_USE_XTALIN 0x00000010L +#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE_MASK 0x00000020L +#define CLK_PIN_CNTL__SLOW_CLOCK_SOURCE 0x00000020L +#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN_MASK 0x00000800L +#define CLK_PIN_CNTL__CG_CLK_TO_OUTPIN 0x00000800L +#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN_MASK 0x00001000L +#define CLK_PIN_CNTL__CG_COUNT_UP_TO_OUTPIN 0x00001000L +#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND_MASK 0x00002000L +#define CLK_PIN_CNTL__ACCESS_REGS_IN_SUSPEND 0x00002000L +#define CLK_PIN_CNTL__CG_SPARE_MASK 0x00004000L +#define CLK_PIN_CNTL__CG_SPARE 0x00004000L +#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL_MASK 0x00008000L +#define CLK_PIN_CNTL__SCLK_DYN_START_CNTL 0x00008000L +#define CLK_PIN_CNTL__CP_CLK_RUNNING_MASK 0x00010000L +#define CLK_PIN_CNTL__CP_CLK_RUNNING 0x00010000L +#define CLK_PIN_CNTL__CG_SPARE_RD_MASK 0x00060000L +#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb_MASK 0x00080000L +#define CLK_PIN_CNTL__XTALIN_ALWAYS_ONb 0x00080000L +#define CLK_PIN_CNTL__PWRSEQ_DELAY_MASK 0xff000000L + +/* pllCLK_PWRMGT_CNTL */ +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF__SHIFT 0x00000000 +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF__SHIFT 0x00000001 +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF__SHIFT 0x00000002 +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF__SHIFT 0x00000003 +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF__SHIFT 0x00000004 +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF__SHIFT 0x00000005 +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF__SHIFT 0x00000006 +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF__SHIFT 0x00000007 +#define CLK_PWRMGT_CNTL__MC_CH_MODE__SHIFT 0x00000008 +#define CLK_PWRMGT_CNTL__TEST_MODE__SHIFT 0x00000009 +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN__SHIFT 0x0000000a +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE__SHIFT 0x0000000c +#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT__SHIFT 0x0000000d +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT__SHIFT 0x0000000f +#define CLK_PWRMGT_CNTL__MC_BUSY__SHIFT 0x00000010 +#define CLK_PWRMGT_CNTL__MC_INT_CNTL__SHIFT 0x00000011 +#define CLK_PWRMGT_CNTL__MC_SWITCH__SHIFT 0x00000012 +#define CLK_PWRMGT_CNTL__DLL_READY__SHIFT 0x00000013 +#define CLK_PWRMGT_CNTL__DISP_PM__SHIFT 0x00000014 +#define CLK_PWRMGT_CNTL__DYN_STOP_MODE__SHIFT 0x00000015 +#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG__SHIFT 0x00000018 +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF__SHIFT 0x0000001e +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF__SHIFT 0x0000001f + +/* pllP2PLL_CNTL */ +#define P2PLL_CNTL__P2PLL_RESET_MASK 0x00000001L +#define P2PLL_CNTL__P2PLL_RESET 0x00000001L +#define P2PLL_CNTL__P2PLL_SLEEP_MASK 0x00000002L +#define P2PLL_CNTL__P2PLL_SLEEP 0x00000002L +#define P2PLL_CNTL__P2PLL_TST_EN_MASK 0x00000004L +#define P2PLL_CNTL__P2PLL_TST_EN 0x00000004L +#define P2PLL_CNTL__P2PLL_REFCLK_SEL_MASK 0x00000010L +#define P2PLL_CNTL__P2PLL_REFCLK_SEL 0x00000010L +#define P2PLL_CNTL__P2PLL_FBCLK_SEL_MASK 0x00000020L +#define P2PLL_CNTL__P2PLL_FBCLK_SEL 0x00000020L +#define P2PLL_CNTL__P2PLL_TCPOFF_MASK 0x00000040L +#define P2PLL_CNTL__P2PLL_TCPOFF 0x00000040L +#define P2PLL_CNTL__P2PLL_TVCOMAX_MASK 0x00000080L +#define P2PLL_CNTL__P2PLL_TVCOMAX 0x00000080L +#define P2PLL_CNTL__P2PLL_PCP_MASK 0x00000700L +#define P2PLL_CNTL__P2PLL_PVG_MASK 0x00003800L +#define P2PLL_CNTL__P2PLL_PDC_MASK 0x0000c000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN_MASK 0x00010000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_EN 0x00010000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC_MASK 0x00040000L +#define P2PLL_CNTL__P2PLL_ATOMIC_UPDATE_SYNC 0x00040000L +#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET_MASK 0x00080000L +#define P2PLL_CNTL__P2PLL_DISABLE_AUTO_RESET 0x00080000L + +/* pllPIXCLKS_CNTL */ +#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL__SHIFT 0x00000000 +#define PIXCLKS_CNTL__PIX2CLK_INVERT__SHIFT 0x00000004 +#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT__SHIFT 0x00000005 +#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb__SHIFT 0x00000006 +#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb__SHIFT 0x00000007 +#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL__SHIFT 0x00000008 +#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb__SHIFT 0x0000000b +#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb__SHIFT 0x0000000c +#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb__SHIFT 0x0000000d +#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb__SHIFT 0x0000000e +#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb__SHIFT 0x0000000f + + +/* pllPIXCLKS_CNTL */ +#define PIXCLKS_CNTL__PIX2CLK_SRC_SEL_MASK 0x00000003L +#define PIXCLKS_CNTL__PIX2CLK_INVERT 0x00000010L +#define PIXCLKS_CNTL__PIX2CLK_SRC_INVERT 0x00000020L +#define PIXCLKS_CNTL__PIX2CLK_ALWAYS_ONb 0x00000040L +#define PIXCLKS_CNTL__PIX2CLK_DAC_ALWAYS_ONb 0x00000080L +#define PIXCLKS_CNTL__PIXCLK_TV_SRC_SEL 0x00000100L +#define PIXCLKS_CNTL__PIXCLK_BLEND_ALWAYS_ONb 0x00000800L +#define PIXCLKS_CNTL__PIXCLK_GV_ALWAYS_ONb 0x00001000L +#define PIXCLKS_CNTL__PIXCLK_DIG_TMDS_ALWAYS_ONb 0x00002000L +#define PIXCLKS_CNTL__PIXCLK_LVDS_ALWAYS_ONb 0x00004000L +#define PIXCLKS_CNTL__PIXCLK_TMDS_ALWAYS_ONb 0x00008000L +#define PIXCLKS_CNTL__DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) +#define PIXCLKS_CNTL__R300_DVOCLK_ALWAYS_ONb (1 << 10) +#define PIXCLKS_CNTL__R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) +#define PIXCLKS_CNTL__R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) +#define PIXCLKS_CNTL__R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) +#define PIXCLKS_CNTL__R300_P2G2CLK_ALWAYS_ONb (1 << 18) +#define PIXCLKS_CNTL__R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) +#define PIXCLKS_CNTL__R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) + + +/* pllP2PLL_DIV_0 */ +#define P2PLL_DIV_0__P2PLL_FB_DIV_MASK 0x000007ffL +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W_MASK 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_W 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R_MASK 0x00008000L +#define P2PLL_DIV_0__P2PLL_ATOMIC_UPDATE_R 0x00008000L +#define P2PLL_DIV_0__P2PLL_POST_DIV_MASK 0x00070000L + +/* pllSCLK_CNTL */ +#define SCLK_CNTL__SCLK_SRC_SEL_MASK 0x00000007L +#define SCLK_CNTL__CP_MAX_DYN_STOP_LAT 0x00000008L +#define SCLK_CNTL__HDP_MAX_DYN_STOP_LAT 0x00000010L +#define SCLK_CNTL__TV_MAX_DYN_STOP_LAT 0x00000020L +#define SCLK_CNTL__E2_MAX_DYN_STOP_LAT 0x00000040L +#define SCLK_CNTL__SE_MAX_DYN_STOP_LAT 0x00000080L +#define SCLK_CNTL__IDCT_MAX_DYN_STOP_LAT 0x00000100L +#define SCLK_CNTL__VIP_MAX_DYN_STOP_LAT 0x00000200L +#define SCLK_CNTL__RE_MAX_DYN_STOP_LAT 0x00000400L +#define SCLK_CNTL__PB_MAX_DYN_STOP_LAT 0x00000800L +#define SCLK_CNTL__TAM_MAX_DYN_STOP_LAT 0x00001000L +#define SCLK_CNTL__TDM_MAX_DYN_STOP_LAT 0x00002000L +#define SCLK_CNTL__RB_MAX_DYN_STOP_LAT 0x00004000L +#define SCLK_CNTL__DYN_STOP_LAT_MASK 0x00007ff8 +#define SCLK_CNTL__FORCE_DISP2 0x00008000L +#define SCLK_CNTL__FORCE_CP 0x00010000L +#define SCLK_CNTL__FORCE_HDP 0x00020000L +#define SCLK_CNTL__FORCE_DISP1 0x00040000L +#define SCLK_CNTL__FORCE_TOP 0x00080000L +#define SCLK_CNTL__FORCE_E2 0x00100000L +#define SCLK_CNTL__FORCE_SE 0x00200000L +#define SCLK_CNTL__FORCE_IDCT 0x00400000L +#define SCLK_CNTL__FORCE_VIP 0x00800000L +#define SCLK_CNTL__FORCE_RE 0x01000000L +#define SCLK_CNTL__FORCE_PB 0x02000000L +#define SCLK_CNTL__FORCE_TAM 0x04000000L +#define SCLK_CNTL__FORCE_TDM 0x08000000L +#define SCLK_CNTL__FORCE_RB 0x10000000L +#define SCLK_CNTL__FORCE_TV_SCLK 0x20000000L +#define SCLK_CNTL__FORCE_SUBPIC 0x40000000L +#define SCLK_CNTL__FORCE_OV0 0x80000000L +#define SCLK_CNTL__R300_FORCE_VAP (1<<21) +#define SCLK_CNTL__R300_FORCE_SR (1<<25) +#define SCLK_CNTL__R300_FORCE_PX (1<<26) +#define SCLK_CNTL__R300_FORCE_TX (1<<27) +#define SCLK_CNTL__R300_FORCE_US (1<<28) +#define SCLK_CNTL__R300_FORCE_SU (1<<30) +#define SCLK_CNTL__FORCEON_MASK 0xffff8000L + +/* pllSCLK_CNTL2 */ +#define SCLK_CNTL2__R300_TCL_MAX_DYN_STOP_LAT (1<<10) +#define SCLK_CNTL2__R300_GA_MAX_DYN_STOP_LAT (1<<11) +#define SCLK_CNTL2__R300_CBA_MAX_DYN_STOP_LAT (1<<12) +#define SCLK_CNTL2__R300_FORCE_TCL (1<<13) +#define SCLK_CNTL2__R300_FORCE_CBA (1<<14) +#define SCLK_CNTL2__R300_FORCE_GA (1<<15) + +/* SCLK_MORE_CNTL */ +#define SCLK_MORE_CNTL__DISPREGS_MAX_DYN_STOP_LAT 0x00000001L +#define SCLK_MORE_CNTL__MC_GUI_MAX_DYN_STOP_LAT 0x00000002L +#define SCLK_MORE_CNTL__MC_HOST_MAX_DYN_STOP_LAT 0x00000004L +#define SCLK_MORE_CNTL__FORCE_DISPREGS 0x00000100L +#define SCLK_MORE_CNTL__FORCE_MC_GUI 0x00000200L +#define SCLK_MORE_CNTL__FORCE_MC_HOST 0x00000400L +#define SCLK_MORE_CNTL__STOP_SCLK_EN 0x00001000L +#define SCLK_MORE_CNTL__STOP_SCLK_A 0x00002000L +#define SCLK_MORE_CNTL__STOP_SCLK_B 0x00004000L +#define SCLK_MORE_CNTL__STOP_SCLK_C 0x00008000L +#define SCLK_MORE_CNTL__HALF_SPEED_SCLK 0x00010000L +#define SCLK_MORE_CNTL__IO_CG_VOLTAGE_DROP 0x00020000L +#define SCLK_MORE_CNTL__TVFB_SOFT_RESET 0x00040000L +#define SCLK_MORE_CNTL__VOLTAGE_DROP_SYNC 0x00080000L +#define SCLK_MORE_CNTL__IDLE_DELAY_HALF_SCLK 0x00400000L +#define SCLK_MORE_CNTL__AGP_BUSY_HALF_SCLK 0x00800000L +#define SCLK_MORE_CNTL__CG_SPARE_RD_C_MASK 0xff000000L +#define SCLK_MORE_CNTL__FORCEON 0x00000700L + +/* MCLK_CNTL */ +#define MCLK_CNTL__MCLKA_SRC_SEL_MASK 0x00000007L +#define MCLK_CNTL__YCLKA_SRC_SEL_MASK 0x00000070L +#define MCLK_CNTL__MCLKB_SRC_SEL_MASK 0x00000700L +#define MCLK_CNTL__YCLKB_SRC_SEL_MASK 0x00007000L +#define MCLK_CNTL__FORCE_MCLKA_MASK 0x00010000L +#define MCLK_CNTL__FORCE_MCLKA 0x00010000L +#define MCLK_CNTL__FORCE_MCLKB_MASK 0x00020000L +#define MCLK_CNTL__FORCE_MCLKB 0x00020000L +#define MCLK_CNTL__FORCE_YCLKA_MASK 0x00040000L +#define MCLK_CNTL__FORCE_YCLKA 0x00040000L +#define MCLK_CNTL__FORCE_YCLKB_MASK 0x00080000L +#define MCLK_CNTL__FORCE_YCLKB 0x00080000L +#define MCLK_CNTL__FORCE_MC_MASK 0x00100000L +#define MCLK_CNTL__FORCE_MC 0x00100000L +#define MCLK_CNTL__FORCE_AIC_MASK 0x00200000L +#define MCLK_CNTL__FORCE_AIC 0x00200000L +#define MCLK_CNTL__MRDCKA0_SOUTSEL_MASK 0x03000000L +#define MCLK_CNTL__MRDCKA1_SOUTSEL_MASK 0x0c000000L +#define MCLK_CNTL__MRDCKB0_SOUTSEL_MASK 0x30000000L +#define MCLK_CNTL__MRDCKB1_SOUTSEL_MASK 0xc0000000L +#define MCLK_CNTL__R300_DISABLE_MC_MCLKA (1 << 21) +#define MCLK_CNTL__R300_DISABLE_MC_MCLKB (1 << 21) + +/* MCLK_MISC */ +#define MCLK_MISC__SCLK_SOURCED_FROM_MPLL_SEL_MASK 0x00000003L +#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL_MASK 0x00000004L +#define MCLK_MISC__MCLK_FROM_SPLL_DIV_SEL 0x00000004L +#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL_MASK 0x00000008L +#define MCLK_MISC__ENABLE_SCLK_FROM_MPLL 0x00000008L +#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN_MASK 0x00000010L +#define MCLK_MISC__MPLL_MODEA_MODEC_HW_SEL_EN 0x00000010L +#define MCLK_MISC__DLL_READY_LAT_MASK 0x00000100L +#define MCLK_MISC__DLL_READY_LAT 0x00000100L +#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT_MASK 0x00001000L +#define MCLK_MISC__MC_MCLK_MAX_DYN_STOP_LAT 0x00001000L +#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT_MASK 0x00002000L +#define MCLK_MISC__IO_MCLK_MAX_DYN_STOP_LAT 0x00002000L +#define MCLK_MISC__MC_MCLK_DYN_ENABLE_MASK 0x00004000L +#define MCLK_MISC__MC_MCLK_DYN_ENABLE 0x00004000L +#define MCLK_MISC__IO_MCLK_DYN_ENABLE_MASK 0x00008000L +#define MCLK_MISC__IO_MCLK_DYN_ENABLE 0x00008000L +#define MCLK_MISC__CGM_CLK_TO_OUTPIN_MASK 0x00010000L +#define MCLK_MISC__CGM_CLK_TO_OUTPIN 0x00010000L +#define MCLK_MISC__CLK_OR_COUNT_SEL_MASK 0x00020000L +#define MCLK_MISC__CLK_OR_COUNT_SEL 0x00020000L +#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND_MASK 0x00040000L +#define MCLK_MISC__EN_MCLK_TRISTATE_IN_SUSPEND 0x00040000L +#define MCLK_MISC__CGM_SPARE_RD_MASK 0x00300000L +#define MCLK_MISC__CGM_SPARE_A_RD_MASK 0x00c00000L +#define MCLK_MISC__TCLK_TO_YCLKB_EN_MASK 0x01000000L +#define MCLK_MISC__TCLK_TO_YCLKB_EN 0x01000000L +#define MCLK_MISC__CGM_SPARE_A_MASK 0x0e000000L + +/* VCLK_ECP_CNTL */ +#define VCLK_ECP_CNTL__VCLK_SRC_SEL_MASK 0x00000003L +#define VCLK_ECP_CNTL__VCLK_INVERT 0x00000010L +#define VCLK_ECP_CNTL__PIXCLK_SRC_INVERT 0x00000020L +#define VCLK_ECP_CNTL__PIXCLK_ALWAYS_ONb 0x00000040L +#define VCLK_ECP_CNTL__PIXCLK_DAC_ALWAYS_ONb 0x00000080L +#define VCLK_ECP_CNTL__ECP_DIV_MASK 0x00000300L +#define VCLK_ECP_CNTL__ECP_FORCE_ON 0x00040000L +#define VCLK_ECP_CNTL__SUBCLK_FORCE_ON 0x00080000L #define VCLK_ECP_CNTL__R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) -// PLL_PWRMGT_CNTL -#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L -#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L -#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L -#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L -#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L -#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L -#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L -#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L -#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L -#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L -#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L -#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L -#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L -#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L -#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L -#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L -#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L -#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L -#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L -#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L -#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L -#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L -#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L -#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L -#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L -#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L -#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L -#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L -#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L -#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L -#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L -#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L - -// CLK_PWRMGT_CNTL -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L -#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L -#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L -#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L -#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L -#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L -#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L -#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L -#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L -#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L -#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L -#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L -#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L -#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L -#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L -#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L -#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L -#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L -#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L -#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L -#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L -#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L -#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L -#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L -#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L -#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L -#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L -#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L -#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L -#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L -#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L - -// BUS_CNTL1 -#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L -#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L -#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L -#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L -#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L -#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L -#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L -#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L -#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L -#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L -#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L -#define BUS_CNTL1__AGPCLK_VALID 0x80000000L - -// BUS_CNTL1 -#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 -#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 -#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 -#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 -#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 -#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 -#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 -#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a -#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b -#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a -#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c -#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f - -// CRTC_OFFSET_CNTL -#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL -#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L -#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L -#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L +/* PLL_PWRMGT_CNTL */ +#define PLL_PWRMGT_CNTL__MPLL_TURNOFF_MASK 0x00000001L +#define PLL_PWRMGT_CNTL__MPLL_TURNOFF 0x00000001L +#define PLL_PWRMGT_CNTL__SPLL_TURNOFF_MASK 0x00000002L +#define PLL_PWRMGT_CNTL__SPLL_TURNOFF 0x00000002L +#define PLL_PWRMGT_CNTL__PPLL_TURNOFF_MASK 0x00000004L +#define PLL_PWRMGT_CNTL__PPLL_TURNOFF 0x00000004L +#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF_MASK 0x00000008L +#define PLL_PWRMGT_CNTL__P2PLL_TURNOFF 0x00000008L +#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF_MASK 0x00000010L +#define PLL_PWRMGT_CNTL__TVPLL_TURNOFF 0x00000010L +#define PLL_PWRMGT_CNTL__AGPCLK_DYN_STOP_LAT_MASK 0x000001e0L +#define PLL_PWRMGT_CNTL__APM_POWER_STATE_MASK 0x00000600L +#define PLL_PWRMGT_CNTL__APM_PWRSTATE_RD_MASK 0x00001800L +#define PLL_PWRMGT_CNTL__PM_MODE_SEL_MASK 0x00002000L +#define PLL_PWRMGT_CNTL__PM_MODE_SEL 0x00002000L +#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND_MASK 0x00004000L +#define PLL_PWRMGT_CNTL__EN_PWRSEQ_DONE_COND 0x00004000L +#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND_MASK 0x00008000L +#define PLL_PWRMGT_CNTL__EN_DISP_PARKED_COND 0x00008000L +#define PLL_PWRMGT_CNTL__MOBILE_SU_MASK 0x00010000L +#define PLL_PWRMGT_CNTL__MOBILE_SU 0x00010000L +#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK_MASK 0x00020000L +#define PLL_PWRMGT_CNTL__SU_SCLK_USE_BCLK 0x00020000L +#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK_MASK 0x00040000L +#define PLL_PWRMGT_CNTL__SU_MCLK_USE_BCLK 0x00040000L +#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE_MASK 0x00080000L +#define PLL_PWRMGT_CNTL__SU_SUSTAIN_DISABLE 0x00080000L +#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE_MASK 0x00100000L +#define PLL_PWRMGT_CNTL__TCL_BYPASS_DISABLE 0x00100000L +#define PLL_PWRMGT_CNTL__TCL_CLOCK_CTIVE_RD_MASK 0x00200000L +#define PLL_PWRMGT_CNTL__TCL_CLOCK_ACTIVE_RD 0x00200000L +#define PLL_PWRMGT_CNTL__CG_NO2_DEBUG_MASK 0xff000000L + +/* CLK_PWRMGT_CNTL */ +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF_MASK 0x00000001L +#define CLK_PWRMGT_CNTL__MPLL_PWRMGT_OFF 0x00000001L +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF_MASK 0x00000002L +#define CLK_PWRMGT_CNTL__SPLL_PWRMGT_OFF 0x00000002L +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF_MASK 0x00000004L +#define CLK_PWRMGT_CNTL__PPLL_PWRMGT_OFF 0x00000004L +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF_MASK 0x00000008L +#define CLK_PWRMGT_CNTL__P2PLL_PWRMGT_OFF 0x00000008L +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF_MASK 0x00000010L +#define CLK_PWRMGT_CNTL__MCLK_TURNOFF 0x00000010L +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF_MASK 0x00000020L +#define CLK_PWRMGT_CNTL__SCLK_TURNOFF 0x00000020L +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF_MASK 0x00000040L +#define CLK_PWRMGT_CNTL__PCLK_TURNOFF 0x00000040L +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF_MASK 0x00000080L +#define CLK_PWRMGT_CNTL__P2CLK_TURNOFF 0x00000080L +#define CLK_PWRMGT_CNTL__MC_CH_MODE_MASK 0x00000100L +#define CLK_PWRMGT_CNTL__MC_CH_MODE 0x00000100L +#define CLK_PWRMGT_CNTL__TEST_MODE_MASK 0x00000200L +#define CLK_PWRMGT_CNTL__TEST_MODE 0x00000200L +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN_MASK 0x00000400L +#define CLK_PWRMGT_CNTL__GLOBAL_PMAN_EN 0x00000400L +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE_MASK 0x00001000L +#define CLK_PWRMGT_CNTL__ENGINE_DYNCLK_MODE 0x00001000L +#define CLK_PWRMGT_CNTL__ACTIVE_HILO_LAT_MASK 0x00006000L +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT_MASK 0x00008000L +#define CLK_PWRMGT_CNTL__DISP_DYN_STOP_LAT 0x00008000L +#define CLK_PWRMGT_CNTL__MC_BUSY_MASK 0x00010000L +#define CLK_PWRMGT_CNTL__MC_BUSY 0x00010000L +#define CLK_PWRMGT_CNTL__MC_INT_CNTL_MASK 0x00020000L +#define CLK_PWRMGT_CNTL__MC_INT_CNTL 0x00020000L +#define CLK_PWRMGT_CNTL__MC_SWITCH_MASK 0x00040000L +#define CLK_PWRMGT_CNTL__MC_SWITCH 0x00040000L +#define CLK_PWRMGT_CNTL__DLL_READY_MASK 0x00080000L +#define CLK_PWRMGT_CNTL__DLL_READY 0x00080000L +#define CLK_PWRMGT_CNTL__DISP_PM_MASK 0x00100000L +#define CLK_PWRMGT_CNTL__DISP_PM 0x00100000L +#define CLK_PWRMGT_CNTL__DYN_STOP_MODE_MASK 0x00e00000L +#define CLK_PWRMGT_CNTL__CG_NO1_DEBUG_MASK 0x3f000000L +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF_MASK 0x40000000L +#define CLK_PWRMGT_CNTL__TVPLL_PWRMGT_OFF 0x40000000L +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF_MASK 0x80000000L +#define CLK_PWRMGT_CNTL__TVCLK_TURNOFF 0x80000000L + +/* BUS_CNTL1 */ +#define BUS_CNTL1__PMI_IO_DISABLE_MASK 0x00000001L +#define BUS_CNTL1__PMI_IO_DISABLE 0x00000001L +#define BUS_CNTL1__PMI_MEM_DISABLE_MASK 0x00000002L +#define BUS_CNTL1__PMI_MEM_DISABLE 0x00000002L +#define BUS_CNTL1__PMI_BM_DISABLE_MASK 0x00000004L +#define BUS_CNTL1__PMI_BM_DISABLE 0x00000004L +#define BUS_CNTL1__PMI_INT_DISABLE_MASK 0x00000008L +#define BUS_CNTL1__PMI_INT_DISABLE 0x00000008L +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE_MASK 0x00000020L +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE 0x00000020L +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS_MASK 0x00000100L +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS 0x00000100L +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS_MASK 0x00000200L +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS 0x00000200L +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS_MASK 0x00000400L +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS 0x00000400L +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS_MASK 0x00000800L +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS 0x00000800L +#define BUS_CNTL1__MOBILE_PLATFORM_SEL_MASK 0x0c000000L +#define BUS_CNTL1__SEND_SBA_LATENCY_MASK 0x70000000L +#define BUS_CNTL1__AGPCLK_VALID_MASK 0x80000000L +#define BUS_CNTL1__AGPCLK_VALID 0x80000000L + +/* BUS_CNTL1 */ +#define BUS_CNTL1__PMI_IO_DISABLE__SHIFT 0x00000000 +#define BUS_CNTL1__PMI_MEM_DISABLE__SHIFT 0x00000001 +#define BUS_CNTL1__PMI_BM_DISABLE__SHIFT 0x00000002 +#define BUS_CNTL1__PMI_INT_DISABLE__SHIFT 0x00000003 +#define BUS_CNTL1__BUS2_IMMEDIATE_PMI_DISABLE__SHIFT 0x00000005 +#define BUS_CNTL1__BUS2_VGA_REG_COHERENCY_DIS__SHIFT 0x00000008 +#define BUS_CNTL1__BUS2_VGA_MEM_COHERENCY_DIS__SHIFT 0x00000009 +#define BUS_CNTL1__BUS2_HDP_REG_COHERENCY_DIS__SHIFT 0x0000000a +#define BUS_CNTL1__BUS2_GUI_INITIATOR_COHERENCY_DIS__SHIFT 0x0000000b +#define BUS_CNTL1__MOBILE_PLATFORM_SEL__SHIFT 0x0000001a +#define BUS_CNTL1__SEND_SBA_LATENCY__SHIFT 0x0000001c +#define BUS_CNTL1__AGPCLK_VALID__SHIFT 0x0000001f + +/* CRTC_OFFSET_CNTL */ +#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_MASK 0x0000000fL +#define CRTC_OFFSET_CNTL__CRTC_TILE_LINE_RIGHT_MASK 0x000000f0L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT_MASK 0x00004000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_RIGHT 0x00004000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN_MASK 0x00008000L +#define CRTC_OFFSET_CNTL__CRTC_TILE_EN 0x00008000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL_MASK 0x00010000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_FLIP_CNTL 0x00010000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN_MASK 0x00020000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_OFFSET_EN 0x00020000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_EN_MASK 0x000c0000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN_MASK 0x00100000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_OUT_EN 0x00100000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC_MASK 0x00200000L +#define CRTC_OFFSET_CNTL__CRTC_STEREO_SYNC 0x00200000L #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN_MASK 0x10000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_LEFT_EN 0x10000000L #define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN_MASK 0x20000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L -#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L -#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L - -// CRTC_GEN_CNTL -#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L -#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L -#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L -#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L -#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L -#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L -#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L -#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L -#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L -#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L -#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L -#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L -#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L -#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L -#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L -#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L -#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L -#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L -#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L - -// CRTC2_GEN_CNTL -#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L -#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L -#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L -#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L -#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L -#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L -#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L -#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L -#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L -#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L -#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L -#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L -#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L -#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L -#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L -#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L -#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L -#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L -#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L -#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L -#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L -#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L - -// AGP_CNTL -#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL -#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L -#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L -#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L -#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L -#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L -#define AGP_CNTL__EN_2X_STBB 0x00000400L -#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L -#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L -#define AGP_CNTL__SBA_DIS_MASK 0x00001000L -#define AGP_CNTL__SBA_DIS 0x00001000L -#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L -#define AGP_CNTL__AGP_REV_ID 0x00002000L -#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L -#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L -#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L -#define AGP_CNTL__FORCE_INT_VREF 0x00010000L -#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L -#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L -#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L -#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L -#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L -#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L -#define AGP_CNTL__EN_RBFCALM 0x00800000L -#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L -#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L -#define AGP_CNTL__DIS_RBF_MASK 0x02000000L -#define AGP_CNTL__DIS_RBF 0x02000000L -#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L -#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L -#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L -#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L - -// AGP_CNTL -#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 -#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 -#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 -#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a -#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b -#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c -#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d -#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e -#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f -#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 -#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 -#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 -#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 -#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 -#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 -#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 -#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 -#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 -#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a -#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b -#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e - -// DISP_MISC_CNTL -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L -#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L -#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L -#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L -#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L -#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L -#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L -#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L -#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L -#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L -#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L -#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L -#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L -#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L -#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L -#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L -#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L -#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L - -// DISP_PWR_MAN -#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L -#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L -#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L -#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L -#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L -#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L -#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L -#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L -#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L -#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L -#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L -#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L -#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L -#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L -#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L -#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L -#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L -#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L -#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L -#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L -#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L -#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L -#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L -#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L -#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L -#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L -#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L - -// MC_IND_INDEX -#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL -#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L -#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L - -// MC_IND_DATA -#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL - -// MC_CHP_IO_CNTL_A1 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a -#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c -#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e -#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 -#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f - -// MC_CHP_IO_CNTL_B1 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a -#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c -#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e -#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 -#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f - -// MC_CHP_IO_CNTL_A1 -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L -#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L -#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L -#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L -#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L -#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L -#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L -#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L -#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L - -// MC_CHP_IO_CNTL_B1 -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L -#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L -#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L -#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L -#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L -#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L -#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L -#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L -#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L - -// MEM_SDRAM_MODE_REG -#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL -#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L -#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L - -// MEM_SDRAM_MODE_REG -#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 -#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 -#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 -#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 -#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a -#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b -#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c -#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d -#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e -#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f - -// MEM_REFRESH_CNTL -#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL -#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L -#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L -#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L -#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L -#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L -#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L -#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L -#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L -#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L -#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L -#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L -#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L -#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L -#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L -#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L -#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L -#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L -#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L -#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L -#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L -#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L -#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L - -// MC_STATUS -#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L -#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L -#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L -#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L -#define MC_STATUS__MC_IDLE_MASK 0x00000004L -#define MC_STATUS__MC_IDLE 0x00000004L -#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L -#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L -#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L -#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L -#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L -#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L -#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L -#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L -#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L -#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L - -// MDLL_CKO -#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L -#define MDLL_CKO__MCKOA_SLEEP 0x00000001L -#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L -#define MDLL_CKO__MCKOA_RESET 0x00000002L -#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL -#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L -#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L -#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L -#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L -#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L -#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L -#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L -#define MDLL_CKO__MCKOB_SLEEP 0x00010000L -#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L -#define MDLL_CKO__MCKOB_RESET 0x00020000L -#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L -#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L -#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L -#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L -#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L -#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L -#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L - -// MDLL_RDCKA -#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L -#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L -#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L -#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L -#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL -#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L -#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L -#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L -#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L -#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L -#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L -#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L -#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L -#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L -#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L -#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L -#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L -#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L -#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L -#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L -#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L -#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L -#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L -#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L -#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L -#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L - -// MDLL_RDCKB -#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L -#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L -#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L -#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L -#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL -#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L -#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L -#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L -#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L -#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L -#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L -#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L -#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L -#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L -#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L -#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L -#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L -#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L -#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L -#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L -#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L -#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L -#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L -#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L -#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L -#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L - -#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L -#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L -#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L -#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L -#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L -#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L -#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L -#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L - -#define pllCLK_PIN_CNTL 0x0001 -#define pllPPLL_CNTL 0x0002 -#define pllPPLL_REF_DIV 0x0003 -#define pllPPLL_DIV_0 0x0004 -#define pllPPLL_DIV_1 0x0005 -#define pllPPLL_DIV_2 0x0006 -#define pllPPLL_DIV_3 0x0007 -#define pllVCLK_ECP_CNTL 0x0008 -#define pllHTOTAL_CNTL 0x0009 -#define pllM_SPLL_REF_FB_DIV 0x000A -#define pllAGP_PLL_CNTL 0x000B -#define pllSPLL_CNTL 0x000C -#define pllSCLK_CNTL 0x000D -#define pllMPLL_CNTL 0x000E -#define pllMDLL_CKO 0x000F -#define pllMDLL_RDCKA 0x0010 -#define pllMDLL_RDCKB 0x0011 -#define pllMCLK_CNTL 0x0012 -#define pllPLL_TEST_CNTL 0x0013 -#define pllCLK_PWRMGT_CNTL 0x0014 -#define pllPLL_PWRMGT_CNTL 0x0015 -#define pllCG_TEST_MACRO_RW_WRITE 0x0016 -#define pllCG_TEST_MACRO_RW_READ 0x0017 -#define pllCG_TEST_MACRO_RW_DATA 0x0018 -#define pllCG_TEST_MACRO_RW_CNTL 0x0019 -#define pllDISP_TEST_MACRO_RW_WRITE 0x001A -#define pllDISP_TEST_MACRO_RW_READ 0x001B -#define pllDISP_TEST_MACRO_RW_DATA 0x001C -#define pllDISP_TEST_MACRO_RW_CNTL 0x001D -#define pllSCLK_CNTL2 0x001E -#define pllMCLK_MISC 0x001F -#define pllTV_PLL_FINE_CNTL 0x0020 -#define pllTV_PLL_CNTL 0x0021 -#define pllTV_PLL_CNTL1 0x0022 -#define pllTV_DTO_INCREMENTS 0x0023 -#define pllSPLL_AUX_CNTL 0x0024 -#define pllMPLL_AUX_CNTL 0x0025 -#define pllP2PLL_CNTL 0x002A -#define pllP2PLL_REF_DIV 0x002B -#define pllP2PLL_DIV_0 0x002C -#define pllPIXCLKS_CNTL 0x002D -#define pllHTOTAL2_CNTL 0x002E -#define pllSSPLL_CNTL 0x0030 -#define pllSSPLL_REF_DIV 0x0031 -#define pllSSPLL_DIV_0 0x0032 -#define pllSS_INT_CNTL 0x0033 -#define pllSS_TST_CNTL 0x0034 -#define pllSCLK_MORE_CNTL 0x0035 - -#define ixMC_PERF_CNTL 0x0000 -#define ixMC_PERF_SEL 0x0001 -#define ixMC_PERF_REGION_0 0x0002 -#define ixMC_PERF_REGION_1 0x0003 -#define ixMC_PERF_COUNT_0 0x0004 -#define ixMC_PERF_COUNT_1 0x0005 -#define ixMC_PERF_COUNT_2 0x0006 -#define ixMC_PERF_COUNT_3 0x0007 -#define ixMC_PERF_COUNT_MEMCH_A 0x0008 -#define ixMC_PERF_COUNT_MEMCH_B 0x0009 -#define ixMC_IMP_CNTL 0x000A -#define ixMC_CHP_IO_CNTL_A0 0x000B -#define ixMC_CHP_IO_CNTL_A1 0x000C -#define ixMC_CHP_IO_CNTL_B0 0x000D -#define ixMC_CHP_IO_CNTL_B1 0x000E -#define ixMC_IMP_CNTL_0 0x000F -#define ixTC_MISMATCH_1 0x0010 -#define ixTC_MISMATCH_2 0x0011 -#define ixMC_BIST_CTRL 0x0012 -#define ixREG_COLLAR_WRITE 0x0013 -#define ixREG_COLLAR_READ 0x0014 -#define ixR300_MC_IMP_CNTL 0x0018 -#define ixR300_MC_CHP_IO_CNTL_A0 0x0019 -#define ixR300_MC_CHP_IO_CNTL_A1 0x001a -#define ixR300_MC_CHP_IO_CNTL_B0 0x001b -#define ixR300_MC_CHP_IO_CNTL_B1 0x001c -#define ixR300_MC_CHP_IO_CNTL_C0 0x001d -#define ixR300_MC_CHP_IO_CNTL_C1 0x001e -#define ixR300_MC_CHP_IO_CNTL_D0 0x001f -#define ixR300_MC_CHP_IO_CNTL_D1 0x0020 -#define ixR300_MC_IMP_CNTL_0 0x0021 -#define ixR300_MC_ELPIDA_CNTL 0x0022 -#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023 -#define ixR300_MC_READ_CNTL_CD 0x0024 -#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025 -#define ixR300_MC_DEBUG_CNTL 0x0026 -#define ixR300_MC_BIST_CNTL_0 0x0028 -#define ixR300_MC_BIST_CNTL_1 0x0029 -#define ixR300_MC_BIST_CNTL_2 0x002a -#define ixR300_MC_BIST_CNTL_3 0x002b -#define ixR300_MC_BIST_CNTL_4 0x002c -#define ixR300_MC_BIST_CNTL_5 0x002d -#define ixR300_MC_IMP_STATUS 0x002e -#define ixR300_MC_DLL_CNTL 0x002f -#define NB_TOM 0x15C - +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_RIGHT_EN 0x20000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET_MASK 0x40000000L +#define CRTC_OFFSET_CNTL__CRTC_GUI_TRIG_OFFSET 0x40000000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK_MASK 0x80000000L +#define CRTC_OFFSET_CNTL__CRTC_OFFSET_LOCK 0x80000000L + +/* CRTC_GEN_CNTL */ +#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN_MASK 0x00000001L +#define CRTC_GEN_CNTL__CRTC_DBL_SCAN_EN 0x00000001L +#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN_MASK 0x00000002L +#define CRTC_GEN_CNTL__CRTC_INTERLACE_EN 0x00000002L +#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN_MASK 0x00000010L +#define CRTC_GEN_CNTL__CRTC_C_SYNC_EN 0x00000010L +#define CRTC_GEN_CNTL__CRTC_PIX_WIDTH_MASK 0x00000f00L +#define CRTC_GEN_CNTL__CRTC_ICON_EN_MASK 0x00008000L +#define CRTC_GEN_CNTL__CRTC_ICON_EN 0x00008000L +#define CRTC_GEN_CNTL__CRTC_CUR_EN_MASK 0x00010000L +#define CRTC_GEN_CNTL__CRTC_CUR_EN 0x00010000L +#define CRTC_GEN_CNTL__CRTC_VSTAT_MODE_MASK 0x00060000L +#define CRTC_GEN_CNTL__CRTC_CUR_MODE_MASK 0x00700000L +#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN_MASK 0x01000000L +#define CRTC_GEN_CNTL__CRTC_EXT_DISP_EN 0x01000000L +#define CRTC_GEN_CNTL__CRTC_EN_MASK 0x02000000L +#define CRTC_GEN_CNTL__CRTC_EN 0x02000000L +#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B_MASK 0x04000000L +#define CRTC_GEN_CNTL__CRTC_DISP_REQ_EN_B 0x04000000L + +/* CRTC2_GEN_CNTL */ +#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN_MASK 0x00000001L +#define CRTC2_GEN_CNTL__CRTC2_DBL_SCAN_EN 0x00000001L +#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN_MASK 0x00000002L +#define CRTC2_GEN_CNTL__CRTC2_INTERLACE_EN 0x00000002L +#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE_MASK 0x00000010L +#define CRTC2_GEN_CNTL__CRTC2_SYNC_TRISTATE 0x00000010L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE_MASK 0x00000020L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_TRISTATE 0x00000020L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE_MASK 0x00000040L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_TRISTATE 0x00000040L +#define CRTC2_GEN_CNTL__CRT2_ON_MASK 0x00000080L +#define CRTC2_GEN_CNTL__CRT2_ON 0x00000080L +#define CRTC2_GEN_CNTL__CRTC2_PIX_WIDTH_MASK 0x00000f00L +#define CRTC2_GEN_CNTL__CRTC2_ICON_EN_MASK 0x00008000L +#define CRTC2_GEN_CNTL__CRTC2_ICON_EN 0x00008000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_EN_MASK 0x00010000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_EN 0x00010000L +#define CRTC2_GEN_CNTL__CRTC2_CUR_MODE_MASK 0x00700000L +#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS_MASK 0x00800000L +#define CRTC2_GEN_CNTL__CRTC2_DISPLAY_DIS 0x00800000L +#define CRTC2_GEN_CNTL__CRTC2_EN_MASK 0x02000000L +#define CRTC2_GEN_CNTL__CRTC2_EN 0x02000000L +#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B_MASK 0x04000000L +#define CRTC2_GEN_CNTL__CRTC2_DISP_REQ_EN_B 0x04000000L +#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN_MASK 0x08000000L +#define CRTC2_GEN_CNTL__CRTC2_C_SYNC_EN 0x08000000L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS_MASK 0x10000000L +#define CRTC2_GEN_CNTL__CRTC2_HSYNC_DIS 0x10000000L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS_MASK 0x20000000L +#define CRTC2_GEN_CNTL__CRTC2_VSYNC_DIS 0x20000000L + +/* AGP_CNTL */ +#define AGP_CNTL__MAX_IDLE_CLK_MASK 0x000000ffL +#define AGP_CNTL__HOLD_RD_FIFO_MASK 0x00000100L +#define AGP_CNTL__HOLD_RD_FIFO 0x00000100L +#define AGP_CNTL__HOLD_RQ_FIFO_MASK 0x00000200L +#define AGP_CNTL__HOLD_RQ_FIFO 0x00000200L +#define AGP_CNTL__EN_2X_STBB_MASK 0x00000400L +#define AGP_CNTL__EN_2X_STBB 0x00000400L +#define AGP_CNTL__FORCE_FULL_SBA_MASK 0x00000800L +#define AGP_CNTL__FORCE_FULL_SBA 0x00000800L +#define AGP_CNTL__SBA_DIS_MASK 0x00001000L +#define AGP_CNTL__SBA_DIS 0x00001000L +#define AGP_CNTL__AGP_REV_ID_MASK 0x00002000L +#define AGP_CNTL__AGP_REV_ID 0x00002000L +#define AGP_CNTL__REG_CRIPPLE_AGP4X_MASK 0x00004000L +#define AGP_CNTL__REG_CRIPPLE_AGP4X 0x00004000L +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X_MASK 0x00008000L +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X 0x00008000L +#define AGP_CNTL__FORCE_INT_VREF_MASK 0x00010000L +#define AGP_CNTL__FORCE_INT_VREF 0x00010000L +#define AGP_CNTL__PENDING_SLOTS_VAL_MASK 0x00060000L +#define AGP_CNTL__PENDING_SLOTS_SEL_MASK 0x00080000L +#define AGP_CNTL__PENDING_SLOTS_SEL 0x00080000L +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X_MASK 0x00100000L +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X 0x00100000L +#define AGP_CNTL__DIS_QUEUED_GNT_FIX_MASK 0x00200000L +#define AGP_CNTL__DIS_QUEUED_GNT_FIX 0x00200000L +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET_MASK 0x00400000L +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET 0x00400000L +#define AGP_CNTL__EN_RBFCALM_MASK 0x00800000L +#define AGP_CNTL__EN_RBFCALM 0x00800000L +#define AGP_CNTL__FORCE_EXT_VREF_MASK 0x01000000L +#define AGP_CNTL__FORCE_EXT_VREF 0x01000000L +#define AGP_CNTL__DIS_RBF_MASK 0x02000000L +#define AGP_CNTL__DIS_RBF 0x02000000L +#define AGP_CNTL__DELAY_FIRST_SBA_EN_MASK 0x04000000L +#define AGP_CNTL__DELAY_FIRST_SBA_EN 0x04000000L +#define AGP_CNTL__DELAY_FIRST_SBA_VAL_MASK 0x38000000L +#define AGP_CNTL__AGP_MISC_MASK 0xc0000000L + +/* AGP_CNTL */ +#define AGP_CNTL__MAX_IDLE_CLK__SHIFT 0x00000000 +#define AGP_CNTL__HOLD_RD_FIFO__SHIFT 0x00000008 +#define AGP_CNTL__HOLD_RQ_FIFO__SHIFT 0x00000009 +#define AGP_CNTL__EN_2X_STBB__SHIFT 0x0000000a +#define AGP_CNTL__FORCE_FULL_SBA__SHIFT 0x0000000b +#define AGP_CNTL__SBA_DIS__SHIFT 0x0000000c +#define AGP_CNTL__AGP_REV_ID__SHIFT 0x0000000d +#define AGP_CNTL__REG_CRIPPLE_AGP4X__SHIFT 0x0000000e +#define AGP_CNTL__REG_CRIPPLE_AGP2X4X__SHIFT 0x0000000f +#define AGP_CNTL__FORCE_INT_VREF__SHIFT 0x00000010 +#define AGP_CNTL__PENDING_SLOTS_VAL__SHIFT 0x00000011 +#define AGP_CNTL__PENDING_SLOTS_SEL__SHIFT 0x00000013 +#define AGP_CNTL__EN_EXTENDED_AD_STB_2X__SHIFT 0x00000014 +#define AGP_CNTL__DIS_QUEUED_GNT_FIX__SHIFT 0x00000015 +#define AGP_CNTL__EN_RDATA2X4X_MULTIRESET__SHIFT 0x00000016 +#define AGP_CNTL__EN_RBFCALM__SHIFT 0x00000017 +#define AGP_CNTL__FORCE_EXT_VREF__SHIFT 0x00000018 +#define AGP_CNTL__DIS_RBF__SHIFT 0x00000019 +#define AGP_CNTL__DELAY_FIRST_SBA_EN__SHIFT 0x0000001a +#define AGP_CNTL__DELAY_FIRST_SBA_VAL__SHIFT 0x0000001b +#define AGP_CNTL__AGP_MISC__SHIFT 0x0000001e + +/* DISP_MISC_CNTL */ +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP_MASK 0x00000001L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_PP 0x00000001L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP_MASK 0x00000002L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_PP 0x00000002L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP_MASK 0x00000004L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_PP 0x00000004L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK_MASK 0x00000010L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH_SCLK 0x00000010L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK_MASK 0x00000020L +#define DISP_MISC_CNTL__SOFT_RESET_SUBPIC_SCLK 0x00000020L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK_MASK 0x00000040L +#define DISP_MISC_CNTL__SOFT_RESET_OV0_SCLK 0x00000040L +#define DISP_MISC_CNTL__SYNC_STRENGTH_MASK 0x00000300L +#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN_MASK 0x00000400L +#define DISP_MISC_CNTL__SYNC_PAD_FLOP_EN 0x00000400L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP_MASK 0x00001000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_PP 0x00001000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK_MASK 0x00008000L +#define DISP_MISC_CNTL__SOFT_RESET_GRPH2_SCLK 0x00008000L +#define DISP_MISC_CNTL__SOFT_RESET_LVDS_MASK 0x00010000L +#define DISP_MISC_CNTL__SOFT_RESET_LVDS 0x00010000L +#define DISP_MISC_CNTL__SOFT_RESET_TMDS_MASK 0x00020000L +#define DISP_MISC_CNTL__SOFT_RESET_TMDS 0x00020000L +#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS_MASK 0x00040000L +#define DISP_MISC_CNTL__SOFT_RESET_DIG_TMDS 0x00040000L +#define DISP_MISC_CNTL__SOFT_RESET_TV_MASK 0x00080000L +#define DISP_MISC_CNTL__SOFT_RESET_TV 0x00080000L +#define DISP_MISC_CNTL__PALETTE2_MEM_RD_MARGIN_MASK 0x00f00000L +#define DISP_MISC_CNTL__PALETTE_MEM_RD_MARGIN_MASK 0x0f000000L +#define DISP_MISC_CNTL__RMX_BUF_MEM_RD_MARGIN_MASK 0xf0000000L + +/* DISP_PWR_MAN */ +#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN_MASK 0x00000001L +#define DISP_PWR_MAN__DISP_PWR_MAN_D3_CRTC_EN 0x00000001L +#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN_MASK 0x00000010L +#define DISP_PWR_MAN__DISP2_PWR_MAN_D3_CRTC2_EN 0x00000010L +#define DISP_PWR_MAN__DISP_PWR_MAN_DPMS_MASK 0x00000300L +#define DISP_PWR_MAN__DISP_D3_RST_MASK 0x00010000L +#define DISP_PWR_MAN__DISP_D3_RST 0x00010000L +#define DISP_PWR_MAN__DISP_D3_REG_RST_MASK 0x00020000L +#define DISP_PWR_MAN__DISP_D3_REG_RST 0x00020000L +#define DISP_PWR_MAN__DISP_D3_GRPH_RST_MASK 0x00040000L +#define DISP_PWR_MAN__DISP_D3_GRPH_RST 0x00040000L +#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST_MASK 0x00080000L +#define DISP_PWR_MAN__DISP_D3_SUBPIC_RST 0x00080000L +#define DISP_PWR_MAN__DISP_D3_OV0_RST_MASK 0x00100000L +#define DISP_PWR_MAN__DISP_D3_OV0_RST 0x00100000L +#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST_MASK 0x00200000L +#define DISP_PWR_MAN__DISP_D1D2_GRPH_RST 0x00200000L +#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST_MASK 0x00400000L +#define DISP_PWR_MAN__DISP_D1D2_SUBPIC_RST 0x00400000L +#define DISP_PWR_MAN__DISP_D1D2_OV0_RST_MASK 0x00800000L +#define DISP_PWR_MAN__DISP_D1D2_OV0_RST 0x00800000L +#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST_MASK 0x01000000L +#define DISP_PWR_MAN__DIG_TMDS_ENABLE_RST 0x01000000L +#define DISP_PWR_MAN__TV_ENABLE_RST_MASK 0x02000000L +#define DISP_PWR_MAN__TV_ENABLE_RST 0x02000000L +#define DISP_PWR_MAN__AUTO_PWRUP_EN_MASK 0x04000000L +#define DISP_PWR_MAN__AUTO_PWRUP_EN 0x04000000L + +/* MC_IND_INDEX */ +#define MC_IND_INDEX__MC_IND_ADDR_MASK 0x0000001fL +#define MC_IND_INDEX__MC_IND_WR_EN_MASK 0x00000100L +#define MC_IND_INDEX__MC_IND_WR_EN 0x00000100L + +/* MC_IND_DATA */ +#define MC_IND_DATA__MC_IND_DATA_MASK 0xffffffffL + +/* MC_CHP_IO_CNTL_A1 */ +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA__SHIFT 0x00000000 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA__SHIFT 0x00000001 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA__SHIFT 0x00000002 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA__SHIFT 0x00000003 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA__SHIFT 0x00000004 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA__SHIFT 0x00000005 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA__SHIFT 0x00000006 +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA__SHIFT 0x00000007 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA__SHIFT 0x00000008 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA__SHIFT 0x00000009 +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA__SHIFT 0x0000000a +#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA__SHIFT 0x0000000c +#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA__SHIFT 0x0000000e +#define MC_CHP_IO_CNTL_A1__MEM_REC_AA__SHIFT 0x00000010 +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA__SHIFT 0x00000012 +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA__SHIFT 0x00000014 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA__SHIFT 0x00000016 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA__SHIFT 0x00000017 +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA__SHIFT 0x00000018 +#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA__SHIFT 0x0000001a +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA__SHIFT 0x0000001c +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A__SHIFT 0x0000001e +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A__SHIFT 0x0000001f + +/* MC_CHP_IO_CNTL_B1 */ +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB__SHIFT 0x00000000 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB__SHIFT 0x00000001 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB__SHIFT 0x00000002 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB__SHIFT 0x00000003 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB__SHIFT 0x00000004 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB__SHIFT 0x00000005 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB__SHIFT 0x00000006 +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB__SHIFT 0x00000007 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB__SHIFT 0x00000008 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB__SHIFT 0x00000009 +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB__SHIFT 0x0000000a +#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB__SHIFT 0x0000000c +#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB__SHIFT 0x0000000e +#define MC_CHP_IO_CNTL_B1__MEM_REC_AB__SHIFT 0x00000010 +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB__SHIFT 0x00000012 +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB__SHIFT 0x00000014 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB__SHIFT 0x00000016 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB__SHIFT 0x00000017 +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB__SHIFT 0x00000018 +#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB__SHIFT 0x0000001a +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB__SHIFT 0x0000001c +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B__SHIFT 0x0000001e +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B__SHIFT 0x0000001f + +/* MC_CHP_IO_CNTL_A1 */ +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA_MASK 0x00000001L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_CKA 0x00000001L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA_MASK 0x00000002L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_AA 0x00000002L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA_MASK 0x00000004L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQMA 0x00000004L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA_MASK 0x00000008L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWN_DQSA 0x00000008L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA_MASK 0x00000010L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_CKA 0x00000010L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA_MASK 0x00000020L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_AA 0x00000020L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA_MASK 0x00000040L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQMA 0x00000040L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA_MASK 0x00000080L +#define MC_CHP_IO_CNTL_A1__MEM_SLEWP_DQSA 0x00000080L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA_MASK 0x00000100L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_AA 0x00000100L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA_MASK 0x00000200L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQMA 0x00000200L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA_MASK 0x00000400L +#define MC_CHP_IO_CNTL_A1__MEM_PREAMP_DQSA 0x00000400L +#define MC_CHP_IO_CNTL_A1__MEM_IO_MODEA_MASK 0x00003000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_CKA_MASK 0x0000c000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_AA_MASK 0x00030000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQMA_MASK 0x000c0000L +#define MC_CHP_IO_CNTL_A1__MEM_REC_DQSA_MASK 0x00300000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA_MASK 0x00400000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_PHASEA 0x00400000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA_MASK 0x00800000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_CENTERA 0x00800000L +#define MC_CHP_IO_CNTL_A1__MEM_SYNC_ENA_MASK 0x03000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_SELA_MASK 0x0c000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA_MASK 0x10000000L +#define MC_CHP_IO_CNTL_A1__MEM_CLK_INVA 0x10000000L +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A_MASK 0x40000000L +#define MC_CHP_IO_CNTL_A1__MEM_DATA_ENIMP_A 0x40000000L +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A_MASK 0x80000000L +#define MC_CHP_IO_CNTL_A1__MEM_CNTL_ENIMP_A 0x80000000L + +/* MC_CHP_IO_CNTL_B1 */ +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB_MASK 0x00000001L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_CKB 0x00000001L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB_MASK 0x00000002L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_AB 0x00000002L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB_MASK 0x00000004L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQMB 0x00000004L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB_MASK 0x00000008L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWN_DQSB 0x00000008L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB_MASK 0x00000010L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_CKB 0x00000010L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB_MASK 0x00000020L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_AB 0x00000020L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB_MASK 0x00000040L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQMB 0x00000040L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB_MASK 0x00000080L +#define MC_CHP_IO_CNTL_B1__MEM_SLEWP_DQSB 0x00000080L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB_MASK 0x00000100L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_AB 0x00000100L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB_MASK 0x00000200L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQMB 0x00000200L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB_MASK 0x00000400L +#define MC_CHP_IO_CNTL_B1__MEM_PREAMP_DQSB 0x00000400L +#define MC_CHP_IO_CNTL_B1__MEM_IO_MODEB_MASK 0x00003000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_CKB_MASK 0x0000c000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_AB_MASK 0x00030000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQMB_MASK 0x000c0000L +#define MC_CHP_IO_CNTL_B1__MEM_REC_DQSB_MASK 0x00300000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB_MASK 0x00400000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_PHASEB 0x00400000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB_MASK 0x00800000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_CENTERB 0x00800000L +#define MC_CHP_IO_CNTL_B1__MEM_SYNC_ENB_MASK 0x03000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_SELB_MASK 0x0c000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB_MASK 0x10000000L +#define MC_CHP_IO_CNTL_B1__MEM_CLK_INVB 0x10000000L +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B_MASK 0x40000000L +#define MC_CHP_IO_CNTL_B1__MEM_DATA_ENIMP_B 0x40000000L +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B_MASK 0x80000000L +#define MC_CHP_IO_CNTL_B1__MEM_CNTL_ENIMP_B 0x80000000L + +/* MEM_SDRAM_MODE_REG */ +#define MEM_SDRAM_MODE_REG__MEM_MODE_REG_MASK 0x00007fffL +#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY_MASK 0x000f0000L +#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY_MASK 0x00700000L +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY_MASK 0x00800000L +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY 0x00800000L +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY_MASK 0x01000000L +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY 0x01000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD_MASK 0x02000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD 0x02000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA_MASK 0x04000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA 0x04000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR_MASK 0x08000000L +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR 0x08000000L +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE_MASK 0x10000000L +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE 0x10000000L +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL_MASK 0x20000000L +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL 0x20000000L +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE_MASK 0x40000000L +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE 0x40000000L +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET_MASK 0x80000000L +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET 0x80000000L + +/* MEM_SDRAM_MODE_REG */ +#define MEM_SDRAM_MODE_REG__MEM_MODE_REG__SHIFT 0x00000000 +#define MEM_SDRAM_MODE_REG__MEM_WR_LATENCY__SHIFT 0x00000010 +#define MEM_SDRAM_MODE_REG__MEM_CAS_LATENCY__SHIFT 0x00000014 +#define MEM_SDRAM_MODE_REG__MEM_CMD_LATENCY__SHIFT 0x00000017 +#define MEM_SDRAM_MODE_REG__MEM_STR_LATENCY__SHIFT 0x00000018 +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_CMD__SHIFT 0x00000019 +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_DATA__SHIFT 0x0000001a +#define MEM_SDRAM_MODE_REG__MEM_FALL_OUT_STR__SHIFT 0x0000001b +#define MEM_SDRAM_MODE_REG__MC_INIT_COMPLETE__SHIFT 0x0000001c +#define MEM_SDRAM_MODE_REG__MEM_DDR_DLL__SHIFT 0x0000001d +#define MEM_SDRAM_MODE_REG__MEM_CFG_TYPE__SHIFT 0x0000001e +#define MEM_SDRAM_MODE_REG__MEM_SDRAM_RESET__SHIFT 0x0000001f + +/* MEM_REFRESH_CNTL */ +#define MEM_REFRESH_CNTL__MEM_REFRESH_RATE_MASK 0x000000ffL +#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS_MASK 0x00000100L +#define MEM_REFRESH_CNTL__MEM_REFRESH_DIS 0x00000100L +#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE_MASK 0x00000200L +#define MEM_REFRESH_CNTL__MEM_DYNAMIC_CKE 0x00000200L +#define MEM_REFRESH_CNTL__MEM_TRFC_MASK 0x0000f000L +#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE_MASK 0x00010000L +#define MEM_REFRESH_CNTL__MEM_CLKA0_ENABLE 0x00010000L +#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE_MASK 0x00020000L +#define MEM_REFRESH_CNTL__MEM_CLKA0b_ENABLE 0x00020000L +#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE_MASK 0x00040000L +#define MEM_REFRESH_CNTL__MEM_CLKA1_ENABLE 0x00040000L +#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE_MASK 0x00080000L +#define MEM_REFRESH_CNTL__MEM_CLKA1b_ENABLE 0x00080000L +#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE_MASK 0x00100000L +#define MEM_REFRESH_CNTL__MEM_CLKAFB_ENABLE 0x00100000L +#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKA_MASK 0x00c00000L +#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE_MASK 0x01000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0_ENABLE 0x01000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE_MASK 0x02000000L +#define MEM_REFRESH_CNTL__MEM_CLKB0b_ENABLE 0x02000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE_MASK 0x04000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1_ENABLE 0x04000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE_MASK 0x08000000L +#define MEM_REFRESH_CNTL__MEM_CLKB1b_ENABLE 0x08000000L +#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE_MASK 0x10000000L +#define MEM_REFRESH_CNTL__MEM_CLKBFB_ENABLE 0x10000000L +#define MEM_REFRESH_CNTL__DLL_FB_SLCT_CKB_MASK 0xc0000000L + +/* MC_STATUS */ +#define MC_STATUS__MEM_PWRUP_COMPL_A_MASK 0x00000001L +#define MC_STATUS__MEM_PWRUP_COMPL_A 0x00000001L +#define MC_STATUS__MEM_PWRUP_COMPL_B_MASK 0x00000002L +#define MC_STATUS__MEM_PWRUP_COMPL_B 0x00000002L +#define MC_STATUS__MC_IDLE_MASK 0x00000004L +#define MC_STATUS__MC_IDLE 0x00000004L +#define MC_STATUS__IMP_N_VALUE_R_BACK_MASK 0x00000078L +#define MC_STATUS__IMP_P_VALUE_R_BACK_MASK 0x00000780L +#define MC_STATUS__TEST_OUT_R_BACK_MASK 0x00000800L +#define MC_STATUS__TEST_OUT_R_BACK 0x00000800L +#define MC_STATUS__DUMMY_OUT_R_BACK_MASK 0x00001000L +#define MC_STATUS__DUMMY_OUT_R_BACK 0x00001000L +#define MC_STATUS__IMP_N_VALUE_A_R_BACK_MASK 0x0001e000L +#define MC_STATUS__IMP_P_VALUE_A_R_BACK_MASK 0x001e0000L +#define MC_STATUS__IMP_N_VALUE_CK_R_BACK_MASK 0x01e00000L +#define MC_STATUS__IMP_P_VALUE_CK_R_BACK_MASK 0x1e000000L + +/* MDLL_CKO */ +#define MDLL_CKO__MCKOA_SLEEP_MASK 0x00000001L +#define MDLL_CKO__MCKOA_SLEEP 0x00000001L +#define MDLL_CKO__MCKOA_RESET_MASK 0x00000002L +#define MDLL_CKO__MCKOA_RESET 0x00000002L +#define MDLL_CKO__MCKOA_RANGE_MASK 0x0000000cL +#define MDLL_CKO__ERSTA_SOUTSEL_MASK 0x00000030L +#define MDLL_CKO__MCKOA_FB_SEL_MASK 0x000000c0L +#define MDLL_CKO__MCKOA_REF_SKEW_MASK 0x00000700L +#define MDLL_CKO__MCKOA_FB_SKEW_MASK 0x00007000L +#define MDLL_CKO__MCKOA_BP_SEL_MASK 0x00008000L +#define MDLL_CKO__MCKOA_BP_SEL 0x00008000L +#define MDLL_CKO__MCKOB_SLEEP_MASK 0x00010000L +#define MDLL_CKO__MCKOB_SLEEP 0x00010000L +#define MDLL_CKO__MCKOB_RESET_MASK 0x00020000L +#define MDLL_CKO__MCKOB_RESET 0x00020000L +#define MDLL_CKO__MCKOB_RANGE_MASK 0x000c0000L +#define MDLL_CKO__ERSTB_SOUTSEL_MASK 0x00300000L +#define MDLL_CKO__MCKOB_FB_SEL_MASK 0x00c00000L +#define MDLL_CKO__MCKOB_REF_SKEW_MASK 0x07000000L +#define MDLL_CKO__MCKOB_FB_SKEW_MASK 0x70000000L +#define MDLL_CKO__MCKOB_BP_SEL_MASK 0x80000000L +#define MDLL_CKO__MCKOB_BP_SEL 0x80000000L + +/* MDLL_RDCKA */ +#define MDLL_RDCKA__MRDCKA0_SLEEP_MASK 0x00000001L +#define MDLL_RDCKA__MRDCKA0_SLEEP 0x00000001L +#define MDLL_RDCKA__MRDCKA0_RESET_MASK 0x00000002L +#define MDLL_RDCKA__MRDCKA0_RESET 0x00000002L +#define MDLL_RDCKA__MRDCKA0_RANGE_MASK 0x0000000cL +#define MDLL_RDCKA__MRDCKA0_REF_SEL_MASK 0x00000030L +#define MDLL_RDCKA__MRDCKA0_FB_SEL_MASK 0x000000c0L +#define MDLL_RDCKA__MRDCKA0_REF_SKEW_MASK 0x00000700L +#define MDLL_RDCKA__MRDCKA0_SINSEL_MASK 0x00000800L +#define MDLL_RDCKA__MRDCKA0_SINSEL 0x00000800L +#define MDLL_RDCKA__MRDCKA0_FB_SKEW_MASK 0x00007000L +#define MDLL_RDCKA__MRDCKA0_BP_SEL_MASK 0x00008000L +#define MDLL_RDCKA__MRDCKA0_BP_SEL 0x00008000L +#define MDLL_RDCKA__MRDCKA1_SLEEP_MASK 0x00010000L +#define MDLL_RDCKA__MRDCKA1_SLEEP 0x00010000L +#define MDLL_RDCKA__MRDCKA1_RESET_MASK 0x00020000L +#define MDLL_RDCKA__MRDCKA1_RESET 0x00020000L +#define MDLL_RDCKA__MRDCKA1_RANGE_MASK 0x000c0000L +#define MDLL_RDCKA__MRDCKA1_REF_SEL_MASK 0x00300000L +#define MDLL_RDCKA__MRDCKA1_FB_SEL_MASK 0x00c00000L +#define MDLL_RDCKA__MRDCKA1_REF_SKEW_MASK 0x07000000L +#define MDLL_RDCKA__MRDCKA1_SINSEL_MASK 0x08000000L +#define MDLL_RDCKA__MRDCKA1_SINSEL 0x08000000L +#define MDLL_RDCKA__MRDCKA1_FB_SKEW_MASK 0x70000000L +#define MDLL_RDCKA__MRDCKA1_BP_SEL_MASK 0x80000000L +#define MDLL_RDCKA__MRDCKA1_BP_SEL 0x80000000L + +/* MDLL_RDCKB */ +#define MDLL_RDCKB__MRDCKB0_SLEEP_MASK 0x00000001L +#define MDLL_RDCKB__MRDCKB0_SLEEP 0x00000001L +#define MDLL_RDCKB__MRDCKB0_RESET_MASK 0x00000002L +#define MDLL_RDCKB__MRDCKB0_RESET 0x00000002L +#define MDLL_RDCKB__MRDCKB0_RANGE_MASK 0x0000000cL +#define MDLL_RDCKB__MRDCKB0_REF_SEL_MASK 0x00000030L +#define MDLL_RDCKB__MRDCKB0_FB_SEL_MASK 0x000000c0L +#define MDLL_RDCKB__MRDCKB0_REF_SKEW_MASK 0x00000700L +#define MDLL_RDCKB__MRDCKB0_SINSEL_MASK 0x00000800L +#define MDLL_RDCKB__MRDCKB0_SINSEL 0x00000800L +#define MDLL_RDCKB__MRDCKB0_FB_SKEW_MASK 0x00007000L +#define MDLL_RDCKB__MRDCKB0_BP_SEL_MASK 0x00008000L +#define MDLL_RDCKB__MRDCKB0_BP_SEL 0x00008000L +#define MDLL_RDCKB__MRDCKB1_SLEEP_MASK 0x00010000L +#define MDLL_RDCKB__MRDCKB1_SLEEP 0x00010000L +#define MDLL_RDCKB__MRDCKB1_RESET_MASK 0x00020000L +#define MDLL_RDCKB__MRDCKB1_RESET 0x00020000L +#define MDLL_RDCKB__MRDCKB1_RANGE_MASK 0x000c0000L +#define MDLL_RDCKB__MRDCKB1_REF_SEL_MASK 0x00300000L +#define MDLL_RDCKB__MRDCKB1_FB_SEL_MASK 0x00c00000L +#define MDLL_RDCKB__MRDCKB1_REF_SKEW_MASK 0x07000000L +#define MDLL_RDCKB__MRDCKB1_SINSEL_MASK 0x08000000L +#define MDLL_RDCKB__MRDCKB1_SINSEL 0x08000000L +#define MDLL_RDCKB__MRDCKB1_FB_SKEW_MASK 0x70000000L +#define MDLL_RDCKB__MRDCKB1_BP_SEL_MASK 0x80000000L +#define MDLL_RDCKB__MRDCKB1_BP_SEL 0x80000000L + +#define MDLL_R300_RDCK__MRDCKA_SLEEP 0x00000001L +#define MDLL_R300_RDCK__MRDCKA_RESET 0x00000002L +#define MDLL_R300_RDCK__MRDCKB_SLEEP 0x00000004L +#define MDLL_R300_RDCK__MRDCKB_RESET 0x00000008L +#define MDLL_R300_RDCK__MRDCKC_SLEEP 0x00000010L +#define MDLL_R300_RDCK__MRDCKC_RESET 0x00000020L +#define MDLL_R300_RDCK__MRDCKD_SLEEP 0x00000040L +#define MDLL_R300_RDCK__MRDCKD_RESET 0x00000080L + +#define pllCLK_PIN_CNTL 0x0001 +#define pllPPLL_CNTL 0x0002 +#define pllPPLL_REF_DIV 0x0003 +#define pllPPLL_DIV_0 0x0004 +#define pllPPLL_DIV_1 0x0005 +#define pllPPLL_DIV_2 0x0006 +#define pllPPLL_DIV_3 0x0007 +#define pllVCLK_ECP_CNTL 0x0008 +#define pllHTOTAL_CNTL 0x0009 +#define pllM_SPLL_REF_FB_DIV 0x000A +#define pllAGP_PLL_CNTL 0x000B +#define pllSPLL_CNTL 0x000C +#define pllSCLK_CNTL 0x000D +#define pllMPLL_CNTL 0x000E +#define pllMDLL_CKO 0x000F +#define pllMDLL_RDCKA 0x0010 +#define pllMDLL_RDCKB 0x0011 +#define pllMCLK_CNTL 0x0012 +#define pllPLL_TEST_CNTL 0x0013 +#define pllCLK_PWRMGT_CNTL 0x0014 +#define pllPLL_PWRMGT_CNTL 0x0015 +#define pllCG_TEST_MACRO_RW_WRITE 0x0016 +#define pllCG_TEST_MACRO_RW_READ 0x0017 +#define pllCG_TEST_MACRO_RW_DATA 0x0018 +#define pllCG_TEST_MACRO_RW_CNTL 0x0019 +#define pllDISP_TEST_MACRO_RW_WRITE 0x001A +#define pllDISP_TEST_MACRO_RW_READ 0x001B +#define pllDISP_TEST_MACRO_RW_DATA 0x001C +#define pllDISP_TEST_MACRO_RW_CNTL 0x001D +#define pllSCLK_CNTL2 0x001E +#define pllMCLK_MISC 0x001F +#define pllTV_PLL_FINE_CNTL 0x0020 +#define pllTV_PLL_CNTL 0x0021 +#define pllTV_PLL_CNTL1 0x0022 +#define pllTV_DTO_INCREMENTS 0x0023 +#define pllSPLL_AUX_CNTL 0x0024 +#define pllMPLL_AUX_CNTL 0x0025 +#define pllP2PLL_CNTL 0x002A +#define pllP2PLL_REF_DIV 0x002B +#define pllP2PLL_DIV_0 0x002C +#define pllPIXCLKS_CNTL 0x002D +#define pllHTOTAL2_CNTL 0x002E +#define pllSSPLL_CNTL 0x0030 +#define pllSSPLL_REF_DIV 0x0031 +#define pllSSPLL_DIV_0 0x0032 +#define pllSS_INT_CNTL 0x0033 +#define pllSS_TST_CNTL 0x0034 +#define pllSCLK_MORE_CNTL 0x0035 + +#define ixMC_PERF_CNTL 0x0000 +#define ixMC_PERF_SEL 0x0001 +#define ixMC_PERF_REGION_0 0x0002 +#define ixMC_PERF_REGION_1 0x0003 +#define ixMC_PERF_COUNT_0 0x0004 +#define ixMC_PERF_COUNT_1 0x0005 +#define ixMC_PERF_COUNT_2 0x0006 +#define ixMC_PERF_COUNT_3 0x0007 +#define ixMC_PERF_COUNT_MEMCH_A 0x0008 +#define ixMC_PERF_COUNT_MEMCH_B 0x0009 +#define ixMC_IMP_CNTL 0x000A +#define ixMC_CHP_IO_CNTL_A0 0x000B +#define ixMC_CHP_IO_CNTL_A1 0x000C +#define ixMC_CHP_IO_CNTL_B0 0x000D +#define ixMC_CHP_IO_CNTL_B1 0x000E +#define ixMC_IMP_CNTL_0 0x000F +#define ixTC_MISMATCH_1 0x0010 +#define ixTC_MISMATCH_2 0x0011 +#define ixMC_BIST_CTRL 0x0012 +#define ixREG_COLLAR_WRITE 0x0013 +#define ixREG_COLLAR_READ 0x0014 +#define ixR300_MC_IMP_CNTL 0x0018 +#define ixR300_MC_CHP_IO_CNTL_A0 0x0019 +#define ixR300_MC_CHP_IO_CNTL_A1 0x001a +#define ixR300_MC_CHP_IO_CNTL_B0 0x001b +#define ixR300_MC_CHP_IO_CNTL_B1 0x001c +#define ixR300_MC_CHP_IO_CNTL_C0 0x001d +#define ixR300_MC_CHP_IO_CNTL_C1 0x001e +#define ixR300_MC_CHP_IO_CNTL_D0 0x001f +#define ixR300_MC_CHP_IO_CNTL_D1 0x0020 +#define ixR300_MC_IMP_CNTL_0 0x0021 +#define ixR300_MC_ELPIDA_CNTL 0x0022 +#define ixR300_MC_CHP_IO_OE_CNTL_CD 0x0023 +#define ixR300_MC_READ_CNTL_CD 0x0024 +#define ixR300_MC_MC_INIT_WR_LAT_TIMER 0x0025 +#define ixR300_MC_DEBUG_CNTL 0x0026 +#define ixR300_MC_BIST_CNTL_0 0x0028 +#define ixR300_MC_BIST_CNTL_1 0x0029 +#define ixR300_MC_BIST_CNTL_2 0x002a +#define ixR300_MC_BIST_CNTL_3 0x002b +#define ixR300_MC_BIST_CNTL_4 0x002c +#define ixR300_MC_BIST_CNTL_5 0x002d +#define ixR300_MC_IMP_STATUS 0x002e +#define ixR300_MC_DLL_CNTL 0x002f +#define NB_TOM 0x15C #endif /* _RADEON_H */ - -- cgit v1.3.1