From 467dc9a44b7b5654089ea1334a14ffd20c028916 Mon Sep 17 00:00:00 2001 From: Austin Shirley Date: Wed, 6 May 2026 16:37:58 -0600 Subject: configs: stm32mp13: add SPI-NAND UBI boot support The STM32MP13 default environment only handles MMC and serial/USB boot. When TF-A reports BOOT_FLASH_SPINAND the boot_device variable is set to 'spi-nand' but bootcmd_stm32mp never redirects boot_targets to ubifs0, so distro_bootcmd falls through to MMC/USB. This change mirrors the STM32MP15 logic: - Add a BOOT_TARGET_UBIFS entry to BOOT_TARGET_DEVICES so that bootcmd_ubifs0 is defined (ubi part UBI; ubifsmount ubi0:boot). - Add the 'spi-nand' / 'nand' clause to bootcmd_stm32mp so that boot_targets is set to 'ubifs0' when booting from NAND. Signed-off-by: Austin Shirley Cc: Patrick Delaunay Cc: Patrice Chotard Cc: Tom Rini Cc: uboot-stm32@st-md-mailman.stormreply.com --- include/configs/stm32mp13_common.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index 3e3f49abae0..e707b146f90 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -33,6 +33,12 @@ #define BOOT_TARGET_MMC1(func) #endif +#ifdef CONFIG_CMD_UBIFS +#define BOOT_TARGET_UBIFS(func) func(UBIFS, ubifs, 0, UBI, boot) +#else +#define BOOT_TARGET_UBIFS(func) +#endif + #ifdef CONFIG_CMD_USB #define BOOT_TARGET_USB(func) func(USB, usb, 0) #else @@ -41,12 +47,14 @@ #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_MMC1(func) \ + BOOT_TARGET_UBIFS(func) \ BOOT_TARGET_MMC0(func) \ BOOT_TARGET_USB(func) /* * default bootcmd for stm32mp13: * for serial/usb: execute the stm32prog command + * for nand or spi-nand boot, distro boot with ubifs on UBI partition * for mmc boot (eMMC, SD card), distro boot on the same mmc device */ #define STM32MP_BOOTCMD "bootcmd_stm32mp=" \ @@ -56,7 +64,10 @@ "else " \ "run env_check;" \ "if test ${boot_device} = mmc;" \ - "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ + "then env set boot_targets \"mmc${boot_instance}\"; fi; " \ + "if test ${boot_device} = nand ||" \ + " test ${boot_device} = spi-nand ;" \ + "then env set boot_targets ubifs0; fi;" \ "run distro_bootcmd;" \ "fi;\0" -- cgit v1.3.1 From 2a55938b42b90eb656fe32384294318e37305830 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 30 Apr 2026 10:06:02 +0200 Subject: lib: uuid: add partition type GUID for extended bootloader The Extended Boot Loader Partition (XBOOTLDR) is a standard defined by the Discoverable Partitions Specification (DPS) to host boot loader resources outside of the EFI System Partition ([1], [2]). Defining this GUID (bc13c2ff-59e6-4262-a352-b275fd6f7172) allows U-Boot to correctly identify and label these partitions using the "xbootldr" shorthand. [1] https://uapi-group.org/specifications/specs/discoverable_partitions_specification/#extended-boot-loader-partition:~:text=UEFI%20Specification.-,Extended%20Boot%20Loader%20Partition,-bc13c2ff%2D59e6%2D4262 [2] https://uapi-group.org/specifications/specs/boot_loader_specification/ Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass --- doc/README.gpt | 2 ++ include/part_efi.h | 3 +++ lib/uuid.c | 1 + 3 files changed, 6 insertions(+) (limited to 'include') diff --git a/doc/README.gpt b/doc/README.gpt index 386ac2e0fc8..a6e1fd7ce8d 100644 --- a/doc/README.gpt +++ b/doc/README.gpt @@ -286,6 +286,8 @@ Some strings can be also used at the place of known GUID : (E6D6D379-F507-44C2-A23C-238F2A3DF928) "u-boot-env" = PARTITION_U_BOOT_ENVIRONMENT (3DE21764-95BD-54BD-A5C3-4ABE786F38A8) + "xbootldr" = PARTITION_XBOOTLDR + (BC13C2FF-59E6-4262-A352-B275FD6F7172) "uuid_disk=...;name=u-boot,size=60MiB,uuid=...; name=kernel,size=60MiB,uuid=...,type=linux;" diff --git a/include/part_efi.h b/include/part_efi.h index 2cea5088046..5713b3018f4 100644 --- a/include/part_efi.h +++ b/include/part_efi.h @@ -60,6 +60,9 @@ #define PARTITION_U_BOOT_ENVIRONMENT \ EFI_GUID( 0x3de21764, 0x95bd, 0x54bd, \ 0xa5, 0xc3, 0x4a, 0xbe, 0x78, 0x6f, 0x38, 0xa8) +#define PARTITION_XBOOTLDR \ + EFI_GUID( 0xbc13c2ff, 0x59e6, 0x4262, \ + 0xa3, 0x52, 0xb2, 0x75, 0xfd, 0x6f, 0x71, 0x72) /* Special ChromiumOS things */ #define PARTITION_CROS_KERNEL \ diff --git a/lib/uuid.c b/lib/uuid.c index 3a666d0430d..d7c164ea06b 100644 --- a/lib/uuid.c +++ b/lib/uuid.c @@ -86,6 +86,7 @@ static const struct { {"swap", NULL, PARTITION_LINUX_SWAP_GUID}, {"lvm", NULL, PARTITION_LINUX_LVM_GUID}, {"u-boot-env", NULL, PARTITION_U_BOOT_ENVIRONMENT}, + {"xbootldr", NULL, PARTITION_XBOOTLDR}, {"cros-kern", NULL, PARTITION_CROS_KERNEL}, {"cros-root", NULL, PARTITION_CROS_ROOT}, {"cros-fw", NULL, PARTITION_CROS_FIRMWARE}, -- cgit v1.3.1 From 97cdde6dfad31341d5efc9a8030b90049577ab90 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 30 Apr 2026 10:06:07 +0200 Subject: fwu: add helper to get image GUID by type and bank index Introduce fwu_mdata_get_image_guid() to retrieve a specific image GUID from the FWU metadata based on the bank index and image type GUID. This allows identifying the correct partition in multi-bank (A/B) scenarios, ensuring the correct image is targeted depending on the current bank. Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass Acked-by: Ilias Apalodimas --- include/fwu.h | 11 +++++++++++ lib/fwu_updates/fwu.c | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 44 insertions(+) (limited to 'include') diff --git a/include/fwu.h b/include/fwu.h index 9cee8fb085c..68a51fb4296 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -396,6 +396,17 @@ void fwu_populate_mdata_image_info(struct fwu_data *data); */ int fwu_get_mdata_size(uint32_t *mdata_size); +/** + * fwu_mdata_get_image_guid() - Get image GUID for a type and bank + * @image_guid: Pointer to be filled with the found image GUID + * @image_type_guid: Pointer to the image type GUID to search for + * @bank_index: Index of the bank + * + * Return: 0 if OK, -ve on error + */ +int fwu_mdata_get_image_guid(efi_guid_t *image_guid, + const efi_guid_t *image_type_guid, u32 bank_index); + /** * fwu_state_machine_updates() - Update FWU state of the platform * @state: FWU bank state diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c index e82600a29a4..2b11e5da061 100644 --- a/lib/fwu_updates/fwu.c +++ b/lib/fwu_updates/fwu.c @@ -243,6 +243,39 @@ int fwu_sync_mdata(struct fwu_mdata *mdata, int part) return 0; } +/** + * fwu_mdata_get_image_guid() - Get image GUID for a type and bank + * @image_guid: Pointer to be filled with the found image GUID + * @image_type_guid: Pointer to the image type GUID to search for + * @bank_index: Index of the bank + * + * Return: 0 if OK, -ve on error + */ +int fwu_mdata_get_image_guid(efi_guid_t *image_guid, + const efi_guid_t *image_type_guid, u32 bank_index) +{ + struct fwu_data *data = &g_fwu_data; + struct fwu_image_entry *image; + int i; + + if (bank_index >= data->num_banks) + return -EINVAL; + + for (i = 0; i < data->num_images; i++) { + image = &data->fwu_images[i]; + + if (!guidcmp(image_type_guid, &image->image_type_guid)) { + struct fwu_image_bank_info *bank; + + bank = &image->img_bank_info[bank_index]; + guidcpy(image_guid, &bank->image_guid); + return 0; + } + } + + return -ENOENT; +} + /** * fwu_mdata_copies_allocate() - Allocate memory for metadata * @mdata_size: Size of the metadata structure -- cgit v1.3.1 From 4300f9f4c5d709c86297c8a8702b92af604ed7c3 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Thu, 30 Apr 2026 10:06:09 +0200 Subject: board: st: stm32mp25: support dynamic A/B bank bootup Enable automatic detection of the active A/B bank by retrieving partition GUIDs from FWU metadata. This ensures the system correctly identifies the bootable partitions even in multi-bank scenarios, falling back to a standard bootable flag scan if the UUIDs are missing. To enable A/B bank bootup on stm32mp25 boards, add the following Kconfig options to the stm32mp25_defconfig: CONFIG_FWU_MULTI_BANK_UPDATE=y CONFIG_FWU_MDATA=y CONFIG_FWU_NUM_BANKS=2 CONFIG_FWU_NUM_IMAGES_PER_BANK=3 CONFIG_CMD_FWU_METADATA=y CONFIG_FWU_MDATA_V2=y Signed-off-by: Dario Binacchi Reviewed-by: Simon Glass Reviewed-by: Patrice Chotard --- board/st/stm32mp2/stm32mp2.c | 32 ++++++++++++++++++++++++++++++++ include/configs/stm32mp25_st_common.h | 15 +++++++++++++++ 2 files changed, 47 insertions(+) (limited to 'include') diff --git a/board/st/stm32mp2/stm32mp2.c b/board/st/stm32mp2/stm32mp2.c index 43bc583378e..5cbbbc322a3 100644 --- a/board/st/stm32mp2/stm32mp2.c +++ b/board/st/stm32mp2/stm32mp2.c @@ -208,4 +208,36 @@ void fwu_plat_get_bootidx(uint *boot_idx) *boot_idx = (readl(TAMP_FWU_BOOT_INFO_REG) >> TAMP_FWU_BOOT_IDX_OFFSET) & TAMP_FWU_BOOT_IDX_MASK; } + +int fwu_platform_hook(struct udevice *dev, struct fwu_data *data) +{ + uint boot_idx; + efi_guid_t boot_uuid, root_uuid; + const efi_guid_t boot_type_guid = PARTITION_XBOOTLDR; + const efi_guid_t root_type_guid = + PARTITION_LINUX_FILE_SYSTEM_DATA_GUID; + char uuidbuf[UUID_STR_LEN + 1]; + int retb, retr; + + fwu_plat_get_bootidx(&boot_idx); + + retb = fwu_mdata_get_image_guid(&boot_uuid, &boot_type_guid, boot_idx); + retr = fwu_mdata_get_image_guid(&root_uuid, &root_type_guid, boot_idx); + + if (!retb && !retr) { + uuid_bin_to_str(boot_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID); + env_set("boot_partuuid", uuidbuf); + + uuid_bin_to_str(root_uuid.b, uuidbuf, UUID_STR_FORMAT_GUID); + env_set("root_partuuid", uuidbuf); + } else if (!retb && retr) { + log_warning("%s: found boot GUID but missing root GUID (%d)\n", + __func__, retr); + } else if (!retr && retb) { + log_warning("%s: found root GUID but missing boot GUID (%d)\n", + __func__, retb); + } + + return 0; +} #endif /* CONFIG_FWU_MULTI_BANK_UPDATE */ diff --git a/include/configs/stm32mp25_st_common.h b/include/configs/stm32mp25_st_common.h index cb679eb1be2..0b0267ae99b 100644 --- a/include/configs/stm32mp25_st_common.h +++ b/include/configs/stm32mp25_st_common.h @@ -8,7 +8,22 @@ #ifndef __CONFIG_STM32MP25_ST_COMMON_H__ #define __CONFIG_STM32MP25_ST_COMMON_H__ +#ifdef CONFIG_FWU_MULTI_BANK_UPDATE +#define SCAN_DEV_FOR_BOOT_PARTS \ + "setenv devplist; " \ + "env exists boot_partuuid && " \ + "part number ${devtype} ${devnum} ${boot_partuuid} devplist; " \ + "env exists devplist || " \ + "part list ${devtype} ${devnum} -bootable devplist; " + +#define ST_STM32MP25_FWU_ENV \ + "altbootcmd=${bootcmd}\0" +#else +#define ST_STM32MP25_FWU_ENV +#endif + #define STM32MP_BOARD_EXTRA_ENV \ + ST_STM32MP25_FWU_ENV \ "usb_pgood_delay=2000\0" \ "console=ttySTM0\0" -- cgit v1.3.1 From 0f0ff73bac5dc43f8fe336f2828900035e260f1a Mon Sep 17 00:00:00 2001 From: Janne Grunau Date: Fri, 1 May 2026 00:31:16 +0200 Subject: arm: apple: Switch to board based text env The main use case for u-boot on Apple silicon based devices is to provide an EFI based bootloader for operating systems. This uses a generic u-boot image with DTBs passed from an earlier boot loader (m1n1). Use the generic board name "mac" for this purpose. Signed-off-by: Janne Grunau --- MAINTAINERS | 1 + arch/arm/mach-apple/Kconfig | 14 ++++++++++++-- arch/arm/mach-apple/rtkit_helper.c | 1 + board/apple/mac/mac.env | 4 ++++ configs/apple_m1_defconfig | 2 ++ drivers/iommu/apple_dart.c | 1 + drivers/nvme/nvme_apple.c | 1 + include/configs/apple.h | 18 ------------------ 8 files changed, 22 insertions(+), 20 deletions(-) create mode 100644 board/apple/mac/mac.env delete mode 100644 include/configs/apple.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index ae4013767d1..ea646f618a5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -137,6 +137,7 @@ R: Janne Grunau S: Maintained F: arch/arm/include/asm/arch-apple/ F: arch/arm/mach-apple/ +F: board/apple/ F: configs/apple_m1_defconfig F: doc/board/apple/ F: drivers/input/apple_spi_kbd.c diff --git a/arch/arm/mach-apple/Kconfig b/arch/arm/mach-apple/Kconfig index 294690ec0e8..fdc8c32152f 100644 --- a/arch/arm/mach-apple/Kconfig +++ b/arch/arm/mach-apple/Kconfig @@ -3,12 +3,22 @@ if ARCH_APPLE config TEXT_BASE default 0x00000000 -config SYS_CONFIG_NAME +config SYS_SOC default "apple" -config SYS_SOC +config SYS_VENDOR default "apple" +config SYS_BOARD + string "Board name" + default "mac" + help + This option contains information about board name. + Based on this option board// will + be used. + Apple silicon based devices are expected to use the generic board name + "mac". + config SYS_MALLOC_LEN default 0x4000000 diff --git a/arch/arm/mach-apple/rtkit_helper.c b/arch/arm/mach-apple/rtkit_helper.c index b7d60e15700..cbdc204f141 100644 --- a/arch/arm/mach-apple/rtkit_helper.c +++ b/arch/arm/mach-apple/rtkit_helper.c @@ -11,6 +11,7 @@ #include #include #include +#include /* ASC registers */ #define REG_CPU_CTRL 0x0044 diff --git a/board/apple/mac/mac.env b/board/apple/mac/mac.env new file mode 100644 index 00000000000..109379c8c67 --- /dev/null +++ b/board/apple/mac/mac.env @@ -0,0 +1,4 @@ +stdin=serial,usbkbd,spikbd +stdout=vidconsole,serial +stderr=vidconsole,serial +boot_targets=nvme usb diff --git a/configs/apple_m1_defconfig b/configs/apple_m1_defconfig index 1ce69f2882a..6020cd3f215 100644 --- a/configs/apple_m1_defconfig +++ b/configs/apple_m1_defconfig @@ -29,3 +29,5 @@ CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_NO_FB_CLEAR=y CONFIG_VIDEO_SIMPLE=y CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE=y +CONFIG_SYS_VENDOR=apple +CONFIG_SYS_BOARD=mac diff --git a/drivers/iommu/apple_dart.c b/drivers/iommu/apple_dart.c index bfd4ad20105..ebef28d0b9d 100644 --- a/drivers/iommu/apple_dart.c +++ b/drivers/iommu/apple_dart.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/nvme/nvme_apple.c b/drivers/nvme/nvme_apple.c index 48f82bc826c..3e7d95c2b54 100644 --- a/drivers/nvme/nvme_apple.c +++ b/drivers/nvme/nvme_apple.c @@ -13,6 +13,7 @@ #include #include #include +#include /* ASC registers */ #define REG_CPU_CTRL 0x0044 diff --git a/include/configs/apple.h b/include/configs/apple.h deleted file mode 100644 index 1e08b114480..00000000000 --- a/include/configs/apple.h +++ /dev/null @@ -1,18 +0,0 @@ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* Environment */ -#define ENV_DEVICE_SETTINGS \ - "stdin=serial,usbkbd,spikbd\0" \ - "stdout=vidconsole,serial\0" \ - "stderr=vidconsole,serial\0" - -#define BOOT_TARGETS "nvme usb" - -#define CFG_EXTRA_ENV_SETTINGS \ - ENV_DEVICE_SETTINGS \ - "boot_targets=" BOOT_TARGETS "\0" - -#endif -- cgit v1.3.1 From 4839ba90456cd38fe4229b9b804002e2414c2e21 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 6 May 2026 14:34:16 +0200 Subject: p2041rdb: use the upstream device tree Switch to the upstream device tree, which already includes the UART nodes we need for the DM. We also need to increase malloc area before relocation otherwise you'll get the following error and the board panics: DRAM: Initializing....using SPD alloc space exhausted ptr 414 limit 400 Signed-off-by: Michael Walle Signed-off-by: Peng Fan --- arch/powerpc/dts/Makefile | 1 - arch/powerpc/dts/p2041.dtsi | 138 ---------------------------------- arch/powerpc/dts/p2041rdb-u-boot.dtsi | 19 +++++ arch/powerpc/dts/p2041rdb.dts | 127 ------------------------------- arch/powerpc/dts/p2041si-post.dtsi | 43 ----------- configs/P2041RDB_SPIFLASH_defconfig | 4 +- configs/P2041RDB_defconfig | 4 +- include/configs/P2041RDB.h | 2 + 8 files changed, 27 insertions(+), 311 deletions(-) delete mode 100644 arch/powerpc/dts/p2041.dtsi create mode 100644 arch/powerpc/dts/p2041rdb-u-boot.dtsi delete mode 100644 arch/powerpc/dts/p2041rdb.dts delete mode 100644 arch/powerpc/dts/p2041si-post.dtsi (limited to 'include') diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 766b0c05951..4fd3478ac2f 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -14,7 +14,6 @@ dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb -dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi deleted file mode 100644 index ad09b138fc8..00000000000 --- a/arch/powerpc/dts/p2041.dtsi +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * P2041 Silicon/SoC Device Tree Source (pre include) - * - * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019-2020 NXP - */ - -/dts-v1/; - -/include/ "e500mc_power_isa.dtsi" - -/ { - compatible = "fsl,P2041"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&mpic>; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: PowerPC,e500mc@0 { - device_type = "cpu"; - reg = <0>; - fsl,portid-mapping = <0x80000000>; - }; - cpu1: PowerPC,e500mc@1 { - device_type = "cpu"; - reg = <1>; - fsl,portid-mapping = <0x40000000>; - }; - cpu2: PowerPC,e500mc@2 { - device_type = "cpu"; - reg = <2>; - fsl,portid-mapping = <0x20000000>; - }; - cpu3: PowerPC,e500mc@3 { - device_type = "cpu"; - reg = <3>; - fsl,portid-mapping = <0x10000000>; - }; - }; - - soc: soc@ffe000000 { - ranges = <0x00000000 0xf 0xfe000000 0x1000000>; - reg = <0xf 0xfe000000 0 0x00001000>; - #address-cells = <1>; - #size-cells = <1>; - device_type = "soc"; - compatible = "simple-bus"; - - mpic: pic@40000 { - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <4>; - reg = <0x40000 0x40000>; - compatible = "fsl,mpic", "chrp,open-pic"; - device_type = "open-pic"; - clock-frequency = <0x0>; - }; - - espi0: spi@110000 { - compatible = "fsl,mpc8536-espi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x110000 0x1000>; - fsl,espi-num-chipselects = <4>; - status = "disabled"; - }; - - usb0: usb@210000 { - compatible = "fsl-usb2-mph"; - reg = <0x210000 0x1000>; - phy_type = "utmi"; - }; - - usb1: usb@211000 { - compatible = "fsl-usb2-mph"; - reg = <0x210000 0x1000>; - phy_type = "utmi"; - }; - - sata: sata@220000 { - compatible = "fsl,pq-sata-v2"; - reg = <0x220000 0x1000>; - interrupts = <68 0x2 0 0>; - sata-offset = <0x1000>; - sata-number = <2>; - sata-fpdma = <0>; - }; - - esdhc: esdhc@114000 { - compatible = "fsl,esdhc"; - reg = <0x114000 0x1000>; - clock-frequency = <0>; - }; - - /include/ "qoriq-i2c-0.dtsi" - /include/ "qoriq-i2c-1.dtsi" - }; - - pcie@ffe200000 { - compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ - law_trgt_if = <0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; - - pcie@ffe201000 { - compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ - law_trgt_if = <1>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; - - pcie@ffe202000 { - compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; - reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ - law_trgt_if = <2>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - bus-range = <0x0 0xff>; - ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ - 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ - }; -}; diff --git a/arch/powerpc/dts/p2041rdb-u-boot.dtsi b/arch/powerpc/dts/p2041rdb-u-boot.dtsi new file mode 100644 index 00000000000..1dc83cf846b --- /dev/null +++ b/arch/powerpc/dts/p2041rdb-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&serial0 { + bootph-all; +}; + +&soc { + i2c@118000 { + bootph-all; + }; + + spi@110000 { + flash@0 { + spi-max-frequency = <10000000>; + }; + }; +}; + +#include "u-boot.dtsi" diff --git a/arch/powerpc/dts/p2041rdb.dts b/arch/powerpc/dts/p2041rdb.dts deleted file mode 100644 index 0fa1f098524..00000000000 --- a/arch/powerpc/dts/p2041rdb.dts +++ /dev/null @@ -1,127 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * P2041RDB Device Tree Source - * - * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2019-2020 NXP - */ - -/include/ "p2041.dtsi" - -/ { - model = "fsl,P2041RDB"; - compatible = "fsl,P2041RDB"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&mpic>; - - aliases { - phy_rgmii_0 = &phy_rgmii_0; - phy_rgmii_1 = &phy_rgmii_1; - phy_sgmii_2 = &phy_sgmii_2; - phy_sgmii_3 = &phy_sgmii_3; - phy_sgmii_4 = &phy_sgmii_4; - phy_sgmii_1c = &phy_sgmii_1c; - phy_sgmii_1d = &phy_sgmii_1d; - phy_sgmii_1e = &phy_sgmii_1e; - phy_sgmii_1f = &phy_sgmii_1f; - phy_xgmii_2 = &phy_xgmii_2; - spi0 = &espi0; - }; - - soc: soc@ffe000000 { - ranges = <0x00000000 0xf 0xfe000000 0x1000000>; - reg = <0xf 0xfe000000 0 0x00001000>; - - fman@400000 { - ethernet@e0000 { - phy-handle = <&phy_sgmii_2>; - phy-connection-type = "sgmii"; - }; - - mdio@e1120 { - phy_rgmii_0: ethernet-phy@0 { - reg = <0x0>; - }; - - phy_rgmii_1: ethernet-phy@1 { - reg = <0x1>; - }; - - phy_sgmii_2: ethernet-phy@2 { - reg = <0x2>; - }; - - phy_sgmii_3: ethernet-phy@3 { - reg = <0x3>; - }; - - phy_sgmii_4: ethernet-phy@4 { - reg = <0x4>; - }; - - phy_sgmii_1c: ethernet-phy@1c { - reg = <0x1c>; - }; - - phy_sgmii_1d: ethernet-phy@1d { - reg = <0x1d>; - }; - - phy_sgmii_1e: ethernet-phy@1e { - reg = <0x1e>; - }; - - phy_sgmii_1f: ethernet-phy@1f { - reg = <0x1f>; - }; - }; - - ethernet@e2000 { - phy-handle = <&phy_sgmii_3>; - phy-connection-type = "sgmii"; - }; - - ethernet@e4000 { - phy-handle = <&phy_sgmii_4>; - phy-connection-type = "sgmii"; - }; - - ethernet@e6000 { - phy-handle = <&phy_rgmii_1>; - phy-connection-type = "rgmii"; - }; - - ethernet@e8000 { - phy-handle = <&phy_rgmii_0>; - phy-connection-type = "rgmii"; - }; - - ethernet@f0000 { - phy-handle = <&phy_xgmii_2>; - phy-connection-type = "xgmii"; - }; - - mdio@f1000 { - phy_xgmii_2: ethernet-phy@0 { - compatible = "ethernet-phy-ieee802.3-c45"; - reg = <0x0>; - }; - }; - }; - }; -}; - -&espi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0>; - /* input clock */ - spi-max-frequency = <10000000>; - }; -}; - -/include/ "p2041si-post.dtsi" diff --git a/arch/powerpc/dts/p2041si-post.dtsi b/arch/powerpc/dts/p2041si-post.dtsi deleted file mode 100644 index 8819199646f..00000000000 --- a/arch/powerpc/dts/p2041si-post.dtsi +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -/* - * P2041/P2040 Silicon/SoC Device Tree Source (post include) - * - * Copyright 2011 - 2015 Freescale Semiconductor Inc. - * Copyright 2020 NXP - * - */ - -&soc { - -/include/ "qoriq-clockgen1.dtsi" -/include/ "qoriq-gpio-0.dtsi" -/include/ "qoriq-sec4.2-0.dtsi" - -/* include used FMan blocks */ -/include/ "qoriq-fman-0.dtsi" -/include/ "qoriq-fman-0-1g-0.dtsi" -/include/ "qoriq-fman-0-1g-1.dtsi" -/include/ "qoriq-fman-0-1g-2.dtsi" -/include/ "qoriq-fman-0-1g-3.dtsi" -/include/ "qoriq-fman-0-1g-4.dtsi" -/include/ "qoriq-fman-0-10g-0.dtsi" - fman@400000 { - enet0: ethernet@e0000 { - }; - - enet1: ethernet@e2000 { - }; - - enet2: ethernet@e4000 { - }; - - enet3: ethernet@e6000 { - }; - - enet4: ethernet@e8000 { - }; - - enet5: ethernet@f0000 { - }; - }; -}; diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 599eda68f37..25af3cd6fcd 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -1,11 +1,12 @@ CONFIG_PPC=y CONFIG_TEXT_BASE=0xFFF40000 CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SYS_MALLOC_F_LEN=0x600 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" +CONFIG_DEFAULT_DEVICE_TREE="fsl/p2041rdb" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MPC85xx=y CONFIG_SYS_INIT_RAM_LOCK=y @@ -56,6 +57,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index f9e6a9e454c..c2c00d54bfa 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -1,10 +1,11 @@ CONFIG_PPC=y CONFIG_TEXT_BASE=0xEFF40000 CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SYS_MALLOC_F_LEN=0x600 CONFIG_SF_DEFAULT_SPEED=10000000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" +CONFIG_DEFAULT_DEVICE_TREE="fsl/p2041rdb" CONFIG_SYS_MONITOR_LEN=786432 CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y @@ -52,6 +53,7 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT2=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_OF_UPSTREAM=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_USE_BOOTFILE=y diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index f88fb9cdb9a..3525e29acc4 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -149,6 +149,8 @@ * shorted - index 1 */ +#define CFG_SYS_NS16550_CLK (get_bus_freq(0) / 2) + #define CFG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -- cgit v1.3.1 From 7252890625d5c56cdce41e5fbe3686c4e47f4f61 Mon Sep 17 00:00:00 2001 From: Vincent Jardin Date: Mon, 11 May 2026 09:37:34 +0200 Subject: board: nxp: lx2160a: without QIXIS, MC-ENET, PCI, LTC3882 The shared LX2160A board file calls helpers that only exist when their subsystem is enabled. Gate them on the matching CONFIG_*: - pci_init() under CONFIG_PCI. - fdt_fixup_mc_ddr() and fsl_rgmii_init() under CONFIG_FSL_MC_ENET. - qixis_*() and the QIXIS branch of checkboard() under CONFIG_FSL_QIXIS; cpu_name(buf) moves out so the non-QIXIS path still prints "Board: ". - EVENT_SPY_SIMPLE on init_func_vid moves inside the CONFIG_VOL_MONITOR_LTC3882_READ guard (was outside, dangling symbol when LTC3882 off). #if / #ifdef, not IS_ENABLED(), because the helpers are themselves conditionally compiled. While here, lx2160a_common.h: fix BOOT_TARGET_DEVICES_MMC 1 arg vs 2 args and gate the MMC target on CONFIG_CMD_MMC, not CONFIG_MMC. No functional change for NXP boards: LX2160ARDB, LX2160AQDS, or LX2162AQDS, but mainly build clean up in order to support other NXP lx2160a boards without those HW dependencies. Signed-off-by: Vincent Jardin Signed-off-by: Peng Fan --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 +++++- board/nxp/lx2160a/lx2160a.c | 18 +++++++++++++----- include/configs/lx2160a_common.h | 4 ++-- 3 files changed, 20 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 7f0cb28f52d..a047494b1fd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1143,7 +1143,7 @@ int arch_early_init_r(void) #ifdef CONFIG_SYS_HAS_SERDES fsl_serdes_init(); #endif -#ifdef CONFIG_SYS_FSL_HAS_RGMII +#if defined(CONFIG_SYS_FSL_HAS_RGMII) && defined(CONFIG_FSL_MC_ENET) /* some dpmacs in armv8a based freescale layerscape SOCs can be * configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via * EC*_PMUX(rgmii) bits in RCW. @@ -1158,6 +1158,10 @@ int arch_early_init_r(void) * function of SOC, the dpmac will be enabled as RGMII even if it was * also enabled before as SGMII. If ECx_PMUX is not configured for * RGMII, DPMAC will remain configured as SGMII from fsl_serdes_init(). + * + * fsl_rgmii_init() itself is only built under CONFIG_FSL_MC_ENET + * (drivers/net/ldpaa_eth/); gate the call the same way so builds + * without MC-ENET still link. */ fsl_rgmii_init(); #endif diff --git a/board/nxp/lx2160a/lx2160a.c b/board/nxp/lx2160a/lx2160a.c index d34865de8c2..b7a6ccf46aa 100644 --- a/board/nxp/lx2160a/lx2160a.c +++ b/board/nxp/lx2160a/lx2160a.c @@ -242,13 +242,17 @@ int init_func_vid(void) return 0; } -#endif EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, init_func_vid); +#endif int checkboard(void) { - enum boot_src src = get_boot_src(); char buf[64]; + + cpu_name(buf); + +#if IS_ENABLED(CONFIG_FSL_QIXIS) + enum boot_src src = get_boot_src(); u8 sw; #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) int clock; @@ -258,7 +262,6 @@ int checkboard(void) "100 separate SSCG"}; #endif - cpu_name(buf); #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) printf("Board: %s-QDS, ", buf); #else @@ -325,7 +328,10 @@ int checkboard(void) clock = sw >> 4; printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]); #endif -#endif +#endif /* LX2160ARDB-inside-QIXIS switch */ +#else /* !CONFIG_FSL_QIXIS */ + printf("Board: %s\n", buf); +#endif /* CONFIG_FSL_QIXIS */ return 0; } @@ -554,7 +560,7 @@ int board_init(void) out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK); #endif -#if !defined(CONFIG_SYS_EARLY_PCI_INIT) +#if defined(CONFIG_PCI) && !defined(CONFIG_SYS_EARLY_PCI_INIT) pci_init(); #endif return 0; @@ -788,7 +794,9 @@ int ft_board_setup(void *blob, struct bd_info *bd) ft_cpu_setup(blob, bd); +#if IS_ENABLED(CONFIG_FSL_MC_ENET) fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size); +#endif if (mc_memory_base != 0) mc_memory_bank++; diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 45b5cbdd85a..dc0d24dca0a 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -197,10 +197,10 @@ #define BOOT_TARGET_DEVICES_USB(func) #endif -#ifdef CONFIG_MMC +#ifdef CONFIG_CMD_MMC #define BOOT_TARGET_DEVICES_MMC(func, instance) func(MMC, mmc, instance) #else -#define BOOT_TARGET_DEVICES_MMC(func) +#define BOOT_TARGET_DEVICES_MMC(func, instance) #endif #ifdef CONFIG_SCSI -- cgit v1.3.1 From d77f8443c7c07ac37b70f812ffa774b55bcef91c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 7 May 2026 19:37:48 +0200 Subject: arm64: dts: renesas: Switch to upstream DT on Renesas R-Car X5H R8A78000 Enable OF_UPSTREAM to use upstream Linux kernel DT source as a base for U-Boot control DT. Retain currently present parts of the DT which are not yet part of upstream Linux kernel DT in -u-boot.dtsi files until they get replaced by upstream equivalents. Add renesas/ prefix to the DEFAULT_DEVICE_TREE as part of the switch. Unused i2c2..i2c8 nodes have been removed, and will become available once upstream Linux kernel DT adds those nodes. The DRAM_RSV_SIZE has been updated to cover first 518 MiB of DRAM, which are reserved for firmware and other use. Note that all DT parts in -u-boot.dtsi are not considered stable DT bindings and may change before they land in Linux kernel and become stable DT ABI. Signed-off-by: Marek Vasut --- arch/arm/dts/Makefile | 7 - arch/arm/dts/r8a78000-ironhide-u-boot.dtsi | 174 +++++ arch/arm/dts/r8a78000-ironhide.dts | 257 ------ arch/arm/dts/r8a78000-u-boot.dtsi | 375 +++++++-- arch/arm/dts/r8a78000.dtsi | 1164 ---------------------------- configs/r8a78000_ironhide_defconfig | 3 +- include/configs/rcar-gen5-common.h | 2 +- 7 files changed, 481 insertions(+), 1501 deletions(-) delete mode 100644 arch/arm/dts/r8a78000-ironhide.dts delete mode 100644 arch/arm/dts/r8a78000.dtsi (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d5dd0867622..820fd6002bd 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -899,13 +899,6 @@ dtb-$(CONFIG_RZA1) += \ r7s72100-genmai.dtb \ r7s72100-gr-peach.dtb -dtb-$(CONFIG_RCAR_GEN5) += \ - r8a78000-ironhide.dtb - -ifdef CONFIG_RCAR_GEN5 -DTC_FLAGS += -R 4 -p 0x1000 -endif - dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb diff --git a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi index 9c72f3e55f4..eebad1281fc 100644 --- a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi @@ -5,4 +5,178 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ +#include #include "r8a78000-u-boot.dtsi" + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &mmc0; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +ð_pcs { + phys = <&mp_phy 2 1>; + status = "okay"; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&mmc0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-1 = <&mmc0_pins>; + pinctrl-names = "default", "state_uhs"; + + bus-width = <8>; + full-pwr-cycle-in-suspend; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sd; + no-sdio; + non-removable; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + + status = "okay"; +}; + +&mp_phy { + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + eth25g2_pins: eth25g2 { + groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint"; + function = "eth25g2"; + drive-strength = <24>; + }; + + ethes0_pins: ethes0 { + groups = "ethes0_match", "ethes0_capture", "ethes0_pps"; + function = "ethes0"; + drive-strength = <24>; + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + mmc0_pins: mmc0 { + groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds"; + function = "mmc0"; + drive-strength = <24>; + }; + + rsw3_pins: rsw3 { + groups = "rsw3_match", "rsw3_capture", "rsw3_pps"; + function = "rsw3"; + drive-strength = <24>; + }; + + scif_clk_pins: scif-clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&rswitch3 { + pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>; + pinctrl-names = "default"; + status = "okay"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* + * NOTE: Only port@4 is configured for R-Car X5H board. + * Other ports (0-3, 5-12) are currently unused or not + * connected. + */ + port@4 { + reg = <4>; + renesas,connect_to_xpcs; + phy-handle = <&dp83869_phy>; + phy-mode = "sgmii"; + phys = <ð_pcs 5>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + dp83869_phy: ethernet-phy@2 { + reg = <2>; + ti,sgmii-interface; + ti,max-output-impedance; + ti,refclk-output-enable; + ti,clk-output-sel = ; + }; + }; + }; + }; +}; + +&ufs0 { + status = "okay"; +}; + +&ufs1 { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a78000-ironhide.dts b/arch/arm/dts/r8a78000-ironhide.dts deleted file mode 100644 index 601f2740b54..00000000000 --- a/arch/arm/dts/r8a78000-ironhide.dts +++ /dev/null @@ -1,257 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the Ironhide board - * - * Copyright (C) 2025 Renesas Electronics Corp. - */ - -/dts-v1/; -#include "r8a78000.dtsi" -#include - -/ { - model = "Renesas Ironhide board based on r8a78000"; - compatible = "renesas,ironhide", "renesas,r8a78000"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - i2c8 = &i2c8; - mmc0 = &mmc0; - serial0 = &hscif0; - }; - - chosen { - stdout-path = "serial0:1843200n8"; - }; - - memory@40000000 { - device_type = "memory"; - reg = <0x0 0x40000000 0x0 0x80000000>; - }; - - memory@1080000000 { - device_type = "memory"; - reg = <0x10 0x80000000 0x0 0x80000000>; - }; - - memory@1200000000 { - device_type = "memory"; - reg = <0x12 0x00000000 0x1 0x00000000>; - }; - - memory@1400000000 { - device_type = "memory"; - reg = <0x14 0x00000000 0x1 0x00000000>; - }; - - memory@1600000000 { - device_type = "memory"; - reg = <0x16 0x00000000 0x1 0x00000000>; - }; - - memory@1800000000 { - device_type = "memory"; - reg = <0x18 0x00000000 0x1 0x00000000>; - }; - - memory@1a00000000 { - device_type = "memory"; - reg = <0x1a 0x00000000 0x1 0x00000000>; - }; - - memory@1c00000000 { - device_type = "memory"; - reg = <0x1c 0x00000000 0x1 0x00000000>; - }; - - memory@1e00000000 { - device_type = "memory"; - reg = <0x1e 0x00000000 0x1 0x00000000>; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&extal_clk { - clock-frequency = <16666600>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hscif0 { - pinctrl-0 = <&hscif0_pins>; - pinctrl-names = "default"; - uart-has-rtscts; - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - status = "okay"; - - eeprom@50 { - compatible = "rohm,br24g01", "atmel,24c01"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - status = "okay"; -}; - -ð_pcs { - phys = <&mp_phy 2 1>; - status = "okay"; -}; - -&mmc0 { - pinctrl-0 = <&mmc0_pins>; - pinctrl-1 = <&mmc0_pins>; - pinctrl-names = "default", "state_uhs"; - - bus-width = <8>; - full-pwr-cycle-in-suspend; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - no-sd; - no-sdio; - non-removable; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - - status = "okay"; -}; - -&ufs0 { - status = "okay"; -}; - -&ufs1 { - status = "okay"; -}; - -&mp_phy { - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - eth25g2_pins: eth25g2 { - groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint"; - function = "eth25g2"; - drive-strength = <24>; - }; - - ethes0_pins: ethes0 { - groups = "ethes0_match", "ethes0_capture", "ethes0_pps"; - function = "ethes0"; - drive-strength = <24>; - }; - - hscif0_pins: hscif0 { - groups = "hscif0_data", "hscif0_ctrl"; - function = "hscif0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - mmc0_pins: mmc0 { - groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds"; - function = "mmc0"; - drive-strength = <24>; - }; - - rsw3_pins: rsw3 { - groups = "rsw3_match", "rsw3_capture", "rsw3_pps"; - function = "rsw3"; - drive-strength = <24>; - }; - - scif_clk_pins: scif-clk { - groups = "scif_clk"; - function = "scif_clk"; - }; -}; - -&rswitch3 { - pinctrl-0 = <&rsw3_pins>, <ð25g2_pins>, <ðes0_pins>; - pinctrl-names = "default"; - status = "okay"; - - ethernet-ports { - #address-cells = <1>; - #size-cells = <0>; - - /* - * NOTE: Only port@4 is configured for R-Car X5H board. - * Other ports (0-3, 5-12) are currently unused or not - * connected. - */ - port@4 { - reg = <4>; - renesas,connect_to_xpcs; - phy-handle = <&dp83869_phy>; - phy-mode = "sgmii"; - phys = <ð_pcs 5>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - dp83869_phy: ethernet-phy@2 { - reg = <2>; - ti,sgmii-interface; - ti,max-output-impedance; - ti,refclk-output-enable; - ti,clk-output-sel = ; - }; - }; - }; - }; -}; - -&scif_clk { - clock-frequency = <26000000>; -}; diff --git a/arch/arm/dts/r8a78000-u-boot.dtsi b/arch/arm/dts/r8a78000-u-boot.dtsi index 1bc73252430..5e29ad3df33 100644 --- a/arch/arm/dts/r8a78000-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-u-boot.dtsi @@ -5,9 +5,41 @@ * Copyright (C) 2025 Renesas Electronics Corp. */ +#include +#include +#include + / { - soc { - bootph-all; + firmware { + scmi { + compatible = "arm,scmi"; + arm,poll-transport; + mbox-names = "tx", "rx"; + mboxes = <&mailbox 0>, <&mailbox 1>; + shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>; + #address-cells = <1>; + #size-cells = <0>; + + scmi_devpd: protocol@11 { + reg = <0x11>; + #power-domain-cells = <1>; + }; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; }; /* Placeholder clock until the clock provider is in place */ @@ -38,10 +70,6 @@ }; }; -&cpg { - bootph-all; -}; - &extal_clk { bootph-all; }; @@ -50,90 +78,297 @@ bootph-all; }; -&gpio0 { - clocks = <&clk_stub_gpio>; +&prr { + bootph-all; }; -&gpio1 { - clocks = <&clk_stub_gpio>; -}; +&soc { + bootph-all; -&gpio2 { - clocks = <&clk_stub_gpio>; -}; + mailbox: mfis_mbox@18842000 { + compatible = "renesas,mfis-mbox"; + #mbox-cells = <1>; + reg = <0 0x18842004 0 0x8>; + interrupts = ; + }; -&gpio3 { - clocks = <&clk_stub_gpio>; -}; + pfc: pinctrl@c0400000 { + compatible = "renesas,pfc-r8a78000"; + reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>, + <0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>, + <0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>, + <0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>, + <0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>, + <0 0xc9b00800 0 0x104>; + }; -&gpio4 { - clocks = <&clk_stub_gpio>; -}; + mmc0: mmc@c0880000 { + compatible = "renesas,rcar-gen5-sdhi"; + reg = <0 0xc0880000 0 0x2000>; + clock-names = "core"; + max-frequency = <200000000>; + clocks = <&clk_stub_mmc>; + status = "disabled"; + }; -&gpio5 { - clocks = <&clk_stub_gpio>; -}; + ufs0: ufs@c0a80000 { + compatible = "renesas,r8a78000-ufs"; + reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>; + reg-names = "hcr", "phy"; + interrupts = ; + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS0>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS0>; + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS0>; + freq-table-hz = <38400000 38400000>; + status = "disabled"; + }; -&gpio6 { - clocks = <&clk_stub_gpio>; -}; + ufs1: ufs@c0a90000 { + compatible = "renesas,r8a78000-ufs"; + reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>; + reg-names = "hcr", "phy"; + interrupts = ; + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS1>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS1>; + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS1>; + freq-table-hz = <38400000 38400000>; + status = "disabled"; + }; -&gpio7 { - clocks = <&clk_stub_gpio>; -}; + scp: sram@c1000000 { + compatible = "arm,rcar-sram-ns", "mmio-sram"; + reg = <0x0 0xc1000000 0x0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xc1000000 0x80000>; -&gpio8 { - clocks = <&clk_stub_gpio>; -}; + cpu_scp_lpri0: scp-shmem@60000 { + compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; + reg = <0x61200 0x0100>; + }; -&gpio9 { - clocks = <&clk_stub_gpio>; -}; + cpu_scp_hpri0: scp-shmem@60300 { + compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; + reg = <0x61300 0x100>; + }; + }; -&gpio10 { - clocks = <&clk_stub_gpio>; -}; + cpg: clock-controller@c64f0000 { + compatible = "renesas,r8a78000-cpg-mssr"; + reg = <0 0xc64f0000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + bootph-all; + }; -&i2c0 { - clocks = <&clk_stub_i2c0>; -}; + i2c0: i2c@c11d0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc11d0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_stub_i2c0>; + status = "disabled"; + }; -&i2c1 { - clocks = <&clk_stub_i2c1>; -}; + i2c1: i2c@c06c0000 { + compatible = "renesas,i2c-r8a78000", + "renesas,rcar-gen5-i2c"; + reg = <0 0xc06c0000 0 0x40>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk_stub_i2c1>; + status = "disabled"; + }; -&i2c2 { - clocks = <&clk_stub_i2c1>; -}; + gpio0: gpio@c1080110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1080110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 28>; + clocks = <&clk_stub_gpio>; + }; -&i2c3 { - clocks = <&clk_stub_i2c1>; -}; + gpio1: gpio@c1080910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1080910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 22>; + clocks = <&clk_stub_gpio>; + }; -&i2c4 { - clocks = <&clk_stub_i2c1>; -}; + gpio2: gpio@c1081110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc1081110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 29>; + clocks = <&clk_stub_gpio>; + }; -&i2c5 { - clocks = <&clk_stub_i2c1>; -}; + gpio3: gpio@c0800110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0800110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 17>; + clocks = <&clk_stub_gpio>; + }; -&i2c6 { - clocks = <&clk_stub_i2c1>; -}; + gpio4: gpio@c0800910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0800910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 16>; + clocks = <&clk_stub_gpio>; + }; -&i2c7 { - clocks = <&clk_stub_i2c1>; -}; + gpio5: gpio@c0400110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0400110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 23>; + clocks = <&clk_stub_gpio>; + }; -&i2c8 { - clocks = <&clk_stub_i2c1>; -}; + gpio6: gpio@c0400910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0400910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 31>; + clocks = <&clk_stub_gpio>; + }; -&mmc0 { - clocks = <&clk_stub_mmc>; -}; + gpio7: gpio@c0401110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0401110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 31>; + clocks = <&clk_stub_gpio>; + }; -&prr { - bootph-all; + gpio8: gpio@c0401910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc0401910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 256 32>; + gpio-reserved-ranges = <16 10>; + clocks = <&clk_stub_gpio>; + }; + + gpio9: gpio@c9b00110 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc9b00110 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 288 17>; + clocks = <&clk_stub_gpio>; + }; + + gpio10: gpio@c9b00910 { + compatible = "renesas,gpio-r8a78000", + "renesas,rcar-gen5-gpio"; + reg = <0 0xc9b00910 0 0xc0>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 320 14>; + clocks = <&clk_stub_gpio>; + }; + + mp_phy: mp_phy@c9a00000 { + compatible = "renesas,r8a78000-multi-protocol-phy"; + reg = <0 0xc9a00000 0 0x100000>; + #phy-cells = <2>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY01>, + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY11>, + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY21>, + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY31>, + <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY02>; + clock-names = "mpphy01", "mpphy11", "mpphy21", + "mpphy31", "mpphy02"; + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP0>, + <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP1>, + <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP2>, + <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP3>; + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY01>, + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY11>, + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY21>, + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY31>, + <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY02>; + status = "disabled"; + }; + + rswitch3: ethernet@c9bc0000 { + compatible = "renesas,r8a78000-ether-switch3", + "renesas,etherswitch"; + reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>; + reg-names = "base", "secure_base"; + power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_RSW>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSN>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3AES>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES0>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES1>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES2>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES3>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES4>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES5>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES6>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES7>, + <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3MFWD>; + clock-names = "rsw3", "rsw3tsn", "rsw3aes", + "rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2", + "rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5", + "rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd"; + status = "disabled"; + }; + + eth_pcs: phy@c9c50000 { + compatible = "renesas,r8a78000-ether-pcs"; + reg = <0 0xc9c50000 0 0x4000>; + #phy-cells = <1>; + clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS0>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS1>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS2>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS3>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS4>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS5>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS6>, + <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS7>; + clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", + "xpcs4", "xpcs5", "xpcs6", "xpcs7"; + resets = <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS0>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS1>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS2>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS3>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS4>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS5>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS6>, + <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS7>; + reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", + "xpcs4", "xpcs5", "xpcs6", "xpcs7"; + status = "disabled"; + }; }; diff --git a/arch/arm/dts/r8a78000.dtsi b/arch/arm/dts/r8a78000.dtsi deleted file mode 100644 index 89c2881fa94..00000000000 --- a/arch/arm/dts/r8a78000.dtsi +++ /dev/null @@ -1,1164 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -/* - * Device Tree Source for the R-Car X5H (R8A78000) SoC - * - * Copyright (C) 2025 Renesas Electronics Corp. - */ - -#include -#include -#include -#include - -/ { - compatible = "renesas,r8a78000"; - #address-cells = <2>; - #size-cells = <2>; - interrupt-parent = <&gic>; - - cpus { - #address-cells = <2>; - #size-cells = <0>; - - cpu-map { - cluster0 { - core0 { - cpu = <&a720_0>; - }; - core1 { - cpu = <&a720_1>; - }; - core2 { - cpu = <&a720_2>; - }; - core3 { - cpu = <&a720_3>; - }; - }; - - cluster1 { - core0 { - cpu = <&a720_4>; - }; - core1 { - cpu = <&a720_5>; - }; - core2 { - cpu = <&a720_6>; - }; - core3 { - cpu = <&a720_7>; - }; - }; - - cluster2 { - core0 { - cpu = <&a720_8>; - }; - core1 { - cpu = <&a720_9>; - }; - core2 { - cpu = <&a720_10>; - }; - core3 { - cpu = <&a720_11>; - }; - }; - - cluster3 { - core0 { - cpu = <&a720_12>; - }; - core1 { - cpu = <&a720_13>; - }; - core2 { - cpu = <&a720_14>; - }; - core3 { - cpu = <&a720_15>; - }; - }; - - cluster4 { - core0 { - cpu = <&a720_16>; - }; - core1 { - cpu = <&a720_17>; - }; - core2 { - cpu = <&a720_18>; - }; - core3 { - cpu = <&a720_19>; - }; - }; - - cluster5 { - core0 { - cpu = <&a720_20>; - }; - core1 { - cpu = <&a720_21>; - }; - core2 { - cpu = <&a720_22>; - }; - core3 { - cpu = <&a720_23>; - }; - }; - - cluster6 { - core0 { - cpu = <&a720_24>; - }; - core1 { - cpu = <&a720_25>; - }; - core2 { - cpu = <&a720_26>; - }; - core3 { - cpu = <&a720_27>; - }; - }; - - cluster7 { - core0 { - cpu = <&a720_28>; - }; - core1 { - cpu = <&a720_29>; - }; - core2 { - cpu = <&a720_30>; - }; - core3 { - cpu = <&a720_31>; - }; - }; - }; - - a720_0: cpu@0 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x0>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_0>; - }; - - a720_1: cpu@100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_1>; - }; - - a720_2: cpu@200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_2>; - }; - - a720_3: cpu@300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_3>; - }; - - a720_4: cpu@10000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_4>; - }; - - a720_5: cpu@10100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_5>; - }; - - a720_6: cpu@10200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_6>; - }; - - a720_7: cpu@10300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x10300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_7>; - }; - - a720_8: cpu@20000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_8>; - }; - - a720_9: cpu@20100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_9>; - }; - - a720_10: cpu@20200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_10>; - }; - - a720_11: cpu@20300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x20300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_11>; - }; - - a720_12: cpu@30000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_12>; - }; - - a720_13: cpu@30100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_13>; - }; - - a720_14: cpu@30200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_14>; - }; - - a720_15: cpu@30300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x30300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_15>; - }; - - a720_16: cpu@40000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_16>; - }; - - a720_17: cpu@40100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_17>; - }; - - a720_18: cpu@40200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_18>; - }; - - a720_19: cpu@40300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x40300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_19>; - }; - - a720_20: cpu@50000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_20>; - }; - - a720_21: cpu@50100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_21>; - }; - - a720_22: cpu@50200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_22>; - }; - - a720_23: cpu@50300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x50300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_23>; - }; - - a720_24: cpu@60000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_24>; - }; - - a720_25: cpu@60100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_25>; - }; - - a720_26: cpu@60200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_26>; - }; - - a720_27: cpu@60300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x60300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_27>; - }; - - a720_28: cpu@70000 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70000>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_28>; - }; - - a720_29: cpu@70100 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70100>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_29>; - }; - - a720_30: cpu@70200 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70200>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_30>; - }; - - a720_31: cpu@70300 { - compatible = "arm,cortex-a720ae"; - reg = <0x0 0x70300>; - device_type = "cpu"; - next-level-cache = <&L2_CA720_31>; - }; - - L2_CA720_0: cache-controller-200 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_1: cache-controller-201 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_2: cache-controller-202 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_3: cache-controller-203 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_0>; - }; - - L2_CA720_4: cache-controller-204 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_5: cache-controller-205 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_6: cache-controller-206 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_7: cache-controller-207 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_1>; - }; - - L2_CA720_8: cache-controller-208 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_9: cache-controller-209 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_10: cache-controller-210 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_11: cache-controller-211 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_2>; - }; - - L2_CA720_12: cache-controller-212 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_13: cache-controller-213 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_14: cache-controller-214 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_15: cache-controller-215 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_3>; - }; - - L2_CA720_16: cache-controller-216 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_17: cache-controller-217 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_18: cache-controller-218 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_19: cache-controller-219 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_4>; - }; - - L2_CA720_20: cache-controller-220 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_21: cache-controller-221 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_22: cache-controller-222 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_23: cache-controller-223 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_5>; - }; - - L2_CA720_24: cache-controller-224 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_25: cache-controller-225 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_26: cache-controller-226 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_27: cache-controller-227 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_6>; - }; - - L2_CA720_28: cache-controller-228 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L2_CA720_29: cache-controller-229 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L2_CA720_30: cache-controller-230 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L2_CA720_31: cache-controller-231 { - compatible = "cache"; - cache-unified; - cache-level = <2>; - next-level-cache = <&L3_CA720_7>; - }; - - L3_CA720_0: cache-controller-30 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_1: cache-controller-31 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_2: cache-controller-32 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_3: cache-controller-33 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_4: cache-controller-34 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_5: cache-controller-35 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_6: cache-controller-36 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - - L3_CA720_7: cache-controller-37 { - compatible = "cache"; - cache-unified; - cache-level = <3>; - }; - }; - - /* - * In the early phase, there is no clock control support, - * so assume that the clocks are enabled by default. - * Therefore, dummy clocks are used. - */ - dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <66666000>; - }; - - dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <266660000>; - }; - - extal_clk: extal-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* clock-frequency must be set on board */ - }; - - extalr_clk: extalr-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* clock-frequency must be set on board */ - }; - - firmware { - scmi { - compatible = "arm,scmi"; - arm,poll-transport; - mbox-names = "tx", "rx"; - mboxes = <&mailbox 0>, <&mailbox 1>; - shmem = <&cpu_scp_lpri0>, <&cpu_scp_hpri0>; - #address-cells = <1>; - #size-cells = <0>; - - scmi_devpd: protocol@11 { - reg = <0x11>; - #power-domain-cells = <1>; - }; - - scmi_clk: protocol@14 { - reg = <0x14>; - #clock-cells = <1>; - }; - - scmi_reset: protocol@16 { - reg = <0x16>; - #reset-cells = <1>; - }; - }; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - /* External SCIF clock - to be overridden by boards that provide it */ - scif_clk: scif-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; /* optional */ - }; - - soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - mailbox: mfis_mbox@18842000 { - compatible = "renesas,mfis-mbox"; - #mbox-cells = <1>; - reg = <0 0x18842004 0 0x8>; - interrupts = ; - }; - - prr: chipid@189e0044 { - compatible = "renesas,prr"; - reg = <0 0x189e0044 0 4>; - }; - - /* Application Processors manage View-1 of a GIC-720AE */ - gic: interrupt-controller@39000000 { - compatible = "arm,gic-v3"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0x39000000 0 0x10000>, - <0 0x39080000 0 0x800000>; - interrupts = ; - }; - - pfc: pinctrl@c0400000 { - compatible = "renesas,pfc-r8a78000"; - reg = <0 0xc1080000 0 0x104>, <0 0xc1080800 0 0x104>, - <0 0xc1081000 0 0x104>, <0 0xc0800000 0 0x104>, - <0 0xc0800800 0 0x104>, <0 0xc0400000 0 0x104>, - <0 0xc0400800 0 0x104>, <0 0xc0401000 0 0x104>, - <0 0xc0401800 0 0x104>, <0 0xc9b00000 0 0x104>, - <0 0xc9b00800 0 0x104>; - }; - - scif0: serial@c0700000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc0700000 0 0x40>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - scif1: serial@c0704000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc0704000 0 0x40>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - scif3: serial@c0708000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc0708000 0 0x40>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - scif4: serial@c070c000 { - compatible = "renesas,scif-r8a78000", - "renesas,rcar-gen5-scif", "renesas,scif"; - reg = <0 0xc070c000 0 0x40>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd16>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - mmc0: mmc@c0880000 { - compatible = "renesas,rcar-gen5-sdhi"; - reg = <0 0xc0880000 0 0x2000>; - clock-names = "core"; - max-frequency = <200000000>; - status = "disabled"; - }; - - ufs0: ufs@c0a80000 { - compatible = "renesas,r8a78000-ufs"; - reg = <0 0xc0a80000 0 0x1100>, <0 0xc0a00000 0 0x40000>; - reg-names = "hcr", "phy"; - interrupts = ; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS0>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS0>; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS0>; - freq-table-hz = <38400000 38400000>; - status = "disabled"; - }; - - ufs1: ufs@c0a90000 { - compatible = "renesas,r8a78000-ufs"; - reg = <0 0xc0a90000 0 0x1100>, <0 0xc0a40000 0 0x40000>; - reg-names = "hcr", "phy"; - interrupts = ; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_UFS1>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_UFS1>; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_UFS1>; - freq-table-hz = <38400000 38400000>; - status = "disabled"; - }; - - scp: sram@c1000000 { - compatible = "arm,rcar-sram-ns", "mmio-sram"; - reg = <0x0 0xc1000000 0x0 0x80000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xc1000000 0x80000>; - - cpu_scp_lpri0: scp-shmem@60000 { - compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; - reg = <0x61200 0x0100>; - }; - - cpu_scp_hpri0: scp-shmem@60300 { - compatible = "arm,rcar-scp-shmem", "arm,scmi-shmem"; - reg = <0x61300 0x100>; - }; - }; - - cpg: clock-controller@c64f0000 { - compatible = "renesas,r8a78000-cpg-mssr"; - reg = <0 0xc64f0000 0 0x4000>; - clocks = <&extal_clk>, <&extalr_clk>; - clock-names = "extal", "extalr"; - #clock-cells = <2>; - #power-domain-cells = <0>; - #reset-cells = <1>; - }; - - hscif0: serial@c0710000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc0710000 0 0x60>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - hscif1: serial@c0714000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc0714000 0 0x60>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - hscif2: serial@c0718000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc0718000 0 0x60>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - hscif3: serial@c071c000 { - compatible = "renesas,hscif-r8a78000", - "renesas,rcar-gen5-hscif", "renesas,hscif"; - reg = <0 0xc071c000 0 0x60>; - interrupts = ; - clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>; - clock-names = "fck", "brg_int", "scif_clk"; - status = "disabled"; - }; - - i2c0: i2c@c11d0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc11d0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c1: i2c@c06c0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06c0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c2: i2c@c06c8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06c8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c3: i2c@c06d0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06d0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c4: i2c@c06d8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06d8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c5: i2c@c06e0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06e0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c6: i2c@c06e8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06e8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c7: i2c@c06f0000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06f0000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c8: i2c@c06f8000 { - compatible = "renesas,i2c-r8a78000", - "renesas,rcar-gen5-i2c"; - reg = <0 0xc06f8000 0 0x40>; - i2c-scl-internal-delay-ns = <110>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - gpio0: gpio@c1080110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc1080110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 0 28>; - }; - - gpio1: gpio@c1080910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc1080910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 32 22>; - }; - - gpio2: gpio@c1081110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc1081110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 64 29>; - }; - - gpio3: gpio@c0800110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0800110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 96 17>; - }; - - gpio4: gpio@c0800910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0800910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 128 16>; - }; - - gpio5: gpio@c0400110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0400110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 160 23>; - }; - - gpio6: gpio@c0400910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0400910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 192 31>; - }; - - gpio7: gpio@c0401110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0401110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 224 31>; - }; - - gpio8: gpio@c0401910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc0401910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 256 32>; - gpio-reserved-ranges = <16 10>; - }; - - gpio9: gpio@c9b00110 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc9b00110 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 288 17>; - }; - - gpio10: gpio@c9b00910 { - compatible = "renesas,gpio-r8a78000", - "renesas,rcar-gen5-gpio"; - reg = <0 0xc9b00910 0 0xc0>; - #gpio-cells = <2>; - gpio-controller; - gpio-ranges = <&pfc 0 320 14>; - }; - - mp_phy: mp_phy@c9a00000 { - compatible = "renesas,r8a78000-multi-protocol-phy"; - reg = <0 0xc9a00000 0 0x100000>; - #phy-cells = <2>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY01>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY11>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY21>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY31>, - <&scmi_clk SCP_CLOCK_ID_MDLC_MPPHY02>; - clock-names = "mpphy01", "mpphy11", "mpphy21", - "mpphy31", "mpphy02"; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP0>, - <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP1>, - <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP2>, - <&scmi_devpd X5H_POWER_DOMAIN_ID_MPP3>; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY01>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY11>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY21>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY31>, - <&scmi_reset SCP_RESET_DOMAIN_ID_MPPHY02>; - status = "disabled"; - }; - - rswitch3: ethernet@c9bc0000 { - compatible = "renesas,r8a78000-ether-switch3", - "renesas,etherswitch"; - reg = <0 0xc9bc0000 0 0x40000>, <0 0xc9b80000 0 0x240000>; - reg-names = "base", "secure_base"; - power-domains = <&scmi_devpd X5H_POWER_DOMAIN_ID_RSW>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSN>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3AES>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES0>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES1>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES2>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES3>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES4>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES5>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES6>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3TSNTES7>, - <&scmi_clk SCP_CLOCK_ID_MDLC_RSW3MFWD>; - clock-names = "rsw3", "rsw3tsn", "rsw3aes", - "rsw3tsntes0", "rsw3tsntes1", "rsw3tsntes2", - "rsw3tsntes3", "rsw3tsntes4", "rsw3tsntes5", - "rsw3tsntes6", "rsw3tsntes7", "rsw3mfwd"; - status = "disabled"; - }; - - eth_pcs: phy@c9c50000 { - compatible = "renesas,r8a78000-ether-pcs"; - reg = <0 0xc9c50000 0 0x4000>; - #phy-cells = <1>; - clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS0>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS1>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS2>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS3>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS4>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS5>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS6>, - <&scmi_clk SCP_CLOCK_ID_MDLC_XPCS7>; - clock-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", - "xpcs4", "xpcs5", "xpcs6", "xpcs7"; - resets = <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS0>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS1>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS2>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS3>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS4>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS5>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS6>, - <&scmi_reset SCP_RESET_DOMAIN_ID_XPCS7>; - reset-names = "xpcs0", "xpcs1", "xpcs2", "xpcs3", - "xpcs4", "xpcs5", "xpcs6", "xpcs7"; - status = "disabled"; - }; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - , - ; - interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; - }; -}; diff --git a/configs/r8a78000_ironhide_defconfig b/configs/r8a78000_ironhide_defconfig index 180704e75af..f8a1403ae0d 100644 --- a/configs/r8a78000_ironhide_defconfig +++ b/configs/r8a78000_ironhide_defconfig @@ -5,12 +5,11 @@ CONFIG_ARCH_RENESAS=y CONFIG_RCAR_GEN5=y CONFIG_TARGET_IRONHIDE=y -# CONFIG_OF_UPSTREAM is not set CONFIG_ARMV8_PSCI=y CONFIG_ARM_SMCCC=y CONFIG_BAUDRATE=1843200 CONFIG_BOOTCOMMAND="setexpr dloadaddr ${loadaddr} + 0x200000 && setexpr dloadaddr ${dloadaddr} \\\\& 0xffc00000 && setexpr kloadaddr ${dloadaddr} + 0x200000 && tftp ${dloadaddr} r8a78000-ironhide.dtb && tftp ${kloadaddr} Image && booti ${kloadaddr} - ${dloadaddr}" -CONFIG_DEFAULT_DEVICE_TREE="r8a78000-ironhide" +CONFIG_DEFAULT_DEVICE_TREE="renesas/r8a78000-ironhide" CONFIG_CLK_CCF=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_SCMI=y diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h index 81b5e2aa5bb..9edc37cba8b 100644 --- a/include/configs/rcar-gen5-common.h +++ b/include/configs/rcar-gen5-common.h @@ -12,7 +12,7 @@ #define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200, 3250000 } /* Memory */ -#define DRAM_RSV_SIZE 0x08000000 +#define DRAM_RSV_SIZE 0x20600000 #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) -- cgit v1.3.1 From 9692469b18457af5039cf44b4d2e06ae1384f40d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 7 May 2026 19:37:49 +0200 Subject: arm64: dts: renesas: Use SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN on R-Car X5H Use macro SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN for SCMI clock 1691 instead of hardcoding the number in DT. No functional change. Signed-off-by: Marek Vasut --- arch/arm/dts/r8a78000-u-boot.dtsi | 2 +- include/dt-bindings/clock/r8a78000-clock-scmi.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/dts/r8a78000-u-boot.dtsi b/arch/arm/dts/r8a78000-u-boot.dtsi index 5e29ad3df33..ee8aa9ee199 100644 --- a/arch/arm/dts/r8a78000-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-u-boot.dtsi @@ -65,7 +65,7 @@ compatible = "renesas,compound-clock"; #clock-cells = <0>; clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_SDHI0>, - <&scmi_clk 1691>; + <&scmi_clk SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN>; clock-names = "mdlc", "per"; }; }; diff --git a/include/dt-bindings/clock/r8a78000-clock-scmi.h b/include/dt-bindings/clock/r8a78000-clock-scmi.h index 455402ee8cc..663effddeb4 100644 --- a/include/dt-bindings/clock/r8a78000-clock-scmi.h +++ b/include/dt-bindings/clock/r8a78000-clock-scmi.h @@ -43,4 +43,6 @@ #define SCP_CLOCK_ID_MDLC_MPPHY31 347 #define SCP_CLOCK_ID_MDLC_MPPHY02 348 +#define SCP_CLOCK_ID_CLK_S0D6_PERE_MAIN 1691 + #endif /* __DT_BINDINGS_R8A78000_SCMI_CLOCK_H__ */ -- cgit v1.3.1 From 3e24519d6f7ed84581d159d501b973b9ada74588 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 00:56:29 +0200 Subject: arm64: renesas: Select HSCIF for DEBUG UART on R-Car Gen5 R8A78000 X5H The R-Car Gen5 R8A78000 X5H uses HSCIF as default serial console interface. Select CFG_HSCIF to make debug UART code also configure serial console interface as HSCIF instead of SCIF in case the CONFIG_DEBUG_UART would be enabled. Signed-off-by: Marek Vasut --- include/configs/rcar-gen5-common.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h index 9edc37cba8b..4fbe8994f62 100644 --- a/include/configs/rcar-gen5-common.h +++ b/include/configs/rcar-gen5-common.h @@ -10,6 +10,7 @@ /* Console */ #define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200, 3250000 } +#define CFG_HSCIF /* Memory */ #define DRAM_RSV_SIZE 0x20600000 -- cgit v1.3.1 From 5fa536f698355d050c946a552b4b068925d620bc Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 8 May 2026 01:23:33 +0200 Subject: arm64: dts: renesas: Update reset IDs on R-Car Gen5 R8A78000 X5H The current DT reset ID encoding in R-Car Gen5 R8A78000 X5H U-Boot DTs is inherited from downstream BSP. New reset bindings for this SoC are now submitted and under review [1]. Replace the DT reset IDs with the ones used in the new bindings. [1] https://lore.kernel.org/all/053c312d07445517d8f9c84bfe3cc8fb72d4cd9a.1776793163.git.geert+renesas@glider.be/ Signed-off-by: Marek Vasut --- include/dt-bindings/reset/r8a78000-reset-scmi.h | 38 +++++++++++-------------- 1 file changed, 16 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/reset/r8a78000-reset-scmi.h b/include/dt-bindings/reset/r8a78000-reset-scmi.h index e0d10caa589..3d84bfb073a 100644 --- a/include/dt-bindings/reset/r8a78000-reset-scmi.h +++ b/include/dt-bindings/reset/r8a78000-reset-scmi.h @@ -1,33 +1,27 @@ /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (C) 2025 Renesas Electronics Corp. - * - * IDs match SCP 4.27 + * Copyright (C) 2025-2026 Renesas Electronics Corp. */ #ifndef __DT_BINDINGS_R8A78000_SCMI_RESET_H__ #define __DT_BINDINGS_R8A78000_SCMI_RESET_H__ -/* - * These definition indices match the Reset ID defined by SCP FW 4.27. - */ - -#define SCP_RESET_DOMAIN_ID_UFS0 202 -#define SCP_RESET_DOMAIN_ID_UFS1 203 +#define SCP_RESET_DOMAIN_ID_UFS0 0x60 +#define SCP_RESET_DOMAIN_ID_UFS1 0x61 -#define SCP_RESET_DOMAIN_ID_XPCS0 316 -#define SCP_RESET_DOMAIN_ID_XPCS1 317 -#define SCP_RESET_DOMAIN_ID_XPCS2 318 -#define SCP_RESET_DOMAIN_ID_XPCS3 319 -#define SCP_RESET_DOMAIN_ID_XPCS4 320 -#define SCP_RESET_DOMAIN_ID_XPCS5 321 -#define SCP_RESET_DOMAIN_ID_XPCS6 322 -#define SCP_RESET_DOMAIN_ID_XPCS7 323 +#define SCP_RESET_DOMAIN_ID_XPCS0 0x30 +#define SCP_RESET_DOMAIN_ID_XPCS1 0x31 +#define SCP_RESET_DOMAIN_ID_XPCS2 0x32 +#define SCP_RESET_DOMAIN_ID_XPCS3 0x33 +#define SCP_RESET_DOMAIN_ID_XPCS4 0x34 +#define SCP_RESET_DOMAIN_ID_XPCS5 0x35 +#define SCP_RESET_DOMAIN_ID_XPCS6 0x36 +#define SCP_RESET_DOMAIN_ID_XPCS7 0x37 -#define SCP_RESET_DOMAIN_ID_MPPHY01 344 -#define SCP_RESET_DOMAIN_ID_MPPHY11 345 -#define SCP_RESET_DOMAIN_ID_MPPHY21 346 -#define SCP_RESET_DOMAIN_ID_MPPHY31 347 -#define SCP_RESET_DOMAIN_ID_MPPHY02 348 +#define SCP_RESET_DOMAIN_ID_MPPHY01 0x64 +#define SCP_RESET_DOMAIN_ID_MPPHY11 0x65 +#define SCP_RESET_DOMAIN_ID_MPPHY21 0x66 +#define SCP_RESET_DOMAIN_ID_MPPHY31 0x67 +#define SCP_RESET_DOMAIN_ID_MPPHY02 0x68 #endif /* __DT_BINDINGS_R8A78000_SCMI_RESET_H__ */ -- cgit v1.3.1 From 9d47a5a4d56069915c758c06b0b22b659546f04b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 19 May 2026 16:28:15 +0200 Subject: arm: renesas: Add Renesas R-Car R8A78000 X5H Cortex-M33 RSIP port Add support for building U-Boot for Cortex-M33 RSIP core in Renesas R-Car Gen5 R8A78000 X5H SoC. The main goal is to start U-Boot on the Cortex-M33 RSIP core, which initializes the hardware and then starts the Cortex-M33 SCP and Cortex-A720 cores which run the SCP firmware and applications software respectively. The SCP is responsible for platform resource management, and is used to start other CPU cores. The Cortex-M33 build contains its own r8a78000_ironhide_cm33_defconfig which configures the build for aarch32 instruction set compatible with the ARMv8M core. The build also uses -cm33 DT and -u-boot.dtsi which are derived from their non-CM33 counterparts, and add CM33 specifics. The arch/arm/mach-renesas/u-boot-rsip.lds is derived from generic arch/arm/cpu/u-boot.lds with adjustments to cater to the RSIP core, those are entrypoint before vectors, __data_start/__data_end symbols for data-only relocation, and placement of BSS into read-write SRAM area. Signed-off-by: Marek Vasut --- arch/arm/dts/Makefile | 3 + arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi | 130 ++ arch/arm/dts/r8a78000-ironhide-cm33.dts | 8 + arch/arm/mach-renesas/u-boot-rsip.lds | 203 +++ board/renesas/common/Makefile | 4 + board/renesas/common/gen5-cm33.c | 1409 ++++++++++++++++ board/renesas/common/gen5-cm33.h | 2001 +++++++++++++++++++++++ configs/r8a78000_ironhide_cm33_defconfig | 80 + include/configs/rcar-gen5-common.h | 4 + 9 files changed, 3842 insertions(+) create mode 100644 arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi create mode 100644 arch/arm/dts/r8a78000-ironhide-cm33.dts create mode 100644 arch/arm/mach-renesas/u-boot-rsip.lds create mode 100644 board/renesas/common/gen5-cm33.c create mode 100644 board/renesas/common/gen5-cm33.h create mode 100644 configs/r8a78000_ironhide_cm33_defconfig (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 820fd6002bd..3cbb1f14d25 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -899,6 +899,9 @@ dtb-$(CONFIG_RZA1) += \ r7s72100-genmai.dtb \ r7s72100-gr-peach.dtb +dtb-$(CONFIG_RCAR_GEN5) += \ + r8a78000-ironhide-cm33.dtb + dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb diff --git a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi new file mode 100644 index 00000000000..2d4cdbac62a --- /dev/null +++ b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source extras for U-Boot for the Ironhide CM33 board + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include "r8a78000-ironhide-u-boot.dtsi" + +/ { + model = "Renesas Ironhide board CM33 based on r8a78000"; + compatible = "renesas,ironhide-cm33", "renesas,r8a78000-cm33"; + + aliases { + serial1 = &hscif1; + }; + + chosen { + stdout-path = "serial1:1843200n8"; + }; + + /delete-node/ firmware; + /delete-node/ memory@40000000; + /delete-node/ memory@60600000; + /delete-node/ memory@1080000000; + /delete-node/ memory@1200000000; + /delete-node/ memory@1400000000; + /delete-node/ memory@1600000000; + /delete-node/ memory@1800000000; + /delete-node/ memory@1a00000000; + /delete-node/ memory@1c00000000; + /delete-node/ memory@1e00000000; + /delete-node/ reserved-memory; + + memory@b8400000 { + device_type = "memory"; + reg = <0x0 0xb8400000 0x0 0x00200000>; + }; + + dummy_clk_rclk: dummy-clk-rclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + dummy_clk_sasyncd4_rt: dummy-clk-sasyncd4-rt { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16660000>; + }; + + ctl: syscon@5fffd000 { + compatible = "renesas,r8a78000-ctl", + "renesas,rcar-gen5-ctl", + "syscon"; + reg = <0 0x5fffd000 0 0xc4>; + }; + + watchdog@5fffd800 { + compatible = "renesas,r8a78000-wwdt", + "renesas,rcar-gen5-wwdt"; + clocks = <&dummy_clk_rclk>, <&dummy_clk_sasyncd4_rt>; + clock-names = "cnt", "bus"; + reg = <0 0x5fffd800 0 0x10>; + syscon = <&ctl>; + }; + + scp@c1340000 { + compatible = "renesas,r8a78000-rproc"; + reg = <0 0xc1340000 0 0x80000>; + }; +}; + +&cpg { + /delete-property/ firmware; +}; + +ð_pcs { + /* Stub clock */ + clocks = <&dummy_clk_rclk>; +}; + +&hscif1 { + pinctrl-0 = <&hscif1_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; +}; + +&mdlc_hscn { + /delete-property/ firmware; +}; + +&mdlc_pere { + /delete-property/ firmware; +}; + +&mmc0 { + status = "disabled"; +}; + +&mp_phy { + /* Stub clock */ + clocks = <&dummy_clk_rclk>; +}; + +&pfc { + hscif1_pins: hscif1 { + groups = "hscif1_data", "hscif1_ctrl"; + function = "hscif1"; + }; +}; + +&rswitch3 { + /* Stub clock */ + clocks = <&dummy_clk_rclk>; +}; + +&soc { + dma-ranges = <0 0x00000000 0 0xa0000000 0 0x20000000>; +}; + +&ufs0 { + /delete-property/ power-domains; +}; + +&ufs1 { + /delete-property/ power-domains; + status = "disabled"; +}; diff --git a/arch/arm/dts/r8a78000-ironhide-cm33.dts b/arch/arm/dts/r8a78000-ironhide-cm33.dts new file mode 100644 index 00000000000..79ad844165c --- /dev/null +++ b/arch/arm/dts/r8a78000-ironhide-cm33.dts @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the Ironhide CM33 board + * + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include "../../../dts/upstream/src/arm64/renesas/r8a78000-ironhide.dts" diff --git a/arch/arm/mach-renesas/u-boot-rsip.lds b/arch/arm/mach-renesas/u-boot-rsip.lds new file mode 100644 index 00000000000..c5a74f8a608 --- /dev/null +++ b/arch/arm/mach-renesas/u-boot-rsip.lds @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + */ + +#include +#include + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ +#if defined(CONFIG_ARMV7_SECURE_BASE) && defined(CONFIG_ARMV7_NONSEC) + /* + * If CONFIG_ARMV7_SECURE_BASE is true, secure code will not + * bundle with u-boot, and code offsets are fixed. Secure zone + * only needs to be copied from the loading address to + * CONFIG_ARMV7_SECURE_BASE, which is the linking and running + * address for secure code. + * + * If CONFIG_ARMV7_SECURE_BASE is undefined, the secure zone will + * be included in u-boot address space, and some absolute address + * were used in secure code. The absolute addresses of the secure + * code also needs to be relocated along with the accompanying u-boot + * code. + * + * So DISCARD is only for CONFIG_ARMV7_SECURE_BASE. + */ + /DISCARD/ : { *(.rel._secure*) } +#endif + . = 0x00000000; + + . = ALIGN(4); + __image_copy_start = ADDR(.text); + .text : + { + CPUDIR/start.o (.text*) + *(.vectors) + } + + /* This needs to come before *(.text*) */ + .efi_runtime : { + __efi_runtime_start = .; + *(.text.efi_runtime*) + *(.rodata.efi_runtime*) + *(.data.efi_runtime*) + __efi_runtime_stop = .; + } + + .text_rest : + { + *(.text*) + } + +#ifdef CONFIG_ARMV7_NONSEC + + /* Align the secure section only if we're going to use it in situ */ + .__secure_start +#ifndef CONFIG_ARMV7_SECURE_BASE + ALIGN(CONSTANT(COMMONPAGESIZE)) +#endif + : { + KEEP(*(.__secure_start)) + } + +#ifndef CONFIG_ARMV7_SECURE_BASE +#define __ARMV7_SECURE_BASE +#define __ARMV7_PSCI_STACK_IN_RAM +#else +#define __ARMV7_SECURE_BASE CONFIG_ARMV7_SECURE_BASE +#endif + + .secure_text __ARMV7_SECURE_BASE : + AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) + { + *(._secure.text) + } + + .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text)) + { + *(._secure.data) + } + +#ifdef CONFIG_ARMV7_PSCI + .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data), + CONSTANT(COMMONPAGESIZE)) (NOLOAD) : +#ifdef __ARMV7_PSCI_STACK_IN_RAM + AT(ADDR(.secure_stack)) +#else + AT(LOADADDR(.secure_data) + SIZEOF(.secure_data)) +#endif + { + KEEP(*(.__secure_stack_start)) + + /* Skip addresses for stack */ + . = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE; + + /* Align end of stack section to page boundary */ + . = ALIGN(CONSTANT(COMMONPAGESIZE)); + + KEEP(*(.__secure_stack_end)) + +#ifdef CONFIG_ARMV7_SECURE_MAX_SIZE + /* + * We are not checking (__secure_end - __secure_start) here, + * as these are the load addresses, and do not include the + * stack section. Instead, use the end of the stack section + * and the start of the text section. + */ + ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV7_SECURE_MAX_SIZE, + "Error: secure section exceeds secure memory size"); +#endif + } + +#ifndef __ARMV7_PSCI_STACK_IN_RAM + /* Reset VMA but don't allocate space if we have secure SRAM */ + . = LOADADDR(.secure_stack); +#endif + +#endif + + .__secure_end : AT(ADDR(.__secure_end)) { + *(.__secure_end) + LONG(0x1d1071c); /* Must output something to reset LMA */ + } +#endif + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + __data_start = .; + *(.data*) + __data_end = .; + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + __u_boot_list : { + KEEP(*(SORT(__u_boot_list*))); + } + + .efi_runtime_rel : { + __efi_runtime_rel_start = .; + *(.rel*.efi_runtime) + *(.rel*.efi_runtime.*) + __efi_runtime_rel_stop = .; + } + + . = ALIGN(8); + __image_copy_end = .; + + /* + * if CONFIG_USE_ARCH_MEMSET is not selected __bss_end - __bss_start + * needs to be a multiple of 8 and we overlay .bss with .rel.dyn + */ + .rel.dyn ALIGN(8) : { + __rel_dyn_start = .; + *(.rel*) + __rel_dyn_end = .; + . = ALIGN(8); + } + + _end = .; + _image_binary_end = .; + +/* + * These sections occupy the same memory, but their lifetimes do + * not overlap: U-Boot initializes .bss only after applying dynamic + * relocations and therefore after it doesn't need .rel.dyn any more. + */ + + /* BSS goes to special read-write offset below U-Boot entry point */ + . = 0xb8400000; + .bss (OVERLAY): { + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynbss) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu.hash) } + /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.ARM.exidx*) } + /DISCARD/ : { *(.gnu.linkonce.armexidx.*) } +} + +ASSERT(_image_binary_end % 8 == 0, \ + "_image_binary_end must be 8-byte aligned for device tree"); diff --git a/board/renesas/common/Makefile b/board/renesas/common/Makefile index 889de8ea9ac..16902d216f6 100644 --- a/board/renesas/common/Makefile +++ b/board/renesas/common/Makefile @@ -45,9 +45,13 @@ endif endif ifdef CONFIG_RCAR_GEN5 +ifdef CONFIG_RCAR_64_RSIP +obj-y += gen5-cm33.o +else obj-y += gen5-common.o endif endif +endif endif endif diff --git a/board/renesas/common/gen5-cm33.c b/board/renesas/common/gen5-cm33.c new file mode 100644 index 00000000000..e07db9817f2 --- /dev/null +++ b/board/renesas/common/gen5-cm33.c @@ -0,0 +1,1409 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gen5-cm33.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) + +#define PKC_PROT_LOCK 0xa5a5a500 +#define PKC_PROT_UNLOCK 0xa5a5a501 + +#define RSIP_BASE 0xe0000000 +#define RSIP_NVIC_ISER_00 (RSIP_BASE + 0xe100) +#define RSIP_NVIC_ISER_00_SETENA_INTIWDTA0 BIT(16) +#define RSIP_NVIC_ICER_00 (RSIP_BASE + 0xe180) +#define RSIP_NVIC_ICER_01 (RSIP_BASE + 0xe184) +#define RSIP_NVIC_ICER_02 (RSIP_BASE + 0xe188) +#define RSIP_NVIC_ICER_03 (RSIP_BASE + 0xe18c) +#define RSIP_NVIC_ICER_04 (RSIP_BASE + 0xe190) +#define RSIP_NVIC_ICER_05 (RSIP_BASE + 0xe194) +#define RSIP_NVIC_ICER_06 (RSIP_BASE + 0xe198) +#define RSIP_NVIC_ICER_07 (RSIP_BASE + 0xe19c) +#define RSIP_NVIC_ICER_08 (RSIP_BASE + 0xe1a0) +#define RSIP_NVIC_ICER_09 (RSIP_BASE + 0xe1a4) +#define RSIP_NVIC_ICER_10 (RSIP_BASE + 0xe1a8) +#define RSIP_NVIC_ICER_11 (RSIP_BASE + 0xe1ac) +#define RSIP_NVIC_ICER_12 (RSIP_BASE + 0xe1b0) +#define RSIP_NVIC_ICER_13 (RSIP_BASE + 0xe1b4) +#define RSIP_NVIC_ICER_14 (RSIP_BASE + 0xe1b8) +#define RSIP_NVIC_ICER_15 (RSIP_BASE + 0xe1bc) +#define RSIP_SHCSR (RSIP_BASE + 0xed24) +#define RSIP_SHCSR_USGFAULTENA BIT(18) +#define RSIP_SHCSR_BUSFAULTENA BIT(17) +#define RSIP_SHCSR_MEMFAULTENA BIT(16) + +#define RSIP_CTL_BASE 0x5fffd000 +#define RSIP_CTL_CFG4 (RSIP_CTL_BASE + 0xb0) +#define RSIP_CTL_CFG4_OPWDEN BIT(3) +#define RSIP_CTL_CFG4_OPWDVAC BIT(5) +#define RSIP_CTL_ESICREMAP0 (RSIP_CTL_BASE + 0x70) +#define RSIP_CTL_PROT0PCMD (RSIP_CTL_BASE + 0x840) +#define RSIP_CTL_PROT0PCMD_WREN 0xa5 +#define RSIP_CTL_PROT0PS (RSIP_CTL_BASE + 0x844) +#define RSIP_CTL_PROT0PS_ERR BIT(0) + +#define SYSSS_BASE 0xc1320000 +#define SYSSS_MODE1 (SYSSS_BASE + 0x1010) +#define SYSSS_MODE1_MASK GENMASK(11, 0) +#define SYSSS_MODE1_BAUDRATE_MASK GENMASK(10, 9) +#define SYSSS_MODE1_BAUDRATE_921600 1 +#define SYSSS_MODE1_BAUDRATE_1843200 2 +#define SYSSS_MODE1_BAUDRATE_3250000 3 +#define SYSSS_MODE1_BOOTMODE_MASK GENMASK(20, 18) +#define SYSSS_MODE1_BOOTMODE_HF_DMA 2 +#define SYSSS_MODE1_BOOTMODE_QSPI 4 +#define SYSSS_MODE1_BOOTMODE_UFS 6 + +#define CLK_CONTROL_TOP_BASE 0xc6480000 +#define CLK_CONTROL_SCP_BASE 0xc1330000 +#define CLK_CONTROL_PERE_BASE 0xc08f0000 + +#define CLK_CONTROL_PLL01_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1108) +#define CLK_CONTROL_PLL01_1_CR0 (CLK_CONTROL_TOP_BASE + 0x1114) +#define CLK_CONTROL_PLL02_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1120) +#define CLK_CONTROL_PLL02_1_CR0 (CLK_CONTROL_TOP_BASE + 0x112c) +#define CLK_CONTROL_PLL02_2_CR0 (CLK_CONTROL_TOP_BASE + 0x1138) +#define CLK_CONTROL_PLL02_3_CR0 (CLK_CONTROL_TOP_BASE + 0x1144) +#define CLK_CONTROL_PLL02_4_CR0 (CLK_CONTROL_TOP_BASE + 0x1150) +#define CLK_CONTROL_PLL02_5_CR0 (CLK_CONTROL_TOP_BASE + 0x115c) +#define CLK_CONTROL_PLL02_6_CR0 (CLK_CONTROL_TOP_BASE + 0x1168) +#define CLK_CONTROL_PLL02_7_CR0 (CLK_CONTROL_TOP_BASE + 0x1174) +#define CLK_CONTROL_PLL03_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1180) +#define CLK_CONTROL_PLL03_1_CR0 (CLK_CONTROL_TOP_BASE + 0x118c) +#define CLK_CONTROL_PLL03_2_CR0 (CLK_CONTROL_TOP_BASE + 0x1198) +#define CLK_CONTROL_PLL03_3_CR0 (CLK_CONTROL_TOP_BASE + 0x11a4) +#define CLK_CONTROL_PLL06_CR0 (CLK_CONTROL_TOP_BASE + 0x11c8) +#define CLK_CONTROL_PLL07_CR0 (CLK_CONTROL_TOP_BASE + 0x11d4) +#define CLK_CONTROL_PLL12_CR0 (CLK_CONTROL_TOP_BASE + 0x121c) +#define CLK_CONTROL_PLL13_CR0 (CLK_CONTROL_SCP_BASE + 0x1228) +#define CLK_CONTROL_PLL14_CR0 (CLK_CONTROL_TOP_BASE + 0x1234) +#define CLK_CONTROL_PLL15_0_CR0 (CLK_CONTROL_TOP_BASE + 0x1240) +#define CLK_CONTROL_PLL15_1_CR0 (CLK_CONTROL_TOP_BASE + 0x124c) +#define CLK_CONTROL_PLL15_2_CR0 (CLK_CONTROL_TOP_BASE + 0x1258) +#define CLK_CONTROL_PLL15_3_CR0 (CLK_CONTROL_TOP_BASE + 0x1264) +#define CLK_CONTROL_PLL01_0_CR1 (CLK_CONTROL_TOP_BASE + 0x110c) +#define CLK_CONTROL_PLL01_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1118) +#define CLK_CONTROL_PLL02_0_CR1 (CLK_CONTROL_TOP_BASE + 0x1124) +#define CLK_CONTROL_PLL02_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1130) +#define CLK_CONTROL_PLL02_2_CR1 (CLK_CONTROL_TOP_BASE + 0x113c) +#define CLK_CONTROL_PLL02_3_CR1 (CLK_CONTROL_TOP_BASE + 0x1148) +#define CLK_CONTROL_PLL02_4_CR1 (CLK_CONTROL_TOP_BASE + 0x1154) +#define CLK_CONTROL_PLL02_5_CR1 (CLK_CONTROL_TOP_BASE + 0x1160) +#define CLK_CONTROL_PLL02_6_CR1 (CLK_CONTROL_TOP_BASE + 0x116c) +#define CLK_CONTROL_PLL02_7_CR1 (CLK_CONTROL_TOP_BASE + 0x1178) +#define CLK_CONTROL_PLL03_0_CR1 (CLK_CONTROL_TOP_BASE + 0x1184) +#define CLK_CONTROL_PLL03_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1190) +#define CLK_CONTROL_PLL03_2_CR1 (CLK_CONTROL_TOP_BASE + 0x119c) +#define CLK_CONTROL_PLL03_3_CR1 (CLK_CONTROL_TOP_BASE + 0x11a8) +#define CLK_CONTROL_PLL06_CR1 (CLK_CONTROL_TOP_BASE + 0x11cc) +#define CLK_CONTROL_PLL07_CR1 (CLK_CONTROL_TOP_BASE + 0x11d8) +#define CLK_CONTROL_PLL12_CR1 (CLK_CONTROL_TOP_BASE + 0x1220) +#define CLK_CONTROL_PLL13_CR1 (CLK_CONTROL_SCP_BASE + 0x122c) +#define CLK_CONTROL_PLL14_CR1 (CLK_CONTROL_TOP_BASE + 0x1238) +#define CLK_CONTROL_PLL15_0_CR1 (CLK_CONTROL_TOP_BASE + 0x1244) +#define CLK_CONTROL_PLL15_1_CR1 (CLK_CONTROL_TOP_BASE + 0x1250) +#define CLK_CONTROL_PLL15_2_CR1 (CLK_CONTROL_TOP_BASE + 0x125c) +#define CLK_CONTROL_PLL15_3_CR1 (CLK_CONTROL_TOP_BASE + 0x1268) +#define CLK_CONTROL_PLL01_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1110) +#define CLK_CONTROL_PLL01_1_CR2 (CLK_CONTROL_TOP_BASE + 0x111c) +#define CLK_CONTROL_PLL02_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1128) +#define CLK_CONTROL_PLL02_1_CR2 (CLK_CONTROL_TOP_BASE + 0x1134) +#define CLK_CONTROL_PLL02_2_CR2 (CLK_CONTROL_TOP_BASE + 0x1140) +#define CLK_CONTROL_PLL02_3_CR2 (CLK_CONTROL_TOP_BASE + 0x114c) +#define CLK_CONTROL_PLL02_4_CR2 (CLK_CONTROL_TOP_BASE + 0x1158) +#define CLK_CONTROL_PLL02_5_CR2 (CLK_CONTROL_TOP_BASE + 0x1164) +#define CLK_CONTROL_PLL02_6_CR2 (CLK_CONTROL_TOP_BASE + 0x1170) +#define CLK_CONTROL_PLL02_7_CR2 (CLK_CONTROL_TOP_BASE + 0x117c) +#define CLK_CONTROL_PLL03_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1188) +#define CLK_CONTROL_PLL03_1_CR2 (CLK_CONTROL_TOP_BASE + 0x1194) +#define CLK_CONTROL_PLL03_2_CR2 (CLK_CONTROL_TOP_BASE + 0x11a0) +#define CLK_CONTROL_PLL03_3_CR2 (CLK_CONTROL_TOP_BASE + 0x11ac) +#define CLK_CONTROL_PLL06_CR2 (CLK_CONTROL_TOP_BASE + 0x11d0) +#define CLK_CONTROL_PLL07_CR2 (CLK_CONTROL_TOP_BASE + 0x11dc) +#define CLK_CONTROL_PLL12_CR2 (CLK_CONTROL_TOP_BASE + 0x1224) +#define CLK_CONTROL_PLL13_CR2 (CLK_CONTROL_SCP_BASE + 0x1230) +#define CLK_CONTROL_PLL14_CR2 (CLK_CONTROL_TOP_BASE + 0x123c) +#define CLK_CONTROL_PLL15_0_CR2 (CLK_CONTROL_TOP_BASE + 0x1248) +#define CLK_CONTROL_PLL15_1_CR2 (CLK_CONTROL_TOP_BASE + 0x1254) +#define CLK_CONTROL_PLL15_2_CR2 (CLK_CONTROL_TOP_BASE + 0x1260) +#define CLK_CONTROL_PLL15_3_CR2 (CLK_CONTROL_TOP_BASE + 0x126c) +#define CLK_CONTROL_PLL01_0_SCR (CLK_CONTROL_TOP_BASE + 0x1270) +#define CLK_CONTROL_PLL01_1_SCR (CLK_CONTROL_TOP_BASE + 0x1278) +#define CLK_CONTROL_PLL02_0_SCR (CLK_CONTROL_TOP_BASE + 0x1280) +#define CLK_CONTROL_PLL02_1_SCR (CLK_CONTROL_TOP_BASE + 0x1288) +#define CLK_CONTROL_PLL02_2_SCR (CLK_CONTROL_TOP_BASE + 0x1290) +#define CLK_CONTROL_PLL02_3_SCR (CLK_CONTROL_TOP_BASE + 0x1298) +#define CLK_CONTROL_PLL02_4_SCR (CLK_CONTROL_TOP_BASE + 0x12a0) +#define CLK_CONTROL_PLL02_5_SCR (CLK_CONTROL_TOP_BASE + 0x12a8) +#define CLK_CONTROL_PLL02_6_SCR (CLK_CONTROL_TOP_BASE + 0x12b0) +#define CLK_CONTROL_PLL02_7_SCR (CLK_CONTROL_TOP_BASE + 0x12b8) +#define CLK_CONTROL_PLL03_0_SCR (CLK_CONTROL_TOP_BASE + 0x12c0) +#define CLK_CONTROL_PLL03_1_SCR (CLK_CONTROL_TOP_BASE + 0x12c8) +#define CLK_CONTROL_PLL03_2_SCR (CLK_CONTROL_TOP_BASE + 0x12d0) +#define CLK_CONTROL_PLL03_3_SCR (CLK_CONTROL_TOP_BASE + 0x12d8) +#define CLK_CONTROL_PLL06_SCR (CLK_CONTROL_TOP_BASE + 0x12f0) +#define CLK_CONTROL_PLL07_SCR (CLK_CONTROL_TOP_BASE + 0x12f8) +#define CLK_CONTROL_PLL12_SCR (CLK_CONTROL_TOP_BASE + 0x1328) +#define CLK_CONTROL_PLL13_SCR (CLK_CONTROL_SCP_BASE + 0x1330) +#define CLK_CONTROL_PLL14_SCR (CLK_CONTROL_TOP_BASE + 0x1338) +#define CLK_CONTROL_PLL15_0_SCR (CLK_CONTROL_TOP_BASE + 0x1340) +#define CLK_CONTROL_PLL15_1_SCR (CLK_CONTROL_TOP_BASE + 0x1348) +#define CLK_CONTROL_PLL15_2_SCR (CLK_CONTROL_TOP_BASE + 0x1350) +#define CLK_CONTROL_PLL15_3_SCR (CLK_CONTROL_TOP_BASE + 0x1358) +#define CLK_CONTROL_PLL01_0_DCR (CLK_CONTROL_TOP_BASE + 0x1274) +#define CLK_CONTROL_PLL01_1_DCR (CLK_CONTROL_TOP_BASE + 0x127c) +#define CLK_CONTROL_PLL02_0_DCR (CLK_CONTROL_TOP_BASE + 0x1284) +#define CLK_CONTROL_PLL02_1_DCR (CLK_CONTROL_TOP_BASE + 0x128c) +#define CLK_CONTROL_PLL02_2_DCR (CLK_CONTROL_TOP_BASE + 0x1294) +#define CLK_CONTROL_PLL02_3_DCR (CLK_CONTROL_TOP_BASE + 0x129c) +#define CLK_CONTROL_PLL02_4_DCR (CLK_CONTROL_TOP_BASE + 0x12a4) +#define CLK_CONTROL_PLL02_5_DCR (CLK_CONTROL_TOP_BASE + 0x12ac) +#define CLK_CONTROL_PLL02_6_DCR (CLK_CONTROL_TOP_BASE + 0x12b4) +#define CLK_CONTROL_PLL02_7_DCR (CLK_CONTROL_TOP_BASE + 0x12bc) +#define CLK_CONTROL_PLL03_0_DCR (CLK_CONTROL_TOP_BASE + 0x12c4) +#define CLK_CONTROL_PLL03_1_DCR (CLK_CONTROL_TOP_BASE + 0x12cc) +#define CLK_CONTROL_PLL03_2_DCR (CLK_CONTROL_TOP_BASE + 0x12d4) +#define CLK_CONTROL_PLL03_3_DCR (CLK_CONTROL_TOP_BASE + 0x12dc) +#define CLK_CONTROL_PLL06_DCR (CLK_CONTROL_TOP_BASE + 0x12f4) +#define CLK_CONTROL_PLL07_DCR (CLK_CONTROL_TOP_BASE + 0x12fc) +#define CLK_CONTROL_PLL12_DCR (CLK_CONTROL_TOP_BASE + 0x132c) +#define CLK_CONTROL_PLL13_DCR (CLK_CONTROL_SCP_BASE + 0x1334) +#define CLK_CONTROL_PLL14_DCR (CLK_CONTROL_TOP_BASE + 0x133c) +#define CLK_CONTROL_PLL15_0_DCR (CLK_CONTROL_TOP_BASE + 0x1344) +#define CLK_CONTROL_PLL15_1_DCR (CLK_CONTROL_TOP_BASE + 0x134c) +#define CLK_CONTROL_PLL15_2_DCR (CLK_CONTROL_TOP_BASE + 0x1354) +#define CLK_CONTROL_PLL15_3_DCR (CLK_CONTROL_TOP_BASE + 0x135c) +#define CLK_CONTROL_RPCCKCR (CLK_CONTROL_PERE_BASE + 0x1030) +#define CLK_CONTROL_RPCCKCR_CKSTP1 BIT(8) +#define CLK_CONTROL_RPCCKCR_RPCFC_MASK GENMASK(4, 0) +#define CLK_CONTROL_PROT_REG_MASK 0xffff +#define CLK_CONTROL_PROT_REG 0x1370 + +#define CLK_CONTROL_PLL_CR2_PLLCLKSTAB BIT(31) +#define CLK_CONTROL_PLL_CR2_PLLDISTRG BIT(29) +#define CLK_CONTROL_PLL_CR2_PLLENTRG BIT(28) +#define CLK_CONTROL_PLL_SCR_SELID_CLK_IOSC BIT(0) +#define CLK_CONTROL_PLL_SCR_SELACT_MASK BIT(16) +#define CLK_CONTROL_PLL_DCR_PLLDIVSYNC BIT(16) + +/** + * sysss_read_modemr() - Read MODE Register 1 + * @return: MD[11:0] pin state + */ +static u32 sysss_read_modemr(void) +{ + return readl(SYSSS_MODE1) & SYSSS_MODE1_MASK; +} + +/** + * clk_control_poll_cr2() - Poll CR2 until PLL is stable + * @cr2: PLL CR2 register address + */ +static void clk_control_poll_cr2(const u32 cr2) +{ + u32 val; + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(cr2); + if (val & CLK_CONTROL_PLL_CR2_PLLCLKSTAB) + break; + } +} + +/** + * clk_control_write_cr() - Write protected clock controller register + * @reg: Register address + * @val: Value to be written + */ +static void clk_control_write_cr(const u32 reg, const u32 val) +{ + const u32 protreg = (reg & ~CLK_CONTROL_PROT_REG_MASK) | CLK_CONTROL_PROT_REG; + + writel(PKC_PROT_UNLOCK, protreg); + writel(val, reg); + writel(PKC_PROT_LOCK, protreg); +} + +/** + * clk_control_write_and_poll_dcr() - Write and poll DCR + * @dcr: DCR register address + * @val: Value to be written + */ +static void clk_control_write_and_poll_dcr(const u32 dcr, const u32 val) +{ + u32 tmp; + + clk_control_write_cr(dcr, val); + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + tmp = readl(dcr); + if (tmp & CLK_CONTROL_PLL_DCR_PLLDIVSYNC) + break; + } +} + +/** + * clk_control_switch_from_iosc_to_pll() - Switch clock from internal oscillator to PLL + * @cr2: PLL CR2 register address + * @scr: PLL SCR register address + */ +static void clk_control_switch_from_iosc_to_pll(const u32 cr2, const u32 scr) +{ + u32 val; + + clk_control_poll_cr2(cr2); + + /* Switch from internal oscillator to PLL. */ + val = readl(scr); + val &= ~CLK_CONTROL_PLL_SCR_SELID_CLK_IOSC; + clk_control_write_cr(scr, val); + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(scr); + if (!(val & CLK_CONTROL_PLL_SCR_SELACT_MASK)) + break; + } +} + +/** + * clk_control_switch_from_pll_to_iosc() - Switch clock from PLL to internal oscillator + * @cr2: PLL CR2 register address + * @scr: PLL SCR register address + */ +static void clk_control_switch_from_pll_to_iosc(const u32 cr2, const u32 scr) +{ + u32 val; + + clk_control_poll_cr2(cr2); + + /* Switch from PLL to internal oscillator. */ + clk_control_write_cr(scr, CLK_CONTROL_PLL_SCR_SELID_CLK_IOSC); + + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(scr); + if (val & CLK_CONTROL_PLL_SCR_SELACT_MASK) + break; + } +} + +/** + * clk_control_set_pll_freq() - Set PLL frequency + * @cr0: PLL CR0 register address + * @cr1: PLL CR1 register address + * @cr2: PLL CR2 register address + * @scr: PLL SCR register address + * @dcr: PLL DCR register address + * @cr0_val: PLL CR0 register value + * @cr1_val: PLL CR1 register value + * @dcr_val: PLL DCR register value + */ +static void clk_control_set_pll_freq(const u32 cr0, const u32 cr1, const u32 cr2, + const u32 scr, const u32 dcr, const u32 cr0_val, + const u32 cr1_val, const u32 dcr_val) +{ + u32 val; + + clk_control_switch_from_pll_to_iosc(cr2, scr); + + /* Disable PLL trigger and wait until it unlocks */ + clk_control_write_cr(cr2, CLK_CONTROL_PLL_CR2_PLLDISTRG); + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (;;) { + val = readl(cr2); + if (!(val & CLK_CONTROL_PLL_CR2_PLLCLKSTAB)) + break; + } + + clk_control_write_cr(cr0, cr0_val); + clk_control_write_cr(cr1, cr1_val); + clk_control_write_cr(dcr, dcr_val); + + /* Enable PLL */ + clk_control_write_cr(cr2, CLK_CONTROL_PLL_CR2_PLLENTRG); +} + +/** + * clk_control_set_pll() - Load configuration into PLLs + */ +static void clk_control_set_pll(void) +{ + /* Switch PLLs to internal oscillator and configure dividers. */ + clk_control_set_pll_freq(CLK_CONTROL_PLL01_0_CR0, CLK_CONTROL_PLL01_0_CR1, + CLK_CONTROL_PLL01_0_CR2, CLK_CONTROL_PLL01_0_SCR, + CLK_CONTROL_PLL01_0_DCR, 0x06500000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL01_1_CR0, CLK_CONTROL_PLL01_1_CR1, + CLK_CONTROL_PLL01_1_CR2, CLK_CONTROL_PLL01_1_SCR, + CLK_CONTROL_PLL01_1_DCR, 0x04c00000, 0x00000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL02_0_CR0, CLK_CONTROL_PLL02_0_CR1, + CLK_CONTROL_PLL02_0_CR2, CLK_CONTROL_PLL02_0_SCR, + CLK_CONTROL_PLL02_0_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_1_CR0, CLK_CONTROL_PLL02_1_CR1, + CLK_CONTROL_PLL02_1_CR2, CLK_CONTROL_PLL02_1_SCR, + CLK_CONTROL_PLL02_1_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_2_CR0, CLK_CONTROL_PLL02_2_CR1, + CLK_CONTROL_PLL02_2_CR2, CLK_CONTROL_PLL02_2_SCR, + CLK_CONTROL_PLL02_2_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_3_CR0, CLK_CONTROL_PLL02_3_CR1, + CLK_CONTROL_PLL02_3_CR2, CLK_CONTROL_PLL02_3_SCR, + CLK_CONTROL_PLL02_3_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_4_CR0, CLK_CONTROL_PLL02_4_CR1, + CLK_CONTROL_PLL02_4_CR2, CLK_CONTROL_PLL02_4_SCR, + CLK_CONTROL_PLL02_4_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_5_CR0, CLK_CONTROL_PLL02_5_CR1, + CLK_CONTROL_PLL02_5_CR2, CLK_CONTROL_PLL02_5_SCR, + CLK_CONTROL_PLL02_5_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_6_CR0, CLK_CONTROL_PLL02_6_CR1, + CLK_CONTROL_PLL02_6_CR2, CLK_CONTROL_PLL02_6_SCR, + CLK_CONTROL_PLL02_6_DCR, 0x08900000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL02_7_CR0, CLK_CONTROL_PLL02_7_CR1, + CLK_CONTROL_PLL02_7_CR2, CLK_CONTROL_PLL02_7_SCR, + CLK_CONTROL_PLL02_7_DCR, 0x08900000, 0x04000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL03_0_CR0, CLK_CONTROL_PLL03_0_CR1, + CLK_CONTROL_PLL03_0_CR2, CLK_CONTROL_PLL03_0_SCR, + CLK_CONTROL_PLL03_0_DCR, 0x05f00000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL03_1_CR0, CLK_CONTROL_PLL03_1_CR1, + CLK_CONTROL_PLL03_1_CR2, CLK_CONTROL_PLL03_1_SCR, + CLK_CONTROL_PLL03_1_DCR, 0x05f00000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL03_2_CR0, CLK_CONTROL_PLL03_2_CR1, + CLK_CONTROL_PLL03_2_CR2, CLK_CONTROL_PLL03_2_SCR, + CLK_CONTROL_PLL03_2_DCR, 0x05f00000, 0x00000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL03_3_CR0, CLK_CONTROL_PLL03_3_CR1, + CLK_CONTROL_PLL03_3_CR2, CLK_CONTROL_PLL03_3_SCR, + CLK_CONTROL_PLL03_3_DCR, 0x05f00000, 0x00000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL06_CR0, CLK_CONTROL_PLL06_CR1, + CLK_CONTROL_PLL06_CR2, CLK_CONTROL_PLL06_SCR, + CLK_CONTROL_PLL06_DCR, 0x0a700000, 0x0c000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL07_CR0, CLK_CONTROL_PLL07_CR1, + CLK_CONTROL_PLL07_CR2, CLK_CONTROL_PLL07_SCR, + CLK_CONTROL_PLL07_DCR, 0x09500000, 0x08000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL12_CR0, CLK_CONTROL_PLL12_CR1, + CLK_CONTROL_PLL12_CR2, CLK_CONTROL_PLL12_SCR, + CLK_CONTROL_PLL12_DCR, 0x0a400000, 0x0c000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL13_CR0, CLK_CONTROL_PLL13_CR1, + CLK_CONTROL_PLL13_CR2, CLK_CONTROL_PLL13_SCR, + CLK_CONTROL_PLL13_DCR, 0x08f00000, 0x08000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL14_CR0, CLK_CONTROL_PLL14_CR1, + CLK_CONTROL_PLL14_CR2, CLK_CONTROL_PLL14_SCR, + CLK_CONTROL_PLL14_DCR, 0x04700000, 0x00000000, 0x18); + + clk_control_set_pll_freq(CLK_CONTROL_PLL15_0_CR0, CLK_CONTROL_PLL15_0_CR1, + CLK_CONTROL_PLL15_0_CR2, CLK_CONTROL_PLL15_0_SCR, + CLK_CONTROL_PLL15_0_DCR, 0x07700000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL15_1_CR0, CLK_CONTROL_PLL15_1_CR1, + CLK_CONTROL_PLL15_1_CR2, CLK_CONTROL_PLL15_1_SCR, + CLK_CONTROL_PLL15_1_DCR, 0x07700000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL15_2_CR0, CLK_CONTROL_PLL15_2_CR1, + CLK_CONTROL_PLL15_2_CR2, CLK_CONTROL_PLL15_2_SCR, + CLK_CONTROL_PLL15_2_DCR, 0x07700000, 0x04000000, 0x18); + clk_control_set_pll_freq(CLK_CONTROL_PLL15_3_CR0, CLK_CONTROL_PLL15_3_CR1, + CLK_CONTROL_PLL15_3_CR2, CLK_CONTROL_PLL15_3_SCR, + CLK_CONTROL_PLL15_3_DCR, 0x07700000, 0x04000000, 0x18); + + /* Switch PLLs back and wait for them to stabilize. */ + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_0_CR2, CLK_CONTROL_PLL01_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_1_CR2, CLK_CONTROL_PLL01_1_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_0_CR2, CLK_CONTROL_PLL02_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_1_CR2, CLK_CONTROL_PLL02_1_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_2_CR2, CLK_CONTROL_PLL02_2_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_3_CR2, CLK_CONTROL_PLL02_3_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_4_CR2, CLK_CONTROL_PLL02_4_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_5_CR2, CLK_CONTROL_PLL02_5_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_6_CR2, CLK_CONTROL_PLL02_6_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL02_7_CR2, CLK_CONTROL_PLL02_7_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_0_CR2, CLK_CONTROL_PLL03_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_1_CR2, CLK_CONTROL_PLL03_1_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_2_CR2, CLK_CONTROL_PLL03_2_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL03_3_CR2, CLK_CONTROL_PLL03_3_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL06_CR2, CLK_CONTROL_PLL06_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL07_CR2, CLK_CONTROL_PLL07_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL12_CR2, CLK_CONTROL_PLL12_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL13_CR2, CLK_CONTROL_PLL13_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL14_CR2, CLK_CONTROL_PLL14_SCR); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_0_CR2, CLK_CONTROL_PLL15_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_1_CR2, CLK_CONTROL_PLL15_1_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_2_CR2, CLK_CONTROL_PLL15_2_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL15_3_CR2, CLK_CONTROL_PLL15_3_SCR); + + /* Write second-stage DCR */ + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_1_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_1_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_2_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_3_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_4_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_5_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_6_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_7_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_1_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_2_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_3_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL06_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL07_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL12_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL13_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL14_DCR, 0x10); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_0_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_1_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_2_DCR, 0x10); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_3_DCR, 0x10); + + udelay(25); + + /* Write third-stage DCR */ + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL01_1_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_1_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_2_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_3_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_4_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_5_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_6_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL02_7_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_1_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_2_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL03_3_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL06_DCR, 0x10); /* 1/2 */ + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL07_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL12_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL13_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL14_DCR, 0x00); + + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_0_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_1_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_2_DCR, 0x00); + clk_control_write_and_poll_dcr(CLK_CONTROL_PLL15_3_DCR, 0x00); + + udelay(25); +} + +#define MDLC_PERW_BASE 0xc05d0000 +#define MDLC_PERE_BASE 0xc08f0000 +#define MDLC_HSCN_BASE 0xc9c90000 +/* The addresses in range 0x08000000..0x1fffffff are incremented by 0xa0000000 */ +#define MDLC_RT_BASE 0xb9440000 +#define MDLC_SCP_BASE 0xc1330000 + +#define MDLC_SCP_MSRES02 (MDLC_SCP_BASE + 0x908) +#define MDLC_SCP_MSRESS02 (MDLC_SCP_BASE + 0x968) +#define MDLC_SCP_MSRES02_SCP_MASK GENMASK(1, 0) +#define MDLC_SCP_PKCPROT1 (MDLC_SCP_BASE + 0xcf4) + +#define MDLC_PERW_MSRES05 (MDLC_PERW_BASE + 0x914) +#define MDLC_PERW_MSRESS05 (MDLC_PERW_BASE + 0x974) +#define MDLC_PERW_MSRES05_HSCIF0_MASK GENMASK(9, 8) +#define MDLC_PERW_MSRES05_HSCIF1_MASK GENMASK(11, 10) +#define MDLC_MSRESS_STANDBY 0 +#define MDLC_MSRESS_RESET 1 +#define MDLC_MSRESS_STOP 2 +#define MDLC_MSRESS_RUN 3 +#define MDLC_PERW_PKCPROT1 (MDLC_PERW_BASE + 0xcf4) + +#define MDLC_MPG_GATING 0 +#define MDLC_MPG_RESET 1 +#define MDLC_MPG_RUN 3 + +#define MDLC_PERE_MPIER (MDLC_PERE_BASE + 0x110) +#define MDLC_PERE_MPIMR (MDLC_PERE_BASE + 0x120) +#define MDLC_PERE_MPDG00 (MDLC_PERE_BASE + 0x200) +#define MDLC_PERE_MPDG01 (MDLC_PERE_BASE + 0x204) +#define MDLC_PERE_MPDGS00 (MDLC_PERE_BASE + 0x300) +#define MDLC_PERE_MPDGS01 (MDLC_PERE_BASE + 0x304) +#define MDLC_PERE_MSRES06 (MDLC_PERE_BASE + 0x918) +#define MDLC_PERE_MSRESS06 (MDLC_PERE_BASE + 0x978) +#define MDLC_PERE_PKCPROT0 (MDLC_PERE_BASE + 0xcf0) +#define MDLC_PERE_PKCPROT1 (MDLC_PERE_BASE + 0xcf4) +#define MDLC_PERE_MSRES06_UFS0_MASK GENMASK(1, 0) +#define MDLC_PERE_MSRES06_UFS1_MASK GENMASK(3, 2) + +#define MDLC_HSCN_MPIER (MDLC_HSCN_BASE + 0x110) +#define MDLC_HSCN_MPIMR (MDLC_HSCN_BASE + 0x120) +#define MDLC_HSCN_MPDG00 (MDLC_HSCN_BASE + 0x200) +#define MDLC_HSCN_MPDG01 (MDLC_HSCN_BASE + 0x204) +#define MDLC_HSCN_MPDG02 (MDLC_HSCN_BASE + 0x208) +#define MDLC_HSCN_MPDG03 (MDLC_HSCN_BASE + 0x20c) +#define MDLC_HSCN_MPDG04 (MDLC_HSCN_BASE + 0x210) +#define MDLC_HSCN_MPDG05 (MDLC_HSCN_BASE + 0x214) +#define MDLC_HSCN_MPDG06 (MDLC_HSCN_BASE + 0x218) +#define MDLC_HSCN_MPDGS00 (MDLC_HSCN_BASE + 0x300) +#define MDLC_HSCN_MPDGS01 (MDLC_HSCN_BASE + 0x304) +#define MDLC_HSCN_MPDGS02 (MDLC_HSCN_BASE + 0x308) +#define MDLC_HSCN_MPDGS03 (MDLC_HSCN_BASE + 0x30c) +#define MDLC_HSCN_MPDGS04 (MDLC_HSCN_BASE + 0x310) +#define MDLC_HSCN_MPDGS05 (MDLC_HSCN_BASE + 0x314) +#define MDLC_HSCN_MPDGS06 (MDLC_HSCN_BASE + 0x318) +#define MDLC_HSCN_PKCPROT0 (MDLC_HSCN_BASE + 0xcf0) + +#define MDLC_RT_MPIER (MDLC_RT_BASE + 0x110) +#define MDLC_RT_MPIMR (MDLC_RT_BASE + 0x120) +#define MDLC_RT_MPDG00 (MDLC_RT_BASE + 0x200) +#define MDLC_RT_MPDG01 (MDLC_RT_BASE + 0x204) +#define MDLC_RT_MPDG02 (MDLC_RT_BASE + 0x208) +#define MDLC_RT_MPDG03 (MDLC_RT_BASE + 0x20c) +#define MDLC_RT_MPDG04 (MDLC_RT_BASE + 0x210) +#define MDLC_RT_MPDG05 (MDLC_RT_BASE + 0x214) +#define MDLC_RT_MPDG06 (MDLC_RT_BASE + 0x218) +#define MDLC_RT_MPDG07 (MDLC_RT_BASE + 0x21c) +#define MDLC_RT_MPDG08 (MDLC_RT_BASE + 0x220) +#define MDLC_RT_MPDG09 (MDLC_RT_BASE + 0x224) +#define MDLC_RT_MPDG10 (MDLC_RT_BASE + 0x228) +#define MDLC_RT_MPDG11 (MDLC_RT_BASE + 0x22c) +#define MDLC_RT_MPDGS00 (MDLC_RT_BASE + 0x300) +#define MDLC_RT_MPDGS01 (MDLC_RT_BASE + 0x304) +#define MDLC_RT_MPDGS02 (MDLC_RT_BASE + 0x308) +#define MDLC_RT_MPDGS03 (MDLC_RT_BASE + 0x30c) +#define MDLC_RT_MPDGS04 (MDLC_RT_BASE + 0x310) +#define MDLC_RT_MPDGS05 (MDLC_RT_BASE + 0x314) +#define MDLC_RT_MPDGS06 (MDLC_RT_BASE + 0x318) +#define MDLC_RT_MPDGS07 (MDLC_RT_BASE + 0x31c) +#define MDLC_RT_MPDGS08 (MDLC_RT_BASE + 0x320) +#define MDLC_RT_MPDGS09 (MDLC_RT_BASE + 0x324) +#define MDLC_RT_MPDGS10 (MDLC_RT_BASE + 0x328) +#define MDLC_RT_MPDGS11 (MDLC_RT_BASE + 0x32c) +#define MDLC_RT_MSRES02 (MDLC_RT_BASE + 0x908) +#define MDLC_RT_MSRESS02 (MDLC_RT_BASE + 0x968) +#define MDLC_RT_MSRES03 (MDLC_RT_BASE + 0x90c) +#define MDLC_RT_MSRESS03 (MDLC_RT_BASE + 0x96c) +#define MDLC_RT_MSRES15 (MDLC_RT_BASE + 0x93c) +#define MDLC_RT_MSRESS15 (MDLC_RT_BASE + 0x99c) +#define MDLC_RT_MSRES15_INTAP0_MASK GENMASK(9, 8) +#define MDLC_RT_MSRES15_INTTP_MASK GENMASK(11, 10) +#define MDLC_RT_MSRES15_INTAP1_MASK GENMASK(13, 12) +#define MDLC_RT_PKCPROT0 (MDLC_RT_BASE + 0xcf0) +#define MDLC_RT_PKCPROT1 (MDLC_RT_BASE + 0xcf4) + +/* + * mdlc_wait_for_reset() - Wait for MDLC reset register and reset status register to align + * @res: Reset register + * @stat: Reset status register + */ +static void mdlc_wait_for_reset(const u32 res, const u32 stat) +{ + /* This can not use readl_poll_timeout(), timer is not available yet. */ + for (; readl(res) != readl(stat);) + ; +} + +/** + * mdlc_write_msres() - Write MSRES register to release IP from reset + * @prot: Protect register + * @res: Reset register + * @val: Value to set in the masked out bits + */ +static void mdlc_write_msres(const u32 prot, const u32 res, const int val) +{ + writel(PKC_PROT_UNLOCK, prot); + writel(val, res); + writel(PKC_PROT_LOCK, prot); +} + +/** + * mdlc_rmw_msres() - Read-modify-write MSRES register to release IP from reset + * @prot: Protect register + * @res: Reset register + * @mask: Mask in the register to clear + * @val: Value to set in the masked out bits + */ +static void mdlc_rmw_msres(const u32 prot, const u32 res, const u32 mask, const int val) +{ + u32 reg; + + reg = readl(res); + reg &= ~mask; + reg |= field_prep(mask, val); + + mdlc_write_msres(prot, res, reg); +} + +/** + * mdlc_set_reset() - Set IP into reset + * @prot: Protect register + * @res: Reset register + * @stat: Reset register + * @mask: Mask in the register to clear + */ +static void mdlc_set_reset(const u32 prot, const u32 res, const u32 stat, const u32 mask) +{ + u32 status; + + mdlc_wait_for_reset(res, stat); + + status = field_get(mask, readl(stat)); + if (status == MDLC_MSRESS_STOP) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_STANDBY); + mdlc_wait_for_reset(res, stat); + status = field_get(mask, readl(stat)); + } + + if (status == MDLC_MSRESS_STANDBY || status == MDLC_MSRESS_RUN) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_RESET); + mdlc_wait_for_reset(res, stat); + } +} + +/** + * mdlc_release_reset() - Release IP from reset + * @prot: Protect register + * @res: Reset register + * @stat: Reset register + * @mask: Mask in the register to clear + */ +static void mdlc_release_reset(const u32 prot, const u32 res, const u32 stat, const u32 mask) +{ + u32 status; + + mdlc_wait_for_reset(res, stat); + + status = field_get(mask, readl(stat)); + if (status == MDLC_MSRESS_STANDBY) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_RESET); + mdlc_wait_for_reset(res, stat); + status = field_get(mask, readl(stat)); + } + + if (status == MDLC_MSRESS_RESET || status == MDLC_MSRESS_STOP) { + mdlc_rmw_msres(prot, res, mask, MDLC_MSRESS_RUN); + mdlc_wait_for_reset(res, stat); + } +} + +/** + * mldc_mpg_module_run() - Release MPG module from gating + * @prot: Protect register + * @res: Reset register + * @stat: Reset status register + * @ier: Interrupt enable register + * @imr: Interrupt mask register + */ +static void mldc_mpg_module_run(const u32 prot, const u32 res, const u32 stat, + const u32 ier, const u32 imr) +{ + u32 val; + + mdlc_wait_for_reset(res, stat); + + val = readl(stat); + if (val == MDLC_MPG_GATING) { + writel(0, ier); + writel(0, imr); + mdlc_write_msres(prot, res, MDLC_MPG_RESET); + mdlc_wait_for_reset(res, stat); + val = readl(stat); + } + + if (val == MDLC_MPG_RESET || val == MDLC_MPG_RUN) { + writel(0, ier); + writel(0, imr); + mdlc_write_msres(prot, res, MDLC_MPG_RUN); + mdlc_wait_for_reset(res, stat); + val = readl(stat); + } +} + +/** + * mdlc_mpg_start() - Configure MPG module state + */ +static void mdlc_mpg_start(void) +{ + mldc_mpg_module_run(MDLC_PERE_PKCPROT0, MDLC_PERE_MPDG01, MDLC_PERE_MPDGS01, + MDLC_PERE_MPIER, MDLC_PERE_MPIMR); + mldc_mpg_module_run(MDLC_PERE_PKCPROT0, MDLC_PERE_MPDG00, MDLC_PERE_MPDGS00, + MDLC_PERE_MPIER, MDLC_PERE_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG11, MDLC_RT_MPDGS11, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG10, MDLC_RT_MPDGS10, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG09, MDLC_RT_MPDGS09, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG08, MDLC_RT_MPDGS08, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG07, MDLC_RT_MPDGS07, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG06, MDLC_RT_MPDGS06, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG05, MDLC_RT_MPDGS05, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG04, MDLC_RT_MPDGS04, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG03, MDLC_RT_MPDGS03, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG02, MDLC_RT_MPDGS02, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG01, MDLC_RT_MPDGS01, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + mldc_mpg_module_run(MDLC_RT_PKCPROT0, MDLC_RT_MPDG00, MDLC_RT_MPDGS00, + MDLC_RT_MPIER, MDLC_RT_MPIMR); + /* Power on RSwitch */ + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG06, MDLC_HSCN_MPDGS06, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG05, MDLC_HSCN_MPDGS05, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG04, MDLC_HSCN_MPDGS04, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG03, MDLC_HSCN_MPDGS03, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG02, MDLC_HSCN_MPDGS02, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG01, MDLC_HSCN_MPDGS01, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); + mldc_mpg_module_run(MDLC_HSCN_PKCPROT0, MDLC_HSCN_MPDG00, MDLC_HSCN_MPDGS00, + MDLC_HSCN_MPIER, MDLC_HSCN_MPIMR); +} + +#define PFC_GP2_BASE 0xc1081000 +#define PFC_GP2_GPSR (PFC_GP2_BASE + 0x40) +#define PFC_GP2_IOINTSEL (PFC_GP2_BASE + 0x110) +#define PFC_GP2_INOUTSEL (PFC_GP2_BASE + 0x114) +#define PFC_GP2_OUTDT (PFC_GP2_BASE + 0x118) +#define PFC_GP2_POSNEG (PFC_GP2_BASE + 0x1a0) +#define PFC_GP2_PIN_AVS0 BIT(21) +#define PFC_GP2_PIN_AVS1 BIT(22) +#define PFC_GP2_PIN_AVS \ + (PFC_GP2_PIN_AVS0 | PFC_GP2_PIN_AVS1) + +#define PFC_GP3_BASE 0xc0800000 +#define PFC_GP3_PULLEN (PFC_GP3_BASE + 0xc0) +#define PFC_GP3_PUDSEL (PFC_GP3_BASE + 0xc4) + +#define PFC_GP5_BASE 0xc0400000 +#define PFC_GROUP_ADDR_MASK GENMASK(31, 11) +#define PFC_GP5_GPSR (PFC_GP5_BASE + 0x40) +#define PFC_GP5_ALTSEL0 (PFC_GP5_BASE + 0x60) +#define PFC_GP5_ALTSEL1 (PFC_GP5_BASE + 0x64) +#define PFC_GP5_ALTSEL2 (PFC_GP5_BASE + 0x68) +#define PFC_GP5_ALTSEL3 (PFC_GP5_BASE + 0x6c) +#define PFC_GP5_PIN_HTX0 BIT(0) +#define PFC_GP5_PIN_HRX0 BIT(1) +#define PFC_GP5_PIN_SCIF_CLK BIT(5) +#define PFC_GP5_PIN_HTX1 BIT(6) +#define PFC_GP5_PIN_HRX1 BIT(7) +#define PFC_GP5_PIN_HSCIF0_HSCIF1 \ + (PFC_GP5_PIN_HTX0 | PFC_GP5_PIN_HRX0 | \ + PFC_GP5_PIN_HTX1 | PFC_GP5_PIN_HRX1) +#define PFC_GP5_ALTSEL_HSCIF0_HSCIF1 \ + (PFC_GP5_PIN_HSCIF0_HSCIF1 | PFC_GP5_PIN_SCIF_CLK) + +/** + * pfc_rmw_reg() - Read-modify-write PFC register + * @reg: Register to write + * @mask: Mask in the register to clear + * @val: Value to set in the masked out bits + */ +static void pfc_rmw_reg(const u32 reg, const u32 mask, const u32 val) +{ + u32 pmmr = reg & PFC_GROUP_ADDR_MASK; + u32 tmp; + + tmp = readl(reg); + tmp &= ~mask; + tmp |= val; + + writel(~tmp, pmmr); + writel(tmp, reg); +} + +/** + * pfc_set_hscif0_hscif1_pinmux() - Set HSCIF0 and HSCIF1 pinmux + * @bd3250k: Set to TRUE if HSCIF configured for 3.25 MBdps + * + * This function configures both HSCIF0 and HSCIF1 pin multiplexing, + * HSCIF0 is used for follow up stages, HSCIF1 is used for IPL console. + */ +static void pfc_set_hscif0_hscif1_pinmux(bool bd3250k) +{ + u32 gpsr_mask = PFC_GP5_PIN_HSCIF0_HSCIF1; + + if (bd3250k) + gpsr_mask |= PFC_GP5_PIN_SCIF_CLK; + + pfc_rmw_reg(PFC_GP5_ALTSEL0, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_ALTSEL1, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_ALTSEL2, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_ALTSEL3, PFC_GP5_ALTSEL_HSCIF0_HSCIF1, 0); + pfc_rmw_reg(PFC_GP5_GPSR, gpsr_mask, gpsr_mask); +} + +/** + * pfc_set_avs_pinmux() - Set AVS pinmux + */ +static void pfc_set_avs_pinmux(void) +{ + clrbits_le32(PFC_GP2_POSNEG, PFC_GP2_PIN_AVS); + clrbits_le32(PFC_GP2_IOINTSEL, PFC_GP2_PIN_AVS); + setbits_le32(PFC_GP2_OUTDT, PFC_GP2_PIN_AVS); + setbits_le32(PFC_GP2_INOUTSEL, PFC_GP2_PIN_AVS); + pfc_rmw_reg(PFC_GP2_GPSR, PFC_GP2_PIN_AVS, 0); +} + +/* The addresses in range 0x08000000..0x1fffffff are incremented by 0xa0000000 */ +#define MFIS_BASE 0xb89e0000 +#define MFIS_WPCNTR (MFIS_BASE + 0x900) +#define MFIS_CODEVALUE 0xacce0000 + +/** + * mfis_unprotect() - Remove MFIS register write protection + */ +static void mfis_unprotect(void) +{ + writel(MFIS_CODEVALUE, MFIS_WPCNTR); +} + +/** + * rsip_irq_setup() - Configure RSIP interrupts + */ +static void rsip_irq_setup(void) +{ + asm volatile("cpsid i"); + + setbits_le32(RSIP_SHCSR, RSIP_SHCSR_USGFAULTENA | RSIP_SHCSR_BUSFAULTENA | + RSIP_SHCSR_MEMFAULTENA); + + writel(0xffffffff, RSIP_NVIC_ICER_00); + writel(0xffffffff, RSIP_NVIC_ICER_01); + writel(0xffffffff, RSIP_NVIC_ICER_02); + writel(0xffffffff, RSIP_NVIC_ICER_03); + writel(0xffffffff, RSIP_NVIC_ICER_04); + writel(0xffffffff, RSIP_NVIC_ICER_05); + writel(0xffffffff, RSIP_NVIC_ICER_06); + writel(0xffffffff, RSIP_NVIC_ICER_07); + writel(0xffffffff, RSIP_NVIC_ICER_08); + writel(0xffffffff, RSIP_NVIC_ICER_09); + writel(0xffffffff, RSIP_NVIC_ICER_10); + writel(0xffffffff, RSIP_NVIC_ICER_11); + writel(0xffffffff, RSIP_NVIC_ICER_12); + writel(0xffffffff, RSIP_NVIC_ICER_13); + writel(0xffffffff, RSIP_NVIC_ICER_14); + writel(0xffffffff, RSIP_NVIC_ICER_15); + + /* WDT IRQ */ + writel(RSIP_NVIC_ISER_00_SETENA_INTIWDTA0, RSIP_NVIC_ISER_00); + + asm volatile("cpsid i"); +} + +#define RPC_BASE 0xc08c0000 +#define RPC_CMNSR (RPC_BASE + 0x48) +#define RPC_PHYCNT (RPC_BASE + 0x7c) +#define RPC_CMNCR (RPC_BASE + 0x00) +#define RPC_SSLDR (RPC_BASE + 0x04) +#define RPC_DRCR (RPC_BASE + 0x0c) +#define RPC_DRCMR (RPC_BASE + 0x10) +#define RPC_DREAR (RPC_BASE + 0x14) +#define RPC_DROPR (RPC_BASE + 0x18) +#define RPC_DRENR (RPC_BASE + 0x1c) +#define RPC_SMCR (RPC_BASE + 0x20) +#define RPC_SMCMR (RPC_BASE + 0x24) +#define RPC_SMADR (RPC_BASE + 0x28) +#define RPC_SMENR (RPC_BASE + 0x30) +#define RPC_SMWDR0 (RPC_BASE + 0x40) +#define RPC_DRDMCR (RPC_BASE + 0x58) +#define RPC_DRDRENR (RPC_BASE + 0x5c) +#define RPC_PHYOFFSET1 (RPC_BASE + 0x80) +#define RPC_PHYINT (RPC_BASE + 0x88) +#define RPC_SEC_CONF (RPC_BASE + 0xb8) + +#define RPC_CMNSR_TEND BIT(0) + +#define RPC_CMNCR_MD BIT(31) +#define RPC_CMNCR_MOIIO3(n) FIELD_PREP(GENMASK(23, 22), (n)) +#define RPC_CMNCR_MOIIO2(n) FIELD_PREP(GENMASK(21, 20), (n)) +#define RPC_CMNCR_MOIIO1(n) FIELD_PREP(GENMASK(19, 18), (n)) +#define RPC_CMNCR_MOIIO0(n) FIELD_PREP(GENMASK(17, 16), (n)) +#define RPC_CMNCR_IO0FV(n) FIELD_PREP(GENMASK(9, 8), (n)) +#define RPC_CMNCR_BSZ(n) FIELD_PREP(GENMASK(1, 0), (n)) + +#define RPC_SSLDR_SPNDL_MASK GENMASK(18, 16) +#define RPC_SSLDR_SPNDL_SPCLK_2_CYCLES FIELD_PREP(RPC_SSLDR_SPNDL_MASK, 1) +#define RPC_SSLDR_SLNDL_MASK GENMASK(10, 8) +#define RPC_SSLDR_SLNDL_SPCLK_5_5_CYCLES FIELD_PREP(RPC_SSLDR_SLNDL_MASK, 4) +#define RPC_SSLDR_SCKDL_MASK GENMASK(2, 0) +#define RPC_SSLDR_SCKDL_SPCLK_2_CYCLES FIELD_PREP(RPC_SSLDR_SCKDL_MASK, 1) + +#define RPC_DRCR_SSLN BIT(24) +#define RPC_DRCR_RBURST_MASK GENMASK(20, 16) +#define RPC_DRCR_RCF_READ_CACHE_CLEARE BIT(9) +#define RPC_DRCR_RBE BIT(8) + +#define RPC_DRCMR_CMD_MASK GENMASK(23, 16) +#define RPC_DRCMR_CMD_HYPERFLASH_READ FIELD_PREP(RPC_DRCMR_CMD_MASK, 0xA0) + +#define RPC_DREAR_EAV_MASK GENMASK(23, 16) +#define RPC_DREAR_EAC_MASK GENMASK(2, 0) + +#define RPC_DRENR_DME BIT(15) +#define RPC_DRENR_CDE BIT(14) +#define RPC_DRENR_OCDE BIT(12) +#define RPC_DRENR_ADE_MASK GENMASK(11, 8) +#define RPC_DRENR_ADE_HYPERFLASH FIELD_PREP(RPC_DRENR_ADE_MASK, 4) +#define RPC_DRENR_OPDE_MASK GENMASK(7, 4) + +#define RPC_DRDMCR_DMCYC_MASK GENMASK(4, 0) +#define RPC_DRDMCR_DMCYC_15_CYCLE FIELD_PREP(RPC_DRDMCR_DMCYC_MASK, 0xe) + +#define RPC_DRDRENR_HYPE_MASK GENMASK(14, 12) +#define RPC_DRDRENR_HYPE_HYPERFLASH FIELD_PREP(RPC_DRDRENR_HYPE_MASK, 5) +#define RPC_DRDRENR_ADDRE BIT(8) +#define RPC_DRDRENR_OPDRE BIT(4) +#define RPC_DRDRENR_DRDRE BIT(0) + +#define RPC_PHYCNT_STRTIM_BIT27BIT17_15_MASK 0x08038000 + +#define RPC_PHYCNT_HS BIT(18) +#define RPC_PHYCNT_PHYMEM_MASK GENMASK(1, 0) +#define RPC_PHYCNT_PHYMEM_HYPERFLASH FIELD_PREP(RPC_PHYCNT_PHYMEM_MASK, 3) + +/** + * rpc_safe_setup() - Configure RPC with safe static settings + */ +static void rpc_safe_setup(void) +{ + writel(RPC_CMNCR_MOIIO3(2) | RPC_CMNCR_MOIIO2(2) | RPC_CMNCR_MOIIO1(2) | + RPC_CMNCR_MOIIO0(2) | RPC_CMNCR_IO0FV(3) | RPC_CMNCR_BSZ(1) | + 0x01007000, RPC_CMNCR); + writel(RPC_SSLDR_SPNDL_SPCLK_2_CYCLES | RPC_SSLDR_SLNDL_SPCLK_5_5_CYCLES | + RPC_SSLDR_SCKDL_SPCLK_2_CYCLES, RPC_SSLDR); + writel(RPC_DRCR_RBURST_MASK | RPC_DRCR_RBE, RPC_DRCR); + writel(RPC_DRCMR_CMD_HYPERFLASH_READ, RPC_DRCMR); + writel(0, RPC_DREAR); + writel(RPC_DRENR_ADE_HYPERFLASH | 0xa222d000, RPC_DRENR); + writel(0, RPC_SMCR); + writel(0, RPC_SMCMR); + writel(0, RPC_SMADR); + writel(BIT(14), RPC_SMENR); + writel(0, RPC_SMWDR0); + writel(RPC_CMNSR_TEND, RPC_CMNSR); + writel(RPC_DRDMCR_DMCYC_15_CYCLE, RPC_DRDMCR); + writel(RPC_DRDRENR_HYPE_HYPERFLASH | RPC_DRDRENR_ADDRE | RPC_DRDRENR_DRDRE, + RPC_DRDRENR); + writel(0x08078263, RPC_PHYCNT); + writel(0x21511144, RPC_PHYOFFSET1); + writel(0x07070002, RPC_PHYINT); + writel(0x00000155, RPC_SEC_CONF); + writel(0x11, CLK_CONTROL_RPCCKCR); + writel(0x10100, PFC_GP3_PULLEN); + writel(0x10100, PFC_GP3_PUDSEL); +} + +/** + * rpc_boot_setup() - Configure RPC after boot from HF + */ +static void rpc_boot_setup(void) +{ + clrsetbits_le32(RPC_PHYCNT, + RPC_PHYCNT_STRTIM_BIT27BIT17_15_MASK | RPC_PHYCNT_HS | + RPC_PHYCNT_PHYMEM_MASK, + RPC_PHYCNT_STRTIM_BIT27BIT17_15_MASK | + RPC_PHYCNT_HS | RPC_PHYCNT_PHYMEM_HYPERFLASH); + + clrsetbits_le32(RPC_CMNCR, + RPC_CMNCR_MD | + RPC_CMNCR_MOIIO3(3) | RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO1(3) | + RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_IO0FV(3) | RPC_CMNCR_BSZ(3), + RPC_CMNCR_MOIIO3(2) | RPC_CMNCR_MOIIO2(2) | RPC_CMNCR_MOIIO1(2) | + RPC_CMNCR_MOIIO0(2) | RPC_CMNCR_IO0FV(3) | RPC_CMNCR_BSZ(1)); + + clrsetbits_le32(RPC_SSLDR, + RPC_SSLDR_SPNDL_MASK | RPC_SSLDR_SLNDL_MASK | RPC_SSLDR_SCKDL_MASK, + RPC_SSLDR_SPNDL_SPCLK_2_CYCLES | RPC_SSLDR_SLNDL_SPCLK_5_5_CYCLES | + RPC_SSLDR_SCKDL_SPCLK_2_CYCLES); + + clrsetbits_le32(RPC_DRCR, + RPC_DRCR_SSLN | RPC_DRCR_RBURST_MASK | RPC_DRCR_RBE, + RPC_DRCR_SSLN | RPC_DRCR_RBURST_MASK | + RPC_DRCR_RCF_READ_CACHE_CLEARE | RPC_DRCR_RBE); + readl(RPC_DRCR); /* Dummy readback */ + + clrsetbits_le32(RPC_DRCMR, RPC_DRCMR_CMD_MASK, RPC_DRCMR_CMD_HYPERFLASH_READ); + + clrbits_le32(RPC_DREAR, RPC_DREAR_EAV_MASK | RPC_DREAR_EAC_MASK); + + writel(0, RPC_DROPR); + + clrsetbits_le32(RPC_DRENR, + RPC_DRENR_DME | RPC_DRENR_CDE | RPC_DRENR_OCDE | + RPC_DRENR_ADE_MASK | RPC_DRENR_OPDE_MASK, + RPC_DRENR_DME | RPC_DRENR_CDE | RPC_DRENR_OCDE | + RPC_DRENR_ADE_HYPERFLASH); + + clrsetbits_le32(RPC_DRDMCR, RPC_DRDMCR_DMCYC_MASK, RPC_DRDMCR_DMCYC_15_CYCLE); + + clrsetbits_le32(RPC_DRDRENR, + RPC_DRDRENR_HYPE_MASK | RPC_DRDRENR_ADDRE | + RPC_DRDRENR_OPDRE | RPC_DRDRENR_DRDRE, + RPC_DRDRENR_HYPE_HYPERFLASH | RPC_DRDRENR_ADDRE | + RPC_DRDRENR_DRDRE); +} + +/** + * rpc_setup() - Configure RPC + */ +static void rpc_setup(void) +{ + const u32 boot = field_get(SYSSS_MODE1_BOOTMODE_MASK, sysss_read_modemr()); + + if (boot != SYSSS_MODE1_BOOTMODE_HF_DMA) { + /* Not booted from HF, this may be SCIF loader, use safe setup. */ + rpc_safe_setup(); + return; + } + + /* Wait for any outstanding transfer to end. */ + /* This can not use readl_poll_timeout(), timer is not available yet. */ + while (!(readl(RPC_CMNSR) & RPC_CMNSR_TEND)) + ; + + /* Tristate IO */ + setbits_le32(RPC_CMNCR, RPC_CMNCR_MOIIO3(3) | RPC_CMNCR_MOIIO2(3) | + RPC_CMNCR_MOIIO1(3) | RPC_CMNCR_MOIIO0(3)); + + /* Set 160 MHz RPC HF clock */ + clrsetbits_le32(CLK_CONTROL_RPCCKCR, + CLK_CONTROL_RPCCKCR_CKSTP1 | CLK_CONTROL_RPCCKCR_RPCFC_MASK, + 0x11); + + rpc_boot_setup(); +} + +#define AXMM10_ADSPLCR0_CTRL 0xe9a07100 +#define AXMM10_ADSPLCR1_CTRL 0xe9a07104 +#define AXMM11_ADSPLCR0_CTRL 0xe9a07150 +#define AXMM11_ADSPLCR1_CTRL 0xe9a07154 + +/** + * axi_qos_init() - Configure AXI bus QoS + */ +static void axi_qos_init(void) +{ + writel(0x00011d0c, AXMM10_ADSPLCR0_CTRL); + writel(0x0000ffff, AXMM10_ADSPLCR1_CTRL); + writel(0x00011d0c, AXMM11_ADSPLCR0_CTRL); + writel(0x0000ffff, AXMM11_ADSPLCR1_CTRL); + dsb(); +} + +/** + * load_perm_table() - Load shared table into SRAM and hardware + * @dstaddr: SRAM destination address + * @dstsize: SRAM destination area size + * @listtable: Table of registers to write at offset 2i + * @listsize: Size of table of registers + * @listval: Value to write at offset 2i+1 + */ +static void load_perm_table(const u32 dstaddr, const u32 dstsize, + const u32 *listtable, const u32 listsize, + const u32 listval) +{ + /* + * The addresses in range 0x08000000..0x1fffffff are + * incremented by 0xa0000000 . + */ + u32 *dmabuf = (u32 *)(dstaddr + 0xa0000000); + u32 reg, rv; + int i; + + /* Place shared bus access permissions configuration table into SRAM */ + for (i = 0; i < dstsize / (2 * sizeof(u32)); i++) { + if (i >= listsize) { + dmabuf[2 * i] = 0; + dmabuf[(2 * i) + 1] = 0; + continue; + } + + dmabuf[2 * i] = listtable[i]; + dmabuf[(2 * i) + 1] = listval; + + /* + * The addresses in range 0x08000000..0x1fffffff are + * incremented by 0xa0000000 . + */ + reg = listtable[i]; + if (reg > 0x08000000 && reg < 0x20000000) + reg += 0xa0000000; + writel(listval, reg); + } + + /* Validate hardware write. */ + for (i = 0; i < listsize; i++) { + reg = listtable[i]; + if (reg > 0x08000000 && reg < 0x20000000) + reg += 0xa0000000; + rv = readl(reg); + if (rv == listval) + continue; + printf("RG[%d] = 0x%x / expected 0x%x\n", i, rv, listval); + } +} + +/** + * load_perm_tables() - Load shared tables into SRAM and hardware + */ +static void load_perm_tables(void) +{ + load_perm_table(RGIDM_SHARED_ADDR, RGIDM_SHARED_SIZE, + rgidm_register_list, ARRAY_SIZE(rgidm_register_list), 0); + load_perm_table(SEC_MODID_SHARED_ADDR, SEC_MODID_SHARED_SIZE, + sec_modid_register_list, ARRAY_SIZE(sec_modid_register_list), 0xffff); + load_perm_table(RGIDR_SHARED_ADDR, RGIDR_SHARED_SIZE, + rgidr_register_list, ARRAY_SIZE(rgidr_register_list), 1); + load_perm_table(RGIDW_SHARED_ADDR, RGIDW_SHARED_SIZE, + rgidw_register_list, ARRAY_SIZE(rgidw_register_list), 1); + + /* Override Region ID secure group settings */ + writel(0xffffffff, 0xc0983820); + writel(0xffffffff, 0xc0983828); + + writel(0xffffffff, 0xec603828); + writel(0xffffffff, 0xec60382c); + writel(0xffffffff, 0xec603830); + writel(0xffffffff, 0xec603834); + writel(0xffffffff, 0xec603838); + writel(0xffffffff, 0xec60383c); + + writel(0xffffffff, 0xc9d03880); + writel(0xffffffff, 0xc9d03884); + + /* + * The addresses in range 0x08000000..0x1fffffff + * are incremented by 0xa0000000 + */ + writel(0xffffffff, 0xba80383c); + writel(0xffffffff, 0xba803840); + writel(0xffffffff, 0xba803848); + writel(0xffffffff, 0xba80384c); + writel(0xffffffff, 0xba803974); + + writel(0xffffffff, 0xde803804); + writel(0xffffffff, 0xde803808); + writel(0xffffffff, 0xde803810); + writel(0xffffffff, 0xde803814); + writel(0xffffffff, 0xde803838); + writel(0xffffffff, 0xde80383c); + writel(0xffffffff, 0xde803840); + writel(0xffffffff, 0xde803844); + + writel(0xffffffff, 0xc1283808); + + writel(0xffffffff, 0xe9a08000); + writel(0xffffffff, 0xe9a081fc); + writel(0xffffffff, 0xe9a08200); + writel(0xffffffff, 0xe9a081fc); +} + +#define SCP_STCM_BASE 0xc1000000 +#define SCP_BASE 0xc1340000 +#define SCP_CFGVECTABLE (SCP_BASE + 0x0) +#define SCP_CFGNSSTCALIB (SCP_BASE + 0x10) +#define SCP_CPUWAIT (SCP_BASE + 0x30) +#define SCP_CFGNSSTCALIB_13_3MHZ 0x010040f0 +#define SCP_CPUWAIT_WAIT BIT(0) + +/** + * scp_initialize() - Initialize SCP + * + * Put SCP into reset, configure SCP entry point address and systick timer, + * release SCP from reset, and zero out SCP STCM regions. + */ +static void scp_initialize(void) +{ + u32 addr; + + mdlc_set_reset(MDLC_SCP_PKCPROT1, MDLC_SCP_MSRES02, MDLC_SCP_MSRESS02, + MDLC_SCP_MSRES02_SCP_MASK); + + writel(SCP_STCM_BASE, SCP_CFGVECTABLE); + writel(SCP_CFGNSSTCALIB_13_3MHZ, SCP_CFGNSSTCALIB); + setbits_le32(SCP_CPUWAIT, SCP_CPUWAIT_WAIT); + + mdlc_release_reset(MDLC_SCP_PKCPROT1, MDLC_SCP_MSRES02, MDLC_SCP_MSRESS02, + MDLC_SCP_MSRES02_SCP_MASK); + + /* Fill zero to SCP STCM regions 0 ... 27 */ + for (addr = SCP_STCM_BASE; addr < 0xc1061b00; addr += 8) + writeq(0, addr); + + asm volatile("dsb sy"); +} + +#define GIC720AE_GICR_PWRR(cpu) \ + (GICR_BASE + 0x24 + ((cpu) * 0x40000)) + +#define GIC720AE_GICD_IVIEWR(num) \ + (GICD_BASE + 0xf600 + ((num) * 0x4)) +#define GIC720AE_GICD_IVIEWRE(num) \ + (GICD_BASE + 0xf800 + ((num) * 0x4)) +#define GIC720AE_GICR_TYPER(cpu) \ + (GICD_BASE + 0x80000 + ((cpu) * 0x40000) + 0x8) +#define GIC720AE_GICR_VIEWR(cpu) \ + (GICD_BASE + 0x80000 + ((cpu) * 0x40000) + 0x2c) +#define GIC720AE_GICR_MPIDR(cpu) \ + (GICD_BASE + 0x80000 + ((cpu) * 0x40000) + 0x100) +#define GIC720AE_GICR_TYPER_AFF_MASK GENMASK_ULL(63, 32) + +#define CA_CORE_MAX 32 + +/** + * gic720ae_init() - GIC720AE initialization + */ +static void gic720ae_init(void) +{ + u64 val; + int i; + + mdlc_release_reset(MDLC_RT_PKCPROT1, MDLC_RT_MSRES15, MDLC_RT_MSRESS15, + MDLC_RT_MSRES15_INTAP0_MASK); + mdlc_release_reset(MDLC_RT_PKCPROT1, MDLC_RT_MSRES15, MDLC_RT_MSRESS15, + MDLC_RT_MSRES15_INTTP_MASK); + mdlc_release_reset(MDLC_RT_PKCPROT1, MDLC_RT_MSRES15, MDLC_RT_MSRESS15, + MDLC_RT_MSRES15_INTAP1_MASK); + + for (i = 0; i < CA_CORE_MAX; i++) + writel(BIT(1), GIC720AE_GICR_PWRR(i)); + + for (i = 0; i < CA_CORE_MAX; i++) { + val = readq(GIC720AE_GICR_TYPER(i)) & GIC720AE_GICR_TYPER_AFF_MASK; + writel((u32)(val >> 32U), GIC720AE_GICR_MPIDR(i)); + } + + writel(0x3f, GICD_BASE); /* CTRL register */ + + for (i = 2; i <= 61; i++) /* From IVIEWR min..max */ + writel(0x55555555, GIC720AE_GICD_IVIEWR(i)); + + for (i = 0; i <= 63; i++) /* From IVIEWRE min..max */ + writel(0x55555555, GIC720AE_GICD_IVIEWRE(i)); + + for (i = 0; i < CA_CORE_MAX; i++) + writel(1, GIC720AE_GICR_VIEWR(i)); /* View 1 */ +} + +/** + * mach_cpu_init() - Initialize hardware and start other cores + */ +int mach_cpu_init(void) +{ + mfis_unprotect(); + pfc_set_avs_pinmux(); + mdlc_mpg_start(); + clk_control_set_pll(); + rsip_irq_setup(); + rpc_setup(); + axi_qos_init(); + load_perm_tables(); + gic720ae_init(); + + /* Release SCP from reset */ + scp_initialize(); + + return 0; +} + +/** + * board_debug_uart_init() - Initialize all HSCIF + */ +void board_debug_uart_init(void) +{ + const u32 baud = field_get(SYSSS_MODE1_BAUDRATE_MASK, sysss_read_modemr()); + + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_0_CR2, + CLK_CONTROL_PLL01_0_SCR); + clk_control_switch_from_iosc_to_pll(CLK_CONTROL_PLL01_1_CR2, + CLK_CONTROL_PLL01_1_SCR); + + mdlc_release_reset(MDLC_PERW_PKCPROT1, MDLC_PERW_MSRES05, MDLC_PERW_MSRESS05, + MDLC_PERW_MSRES05_HSCIF0_MASK); + mdlc_release_reset(MDLC_PERW_PKCPROT1, MDLC_PERW_MSRES05, MDLC_PERW_MSRESS05, + MDLC_PERW_MSRES05_HSCIF1_MASK); + + pfc_set_hscif0_hscif1_pinmux(baud == SYSSS_MODE1_BAUDRATE_3250000); +} + +/** + * board_init() - Board specific initialization + */ +int board_init(void) +{ + /* Allow WDT reset */ + writel(RST_KCPROT_DIS, RST_RESKCPROT0); + clrbits_le32(RST_WDTRSTCR, RST_WWDT_RSTMSK | RST_RWDT_RSTMSK); + + return 0; +} + +/** + * arm_reserve_mmu() - Reserve space for MMU tables + */ +int arm_reserve_mmu(void) +{ + /* Reserve space for MMU tables just above stack in STCM */ + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = CONFIG_CUSTOM_SYS_INIT_SP_ADDR; + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + return 0; +} + +/** + * reset_cpu() - Reset this CPU core + */ +void __weak reset_cpu(void) +{ + writel(RST_KCPROT_DIS, RST_RESKCPROT0); + writel(0x1, RST_SWSRES1A); +} diff --git a/board/renesas/common/gen5-cm33.h b/board/renesas/common/gen5-cm33.h new file mode 100644 index 00000000000..2dfb0b06cf7 --- /dev/null +++ b/board/renesas/common/gen5-cm33.h @@ -0,0 +1,2001 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2025-2026 Renesas Electronics Corp. + */ + +#ifndef __GEN5_CM33_H__ +#define __GEN5_CM33_H__ + +#define RGIDM_SHARED_ADDR 0x1001c000 +#define RGIDM_SHARED_SIZE 0x1000 +#define SEC_MODID_SHARED_ADDR 0x1001d000 +#define SEC_MODID_SHARED_SIZE 0x3000 +#define RGIDR_SHARED_ADDR 0x10020000 +#define RGIDR_SHARED_SIZE 0x8000 +#define RGIDW_SHARED_ADDR 0x10028000 +#define RGIDW_SHARED_SIZE 0x8000 + +static const u32 rgidm_register_list[] = { + 0xec601000, 0xcbf01000, 0xcbf01004, 0xcbf01008, + 0xcbf0100c, 0xcbf01010, 0xcbf01014, 0xcbf01018, + 0xcbf0101c, 0xcbf01020, 0xcbf01024, 0xcbf01028, + 0xcbf0102c, 0xcbf01030, 0xcbf01034, 0xcbf01038, + 0xcbf0103c, 0xcbf01040, 0xcbf01044, 0xcbf01048, + 0xcbf0104c, 0xcbf01050, 0xcbf01054, 0xcbf01058, + 0xcbf0105c, 0xcbf01060, 0xcbf01064, 0xcbf01068, + 0xcbf0106c, 0xcbf01070, 0xcbf01074, 0xcbf01078, + 0xcbf0107c, 0xcbf01080, 0xc9d01000, 0xc9d01004, + 0xc9d01008, 0xc9d0100c, 0xc9d01010, 0xc9d01014, + 0xc9d01018, 0xc9d0101c, 0xc9d01020, 0xc9d01024, + 0xc9d01028, 0xc9d0102c, 0xc9d01030, 0xc9d01034, + 0xc9d01038, 0xc9d0103c, 0xc9d01040, 0xde801000, + 0xde801004, 0xc1a01000, 0xc1a01004, 0xc1a01008, + 0xc1a0100c, 0xc1a01010, 0xc1a01014, 0xc1a01018, + 0xc1a0101c, 0xc1a01020, 0xc1a01024, 0xc1e01000, + 0xc1e01004, 0xc1e01008, 0xc1e0100c, 0xc1e01010, + 0xc1e01014, 0xc1e01018, 0xc1e0101c, 0xc1e01020, + 0xc1e01024, 0xe9a01000, 0xe9a01004, 0xe9a01008, + 0xe9a0100c, 0xd2f01000, 0xd2f01004, 0xd2f01008, + 0xd2f0100c, 0xd2f01010, 0xd2f01014, 0xd2f01018, + 0xd2f0101c, 0xd2f01020, 0xd2f01024, 0xd2f01028, + 0xd2f0102c, 0xd2f01030, 0xd2f01034, 0xd2f01038, + 0xd6f01000, 0xd6f01004, 0xd6f01008, 0xd6f0100c, + 0xd6f01010, 0xd6f01014, 0xd6f01018, 0xd6f0101c, + 0xd6f01020, 0xd6f01024, 0xd6f01028, 0xd6f0102c, + 0xd6f01030, 0xd6f01034, 0xd6f01038, 0xc0981000, + 0xc0981004, 0xc0981008, 0xc098100c, 0xc0581000, + 0xcb401000, 0xcb401004, 0xcb401008, 0xcb40100c, + 0xcb401010, 0xcb401014, 0x1a801000, 0x1a801004, + 0x1a801008, 0x1a80100c, 0x1a801010, 0x1a801014, + 0x1a801018, 0x1a80101c, 0x1a801020, 0x1a801024, + 0x1a801028, 0x1a80102c, 0x1a801030, 0x1a801034, + 0x1a801038, 0x1a80103c, 0x1a801040, 0x1a801044, + 0x1a801048, 0x1a80104c, 0x1a801050, 0x1a801054, + 0x1a801058, 0x1a80105c, 0x1a801060, 0x1a801064, + 0x1a801068, 0x1a80106c, 0x1a801070, 0x1a801074, + 0x1a801078, 0x1a80107c, 0x1a801080, 0x1a801084, + 0x1a801088, 0x1a80108c, 0x1a801090, 0x1a801094, + 0x18b41000, 0x18b41004, 0x18b41008, 0x18b4100c, + 0xc1281000, 0xc1281004, 0xc1281008, 0xc128100c, + 0xc1281010, 0xc1281014, 0xc5801000, 0xc5801004, + 0xc5801008, 0xc580100c, 0xc5801010, 0xc5801014, + 0xc5801018, 0xc580101c, 0xc5801020, 0xc5801024, + 0xc5801028, 0xc580102c, 0xc5801030, 0xc5801034, + 0xc5801038, 0xc580103c, 0xc5801040, 0xc5801044, + 0xc5801048, 0xc580104c, 0xc5801050, 0xc5801054, + 0xc5801058, 0xc580105c, 0xc5801060, 0xc5801064, + 0xc5801068, 0xc580106c, 0xc5801070, 0xc5801074, + 0xc5801078, 0xc580107c, 0xc5801080, 0xc5801084, + 0xc5801088, 0xc580108c, 0xc5801090, 0xc5801094, + 0xc5801098, 0xc580109c, 0xc58010a0, 0xc58010a4, + 0xc58010a8, 0xc58010ac, 0xc58010b0, 0xc58010b4, + 0xc58010b8, 0xc58010bc, 0xc58010c0, 0xc58010c4, + 0xc58010c8, 0xc58010cc, 0xc58010d0, 0xc58010d4, + 0xc58010d8, 0xc58010dc, 0xc58010e0, 0xc3021000, + 0xc3021004, 0xc3021008, 0xc302100c, 0xc3021010, + 0xc3021014, 0xc3421000, 0xc3421004, 0xc3421008, + 0xc342100c, 0xc3421010, 0xc3421014 +}; + +static const u32 rgidr_register_list[] = { + 0xe8022000, 0xe8022004, 0xe8022008, 0xe802200c, + 0xe8022010, 0xe8022014, 0xe8022018, 0xe802201c, + 0xe8022020, 0xe8022024, 0xe8022028, 0xe802202c, + 0xe8022030, 0xe8022034, 0xe8022038, 0xe802203c, + 0xe8022040, 0xe8022044, 0xe8022048, 0xe802204c, + 0xe80a2000, 0xe80a2004, 0xe80a2008, 0xe80a200c, + 0xe80a2010, 0xe80a2014, 0xe80a2018, 0xe80a201c, + 0xe80a2020, 0xe80a2024, 0xe80a2028, 0xe80a202c, + 0xe80a2030, 0xe80a2034, 0xe80a2038, 0xe80a203c, + 0xe80a2040, 0xe80a2044, 0xe80a2048, 0xe80a204c, + 0xe8122000, 0xe8122004, 0xe8122008, 0xe812200c, + 0xe8122010, 0xe8122014, 0xe8122018, 0xe812201c, + 0xe8122020, 0xe8122024, 0xe8122028, 0xe812202c, + 0xe8122030, 0xe8122034, 0xe8122038, 0xe812203c, + 0xe8122040, 0xe8122044, 0xe8122048, 0xe812204c, + 0xe81a2000, 0xe81a2004, 0xe81a2008, 0xe81a200c, + 0xe81a2010, 0xe81a2014, 0xe81a2018, 0xe81a201c, + 0xe81a2020, 0xe81a2024, 0xe81a2028, 0xe81a202c, + 0xe81a2030, 0xe81a2034, 0xe81a2038, 0xe81a203c, + 0xe81a2040, 0xe81a2044, 0xe81a2048, 0xe81a204c, + 0xe8222000, 0xe8222004, 0xe8222008, 0xe822200c, + 0xe8222010, 0xe8222014, 0xe8222018, 0xe822201c, + 0xe8222020, 0xe8222024, 0xe8222028, 0xe822202c, + 0xe8222030, 0xe8222034, 0xe8222038, 0xe822203c, + 0xe8222040, 0xe8222044, 0xe8222048, 0xe822204c, + 0xe82a2000, 0xe82a2004, 0xe82a2008, 0xe82a200c, + 0xe82a2010, 0xe82a2014, 0xe82a2018, 0xe82a201c, + 0xe82a2020, 0xe82a2024, 0xe82a2028, 0xe82a202c, + 0xe82a2030, 0xe82a2034, 0xe82a2038, 0xe82a203c, + 0xe82a2040, 0xe82a2044, 0xe82a2048, 0xe82a204c, + 0xe8322000, 0xe8322004, 0xe8322008, 0xe832200c, + 0xe8322010, 0xe8322014, 0xe8322018, 0xe832201c, + 0xe8322020, 0xe8322024, 0xe8322028, 0xe832202c, + 0xe8322030, 0xe8322034, 0xe8322038, 0xe832203c, + 0xe8322040, 0xe8322044, 0xe8322048, 0xe832204c, + 0xe83a2000, 0xe83a2004, 0xe83a2008, 0xe83a200c, + 0xe83a2010, 0xe83a2014, 0xe83a2018, 0xe83a201c, + 0xe83a2020, 0xe83a2024, 0xe83a2028, 0xe83a202c, + 0xe83a2030, 0xe83a2034, 0xe83a2038, 0xe83a203c, + 0xe83a2040, 0xe83a2044, 0xe83a2048, 0xe83a204c, + 0xc0622000, 0xc0622004, 0xc0622008, 0xc062200c, + 0xc0622010, 0xc0622014, 0xc0622018, 0xc062201c, + 0xc0622020, 0xc0622024, 0xc0622028, 0xc062202c, + 0xc0622030, 0xc0622034, 0xc0622038, 0xc062203c, + 0xc0622040, 0xc0622044, 0xc0622048, 0xc062204c, + 0xc0622050, 0xc0622054, 0xc0762000, 0xc0762004, + 0xc0762008, 0xc076200c, 0xc0762010, 0xc0762014, + 0xc0762018, 0xc076201c, 0xc0762020, 0xc0762024, + 0xc0762028, 0xc076202c, 0xc0762030, 0xc0762034, + 0xc0762038, 0xc076203c, 0xc0762040, 0xc0762044, + 0xc0762048, 0xc076204c, 0xc0762050, 0xc0762054, + 0xc0762058, 0xc076205c, 0xc0762060, 0xc0762064, + 0xc0762068, 0xc076206c, 0xc0762070, 0xc0762074, + 0xc0762078, 0xc076207c, 0xc0762080, 0xc0762084, + 0xc0762088, 0xc076208c, 0xc0762090, 0xc0762094, + 0xc0762098, 0xc076209c, 0xc07620a0, 0xc07620a4, + 0xc07620a8, 0xc07620ac, 0xc07620b0, 0xc07620b4, + 0xc07620b8, 0xc07620bc, 0xc07620c0, 0xc07620c4, + 0xc07620c8, 0xc07620cc, 0xc07620d0, 0xc07620d4, + 0xc07620d8, 0xc07620dc, 0xc07a2000, 0xc07a2004, + 0xc07a2008, 0xc07a200c, 0xc07a2010, 0xc07a2014, + 0xc07a2018, 0xc07a201c, 0xc07a2020, 0xc07a2024, + 0xc07a2028, 0xc07a202c, 0xc07a2030, 0xc07a2034, + 0xc07a2038, 0xc07a203c, 0xc07a2040, 0xc07a2044, + 0xc07a2048, 0xc07a204c, 0xc07a2050, 0xc07a2054, + 0xc07a2058, 0x1d002000, 0x1d002004, 0x1d002008, + 0x1d00200c, 0x1d002010, 0x1d002014, 0x1d002018, + 0x1d00201c, 0x1d002020, 0x1d002024, 0x1d002028, + 0x1d00202c, 0x1d002030, 0x1d002034, 0x1d002038, + 0x1d00203c, 0x1d002040, 0x1d002044, 0x1d002048, + 0x1d00204c, 0x1d002050, 0x1d002054, 0x1d002058, + 0x1d00205c, 0x1d002060, 0x1d002064, 0x1d002068, + 0x1d00206c, 0x1d002070, 0x1d002074, 0x1d002078, + 0x1d00207c, 0x1d002080, 0x1d002084, 0x1d002088, + 0x1d00208c, 0x1d002090, 0x1d002094, 0x1d002098, + 0x1d00209c, 0x1d0020a0, 0x1d0020a4, 0x1d0020a8, + 0x1d0020ac, 0x1d0020b0, 0x1d0020b4, 0x1d0020b8, + 0xc6702000, 0xc6702004, 0xc6702008, 0xc670200c, + 0xc6702010, 0xc6702014, 0xc6702018, 0xc670201c, + 0xc6702020, 0xc6702024, 0xc6702028, 0xc670202c, + 0xc6702030, 0xc6702034, 0xc6702038, 0xc670203c, + 0xc6702040, 0xc6702044, 0xc6702048, 0xc670204c, + 0xc6702050, 0xc6702054, 0xc6702058, 0xc670205c, + 0xc6702060, 0xc6702064, 0xc6702068, 0xc670206c, + 0xc6702070, 0xc6702074, 0xc6702078, 0xc670207c, + 0xc6702080, 0xc6702084, 0xc6702088, 0xc670208c, + 0xc6702090, 0xc6702094, 0xc6702098, 0xc670209c, + 0xc67020a0, 0xc67020a4, 0xc67020a8, 0xc1742000, + 0xc1742004, 0xc1742008, 0xc174200c, 0xc1742010, + 0xc1742014, 0xc1742018, 0xc174201c, 0xc1742020, + 0xc1742024, 0xc1742028, 0xc174202c, 0xc1742030, + 0xc1742034, 0xc1742038, 0xc174203c, 0xc1742040, + 0xc1742044, 0xc1742048, 0xc174204c, 0xc1742050, + 0xc1742054, 0xec602000, 0xec602004, 0xec602008, + 0xec60200c, 0xec602010, 0xec602014, 0xec602018, + 0xec60201c, 0xec602020, 0xec602024, 0xec602028, + 0xec60202c, 0xec602030, 0xec602034, 0xec602038, + 0xec60203c, 0xec602040, 0xec602044, 0xec602048, + 0xec60204c, 0xec602050, 0xec602054, 0xec602058, + 0xec60205c, 0xec602060, 0xec602064, 0xec602068, + 0xec60206c, 0xec602070, 0xec602074, 0xec602078, + 0xec60207c, 0xec602080, 0xec602084, 0xec602088, + 0xec60208c, 0xec602090, 0xec602094, 0xec602098, + 0xec60209c, 0xec6020a0, 0xec6020a4, 0xec6020a8, + 0xec6020ac, 0xec6020b0, 0xec6020b4, 0xec6020b8, + 0xec6020bc, 0xec6020c0, 0xec6020c4, 0xec6020c8, + 0xec6020cc, 0xec6020d0, 0xec6020d4, 0xec6020d8, + 0xec6020dc, 0xec6020e0, 0xec6020e4, 0xec6020e8, + 0xec6020ec, 0xec6020f0, 0xec6020f4, 0xec6020f8, + 0xec6020fc, 0xec602100, 0xec602104, 0xec602108, + 0xec60210c, 0xec602110, 0xec602114, 0xec602118, + 0xec60211c, 0xec602120, 0xec602124, 0xec602128, + 0xec60212c, 0xec602130, 0xec602134, 0xec602138, + 0xec60213c, 0xec602140, 0xec602144, 0xec602148, + 0xec60214c, 0xec602150, 0xec602154, 0xec602158, + 0xec60215c, 0xec602160, 0xec602164, 0xec602168, + 0xec60216c, 0xec602170, 0xec602174, 0xec602178, + 0xec60217c, 0xec602180, 0xec602184, 0xec602188, + 0xec60218c, 0xec602190, 0xec602194, 0xec602198, + 0xec60219c, 0xec6021a0, 0xec6021a4, 0xec6021a8, + 0xec6021ac, 0xec6021b0, 0xec6021b4, 0xec6021b8, + 0xec6021bc, 0xec6021c0, 0xec6021c4, 0xec6021c8, + 0xec6021cc, 0xec6021d0, 0xec6021d4, 0xec6021d8, + 0xec6021dc, 0xec6021e0, 0xec6021e4, 0xec6021e8, + 0xec6021ec, 0xec6021f0, 0xec6021f4, 0xec6021f8, + 0xec6021fc, 0xec602200, 0xec602204, 0xec602208, + 0xec60220c, 0xec602210, 0xec602214, 0xec602218, + 0xec60221c, 0xec602220, 0xec602224, 0xec602228, + 0xec60222c, 0xec602230, 0xec602234, 0xec602238, + 0xec60223c, 0xec602240, 0xec602244, 0xec602248, + 0xec60224c, 0xec602250, 0xec602254, 0xec602258, + 0xec60225c, 0xec602260, 0xec602264, 0xec602268, + 0xec60226c, 0xec602270, 0xec602274, 0xec602278, + 0xec60227c, 0xec602280, 0xec602284, 0xec602288, + 0xec60228c, 0xec602290, 0xec602294, 0xec602298, + 0xec60229c, 0xec6022a0, 0xec6022a4, 0xec6022a8, + 0xec6022ac, 0xec6022b0, 0xec6022b4, 0xec6022b8, + 0xec6022bc, 0xec6022c0, 0xec6022c4, 0xec6022c8, + 0xec6022cc, 0xec6022d0, 0xec6022d4, 0xec6022d8, + 0xec6022dc, 0xec6022e0, 0xec6022e4, 0xec6022e8, + 0xec6022ec, 0xec6022f0, 0xec6022f4, 0xec6022f8, + 0xec6022fc, 0xec602300, 0xec602304, 0xec602308, + 0xec60230c, 0xec602310, 0xec602314, 0xec602318, + 0xec60231c, 0xec602320, 0xec602324, 0xec602328, + 0xec60232c, 0xec602330, 0xec602334, 0xec602338, + 0xec60233c, 0xec602340, 0xec602344, 0xec602348, + 0xec60234c, 0xec602350, 0xec602354, 0xec602358, + 0xec60235c, 0xec602360, 0xec602364, 0xec602368, + 0xec60236c, 0xec602370, 0xec602374, 0xec602378, + 0xec60237c, 0xec602380, 0xec602384, 0xec602388, + 0xec60238c, 0xec602390, 0xec602394, 0xec602398, + 0xec60239c, 0xec6023a0, 0xec6023a4, 0xec6023a8, + 0xec6023ac, 0xec6023b0, 0xec6023b4, 0xec6023b8, + 0xec6023bc, 0xec6023c0, 0xec6023c4, 0xec6023c8, + 0xec6023cc, 0xec6023d0, 0xec6023d4, 0xec6023d8, + 0xec6023dc, 0xec6023e0, 0xec6023e4, 0xec6023e8, + 0xec6023ec, 0xec6023f0, 0xec6023f4, 0xec6023f8, + 0xec6023fc, 0xec602400, 0xec602404, 0xec602408, + 0xec60240c, 0xec602410, 0xec602414, 0xec602418, + 0xec60241c, 0xec602420, 0xec602424, 0xec602428, + 0xec60242c, 0xec602430, 0xec602434, 0xec602438, + 0xec60243c, 0xec602440, 0xec602444, 0xec602448, + 0xec60244c, 0xec602450, 0xec602454, 0xec602458, + 0xec60245c, 0xec602460, 0xec602464, 0xec602468, + 0xec60246c, 0xec602470, 0xec602474, 0xec602478, + 0xec60247c, 0xec602480, 0xec602484, 0xec602488, + 0xec60248c, 0xec602490, 0xec602494, 0xec602498, + 0xec60249c, 0xec6024a0, 0xec6024a4, 0xec6024a8, + 0xec6024ac, 0xec6024b0, 0xec6024b4, 0xec6024b8, + 0xec6024bc, 0xec6024c0, 0xec6024c4, 0xec6024c8, + 0xec6024cc, 0xec6024d0, 0xec6024d4, 0xec6024d8, + 0xec6024dc, 0xec6024e0, 0xec6024e4, 0xec6024e8, + 0xec6024ec, 0xec6024f0, 0xec6024f4, 0xec6024f8, + 0xec6024fc, 0xec602500, 0xec602504, 0xec602508, + 0xec60250c, 0xec602510, 0xec602514, 0xec602518, + 0xec60251c, 0xec602520, 0xec602524, 0xec602528, + 0xec60252c, 0xec602530, 0xec602534, 0xec602538, + 0xec60253c, 0xec602540, 0xec602544, 0xec602548, + 0xec60254c, 0xec602550, 0xec602554, 0xec602558, + 0xec60255c, 0xec602560, 0xec602564, 0xec602568, + 0xec60256c, 0xec602570, 0xec602574, 0xec602578, + 0xec60257c, 0xec602580, 0xec602584, 0xec602588, + 0xec60258c, 0xec602590, 0xec602594, 0xec602598, + 0xec60259c, 0xec6025a0, 0xec6025a4, 0xec6025a8, + 0xec6025ac, 0xec6025b0, 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0x1a802124, 0x1a802128, + 0x1a80212c, 0x1a802130, 0x1a802134, 0x1a802138, + 0x1a80213c, 0x1a802140, 0x1a802144, 0x1a802148, + 0x1a80214c, 0x1a802150, 0x1a802154, 0x1a802158, + 0x1a80215c, 0x1a802160, 0x1a802164, 0x1a802168, + 0x1a80216c, 0x1a802170, 0x1a802174, 0x1a802178, + 0x1a80217c, 0x1a802180, 0x1a802184, 0x1a802188, + 0x1a80218c, 0x1a802190, 0x1a802194, 0x1a802198, + 0x1a80219c, 0x1a8021a0, 0x1a8021a4, 0x1a8021a8, + 0x1a8021ac, 0x1a8021b0, 0x1a8021b4, 0x1a8021b8, + 0x1a8021bc, 0x1a8021c0, 0x1a8021c4, 0x1a8021c8, + 0x1a8021cc, 0x1a8021d0, 0x1a8021d4, 0x1a8021d8, + 0x1a8021dc, 0x1a8021e0, 0x1a8021e4, 0x1a8021e8, + 0x1a8021ec, 0x1a8021f0, 0x1a8021f4, 0x1a8021f8, + 0x1a8021fc, 0x1a802200, 0x1a802204, 0x1a802208, + 0x1a80220c, 0x1a802210, 0x1a802214, 0x1a802218, + 0x1a80221c, 0x1a802220, 0x1a802224, 0x1a802228, + 0x1a80222c, 0x1a802230, 0x1a802234, 0x1a802238, + 0x1a80223c, 0x1a802240, 0x1a802244, 0x1a802248, + 0x1a80224c, 0x1a802250, 0x1a802254, 0x1a802258, + 0x1a80225c, 0x1a802260, 0x1a802264, 0x1a802268, + 0x1a80226c, 0x1a802270, 0x1a802274, 0x1a802278, + 0x1a80227c, 0x1a802280, 0x1a802284, 0x1a802288, + 0x1a80228c, 0x1a802290, 0x1a802294, 0x1a802298, + 0x1a80229c, 0x1a8022a0, 0x1a8022a4, 0x1a8022a8, + 0x1a8022ac, 0x1a8022b0, 0x1a8022b4, 0x1a8022b8, + 0x1a8022bc, 0x1a8022c0, 0x1a8022c4, 0x1a8022c8, + 0x1a8022cc, 0x1a8022d0, 0x1a8022d4, 0x1a8022d8, + 0x1a8022dc, 0x1a8022e0, 0x1a8022e4, 0x1a8022e8, + 0x1a8022ec, 0x1a8022f0, 0x1a8022f4, 0x1a8022f8, + 0x1a8022fc, 0x1a802300, 0x1a802304, 0x1a802308, + 0x1a80230c, 0x1a802310, 0x1a802314, 0x1a802318, + 0x1a80231c, 0x1a802320, 0x1a802324, 0x1a802328, + 0x1a80232c, 0x1a802330, 0x1a802334, 0x1a802338, + 0x1a80233c, 0x1a802340, 0x1a802344, 0x1a802348, + 0x1a80234c, 0x1a802350, 0x1a802354, 0x1a802358, + 0x1a80235c, 0x1a802360, 0x1a802364, 0x1a802368, + 0x1a80236c, 0x1a802370, 0x1a802374, 0x1a802378, + 0x1a80237c, 0x1a802380, 0x1a802384, 0x1a802388, + 0x1a80238c, 0x1a802390, 0x1a802394, 0x1a802398, + 0x1a80239c, 0x1a8023a0, 0x1a8023a4, 0x1a8023a8, + 0x1a8023ac, 0x1a8023b0, 0x1a8023b4, 0x1a8023b8, + 0x1a8023bc, 0x1a8023c0, 0x1a8023c4, 0x1a8023c8, + 0x1a8023cc, 0x1a8023d0, 0x1a8023d4, 0x1a8023d8, + 0x1a8023dc, 0x1a8023e0, 0x1a8023e4, 0x1a8023e8, + 0x1a8023ec, 0x1a8023f0, 0x1a8023f4, 0x1a8023f8, + 0x1a8023fc, 0x1a802400, 0x1a802404, 0x1a802408, + 0x1a80240c, 0x1a802410, 0x1a802414, 0x1a802418, + 0x1a80241c, 0x1a802420, 0x1a802424, 0x1a802428, + 0x1a80242c, 0x1a802430, 0x1a802434, 0x1a802438, + 0x1a80243c, 0x1a802440, 0x1a802444, 0x1a802448, + 0x1a80244c, 0x1a802450, 0x1a802454, 0x1a802458, + 0x1a80245c, 0x1a802460, 0x1a802464, 0x1a802468, + 0x1a80246c, 0x1a802470, 0x1a802474, 0x1a802478, + 0x1a80247c, 0x1a802480, 0x1a802484, 0x1a802488, + 0x1a80248c, 0x1a802490, 0x1a802494, 0x1a802498, + 0x1a80249c, 0x1a8024a0, 0x1a8024a4, 0x1a8024a8, + 0x1a8024ac, 0x1a8024b0, 0x1a8024b4, 0x1a8024b8, + 0x1a8024bc, 0x1a8024c0, 0x1a8024c4, 0x1a8024c8, + 0x1a8024cc, 0x1a8024d0, 0x1a8024d4, 0x1a8024d8, + 0x1a8024dc, 0x1a8024e0, 0x1a8024e4, 0x1a8024e8, + 0x1a8024ec, 0x1a8024f0, 0x1a8024f4, 0x1a8024f8, + 0x1a8024fc, 0x1a802500, 0x1a802504, 0x1a802508, + 0x1a80250c, 0x1a802510, 0x1a802514, 0x1a802518, + 0x1a80251c, 0x1a802520, 0x1a802524, 0x1a802528, + 0x1a80252c, 0x1a802530, 0x1a802534, 0x1a802538, + 0x1a80253c, 0x1a802540, 0x1a802544, 0x1a802548, + 0x1a80254c, 0x1a802550, 0x1a802554, 0x1a802558, + 0x1a80255c, 0x1a802560, 0x1a802564, 0x1a802568, + 0x1a80256c, 0x1a802570, 0x1a802574, 0x1a802578, + 0x1a80257c, 0x1a802580, 0x1a802584, 0x1a802588, + 0x1a80258c, 0x1a802590, 0x1a802594, 0x1a802598, + 0x1a80259c, 0x1a8025a0, 0x1a8025a4, 0x1a8025a8, + 0x1a8025ac, 0x1a8025b0, 0x1a8025b4, 0x1a8025b8, + 0x1a8025bc, 0x1a8025c0, 0x1a8025c4, 0x1a8025c8, + 0x1a8025cc, 0x1a8025d0, 0x1a8025d4, 0x1a8025d8, + 0x18b42000, 0x18b42004, 0x18b42008, 0x18b4200c, + 0x18b42010, 0x18b42014, 0x18b42018, 0x18b4201c, + 0x18b42020, 0x18b42024, 0x18b42028, 0x18b4202c, + 0x18b42030, 0x18b42034, 0x18b42038, 0x18b4203c, + 0x18b42040, 0x18b42044, 0x18b42048, 0x18b4204c, + 0x18b42050, 0x18b42054, 0x18b42058, 0x18b4205c, + 0x18b42060, 0x18b42064, 0x18b42068, 0x18b4206c, + 0x18b42070, 0x18b42074, 0x18b42078, 0x18b4207c, + 0x18b42080, 0x18b42084, 0x18b42088, 0x18b4208c, + 0x18b42090, 0x18b42094, 0x18b42098, 0x18b4209c, + 0x18b420a0, 0x18b420a4, 0x18b420a8, 0x18b420ac, + 0x18b420b0, 0x18b420b4, 0x18b420b8, 0x18b420bc, + 0x18b420c0, 0x18b420c4, 0x18b420c8, 0x18b420cc, + 0x18b420d0, 0x18b420d4, 0x18b420d8, 0x18b420dc, + 0x18b420e0, 0x18b420e4, 0x18b420e8, 0x18b420ec, + 0x18b420f0, 0x18b420f4, 0x18b420f8, 0x18b420fc, + 0x18b42100, 0x18b42104, 0x18b42108, 0x18b4210c, + 0x18b42110, 0x18b42114, 0x18b42118, 0x18b4211c, + 0x18b42120, 0x18b42124, 0x18b42128, 0x18b4212c, + 0x18b42130, 0x18b42134, 0x18b42138, 0x18b4213c, + 0x18b42140, 0x18b42144, 0x18b42148, 0x18b4214c, + 0x18b42150, 0x18b42154, 0x18b42158, 0x18b4215c, + 0x18b42160, 0x18b42164, 0x18b42168, 0x18b4216c, + 0x18b42170, 0x18b42174, 0x18b42178, 0x18b4217c, + 0x18b42180, 0x18b42184, 0x18b42188, 0x18b4218c, + 0x18b42190, 0x18b42194, 0x18b42198, 0x18b4219c, + 0x18b421a0, 0x18b421a4, 0x18b421a8, 0x18b421ac, + 0x18b421b0, 0x18b421b4, 0x18b421b8, 0x18b421bc, + 0x18b421c0, 0x18b421c4, 0x18b421c8, 0x18b421cc, + 0x18b421d0, 0x18b421d4, 0x18b421d8, 0x18b421dc, + 0x18b421e0, 0x18b421e4, 0x18b421e8, 0x18b421ec, + 0x18b421f0, 0x18b421f4, 0x18b421f8, 0x18b421fc, + 0x18b42200, 0x18b42204, 0x18b42208, 0x18b4220c, + 0x18b42210, 0x18b42214, 0x18b42218, 0x18b4221c, + 0x18b42220, 0x18b42224, 0x18b42228, 0x18b4222c, + 0x18b42230, 0xc1282000, 0xc1282004, 0xc1282008, + 0xc128200c, 0xc1282010, 0xc1282014, 0xc1282018, + 0xc128201c, 0xc1282020, 0xc1282024, 0xc1282028, + 0xc128202c, 0xc1282030, 0xc1282034, 0xc1282038, + 0xc128203c, 0xc1282040, 0xc1282044, 0xc1282048, + 0xc128204c, 0xc1282050, 0xc1282054, 0xc1282058, + 0xc128205c, 0xc1282060, 0xc1282064, 0xc1282068, + 0xc128206c, 0xc1282070, 0xc1282074, 0xc1282078, + 0xc128207c, 0xc1282080, 0xc1282084, 0xc1282088, + 0xc128208c, 0xc1282090, 0xc1282094, 0xc1282098, + 0xc128209c, 0xc12820a0, 0xc12820a4, 0xc12820a8, + 0xc12820ac, 0xc12820b0, 0xc12820b4, 0xc12820b8, + 0xc12820bc, 0xc12820c0, 0xc12820c4, 0xc12820c8, + 0xc12820cc, 0xc12820d0, 0xc12820d4, 0xc12820d8, + 0xc12820dc, 0xc12820e0, 0xc12820e4, 0xc12820e8, + 0xc12820ec, 0xc12820f0, 0xc12820f4, 0xc12820f8, + 0xc12820fc, 0xc1282100, 0xc1282104, 0xc1282108, + 0xc128210c, 0xc1282110, 0xc1282114, 0xc1282118, + 0xc128211c, 0xc1282120, 0xc1282124, 0xc1282128, + 0xc128212c, 0xc1282130, 0xc1282134, 0xc1282138, + 0xc128213c, 0xc1282140, 0xc1282144, 0xc1282148, + 0xc128214c, 0xc1282150, 0xc1282154, 0xc1282158, + 0xc128215c, 0xc1282160, 0xc1282164, 0xc1282168, + 0xc128216c, 0xc1282170, 0xc1282174, 0xc1282178, + 0xc128217c, 0xc1282180, 0xc1282184, 0xc1282188, + 0xc128218c, 0xc1282190, 0xc1282194, 0xc1282198, + 0xc128219c, 0xc12821a0, 0xc12821a4, 0xc12821a8, + 0xc12821ac, 0xc12821b0, 0xc12821b4, 0xc12821b8, + 0xc12821bc, 0xc12821c0, 0xc12821c4, 0xc12821c8, + 0xc12821cc, 0xc12821d0, 0xc12821d4, 0xc12821d8, + 0xc12821dc, 0xc12821e0, 0xc12821e4, 0xc12821e8, + 0xc12821ec, 0xc12821f0, 0xc12821f4, 0xc12821f8, + 0xc12821fc, 0xc1282200, 0xc1282204, 0xc1282208, + 0xc128220c, 0xc1282210, 0xc1282214, 0xc1282218, + 0xc128221c, 0xc1282220, 0xc1282224, 0xc1282228, + 0xc128222c, 0xc1282230, 0xc1282234, 0xc1282238, + 0xc128223c, 0xc1282240, 0xc1282244, 0xc1282248, + 0xc128224c, 0xc1282250, 0xc1282254, 0xc1282258, + 0xc128225c, 0xc1282260, 0xc1282264, 0xc1282268, + 0xc128226c, 0xc1282270, 0xc1282274, 0xc1282278, + 0xc128227c, 0xc1282280, 0xc1282284, 0xc1282288, + 0xc128228c, 0xc1282290, 0xc1282294, 0xc1282298, + 0xc128229c, 0xc12822a0, 0xc12822a4, 0xc12822a8, + 0xc12822ac, 0xc12822b0, 0xc12822b4, 0xc12822b8, + 0xc6802000, 0xc6802004, 0xc6802008, 0xc680200c, + 0xc6802010, 0xc6802014, 0xc6802018, 0xc680201c, + 0xc6802020, 0xc6802024, 0xc6802028, 0xc680202c, + 0xc6802030, 0xc6802034, 0xc6802038, 0xc680203c, + 0xc6802040, 0xc6802044, 0xc6802048, 0xc680204c, + 0xc6802050, 0xc6802054, 0xc6802058, 0xc680205c, + 0xc6802060, 0xc6802064, 0xc6802068, 0xc680206c, + 0xc6802070, 0xc6802074, 0xc6802078, 0xc680207c, + 0xc6802080, 0xc6802084, 0xc6802088, 0xc680208c, + 0xc6802090, 0xc6802094, 0xc6802098, 0xc680209c, + 0xc68020a0, 0xc68020a4, 0xc68020a8, 0xc68020ac, + 0xc68020b0, 0xc68020b4, 0xc68020b8, 0xc68020bc, + 0xc68020c0, 0xc68020c4, 0xc68020c8, 0xc68020cc, + 0xc5802000, 0xc5802004, 0xc5802008, 0xc580200c, + 0xc5802010, 0xc5802014, 0xc5802018, 0xc580201c, + 0xc5802020, 0xc5802024, 0xc5802028, 0xc580202c, + 0xc5802030, 0xc5802034, 0xc5802038, 0xc580203c, + 0xc5802040, 0xc5802044, 0xc5802048, 0xc580204c, + 0xc5802050, 0xc5802054, 0xc5802058, 0xc580205c, + 0xc5802060, 0xc5802064, 0xc5802068, 0xc580206c, + 0xc5802070, 0xc5802074, 0xc5802078, 0xc580207c, + 0xc5802080, 0xc5802084, 0xc5802088, 0xc580208c, + 0xc5802090, 0xc5802094, 0xc5802098, 0xc580209c, + 0xc58020a0, 0xc58020a4, 0xc58020a8, 0xc58020ac, + 0xc58020b0, 0xc58020b4, 0xc58020b8, 0xc58020bc, + 0xc58020c0, 0xc58020c4, 0xc58020c8, 0xc58020cc, + 0xc58020d0, 0xc58020d4, 0xc58020d8, 0xc58020dc, + 0xc58020e0, 0xc58020e4, 0xc58020e8, 0xc58020ec, + 0xc58020f0, 0xc58020f4, 0xc58020f8, 0xc58020fc, + 0xc5802100, 0xc5802104, 0xc5802108, 0xc580210c, + 0xc5802110, 0xc5802114, 0xc5802118, 0xc580211c, + 0xc5802120, 0xc5802124, 0xc5802128, 0xc580212c, + 0xc5802130, 0xc5802134, 0xc5802138, 0xc580213c, + 0xc5802140, 0xc5802144, 0xc5802148, 0xc580214c, + 0xc5802150, 0xc5802154, 0xc5802158, 0xc580215c, + 0xc5802160, 0xc5802164, 0xc5802168, 0xc580216c, + 0xc5802170, 0xc5802174, 0xc5802178, 0xc580217c, + 0xc5802180, 0xc5802184, 0xc5802188, 0xc580218c, + 0xc5802190, 0xc5802194, 0xc5802198, 0xc580219c, + 0xc58021a0, 0xc58021a4, 0xc58021a8, 0xc58021ac, + 0xc58021b0, 0xc58021b4, 0xc58021b8, 0xc58021bc, + 0xc58021c0, 0xc58021c4, 0xc58021c8, 0xc58021cc, + 0xc58021d0, 0xc58021d4, 0xc58021d8, 0xc58021dc, + 0xc58021e0, 0xc58021e4, 0xc58021e8, 0xc58021ec, + 0xc58021f0, 0xc58021f4, 0xc58021f8, 0xc58021fc, + 0xc5802200, 0xc5802204, 0xc5802208, 0xc580220c, + 0xc5802210, 0xc5802214, 0xc5802218, 0xc580221c, + 0xc5802220, 0xc5802224, 0xc5802228, 0xc580222c, + 0xc5802230, 0xc5802234, 0xc5802238, 0xc580223c, + 0xc5802240, 0xc5802244, 0xc5802248, 0xc580224c, + 0xc5802250, 0xc5802254, 0xc5802258, 0xc580225c, + 0xc5802260, 0xc5802264, 0xc5802268, 0xc580226c, + 0xc5802270, 0xc5802274, 0xc5802278, 0xc580227c, + 0xc5802280, 0xc5802284, 0xc5802288, 0xc580228c, + 0xc5802290, 0xc5802294, 0xc5802298, 0xc580229c, + 0xc58022a0, 0xc58022a4, 0xc58022a8, 0xc58022ac, + 0xc58022b0, 0xc58022b4, 0xc58022b8, 0xc58022bc, + 0xc58022c0, 0xc58022c4, 0xc58022c8, 0xc58022cc, + 0xc58022d0, 0xc58022d4, 0xc58022d8, 0xc58022dc, + 0xc58022e0, 0xc58022e4, 0xc58022e8, 0xc58022ec, + 0xc58022f0, 0xc58022f4, 0xc58022f8, 0xc58022fc, + 0xc5802300, 0xc5802304, 0xc5802308, 0xc580230c, + 0xc3022000, 0xc3022004, 0xc3022008, 0xc302200c, + 0xc3022010, 0xc3022014, 0xc3022018, 0xc302201c, + 0xc3022020, 0xc3022024, 0xc3022028, 0xc302202c, + 0xc3022030, 0xc3022034, 0xc3022038, 0xc302203c, + 0xc3022040, 0xc3022044, 0xc3022048, 0xc302204c, + 0xc3022050, 0xc3022054, 0xc3022058, 0xc302205c, + 0xc3022060, 0xc3022064, 0xc3022068, 0xc302206c, + 0xc3022070, 0xc3022074, 0xc3022078, 0xc302207c, + 0xc3022080, 0xc3022084, 0xc3022088, 0xc302208c, + 0xc3022090, 0xc3022094, 0xc3022098, 0xc302209c, + 0xc30220a0, 0xc30220a4, 0xc30220a8, 0xc30220ac, + 0xc30220b0, 0xc3422000, 0xc3422004, 0xc3422008, + 0xc342200c, 0xc3422010, 0xc3422014, 0xc3422018, + 0xc342201c, 0xc3422020, 0xc3422024, 0xc3422028, + 0xc342202c, 0xc3422030, 0xc3422034, 0xc3422038, + 0xc342203c, 0xc3422040, 0xc3422044, 0xc3422048, + 0xc342204c, 0xc3422050, 0xc3422054, 0xc3422058, + 0xc342205c, 0xc3422060, 0xc3422064, 0xc3422068, + 0xc342206c, 0xc3422070, 0xc3422074, 0xc3422078, + 0xc342207c, 0xc3422080, 0xc3422084, 0xc3422088, + 0xc342208c, 0xc3422090, 0xc3422094, 0xc3422098, + 0xc342209c, 0xc34220a0, 0xc34220a4, 0xc34220a8, + 0xc34220ac, 0xc34220b0 +}; + +static const u32 rgidw_register_list[] = { + 0xe8026000, 0xe8026004, 0xe8026008, 0xe802600c, + 0xe8026010, 0xe8026014, 0xe8026018, 0xe802601c, + 0xe8026020, 0xe8026024, 0xe8026028, 0xe802602c, + 0xe8026030, 0xe8026034, 0xe8026038, 0xe802603c, + 0xe8026040, 0xe8026044, 0xe8026048, 0xe802604c, + 0xe80a6000, 0xe80a6004, 0xe80a6008, 0xe80a600c, + 0xe80a6010, 0xe80a6014, 0xe80a6018, 0xe80a601c, + 0xe80a6020, 0xe80a6024, 0xe80a6028, 0xe80a602c, + 0xe80a6030, 0xe80a6034, 0xe80a6038, 0xe80a603c, + 0xe80a6040, 0xe80a6044, 0xe80a6048, 0xe80a604c, + 0xe8126000, 0xe8126004, 0xe8126008, 0xe812600c, + 0xe8126010, 0xe8126014, 0xe8126018, 0xe812601c, + 0xe8126020, 0xe8126024, 0xe8126028, 0xe812602c, + 0xe8126030, 0xe8126034, 0xe8126038, 0xe812603c, + 0xe8126040, 0xe8126044, 0xe8126048, 0xe812604c, + 0xe81a6000, 0xe81a6004, 0xe81a6008, 0xe81a600c, + 0xe81a6010, 0xe81a6014, 0xe81a6018, 0xe81a601c, + 0xe81a6020, 0xe81a6024, 0xe81a6028, 0xe81a602c, + 0xe81a6030, 0xe81a6034, 0xe81a6038, 0xe81a603c, + 0xe81a6040, 0xe81a6044, 0xe81a6048, 0xe81a604c, + 0xe8226000, 0xe8226004, 0xe8226008, 0xe822600c, + 0xe8226010, 0xe8226014, 0xe8226018, 0xe822601c, + 0xe8226020, 0xe8226024, 0xe8226028, 0xe822602c, + 0xe8226030, 0xe8226034, 0xe8226038, 0xe822603c, + 0xe8226040, 0xe8226044, 0xe8226048, 0xe822604c, + 0xe82a6000, 0xe82a6004, 0xe82a6008, 0xe82a600c, + 0xe82a6010, 0xe82a6014, 0xe82a6018, 0xe82a601c, + 0xe82a6020, 0xe82a6024, 0xe82a6028, 0xe82a602c, + 0xe82a6030, 0xe82a6034, 0xe82a6038, 0xe82a603c, + 0xe82a6040, 0xe82a6044, 0xe82a6048, 0xe82a604c, + 0xe8326000, 0xe8326004, 0xe8326008, 0xe832600c, + 0xe8326010, 0xe8326014, 0xe8326018, 0xe832601c, + 0xe8326020, 0xe8326024, 0xe8326028, 0xe832602c, + 0xe8326030, 0xe8326034, 0xe8326038, 0xe832603c, + 0xe8326040, 0xe8326044, 0xe8326048, 0xe832604c, + 0xe83a6000, 0xe83a6004, 0xe83a6008, 0xe83a600c, + 0xe83a6010, 0xe83a6014, 0xe83a6018, 0xe83a601c, + 0xe83a6020, 0xe83a6024, 0xe83a6028, 0xe83a602c, + 0xe83a6030, 0xe83a6034, 0xe83a6038, 0xe83a603c, + 0xe83a6040, 0xe83a6044, 0xe83a6048, 0xe83a604c, + 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0xc128604c, 0xc1286050, 0xc1286054, 0xc1286058, + 0xc128605c, 0xc1286060, 0xc1286064, 0xc1286068, + 0xc128606c, 0xc1286070, 0xc1286074, 0xc1286078, + 0xc128607c, 0xc1286080, 0xc1286084, 0xc1286088, + 0xc128608c, 0xc1286090, 0xc1286094, 0xc1286098, + 0xc128609c, 0xc12860a0, 0xc12860a4, 0xc12860a8, + 0xc12860ac, 0xc12860b0, 0xc12860b4, 0xc12860b8, + 0xc12860bc, 0xc12860c0, 0xc12860c4, 0xc12860c8, + 0xc12860cc, 0xc12860d0, 0xc12860d4, 0xc12860d8, + 0xc12860dc, 0xc12860e0, 0xc12860e4, 0xc12860e8, + 0xc12860ec, 0xc12860f0, 0xc12860f4, 0xc12860f8, + 0xc12860fc, 0xc1286100, 0xc1286104, 0xc1286108, + 0xc128610c, 0xc1286110, 0xc1286114, 0xc1286118, + 0xc128611c, 0xc1286120, 0xc1286124, 0xc1286128, + 0xc128612c, 0xc1286130, 0xc1286134, 0xc1286138, + 0xc128613c, 0xc1286140, 0xc1286144, 0xc1286148, + 0xc128614c, 0xc1286150, 0xc1286154, 0xc1286158, + 0xc128615c, 0xc1286160, 0xc1286164, 0xc1286168, + 0xc128616c, 0xc1286170, 0xc1286174, 0xc1286178, + 0xc128617c, 0xc1286180, 0xc1286184, 0xc1286188, + 0xc128618c, 0xc1286190, 0xc1286194, 0xc1286198, + 0xc128619c, 0xc12861a0, 0xc12861a4, 0xc12861a8, + 0xc12861ac, 0xc12861b0, 0xc12861b4, 0xc12861b8, + 0xc12861bc, 0xc12861c0, 0xc12861c4, 0xc12861c8, + 0xc12861cc, 0xc12861d0, 0xc12861d4, 0xc12861d8, + 0xc12861dc, 0xc12861e0, 0xc12861e4, 0xc12861e8, + 0xc12861ec, 0xc12861f0, 0xc12861f4, 0xc12861f8, + 0xc12861fc, 0xc1286200, 0xc1286204, 0xc1286208, + 0xc128620c, 0xc1286210, 0xc1286214, 0xc1286218, + 0xc128621c, 0xc1286220, 0xc1286224, 0xc1286228, + 0xc128622c, 0xc1286230, 0xc1286234, 0xc1286238, + 0xc128623c, 0xc1286240, 0xc1286244, 0xc1286248, + 0xc128624c, 0xc1286250, 0xc1286254, 0xc1286258, + 0xc128625c, 0xc1286260, 0xc1286264, 0xc1286268, + 0xc128626c, 0xc1286270, 0xc1286274, 0xc1286278, + 0xc128627c, 0xc1286280, 0xc1286284, 0xc1286288, + 0xc128628c, 0xc1286290, 0xc1286294, 0xc1286298, + 0xc128629c, 0xc12862a0, 0xc12862a4, 0xc12862a8, + 0xc12862ac, 0xc12862b0, 0xc12862b4, 0xc12862b8, + 0xc6806000, 0xc6806004, 0xc6806008, 0xc680600c, + 0xc6806010, 0xc6806014, 0xc6806018, 0xc680601c, + 0xc6806020, 0xc6806024, 0xc6806028, 0xc680602c, + 0xc6806030, 0xc6806034, 0xc6806038, 0xc680603c, + 0xc6806040, 0xc6806044, 0xc6806048, 0xc680604c, + 0xc6806050, 0xc6806054, 0xc6806058, 0xc680605c, + 0xc6806060, 0xc6806064, 0xc6806068, 0xc680606c, + 0xc6806070, 0xc6806074, 0xc6806078, 0xc680607c, + 0xc6806080, 0xc6806084, 0xc6806088, 0xc680608c, + 0xc6806090, 0xc6806094, 0xc6806098, 0xc680609c, + 0xc68060a0, 0xc68060a4, 0xc68060a8, 0xc68060ac, + 0xc68060b0, 0xc68060b4, 0xc68060b8, 0xc68060bc, + 0xc68060c0, 0xc68060c4, 0xc68060c8, 0xc68060cc, + 0xc5806000, 0xc5806004, 0xc5806008, 0xc580600c, + 0xc5806010, 0xc5806014, 0xc5806018, 0xc580601c, + 0xc5806020, 0xc5806024, 0xc5806028, 0xc580602c, + 0xc5806030, 0xc5806034, 0xc5806038, 0xc580603c, + 0xc5806040, 0xc5806044, 0xc5806048, 0xc580604c, + 0xc5806050, 0xc5806054, 0xc5806058, 0xc580605c, + 0xc5806060, 0xc5806064, 0xc5806068, 0xc580606c, + 0xc5806070, 0xc5806074, 0xc5806078, 0xc580607c, + 0xc5806080, 0xc5806084, 0xc5806088, 0xc580608c, + 0xc5806090, 0xc5806094, 0xc5806098, 0xc580609c, + 0xc58060a0, 0xc58060a4, 0xc58060a8, 0xc58060ac, + 0xc58060b0, 0xc58060b4, 0xc58060b8, 0xc58060bc, + 0xc58060c0, 0xc58060c4, 0xc58060c8, 0xc58060cc, + 0xc58060d0, 0xc58060d4, 0xc58060d8, 0xc58060dc, + 0xc58060e0, 0xc58060e4, 0xc58060e8, 0xc58060ec, + 0xc58060f0, 0xc58060f4, 0xc58060f8, 0xc58060fc, + 0xc5806100, 0xc5806104, 0xc5806108, 0xc580610c, + 0xc5806110, 0xc5806114, 0xc5806118, 0xc580611c, + 0xc5806120, 0xc5806124, 0xc5806128, 0xc580612c, + 0xc5806130, 0xc5806134, 0xc5806138, 0xc580613c, + 0xc5806140, 0xc5806144, 0xc5806148, 0xc580614c, + 0xc5806150, 0xc5806154, 0xc5806158, 0xc580615c, + 0xc5806160, 0xc5806164, 0xc5806168, 0xc580616c, + 0xc5806170, 0xc5806174, 0xc5806178, 0xc580617c, + 0xc5806180, 0xc5806184, 0xc5806188, 0xc580618c, + 0xc5806190, 0xc5806194, 0xc5806198, 0xc580619c, + 0xc58061a0, 0xc58061a4, 0xc58061a8, 0xc58061ac, + 0xc58061b0, 0xc58061b4, 0xc58061b8, 0xc58061bc, + 0xc58061c0, 0xc58061c4, 0xc58061c8, 0xc58061cc, + 0xc58061d0, 0xc58061d4, 0xc58061d8, 0xc58061dc, + 0xc58061e0, 0xc58061e4, 0xc58061e8, 0xc58061ec, + 0xc58061f0, 0xc58061f4, 0xc58061f8, 0xc58061fc, + 0xc5806200, 0xc5806204, 0xc5806208, 0xc580620c, + 0xc5806210, 0xc5806214, 0xc5806218, 0xc580621c, + 0xc5806220, 0xc5806224, 0xc5806228, 0xc580622c, + 0xc5806230, 0xc5806234, 0xc5806238, 0xc580623c, + 0xc5806240, 0xc5806244, 0xc5806248, 0xc580624c, + 0xc5806250, 0xc5806254, 0xc5806258, 0xc580625c, + 0xc5806260, 0xc5806264, 0xc5806268, 0xc580626c, + 0xc5806270, 0xc5806274, 0xc5806278, 0xc580627c, + 0xc5806280, 0xc5806284, 0xc5806288, 0xc580628c, + 0xc5806290, 0xc5806294, 0xc5806298, 0xc580629c, + 0xc58062a0, 0xc58062a4, 0xc58062a8, 0xc58062ac, + 0xc58062b0, 0xc58062b4, 0xc58062b8, 0xc58062bc, + 0xc58062c0, 0xc58062c4, 0xc58062c8, 0xc58062cc, + 0xc58062d0, 0xc58062d4, 0xc58062d8, 0xc58062dc, + 0xc58062e0, 0xc58062e4, 0xc58062e8, 0xc58062ec, + 0xc58062f0, 0xc58062f4, 0xc58062f8, 0xc58062fc, + 0xc5806300, 0xc5806304, 0xc5806308, 0xc580630c, + 0xc3026000, 0xc3026004, 0xc3026008, 0xc302600c, + 0xc3026010, 0xc3026014, 0xc3026018, 0xc302601c, + 0xc3026020, 0xc3026024, 0xc3026028, 0xc302602c, + 0xc3026030, 0xc3026034, 0xc3026038, 0xc302603c, + 0xc3026040, 0xc3026044, 0xc3026048, 0xc302604c, + 0xc3026050, 0xc3026054, 0xc3026058, 0xc302605c, + 0xc3026060, 0xc3026064, 0xc3026068, 0xc302606c, + 0xc3026070, 0xc3026074, 0xc3026078, 0xc302607c, + 0xc3026080, 0xc3026084, 0xc3026088, 0xc302608c, + 0xc3026090, 0xc3026094, 0xc3026098, 0xc302609c, + 0xc30260a0, 0xc30260a4, 0xc30260a8, 0xc30260ac, + 0xc30260b0, 0xc3426000, 0xc3426004, 0xc3426008, + 0xc342600c, 0xc3426010, 0xc3426014, 0xc3426018, + 0xc342601c, 0xc3426020, 0xc3426024, 0xc3426028, + 0xc342602c, 0xc3426030, 0xc3426034, 0xc3426038, + 0xc342603c, 0xc3426040, 0xc3426044, 0xc3426048, + 0xc342604c, 0xc3426050, 0xc3426054, 0xc3426058, + 0xc342605c, 0xc3426060, 0xc3426064, 0xc3426068, + 0xc342606c, 0xc3426070, 0xc3426074, 0xc3426078, + 0xc342607c, 0xc3426080, 0xc3426084, 0xc3426088, + 0xc342608c, 0xc3426090, 0xc3426094, 0xc3426098, + 0xc342609c, 0xc34260a0, 0xc34260a4, 0xc34260a8, + 0xc34260ac, 0xc34260b0 +}; + +static const u32 sec_modid_register_list[] = { + 0xe8023800, 0xe8023804, 0xe8023808, 0xe802380c, + 0xe8023810, 0xe8023814, 0xe80a3800, 0xe80a3804, + 0xe80a3808, 0xe80a380c, 0xe80a3810, 0xe80a3814, + 0xe8123800, 0xe8123804, 0xe8123808, 0xe812380c, + 0xe8123810, 0xe8123814, 0xe81a3800, 0xe81a3804, + 0xe81a3808, 0xe81a380c, 0xe81a3810, 0xe81a3814, + 0xe8223800, 0xe8223804, 0xe8223808, 0xe822380c, + 0xe8223810, 0xe8223814, 0xe82a3800, 0xe82a3804, + 0xe82a3808, 0xe82a380c, 0xe82a3810, 0xe82a3814, + 0xe8323800, 0xe8323804, 0xe8323808, 0xe832380c, + 0xe8323810, 0xe8323814, 0xe83a3800, 0xe83a3804, + 0xe83a3808, 0xe83a380c, 0xe83a3810, 0xe83a3814, + 0xc0623800, 0xc0623804, 0xc0623808, 0xc062380c, + 0xc0623810, 0xc0623814, 0xc0623818, 0xc062381c, + 0xc0623820, 0xc0623824, 0xc0623828, 0xc0763800, + 0xc0763804, 0xc0763808, 0xc076380c, 0xc0763810, + 0xc0763814, 0xc0763818, 0xc076381c, 0xc0763820, + 0xc0763824, 0xc0763828, 0xc076382c, 0xc0763830, + 0xc0763834, 0xc0763838, 0xc076383c, 0xc0763840, + 0xc0763844, 0xc0763848, 0xc076384c, 0xc0763850, + 0xc0763854, 0xc0763858, 0xc076385c, 0xc0763860, + 0xc0763864, 0xc0763868, 0xc076386c, 0xc0763870, + 0xc0763874, 0xc0763878, 0xc076387c, 0xc0763880, + 0xc0763884, 0xc0763888, 0xc076388c, 0xc0763890, + 0xc0763894, 0xc0763898, 0xc076389c, 0xc07638a0, + 0xc07638a4, 0xc07638a8, 0xc07638ac, 0xc07638b0, + 0xc07a3800, 0xc07a3804, 0xc07a3808, 0xc07a380c, + 0xc07a3810, 0xc07a3814, 0xc07a3818, 0xc07a381c, + 0xc07a3820, 0xc07a3824, 0xc07a3828, 0xc07a382c, + 0x1d003800, 0x1d003804, 0x1d003808, 0x1d00380c, + 0x1d003810, 0x1d003814, 0x1d003818, 0x1d00381c, + 0x1d003820, 0x1d003824, 0x1d003828, 0x1d00382c, + 0x1d003830, 0x1d003834, 0x1d003838, 0x1d00383c, + 0x1d003840, 0x1d003844, 0x1d003848, 0x1d00384c, + 0x1d003850, 0x1d003854, 0x1d003858, 0x1d00385c, + 0x1d003860, 0x1d003864, 0x1d003868, 0x1d00386c, + 0x1d003870, 0x1d003874, 0x1d003878, 0x1d00387c, + 0x1d003880, 0x1d003884, 0xc6703800, 0xc6703804, + 0xc6703808, 0xc670380c, 0xc6703810, 0xc6703814, + 0xc6703818, 0xc670381c, 0xc6703820, 0xc6703824, + 0xc6703828, 0xc670382c, 0xc6703830, 0xc6703834, + 0xc6703838, 0xc670383c, 0xc6703840, 0xc6703844, + 0xc6703848, 0xc1743800, 0xc1743804, 0xc1743808, + 0xc174380c, 0xc1743810, 0xc1743814, 0xc1743818, + 0xc174381c, 0xc1743820, 0xc1743824, 0xc1743828, + 0xec603800, 0xec603804, 0xec603808, 0xec60380c, + 0xec603810, 0xec603814, 0xec603818, 0xec60381c, + 0xec603820, 0xec603824, 0xec603828, 0xec60382c, + 0xec603830, 0xec603834, 0xec603838, 0xec60383c, + 0xec603840, 0xec603844, 0xec603848, 0xec60384c, + 0xec603850, 0xec603854, 0xec603858, 0xec60385c, + 0xec603860, 0xec603864, 0xec603868, 0xec60386c, + 0xec603870, 0xec603874, 0xec603878, 0xec60387c, + 0xec603880, 0xec603884, 0xec603888, 0xec60388c, + 0xec603890, 0xec603894, 0xec603898, 0xec60389c, + 0xec6038a0, 0xec6038a4, 0xec6038a8, 0xec6038ac, + 0xec6038b0, 0xe9e23800, 0xe9e23804, 0xe9e23808, + 0x3fe08000, 0x3fe08000, 0x3fe08000, 0xca443800, + 0xca443804, 0xca443808, 0xca44380c, 0xca443810, + 0xca443814, 0xca443818, 0xca44381c, 0xca443820, + 0xca443824, 0xca543800, 0xca543804, 0xca543808, + 0xca54380c, 0xca543810, 0xca543814, 0xca543818, + 0xca54381c, 0xca543820, 0xcbf03800, 0xcbf03804, + 0xcbf03808, 0xcbf0380c, 0xcbf03810, 0xcbf03814, + 0xcbf03818, 0xcbf0381c, 0xcbf03820, 0xcbf03824, + 0xcbf03828, 0xcbf0382c, 0xcbf03830, 0xcbf03834, + 0xcbf03838, 0xcbf0383c, 0xcbf03840, 0xcbf03844, + 0xcbf03848, 0xcbf0384c, 0xcbf03850, 0xcbf03854, + 0xcbf03858, 0xcbf0385c, 0xcbf03860, 0xcbf03864, + 0xcbf03868, 0xcbf0386c, 0xcbf03870, 0xcbf03874, + 0xcbf03878, 0xcbf0387c, 0xcbf03880, 0xcbf03884, + 0xcbf03888, 0xcbf0388c, 0xcbf03890, 0xcbf03894, + 0xcbf03898, 0xcbf0389c, 0xcbf038a0, 0xcbf038a4, + 0xcbf038a8, 0xcbf038ac, 0xc9d03800, 0xc9d03804, + 0xc9d03808, 0xc9d0380c, 0xc9d03810, 0xc9d03814, + 0xc9d03818, 0xc9d0381c, 0xc9d03820, 0xc9d03824, + 0xc9d03828, 0xc9d0382c, 0xc9d03830, 0xc9d03834, + 0xc9d03838, 0xc9d0383c, 0xc9d03840, 0xc9d03844, + 0xc9d03848, 0xc9d0384c, 0xc9d03850, 0xc9d03854, + 0xc9d03858, 0xc9d0385c, 0xc9d03860, 0xc9d03864, + 0xc9d03868, 0xc9d0386c, 0xc9d03870, 0xc9d03874, + 0xc9d03878, 0xc9d0387c, 0xc9d03880, 0xc9d03884, + 0xc9d03888, 0xc9d0388c, 0xc9d03890, 0xc9d03894, + 0xc9d03898, 0xc9d0389c, 0xc9d038a0, 0xc9d038a4, + 0xc9d038a8, 0xc9d038ac, 0xc9d038b0, 0xc9d038b4, + 0xc9d038b8, 0xc9d038bc, 0xc9d038c0, 0xc9d038c4, + 0xc9d038c8, 0xc9d038cc, 0xde803800, 0xde803804, + 0xde803808, 0xde80380c, 0xde803810, 0xde803814, + 0xde803818, 0xde80381c, 0xde803820, 0xde803824, + 0xde803828, 0xde80382c, 0xde803830, 0xde803834, + 0xde803838, 0xde80383c, 0xde803840, 0xde803844, + 0xde803848, 0xde80384c, 0xde803850, 0xde803854, + 0xde803858, 0xc1a03800, 0xc1a03804, 0xc1a03808, + 0xc1a0380c, 0xc1a03810, 0xc1a03814, 0xc1a03818, + 0xc1a0381c, 0xc1a03820, 0xc1a03824, 0xc1a03828, + 0xc1a0382c, 0xc1a03830, 0xc1e03800, 0xc1e03804, + 0xc1e03808, 0xc1e0380c, 0xc1e03810, 0xc1e03814, + 0xc1e03818, 0xc1e0381c, 0xc1e03820, 0xc1e03824, + 0xc1e03828, 0xc1e0382c, 0xc1e03830, 0xe9a03800, + 0xe9a03804, 0xe9a03808, 0xe9a0380c, 0xe9a03810, + 0xe9a03814, 0xe9a03818, 0xe9a0381c, 0xe9a03820, + 0xe9a03824, 0xe9a03828, 0xe9a0382c, 0xe9a03830, + 0xe9a03834, 0xe9a03838, 0xe9a0383c, 0xe9a03840, + 0xe9a03844, 0xe9a03848, 0xe9a0384c, 0xe9a03850, + 0xe9a03854, 0xe9a03858, 0xe9a0385c, 0xe9a03860, + 0xe9a03864, 0xe9a03868, 0xe9a0386c, 0xe9a03870, + 0xe9a03874, 0xe9a03878, 0xe9a0387c, 0xe9a03880, + 0xe9a03884, 0xe9a03888, 0xe9a0388c, 0xe9a03890, + 0xe9a03894, 0xe9a03898, 0xe9a0389c, 0xe9a038a0, + 0xe9a038a4, 0xe9a038a8, 0xe9a038ac, 0xe9a038b0, + 0xe9a038b4, 0xe9a038b8, 0xe9a038bc, 0xe9a038c0, + 0xe9a038c4, 0xe9a038c8, 0xe9a038cc, 0xe9a038d0, + 0xe9a038d4, 0xe9a038d8, 0xe9a038dc, 0xe9a038e0, + 0xe9a038e4, 0xe9a038e8, 0xe9a038ec, 0xe9a038f0, + 0xe9a038f4, 0xe9a038f8, 0xe9a038fc, 0xe9a03900, + 0xe9a03904, 0xe9a03908, 0xe9a0390c, 0xe9a03910, + 0xe9a03914, 0xe9a03918, 0xe9a0391c, 0xe9a03920, + 0xe9a03924, 0xe9a03928, 0xe9a0392c, 0xe9a03930, + 0xe9a03934, 0xe9a03938, 0xe9a0393c, 0xe9a03940, + 0xe9a03944, 0xe9a03948, 0xe9a0394c, 0xe9a03950, + 0xe9a03954, 0xe9a03958, 0xd2f03800, 0xd2f03804, + 0xd2f03808, 0xd2f0380c, 0xd2f03810, 0xd2f03814, + 0xd2f03818, 0xd2f0381c, 0xd2f03820, 0xd2f03824, + 0xd2f03828, 0xd2f0382c, 0xd2f03830, 0xd2f03834, + 0xd2f03838, 0xd2f0383c, 0xd2f03840, 0xd2f03844, + 0xd2f03848, 0xd2f0384c, 0xd2f03850, 0xd6f03800, + 0xd6f03804, 0xd6f03808, 0xd6f0380c, 0xd6f03810, + 0xd6f03814, 0xd6f03818, 0xd6f0381c, 0xd6f03820, + 0xd6f03824, 0xd6f03828, 0xd6f0382c, 0xd6f03830, + 0xd6f03834, 0xd6f03838, 0xd6f0383c, 0xd6f03840, + 0xd6f03844, 0xd6f03848, 0xd6f0384c, 0xd6f03850, + 0xc0983800, 0xc0983804, 0xc0983808, 0xc098380c, + 0xc0983810, 0xc0983814, 0xc0983818, 0xc098381c, + 0xc0983820, 0xc0983824, 0xc0983828, 0xc098382c, + 0xc0983830, 0xc0983834, 0xc0983838, 0xc098383c, + 0xc0983840, 0xc0583800, 0xc0583804, 0xc0583808, + 0xc058380c, 0xc0583810, 0xc0583814, 0xc0583818, + 0xc058381c, 0xc0583820, 0xc0583824, 0xc0583828, + 0xc058382c, 0xc0583830, 0xc0583834, 0xc0583838, + 0xc058383c, 0xc0583840, 0xc0583844, 0xc0583848, + 0xc058384c, 0xc0583850, 0xc0583854, 0xc0583858, + 0xc058385c, 0xc0583860, 0xc0583864, 0xc0583868, + 0xc058386c, 0xc0583870, 0xc0583874, 0xc0583878, + 0xc058387c, 0xc0583880, 0xc0583884, 0xc0583888, + 0xc058388c, 0xc0583890, 0xc0583894, 0xc0583898, + 0xc058389c, 0xc05838a0, 0xc05838a4, 0xc05838a8, + 0xc05838ac, 0xc05838b0, 0xc05838b4, 0xc05838b8, + 0xc05838bc, 0xc05838c0, 0xc05838c4, 0xc05838c8, + 0xc05838cc, 0xc05838d0, 0xc05838d4, 0xc05838d8, + 0xc05838dc, 0xc05838e0, 0xc05838e4, 0xc05838e8, + 0xc05838ec, 0xc05838f0, 0xc05838f4, 0xc05838f8, + 0xc05838fc, 0xc0583900, 0xc0583904, 0xc0583908, + 0xc058390c, 0xc0583910, 0xcb403800, 0xcb403804, + 0xcb403808, 0xcb40380c, 0xcb403810, 0xcb403814, + 0xcb403818, 0xcb40381c, 0xcb403820, 0xcb403824, + 0xcb403828, 0x1a803800, 0x1a803804, 0x1a803808, + 0x1a80380c, 0x1a803810, 0x1a803814, 0x1a803818, + 0x1a80381c, 0x1a803820, 0x1a803824, 0x1a803828, + 0x1a80382c, 0x1a803830, 0x1a803834, 0x1a803838, + 0x1a80383c, 0x1a803840, 0x1a803844, 0x1a803848, + 0x1a80384c, 0x1a803850, 0x1a803854, 0x1a803858, + 0x1a80385c, 0x1a803860, 0x1a803864, 0x1a803868, + 0x1a80386c, 0x1a803870, 0x1a803874, 0x1a803878, + 0x1a80387c, 0x1a803880, 0x1a803884, 0x1a803888, + 0x1a80388c, 0x1a803890, 0x1a803894, 0x1a803898, + 0x1a80389c, 0x1a8038a0, 0x1a8038a4, 0x1a8038a8, + 0x1a8038ac, 0x1a8038b0, 0x1a8038b4, 0x1a8038b8, + 0x1a8038bc, 0x1a8038c0, 0x1a8038c4, 0x1a8038c8, + 0x1a8038cc, 0x1a8038d0, 0x1a8038d4, 0x1a8038d8, + 0x1a8038dc, 0x1a8038e0, 0x1a8038e4, 0x1a8038e8, + 0x1a8038ec, 0x1a8038f0, 0x1a8038f4, 0x1a8038f8, + 0x1a8038fc, 0x1a803900, 0x1a803904, 0x1a803908, + 0x1a80390c, 0x1a803910, 0x1a803914, 0x1a803918, + 0x1a80391c, 0x1a803920, 0x1a803924, 0x1a803928, + 0x1a80392c, 0x1a803930, 0x1a803934, 0x1a803938, + 0x1a80393c, 0x1a803940, 0x1a803944, 0x1a803948, + 0x1a80394c, 0x1a803950, 0x1a803954, 0x1a803958, + 0x1a80395c, 0x1a803960, 0x1a803964, 0x1a803968, + 0x1a80396c, 0x1a803970, 0x1a803974, 0x1a803978, + 0x1a80397c, 0x1a803980, 0x1a803984, 0x1a803988, + 0x1a80398c, 0x1a803990, 0x1a803994, 0x18b43800, + 0x18b43804, 0x18b43808, 0x18b4380c, 0x18b43810, + 0x18b43814, 0x18b43818, 0x18b4381c, 0x18b43820, + 0x18b43824, 0x18b43828, 0x18b4382c, 0x18b43830, + 0x18b43834, 0x18b43838, 0x18b4383c, 0x18b43840, + 0x18b43844, 0x18b43848, 0x18b4384c, 0x18b43850, + 0x18b43854, 0x18b43858, 0x18b4385c, 0x18b43860, + 0x18b43864, 0x18b43868, 0x18b4386c, 0x18b43870, + 0x18b43874, 0x18b43878, 0x18b4387c, 0x18b43880, + 0x18b43884, 0x18b43888, 0x18b4388c, 0x18b43890, + 0x18b43894, 0x18b43898, 0x18b4389c, 0x18b438a0, + 0x18b438a4, 0x18b438a8, 0x18b438ac, 0x18b438b0, + 0x18b438b4, 0xc1283800, 0xc1283804, 0xc1283808, + 0xc128380c, 0xc1283810, 0xc1283814, 0xc1283818, + 0xc128381c, 0xc1283820, 0xc1283824, 0xc1283828, + 0xc128382c, 0xc1283830, 0xc1283834, 0xc1283838, + 0xc128383c, 0xc1283840, 0xc1283844, 0xc1283848, + 0xc128384c, 0xc1283850, 0xc1283854, 0xc1283858, + 0xc128385c, 0xc1283860, 0xc1283864, 0xc1283868, + 0xc128386c, 0xc1283870, 0xc1283874, 0xc1283878, + 0xc128387c, 0xc1283880, 0xc1283884, 0xc1283888, + 0xc128388c, 0xc1283890, 0xc1283894, 0xc1283898, + 0xc128389c, 0xc12838a0, 0xc12838a4, 0xc12838a8, + 0xc12838ac, 0xc12838b0, 0xc12838b4, 0xc12838b8, + 0xc12838bc, 0xc12838c0, 0xc12838c4, 0xc12838c8, + 0xc12838cc, 0xc12838d0, 0xc12838d4, 0xc12838d8, + 0xc12838dc, 0xc12838e0, 0xc12838e4, 0xc12838e8, + 0xc12838ec, 0xc12838f0, 0xc12838f4, 0xc12838f8, + 0xc6803800, 0xc6803804, 0xc6803808, 0xc680380c, + 0xc6803810, 0xc6803814, 0xc6803818, 0xc680381c, + 0xc6803820, 0xc6803824, 0xc6803828, 0xc680382c, + 0xc6803830, 0xc5803800, 0xc5803804, 0xc5803808, + 0xc580380c, 0xc5803810, 0xc5803814, 0xc5803818, + 0xc580381c, 0xc5803820, 0xc5803824, 0xc5803828, + 0xc580382c, 0xc5803830, 0xc5803834, 0xc5803838, + 0xc580383c, 0xc5803840, 0xc5803844, 0xc5803848, + 0xc580384c, 0xc5803850, 0xc5803854, 0xc5803858, + 0xc580385c, 0xc5803860, 0xc5803864, 0xc5803868, + 0xc580386c, 0xc5803870, 0xc5803874, 0xc5803878, + 0xc580387c, 0xc5803880, 0xc5803884, 0xc5803888, + 0xc580388c, 0xc5803890, 0xc5803894, 0xc5803898, + 0xc580389c, 0xc58038a0, 0xc58038a4, 0xc58038a8, + 0xc58038ac, 0xc58038b0, 0xc58038b4, 0xc58038b8, + 0xc58038bc, 0xc58038c0, 0xc58038c4, 0xc58038c8, + 0xc58038cc, 0xc58038d0, 0xc58038d4, 0xc58038d8, + 0xc58038dc, 0xc58038e0, 0xc58038e4, 0xc58038e8, + 0xc58038ec, 0xc58038f0, 0xc58038f4, 0xc58038f8, + 0xc58038fc, 0xc5803900, 0xc5803904, 0xc5803908, + 0xc580390c, 0xc5803910, 0xc5803914, 0xc5803918, + 0xc580391c, 0xc5803920, 0xc5803924, 0xc5803928, + 0xc580392c, 0xc5803930, 0xc5803934, 0xc5803938, + 0xc580393c, 0xc5803940, 0xc5803944, 0xc5803948, + 0xc580394c, 0xc5803950, 0xc5803954, 0xc5803958, + 0xc580395c, 0xc5803960, 0xc5803964, 0xc5803968, + 0xc580396c, 0xc5803970, 0xc5803974, 0xc5803978, + 0xc580397c, 0xc5803980, 0xc5803984, 0xc5803988, + 0xc580398c, 0xc5803990, 0xc5803994, 0xc5803998, + 0xc580399c, 0xc58039a0, 0xc58039a4, 0xc58039a8, + 0xc58039ac, 0xc58039b0, 0xc58039b4, 0xc58039b8, + 0xc58039bc, 0xc58039c0, 0xc58039c4, 0xc58039c8, + 0xc58039cc, 0xc58039d0, 0xc58039d4, 0xc58039d8, + 0xc58039dc, 0xc58039e0, 0xc58039e4, 0xc58039e8, + 0xc58039ec, 0xc58039f0, 0xc58039f4, 0xc58039f8, + 0xc58039fc, 0xc5803a00, 0xc5803a04, 0xc5803a08, + 0xc5803a0c, 0xc5803a10, 0xc5803a14, 0xc5803a18, + 0xc5803a1c, 0xc5803a20, 0xc5803a24, 0xc5803a28, + 0xc5803a2c, 0xc5803a30, 0xc5803a34, 0xc5803a38, + 0xc5803a3c, 0xc5803a40, 0xc5803a44, 0xc5803a48, + 0xc5803a4c, 0xc5803a50, 0xc5803a54, 0xc5803a58, + 0xc5803a5c, 0xc5803a60, 0xc5803a64, 0xc5803a68, + 0xc5803a6c, 0xc5803a70, 0xc5803a74, 0xc5803a78, + 0xc5803a7c, 0xc5803a80, 0xc5803a84, 0xc5803a88, + 0xc5803a8c, 0xc5803a90, 0xc5803a94, 0xc5803a98, + 0xc5803a9c, 0xc5803aa0, 0xc5803aa4, 0xc5803aa8, + 0xc5803aac, 0xc5803ab0, 0xc5803ab4, 0xc5803ab8, + 0xc5803abc, 0xc5803ac0, 0xc3023800, 0xc3023804, + 0xc3023808, 0xc302380c, 0xc3023810, 0xc3023814, + 0xc3023818, 0xc302381c, 0xc3023820, 0xc3023824, + 0xc3023828, 0xc302382c, 0xc3023830, 0xc3023834, + 0xc3023838, 0xc302383c, 0xc3023840, 0xc3423800, + 0xc3423804, 0xc3423808, 0xc342380c, 0xc3423810, + 0xc3423814, 0xc3423818, 0xc342381c, 0xc3423820, + 0xc3423824, 0xc3423828, 0xc342382c, 0xc3423830, + 0xc3423834, 0xc3423838, 0xc342383c, 0xc3423840, +}; + +#endif /* __GEN5_CM33_H__ */ diff --git a/configs/r8a78000_ironhide_cm33_defconfig b/configs/r8a78000_ironhide_cm33_defconfig new file mode 100644 index 00000000000..dda096634b5 --- /dev/null +++ b/configs/r8a78000_ironhide_cm33_defconfig @@ -0,0 +1,80 @@ +#include + +CONFIG_ARM=y +CONFIG_ARCH_RENESAS=y +CONFIG_RCAR_64_RSIP=y +CONFIG_RCAR_GEN5=y +CONFIG_TARGET_IRONHIDE=y +CONFIG_DEFAULT_DEVICE_TREE="r8a78000-ironhide-cm33" +CONFIG_DEFAULT_FDT_FILE="r8a78000-ironhide-cm33.dtb" + +CONFIG_TEXT_BASE=0x18410000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x3fe10000 +CONFIG_SYS_CUSTOM_LDSCRIPT=y +CONFIG_SYS_LDSCRIPT="arch/arm/mach-renesas/u-boot-rsip.lds" +CONFIG_SKIP_RELOCATE_CODE=y +CONFIG_SKIP_RELOCATE_CODE_DATA_OFFSET=0xa0000000 + +CONFIG_ARCH_CPU_INIT=y +CONFIG_BAUDRATE=1843200 +CONFIG_BOOTCOMMAND="" +CONFIG_BOUNCE_BUFFER=y +CONFIG_CMD_IMI=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_UFS=y +CONFIG_DM_DMA=y +CONFIG_DM_ETH_PHY=y +CONFIG_DM_RESET=y +CONFIG_ENV_SIZE=0x20000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_NET_LWIP=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_OF_LIVE=y +CONFIG_PHY_R8A78000_ETHERNET_PCS=y +CONFIG_PHY_R8A78000_MP_PHY=y +CONFIG_PHY_TI_DP83869=y +CONFIG_POWER_DOMAIN=y +CONFIG_RAM=y +CONFIG_REMOTEPROC_RENESAS_RSIP=y +CONFIG_RENESAS_ETHER_SWITCH=y +CONFIG_RENESAS_R8A78000_POWER_DOMAIN=y +CONFIG_SCSI=y +CONFIG_SERIAL_PROBE_ALL=y +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SIMPLE_BUS_CORRECT_RANGE=y +CONFIG_SKIP_RELOCATE=y +CONFIG_SYS_ARCH_TIMER=y +CONFIG_SYS_BARGSIZE=2048 +CONFIG_SYS_BOOT_GET_CMDLINE=y +CONFIG_SYS_CLK_FREQ=16666666 +CONFIG_SYS_LOAD_ADDR=0xb8000000 +CONFIG_SYS_MALLOC_LEN=0x80000 +CONFIG_SYS_TIMER_COUNTS_DOWN=y +CONFIG_UFS=y +CONFIG_UFS_RENESAS_GEN5=y +CONFIG_USE_BOOTARGS=y +CONFIG_USE_BOOTCOMMAND=y +CONFIG_WATCHDOG_TIMEOUT_MSECS=2000 +CONFIG_WDT=y +CONFIG_WDT_RENESAS_WWDT=y +# CONFIG_DM_THERMAL is not set +# CONFIG_EFI_LOADER is not set +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_BOOTM is not set +# CONFIG_CMD_BOOTFLOW is not set +# CONFIG_CMD_BOOTZ is not set +# CONFIG_PROT_TCP is not set +# CONFIG_OF_UPSTREAM is not set +# CONFIG_BOARD_EARLY_INIT_F is not set +# CONFIG_OF_BOARD_SETUP is not set +# CONFIG_SYS_ARCH_TIMER is not set + +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_SCIF=y +CONFIG_DEBUG_UART_BASE=0xc0714000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_DEBUG_UART_BOARD_INIT=y diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h index 4fbe8994f62..5ff2a76fc05 100644 --- a/include/configs/rcar-gen5-common.h +++ b/include/configs/rcar-gen5-common.h @@ -14,7 +14,11 @@ /* Memory */ #define DRAM_RSV_SIZE 0x20600000 +#ifdef CONFIG_RCAR_64_RSIP +#define CFG_SYS_SDRAM_BASE 0xb8400000 +#else #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) +#endif #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) -- cgit v1.3.1