From 9879842c6fdb64d95085ac66647ed77d7abfd439 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:45 +0900 Subject: ARM: uniphier: drop DCC micro support card support Historically (for compatibility with very old platforms), two different types of micro support cards have been used with the UniPhier SoC development boards. It has been painful to maintain both. Having one of them is enough. Signed-off-by: Masahiro Yamada Reviewed-by: Simon Glass --- include/configs/uniphier.h | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index d59564bafd0..7316046952e 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -62,19 +62,10 @@ /* * Support card address map */ -#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD) -# define CONFIG_SUPPORT_CARD_BASE 0x03f00000 -# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) -# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000) -# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000) -#endif - -#if defined(CONFIG_DCC_MICRO_SUPPORT_CARD) -# define CONFIG_SUPPORT_CARD_BASE 0x08000000 -# define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) -# define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00401630) -# define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00200000) -#endif +#define CONFIG_SUPPORT_CARD_BASE 0x03f00000 +#define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) +#define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000) +#define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000) #ifdef CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550 @@ -140,7 +131,7 @@ #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 /* serial console configuration */ #define CONFIG_BAUDRATE 115200 -- cgit v1.3.1 From d5ed8c5727f6985505ceb6e8640528e7e08e9670 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:47 +0900 Subject: ARM: uniphier: change the external bus address mapping In UniPhier SoCs before ProXstream2 and PH1-LD6b, two address spaces 0x00000000 - 0x0fffffff 0x40000000 - 0x4fffffff are both mapped to the external bus (also called system bus), so either was OK. In the newest two SoCs, the former (0x00000000 - 0x0fffffff) is assigned for the serial NOR interface. Going forward, use the latter for the external bus. Signed-off-by: Masahiro Yamada Reviewed-by: Simon Glass --- arch/arm/mach-uniphier/ph1-ld4/sbc_init.c | 12 ++++++------ arch/arm/mach-uniphier/ph1-pro4/sbc_init.c | 12 ++++++------ arch/arm/mach-uniphier/ph1-sld3/sbc_init.c | 12 ++++++------ arch/arm/mach-uniphier/support_card.c | 2 +- include/configs/uniphier.h | 7 ++++++- 5 files changed, 25 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c index 8e25792b501..4435a47e73c 100644 --- a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c +++ b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c @@ -30,18 +30,18 @@ void sbc_init(void) if (boot_is_swapped()) { /* * Boot Swap On: boot from external NOR/SRAM - * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. * - * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank - * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals */ writel(0x0000bc01, SBBASE0); } else { /* * Boot Swap Off: boot from mask ROM - * 0x00000000-0x01ffffff: mask ROM - * 0x02000000-0x03efffff: memory bank (31MB) - * 0x03f00000-0x03ffffff: peripherals (1MB) + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) */ writel(0x0000be01, SBBASE0); /* dummy */ writel(0x0200be01, SBBASE1); diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c index 533739c364d..685f9c736c9 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c +++ b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c @@ -23,18 +23,18 @@ void sbc_init(void) if (boot_is_swapped()) { /* * Boot Swap On: boot from external NOR/SRAM - * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. * - * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank - * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals */ writel(0x0000bc01, SBBASE0); } else { /* * Boot Swap Off: boot from mask ROM - * 0x00000000-0x01ffffff: mask ROM - * 0x02000000-0x03efffff: memory bank (31MB) - * 0x03f00000-0x03ffffff: peripherals (1MB) + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) */ writel(0x0000be01, SBBASE0); /* dummy */ writel(0x0200be01, SBBASE1); diff --git a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c index d66f89ea51f..bafab4b0e66 100644 --- a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c +++ b/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c @@ -24,18 +24,18 @@ void sbc_init(void) if (boot_is_swapped()) { /* * Boot Swap On: boot from external NOR/SRAM - * 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff. + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. * - * 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank - * 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals */ writel(0x0000bc01, SBBASE0); } else { /* * Boot Swap Off: boot from mask ROM - * 0x00000000-0x01ffffff: mask ROM - * 0x02000000-0x03efffff: memory bank (31MB) - * 0x03f00000-0x03ffffff: peripherals (1MB) + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) */ writel(0x0000be01, SBBASE0); /* dummy */ writel(0x0200be01, SBBASE1); diff --git a/arch/arm/mach-uniphier/support_card.c b/arch/arm/mach-uniphier/support_card.c index 4ca6ffea2dc..ef4576de432 100644 --- a/arch/arm/mach-uniphier/support_card.c +++ b/arch/arm/mach-uniphier/support_card.c @@ -103,7 +103,7 @@ static int mem_is_flash(const struct memory_bank *mem) /* {address, size} */ static const struct memory_bank memory_banks[] = { - {0x02000000, 0x01f00000}, + {0x42000000, 0x01f00000}, }; static const struct memory_bank diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 7316046952e..45b39c075e5 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -62,7 +62,7 @@ /* * Support card address map */ -#define CONFIG_SUPPORT_CARD_BASE 0x03f00000 +#define CONFIG_SUPPORT_CARD_BASE 0x43f00000 #define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) #define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000) #define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000) @@ -240,6 +240,7 @@ "fit_addr_r=0x84100000\0" \ "fit_size=0x00f00000\0" \ "norboot=run add_default_bootargs &&" \ + "setexpr fit_addr $nor_base + $fit_addr &&" \ "bootm $fit_addr\0" \ "nandboot=run add_default_bootargs &&" \ "nand read $fit_addr_r $fit_addr $fit_size &&" \ @@ -262,6 +263,9 @@ "ramdisk_size=0x00600000\0" \ "ramdisk_file=rootfs.cpio.uboot\0" \ "norboot=run add_default_bootargs &&" \ + "setexpr kernel_addr $nor_base + $kernel_addr &&" \ + "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \ + "setexpr fdt_addr $nor_base + $fdt_addr &&" \ "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ "nandboot=run add_default_bootargs &&" \ "nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ @@ -278,6 +282,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "verify=n\0" \ + "norbase=0x42000000\0" \ "nandupdate=nand erase 0 0x00100000 &&" \ "tftpboot u-boot-spl-dtb.bin &&" \ "nand write $loadaddr 0 0x00010000 &&" \ -- cgit v1.3.1 From cf88affab6c46bc728d47fe2590c465734d78efb Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 11 Sep 2015 20:17:49 +0900 Subject: ARM: uniphier: parse device tree to determine DRAM base and size Device tree specifies the available memory ranges in its "/memory" node. Use it to simplify the CONFIG defines. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/board_common.c | 12 --------- arch/arm/mach-uniphier/dram_init.c | 51 ++++++++++++++++++++++++++++++++--- include/configs/uniphier.h | 11 +------- 3 files changed, 48 insertions(+), 26 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-uniphier/board_common.c b/arch/arm/mach-uniphier/board_common.c index 5f2d5f6f5b9..967fa6c0865 100644 --- a/arch/arm/mach-uniphier/board_common.c +++ b/arch/arm/mach-uniphier/board_common.c @@ -18,15 +18,3 @@ int board_init(void) return 0; } - -#if CONFIG_NR_DRAM_BANKS >= 2 -void dram_init_banksize(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - gd->bd->bi_dram[0].start = CONFIG_SDRAM0_BASE; - gd->bd->bi_dram[0].size = CONFIG_SDRAM0_SIZE; - gd->bd->bi_dram[1].start = CONFIG_SDRAM1_BASE; - gd->bd->bi_dram[1].size = CONFIG_SDRAM1_SIZE; -} -#endif diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c index 4b8c938b5ea..32cc448aeb5 100644 --- a/arch/arm/mach-uniphier/dram_init.c +++ b/arch/arm/mach-uniphier/dram_init.c @@ -1,16 +1,59 @@ /* - * Copyright (C) 2012-2015 Panasonic Corporation - * Author: Masahiro Yamada + * Copyright (C) 2012-2015 Masahiro Yamada * * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const void *get_memory_reg_prop(const void *fdt, int *lenp) +{ + int offset; + + offset = fdt_path_offset(fdt, "/memory"); + if (offset < 0) + return NULL; + + return fdt_getprop(fdt, offset, "reg", lenp); +} int dram_init(void) { - DECLARE_GLOBAL_DATA_PTR; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + const fdt32_t *val; + int len; + + val = get_memory_reg_prop(gd->fdt_blob, &len); + if (len < sizeof(*val)) + return -EINVAL; + + gd->ram_size = fdt32_to_cpu(*(val + 1)); + + debug("DRAM size = %08lx\n", gd->ram_size); return 0; } + +void dram_init_banksize(void) +{ + const fdt32_t *val; + int len, i; + + val = get_memory_reg_prop(gd->fdt_blob, &len); + if (len < 0) + return; + + len /= sizeof(*val); + len /= 2; + + for (i = 0; i < len; i++) { + gd->bd->bi_dram[i].start = fdt32_to_cpu(*val++); + gd->bd->bi_dram[i].size = fdt32_to_cpu(*val++); + + debug("DRAM bank %d: start = %08lx, size = %08lx\n", + i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); + } +} diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 45b39c075e5..a15838b1725 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -295,17 +295,8 @@ /* Open Firmware flat tree */ #define CONFIG_OF_LIBFDT -/* Memory Size & Mapping */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SDRAM0_BASE - -#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE >= CONFIG_SDRAM1_BASE -/* Thre is no memory hole */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE + CONFIG_SDRAM1_SIZE) -#else +#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_NR_DRAM_BANKS 2 -#define CONFIG_SYS_SDRAM_SIZE (CONFIG_SDRAM0_SIZE) -#endif #if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \ defined(CONFIG_MACH_PH1_SLD8) -- cgit v1.3.1 From d7728aa408b478f83ec7f39ad80abf1046d71e39 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 22 Sep 2015 00:27:32 +0900 Subject: ARM: uniphier: move CONFIG_SUPPORT_CARD_* macros to local file It is no longer necessary to define CONFIG_SUPPORT_CARD_* globally. Move them to a C file as local macros. Also, rename the C file. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/Makefile | 2 +- arch/arm/mach-uniphier/micro-support-card.c | 231 ++++++++++++++++++++++++++++ arch/arm/mach-uniphier/support_card.c | 228 --------------------------- include/configs/uniphier.h | 11 +- 4 files changed, 234 insertions(+), 238 deletions(-) create mode 100644 arch/arm/mach-uniphier/micro-support-card.c delete mode 100644 arch/arm/mach-uniphier/support_card.c (limited to 'include') diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 5f175575e86..df6a569b9a4 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -29,7 +29,7 @@ endif obj-y += timer.o -obj-$(CONFIG_MICRO_SUPPORT_CARD) += support_card.o +obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o obj-$(CONFIG_MACH_PH1_SLD3) += ph1-sld3/ obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/ diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c new file mode 100644 index 00000000000..4c34748c25c --- /dev/null +++ b/arch/arm/mach-uniphier/micro-support-card.c @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2012-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#define MICRO_SUPPORT_CARD_BASE 0x43f00000 +#define SMC911X_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x00000) +#define LED_BASE ((MICRO_SUPPORT_CARD_BASE) + 0x90000) +#define NS16550A_BASE ((MICRO_SUPPORT_CARD_BASE) + 0xb0000) +#define MICRO_SUPPORT_CARD_RESET ((MICRO_SUPPORT_CARD_BASE) + 0xd0034) +#define MICRO_SUPPORT_CARD_REVISION ((MICRO_SUPPORT_CARD_BASE) + 0xd00E0) + +/* + * 0: reset deassert, 1: reset + * + * bit[0]: LAN, I2C, LED + * bit[1]: UART + */ +void support_card_reset_deassert(void) +{ + writel(0, MICRO_SUPPORT_CARD_RESET); +} + +void support_card_reset(void) +{ + writel(3, MICRO_SUPPORT_CARD_RESET); +} + +static int support_card_show_revision(void) +{ + u32 revision; + + revision = readl(MICRO_SUPPORT_CARD_REVISION); + printf("(CPLD version %d.%d)\n", revision >> 4, revision & 0xf); + return 0; +} + +int check_support_card(void) +{ + printf("SC: Micro Support Card "); + return support_card_show_revision(); +} + +void support_card_init(void) +{ + /* + * After power on, we need to keep the LAN controller in reset state + * for a while. (200 usec) + * Fortunately, enough wait time is already inserted in pll_init() + * function. So we do not have to wait here. + */ + support_card_reset_deassert(); +} + +#if defined(CONFIG_SMC911X) +#include + +int board_eth_init(bd_t *bis) +{ + return smc911x_initialize(0, SMC911X_BASE); +} +#endif + +#if !defined(CONFIG_SYS_NO_FLASH) + +#include +#include + +struct memory_bank { + phys_addr_t base; + unsigned long size; +}; + +static int mem_is_flash(const struct memory_bank *mem) +{ + const int loop = 128; + u32 *scratch_addr; + u32 saved_value; + int ret = 1; + int i; + + /* just in case, use the tail of the memory bank */ + scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop, + sizeof(u32) * loop, MAP_NOCACHE); + + for (i = 0; i < loop; i++, scratch_addr++) { + saved_value = readl(scratch_addr); + writel(~saved_value, scratch_addr); + if (readl(scratch_addr) != saved_value) { + /* We assume no memory or SRAM here. */ + writel(saved_value, scratch_addr); + ret = 0; + break; + } + } + + unmap_physmem(scratch_addr, MAP_NOCACHE); + + return ret; +} + +/* {address, size} */ +static const struct memory_bank memory_banks[] = { + {0x42000000, 0x01f00000}, +}; + +static const struct memory_bank +*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT]; + +phys_addr_t cfi_flash_bank_addr(int i) +{ + return flash_banks_list[i]->base; +} + +unsigned long cfi_flash_bank_size(int i) +{ + return flash_banks_list[i]->size; +} + +static void detect_num_flash_banks(void) +{ + const struct memory_bank *memory_bank, *end; + + cfi_flash_num_flash_banks = 0; + + memory_bank = memory_banks; + end = memory_bank + ARRAY_SIZE(memory_banks); + + for (; memory_bank < end; memory_bank++) { + if (cfi_flash_num_flash_banks >= + CONFIG_SYS_MAX_FLASH_BANKS_DETECT) + break; + + if (mem_is_flash(memory_bank)) { + flash_banks_list[cfi_flash_num_flash_banks] = + memory_bank; + + debug("flash bank found: base = 0x%lx, size = 0x%lx\n", + memory_bank->base, memory_bank->size); + cfi_flash_num_flash_banks++; + } + } + + debug("number of flash banks: %d\n", cfi_flash_num_flash_banks); +} +#else /* CONFIG_SYS_NO_FLASH */ +void detect_num_flash_banks(void) +{ +}; +#endif /* CONFIG_SYS_NO_FLASH */ + +void support_card_late_init(void) +{ + detect_num_flash_banks(); +} + +static const u8 ledval_num[] = { + 0x7e, /* 0 */ + 0x0c, /* 1 */ + 0xb6, /* 2 */ + 0x9e, /* 3 */ + 0xcc, /* 4 */ + 0xda, /* 5 */ + 0xfa, /* 6 */ + 0x4e, /* 7 */ + 0xfe, /* 8 */ + 0xde, /* 9 */ +}; + +static const u8 ledval_alpha[] = { + 0xee, /* A */ + 0xf8, /* B */ + 0x72, /* C */ + 0xbc, /* D */ + 0xf2, /* E */ + 0xe2, /* F */ + 0x7a, /* G */ + 0xe8, /* H */ + 0x08, /* I */ + 0x3c, /* J */ + 0xea, /* K */ + 0x70, /* L */ + 0x6e, /* M */ + 0xa8, /* N */ + 0xb8, /* O */ + 0xe6, /* P */ + 0xce, /* Q */ + 0xa0, /* R */ + 0xc8, /* S */ + 0x8c, /* T */ + 0x7c, /* U */ + 0x54, /* V */ + 0xfc, /* W */ + 0xec, /* X */ + 0xdc, /* Y */ + 0xa4, /* Z */ +}; + +static u8 char2ledval(char c) +{ + if (isdigit(c)) + return ledval_num[c - '0']; + else if (isalpha(c)) + return ledval_alpha[toupper(c) - 'A']; + + return 0; +} + +void led_puts(const char *s) +{ + int i; + u32 val = 0; + + if (!s) + return; + + for (i = 0; i < 4; i++) { + val <<= 8; + val |= char2ledval(*s); + if (*s != '\0') + s++; + } + + writel(~val, LED_BASE); +} diff --git a/arch/arm/mach-uniphier/support_card.c b/arch/arm/mach-uniphier/support_card.c deleted file mode 100644 index f8333060301..00000000000 --- a/arch/arm/mach-uniphier/support_card.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright (C) 2012-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define MICRO_SUPPORT_CARD_RESET \ - ((CONFIG_SUPPORT_CARD_BASE) + 0x000D0034) -#define MICRO_SUPPORT_CARD_REVISION \ - ((CONFIG_SUPPORT_CARD_BASE) + 0x000D00E0) -/* - * 0: reset deassert, 1: reset - * - * bit[0]: LAN, I2C, LED - * bit[1]: UART - */ -void support_card_reset_deassert(void) -{ - writel(0, MICRO_SUPPORT_CARD_RESET); -} - -void support_card_reset(void) -{ - writel(3, MICRO_SUPPORT_CARD_RESET); -} - -static int support_card_show_revision(void) -{ - u32 revision; - - revision = readl(MICRO_SUPPORT_CARD_REVISION); - printf("(CPLD version %d.%d)\n", revision >> 4, revision & 0xf); - return 0; -} - -int check_support_card(void) -{ - printf("SC: Micro Support Card "); - return support_card_show_revision(); -} - -void support_card_init(void) -{ - /* - * After power on, we need to keep the LAN controller in reset state - * for a while. (200 usec) - * Fortunately, enough wait time is already inserted in pll_init() - * function. So we do not have to wait here. - */ - support_card_reset_deassert(); -} - -#if defined(CONFIG_SMC911X) -#include - -int board_eth_init(bd_t *bis) -{ - return smc911x_initialize(0, CONFIG_SMC911X_BASE); -} -#endif - -#if !defined(CONFIG_SYS_NO_FLASH) - -#include -#include - -struct memory_bank { - phys_addr_t base; - unsigned long size; -}; - -static int mem_is_flash(const struct memory_bank *mem) -{ - const int loop = 128; - u32 *scratch_addr; - u32 saved_value; - int ret = 1; - int i; - - /* just in case, use the tail of the memory bank */ - scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop, - sizeof(u32) * loop, MAP_NOCACHE); - - for (i = 0; i < loop; i++, scratch_addr++) { - saved_value = readl(scratch_addr); - writel(~saved_value, scratch_addr); - if (readl(scratch_addr) != saved_value) { - /* We assume no memory or SRAM here. */ - writel(saved_value, scratch_addr); - ret = 0; - break; - } - } - - unmap_physmem(scratch_addr, MAP_NOCACHE); - - return ret; -} - -/* {address, size} */ -static const struct memory_bank memory_banks[] = { - {0x42000000, 0x01f00000}, -}; - -static const struct memory_bank -*flash_banks_list[CONFIG_SYS_MAX_FLASH_BANKS_DETECT]; - -phys_addr_t cfi_flash_bank_addr(int i) -{ - return flash_banks_list[i]->base; -} - -unsigned long cfi_flash_bank_size(int i) -{ - return flash_banks_list[i]->size; -} - -static void detect_num_flash_banks(void) -{ - const struct memory_bank *memory_bank, *end; - - cfi_flash_num_flash_banks = 0; - - memory_bank = memory_banks; - end = memory_bank + ARRAY_SIZE(memory_banks); - - for (; memory_bank < end; memory_bank++) { - if (cfi_flash_num_flash_banks >= - CONFIG_SYS_MAX_FLASH_BANKS_DETECT) - break; - - if (mem_is_flash(memory_bank)) { - flash_banks_list[cfi_flash_num_flash_banks] = - memory_bank; - - debug("flash bank found: base = 0x%lx, size = 0x%lx\n", - memory_bank->base, memory_bank->size); - cfi_flash_num_flash_banks++; - } - } - - debug("number of flash banks: %d\n", cfi_flash_num_flash_banks); -} -#else /* CONFIG_SYS_NO_FLASH */ -void detect_num_flash_banks(void) -{ -}; -#endif /* CONFIG_SYS_NO_FLASH */ - -void support_card_late_init(void) -{ - detect_num_flash_banks(); -} - -static const u8 ledval_num[] = { - 0x7e, /* 0 */ - 0x0c, /* 1 */ - 0xb6, /* 2 */ - 0x9e, /* 3 */ - 0xcc, /* 4 */ - 0xda, /* 5 */ - 0xfa, /* 6 */ - 0x4e, /* 7 */ - 0xfe, /* 8 */ - 0xde, /* 9 */ -}; - -static const u8 ledval_alpha[] = { - 0xee, /* A */ - 0xf8, /* B */ - 0x72, /* C */ - 0xbc, /* D */ - 0xf2, /* E */ - 0xe2, /* F */ - 0x7a, /* G */ - 0xe8, /* H */ - 0x08, /* I */ - 0x3c, /* J */ - 0xea, /* K */ - 0x70, /* L */ - 0x6e, /* M */ - 0xa8, /* N */ - 0xb8, /* O */ - 0xe6, /* P */ - 0xce, /* Q */ - 0xa0, /* R */ - 0xc8, /* S */ - 0x8c, /* T */ - 0x7c, /* U */ - 0x54, /* V */ - 0xfc, /* W */ - 0xec, /* X */ - 0xdc, /* Y */ - 0xa4, /* Z */ -}; - -static u8 char2ledval(char c) -{ - if (isdigit(c)) - return ledval_num[c - '0']; - else if (isalpha(c)) - return ledval_alpha[toupper(c) - 'A']; - - return 0; -} - -void led_puts(const char *s) -{ - int i; - u32 val = 0; - - if (!s) - return; - - for (i = 0; i < 4; i++) { - val <<= 8; - val |= char2ledval(*s); - if (*s != '\0') - s++; - } - - writel(~val, CONFIG_SUPPORT_CARD_LED_BASE); -} diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index a15838b1725..64059612f32 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -59,14 +59,6 @@ #define CONFIG_I2C_EEPROM #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -/* - * Support card address map - */ -#define CONFIG_SUPPORT_CARD_BASE 0x43f00000 -#define CONFIG_SUPPORT_CARD_ETHER_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00000000) -#define CONFIG_SUPPORT_CARD_LED_BASE (CONFIG_SUPPORT_CARD_BASE + 0x00090000) -#define CONFIG_SUPPORT_CARD_UART_BASE (CONFIG_SUPPORT_CARD_BASE + 0x000b0000) - #ifdef CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_COM1 CONFIG_SUPPORT_CARD_UART_BASE @@ -81,7 +73,8 @@ #define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE +/* dummy: referenced by examples/standalone/smc911x_eeprom.c */ +#define CONFIG_SMC911X_BASE 0 #define CONFIG_SMC911X_32_BIT /*----------------------------------------------------------------------- -- cgit v1.3.1 From 8497ccc4c23beae38130489d85c97ae38058f20b Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 22 Sep 2015 00:27:34 +0900 Subject: ARM: uniphier: rename CONFIG_MACH_* to CONFIG_ARCH_UNIPHIER_* I want these prefixed with CONFIG_ARCH_UNIPHIER_ to clarify they belong to UniPhier SoC family. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/Kconfig | 14 +++++++------- arch/arm/mach-uniphier/Makefile | 8 ++++---- arch/arm/mach-uniphier/include/mach/ddrphy-regs.h | 3 ++- arch/arm/mach-uniphier/include/mach/sc-regs.h | 2 +- arch/arm/mach-uniphier/ph1-pro4/pll_init.c | 2 -- configs/ph1_ld4_defconfig | 2 +- configs/ph1_sld3_defconfig | 2 +- configs/ph1_sld8_defconfig | 2 +- drivers/pinctrl/uniphier/Kconfig | 12 ++++++------ include/configs/uniphier.h | 17 +++++++++-------- 10 files changed, 32 insertions(+), 32 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 28d574fbb80..d7a19c6772c 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -8,20 +8,20 @@ config UNIPHIER_SMP choice prompt "UniPhier SoC select" - default MACH_PH1_PRO4 + default ARCH_UNIPHIER_PH1_PRO4 -config MACH_PH1_SLD3 +config ARCH_UNIPHIER_PH1_SLD3 bool "PH1-sLD3" select UNIPHIER_SMP -config MACH_PH1_LD4 +config ARCH_UNIPHIER_PH1_LD4 bool "PH1-LD4" -config MACH_PH1_PRO4 +config ARCH_UNIPHIER_PH1_PRO4 bool "PH1-Pro4" select UNIPHIER_SMP -config MACH_PH1_SLD8 +config ARCH_UNIPHIER_PH1_SLD8 bool "PH1-sLD8" endchoice @@ -53,11 +53,11 @@ choice config DDR_FREQ_1600 bool "DDR3 1600" - depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_PRO4 + depends on ARCH_UNIPHIER_PH1_SLD3 || ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_PRO4 config DDR_FREQ_1333 bool "DDR3 1333" - depends on MACH_PH1_SLD3 || MACH_PH1_LD4 || MACH_PH1_SLD8 + depends on ARCH_UNIPHIER_PH1_SLD3 || ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_SLD8 endchoice diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index df6a569b9a4..d30cc27009b 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -31,7 +31,7 @@ obj-y += timer.o obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o -obj-$(CONFIG_MACH_PH1_SLD3) += ph1-sld3/ -obj-$(CONFIG_MACH_PH1_LD4) += ph1-ld4/ -obj-$(CONFIG_MACH_PH1_PRO4) += ph1-pro4/ -obj-$(CONFIG_MACH_PH1_SLD8) += ph1-sld8/ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += ph1-sld3/ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ph1-ld4/ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ph1-pro4/ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ph1-sld8/ diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h index fce0c01246b..01f5c52c9c4 100644 --- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h @@ -156,7 +156,8 @@ struct ddrphy { /* SoC-specific parameters */ #define NR_DATX8_PER_DDRPHY 2 -#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) #define NR_DDRPHY_PER_CH 1 #else #define NR_DDRPHY_PER_CH 2 diff --git a/arch/arm/mach-uniphier/include/mach/sc-regs.h b/arch/arm/mach-uniphier/include/mach/sc-regs.h index df502940779..9d697b16ee6 100644 --- a/arch/arm/mach-uniphier/include/mach/sc-regs.h +++ b/arch/arm/mach-uniphier/include/mach/sc-regs.h @@ -9,7 +9,7 @@ #ifndef ARCH_SC_REGS_H #define ARCH_SC_REGS_H -#if defined(CONFIG_MACH_PH1_SLD3) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) #define SC_BASE_ADDR 0xf1840000 #else #define SC_BASE_ADDR 0x61840000 diff --git a/arch/arm/mach-uniphier/ph1-pro4/pll_init.c b/arch/arm/mach-uniphier/ph1-pro4/pll_init.c index d693368816c..8ae8ed65b87 100644 --- a/arch/arm/mach-uniphier/ph1-pro4/pll_init.c +++ b/arch/arm/mach-uniphier/ph1-pro4/pll_init.c @@ -54,12 +54,10 @@ static void vpll_init(void) tmp = readl(SG_PINMON0); clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; -#if defined(CONFIG_MACH_PH1_PRO4) /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */ if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) return; -#endif /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ tmp = readl(SC_VPLL27ACTRL); diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index 899a7238f38..e1665c090c8 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_MACH_PH1_LD4=y +CONFIG_ARCH_UNIPHIER_PH1_LD4=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld4-ref" diff --git a/configs/ph1_sld3_defconfig b/configs/ph1_sld3_defconfig index 79ce0e28cde..4b871d0ebd5 100644 --- a/configs/ph1_sld3_defconfig +++ b/configs/ph1_sld3_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y -CONFIG_MACH_PH1_SLD3=y +CONFIG_ARCH_UNIPHIER_PH1_SLD3=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld3-ref" diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index 216d49be124..00917fbc515 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 -CONFIG_MACH_PH1_SLD8=y +CONFIG_ARCH_UNIPHIER_PH1_SLD8=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-sld8-ref" diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig index 757edce178f..2ff616e9463 100644 --- a/drivers/pinctrl/uniphier/Kconfig +++ b/drivers/pinctrl/uniphier/Kconfig @@ -5,37 +5,37 @@ config PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_LD4 bool "UniPhier PH1-LD4 SoC pinctrl driver" - depends on MACH_PH1_LD4 + depends on ARCH_UNIPHIER_PH1_LD4 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_PRO4 bool "UniPhier PH1-Pro4 SoC pinctrl driver" - depends on MACH_PH1_PRO4 + depends on ARCH_UNIPHIER_PH1_PRO4 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_SLD8 bool "UniPhier PH1-sLD8 SoC pinctrl driver" - depends on MACH_PH1_SLD8 + depends on ARCH_UNIPHIER_PH1_SLD8 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_PRO5 bool "UniPhier PH1-Pro5 SoC pinctrl driver" - depends on MACH_PH1_PRO5 + depends on ARCH_UNIPHIER_PH1_PRO5 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PROXSTREAM2 bool "UniPhier ProXstream2 SoC pinctrl driver" - depends on MACH_PROXSTREAM2 + depends on ARCH_UNIPHIER_PROXSTREAM2 default y select PINCTRL_UNIPHIER_CORE config PINCTRL_UNIPHIER_PH1_LD6B bool "UniPhier PH1-LD6b SoC pinctrl driver" - depends on MACH_PH1_LD6B + depends on ARCH_UNIPHIER_PH1_LD6B default y select PINCTRL_UNIPHIER_CORE diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 64059612f32..bd0769e6d92 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_UNIPHIER_COMMON_H__ #define __CONFIG_UNIPHIER_COMMON_H__ -#if defined(CONFIG_MACH_PH1_SLD3) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) #define CONFIG_DDR_NUM_CH0 2 #define CONFIG_DDR_NUM_CH1 1 #define CONFIG_DDR_NUM_CH2 1 @@ -23,7 +23,7 @@ #define CONFIG_SDRAM2_SIZE 0x10000000 #endif -#if defined(CONFIG_MACH_PH1_LD4) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) #define CONFIG_DDR_NUM_CH0 1 #define CONFIG_DDR_NUM_CH1 1 @@ -34,7 +34,7 @@ #define CONFIG_SDRAM1_SIZE 0x10000000 #endif -#if defined(CONFIG_MACH_PH1_PRO4) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) #define CONFIG_DDR_NUM_CH0 2 #define CONFIG_DDR_NUM_CH1 2 @@ -45,7 +45,7 @@ #define CONFIG_SDRAM1_SIZE 0x20000000 #endif -#if defined(CONFIG_MACH_PH1_SLD8) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) #define CONFIG_DDR_NUM_CH0 1 #define CONFIG_DDR_NUM_CH1 1 @@ -175,7 +175,7 @@ #define CONFIG_NAND_DENALI_ECC_SIZE 1024 -#ifdef CONFIG_MACH_PH1_SLD3 +#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3 #define CONFIG_SYS_NAND_REGS_BASE 0xf8100000 #define CONFIG_SYS_NAND_DATA_BASE 0xf8000000 #else @@ -291,11 +291,12 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_NR_DRAM_BANKS 2 -#if defined(CONFIG_MACH_PH1_SLD3) || defined(CONFIG_MACH_PH1_LD4) || \ - defined(CONFIG_MACH_PH1_SLD8) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) #define CONFIG_SPL_TEXT_BASE 0x00040000 #endif -#if defined(CONFIG_MACH_PH1_PRO4) +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif -- cgit v1.3.1 From 5451b777de392043c03626f6cbbc3940c49c3417 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 22 Sep 2015 00:27:38 +0900 Subject: ARM: uniphier: remove kernel parameter settings from environment Currently, console=ttyS0 is hard-coded in CONFIG_EXTRA_ENV_SETTINGS and it replaces the bootargs in the chosen node of the device tree passed to the kernel. This is not preferable because I am going to add some boards whose console is not ttyS0. Drop bootargs settings from U-Boot's environment and use the one in device tree by default. Signed-off-by: Masahiro Yamada --- include/configs/uniphier.h | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index bd0769e6d92..f44c58bf9d0 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -224,22 +224,17 @@ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ "tftpboot; bootm;" -#define CONFIG_BOOTARGS " earlyprintk loglevel=8" - #ifdef CONFIG_FIT #define CONFIG_BOOTFILE "fitImage" #define LINUXBOOT_ENV_SETTINGS \ "fit_addr=0x00100000\0" \ "fit_addr_r=0x84100000\0" \ "fit_size=0x00f00000\0" \ - "norboot=run add_default_bootargs &&" \ - "setexpr fit_addr $nor_base + $fit_addr &&" \ + "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ "bootm $fit_addr\0" \ - "nandboot=run add_default_bootargs &&" \ - "nand read $fit_addr_r $fit_addr $fit_size &&" \ + "nandboot=nand read $fit_addr_r $fit_addr $fit_size &&" \ "bootm $fit_addr_r\0" \ - "tftpboot=run add_default_bootargs &&" \ - "tftpboot $fit_addr_r $bootfile &&" \ + "tftpboot=tftpboot $fit_addr_r $bootfile &&" \ "bootm $fit_addr_r\0" #else #define CONFIG_BOOTFILE "uImage" @@ -255,18 +250,15 @@ "ramdisk_addr_r=0x84a00000\0" \ "ramdisk_size=0x00600000\0" \ "ramdisk_file=rootfs.cpio.uboot\0" \ - "norboot=run add_default_bootargs &&" \ - "setexpr kernel_addr $nor_base + $kernel_addr &&" \ + "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ "setexpr ramdisk_addr $nor_base + $ramdisk_addr &&" \ "setexpr fdt_addr $nor_base + $fdt_addr &&" \ "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ - "nandboot=run add_default_bootargs &&" \ - "nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ + "nandboot=nand read $kernel_addr_r $kernel_addr $kernel_size &&" \ "nand read $ramdisk_addr_r $ramdisk_addr $ramdisk_size &&" \ "nand read $fdt_addr_r $fdt_addr $fdt_size &&" \ "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ - "tftpboot=run add_default_bootargs &&" \ - "tftpboot $kernel_addr_r $bootfile &&" \ + "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ "tftpboot $fdt_addr_r $fdt_file &&" \ "bootm $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" @@ -281,8 +273,6 @@ "nand write $loadaddr 0 0x00010000 &&" \ "tftpboot u-boot-dtb.img &&" \ "nand write $loadaddr 0x00010000 0x000f0000\0" \ - "add_default_bootargs=setenv bootargs $bootargs" \ - " console=ttyS0,$baudrate\0" \ LINUXBOOT_ENV_SETTINGS /* Open Firmware flat tree */ -- cgit v1.3.1 From 323d1f9d5bebfe55e97e23c8094055685665afef Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 22 Sep 2015 00:27:39 +0900 Subject: ARM: uniphier: allow to enable multiple SoCs Before this commit, the Kconfig menu in mach-uniphier only allowed us to choose one SoC to be compiled. Each SoC has its own defconfig file for the build-test coverage. Consequently, some defconfig files are duplicated with only the difference in CONFIG_DEFAULT_DEVICE_TREE and CONFIG_{SOC_NAME}=y. Now, most of board-specific parameters have been moved to device trees, so it makes sense to include init code of multiple SoCs into a single image as long as the SoCs have similar architecture. In fact, some SoCs of UniPhier family are very similar: - PH1-LD4 and PH1-sLD8 - PH1-LD6b and ProXstream2 (will be added in the upcoming commit) This commit will be helpful to merge some defconfig files for better maintainability. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/Kconfig | 45 ++--- arch/arm/mach-uniphier/Makefile | 16 +- arch/arm/mach-uniphier/bcu/Makefile | 3 + arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c | 34 ++++ arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c | 38 ++++ arch/arm/mach-uniphier/board_early_init_f.c | 42 ++++- arch/arm/mach-uniphier/boards.c | 93 ++++++++++ arch/arm/mach-uniphier/boot-mode/Makefile | 6 + .../mach-uniphier/boot-mode/boot-mode-ph1-ld4.c | 74 ++++++++ .../mach-uniphier/boot-mode/boot-mode-ph1-sld3.c | 106 +++++++++++ arch/arm/mach-uniphier/boot-mode/boot-mode.c | 35 ++++ arch/arm/mach-uniphier/clk/Makefile | 4 + arch/arm/mach-uniphier/clk/clk-ph1-ld4.c | 42 +++++ arch/arm/mach-uniphier/clk/clk-ph1-pro4.c | 57 ++++++ arch/arm/mach-uniphier/cmd_pinmon.c | 31 ++-- arch/arm/mach-uniphier/ddrphy/Makefile | 3 + arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c | 72 ++++++++ arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c | 72 ++++++++ arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c | 77 ++++++++ arch/arm/mach-uniphier/ddrphy/ddrphy-training.c | 139 ++++++++++++++ arch/arm/mach-uniphier/ddrphy_training.c | 139 -------------- arch/arm/mach-uniphier/early-clk/Makefile | 4 + .../mach-uniphier/early-clk/early-clk-ph1-ld4.c | 33 ++++ arch/arm/mach-uniphier/early-pinctrl/Makefile | 1 + .../early-pinctrl/early-pinctrl-ph1-sld3.c | 26 +++ arch/arm/mach-uniphier/include/mach/boot-device.h | 11 +- arch/arm/mach-uniphier/include/mach/ddrphy-regs.h | 4 +- arch/arm/mach-uniphier/include/mach/init.h | 83 +++++++++ arch/arm/mach-uniphier/include/mach/sg-regs.h | 6 + arch/arm/mach-uniphier/include/mach/soc_info.h | 63 +++++++ arch/arm/mach-uniphier/init/Makefile | 6 + arch/arm/mach-uniphier/init/init-ph1-ld4.c | 60 ++++++ arch/arm/mach-uniphier/init/init-ph1-pro4.c | 58 ++++++ arch/arm/mach-uniphier/init/init-ph1-sld3.c | 53 ++++++ arch/arm/mach-uniphier/init/init-ph1-sld8.c | 60 ++++++ arch/arm/mach-uniphier/init/init.c | 46 +++++ arch/arm/mach-uniphier/memconf.c | 103 ----------- arch/arm/mach-uniphier/memconf/Makefile | 2 + arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c | 59 ++++++ arch/arm/mach-uniphier/memconf/memconf.c | 104 +++++++++++ arch/arm/mach-uniphier/ph1-ld4/Makefile | 13 -- arch/arm/mach-uniphier/ph1-ld4/bcu_init.c | 32 ---- arch/arm/mach-uniphier/ph1-ld4/boot-mode.c | 1 - arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c | 41 ----- arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c | 70 ------- arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c | 1 - arch/arm/mach-uniphier/ph1-ld4/pinctrl.c | 48 ----- arch/arm/mach-uniphier/ph1-ld4/pll_init.c | 189 ------------------- arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c | 1 - arch/arm/mach-uniphier/ph1-ld4/sbc_init.c | 49 ----- arch/arm/mach-uniphier/ph1-ld4/umc_init.c | 171 ----------------- arch/arm/mach-uniphier/ph1-pro4/Makefile | 13 -- arch/arm/mach-uniphier/ph1-pro4/boot-mode.c | 65 ------- arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c | 56 ------ arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c | 70 ------- .../arm/mach-uniphier/ph1-pro4/early_clkrst_init.c | 30 --- arch/arm/mach-uniphier/ph1-pro4/pinctrl.c | 49 ----- arch/arm/mach-uniphier/ph1-pro4/pll_init.c | 149 --------------- arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c | 18 -- arch/arm/mach-uniphier/ph1-pro4/sbc_init.c | 42 ----- arch/arm/mach-uniphier/ph1-pro4/umc_init.c | 157 ---------------- arch/arm/mach-uniphier/ph1-sld3/Makefile | 13 -- arch/arm/mach-uniphier/ph1-sld3/bcu_init.c | 36 ---- arch/arm/mach-uniphier/ph1-sld3/boot-mode.c | 97 ---------- arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c | 1 - .../arm/mach-uniphier/ph1-sld3/early_clkrst_init.c | 1 - arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c | 23 --- arch/arm/mach-uniphier/ph1-sld3/memconf.c | 52 ------ arch/arm/mach-uniphier/ph1-sld3/pinctrl.c | 24 --- arch/arm/mach-uniphier/ph1-sld3/pll_init.c | 10 - arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c | 18 -- arch/arm/mach-uniphier/ph1-sld3/sbc_init.c | 45 ----- arch/arm/mach-uniphier/ph1-sld3/sg_init.c | 9 - arch/arm/mach-uniphier/ph1-sld3/umc_init.c | 15 -- arch/arm/mach-uniphier/ph1-sld8/Makefile | 1 - arch/arm/mach-uniphier/ph1-sld8/bcu_init.c | 1 - arch/arm/mach-uniphier/ph1-sld8/boot-mode.c | 1 - arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c | 1 - arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c | 75 -------- .../arm/mach-uniphier/ph1-sld8/early_clkrst_init.c | 1 - arch/arm/mach-uniphier/ph1-sld8/pinctrl.c | 42 ----- arch/arm/mach-uniphier/ph1-sld8/pll_init.c | 201 -------------------- arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c | 1 - arch/arm/mach-uniphier/ph1-sld8/sbc_init.c | 1 - arch/arm/mach-uniphier/ph1-sld8/umc_init.c | 151 --------------- arch/arm/mach-uniphier/pinctrl/Makefile | 4 + arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c | 49 +++++ arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c | 50 +++++ arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c | 25 +++ arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c | 43 +++++ arch/arm/mach-uniphier/pll/Makefile | 8 + arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c | 203 ++++++++++++++++++++ arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c | 163 ++++++++++++++++ arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c | 13 ++ arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c | 204 +++++++++++++++++++++ arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c | 20 ++ arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c | 21 +++ arch/arm/mach-uniphier/sbc/Makefile | 4 + arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c | 52 ++++++ arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c | 45 +++++ arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c | 48 +++++ arch/arm/mach-uniphier/soc_info.c | 61 ++++++ arch/arm/mach-uniphier/spl.c | 87 --------- arch/arm/mach-uniphier/umc/Makefile | 3 + arch/arm/mach-uniphier/umc/umc-ph1-ld4.c | 175 ++++++++++++++++++ arch/arm/mach-uniphier/umc/umc-ph1-pro4.c | 161 ++++++++++++++++ arch/arm/mach-uniphier/umc/umc-ph1-sld8.c | 155 ++++++++++++++++ configs/ph1_pro4_defconfig | 1 + include/configs/uniphier.h | 50 +---- 109 files changed, 3116 insertions(+), 2524 deletions(-) create mode 100644 arch/arm/mach-uniphier/bcu/Makefile create mode 100644 arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/boards.c create mode 100644 arch/arm/mach-uniphier/boot-mode/Makefile create mode 100644 arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/boot-mode/boot-mode.c create mode 100644 arch/arm/mach-uniphier/clk/Makefile create mode 100644 arch/arm/mach-uniphier/clk/clk-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/clk/clk-ph1-pro4.c create mode 100644 arch/arm/mach-uniphier/ddrphy/Makefile create mode 100644 arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c create mode 100644 arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c create mode 100644 arch/arm/mach-uniphier/ddrphy/ddrphy-training.c delete mode 100644 arch/arm/mach-uniphier/ddrphy_training.c create mode 100644 arch/arm/mach-uniphier/early-clk/Makefile create mode 100644 arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/early-pinctrl/Makefile create mode 100644 arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/include/mach/init.h create mode 100644 arch/arm/mach-uniphier/include/mach/soc_info.h create mode 100644 arch/arm/mach-uniphier/init/Makefile create mode 100644 arch/arm/mach-uniphier/init/init-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/init/init-ph1-pro4.c create mode 100644 arch/arm/mach-uniphier/init/init-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/init/init-ph1-sld8.c create mode 100644 arch/arm/mach-uniphier/init/init.c delete mode 100644 arch/arm/mach-uniphier/memconf.c create mode 100644 arch/arm/mach-uniphier/memconf/Makefile create mode 100644 arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/memconf/memconf.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/Makefile delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/bcu_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/boot-mode.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/pinctrl.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/pll_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/sbc_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-ld4/umc_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/Makefile delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/boot-mode.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/pinctrl.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/pll_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/sbc_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-pro4/umc_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/Makefile delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/bcu_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/boot-mode.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/memconf.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/pinctrl.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/pll_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/sbc_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/sg_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld3/umc_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/Makefile delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/bcu_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/boot-mode.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/pinctrl.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/pll_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/sbc_init.c delete mode 100644 arch/arm/mach-uniphier/ph1-sld8/umc_init.c create mode 100644 arch/arm/mach-uniphier/pinctrl/Makefile create mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c create mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c create mode 100644 arch/arm/mach-uniphier/pll/Makefile create mode 100644 arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c create mode 100644 arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c create mode 100644 arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/sbc/Makefile create mode 100644 arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c create mode 100644 arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c create mode 100644 arch/arm/mach-uniphier/soc_info.c delete mode 100644 arch/arm/mach-uniphier/spl.c create mode 100644 arch/arm/mach-uniphier/umc/Makefile create mode 100644 arch/arm/mach-uniphier/umc/umc-ph1-ld4.c create mode 100644 arch/arm/mach-uniphier/umc/umc-ph1-pro4.c create mode 100644 arch/arm/mach-uniphier/umc/umc-ph1-sld8.c (limited to 'include') diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index d7a19c6772c..2cc5dac0700 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -6,25 +6,32 @@ config SYS_CONFIG_NAME config UNIPHIER_SMP bool -choice - prompt "UniPhier SoC select" - default ARCH_UNIPHIER_PH1_PRO4 - config ARCH_UNIPHIER_PH1_SLD3 - bool "PH1-sLD3" + bool "UniPhier PH1-sLD3 SoC" select UNIPHIER_SMP + help + This enables support for UniPhier PH1-sLD3 SoC. config ARCH_UNIPHIER_PH1_LD4 - bool "PH1-LD4" + bool "UniPhier PH1-LD4 SoC" + depends on !ARCH_UNIPHIER_PH1_SLD3 + help + This enables support for UniPhier PH1-LD4 SoC. config ARCH_UNIPHIER_PH1_PRO4 - bool "PH1-Pro4" + bool "UniPhier PH1-Pro4 SoC" select UNIPHIER_SMP + depends on !ARCH_UNIPHIER_PH1_SLD3 && \ + !ARCH_UNIPHIER_PH1_LD4 && \ + !ARCH_UNIPHIER_PH1_SLD8 + help + This enables support for UniPhier PH1-Pro4 SoC. config ARCH_UNIPHIER_PH1_SLD8 - bool "PH1-sLD8" - -endchoice + bool "UniPhier PH1-sLD8 SoC" + depends on !ARCH_UNIPHIER_PH1_SLD3 + help + This enables support for UniPhier PH1-sLD8 SoC. config MICRO_SUPPORT_CARD bool "Use Micro Support Card" @@ -48,22 +55,4 @@ config CMD_DDRPHY_DUMP The command "ddrphy" shows the resulting parameters of DDR PHY training; it is useful for the evaluation of DDR PHY training. -choice - prompt "DDR3 Frequency select" - -config DDR_FREQ_1600 - bool "DDR3 1600" - depends on ARCH_UNIPHIER_PH1_SLD3 || ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_PRO4 - -config DDR_FREQ_1333 - bool "DDR3 1333" - depends on ARCH_UNIPHIER_PH1_SLD3 || ARCH_UNIPHIER_PH1_LD4 || ARCH_UNIPHIER_PH1_SLD8 - -endchoice - -config DDR_FREQ - int - default 1333 if DDR_FREQ_1333 - default 1600 if DDR_FREQ_1600 - endif diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 5c2ccbd7a88..b597a1352c2 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -6,9 +6,10 @@ ifdef CONFIG_SPL_BUILD obj-y += lowlevel_init.o obj-y += init_page_table.o -obj-y += spl.o -obj-y += memconf.o -obj-y += ddrphy_training.o +obj-y += boards.o + +obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ umc/ ddrphy/ +obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/ obj-$(CONFIG_DEBUG_LL) += debug_ll.o @@ -27,13 +28,12 @@ obj-y += cache_uniphier.o obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o obj-$(CONFIG_CMD_DDRPHY_DUMP) += cmd_ddrphy.o +obj-y += pinctrl/ clk/ + endif obj-y += timer.o +obj-y += soc_info.o +obj-y += boot-mode/ obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o - -obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += ph1-sld3/ -obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ph1-ld4/ -obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ph1-pro4/ -obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ph1-sld8/ diff --git a/arch/arm/mach-uniphier/bcu/Makefile b/arch/arm/mach-uniphier/bcu/Makefile new file mode 100644 index 00000000000..5b95bdad957 --- /dev/null +++ b/arch/arm/mach-uniphier/bcu/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += bcu-ph1-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += bcu-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += bcu-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c new file mode 100644 index 00000000000..e9d3761fde9 --- /dev/null +++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-ld4.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) + +int ph1_ld4_bcu_init(const struct uniphier_board_data *bd) +{ + int shift; + + writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */ + writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ + + /* Specify DDR channel */ + shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4; + writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ + + return 0; +} diff --git a/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c new file mode 100644 index 00000000000..cb6f8627211 --- /dev/null +++ b/arch/arm/mach-uniphier/bcu/bcu-ph1-sld3.c @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) + +int ph1_sld3_bcu_init(const struct uniphier_board_data *bd) +{ + int shift; + + writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ + writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ + /* + * 0xe0000000-0xefffffff: Ex-bus + * 0xf0000000-0xfbffffff: ASM bus + * 0xfc000000-0xffffffff: OCM bus + */ + writel(0x24440000, BCSCR5); + + /* Specify DDR channel */ + shift = (bd->dram_ch1_base - bd->dram_ch0_base) / 0x04000000 * 4; + writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ + + shift -= 32; + writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ + + return 0; +} diff --git a/arch/arm/mach-uniphier/board_early_init_f.c b/arch/arm/mach-uniphier/board_early_init_f.c index 45f5cea4334..cd516c3121a 100644 --- a/arch/arm/mach-uniphier/board_early_init_f.c +++ b/arch/arm/mach-uniphier/board_early_init_f.c @@ -4,20 +4,46 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include - -void pin_init(void); -void clkrst_init(void); +#include int board_early_init_f(void) { led_puts("U0"); - pin_init(); - - led_puts("U1"); - - clkrst_init(); + switch (uniphier_get_soc_type()) { +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + case SOC_UNIPHIER_PH1_SLD3: + ph1_sld3_pin_init(); + led_puts("U1"); + ph1_ld4_clk_init(); + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) + case SOC_UNIPHIER_PH1_LD4: + ph1_ld4_pin_init(); + led_puts("U1"); + ph1_ld4_clk_init(); + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + case SOC_UNIPHIER_PH1_PRO4: + ph1_pro4_pin_init(); + led_puts("U1"); + ph1_pro4_clk_init(); + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + case SOC_UNIPHIER_PH1_SLD8: + ph1_sld8_pin_init(); + led_puts("U1"); + ph1_ld4_clk_init(); + break; +#endif + default: + break; + } led_puts("U2"); diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c new file mode 100644 index 00000000000..6a5ea2e585f --- /dev/null +++ b/arch/arm/mach-uniphier/boards.c @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) +static const struct uniphier_board_data ph1_sld3_data = { + .dram_ch0_base = 0x80000000, + .dram_ch0_size = 0x20000000, + .dram_ch0_width = 32, + .dram_ch1_base = 0xc0000000, + .dram_ch1_size = 0x20000000, + .dram_ch1_width = 16, + .dram_ch2_base = 0xc0000000, + .dram_ch2_size = 0x10000000, + .dram_ch2_width = 16, + .dram_freq = 1600, +}; +#endif + +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) +static const struct uniphier_board_data ph1_ld4_data = { + .dram_ch0_base = 0x80000000, + .dram_ch0_size = 0x10000000, + .dram_ch0_width = 16, + .dram_ch1_base = 0x90000000, + .dram_ch1_size = 0x10000000, + .dram_ch1_width = 16, + .dram_freq = 1600, +}; +#endif + +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) +static const struct uniphier_board_data ph1_pro4_data = { + .dram_ch0_base = 0x80000000, + .dram_ch0_size = 0x20000000, + .dram_ch0_width = 32, + .dram_ch1_base = 0xa0000000, + .dram_ch1_size = 0x20000000, + .dram_ch1_width = 32, + .dram_freq = 1600, +}; +#endif + +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) +static const struct uniphier_board_data ph1_sld8_data = { + .dram_ch0_base = 0x80000000, + .dram_ch0_size = 0x10000000, + .dram_ch0_width = 16, + .dram_ch1_base = 0x90000000, + .dram_ch1_size = 0x10000000, + .dram_ch1_width = 16, + .dram_freq = 1333, +}; +#endif + +struct uniphier_board_id { + const char *compatible; + const struct uniphier_board_data *param; +}; + +static const struct uniphier_board_id uniphier_boards[] = { +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + { "socionext,ph1-sld3", &ph1_sld3_data, }, +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) + { "socionext,ph1-ld4", &ph1_ld4_data, }, +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + { "socionext,ph1-pro4", &ph1_pro4_data, }, +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + { "socionext,ph1-sld8", &ph1_sld8_data, }, +#endif +}; + +const struct uniphier_board_data *uniphier_get_board_param(const void *fdt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(uniphier_boards); i++) { + if (!fdt_node_check_compatible(fdt, 0, + uniphier_boards[i].compatible)) + return uniphier_boards[i].param; + } + + return NULL; +} diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile new file mode 100644 index 00000000000..bd6d0a3d7c9 --- /dev/null +++ b/arch/arm/mach-uniphier/boot-mode/Makefile @@ -0,0 +1,6 @@ +obj-y += boot-mode.o + +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += boot-mode-ph1-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += boot-mode-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += boot-mode-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += boot-mode-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c new file mode 100644 index 00000000000..f974d9f08d1 --- /dev/null +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-ld4.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2014-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +struct boot_device_info boot_device_table[] = { + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"}, + {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, +}; + +static int get_boot_mode_sel(void) +{ + return (readl(SG_PINMON0) >> 1) & 0x1f; +} + +u32 ph1_ld4_boot_device(void) +{ + int boot_mode; + + boot_mode = get_boot_mode_sel(); + + return boot_device_table[boot_mode].type; +} + +void ph1_ld4_boot_mode_show(void) +{ + int mode_sel, i; + + mode_sel = get_boot_mode_sel(); + + puts("Boot Mode Pin:\n"); + + for (i = 0; i < ARRAY_SIZE(boot_device_table); i++) + printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i, + boot_device_table[i].info); +} diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c new file mode 100644 index 00000000000..c943e12db15 --- /dev/null +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ph1-sld3.c @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2014-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +static struct boot_device_info boot_device_table[] = { + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "External Master"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, + {BOOT_DEVICE_NONE, "Reserved"}, +}; + +static int get_boot_mode_sel(void) +{ + return readl(SG_PINMON0) & 0x3f; +} + +u32 ph1_sld3_boot_device(void) +{ + int boot_mode; + + boot_mode = get_boot_mode_sel(); + + return boot_device_table[boot_mode].type; +} + +void ph1_sld3_boot_mode_show(void) +{ + int mode_sel, i; + + mode_sel = get_boot_mode_sel(); + + puts("Boot Mode Pin:\n"); + + for (i = 0; i < ARRAY_SIZE(boot_device_table); i++) + printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i, + boot_device_table[i].info); +} diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c new file mode 100644 index 00000000000..71abdef1f4d --- /dev/null +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +u32 spl_boot_device(void) +{ + if (boot_is_swapped()) + return BOOT_DEVICE_NOR; + + switch (uniphier_get_soc_type()) { +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + case SOC_UNIPHIER_PH1_SLD3: + return ph1_sld3_boot_device(); +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + case SOC_UNIPHIER_PH1_LD4: + case SOC_UNIPHIER_PH1_PRO4: + case SOC_UNIPHIER_PH1_SLD8: + return ph1_ld4_boot_device(); +#endif + default: + return BOOT_DEVICE_NONE; + } +} diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile new file mode 100644 index 00000000000..e6931d6461b --- /dev/null +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += clk-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += clk-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += clk-ph1-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += clk-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c new file mode 100644 index 00000000000..8b95fbb008a --- /dev/null +++ b/arch/arm/mach-uniphier/clk/clk-ph1-ld4.c @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ph1_ld4_clk_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_RSTCTRL_NRST_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_RSTCTRL_NRST_NAND; +#endif + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_CLKCTRL_CEN_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_CLKCTRL_CEN_NAND; +#endif + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c new file mode 100644 index 00000000000..2e1b20a423c --- /dev/null +++ b/arch/arm/mach-uniphier/clk/clk-ph1-pro4.c @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ph1_pro4_clk_init(void) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | + SC_RSTCTRL_NRST_GIO; +#endif +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_RSTCTRL_NRST_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_RSTCTRL_NRST_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_RSTCTRL_NRST_NAND; +#endif + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp = readl(SC_RSTCTRL2); + tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; + writel(tmp, SC_RSTCTRL2); + readl(SC_RSTCTRL2); /* dummy read */ +#endif + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); +#ifdef CONFIG_USB_XHCI_UNIPHIER + tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | + SC_CLKCTRL_CEN_GIO; +#endif +#ifdef CONFIG_UNIPHIER_ETH + tmp |= SC_CLKCTRL_CEN_ETHER; +#endif +#ifdef CONFIG_USB_EHCI_UNIPHIER + tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; +#endif +#ifdef CONFIG_NAND_DENALI + tmp |= SC_CLKCTRL_CEN_NAND; +#endif + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ +} diff --git a/arch/arm/mach-uniphier/cmd_pinmon.c b/arch/arm/mach-uniphier/cmd_pinmon.c index 8be2ed4fe63..a61d40e6c5a 100644 --- a/arch/arm/mach-uniphier/cmd_pinmon.c +++ b/arch/arm/mach-uniphier/cmd_pinmon.c @@ -1,6 +1,5 @@ /* - * Copyright (C) 2014 Panasonic Corporation - * Author: Masahiro Yamada + * Copyright (C) 2014-2015 Masahiro Yamada * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,20 +7,30 @@ #include #include #include +#include static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - int mode_sel, i; - printf("Boot Swap: %s\n\n", boot_is_swapped() ? "ON" : "OFF"); - mode_sel = get_boot_mode_sel(); - - puts("Boot Mode Pin:\n"); - - for (i = 0; boot_device_table[i].info; i++) - printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i, - boot_device_table[i].info); + switch (uniphier_get_soc_type()) { +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + case SOC_UNIPHIER_PH1_SLD3: + ph1_sld3_boot_mode_show(); + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) || \ + defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + case SOC_UNIPHIER_PH1_LD4: + case SOC_UNIPHIER_PH1_PRO4: + case SOC_UNIPHIER_PH1_SLD8: + ph1_ld4_boot_mode_show(); + break; +#endif + default: + break; + } return 0; } diff --git a/arch/arm/mach-uniphier/ddrphy/Makefile b/arch/arm/mach-uniphier/ddrphy/Makefile new file mode 100644 index 00000000000..e2d109df57a --- /dev/null +++ b/arch/arm/mach-uniphier/ddrphy/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += ddrphy-training.o ddrphy-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += ddrphy-training.o ddrphy-ph1-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += ddrphy-training.o ddrphy-ph1-sld8.o diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c new file mode 100644 index 00000000000..991d9294fd0 --- /dev/null +++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-ld4.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2014-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8253c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a82dbc0, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + + writel(0x00000800, &phy->mr3); + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); + + return 0; +} diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c new file mode 100644 index 00000000000..bc47ba3280d --- /dev/null +++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-pro4.c @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2014-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8363c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a878400, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + + writel(0x00000000, &phy->mr3); + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); + + return 0; +} diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c new file mode 100644 index 00000000000..39024a09d5e --- /dev/null +++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-ph1-sld8.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2014-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) +{ + u32 tmp; + + writel(0x0300c473, &phy->pgcr[1]); + if (freq == 1333) { + writel(0x0a806844, &phy->ptr[0]); + writel(0x208e0124, &phy->ptr[1]); + } else { + writel(0x0c807d04, &phy->ptr[0]); + writel(0x2710015E, &phy->ptr[1]); + } + writel(0x00083DEF, &phy->ptr[2]); + if (freq == 1333) { + writel(0x0f051616, &phy->ptr[3]); + writel(0x06ae08d6, &phy->ptr[4]); + } else { + writel(0x12061A80, &phy->ptr[3]); + writel(0x08027100, &phy->ptr[4]); + } + writel(0xF004001A, &phy->dsgcr); + + /* change the value of the on-die pull-up/pull-down registors */ + tmp = readl(&phy->dxccr); + tmp &= ~0x0ee0; + tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; + writel(tmp, &phy->dxccr); + + writel(0x0000040B, &phy->dcr); + if (freq == 1333) { + writel(0x85589955, &phy->dtpr[0]); + if (size == 1) + writel(0x1a8363c0, &phy->dtpr[1]); + else + writel(0x1a8363c0, &phy->dtpr[1]); + writel(0x5002c200, &phy->dtpr[2]); + writel(0x00000b51, &phy->mr0); + } else { + writel(0x999cbb66, &phy->dtpr[0]); + if (size == 1) + writel(0x1a878400, &phy->dtpr[1]); + else + writel(0x1a878400, &phy->dtpr[1]); + writel(0xa00214f8, &phy->dtpr[2]); + writel(0x00000d71, &phy->mr0); + } + writel(0x00000006, &phy->mr1); + if (freq == 1333) + writel(0x00000290, &phy->mr2); + else + writel(0x00000298, &phy->mr2); + +#ifdef CONFIG_DDR_STANDARD + writel(0x00000000, &phy->mr3); +#else + writel(0x00000800, &phy->mr3); +#endif + + while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) + ; + + writel(0x0300C473, &phy->pgcr[1]); + writel(0x0000005D, &phy->zq[0].cr[1]); + + return 0; +} diff --git a/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c b/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c new file mode 100644 index 00000000000..a98b814df07 --- /dev/null +++ b/arch/arm/mach-uniphier/ddrphy/ddrphy-training.c @@ -0,0 +1,139 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank) +{ + int dx; + u32 __iomem tmp, *p; + + for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { + p = &phy->dx[dx].gcr; + + tmp = readl(p); + /* Specify the rank that should be write leveled */ + tmp &= ~DXGCR_WLRKEN_MASK; + tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK; + writel(tmp, p); + } + + p = &phy->dtcr; + + tmp = readl(p); + /* Specify the rank used during data bit deskew and eye centering */ + tmp &= ~DTCR_DTRANK_MASK; + tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK; + /* Use Multi-Purpose Register for DQS gate training */ + tmp |= DTCR_DTMPR; + /* Specify the rank enabled for data-training */ + tmp &= ~DTCR_RNKEN_MASK; + tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK; + writel(tmp, p); +} + +struct ddrphy_init_sequence { + char *description; + u32 init_flag; + u32 done_flag; + u32 err_flag; +}; + +static struct ddrphy_init_sequence init_sequence[] = { + { + "DRAM Initialization", + PIR_DRAMRST | PIR_DRAMINIT, + PGSR0_DIDONE, + PGSR0_DIERR + }, + { + "Write Leveling", + PIR_WL, + PGSR0_WLDONE, + PGSR0_WLERR + }, + { + "Read DQS Gate Training", + PIR_QSGATE, + PGSR0_QSGDONE, + PGSR0_QSGERR + }, + { + "Write Leveling Adjustment", + PIR_WLADJ, + PGSR0_WLADONE, + PGSR0_WLAERR + }, + { + "Read Bit Deskew", + PIR_RDDSKW, + PGSR0_RDDONE, + PGSR0_RDERR + }, + { + "Write Bit Deskew", + PIR_WRDSKW, + PGSR0_WDDONE, + PGSR0_WDERR + }, + { + "Read Eye Training", + PIR_RDEYE, + PGSR0_REDONE, + PGSR0_REERR + }, + { + "Write Eye Training", + PIR_WREYE, + PGSR0_WEDONE, + PGSR0_WEERR + } +}; + +int ddrphy_training(struct ddrphy __iomem *phy) +{ + int i; + u32 pgsr0; + u32 init_flag = PIR_INIT; + u32 done_flag = PGSR0_IDONE; + int timeout = 50000; /* 50 msec is long enough */ +#ifdef DISPLAY_ELAPSED_TIME + ulong start = get_timer(0); +#endif + + for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { + init_flag |= init_sequence[i].init_flag; + done_flag |= init_sequence[i].done_flag; + } + + writel(init_flag, &phy->pir); + + do { + if (--timeout < 0) { + printf("%s: error: timeout during DDR training\n", + __func__); + return -1; + } + udelay(1); + pgsr0 = readl(&phy->pgsr[0]); + } while ((pgsr0 & done_flag) != done_flag); + + for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { + if (pgsr0 & init_sequence[i].err_flag) { + printf("%s: error: %s failed\n", __func__, + init_sequence[i].description); + return -1; + } + } + +#ifdef DISPLAY_ELAPSED_TIME + printf("%s: info: elapsed time %ld msec\n", get_timer(start)); +#endif + + return 0; +} diff --git a/arch/arm/mach-uniphier/ddrphy_training.c b/arch/arm/mach-uniphier/ddrphy_training.c deleted file mode 100644 index a98b814df07..00000000000 --- a/arch/arm/mach-uniphier/ddrphy_training.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank) -{ - int dx; - u32 __iomem tmp, *p; - - for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { - p = &phy->dx[dx].gcr; - - tmp = readl(p); - /* Specify the rank that should be write leveled */ - tmp &= ~DXGCR_WLRKEN_MASK; - tmp |= (1 << (DXGCR_WLRKEN_SHIFT + rank)) & DXGCR_WLRKEN_MASK; - writel(tmp, p); - } - - p = &phy->dtcr; - - tmp = readl(p); - /* Specify the rank used during data bit deskew and eye centering */ - tmp &= ~DTCR_DTRANK_MASK; - tmp |= (rank << DTCR_DTRANK_SHIFT) & DTCR_DTRANK_MASK; - /* Use Multi-Purpose Register for DQS gate training */ - tmp |= DTCR_DTMPR; - /* Specify the rank enabled for data-training */ - tmp &= ~DTCR_RNKEN_MASK; - tmp |= (1 << (DTCR_RNKEN_SHIFT + rank)) & DTCR_RNKEN_MASK; - writel(tmp, p); -} - -struct ddrphy_init_sequence { - char *description; - u32 init_flag; - u32 done_flag; - u32 err_flag; -}; - -static struct ddrphy_init_sequence init_sequence[] = { - { - "DRAM Initialization", - PIR_DRAMRST | PIR_DRAMINIT, - PGSR0_DIDONE, - PGSR0_DIERR - }, - { - "Write Leveling", - PIR_WL, - PGSR0_WLDONE, - PGSR0_WLERR - }, - { - "Read DQS Gate Training", - PIR_QSGATE, - PGSR0_QSGDONE, - PGSR0_QSGERR - }, - { - "Write Leveling Adjustment", - PIR_WLADJ, - PGSR0_WLADONE, - PGSR0_WLAERR - }, - { - "Read Bit Deskew", - PIR_RDDSKW, - PGSR0_RDDONE, - PGSR0_RDERR - }, - { - "Write Bit Deskew", - PIR_WRDSKW, - PGSR0_WDDONE, - PGSR0_WDERR - }, - { - "Read Eye Training", - PIR_RDEYE, - PGSR0_REDONE, - PGSR0_REERR - }, - { - "Write Eye Training", - PIR_WREYE, - PGSR0_WEDONE, - PGSR0_WEERR - } -}; - -int ddrphy_training(struct ddrphy __iomem *phy) -{ - int i; - u32 pgsr0; - u32 init_flag = PIR_INIT; - u32 done_flag = PGSR0_IDONE; - int timeout = 50000; /* 50 msec is long enough */ -#ifdef DISPLAY_ELAPSED_TIME - ulong start = get_timer(0); -#endif - - for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { - init_flag |= init_sequence[i].init_flag; - done_flag |= init_sequence[i].done_flag; - } - - writel(init_flag, &phy->pir); - - do { - if (--timeout < 0) { - printf("%s: error: timeout during DDR training\n", - __func__); - return -1; - } - udelay(1); - pgsr0 = readl(&phy->pgsr[0]); - } while ((pgsr0 & done_flag) != done_flag); - - for (i = 0; i < ARRAY_SIZE(init_sequence); i++) { - if (pgsr0 & init_sequence[i].err_flag) { - printf("%s: error: %s failed\n", __func__, - init_sequence[i].description); - return -1; - } - } - -#ifdef DISPLAY_ELAPSED_TIME - printf("%s: info: elapsed time %ld msec\n", get_timer(start)); -#endif - - return 0; -} diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile new file mode 100644 index 00000000000..58af1add582 --- /dev/null +++ b/arch/arm/mach-uniphier/early-clk/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-clk-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += early-clk-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += early-clk-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += early-clk-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c new file mode 100644 index 00000000000..f646c9b7df9 --- /dev/null +++ b/arch/arm/mach-uniphier/early-clk/early-clk-ph1-ld4.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL); + + tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0; + if (spl_boot_device() != BOOT_DEVICE_NAND) + tmp &= ~SC_RSTCTRL_NRST_NAND; + writel(tmp, SC_RSTCTRL); + readl(SC_RSTCTRL); /* dummy read */ + + /* privide clocks */ + tmp = readl(SC_CLKCTRL); + tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; + writel(tmp, SC_CLKCTRL); + readl(SC_CLKCTRL); /* dummy read */ + + return 0; +} diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile new file mode 100644 index 00000000000..e497d28f792 --- /dev/null +++ b/arch/arm/mach-uniphier/early-pinctrl/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += early-pinctrl-ph1-sld3.o diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c new file mode 100644 index 00000000000..1bb9375016d --- /dev/null +++ b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ph1-sld3.c @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_UNIPHIER_SERIAL + sg_set_pinsel(63, 0, 4, 4); /* RXD0 */ + sg_set_pinsel(64, 1, 4, 4); /* TXD0 */ + + sg_set_pinsel(65, 0, 4, 4); /* RXD1 */ + sg_set_pinsel(66, 1, 4, 4); /* TXD1 */ + + sg_set_pinsel(96, 2, 4, 4); /* RXD2 */ + sg_set_pinsel(102, 2, 4, 4); /* TXD2 */ +#endif + + return 0; +} diff --git a/arch/arm/mach-uniphier/include/mach/boot-device.h b/arch/arm/mach-uniphier/include/mach/boot-device.h index 7a10f1c5b2c..eddb25ffa45 100644 --- a/arch/arm/mach-uniphier/include/mach/boot-device.h +++ b/arch/arm/mach-uniphier/include/mach/boot-device.h @@ -1,6 +1,5 @@ /* - * Copyright (C) 2011-2014 Panasonic Corporation - * Author: Masahiro Yamada + * Copyright (C) 2011-2015 Masahiro Yamada * * SPDX-License-Identifier: GPL-2.0+ */ @@ -8,13 +7,15 @@ #ifndef _ASM_BOOT_DEVICE_H_ #define _ASM_BOOT_DEVICE_H_ -int get_boot_mode_sel(void); - struct boot_device_info { u32 type; char *info; }; -extern struct boot_device_info boot_device_table[]; +u32 ph1_sld3_boot_device(void); +u32 ph1_ld4_boot_device(void); + +void ph1_sld3_boot_mode_show(void); +void ph1_ld4_boot_mode_show(void); #endif /* _ASM_BOOT_DEVICE_H_ */ diff --git a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h index 01f5c52c9c4..adcc972877e 100644 --- a/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h +++ b/arch/arm/mach-uniphier/include/mach/ddrphy-regs.h @@ -168,7 +168,9 @@ struct ddrphy { #define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy)) #ifndef __ASSEMBLY__ -void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); +int ph1_ld4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); +int ph1_pro4_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); +int ph1_sld8_ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank); int ddrphy_training(struct ddrphy __iomem *phy); #endif diff --git a/arch/arm/mach-uniphier/include/mach/init.h b/arch/arm/mach-uniphier/include/mach/init.h new file mode 100644 index 00000000000..228cbb1a195 --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/init.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MACH_INIT_H +#define __MACH_INIT_H + +struct uniphier_board_data { + unsigned long dram_ch0_base; + unsigned long dram_ch0_size; + unsigned long dram_ch0_width; + unsigned long dram_ch1_base; + unsigned long dram_ch1_size; + unsigned long dram_ch1_width; + unsigned long dram_ch2_base; + unsigned long dram_ch2_size; + unsigned long dram_ch2_width; + unsigned int dram_freq; +}; + +const struct uniphier_board_data *uniphier_get_board_param(const void *fdt); + +int ph1_sld3_init(const struct uniphier_board_data *bd); +int ph1_ld4_init(const struct uniphier_board_data *bd); +int ph1_pro4_init(const struct uniphier_board_data *bd); +int ph1_sld8_init(const struct uniphier_board_data *bd); + +#if defined(CONFIG_MICRO_SUPPORT_CARD) +int ph1_sld3_sbc_init(const struct uniphier_board_data *bd); +int ph1_ld4_sbc_init(const struct uniphier_board_data *bd); +int ph1_pro4_sbc_init(const struct uniphier_board_data *bd); +#else +static inline int ph1_sld3_sbc_init(const struct uniphier_board_data *bd) +{ + return 0; +} + +static inline int ph1_ld4_sbc_init(const struct uniphier_board_data *bd) +{ + return 0; +} + +static inline int ph1_pro4_sbc_init(const struct uniphier_board_data *bd) +{ + return 0; +} +#endif + +int ph1_sld3_bcu_init(const struct uniphier_board_data *bd); +int ph1_ld4_bcu_init(const struct uniphier_board_data *bd); + +int memconf_init(const struct uniphier_board_data *bd); +int ph1_sld3_memconf_init(const struct uniphier_board_data *bd); + +int ph1_sld3_pll_init(const struct uniphier_board_data *bd); +int ph1_ld4_pll_init(const struct uniphier_board_data *bd); +int ph1_pro4_pll_init(const struct uniphier_board_data *bd); +int ph1_sld8_pll_init(const struct uniphier_board_data *bd); + +int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd); +int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd); + +int ph1_ld4_early_clk_init(const struct uniphier_board_data *bd); + +int ph1_sld3_early_pin_init(const struct uniphier_board_data *bd); + +int ph1_ld4_umc_init(const struct uniphier_board_data *bd); +int ph1_pro4_umc_init(const struct uniphier_board_data *bd); +int ph1_sld8_umc_init(const struct uniphier_board_data *bd); + +void ph1_sld3_pin_init(void); +void ph1_ld4_pin_init(void); +void ph1_pro4_pin_init(void); +void ph1_sld8_pin_init(void); + +void ph1_ld4_clk_init(void); +void ph1_pro4_clk_init(void); + +#define pr_err(fmt, args...) printf(fmt, ##args) + +#endif /* __MACH_INIT_H */ diff --git a/arch/arm/mach-uniphier/include/mach/sg-regs.h b/arch/arm/mach-uniphier/include/mach/sg-regs.h index c886e1c6555..d8239f28bc5 100644 --- a/arch/arm/mach-uniphier/include/mach/sg-regs.h +++ b/arch/arm/mach-uniphier/include/mach/sg-regs.h @@ -25,26 +25,32 @@ /* Memory Configuration */ #define SG_MEMCONF (SG_CTRL_BASE | 0x0400) +#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) | (0x03 << 0)) #define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) | (0x01 << 0)) #define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) | (0x02 << 0)) #define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) | (0x03 << 0)) #define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) | (0x00 << 0)) #define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) | (0x01 << 0)) +#define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8) #define SG_MEMCONF_CH0_NUM_1 (0x1 << 8) #define SG_MEMCONF_CH0_NUM_2 (0x0 << 8) +#define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) | (0x03 << 2)) #define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) | (0x01 << 2)) #define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) | (0x02 << 2)) #define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) | (0x03 << 2)) #define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) | (0x00 << 2)) #define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) | (0x01 << 2)) +#define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9) #define SG_MEMCONF_CH1_NUM_1 (0x1 << 9) #define SG_MEMCONF_CH1_NUM_2 (0x0 << 9) +#define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) | (0x03 << 16)) #define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) | (0x01 << 16)) #define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16)) #define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16)) #define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16)) +#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24) #define SG_MEMCONF_CH2_NUM_1 (0x1 << 24) #define SG_MEMCONF_CH2_NUM_2 (0x0 << 24) diff --git a/arch/arm/mach-uniphier/include/mach/soc_info.h b/arch/arm/mach-uniphier/include/mach/soc_info.h new file mode 100644 index 00000000000..623e7ef20ee --- /dev/null +++ b/arch/arm/mach-uniphier/include/mach/soc_info.h @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __MACH_SOC_INFO_H__ +#define __MACH_SOC_INFO_H__ + +enum uniphier_soc_id { + SOC_UNIPHIER_PH1_SLD3, + SOC_UNIPHIER_PH1_LD4, + SOC_UNIPHIER_PH1_PRO4, + SOC_UNIPHIER_PH1_SLD8, + SOC_UNIPHIER_PH1_PRO5, + SOC_UNIPHIER_PROXSTREAM2, + SOC_UNIPHIER_PH1_LD6B, + SOC_UNIPHIER_UNKNOWN, +}; + +#define UNIPHIER_NR_ENABLED_SOCS \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD4) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + \ + IS_ENABLED(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + +#define UNIPHIER_MULTI_SOC ((UNIPHIER_NR_ENABLED_SOCS) > 1) + +#if UNIPHIER_MULTI_SOC +enum uniphier_soc_id uniphier_get_soc_type(void); +#else +static inline enum uniphier_soc_id uniphier_get_soc_type(void) +{ +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + return SOC_UNIPHIER_PH1_SLD3; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) + return SOC_UNIPHIER_PH1_LD4; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + return SOC_UNIPHIER_PH1_PRO4; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + return SOC_UNIPHIER_PH1_SLD8; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5) + return SOC_UNIPHIER_PH1_PRO5; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2) + return SOC_UNIPHIER_PROXSTREAM2; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B) + return SOC_UNIPHIER_PH1_LD6B; +#endif + + return SOC_UNIPHIER_UNKNOWN; +} +#endif + +#endif /* __MACH_SOC_INFO_H__ */ diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile new file mode 100644 index 00000000000..dd9804d33b5 --- /dev/null +++ b/arch/arm/mach-uniphier/init/Makefile @@ -0,0 +1,6 @@ +obj-y += init.o + +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += init-ph1-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += init-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += init-ph1-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += init-ph1-sld8.o diff --git a/arch/arm/mach-uniphier/init/init-ph1-ld4.c b/arch/arm/mach-uniphier/init/init-ph1-ld4.c new file mode 100644 index 00000000000..8d0ef0389e1 --- /dev/null +++ b/arch/arm/mach-uniphier/init/init-ph1-ld4.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2013-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_ld4_init(const struct uniphier_board_data *bd) +{ + ph1_ld4_bcu_init(bd); + + ph1_ld4_sbc_init(bd); + + support_card_reset(); + + ph1_ld4_pll_init(bd); + + support_card_init(); + + led_puts("L0"); + + memconf_init(bd); + + led_puts("L1"); + + ph1_ld4_early_clk_init(bd); + + led_puts("L2"); + + led_puts("L3"); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_puts("L4"); + + { + int res; + + res = ph1_ld4_umc_init(bd); + if (res < 0) { + while (1) + ; + } + } + + led_puts("L5"); + + ph1_ld4_enable_dpll_ssc(bd); + + led_puts("L6"); + + return 0; +} diff --git a/arch/arm/mach-uniphier/init/init-ph1-pro4.c b/arch/arm/mach-uniphier/init/init-ph1-pro4.c new file mode 100644 index 00000000000..b9ce08d88f9 --- /dev/null +++ b/arch/arm/mach-uniphier/init/init-ph1-pro4.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2013-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_pro4_init(const struct uniphier_board_data *bd) +{ + ph1_pro4_sbc_init(bd); + + support_card_reset(); + + ph1_pro4_pll_init(bd); + + support_card_init(); + + led_puts("L0"); + + memconf_init(bd); + + led_puts("L1"); + + ph1_ld4_early_clk_init(bd); + + led_puts("L2"); + + led_puts("L3"); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_puts("L4"); + + { + int res; + + res = ph1_pro4_umc_init(bd); + if (res < 0) { + while (1) + ; + } + } + + led_puts("L5"); + + ph1_ld4_enable_dpll_ssc(bd); + + led_puts("L6"); + + return 0; +} diff --git a/arch/arm/mach-uniphier/init/init-ph1-sld3.c b/arch/arm/mach-uniphier/init/init-ph1-sld3.c new file mode 100644 index 00000000000..1146fdab977 --- /dev/null +++ b/arch/arm/mach-uniphier/init/init-ph1-sld3.c @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2013-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_sld3_init(const struct uniphier_board_data *bd) +{ + ph1_sld3_bcu_init(bd); + + ph1_sld3_sbc_init(bd); + + support_card_reset(); + + ph1_sld3_pll_init(bd); + + support_card_init(); + + led_puts("L0"); + + memconf_init(bd); + ph1_sld3_memconf_init(bd); + + led_puts("L1"); + + ph1_ld4_early_clk_init(bd); + + led_puts("L2"); + + ph1_sld3_early_pin_init(bd); + + led_puts("L3"); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_puts("L4"); + + led_puts("L5"); + + ph1_sld3_enable_dpll_ssc(bd); + + led_puts("L6"); + + return 0; +} diff --git a/arch/arm/mach-uniphier/init/init-ph1-sld8.c b/arch/arm/mach-uniphier/init/init-ph1-sld8.c new file mode 100644 index 00000000000..741e88c212f --- /dev/null +++ b/arch/arm/mach-uniphier/init/init-ph1-sld8.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2013-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_sld8_init(const struct uniphier_board_data *bd) +{ + ph1_ld4_bcu_init(bd); + + ph1_ld4_sbc_init(bd); + + support_card_reset(); + + ph1_sld8_pll_init(bd); + + support_card_init(); + + led_puts("L0"); + + memconf_init(bd); + + led_puts("L1"); + + ph1_ld4_early_clk_init(bd); + + led_puts("L2"); + + led_puts("L3"); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_puts("L4"); + + { + int res; + + res = ph1_sld8_umc_init(bd); + if (res < 0) { + while (1) + ; + } + } + + led_puts("L5"); + + ph1_ld4_enable_dpll_ssc(bd); + + led_puts("L6"); + + return 0; +} diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c new file mode 100644 index 00000000000..316be029ae6 --- /dev/null +++ b/arch/arm/mach-uniphier/init/init.c @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void spl_board_init(void) +{ + const struct uniphier_board_data *param; + + param = uniphier_get_board_param(gd->fdt_blob); + if (!param) + hang(); + + switch (uniphier_get_soc_type()) { +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) + case SOC_UNIPHIER_PH1_SLD3: + ph1_sld3_init(param); + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) + case SOC_UNIPHIER_PH1_LD4: + ph1_ld4_init(param); + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) + case SOC_UNIPHIER_PH1_PRO4: + ph1_pro4_init(param); + break; +#endif +#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) + case SOC_UNIPHIER_PH1_SLD8: + ph1_sld8_init(param); + break; +#endif + default: + break; + } +} diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c deleted file mode 100644 index 59ed0b5dd8f..00000000000 --- a/arch/arm/mach-uniphier/memconf.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static inline u32 sg_memconf_val_ch0(unsigned long size, int num) -{ - int size_mb = size / num; - u32 ret; - - switch (size_mb) { - case SZ_64M: - ret = SG_MEMCONF_CH0_SZ_64M; - break; - case SZ_128M: - ret = SG_MEMCONF_CH0_SZ_128M; - break; - case SZ_256M: - ret = SG_MEMCONF_CH0_SZ_256M; - break; - case SZ_512M: - ret = SG_MEMCONF_CH0_SZ_512M; - break; - case SZ_1G: - ret = SG_MEMCONF_CH0_SZ_1G; - break; - default: - BUG(); - break; - } - - switch (num) { - case 1: - ret |= SG_MEMCONF_CH0_NUM_1; - break; - case 2: - ret |= SG_MEMCONF_CH0_NUM_2; - break; - default: - BUG(); - break; - } - return ret; -} - -static inline u32 sg_memconf_val_ch1(unsigned long size, int num) -{ - int size_mb = size / num; - u32 ret; - - switch (size_mb) { - case SZ_64M: - ret = SG_MEMCONF_CH1_SZ_64M; - break; - case SZ_128M: - ret = SG_MEMCONF_CH1_SZ_128M; - break; - case SZ_256M: - ret = SG_MEMCONF_CH1_SZ_256M; - break; - case SZ_512M: - ret = SG_MEMCONF_CH1_SZ_512M; - break; - case SZ_1G: - ret = SG_MEMCONF_CH1_SZ_1G; - break; - default: - BUG(); - break; - } - - switch (num) { - case 1: - ret |= SG_MEMCONF_CH1_NUM_1; - break; - case 2: - ret |= SG_MEMCONF_CH1_NUM_2; - break; - default: - BUG(); - break; - } - return ret; -} - -void memconf_init(void) -{ - u32 tmp; - - /* Set DDR size */ - tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0); - tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1); -#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE - tmp |= SG_MEMCONF_SPARSEMEM; -#endif - writel(tmp, SG_MEMCONF); -} diff --git a/arch/arm/mach-uniphier/memconf/Makefile b/arch/arm/mach-uniphier/memconf/Makefile new file mode 100644 index 00000000000..1a718f31fae --- /dev/null +++ b/arch/arm/mach-uniphier/memconf/Makefile @@ -0,0 +1,2 @@ +obj-y += memconf.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += memconf-ph1-sld3.o diff --git a/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c new file mode 100644 index 00000000000..e13f56d1dcb --- /dev/null +++ b/arch/arm/mach-uniphier/memconf/memconf-ph1-sld3.c @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +int ph1_sld3_memconf_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + unsigned long size_per_word; + + tmp = readl(SG_MEMCONF); + + tmp &= ~(SG_MEMCONF_CH2_SZ_MASK | SG_MEMCONF_CH2_NUM_MASK); + + switch (bd->dram_ch2_width) { + case 16: + tmp |= SG_MEMCONF_CH2_NUM_1; + size_per_word = bd->dram_ch2_size; + break; + case 32: + tmp |= SG_MEMCONF_CH2_NUM_2; + size_per_word = bd->dram_ch2_size >> 1; + break; + default: + pr_err("error: unsupported DRAM Ch2 width\n"); + return -EINVAL; + } + + /* Set DDR size */ + switch (size_per_word) { + case SZ_64M: + tmp |= SG_MEMCONF_CH2_SZ_64M; + break; + case SZ_128M: + tmp |= SG_MEMCONF_CH2_SZ_128M; + break; + case SZ_256M: + tmp |= SG_MEMCONF_CH2_SZ_256M; + break; + case SZ_512M: + tmp |= SG_MEMCONF_CH2_SZ_512M; + break; + default: + pr_err("error: unsupported DRAM Ch2 size\n"); + return -EINVAL; + } + + writel(tmp, SG_MEMCONF); + + return 0; +} diff --git a/arch/arm/mach-uniphier/memconf/memconf.c b/arch/arm/mach-uniphier/memconf/memconf.c new file mode 100644 index 00000000000..d490736fa43 --- /dev/null +++ b/arch/arm/mach-uniphier/memconf/memconf.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +int memconf_init(const struct uniphier_board_data *bd) +{ + u32 tmp = 0; + unsigned long size_per_word; + + tmp = readl(SG_MEMCONF); + + tmp &= ~(SG_MEMCONF_CH0_SZ_MASK | SG_MEMCONF_CH0_NUM_MASK); + + switch (bd->dram_ch0_width) { + case 16: + tmp |= SG_MEMCONF_CH0_NUM_1; + size_per_word = bd->dram_ch0_size; + break; + case 32: + tmp |= SG_MEMCONF_CH0_NUM_2; + size_per_word = bd->dram_ch0_size >> 1; + break; + default: + pr_err("error: unsupported DRAM Ch0 width\n"); + return -EINVAL; + } + + /* Set DDR size */ + switch (size_per_word) { + case SZ_64M: + tmp |= SG_MEMCONF_CH0_SZ_64M; + break; + case SZ_128M: + tmp |= SG_MEMCONF_CH0_SZ_128M; + break; + case SZ_256M: + tmp |= SG_MEMCONF_CH0_SZ_256M; + break; + case SZ_512M: + tmp |= SG_MEMCONF_CH0_SZ_512M; + break; + case SZ_1G: + tmp |= SG_MEMCONF_CH0_SZ_1G; + break; + default: + pr_err("error: unsupported DRAM Ch0 size\n"); + return -EINVAL; + } + + tmp &= ~(SG_MEMCONF_CH1_SZ_MASK | SG_MEMCONF_CH1_NUM_MASK); + + switch (bd->dram_ch1_width) { + case 16: + tmp |= SG_MEMCONF_CH1_NUM_1; + size_per_word = bd->dram_ch1_size; + break; + case 32: + tmp |= SG_MEMCONF_CH1_NUM_2; + size_per_word = bd->dram_ch1_size >> 1; + break; + default: + pr_err("error: unsupported DRAM Ch1 width\n"); + return -EINVAL; + } + + switch (size_per_word) { + case SZ_64M: + tmp |= SG_MEMCONF_CH1_SZ_64M; + break; + case SZ_128M: + tmp |= SG_MEMCONF_CH1_SZ_128M; + break; + case SZ_256M: + tmp |= SG_MEMCONF_CH1_SZ_256M; + break; + case SZ_512M: + tmp |= SG_MEMCONF_CH1_SZ_512M; + break; + case SZ_1G: + tmp |= SG_MEMCONF_CH1_SZ_1G; + break; + default: + pr_err("error: unsupported DRAM Ch1 size\n"); + return -EINVAL; + } + + if (bd->dram_ch0_base + bd->dram_ch0_size < bd->dram_ch1_base) + tmp |= SG_MEMCONF_SPARSEMEM; + else + tmp &= ~SG_MEMCONF_SPARSEMEM; + + writel(tmp, SG_MEMCONF); + + return 0; +} diff --git a/arch/arm/mach-uniphier/ph1-ld4/Makefile b/arch/arm/mach-uniphier/ph1-ld4/Makefile deleted file mode 100644 index 4b9fe91fb03..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-y += bcu_init.o pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o -obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o -else -obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -endif - -obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-ld4/bcu_init.c b/arch/arm/mach-uniphier/ph1-ld4/bcu_init.c deleted file mode 100644 index a7bc15e7e06..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/bcu_init.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) - -void bcu_init(void) -{ - int shift; - - writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */ - writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */ - - /* Specify DDR channel */ - shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4; - writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ - - shift -= 32; - writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ - - shift -= 32; - writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ -} diff --git a/arch/arm/mach-uniphier/ph1-ld4/boot-mode.c b/arch/arm/mach-uniphier/ph1-ld4/boot-mode.c deleted file mode 100644 index d359b562919..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/boot-mode.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-pro4/boot-mode.c" diff --git a/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c b/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c deleted file mode 100644 index 2de81f0a560..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -void clkrst_init(void) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(SC_RSTCTRL); -#ifdef CONFIG_UNIPHIER_ETH - tmp |= SC_RSTCTRL_NRST_ETHER; -#endif -#ifdef CONFIG_USB_EHCI_UNIPHIER - tmp |= SC_RSTCTRL_NRST_STDMAC; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_RSTCTRL_NRST_NAND; -#endif - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ - - /* privide clocks */ - tmp = readl(SC_CLKCTRL); -#ifdef CONFIG_UNIPHIER_ETH - tmp |= SC_CLKCTRL_CEN_ETHER; -#endif -#ifdef CONFIG_USB_EHCI_UNIPHIER - tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_CLKCTRL_CEN_NAND; -#endif - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ -} diff --git a/arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c b/arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c deleted file mode 100644 index 2add8fa691f..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) -{ - u32 tmp; - - writel(0x0300c473, &phy->pgcr[1]); - if (freq == 1333) { - writel(0x0a806844, &phy->ptr[0]); - writel(0x208e0124, &phy->ptr[1]); - } else { - writel(0x0c807d04, &phy->ptr[0]); - writel(0x2710015E, &phy->ptr[1]); - } - writel(0x00083DEF, &phy->ptr[2]); - if (freq == 1333) { - writel(0x0f051616, &phy->ptr[3]); - writel(0x06ae08d6, &phy->ptr[4]); - } else { - writel(0x12061A80, &phy->ptr[3]); - writel(0x08027100, &phy->ptr[4]); - } - writel(0xF004001A, &phy->dsgcr); - - /* change the value of the on-die pull-up/pull-down registors */ - tmp = readl(&phy->dxccr); - tmp &= ~0x0ee0; - tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; - writel(tmp, &phy->dxccr); - - writel(0x0000040B, &phy->dcr); - if (freq == 1333) { - writel(0x85589955, &phy->dtpr[0]); - if (size == 1) - writel(0x1a8253c0, &phy->dtpr[1]); - else - writel(0x1a8363c0, &phy->dtpr[1]); - writel(0x5002c200, &phy->dtpr[2]); - writel(0x00000b51, &phy->mr0); - } else { - writel(0x999cbb66, &phy->dtpr[0]); - if (size == 1) - writel(0x1a82dbc0, &phy->dtpr[1]); - else - writel(0x1a878400, &phy->dtpr[1]); - writel(0xa00214f8, &phy->dtpr[2]); - writel(0x00000d71, &phy->mr0); - } - writel(0x00000006, &phy->mr1); - if (freq == 1333) - writel(0x00000290, &phy->mr2); - else - writel(0x00000298, &phy->mr2); - - writel(0x00000800, &phy->mr3); - - while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) - ; - - writel(0x0300C473, &phy->pgcr[1]); - writel(0x0000005D, &phy->zq[0].cr[1]); -} diff --git a/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c deleted file mode 100644 index d7ef16b10a1..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-pro4/early_clkrst_init.c" diff --git a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c b/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c deleted file mode 100644 index 293a6ab4234..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/pinctrl.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -void pin_init(void) -{ - u32 tmp; - - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(158, 0, 8, 4); /* XNFRE -> XNFRE_GB */ - sg_set_pinsel(159, 0, 8, 4); /* XNFWE -> XNFWE_GB */ - sg_set_pinsel(160, 0, 8, 4); /* XFALE -> NFALE_GB */ - sg_set_pinsel(161, 0, 8, 4); /* XFCLE -> NFCLE_GB */ - sg_set_pinsel(162, 0, 8, 4); /* XNFWP -> XFNWP_GB */ - sg_set_pinsel(163, 0, 8, 4); /* XNFCE0 -> XNFCE0_GB */ - sg_set_pinsel(164, 0, 8, 4); /* NANDRYBY0 -> NANDRYBY0_GB */ - sg_set_pinsel(22, 0, 8, 4); /* MMCCLK -> XFNCE1_GB */ - sg_set_pinsel(23, 0, 8, 4); /* MMCCMD -> NANDRYBY1_GB */ - sg_set_pinsel(24, 0, 8, 4); /* MMCDAT0 -> NFD0_GB */ - sg_set_pinsel(25, 0, 8, 4); /* MMCDAT1 -> NFD1_GB */ - sg_set_pinsel(26, 0, 8, 4); /* MMCDAT2 -> NFD2_GB */ - sg_set_pinsel(27, 0, 8, 4); /* MMCDAT3 -> NFD3_GB */ - sg_set_pinsel(28, 0, 8, 4); /* MMCDAT4 -> NFD4_GB */ - sg_set_pinsel(29, 0, 8, 4); /* MMCDAT5 -> NFD5_GB */ - sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */ - sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */ -#endif - -#ifdef CONFIG_USB_EHCI_UNIPHIER - sg_set_pinsel(53, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(54, 0, 8, 4); /* USB0OD -> USB0OD */ - sg_set_pinsel(55, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(56, 0, 8, 4); /* USB1OD -> USB1OD */ - /* sg_set_pinsel(67, 23, 8, 4); */ /* PCOE -> USB2VBUS */ - /* sg_set_pinsel(68, 23, 8, 4); */ /* PCWAIT -> USB2OD */ -#endif - - tmp = readl(SG_IECTRL); - tmp |= 0x41; - writel(tmp, SG_IECTRL); -} diff --git a/arch/arm/mach-uniphier/ph1-ld4/pll_init.c b/arch/arm/mach-uniphier/ph1-ld4/pll_init.c deleted file mode 100644 index f8ec2b61fb4..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/pll_init.c +++ /dev/null @@ -1,189 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#undef DPLL_SSC_RATE_1PER - -static void dpll_init(void) -{ - u32 tmp; - - /* - * Set Frequency - * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) - * to FOUT (DPLLCTRL.bit[29:20]) - */ - tmp = readl(SC_DPLLCTRL); - tmp &= ~0x000f0000; -#if CONFIG_DDR_FREQ == 1600 - tmp |= 0x000c0000; -#elif CONFIG_DDR_FREQ == 1333 - tmp |= 0x000d0000; -#else -# error "Unknown frequency" -#endif - -#if defined(DPLL_SSC_RATE_1PER) - tmp &= ~SC_DPLLCTRL_SSC_RATE; -#else - tmp |= SC_DPLLCTRL_SSC_RATE; -#endif - writel(tmp, SC_DPLLCTRL); - - tmp = readl(SC_DPLLCTRL2); - tmp |= SC_DPLLCTRL2_NRSTDS; - writel(tmp, SC_DPLLCTRL2); -} - -static void upll_init(void) -{ - u32 tmp, clk_mode_upll, clk_mode_axosel; - - tmp = readl(SG_PINMON0); - clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; - clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; - - /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ - tmp = readl(SC_UPLLCTRL); - tmp &= ~0x18000000; - writel(tmp, SC_UPLLCTRL); - - if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { - if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || - clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { - /* AXO: 25MHz */ - tmp &= ~0x07ffffff; - tmp |= 0x0228f5c0; - } else { - /* AXO: default 24.576MHz */ - tmp &= ~0x07ffffff; - tmp |= 0x02328000; - } - } - - writel(tmp, SC_UPLLCTRL); - - /* set 1 to K_LD(UPLLCTRL.bit[27]) */ - tmp |= 0x08000000; - writel(tmp, SC_UPLLCTRL); - - /* wait 10 usec */ - udelay(10); - - /* set 1 to SNRT(UPLLCTRL.bit[28]) */ - tmp |= 0x10000000; - writel(tmp, SC_UPLLCTRL); -} - -static void vpll_init(void) -{ - u32 tmp, clk_mode_axosel; - - tmp = readl(SG_PINMON0); - clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; - - /* set 1 to VPLA27WP and VPLA27WP */ - tmp = readl(SC_VPLL27ACTRL); - tmp |= 0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); - tmp |= 0x00000001; - writel(tmp, SC_VPLL27BCTRL); - - /* Set 0 to VPLA_K_LD and VPLB_K_LD */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL3); - - /* Set 0 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL2); - - /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp &= ~0x0000007f; - tmp |= 0x00000020; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp &= ~0x0000007f; - tmp |= 0x00000020; - writel(tmp, SC_VPLL27BCTRL2); - - if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || - clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { - /* AXO: 25MHz */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x000fffff; - tmp |= 0x00066664; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x000fffff; - tmp |= 0x00066664; - writel(tmp, SC_VPLL27BCTRL3); - } else { - /* AXO: default 24.576MHz */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x000fffff; - tmp |= 0x000f5800; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x000fffff; - tmp |= 0x000f5800; - writel(tmp, SC_VPLL27BCTRL3); - } - - /* Set 1 to VPLA_K_LD and VPLB_K_LD */ - tmp = readl(SC_VPLL27ACTRL3); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL3); - - /* wait 10 usec */ - udelay(10); - - /* Set 0 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL2); - - /* set 0 to VPLA27WP and VPLA27WP */ - tmp = readl(SC_VPLL27ACTRL); - tmp &= ~0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); - tmp |= ~0x00000001; - writel(tmp, SC_VPLL27BCTRL); -} - -void pll_init(void) -{ - dpll_init(); - upll_init(); - vpll_init(); - - /* - * Wait 500 usec until dpll get stable - * We wait 10 usec in upll_init() and vpll_init() - * so 20 usec can be saved here. - */ - udelay(480); -} diff --git a/arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c deleted file mode 100644 index 837b2a891b7..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-pro4/pll_spectrum.c" diff --git a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c b/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c deleted file mode 100644 index 4435a47e73c..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/sbc_init.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void sbc_init(void) -{ - u32 tmp; - - /* system bus output enable */ - tmp = readl(PC0CTRL); - tmp &= 0xfffffcff; - writel(tmp, PC0CTRL); - - /* - * Only CS1 is connected to support card. - * BKSZ[1:0] should be set to "01". - */ - writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); - writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); - writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); - writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); - - if (boot_is_swapped()) { - /* - * Boot Swap On: boot from external NOR/SRAM - * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. - * - * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank - * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals - */ - writel(0x0000bc01, SBBASE0); - } else { - /* - * Boot Swap Off: boot from mask ROM - * 0x40000000-0x41ffffff: mask ROM - * 0x42000000-0x43efffff: memory bank (31MB) - * 0x43f00000-0x43ffffff: peripherals (1MB) - */ - writel(0x0000be01, SBBASE0); /* dummy */ - writel(0x0200be01, SBBASE1); - } -} diff --git a/arch/arm/mach-uniphier/ph1-ld4/umc_init.c b/arch/arm/mach-uniphier/ph1-ld4/umc_init.c deleted file mode 100644 index a7a4157e793..00000000000 --- a/arch/arm/mach-uniphier/ph1-ld4/umc_init.c +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static void umc_start_ssif(void __iomem *ssif_base) -{ - writel(0x00000000, ssif_base + 0x0000b004); - writel(0xffffffff, ssif_base + 0x0000c004); - writel(0x000fffcf, ssif_base + 0x0000c008); - writel(0x00000001, ssif_base + 0x0000b000); - writel(0x00000001, ssif_base + 0x0000c000); - writel(0x03010101, ssif_base + UMC_MDMCHSEL); - writel(0x03010100, ssif_base + UMC_DMDCHSEL); - - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); - - writel(0x00000001, ssif_base + UMC_CPURST); - writel(0x00000001, ssif_base + UMC_IDSRST); - writel(0x00000001, ssif_base + UMC_IXMRST); - writel(0x00000001, ssif_base + UMC_MDMRST); - writel(0x00000001, ssif_base + UMC_MDDRST); - writel(0x00000001, ssif_base + UMC_SIORST); - writel(0x00000001, ssif_base + UMC_VIORST); - writel(0x00000001, ssif_base + UMC_FRCRST); - writel(0x00000001, ssif_base + UMC_RGLRST); - writel(0x00000001, ssif_base + UMC_AIORST); - writel(0x00000001, ssif_base + UMC_DMDRST); -} - -static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) -{ - if (freq == 1333) { - writel(0x45990b11, dramcont + UMC_CMDCTLA); - writel(0x16958924, dramcont + UMC_CMDCTLB); - writel(0x5101046A, dramcont + UMC_INITCTLA); - - if (size == 1) - writel(0x27028B0A, dramcont + UMC_INITCTLB); - else if (size == 2) - writel(0x38028B0A, dramcont + UMC_INITCTLB); - - writel(0x000FF0FF, dramcont + UMC_INITCTLC); - writel(0x00000b51, dramcont + UMC_DRMMR0); - } else if (freq == 1600) { - writel(0x36BB0F17, dramcont + UMC_CMDCTLA); - writel(0x18C6AA24, dramcont + UMC_CMDCTLB); - writel(0x5101387F, dramcont + UMC_INITCTLA); - - if (size == 1) - writel(0x2F030D3F, dramcont + UMC_INITCTLB); - else if (size == 2) - writel(0x43030D3F, dramcont + UMC_INITCTLB); - - writel(0x00FF00FF, dramcont + UMC_INITCTLC); - writel(0x00000d71, dramcont + UMC_DRMMR0); - } - - writel(0x00000006, dramcont + UMC_DRMMR1); - - if (freq == 1333) - writel(0x00000290, dramcont + UMC_DRMMR2); - else if (freq == 1600) - writel(0x00000298, dramcont + UMC_DRMMR2); - - writel(0x00000800, dramcont + UMC_DRMMR3); - - if (freq == 1333) { - if (size == 1) - writel(0x00240512, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x00350512, dramcont + UMC_SPCCTLA); - - writel(0x00ff0006, dramcont + UMC_SPCCTLB); - writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); - } else if (freq == 1600) { - if (size == 1) - writel(0x002B0617, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x003F0617, dramcont + UMC_SPCCTLA); - - writel(0x00ff0008, dramcont + UMC_SPCCTLB); - writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); - } - - writel(0x04060806, dramcont + UMC_WDATACTL_D0); - writel(0x04a02000, dramcont + UMC_DATASET); - writel(0x00000000, ca_base + 0x2300); - writel(0x00400020, dramcont + UMC_DCCGCTL); - writel(0x00000003, dramcont + 0x7000); - writel(0x0000000f, dramcont + 0x8000); - writel(0x000000c3, dramcont + 0x8004); - writel(0x00000071, dramcont + 0x8008); - writel(0x0000003b, dramcont + UMC_DICGCTLA); - writel(0x020a0808, dramcont + UMC_DICGCTLB); - writel(0x00000004, dramcont + UMC_FLOWCTLG); - writel(0x80000201, ca_base + 0xc20); - writel(0x0801e01e, dramcont + UMC_FLOWCTLA); - writel(0x00200000, dramcont + UMC_FLOWCTLB); - writel(0x00004444, dramcont + UMC_FLOWCTLC); - writel(0x200a0a00, dramcont + UMC_SPCSETB); - writel(0x00000000, dramcont + UMC_SPCSETD); - writel(0x00000520, dramcont + UMC_DFICUPDCTLA); -} - -static int umc_init_sub(int freq, int size_ch0, int size_ch1) -{ - void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; - void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); - void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); - void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); - void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); - void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); - void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); - - umc_dram_init_start(dramcont0); - umc_dram_init_start(dramcont1); - umc_dram_init_poll(dramcont0); - umc_dram_init_poll(dramcont1); - - writel(0x00000101, dramcont0 + UMC_DIOCTLA); - - ddrphy_init(phy0_0, freq, size_ch0); - - ddrphy_prepare_training(phy0_0, 0); - ddrphy_training(phy0_0); - - writel(0x00000101, dramcont1 + UMC_DIOCTLA); - - ddrphy_init(phy1_0, freq, size_ch1); - - ddrphy_prepare_training(phy1_0, 1); - ddrphy_training(phy1_0); - - umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); - - umc_start_ssif(ssif_base); - - return 0; -} - -int umc_init(void) -{ - return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, - CONFIG_SDRAM1_SIZE / 0x08000000); -} - -#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ - (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ - CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 -/* OK */ -#else -#error Unsupported DDR configuration. -#endif diff --git a/arch/arm/mach-uniphier/ph1-pro4/Makefile b/arch/arm/mach-uniphier/ph1-pro4/Makefile deleted file mode 100644 index e8b2c9e8ac2..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-y += pll_init.o early_clkrst_init.o \ - pll_spectrum.o umc_init.o ddrphy_init.o -obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o -else -obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -endif - -obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-pro4/boot-mode.c b/arch/arm/mach-uniphier/ph1-pro4/boot-mode.c deleted file mode 100644 index 54a2510b97f..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/boot-mode.c +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -struct boot_device_info boot_device_table[] = { - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_MMC1, "eMMC Boot (3.3V)"}, - {BOOT_DEVICE_MMC1, "eMMC Boot (1.8V)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - { /* sentinel */ } -}; - -int get_boot_mode_sel(void) -{ - return (readl(SG_PINMON0) >> 1) & 0x1f; -} - -u32 spl_boot_device(void) -{ - int boot_mode; - - if (boot_is_swapped()) - return BOOT_DEVICE_NOR; - - boot_mode = get_boot_mode_sel(); - - return boot_device_table[boot_mode].type; -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c b/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c deleted file mode 100644 index 46cace77e54..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -void clkrst_init(void) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(SC_RSTCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER - tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 | - SC_RSTCTRL_NRST_GIO; -#endif -#ifdef CONFIG_UNIPHIER_ETH - tmp |= SC_RSTCTRL_NRST_ETHER; -#endif -#ifdef CONFIG_USB_EHCI_UNIPHIER - tmp |= SC_RSTCTRL_NRST_STDMAC; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_RSTCTRL_NRST_NAND; -#endif - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ - -#ifdef CONFIG_USB_XHCI_UNIPHIER - tmp = readl(SC_RSTCTRL2); - tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1; - writel(tmp, SC_RSTCTRL2); - readl(SC_RSTCTRL2); /* dummy read */ -#endif - - /* privide clocks */ - tmp = readl(SC_CLKCTRL); -#ifdef CONFIG_USB_XHCI_UNIPHIER - tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | - SC_CLKCTRL_CEN_GIO; -#endif -#ifdef CONFIG_UNIPHIER_ETH - tmp |= SC_CLKCTRL_CEN_ETHER; -#endif -#ifdef CONFIG_USB_EHCI_UNIPHIER - tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC; -#endif -#ifdef CONFIG_NAND_DENALI - tmp |= SC_CLKCTRL_CEN_NAND; -#endif - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c b/arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c deleted file mode 100644 index 61ddcf4ec63..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) -{ - u32 tmp; - - writel(0x0300c473, &phy->pgcr[1]); - if (freq == 1333) { - writel(0x0a806844, &phy->ptr[0]); - writel(0x208e0124, &phy->ptr[1]); - } else { - writel(0x0c807d04, &phy->ptr[0]); - writel(0x2710015E, &phy->ptr[1]); - } - writel(0x00083DEF, &phy->ptr[2]); - if (freq == 1333) { - writel(0x0f051616, &phy->ptr[3]); - writel(0x06ae08d6, &phy->ptr[4]); - } else { - writel(0x12061A80, &phy->ptr[3]); - writel(0x08027100, &phy->ptr[4]); - } - writel(0xF004001A, &phy->dsgcr); - - /* change the value of the on-die pull-up/pull-down registors */ - tmp = readl(&phy->dxccr); - tmp &= ~0x0ee0; - tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; - writel(tmp, &phy->dxccr); - - writel(0x0000040B, &phy->dcr); - if (freq == 1333) { - writel(0x85589955, &phy->dtpr[0]); - if (size == 1) - writel(0x1a8363c0, &phy->dtpr[1]); - else - writel(0x1a8363c0, &phy->dtpr[1]); - writel(0x5002c200, &phy->dtpr[2]); - writel(0x00000b51, &phy->mr0); - } else { - writel(0x999cbb66, &phy->dtpr[0]); - if (size == 1) - writel(0x1a878400, &phy->dtpr[1]); - else - writel(0x1a878400, &phy->dtpr[1]); - writel(0xa00214f8, &phy->dtpr[2]); - writel(0x00000d71, &phy->mr0); - } - writel(0x00000006, &phy->mr1); - if (freq == 1333) - writel(0x00000290, &phy->mr2); - else - writel(0x00000298, &phy->mr2); - - writel(0x00000000, &phy->mr3); - - while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) - ; - - writel(0x0300C473, &phy->pgcr[1]); - writel(0x0000005D, &phy->zq[0].cr[1]); -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c deleted file mode 100644 index 60204b53ba5..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void early_clkrst_init(void) -{ - u32 tmp; - - /* deassert reset */ - tmp = readl(SC_RSTCTRL); - - tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0; - if (spl_boot_device() != BOOT_DEVICE_NAND) - tmp &= ~SC_RSTCTRL_NRST_NAND; - writel(tmp, SC_RSTCTRL); - readl(SC_RSTCTRL); /* dummy read */ - - /* privide clocks */ - tmp = readl(SC_CLKCTRL); - tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI; - writel(tmp, SC_CLKCTRL); - readl(SC_CLKCTRL); /* dummy read */ -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c b/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c deleted file mode 100644 index bfaff4fea9a..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/pinctrl.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -void pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(40, 0, 4, 8); /* NFD0 -> NFD0 */ - sg_set_pinsel(41, 0, 4, 8); /* NFD1 -> NFD1 */ - sg_set_pinsel(42, 0, 4, 8); /* NFD2 -> NFD2 */ - sg_set_pinsel(43, 0, 4, 8); /* NFD3 -> NFD3 */ - sg_set_pinsel(44, 0, 4, 8); /* NFD4 -> NFD4 */ - sg_set_pinsel(45, 0, 4, 8); /* NFD5 -> NFD5 */ - sg_set_pinsel(46, 0, 4, 8); /* NFD6 -> NFD6 */ - sg_set_pinsel(47, 0, 4, 8); /* NFD7 -> NFD7 */ - sg_set_pinsel(48, 0, 4, 8); /* NFALE -> NFALE */ - sg_set_pinsel(49, 0, 4, 8); /* NFCLE -> NFCLE */ - sg_set_pinsel(50, 0, 4, 8); /* XNFRE -> XNFRE */ - sg_set_pinsel(51, 0, 4, 8); /* XNFWE -> XNFWE */ - sg_set_pinsel(52, 0, 4, 8); /* XNFWP -> XNFWP */ - sg_set_pinsel(53, 0, 4, 8); /* XNFCE0 -> XNFCE0 */ - sg_set_pinsel(54, 0, 4, 8); /* NRYBY0 -> NRYBY0 */ - /* sg_set_pinsel(131, 1, 4, 8); */ /* RXD2 -> NRYBY1 */ - /* sg_set_pinsel(132, 1, 4, 8); */ /* TXD2 -> XNFCE1 */ -#endif - -#ifdef CONFIG_USB_XHCI_UNIPHIER - sg_set_pinsel(180, 0, 4, 8); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(181, 0, 4, 8); /* USB0OD -> USB0OD */ - sg_set_pinsel(182, 0, 4, 8); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */ -#endif - -#ifdef CONFIG_USB_EHCI_UNIPHIER - sg_set_pinsel(184, 0, 4, 8); /* USB2VBUS -> USB2VBUS */ - sg_set_pinsel(185, 0, 4, 8); /* USB2OD -> USB2OD */ - sg_set_pinsel(187, 0, 4, 8); /* USB3VBUS -> USB3VBUS */ - sg_set_pinsel(188, 0, 4, 8); /* USB3OD -> USB3OD */ -#endif - - writel(1, SG_LOADPINCTRL); -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/pll_init.c b/arch/arm/mach-uniphier/ph1-pro4/pll_init.c deleted file mode 100644 index 8ae8ed65b87..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/pll_init.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#undef DPLL_SSC_RATE_1PER - -static void dpll_init(void) -{ - u32 tmp; - - /* - * Set Frequency - * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) - * to FOUT ( DPLLCTRL.bit[29:20] ) - */ - tmp = readl(SC_DPLLCTRL); - tmp &= ~(0x000f0000); -#if CONFIG_DDR_FREQ == 1600 - tmp |= 0x000c0000; -#elif CONFIG_DDR_FREQ == 1333 - tmp |= 0x000d0000; -#else -# error "Unsupported frequency" -#endif - - /* - * Set Moduration rate - * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15]) - */ -#if defined(DPLL_SSC_RATE_1PER) - tmp &= ~0x00008000; -#else - tmp |= 0x00008000; -#endif - writel(tmp, SC_DPLLCTRL); - - tmp = readl(SC_DPLLCTRL2); - tmp |= SC_DPLLCTRL2_NRSTDS; - writel(tmp, SC_DPLLCTRL2); -} - -static void vpll_init(void) -{ - u32 tmp, clk_mode_axosel; - - /* Set VPLL27A & VPLL27B */ - tmp = readl(SG_PINMON0); - clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; - - /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */ - if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || - clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) - return; - - /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ - tmp = readl(SC_VPLL27ACTRL); - tmp |= 0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); - tmp |= 0x00000001; - writel(tmp, SC_VPLL27BCTRL); - - /* Unset VPLA_K_LD and VPLB_K_LD bit */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL3); - - /* Set VPLA_M and VPLB_M to 0x20 */ - tmp = readl(SC_VPLL27ACTRL2); - tmp &= ~0x0000007f; - tmp |= 0x00000020; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp &= ~0x0000007f; - tmp |= 0x00000020; - writel(tmp, SC_VPLL27BCTRL2); - - if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || - clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) { - /* Set VPLA_K and VPLB_K for AXO: 25MHz */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x000fffff; - tmp |= 0x00066666; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x000fffff; - tmp |= 0x00066666; - writel(tmp, SC_VPLL27BCTRL3); - } else { - /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x000fffff; - tmp |= 0x000f5800; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x000fffff; - tmp |= 0x000f5800; - writel(tmp, SC_VPLL27BCTRL3); - } - - /* wait 1 usec */ - udelay(1); - - /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */ - tmp = readl(SC_VPLL27ACTRL3); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL3); - - /* Unset VPLA_SNRST and VPLB_SNRST bit */ - tmp = readl(SC_VPLL27ACTRL2); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL2); - - /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ - tmp = readl(SC_VPLL27ACTRL); - tmp &= ~0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); - tmp &= ~0x00000001; - writel(tmp, SC_VPLL27BCTRL); -} - -void pll_init(void) -{ - dpll_init(); - vpll_init(); - - /* - * Wait 500 usec until dpll get stable - * We wait 1 usec in vpll_init() so 1 usec can be saved here. - */ - udelay(499); -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c deleted file mode 100644 index fcf2ad282a7..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -void enable_dpll_ssc(void) -{ - u32 tmp; - - tmp = readl(SC_DPLLCTRL); - tmp |= SC_DPLLCTRL_SSC_EN; - writel(tmp, SC_DPLLCTRL); -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c b/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c deleted file mode 100644 index 685f9c736c9..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/sbc_init.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void sbc_init(void) -{ - /* - * Only CS1 is connected to support card. - * BKSZ[1:0] should be set to "01". - */ - writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); - writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); - writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); - writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); - - if (boot_is_swapped()) { - /* - * Boot Swap On: boot from external NOR/SRAM - * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. - * - * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank - * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals - */ - writel(0x0000bc01, SBBASE0); - } else { - /* - * Boot Swap Off: boot from mask ROM - * 0x40000000-0x41ffffff: mask ROM - * 0x42000000-0x43efffff: memory bank (31MB) - * 0x43f00000-0x43ffffff: peripherals (1MB) - */ - writel(0x0000be01, SBBASE0); /* dummy */ - writel(0x0200be01, SBBASE1); - } -} diff --git a/arch/arm/mach-uniphier/ph1-pro4/umc_init.c b/arch/arm/mach-uniphier/ph1-pro4/umc_init.c deleted file mode 100644 index bd8b9d83b2b..00000000000 --- a/arch/arm/mach-uniphier/ph1-pro4/umc_init.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static void umc_start_ssif(void __iomem *ssif_base) -{ - writel(0x00000001, ssif_base + 0x0000b004); - writel(0xffffffff, ssif_base + 0x0000c004); - writel(0x07ffffff, ssif_base + 0x0000c008); - writel(0x00000001, ssif_base + 0x0000b000); - writel(0x00000001, ssif_base + 0x0000c000); - - writel(0x03010100, ssif_base + UMC_HDMCHSEL); - writel(0x03010101, ssif_base + UMC_MDMCHSEL); - writel(0x03010100, ssif_base + UMC_DVCCHSEL); - writel(0x03010100, ssif_base + UMC_DMDCHSEL); - - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); - writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */ - - writel(0x00000001, ssif_base + UMC_CPURST); - writel(0x00000001, ssif_base + UMC_IDSRST); - writel(0x00000001, ssif_base + UMC_IXMRST); - writel(0x00000001, ssif_base + UMC_HDMRST); - writel(0x00000001, ssif_base + UMC_MDMRST); - writel(0x00000001, ssif_base + UMC_HDDRST); - writel(0x00000001, ssif_base + UMC_MDDRST); - writel(0x00000001, ssif_base + UMC_SIORST); - writel(0x00000001, ssif_base + UMC_GIORST); - writel(0x00000001, ssif_base + UMC_HD2RST); - writel(0x00000001, ssif_base + UMC_VIORST); - writel(0x00000001, ssif_base + UMC_DVCRST); - writel(0x00000001, ssif_base + UMC_RGLRST); - writel(0x00000001, ssif_base + UMC_VPERST); - writel(0x00000001, ssif_base + UMC_AIORST); - writel(0x00000001, ssif_base + UMC_DMDRST); -} - -static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) -{ - writel(0x66bb0f17, dramcont + UMC_CMDCTLA); - writel(0x18c6aa44, dramcont + UMC_CMDCTLB); - writel(0x5101387f, dramcont + UMC_INITCTLA); - writel(0x43030d3f, dramcont + UMC_INITCTLB); - writel(0x00ff00ff, dramcont + UMC_INITCTLC); - writel(0x00000d71, dramcont + UMC_DRMMR0); - writel(0x00000006, dramcont + UMC_DRMMR1); - writel(0x00000298, dramcont + UMC_DRMMR2); - writel(0x00000000, dramcont + UMC_DRMMR3); - writel(0x003f0617, dramcont + UMC_SPCCTLA); - writel(0x00ff0008, dramcont + UMC_SPCCTLB); - writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); - writel(0x000c00ae, dramcont + UMC_RDATACTL_D1); - writel(0x04060802, dramcont + UMC_WDATACTL_D0); - writel(0x04060802, dramcont + UMC_WDATACTL_D1); - writel(0x04a02000, dramcont + UMC_DATASET); - writel(0x00000000, ca_base + 0x2300); - writel(0x00400020, dramcont + UMC_DCCGCTL); - writel(0x0000000f, dramcont + 0x7000); - writel(0x0000000f, dramcont + 0x8000); - writel(0x000000c3, dramcont + 0x8004); - writel(0x00000071, dramcont + 0x8008); - writel(0x00000004, dramcont + UMC_FLOWCTLG); - writel(0x00000000, dramcont + 0x0060); - writel(0x80000201, ca_base + 0xc20); - writel(0x0801e01e, dramcont + UMC_FLOWCTLA); - writel(0x00200000, dramcont + UMC_FLOWCTLB); - writel(0x00004444, dramcont + UMC_FLOWCTLC); - writel(0x200a0a00, dramcont + UMC_SPCSETB); - writel(0x00010000, dramcont + UMC_SPCSETD); - writel(0x80000020, dramcont + UMC_DFICUPDCTLA); -} - -static int umc_init_sub(int freq, int size_ch0, int size_ch1) -{ - void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; - void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); - void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); - void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); - void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); - void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); - void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1); - void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); - void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1); - - umc_dram_init_start(dramcont0); - umc_dram_init_start(dramcont1); - umc_dram_init_poll(dramcont0); - umc_dram_init_poll(dramcont1); - - writel(0x00000101, dramcont0 + UMC_DIOCTLA); - - ddrphy_init(phy0_0, freq, size_ch0); - - ddrphy_prepare_training(phy0_0, 0); - ddrphy_training(phy0_0); - - writel(0x00000103, dramcont0 + UMC_DIOCTLA); - - ddrphy_init(phy0_1, freq, size_ch0); - - ddrphy_prepare_training(phy0_1, 1); - ddrphy_training(phy0_1); - - writel(0x00000101, dramcont1 + UMC_DIOCTLA); - - ddrphy_init(phy1_0, freq, size_ch1); - - ddrphy_prepare_training(phy1_0, 0); - ddrphy_training(phy1_0); - - writel(0x00000103, dramcont1 + UMC_DIOCTLA); - - ddrphy_init(phy1_1, freq, size_ch1); - - ddrphy_prepare_training(phy1_1, 1); - ddrphy_training(phy1_1); - - umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); - - umc_start_ssif(ssif_base); - - return 0; -} - -int umc_init(void) -{ - return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, - CONFIG_SDRAM1_SIZE / 0x08000000); -} - -#if ((CONFIG_SDRAM0_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH0 == 2) || \ - (CONFIG_SDRAM0_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH0 == 1)) && \ - ((CONFIG_SDRAM1_SIZE == 0x20000000 && CONFIG_DDR_NUM_CH1 == 2) || \ - (CONFIG_SDRAM1_SIZE == 0x10000000 && CONFIG_DDR_NUM_CH1 == 1)) -/* OK */ -#else - #error Unsupported DDR configuration. -#endif diff --git a/arch/arm/mach-uniphier/ph1-sld3/Makefile b/arch/arm/mach-uniphier/ph1-sld3/Makefile deleted file mode 100644 index 48a3756c1d0..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -ifdef CONFIG_SPL_BUILD -obj-y += bcu_init.o memconf.o sg_init.o pll_init.o early_clkrst_init.o \ - early_pinctrl.o pll_spectrum.o umc_init.o -obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc_init.o -else -obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o -endif - -obj-y += boot-mode.o diff --git a/arch/arm/mach-uniphier/ph1-sld3/bcu_init.c b/arch/arm/mach-uniphier/ph1-sld3/bcu_init.c deleted file mode 100644 index ccc6897d0ad..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/bcu_init.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x)) - -void bcu_init(void) -{ - int shift; - - writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */ - writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */ - /* - * 0xe0000000-0xefffffff: Ex-bus - * 0xf0000000-0xfbffffff: ASM bus - * 0xfc000000-0xffffffff: OCM bus - */ - writel(0x24440000, BCSCR5); - - /* Specify DDR channel */ - shift = (CONFIG_SDRAM1_BASE - CONFIG_SDRAM0_BASE) / 0x04000000 * 4; - writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ - - shift -= 32; - writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ - - shift -= 32; - writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/boot-mode.c b/arch/arm/mach-uniphier/ph1-sld3/boot-mode.c deleted file mode 100644 index 40000afe741..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/boot-mode.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -struct boot_device_info boot_device_table[] = { - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "External Master"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize 1MB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize 1MB, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI, Addr 5)"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - {BOOT_DEVICE_NONE, "Reserved"}, - { /* sentinel */ } -}; - -int get_boot_mode_sel(void) -{ - return readl(SG_PINMON0) & 0x3f; -} - -u32 spl_boot_device(void) -{ - int boot_mode; - - if (boot_is_swapped()) - return BOOT_DEVICE_NOR; - - boot_mode = get_boot_mode_sel(); - - return boot_device_table[boot_mode].type; -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c deleted file mode 100644 index 3a3dab7a153..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/clkrst_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-pro4/clkrst_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c deleted file mode 100644 index d7ef16b10a1..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/early_clkrst_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-pro4/early_clkrst_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c b/arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c deleted file mode 100644 index f6ceef5f1c0..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/early_pinctrl.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -void early_pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_UNIPHIER_SERIAL - sg_set_pinsel(63, 0, 4, 4); /* RXD0 */ - sg_set_pinsel(64, 1, 4, 4); /* TXD0 */ - - sg_set_pinsel(65, 0, 4, 4); /* RXD1 */ - sg_set_pinsel(66, 1, 4, 4); /* TXD1 */ - - sg_set_pinsel(96, 2, 4, 4); /* RXD2 */ - sg_set_pinsel(102, 2, 4, 4); /* TXD2 */ -#endif -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/memconf.c b/arch/arm/mach-uniphier/ph1-sld3/memconf.c deleted file mode 100644 index 553a9e33844..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/memconf.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static inline u32 sg_memconf_val_ch2(unsigned long size, int num) -{ - int size_mb = size / num; - u32 ret; - - switch (size_mb) { - case SZ_64M: - ret = SG_MEMCONF_CH2_SZ_64M; - break; - case SZ_128M: - ret = SG_MEMCONF_CH2_SZ_128M; - break; - case SZ_256M: - ret = SG_MEMCONF_CH2_SZ_256M; - break; - case SZ_512M: - ret = SG_MEMCONF_CH2_SZ_512M; - break; - default: - BUG(); - break; - } - - switch (num) { - case 1: - ret |= SG_MEMCONF_CH2_NUM_1; - break; - case 2: - ret |= SG_MEMCONF_CH2_NUM_2; - break; - default: - BUG(); - break; - } - return ret; -} - -u32 memconf_additional_val(void) -{ - return sg_memconf_val_ch2(CONFIG_SDRAM2_SIZE, CONFIG_DDR_NUM_CH2); -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld3/pinctrl.c deleted file mode 100644 index dea938ed2fa..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/pinctrl.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -void pin_init(void) -{ -#ifdef CONFIG_USB_EHCI_UNIPHIER - sg_set_pinsel(13, 0, 4, 4); /* USB0OC */ - sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */ - - sg_set_pinsel(15, 0, 4, 4); /* USB1OC */ - sg_set_pinsel(16, 1, 4, 4); /* USB1VBUS */ - - sg_set_pinsel(17, 0, 4, 4); /* USB2OC */ - sg_set_pinsel(18, 1, 4, 4); /* USB2VBUS */ - - sg_set_pinsel(19, 0, 4, 4); /* USB3OC */ - sg_set_pinsel(20, 1, 4, 4); /* USB3VBUS */ -#endif -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/pll_init.c b/arch/arm/mach-uniphier/ph1-sld3/pll_init.c deleted file mode 100644 index ebd1c310b7a..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/pll_init.c +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -void pll_init(void) -{ - /* add pll init code here */ -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c deleted file mode 100644 index fcf2ad282a7..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/pll_spectrum.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -void enable_dpll_ssc(void) -{ - u32 tmp; - - tmp = readl(SC_DPLLCTRL); - tmp |= SC_DPLLCTRL_SSC_EN; - writel(tmp, SC_DPLLCTRL); -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c deleted file mode 100644 index 3e62121ba95..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/sbc_init.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void sbc_init(void) -{ - /* only address/data multiplex mode is supported */ - - /* - * Only CS1 is connected to support card. - * BKSZ[1:0] should be set to "01". - */ - writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10); - writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11); - writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); - - if (boot_is_swapped()) { - /* - * Boot Swap On: boot from external NOR/SRAM - * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. - * - * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank - * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals - */ - writel(0x0000bc01, SBBASE0); - } else { - /* - * Boot Swap Off: boot from mask ROM - * 0x40000000-0x41ffffff: mask ROM - * 0x42000000-0x43efffff: memory bank (31MB) - * 0x43f00000-0x43ffffff: peripherals (1MB) - */ - writel(0x0000be01, SBBASE0); /* dummy */ - writel(0x0200be01, SBBASE1); - } - - sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */ -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/sg_init.c b/arch/arm/mach-uniphier/ph1-sld3/sg_init.c deleted file mode 100644 index ca3cb9c6b8e..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/sg_init.c +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -void sg_init(void) -{ -} diff --git a/arch/arm/mach-uniphier/ph1-sld3/umc_init.c b/arch/arm/mach-uniphier/ph1-sld3/umc_init.c deleted file mode 100644 index 91ee3de2827..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld3/umc_init.c +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -int umc_init(void) -{ - /* add UMC init code here */ - printf("Implement memory init code\n"); - - return 0; -} diff --git a/arch/arm/mach-uniphier/ph1-sld8/Makefile b/arch/arm/mach-uniphier/ph1-sld8/Makefile deleted file mode 100644 index 8eb575e1d38..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/Makefile +++ /dev/null @@ -1 +0,0 @@ -include $(src)/../ph1-ld4/Makefile diff --git a/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c b/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c deleted file mode 100644 index 69b172e4e7b..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/bcu_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-ld4/bcu_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c b/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c deleted file mode 100644 index d359b562919..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/boot-mode.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-pro4/boot-mode.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c deleted file mode 100644 index 8d3435d6321..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/clkrst_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-ld4/clkrst_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c b/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c deleted file mode 100644 index 21efe62da6b..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/ddrphy_init.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright (C) 2014-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size) -{ - u32 tmp; - - writel(0x0300c473, &phy->pgcr[1]); - if (freq == 1333) { - writel(0x0a806844, &phy->ptr[0]); - writel(0x208e0124, &phy->ptr[1]); - } else { - writel(0x0c807d04, &phy->ptr[0]); - writel(0x2710015E, &phy->ptr[1]); - } - writel(0x00083DEF, &phy->ptr[2]); - if (freq == 1333) { - writel(0x0f051616, &phy->ptr[3]); - writel(0x06ae08d6, &phy->ptr[4]); - } else { - writel(0x12061A80, &phy->ptr[3]); - writel(0x08027100, &phy->ptr[4]); - } - writel(0xF004001A, &phy->dsgcr); - - /* change the value of the on-die pull-up/pull-down registors */ - tmp = readl(&phy->dxccr); - tmp &= ~0x0ee0; - tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM; - writel(tmp, &phy->dxccr); - - writel(0x0000040B, &phy->dcr); - if (freq == 1333) { - writel(0x85589955, &phy->dtpr[0]); - if (size == 1) - writel(0x1a8363c0, &phy->dtpr[1]); - else - writel(0x1a8363c0, &phy->dtpr[1]); - writel(0x5002c200, &phy->dtpr[2]); - writel(0x00000b51, &phy->mr0); - } else { - writel(0x999cbb66, &phy->dtpr[0]); - if (size == 1) - writel(0x1a878400, &phy->dtpr[1]); - else - writel(0x1a878400, &phy->dtpr[1]); - writel(0xa00214f8, &phy->dtpr[2]); - writel(0x00000d71, &phy->mr0); - } - writel(0x00000006, &phy->mr1); - if (freq == 1333) - writel(0x00000290, &phy->mr2); - else - writel(0x00000298, &phy->mr2); - -#ifdef CONFIG_DDR_STANDARD - writel(0x00000000, &phy->mr3); -#else - writel(0x00000800, &phy->mr3); -#endif - - while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE)) - ; - - writel(0x0300C473, &phy->pgcr[1]); - writel(0x0000005D, &phy->zq[0].cr[1]); -} diff --git a/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c b/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c deleted file mode 100644 index dd236b7e500..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/early_clkrst_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-ld4/early_clkrst_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c b/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c deleted file mode 100644 index 1b64414553b..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/pinctrl.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -void pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(15, 0, 8, 4); /* XNFRE_GB -> XNFRE_GB */ - sg_set_pinsel(16, 0, 8, 4); /* XNFWE_GB -> XNFWE_GB */ - sg_set_pinsel(17, 0, 8, 4); /* XFALE_GB -> NFALE_GB */ - sg_set_pinsel(18, 0, 8, 4); /* XFCLE_GB -> NFCLE_GB */ - sg_set_pinsel(19, 0, 8, 4); /* XNFWP_GB -> XFNWP_GB */ - sg_set_pinsel(20, 0, 8, 4); /* XNFCE0_GB -> XNFCE0_GB */ - sg_set_pinsel(21, 0, 8, 4); /* NANDRYBY0_GB -> NANDRYBY0_GB */ - sg_set_pinsel(22, 0, 8, 4); /* XFNCE1_GB -> XFNCE1_GB */ - sg_set_pinsel(23, 0, 8, 4); /* NANDRYBY1_GB -> NANDRYBY1_GB */ - sg_set_pinsel(24, 0, 8, 4); /* NFD0_GB -> NFD0_GB */ - sg_set_pinsel(25, 0, 8, 4); /* NFD1_GB -> NFD1_GB */ - sg_set_pinsel(26, 0, 8, 4); /* NFD2_GB -> NFD2_GB */ - sg_set_pinsel(27, 0, 8, 4); /* NFD3_GB -> NFD3_GB */ - sg_set_pinsel(28, 0, 8, 4); /* NFD4_GB -> NFD4_GB */ - sg_set_pinsel(29, 0, 8, 4); /* NFD5_GB -> NFD5_GB */ - sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */ - sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */ -#endif - -#ifdef CONFIG_USB_EHCI_UNIPHIER - sg_set_pinsel(41, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ - sg_set_pinsel(42, 0, 8, 4); /* USB0OD -> USB0OD */ - sg_set_pinsel(43, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ - sg_set_pinsel(44, 0, 8, 4); /* USB1OD -> USB1OD */ - /* sg_set_pinsel(114, 1, 8, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */ - /* sg_set_pinsel(115, 1, 8, 4); */ /* RXD1 -> USB2OD */ -#endif -} diff --git a/arch/arm/mach-uniphier/ph1-sld8/pll_init.c b/arch/arm/mach-uniphier/ph1-sld8/pll_init.c deleted file mode 100644 index 109cb5fee08..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/pll_init.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static void dpll_init(void) -{ - u32 tmp; - /* - * Set DPLL SSC parameters for DPLLCTRL3 - * [23] DIVN_TEST 0x1 - * [22:16] DIVN 0x50 - * [10] FREFSEL_TEST 0x1 - * [9:8] FREFSEL 0x2 - * [4] ICPD_TEST 0x1 - * [3:0] ICPD 0xb - */ - tmp = readl(SC_DPLLCTRL3); - tmp &= ~0x00ff0717; - tmp |= 0x00d0061b; - writel(tmp, SC_DPLLCTRL3); - - /* - * Set DPLL SSC parameters for DPLLCTRL - * <-1%> <-2%> - * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) - * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) - */ - tmp = readl(SC_DPLLCTRL); - tmp &= ~0x3ff07fff; -#ifdef CONFIG_DPLL_SSC_RATE_1PER - tmp |= 0x084018bf; -#else - tmp |= 0x084031a6; -#endif - writel(tmp, SC_DPLLCTRL); - - /* - * Set DPLL SSC parameters for DPLLCTRL2 - * [31:29] SSC_STEP 0 - * [27] SSC_REG_REF 1 - * [26:20] SSC_M 79 (0x4f) - * [19:0] SSC_K 964689 (0xeb851) - */ - tmp = readl(SC_DPLLCTRL2); - tmp &= ~0xefffffff; - tmp |= 0x0cfeb851; - writel(tmp, SC_DPLLCTRL2); -} - -static void upll_init(void) -{ - u32 tmp, clk_mode_upll, clk_mode_axosel; - - tmp = readl(SG_PINMON0); - clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; - clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; - - /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ - tmp = readl(SC_UPLLCTRL); - tmp &= ~0x18000000; - writel(tmp, SC_UPLLCTRL); - - if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { - if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || - clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { - /* AXO: 25MHz */ - tmp &= ~0x07ffffff; - tmp |= 0x0228f5c0; - } else { - /* AXO: default 24.576MHz */ - tmp &= ~0x07ffffff; - tmp |= 0x02328000; - } - } - - writel(tmp, SC_UPLLCTRL); - - /* set 1 to K_LD(UPLLCTRL.bit[27]) */ - tmp |= 0x08000000; - writel(tmp, SC_UPLLCTRL); - - /* wait 10 usec */ - udelay(10); - - /* set 1 to SNRT(UPLLCTRL.bit[28]) */ - tmp |= 0x10000000; - writel(tmp, SC_UPLLCTRL); -} - -static void vpll_init(void) -{ - u32 tmp, clk_mode_axosel; - - tmp = readl(SG_PINMON0); - clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; - - /* set 1 to VPLA27WP and VPLA27WP */ - tmp = readl(SC_VPLL27ACTRL); - tmp |= 0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); - tmp |= 0x00000001; - writel(tmp, SC_VPLL27BCTRL); - - /* Set 0 to VPLA_K_LD and VPLB_K_LD */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL3); - - /* Set 0 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp &= ~0x10000000; - writel(tmp, SC_VPLL27BCTRL2); - - /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp &= ~0x0000007f; - tmp |= 0x00000020; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp &= ~0x0000007f; - tmp |= 0x00000020; - writel(tmp, SC_VPLL27BCTRL2); - - if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || - clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { - /* AXO: 25MHz */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x000fffff; - tmp |= 0x00066664; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x000fffff; - tmp |= 0x00066664; - writel(tmp, SC_VPLL27BCTRL3); - } else { - /* AXO: default 24.576MHz */ - tmp = readl(SC_VPLL27ACTRL3); - tmp &= ~0x000fffff; - tmp |= 0x000f5800; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp &= ~0x000fffff; - tmp |= 0x000f5800; - writel(tmp, SC_VPLL27BCTRL3); - } - - /* Set 1 to VPLA_K_LD and VPLB_K_LD */ - tmp = readl(SC_VPLL27ACTRL3); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL3); - tmp = readl(SC_VPLL27BCTRL3); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL3); - - /* wait 10 usec */ - udelay(10); - - /* Set 0 to VPLA_SNRST and VPLB_SNRST */ - tmp = readl(SC_VPLL27ACTRL2); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27ACTRL2); - tmp = readl(SC_VPLL27BCTRL2); - tmp |= 0x10000000; - writel(tmp, SC_VPLL27BCTRL2); - - /* set 0 to VPLA27WP and VPLA27WP */ - tmp = readl(SC_VPLL27ACTRL); - tmp &= ~0x00000001; - writel(tmp, SC_VPLL27ACTRL); - tmp = readl(SC_VPLL27BCTRL); - tmp |= ~0x00000001; - writel(tmp, SC_VPLL27BCTRL); -} - -void pll_init(void) -{ - dpll_init(); - upll_init(); - vpll_init(); - - /* - * Wait 500 usec until dpll get stable - * We wait 10 usec in upll_init() and vpll_init() - * so 20 usec can be saved here. - */ - udelay(480); -} diff --git a/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c b/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c deleted file mode 100644 index 9b8c4855e58..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/pll_spectrum.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-ld4/pll_spectrum.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c b/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c deleted file mode 100644 index 225c0d24de3..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/sbc_init.c +++ /dev/null @@ -1 +0,0 @@ -#include "../ph1-ld4/sbc_init.c" diff --git a/arch/arm/mach-uniphier/ph1-sld8/umc_init.c b/arch/arm/mach-uniphier/ph1-sld8/umc_init.c deleted file mode 100644 index 7baea7e8528..00000000000 --- a/arch/arm/mach-uniphier/ph1-sld8/umc_init.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -static void umc_start_ssif(void __iomem *ssif_base) -{ - writel(0x00000000, ssif_base + 0x0000b004); - writel(0xffffffff, ssif_base + 0x0000c004); - writel(0x000fffcf, ssif_base + 0x0000c008); - writel(0x00000001, ssif_base + 0x0000b000); - writel(0x00000001, ssif_base + 0x0000c000); - writel(0x03010101, ssif_base + UMC_MDMCHSEL); - writel(0x03010100, ssif_base + UMC_DMDCHSEL); - - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); - writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); - - writel(0x00000001, ssif_base + UMC_CPURST); - writel(0x00000001, ssif_base + UMC_IDSRST); - writel(0x00000001, ssif_base + UMC_IXMRST); - writel(0x00000001, ssif_base + UMC_MDMRST); - writel(0x00000001, ssif_base + UMC_MDDRST); - writel(0x00000001, ssif_base + UMC_SIORST); - writel(0x00000001, ssif_base + UMC_VIORST); - writel(0x00000001, ssif_base + UMC_FRCRST); - writel(0x00000001, ssif_base + UMC_RGLRST); - writel(0x00000001, ssif_base + UMC_AIORST); - writel(0x00000001, ssif_base + UMC_DMDRST); -} - -static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, - int size, int freq) -{ -#ifdef CONFIG_DDR_STANDARD - writel(0x55990b11, dramcont + UMC_CMDCTLA); - writel(0x16958944, dramcont + UMC_CMDCTLB); -#else - writel(0x45990b11, dramcont + UMC_CMDCTLA); - writel(0x16958924, dramcont + UMC_CMDCTLB); -#endif - - writel(0x5101046A, dramcont + UMC_INITCTLA); - - if (size == 1) - writel(0x27028B0A, dramcont + UMC_INITCTLB); - else if (size == 2) - writel(0x38028B0A, dramcont + UMC_INITCTLB); - - writel(0x00FF00FF, dramcont + UMC_INITCTLC); - writel(0x00000b51, dramcont + UMC_DRMMR0); - writel(0x00000006, dramcont + UMC_DRMMR1); - writel(0x00000290, dramcont + UMC_DRMMR2); - -#ifdef CONFIG_DDR_STANDARD - writel(0x00000000, dramcont + UMC_DRMMR3); -#else - writel(0x00000800, dramcont + UMC_DRMMR3); -#endif - - if (size == 1) - writel(0x00240512, dramcont + UMC_SPCCTLA); - else if (size == 2) - writel(0x00350512, dramcont + UMC_SPCCTLA); - - writel(0x00ff0006, dramcont + UMC_SPCCTLB); - writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); - writel(0x04060806, dramcont + UMC_WDATACTL_D0); - writel(0x04a02000, dramcont + UMC_DATASET); - writel(0x00000000, ca_base + 0x2300); - writel(0x00400020, dramcont + UMC_DCCGCTL); - writel(0x00000003, dramcont + 0x7000); - writel(0x0000004f, dramcont + 0x8000); - writel(0x000000c3, dramcont + 0x8004); - writel(0x00000077, dramcont + 0x8008); - writel(0x0000003b, dramcont + UMC_DICGCTLA); - writel(0x020a0808, dramcont + UMC_DICGCTLB); - writel(0x00000004, dramcont + UMC_FLOWCTLG); - writel(0x80000201, ca_base + 0xc20); - writel(0x0801e01e, dramcont + UMC_FLOWCTLA); - writel(0x00200000, dramcont + UMC_FLOWCTLB); - writel(0x00004444, dramcont + UMC_FLOWCTLC); - writel(0x200a0a00, dramcont + UMC_SPCSETB); - writel(0x00000000, dramcont + UMC_SPCSETD); - writel(0x00000520, dramcont + UMC_DFICUPDCTLA); -} - -static int umc_init_sub(int freq, int size_ch0, int size_ch1) -{ - void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; - void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); - void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); - void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); - void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); - void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); - void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); - - umc_dram_init_start(dramcont0); - umc_dram_init_start(dramcont1); - umc_dram_init_poll(dramcont0); - umc_dram_init_poll(dramcont1); - - writel(0x00000101, dramcont0 + UMC_DIOCTLA); - - ddrphy_init(phy0_0, freq, size_ch0); - - ddrphy_prepare_training(phy0_0, 0); - ddrphy_training(phy0_0); - - writel(0x00000101, dramcont1 + UMC_DIOCTLA); - - ddrphy_init(phy1_0, freq, size_ch1); - - ddrphy_prepare_training(phy1_0, 1); - ddrphy_training(phy1_0); - - umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); - umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); - - umc_start_ssif(ssif_base); - - return 0; -} - -int umc_init(void) -{ - return umc_init_sub(CONFIG_DDR_FREQ, CONFIG_SDRAM0_SIZE / 0x08000000, - CONFIG_SDRAM1_SIZE / 0x08000000); -} - -#if (CONFIG_SDRAM0_SIZE == 0x08000000 || CONFIG_SDRAM0_SIZE == 0x10000000) && \ - (CONFIG_SDRAM1_SIZE == 0x08000000 || CONFIG_SDRAM1_SIZE == 0x10000000) && \ - CONFIG_DDR_NUM_CH0 == 1 && CONFIG_DDR_NUM_CH1 == 1 -/* OK */ -#else -#error Unsupported DDR configuration. -#endif diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile new file mode 100644 index 00000000000..542c670f978 --- /dev/null +++ b/arch/arm/mach-uniphier/pinctrl/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pinctrl-ph1-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pinctrl-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pinctrl-ph1-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += pinctrl-ph1-sld8.o diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c new file mode 100644 index 00000000000..160d3ef2991 --- /dev/null +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-ld4.c @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ph1_ld4_pin_init(void) +{ + u32 tmp; + + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(158, 0, 8, 4); /* XNFRE -> XNFRE_GB */ + sg_set_pinsel(159, 0, 8, 4); /* XNFWE -> XNFWE_GB */ + sg_set_pinsel(160, 0, 8, 4); /* XFALE -> NFALE_GB */ + sg_set_pinsel(161, 0, 8, 4); /* XFCLE -> NFCLE_GB */ + sg_set_pinsel(162, 0, 8, 4); /* XNFWP -> XFNWP_GB */ + sg_set_pinsel(163, 0, 8, 4); /* XNFCE0 -> XNFCE0_GB */ + sg_set_pinsel(164, 0, 8, 4); /* NANDRYBY0 -> NANDRYBY0_GB */ + sg_set_pinsel(22, 0, 8, 4); /* MMCCLK -> XFNCE1_GB */ + sg_set_pinsel(23, 0, 8, 4); /* MMCCMD -> NANDRYBY1_GB */ + sg_set_pinsel(24, 0, 8, 4); /* MMCDAT0 -> NFD0_GB */ + sg_set_pinsel(25, 0, 8, 4); /* MMCDAT1 -> NFD1_GB */ + sg_set_pinsel(26, 0, 8, 4); /* MMCDAT2 -> NFD2_GB */ + sg_set_pinsel(27, 0, 8, 4); /* MMCDAT3 -> NFD3_GB */ + sg_set_pinsel(28, 0, 8, 4); /* MMCDAT4 -> NFD4_GB */ + sg_set_pinsel(29, 0, 8, 4); /* MMCDAT5 -> NFD5_GB */ + sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */ + sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(53, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(54, 0, 8, 4); /* USB0OD -> USB0OD */ + sg_set_pinsel(55, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(56, 0, 8, 4); /* USB1OD -> USB1OD */ + /* sg_set_pinsel(67, 23, 8, 4); */ /* PCOE -> USB2VBUS */ + /* sg_set_pinsel(68, 23, 8, 4); */ /* PCWAIT -> USB2OD */ +#endif + + tmp = readl(SG_IECTRL); + tmp |= 0x41; + writel(tmp, SG_IECTRL); +} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c new file mode 100644 index 00000000000..f50644c52bb --- /dev/null +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-pro4.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ph1_pro4_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(40, 0, 4, 8); /* NFD0 -> NFD0 */ + sg_set_pinsel(41, 0, 4, 8); /* NFD1 -> NFD1 */ + sg_set_pinsel(42, 0, 4, 8); /* NFD2 -> NFD2 */ + sg_set_pinsel(43, 0, 4, 8); /* NFD3 -> NFD3 */ + sg_set_pinsel(44, 0, 4, 8); /* NFD4 -> NFD4 */ + sg_set_pinsel(45, 0, 4, 8); /* NFD5 -> NFD5 */ + sg_set_pinsel(46, 0, 4, 8); /* NFD6 -> NFD6 */ + sg_set_pinsel(47, 0, 4, 8); /* NFD7 -> NFD7 */ + sg_set_pinsel(48, 0, 4, 8); /* NFALE -> NFALE */ + sg_set_pinsel(49, 0, 4, 8); /* NFCLE -> NFCLE */ + sg_set_pinsel(50, 0, 4, 8); /* XNFRE -> XNFRE */ + sg_set_pinsel(51, 0, 4, 8); /* XNFWE -> XNFWE */ + sg_set_pinsel(52, 0, 4, 8); /* XNFWP -> XNFWP */ + sg_set_pinsel(53, 0, 4, 8); /* XNFCE0 -> XNFCE0 */ + sg_set_pinsel(54, 0, 4, 8); /* NRYBY0 -> NRYBY0 */ + /* sg_set_pinsel(131, 1, 4, 8); */ /* RXD2 -> NRYBY1 */ + /* sg_set_pinsel(132, 1, 4, 8); */ /* TXD2 -> XNFCE1 */ +#endif + +#ifdef CONFIG_USB_XHCI_UNIPHIER + sg_set_pinsel(180, 0, 4, 8); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(181, 0, 4, 8); /* USB0OD -> USB0OD */ + sg_set_pinsel(182, 0, 4, 8); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(183, 0, 4, 8); /* USB1OD -> USB1OD */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(184, 0, 4, 8); /* USB2VBUS -> USB2VBUS */ + sg_set_pinsel(185, 0, 4, 8); /* USB2OD -> USB2OD */ + sg_set_pinsel(187, 0, 4, 8); /* USB3VBUS -> USB3VBUS */ + sg_set_pinsel(188, 0, 4, 8); /* USB3OD -> USB3OD */ +#endif + + writel(1, SG_LOADPINCTRL); +} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c new file mode 100644 index 00000000000..f1b2bbbb4a2 --- /dev/null +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld3.c @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +void ph1_sld3_pin_init(void) +{ +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(13, 0, 4, 4); /* USB0OC */ + sg_set_pinsel(14, 1, 4, 4); /* USB0VBUS */ + + sg_set_pinsel(15, 0, 4, 4); /* USB1OC */ + sg_set_pinsel(16, 1, 4, 4); /* USB1VBUS */ + + sg_set_pinsel(17, 0, 4, 4); /* USB2OC */ + sg_set_pinsel(18, 1, 4, 4); /* USB2VBUS */ + + sg_set_pinsel(19, 0, 4, 4); /* USB3OC */ + sg_set_pinsel(20, 1, 4, 4); /* USB3VBUS */ +#endif +} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c new file mode 100644 index 00000000000..f936a53d1f1 --- /dev/null +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ph1-sld8.c @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +void ph1_sld8_pin_init(void) +{ + /* Comment format: PAD Name -> Function Name */ + +#ifdef CONFIG_NAND_DENALI + sg_set_pinsel(15, 0, 8, 4); /* XNFRE_GB -> XNFRE_GB */ + sg_set_pinsel(16, 0, 8, 4); /* XNFWE_GB -> XNFWE_GB */ + sg_set_pinsel(17, 0, 8, 4); /* XFALE_GB -> NFALE_GB */ + sg_set_pinsel(18, 0, 8, 4); /* XFCLE_GB -> NFCLE_GB */ + sg_set_pinsel(19, 0, 8, 4); /* XNFWP_GB -> XFNWP_GB */ + sg_set_pinsel(20, 0, 8, 4); /* XNFCE0_GB -> XNFCE0_GB */ + sg_set_pinsel(21, 0, 8, 4); /* NANDRYBY0_GB -> NANDRYBY0_GB */ + sg_set_pinsel(22, 0, 8, 4); /* XFNCE1_GB -> XFNCE1_GB */ + sg_set_pinsel(23, 0, 8, 4); /* NANDRYBY1_GB -> NANDRYBY1_GB */ + sg_set_pinsel(24, 0, 8, 4); /* NFD0_GB -> NFD0_GB */ + sg_set_pinsel(25, 0, 8, 4); /* NFD1_GB -> NFD1_GB */ + sg_set_pinsel(26, 0, 8, 4); /* NFD2_GB -> NFD2_GB */ + sg_set_pinsel(27, 0, 8, 4); /* NFD3_GB -> NFD3_GB */ + sg_set_pinsel(28, 0, 8, 4); /* NFD4_GB -> NFD4_GB */ + sg_set_pinsel(29, 0, 8, 4); /* NFD5_GB -> NFD5_GB */ + sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */ + sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */ +#endif + +#ifdef CONFIG_USB_EHCI_UNIPHIER + sg_set_pinsel(41, 0, 8, 4); /* USB0VBUS -> USB0VBUS */ + sg_set_pinsel(42, 0, 8, 4); /* USB0OD -> USB0OD */ + sg_set_pinsel(43, 0, 8, 4); /* USB1VBUS -> USB1VBUS */ + sg_set_pinsel(44, 0, 8, 4); /* USB1OD -> USB1OD */ + /* sg_set_pinsel(114, 1, 8, 4); */ /* TXD1 -> USB2VBUS (shared with UART) */ + /* sg_set_pinsel(115, 1, 8, 4); */ /* RXD1 -> USB2OD */ +#endif +} diff --git a/arch/arm/mach-uniphier/pll/Makefile b/arch/arm/mach-uniphier/pll/Makefile new file mode 100644 index 00000000000..d33f99e4461 --- /dev/null +++ b/arch/arm/mach-uniphier/pll/Makefile @@ -0,0 +1,8 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += pll-init-ph1-sld3.o \ + pll-spectrum-ph1-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += pll-init-ph1-ld4.o \ + pll-spectrum-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += pll-init-ph1-pro4.o \ + pll-spectrum-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += pll-init-ph1-sld8.o \ + pll-spectrum-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c new file mode 100644 index 00000000000..a272a900e11 --- /dev/null +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-ld4.c @@ -0,0 +1,203 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#undef DPLL_SSC_RATE_1PER + +static int dpll_init(unsigned int dram_freq) +{ + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT (DPLLCTRL.bit[29:20]) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x000f0000; + switch (dram_freq) { + case 1333: + tmp |= 0x000d0000; + break; + case 1600: + tmp |= 0x000c0000; + break; + default: + pr_err("Unsupported frequency"); + return -EINVAL; + } + +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~SC_DPLLCTRL_SSC_RATE; +#else + tmp |= SC_DPLLCTRL_SSC_RATE; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); + + return 0; +} + +static void upll_init(void) +{ + u32 tmp, clk_mode_upll, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ + tmp = readl(SC_UPLLCTRL); + tmp &= ~0x18000000; + writel(tmp, SC_UPLLCTRL); + + if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x0228f5c0; + } else { + /* AXO: default 24.576MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x02328000; + } + } + + writel(tmp, SC_UPLLCTRL); + + /* set 1 to K_LD(UPLLCTRL.bit[27]) */ + tmp |= 0x08000000; + writel(tmp, SC_UPLLCTRL); + + /* wait 10 usec */ + udelay(10); + + /* set 1 to SNRT(UPLLCTRL.bit[28]) */ + tmp |= 0x10000000; + writel(tmp, SC_UPLLCTRL); +} + +static void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 1 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Set 0 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* AXO: default 24.576MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* Set 1 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* wait 10 usec */ + udelay(10); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* set 0 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +int ph1_ld4_pll_init(const struct uniphier_board_data *bd) +{ + int ret; + + ret = dpll_init(bd->dram_freq); + if (ret) + return ret; + upll_init(); + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 10 usec in upll_init() and vpll_init() + * so 20 usec can be saved here. + */ + udelay(480); + + return 0; +} diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c new file mode 100644 index 00000000000..906c22f6c58 --- /dev/null +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-pro4.c @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#undef DPLL_SSC_RATE_1PER + +static int dpll_init(unsigned int dram_freq) +{ + u32 tmp; + + /* + * Set Frequency + * Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz) + * to FOUT ( DPLLCTRL.bit[29:20] ) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~(0x000f0000); + switch (dram_freq) { + case 1333: + tmp |= 0x000d0000; + break; + case 1600: + tmp |= 0x000c0000; + break; + default: + pr_err("Unsupported frequency"); + return -EINVAL; + } + + /* + * Set Moduration rate + * Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15]) + */ +#if defined(DPLL_SSC_RATE_1PER) + tmp &= ~0x00008000; +#else + tmp |= 0x00008000; +#endif + writel(tmp, SC_DPLLCTRL); + + tmp = readl(SC_DPLLCTRL2); + tmp |= SC_DPLLCTRL2_NRSTDS; + writel(tmp, SC_DPLLCTRL2); + + return 0; +} + +static void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + /* Set VPLL27A & VPLL27B */ + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */ + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) + return; + + /* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Unset VPLA_K_LD and VPLB_K_LD bit */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set VPLA_M and VPLB_M to 0x20 */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) { + /* Set VPLA_K and VPLB_K for AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066666; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066666; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* wait 1 usec */ + udelay(1); + + /* Set VPLA_K_LD and VPLB_K_LD to load K parameters */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Unset VPLA_SNRST and VPLB_SNRST bit */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +int ph1_pro4_pll_init(const struct uniphier_board_data *bd) +{ + int ret; + + ret = dpll_init(bd->dram_freq); + if (ret) + return ret; + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 1 usec in vpll_init() so 1 usec can be saved here. + */ + udelay(499); + + return 0; +} diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c new file mode 100644 index 00000000000..6294a452c29 --- /dev/null +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld3.c @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +int ph1_sld3_pll_init(const struct uniphier_board_data *bd) +{ + /* add pll init code here */ + return 0; +} diff --git a/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c new file mode 100644 index 00000000000..f249abeeda3 --- /dev/null +++ b/arch/arm/mach-uniphier/pll/pll-init-ph1-sld8.c @@ -0,0 +1,204 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +static void dpll_init(void) +{ + u32 tmp; + /* + * Set DPLL SSC parameters for DPLLCTRL3 + * [23] DIVN_TEST 0x1 + * [22:16] DIVN 0x50 + * [10] FREFSEL_TEST 0x1 + * [9:8] FREFSEL 0x2 + * [4] ICPD_TEST 0x1 + * [3:0] ICPD 0xb + */ + tmp = readl(SC_DPLLCTRL3); + tmp &= ~0x00ff0717; + tmp |= 0x00d0061b; + writel(tmp, SC_DPLLCTRL3); + + /* + * Set DPLL SSC parameters for DPLLCTRL + * <-1%> <-2%> + * [29:20] SSC_UPCNT 132 (0x084) 132 (0x084) + * [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6) + */ + tmp = readl(SC_DPLLCTRL); + tmp &= ~0x3ff07fff; +#ifdef CONFIG_DPLL_SSC_RATE_1PER + tmp |= 0x084018bf; +#else + tmp |= 0x084031a6; +#endif + writel(tmp, SC_DPLLCTRL); + + /* + * Set DPLL SSC parameters for DPLLCTRL2 + * [31:29] SSC_STEP 0 + * [27] SSC_REG_REF 1 + * [26:20] SSC_M 79 (0x4f) + * [19:0] SSC_K 964689 (0xeb851) + */ + tmp = readl(SC_DPLLCTRL2); + tmp &= ~0xefffffff; + tmp |= 0x0cfeb851; + writel(tmp, SC_DPLLCTRL2); +} + +static void upll_init(void) +{ + u32 tmp, clk_mode_upll, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK; + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */ + tmp = readl(SC_UPLLCTRL); + tmp &= ~0x18000000; + writel(tmp, SC_UPLLCTRL); + + if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) { + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x0228f5c0; + } else { + /* AXO: default 24.576MHz */ + tmp &= ~0x07ffffff; + tmp |= 0x02328000; + } + } + + writel(tmp, SC_UPLLCTRL); + + /* set 1 to K_LD(UPLLCTRL.bit[27]) */ + tmp |= 0x08000000; + writel(tmp, SC_UPLLCTRL); + + /* wait 10 usec */ + udelay(10); + + /* set 1 to SNRT(UPLLCTRL.bit[28]) */ + tmp |= 0x10000000; + writel(tmp, SC_UPLLCTRL); +} + +static void vpll_init(void) +{ + u32 tmp, clk_mode_axosel; + + tmp = readl(SG_PINMON0); + clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK; + + /* set 1 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= 0x00000001; + writel(tmp, SC_VPLL27BCTRL); + + /* Set 0 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* Set 0x20 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp &= ~0x0000007f; + tmp |= 0x00000020; + writel(tmp, SC_VPLL27BCTRL2); + + if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U || + clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) { + /* AXO: 25MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x00066664; + writel(tmp, SC_VPLL27BCTRL3); + } else { + /* AXO: default 24.576MHz */ + tmp = readl(SC_VPLL27ACTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp &= ~0x000fffff; + tmp |= 0x000f5800; + writel(tmp, SC_VPLL27BCTRL3); + } + + /* Set 1 to VPLA_K_LD and VPLB_K_LD */ + tmp = readl(SC_VPLL27ACTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL3); + tmp = readl(SC_VPLL27BCTRL3); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL3); + + /* wait 10 usec */ + udelay(10); + + /* Set 0 to VPLA_SNRST and VPLB_SNRST */ + tmp = readl(SC_VPLL27ACTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27ACTRL2); + tmp = readl(SC_VPLL27BCTRL2); + tmp |= 0x10000000; + writel(tmp, SC_VPLL27BCTRL2); + + /* set 0 to VPLA27WP and VPLA27WP */ + tmp = readl(SC_VPLL27ACTRL); + tmp &= ~0x00000001; + writel(tmp, SC_VPLL27ACTRL); + tmp = readl(SC_VPLL27BCTRL); + tmp |= ~0x00000001; + writel(tmp, SC_VPLL27BCTRL); +} + +int ph1_sld8_pll_init(const struct uniphier_board_data *bd) +{ + dpll_init(); + upll_init(); + vpll_init(); + + /* + * Wait 500 usec until dpll get stable + * We wait 10 usec in upll_init() and vpll_init() + * so 20 usec can be saved here. + */ + udelay(480); + + return 0; +} diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c new file mode 100644 index 00000000000..cad0ed8cdd4 --- /dev/null +++ b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-ld4.c @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +int ph1_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd) +{ + u32 tmp; + + tmp = readl(SC_DPLLCTRL); + tmp |= SC_DPLLCTRL_SSC_EN; + writel(tmp, SC_DPLLCTRL); + + return 0; +} diff --git a/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c new file mode 100644 index 00000000000..43dc9736549 --- /dev/null +++ b/arch/arm/mach-uniphier/pll/pll-spectrum-ph1-sld3.c @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +int ph1_sld3_enable_dpll_ssc(const struct uniphier_board_data *bd) +{ + u32 tmp; + + tmp = readl(SC_DPLLCTRL); + tmp |= SC_DPLLCTRL_SSC_EN; + writel(tmp, SC_DPLLCTRL); + + return 0; +} diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile new file mode 100644 index 00000000000..68ffd1c626b --- /dev/null +++ b/arch/arm/mach-uniphier/sbc/Makefile @@ -0,0 +1,4 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD3) += sbc-ph1-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += sbc-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += sbc-ph1-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += sbc-ph1-ld4.o diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c new file mode 100644 index 00000000000..929f50a883a --- /dev/null +++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-ld4.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_ld4_sbc_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + + /* system bus output enable */ + tmp = readl(PC0CTRL); + tmp &= 0xfffffcff; + writel(tmp, PC0CTRL); + + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); + + if (boot_is_swapped()) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. + * + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } + + return 0; +} diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c new file mode 100644 index 00000000000..1032c54e644 --- /dev/null +++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-pro4.c @@ -0,0 +1,45 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_pro4_sbc_init(const struct uniphier_board_data *bd) +{ + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10); + writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11); + writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12); + writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14); + + if (boot_is_swapped()) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. + * + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } + + return 0; +} diff --git a/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c b/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c new file mode 100644 index 00000000000..fb707be83a2 --- /dev/null +++ b/arch/arm/mach-uniphier/sbc/sbc-ph1-sld3.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +int ph1_sld3_sbc_init(const struct uniphier_board_data *bd) +{ + /* only address/data multiplex mode is supported */ + + /* + * Only CS1 is connected to support card. + * BKSZ[1:0] should be set to "01". + */ + writel(SBCTRL0_ADMULTIPLX_MEM_VALUE, SBCTRL10); + writel(SBCTRL1_ADMULTIPLX_MEM_VALUE, SBCTRL11); + writel(SBCTRL2_ADMULTIPLX_MEM_VALUE, SBCTRL12); + + if (boot_is_swapped()) { + /* + * Boot Swap On: boot from external NOR/SRAM + * 0x42000000-0x43ffffff is a mirror of 0x40000000-0x41ffffff. + * + * 0x40000000-0x41efffff, 0x42000000-0x43efffff: memory bank + * 0x41f00000-0x41ffffff, 0x43f00000-0x43ffffff: peripherals + */ + writel(0x0000bc01, SBBASE0); + } else { + /* + * Boot Swap Off: boot from mask ROM + * 0x40000000-0x41ffffff: mask ROM + * 0x42000000-0x43efffff: memory bank (31MB) + * 0x43f00000-0x43ffffff: peripherals (1MB) + */ + writel(0x0000be01, SBBASE0); /* dummy */ + writel(0x0200be01, SBBASE1); + } + + sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */ + + return 0; +} diff --git a/arch/arm/mach-uniphier/soc_info.c b/arch/arm/mach-uniphier/soc_info.c new file mode 100644 index 00000000000..3e8e7f4ef33 --- /dev/null +++ b/arch/arm/mach-uniphier/soc_info.c @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#if UNIPHIER_MULTI_SOC +enum uniphier_soc_id uniphier_get_soc_type(void) +{ + u32 revision = readl(SG_REVISION); + enum uniphier_soc_id ret; + + switch ((revision & SG_REVISION_TYPE_MASK) >> SG_REVISION_TYPE_SHIFT) { +#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD3 + case 0x25: + ret = SOC_UNIPHIER_PH1_SLD3; + break; +#endif +#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD4 + case 0x26: + ret = SOC_UNIPHIER_PH1_LD4; + break; +#endif +#ifdef CONFIG_ARCH_UNIPHIER_PH1_PRO4 + case 0x28: + ret = SOC_UNIPHIER_PH1_PRO4; + break; +#endif +#ifdef CONFIG_ARCH_UNIPHIER_PH1_SLD8 + case 0x29: + ret = SOC_UNIPHIER_PH1_SLD8; + break; +#endif +#ifdef CONFIG_ARCH_UNIPHIER_PH1_PRO5 + case 0x2A: + ret = SOC_UNIPHIER_PH1_PRO5; + break; +#endif +#ifdef CONFIG_ARCH_UNIPHIER_PROXSTREAM2 + case 0x2E: + ret = SOC_UNIPHIER_PROXSTREAM2; + break; +#endif +#ifdef CONFIG_ARCH_UNIPHIER_PH1_LD6B + case 0x2F: + ret = SOC_UNIPHIER_PH1_LD6B; + break; +#endif + default: + ret = SOC_UNIPHIER_UNKNOWN; + break; + } + + return ret; +} +#endif diff --git a/arch/arm/mach-uniphier/spl.c b/arch/arm/mach-uniphier/spl.c deleted file mode 100644 index 4c3cad3b88b..00000000000 --- a/arch/arm/mach-uniphier/spl.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (C) 2013-2015 Masahiro Yamada - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void __weak bcu_init(void) -{ -}; - -void __weak sbc_init(void) -{ -}; - -void __weak sg_init(void) -{ -}; - -void __weak early_pin_init(void) -{ -}; - -void sbc_init(void); -void sg_init(void); -void pll_init(void); -void pin_init(void); -void memconf_init(void); -void early_clkrst_init(void); -void early_pin_init(void); -int umc_init(void); -void enable_dpll_ssc(void); - -void spl_board_init(void) -{ - bcu_init(); - - sbc_init(); - - sg_init(); - - support_card_reset(); - - pll_init(); - - support_card_init(); - - led_puts("L0"); - - memconf_init(); - - led_puts("L1"); - - early_clkrst_init(); - - led_puts("L2"); - - early_pin_init(); - - led_puts("L3"); - -#ifdef CONFIG_SPL_SERIAL_SUPPORT - preloader_console_init(); -#endif - - led_puts("L4"); - - { - int res; - - res = umc_init(); - if (res < 0) { - while (1) - ; - } - } - - led_puts("L5"); - - enable_dpll_ssc(); - - led_puts("L6"); -} diff --git a/arch/arm/mach-uniphier/umc/Makefile b/arch/arm/mach-uniphier/umc/Makefile new file mode 100644 index 00000000000..dd35e77dab4 --- /dev/null +++ b/arch/arm/mach-uniphier/umc/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_ARCH_UNIPHIER_PH1_LD4) += umc-ph1-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_PRO4) += umc-ph1-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_PH1_SLD8) += umc-ph1-sld8.o diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c b/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c new file mode 100644 index 00000000000..81246850b38 --- /dev/null +++ b/arch/arm/mach-uniphier/umc/umc-ph1-ld4.c @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +static void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000000, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x000fffcf, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_FRCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ + if (freq == 1333) { + writel(0x45990b11, dramcont + UMC_CMDCTLA); + writel(0x16958924, dramcont + UMC_CMDCTLB); + writel(0x5101046A, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x27028B0A, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x38028B0A, dramcont + UMC_INITCTLB); + + writel(0x000FF0FF, dramcont + UMC_INITCTLC); + writel(0x00000b51, dramcont + UMC_DRMMR0); + } else if (freq == 1600) { + writel(0x36BB0F17, dramcont + UMC_CMDCTLA); + writel(0x18C6AA24, dramcont + UMC_CMDCTLB); + writel(0x5101387F, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x2F030D3F, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x43030D3F, dramcont + UMC_INITCTLB); + + writel(0x00FF00FF, dramcont + UMC_INITCTLC); + writel(0x00000d71, dramcont + UMC_DRMMR0); + } + + writel(0x00000006, dramcont + UMC_DRMMR1); + + if (freq == 1333) + writel(0x00000290, dramcont + UMC_DRMMR2); + else if (freq == 1600) + writel(0x00000298, dramcont + UMC_DRMMR2); + + writel(0x00000800, dramcont + UMC_DRMMR3); + + if (freq == 1333) { + if (size == 1) + writel(0x00240512, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x00350512, dramcont + UMC_SPCCTLA); + + writel(0x00ff0006, dramcont + UMC_SPCCTLB); + writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); + } else if (freq == 1600) { + if (size == 1) + writel(0x002B0617, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x003F0617, dramcont + UMC_SPCCTLA); + + writel(0x00ff0008, dramcont + UMC_SPCCTLB); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); + } + + writel(0x04060806, dramcont + UMC_WDATACTL_D0); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x00000003, dramcont + 0x7000); + writel(0x0000000f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000071, dramcont + 0x8008); + writel(0x0000003b, dramcont + UMC_DICGCTLA); + writel(0x020a0808, dramcont + UMC_DICGCTLB); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00000000, dramcont + UMC_SPCSETD); + writel(0x00000520, dramcont + UMC_DFICUPDCTLA); +} + +static int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + ph1_ld4_ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + ph1_ld4_ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 1); + ddrphy_training(phy1_0); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int ph1_ld4_umc_init(const struct uniphier_board_data *bd) +{ + if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) && + (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) && + (bd->dram_freq == 1333 || bd->dram_freq == 1600) && + bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) { + return umc_init_sub(bd->dram_freq, + bd->dram_ch0_size / SZ_128M, + bd->dram_ch1_size / SZ_128M); + } else { + pr_err("Unsupported DDR configuration\n"); + return -EINVAL; + } +} diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c b/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c new file mode 100644 index 00000000000..8c9f0579fc7 --- /dev/null +++ b/arch/arm/mach-uniphier/umc/umc-ph1-pro4.c @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +static void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000001, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x07ffffff, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + + writel(0x03010100, ssif_base + UMC_HDMCHSEL); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DVCCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + writel(0x00000000, ssif_base + 0x0000c044); /* DCGIV_SSIF_REG */ + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_HDMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_HDDRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_GIORST); + writel(0x00000001, ssif_base + UMC_HD2RST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_DVCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_VPERST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ + writel(0x66bb0f17, dramcont + UMC_CMDCTLA); + writel(0x18c6aa44, dramcont + UMC_CMDCTLB); + writel(0x5101387f, dramcont + UMC_INITCTLA); + writel(0x43030d3f, dramcont + UMC_INITCTLB); + writel(0x00ff00ff, dramcont + UMC_INITCTLC); + writel(0x00000d71, dramcont + UMC_DRMMR0); + writel(0x00000006, dramcont + UMC_DRMMR1); + writel(0x00000298, dramcont + UMC_DRMMR2); + writel(0x00000000, dramcont + UMC_DRMMR3); + writel(0x003f0617, dramcont + UMC_SPCCTLA); + writel(0x00ff0008, dramcont + UMC_SPCCTLB); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D0); + writel(0x000c00ae, dramcont + UMC_RDATACTL_D1); + writel(0x04060802, dramcont + UMC_WDATACTL_D0); + writel(0x04060802, dramcont + UMC_WDATACTL_D1); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x0000000f, dramcont + 0x7000); + writel(0x0000000f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000071, dramcont + 0x8008); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x00000000, dramcont + 0x0060); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00010000, dramcont + UMC_SPCSETD); + writel(0x80000020, dramcont + UMC_DFICUPDCTLA); +} + +static int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy0_1 = (void __iomem *)DDRPHY_BASE(0, 1); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); + void __iomem *phy1_1 = (void __iomem *)DDRPHY_BASE(1, 1); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + ph1_pro4_ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + + writel(0x00000103, dramcont0 + UMC_DIOCTLA); + + ph1_pro4_ddrphy_init(phy0_1, freq, size_ch0); + + ddrphy_prepare_training(phy0_1, 1); + ddrphy_training(phy0_1); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + ph1_pro4_ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 0); + ddrphy_training(phy1_0); + + writel(0x00000103, dramcont1 + UMC_DIOCTLA); + + ph1_pro4_ddrphy_init(phy1_1, freq, size_ch1); + + ddrphy_prepare_training(phy1_1, 1); + ddrphy_training(phy1_1); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int ph1_pro4_umc_init(const struct uniphier_board_data *bd) +{ + if (((bd->dram_ch0_size == SZ_512M && bd->dram_ch0_width == 32) || + (bd->dram_ch0_size == SZ_256M && bd->dram_ch0_width == 16)) && + ((bd->dram_ch1_size == SZ_512M && bd->dram_ch1_width == 32) || + (bd->dram_ch1_size == SZ_256M && bd->dram_ch1_width == 16)) && + bd->dram_freq == 1600) { + return umc_init_sub(bd->dram_freq, + bd->dram_ch0_size / SZ_128M, + bd->dram_ch1_size / SZ_128M); + } else { + pr_err("Unsupported DDR configuration\n"); + return -EINVAL; + } +} diff --git a/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c b/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c new file mode 100644 index 00000000000..bc60a3472e1 --- /dev/null +++ b/arch/arm/mach-uniphier/umc/umc-ph1-sld8.c @@ -0,0 +1,155 @@ +/* + * Copyright (C) 2011-2015 Masahiro Yamada + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +static void umc_start_ssif(void __iomem *ssif_base) +{ + writel(0x00000000, ssif_base + 0x0000b004); + writel(0xffffffff, ssif_base + 0x0000c004); + writel(0x000fffcf, ssif_base + 0x0000c008); + writel(0x00000001, ssif_base + 0x0000b000); + writel(0x00000001, ssif_base + 0x0000c000); + writel(0x03010101, ssif_base + UMC_MDMCHSEL); + writel(0x03010100, ssif_base + UMC_DMDCHSEL); + + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC); + writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST); + + writel(0x00000001, ssif_base + UMC_CPURST); + writel(0x00000001, ssif_base + UMC_IDSRST); + writel(0x00000001, ssif_base + UMC_IXMRST); + writel(0x00000001, ssif_base + UMC_MDMRST); + writel(0x00000001, ssif_base + UMC_MDDRST); + writel(0x00000001, ssif_base + UMC_SIORST); + writel(0x00000001, ssif_base + UMC_VIORST); + writel(0x00000001, ssif_base + UMC_FRCRST); + writel(0x00000001, ssif_base + UMC_RGLRST); + writel(0x00000001, ssif_base + UMC_AIORST); + writel(0x00000001, ssif_base + UMC_DMDRST); +} + +static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base, + int size, int freq) +{ +#ifdef CONFIG_DDR_STANDARD + writel(0x55990b11, dramcont + UMC_CMDCTLA); + writel(0x16958944, dramcont + UMC_CMDCTLB); +#else + writel(0x45990b11, dramcont + UMC_CMDCTLA); + writel(0x16958924, dramcont + UMC_CMDCTLB); +#endif + + writel(0x5101046A, dramcont + UMC_INITCTLA); + + if (size == 1) + writel(0x27028B0A, dramcont + UMC_INITCTLB); + else if (size == 2) + writel(0x38028B0A, dramcont + UMC_INITCTLB); + + writel(0x00FF00FF, dramcont + UMC_INITCTLC); + writel(0x00000b51, dramcont + UMC_DRMMR0); + writel(0x00000006, dramcont + UMC_DRMMR1); + writel(0x00000290, dramcont + UMC_DRMMR2); + +#ifdef CONFIG_DDR_STANDARD + writel(0x00000000, dramcont + UMC_DRMMR3); +#else + writel(0x00000800, dramcont + UMC_DRMMR3); +#endif + + if (size == 1) + writel(0x00240512, dramcont + UMC_SPCCTLA); + else if (size == 2) + writel(0x00350512, dramcont + UMC_SPCCTLA); + + writel(0x00ff0006, dramcont + UMC_SPCCTLB); + writel(0x000a00ac, dramcont + UMC_RDATACTL_D0); + writel(0x04060806, dramcont + UMC_WDATACTL_D0); + writel(0x04a02000, dramcont + UMC_DATASET); + writel(0x00000000, ca_base + 0x2300); + writel(0x00400020, dramcont + UMC_DCCGCTL); + writel(0x00000003, dramcont + 0x7000); + writel(0x0000004f, dramcont + 0x8000); + writel(0x000000c3, dramcont + 0x8004); + writel(0x00000077, dramcont + 0x8008); + writel(0x0000003b, dramcont + UMC_DICGCTLA); + writel(0x020a0808, dramcont + UMC_DICGCTLB); + writel(0x00000004, dramcont + UMC_FLOWCTLG); + writel(0x80000201, ca_base + 0xc20); + writel(0x0801e01e, dramcont + UMC_FLOWCTLA); + writel(0x00200000, dramcont + UMC_FLOWCTLB); + writel(0x00004444, dramcont + UMC_FLOWCTLC); + writel(0x200a0a00, dramcont + UMC_SPCSETB); + writel(0x00000000, dramcont + UMC_SPCSETD); + writel(0x00000520, dramcont + UMC_DFICUPDCTLA); +} + +static int umc_init_sub(int freq, int size_ch0, int size_ch1) +{ + void __iomem *ssif_base = (void __iomem *)UMC_SSIF_BASE; + void __iomem *ca_base0 = (void __iomem *)UMC_CA_BASE(0); + void __iomem *ca_base1 = (void __iomem *)UMC_CA_BASE(1); + void __iomem *dramcont0 = (void __iomem *)UMC_DRAMCONT_BASE(0); + void __iomem *dramcont1 = (void __iomem *)UMC_DRAMCONT_BASE(1); + void __iomem *phy0_0 = (void __iomem *)DDRPHY_BASE(0, 0); + void __iomem *phy1_0 = (void __iomem *)DDRPHY_BASE(1, 0); + + umc_dram_init_start(dramcont0); + umc_dram_init_start(dramcont1); + umc_dram_init_poll(dramcont0); + umc_dram_init_poll(dramcont1); + + writel(0x00000101, dramcont0 + UMC_DIOCTLA); + + ph1_sld8_ddrphy_init(phy0_0, freq, size_ch0); + + ddrphy_prepare_training(phy0_0, 0); + ddrphy_training(phy0_0); + + writel(0x00000101, dramcont1 + UMC_DIOCTLA); + + ph1_sld8_ddrphy_init(phy1_0, freq, size_ch1); + + ddrphy_prepare_training(phy1_0, 1); + ddrphy_training(phy1_0); + + umc_dramcont_init(dramcont0, ca_base0, size_ch0, freq); + umc_dramcont_init(dramcont1, ca_base1, size_ch1, freq); + + umc_start_ssif(ssif_base); + + return 0; +} + +int ph1_sld8_umc_init(const struct uniphier_board_data *bd) +{ + if ((bd->dram_ch0_size == SZ_128M || bd->dram_ch0_size == SZ_256M) && + (bd->dram_ch1_size == SZ_128M || bd->dram_ch1_size == SZ_256M) && + bd->dram_freq == 1333 && + bd->dram_ch0_width == 16 && bd->dram_ch1_width == 16) { + return umc_init_sub(bd->dram_freq, + bd->dram_ch0_size / SZ_128M, + bd->dram_ch1_size / SZ_128M); + } else { + pr_err("Unsupported DDR configuration\n"); + return -EINVAL; + } +} diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 139767a6ee3..aaf1f460388 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_UNIPHIER=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ARCH_UNIPHIER_PH1_PRO4=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_TEXT_BASE=0x84000000 CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-pro4-ref" diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index f44c58bf9d0..9109b7f8d9d 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -9,53 +9,6 @@ #ifndef __CONFIG_UNIPHIER_COMMON_H__ #define __CONFIG_UNIPHIER_COMMON_H__ -#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) -#define CONFIG_DDR_NUM_CH0 2 -#define CONFIG_DDR_NUM_CH1 1 -#define CONFIG_DDR_NUM_CH2 1 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x20000000 -#define CONFIG_SDRAM1_BASE 0xc0000000 -#define CONFIG_SDRAM1_SIZE 0x20000000 -#define CONFIG_SDRAM2_BASE 0xc0000000 -#define CONFIG_SDRAM2_SIZE 0x10000000 -#endif - -#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) -#define CONFIG_DDR_NUM_CH0 1 -#define CONFIG_DDR_NUM_CH1 1 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x10000000 -#define CONFIG_SDRAM1_BASE 0x90000000 -#define CONFIG_SDRAM1_SIZE 0x10000000 -#endif - -#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) -#define CONFIG_DDR_NUM_CH0 2 -#define CONFIG_DDR_NUM_CH1 2 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x20000000 -#define CONFIG_SDRAM1_BASE 0xa0000000 -#define CONFIG_SDRAM1_SIZE 0x20000000 -#endif - -#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) -#define CONFIG_DDR_NUM_CH0 1 -#define CONFIG_DDR_NUM_CH1 1 - -/* Physical start address of SDRAM */ -#define CONFIG_SDRAM0_BASE 0x80000000 -#define CONFIG_SDRAM0_SIZE 0x10000000 -#define CONFIG_SDRAM1_BASE 0x90000000 -#define CONFIG_SDRAM1_SIZE 0x10000000 -#endif - #define CONFIG_I2C_EEPROM #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 @@ -285,8 +238,7 @@ defined(CONFIG_ARCH_UNIPHIER_PH1_LD4) || \ defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8) #define CONFIG_SPL_TEXT_BASE 0x00040000 -#endif -#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4) +#else #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif -- cgit v1.3.1