From 9a7881abeb8c57e6d132c9303e487409a5340e51 Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Sun, 3 Aug 2025 18:24:42 -0700 Subject: include: configs: socfpga: Add environment variables for distro boot Added environment variables needed to support NAND distro boot Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- include/configs/socfpga_soc64_common.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 83b600c7fcc..e48673e6151 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -39,6 +39,9 @@ * U-Boot environment configurations */ +#define CFG_SYS_NAND_U_BOOT_SIZE (1 * 1024 * 1024) +#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE + /* * Environment variable */ @@ -159,6 +162,7 @@ " ${qspi_clock}; echo QSPI clock frequency updated; fi; fi\0" \ "scriptaddr=0x05FF0000\0" \ "scriptfile=boot.scr\0" \ + "nandroot=ubi0:rootfs\0" \ "socfpga_legacy_reset_compat=1\0" \ "smc_fid_rd=0xC2000007\0" \ "smc_fid_wr=0xC2000008\0" \ @@ -214,6 +218,10 @@ "scriptfile=u-boot.scr\0" \ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ "then source ${scriptaddr}:script; fi\0" \ + "nandfitboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${nandroot} rw rootwait rootfstype=ubifs ubi.mtd=1; " \ + "bootm ${loadaddr}\0" \ + "nandfitload=ubi part root; ubi readvol ${loadaddr} kernel\0" \ "socfpga_legacy_reset_compat=1\0" \ "smc_fid_rd=0xC2000007\0" \ "smc_fid_wr=0xC2000008\0" \ -- cgit v1.3.1 From c8f5166cff0ccdb1966ed786dba88e9548ce632e Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Sun, 3 Aug 2025 18:24:44 -0700 Subject: sysreset: socfpga: soc64: Enable L2 reset Put all slave CPUs (CPU1-3) into WFI mode. Master CPU (CPU0) writes the magic word into system manager's scratch register to indicate the system has performed L2 reset and request reset manager to perform hardware handshake and then trigger L2 reset. CPU0 put itself into WFI mode. L2 reset will reboot all HPS CPU cores after which all HPS cores are in WFI mode. L2 reset is followed by warm reset request by SPL via RMR_EL3 system register. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- arch/arm/Kconfig | 2 +- drivers/sysreset/sysreset_socfpga_soc64.c | 63 ++++++++++++++++++++++++++++++- include/configs/socfpga_soc64_common.h | 9 +++++ 3 files changed, 71 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4e7593616d8..af81d937201 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1173,7 +1173,7 @@ config ARCH_SOCFPGA select SYSRESET select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \ - TARGET_SOCFPGA_SOC64 + TARGET_SOCFPGA_SOC64 select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5 imply CMD_DM imply CMD_MTDPARTS diff --git a/drivers/sysreset/sysreset_socfpga_soc64.c b/drivers/sysreset/sysreset_socfpga_soc64.c index 6f44792abb0..6ce30d9eaf0 100644 --- a/drivers/sysreset/sysreset_socfpga_soc64.c +++ b/drivers/sysreset/sysreset_socfpga_soc64.c @@ -1,19 +1,78 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Pepperl+Fuchs + * Copyright (C) 2025 Altera Corporation * Simon Goldschmidt */ +#include +#include #include #include #include #include +#include +#include + +#define GICD_CTRL_ADDRESS 0xfffc1000 + +static __always_inline void __l2_reset_cpu(void) +{ + asm volatile(/* Disable GIC distributor (IRQs). */ + "str wzr, [%3]\n" + /* Set Magic Number */ + "str %0, [%1]\n" + /* Increase timeout in rstmgr.hdsktimeout */ + "ldr x2, =0xFFFFFF\n" + "str w2, [%2, #0x64]\n" + "ldr w2, [%2, #0x10]\n" + /* + * Set l2flushen = 1, etrstallen = 1, + * fpgahsen = 1 and sdrselfrefen = 1 + * in rstmgr.hdsken to perform handshake + * in certain peripherals before trigger + * L2 reset. + */ + "ldr x3, =0x10D\n" + "orr x2, x2, x3\n" + "str w2, [%2, #0x10]\n" + /* Trigger L2 reset in rstmgr.coldmodrst */ + "ldr w2, [%2, #0x34]\n" + "orr x2, x2, #0x100\n" + "isb\n" + "dsb sy\n" + "str w2, [%2, #0x34]\n" + /* Put all cores into WFI mode */ + "1:\n" + " wfi\n" + " b 1b\n" + : : "r" (L2_RESET_DONE_STATUS), + "r" (L2_RESET_DONE_REG), + "r" (SOCFPGA_RSTMGR_ADDRESS), + "r" (GICD_CTRL_ADDRESS) + : "x1", "x2", "x3"); +} + +static void l2_reset_cpu(void) +{ + __l2_reset_cpu(); +} static int socfpga_sysreset_request(struct udevice *dev, enum sysreset_t type) { - puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); - mbox_reset_cold(); + if (type == SYSRESET_WARM) { + /* flush dcache */ + flush_dcache_all(); + + /* request a warm reset */ + puts("Do warm reset now...\n"); + l2_reset_cpu(); + } else { + puts("Mailbox: Issuing mailbox cmd REBOOT_HPS\n"); + mbox_reset_cold(); + } + return -EINPROGRESS; } diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index e48673e6151..8755532ea82 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -18,6 +18,15 @@ /* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ #define CPU_RELEASE_ADDR 0xFFD12210 +/* + * Share sysmgr.boot_scratch_cold6 & 7 (64bit) with VBAR_LE3_BASE_ADDR + * Indicate L2 reset is done. HPS should trigger warm reset via RMR_EL3. + */ +#define L2_RESET_DONE_REG 0xFFD12218 + +/* Magic word to indicate L2 reset is completed */ +#define L2_RESET_DONE_STATUS 0x1228E5E7 + /* * U-Boot console configurations */ -- cgit v1.3.1 From 71916a72f106ed2aaae5a49885fb86623e5f7aec Mon Sep 17 00:00:00 2001 From: Alif Zakuan Yuslaimi Date: Sun, 3 Aug 2025 18:24:45 -0700 Subject: arm: socfpga: soc64: Perform warm reset after L2 reset in SPL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SPL checks for a magic word in the system manager's scratch register to determine if an L2 reset has occurred. If detected, SPL places all slave CPUs (CPU1–3) into WFI mode. The master CPU (CPU0) then initiates a warm reset by writing to the RMR_EL3 system register and also enters WFI mode. This warm reset flow is handled entirely within the HPS. The function `socfpga_sysreset_request()` triggers the warm reset, and upon SPL re-entry, the updated `lowlevel_init_soc64.S` handles the necessary initialization. Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- .../include/mach/system_manager_soc64.h | 2 + arch/arm/mach-socfpga/lowlevel_init_soc64.S | 95 ++++++++++++++++++++++ include/configs/socfpga_soc64_common.h | 5 ++ 3 files changed, 102 insertions(+) (limited to 'include') diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 0871cf949e5..713fa2c517b 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -148,6 +148,8 @@ void populate_sysmgr_pinmux(void); * Bit[30] reserved for FSBL to update the DDR init progress * 1 - means in progress, 0 - haven't started / DDR is up running. * + * Bit[19] store ATF CPU0 ON OFF value. + * * Bit[18] reserved for SDM to configure ACF * Bit[17:1] - Setting by Linux EDAC. * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1) diff --git a/arch/arm/mach-socfpga/lowlevel_init_soc64.S b/arch/arm/mach-socfpga/lowlevel_init_soc64.S index 8926c2d1d9c..b39565f591d 100644 --- a/arch/arm/mach-socfpga/lowlevel_init_soc64.S +++ b/arch/arm/mach-socfpga/lowlevel_init_soc64.S @@ -12,15 +12,110 @@ ENTRY(lowlevel_init) mov x29, lr /* Save LR */ +#ifdef CONFIG_XPL_BUILD + /* Check for L2 reset magic word */ + ldr x4, =L2_RESET_DONE_REG + ldr x5, [x4] + ldr x1, =L2_RESET_DONE_STATUS + cmp x1, x5 + /* No L2 reset, skip warm reset */ + b.ne skipwarmreset + /* Put all slaves CPUs into WFI mode */ + branch_if_slave x0, put_cpu_in_wfi + /* L2 reset completed */ + str xzr, [x4] + /* Clear previous CPU release address */ + ldr x4, =CPU_RELEASE_ADDR + str wzr, [x4] + /* Master CPU (CPU0) request for warm reset */ + mrs x1, rmr_el3 + orr x1, x1, #0x02 + msr rmr_el3, x1 + isb + dsb sy +put_cpu_in_wfi: + wfi + b put_cpu_in_wfi +skipwarmreset: +#endif + #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) #if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF) + + /* + * In ATF flow, need to clear the old CPU address when cold reset + * being triggered, but shouldn't clear CPU address if it is reset + * by CPU-ON, so that the core can correctly jump to ATF code after + * reset by CPU-ON. CPU-ON trigger the reset via mpumodrst. + * + * Hardware will set 1 to core*_irq in mpurststat register in + * reset manager if the core is reset by mpumodrst. + * + * The following code will check the mpurststat to identify if the + * core is reset by mpumodrst, and it will skip CPU address clearing + * if the core is reset by mpumodrst. At last, the code need to clear + * the core*_irq by set it to 1. So that it can reflect the correct + * and latest status in next reset. + */ + + /* Check if it is a master core off/on from kernel using boot scratch + * cold register 8 bit 19. This bit is set by ATF. + */ + ldr x4, =BOOT_SCRATCH_COLD8 + ldr x5, [x4] + and x6, x5, #0x80000 + cbnz x6, wait_for_atf_master + + /* Retrieve mpurststat register in reset manager */ + ldr x4, =SOCFPGA_RSTMGR_ADDRESS + ldr w5, [x4, #0x04] + + /* Set mask based on current core id */ + mrs x0, mpidr_el1 + and x1, x0, #0xF + ldr x2, =0x00000100 + lsl x2, x2, x1 + + /* Skip if core*_irq register is set */ + and x6, x5, x2 + cbnz x6, skip_clear_cpu_address + + /* + * Reach here means core*_irq is 0, means the core is + * reset by cold, warm or watchdog reset. + * Clear previous CPU release address + */ + ldr x4, =CPU_RELEASE_ADDR + str wzr, [x4] + b skip_clear_core_irq + +skip_clear_cpu_address: + /* Clear core*_irq register by writing 1 */ + ldr x4, =SOCFPGA_RSTMGR_ADDRESS + str w2, [x4, #0x04] + +skip_clear_core_irq: + /* Master CPU (CPU0) does not need to wait for atf */ + branch_if_master x0, master_cpu + wait_for_atf: ldr x4, =CPU_RELEASE_ADDR ldr x5, [x4] cbz x5, slave_wait_atf br x5 + slave_wait_atf: branch_if_slave x0, wait_for_atf + +wait_for_atf_master: + ldr x4, =CPU_RELEASE_ADDR + ldr x5, [x4] + cbz x5, master_wait_atf + br x5 +master_wait_atf: + branch_if_master x0, wait_for_atf_master + +master_cpu: #else branch_if_slave x0, 1f #endif diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 8755532ea82..3d09a06f63e 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -24,6 +24,11 @@ */ #define L2_RESET_DONE_REG 0xFFD12218 +/* sysmgr.boot_scratch_cold8 bit 17 (1bit) will be used to check whether CPU0 + * is being powered off/on from kernel + */ +#define BOOT_SCRATCH_COLD8 0xFFD12220 + /* Magic word to indicate L2 reset is completed */ #define L2_RESET_DONE_STATUS 0x1228E5E7 -- cgit v1.3.1 From f64130138aa743e1508f275c56593b85168b53a2 Mon Sep 17 00:00:00 2001 From: Tingting Meng Date: Sun, 3 Aug 2025 18:24:52 -0700 Subject: include: configs: Add config header file for Agilex7 M-series Add config header file for new platform Agilex7 M-series. Signed-off-by: Tingting Meng Signed-off-by: Alif Zakuan Yuslaimi Reviewed-by: Tien Fong Chee --- include/configs/socfpga_agilex7m_socdk.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 include/configs/socfpga_agilex7m_socdk.h (limited to 'include') diff --git a/include/configs/socfpga_agilex7m_socdk.h b/include/configs/socfpga_agilex7m_socdk.h new file mode 100644 index 00000000000..deff70ee67a --- /dev/null +++ b/include/configs/socfpga_agilex7m_socdk.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2025 Altera Corporation + * + */ + +#ifndef __CONFIG_SOCFGPA_AGILEX7M_H__ +#define __CONFIG_SOCFGPA_AGILEX7M_H__ + +#include + +#endif /* __CONFIG_SOCFGPA_AGILEX7M_H__ */ -- cgit v1.3.1