From 2dbe777753927176580dd4121b826241283009cb Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Fri, 26 Feb 2021 15:17:36 +0100 Subject: configs: meson64: add NVME boot target Let's add a boot target for NVMe so we can do a full boot over NVMe. Signed-off-by: Neil Armstrong --- include/configs/meson64.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 7e97f890526..17ebccd2c4b 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -58,6 +58,12 @@ #define BOOT_TARGET_DEVICES_USB(func) #endif +#ifdef CONFIG_CMD_NVME + #define BOOT_TARGET_NVME(func) func(NVME, nvme, 0) +#else + #define BOOT_TARGET_NVME(func) +#endif + #ifndef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ func(ROMUSB, romusb, na) \ @@ -65,6 +71,7 @@ func(MMC, mmc, 1) \ func(MMC, mmc, 2) \ BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_NVME(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) #endif -- cgit v1.3.1 From 0a527fda7821c133ff34132b50e29e2b707db3f0 Mon Sep 17 00:00:00 2001 From: Reinoud Zandijk Date: Wed, 24 Feb 2021 17:44:42 +0100 Subject: Fix IDE commands issued, fix endian issues, fix non MMIO Fixes IDE issues found on the Malta board under Qemu: 1) DMA implied commands were sent to the controller in stead of the PIO variants. The rest of the code is DMA free and written for PIO operation. 2) direct pointer access was used to read and write the registers instead of the inb/inw/outb/outw functions/macros. Registers don't have to be memory mapped and ATA_CURR_BASE() does not have to return an offset from address zero. 3) Endian isues in ide_ident() and reading/writing data in general. Names were corrupted and sizes misreported. Tested malta_defconfig and maltael_defconfig to work again in Qemu. Signed-off-by: Reinoud Zandijk Tested-by: Heinrich Schuchardt --- drivers/block/ide.c | 152 +++++++++++++++------------------------------------- include/ata.h | 2 +- 2 files changed, 44 insertions(+), 110 deletions(-) (limited to 'include') diff --git a/drivers/block/ide.c b/drivers/block/ide.c index 43a0776099c..862a85bc87b 100644 --- a/drivers/block/ide.c +++ b/drivers/block/ide.c @@ -130,56 +130,38 @@ OUT: * ATAPI Support */ -#if defined(CONFIG_IDE_SWAP_IO) /* since ATAPI may use commands with not 4 bytes alligned length * we have our own transfer functions, 2 bytes alligned */ __weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) { + uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG); ushort *dbuf; - volatile ushort *pbuf; - pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG); dbuf = (ushort *)sect_buf; - debug("in output data shorts base for read is %lx\n", - (unsigned long) pbuf); + debug("in output data shorts base for read is %p\n", (void *)paddr); while (shorts--) { EIEIO; - *pbuf = *dbuf++; + outw(cpu_to_le16(*dbuf++), paddr); } } __weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) { + uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG); ushort *dbuf; - volatile ushort *pbuf; - pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG); dbuf = (ushort *)sect_buf; - debug("in input data shorts base for read is %lx\n", - (unsigned long) pbuf); + debug("in input data shorts base for read is %p\n", (void *)paddr); while (shorts--) { EIEIO; - *dbuf++ = *pbuf; + *dbuf++ = le16_to_cpu(inw(paddr)); } } -#else /* ! CONFIG_IDE_SWAP_IO */ -__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts) -{ - outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts); -} - -__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts) -{ - insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts); -} - -#endif /* CONFIG_IDE_SWAP_IO */ - /* * Wait until (Status & mask) == res, or timeout (in ms) * Return last status @@ -636,19 +618,6 @@ static void ide_ident(struct blk_desc *dev_desc) sizeof(dev_desc->vendor)); ident_cpy((unsigned char *)dev_desc->product, iop.serial_no, sizeof(dev_desc->product)); -#ifdef __LITTLE_ENDIAN - /* - * firmware revision, model, and serial number have Big Endian Byte - * order in Word. Convert all three to little endian. - * - * See CF+ and CompactFlash Specification Revision 2.0: - * 6.2.1.6: Identify Drive, Table 39 for more details - */ - - strswab(dev_desc->revision); - strswab(dev_desc->vendor); - strswab(dev_desc->product); -#endif /* __LITTLE_ENDIAN */ if ((iop.config & 0x0080) == 0x0080) dev_desc->removable = 1; @@ -662,26 +631,22 @@ static void ide_ident(struct blk_desc *dev_desc) } #endif /* CONFIG_ATAPI */ -#ifdef __BIG_ENDIAN - /* swap shorts */ - dev_desc->lba = (iop.lba_capacity << 16) | (iop.lba_capacity >> 16); -#else /* ! __BIG_ENDIAN */ - /* - * do not swap shorts on little endian - * - * See CF+ and CompactFlash Specification Revision 2.0: - * 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details. - */ - dev_desc->lba = iop.lba_capacity; -#endif /* __BIG_ENDIAN */ + iop.lba_capacity[0] = be16_to_cpu(iop.lba_capacity[0]); + iop.lba_capacity[1] = be16_to_cpu(iop.lba_capacity[1]); + dev_desc->lba = + ((unsigned long)iop.lba_capacity[0]) | + ((unsigned long)iop.lba_capacity[1] << 16); #ifdef CONFIG_LBA48 if (iop.command_set_2 & 0x0400) { /* LBA 48 support */ dev_desc->lba48 = 1; - dev_desc->lba = (unsigned long long) iop.lba48_capacity[0] | - ((unsigned long long) iop.lba48_capacity[1] << 16) | - ((unsigned long long) iop.lba48_capacity[2] << 32) | - ((unsigned long long) iop.lba48_capacity[3] << 48); + for (int i = 0; i < 4; i++) + iop.lba48_capacity[i] = be16_to_cpu(iop.lba48_capacity[i]); + dev_desc->lba = + ((unsigned long long)iop.lba48_capacity[0] | + ((unsigned long long)iop.lba48_capacity[1] << 16) | + ((unsigned long long)iop.lba48_capacity[2] << 32) | + ((unsigned long long)iop.lba48_capacity[3] << 48)); } else { dev_desc->lba48 = 0; } @@ -846,90 +811,59 @@ void ide_init(void) #endif } -/* We only need to swap data if we are running on a big endian cpu. */ -#if defined(__LITTLE_ENDIAN) __weak void ide_input_swap_data(int dev, ulong *sect_buf, int words) { - ide_input_data(dev, sect_buf, words); -} -#else -__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words) -{ - volatile ushort *pbuf = - (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG); + uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG); ushort *dbuf = (ushort *)sect_buf; - debug("in input swap data base for read is %lx\n", - (unsigned long) pbuf); + debug("in input swap data base for read is %p\n", (void *)paddr); while (words--) { -#ifdef __MIPS__ - *dbuf++ = swab16p((u16 *)pbuf); - *dbuf++ = swab16p((u16 *)pbuf); -#else - *dbuf++ = ld_le16(pbuf); - *dbuf++ = ld_le16(pbuf); -#endif /* !MIPS */ + EIEIO; + *dbuf++ = be16_to_cpu(inw(paddr)); + EIEIO; + *dbuf++ = be16_to_cpu(inw(paddr)); } } -#endif /* __LITTLE_ENDIAN */ - -#if defined(CONFIG_IDE_SWAP_IO) __weak void ide_output_data(int dev, const ulong *sect_buf, int words) { +#if defined(CONFIG_IDE_AHB) + ide_write_data(dev, sect_buf, words); +#else + uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG); ushort *dbuf; - volatile ushort *pbuf; - pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG); dbuf = (ushort *)sect_buf; while (words--) { EIEIO; - *pbuf = *dbuf++; + outw(cpu_to_le16(*dbuf++), paddr); EIEIO; - *pbuf = *dbuf++; + outw(cpu_to_le16(*dbuf++), paddr); } +#endif /* CONFIG_IDE_AHB */ } -#else /* ! CONFIG_IDE_SWAP_IO */ -__weak void ide_output_data(int dev, const ulong *sect_buf, int words) -{ -#if defined(CONFIG_IDE_AHB) - ide_write_data(dev, sect_buf, words); -#else - outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1); -#endif -} -#endif /* CONFIG_IDE_SWAP_IO */ -#if defined(CONFIG_IDE_SWAP_IO) __weak void ide_input_data(int dev, ulong *sect_buf, int words) { +#if defined(CONFIG_IDE_AHB) + ide_read_data(dev, sect_buf, words); +#else + uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG); ushort *dbuf; - volatile ushort *pbuf; - pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG); dbuf = (ushort *)sect_buf; - debug("in input data base for read is %lx\n", (unsigned long) pbuf); + debug("in input data base for read is %p\n", (void *)paddr); while (words--) { EIEIO; - *dbuf++ = *pbuf; + *dbuf++ = le16_to_cpu(inw(paddr)); EIEIO; - *dbuf++ = *pbuf; + *dbuf++ = le16_to_cpu(inw(paddr)); } +#endif /* CONFIG_IDE_AHB */ } -#else /* ! CONFIG_IDE_SWAP_IO */ -__weak void ide_input_data(int dev, ulong *sect_buf, int words) -{ -#if defined(CONFIG_IDE_AHB) - ide_read_data(dev, sect_buf, words); -#else - insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1); -#endif -} - -#endif /* CONFIG_IDE_SWAP_IO */ #ifdef CONFIG_BLK ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt, @@ -1019,14 +953,14 @@ ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt, if (lba48) { ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); - ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT); + ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_READ_EXT); } else #endif { ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device) | ((blknr >> 24) & 0xF)); - ide_outb(device, ATA_COMMAND, ATA_CMD_READ); + ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_READ); } udelay(50); @@ -1116,14 +1050,14 @@ ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt, if (lba48) { ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device)); - ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT); + ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_WRITE_EXT); } else #endif { ide_outb(device, ATA_DEV_HD, ATA_LBA | ATA_DEVICE(device) | ((blknr >> 24) & 0xF)); - ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE); + ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_WRITE); } udelay(50); diff --git a/include/ata.h b/include/ata.h index 3d870c973f2..32ad5f64271 100644 --- a/include/ata.h +++ b/include/ata.h @@ -134,7 +134,7 @@ typedef struct hd_driveid { unsigned short cur_capacity1; /* (2 words, misaligned int) */ unsigned char multsect; /* current multiple sector count */ unsigned char multsect_valid; /* when (bit0==1) multsect is ok */ - unsigned int lba_capacity; /* total number of sectors */ + unsigned short lba_capacity[2];/* two words containing total number of sectors */ unsigned short dma_1word; /* single-word dma info */ unsigned short dma_mword; /* multiple-word dma info */ unsigned short eide_pio_modes; /* bits 0:mode3 1:mode4 */ -- cgit v1.3.1 From ab7f8d18502eda35cef5539b1cf2dbbce9d48c30 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 25 Mar 2021 17:07:32 -0700 Subject: arm: octeontx: move CONFIG_SUPPORT_RAW_INITRD to configs Move CONFIG_SUPPORT_RAW_INITRD out of the octeontx_common header and into the defconfig files. Signed-off-by: Tim Harvey Reviewed-by: Stefan Roese --- configs/octeontx_81xx_defconfig | 1 + configs/octeontx_83xx_defconfig | 1 + include/configs/octeontx_common.h | 2 -- 3 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index f0585a74884..9881c1089b4 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -17,6 +17,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y +CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig index 86b4bc5190b..1fc7f0cb832 100644 --- a/configs/octeontx_83xx_defconfig +++ b/configs/octeontx_83xx_defconfig @@ -15,6 +15,7 @@ CONFIG_DEBUG_UART=y CONFIG_AHCI=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y +CONFIG_SUPPORT_RAW_INITRD=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 810b2bdbd5b..55d329f55e9 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -8,8 +8,6 @@ #ifndef __OCTEONTX_COMMON_H__ #define __OCTEONTX_COMMON_H__ -#define CONFIG_SUPPORT_RAW_INITRD - /** Maximum size of image supported for bootm (and bootable FIT images) */ #define CONFIG_SYS_BOOTM_LEN (256 << 20) -- cgit v1.3.1 From 8bb5a66e5b100b7de1d787a471c117c14743537b Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 25 Mar 2021 17:07:33 -0700 Subject: arm: octeontx: support generic distro config Support Generic Distro Default config Signed-off-by: Tim Harvey Reviewed-by: Stefan Roese --- include/configs/octeontx_common.h | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index 55d329f55e9..434e54442fc 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -8,6 +8,32 @@ #ifndef __OCTEONTX_COMMON_H__ #define __OCTEONTX_COMMON_H__ +#ifdef CONFIG_DISTRO_DEFAULTS +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) \ + func(USB, usb, 0) \ + func(SCSI, scsi, 0) + +#include +/* Extra environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=0\0" \ + "loadaddr=0x20080000\0" \ + "kernel_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x03000000\0" \ + "scriptaddr=0x04000000\0" \ + BOOTENV + +#else + +/** Extra environment settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=20080000\0" \ + "autoload=0\0" + +#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ + /** Maximum size of image supported for bootm (and bootable FIT images) */ #define CONFIG_SYS_BOOTM_LEN (256 << 20) @@ -50,11 +76,6 @@ # define CONFIG_SF_DEFAULT_CS 0 #endif -/** Extra environment settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=20080000\0" \ - "autoload=0\0" - /** Environment defines */ #if defined(CONFIG_ENV_IS_IN_MMC) #define CONFIG_SYS_MMC_ENV_DEV 0 -- cgit v1.3.1 From 84b2cd74f370dabb707e2611bf57714a66d08622 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 12 Apr 2021 01:04:50 +0100 Subject: arm: highbank: Limit FDT and initrd load addresses So far on Highbank/Midway machines U-Boot only ever uses 512MB of DRAM, even though the machines have typically 4GB and 8GB, respectively. That means that so far we didn't need an extra limit for placing the DTB and initrd, as the 512MB are lower than the kernel's limit ("lowmem", typically 768MB). With U-Boot now needing to learn about the actual memory size (to correctly populate the EFI memory map), it might relocate fdt and initrd to the end of DRAM, which is out of reach of the kernel. So add limiting values to the fdt_high and initrd_high environment variables, to prevent U-Boot from using too high addresses. Signed-off-by: Andre Przywara Reviewed-by: Tom Rini --- include/configs/highbank.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/highbank.h b/include/configs/highbank.h index bdbaa475d20..5e3cc3a1db6 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -57,4 +57,8 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x01000000 #define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x20000000\0" \ + "initrd_high=0x20000000\0" + #endif -- cgit v1.3.1 From 109552d773e7aeb0f6417d8245fb0ecf01599ef3 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 12 Apr 2021 01:04:51 +0100 Subject: arm: highbank: Enable OF_CONTROL All Calxeda machines are actually a poster book example of device tree usage: the DT is loaded from flash by the management processor into DRAM, the memory node is populated with the detected DRAM size and this DT is then handed over to the kernel. So it's a shame that U-Boot didn't participate in this chain, but fortunately this is easy to fix: Define CONFIG_OF_CONTROL and CONFIG_OF_BOARD, and provide a trivial function to tell U-Boot about the (fixed) location of the DTB in DRAM. Then enable DM_SERIAL, to let the PL011 driver pick up the UART platform data from the DT. Also define AHCI, to bring this driver into the driver model world as well. Signed-off-by: Andre Przywara --- arch/arm/Kconfig | 9 ++++++++- board/highbank/highbank.c | 10 ++++++++++ configs/highbank_defconfig | 1 + include/configs/highbank.h | 1 - 4 files changed, 19 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 15b845449db..358642669c7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -711,7 +711,14 @@ config ARCH_S5PC1XX config ARCH_HIGHBANK bool "Calxeda Highbank" select CPU_V7A - select PL011_SERIAL + select PL01X_SERIAL + select DM + select DM_SERIAL + select OF_CONTROL + select OF_BOARD + select CLK + select CLK_CCF + select AHCI config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 906bd9b6dda..2e2300a307f 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -119,6 +119,16 @@ int ft_board_setup(void *fdt, struct bd_info *bd) } #endif +void *board_fdt_blob_setup(void) +{ + /* + * The ECME management processor loads the DTB from NOR flash + * into DRAM (at 4KB), where it gets patched to contain the + * detected memory size. + */ + return (void *)0x1000; +} + static int is_highbank(void) { uint32_t midr; diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig index 369b65ceee8..773ed7a00bf 100644 --- a/configs/highbank_defconfig +++ b/configs/highbank_defconfig @@ -26,3 +26,4 @@ CONFIG_BOOTCOUNT_LIMIT=y CONFIG_SCSI=y CONFIG_CONS_INDEX=0 CONFIG_OF_LIBFDT=y +CONFIG_OF_BOARD=y diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 5e3cc3a1db6..7f37c81fc9f 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -18,7 +18,6 @@ #define CONFIG_SYS_MALLOC_LEN (512 * 1024) #define CONFIG_PL011_CLOCK 150000000 -#define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) } #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ -- cgit v1.3.1 From debb07bf107a9feb3cbf03db6b10abae466e4d41 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 12 Apr 2021 01:04:52 +0100 Subject: net: calxedagmac: Convert to DM_ETH To squash that nasty warning message and make better use of the newly gained OF_CONTROL feature, let's convert the calxedagmac driver to the "new" driver model. The conversion is pretty straight forward, mostly just adjusting the use of the involved data structures. The only actual change is the required split of the receive routine into a receive and free_pkt part. Also this allows us to get rid of the hardcoded platform information and explicit init calls. This also uses the opportunity to wrap the code decoding the MMIO register base address, to make it safe for using PHYS_64BIT later. Signed-off-by: Andre Przywara Reviewed-by: Ramon Fried --- arch/arm/Kconfig | 1 + board/highbank/highbank.c | 13 --- configs/highbank_defconfig | 1 + drivers/net/Kconfig | 7 ++ drivers/net/calxedaxgmac.c | 192 ++++++++++++++++++++++++++++--------------- include/configs/highbank.h | 2 - include/netdev.h | 1 - scripts/config_whitelist.txt | 1 - 8 files changed, 137 insertions(+), 81 deletions(-) (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 358642669c7..e9f72b155ca 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -719,6 +719,7 @@ config ARCH_HIGHBANK select CLK select CLK_CCF select AHCI + select DM_ETH config ARCH_INTEGRATOR bool "ARM Ltd. Integrator family" diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 2e2300a307f..0667a48965c 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include @@ -52,18 +51,6 @@ int board_init(void) return 0; } -/* We know all the init functions have been run now */ -int board_eth_init(struct bd_info *bis) -{ - int rc = 0; - -#ifdef CONFIG_CALXEDA_XGMAC - rc += calxedaxgmac_initialize(0, 0xfff50000); - rc += calxedaxgmac_initialize(1, 0xfff51000); -#endif - return rc; -} - #ifdef CONFIG_SCSI_AHCI_PLAT void scsi_init(void) { diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig index 773ed7a00bf..c3352b827d7 100644 --- a/configs/highbank_defconfig +++ b/configs/highbank_defconfig @@ -27,3 +27,4 @@ CONFIG_SCSI=y CONFIG_CONS_INDEX=0 CONFIG_OF_LIBFDT=y CONFIG_OF_BOARD=y +CONFIG_CALXEDA_XGMAC=y diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 72822eaec4b..382639044bf 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -180,6 +180,13 @@ config CORTINA_NI_ENET This driver supports the Cortina-Access Ethernet MAC for all supported CAxxxx SoCs. +config CALXEDA_XGMAC + bool "Calxeda XGMAC support" + depends on DM_ETH + help + This driver supports the XGMAC in Calxeda Highbank and Midway + machines. + config DWC_ETH_QOS bool "Synopsys DWC Ethernet QOS device support" depends on DM_ETH diff --git a/drivers/net/calxedaxgmac.c b/drivers/net/calxedaxgmac.c index 8b2ee49b441..b98d709117a 100644 --- a/drivers/net/calxedaxgmac.c +++ b/drivers/net/calxedaxgmac.c @@ -10,6 +10,8 @@ #include #include #include +#include +#include /* for dev_set_priv() */ #define TX_NUM_DESC 1 #define RX_NUM_DESC 32 @@ -212,6 +214,18 @@ struct xgmac_dma_desc { __le32 res[3]; }; +static struct xgmac_regs *xgmac_get_regs(struct eth_pdata *pdata) +{ + /* + * We use PHYS_64BIT on Highbank, so phys_addr_t is bigger than + * a pointer. U-Boot doesn't use LPAE (not even the MMU on highbank), + * so we can't access anything above 4GB. + * We have a check in the probe function below the ensure this, + * so casting to a 32-bit pointer type is fine here. + */ + return (struct xgmac_regs *)(uintptr_t)pdata->iobase; +} + /* XGMAC Descriptor Access Helpers */ static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz) { @@ -304,8 +318,6 @@ struct calxeda_eth_dev { u32 tx_currdesc; u32 rx_currdesc; - - struct eth_device *dev; } __aligned(32); /* @@ -313,10 +325,10 @@ struct calxeda_eth_dev { * advanced descriptors. */ -static void init_rx_desc(struct calxeda_eth_dev *priv) +static void init_rx_desc(struct eth_pdata *pdata, struct calxeda_eth_dev *priv) { struct xgmac_dma_desc *rxdesc = priv->rx_chain; - struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase; + struct xgmac_regs *regs = xgmac_get_regs(pdata); void *rxbuffer = priv->rxbuffer; int i; @@ -330,17 +342,16 @@ static void init_rx_desc(struct calxeda_eth_dev *priv) } } -static void init_tx_desc(struct calxeda_eth_dev *priv) +static void init_tx_desc(struct eth_pdata *pdata, struct calxeda_eth_dev *priv) { - struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase; + struct xgmac_regs *regs = xgmac_get_regs(pdata); desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC); writel((ulong)priv->tx_chain, ®s->txdesclist); } -static int xgmac_reset(struct eth_device *dev) +static int xgmac_reset(struct xgmac_regs *regs) { - struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; int timeout = MAC_TIMEOUT; u32 value; @@ -356,27 +367,28 @@ static int xgmac_reset(struct eth_device *dev) return timeout; } -static void xgmac_hwmacaddr(struct eth_device *dev) +static void xgmac_hwmacaddr(struct eth_pdata *pdata) { - struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; + struct xgmac_regs *regs = xgmac_get_regs(pdata); u32 macaddr[2]; - memcpy(macaddr, dev->enetaddr, 6); + memcpy(macaddr, pdata->enetaddr, ARP_HLEN); writel(macaddr[1], ®s->macaddr[0].hi); writel(macaddr[0], ®s->macaddr[0].lo); } -static int xgmac_init(struct eth_device *dev, struct bd_info * bis) +static int xgmac_eth_start(struct udevice *dev) { - struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; - struct calxeda_eth_dev *priv = dev->priv; - int value; + struct eth_pdata *pdata = dev_get_plat(dev); + struct xgmac_regs *regs = xgmac_get_regs(pdata); + struct calxeda_eth_dev *priv = dev_get_priv(dev); + u32 value; - if (xgmac_reset(dev) < 0) - return -1; + if (xgmac_reset(regs) < 0) + return -ETIMEDOUT; /* set the hardware MAC address */ - xgmac_hwmacaddr(dev); + xgmac_hwmacaddr(pdata); /* set the AXI bus modes */ value = XGMAC_DMA_BUSMODE_ATDS | @@ -401,8 +413,8 @@ static int xgmac_init(struct eth_device *dev, struct bd_info * bis) writel(value, ®s->flow_control); /* Initialize the descriptor chains */ - init_rx_desc(priv); - init_tx_desc(priv); + init_rx_desc(pdata, priv); + init_tx_desc(pdata, priv); /* must set to 0, or when started up will cause issues */ priv->tx_currdesc = 0; @@ -425,10 +437,11 @@ static int xgmac_init(struct eth_device *dev, struct bd_info * bis) return 0; } -static int xgmac_tx(struct eth_device *dev, void *packet, int length) +static int xgmac_tx(struct udevice *dev, void *packet, int length) { - struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; - struct calxeda_eth_dev *priv = dev->priv; + struct calxeda_eth_dev *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + struct xgmac_regs *regs = xgmac_get_regs(pdata); u32 currdesc = priv->tx_currdesc; struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc]; int timeout; @@ -453,35 +466,45 @@ static int xgmac_tx(struct eth_device *dev, void *packet, int length) return 0; } -static int xgmac_rx(struct eth_device *dev) +static int xgmac_rx(struct udevice *dev, int flags, uchar **packetp) { - struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; - struct calxeda_eth_dev *priv = dev->priv; + struct calxeda_eth_dev *priv = dev_get_priv(dev); u32 currdesc = priv->rx_currdesc; struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc]; int length = 0; /* check if the host has the desc */ if (desc_get_owner(rxdesc)) - return -1; /* something bad happened */ + return -EAGAIN; /* the MAC is still chewing on it */ length = desc_get_rx_frame_len(rxdesc); + *packetp = desc_get_buf_addr(rxdesc); - net_process_received_packet(desc_get_buf_addr(rxdesc), length); + priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1); + + return length; +} + +static int xgmac_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct xgmac_regs *regs = xgmac_get_regs(pdata); + struct calxeda_eth_dev *priv = dev_get_priv(dev); + u32 rxdesc = ((char *)packet - priv->rxbuffer) / ETH_BUF_SZ; + struct xgmac_dma_desc *p = &priv->rx_chain[rxdesc]; /* set descriptor back to owned by XGMAC */ - desc_set_rx_owner(rxdesc); + desc_set_rx_owner(p); writel(1, ®s->rxpoll); - priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1); - - return length; + return 0; } -static void xgmac_halt(struct eth_device *dev) +static void xgmac_eth_stop(struct udevice *dev) { - struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase; - struct calxeda_eth_dev *priv = dev->priv; + struct calxeda_eth_dev *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_plat(dev); + struct xgmac_regs *regs = xgmac_get_regs(pdata); int value; /* Disable TX/RX */ @@ -499,47 +522,88 @@ static void xgmac_halt(struct eth_device *dev) priv->rx_currdesc = 0; } -int calxedaxgmac_initialize(u32 id, ulong base_addr) +/* + * Changing the MAC address is not a good idea, as the fabric would + * need to know about this as well (it does not learn MAC addresses). + */ +static int xgmac_eth_write_hwaddr(struct udevice *dev) +{ + return -ENOSYS; +} + +static int xgmac_eth_read_rom_hwaddr(struct udevice *dev) { - struct eth_device *dev; - struct calxeda_eth_dev *priv; - struct xgmac_regs *regs; + struct eth_pdata *pdata = dev_get_plat(dev); + struct xgmac_regs *regs = xgmac_get_regs(pdata); u32 macaddr[2]; - regs = (struct xgmac_regs *)base_addr; + /* The MAC address is already configured, so read it from registers. */ + macaddr[1] = readl(®s->macaddr[0].hi); + macaddr[0] = readl(®s->macaddr[0].lo); + memcpy(pdata->enetaddr, macaddr, ARP_HLEN); - /* check hardware version */ - if (readl(®s->version) != 0x1012) - return -1; + return 0; +} - dev = malloc(sizeof(*dev)); - if (!dev) - return 0; - memset(dev, 0, sizeof(*dev)); +static int xgmac_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct calxeda_eth_dev *priv; /* Structure must be aligned, because it contains the descriptors */ priv = memalign(32, sizeof(*priv)); - if (!priv) { - free(dev); - return 0; + if (!priv) + return -ENOMEM; + dev_set_priv(dev, priv); + + pdata->iobase = devfdt_get_addr(dev); + if (pdata->iobase == FDT_ADDR_T_NONE) { + printf("%s: Cannot find XGMAC base address\n", __func__); + return -EINVAL; + } + if (pdata->iobase >= (1ULL << 32)) { + printf("%s: MMIO base address cannot be above 4GB\n", __func__); + return -EINVAL; } - dev->iobase = (int)base_addr; - dev->priv = priv; - priv->dev = dev; - sprintf(dev->name, "xgmac%d", id); + return 0; +} - /* The MAC address is already configured, so read it from registers. */ - macaddr[1] = readl(®s->macaddr[0].hi); - macaddr[0] = readl(®s->macaddr[0].lo); - memcpy(dev->enetaddr, macaddr, 6); +static int xgmac_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_plat(dev); + struct xgmac_regs *regs = xgmac_get_regs(pdata); - dev->init = xgmac_init; - dev->send = xgmac_tx; - dev->recv = xgmac_rx; - dev->halt = xgmac_halt; + /* check hardware version */ + if (readl(®s->version) != 0x1012) + return -ENODEV; - eth_register(dev); + xgmac_eth_read_rom_hwaddr(dev); - return 1; + return 0; } + +static const struct eth_ops xgmac_eth_ops = { + .start = xgmac_eth_start, + .send = xgmac_tx, + .recv = xgmac_rx, + .free_pkt = xgmac_free_pkt, + .stop = xgmac_eth_stop, + .write_hwaddr = xgmac_eth_write_hwaddr, + .read_rom_hwaddr = xgmac_eth_read_rom_hwaddr, +}; + +static const struct udevice_id xgmac_eth_ids[] = { + { .compatible = "calxeda,hb-xgmac" }, + { } +}; + +U_BOOT_DRIVER(eth_xgmac) = { + .name = "eth_xgmac", + .id = UCLASS_ETH, + .of_match = xgmac_eth_ids, + .of_to_plat = xgmac_ofdata_to_platdata, + .probe = xgmac_eth_probe, + .ops = &xgmac_eth_ops, + .plat_auto = sizeof(struct eth_pdata), +}; diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 7f37c81fc9f..fbd26ddd0fc 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -27,8 +27,6 @@ #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ CONFIG_SYS_SCSI_MAX_LUN) -#define CONFIG_CALXEDA_XGMAC - #define CONFIG_BOOT_RETRY_TIME -1 #define CONFIG_RESET_TO_RETRY diff --git a/include/netdev.h b/include/netdev.h index 0ad9f8dc3a5..b960c421063 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -33,7 +33,6 @@ int at91emac_register(struct bd_info *bis, unsigned long iobase); int ax88180_initialize(struct bd_info *bis); int bcm_sf2_eth_register(struct bd_info *bis, u8 dev_num); int bfin_EMAC_initialize(struct bd_info *bis); -int calxedaxgmac_initialize(u32 id, ulong base_addr); int cs8900_initialize(u8 dev_num, int base_addr); int dc21x4x_initialize(struct bd_info *bis); int designware_initialize(ulong base_addr, u32 interface); diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index b24fa36da0f..a2fcafd2e6c 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -149,7 +149,6 @@ CONFIG_BTB CONFIG_BUFNO_AUTO_INCR_BIT CONFIG_BUILD_ENVCRC CONFIG_BUS_WIDTH -CONFIG_CALXEDA_XGMAC CONFIG_CDP_APPLIANCE_VLAN_TYPE CONFIG_CDP_CAPABILITIES CONFIG_CDP_DEVICE_ID -- cgit v1.3.1 From ff47d539f28bcae15bc680d2e32fec6cc9551eb4 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 12 Apr 2021 01:04:53 +0100 Subject: arm: highbank: Remove artificial SDRAM size So far we were defining a somewhat confusing PHYS_SDRAM_1_SIZE variable, which originally was only used for setting the memtest boundaries. This definition in highbank.h has been removed about a year ago (moved to Kconfig), so we also don't need the hard-coded size definition any longer. Get rid of the misleading memory size definition, which was actually wrong anyway (it's 4088 MB for those machines with just 4GB of DRAM). Signed-off-by: Andre Przywara --- include/configs/highbank.h | 6 ------ 1 file changed, 6 deletions(-) (limited to 'include') diff --git a/include/configs/highbank.h b/include/configs/highbank.h index fbd26ddd0fc..ff92c4f5540 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -39,12 +39,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x800000 #define CONFIG_SYS_64BIT_LBA -/*----------------------------------------------------------------------- - * Physical Memory Map - * The DRAM is already setup, so do not touch the DT node later. - */ -#define PHYS_SDRAM_1_SIZE (4089 << 20) - /* Environment data setup */ #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */ -- cgit v1.3.1 From 56a3433ef559512e731a943d8af7965973d090df Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 19 Apr 2021 16:18:49 -0400 Subject: sysinfo.h: Add re-inclusion guard Add #ifndef __SYSINFO_H__ ... #endif to prevent re-inclusion of this file. Signed-off-by: Tom Rini --- include/sysinfo.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/sysinfo.h b/include/sysinfo.h index 68fad25a065..8054d4d4a1f 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -4,6 +4,9 @@ * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc */ +#ifndef __SYSINFO_H__ +#define __SYSINFO_H__ + struct udevice; /* @@ -228,3 +231,4 @@ static inline int sysinfo_get_fit_loadable(struct udevice *dev, int index, } #endif +#endif -- cgit v1.3.1 From 2963d606bc6bbaf7b097ec8a42abec7f71339a9d Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Thu, 1 Apr 2021 02:01:52 +0300 Subject: psci: add v1.0/v1.1 definitions from Linux Sync and add PSCI API versions 1.0/1.1 definitions from Linux. Signed-off-by: Igor Opaniuk --- include/linux/psci.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'include') diff --git a/include/linux/psci.h b/include/linux/psci.h index 841dbc8da7e..38edde31370 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -46,6 +46,14 @@ #define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5) #define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7) +#define PSCI_1_0_FN_PSCI_FEATURES PSCI_0_2_FN(10) +#define PSCI_1_0_FN_SYSTEM_SUSPEND PSCI_0_2_FN(14) +#define PSCI_1_0_FN_SET_SUSPEND_MODE PSCI_0_2_FN(15) +#define PSCI_1_1_FN_SYSTEM_RESET2 PSCI_0_2_FN(18) + +#define PSCI_1_0_FN64_SYSTEM_SUSPEND PSCI_0_2_FN64(14) +#define PSCI_1_1_FN64_SYSTEM_RESET2 PSCI_0_2_FN64(18) + /* PSCI v0.2 power state encoding for CPU_SUSPEND function */ #define PSCI_0_2_POWER_STATE_ID_MASK 0xffff #define PSCI_0_2_POWER_STATE_ID_SHIFT 0 @@ -56,6 +64,13 @@ #define PSCI_0_2_POWER_STATE_AFFL_MASK \ (0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) +/* PSCI extended power state encoding for CPU_SUSPEND function */ +#define PSCI_1_0_EXT_POWER_STATE_ID_MASK 0xfffffff +#define PSCI_1_0_EXT_POWER_STATE_ID_SHIFT 0 +#define PSCI_1_0_EXT_POWER_STATE_TYPE_SHIFT 30 +#define PSCI_1_0_EXT_POWER_STATE_TYPE_MASK \ + (0x1 << PSCI_1_0_EXT_POWER_STATE_TYPE_SHIFT) + /* PSCI v0.2 affinity level state returned by AFFINITY_INFO */ #define PSCI_0_2_AFFINITY_LEVEL_ON 0 #define PSCI_0_2_AFFINITY_LEVEL_OFF 1 @@ -75,6 +90,18 @@ (((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT) #define PSCI_VERSION_MINOR(ver) \ ((ver) & PSCI_VERSION_MINOR_MASK) +#define PSCI_VERSION(maj, min) \ + ((((maj) << PSCI_VERSION_MAJOR_SHIFT) & PSCI_VERSION_MAJOR_MASK) | \ + ((min) & PSCI_VERSION_MINOR_MASK)) + +/* PSCI features decoding (>=1.0) */ +#define PSCI_1_0_FEATURES_CPU_SUSPEND_PF_SHIFT 1 +#define PSCI_1_0_FEATURES_CPU_SUSPEND_PF_MASK \ + (0x1 << PSCI_1_0_FEATURES_CPU_SUSPEND_PF_SHIFT) + +#define PSCI_1_0_OS_INITIATED BIT(0) +#define PSCI_1_0_SUSPEND_MODE_PC 0 +#define PSCI_1_0_SUSPEND_MODE_OSI 1 /* PSCI return values (inclusive of all PSCI versions) */ #define PSCI_RET_SUCCESS 0 @@ -86,6 +113,7 @@ #define PSCI_RET_INTERNAL_FAILURE -6 #define PSCI_RET_NOT_PRESENT -7 #define PSCI_RET_DISABLED -8 +#define PSCI_RET_INVALID_ADDRESS -9 #ifdef CONFIG_ARM_PSCI_FW unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1, -- cgit v1.3.1 From b7135b034f9f19a89516bb53535891e14a545395 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Thu, 1 Apr 2021 02:01:53 +0300 Subject: psci: add features/reset2 support Adds support for: * PSCI_FEATURES, which was introduced in PSCI 1.0. This provides API that allows discovering whether a specific PSCI function is implemented and its features. * SYSTEM_RESET2, which was introduced in PSCI 1.1, which extends existing SYSTEM_RESET. It provides support for vendor-specific resets, providing reset_type as an additional param. For additional details visit [1]. Implementations of some functions were borrowed from Linux PSCI driver code [2]. [1] https://developer.arm.com/documentation/den0022/latest/ [2] drivers/firmware/psci/psci.c Signed-off-by: Igor Opaniuk --- drivers/firmware/psci.c | 68 +++++++++++++++++++++++++++++++++++++++++++++++++ include/linux/psci.h | 3 +++ 2 files changed, 71 insertions(+) (limited to 'include') diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index 68953cc4f4e..be57552aba0 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -26,6 +27,18 @@ #define PSCI_METHOD_HVC 1 #define PSCI_METHOD_SMC 2 +/* + * While a 64-bit OS can make calls with SMC32 calling conventions, for some + * calls it is necessary to use SMC64 to pass or return 64-bit values. + * For such calls PSCI_FN_NATIVE(version, name) will choose the appropriate + * (native-width) function ID. + */ +#if defined(CONFIG_ARM64) +#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name +#else +#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN_##name +#endif + #if CONFIG_IS_ENABLED(EFI_LOADER) int __efi_runtime_data psci_method; #else @@ -53,6 +66,34 @@ unsigned long __efi_runtime invoke_psci_fn return res.a0; } +static int psci_features(u32 psci_func_id) +{ + return invoke_psci_fn(PSCI_1_0_FN_PSCI_FEATURES, + psci_func_id, 0, 0); +} + +static u32 psci_0_2_get_version(void) +{ + return invoke_psci_fn(PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0); +} + +static bool psci_is_system_reset2_supported(void) +{ + int ret; + u32 ver; + + ver = psci_0_2_get_version(); + + if (PSCI_VERSION_MAJOR(ver) >= 1) { + ret = psci_features(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2)); + + if (ret != PSCI_RET_NOT_SUPPORTED) + return true; + } + + return false; +} + static int psci_bind(struct udevice *dev) { /* No SYSTEM_RESET support for PSCI 0.1 */ @@ -141,6 +182,33 @@ void reset_misc(void) } #endif /* CONFIG_PSCI_RESET */ +void psci_sys_reset(u32 type) +{ + bool reset2_supported; + + do_psci_probe(); + + reset2_supported = psci_is_system_reset2_supported(); + + if (type == SYSRESET_WARM && reset2_supported) { + /* + * reset_type[31] = 0 (architectural) + * reset_type[30:0] = 0 (SYSTEM_WARM_RESET) + * cookie = 0 (ignored by the implementation) + */ + invoke_psci_fn(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2), 0, 0, 0); + } else { + invoke_psci_fn(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0); + } +} + +void psci_sys_poweroff(void) +{ + do_psci_probe(); + + invoke_psci_fn(PSCI_0_2_FN_SYSTEM_OFF, 0, 0, 0); +} + #ifdef CONFIG_CMD_POWEROFF int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { diff --git a/include/linux/psci.h b/include/linux/psci.h index 38edde31370..c78c1079a82 100644 --- a/include/linux/psci.h +++ b/include/linux/psci.h @@ -118,6 +118,9 @@ #ifdef CONFIG_ARM_PSCI_FW unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3); +void psci_sys_reset(u32 type); +void psci_sys_poweroff(void); + #else static inline unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3) -- cgit v1.3.1