From 898cc1365c1adedeaf033838ab9e767c4dcdcdcf Mon Sep 17 00:00:00 2001 From: Ryder Lee Date: Thu, 22 Aug 2019 12:26:52 +0200 Subject: arm: dts: split mtk-reset.h into per-chip header This follows the linux header rules to avoid conflict bitfields. Tested-by: Frank Wunderlich Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- include/dt-bindings/reset/mt7623-reset.h | 25 ++++++++++++++++++++++ include/dt-bindings/reset/mt7629-reset.h | 36 ++++++++++++++++++++++++++++++++ include/dt-bindings/reset/mtk-reset.h | 27 ------------------------ 3 files changed, 61 insertions(+), 27 deletions(-) create mode 100644 include/dt-bindings/reset/mt7623-reset.h create mode 100644 include/dt-bindings/reset/mt7629-reset.h delete mode 100644 include/dt-bindings/reset/mtk-reset.h (limited to 'include') diff --git a/include/dt-bindings/reset/mt7623-reset.h b/include/dt-bindings/reset/mt7623-reset.h new file mode 100644 index 00000000000..a859a5b26a4 --- /dev/null +++ b/include/dt-bindings/reset/mt7623-reset.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MTK_RESET_H_ +#define _DT_BINDINGS_MTK_RESET_H_ + +/* ETHSYS resets */ +#define ETHSYS_PPE_RST 31 +#define ETHSYS_GMAC_RST 23 +#define ETHSYS_FE_RST 6 +#define ETHSYS_MCM_RST 2 +#define ETHSYS_SYS_RST 0 + +/* HIFSYS resets */ +#define HIFSYS_PCIE2_RST 26 +#define HIFSYS_PCIE1_RST 25 +#define HIFSYS_PCIE0_RST 24 +#define HIFSYS_UPHY1_RST 22 +#define HIFSYS_UPHY0_RST 21 +#define HIFSYS_UHOST1_RST 4 +#define HIFSYS_UHOST0_RST 3 + +#endif /* _DT_BINDINGS_MTK_RESET_H_ */ diff --git a/include/dt-bindings/reset/mt7629-reset.h b/include/dt-bindings/reset/mt7629-reset.h new file mode 100644 index 00000000000..8f1634f7a65 --- /dev/null +++ b/include/dt-bindings/reset/mt7629-reset.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MTK_RESET_H_ +#define _DT_BINDINGS_MTK_RESET_H_ + +/* PCIe Subsystem resets */ +#define PCIE1_CORE_RST 19 +#define PCIE1_MMIO_RST 20 +#define PCIE1_HRST 21 +#define PCIE1_USER_RST 22 +#define PCIE1_PIPE_RST 23 +#define PCIE0_CORE_RST 27 +#define PCIE0_MMIO_RST 28 +#define PCIE0_HRST 29 +#define PCIE0_USER_RST 30 +#define PCIE0_PIPE_RST 31 + +/* SSUSB Subsystem resets */ +#define SSUSB_PHY_PWR_RST 3 +#define SSUSB_MAC_PWR_RST 4 + +/* ETH Subsystem resets */ +#define ETHSYS_SYS_RST 0 +#define ETHSYS_MCM_RST 2 +#define ETHSYS_HSDMA_RST 5 +#define ETHSYS_FE_RST 6 +#define ETHSYS_ESW_RST 16 +#define ETHSYS_GMAC_RST 23 +#define ETHSYS_EPHY_RST 24 +#define ETHSYS_CRYPTO_RST 29 +#define ETHSYS_PPE_RST 31 + +#endif /* _DT_BINDINGS_MTK_RESET_H_ */ diff --git a/include/dt-bindings/reset/mtk-reset.h b/include/dt-bindings/reset/mtk-reset.h deleted file mode 100644 index 78fcdab009d..00000000000 --- a/include/dt-bindings/reset/mtk-reset.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018 MediaTek Inc. - */ - -#ifndef _DT_BINDINGS_MTK_RESET_H_ -#define _DT_BINDINGS_MTK_RESET_H_ - -/* ETHSYS */ -#define ETHSYS_PPE_RST 31 -#define ETHSYS_EPHY_RST 24 -#define ETHSYS_GMAC_RST 23 -#define ETHSYS_ESW_RST 16 -#define ETHSYS_FE_RST 6 -#define ETHSYS_MCM_RST 2 -#define ETHSYS_SYS_RST 0 - -/* HIFSYS resets */ -#define HIFSYS_PCIE2_RST 26 -#define HIFSYS_PCIE1_RST 25 -#define HIFSYS_PCIE0_RST 24 -#define HIFSYS_UPHY1_RST 22 -#define HIFSYS_UPHY0_RST 21 -#define HIFSYS_UHOST1_RST 4 -#define HIFSYS_UHOST0_RST 3 - -#endif /* _DT_BINDINGS_MTK_RESET_H_ */ -- cgit v1.2.3