From b416df33c9701955752a8ba22c1cf46ee6465ef6 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Fri, 22 Apr 2022 13:50:06 +0530 Subject: configs: Layerscape: Remove the 'fdt_addr' env On Layerscape platforms, the DTB is loaded from boot filesystem, per the fdt_addr description in doc/README.distro, it must be removed. Signed-off-by: Hou Zhiqiang [Rebased] Signed-off-by: Priyanka Jain --- include/configs/ls1012a2g5rdb.h | 1 - include/configs/ls1012afrdm.h | 2 +- include/configs/ls1012afrwy.h | 1 - include/configs/ls1012aqds.h | 1 - include/configs/ls1012ardb.h | 1 - include/configs/ls1021atsn.h | 1 - include/configs/ls1021atwr.h | 4 +--- include/configs/ls1028aqds.h | 3 +-- include/configs/ls1028ardb.h | 3 +-- include/configs/ls1043a_common.h | 1 - include/configs/ls1046a_common.h | 1 - include/configs/ls1088ardb.h | 2 -- include/configs/ls2080ardb.h | 2 -- include/configs/lx2160a_common.h | 1 - 14 files changed, 4 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 835eca7726d..f0248e64646 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -19,7 +19,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "kernelheader_addr=0x800000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index 44518cdf641..cb79d6362fc 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2021 NXP */ #ifndef __LS1012ARDB_H__ @@ -21,7 +22,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "fdt_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "scriptaddr=0x80000000\0" \ "fdtheader_addr_r=0x80100000\0" \ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 16ce89233fb..a1d23b64630 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -35,7 +35,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "kernel_size_sd=0x16000\0" \ "kernelhdr_size_sd=0x10\0" \ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h index e7a0294644c..b5992366cf4 100644 --- a/include/configs/ls1012aqds.h +++ b/include/configs/ls1012aqds.h @@ -89,7 +89,6 @@ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "kernelheader_addr=0x600000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 2490ba3212a..c57b598d70d 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -44,7 +44,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "kernelheader_addr=0x600000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 546c4fcdb95..09168a28e7d 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -114,7 +114,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ "initrd_high=0xffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "kernelheader_addr=0x60800000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index b4383d4bbdb..b36c8dccf17 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2014 Freescale Semiconductor, Inc. - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ #ifndef __CONFIG_H @@ -209,7 +209,6 @@ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \ "cma=64M@0x0-0xb0000000\0" \ "initrd_high=0xffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x65000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ @@ -266,7 +265,6 @@ "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \ "cma=64M@0x0-0xb0000000\0" \ "initrd_high=0xffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "kernelheader_addr=0x60800000\0" \ "scriptaddr=0x80000000\0" \ diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h index b9c05943ec2..35363ccda1a 100644 --- a/include/configs/ls1028aqds.h +++ b/include/configs/ls1028aqds.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP */ #ifndef __LS1028A_QDS_H @@ -68,7 +68,6 @@ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 15ac1f565e4..91223789b83 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright 2019 NXP + * Copyright 2019, 2021 NXP */ #ifndef __LS1028A_RDB_H @@ -64,7 +64,6 @@ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ "bootm_size=0x10000000\0" \ - "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 61c6d456764..26db8ffe7e2 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -173,7 +173,6 @@ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index f9279e4ab46..fb2011aa559 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -165,7 +165,6 @@ "ramdisk_addr=0x800000\0" \ "ramdisk_size=0x2000000\0" \ "bootm_size=0x10000000\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x61000000\0" \ "scriptaddr=0x80000000\0" \ "scripthdraddr=0x80080000\0" \ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 693a2f64b6c..c69003018bf 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -271,7 +271,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x1000000\0" \ "kernel_addr_sd=0x8000\0" \ "kernelhdr_addr_sd=0x3000\0" \ @@ -340,7 +339,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x1000000\0" \ "kernel_addr_sd=0x8000\0" \ "kernelhdr_addr_sd=0x3000\0" \ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index de269f4c7ed..52a48bd4b89 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -323,7 +323,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x581000000\0" \ "kernel_start=0x1000000\0" \ "kernelheader_start=0x800000\0" \ @@ -386,7 +385,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_addr=0x581000000\0" \ "kernel_start=0x1000000\0" \ "kernelheader_start=0x600000\0" \ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index d5690148195..aaba8fc26d9 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -164,7 +164,6 @@ "ramdisk_size=0x2000000\0" \ "fdt_high=0xa0000000\0" \ "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ "kernel_start=0x1000000\0" \ "kernelheader_start=0x600000\0" \ "scriptaddr=0x80000000\0" \ -- cgit v1.2.3 From 44564e79eb2eac4b38f5493748018906e7239e2e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 4 Apr 2022 18:32:13 +0200 Subject: mmc: fsl_esdhc: Define macro ESDHCCTL_SNOOP for Snoop attribute MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- include/fsl_esdhc.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index f86afe5dad8..7ab1460abc6 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -76,6 +76,7 @@ /* eSDHC control register */ #define ESDHCCTL 0x0002e40c +#define ESDHCCTL_SNOOP (0x00000040) #define ESDHCCTL_PCS (0x00080000) #define ESDHCCTL_FAF (0x00040000) -- cgit v1.2.3 From ab37df9d221e12adf709c7391c001b9dd5d33606 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 25 Apr 2022 14:21:20 +0530 Subject: powerpc: mpc85xx: Remove duplicate u-boot-nand.lds Signed-off-by: Priyanka Jain --- include/configs/P1010RDB.h | 4 ++++ include/configs/T102xRDB.h | 3 +++ include/configs/T104xRDB.h | 3 +++ include/configs/T208xQDS.h | 3 +++ include/configs/T208xRDB.h | 3 +++ include/configs/p1_p2_rdb_pc.h | 4 ++++ 6 files changed, 20 insertions(+) (limited to 'include') diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 0d8f13eeb06..0c19b92940e 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -81,6 +81,10 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 +#else +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_TPL_PAD_TO 0x20000 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index bedd931b186..e7cc39e78a9 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -36,6 +36,9 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 8ef6068cb91..de31f695c60 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -40,6 +40,9 @@ #endif #define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 #define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 5a338f743a3..82e0fc46c7b 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -44,6 +44,9 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 3c13905729a..94385443253 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -39,6 +39,9 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif #ifdef CONFIG_SPIFLASH diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 17b9021fbf8..81dc0177c0c 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -111,6 +111,10 @@ #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 +#else +#ifndef CONFIG_MPC85XX_HAVE_RESET_VECTOR +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#endif #endif /* not CONFIG_TPL_BUILD */ #define CONFIG_SPL_PAD_TO 0x20000 -- cgit v1.2.3 From 4aceaec585d925eed468c3bd25fdcdfd7568033e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Apr 2022 12:16:15 +0200 Subject: board: freescale: p1_p2_rdb_pc: Detect both P2020 SD switch configurations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As written in comment, P2020 has two possible SD switch configurations. Extend code to detect both of them. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- include/configs/p1_p2_rdb_pc.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 81dc0177c0c..cc703309e3e 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -57,7 +57,8 @@ #define __SW_BOOT_MASK 0x03 #define __SW_BOOT_NOR 0xc8 #define __SW_BOOT_SPI 0x28 -#define __SW_BOOT_SD 0x68 /* or 0x18 */ +#define __SW_BOOT_SD 0x68 +#define __SW_BOOT_SD2 0x18 #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 #define CONFIG_SYS_L2_SIZE (512 << 10) -- cgit v1.2.3 From ac56055c41ae56756ee07805f998eaf9bc33f332 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Apr 2022 12:16:20 +0200 Subject: board: freescale: p1_p2_rdb_pc: Fix env $vscfw_addr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Do not stringify env $vscfw_addr two times (once implicitly via string operator "" and second time explicitly via __stringify() macro) and allow to compile U-Boot without CONFIG_VSC7385_ENET (when __VSCFW_ADDR was not defined and so macro name was stringified into CONFIG_EXTRA_ENV_SETTINGS). Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- include/configs/p1_p2_rdb_pc.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index cc703309e3e..c3df6381835 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -325,7 +325,7 @@ /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET -#define __VSCFW_ADDR "vscfw_addr=ef000000" +#define __VSCFW_ADDR "vscfw_addr=ef000000\0" #define CONFIG_SYS_VSC7385_BASE 0xffb00000 #ifdef CONFIG_PHYS_64BIT @@ -344,6 +344,10 @@ #define CONFIG_VSC7385_IMAGE_SIZE 8192 #endif +#ifndef __VSCFW_ADDR +#define __VSCFW_ADDR "" +#endif + /* * Config the L2 Cache as L2 SRAM */ @@ -581,7 +585,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "ramdisk_size=120000\0" \ "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ -__stringify(__VSCFW_ADDR)"\0" \ +__VSCFW_ADDR \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ -- cgit v1.2.3 From 6496a89a5723a24dfaaf904384177f4119cae2c8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Apr 2022 12:16:21 +0200 Subject: board: freescale: p1_p2_rdb_pc: Use named macros for i2c bus num and address MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace hardcoded boot i2c bus num and address by existing macros when generating env for CONFIG_EXTRA_ENV_SETTINGS. Same macros are used in U-Boot board code when reading information from boot i2c data. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- include/configs/p1_p2_rdb_pc.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index c3df6381835..08e3f8de030 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -535,28 +535,28 @@ #ifdef __SW_BOOT_NOR #define __NOR_RST_CMD \ -norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_SPI #define __SPI_RST_CMD \ -spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_SD #define __SD_RST_CMD \ -sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_NAND #define __NAND_RST_CMD \ -nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #ifdef __SW_BOOT_PCIE #define __PCIE_RST_CMD \ -pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \ -i2c mw 18 3 __SW_BOOT_MASK 1; reset +pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \ +i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset #endif #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -583,9 +583,9 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "nandbootaddr=100000\0" \ "nandfdtaddr=80000\0" \ "ramdisk_size=120000\0" \ -"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ -"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ __VSCFW_ADDR \ +"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 02 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \ +"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 00 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ -- cgit v1.2.3 From c7d0295c25c1a4d287eb5126e78b6d380893e141 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Thu, 7 Apr 2022 12:16:22 +0200 Subject: board: freescale: p1_p2_rdb_pc: Define SW macros for lower and upper NOR banks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace hardcoded i2c hex values for NOR banks by named SW macros in map_lowernorbank/map_uppernorbank env commands. Signed-off-by: Pali Rohár Reviewed-by: Priyanka Jain --- include/configs/p1_p2_rdb_pc.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 08e3f8de030..f6ecf2a7a8b 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -21,6 +21,9 @@ #define __SW_BOOT_SD 0x9c #define __SW_BOOT_NAND 0xec #define __SW_BOOT_PCIE 0x6c +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (256 << 10) #endif @@ -46,6 +49,9 @@ #define __SW_BOOT_SD 0x24 #define __SW_BOOT_NAND 0x44 #define __SW_BOOT_PCIE 0x74 +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (256 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -61,6 +67,9 @@ #define __SW_BOOT_SD2 0x18 #define __SW_BOOT_NAND 0xe8 #define __SW_BOOT_PCIE 0xa8 +#define __SW_NOR_BANK_MASK 0xfd +#define __SW_NOR_BANK_UP 0x00 +#define __SW_NOR_BANK_LO 0x02 #define CONFIG_SYS_L2_SIZE (512 << 10) /* * Dynamic MTD Partition support with mtdparts @@ -584,8 +593,8 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset "nandfdtaddr=80000\0" \ "ramdisk_size=120000\0" \ __VSCFW_ADDR \ -"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 02 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \ -"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 00 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 fd 1\0" \ +"map_lowernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_LO)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ +"map_uppernorbank=i2c dev "__stringify(CONFIG_SYS_SPD_BUS_NUM)"; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 1 "__stringify(__SW_NOR_BANK_UP)" 1; i2c mw "__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)" 3 "__stringify(__SW_NOR_BANK_MASK)" 1\0" \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ -- cgit v1.2.3