From e7005b3e80d396f45a3ba88448818eee5d592f27 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Mon, 4 May 2020 11:24:26 +0300 Subject: fsl_dspi: Introduce DT bindings for CS-SCK and SCK-CS delays Communication with some SPI slaves just won't cut it if these delays (before the beginning, and after the end of a transfer) are not added to the Chip Select signal. These are a straight copy from Linux: Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt drivers/spi/spi-fsl-dspi.c Signed-off-by: Vladimir Oltean [Rebased] Signed-off-by: Priyanka Jain --- include/fsl_dspi.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fsl_dspi.h b/include/fsl_dspi.h index 114f63bce37..4fec83549e1 100644 --- a/include/fsl_dspi.h +++ b/include/fsl_dspi.h @@ -94,6 +94,7 @@ struct dspi { #define DSPI_CTAR_ASC(x) (((x) & 0x0F) << 8) #define DSPI_CTAR_DT(x) (((x) & 0x0F) << 4) #define DSPI_CTAR_BR(x) ((x) & 0x0F) +#define DSPI_CTAR_SCALE_BITS 0xf /* Status */ #define DSPI_SR_TCF 0x80000000 -- cgit v1.3.1 From f8c5815c1b5728b005c97145f5b39df1e59af53b Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 10 May 2020 01:20:11 +0200 Subject: armv8: ls1028a: move FSL_LAYERSCAPE to kconfig CONFIG_FSL_LAYERSCAPE is available in kconfig. There is no need to define it per board; the ls1028a_common.h is really board dependent and only fits to the NXP eval boards. Instead select CONFIG_FSL_LAYERSCAPE when ARCH_LS1028A is selected. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 + include/configs/ls1028a_common.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 2f75b2cdd32..116b6b0617b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -23,6 +23,7 @@ config ARCH_LS1012A config ARCH_LS1028A bool select ARMV8_SET_SMPEN + select FSL_LAYERSCAPE select FSL_LSCH3 select NXP_LSCH3_2 select SYS_FSL_HAS_CCI400 diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index d184673a71b..fe4a87b6972 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -7,7 +7,6 @@ #define __L1028A_COMMON_H #define CONFIG_REMAKE_ELF -#define CONFIG_FSL_LAYERSCAPE #define CONFIG_MP #include -- cgit v1.3.1 From e08bcc0e948de2a1ea73b9c58d642d08b1488ce0 Mon Sep 17 00:00:00 2001 From: Era Tiwari Date: Fri, 15 May 2020 12:48:39 +0530 Subject: configs: ls1088ardb: Add support for usb boot target LS1088A-RDB has MMC, SCSI, DHCP as boot targets, but the USB support was missing. Add support for USB as Boot_targets_devices. Signed-off-by: Era Tiwari Signed-off-by: Pramod Kumar [Rebased] Signed-off-by: Priyanka Jain --- include/configs/ls1088ardb.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 16e0486d403..28a458772d7 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -524,6 +524,7 @@ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ + func(USB, usb, 0) \ func(SCSI, scsi, 0) \ func(DHCP, dhcp, na) #include -- cgit v1.3.1 From e0152dbed683ed02af9294551fd4f03823ef7a5a Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 28 May 2020 11:42:53 +0530 Subject: net: pfe_eth: Use spi_flash_read API to access flash memory Current PFE firmware access spi-nor memory directly. New spi-mem framework does not support direct memory access. So, let's use spi_flash_read API to access memory instead of directly using it. Signed-off-by: Kuldeep Singh Reviewed-by: Frieder Schrempf Reviewed-by: Priyanka Jain --- drivers/net/pfe_eth/pfe_firmware.c | 45 +++++++++++++++++++++++++++++++++++++- include/configs/ls1012a_common.h | 5 ++++- 2 files changed, 48 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c index 0493cfe8724..55e661c0e1d 100644 --- a/drivers/net/pfe_eth/pfe_firmware.c +++ b/drivers/net/pfe_eth/pfe_firmware.c @@ -16,13 +16,14 @@ #include #include #include +#include #ifdef CONFIG_CHAIN_OF_TRUST #include #endif #define PFE_FIRMWARE_FIT_CNF_NAME "config@1" -static const void *pfe_fit_addr = (void *)CONFIG_SYS_LS_PFE_FW_ADDR; +static const void *pfe_fit_addr; /* * PFE elf firmware loader. @@ -163,6 +164,44 @@ static int pfe_fit_check(void) return ret; } +int pfe_spi_flash_init(void) +{ + struct spi_flash *pfe_flash; + int ret = 0; + void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH); + +#ifdef CONFIG_DM_SPI_FLASH + struct udevice *new; + + /* speed and mode will be read from DT */ + ret = spi_flash_probe_bus_cs(CONFIG_ENV_SPI_BUS, + CONFIG_ENV_SPI_CS, 0, 0, &new); + + pfe_flash = dev_get_uclass_priv(new); +#else + pfe_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, + CONFIG_ENV_SPI_CS, + CONFIG_ENV_SPI_MAX_HZ, + CONFIG_ENV_SPI_MODE); +#endif + if (!pfe_flash) { + printf("SF: probe for pfe failed\n"); + return -ENODEV; + } + + ret = spi_flash_read(pfe_flash, + CONFIG_SYS_LS_PFE_FW_ADDR, + CONFIG_SYS_QE_FMAN_FW_LENGTH, + addr); + if (ret) + printf("SF: read for pfe failed\n"); + + pfe_fit_addr = addr; + spi_flash_free(pfe_flash); + + return ret; +} + /* * PFE firmware initialization. * Loads different firmware files from FIT image. @@ -187,6 +226,10 @@ int pfe_firmware_init(void) int ret = 0; int fw_count; + ret = pfe_spi_flash_init(); + if (ret) + goto err; + ret = pfe_fit_check(); if (ret) goto err; diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 3bea9a91868..06af8bf79fe 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -36,8 +36,11 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) -/*SPI device */ +/* PFE */ #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x300000 + +/*SPI device */ #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 /* SATA */ -- cgit v1.3.1 From 3d3fe8b12d1973b207ee0406709ff521eec83bf7 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 1 Jun 2020 21:53:26 +0200 Subject: armv8: layerscape: properly use CPU_RELEASE_ADDR The generic armv8 code already has support to bring up the secondary cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to the spin table code; instead just return early and let the common armv8 code handle the jump. This way we can actually use the CPU_RELEASE_ADDR feature. Signed-off-by: Michael Walle [Rebased, Removed kontron_sl28.h change as file does not exist] Signed-off-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 14 ++++++++++++-- arch/arm/include/asm/arch-fsl-layerscape/mp.h | 1 - include/configs/ls1028a_common.h | 2 +- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- include/configs/ls1088a_common.h | 2 +- include/configs/ls2080a_common.h | 2 +- include/configs/lx2160a_common.h | 2 +- 8 files changed, 18 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 2a8d592cc5c..d75013eb9c8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -208,8 +208,13 @@ ENTRY(lowlevel_init) branch_if_master x0, x1, 2f #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY) - ldr x0, =secondary_boot_func - blr x0 + /* + * Formerly, here was a jump to secondary_boot_func, but we just + * return early here and let the generic code in start.S handle + * the jump to secondary_boot_func. + */ + mov lr, x29 /* Restore LR */ + ret #endif 2: @@ -421,6 +426,11 @@ ENDPROC(__asm_flush_l3_dcache) #endif /* CONFIG_SYS_FSL_HAS_CCN504 */ #ifdef CONFIG_MP + .align 3 + .global secondary_boot_addr +secondary_boot_addr: + .quad secondary_boot_func + /* Keep literals not used by the secondary boot code outside it */ .ltorg diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index 00aa91b0a20..623977651a9 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -43,7 +43,6 @@ static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; } #endif void *get_spin_tbl_addr(void); phys_addr_t determine_mp_bootpg(void); -void secondary_boot_func(void); int is_core_online(u64 cpu_id); u32 cpu_pos_mask(void); #endif diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index fe4a87b6972..4863fb2b643 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -28,7 +28,7 @@ /* * SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 3efac1fa780..1271d706108 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -47,7 +47,7 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL -#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 8fe6937dfbc..5899e32c213 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -48,7 +48,7 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL -#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 25000000 /* 25MHz */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 3ea16752de0..5b83e61ab23 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -48,7 +48,7 @@ /* * SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 410872dfd86..d93ff291bdc 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -42,7 +42,7 @@ /* * SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS #ifdef CONFIG_SYS_FSL_HAS_DP_DDR diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 9bc287f7aa4..0c3d6835516 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -52,7 +52,7 @@ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) /* SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func +#define CPU_RELEASE_ADDR secondary_boot_addr /* Generic Timer Definitions */ /* -- cgit v1.3.1 From af0e08ca108dabced8f2dd8796938a723483e6c1 Mon Sep 17 00:00:00 2001 From: Biwen Li Date: Thu, 4 Jun 2020 18:42:14 +0800 Subject: I2C: ls1043a, ls1046a: enable SYS_I2C_MXC This enables SYS_I2C_MXC to fix a bug that failed to boot from sd card with image u-boot-with-spl-pbl.bin Signed-off-by: Biwen Li Reviewed-by: Priyanka Jain --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++-- include/configs/ls1043a_common.h | 3 +-- include/configs/ls1046a_common.h | 1 - 3 files changed, 3 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 116b6b0617b..bfc847303a1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -76,7 +76,7 @@ config ARCH_LS1043A select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F - select SYS_I2C_MXC if !DM_I2C + select SYS_I2C_MXC select SYS_I2C_MXC_I2C1 if !DM_I2C select SYS_I2C_MXC_I2C2 if !DM_I2C select SYS_I2C_MXC_I2C3 if !DM_I2C @@ -109,7 +109,7 @@ config ARCH_LS1046A select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F - select SYS_I2C_MXC if !DM_I2C + select SYS_I2C_MXC select SYS_I2C_MXC_I2C1 if !DM_I2C select SYS_I2C_MXC_I2C2 if !DM_I2C select SYS_I2C_MXC_I2C3 if !DM_I2C diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 1271d706108..96fdd6417ed 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2015 Freescale Semiconductor - * Copyright (C) 2019 NXP + * Copyright 2019-2020 NXP */ #ifndef __LS1043A_COMMON_H @@ -144,7 +144,6 @@ /* I2C */ #ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 5899e32c213..d44a7f105e6 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -129,7 +129,6 @@ /* I2C */ #ifndef CONFIG_DM_I2C #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -- cgit v1.3.1 From 3fba2311a3c4bbe6301fbdfbdb97f8ecba75778a Mon Sep 17 00:00:00 2001 From: Udit Agarwal Date: Mon, 8 Jun 2020 18:55:44 +0530 Subject: include/configs: ls1012a: Remove fdt_high env variable Remove "fdt_high" environment variable to use the bootm_size to safely contain a kernel, device tree and initrd for relocation. Signed-off-by: Udit Agarwal Reviewed-by: Priyanka Jain --- include/configs/ls1012a2g5rdb.h | 2 +- include/configs/ls1012a_common.h | 2 +- include/configs/ls1012afrdm.h | 2 +- include/configs/ls1012afrwy.h | 2 +- include/configs/ls1012ardb.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h index 86cc4b6d301..bbc3ffd7f0d 100644 --- a/include/configs/ls1012a2g5rdb.h +++ b/include/configs/ls1012a2g5rdb.h @@ -33,7 +33,6 @@ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ - "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ @@ -47,6 +46,7 @@ "load_addr=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernelheader_size=0x40000\0" \ + "bootm_size=0x10000000\0" \ "console=ttyS0,115200\0" \ BOOTENV \ "boot_scripts=ls1012ardb_boot.scr\0" \ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 06af8bf79fe..b3fe72279c4 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -86,11 +86,11 @@ "verify=no\0" \ "loadaddr=0x80100000\0" \ "kernel_addr=0x100000\0" \ - "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x1000000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ + "bootm_size=0x10000000\0" \ #undef CONFIG_BOOTCOMMAND #ifdef CONFIG_TFABOOT diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h index f8cb97bd126..8de20e3ff45 100644 --- a/include/configs/ls1012afrdm.h +++ b/include/configs/ls1012afrdm.h @@ -24,7 +24,6 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ "scriptaddr=0x80000000\0" \ @@ -34,6 +33,7 @@ "fdt_addr_r=0x90000000\0" \ "load_addr=0x96000000\0" \ "kernel_size=0x2800000\0" \ + "bootm_size=0x10000000\0" \ "console=ttyS0,115200\0" \ BOOTENV \ "boot_scripts=ls1012afrdm_boot.scr\0" \ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index 2e20e11377d..29c344c63a9 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -45,7 +45,6 @@ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ - "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ @@ -65,6 +64,7 @@ "load_addr=0x92000000\0" \ "kernel_size=0x2800000\0" \ "kernelheader_size=0x40000\0" \ + "bootm_size=0x10000000\0" \ "console=ttyS0,115200\0" \ "BOARD=ls1012afrwy\0" \ BOOTENV \ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h index 7eb1ec9366a..94e742ee844 100644 --- a/include/configs/ls1012ardb.h +++ b/include/configs/ls1012ardb.h @@ -51,7 +51,6 @@ #undef CONFIG_EXTRA_ENV_SETTINGS #define CONFIG_EXTRA_ENV_SETTINGS \ "verify=no\0" \ - "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "fdt_addr=0x00f00000\0" \ "kernel_addr=0x01000000\0" \ @@ -65,6 +64,7 @@ "load_addr=0xa0000000\0" \ "kernel_size=0x2800000\0" \ "kernelheader_size=0x40000\0" \ + "bootm_size=0x10000000\0" \ "console=ttyS0,115200\0" \ BOOTENV \ "boot_scripts=ls1012ardb_boot.scr\0" \ -- cgit v1.3.1 From c8f8830e0bae17f1163de6d413d0553ba5a67416 Mon Sep 17 00:00:00 2001 From: Yuantian Tang Date: Wed, 10 Jun 2020 16:13:50 +0800 Subject: armv8: ls1028ardb: add xspi parameter to qixis command Add xspi boot source to qixis command to let the soc boot from flex-nor flash chip. Signed-off-by: Yuantian Tang Reviewed-by: Priyanka Jain --- board/freescale/common/qixis.c | 13 +++++++++++++ include/configs/ls1028ardb.h | 4 ++-- 2 files changed, 15 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 591203132f9..1696c24e27b 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -323,6 +323,19 @@ static int qixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc, QIXIS_RCFG_CTL_RECONFIG_START); #else printf("Not implemented\n"); +#endif + } else if (strcmp(argv[1], "xspi") == 0) { +#ifdef QIXIS_LBMAP_XSPI + QIXIS_WRITE(rst_ctl, 0x30); + QIXIS_WRITE(rcfg_ctl, 0); + set_lbmap(QIXIS_LBMAP_XSPI); + set_rcw_src(QIXIS_RCW_SRC_XSPI); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_IDLE); + qixis_write_i2c(offsetof(struct qixis, rcfg_ctl), + QIXIS_RCFG_CTL_RECONFIG_START); +#else + printf("Not implemented\n"); #endif } else if (strcmp(argv[1], "watchdog") == 0) { static char *period[9] = {"2s", "4s", "8s", "16s", "32s", diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 07450113269..e6f38f5d00e 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -38,10 +38,10 @@ #define QIXIS_LBMAP_ALTBANK 0x00 #define QIXIS_LBMAP_SD 0x00 #define QIXIS_LBMAP_EMMC 0x00 -#define QIXIS_LBMAP_QSPI 0x00 +#define QIXIS_LBMAP_XSPI 0x00 #define QIXIS_RCW_SRC_SD 0xf8 #define QIXIS_RCW_SRC_EMMC 0xf9 -#define QIXIS_RCW_SRC_QSPI 0xff +#define QIXIS_RCW_SRC_XSPI 0xff #define QIXIS_RST_CTL_RESET 0x31 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x10 #define QIXIS_RCFG_CTL_RECONFIG_START 0x11 -- cgit v1.3.1 From 39913acedd673c815af06da8dc3ef04c6e674d4a Mon Sep 17 00:00:00 2001 From: Yangbo Lu Date: Wed, 17 Jun 2020 18:08:58 +0800 Subject: Move eSDHC adapter card identification to board files The eSDHC adapter card identification and multiplexing configuration through FPGA had been implemented in both common mmc driver and fsl_esdhc driver. However it is proper to move these code to board files and do it during board initialization. The FPGA registers are also board specific. This patch is to move eSDHC adapter card identification and multiplexing configuration from mmc driver to specific board files. And the option CONFIG_FSL_ESDHC_ADAPTER_IDENT is no longer needed. Signed-off-by: Yangbo Lu [Rebased, Removed T1040QDS change as board does not exist] Signed-off-by: Priyanka Jain --- board/freescale/common/qixis.h | 3 +-- board/freescale/t208xqds/t208xqds.c | 29 +++++++++++++++++++++++++++- doc/README.fsl-esdhc | 14 -------------- drivers/mmc/fsl_esdhc.c | 38 ------------------------------------- drivers/mmc/mmc-uclass.c | 4 +--- drivers/mmc/mmc.c | 7 +------ drivers/mmc/mmc_legacy.c | 7 +------ drivers/mmc/mmc_private.h | 4 +--- include/configs/T208xQDS.h | 1 - include/fsl_esdhc.h | 4 ---- scripts/config_whitelist.txt | 1 - 11 files changed, 33 insertions(+), 79 deletions(-) (limited to 'include') diff --git a/board/freescale/common/qixis.h b/board/freescale/common/qixis.h index c11062e75ed..ac5abc36f93 100644 --- a/board/freescale/common/qixis.h +++ b/board/freescale/common/qixis.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2011 Freescale Semiconductor + * Copyright 2020 NXP * Author: Shengzhou Liu * * This file provides support for the QIXIS of some Freescale reference boards. @@ -115,7 +116,6 @@ void qixis_write_i2c(unsigned int reg, u8 value); #endif /* Use for SDHC adapter card type identification and operation */ -#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT #define QIXIS_SDID_MASK 0x07 #define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45 0x1 /* eMMC Card Rev4.5 */ #define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY 0x2 /* SD/MMC Legacy Card */ @@ -131,6 +131,5 @@ void qixis_write_i2c(unsigned int reg, u8 value); #define QIXIS_DAT4 0X01 #define QIXIS_EVDD_BY_SDHC_VS 0x0c -#endif #endif diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 1dbfd493a24..f3af8d52925 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -345,6 +345,33 @@ int brd_mux_lane_to_slot(void) return 0; } +static void esdhc_adapter_card_ident(void) +{ + u8 card_id, value; + + card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; + + switch (card_id) { + case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: + value = QIXIS_READ(brdcfg[5]); + value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); + QIXIS_WRITE(brdcfg[5], value); + break; + case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: + value = QIXIS_READ(pwr_ctl[1]); + value |= QIXIS_EVDD_BY_SDHC_VS; + QIXIS_WRITE(pwr_ctl[1], value); + break; + case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: + value = QIXIS_READ(brdcfg[5]); + value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); + QIXIS_WRITE(brdcfg[5], value); + break; + default: + break; + } +} + int board_early_init_r(void) { const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; @@ -384,7 +411,7 @@ int board_early_init_r(void) brd_mux_lane_to_slot(); select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); - + esdhc_adapter_card_ident(); return 0; } diff --git a/doc/README.fsl-esdhc b/doc/README.fsl-esdhc index 29cc6619eab..b620625dfbd 100644 --- a/doc/README.fsl-esdhc +++ b/doc/README.fsl-esdhc @@ -1,19 +1,5 @@ Freescale esdhc-specific options - - CONFIG_FSL_ESDHC_ADAPTER_IDENT - Support Freescale adapter card type identification. This is implemented by - operating Qixis FPGA relevant registers. The STAT_PRES1 register has SDHC - Card ID[0:2] bits showing the type of card installed in the SDHC Adapter Slot. - - SDHC Card ID[0:2] Adapter Card Type - 0b000 reserved - 0b001 eMMC Card Rev4.5 - 0b010 SD/MMC Legacy Card - 0b011 eMMC Card Rev4.4 - 0b100 reserved - 0b101 MMC Card - 0b110 SD Card Rev2.0/3.0 - 0b111 No card is present - CONFIG_SYS_FSL_ESDHC_LE ESDHC IP is in little-endian mode. Accessing ESDHC registers can be determined by ESDHC IP's endian mode or processor's endian mode. diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index ba10540d048..de9fe01bc5c 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -671,44 +671,6 @@ static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv, cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; } -#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT -void mmc_adapter_card_type_ident(void) -{ - u8 card_id; - u8 value; - - card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; - - switch (card_id) { - case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: - value = QIXIS_READ(brdcfg[5]); - value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); - QIXIS_WRITE(brdcfg[5], value); - break; - case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: - value = QIXIS_READ(pwr_ctl[1]); - value |= QIXIS_EVDD_BY_SDHC_VS; - QIXIS_WRITE(pwr_ctl[1], value); - break; - case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: - value = QIXIS_READ(brdcfg[5]); - value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); - QIXIS_WRITE(brdcfg[5], value); - break; - case QIXIS_ESDHC_ADAPTER_TYPE_RSV: - break; - case QIXIS_ESDHC_ADAPTER_TYPE_MMC: - break; - case QIXIS_ESDHC_ADAPTER_TYPE_SD: - break; - case QIXIS_ESDHC_NO_ADAPTER: - break; - default: - break; - } -} -#endif - #ifdef CONFIG_OF_LIBFDT __weak int esdhc_status_fixup(void *blob, const char *compat) { diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index c5b78729001..90690c8d1e3 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2015 Google, Inc + * Copyright 2020 NXP * Written by Simon Glass */ @@ -309,9 +310,6 @@ void mmc_do_preinit(void) if (!m) continue; -#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT - mmc_set_preinit(m, 1); -#endif if (m->preinit) mmc_start_init(m); } diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index f36d11ddc87..d79cdef62ed 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2008, Freescale Semiconductor, Inc + * Copyright 2020 NXP * Andy Fleming * * Based vaguely on the Linux code @@ -2789,9 +2790,6 @@ int mmc_get_op_cond(struct mmc *mmc) if (mmc->has_init) return 0; -#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT - mmc_adapter_card_type_ident(); -#endif err = mmc_power_init(mmc); if (err) return err; @@ -3073,9 +3071,6 @@ int mmc_init_device(int num) m = mmc_get_mmc_dev(dev); if (!m) return 0; -#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT - mmc_set_preinit(m, 1); -#endif if (m->preinit) mmc_start_init(m); diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c index 2bb12ceeaf1..a05da6c2e88 100644 --- a/drivers/mmc/mmc_legacy.c +++ b/drivers/mmc/mmc_legacy.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Google, Inc + * Copyright 2020 NXP * Written by Simon Glass */ @@ -23,9 +24,6 @@ struct mmc *find_mmc_device(int dev_num) void mmc_do_preinit(void) { struct mmc *m = &mmc_static; -#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT - mmc_set_preinit(m, 1); -#endif if (m->preinit) mmc_start_init(m); } @@ -77,9 +75,6 @@ void mmc_do_preinit(void) list_for_each(entry, &mmc_devices) { m = list_entry(entry, struct mmc, link); -#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT - mmc_set_preinit(m, 1); -#endif if (m->preinit) mmc_start_init(m); } diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h index 35170d03abb..a0900e8cadd 100644 --- a/drivers/mmc/mmc_private.h +++ b/drivers/mmc/mmc_private.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2008,2010 Freescale Semiconductor, Inc + * Copyright 2020 NXP * Andy Fleming * * Based (loosely) on the Linux code @@ -16,9 +17,6 @@ int mmc_send_status(struct mmc *mmc, unsigned int *status); int mmc_poll_for_busy(struct mmc *mmc, int timeout); int mmc_set_blocklen(struct mmc *mmc, int len); -#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT -void mmc_adapter_card_type_ident(void); -#endif #if CONFIG_IS_ENABLED(BLK) ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index f32e6680b3a..b502b0b1387 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -632,7 +632,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#define CONFIG_FSL_ESDHC_ADAPTER_IDENT #endif /* diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 2615d1ad2ff..7f8f8edc621 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -16,10 +16,6 @@ /* needed for the mmc_cfg definition */ #include -#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT -#include "../board/freescale/common/qixis.h" -#endif - /* FSL eSDHC-specific constants */ #define SYSCTL 0x0002e02c #define SYSCTL_INITA 0x08000000 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 2ec7642583d..d822abbfa16 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -549,7 +549,6 @@ CONFIG_FSL_DIU_CH7301 CONFIG_FSL_DIU_FB CONFIG_FSL_DMA CONFIG_FSL_DSPI1 -CONFIG_FSL_ESDHC_ADAPTER_IDENT CONFIG_FSL_ESDHC_PIN_MUX CONFIG_FSL_FIXED_MMC_LOCATION CONFIG_FSL_FM_10GEC_REGULAR_NOTATION -- cgit v1.3.1 From 10669ed96576f367af57bb4200327b9dfed2b44b Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 25 Jun 2020 12:56:22 +0530 Subject: configs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN value Previous attempt to increase CONFIG_SYS_MALLOC_LEN was done in commit c084a8edf4e2 ("configs: ls1012a: Increase CONFIG_SYS_MALLOC_LEN size") which increased malloc memory to ~1M. PFE firmware alone requires 3M of dynamic memory allocation and therefore, increase the config value to a larger value i.e 5M. This size should be enough as of now to accommodate further memory requirements. Signed-off-by: Kuldeep Singh Reviewed-by: Priyanka Jain --- include/configs/ls1012a_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index b3fe72279c4..6cf6a31d767 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -10,6 +10,7 @@ #include #include +#include #define CONFIG_SYS_CLK_FREQ 125000000 @@ -34,7 +35,7 @@ #define CONFIG_LAYERSCAPE_NS_ACCESS /* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) +#define CONFIG_SYS_MALLOC_LEN (5 * SZ_1M) /* PFE */ #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 -- cgit v1.3.1 From 277405b86ce112e5be39d75ceccb4f0b4e45e1dc Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sat, 27 Jun 2020 22:58:49 +0200 Subject: crypto/fsl: export caam_get_era() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need the era in other modules, too. For example, to get the RNG version. Signed-off-by: Michael Walle Reviewed-by: Horia Geantă Reviewed-by: Priyanka Jain --- drivers/crypto/fsl/sec.c | 10 +++++++++- include/fsl_sec.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c index a2c0bfaf44c..f0a4a63d886 100644 --- a/drivers/crypto/fsl/sec.c +++ b/drivers/crypto/fsl/sec.c @@ -98,7 +98,15 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev) fdt_strerror(err)); } #elif CONFIG_SYS_FSL_SEC_COMPAT >= 4 /* SEC4 */ -static u8 caam_get_era(void) +/** + * caam_get_era() - fetch the CAAM's era + * + * The SEC module povides an "Era" which can be used to differentiate + * between different revisions. + * + * Return: era of the SEC. + */ +u8 caam_get_era(void) { static const struct { u16 ip_id; diff --git a/include/fsl_sec.h b/include/fsl_sec.h index c0d2c7e8667..2ebb75c9b27 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -316,6 +316,8 @@ int blob_dek(const u8 *src, u8 *dst, u8 len); int sec_init_idx(uint8_t); #endif int sec_init(void); + +u8 caam_get_era(void); #endif #endif /* __FSL_SEC_H */ -- cgit v1.3.1 From 0dc596127c55e5430bd8f213e41a24c8f440c01a Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sat, 27 Jun 2020 22:58:50 +0200 Subject: crypto/fsl: support newer SEC modules MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since Era 10, the version registers changed. Add the version registers and use them on newer modules. Signed-off-by: Michael Walle Reviewed-by: Horia Geantă Reviewed-by: Priyanka Jain --- drivers/crypto/fsl/jr.c | 12 ++++++++++-- include/fsl_sec.h | 51 ++++++++++++++++++++++++++++++++++++++++++------- 2 files changed, 54 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index bbdbcb8e58a..5275c50e8b2 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -498,9 +498,17 @@ static int instantiate_rng(uint8_t sec_idx) static u8 get_rng_vid(uint8_t sec_idx) { ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx); - u32 cha_vid = sec_in32(&sec->chavid_ls); + u8 vid; - return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT; + if (caam_get_era() < 10) { + vid = (sec_in32(&sec->chavid_ls) & SEC_CHAVID_RNG_LS_MASK) + >> SEC_CHAVID_LS_RNG_SHIFT; + } else { + vid = (sec_in32(&sec->vreg.rng) & CHA_VER_VID_MASK) + >> CHA_VER_VID_SHIFT; + } + + return vid; } /* diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 2ebb75c9b27..8dce0bbb1bd 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -73,6 +73,41 @@ struct rng4tst { u32 rsvd2[15]; }; +/* Version registers (Era 10+) */ +struct version_regs { + u32 crca; /* CRCA_VERSION */ + u32 afha; /* AFHA_VERSION */ + u32 kfha; /* KFHA_VERSION */ + u32 pkha; /* PKHA_VERSION */ + u32 aesa; /* AESA_VERSION */ + u32 mdha; /* MDHA_VERSION */ + u32 desa; /* DESA_VERSION */ + u32 snw8a; /* SNW8A_VERSION */ + u32 snw9a; /* SNW9A_VERSION */ + u32 zuce; /* ZUCE_VERSION */ + u32 zuca; /* ZUCA_VERSION */ + u32 ccha; /* CCHA_VERSION */ + u32 ptha; /* PTHA_VERSION */ + u32 rng; /* RNG_VERSION */ + u32 trng; /* TRNG_VERSION */ + u32 aaha; /* AAHA_VERSION */ + u32 rsvd[10]; + u32 sr; /* SR_VERSION */ + u32 dma; /* DMA_VERSION */ + u32 ai; /* AI_VERSION */ + u32 qi; /* QI_VERSION */ + u32 jr; /* JR_VERSION */ + u32 deco; /* DECO_VERSION */ +}; + +#define CHA_VER_NUM_MASK 0x000000ff +#define CHA_VER_MISC_SHIFT 8 +#define CHA_VER_MISC_MASK 0x0000ff00 +#define CHA_VER_REV_SHIFT 16 +#define CHA_VER_REV_MASK 0x00ff0000 +#define CHA_VER_VID_SHIFT 24 +#define CHA_VER_VID_MASK 0xff000000 + typedef struct ccsr_sec { u32 res0; u32 mcfgr; /* Master CFG Register */ @@ -98,17 +133,19 @@ typedef struct ccsr_sec { u32 drr; /* DECO Reset Register */ u8 res5[0x4d8]; struct rng4tst rng; /* RNG Registers */ - u8 res6[0x8a0]; + u8 res6[0x780]; + struct version_regs vreg; /* version registers since era 10 */ + u8 res7[0xa0]; u32 crnr_ms; /* CHA Revision Number Register, MS */ u32 crnr_ls; /* CHA Revision Number Register, LS */ u32 ctpr_ms; /* Compile Time Parameters Register, MS */ u32 ctpr_ls; /* Compile Time Parameters Register, LS */ - u8 res7[0x10]; + u8 res8[0x10]; u32 far_ms; /* Fault Address Register, MS */ u32 far_ls; /* Fault Address Register, LS */ u32 falr; /* Fault Address LIODN Register */ u32 fadr; /* Fault Address Detail Register */ - u8 res8[0x4]; + u8 res9[0x4]; u32 csta; /* CAAM Status Register */ u32 smpart; /* Secure Memory Partition Parameters */ u32 smvid; /* Secure Memory Version ID */ @@ -121,16 +158,16 @@ typedef struct ccsr_sec { u32 secvid_ms; /* SEC Version ID Register, MS */ u32 secvid_ls; /* SEC Version ID Register, LS */ #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) - u8 res9[0x6f020]; + u8 res10[0x6f020]; #else - u8 res9[0x6020]; + u8 res10[0x6020]; #endif u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */ u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */ #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) - u8 res10[0x8ffd8]; + u8 res11[0x8ffd8]; #else - u8 res10[0x8fd8]; + u8 res11[0x8fd8]; #endif } ccsr_sec_t; -- cgit v1.3.1 From c269a970f23fabbb0d35708ff021bf2962780f9f Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sat, 27 Jun 2020 22:58:51 +0200 Subject: crypto/fsl: don't regenerate secure keys MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The secure keys (TDKEK, JDKEK, TDSK) can only be generated once after a POR. Otherwise the RNG4 will throw an error. Signed-off-by: Michael Walle Reviewed-by: Horia Geantă Reviewed-by: Priyanka Jain --- drivers/crypto/fsl/jobdesc.c | 4 ++-- drivers/crypto/fsl/jobdesc.h | 2 +- drivers/crypto/fsl/jr.c | 9 +++++---- include/fsl_sec.h | 1 + 4 files changed, 9 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index dbafb5b1617..c30ea88cb08 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -258,7 +258,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, * Descriptor to instantiate RNG State Handle 0 in normal mode and * load the JDKEK, TDKEK and TDSK registers */ -void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc, int handle) +void inline_cnstr_jobdesc_rng_instantiation(u32 *desc, int handle, int do_sk) { u32 *jump_cmd; @@ -269,7 +269,7 @@ void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc, int handle) (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT); /* For SH0, Secure Keys must be generated as well */ - if (handle == 0) { + if (!handle && do_sk) { /* wait for done */ jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1); set_jump_tgt_here(desc, jump_cmd); diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h index d782c46b9db..14b2a119d77 100644 --- a/drivers/crypto/fsl/jobdesc.h +++ b/drivers/crypto/fsl/jobdesc.h @@ -39,7 +39,7 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, uint8_t *enc_blob, uint8_t *plain_txt, uint32_t out_sz); -void inline_cnstr_jobdesc_rng_instantiation(uint32_t *desc, int handle); +void inline_cnstr_jobdesc_rng_instantiation(u32 *desc, int handle, int do_sk); void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc, struct pk_in_params *pkin, uint8_t *out, diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 5275c50e8b2..42865a6cd76 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -446,7 +446,7 @@ int sec_reset(void) return sec_reset_idx(0); } #ifndef CONFIG_SPL_BUILD -static int instantiate_rng(uint8_t sec_idx) +static int instantiate_rng(u8 sec_idx, int gen_sk) { u32 *desc; u32 rdsta_val; @@ -470,7 +470,7 @@ static int instantiate_rng(uint8_t sec_idx) if (rdsta_val & (1 << sh_idx)) continue; - inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx); + inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx, gen_sk); size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN); flush_dcache_range((unsigned long)desc, (unsigned long)desc + size); @@ -546,12 +546,13 @@ static void kick_trng(int ent_delay, uint8_t sec_idx) static int rng_init(uint8_t sec_idx) { - int ret, ent_delay = RTSDCTL_ENT_DLY_MIN; + int ret, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN; ccsr_sec_t __iomem *sec = (ccsr_sec_t __iomem *)SEC_ADDR(sec_idx); struct rng4tst __iomem *rng = (struct rng4tst __iomem *)&sec->rng; u32 inst_handles; + gen_sk = !(sec_in32(&rng->rdsta) & RDSTA_SKVN); do { inst_handles = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK; @@ -574,7 +575,7 @@ static int rng_init(uint8_t sec_idx) * interval, leading to a sucessful initialization of * the RNG. */ - ret = instantiate_rng(sec_idx); + ret = instantiate_rng(sec_idx, gen_sk); } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX)); if (ret) { printf("SEC%u: Failed to instantiate RNG\n", sec_idx); diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 8dce0bbb1bd..64b8751f2de 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -69,6 +69,7 @@ struct rng4tst { #define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002 #define RNG_STATE_HANDLE_MASK \ (RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED) +#define RDSTA_SKVN 0x40000000 u32 rdsta; /*RNG DRNG Status Register*/ u32 rsvd2[15]; }; -- cgit v1.3.1 From b980f9e2597b52ce71247e79d534349f7d174b38 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sat, 27 Jun 2020 22:58:52 +0200 Subject: crypto/fsl: instantiate the RNG with prediciton resistance If it is already instantiated tear it down first and then reinstanciate it again with prediction resistance. Signed-off-by: Michael Walle Reviewed-by: Priyanka Jain --- drivers/crypto/fsl/desc.h | 2 ++ drivers/crypto/fsl/jobdesc.c | 12 +++++++- drivers/crypto/fsl/jobdesc.h | 2 ++ drivers/crypto/fsl/jr.c | 67 ++++++++++++++++++++++++++++++++++++++++---- include/fsl_sec.h | 7 ++--- 5 files changed, 79 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h index 11ad506829f..3589e6ea024 100644 --- a/drivers/crypto/fsl/desc.h +++ b/drivers/crypto/fsl/desc.h @@ -520,6 +520,8 @@ #define OP_ALG_ICV_OFF (0 << OP_ALG_ICV_SHIFT) #define OP_ALG_ICV_ON (1 << OP_ALG_ICV_SHIFT) +#define OP_ALG_PR_ON 0x02 + #define OP_ALG_DIR_SHIFT 0 #define OP_ALG_DIR_MASK 1 #define OP_ALG_DECRYPT 0 diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index c30ea88cb08..a8887588fcd 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -266,7 +266,8 @@ void inline_cnstr_jobdesc_rng_instantiation(u32 *desc, int handle, int do_sk) /* INIT RNG in non-test mode */ append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | - (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT); + (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT | + OP_ALG_PR_ON); /* For SH0, Secure Keys must be generated as well */ if (!handle && do_sk) { @@ -286,6 +287,15 @@ void inline_cnstr_jobdesc_rng_instantiation(u32 *desc, int handle, int do_sk) } } +/* Descriptor for deinstantiation of the RNG block. */ +void inline_cnstr_jobdesc_rng_deinstantiation(u32 *desc, int handle) +{ + init_job_desc(desc, 0); + + append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG | + (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL); +} + /* Change key size to bytes form bits in calling function*/ void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc, struct pk_in_params *pkin, uint8_t *out, diff --git a/drivers/crypto/fsl/jobdesc.h b/drivers/crypto/fsl/jobdesc.h index 14b2a119d77..5185ddd5350 100644 --- a/drivers/crypto/fsl/jobdesc.h +++ b/drivers/crypto/fsl/jobdesc.h @@ -41,6 +41,8 @@ void inline_cnstr_jobdesc_blob_decap(uint32_t *desc, uint8_t *key_idnfr, void inline_cnstr_jobdesc_rng_instantiation(u32 *desc, int handle, int do_sk); +void inline_cnstr_jobdesc_rng_deinstantiation(u32 *desc, int handle); + void inline_cnstr_jobdesc_pkha_rsaexp(uint32_t *desc, struct pk_in_params *pkin, uint8_t *out, uint32_t out_siz); diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 42865a6cd76..c5802f7d519 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include "fsl_sec.h" @@ -446,6 +447,51 @@ int sec_reset(void) return sec_reset_idx(0); } #ifndef CONFIG_SPL_BUILD +static int deinstantiate_rng(u8 sec_idx, int state_handle_mask) +{ + u32 *desc; + int sh_idx, ret = 0; + int desc_size = ALIGN(sizeof(u32) * 2, ARCH_DMA_MINALIGN); + + desc = memalign(ARCH_DMA_MINALIGN, desc_size); + if (!desc) { + debug("cannot allocate RNG init descriptor memory\n"); + return -ENOMEM; + } + + for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) { + /* + * If the corresponding bit is set, then it means the state + * handle was initialized by us, and thus it needs to be + * deinitialized as well + */ + + if (state_handle_mask & RDSTA_IF(sh_idx)) { + /* + * Create the descriptor for deinstantating this state + * handle. + */ + inline_cnstr_jobdesc_rng_deinstantiation(desc, sh_idx); + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + desc_size); + + ret = run_descriptor_jr_idx(desc, sec_idx); + if (ret) { + printf("SEC%u: RNG4 SH%d deinstantiation failed with error 0x%x\n", + sec_idx, sh_idx, ret); + ret = -EIO; + break; + } + + printf("SEC%u: Deinstantiated RNG4 SH%d\n", + sec_idx, sh_idx); + } + } + + free(desc); + return ret; +} + static int instantiate_rng(u8 sec_idx, int gen_sk) { u32 *desc; @@ -466,9 +512,18 @@ static int instantiate_rng(u8 sec_idx, int gen_sk) * If the corresponding bit is set, this state handle * was initialized by somebody else, so it's left alone. */ - rdsta_val = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK; - if (rdsta_val & (1 << sh_idx)) - continue; + rdsta_val = sec_in32(&rng->rdsta); + if (rdsta_val & (RDSTA_IF(sh_idx))) { + if (rdsta_val & RDSTA_PR(sh_idx)) + continue; + + printf("SEC%u: RNG4 SH%d was instantiated w/o prediction resistance. Tearing it down\n", + sec_idx, sh_idx); + + ret = deinstantiate_rng(sec_idx, RDSTA_IF(sh_idx)); + if (ret) + break; + } inline_cnstr_jobdesc_rng_instantiation(desc, sh_idx, gen_sk); size = roundup(sizeof(uint32_t) * 6, ARCH_DMA_MINALIGN); @@ -481,8 +536,8 @@ static int instantiate_rng(u8 sec_idx, int gen_sk) printf("SEC%u: RNG4 SH%d instantiation failed with error 0x%x\n", sec_idx, sh_idx, ret); - rdsta_val = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK; - if (!(rdsta_val & (1 << sh_idx))) { + rdsta_val = sec_in32(&rng->rdsta); + if (!(rdsta_val & RDSTA_IF(sh_idx))) { free(desc); return -1; } @@ -554,7 +609,7 @@ static int rng_init(uint8_t sec_idx) gen_sk = !(sec_in32(&rng->rdsta) & RDSTA_SKVN); do { - inst_handles = sec_in32(&rng->rdsta) & RNG_STATE_HANDLE_MASK; + inst_handles = sec_in32(&rng->rdsta) & RDSTA_MASK; /* * If either of the SH's were instantiated by somebody else diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 64b8751f2de..1c6f1eb23ec 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -65,10 +65,9 @@ struct rng4tst { u32 rtfreqcnt; /* PRGM=0: freq. count register */ }; u32 rsvd1[40]; -#define RNG_STATE0_HANDLE_INSTANTIATED 0x00000001 -#define RNG_STATE1_HANDLE_INSTANTIATED 0x00000002 -#define RNG_STATE_HANDLE_MASK \ - (RNG_STATE0_HANDLE_INSTANTIATED | RNG_STATE1_HANDLE_INSTANTIATED) +#define RDSTA_IF(idx) (0x00000001 << (idx)) +#define RDSTA_PR(idx) (0x00000010 << (idx)) +#define RDSTA_MASK (RDSTA_PR(1) | RDSTA_PR(0) | RDSTA_IF(1) | RDSTA_IF(0)) #define RDSTA_SKVN 0x40000000 u32 rdsta; /*RNG DRNG Status Register*/ u32 rsvd2[15]; -- cgit v1.3.1 From fd00c53fb399708a210e365d768b35e8692a46b8 Mon Sep 17 00:00:00 2001 From: Xiaowei Bao Date: Thu, 9 Jul 2020 23:31:34 +0800 Subject: pci_ep: Add the init function Some EP deivces need to initialize before RC scan it, e.g. NXP layerscape platform, so add the init function in pci_ep uclass. Signed-off-by: Xiaowei Bao Signed-off-by: Hou Zhiqiang Reviewed-by: Priyanka Jain --- common/board_r.c | 12 ++++++++++++ drivers/pci_endpoint/pci_ep-uclass.c | 11 +++++++++++ include/init.h | 1 + 3 files changed, 24 insertions(+) (limited to 'include') diff --git a/common/board_r.c b/common/board_r.c index 67dc25c7d28..d9307f02e06 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -233,6 +233,15 @@ static int initr_unlock_ram_in_cache(void) } #endif +#ifdef CONFIG_PCI_ENDPOINT +static int initr_pci_ep(void) +{ + pci_ep_init(); + + return 0; +} +#endif + #ifdef CONFIG_PCI static int initr_pci(void) { @@ -816,6 +825,9 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_BITBANGMII initr_bbmii, #endif +#ifdef CONFIG_PCI_ENDPOINT + initr_pci_ep, +#endif #ifdef CONFIG_CMD_NET INIT_FUNC_WATCHDOG_RESET initr_net, diff --git a/drivers/pci_endpoint/pci_ep-uclass.c b/drivers/pci_endpoint/pci_ep-uclass.c index 9f53a9a9b97..38a5f083769 100644 --- a/drivers/pci_endpoint/pci_ep-uclass.c +++ b/drivers/pci_endpoint/pci_ep-uclass.c @@ -209,3 +209,14 @@ UCLASS_DRIVER(pci_ep) = { .name = "pci_ep", .flags = DM_UC_FLAG_SEQ_ALIAS, }; + +void pci_ep_init(void) +{ + struct udevice *dev; + + for (uclass_first_device_check(UCLASS_PCI_EP, &dev); + dev; + uclass_next_device_check(&dev)) { + ; + } +} diff --git a/include/init.h b/include/init.h index e727031514c..de408baf892 100644 --- a/include/init.h +++ b/include/init.h @@ -213,6 +213,7 @@ int set_cpu_clk_info(void); int update_flash_size(int flash_size); int arch_early_init_r(void); void pci_init(void); +void pci_ep_init(void); int misc_init_r(void); #if defined(CONFIG_VID) int init_func_vid(void); -- cgit v1.3.1