From 864aa6a6a466fcb92bf32b1d7dba79cd709b52c9 Mon Sep 17 00:00:00 2001 From: Grzegorz Wianecki Date: Sun, 29 Apr 2007 14:01:54 +0200 Subject: [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot message MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up message. Use PVR to distinguish between the two variants, and print proper CPU information. Signed-off-by: Grzegorz Wianecki Signed-off-by: Bartlomiej Sieka Signed-off-by: Grant Likely --- include/asm-ppc/processor.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 058596275f4..7c11c9e0231 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -701,8 +701,6 @@ #define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ #define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ -/* System-On-Chip Version Numbers (version field only) */ -#define SVR_MPC5200 0x8011 /* Processor Version Register */ @@ -813,6 +811,12 @@ #define PVR_8260_HIP7R1 0x80822013 #define PVR_8260_HIP7RA 0x80822014 +/* + * MPC 52xx + */ +#define PVR_5200 0x80822011 +#define PVR_5200B 0x80822014 + /* * System Version Register -- cgit v1.2.3 From 56fd7162985c412317bbf763a225fba23c64fd31 Mon Sep 17 00:00:00 2001 From: Stephen Williams Date: Tue, 15 May 2007 07:55:42 -0700 Subject: Fix for compile of JSE target The attached patch fixes the compile of the JSE board in the denx git as of 14 may 2007. It is an extremely simple patch, it just adds the missing define of CFG_SYSTEMACE_WIDTH. Fix to compile JSE against 20070514 git of u-boot --- include/configs/JSE.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/JSE.h b/include/configs/JSE.h index ccd1f19903b..7fa9ed2d42a 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -49,6 +49,7 @@ /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */ #define CONFIG_SYSTEMACE 1 #define CFG_SYSTEMACE_BASE 0xf0000000 +#define CFG_SYSTEMACE_WIDTH 8 #define CONFIG_DOS_PARTITION 1 /* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */ -- cgit v1.2.3 From 66d9dbec1cc27d6398ee6cf84639dbe14971251e Mon Sep 17 00:00:00 2001 From: mushtaq khan Date: Fri, 20 Apr 2007 14:23:02 +0530 Subject: Add driver for S-ATA-controller on Intel processors with South Bridge, ICH-5, ICH-6 and ICH-7. Implementation: 1. Code is divided in to two files. All functions, which are controller specific are kept in "drivers/ata_piix.c" file and functions, which are not controller specific, are kept in "common/cmd_sata.c" file. 2. Reading and Writing from the S-ATA drive is done using PIO method. 3. Driver can be configured for 48-bit addressing by defining macro CONFIG_LBA48, if this macro is not defined driver uses the 28-bit addressing. 4. S-ATA read function is hooked to the File system, commands like ext2ls and ext2load file can be used. This has been tested. 5. U-Boot command "SATA_init" is added, which initializes the S-ATA controller and identifies the S-ATA drives connected to it. 6. U-Boot command "sata" is added, which is used to read/write, print partition table and get info about the drives present. This I have implemented in same way as "ide" command is implemented in U-Boot. 7. This driver is for S-ATA in native mode. 8. This driver does not support the Native command queuing and Hot-plugging. Signed-off-by: Mushtaq Khan --- include/ata.h | 60 ++++++++++++++++++++++++ include/configs/sc520_cdp.h | 9 ++++ include/sata.h | 108 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 177 insertions(+) create mode 100644 include/sata.h (limited to 'include') diff --git a/include/ata.h b/include/ata.h index 8584226eb07..d36bdf6cd1c 100644 --- a/include/ata.h +++ b/include/ata.h @@ -83,6 +83,66 @@ #define ATA_DEVICE(x) ((x & 1)<<4) #define ATA_LBA 0xE0 +enum { + ATA_MAX_DEVICES = 1, /* per bus/port */ + ATA_MAX_PRD = 256, /* we could make these 256/256 */ + ATA_SECT_SIZE = 256, /*256 words per sector */ + + /* bits in ATA command block registers */ + ATA_HOB = (1 << 7), /* LBA48 selector */ + ATA_NIEN = (1 << 1), /* disable-irq flag */ + /*ATA_LBA = (1 << 6), *//* LBA28 selector */ + ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */ + ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */ + ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */ + ATA_BUSY = (1 << 7), /* BSY status bit */ + ATA_DRDY = (1 << 6), /* device ready */ + ATA_DF = (1 << 5), /* device fault */ + ATA_DRQ = (1 << 3), /* data request i/o */ + ATA_ERR = (1 << 0), /* have an error */ + ATA_SRST = (1 << 2), /* software reset */ + ATA_ABORTED = (1 << 2), /* command aborted */ + /* ATA command block registers */ + ATA_REG_DATA = 0x00, + ATA_REG_ERR = 0x01, + ATA_REG_NSECT = 0x02, + ATA_REG_LBAL = 0x03, + ATA_REG_LBAM = 0x04, + ATA_REG_LBAH = 0x05, + ATA_REG_DEVICE = 0x06, + ATA_REG_STATUS = 0x07, + ATA_PCI_CTL_OFS = 0x02, + /* and their aliases */ + ATA_REG_FEATURE = ATA_REG_ERR, + ATA_REG_CMD = ATA_REG_STATUS, + ATA_REG_BYTEL = ATA_REG_LBAM, + ATA_REG_BYTEH = ATA_REG_LBAH, + ATA_REG_DEVSEL = ATA_REG_DEVICE, + ATA_REG_IRQ = ATA_REG_NSECT, + + /* SETFEATURES stuff */ + SETFEATURES_XFER = 0x03, + XFER_UDMA_7 = 0x47, + XFER_UDMA_6 = 0x46, + XFER_UDMA_5 = 0x45, + XFER_UDMA_4 = 0x44, + XFER_UDMA_3 = 0x43, + XFER_UDMA_2 = 0x42, + XFER_UDMA_1 = 0x41, + XFER_UDMA_0 = 0x40, + XFER_MW_DMA_2 = 0x22, + XFER_MW_DMA_1 = 0x21, + XFER_MW_DMA_0 = 0x20, + XFER_PIO_4 = 0x0C, + XFER_PIO_3 = 0x0B, + XFER_PIO_2 = 0x0A, + XFER_PIO_1 = 0x09, + XFER_PIO_0 = 0x08, + XFER_SW_DMA_2 = 0x12, + XFER_SW_DMA_1 = 0x11, + XFER_SW_DMA_0 = 0x10, + XFER_PIO_SLOW = 0x00 +}; /* * ATA Commands (only mandatory commands listed here) */ diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h index d7d07a62fc9..8b2ec077bd9 100644 --- a/include/configs/sc520_cdp.h +++ b/include/configs/sc520_cdp.h @@ -181,6 +181,15 @@ #undef CONFIG_IDE_RESET /* reset for ide unsupported... */ #undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */ +/************************************************************ +*SATA/Native Stuff +************************************************************/ +#define CFG_SATA_SUPPORTED 1 +#define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */ +#define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */ +#define CFG_SATA_MAXDEVICES (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS) +#define CFG_ATA_PIIX 1 /*Supports ata_piix driver */ + /************************************************************ * ATAPI support (experimental) ************************************************************/ diff --git a/include/sata.h b/include/sata.h new file mode 100644 index 00000000000..c6fa2ab5bcd --- /dev/null +++ b/include/sata.h @@ -0,0 +1,108 @@ + +#if (DEBUG_SATA) +#define PRINTF(fmt,args...) printf (fmt ,##args) +#else +#define PRINTF(fmt,args...) +#endif + +struct sata_ioports { + unsigned long cmd_addr; + unsigned long data_addr; + unsigned long error_addr; + unsigned long feature_addr; + unsigned long nsect_addr; + unsigned long lbal_addr; + unsigned long lbam_addr; + unsigned long lbah_addr; + unsigned long device_addr; + unsigned long status_addr; + unsigned long command_addr; + unsigned long altstatus_addr; + unsigned long ctl_addr; + unsigned long bmdma_addr; + unsigned long scr_addr; +}; + +struct sata_port { + unsigned char port_no; /*primary-0, secondary=1 */ + struct sata_ioports ioaddr; /*ATA cmd/ctl/dma reg blks */ + unsigned char ctl_reg; + unsigned char last_ctl; + unsigned char port_state; /*1-port is present and + 0-port is not available */ + unsigned char dev_mask; +}; + +/***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/ +#ifdef SATA_DECL /*SATA library specific declarations */ +#define ata_id_has_lba48(id) ((id)[83] & (1 << 10)) +#define ata_id_has_lba(id) ((id)[49] & (1 << 9)) +#define ata_id_has_dma(id) ((id)[49] & (1 << 8)) +#define ata_id_u32(id,n) \ + (((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)])) +#define ata_id_u64(id,n) \ + (((u64) (id)[(n) + 3] << 48) | \ + ((u64) (id)[(n) + 2] << 32) | \ + ((u64) (id)[(n) + 1] << 16) | \ + ((u64) (id)[(n) + 0]) ) +#endif + +#ifdef SATA_DECL /*SATA library specific declarations */ +static inline void +ata_dump_id (u16 * id) +{ + PRINTF ("49==0x%04x " + "53==0x%04x " + "63==0x%04x " + "64==0x%04x " + "75==0x%04x \n", id[49], id[53], id[63], id[64], id[75]); + PRINTF ("80==0x%04x " + "81==0x%04x " + "82==0x%04x " + "83==0x%04x " + "84==0x%04x \n", id[80], id[81], id[82], id[83], id[84]); + PRINTF ("88==0x%04x " "93==0x%04x\n", id[88], id[93]); +} +#endif + +#ifdef SATA_DECL /*SATA library specific declarations */ +int sata_bus_softreset (int num); +void sata_identify (int num, int dev); +void sata_port (struct sata_ioports *ioport); +void set_Feature_cmd (int num, int dev); +int sata_devchk (struct sata_ioports *ioaddr, int dev); +void dev_select (struct sata_ioports *ioaddr, int dev); +u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max); +u8 sata_chk_status (struct sata_ioports *ioaddr); +ulong sata_read (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer); +ulong sata_write (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer); +void msleep (int count); +#else +extern int sata_bus_softreset (int num); +extern void sata_identify (int num, int dev); +extern void sata_port (struct sata_ioports *ioport); +extern void set_Feature_cmd (int num, int dev); +extern ulong sata_read (int device, lbaint_t blknr, + ulong blkcnt, ulong * buffer); +extern ulong sata_write (int device, lbaint_t blknr, + ulong blkcnt, ulong * buffer); +extern void msleep (int count); +#endif + +/************DRIVER SPECIFIC DEFINITIONS AND DECLARATIONS**************/ + +#ifdef DRV_DECL /*Driver specific declaration */ +int init_sata (void); +#else +extern int init_sata (void); +#endif + +#ifdef DRV_DECL /*Defines Driver Specific variables */ +struct sata_port port[CFG_SATA_MAXBUS]; +block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES]; +int curr_dev = -1; +#else +extern struct sata_port port[CFG_SATA_MAXBUS]; +extern block_dev_desc_t sata_dev_desc[CFG_SATA_MAXDEVICES]; +extern int curr_dev; +#endif -- cgit v1.2.3 From 3162eb836903c8b247fdc7470dd39bfa6996f495 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 15 May 2007 23:38:05 +0200 Subject: Minor coding style cleanup. --- include/ata.h | 2 +- include/sata.h | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/ata.h b/include/ata.h index d36bdf6cd1c..aa6e90d4702 100644 --- a/include/ata.h +++ b/include/ata.h @@ -91,7 +91,7 @@ enum { /* bits in ATA command block registers */ ATA_HOB = (1 << 7), /* LBA48 selector */ ATA_NIEN = (1 << 1), /* disable-irq flag */ - /*ATA_LBA = (1 << 6), *//* LBA28 selector */ + /*ATA_LBA = (1 << 6), */ /* LBA28 selector */ ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */ ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */ ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */ diff --git a/include/sata.h b/include/sata.h index c6fa2ab5bcd..a8713f817e9 100644 --- a/include/sata.h +++ b/include/sata.h @@ -24,12 +24,12 @@ struct sata_ioports { }; struct sata_port { - unsigned char port_no; /*primary-0, secondary=1 */ - struct sata_ioports ioaddr; /*ATA cmd/ctl/dma reg blks */ + unsigned char port_no; /* primary=0, secondary=1 */ + struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */ unsigned char ctl_reg; unsigned char last_ctl; - unsigned char port_state; /*1-port is present and - 0-port is not available */ + unsigned char port_state; /* 1-port is present and */ + 0-port is not available */ unsigned char dev_mask; }; -- cgit v1.2.3 From 255a3577c848706441daee0174543efe205a77f8 Mon Sep 17 00:00:00 2001 From: Kim Phillips Date: Wed, 16 May 2007 16:52:19 -0500 Subject: Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx For all practical u-boot purposes, TSECs don't differ throughout the mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx. Signed-off-by: Kim Phillips --- include/configs/MPC8313ERDB.h | 8 ++++---- include/configs/MPC8349EMDS.h | 8 ++++---- include/configs/MPC8349ITX.h | 14 +++++++------- include/configs/MPC8540ADS.h | 8 ++++---- include/configs/MPC8540EVAL.h | 8 ++++---- include/configs/MPC8541CDS.h | 8 ++++---- include/configs/MPC8544DS.h | 8 ++++---- include/configs/MPC8548CDS.h | 16 ++++++++-------- include/configs/MPC8555CDS.h | 8 ++++---- include/configs/MPC8560ADS.h | 8 ++++---- include/configs/MPC8568MDS.h | 12 ++++++------ include/configs/MPC8641HPCN.h | 16 ++++++++-------- include/configs/PM854.h | 8 ++++---- include/configs/PM856.h | 8 ++++---- include/configs/TQM834x.h | 8 ++++---- include/configs/TQM85xx.h | 8 ++++---- include/configs/sbc8349.h | 8 ++++---- include/configs/stxgp3.h | 8 ++++---- include/configs/stxssa.h | 8 ++++---- 19 files changed, 89 insertions(+), 89 deletions(-) (limited to 'include') diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 697631345f6..7e1005c1ae9 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -303,11 +303,11 @@ #endif #define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_MPC83XX_TSEC1 1 +#define CONFIG_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0x1c #define TSEC2_PHY_ADDR 4 #define TSEC1_PHYIDX 0 diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 0460be9e569..20c6d5a365e 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -432,10 +432,10 @@ #endif #define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_MPC83XX_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 906339e9d88..834934d0b6a 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -374,18 +374,18 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_MII #define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */ -#define CONFIG_MPC83XX_TSEC1 +#define CONFIG_TSEC1 -#ifdef CONFIG_MPC83XX_TSEC1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" +#ifdef CONFIG_TSEC1 +#define CONFIG_TSEC1_NAME "TSEC0" #define CFG_TSEC1_OFFSET 0x24000 #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ #define TSEC1_PHYIDX 0 #endif -#ifdef CONFIG_MPC83XX_TSEC2 +#ifdef CONFIG_TSEC2 #define CONFIG_HAS_ETH1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC2_NAME "TSEC1" #define CFG_TSEC2_OFFSET 0x25000 #define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */ #define TSEC2_PHY_ADDR 4 @@ -628,11 +628,11 @@ boards, we say we have two, but don't display a message if we find only one. */ */ #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_MPC83XX_TSEC1 +#ifdef CONFIG_TSEC1 #define CONFIG_ETHADDR 00:E0:0C:00:8C:01 #endif -#ifdef CONFIG_MPC83XX_TSEC2 +#ifdef CONFIG_TSEC2 #define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02 #endif diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5aeea586800..9176be388e6 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -366,10 +366,10 @@ #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 418a3a38e68..b568cb4df75 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -212,10 +212,10 @@ #elif defined(CONFIG_TSEC_ENET) #define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define CONFIG_MPC85XX_FEC 1 #define CONFIG_MPC85XX_FEC_NAME "FEC" #define TSEC1_PHY_ADDR 7 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index fb360d282cd..e047e259a5b 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 4c3430897da..7cd62e95a91 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -359,10 +359,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC1" -#define CONFIG_MPC85XX_TSEC3 1 -#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC3" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 680009d6006..a0d291eef48 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -391,14 +391,14 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" -#define CONFIG_MPC85XX_TSEC3 1 -#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2" -#undef CONFIG_MPC85XX_TSEC4 -#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC2" +#undef CONFIG_TSEC4 +#define CONFIG_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 4c8b4e73f3b..b7e703ca183 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 21e66376805..043397fc21b 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -356,10 +356,10 @@ #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 3f65644fdd4..0ff0416138d 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -353,12 +353,12 @@ extern unsigned long get_clock_freq(void); #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1" -#undef CONFIG_MPC85XX_TSEC3 -#undef CONFIG_MPC85XX_TSEC4 +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC1" +#undef CONFIG_TSEC3 +#undef CONFIG_TSEC4 #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 2 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index bbe35053dd7..43a9d6ff288 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -359,14 +359,14 @@ #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC86XX_TSEC1 1 -#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1" -#define CONFIG_MPC86XX_TSEC2 1 -#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2" -#define CONFIG_MPC86XX_TSEC3 1 -#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3" -#define CONFIG_MPC86XX_TSEC4 1 -#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "eTSEC3" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "eTSEC4" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 4fb54402b1b..8f130f5ccd8 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -262,10 +262,10 @@ #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 87ab9348735..0286b53e017 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -258,10 +258,10 @@ #endif #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index ed0357791b4..4a5f8b67578 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -248,10 +248,10 @@ extern int tqm834x_num_flash_banks; #define CONFIG_NET_MULTI #endif -#define CONFIG_MPC83XX_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index f45f3a2f5ac..b0b9dd3ab89 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -258,10 +258,10 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define TSEC1_PHY_ADDR 2 #define TSEC2_PHY_ADDR 1 #define TSEC1_PHYIDX 0 diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 65aac5cefd3..e6e3866a07e 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -401,10 +401,10 @@ #define CONFIG_NET_MULTI 1 #endif -#define CONFIG_MPC83XX_TSEC1 1 -#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC83XX_TSEC2 1 -#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #define CONFIG_PHY_BCM5421S 1 #define TSEC1_PHY_ADDR 0x19 #define TSEC2_PHY_ADDR 0x1a diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 625cf20144f..21065b9d05c 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -230,10 +230,10 @@ #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 8624f4b74b8..2a341855401 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -252,10 +252,10 @@ #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_MPC85XX_TSEC1 1 -#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0" -#define CONFIG_MPC85XX_TSEC2 1 -#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "TSEC0" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "TSEC1" #undef CONFIG_MPS85XX_FEC #define TSEC1_PHY_ADDR 2 -- cgit v1.2.3 From 02032e8f14751a1a751b09240a4f1cf9f8a2077f Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Fri, 22 Jun 2007 14:58:04 +0200 Subject: [ppc] Fix build breakage for all non-4xx PowerPC variants. - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup --- include/74xx_7xx.h | 1 + include/mpc5xx.h | 1 + include/mpc5xxx.h | 1 + include/mpc8220.h | 1 + include/mpc824x.h | 2 ++ include/mpc8260.h | 2 +- include/mpc83xx.h | 1 + include/mpc85xx.h | 1 + include/mpc86xx.h | 2 +- include/mpc8xx.h | 2 +- include/ppc4xx.h | 3 ++- include/ppc_asm.tmpl | 2 +- 12 files changed, 14 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h index ba73bae9e5f..4a03cecb591 100644 --- a/include/74xx_7xx.h +++ b/include/74xx_7xx.h @@ -34,6 +34,7 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */ +#define _START_OFFSET EXC_OFF_SYS_RESET /*---------------------------------------------------------------- * l2cr values diff --git a/include/mpc5xx.h b/include/mpc5xx.h index 7508f6df20e..e9b08a0dc72 100644 --- a/include/mpc5xx.h +++ b/include/mpc5xx.h @@ -36,6 +36,7 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET EXC_OFF_SYS_RESET /*----------------------------------------------------------------------- * ISB bit in IMMR to set internal memory map diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index 089aa1322b8..a4581a3e6bb 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -39,6 +39,7 @@ /* Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET /* useful macros for manipulating CSx_START/STOP */ #if defined(CONFIG_MGT5100) diff --git a/include/mpc8220.h b/include/mpc8220.h index ff7acc6d3ab..d3b1457f9c5 100644 --- a/include/mpc8220.h +++ b/include/mpc8220.h @@ -35,6 +35,7 @@ /* Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET /* Internal memory map */ /* MPC8220 Internal Register MMAP */ diff --git a/include/mpc824x.h b/include/mpc824x.h index 30fc795382f..4bd88634819 100644 --- a/include/mpc824x.h +++ b/include/mpc824x.h @@ -142,6 +142,8 @@ #define EXC_OFF_JMDDI 0x1600 /* Java Mode denorm detect Interr -- WTF??*/ #define EXC_OFF_RMTE 0x2000 /* Run Mode or Trace Exception */ +#define _START_OFFSET EXC_OFF_SYS_RESET + #define MAP_A_CONFIG_ADDR_HIGH 0x8000 /* Upper half of CONFIG_ADDR for Map A */ #define MAP_A_CONFIG_ADDR_LOW 0x0CF8 /* Lower half of CONFIG_ADDR for Map A */ #define MAP_A_CONFIG_DATA_HIGH 0x8000 /* Upper half of CONFIG_DAT for Map A */ diff --git a/include/mpc8260.h b/include/mpc8260.h index d9dd92d9a5e..b61218ccc29 100644 --- a/include/mpc8260.h +++ b/include/mpc8260.h @@ -53,7 +53,7 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ - +#define _START_OFFSET EXC_OFF_SYS_RESET /*----------------------------------------------------------------------- * BCR - Bus Configuration Register 4-25 diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 60fc214b3e2..cbf41c3a939 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -25,6 +25,7 @@ /* System reset offset (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 +#define _START_OFFSET EXC_OFF_SYS_RESET /* IMMRBAR - Internal Memory Register Base Address */ diff --git a/include/mpc85xx.h b/include/mpc85xx.h index a4d99b2a165..6fbd50457c4 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -8,6 +8,7 @@ #define __MPC85xx_H__ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET EXC_OFF_SYS_RESET #if defined(CONFIG_E500) #include diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 673bfed16e9..9fd349af986 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -8,7 +8,7 @@ #define __MPC86xx_H__ #define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ - +#define _START_OFFSET EXC_OFF_SYS_RESET /* * platform register addresses diff --git a/include/mpc8xx.h b/include/mpc8xx.h index 29117589be9..11305987f89 100644 --- a/include/mpc8xx.h +++ b/include/mpc8xx.h @@ -35,7 +35,7 @@ * Exception offsets (PowerPC standard) */ #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ - +#define _START_OFFSET EXC_OFF_SYS_RESET /*----------------------------------------------------------------------- * SYPCR - System Protection Control Register 11-9 diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 8cead66ad1a..ca241d2c13c 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -22,7 +22,8 @@ #ifndef __PPC4XX_H__ #define __PPC4XX_H__ -#define _START_OFFSET 0x2100 +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) #if defined(CONFIG_440) #include diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl index ad027d61f40..9f4029f2afc 100644 --- a/include/ppc_asm.tmpl +++ b/include/ppc_asm.tmpl @@ -274,7 +274,7 @@ label: \ #define CRIT_EXCEPTION(n, label, hdlr) \ . = n; \ label: \ - EXCEPTION_PROLOG(csrr0, csrr1); \ + EXCEPTION_PROLOG(CSRR0, CSRR1); \ lwz r3,GOT(transfer_to_handler); \ mtlr r3; \ addi r3,r1,STACK_FRAME_OVERHEAD; \ -- cgit v1.2.3 From a11e06965ec91270c51853407ff1261d3c740386 Mon Sep 17 00:00:00 2001 From: Igor Lisitsin Date: Wed, 28 Mar 2007 19:06:19 +0400 Subject: Extend POST support for PPC440 Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin -- --- include/configs/sequoia.h | 15 +++++++++++++- include/post.h | 1 + include/ppc440.h | 50 ++++++++++++++++++++++++----------------------- 3 files changed, 41 insertions(+), 25 deletions(-) (limited to 'include') diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 42b42fc57f3..ae1c129109f 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -59,6 +59,7 @@ #define CFG_MONITOR_BASE TEXT_BASE #define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */ #define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_OCM_DATA_ADDR CFG_OCM_BASE #define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ #define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 @@ -81,7 +82,7 @@ #define CFG_INIT_RAM_END (4 << 10) #define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR /*----------------------------------------------------------------------- * Serial Port @@ -328,6 +329,18 @@ CFG_CMD_SDRAM | \ CMD_USB) +/* POST support */ +#define CONFIG_POST (CFG_POST_MEMORY | \ + CFG_POST_CPU | \ + CFG_POST_UART | \ + CFG_POST_I2C | \ + CFG_POST_SPR) + +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CONFIG_LOGBUFFER + +#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */ + #define CONFIG_SUPPORT_VFAT /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ diff --git a/include/post.h b/include/post.h index cdefbddb6f5..8259e5d2ea6 100644 --- a/include/post.h +++ b/include/post.h @@ -91,6 +91,7 @@ extern int post_hotkeys_pressed(void); #define CFG_POST_SYSMON 0x00000800 #define CFG_POST_DSP 0x00001000 #define CFG_POST_CODEC 0x00002000 +#define CFG_POST_FPU 0x00004000 #endif /* CONFIG_POST */ diff --git a/include/ppc440.h b/include/ppc440.h index 09f843041da..9ba47a53cf5 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -282,6 +282,32 @@ #define sdr_sdstp3 0x4003 #endif /* CONFIG_440GX */ +#ifdef CONFIG_440 +/*----------------------------------------------------------------------------+ +| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). ++----------------------------------------------------------------------------*/ +#define CCR0_PRE 0x40000000 +#define CCR0_CRPE 0x08000000 +#define CCR0_DSTG 0x00200000 +#define CCR0_DAPUIB 0x00100000 +#define CCR0_DTB 0x00008000 +#define CCR0_GICBT 0x00004000 +#define CCR0_GDCBT 0x00002000 +#define CCR0_FLSTA 0x00000100 +#define CCR0_ICSLC_MASK 0x0000000C +#define CCR0_ICSLT_MASK 0x00000003 +#define CCR1_TCS_MASK 0x00000080 +#define CCR1_TCS_INTCLK 0x00000000 +#define CCR1_TCS_EXTCLK 0x00000080 +#define MMUCR_SWOA 0x01000000 +#define MMUCR_U1TE 0x00400000 +#define MMUCR_U2SWOAE 0x00200000 +#define MMUCR_DULXE 0x00800000 +#define MMUCR_IULXE 0x00400000 +#define MMUCR_STS 0x00100000 +#define MMUCR_STID_MASK 0x000000FF +#endif /* CONFIG_440 */ + #ifdef CONFIG_440SPE #undef sdr_sdstp2 #define sdr_sdstp2 0x0022 @@ -307,30 +333,6 @@ #define sdr_sdstp6 0x4005 #define sdr_sdstp7 0x4007 -/*----------------------------------------------------------------------------+ -| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). -+----------------------------------------------------------------------------*/ -#define CCR0_PRE 0x40000000 -#define CCR0_CRPE 0x08000000 -#define CCR0_DSTG 0x00200000 -#define CCR0_DAPUIB 0x00100000 -#define CCR0_DTB 0x00008000 -#define CCR0_GICBT 0x00004000 -#define CCR0_GDCBT 0x00002000 -#define CCR0_FLSTA 0x00000100 -#define CCR0_ICSLC_MASK 0x0000000C -#define CCR0_ICSLT_MASK 0x00000003 -#define CCR1_TCS_MASK 0x00000080 -#define CCR1_TCS_INTCLK 0x00000000 -#define CCR1_TCS_EXTCLK 0x00000080 -#define MMUCR_SEOA 0x01000000 -#define MMUCR_U1TE 0x00400000 -#define MMUCR_U2SWOAE 0x00200000 -#define MMUCR_DULXE 0x00800000 -#define MMUCR_IULXE 0x00400000 -#define MMUCR_STS 0x00100000 -#define MMUCR_STID_MASK 0x000000FF - #define SDR0_CFGADDR 0x00E #define SDR0_CFGDATA 0x00F -- cgit v1.2.3 From 2dc64451b4c08ffd619372abfdc2506a2e2363b9 Mon Sep 17 00:00:00 2001 From: Igor Lisitsin Date: Wed, 18 Apr 2007 14:55:19 +0400 Subject: Adapt log buffer code to support Linux 2.6 A new environment variable, "logversion", selects the log buffer behaviour. If it is not set or set to a value other than 2, then the old, Linux 2.4.4, behaviour is selected. Signed-off-by: Igor Lisitsin -- --- include/logbuff.h | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/logbuff.h b/include/logbuff.h index 3acfc18a782..d4157290538 100644 --- a/include/logbuff.h +++ b/include/logbuff.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2002-2007 * Detlev Zundel, dzu@denx.de. * * See file CREDITS for list of people who contributed to this @@ -25,6 +25,7 @@ #ifdef CONFIG_LOGBUFFER +#define LOGBUFF_MAGIC 0xc0de4ced /* Forced by code, eh! */ #define LOGBUFF_LEN (16384) /* Must be 16k right now */ #define LOGBUFF_MASK (LOGBUFF_LEN-1) #define LOGBUFF_OVERHEAD (4096) /* Logbuffer overhead for extra info */ @@ -32,6 +33,29 @@ #define LOGBUFF_INITIALIZED (1<<31) +/* The mapping used here has to be the same as in setup_ext_logbuff () + in linux/kernel/printk */ + +typedef struct { + union { + struct { + unsigned long tag; + unsigned long start; + unsigned long con; + unsigned long end; + unsigned long chars; + } v2; + struct { + unsigned long dummy; + unsigned long tag; + unsigned long start; + unsigned long size; + unsigned long chars; + } v1; + }; + unsigned char buf[0]; +} logbuff_t; + int drv_logbuff_init (void); void logbuff_init_ptrs (void); void logbuff_log(char *msg); -- cgit v1.2.3 From 1636d1c8529c006d106287cfbc20cd0a246fe1cb Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Fri, 22 Jun 2007 23:59:00 +0200 Subject: Coding stylke cleanup; rebuild CHANGELOG --- include/asm-ppc/processor.h | 46 ++++++++++++++++++++++----------------------- include/configs/TQM5200.h | 4 ++-- include/configs/alpr.h | 4 ++-- include/configs/bamboo.h | 14 +++++++------- include/configs/ebony.h | 2 +- include/configs/lwmon5.h | 4 ++-- include/configs/ocotea.h | 2 +- include/configs/p3p440.h | 2 +- include/configs/pcs440ep.h | 2 +- include/configs/sequoia.h | 2 +- include/configs/taishan.h | 4 ++-- include/configs/yosemite.h | 2 +- include/mpc5xx.h | 42 ++++++++++++++++++++--------------------- include/mpc824x.h | 6 +++--- include/mpc8260.h | 16 ++++++++-------- include/mpc83xx.h | 10 +++++----- include/mpc8xx.h | 12 ++++++------ include/ppc405.h | 14 +++++++------- include/ppc440.h | 8 ++++---- 19 files changed, 98 insertions(+), 98 deletions(-) (limited to 'include') diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 29e6101a157..9780fe15c0d 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -35,18 +35,18 @@ #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ #define MSR_BE (1<<9) /* Branch Trace */ -#define MSR_DE (1<<9) /* Debug Exception Enable */ +#define MSR_DE (1<<9) /* Debug Exception Enable */ #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ -#define MSR_IR (1<<5) /* Instruction Relocate */ +#define MSR_IR (1<<5) /* Instruction Relocate */ #define MSR_IS (1<<5) /* Book E Instruction space */ -#define MSR_DR (1<<4) /* Data Relocate */ +#define MSR_DR (1<<4) /* Data Relocate */ #define MSR_DS (1<<4) /* Book E Data space */ #define MSR_PE (1<<3) /* Protection Enable */ #define MSR_PX (1<<2) /* Protection Exclusive Mode */ #define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ #define MSR_RI (1<<1) /* Recoverable Exception */ -#define MSR_LE (1<<0) /* Little Endian */ +#define MSR_LE (1<<0) /* Little Endian */ #ifdef CONFIG_APUS_FAST_EXCEPT #define MSR_ MSR_ME|MSR_IP|MSR_RI @@ -123,9 +123,9 @@ #define DBCR_EDM 0x80000000 #define DBCR_IDM 0x40000000 #define DBCR_RST(x) (((x) & 0x3) << 28) -#define DBCR_RST_NONE 0 -#define DBCR_RST_CORE 1 -#define DBCR_RST_CHIP 2 +#define DBCR_RST_NONE 0 +#define DBCR_RST_CORE 1 +#define DBCR_RST_CHIP 2 #define DBCR_RST_SYSTEM 3 #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ @@ -266,7 +266,7 @@ #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ -#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ #define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ #define SPRN_LR 0x008 /* Link Register */ @@ -495,17 +495,17 @@ #define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ #define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ #define DBSR SPRN_DBSR /* Debug Status Register */ -#define DCMP SPRN_DCMP /* Data TLB Compare Register */ -#define DEC SPRN_DEC /* Decrement Register */ -#define DMISS SPRN_DMISS /* Data TLB Miss Register */ +#define DCMP SPRN_DCMP /* Data TLB Compare Register */ +#define DEC SPRN_DEC /* Decrement Register */ +#define DMISS SPRN_DMISS /* Data TLB Miss Register */ #define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ -#define EAR SPRN_EAR /* External Address Register */ +#define EAR SPRN_EAR /* External Address Register */ #define ESR SPRN_ESR /* Exception Syndrome Register */ #define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ #define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ #define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ #define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ -#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ +#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ #define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ #define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ #define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ @@ -522,13 +522,13 @@ #define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ #define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ #define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ -#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ +#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ #define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ -#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ +#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ #define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ -#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ +#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ #define LR SPRN_LR #define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_MPC86xx) @@ -540,7 +540,7 @@ #define SVR SPRN_SVR /* System-On-Chip Version Register */ #define PVR SPRN_PVR /* Processor Version */ #define RPA SPRN_RPA /* Required Physical Address Register */ -#define SDR1 SPRN_SDR1 /* MMU hash base register */ +#define SDR1 SPRN_SDR1 /* MMU hash base register */ #define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ #define SPR1 SPRN_SPRG1 #define SPR2 SPRN_SPRG2 @@ -611,7 +611,7 @@ #define IVOR35 SPRN_IVOR35 #define MCSRR0 SPRN_MCSRR0 #define MCSRR1 SPRN_MCSRR1 -#define L1CSR0 SPRN_L1CSR0 +#define L1CSR0 SPRN_L1CSR0 #define L1CSR1 SPRN_L1CSR1 #define MCSR SPRN_MCSR #define MMUCSR0 SPRN_MMUCSR0 @@ -620,7 +620,7 @@ #define PID1 SPRN_PID1 #define PID2 SPRN_PID2 #define MAS0 SPRN_MAS0 -#define MAS1 SPRN_MAS1 +#define MAS1 SPRN_MAS1 #define MAS2 SPRN_MAS2 #define MAS3 SPRN_MAS3 #define MAS4 SPRN_MAS4 @@ -632,7 +632,7 @@ #define DCRN_BEAR 0x090 /* Bus Error Address Register */ #define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ +#define BESR_DSES 0x80000000 /* Data-Side Error Status */ #define BESR_DMES 0x40000000 /* DMA Error Status */ #define BESR_RWS 0x20000000 /* Read/Write Status */ #define BESR_ETMASK 0x1C000000 /* Error Type */ @@ -689,8 +689,8 @@ #define IOCR_E3LP 0x01000000 #define IOCR_E4TE 0x00800000 #define IOCR_E4LP 0x00400000 -#define IOCR_EDT 0x00080000 -#define IOCR_SOR 0x00040000 +#define IOCR_EDT 0x00080000 +#define IOCR_SOR 0x00040000 #define IOCR_EDO 0x00008000 #define IOCR_2XC 0x00004000 #define IOCR_ATC 0x00002000 @@ -815,7 +815,7 @@ #define PVR_823 PVR_821 #define PVR_850 PVR_821 #define PVR_860 PVR_821 -#define PVR_7400 0x000C0000 +#define PVR_7400 0x000C0000 #define PVR_8240 0x00810100 /* diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 9da1d884b14..aa3627b4d77 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -44,7 +44,7 @@ #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ @@ -238,7 +238,7 @@ "fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \ "u-boot=/tftpboot/tqm5200/u-boot.bin\0" #else -#define CUSTOM_ENV_SETTINGS \ +#define CUSTOM_ENV_SETTINGS \ "bootfile=cam5200/uImage\0" \ "u-boot=cam5200/u-boot.bin\0" \ "setup=tftp 200000 cam5200/setup.img; autoscr 200000\0" diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 47893e824dd..3e571db0e13 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -95,7 +95,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ @@ -257,7 +257,7 @@ #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CONFIG_LOOPW 1 /* enable loopw command */ -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index af337eee8ea..cd5844363f8 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -74,9 +74,9 @@ * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ #define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */ -#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ +#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */ #define CFG_INIT_RAM_END (4 << 10) -#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET @@ -115,8 +115,8 @@ /*----------------------------------------------------------------------- * FLASH related *----------------------------------------------------------------------*/ -#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ -#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ +#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ @@ -126,11 +126,11 @@ #define CFG_FLASH_ADDR1 0x2aa #define CFG_FLASH_WORD_SIZE unsigned char -#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ -#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ +#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ +#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 5bd326b9aee..09efe1d4004 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -122,7 +122,7 @@ #define CFG_FLASH_WORD_SIZE unsigned char #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 675df76267b..ab42b596268 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -117,7 +117,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ -#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ @@ -360,7 +360,7 @@ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \ {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \ -{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ +{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \ {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 31f8bb3fddf..931fb820d1c 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -137,7 +137,7 @@ #define CFG_FLASH_WORD_SIZE unsigned char #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index cae5bd56f86..f67c5135489 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -286,7 +286,7 @@ #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 040e5895977..333b4a2b7fd 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -104,7 +104,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index ae1c129109f..7b7fb9eb415 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -127,7 +127,7 @@ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/configs/taishan.h b/include/configs/taishan.h index cbbb0066e92..b45c51dc921 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -218,8 +218,8 @@ #define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_NET_MULTI 1 -#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ -#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ +#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */ +#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */ #define CONFIG_PHY2_ADDR 0x1 #define CONFIG_PHY3_ADDR 0x3 #define CONFIG_ET1011C_PHY 1 diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index c96b14e8391..b036d444d13 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -123,7 +123,7 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #ifdef CFG_ENV_IS_IN_FLASH -#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ diff --git a/include/mpc5xx.h b/include/mpc5xx.h index e9b08a0dc72..414651fa0f8 100644 --- a/include/mpc5xx.h +++ b/include/mpc5xx.h @@ -76,10 +76,10 @@ #define SIUMCR_DBPC01 0x00080000 /* - " - */ #define SIUMCR_DBPC10 0x00100000 /* - " - */ #define SIUMCR_DBPC11 0x00180000 /* - " - */ -#define SIUMCR_GPC00 0x00000000 /* General Pins Config */ -#define SIUMCR_GPC01 0x00020000 /* General Pins Config */ -#define SIUMCR_GPC10 0x00040000 /* General Pins Config */ -#define SIUMCR_GPC11 0x00060000 /* General Pins Config */ +#define SIUMCR_GPC00 0x00000000 /* General Pins Config */ +#define SIUMCR_GPC01 0x00020000 /* General Pins Config */ +#define SIUMCR_GPC10 0x00040000 /* General Pins Config */ +#define SIUMCR_GPC11 0x00060000 /* General Pins Config */ #define SIUMCR_DLK 0x00010000 /* Debug Register Lock */ #define SIUMCR_SC00 0x00000000 /* Multi Chip 32 bit */ #define SIUMCR_SC01 0x00004000 /* Muilt Chip 16 bit */ @@ -90,7 +90,7 @@ #define SIUMCR_MLRC01 0x00000400 /* - " - */ #define SIUMCR_MLRC10 0x00000800 /* - " - */ #define SIUMCR_MLRC11 0x00000c00 /* - " - */ -#define SIUMCR_MTSC 0x00000100 /* Memory transfer */ +#define SIUMCR_MTSC 0x00000100 /* Memory transfer */ /*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control Register @@ -123,13 +123,13 @@ * SCCR - System Clock and reset Control Register */ #define SCCR_DFNL_MSK 0x00000070 /* DFNL mask */ -#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */ +#define SCCR_DFNH_MSK 0x00000007 /* DFNH mask */ #define SCCR_DFNL_SHIFT 0x0000004 /* DFNL shift value */ #define SCCR_RTSEL 0x00100000 /* RTC circuit input source select */ #define SCCR_EBDF00 0x00000000 /* Division factor 1. CLKOUT is GCLK2 */ #define SCCR_EBDF11 0x00060000 /* reserved */ #define SCCR_TBS 0x02000000 /* Time Base Source */ -#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ +#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */ #define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */ #define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */ #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ @@ -138,11 +138,11 @@ /*----------------------------------------------------------------------- * MC - Memory Controller */ -#define BR_V 0x00000001 /* Bank valid */ -#define BR_BI 0x00000002 /* Burst inhibit */ -#define BR_PS_8 0x00000400 /* 8 bit port size */ -#define BR_PS_16 0x00000800 /* 16 bit port size */ -#define BR_PS_32 0x00000000 /* 32 bit port size */ +#define BR_V 0x00000001 /* Bank valid */ +#define BR_BI 0x00000002 /* Burst inhibit */ +#define BR_PS_8 0x00000400 /* 8 bit port size */ +#define BR_PS_16 0x00000800 /* 16 bit port size */ +#define BR_PS_32 0x00000000 /* 32 bit port size */ #define BR_LBDIR 0x00000008 /* Late burst data in progess */ #define BR_SETA 0x00000004 /* External Data Acknowledge */ #define OR_SCY_3 0x00000030 /* 3 clock cycles wait states */ @@ -159,8 +159,8 @@ /*----------------------------------------------------------------------- * UMCR - UIMB Module Configuration Register */ -#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */ -#define UMCR_HSPEED 0x10000000 /* Half speed */ +#define UMCR_FSPEED 0x00000000 /* Full speed. Opposit of UMCR_HSPEED */ +#define UMCR_HSPEED 0x10000000 /* Half speed */ /*----------------------------------------------------------------------- * ICTRL - I-Bus Support Control Register @@ -174,16 +174,16 @@ * SCI - Serial communication interface */ -#define SCI_TDRE 0x0100 /* Transmit data register empty */ -#define SCI_TE 0x0008 /* Transmitter enabled */ +#define SCI_TDRE 0x0100 /* Transmit data register empty */ +#define SCI_TE 0x0008 /* Transmitter enabled */ #define SCI_RE 0x0004 /* Receiver enabled */ -#define SCI_RDRF 0x0040 /* Receive data register full */ -#define SCI_PE 0x0400 /* Parity enable */ -#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */ -#define SCI_SCXDR_MK 0x00ff /* Data register mask */ +#define SCI_RDRF 0x0040 /* Receive data register full */ +#define SCI_PE 0x0400 /* Parity enable */ +#define SCI_SCXBR_MK 0x1fff /* Baudrate mask */ +#define SCI_SCXDR_MK 0x00ff /* Data register mask */ #define SCI_M_11 0x0200 /* Frame size is 11 bit */ #define SCI_M_10 0x0000 /* Frame size is 10 bit */ -#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */ +#define SCI_PORT_1 ((int)1) /* Place this later somewhere better */ #define SCI_PORT_2 ((int)2) #endif /* __MPC5XX_H__ */ diff --git a/include/mpc824x.h b/include/mpc824x.h index 4bd88634819..30f01d5aa89 100644 --- a/include/mpc824x.h +++ b/include/mpc824x.h @@ -88,7 +88,7 @@ #define PREP_PCI_MEMORY_BUS 0x80000000 #define PREP_PCI_MEMORY_SIZE 0x80000000 #define MPC107_PCI_CMD 0x80000004 /* MPC107 PCI cmd reg */ -#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */ +#define MPC107_PCI_STAT 0x80000006 /* MPC107 PCI status reg */ #define PROC_INT1_ADR 0x800000a8 /* MPC107 Processor i/f cfg1 */ #define PROC_INT2_ADR 0x800000ac /* MPC107 Processor i/f cfg2 */ #define MEM_CONT1_ADR 0x800000f0 /* MPC107 Memory control config. 1 */ @@ -98,8 +98,8 @@ #define MEM_ERREN1_ADR 0x800000c0 /* MPC107 Memory error enable 1 */ #define MEM_START1_ADR 0x80000080 /* MPC107 Memory starting addr */ #define MEM_START2_ADR 0x80000084 /* MPC107 Memory starting addr-lo */ -#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/ -#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/ +#define XMEM_START1_ADR 0x80000088 /* MPC107 Extended mem. start addr-hi*/ +#define XMEM_START2_ADR 0x8000008c /* MPC107 Extended mem. start addr-lo*/ #define MEM_END1_ADR 0x80000090 /* MPC107 Memory ending address */ #define MEM_END2_ADR 0x80000094 /* MPC107 Memory ending addr-lo */ #define XMEM_END1_ADR 0x80000098 /* MPC107 Extended mem. end addrs-hi */ diff --git a/include/mpc8260.h b/include/mpc8260.h index b61218ccc29..052529409a1 100644 --- a/include/mpc8260.h +++ b/include/mpc8260.h @@ -664,7 +664,7 @@ #define PSDMR_CL_3 0x00000003 /* CAS Latency = 3 */ /*----------------------------------------------------------------------- - * LSDMR - Local Bus SDRAM Mode Register 10-24 + * LSDMR - Local Bus SDRAM Mode Register 10-24 */ /* @@ -707,23 +707,23 @@ /*----------------------------------------------------------------------- * TMR1-TMR4 - Timer Mode Registers 17-6 */ -#define TMRx_PS_MSK 0xff00 /* Prescaler Value */ +#define TMRx_PS_MSK 0xff00 /* Prescaler Value */ #define TMRx_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt*/ -#define TMRx_OM 0x0020 /* Output Mode */ +#define TMRx_OM 0x0020 /* Output Mode */ #define TMRx_ORI 0x0010 /* Output Reference Interrupt Enable*/ -#define TMRx_FRR 0x0008 /* Free Run/Restart */ +#define TMRx_FRR 0x0008 /* Free Run/Restart */ #define TMRx_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */ -#define TMRx_GE 0x0001 /* Gate Enable */ +#define TMRx_GE 0x0001 /* Gate Enable */ #define TMRx_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event*/ #define TMRx_CE_RISING 0x0040 /* Capture on Rising TINx edge only */ #define TMRx_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */ -#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */ +#define TMRx_CE_ANY 0x00c0 /* Capture on any TINx edge */ -#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */ +#define TMRx_ICLK_IN_CAS 0x0000 /* Internally cascaded input */ #define TMRx_ICLK_IN_GEN 0x0002 /* Internal General system clock*/ #define TMRx_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16*/ -#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */ +#define TMRx_ICLK_TIN_PIN 0x0006 /* TINx pin */ /*----------------------------------------------------------------------- diff --git a/include/mpc83xx.h b/include/mpc83xx.h index cbf41c3a939..336c0ac4f22 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -439,9 +439,9 @@ #define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000 #if defined(CONFIG_MPC831X) -#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 +#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000 #define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000 -#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 +#define HRCWH_ROM_LOC_NAND_LP_8BIT 0x00500000 #define HRCWH_ROM_LOC_NAND_LP_16BIT 0x00600000 #define HRCWH_RL_EXT_LEGACY 0x00000000 @@ -1218,7 +1218,7 @@ #define FCR_CMD1 0x00FF0000 #define FCR_CMD1_SHIFT 16 #define FCR_CMD2 0x0000FF00 -#define FCR_CMD2_SHIFT 8 +#define FCR_CMD2_SHIFT 8 #define FCR_CMD3 0x000000FF #define FCR_CMD3_SHIFT 0 @@ -1242,8 +1242,8 @@ /* LTESR - Transfer Error Status Register */ #define LTESR_BM 0x80000000 -#define LTESR_FCT 0x40000000 -#define LTESR_PAR 0x20000000 +#define LTESR_FCT 0x40000000 +#define LTESR_PAR 0x20000000 #define LTESR_WP 0x04000000 #define LTESR_ATMW 0x00800000 #define LTESR_ATMR 0x00400000 diff --git a/include/mpc8xx.h b/include/mpc8xx.h index 11305987f89..bef748f9003 100644 --- a/include/mpc8xx.h +++ b/include/mpc8xx.h @@ -208,12 +208,12 @@ #define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */ #define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */ #define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */ -#define SCCR_DFNL001 0x00000100 /* Division by 4 */ -#define SCCR_DFNL010 0x00000200 /* Division by 8 */ -#define SCCR_DFNL011 0x00000300 /* Division by 16 */ -#define SCCR_DFNL100 0x00000400 /* Division by 32 */ -#define SCCR_DFNL101 0x00000500 /* Division by 64 */ -#define SCCR_DFNL110 0x00000600 /* Division by 128 */ +#define SCCR_DFNL001 0x00000100 /* Division by 4 */ +#define SCCR_DFNL010 0x00000200 /* Division by 8 */ +#define SCCR_DFNL011 0x00000300 /* Division by 16 */ +#define SCCR_DFNL100 0x00000400 /* Division by 32 */ +#define SCCR_DFNL101 0x00000500 /* Division by 64 */ +#define SCCR_DFNL110 0x00000600 /* Division by 128 */ #define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */ #define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */ #define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */ diff --git a/include/ppc405.h b/include/ppc405.h index 6be2a50db75..8e64731929e 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -143,12 +143,12 @@ #define UIC_USBH1 0x00040000 /* USB Host 1 */ #define UIC_USBH2 0x00020000 /* USB Host 2 */ #define UIC_USBDEV 0x00010000 /* USB Device */ -#define UIC_ENET 0x00008000 /* Ethernet interrupt status */ -#define UIC_ENET1 0x00008000 /* dummy define */ +#define UIC_ENET 0x00008000 /* Ethernet interrupt status */ +#define UIC_ENET1 0x00008000 /* dummy define */ #define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */ #define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */ -#define UIC_MAL_SERR 0x00002000 /* MAL SERR */ +#define UIC_MAL_SERR 0x00002000 /* MAL SERR */ #define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */ #define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */ @@ -886,7 +886,7 @@ #define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ #define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ #define reset (CNTRL_DCR_BASE+0x3) /* reset register */ -#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ +#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ #define ecr (0xaa) /* edge conditioner register (405gpr) */ @@ -1119,13 +1119,13 @@ | UART Register Offsets '----------------------------------------------------------------------------*/ #define DATA_REG 0x00 -#define DL_LSB 0x00 -#define DL_MSB 0x01 +#define DL_LSB 0x00 +#define DL_MSB 0x01 #define INT_ENABLE 0x01 #define FIFO_CONTROL 0x02 #define LINE_CONTROL 0x03 #define MODEM_CONTROL 0x04 -#define LINE_STATUS 0x05 +#define LINE_STATUS 0x05 #define MODEM_STATUS 0x06 #define SCRATCH 0x07 diff --git a/include/ppc440.h b/include/ppc440.h index 9ba47a53cf5..76330f16ac6 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -112,7 +112,7 @@ #define icdbtrh 0x39f /* instruction cache debug tag register high */ #define mmucr 0x3b2 /* mmu control register */ #define ccr0 0x3b3 /* core configuration register 0 */ -#define ccr1 0x378 /* core configuration for 440x5 only */ +#define ccr1 0x378 /* core configuration for 440x5 only */ #define icdbdr 0x3d3 /* instruction cache debug data register */ #define dbdr 0x3f3 /* debug data register */ @@ -136,7 +136,7 @@ #define clk_opbd 0x00c0 #define clk_perd 0x00e0 #define clk_mald 0x0100 -#define clk_spcid 0x0120 +#define clk_spcid 0x0120 #define clk_icfg 0x0140 /* 440gx sdr register definations */ @@ -686,8 +686,8 @@ #define SDRAM_CODT_CKSE_SINGLE_END 0x00000008 #define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 #define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 -#define SDRAM_CODT_IO_HIZ 0x00000000 -#define SDRAM_CODT_IO_NMODE 0x00000001 +#define SDRAM_CODT_IO_HIZ 0x00000000 +#define SDRAM_CODT_IO_NMODE 0x00000001 /*-----------------------------------------------------------------------------+ | SDRAM Mode Register -- cgit v1.2.3 From 6f35c53166213c24a5a0e2390ed861136ff73870 Mon Sep 17 00:00:00 2001 From: Matthias Fuchs Date: Sun, 24 Jun 2007 17:41:21 +0200 Subject: ppc4xx: Maintenance patch for esd's CPCI405 derivats -add pci_pre_init() for pci interrupt fixup code -disable phy sleep mode via reset_phy() function -use correct io accessors -cleanup Signed-off-by: Matthias Fuchs --- include/configs/CPCI405.h | 5 +++++ include/configs/CPCI4052.h | 6 ++++++ include/configs/CPCI405AB.h | 5 +++++ include/configs/CPCI405DT.h | 5 +++++ 4 files changed, 21 insertions(+) (limited to 'include') diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 047e2f1eef9..67f75811301 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -55,6 +55,10 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ CONFIG_BOOTP_DNS | \ @@ -139,6 +143,7 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index d756f447f7f..8abdbdc6df2 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -37,6 +37,7 @@ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ +#undef CONFIG_CPCI405_6U /* enable this for 6U boards */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ @@ -56,6 +57,10 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ @@ -166,6 +171,7 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index 852d94a410a..ab6d1168f1d 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -57,6 +57,10 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ @@ -150,6 +154,7 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 2260327c3f8..42ec0801ad7 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -56,6 +56,10 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ @@ -171,6 +175,7 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ +#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ -- cgit v1.2.3 From 466fff1a7bb5fe764a06450626f6098219f446b8 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Mon, 25 Jun 2007 15:57:39 +0200 Subject: ppc4xx: Add pci_pre_init() for 405 boards This patch removes the CFG_PCI_PRE_INIT option completely, since it's not needed anymore with the patch from Matthias Fuchs with the "weak" pci_pre_init() implementation. Signed-off-by: Stefan Roese --- include/common.h | 9 +++++---- include/configs/CPCI405.h | 1 - include/configs/CPCI4052.h | 1 - include/configs/CPCI405AB.h | 1 - include/configs/CPCI405DT.h | 1 - include/configs/KAREF.h | 1 - include/configs/METROBOX.h | 1 - include/configs/XPEDITE1K.h | 1 - include/configs/alpr.h | 1 - include/configs/bamboo.h | 1 - include/configs/ebony.h | 1 - include/configs/katmai.h | 1 - include/configs/luan.h | 1 - include/configs/lwmon5.h | 1 - include/configs/ocotea.h | 1 - include/configs/p3p440.h | 1 - include/configs/pcs440ep.h | 1 - include/configs/sequoia.h | 1 - include/configs/taishan.h | 1 - include/configs/yosemite.h | 1 - include/configs/yucca.h | 1 - 21 files changed, 5 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/include/common.h b/include/common.h index 3c4b37b0dcb..d8b6b469e5f 100644 --- a/include/common.h +++ b/include/common.h @@ -38,7 +38,7 @@ typedef volatile unsigned char vu_char; #include #include #include -#if defined(CONFIG_PCI) && defined(CONFIG_440) +#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000)) #include #endif #if defined(CONFIG_8xx) @@ -248,10 +248,11 @@ void pci_init (void); void pci_init_board(void); void pciinfo (int, int); -#if defined(CONFIG_PCI) && defined(CONFIG_440) -# if defined(CFG_PCI_PRE_INIT) +#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000)) int pci_pre_init (struct pci_controller * ); -# endif +#endif + +#if defined(CONFIG_PCI) && defined(CONFIG_440) # if defined(CFG_PCI_TARGET_INIT) void pci_target_init (struct pci_controller *); # endif diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 67f75811301..9acde1e6f03 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -143,7 +143,6 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ -#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index 8abdbdc6df2..3fc99c50244 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -171,7 +171,6 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ -#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index ab6d1168f1d..4e2e1a834d8 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -154,7 +154,6 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ -#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 42ec0801ad7..ab302df7437 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -175,7 +175,6 @@ #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ #define CONFIG_PCI /* include pci support */ -#define CFG_PCI_PRE_INIT /* pci interrupt mapping etc. */ #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index fd9bd316273..48b94ee45ec 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -263,7 +263,6 @@ #define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ #define CFG_PCI_TARGET_INIT /* let board init pci target*/ #define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 148fe9a5c32..7aae2bd1437 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -332,7 +332,6 @@ #define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE) /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/ #define CFG_PCI_TARGET_INIT /* let board init pci target*/ #define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */ diff --git a/include/configs/XPEDITE1K.h b/include/configs/XPEDITE1K.h index 9b32514867a..f2ad097db29 100644 --- a/include/configs/XPEDITE1K.h +++ b/include/configs/XPEDITE1K.h @@ -238,7 +238,6 @@ extern void out32(unsigned int, unsigned long); #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 47893e824dd..a7b99f72c0f 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -275,7 +275,6 @@ #define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_MASTER_INIT diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index af337eee8ea..a1b5682abfa 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -389,7 +389,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 5bd326b9aee..70b199218db 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -270,7 +270,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index cc47a168ed3..a7eda0773bc 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -314,7 +314,6 @@ #undef CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #undef CFG_PCI_MASTER_INIT diff --git a/include/configs/luan.h b/include/configs/luan.h index 045a144aad8..cbb59c50eaf 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -273,7 +273,6 @@ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #undef CFG_PCI_MASTER_INIT diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 675df76267b..9bfc0b56a5e 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -288,7 +288,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 31f8bb3fddf..bc8ee1c6f16 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -294,7 +294,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index cae5bd56f86..544c1b83de3 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -227,7 +227,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/ diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 040e5895977..5c736589517 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -267,7 +267,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 42b42fc57f3..e4f0ac8c9aa 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -371,7 +371,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/taishan.h b/include/configs/taishan.h index cbbb0066e92..b9936fb155a 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -298,7 +298,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index c96b14e8391..6e01244008a 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -312,7 +312,6 @@ #define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT #define CFG_PCI_MASTER_INIT diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 7f8b0228aec..1fdcc4b5052 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -289,7 +289,6 @@ #undef CONFIG_PCI_CONFIG_HOST_BRIDGE /* Board-specific PCI */ -#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */ #define CFG_PCI_TARGET_INIT /* let board init pci target */ #undef CFG_PCI_MASTER_INIT -- cgit v1.2.3 From 1f2a05898658900dc5717761e27abf2052e67e13 Mon Sep 17 00:00:00 2001 From: Mushtaq Khan Date: Sat, 30 Jun 2007 18:50:48 +0200 Subject: Fix S-ATA support. Signed-off-by: mushtaq khan --- include/sata.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/sata.h b/include/sata.h index a8713f817e9..165b471b289 100644 --- a/include/sata.h +++ b/include/sata.h @@ -28,8 +28,8 @@ struct sata_port { struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */ unsigned char ctl_reg; unsigned char last_ctl; - unsigned char port_state; /* 1-port is present and */ - 0-port is not available */ + unsigned char port_state; /* 1-port is available and */ + /* 0-port is not available */ unsigned char dev_mask; }; @@ -74,18 +74,18 @@ int sata_devchk (struct sata_ioports *ioaddr, int dev); void dev_select (struct sata_ioports *ioaddr, int dev); u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max); u8 sata_chk_status (struct sata_ioports *ioaddr); -ulong sata_read (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer); -ulong sata_write (int device, lbaint_t blknr, ulong blkcnt, ulong * buffer); +ulong sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buffer); +ulong sata_write (int device,ulong blknr, lbaint_t blkcnt, void * buffer); void msleep (int count); #else extern int sata_bus_softreset (int num); extern void sata_identify (int num, int dev); extern void sata_port (struct sata_ioports *ioport); extern void set_Feature_cmd (int num, int dev); -extern ulong sata_read (int device, lbaint_t blknr, - ulong blkcnt, ulong * buffer); -extern ulong sata_write (int device, lbaint_t blknr, - ulong blkcnt, ulong * buffer); +extern ulong sata_read (int device, ulong blknr, + lbaint_t blkcnt, void * buffer); +extern ulong sata_write (int device, ulong blknr, + lbaint_t blkcnt, void * buffer); extern void msleep (int count); #endif -- cgit v1.2.3