From 14a4792a71db3561bea065415ac1f2ac69ef32b5 Mon Sep 17 00:00:00 2001 From: Mayuresh Chitale Date: Fri, 4 Apr 2025 14:48:55 +0000 Subject: riscv: image: Add new image type for RV64 Similar to ARM and X86, introduce a new image type which allows u-boot to distinguish between images built for 32-bit vs 64-bit Risc-V CPUs. Signed-off-by: Mayuresh Chitale Reviewed-by: Maxim Moskalets --- include/image.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/image.h b/include/image.h index c1db8383459..4620782c069 100644 --- a/include/image.h +++ b/include/image.h @@ -138,7 +138,8 @@ enum { IH_ARCH_ARC, /* Synopsys DesignWare ARC */ IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */ IH_ARCH_XTENSA, /* Xtensa */ - IH_ARCH_RISCV, /* RISC-V */ + IH_ARCH_RISCV, /* RISC-V 32 bit*/ + IH_ARCH_RISCV64, /* RISC-V 64 bit*/ IH_ARCH_COUNT, }; -- cgit v1.3.1 From 97833f4cf6f681a341e76771bbf42bc8f8611d82 Mon Sep 17 00:00:00 2001 From: E Shattow Date: Sat, 3 May 2025 04:52:52 -0700 Subject: riscv: starfive: jh7110: move uart0 clock frequency to config header Move unnecessary clock frequency assignment out of device-tree and into the board config header so that the ns16550 serial driver can successfully init during SPL after failing to resolve the parent clock from upstream dts. The serial driver will then resolve clock frequency from device-tree node parent clock at init during Main app as it is expected by upstream. Signed-off-by: E Shattow Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/dts/jh7110-common-u-boot.dtsi | 1 - include/configs/starfive-visionfive2.h | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/riscv/dts/jh7110-common-u-boot.dtsi b/arch/riscv/dts/jh7110-common-u-boot.dtsi index 6d85b2d91a7..049b0a7ce28 100644 --- a/arch/riscv/dts/jh7110-common-u-boot.dtsi +++ b/arch/riscv/dts/jh7110-common-u-boot.dtsi @@ -27,7 +27,6 @@ bootph-pre-ram; reg-offset = <0>; current-speed = <115200>; - clock-frequency = <24000000>; }; &mmc0 { diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index 049b0a06301..e7001b26abf 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -39,4 +39,6 @@ "partitions=" PARTS_DEFAULT "\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" +#define CFG_SYS_NS16550_CLK 24000000 + #endif /* _STARFIVE_VISIONFIVE2_H */ -- cgit v1.3.1 From acf9384d8cc372fc71a5857363cfe10c240c497a Mon Sep 17 00:00:00 2001 From: Yao Zi Date: Tue, 13 May 2025 09:04:55 +0000 Subject: configs: th1520_lpi4a: Add UART clock frequency The BROM of TH1520 always initializes UART0's parent clock and configures the baudrate to 115200. Describe the clock frequency to make UART function correctly in SPL without introducing CCF. Signed-off-by: Yao Zi Reviewed-by: Leo Yu-Chi Liang --- include/configs/th1520_lpi4a.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h index 87496a52c4c..7a9b70a3678 100644 --- a/include/configs/th1520_lpi4a.h +++ b/include/configs/th1520_lpi4a.h @@ -9,6 +9,7 @@ #include +#define CFG_SYS_NS16550_CLK 100000000 #define CFG_SYS_SDRAM_BASE 0x00000000 #define UART_BASE 0xffe7014000 -- cgit v1.3.1