From 19c8fc77e1d3ff45d3ea60e4355039a3a54d4a93 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 12 May 2018 11:56:10 +0200 Subject: fdt: Add another Altera Arria10 clock init compatible The DT bindings for the Arria10 clock init have changed, add another compatible to make them work with U-Boot until a proper clock driver gets written. Signed-off-by: Marek Vasut Cc: Tom Rini Cc: Chin Liang See Cc: Dinh Nguyen --- include/fdtdec.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 5456a17d1a7..c15b2a04a7a 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -160,6 +160,7 @@ enum fdt_compat_id { COMPAT_ALTERA_SOCFPGA_F2SDR2, /* SoCFPGA fpga2SDRAM2 bridge */ COMPAT_ALTERA_SOCFPGA_FPGA0, /* SOCFPGA FPGA manager */ COMPAT_ALTERA_SOCFPGA_NOC, /* SOCFPGA Arria 10 NOC */ + COMPAT_ALTERA_SOCFPGA_CLK_INIT, /* SOCFPGA Arria 10 clk init */ COMPAT_COUNT, }; -- cgit v1.2.3 From 768f23dc8ae30993882131bbf0cdadce43fd9619 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 26 Apr 2018 22:23:05 +0200 Subject: ARM: socfpga: Put stack at the end of SRAM The global data are in the .data section, so there's no point in reserving any space for it above stack. Put stack at the end of SRAM. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen --- include/configs/socfpga_common.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4de2aa79290..cb67d539b17 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -35,10 +35,8 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ #endif -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -- cgit v1.2.3 From f79173280c60f0de5c060b456a9aa19a33297ade Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 23 Apr 2018 01:26:10 +0200 Subject: ARM: socfpga: Zap CONFIG_SOCFPGA_VIRTUAL_TARGET This was never used, is not used anywhere and is just in the way by adding annoying ifdeffery. Get rid of it. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen --- include/configs/socfpga_common.h | 13 ++----------- 1 file changed, 2 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index cb67d539b17..54b9edc97cd 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -5,9 +5,6 @@ #ifndef __CONFIG_SOCFPGA_COMMON_H__ #define __CONFIG_SOCFPGA_COMMON_H__ -/* Virtual target or real hardware */ -#undef CONFIG_SOCFPGA_VIRTUAL_TARGET - /* * High level configuration */ @@ -76,7 +73,7 @@ /* * Ethernet on SoC (EMAC) */ -#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) +#ifdef CONFIG_CMD_NET #define CONFIG_DW_ALTDESCRIPTOR #define CONFIG_MII #endif @@ -95,11 +92,7 @@ #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS #define CONFIG_SYS_TIMER_COUNTS_DOWN #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_TIMER_RATE 2400000 -#else #define CONFIG_SYS_TIMER_RATE 25000000 -#endif /* * L4 Watchdog @@ -181,9 +174,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE -4 -#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET -#define CONFIG_SYS_NS16550_CLK 1000000 -#elif defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS #define CONFIG_SYS_NS16550_CLK 100000000 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -- cgit v1.2.3 From 73172753f4f3351ed1c9d2f6586fc599ce4e728c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 11 May 2018 22:26:35 +0200 Subject: ARM: socfpga: Convert to DM serial Pull the serial port configuration from DT and use DM serial instead of having the serial configuration in two places, DT and board config. Signed-off-by: Marek Vasut Cc: Chin Liang See Cc: Dinh Nguyen --- include/configs/socfpga_common.h | 8 -------- 1 file changed, 8 deletions(-) (limited to 'include') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 54b9edc97cd..a60da85499b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -173,14 +173,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * Serial Driver */ #define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART0_ADDRESS -#define CONFIG_SYS_NS16550_CLK 100000000 -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -#define CONFIG_SYS_NS16550_COM1 SOCFPGA_UART1_ADDRESS -#define CONFIG_SYS_NS16550_CLK 50000000 -#endif /* * USB -- cgit v1.2.3 From 421a21c53ae1520acdaf2b2c2544ba295b8fdd27 Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Tue, 5 Dec 2017 15:58:04 +0800 Subject: ARM: socfpga: Enable SPL memory allocation Enable memory allocation in SPL for preparation to enable FAT in SPL. Memory allocation is needed by FAT to work properly. Signed-off-by: Tien Fong Chee Reviewed-by: Dinh Nguyen --- include/configs/socfpga_common.h | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index a60da85499b..acac4a71083 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -226,17 +226,34 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * SPL * - * SRAM Memory layout: + * SRAM Memory layout for gen 5: * * 0xFFFF_0000 ...... Start of SRAM * 0xFFFF_xxxx ...... Top of stack (grows down) * 0xFFFF_yyyy ...... Malloc area * 0xFFFF_zzzz ...... Global Data * 0xFFFF_FF00 ...... End of SRAM + * + * SRAM Memory layout for Arria 10: + * 0xFFE0_0000 ...... Start of SRAM (bottom) + * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) + * 0xFFEy_yyyy ...... Global Data + * 0xFFEz_zzzz ...... Malloc area (grows up to top) + * 0xFFE3_FFFF ...... End of SRAM (top) */ #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +/* SPL memory allocation configuration, this is for FAT implementation */ +#ifndef CONFIG_SYS_SPL_MALLOC_START +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE + \ + CONFIG_SYS_INIT_RAM_ADDR) +#endif +#endif + /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT) @@ -263,7 +280,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * Stack setup */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) #define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START +#endif /* Extra Environment */ #ifndef CONFIG_SPL_BUILD -- cgit v1.2.3